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-rw-r--r--drivers/net/ethernet/mellanox/mlx4/en_port.h6
-rw-r--r--drivers/net/ethernet/mellanox/mlx4/eq.c39
-rw-r--r--drivers/net/ethernet/mellanox/mlx4/mlx4.h456
-rw-r--r--include/linux/mlx4/cmd.h29
-rw-r--r--include/linux/mlx4/device.h42
5 files changed, 523 insertions, 49 deletions
diff --git a/drivers/net/ethernet/mellanox/mlx4/en_port.h b/drivers/net/ethernet/mellanox/mlx4/en_port.h
index 19eb244f5165..c1bb834414b5 100644
--- a/drivers/net/ethernet/mellanox/mlx4/en_port.h
+++ b/drivers/net/ethernet/mellanox/mlx4/en_port.h
@@ -40,12 +40,6 @@
40#define SET_PORT_MC_PROMISC_SHIFT 30 40#define SET_PORT_MC_PROMISC_SHIFT 30
41 41
42enum { 42enum {
43 MLX4_CMD_SET_VLAN_FLTR = 0x47,
44 MLX4_CMD_SET_MCAST_FLTR = 0x48,
45 MLX4_CMD_DUMP_ETH_STATS = 0x49,
46};
47
48enum {
49 MCAST_DIRECT_ONLY = 0, 43 MCAST_DIRECT_ONLY = 0,
50 MCAST_DIRECT = 1, 44 MCAST_DIRECT = 1,
51 MCAST_DEFAULT = 2 45 MCAST_DEFAULT = 2
diff --git a/drivers/net/ethernet/mellanox/mlx4/eq.c b/drivers/net/ethernet/mellanox/mlx4/eq.c
index 24ee96775996..ad9e3770b050 100644
--- a/drivers/net/ethernet/mellanox/mlx4/eq.c
+++ b/drivers/net/ethernet/mellanox/mlx4/eq.c
@@ -102,45 +102,6 @@ struct mlx4_eq_context {
102 (1ull << MLX4_EVENT_TYPE_SRQ_LIMIT) | \ 102 (1ull << MLX4_EVENT_TYPE_SRQ_LIMIT) | \
103 (1ull << MLX4_EVENT_TYPE_CMD)) 103 (1ull << MLX4_EVENT_TYPE_CMD))
104 104
105struct mlx4_eqe {
106 u8 reserved1;
107 u8 type;
108 u8 reserved2;
109 u8 subtype;
110 union {
111 u32 raw[6];
112 struct {
113 __be32 cqn;
114 } __packed comp;
115 struct {
116 u16 reserved1;
117 __be16 token;
118 u32 reserved2;
119 u8 reserved3[3];
120 u8 status;
121 __be64 out_param;
122 } __packed cmd;
123 struct {
124 __be32 qpn;
125 } __packed qp;
126 struct {
127 __be32 srqn;
128 } __packed srq;
129 struct {
130 __be32 cqn;
131 u32 reserved1;
132 u8 reserved2[3];
133 u8 syndrome;
134 } __packed cq_err;
135 struct {
136 u32 reserved1[2];
137 __be32 port;
138 } __packed port_change;
139 } event;
140 u8 reserved3[3];
141 u8 owner;
142} __packed;
143
144static void eq_set_ci(struct mlx4_eq *eq, int req_not) 105static void eq_set_ci(struct mlx4_eq *eq, int req_not)
145{ 106{
146 __raw_writel((__force u32) cpu_to_be32((eq->cons_index & 0xffffff) | 107 __raw_writel((__force u32) cpu_to_be32((eq->cons_index & 0xffffff) |
diff --git a/drivers/net/ethernet/mellanox/mlx4/mlx4.h b/drivers/net/ethernet/mellanox/mlx4/mlx4.h
index 5dfa68ffc11c..69177614666f 100644
--- a/drivers/net/ethernet/mellanox/mlx4/mlx4.h
+++ b/drivers/net/ethernet/mellanox/mlx4/mlx4.h
@@ -46,6 +46,7 @@
46#include <linux/mlx4/device.h> 46#include <linux/mlx4/device.h>
47#include <linux/mlx4/driver.h> 47#include <linux/mlx4/driver.h>
48#include <linux/mlx4/doorbell.h> 48#include <linux/mlx4/doorbell.h>
49#include <linux/mlx4/cmd.h>
49 50
50#define DRV_NAME "mlx4_core" 51#define DRV_NAME "mlx4_core"
51#define DRV_VERSION "1.0" 52#define DRV_VERSION "1.0"
@@ -54,7 +55,9 @@
54enum { 55enum {
55 MLX4_HCR_BASE = 0x80680, 56 MLX4_HCR_BASE = 0x80680,
56 MLX4_HCR_SIZE = 0x0001c, 57 MLX4_HCR_SIZE = 0x0001c,
57 MLX4_CLR_INT_SIZE = 0x00008 58 MLX4_CLR_INT_SIZE = 0x00008,
59 MLX4_SLAVE_COMM_BASE = 0x0,
60 MLX4_COMM_PAGESIZE = 0x1000
58}; 61};
59 62
60enum { 63enum {
@@ -80,6 +83,94 @@ enum {
80 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT 83 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
81}; 84};
82 85
86enum mlx4_mr_state {
87 MLX4_MR_DISABLED = 0,
88 MLX4_MR_EN_HW,
89 MLX4_MR_EN_SW
90};
91
92#define MLX4_COMM_TIME 10000
93enum {
94 MLX4_COMM_CMD_RESET,
95 MLX4_COMM_CMD_VHCR0,
96 MLX4_COMM_CMD_VHCR1,
97 MLX4_COMM_CMD_VHCR2,
98 MLX4_COMM_CMD_VHCR_EN,
99 MLX4_COMM_CMD_VHCR_POST,
100 MLX4_COMM_CMD_FLR = 254
101};
102
103/*The flag indicates that the slave should delay the RESET cmd*/
104#define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
105/*indicates how many retries will be done if we are in the middle of FLR*/
106#define NUM_OF_RESET_RETRIES 10
107#define SLEEP_TIME_IN_RESET (2 * 1000)
108enum mlx4_resource {
109 RES_QP,
110 RES_CQ,
111 RES_SRQ,
112 RES_XRCD,
113 RES_MPT,
114 RES_MTT,
115 RES_MAC,
116 RES_VLAN,
117 RES_EQ,
118 RES_COUNTER,
119 MLX4_NUM_OF_RESOURCE_TYPE
120};
121
122enum mlx4_alloc_mode {
123 RES_OP_RESERVE,
124 RES_OP_RESERVE_AND_MAP,
125 RES_OP_MAP_ICM,
126};
127
128
129/*
130 *Virtual HCR structures.
131 * mlx4_vhcr is the sw representation, in machine endianess
132 *
133 * mlx4_vhcr_cmd is the formalized structure, the one that is passed
134 * to FW to go through communication channel.
135 * It is big endian, and has the same structure as the physical HCR
136 * used by command interface
137 */
138struct mlx4_vhcr {
139 u64 in_param;
140 u64 out_param;
141 u32 in_modifier;
142 u32 errno;
143 u16 op;
144 u16 token;
145 u8 op_modifier;
146 u8 e_bit;
147};
148
149struct mlx4_vhcr_cmd {
150 __be64 in_param;
151 __be32 in_modifier;
152 __be64 out_param;
153 __be16 token;
154 u16 reserved;
155 u8 status;
156 u8 flags;
157 __be16 opcode;
158};
159
160struct mlx4_cmd_info {
161 u16 opcode;
162 bool has_inbox;
163 bool has_outbox;
164 bool out_is_imm;
165 bool encode_slave_id;
166 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
167 struct mlx4_cmd_mailbox *inbox);
168 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
169 struct mlx4_cmd_mailbox *inbox,
170 struct mlx4_cmd_mailbox *outbox,
171 struct mlx4_cmd_info *cmd);
172};
173
83#ifdef CONFIG_MLX4_DEBUG 174#ifdef CONFIG_MLX4_DEBUG
84extern int mlx4_debug_level; 175extern int mlx4_debug_level;
85#else /* CONFIG_MLX4_DEBUG */ 176#else /* CONFIG_MLX4_DEBUG */
@@ -99,6 +190,9 @@ do { \
99#define mlx4_warn(mdev, format, arg...) \ 190#define mlx4_warn(mdev, format, arg...) \
100 dev_warn(&mdev->pdev->dev, format, ##arg) 191 dev_warn(&mdev->pdev->dev, format, ##arg)
101 192
193#define MLX4_MAX_NUM_SLAVES (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF)
194#define ALL_SLAVES 0xff
195
102struct mlx4_bitmap { 196struct mlx4_bitmap {
103 u32 last; 197 u32 last;
104 u32 top; 198 u32 top;
@@ -130,6 +224,62 @@ struct mlx4_icm_table {
130 struct mlx4_icm **icm; 224 struct mlx4_icm **icm;
131}; 225};
132 226
227struct mlx4_eqe {
228 u8 reserved1;
229 u8 type;
230 u8 reserved2;
231 u8 subtype;
232 union {
233 u32 raw[6];
234 struct {
235 __be32 cqn;
236 } __packed comp;
237 struct {
238 u16 reserved1;
239 __be16 token;
240 u32 reserved2;
241 u8 reserved3[3];
242 u8 status;
243 __be64 out_param;
244 } __packed cmd;
245 struct {
246 __be32 qpn;
247 } __packed qp;
248 struct {
249 __be32 srqn;
250 } __packed srq;
251 struct {
252 __be32 cqn;
253 u32 reserved1;
254 u8 reserved2[3];
255 u8 syndrome;
256 } __packed cq_err;
257 struct {
258 u32 reserved1[2];
259 __be32 port;
260 } __packed port_change;
261 struct {
262 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
263 u32 reserved;
264 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
265 } __packed comm_channel_arm;
266 struct {
267 u8 port;
268 u8 reserved[3];
269 __be64 mac;
270 } __packed mac_update;
271 struct {
272 u8 port;
273 } __packed sw_event;
274 struct {
275 __be32 slave_id;
276 } __packed flr_event;
277 } event;
278 u8 slave_id;
279 u8 reserved3[2];
280 u8 owner;
281} __packed;
282
133struct mlx4_eq { 283struct mlx4_eq {
134 struct mlx4_dev *dev; 284 struct mlx4_dev *dev;
135 void __iomem *doorbell; 285 void __iomem *doorbell;
@@ -142,6 +292,18 @@ struct mlx4_eq {
142 struct mlx4_mtt mtt; 292 struct mlx4_mtt mtt;
143}; 293};
144 294
295struct mlx4_slave_eqe {
296 u8 type;
297 u8 port;
298 u32 param;
299};
300
301struct mlx4_slave_event_eq_info {
302 u32 eqn;
303 u16 token;
304 u64 event_type;
305};
306
145struct mlx4_profile { 307struct mlx4_profile {
146 int num_qp; 308 int num_qp;
147 int rdmarc_per_qp; 309 int rdmarc_per_qp;
@@ -155,17 +317,30 @@ struct mlx4_profile {
155struct mlx4_fw { 317struct mlx4_fw {
156 u64 clr_int_base; 318 u64 clr_int_base;
157 u64 catas_offset; 319 u64 catas_offset;
320 u64 comm_base;
158 struct mlx4_icm *fw_icm; 321 struct mlx4_icm *fw_icm;
159 struct mlx4_icm *aux_icm; 322 struct mlx4_icm *aux_icm;
160 u32 catas_size; 323 u32 catas_size;
161 u16 fw_pages; 324 u16 fw_pages;
162 u8 clr_int_bar; 325 u8 clr_int_bar;
163 u8 catas_bar; 326 u8 catas_bar;
327 u8 comm_bar;
328};
329
330struct mlx4_comm {
331 u32 slave_write;
332 u32 slave_read;
164}; 333};
165 334
166#define MGM_QPN_MASK 0x00FFFFFF 335#define MGM_QPN_MASK 0x00FFFFFF
167#define MGM_BLCK_LB_BIT 30 336#define MGM_BLCK_LB_BIT 30
168 337
338#define VLAN_FLTR_SIZE 128
339
340struct mlx4_vlan_fltr {
341 __be32 entry[VLAN_FLTR_SIZE];
342};
343
169struct mlx4_promisc_qp { 344struct mlx4_promisc_qp {
170 struct list_head list; 345 struct list_head list;
171 u32 qpn; 346 u32 qpn;
@@ -184,12 +359,88 @@ struct mlx4_mgm {
184 u8 gid[16]; 359 u8 gid[16];
185 __be32 qp[MLX4_QP_PER_MGM]; 360 __be32 qp[MLX4_QP_PER_MGM];
186}; 361};
362
363struct mlx4_slave_state {
364 u8 comm_toggle;
365 u8 last_cmd;
366 u8 init_port_mask;
367 bool active;
368 u8 function;
369 dma_addr_t vhcr_dma;
370 u16 mtu[MLX4_MAX_PORTS + 1];
371 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
372 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
373 struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
374 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
375 struct mlx4_slave_event_eq_info event_eq;
376 u16 eq_pi;
377 u16 eq_ci;
378 spinlock_t lock;
379 /*initialized via the kzalloc*/
380 u8 is_slave_going_down;
381 u32 cookie;
382};
383
384struct slave_list {
385 struct mutex mutex;
386 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
387};
388
389struct mlx4_resource_tracker {
390 spinlock_t lock;
391 /* tree for each resources */
392 struct radix_tree_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
393 /* num_of_slave's lists, one per slave */
394 struct slave_list *slave_list;
395};
396
397#define SLAVE_EVENT_EQ_SIZE 128
398struct mlx4_slave_event_eq {
399 u32 eqn;
400 u32 cons;
401 u32 prod;
402 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
403};
404
405struct mlx4_master_qp0_state {
406 int proxy_qp0_active;
407 int qp0_active;
408 int port_active;
409};
410
411struct mlx4_mfunc_master_ctx {
412 struct mlx4_slave_state *slave_state;
413 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
414 int init_port_ref[MLX4_MAX_PORTS + 1];
415 u16 max_mtu[MLX4_MAX_PORTS + 1];
416 int disable_mcast_ref[MLX4_MAX_PORTS + 1];
417 struct mlx4_resource_tracker res_tracker;
418 struct workqueue_struct *comm_wq;
419 struct work_struct comm_work;
420 struct work_struct slave_event_work;
421 struct work_struct slave_flr_event_work;
422 spinlock_t slave_state_lock;
423 u32 comm_arm_bit_vector[4];
424 struct mlx4_eqe cmd_eqe;
425 struct mlx4_slave_event_eq slave_eq;
426 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX];
427};
428
429struct mlx4_mfunc {
430 struct mlx4_comm __iomem *comm;
431 struct mlx4_vhcr_cmd *vhcr;
432 dma_addr_t vhcr_dma;
433
434 struct mlx4_mfunc_master_ctx master;
435};
436
187struct mlx4_cmd { 437struct mlx4_cmd {
188 struct pci_pool *pool; 438 struct pci_pool *pool;
189 void __iomem *hcr; 439 void __iomem *hcr;
190 struct mutex hcr_mutex; 440 struct mutex hcr_mutex;
191 struct semaphore poll_sem; 441 struct semaphore poll_sem;
192 struct semaphore event_sem; 442 struct semaphore event_sem;
443 struct semaphore slave_sem;
193 int max_cmds; 444 int max_cmds;
194 spinlock_t context_lock; 445 spinlock_t context_lock;
195 int free_head; 446 int free_head;
@@ -197,6 +448,7 @@ struct mlx4_cmd {
197 u16 token_mask; 448 u16 token_mask;
198 u8 use_events; 449 u8 use_events;
199 u8 toggle; 450 u8 toggle;
451 u8 comm_toggle;
200}; 452};
201 453
202struct mlx4_uar_table { 454struct mlx4_uar_table {
@@ -333,6 +585,7 @@ struct mlx4_priv {
333 585
334 struct mlx4_fw fw; 586 struct mlx4_fw fw;
335 struct mlx4_cmd cmd; 587 struct mlx4_cmd cmd;
588 struct mlx4_mfunc mfunc;
336 589
337 struct mlx4_bitmap pd_bitmap; 590 struct mlx4_bitmap pd_bitmap;
338 struct mlx4_bitmap xrcd_bitmap; 591 struct mlx4_bitmap xrcd_bitmap;
@@ -404,6 +657,42 @@ void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
404void mlx4_cleanup_srq_table(struct mlx4_dev *dev); 657void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
405void mlx4_cleanup_mcg_table(struct mlx4_dev *dev); 658void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
406 659
660int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
661 struct mlx4_vhcr *vhcr,
662 struct mlx4_cmd_mailbox *inbox,
663 struct mlx4_cmd_mailbox *outbox,
664 struct mlx4_cmd_info *cmd);
665int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
666 struct mlx4_vhcr *vhcr,
667 struct mlx4_cmd_mailbox *inbox,
668 struct mlx4_cmd_mailbox *outbox,
669 struct mlx4_cmd_info *cmd);
670int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
671 struct mlx4_vhcr *vhcr,
672 struct mlx4_cmd_mailbox *inbox,
673 struct mlx4_cmd_mailbox *outbox,
674 struct mlx4_cmd_info *cmd);
675int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
676 struct mlx4_vhcr *vhcr,
677 struct mlx4_cmd_mailbox *inbox,
678 struct mlx4_cmd_mailbox *outbox,
679 struct mlx4_cmd_info *cmd);
680int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
681 struct mlx4_vhcr *vhcr,
682 struct mlx4_cmd_mailbox *inbox,
683 struct mlx4_cmd_mailbox *outbox,
684 struct mlx4_cmd_info *cmd);
685int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
686 struct mlx4_vhcr *vhcr,
687 struct mlx4_cmd_mailbox *inbox,
688 struct mlx4_cmd_mailbox *outbox,
689 struct mlx4_cmd_info *cmd);
690int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
691 struct mlx4_vhcr *vhcr,
692 struct mlx4_cmd_mailbox *inbox,
693 struct mlx4_cmd_mailbox *outbox,
694 struct mlx4_cmd_info *cmd);
695
407void mlx4_start_catas_poll(struct mlx4_dev *dev); 696void mlx4_start_catas_poll(struct mlx4_dev *dev);
408void mlx4_stop_catas_poll(struct mlx4_dev *dev); 697void mlx4_stop_catas_poll(struct mlx4_dev *dev);
409void mlx4_catas_init(void); 698void mlx4_catas_init(void);
@@ -419,6 +708,101 @@ u64 mlx4_make_profile(struct mlx4_dev *dev,
419 struct mlx4_profile *request, 708 struct mlx4_profile *request,
420 struct mlx4_dev_cap *dev_cap, 709 struct mlx4_dev_cap *dev_cap,
421 struct mlx4_init_hca_param *init_hca); 710 struct mlx4_init_hca_param *init_hca);
711void mlx4_master_comm_channel(struct work_struct *work);
712void mlx4_gen_slave_eqe(struct work_struct *work);
713void mlx4_master_handle_slave_flr(struct work_struct *work);
714
715int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
716 struct mlx4_vhcr *vhcr,
717 struct mlx4_cmd_mailbox *inbox,
718 struct mlx4_cmd_mailbox *outbox,
719 struct mlx4_cmd_info *cmd);
720int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
721 struct mlx4_vhcr *vhcr,
722 struct mlx4_cmd_mailbox *inbox,
723 struct mlx4_cmd_mailbox *outbox,
724 struct mlx4_cmd_info *cmd);
725int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
726 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
727 struct mlx4_cmd_mailbox *outbox,
728 struct mlx4_cmd_info *cmd);
729int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
730 struct mlx4_vhcr *vhcr,
731 struct mlx4_cmd_mailbox *inbox,
732 struct mlx4_cmd_mailbox *outbox,
733 struct mlx4_cmd_info *cmd);
734int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
735 struct mlx4_vhcr *vhcr,
736 struct mlx4_cmd_mailbox *inbox,
737 struct mlx4_cmd_mailbox *outbox,
738 struct mlx4_cmd_info *cmd);
739int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
740 struct mlx4_vhcr *vhcr,
741 struct mlx4_cmd_mailbox *inbox,
742 struct mlx4_cmd_mailbox *outbox,
743 struct mlx4_cmd_info *cmd);
744int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
745 struct mlx4_vhcr *vhcr,
746 struct mlx4_cmd_mailbox *inbox,
747 struct mlx4_cmd_mailbox *outbox,
748 struct mlx4_cmd_info *cmd);
749int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
750 struct mlx4_vhcr *vhcr,
751 struct mlx4_cmd_mailbox *inbox,
752 struct mlx4_cmd_mailbox *outbox,
753 struct mlx4_cmd_info *cmd);
754int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
755 struct mlx4_vhcr *vhcr,
756 struct mlx4_cmd_mailbox *inbox,
757 struct mlx4_cmd_mailbox *outbox,
758 struct mlx4_cmd_info *cmd);
759int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
760 struct mlx4_vhcr *vhcr,
761 struct mlx4_cmd_mailbox *inbox,
762 struct mlx4_cmd_mailbox *outbox,
763 struct mlx4_cmd_info *cmd);
764int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
765 struct mlx4_vhcr *vhcr,
766 struct mlx4_cmd_mailbox *inbox,
767 struct mlx4_cmd_mailbox *outbox,
768 struct mlx4_cmd_info *cmd);
769int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
770 struct mlx4_vhcr *vhcr,
771 struct mlx4_cmd_mailbox *inbox,
772 struct mlx4_cmd_mailbox *outbox,
773 struct mlx4_cmd_info *cmd);
774int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
775 struct mlx4_vhcr *vhcr,
776 struct mlx4_cmd_mailbox *inbox,
777 struct mlx4_cmd_mailbox *outbox,
778 struct mlx4_cmd_info *cmd);
779int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
780 struct mlx4_vhcr *vhcr,
781 struct mlx4_cmd_mailbox *inbox,
782 struct mlx4_cmd_mailbox *outbox,
783 struct mlx4_cmd_info *cmd);
784int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
785 struct mlx4_vhcr *vhcr,
786 struct mlx4_cmd_mailbox *inbox,
787 struct mlx4_cmd_mailbox *outbox,
788 struct mlx4_cmd_info *cmd);
789int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
790 struct mlx4_vhcr *vhcr,
791 struct mlx4_cmd_mailbox *inbox,
792 struct mlx4_cmd_mailbox *outbox,
793 struct mlx4_cmd_info *cmd);
794int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
795 struct mlx4_vhcr *vhcr,
796 struct mlx4_cmd_mailbox *inbox,
797 struct mlx4_cmd_mailbox *outbox,
798 struct mlx4_cmd_info *cmd);
799int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
800 struct mlx4_vhcr *vhcr,
801 struct mlx4_cmd_mailbox *inbox,
802 struct mlx4_cmd_mailbox *outbox,
803 struct mlx4_cmd_info *cmd);
804
805int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
422 806
423int mlx4_cmd_init(struct mlx4_dev *dev); 807int mlx4_cmd_init(struct mlx4_dev *dev);
424void mlx4_cmd_cleanup(struct mlx4_dev *dev); 808void mlx4_cmd_cleanup(struct mlx4_dev *dev);
@@ -452,12 +836,82 @@ void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
452void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table); 836void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
453 837
454int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port); 838int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port);
839/* resource tracker functions*/
840int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
841 enum mlx4_resource resource_type,
842 int resource_id, int *slave);
843void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
844int mlx4_init_resource_tracker(struct mlx4_dev *dev);
845
846void mlx4_free_resource_tracker(struct mlx4_dev *dev);
847
848int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
849 struct mlx4_vhcr *vhcr,
850 struct mlx4_cmd_mailbox *inbox,
851 struct mlx4_cmd_mailbox *outbox,
852 struct mlx4_cmd_info *cmd);
853int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
854 struct mlx4_vhcr *vhcr,
855 struct mlx4_cmd_mailbox *inbox,
856 struct mlx4_cmd_mailbox *outbox,
857 struct mlx4_cmd_info *cmd);
858int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
859 struct mlx4_vhcr *vhcr,
860 struct mlx4_cmd_mailbox *inbox,
861 struct mlx4_cmd_mailbox *outbox,
862 struct mlx4_cmd_info *cmd);
863int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
864 struct mlx4_vhcr *vhcr,
865 struct mlx4_cmd_mailbox *inbox,
866 struct mlx4_cmd_mailbox *outbox,
867 struct mlx4_cmd_info *cmd);
455int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps); 868int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
456int mlx4_check_ext_port_caps(struct mlx4_dev *dev, u8 port); 869int mlx4_check_ext_port_caps(struct mlx4_dev *dev, u8 port);
457 870
871
872int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
873 struct mlx4_vhcr *vhcr,
874 struct mlx4_cmd_mailbox *inbox,
875 struct mlx4_cmd_mailbox *outbox,
876 struct mlx4_cmd_info *cmd);
877
878int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
879 struct mlx4_vhcr *vhcr,
880 struct mlx4_cmd_mailbox *inbox,
881 struct mlx4_cmd_mailbox *outbox,
882 struct mlx4_cmd_info *cmd);
458int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 883int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
459 enum mlx4_protocol prot, enum mlx4_steer_type steer); 884 enum mlx4_protocol prot, enum mlx4_steer_type steer);
460int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 885int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
461 int block_mcast_loopback, enum mlx4_protocol prot, 886 int block_mcast_loopback, enum mlx4_protocol prot,
462 enum mlx4_steer_type steer); 887 enum mlx4_steer_type steer);
888int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
889 struct mlx4_vhcr *vhcr,
890 struct mlx4_cmd_mailbox *inbox,
891 struct mlx4_cmd_mailbox *outbox,
892 struct mlx4_cmd_info *cmd);
893int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
894 struct mlx4_vhcr *vhcr,
895 struct mlx4_cmd_mailbox *inbox,
896 struct mlx4_cmd_mailbox *outbox,
897 struct mlx4_cmd_info *cmd);
898int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
899 int port, void *buf);
900int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod,
901 struct mlx4_cmd_mailbox *outbox);
902int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
903 struct mlx4_vhcr *vhcr,
904 struct mlx4_cmd_mailbox *inbox,
905 struct mlx4_cmd_mailbox *outbox,
906 struct mlx4_cmd_info *cmd);
907int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
908 struct mlx4_vhcr *vhcr,
909 struct mlx4_cmd_mailbox *inbox,
910 struct mlx4_cmd_mailbox *outbox,
911 struct mlx4_cmd_info *cmd);
912int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
913 struct mlx4_vhcr *vhcr,
914 struct mlx4_cmd_mailbox *inbox,
915 struct mlx4_cmd_mailbox *outbox,
916 struct mlx4_cmd_info *cmd);
463#endif /* MLX4_H */ 917#endif /* MLX4_H */
diff --git a/include/linux/mlx4/cmd.h b/include/linux/mlx4/cmd.h
index b56e4587208d..e8e92814c8a0 100644
--- a/include/linux/mlx4/cmd.h
+++ b/include/linux/mlx4/cmd.h
@@ -59,12 +59,15 @@ enum {
59 MLX4_CMD_HW_HEALTH_CHECK = 0x50, 59 MLX4_CMD_HW_HEALTH_CHECK = 0x50,
60 MLX4_CMD_SET_PORT = 0xc, 60 MLX4_CMD_SET_PORT = 0xc,
61 MLX4_CMD_SET_NODE = 0x5a, 61 MLX4_CMD_SET_NODE = 0x5a,
62 MLX4_CMD_QUERY_FUNC = 0x56,
62 MLX4_CMD_ACCESS_DDR = 0x2e, 63 MLX4_CMD_ACCESS_DDR = 0x2e,
63 MLX4_CMD_MAP_ICM = 0xffa, 64 MLX4_CMD_MAP_ICM = 0xffa,
64 MLX4_CMD_UNMAP_ICM = 0xff9, 65 MLX4_CMD_UNMAP_ICM = 0xff9,
65 MLX4_CMD_MAP_ICM_AUX = 0xffc, 66 MLX4_CMD_MAP_ICM_AUX = 0xffc,
66 MLX4_CMD_UNMAP_ICM_AUX = 0xffb, 67 MLX4_CMD_UNMAP_ICM_AUX = 0xffb,
67 MLX4_CMD_SET_ICM_SIZE = 0xffd, 68 MLX4_CMD_SET_ICM_SIZE = 0xffd,
69 /*master notify fw on finish for slave's flr*/
70 MLX4_CMD_INFORM_FLR_DONE = 0x5b,
68 71
69 /* TPT commands */ 72 /* TPT commands */
70 MLX4_CMD_SW2HW_MPT = 0xd, 73 MLX4_CMD_SW2HW_MPT = 0xd,
@@ -119,6 +122,26 @@ enum {
119 /* miscellaneous commands */ 122 /* miscellaneous commands */
120 MLX4_CMD_DIAG_RPRT = 0x30, 123 MLX4_CMD_DIAG_RPRT = 0x30,
121 MLX4_CMD_NOP = 0x31, 124 MLX4_CMD_NOP = 0x31,
125 MLX4_CMD_ACCESS_MEM = 0x2e,
126 MLX4_CMD_SET_VEP = 0x52,
127
128 /* Ethernet specific commands */
129 MLX4_CMD_SET_VLAN_FLTR = 0x47,
130 MLX4_CMD_SET_MCAST_FLTR = 0x48,
131 MLX4_CMD_DUMP_ETH_STATS = 0x49,
132
133 /* Communication channel commands */
134 MLX4_CMD_ARM_COMM_CHANNEL = 0x57,
135 MLX4_CMD_GEN_EQE = 0x58,
136
137 /* virtual commands */
138 MLX4_CMD_ALLOC_RES = 0xf00,
139 MLX4_CMD_FREE_RES = 0xf01,
140 MLX4_CMD_MCAST_ATTACH = 0xf05,
141 MLX4_CMD_UCAST_ATTACH = 0xf06,
142 MLX4_CMD_PROMISC = 0xf08,
143 MLX4_CMD_QUERY_FUNC_CAP = 0xf0a,
144 MLX4_CMD_QP_ATTACH = 0xf0b,
122 145
123 /* debug commands */ 146 /* debug commands */
124 MLX4_CMD_QUERY_DEBUG_MSG = 0x2a, 147 MLX4_CMD_QUERY_DEBUG_MSG = 0x2a,
@@ -126,6 +149,7 @@ enum {
126 149
127 /* statistics commands */ 150 /* statistics commands */
128 MLX4_CMD_QUERY_IF_STAT = 0X54, 151 MLX4_CMD_QUERY_IF_STAT = 0X54,
152 MLX4_CMD_SET_IF_STAT = 0X55,
129}; 153};
130 154
131enum { 155enum {
@@ -135,7 +159,8 @@ enum {
135}; 159};
136 160
137enum { 161enum {
138 MLX4_MAILBOX_SIZE = 4096 162 MLX4_MAILBOX_SIZE = 4096,
163 MLX4_ACCESS_MEM_ALIGN = 256,
139}; 164};
140 165
141enum { 166enum {
@@ -192,4 +217,6 @@ static inline int mlx4_cmd_imm(struct mlx4_dev *dev, u64 in_param, u64 *out_para
192struct mlx4_cmd_mailbox *mlx4_alloc_cmd_mailbox(struct mlx4_dev *dev); 217struct mlx4_cmd_mailbox *mlx4_alloc_cmd_mailbox(struct mlx4_dev *dev);
193void mlx4_free_cmd_mailbox(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox); 218void mlx4_free_cmd_mailbox(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox);
194 219
220u32 mlx4_comm_get_version(void);
221
195#endif /* MLX4_CMD_H */ 222#endif /* MLX4_CMD_H */
diff --git a/include/linux/mlx4/device.h b/include/linux/mlx4/device.h
index ca2c39771c38..b9466af2348f 100644
--- a/include/linux/mlx4/device.h
+++ b/include/linux/mlx4/device.h
@@ -47,6 +47,9 @@
47enum { 47enum {
48 MLX4_FLAG_MSI_X = 1 << 0, 48 MLX4_FLAG_MSI_X = 1 << 0,
49 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1, 49 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
50 MLX4_FLAG_MASTER = 1 << 2,
51 MLX4_FLAG_SLAVE = 1 << 3,
52 MLX4_FLAG_SRIOV = 1 << 4,
50}; 53};
51 54
52enum { 55enum {
@@ -58,6 +61,15 @@ enum {
58}; 61};
59 62
60enum { 63enum {
64 MLX4_MAX_NUM_PF = 16,
65 MLX4_MAX_NUM_VF = 64,
66 MLX4_MFUNC_MAX = 80,
67 MLX4_MFUNC_EQ_NUM = 4,
68 MLX4_MFUNC_MAX_EQES = 8,
69 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1)
70};
71
72enum {
61 MLX4_DEV_CAP_FLAG_RC = 1LL << 0, 73 MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
62 MLX4_DEV_CAP_FLAG_UC = 1LL << 1, 74 MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
63 MLX4_DEV_CAP_FLAG_UD = 1LL << 2, 75 MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
@@ -117,7 +129,11 @@ enum mlx4_event {
117 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09, 129 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
118 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f, 130 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
119 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e, 131 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
120 MLX4_EVENT_TYPE_CMD = 0x0a 132 MLX4_EVENT_TYPE_CMD = 0x0a,
133 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
134 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
135 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
136 MLX4_EVENT_TYPE_NONE = 0xff,
121}; 137};
122 138
123enum { 139enum {
@@ -184,6 +200,7 @@ enum mlx4_qp_region {
184}; 200};
185 201
186enum mlx4_port_type { 202enum mlx4_port_type {
203 MLX4_PORT_TYPE_NONE = 0,
187 MLX4_PORT_TYPE_IB = 1, 204 MLX4_PORT_TYPE_IB = 1,
188 MLX4_PORT_TYPE_ETH = 2, 205 MLX4_PORT_TYPE_ETH = 2,
189 MLX4_PORT_TYPE_AUTO = 3 206 MLX4_PORT_TYPE_AUTO = 3
@@ -216,6 +233,7 @@ static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
216 233
217struct mlx4_caps { 234struct mlx4_caps {
218 u64 fw_ver; 235 u64 fw_ver;
236 u32 function;
219 int num_ports; 237 int num_ports;
220 int vl_cap[MLX4_MAX_PORTS + 1]; 238 int vl_cap[MLX4_MAX_PORTS + 1];
221 int ib_mtu_cap[MLX4_MAX_PORTS + 1]; 239 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
@@ -466,6 +484,7 @@ struct mlx4_counter {
466struct mlx4_dev { 484struct mlx4_dev {
467 struct pci_dev *pdev; 485 struct pci_dev *pdev;
468 unsigned long flags; 486 unsigned long flags;
487 unsigned long num_slaves;
469 struct mlx4_caps caps; 488 struct mlx4_caps caps;
470 struct radix_tree_root qp_table_tree; 489 struct radix_tree_root qp_table_tree;
471 u8 rev_id; 490 u8 rev_id;
@@ -494,8 +513,27 @@ struct mlx4_init_port_param {
494#define mlx4_foreach_ib_transport_port(port, dev) \ 513#define mlx4_foreach_ib_transport_port(port, dev) \
495 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 514 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
496 if (((dev)->caps.port_mask & 1 << ((port) - 1)) || \ 515 if (((dev)->caps.port_mask & 1 << ((port) - 1)) || \
497 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)) 516 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
517
518static inline int mlx4_is_master(struct mlx4_dev *dev)
519{
520 return dev->flags & MLX4_FLAG_MASTER;
521}
522
523static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
524{
525 return (qpn < dev->caps.sqp_start + 8);
526}
498 527
528static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
529{
530 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
531}
532
533static inline int mlx4_is_slave(struct mlx4_dev *dev)
534{
535 return dev->flags & MLX4_FLAG_SLAVE;
536}
499 537
500int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, 538int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
501 struct mlx4_buf *buf); 539 struct mlx4_buf *buf);
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-10 00:53:00 -0500