diff options
375 files changed, 27745 insertions, 4219 deletions
diff --git a/arch/m68k/amiga/amiints.c b/arch/m68k/amiga/amiints.c index 907a5533c845..c5b5212cc3f9 100644 --- a/arch/m68k/amiga/amiints.c +++ b/arch/m68k/amiga/amiints.c | |||
| @@ -72,10 +72,14 @@ static struct irq_controller amiga_irq_controller = { | |||
| 72 | 72 | ||
| 73 | void __init amiga_init_IRQ(void) | 73 | void __init amiga_init_IRQ(void) |
| 74 | { | 74 | { |
| 75 | request_irq(IRQ_AUTO_1, ami_int1, 0, "int1", NULL); | 75 | if (request_irq(IRQ_AUTO_1, ami_int1, 0, "int1", NULL)) |
| 76 | request_irq(IRQ_AUTO_3, ami_int3, 0, "int3", NULL); | 76 | pr_err("Couldn't register int%d\n", 1); |
| 77 | request_irq(IRQ_AUTO_4, ami_int4, 0, "int4", NULL); | 77 | if (request_irq(IRQ_AUTO_3, ami_int3, 0, "int3", NULL)) |
| 78 | request_irq(IRQ_AUTO_5, ami_int5, 0, "int5", NULL); | 78 | pr_err("Couldn't register int%d\n", 3); |
| 79 | if (request_irq(IRQ_AUTO_4, ami_int4, 0, "int4", NULL)) | ||
| 80 | pr_err("Couldn't register int%d\n", 4); | ||
| 81 | if (request_irq(IRQ_AUTO_5, ami_int5, 0, "int5", NULL)) | ||
| 82 | pr_err("Couldn't register int%d\n", 5); | ||
| 79 | 83 | ||
| 80 | m68k_setup_irq_controller(&amiga_irq_controller, IRQ_USER, AMI_STD_IRQS); | 84 | m68k_setup_irq_controller(&amiga_irq_controller, IRQ_USER, AMI_STD_IRQS); |
| 81 | 85 | ||
diff --git a/arch/m68k/amiga/cia.c b/arch/m68k/amiga/cia.c index 343fab49bd9a..ecd0f7ca6f0e 100644 --- a/arch/m68k/amiga/cia.c +++ b/arch/m68k/amiga/cia.c | |||
| @@ -176,5 +176,7 @@ void __init cia_init_IRQ(struct ciabase *base) | |||
| 176 | /* override auto int and install CIA handler */ | 176 | /* override auto int and install CIA handler */ |
| 177 | m68k_setup_irq_controller(&auto_irq_controller, base->handler_irq, 1); | 177 | m68k_setup_irq_controller(&auto_irq_controller, base->handler_irq, 1); |
| 178 | m68k_irq_startup(base->handler_irq); | 178 | m68k_irq_startup(base->handler_irq); |
| 179 | request_irq(base->handler_irq, cia_handler, IRQF_SHARED, base->name, base); | 179 | if (request_irq(base->handler_irq, cia_handler, IRQF_SHARED, |
| 180 | base->name, base)) | ||
| 181 | pr_err("Couldn't register %s interrupt\n", base->name); | ||
| 180 | } | 182 | } |
diff --git a/arch/m68k/amiga/config.c b/arch/m68k/amiga/config.c index ab9862c3a136..6e562751ad51 100644 --- a/arch/m68k/amiga/config.c +++ b/arch/m68k/amiga/config.c | |||
| @@ -493,7 +493,8 @@ static void __init amiga_sched_init(irq_handler_t timer_routine) | |||
| 493 | * Please don't change this to use ciaa, as it interferes with the | 493 | * Please don't change this to use ciaa, as it interferes with the |
| 494 | * SCSI code. We'll have to take a look at this later | 494 | * SCSI code. We'll have to take a look at this later |
| 495 | */ | 495 | */ |
| 496 | request_irq(IRQ_AMIGA_CIAB_TA, timer_routine, 0, "timer", NULL); | 496 | if (request_irq(IRQ_AMIGA_CIAB_TA, timer_routine, 0, "timer", NULL)) |
| 497 | pr_err("Couldn't register timer interrupt\n"); | ||
| 497 | /* start timer */ | 498 | /* start timer */ |
| 498 | ciab.cra |= 0x11; | 499 | ciab.cra |= 0x11; |
| 499 | } | 500 | } |
diff --git a/arch/m68k/apollo/config.c b/arch/m68k/apollo/config.c index 78df98f2029a..8d3eafab1ffe 100644 --- a/arch/m68k/apollo/config.c +++ b/arch/m68k/apollo/config.c | |||
| @@ -31,10 +31,6 @@ extern unsigned long dn_gettimeoffset(void); | |||
| 31 | extern int dn_dummy_hwclk(int, struct rtc_time *); | 31 | extern int dn_dummy_hwclk(int, struct rtc_time *); |
| 32 | extern int dn_dummy_set_clock_mmss(unsigned long); | 32 | extern int dn_dummy_set_clock_mmss(unsigned long); |
| 33 | extern void dn_dummy_reset(void); | 33 | extern void dn_dummy_reset(void); |
| 34 | extern void dn_dummy_waitbut(void); | ||
| 35 | extern struct fb_info *dn_fb_init(long *); | ||
| 36 | extern void dn_dummy_debug_init(void); | ||
| 37 | extern irqreturn_t dn_process_int(int irq, struct pt_regs *fp); | ||
| 38 | #ifdef CONFIG_HEARTBEAT | 34 | #ifdef CONFIG_HEARTBEAT |
| 39 | static void dn_heartbeat(int on); | 35 | static void dn_heartbeat(int on); |
| 40 | #endif | 36 | #endif |
| @@ -204,7 +200,8 @@ void dn_sched_init(irq_handler_t timer_routine) | |||
| 204 | printk("*(0x10803) %02x\n",*(volatile unsigned char *)(timer+0x3)); | 200 | printk("*(0x10803) %02x\n",*(volatile unsigned char *)(timer+0x3)); |
| 205 | #endif | 201 | #endif |
| 206 | 202 | ||
| 207 | request_irq(IRQ_APOLLO, dn_timer_int, 0, "time", timer_routine); | 203 | if (request_irq(IRQ_APOLLO, dn_timer_int, 0, "time", timer_routine)) |
| 204 | pr_err("Couldn't register timer interrupt\n"); | ||
| 208 | } | 205 | } |
| 209 | 206 | ||
| 210 | unsigned long dn_gettimeoffset(void) { | 207 | unsigned long dn_gettimeoffset(void) { |
diff --git a/arch/m68k/atari/atakeyb.c b/arch/m68k/atari/atakeyb.c index c038b7c7eff0..a5f33c059979 100644 --- a/arch/m68k/atari/atakeyb.c +++ b/arch/m68k/atari/atakeyb.c | |||
| @@ -33,7 +33,6 @@ | |||
| 33 | #include <asm/atari_joystick.h> | 33 | #include <asm/atari_joystick.h> |
| 34 | #include <asm/irq.h> | 34 | #include <asm/irq.h> |
| 35 | 35 | ||
| 36 | extern unsigned int keymap_count; | ||
| 37 | 36 | ||
| 38 | /* Hook for MIDI serial driver */ | 37 | /* Hook for MIDI serial driver */ |
| 39 | void (*atari_MIDI_interrupt_hook) (void); | 38 | void (*atari_MIDI_interrupt_hook) (void); |
| @@ -567,14 +566,19 @@ static int atari_keyb_done = 0; | |||
| 567 | 566 | ||
| 568 | int atari_keyb_init(void) | 567 | int atari_keyb_init(void) |
| 569 | { | 568 | { |
| 569 | int error; | ||
| 570 | |||
| 570 | if (atari_keyb_done) | 571 | if (atari_keyb_done) |
| 571 | return 0; | 572 | return 0; |
| 572 | 573 | ||
| 573 | kb_state.state = KEYBOARD; | 574 | kb_state.state = KEYBOARD; |
| 574 | kb_state.len = 0; | 575 | kb_state.len = 0; |
| 575 | 576 | ||
| 576 | request_irq(IRQ_MFP_ACIA, atari_keyboard_interrupt, IRQ_TYPE_SLOW, | 577 | error = request_irq(IRQ_MFP_ACIA, atari_keyboard_interrupt, |
| 577 | "keyboard/mouse/MIDI", atari_keyboard_interrupt); | 578 | IRQ_TYPE_SLOW, "keyboard/mouse/MIDI", |
| 579 | atari_keyboard_interrupt); | ||
| 580 | if (error) | ||
| 581 | return error; | ||
| 578 | 582 | ||
| 579 | atari_turnoff_irq(IRQ_MFP_ACIA); | 583 | atari_turnoff_irq(IRQ_MFP_ACIA); |
| 580 | do { | 584 | do { |
diff --git a/arch/m68k/atari/stdma.c b/arch/m68k/atari/stdma.c index d1bd029a34ac..604329fafbb8 100644 --- a/arch/m68k/atari/stdma.c +++ b/arch/m68k/atari/stdma.c | |||
| @@ -179,8 +179,9 @@ EXPORT_SYMBOL(stdma_islocked); | |||
| 179 | void __init stdma_init(void) | 179 | void __init stdma_init(void) |
| 180 | { | 180 | { |
| 181 | stdma_isr = NULL; | 181 | stdma_isr = NULL; |
| 182 | request_irq(IRQ_MFP_FDC, stdma_int, IRQ_TYPE_SLOW | IRQF_SHARED, | 182 | if (request_irq(IRQ_MFP_FDC, stdma_int, IRQ_TYPE_SLOW | IRQF_SHARED, |
| 183 | "ST-DMA: floppy/ACSI/IDE/Falcon-SCSI", stdma_int); | 183 | "ST-DMA: floppy/ACSI/IDE/Falcon-SCSI", stdma_int)) |
| 184 | pr_err("Couldn't register ST-DMA interrupt\n"); | ||
| 184 | } | 185 | } |
| 185 | 186 | ||
| 186 | 187 | ||
diff --git a/arch/m68k/atari/time.c b/arch/m68k/atari/time.c index 1edde27fa32d..d076ff8d1b39 100644 --- a/arch/m68k/atari/time.c +++ b/arch/m68k/atari/time.c | |||
| @@ -31,8 +31,9 @@ atari_sched_init(irq_handler_t timer_routine) | |||
| 31 | /* start timer C, div = 1:100 */ | 31 | /* start timer C, div = 1:100 */ |
| 32 | mfp.tim_ct_cd = (mfp.tim_ct_cd & 15) | 0x60; | 32 | mfp.tim_ct_cd = (mfp.tim_ct_cd & 15) | 0x60; |
| 33 | /* install interrupt service routine for MFP Timer C */ | 33 | /* install interrupt service routine for MFP Timer C */ |
| 34 | request_irq(IRQ_MFP_TIMC, timer_routine, IRQ_TYPE_SLOW, | 34 | if (request_irq(IRQ_MFP_TIMC, timer_routine, IRQ_TYPE_SLOW, |
| 35 | "timer", timer_routine); | 35 | "timer", timer_routine)) |
| 36 | pr_err("Couldn't register timer interrupt\n"); | ||
| 36 | } | 37 | } |
| 37 | 38 | ||
| 38 | /* ++andreas: gettimeoffset fixed to check for pending interrupt */ | 39 | /* ++andreas: gettimeoffset fixed to check for pending interrupt */ |
diff --git a/arch/m68k/bvme6000/config.c b/arch/m68k/bvme6000/config.c index c072595928c0..9fe6fefb5e14 100644 --- a/arch/m68k/bvme6000/config.c +++ b/arch/m68k/bvme6000/config.c | |||
| @@ -43,7 +43,6 @@ extern unsigned long bvme6000_gettimeoffset (void); | |||
| 43 | extern int bvme6000_hwclk (int, struct rtc_time *); | 43 | extern int bvme6000_hwclk (int, struct rtc_time *); |
| 44 | extern int bvme6000_set_clock_mmss (unsigned long); | 44 | extern int bvme6000_set_clock_mmss (unsigned long); |
| 45 | extern void bvme6000_reset (void); | 45 | extern void bvme6000_reset (void); |
| 46 | extern void bvme6000_waitbut(void); | ||
| 47 | void bvme6000_set_vectors (void); | 46 | void bvme6000_set_vectors (void); |
| 48 | 47 | ||
| 49 | /* Save tick handler routine pointer, will point to do_timer() in | 48 | /* Save tick handler routine pointer, will point to do_timer() in |
diff --git a/arch/m68k/hp300/time.c b/arch/m68k/hp300/time.c index dd7c8a2583d3..f6312c7d8727 100644 --- a/arch/m68k/hp300/time.c +++ b/arch/m68k/hp300/time.c | |||
| @@ -70,7 +70,8 @@ void __init hp300_sched_init(irq_handler_t vector) | |||
| 70 | 70 | ||
| 71 | asm volatile(" movpw %0,%1@(5)" : : "d" (INTVAL), "a" (CLOCKBASE)); | 71 | asm volatile(" movpw %0,%1@(5)" : : "d" (INTVAL), "a" (CLOCKBASE)); |
| 72 | 72 | ||
| 73 | request_irq(IRQ_AUTO_6, hp300_tick, IRQ_FLG_STD, "timer tick", vector); | 73 | if (request_irq(IRQ_AUTO_6, hp300_tick, IRQ_FLG_STD, "timer tick", vector)) |
| 74 | pr_err("Couldn't register timer interrupt\n"); | ||
| 74 | 75 | ||
| 75 | out_8(CLOCKBASE + CLKCR2, 0x1); /* select CR1 */ | 76 | out_8(CLOCKBASE + CLKCR2, 0x1); /* select CR1 */ |
| 76 | out_8(CLOCKBASE + CLKCR1, 0x40); /* enable irq */ | 77 | out_8(CLOCKBASE + CLKCR1, 0x40); /* enable irq */ |
diff --git a/arch/m68k/kernel/.gitignore b/arch/m68k/kernel/.gitignore new file mode 100644 index 000000000000..c5f676c3c224 --- /dev/null +++ b/arch/m68k/kernel/.gitignore | |||
| @@ -0,0 +1 @@ | |||
| vmlinux.lds | |||
diff --git a/arch/m68k/kernel/entry.S b/arch/m68k/kernel/entry.S index f28404d9a2bc..5b780826647c 100644 --- a/arch/m68k/kernel/entry.S +++ b/arch/m68k/kernel/entry.S | |||
| @@ -424,7 +424,7 @@ resume: | |||
| 424 | .data | 424 | .data |
| 425 | ALIGN | 425 | ALIGN |
| 426 | sys_call_table: | 426 | sys_call_table: |
| 427 | .long sys_ni_syscall /* 0 - old "setup()" system call*/ | 427 | .long sys_restart_syscall /* 0 - old "setup()" system call, used for restarting */ |
| 428 | .long sys_exit | 428 | .long sys_exit |
| 429 | .long sys_fork | 429 | .long sys_fork |
| 430 | .long sys_read | 430 | .long sys_read |
diff --git a/arch/m68k/kernel/setup.c b/arch/m68k/kernel/setup.c index 4d97bd2bd573..303730afb1c9 100644 --- a/arch/m68k/kernel/setup.c +++ b/arch/m68k/kernel/setup.c | |||
| @@ -26,6 +26,7 @@ | |||
| 26 | #include <linux/initrd.h> | 26 | #include <linux/initrd.h> |
| 27 | 27 | ||
| 28 | #include <asm/bootinfo.h> | 28 | #include <asm/bootinfo.h> |
| 29 | #include <asm/sections.h> | ||
| 29 | #include <asm/setup.h> | 30 | #include <asm/setup.h> |
| 30 | #include <asm/fpu.h> | 31 | #include <asm/fpu.h> |
| 31 | #include <asm/irq.h> | 32 | #include <asm/irq.h> |
| @@ -62,7 +63,6 @@ EXPORT_SYMBOL(vme_brdtype); | |||
| 62 | int m68k_is040or060; | 63 | int m68k_is040or060; |
| 63 | EXPORT_SYMBOL(m68k_is040or060); | 64 | EXPORT_SYMBOL(m68k_is040or060); |
| 64 | 65 | ||
| 65 | extern int end; | ||
| 66 | extern unsigned long availmem; | 66 | extern unsigned long availmem; |
| 67 | 67 | ||
| 68 | int m68k_num_memory; | 68 | int m68k_num_memory; |
| @@ -215,11 +215,10 @@ static void __init m68k_parse_bootinfo(const struct bi_record *record) | |||
| 215 | 215 | ||
| 216 | void __init setup_arch(char **cmdline_p) | 216 | void __init setup_arch(char **cmdline_p) |
| 217 | { | 217 | { |
| 218 | extern int _etext, _edata, _end; | ||
| 219 | int i; | 218 | int i; |
| 220 | 219 | ||
| 221 | /* The bootinfo is located right after the kernel bss */ | 220 | /* The bootinfo is located right after the kernel bss */ |
| 222 | m68k_parse_bootinfo((const struct bi_record *)&_end); | 221 | m68k_parse_bootinfo((const struct bi_record *)_end); |
| 223 | 222 | ||
| 224 | if (CPU_IS_040) | 223 | if (CPU_IS_040) |
| 225 | m68k_is040or060 = 4; | 224 | m68k_is040or060 = 4; |
| @@ -252,9 +251,9 @@ void __init setup_arch(char **cmdline_p) | |||
| 252 | } | 251 | } |
| 253 | 252 | ||
| 254 | init_mm.start_code = PAGE_OFFSET; | 253 | init_mm.start_code = PAGE_OFFSET; |
| 255 | init_mm.end_code = (unsigned long) &_etext; | 254 | init_mm.end_code = (unsigned long)_etext; |
| 256 | init_mm.end_data = (unsigned long) &_edata; | 255 | init_mm.end_data = (unsigned long)_edata; |
| 257 | init_mm.brk = (unsigned long) &_end; | 256 | init_mm.brk = (unsigned long)_end; |
| 258 | 257 | ||
| 259 | *cmdline_p = m68k_command_line; | 258 | *cmdline_p = m68k_command_line; |
| 260 | memcpy(boot_command_line, *cmdline_p, CL_SIZE); | 259 | memcpy(boot_command_line, *cmdline_p, CL_SIZE); |
diff --git a/arch/m68k/kernel/signal.c b/arch/m68k/kernel/signal.c index f9af893cd289..de2d05ddd86d 100644 --- a/arch/m68k/kernel/signal.c +++ b/arch/m68k/kernel/signal.c | |||
| @@ -326,6 +326,9 @@ restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *usc, void __u | |||
| 326 | struct sigcontext context; | 326 | struct sigcontext context; |
| 327 | int err; | 327 | int err; |
| 328 | 328 | ||
| 329 | /* Always make any pending restarted system calls return -EINTR */ | ||
| 330 | current_thread_info()->restart_block.fn = do_no_restart_syscall; | ||
| 331 | |||
| 329 | /* get previous context */ | 332 | /* get previous context */ |
| 330 | if (copy_from_user(&context, usc, sizeof(context))) | 333 | if (copy_from_user(&context, usc, sizeof(context))) |
| 331 | goto badframe; | 334 | goto badframe; |
| @@ -411,6 +414,9 @@ rt_restore_ucontext(struct pt_regs *regs, struct switch_stack *sw, | |||
| 411 | unsigned long usp; | 414 | unsigned long usp; |
| 412 | int err; | 415 | int err; |
| 413 | 416 | ||
| 417 | /* Always make any pending restarted system calls return -EINTR */ | ||
| 418 | current_thread_info()->restart_block.fn = do_no_restart_syscall; | ||
| 419 | |||
| 414 | err = __get_user(temp, &uc->uc_mcontext.version); | 420 | err = __get_user(temp, &uc->uc_mcontext.version); |
| 415 | if (temp != MCONTEXT_VERSION) | 421 | if (temp != MCONTEXT_VERSION) |
| 416 | goto badframe; | 422 | goto badframe; |
| @@ -937,6 +943,15 @@ handle_restart(struct pt_regs *regs, struct k_sigaction *ka, int has_handler) | |||
| 937 | regs->d0 = -EINTR; | 943 | regs->d0 = -EINTR; |
| 938 | break; | 944 | break; |
| 939 | 945 | ||
| 946 | case -ERESTART_RESTARTBLOCK: | ||
| 947 | if (!has_handler) { | ||
| 948 | regs->d0 = __NR_restart_syscall; | ||
| 949 | regs->pc -= 2; | ||
| 950 | break; | ||
| 951 | } | ||
| 952 | regs->d0 = -EINTR; | ||
| 953 | break; | ||
| 954 | |||
| 940 | case -ERESTARTSYS: | 955 | case -ERESTARTSYS: |
| 941 | if (has_handler && !(ka->sa.sa_flags & SA_RESTART)) { | 956 | if (has_handler && !(ka->sa.sa_flags & SA_RESTART)) { |
| 942 | regs->d0 = -EINTR; | 957 | regs->d0 = -EINTR; |
diff --git a/arch/m68k/kernel/vmlinux-sun3.lds b/arch/m68k/kernel/vmlinux-sun3.lds index 8a4919e4d36a..d9368c0709ba 100644 --- a/arch/m68k/kernel/vmlinux-sun3.lds +++ b/arch/m68k/kernel/vmlinux-sun3.lds | |||
| @@ -33,6 +33,7 @@ SECTIONS | |||
| 33 | } :data | 33 | } :data |
| 34 | /* End of data goes *here* so that freeing init code works properly. */ | 34 | /* End of data goes *here* so that freeing init code works properly. */ |
| 35 | _edata = .; | 35 | _edata = .; |
| 36 | NOTES | ||
| 36 | 37 | ||
| 37 | /* will be freed after init */ | 38 | /* will be freed after init */ |
| 38 | . = ALIGN(PAGE_SIZE); /* Init code and data */ | 39 | . = ALIGN(PAGE_SIZE); /* Init code and data */ |
diff --git a/arch/m68k/mac/baboon.c b/arch/m68k/mac/baboon.c index 245d16d078ad..2a96bebd8969 100644 --- a/arch/m68k/mac/baboon.c +++ b/arch/m68k/mac/baboon.c | |||
| @@ -92,7 +92,8 @@ static irqreturn_t baboon_irq(int irq, void *dev_id) | |||
| 92 | void __init baboon_register_interrupts(void) | 92 | void __init baboon_register_interrupts(void) |
| 93 | { | 93 | { |
| 94 | baboon_disabled = 0; | 94 | baboon_disabled = 0; |
| 95 | request_irq(IRQ_NUBUS_C, baboon_irq, 0, "baboon", (void *)baboon); | 95 | if (request_irq(IRQ_NUBUS_C, baboon_irq, 0, "baboon", (void *)baboon)) |
| 96 | pr_err("Couldn't register baboon interrupt\n"); | ||
| 96 | } | 97 | } |
| 97 | 98 | ||
| 98 | /* | 99 | /* |
diff --git a/arch/m68k/mac/config.c b/arch/m68k/mac/config.c index 8819b97be324..98b6bcfb37bf 100644 --- a/arch/m68k/mac/config.c +++ b/arch/m68k/mac/config.c | |||
| @@ -47,13 +47,6 @@ | |||
| 47 | 47 | ||
| 48 | struct mac_booter_data mac_bi_data; | 48 | struct mac_booter_data mac_bi_data; |
| 49 | 49 | ||
| 50 | /* New m68k bootinfo stuff and videobase */ | ||
| 51 | |||
| 52 | extern int m68k_num_memory; | ||
| 53 | extern struct mem_info m68k_memory[NUM_MEMINFO]; | ||
| 54 | |||
| 55 | extern struct mem_info m68k_ramdisk; | ||
| 56 | |||
| 57 | /* The phys. video addr. - might be bogus on some machines */ | 50 | /* The phys. video addr. - might be bogus on some machines */ |
| 58 | static unsigned long mac_orig_videoaddr; | 51 | static unsigned long mac_orig_videoaddr; |
| 59 | 52 | ||
| @@ -61,7 +54,6 @@ static unsigned long mac_orig_videoaddr; | |||
| 61 | extern unsigned long mac_gettimeoffset(void); | 54 | extern unsigned long mac_gettimeoffset(void); |
| 62 | extern int mac_hwclk(int, struct rtc_time *); | 55 | extern int mac_hwclk(int, struct rtc_time *); |
| 63 | extern int mac_set_clock_mmss(unsigned long); | 56 | extern int mac_set_clock_mmss(unsigned long); |
| 64 | extern int show_mac_interrupts(struct seq_file *, void *); | ||
| 65 | extern void iop_preinit(void); | 57 | extern void iop_preinit(void); |
| 66 | extern void iop_init(void); | 58 | extern void iop_init(void); |
| 67 | extern void via_init(void); | 59 | extern void via_init(void); |
| @@ -805,10 +797,6 @@ static void __init mac_identify(void) | |||
| 805 | mac_bi_data.boottime, mac_bi_data.gmtbias); | 797 | mac_bi_data.boottime, mac_bi_data.gmtbias); |
| 806 | printk(KERN_DEBUG " Machine ID: %ld CPUid: 0x%lx memory size: 0x%lx \n", | 798 | printk(KERN_DEBUG " Machine ID: %ld CPUid: 0x%lx memory size: 0x%lx \n", |
| 807 | mac_bi_data.id, mac_bi_data.cpuid, mac_bi_data.memsize); | 799 | mac_bi_data.id, mac_bi_data.cpuid, mac_bi_data.memsize); |
| 808 | #if 0 | ||
| 809 | printk("Ramdisk: addr 0x%lx size 0x%lx\n", | ||
| 810 | m68k_ramdisk.addr, m68k_ramdisk.size); | ||
| 811 | #endif | ||
| 812 | 800 | ||
| 813 | iop_init(); | 801 | iop_init(); |
| 814 | via_init(); | 802 | via_init(); |
diff --git a/arch/m68k/mac/debug.c b/arch/m68k/mac/debug.c index 65dd77a742a3..bce074ceb768 100644 --- a/arch/m68k/mac/debug.c +++ b/arch/m68k/mac/debug.c | |||
| @@ -27,7 +27,6 @@ | |||
| 27 | #include <asm/macints.h> | 27 | #include <asm/macints.h> |
| 28 | 28 | ||
| 29 | extern unsigned long mac_videobase; | 29 | extern unsigned long mac_videobase; |
| 30 | extern unsigned long mac_videodepth; | ||
| 31 | extern unsigned long mac_rowbytes; | 30 | extern unsigned long mac_rowbytes; |
| 32 | 31 | ||
| 33 | extern void mac_serial_print(const char *); | 32 | extern void mac_serial_print(const char *); |
diff --git a/arch/m68k/mac/iop.c b/arch/m68k/mac/iop.c index 326fb9978094..1ad4e9d80eba 100644 --- a/arch/m68k/mac/iop.c +++ b/arch/m68k/mac/iop.c | |||
| @@ -305,14 +305,16 @@ void __init iop_register_interrupts(void) | |||
| 305 | { | 305 | { |
| 306 | if (iop_ism_present) { | 306 | if (iop_ism_present) { |
| 307 | if (oss_present) { | 307 | if (oss_present) { |
| 308 | request_irq(OSS_IRQLEV_IOPISM, iop_ism_irq, | 308 | if (request_irq(OSS_IRQLEV_IOPISM, iop_ism_irq, |
| 309 | IRQ_FLG_LOCK, "ISM IOP", | 309 | IRQ_FLG_LOCK, "ISM IOP", |
| 310 | (void *) IOP_NUM_ISM); | 310 | (void *) IOP_NUM_ISM)) |
| 311 | pr_err("Couldn't register ISM IOP interrupt\n"); | ||
| 311 | oss_irq_enable(IRQ_MAC_ADB); | 312 | oss_irq_enable(IRQ_MAC_ADB); |
| 312 | } else { | 313 | } else { |
| 313 | request_irq(IRQ_VIA2_0, iop_ism_irq, | 314 | if (request_irq(IRQ_VIA2_0, iop_ism_irq, |
| 314 | IRQ_FLG_LOCK|IRQ_FLG_FAST, "ISM IOP", | 315 | IRQ_FLG_LOCK|IRQ_FLG_FAST, "ISM IOP", |
| 315 | (void *) IOP_NUM_ISM); | 316 | (void *) IOP_NUM_ISM)) |
| 317 | pr_err("Couldn't register ISM IOP interrupt\n"); | ||
| 316 | } | 318 | } |
| 317 | if (!iop_alive(iop_base[IOP_NUM_ISM])) { | 319 | if (!iop_alive(iop_base[IOP_NUM_ISM])) { |
| 318 | printk("IOP: oh my god, they killed the ISM IOP!\n"); | 320 | printk("IOP: oh my god, they killed the ISM IOP!\n"); |
diff --git a/arch/m68k/mac/macints.c b/arch/m68k/mac/macints.c index 82e560c076ce..23711074e0e2 100644 --- a/arch/m68k/mac/macints.c +++ b/arch/m68k/mac/macints.c | |||
| @@ -134,6 +134,7 @@ | |||
| 134 | #include <asm/errno.h> | 134 | #include <asm/errno.h> |
| 135 | #include <asm/macints.h> | 135 | #include <asm/macints.h> |
| 136 | #include <asm/irq_regs.h> | 136 | #include <asm/irq_regs.h> |
| 137 | #include <asm/mac_oss.h> | ||
| 137 | 138 | ||
| 138 | #define DEBUG_SPURIOUS | 139 | #define DEBUG_SPURIOUS |
| 139 | #define SHUTUP_SONIC | 140 | #define SHUTUP_SONIC |
| @@ -146,7 +147,6 @@ static int scc_mask; | |||
| 146 | * VIA/RBV hooks | 147 | * VIA/RBV hooks |
| 147 | */ | 148 | */ |
| 148 | 149 | ||
| 149 | extern void via_init(void); | ||
| 150 | extern void via_register_interrupts(void); | 150 | extern void via_register_interrupts(void); |
| 151 | extern void via_irq_enable(int); | 151 | extern void via_irq_enable(int); |
| 152 | extern void via_irq_disable(int); | 152 | extern void via_irq_disable(int); |
| @@ -157,9 +157,6 @@ extern int via_irq_pending(int); | |||
| 157 | * OSS hooks | 157 | * OSS hooks |
| 158 | */ | 158 | */ |
| 159 | 159 | ||
| 160 | extern int oss_present; | ||
| 161 | |||
| 162 | extern void oss_init(void); | ||
| 163 | extern void oss_register_interrupts(void); | 160 | extern void oss_register_interrupts(void); |
| 164 | extern void oss_irq_enable(int); | 161 | extern void oss_irq_enable(int); |
| 165 | extern void oss_irq_disable(int); | 162 | extern void oss_irq_disable(int); |
| @@ -170,9 +167,6 @@ extern int oss_irq_pending(int); | |||
| 170 | * PSC hooks | 167 | * PSC hooks |
| 171 | */ | 168 | */ |
| 172 | 169 | ||
| 173 | extern int psc_present; | ||
| 174 | |||
| 175 | extern void psc_init(void); | ||
| 176 | extern void psc_register_interrupts(void); | 170 | extern void psc_register_interrupts(void); |
| 177 | extern void psc_irq_enable(int); | 171 | extern void psc_irq_enable(int); |
| 178 | extern void psc_irq_disable(int); | 172 | extern void psc_irq_disable(int); |
| @@ -191,12 +185,10 @@ extern void iop_register_interrupts(void); | |||
| 191 | 185 | ||
| 192 | extern int baboon_present; | 186 | extern int baboon_present; |
| 193 | 187 | ||
| 194 | extern void baboon_init(void); | ||
| 195 | extern void baboon_register_interrupts(void); | 188 | extern void baboon_register_interrupts(void); |
| 196 | extern void baboon_irq_enable(int); | 189 | extern void baboon_irq_enable(int); |
| 197 | extern void baboon_irq_disable(int); | 190 | extern void baboon_irq_disable(int); |
| 198 | extern void baboon_irq_clear(int); | 191 | extern void baboon_irq_clear(int); |
| 199 | extern int baboon_irq_pending(int); | ||
| 200 | 192 | ||
| 201 | /* | 193 | /* |
| 202 | * SCC interrupt routines | 194 | * SCC interrupt routines |
| @@ -258,8 +250,9 @@ void __init mac_init_IRQ(void) | |||
| 258 | if (baboon_present) | 250 | if (baboon_present) |
| 259 | baboon_register_interrupts(); | 251 | baboon_register_interrupts(); |
| 260 | iop_register_interrupts(); | 252 | iop_register_interrupts(); |
| 261 | request_irq(IRQ_AUTO_7, mac_nmi_handler, 0, "NMI", | 253 | if (request_irq(IRQ_AUTO_7, mac_nmi_handler, 0, "NMI", |
| 262 | mac_nmi_handler); | 254 | mac_nmi_handler)) |
| 255 | pr_err("Couldn't register NMI\n"); | ||
| 263 | #ifdef DEBUG_MACINTS | 256 | #ifdef DEBUG_MACINTS |
| 264 | printk("mac_init_IRQ(): Done!\n"); | 257 | printk("mac_init_IRQ(): Done!\n"); |
| 265 | #endif | 258 | #endif |
diff --git a/arch/m68k/mac/misc.c b/arch/m68k/mac/misc.c index a44c7086ab39..5d818568b343 100644 --- a/arch/m68k/mac/misc.c +++ b/arch/m68k/mac/misc.c | |||
| @@ -35,7 +35,6 @@ | |||
| 35 | 35 | ||
| 36 | #define RTC_OFFSET 2082844800 | 36 | #define RTC_OFFSET 2082844800 |
| 37 | 37 | ||
| 38 | extern struct mac_booter_data mac_bi_data; | ||
| 39 | static void (*rom_reset)(void); | 38 | static void (*rom_reset)(void); |
| 40 | 39 | ||
| 41 | #ifdef CONFIG_ADB_CUDA | 40 | #ifdef CONFIG_ADB_CUDA |
diff --git a/arch/m68k/mac/oss.c b/arch/m68k/mac/oss.c index 8426501119ca..f3d23d6ebcf8 100644 --- a/arch/m68k/mac/oss.c +++ b/arch/m68k/mac/oss.c | |||
| @@ -66,16 +66,21 @@ void __init oss_init(void) | |||
| 66 | 66 | ||
| 67 | void __init oss_register_interrupts(void) | 67 | void __init oss_register_interrupts(void) |
| 68 | { | 68 | { |
| 69 | request_irq(OSS_IRQLEV_SCSI, oss_irq, IRQ_FLG_LOCK, | 69 | if (request_irq(OSS_IRQLEV_SCSI, oss_irq, IRQ_FLG_LOCK, |
| 70 | "scsi", (void *) oss); | 70 | "scsi", (void *) oss)) |
| 71 | request_irq(OSS_IRQLEV_IOPSCC, mac_scc_dispatch, IRQ_FLG_LOCK, | 71 | pr_err("Couldn't register %s interrupt\n", "scsi"); |
| 72 | "scc", mac_scc_dispatch); | 72 | if (request_irq(OSS_IRQLEV_IOPSCC, mac_scc_dispatch, IRQ_FLG_LOCK, |
| 73 | request_irq(OSS_IRQLEV_NUBUS, oss_nubus_irq, IRQ_FLG_LOCK, | 73 | "scc", mac_scc_dispatch)) |
| 74 | "nubus", (void *) oss); | 74 | pr_err("Couldn't register %s interrupt\n", "scc"); |
| 75 | request_irq(OSS_IRQLEV_SOUND, oss_irq, IRQ_FLG_LOCK, | 75 | if (request_irq(OSS_IRQLEV_NUBUS, oss_nubus_irq, IRQ_FLG_LOCK, |
| 76 | "sound", (void *) oss); | 76 | "nubus", (void *) oss)) |
| 77 | request_irq(OSS_IRQLEV_VIA1, via1_irq, IRQ_FLG_LOCK, | 77 | pr_err("Couldn't register %s interrupt\n", "nubus"); |
| 78 | "via1", (void *) via1); | 78 | if (request_irq(OSS_IRQLEV_SOUND, oss_irq, IRQ_FLG_LOCK, |
| 79 | "sound", (void *) oss)) | ||
| 80 | pr_err("Couldn't register %s interrupt\n", "sound"); | ||
| 81 | if (request_irq(OSS_IRQLEV_VIA1, via1_irq, IRQ_FLG_LOCK, | ||
| 82 | "via1", (void *) via1)) | ||
| 83 | pr_err("Couldn't register %s interrupt\n", "via1"); | ||
| 79 | } | 84 | } |
| 80 | 85 | ||
| 81 | /* | 86 | /* |
diff --git a/arch/m68k/mac/psc.c b/arch/m68k/mac/psc.c index f84a4dd64f94..ba6ccab64018 100644 --- a/arch/m68k/mac/psc.c +++ b/arch/m68k/mac/psc.c | |||
| @@ -117,10 +117,14 @@ void __init psc_init(void) | |||
| 117 | 117 | ||
| 118 | void __init psc_register_interrupts(void) | 118 | void __init psc_register_interrupts(void) |
| 119 | { | 119 | { |
| 120 | request_irq(IRQ_AUTO_3, psc_irq, 0, "psc3", (void *) 0x30); | 120 | if (request_irq(IRQ_AUTO_3, psc_irq, 0, "psc3", (void *) 0x30)) |
| 121 | request_irq(IRQ_AUTO_4, psc_irq, 0, "psc4", (void *) 0x40); | 121 | pr_err("Couldn't register psc%d interrupt\n", 3); |
| 122 | request_irq(IRQ_AUTO_5, psc_irq, 0, "psc5", (void *) 0x50); | 122 | if (request_irq(IRQ_AUTO_4, psc_irq, 0, "psc4", (void *) 0x40)) |
| 123 | request_irq(IRQ_AUTO_6, psc_irq, 0, "psc6", (void *) 0x60); | 123 | pr_err("Couldn't register psc%d interrupt\n", 4); |
| 124 | if (request_irq(IRQ_AUTO_5, psc_irq, 0, "psc5", (void *) 0x50)) | ||
| 125 | pr_err("Couldn't register psc%d interrupt\n", 5); | ||
| 126 | if (request_irq(IRQ_AUTO_6, psc_irq, 0, "psc6", (void *) 0x60)) | ||
| 127 | pr_err("Couldn't register psc%d interrupt\n", 6); | ||
| 124 | } | 128 | } |
| 125 | 129 | ||
| 126 | /* | 130 | /* |
diff --git a/arch/m68k/mac/via.c b/arch/m68k/mac/via.c index f01d418e64fe..7d97ba54536e 100644 --- a/arch/m68k/mac/via.c +++ b/arch/m68k/mac/via.c | |||
| @@ -34,6 +34,7 @@ | |||
| 34 | #include <asm/macints.h> | 34 | #include <asm/macints.h> |
| 35 | #include <asm/mac_via.h> | 35 | #include <asm/mac_via.h> |
| 36 | #include <asm/mac_psc.h> | 36 | #include <asm/mac_psc.h> |
| 37 | #include <asm/mac_oss.h> | ||
| 37 | 38 | ||
| 38 | volatile __u8 *via1, *via2; | 39 | volatile __u8 *via1, *via2; |
| 39 | int rbv_present; | 40 | int rbv_present; |
| @@ -84,7 +85,6 @@ void via_irq_disable(int irq); | |||
| 84 | void via_irq_clear(int irq); | 85 | void via_irq_clear(int irq); |
| 85 | 86 | ||
| 86 | extern irqreturn_t mac_scc_dispatch(int, void *); | 87 | extern irqreturn_t mac_scc_dispatch(int, void *); |
| 87 | extern int oss_present; | ||
| 88 | 88 | ||
| 89 | /* | 89 | /* |
| 90 | * Initialize the VIAs | 90 | * Initialize the VIAs |
| @@ -283,7 +283,8 @@ void __init via_init_clock(irq_handler_t func) | |||
| 283 | via1[vT1CL] = MAC_CLOCK_LOW; | 283 | via1[vT1CL] = MAC_CLOCK_LOW; |
| 284 | via1[vT1CH] = MAC_CLOCK_HIGH; | 284 | via1[vT1CH] = MAC_CLOCK_HIGH; |
| 285 | 285 | ||
| 286 | request_irq(IRQ_MAC_TIMER_1, func, IRQ_FLG_LOCK, "timer", func); | 286 | if (request_irq(IRQ_MAC_TIMER_1, func, IRQ_FLG_LOCK, "timer", func)) |
| 287 | pr_err("Couldn't register %s interrupt\n", "timer"); | ||
| 287 | } | 288 | } |
| 288 | 289 | ||
| 289 | /* | 290 | /* |
| @@ -293,25 +294,31 @@ void __init via_init_clock(irq_handler_t func) | |||
| 293 | void __init via_register_interrupts(void) | 294 | void __init via_register_interrupts(void) |
| 294 | { | 295 | { |
| 295 | if (via_alt_mapping) { | 296 | if (via_alt_mapping) { |
| 296 | request_irq(IRQ_AUTO_1, via1_irq, | 297 | if (request_irq(IRQ_AUTO_1, via1_irq, |
| 297 | IRQ_FLG_LOCK|IRQ_FLG_FAST, "software", | 298 | IRQ_FLG_LOCK|IRQ_FLG_FAST, "software", |
| 298 | (void *) via1); | 299 | (void *) via1)) |
| 299 | request_irq(IRQ_AUTO_6, via1_irq, | 300 | pr_err("Couldn't register %s interrupt\n", "software"); |
| 301 | if (request_irq(IRQ_AUTO_6, via1_irq, | ||
| 300 | IRQ_FLG_LOCK|IRQ_FLG_FAST, "via1", | 302 | IRQ_FLG_LOCK|IRQ_FLG_FAST, "via1", |
| 301 | (void *) via1); | 303 | (void *) via1)) |
| 304 | pr_err("Couldn't register %s interrupt\n", "via1"); | ||
| 302 | } else { | 305 | } else { |
| 303 | request_irq(IRQ_AUTO_1, via1_irq, | 306 | if (request_irq(IRQ_AUTO_1, via1_irq, |
| 304 | IRQ_FLG_LOCK|IRQ_FLG_FAST, "via1", | 307 | IRQ_FLG_LOCK|IRQ_FLG_FAST, "via1", |
| 305 | (void *) via1); | 308 | (void *) via1)) |
| 309 | pr_err("Couldn't register %s interrupt\n", "via1"); | ||
| 306 | } | 310 | } |
| 307 | request_irq(IRQ_AUTO_2, via2_irq, IRQ_FLG_LOCK|IRQ_FLG_FAST, | 311 | if (request_irq(IRQ_AUTO_2, via2_irq, IRQ_FLG_LOCK|IRQ_FLG_FAST, |
| 308 | "via2", (void *) via2); | 312 | "via2", (void *) via2)) |
| 313 | pr_err("Couldn't register %s interrupt\n", "via2"); | ||
| 309 | if (!psc_present) { | 314 | if (!psc_present) { |
| 310 | request_irq(IRQ_AUTO_4, mac_scc_dispatch, IRQ_FLG_LOCK, | 315 | if (request_irq(IRQ_AUTO_4, mac_scc_dispatch, IRQ_FLG_LOCK, |
| 311 | "scc", mac_scc_dispatch); | 316 | "scc", mac_scc_dispatch)) |
| 317 | pr_err("Couldn't register %s interrupt\n", "scc"); | ||
| 312 | } | 318 | } |
| 313 | request_irq(IRQ_MAC_NUBUS, via_nubus_irq, IRQ_FLG_LOCK|IRQ_FLG_FAST, | 319 | if (request_irq(IRQ_MAC_NUBUS, via_nubus_irq, |
| 314 | "nubus", (void *) via2); | 320 | IRQ_FLG_LOCK|IRQ_FLG_FAST, "nubus", (void *) via2)) |
| 321 | pr_err("Couldn't register %s interrupt\n", "nubus"); | ||
| 315 | } | 322 | } |
| 316 | 323 | ||
| 317 | /* | 324 | /* |
diff --git a/arch/m68k/math-emu/fp_log.c b/arch/m68k/math-emu/fp_log.c index b1033ae0d6f0..367ecee2f981 100644 --- a/arch/m68k/math-emu/fp_log.c +++ b/arch/m68k/math-emu/fp_log.c | |||
| @@ -24,7 +24,6 @@ static const struct fp_ext fp_one = | |||
| 24 | 24 | ||
| 25 | extern struct fp_ext *fp_fadd(struct fp_ext *dest, const struct fp_ext *src); | 25 | extern struct fp_ext *fp_fadd(struct fp_ext *dest, const struct fp_ext *src); |
| 26 | extern struct fp_ext *fp_fdiv(struct fp_ext *dest, const struct fp_ext *src); | 26 | extern struct fp_ext *fp_fdiv(struct fp_ext *dest, const struct fp_ext *src); |
| 27 | extern struct fp_ext *fp_fmul(struct fp_ext *dest, const struct fp_ext *src); | ||
| 28 | 27 | ||
| 29 | struct fp_ext * | 28 | struct fp_ext * |
| 30 | fp_fsqrt(struct fp_ext *dest, struct fp_ext *src) | 29 | fp_fsqrt(struct fp_ext *dest, struct fp_ext *src) |
diff --git a/arch/m68k/mm/init.c b/arch/m68k/mm/init.c index 81bb08ceec18..0007b2adf3a3 100644 --- a/arch/m68k/mm/init.c +++ b/arch/m68k/mm/init.c | |||
| @@ -28,6 +28,7 @@ | |||
| 28 | #ifdef CONFIG_ATARI | 28 | #ifdef CONFIG_ATARI |
| 29 | #include <asm/atari_stram.h> | 29 | #include <asm/atari_stram.h> |
| 30 | #endif | 30 | #endif |
| 31 | #include <asm/sections.h> | ||
| 31 | #include <asm/tlb.h> | 32 | #include <asm/tlb.h> |
| 32 | 33 | ||
| 33 | DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); | 34 | DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); |
| @@ -73,9 +74,6 @@ extern void init_pointer_table(unsigned long ptable); | |||
| 73 | 74 | ||
| 74 | /* References to section boundaries */ | 75 | /* References to section boundaries */ |
| 75 | 76 | ||
| 76 | extern char _text[], _etext[]; | ||
| 77 | extern char __init_begin[], __init_end[]; | ||
| 78 | |||
| 79 | extern pmd_t *zero_pgtable; | 77 | extern pmd_t *zero_pgtable; |
| 80 | 78 | ||
| 81 | void __init mem_init(void) | 79 | void __init mem_init(void) |
diff --git a/arch/m68k/mm/motorola.c b/arch/m68k/mm/motorola.c index c5dbb9bdb322..4665fc84b7dc 100644 --- a/arch/m68k/mm/motorola.c +++ b/arch/m68k/mm/motorola.c | |||
| @@ -30,6 +30,7 @@ | |||
| 30 | #ifdef CONFIG_ATARI | 30 | #ifdef CONFIG_ATARI |
| 31 | #include <asm/atari_stram.h> | 31 | #include <asm/atari_stram.h> |
| 32 | #endif | 32 | #endif |
| 33 | #include <asm/sections.h> | ||
| 33 | 34 | ||
| 34 | #undef DEBUG | 35 | #undef DEBUG |
| 35 | 36 | ||
| @@ -301,14 +302,12 @@ void __init paging_init(void) | |||
| 301 | } | 302 | } |
| 302 | } | 303 | } |
| 303 | 304 | ||
| 304 | extern char __init_begin, __init_end; | ||
| 305 | |||
| 306 | void free_initmem(void) | 305 | void free_initmem(void) |
| 307 | { | 306 | { |
| 308 | unsigned long addr; | 307 | unsigned long addr; |
| 309 | 308 | ||
| 310 | addr = (unsigned long)&__init_begin; | 309 | addr = (unsigned long)__init_begin; |
| 311 | for (; addr < (unsigned long)&__init_end; addr += PAGE_SIZE) { | 310 | for (; addr < (unsigned long)__init_end; addr += PAGE_SIZE) { |
| 312 | virt_to_page(addr)->flags &= ~(1 << PG_reserved); | 311 | virt_to_page(addr)->flags &= ~(1 << PG_reserved); |
| 313 | init_page_count(virt_to_page(addr)); | 312 | init_page_count(virt_to_page(addr)); |
| 314 | free_page(addr); | 313 | free_page(addr); |
diff --git a/arch/m68k/mvme147/config.c b/arch/m68k/mvme147/config.c index 43cdf476ffab..100baaa692a1 100644 --- a/arch/m68k/mvme147/config.c +++ b/arch/m68k/mvme147/config.c | |||
| @@ -42,7 +42,6 @@ extern unsigned long mvme147_gettimeoffset (void); | |||
| 42 | extern int mvme147_hwclk (int, struct rtc_time *); | 42 | extern int mvme147_hwclk (int, struct rtc_time *); |
| 43 | extern int mvme147_set_clock_mmss (unsigned long); | 43 | extern int mvme147_set_clock_mmss (unsigned long); |
| 44 | extern void mvme147_reset (void); | 44 | extern void mvme147_reset (void); |
| 45 | extern void mvme147_waitbut(void); | ||
| 46 | 45 | ||
| 47 | 46 | ||
| 48 | static int bcd2int (unsigned char b); | 47 | static int bcd2int (unsigned char b); |
| @@ -115,8 +114,9 @@ static irqreturn_t mvme147_timer_int (int irq, void *dev_id) | |||
| 115 | void mvme147_sched_init (irq_handler_t timer_routine) | 114 | void mvme147_sched_init (irq_handler_t timer_routine) |
| 116 | { | 115 | { |
| 117 | tick_handler = timer_routine; | 116 | tick_handler = timer_routine; |
| 118 | request_irq (PCC_IRQ_TIMER1, mvme147_timer_int, | 117 | if (request_irq(PCC_IRQ_TIMER1, mvme147_timer_int, IRQ_FLG_REPLACE, |
| 119 | IRQ_FLG_REPLACE, "timer 1", NULL); | 118 | "timer 1", NULL)) |
| 119 | pr_err("Couldn't register timer interrupt\n"); | ||
| 120 | 120 | ||
| 121 | /* Init the clock with a value */ | 121 | /* Init the clock with a value */ |
| 122 | /* our clock goes off every 6.25us */ | 122 | /* our clock goes off every 6.25us */ |
diff --git a/arch/m68k/mvme16x/config.c b/arch/m68k/mvme16x/config.c index 1521826fc3c7..11edf61cc2c4 100644 --- a/arch/m68k/mvme16x/config.c +++ b/arch/m68k/mvme16x/config.c | |||
| @@ -48,7 +48,6 @@ extern unsigned long mvme16x_gettimeoffset (void); | |||
| 48 | extern int mvme16x_hwclk (int, struct rtc_time *); | 48 | extern int mvme16x_hwclk (int, struct rtc_time *); |
| 49 | extern int mvme16x_set_clock_mmss (unsigned long); | 49 | extern int mvme16x_set_clock_mmss (unsigned long); |
| 50 | extern void mvme16x_reset (void); | 50 | extern void mvme16x_reset (void); |
| 51 | extern void mvme16x_waitbut(void); | ||
| 52 | 51 | ||
| 53 | int bcd2int (unsigned char b); | 52 | int bcd2int (unsigned char b); |
| 54 | 53 | ||
diff --git a/arch/m68k/q40/config.c b/arch/m68k/q40/config.c index 7110546e3c00..31ab3f08bbda 100644 --- a/arch/m68k/q40/config.c +++ b/arch/m68k/q40/config.c | |||
| @@ -36,7 +36,6 @@ | |||
| 36 | #include <asm/machdep.h> | 36 | #include <asm/machdep.h> |
| 37 | #include <asm/q40_master.h> | 37 | #include <asm/q40_master.h> |
| 38 | 38 | ||
| 39 | extern irqreturn_t q40_process_int(int level, struct pt_regs *regs); | ||
| 40 | extern void q40_init_IRQ(void); | 39 | extern void q40_init_IRQ(void); |
| 41 | static void q40_get_model(char *model); | 40 | static void q40_get_model(char *model); |
| 42 | extern void q40_sched_init(irq_handler_t handler); | 41 | extern void q40_sched_init(irq_handler_t handler); |
| @@ -47,8 +46,6 @@ static unsigned int q40_get_ss(void); | |||
| 47 | static int q40_set_clock_mmss(unsigned long); | 46 | static int q40_set_clock_mmss(unsigned long); |
| 48 | static int q40_get_rtc_pll(struct rtc_pll_info *pll); | 47 | static int q40_get_rtc_pll(struct rtc_pll_info *pll); |
| 49 | static int q40_set_rtc_pll(struct rtc_pll_info *pll); | 48 | static int q40_set_rtc_pll(struct rtc_pll_info *pll); |
| 50 | extern void q40_waitbut(void); | ||
| 51 | void q40_set_vectors(void); | ||
| 52 | 49 | ||
| 53 | extern void q40_mksound(unsigned int /*freq*/, unsigned int /*ticks*/); | 50 | extern void q40_mksound(unsigned int /*freq*/, unsigned int /*ticks*/); |
| 54 | 51 | ||
diff --git a/arch/m68k/sun3/config.c b/arch/m68k/sun3/config.c index 8dfaa201342e..2ca25bd01a96 100644 --- a/arch/m68k/sun3/config.c +++ b/arch/m68k/sun3/config.c | |||
| @@ -27,23 +27,21 @@ | |||
| 27 | #include <asm/sun3mmu.h> | 27 | #include <asm/sun3mmu.h> |
| 28 | #include <asm/rtc.h> | 28 | #include <asm/rtc.h> |
| 29 | #include <asm/machdep.h> | 29 | #include <asm/machdep.h> |
| 30 | #include <asm/idprom.h> | ||
| 30 | #include <asm/intersil.h> | 31 | #include <asm/intersil.h> |
| 31 | #include <asm/irq.h> | 32 | #include <asm/irq.h> |
| 33 | #include <asm/sections.h> | ||
| 32 | #include <asm/segment.h> | 34 | #include <asm/segment.h> |
| 33 | #include <asm/sun3ints.h> | 35 | #include <asm/sun3ints.h> |
| 34 | 36 | ||
| 35 | extern char _text, _end; | ||
| 36 | |||
| 37 | char sun3_reserved_pmeg[SUN3_PMEGS_NUM]; | 37 | char sun3_reserved_pmeg[SUN3_PMEGS_NUM]; |
| 38 | 38 | ||
| 39 | extern unsigned long sun3_gettimeoffset(void); | 39 | extern unsigned long sun3_gettimeoffset(void); |
| 40 | static void sun3_sched_init(irq_handler_t handler); | 40 | static void sun3_sched_init(irq_handler_t handler); |
| 41 | extern void sun3_get_model (char* model); | 41 | extern void sun3_get_model (char* model); |
| 42 | extern void idprom_init (void); | ||
| 43 | extern int sun3_hwclk(int set, struct rtc_time *t); | 42 | extern int sun3_hwclk(int set, struct rtc_time *t); |
| 44 | 43 | ||
| 45 | volatile char* clock_va; | 44 | volatile char* clock_va; |
| 46 | extern volatile unsigned char* sun3_intreg; | ||
| 47 | extern unsigned long availmem; | 45 | extern unsigned long availmem; |
| 48 | unsigned long num_pages; | 46 | unsigned long num_pages; |
| 49 | 47 | ||
| @@ -149,7 +147,7 @@ void __init config_sun3(void) | |||
| 149 | mach_halt = sun3_halt; | 147 | mach_halt = sun3_halt; |
| 150 | mach_get_hardware_list = sun3_get_hardware_list; | 148 | mach_get_hardware_list = sun3_get_hardware_list; |
| 151 | 149 | ||
| 152 | memory_start = ((((int)&_end) + 0x2000) & ~0x1fff); | 150 | memory_start = ((((unsigned long)_end) + 0x2000) & ~0x1fff); |
| 153 | // PROM seems to want the last couple of physical pages. --m | 151 | // PROM seems to want the last couple of physical pages. --m |
| 154 | memory_end = *(romvec->pv_sun3mem) + PAGE_OFFSET - 2*PAGE_SIZE; | 152 | memory_end = *(romvec->pv_sun3mem) + PAGE_OFFSET - 2*PAGE_SIZE; |
| 155 | 153 | ||
diff --git a/arch/m68k/sun3/mmu_emu.c b/arch/m68k/sun3/mmu_emu.c index 60f9d4500d72..3cd19390aae5 100644 --- a/arch/m68k/sun3/mmu_emu.c +++ b/arch/m68k/sun3/mmu_emu.c | |||
| @@ -27,7 +27,6 @@ | |||
| 27 | #include <asm/mmu_context.h> | 27 | #include <asm/mmu_context.h> |
| 28 | #include <asm/dvma.h> | 28 | #include <asm/dvma.h> |
| 29 | 29 | ||
| 30 | extern void prom_reboot (char *) __attribute__ ((__noreturn__)); | ||
| 31 | 30 | ||
| 32 | #undef DEBUG_MMU_EMU | 31 | #undef DEBUG_MMU_EMU |
| 33 | #define DEBUG_PROM_MAPS | 32 | #define DEBUG_PROM_MAPS |
diff --git a/arch/m68k/sun3/sun3ints.c b/arch/m68k/sun3/sun3ints.c index 7364cd67455e..ad90393a3361 100644 --- a/arch/m68k/sun3/sun3ints.c +++ b/arch/m68k/sun3/sun3ints.c | |||
| @@ -105,7 +105,10 @@ void __init sun3_init_IRQ(void) | |||
| 105 | m68k_setup_irq_controller(&sun3_irq_controller, IRQ_AUTO_1, 7); | 105 | m68k_setup_irq_controller(&sun3_irq_controller, IRQ_AUTO_1, 7); |
| 106 | m68k_setup_user_interrupt(VEC_USER, 128, NULL); | 106 | m68k_setup_user_interrupt(VEC_USER, 128, NULL); |
| 107 | 107 | ||
| 108 | request_irq(IRQ_AUTO_5, sun3_int5, 0, "int5", NULL); | 108 | if (request_irq(IRQ_AUTO_5, sun3_int5, 0, "int5", NULL)) |
| 109 | request_irq(IRQ_AUTO_7, sun3_int7, 0, "int7", NULL); | 109 | pr_err("Couldn't register %s interrupt\n", "int5"); |
| 110 | request_irq(IRQ_USER+127, sun3_vec255, 0, "vec255", NULL); | 110 | if (request_irq(IRQ_AUTO_7, sun3_int7, 0, "int7", NULL)) |
| 111 | pr_err("Couldn't register %s interrupt\n", "int7"); | ||
| 112 | if (request_irq(IRQ_USER+127, sun3_vec255, 0, "vec255", NULL)) | ||
| 113 | pr_err("Couldn't register %s interrupt\n", "vec255"); | ||
| 111 | } | 114 | } |
diff --git a/arch/m68k/sun3x/config.c b/arch/m68k/sun3x/config.c index 2b1ca2db070f..fc599fad4a54 100644 --- a/arch/m68k/sun3x/config.c +++ b/arch/m68k/sun3x/config.c | |||
| @@ -23,7 +23,6 @@ | |||
| 23 | #include "time.h" | 23 | #include "time.h" |
| 24 | 24 | ||
| 25 | volatile char *clock_va; | 25 | volatile char *clock_va; |
| 26 | extern volatile unsigned char *sun3_intreg; | ||
| 27 | 26 | ||
| 28 | extern void sun3_get_model(char *model); | 27 | extern void sun3_get_model(char *model); |
| 29 | 28 | ||
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index a5255e7c79e0..52c80c2a57f2 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig | |||
| @@ -595,6 +595,44 @@ config WR_PPMC | |||
| 595 | This enables support for the Wind River MIPS32 4KC PPMC evaluation | 595 | This enables support for the Wind River MIPS32 4KC PPMC evaluation |
| 596 | board, which is based on GT64120 bridge chip. | 596 | board, which is based on GT64120 bridge chip. |
| 597 | 597 | ||
| 598 | config CAVIUM_OCTEON_SIMULATOR | ||
| 599 | bool "Support for the Cavium Networks Octeon Simulator" | ||
| 600 | select CEVT_R4K | ||
| 601 | select 64BIT_PHYS_ADDR | ||
| 602 | select DMA_COHERENT | ||
| 603 | select SYS_SUPPORTS_64BIT_KERNEL | ||
| 604 | select SYS_SUPPORTS_BIG_ENDIAN | ||
| 605 | select SYS_SUPPORTS_HIGHMEM | ||
| 606 | select CPU_CAVIUM_OCTEON | ||
| 607 | help | ||
| 608 | The Octeon simulator is software performance model of the Cavium | ||
| 609 | Octeon Processor. It supports simulating Octeon processors on x86 | ||
| 610 | hardware. | ||
| 611 | |||
| 612 | config CAVIUM_OCTEON_REFERENCE_BOARD | ||
| 613 | bool "Support for the Cavium Networks Octeon reference board" | ||
| 614 | select CEVT_R4K | ||
| 615 | select 64BIT_PHYS_ADDR | ||
| 616 | select DMA_COHERENT | ||
| 617 | select SYS_SUPPORTS_64BIT_KERNEL | ||
| 618 | select SYS_SUPPORTS_BIG_ENDIAN | ||
| 619 | select SYS_SUPPORTS_HIGHMEM | ||
| 620 | select SYS_HAS_EARLY_PRINTK | ||
| 621 | select CPU_CAVIUM_OCTEON | ||
| 622 | select SWAP_IO_SPACE | ||
| 623 | help | ||
| 624 | This option supports all of the Octeon reference boards from Cavium | ||
| 625 | Networks. It builds a kernel that dynamically determines the Octeon | ||
| 626 | CPU type and supports all known board reference implementations. | ||
| 627 | Some of the supported boards are: | ||
| 628 | EBT3000 | ||
| 629 | EBH3000 | ||
| 630 | EBH3100 | ||
| 631 | Thunder | ||
| 632 | Kodama | ||
| 633 | Hikari | ||
| 634 | Say Y here for most Octeon reference boards. | ||
| 635 | |||
| 598 | endchoice | 636 | endchoice |
| 599 | 637 | ||
| 600 | source "arch/mips/alchemy/Kconfig" | 638 | source "arch/mips/alchemy/Kconfig" |
| @@ -607,6 +645,7 @@ source "arch/mips/sgi-ip27/Kconfig" | |||
| 607 | source "arch/mips/sibyte/Kconfig" | 645 | source "arch/mips/sibyte/Kconfig" |
| 608 | source "arch/mips/txx9/Kconfig" | 646 | source "arch/mips/txx9/Kconfig" |
| 609 | source "arch/mips/vr41xx/Kconfig" | 647 | source "arch/mips/vr41xx/Kconfig" |
| 648 | source "arch/mips/cavium-octeon/Kconfig" | ||
| 610 | 649 | ||
| 611 | endmenu | 650 | endmenu |
| 612 | 651 | ||
| @@ -682,7 +721,11 @@ config CEVT_DS1287 | |||
| 682 | config CEVT_GT641XX | 721 | config CEVT_GT641XX |
| 683 | bool | 722 | bool |
| 684 | 723 | ||
| 724 | config CEVT_R4K_LIB | ||
| 725 | bool | ||
| 726 | |||
| 685 | config CEVT_R4K | 727 | config CEVT_R4K |
| 728 | select CEVT_R4K_LIB | ||
| 686 | bool | 729 | bool |
| 687 | 730 | ||
| 688 | config CEVT_SB1250 | 731 | config CEVT_SB1250 |
| @@ -697,7 +740,11 @@ config CSRC_BCM1480 | |||
| 697 | config CSRC_IOASIC | 740 | config CSRC_IOASIC |
| 698 | bool | 741 | bool |
| 699 | 742 | ||
| 743 | config CSRC_R4K_LIB | ||
| 744 | bool | ||
| 745 | |||
| 700 | config CSRC_R4K | 746 | config CSRC_R4K |
| 747 | select CSRC_R4K_LIB | ||
| 701 | bool | 748 | bool |
| 702 | 749 | ||
| 703 | config CSRC_SB1250 | 750 | config CSRC_SB1250 |
| @@ -835,6 +882,9 @@ config IRQ_GT641XX | |||
| 835 | config IRQ_GIC | 882 | config IRQ_GIC |
| 836 | bool | 883 | bool |
| 837 | 884 | ||
| 885 | config IRQ_CPU_OCTEON | ||
| 886 | bool | ||
| 887 | |||
| 838 | config MIPS_BOARDS_GEN | 888 | config MIPS_BOARDS_GEN |
| 839 | bool | 889 | bool |
| 840 | 890 | ||
| @@ -924,7 +974,7 @@ config BOOT_ELF32 | |||
| 924 | config MIPS_L1_CACHE_SHIFT | 974 | config MIPS_L1_CACHE_SHIFT |
| 925 | int | 975 | int |
| 926 | default "4" if MACH_DECSTATION || MIKROTIK_RB532 | 976 | default "4" if MACH_DECSTATION || MIKROTIK_RB532 |
| 927 | default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM | 977 | default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON |
| 928 | default "4" if PMC_MSP4200_EVAL | 978 | default "4" if PMC_MSP4200_EVAL |
| 929 | default "5" | 979 | default "5" |
| 930 | 980 | ||
| @@ -1185,6 +1235,23 @@ config CPU_SB1 | |||
| 1185 | select CPU_SUPPORTS_HIGHMEM | 1235 | select CPU_SUPPORTS_HIGHMEM |
| 1186 | select WEAK_ORDERING | 1236 | select WEAK_ORDERING |
| 1187 | 1237 | ||
| 1238 | config CPU_CAVIUM_OCTEON | ||
| 1239 | bool "Cavium Octeon processor" | ||
| 1240 | select IRQ_CPU | ||
| 1241 | select IRQ_CPU_OCTEON | ||
| 1242 | select CPU_HAS_PREFETCH | ||
| 1243 | select CPU_SUPPORTS_64BIT_KERNEL | ||
| 1244 | select SYS_SUPPORTS_SMP | ||
| 1245 | select NR_CPUS_DEFAULT_16 | ||
| 1246 | select WEAK_ORDERING | ||
| 1247 | select WEAK_REORDERING_BEYOND_LLSC | ||
| 1248 | select CPU_SUPPORTS_HIGHMEM | ||
| 1249 | help | ||
| 1250 | The Cavium Octeon processor is a highly integrated chip containing | ||
| 1251 | many ethernet hardware widgets for networking tasks. The processor | ||
| 1252 | can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets. | ||
| 1253 | Full details can be found at http://www.caviumnetworks.com. | ||
| 1254 | |||
| 1188 | endchoice | 1255 | endchoice |
| 1189 | 1256 | ||
| 1190 | config SYS_HAS_CPU_LOONGSON2 | 1257 | config SYS_HAS_CPU_LOONGSON2 |
| @@ -1285,7 +1352,7 @@ config CPU_MIPSR1 | |||
| 1285 | 1352 | ||
| 1286 | config CPU_MIPSR2 | 1353 | config CPU_MIPSR2 |
| 1287 | bool | 1354 | bool |
| 1288 | default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 | 1355 | default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON |
| 1289 | 1356 | ||
| 1290 | config SYS_SUPPORTS_32BIT_KERNEL | 1357 | config SYS_SUPPORTS_32BIT_KERNEL |
| 1291 | bool | 1358 | bool |
diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 28c55f608913..21b00e95daef 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile | |||
| @@ -144,6 +144,10 @@ cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-march=sb1,-march=r5000) \ | |||
| 144 | cflags-$(CONFIG_CPU_R8000) += -march=r8000 -Wa,--trap | 144 | cflags-$(CONFIG_CPU_R8000) += -march=r8000 -Wa,--trap |
| 145 | cflags-$(CONFIG_CPU_R10000) += $(call cc-option,-march=r10000,-march=r8000) \ | 145 | cflags-$(CONFIG_CPU_R10000) += $(call cc-option,-march=r10000,-march=r8000) \ |
| 146 | -Wa,--trap | 146 | -Wa,--trap |
| 147 | cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += $(call cc-option,-march=octeon) -Wa,--trap | ||
| 148 | ifeq (,$(findstring march=octeon, $(cflags-$(CONFIG_CPU_CAVIUM_OCTEON)))) | ||
| 149 | cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -Wa,-march=octeon | ||
| 150 | endif | ||
| 147 | 151 | ||
| 148 | cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,) | 152 | cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,) |
| 149 | cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += $(call cc-option,-mfix-r4400,) | 153 | cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += $(call cc-option,-mfix-r4400,) |
| @@ -184,84 +188,84 @@ cflags-$(CONFIG_SOC_AU1X00) += -I$(srctree)/arch/mips/include/asm/mach-au1x00 | |||
| 184 | # | 188 | # |
| 185 | # AMD Alchemy Pb1000 eval board | 189 | # AMD Alchemy Pb1000 eval board |
| 186 | # | 190 | # |
| 187 | libs-$(CONFIG_MIPS_PB1000) += arch/mips/alchemy/pb1000/ | 191 | core-$(CONFIG_MIPS_PB1000) += arch/mips/alchemy/devboards/ |
| 188 | cflags-$(CONFIG_MIPS_PB1000) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00 | 192 | cflags-$(CONFIG_MIPS_PB1000) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00 |
| 189 | load-$(CONFIG_MIPS_PB1000) += 0xffffffff80100000 | 193 | load-$(CONFIG_MIPS_PB1000) += 0xffffffff80100000 |
| 190 | 194 | ||
| 191 | # | 195 | # |
| 192 | # AMD Alchemy Pb1100 eval board | 196 | # AMD Alchemy Pb1100 eval board |
| 193 | # | 197 | # |
| 194 | libs-$(CONFIG_MIPS_PB1100) += arch/mips/alchemy/pb1100/ | 198 | core-$(CONFIG_MIPS_PB1100) += arch/mips/alchemy/devboards/ |
| 195 | cflags-$(CONFIG_MIPS_PB1100) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00 | 199 | cflags-$(CONFIG_MIPS_PB1100) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00 |
| 196 | load-$(CONFIG_MIPS_PB1100) += 0xffffffff80100000 | 200 | load-$(CONFIG_MIPS_PB1100) += 0xffffffff80100000 |
| 197 | 201 | ||
| 198 | # | 202 | # |
| 199 | # AMD Alchemy Pb1500 eval board | 203 | # AMD Alchemy Pb1500 eval board |
| 200 | # | 204 | # |
| 201 | libs-$(CONFIG_MIPS_PB1500) += arch/mips/alchemy/pb1500/ | 205 | core-$(CONFIG_MIPS_PB1500) += arch/mips/alchemy/devboards/ |
| 202 | cflags-$(CONFIG_MIPS_PB1500) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00 | 206 | cflags-$(CONFIG_MIPS_PB1500) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00 |
| 203 | load-$(CONFIG_MIPS_PB1500) += 0xffffffff80100000 | 207 | load-$(CONFIG_MIPS_PB1500) += 0xffffffff80100000 |
| 204 | 208 | ||
| 205 | # | 209 | # |
| 206 | # AMD Alchemy Pb1550 eval board | 210 | # AMD Alchemy Pb1550 eval board |
| 207 | # | 211 | # |
| 208 | libs-$(CONFIG_MIPS_PB1550) += arch/mips/alchemy/pb1550/ | 212 | core-$(CONFIG_MIPS_PB1550) += arch/mips/alchemy/devboards/ |
| 209 | cflags-$(CONFIG_MIPS_PB1550) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00 | 213 | cflags-$(CONFIG_MIPS_PB1550) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00 |
| 210 | load-$(CONFIG_MIPS_PB1550) += 0xffffffff80100000 | 214 | load-$(CONFIG_MIPS_PB1550) += 0xffffffff80100000 |
| 211 | 215 | ||
| 212 | # | 216 | # |
| 213 | # AMD Alchemy Pb1200 eval board | 217 | # AMD Alchemy Pb1200 eval board |
| 214 | # | 218 | # |
| 215 | libs-$(CONFIG_MIPS_PB1200) += arch/mips/alchemy/pb1200/ | 219 | core-$(CONFIG_MIPS_PB1200) += arch/mips/alchemy/devboards/ |
| 216 | cflags-$(CONFIG_MIPS_PB1200) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00 | 220 | cflags-$(CONFIG_MIPS_PB1200) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00 |
| 217 | load-$(CONFIG_MIPS_PB1200) += 0xffffffff80100000 | 221 | load-$(CONFIG_MIPS_PB1200) += 0xffffffff80100000 |
| 218 | 222 | ||
| 219 | # | 223 | # |
| 220 | # AMD Alchemy Db1000 eval board | 224 | # AMD Alchemy Db1000 eval board |
| 221 | # | 225 | # |
| 222 | libs-$(CONFIG_MIPS_DB1000) += arch/mips/alchemy/db1x00/ | 226 | core-$(CONFIG_MIPS_DB1000) += arch/mips/alchemy/devboards/ |
| 223 | cflags-$(CONFIG_MIPS_DB1000) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 | 227 | cflags-$(CONFIG_MIPS_DB1000) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 |
| 224 | load-$(CONFIG_MIPS_DB1000) += 0xffffffff80100000 | 228 | load-$(CONFIG_MIPS_DB1000) += 0xffffffff80100000 |
| 225 | 229 | ||
| 226 | # | 230 | # |
| 227 | # AMD Alchemy Db1100 eval board | 231 | # AMD Alchemy Db1100 eval board |
| 228 | # | 232 | # |
| 229 | libs-$(CONFIG_MIPS_DB1100) += arch/mips/alchemy/db1x00/ | 233 | core-$(CONFIG_MIPS_DB1100) += arch/mips/alchemy/devboards/ |
| 230 | cflags-$(CONFIG_MIPS_DB1100) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 | 234 | cflags-$(CONFIG_MIPS_DB1100) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 |
| 231 | load-$(CONFIG_MIPS_DB1100) += 0xffffffff80100000 | 235 | load-$(CONFIG_MIPS_DB1100) += 0xffffffff80100000 |
| 232 | 236 | ||
| 233 | # | 237 | # |
| 234 | # AMD Alchemy Db1500 eval board | 238 | # AMD Alchemy Db1500 eval board |
| 235 | # | 239 | # |
| 236 | libs-$(CONFIG_MIPS_DB1500) += arch/mips/alchemy/db1x00/ | 240 | core-$(CONFIG_MIPS_DB1500) += arch/mips/alchemy/devboards/ |
| 237 | cflags-$(CONFIG_MIPS_DB1500) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 | 241 | cflags-$(CONFIG_MIPS_DB1500) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 |
| 238 | load-$(CONFIG_MIPS_DB1500) += 0xffffffff80100000 | 242 | load-$(CONFIG_MIPS_DB1500) += 0xffffffff80100000 |
| 239 | 243 | ||
| 240 | # | 244 | # |
| 241 | # AMD Alchemy Db1550 eval board | 245 | # AMD Alchemy Db1550 eval board |
| 242 | # | 246 | # |
| 243 | libs-$(CONFIG_MIPS_DB1550) += arch/mips/alchemy/db1x00/ | 247 | core-$(CONFIG_MIPS_DB1550) += arch/mips/alchemy/devboards/ |
| 244 | cflags-$(CONFIG_MIPS_DB1550) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 | 248 | cflags-$(CONFIG_MIPS_DB1550) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 |
| 245 | load-$(CONFIG_MIPS_DB1550) += 0xffffffff80100000 | 249 | load-$(CONFIG_MIPS_DB1550) += 0xffffffff80100000 |
| 246 | 250 | ||
| 247 | # | 251 | # |
| 248 | # AMD Alchemy Db1200 eval board | 252 | # AMD Alchemy Db1200 eval board |
| 249 | # | 253 | # |
| 250 | libs-$(CONFIG_MIPS_DB1200) += arch/mips/alchemy/pb1200/ | 254 | core-$(CONFIG_MIPS_DB1200) += arch/mips/alchemy/devboards/ |
| 251 | cflags-$(CONFIG_MIPS_DB1200) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 | 255 | cflags-$(CONFIG_MIPS_DB1200) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 |
| 252 | load-$(CONFIG_MIPS_DB1200) += 0xffffffff80100000 | 256 | load-$(CONFIG_MIPS_DB1200) += 0xffffffff80100000 |
| 253 | 257 | ||
| 254 | # | 258 | # |
| 255 | # AMD Alchemy Bosporus eval board | 259 | # AMD Alchemy Bosporus eval board |
| 256 | # | 260 | # |
| 257 | libs-$(CONFIG_MIPS_BOSPORUS) += arch/mips/alchemy/db1x00/ | 261 | core-$(CONFIG_MIPS_BOSPORUS) += arch/mips/alchemy/devboards/ |
| 258 | cflags-$(CONFIG_MIPS_BOSPORUS) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 | 262 | cflags-$(CONFIG_MIPS_BOSPORUS) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 |
| 259 | load-$(CONFIG_MIPS_BOSPORUS) += 0xffffffff80100000 | 263 | load-$(CONFIG_MIPS_BOSPORUS) += 0xffffffff80100000 |
| 260 | 264 | ||
| 261 | # | 265 | # |
| 262 | # AMD Alchemy Mirage eval board | 266 | # AMD Alchemy Mirage eval board |
| 263 | # | 267 | # |
| 264 | libs-$(CONFIG_MIPS_MIRAGE) += arch/mips/alchemy/db1x00/ | 268 | core-$(CONFIG_MIPS_MIRAGE) += arch/mips/alchemy/devboards/ |
| 265 | cflags-$(CONFIG_MIPS_MIRAGE) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 | 269 | cflags-$(CONFIG_MIPS_MIRAGE) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 |
| 266 | load-$(CONFIG_MIPS_MIRAGE) += 0xffffffff80100000 | 270 | load-$(CONFIG_MIPS_MIRAGE) += 0xffffffff80100000 |
| 267 | 271 | ||
| @@ -586,6 +590,18 @@ core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/txx9/rbtx4927/ | |||
| 586 | core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/txx9/rbtx4938/ | 590 | core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/txx9/rbtx4938/ |
| 587 | core-$(CONFIG_TOSHIBA_RBTX4939) += arch/mips/txx9/rbtx4939/ | 591 | core-$(CONFIG_TOSHIBA_RBTX4939) += arch/mips/txx9/rbtx4939/ |
| 588 | 592 | ||
| 593 | # | ||
| 594 | # Cavium Octeon | ||
| 595 | # | ||
| 596 | core-$(CONFIG_CPU_CAVIUM_OCTEON) += arch/mips/cavium-octeon/ | ||
| 597 | cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -I$(srctree)/arch/mips/include/asm/mach-cavium-octeon | ||
| 598 | core-$(CONFIG_CPU_CAVIUM_OCTEON) += arch/mips/cavium-octeon/executive/ | ||
| 599 | ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL | ||
| 600 | load-$(CONFIG_CPU_CAVIUM_OCTEON) += 0xffffffff84100000 | ||
| 601 | else | ||
| 602 | load-$(CONFIG_CPU_CAVIUM_OCTEON) += 0xffffffff81100000 | ||
| 603 | endif | ||
| 604 | |||
| 589 | cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic | 605 | cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic |
| 590 | drivers-$(CONFIG_PCI) += arch/mips/pci/ | 606 | drivers-$(CONFIG_PCI) += arch/mips/pci/ |
| 591 | 607 | ||
diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig index e4a057d80ab6..7f8ef13d0014 100644 --- a/arch/mips/alchemy/Kconfig +++ b/arch/mips/alchemy/Kconfig | |||
| @@ -128,9 +128,10 @@ config SOC_AU1200 | |||
| 128 | config SOC_AU1X00 | 128 | config SOC_AU1X00 |
| 129 | bool | 129 | bool |
| 130 | select 64BIT_PHYS_ADDR | 130 | select 64BIT_PHYS_ADDR |
| 131 | select CEVT_R4K | 131 | select CEVT_R4K_LIB |
| 132 | select CSRC_R4K | 132 | select CSRC_R4K_LIB |
| 133 | select IRQ_CPU | 133 | select IRQ_CPU |
| 134 | select SYS_HAS_CPU_MIPS32_R1 | 134 | select SYS_HAS_CPU_MIPS32_R1 |
| 135 | select SYS_SUPPORTS_32BIT_KERNEL | 135 | select SYS_SUPPORTS_32BIT_KERNEL |
| 136 | select SYS_SUPPORTS_APM_EMULATION | 136 | select SYS_SUPPORTS_APM_EMULATION |
| 137 | select GENERIC_HARDIRQS_NO__DO_IRQ | ||
diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile index df48fd65bbf3..d50d4764eafe 100644 --- a/arch/mips/alchemy/common/Makefile +++ b/arch/mips/alchemy/common/Makefile | |||
| @@ -6,8 +6,8 @@ | |||
| 6 | # | 6 | # |
| 7 | 7 | ||
| 8 | obj-y += prom.o irq.o puts.o time.o reset.o \ | 8 | obj-y += prom.o irq.o puts.o time.o reset.o \ |
| 9 | au1xxx_irqmap.o clocks.o platform.o power.o setup.o \ | 9 | clocks.o platform.o power.o setup.o \ |
| 10 | sleeper.o cputable.o dma.o dbdma.o gpio.o | 10 | sleeper.o dma.o dbdma.o gpio.o |
| 11 | 11 | ||
| 12 | obj-$(CONFIG_PCI) += pci.o | 12 | obj-$(CONFIG_PCI) += pci.o |
| 13 | 13 | ||
diff --git a/arch/mips/alchemy/common/au1xxx_irqmap.c b/arch/mips/alchemy/common/au1xxx_irqmap.c deleted file mode 100644 index c7ca1596394c..000000000000 --- a/arch/mips/alchemy/common/au1xxx_irqmap.c +++ /dev/null | |||
| @@ -1,205 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * BRIEF MODULE DESCRIPTION | ||
| 3 | * Au1xxx processor specific IRQ tables | ||
| 4 | * | ||
| 5 | * Copyright 2004 Embedded Edge, LLC | ||
| 6 | * dan@embeddededge.com | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify it | ||
| 9 | * under the terms of the GNU General Public License as published by the | ||
| 10 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 11 | * option) any later version. | ||
| 12 | * | ||
| 13 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 14 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 15 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 16 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 17 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 18 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 19 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 20 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 21 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 22 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License along | ||
| 25 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 26 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 27 | */ | ||
| 28 | #include <linux/init.h> | ||
| 29 | #include <linux/kernel.h> | ||
| 30 | |||
| 31 | #include <au1000.h> | ||
| 32 | |||
| 33 | /* The IC0 interrupt table. This is processor, rather than | ||
| 34 | * board dependent, so no reason to keep this info in the board | ||
| 35 | * dependent files. | ||
| 36 | * | ||
| 37 | * Careful if you change match 2 request! | ||
| 38 | * The interrupt handler is called directly from the low level dispatch code. | ||
| 39 | */ | ||
| 40 | struct au1xxx_irqmap __initdata au1xxx_ic0_map[] = { | ||
| 41 | |||
| 42 | #if defined(CONFIG_SOC_AU1000) | ||
| 43 | { AU1000_UART0_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 44 | { AU1000_UART1_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 45 | { AU1000_UART2_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 46 | { AU1000_UART3_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 47 | { AU1000_SSI0_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 48 | { AU1000_SSI1_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 49 | { AU1000_DMA_INT_BASE, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 50 | { AU1000_DMA_INT_BASE+1, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 51 | { AU1000_DMA_INT_BASE+2, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 52 | { AU1000_DMA_INT_BASE+3, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 53 | { AU1000_DMA_INT_BASE+4, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 54 | { AU1000_DMA_INT_BASE+5, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 55 | { AU1000_DMA_INT_BASE+6, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 56 | { AU1000_DMA_INT_BASE+7, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 57 | { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 }, | ||
| 58 | { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, | ||
| 59 | { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, | ||
| 60 | { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 }, | ||
| 61 | { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 }, | ||
| 62 | { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, | ||
| 63 | { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, | ||
| 64 | { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 }, | ||
| 65 | { AU1000_IRDA_TX_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 66 | { AU1000_IRDA_RX_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 67 | { AU1000_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 68 | { AU1000_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 }, | ||
| 69 | { AU1000_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 }, | ||
| 70 | { AU1000_ACSYNC_INT, INTC_INT_RISE_EDGE, 0 }, | ||
| 71 | { AU1000_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 72 | { AU1000_MAC1_DMA_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 73 | { AU1000_AC97C_INT, INTC_INT_RISE_EDGE, 0 }, | ||
| 74 | |||
| 75 | #elif defined(CONFIG_SOC_AU1500) | ||
| 76 | |||
| 77 | { AU1500_UART0_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 78 | { AU1000_PCI_INTA, INTC_INT_LOW_LEVEL, 0 }, | ||
| 79 | { AU1000_PCI_INTB, INTC_INT_LOW_LEVEL, 0 }, | ||
| 80 | { AU1500_UART3_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 81 | { AU1000_PCI_INTC, INTC_INT_LOW_LEVEL, 0 }, | ||
| 82 | { AU1000_PCI_INTD, INTC_INT_LOW_LEVEL, 0 }, | ||
| 83 | { AU1000_DMA_INT_BASE, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 84 | { AU1000_DMA_INT_BASE+1, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 85 | { AU1000_DMA_INT_BASE+2, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 86 | { AU1000_DMA_INT_BASE+3, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 87 | { AU1000_DMA_INT_BASE+4, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 88 | { AU1000_DMA_INT_BASE+5, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 89 | { AU1000_DMA_INT_BASE+6, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 90 | { AU1000_DMA_INT_BASE+7, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 91 | { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 }, | ||
| 92 | { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, | ||
| 93 | { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, | ||
| 94 | { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 }, | ||
| 95 | { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 }, | ||
| 96 | { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, | ||
| 97 | { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, | ||
| 98 | { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 }, | ||
| 99 | { AU1000_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 100 | { AU1000_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 }, | ||
| 101 | { AU1000_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 }, | ||
| 102 | { AU1000_ACSYNC_INT, INTC_INT_RISE_EDGE, 0 }, | ||
| 103 | { AU1500_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 104 | { AU1500_MAC1_DMA_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 105 | { AU1000_AC97C_INT, INTC_INT_RISE_EDGE, 0 }, | ||
| 106 | |||
| 107 | #elif defined(CONFIG_SOC_AU1100) | ||
| 108 | |||
| 109 | { AU1100_UART0_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 110 | { AU1100_UART1_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 111 | { AU1100_SD_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 112 | { AU1100_UART3_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 113 | { AU1000_SSI0_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 114 | { AU1000_SSI1_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 115 | { AU1000_DMA_INT_BASE, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 116 | { AU1000_DMA_INT_BASE+1, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 117 | { AU1000_DMA_INT_BASE+2, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 118 | { AU1000_DMA_INT_BASE+3, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 119 | { AU1000_DMA_INT_BASE+4, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 120 | { AU1000_DMA_INT_BASE+5, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 121 | { AU1000_DMA_INT_BASE+6, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 122 | { AU1000_DMA_INT_BASE+7, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 123 | { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 }, | ||
| 124 | { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, | ||
| 125 | { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, | ||
| 126 | { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 }, | ||
| 127 | { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 }, | ||
| 128 | { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, | ||
| 129 | { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, | ||
| 130 | { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 }, | ||
| 131 | { AU1000_IRDA_TX_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 132 | { AU1000_IRDA_RX_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 133 | { AU1000_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 134 | { AU1000_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 }, | ||
| 135 | { AU1000_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 }, | ||
| 136 | { AU1000_ACSYNC_INT, INTC_INT_RISE_EDGE, 0 }, | ||
| 137 | { AU1100_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 138 | /* { AU1000_GPIO215_208_INT, INTC_INT_HIGH_LEVEL, 0 }, */ | ||
| 139 | { AU1100_LCD_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 140 | { AU1000_AC97C_INT, INTC_INT_RISE_EDGE, 0 }, | ||
| 141 | |||
| 142 | #elif defined(CONFIG_SOC_AU1550) | ||
| 143 | |||
| 144 | { AU1550_UART0_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 145 | { AU1550_PCI_INTA, INTC_INT_LOW_LEVEL, 0 }, | ||
| 146 | { AU1550_PCI_INTB, INTC_INT_LOW_LEVEL, 0 }, | ||
| 147 | { AU1550_DDMA_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 148 | { AU1550_CRYPTO_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 149 | { AU1550_PCI_INTC, INTC_INT_LOW_LEVEL, 0 }, | ||
| 150 | { AU1550_PCI_INTD, INTC_INT_LOW_LEVEL, 0 }, | ||
| 151 | { AU1550_PCI_RST_INT, INTC_INT_LOW_LEVEL, 0 }, | ||
| 152 | { AU1550_UART1_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 153 | { AU1550_UART3_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 154 | { AU1550_PSC0_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 155 | { AU1550_PSC1_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 156 | { AU1550_PSC2_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 157 | { AU1550_PSC3_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 158 | { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 }, | ||
| 159 | { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, | ||
| 160 | { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, | ||
| 161 | { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 }, | ||
| 162 | { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 }, | ||
| 163 | { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, | ||
| 164 | { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, | ||
| 165 | { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 }, | ||
| 166 | { AU1550_NAND_INT, INTC_INT_RISE_EDGE, 0 }, | ||
| 167 | { AU1550_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 168 | { AU1550_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 }, | ||
| 169 | { AU1550_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 }, | ||
| 170 | { AU1550_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 171 | { AU1550_MAC1_DMA_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 172 | |||
| 173 | #elif defined(CONFIG_SOC_AU1200) | ||
| 174 | |||
| 175 | { AU1200_UART0_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 176 | { AU1200_SWT_INT, INTC_INT_RISE_EDGE, 0 }, | ||
| 177 | { AU1200_SD_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 178 | { AU1200_DDMA_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 179 | { AU1200_MAE_BE_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 180 | { AU1200_UART1_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 181 | { AU1200_MAE_FE_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 182 | { AU1200_PSC0_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 183 | { AU1200_PSC1_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 184 | { AU1200_AES_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 185 | { AU1200_CAMERA_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 186 | { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 }, | ||
| 187 | { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, | ||
| 188 | { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, | ||
| 189 | { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 }, | ||
| 190 | { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 }, | ||
| 191 | { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, | ||
| 192 | { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, | ||
| 193 | { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 }, | ||
| 194 | { AU1200_NAND_INT, INTC_INT_RISE_EDGE, 0 }, | ||
| 195 | { AU1200_USB_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 196 | { AU1200_LCD_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 197 | { AU1200_MAE_BOTH_INT, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 198 | |||
| 199 | #else | ||
| 200 | #error "Error: Unknown Alchemy SOC" | ||
| 201 | #endif | ||
| 202 | |||
| 203 | }; | ||
| 204 | |||
| 205 | int __initdata au1xxx_ic0_nr_irqs = ARRAY_SIZE(au1xxx_ic0_map); | ||
diff --git a/arch/mips/alchemy/common/clocks.c b/arch/mips/alchemy/common/clocks.c index 043429d17c5f..d8991854530e 100644 --- a/arch/mips/alchemy/common/clocks.c +++ b/arch/mips/alchemy/common/clocks.c | |||
| @@ -27,12 +27,21 @@ | |||
| 27 | */ | 27 | */ |
| 28 | 28 | ||
| 29 | #include <linux/module.h> | 29 | #include <linux/module.h> |
| 30 | #include <linux/spinlock.h> | ||
| 31 | #include <asm/time.h> | ||
| 30 | #include <asm/mach-au1x00/au1000.h> | 32 | #include <asm/mach-au1x00/au1000.h> |
| 31 | 33 | ||
| 34 | /* | ||
| 35 | * I haven't found anyone that doesn't use a 12 MHz source clock, | ||
| 36 | * but just in case..... | ||
| 37 | */ | ||
| 38 | #define AU1000_SRC_CLK 12000000 | ||
| 39 | |||
| 32 | static unsigned int au1x00_clock; /* Hz */ | 40 | static unsigned int au1x00_clock; /* Hz */ |
| 33 | static unsigned int lcd_clock; /* KHz */ | ||
| 34 | static unsigned long uart_baud_base; | 41 | static unsigned long uart_baud_base; |
| 35 | 42 | ||
| 43 | static DEFINE_SPINLOCK(time_lock); | ||
| 44 | |||
| 36 | /* | 45 | /* |
| 37 | * Set the au1000_clock | 46 | * Set the au1000_clock |
| 38 | */ | 47 | */ |
| @@ -63,31 +72,45 @@ void set_au1x00_uart_baud_base(unsigned long new_baud_base) | |||
| 63 | } | 72 | } |
| 64 | 73 | ||
| 65 | /* | 74 | /* |
| 66 | * Calculate the Au1x00's LCD clock based on the current | 75 | * We read the real processor speed from the PLL. This is important |
| 67 | * cpu clock and the system bus clock, and try to keep it | 76 | * because it is more accurate than computing it from the 32 KHz |
| 68 | * below 40 MHz (the Pb1000 board can lock-up if the LCD | 77 | * counter, if it exists. If we don't have an accurate processor |
| 69 | * clock is over 40 MHz). | 78 | * speed, all of the peripherals that derive their clocks based on |
| 79 | * this advertised speed will introduce error and sometimes not work | ||
| 80 | * properly. This function is futher convoluted to still allow configurations | ||
| 81 | * to do that in case they have really, really old silicon with a | ||
| 82 | * write-only PLL register. -- Dan | ||
| 70 | */ | 83 | */ |
| 71 | void set_au1x00_lcd_clock(void) | 84 | unsigned long au1xxx_calc_clock(void) |
| 72 | { | 85 | { |
| 73 | unsigned int static_cfg0; | 86 | unsigned long cpu_speed; |
| 74 | unsigned int sys_busclk = (get_au1x00_speed() / 1000) / | 87 | unsigned long flags; |
| 75 | ((int)(au_readl(SYS_POWERCTRL) & 0x03) + 2); | ||
| 76 | 88 | ||
| 77 | static_cfg0 = au_readl(MEM_STCFG0); | 89 | spin_lock_irqsave(&time_lock, flags); |
| 78 | 90 | ||
| 79 | if (static_cfg0 & (1 << 11)) | 91 | /* |
| 80 | lcd_clock = sys_busclk / 5; /* note: BCLK switching fails with D5 */ | 92 | * On early Au1000, sys_cpupll was write-only. Since these |
| 93 | * silicon versions of Au1000 are not sold by AMD, we don't bend | ||
| 94 | * over backwards trying to determine the frequency. | ||
| 95 | */ | ||
| 96 | if (au1xxx_cpu_has_pll_wo()) | ||
| 97 | #ifdef CONFIG_SOC_AU1000_FREQUENCY | ||
| 98 | cpu_speed = CONFIG_SOC_AU1000_FREQUENCY; | ||
| 99 | #else | ||
| 100 | cpu_speed = 396000000; | ||
| 101 | #endif | ||
| 81 | else | 102 | else |
| 82 | lcd_clock = sys_busclk / 4; | 103 | cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK; |
| 83 | 104 | ||
| 84 | if (lcd_clock > 50000) /* Epson MAX */ | 105 | /* On Alchemy CPU:counter ratio is 1:1 */ |
| 85 | printk(KERN_WARNING "warning: LCD clock too high (%u KHz)\n", | 106 | mips_hpt_frequency = cpu_speed; |
| 86 | lcd_clock); | 107 | /* Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16) */ |
| 87 | } | 108 | set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL) |
| 109 | & 0x03) + 2) * 16)); | ||
| 88 | 110 | ||
| 89 | unsigned int get_au1x00_lcd_clock(void) | 111 | spin_unlock_irqrestore(&time_lock, flags); |
| 90 | { | 112 | |
| 91 | return lcd_clock; | 113 | set_au1x00_speed(cpu_speed); |
| 114 | |||
| 115 | return cpu_speed; | ||
| 92 | } | 116 | } |
| 93 | EXPORT_SYMBOL(get_au1x00_lcd_clock); | ||
diff --git a/arch/mips/alchemy/common/cputable.c b/arch/mips/alchemy/common/cputable.c deleted file mode 100644 index ba6430bc2d03..000000000000 --- a/arch/mips/alchemy/common/cputable.c +++ /dev/null | |||
| @@ -1,52 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/mips/au1000/common/cputable.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2004 Dan Malek (dan@embeddededge.com) | ||
| 5 | * Copied from PowerPC and updated for Alchemy Au1xxx processors. | ||
| 6 | * | ||
| 7 | * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org) | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or | ||
| 10 | * modify it under the terms of the GNU General Public License | ||
| 11 | * as published by the Free Software Foundation; either version | ||
| 12 | * 2 of the License, or (at your option) any later version. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include <asm/mach-au1x00/au1000.h> | ||
| 16 | |||
| 17 | struct cpu_spec *cur_cpu_spec[NR_CPUS]; | ||
| 18 | |||
| 19 | /* With some thought, we can probably use the mask to reduce the | ||
| 20 | * size of the table. | ||
| 21 | */ | ||
| 22 | struct cpu_spec cpu_specs[] = { | ||
| 23 | { 0xffffffff, 0x00030100, "Au1000 DA", 1, 0, 1 }, | ||
| 24 | { 0xffffffff, 0x00030201, "Au1000 HA", 1, 0, 1 }, | ||
| 25 | { 0xffffffff, 0x00030202, "Au1000 HB", 1, 0, 1 }, | ||
| 26 | { 0xffffffff, 0x00030203, "Au1000 HC", 1, 1, 0 }, | ||
| 27 | { 0xffffffff, 0x00030204, "Au1000 HD", 1, 1, 0 }, | ||
| 28 | { 0xffffffff, 0x01030200, "Au1500 AB", 1, 1, 0 }, | ||
| 29 | { 0xffffffff, 0x01030201, "Au1500 AC", 0, 1, 0 }, | ||
| 30 | { 0xffffffff, 0x01030202, "Au1500 AD", 0, 1, 0 }, | ||
| 31 | { 0xffffffff, 0x02030200, "Au1100 AB", 1, 1, 0 }, | ||
| 32 | { 0xffffffff, 0x02030201, "Au1100 BA", 1, 1, 0 }, | ||
| 33 | { 0xffffffff, 0x02030202, "Au1100 BC", 1, 1, 0 }, | ||
| 34 | { 0xffffffff, 0x02030203, "Au1100 BD", 0, 1, 0 }, | ||
| 35 | { 0xffffffff, 0x02030204, "Au1100 BE", 0, 1, 0 }, | ||
| 36 | { 0xffffffff, 0x03030200, "Au1550 AA", 0, 1, 0 }, | ||
| 37 | { 0xffffffff, 0x04030200, "Au1200 AB", 0, 0, 0 }, | ||
| 38 | { 0xffffffff, 0x04030201, "Au1200 AC", 1, 0, 0 }, | ||
| 39 | { 0x00000000, 0x00000000, "Unknown Au1xxx", 1, 0, 0 } | ||
| 40 | }; | ||
| 41 | |||
| 42 | void set_cpuspec(void) | ||
| 43 | { | ||
| 44 | struct cpu_spec *sp; | ||
| 45 | u32 prid; | ||
| 46 | |||
| 47 | prid = read_c0_prid(); | ||
| 48 | sp = cpu_specs; | ||
| 49 | while ((prid & sp->prid_mask) != sp->prid_value) | ||
| 50 | sp++; | ||
| 51 | cur_cpu_spec[0] = sp; | ||
| 52 | } | ||
diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c index 601ee9180ee4..3ab6d80d150d 100644 --- a/arch/mips/alchemy/common/dbdma.c +++ b/arch/mips/alchemy/common/dbdma.c | |||
| @@ -174,6 +174,11 @@ static dbdev_tab_t dbdev_tab[] = { | |||
| 174 | 174 | ||
| 175 | #define DBDEV_TAB_SIZE ARRAY_SIZE(dbdev_tab) | 175 | #define DBDEV_TAB_SIZE ARRAY_SIZE(dbdev_tab) |
| 176 | 176 | ||
| 177 | #ifdef CONFIG_PM | ||
| 178 | static u32 au1xxx_dbdma_pm_regs[NUM_DBDMA_CHANS + 1][8]; | ||
| 179 | #endif | ||
| 180 | |||
| 181 | |||
| 177 | static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS]; | 182 | static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS]; |
| 178 | 183 | ||
| 179 | static dbdev_tab_t *find_dbdev_id(u32 id) | 184 | static dbdev_tab_t *find_dbdev_id(u32 id) |
| @@ -975,4 +980,64 @@ u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr) | |||
| 975 | return nbytes; | 980 | return nbytes; |
| 976 | } | 981 | } |
| 977 | 982 | ||
| 983 | #ifdef CONFIG_PM | ||
| 984 | void au1xxx_dbdma_suspend(void) | ||
| 985 | { | ||
| 986 | int i; | ||
| 987 | u32 addr; | ||
| 988 | |||
| 989 | addr = DDMA_GLOBAL_BASE; | ||
| 990 | au1xxx_dbdma_pm_regs[0][0] = au_readl(addr + 0x00); | ||
| 991 | au1xxx_dbdma_pm_regs[0][1] = au_readl(addr + 0x04); | ||
| 992 | au1xxx_dbdma_pm_regs[0][2] = au_readl(addr + 0x08); | ||
| 993 | au1xxx_dbdma_pm_regs[0][3] = au_readl(addr + 0x0c); | ||
| 994 | |||
| 995 | /* save channel configurations */ | ||
| 996 | for (i = 1, addr = DDMA_CHANNEL_BASE; i < NUM_DBDMA_CHANS; i++) { | ||
| 997 | au1xxx_dbdma_pm_regs[i][0] = au_readl(addr + 0x00); | ||
| 998 | au1xxx_dbdma_pm_regs[i][1] = au_readl(addr + 0x04); | ||
| 999 | au1xxx_dbdma_pm_regs[i][2] = au_readl(addr + 0x08); | ||
| 1000 | au1xxx_dbdma_pm_regs[i][3] = au_readl(addr + 0x0c); | ||
| 1001 | au1xxx_dbdma_pm_regs[i][4] = au_readl(addr + 0x10); | ||
| 1002 | au1xxx_dbdma_pm_regs[i][5] = au_readl(addr + 0x14); | ||
| 1003 | au1xxx_dbdma_pm_regs[i][6] = au_readl(addr + 0x18); | ||
| 1004 | |||
| 1005 | /* halt channel */ | ||
| 1006 | au_writel(au1xxx_dbdma_pm_regs[i][0] & ~1, addr + 0x00); | ||
| 1007 | au_sync(); | ||
| 1008 | while (!(au_readl(addr + 0x14) & 1)) | ||
| 1009 | au_sync(); | ||
| 1010 | |||
| 1011 | addr += 0x100; /* next channel base */ | ||
| 1012 | } | ||
| 1013 | /* disable channel interrupts */ | ||
| 1014 | au_writel(0, DDMA_GLOBAL_BASE + 0x0c); | ||
| 1015 | au_sync(); | ||
| 1016 | } | ||
| 1017 | |||
| 1018 | void au1xxx_dbdma_resume(void) | ||
| 1019 | { | ||
| 1020 | int i; | ||
| 1021 | u32 addr; | ||
| 1022 | |||
| 1023 | addr = DDMA_GLOBAL_BASE; | ||
| 1024 | au_writel(au1xxx_dbdma_pm_regs[0][0], addr + 0x00); | ||
| 1025 | au_writel(au1xxx_dbdma_pm_regs[0][1], addr + 0x04); | ||
| 1026 | au_writel(au1xxx_dbdma_pm_regs[0][2], addr + 0x08); | ||
| 1027 | au_writel(au1xxx_dbdma_pm_regs[0][3], addr + 0x0c); | ||
| 1028 | |||
| 1029 | /* restore channel configurations */ | ||
| 1030 | for (i = 1, addr = DDMA_CHANNEL_BASE; i < NUM_DBDMA_CHANS; i++) { | ||
| 1031 | au_writel(au1xxx_dbdma_pm_regs[i][0], addr + 0x00); | ||
| 1032 | au_writel(au1xxx_dbdma_pm_regs[i][1], addr + 0x04); | ||
| 1033 | au_writel(au1xxx_dbdma_pm_regs[i][2], addr + 0x08); | ||
| 1034 | au_writel(au1xxx_dbdma_pm_regs[i][3], addr + 0x0c); | ||
| 1035 | au_writel(au1xxx_dbdma_pm_regs[i][4], addr + 0x10); | ||
| 1036 | au_writel(au1xxx_dbdma_pm_regs[i][5], addr + 0x14); | ||
| 1037 | au_writel(au1xxx_dbdma_pm_regs[i][6], addr + 0x18); | ||
| 1038 | au_sync(); | ||
| 1039 | addr += 0x100; /* next channel base */ | ||
| 1040 | } | ||
| 1041 | } | ||
| 1042 | #endif /* CONFIG_PM */ | ||
| 978 | #endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */ | 1043 | #endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */ |
diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c index 40c6ceceb5f9..c88c821b4c36 100644 --- a/arch/mips/alchemy/common/irq.c +++ b/arch/mips/alchemy/common/irq.c | |||
| @@ -24,6 +24,7 @@ | |||
| 24 | * with this program; if not, write to the Free Software Foundation, Inc., | 24 | * with this program; if not, write to the Free Software Foundation, Inc., |
| 25 | * 675 Mass Ave, Cambridge, MA 02139, USA. | 25 | * 675 Mass Ave, Cambridge, MA 02139, USA. |
| 26 | */ | 26 | */ |
| 27 | |||
| 27 | #include <linux/bitops.h> | 28 | #include <linux/bitops.h> |
| 28 | #include <linux/init.h> | 29 | #include <linux/init.h> |
| 29 | #include <linux/interrupt.h> | 30 | #include <linux/interrupt.h> |
| @@ -36,15 +37,172 @@ | |||
| 36 | #include <asm/mach-pb1x00/pb1000.h> | 37 | #include <asm/mach-pb1x00/pb1000.h> |
| 37 | #endif | 38 | #endif |
| 38 | 39 | ||
| 39 | #define EXT_INTC0_REQ0 2 /* IP 2 */ | 40 | static int au1x_ic_settype(unsigned int irq, unsigned int flow_type); |
| 40 | #define EXT_INTC0_REQ1 3 /* IP 3 */ | 41 | |
| 41 | #define EXT_INTC1_REQ0 4 /* IP 4 */ | 42 | /* per-processor fixed function irqs */ |
| 42 | #define EXT_INTC1_REQ1 5 /* IP 5 */ | 43 | struct au1xxx_irqmap au1xxx_ic0_map[] __initdata = { |
| 43 | #define MIPS_TIMER_IP 7 /* IP 7 */ | 44 | |
| 44 | 45 | #if defined(CONFIG_SOC_AU1000) | |
| 45 | void (*board_init_irq)(void) __initdata = NULL; | 46 | { AU1000_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, |
| 47 | { AU1000_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 48 | { AU1000_UART2_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 49 | { AU1000_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 50 | { AU1000_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 51 | { AU1000_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 52 | { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 53 | { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 54 | { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 55 | { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 56 | { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 57 | { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 58 | { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 59 | { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 60 | { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, | ||
| 61 | { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, | ||
| 62 | { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, | ||
| 63 | { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, | ||
| 64 | { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, | ||
| 65 | { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, | ||
| 66 | { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, | ||
| 67 | { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, | ||
| 68 | { AU1000_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 69 | { AU1000_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 70 | { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 71 | { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 }, | ||
| 72 | { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, | ||
| 73 | { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 }, | ||
| 74 | { AU1000_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 75 | { AU1000_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 76 | { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 }, | ||
| 77 | |||
| 78 | #elif defined(CONFIG_SOC_AU1500) | ||
| 79 | |||
| 80 | { AU1500_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 81 | { AU1000_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 0 }, | ||
| 82 | { AU1000_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 0 }, | ||
| 83 | { AU1500_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 84 | { AU1000_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 0 }, | ||
| 85 | { AU1000_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 0 }, | ||
| 86 | { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 87 | { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 88 | { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 89 | { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 90 | { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 91 | { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 92 | { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 93 | { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 94 | { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, | ||
| 95 | { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, | ||
| 96 | { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, | ||
| 97 | { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, | ||
| 98 | { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, | ||
| 99 | { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, | ||
| 100 | { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, | ||
| 101 | { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, | ||
| 102 | { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 103 | { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 }, | ||
| 104 | { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, | ||
| 105 | { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 }, | ||
| 106 | { AU1500_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 107 | { AU1500_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 108 | { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 }, | ||
| 109 | |||
| 110 | #elif defined(CONFIG_SOC_AU1100) | ||
| 111 | |||
| 112 | { AU1100_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 113 | { AU1100_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 114 | { AU1100_SD_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 115 | { AU1100_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 116 | { AU1000_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 117 | { AU1000_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 118 | { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 119 | { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 120 | { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 121 | { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 122 | { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 123 | { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 124 | { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 125 | { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 126 | { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, | ||
| 127 | { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, | ||
| 128 | { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, | ||
| 129 | { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, | ||
| 130 | { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, | ||
| 131 | { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, | ||
| 132 | { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, | ||
| 133 | { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, | ||
| 134 | { AU1000_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 135 | { AU1000_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 136 | { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 137 | { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 }, | ||
| 138 | { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, | ||
| 139 | { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 }, | ||
| 140 | { AU1100_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 141 | { AU1100_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 142 | { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 }, | ||
| 143 | |||
| 144 | #elif defined(CONFIG_SOC_AU1550) | ||
| 145 | |||
| 146 | { AU1550_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 147 | { AU1550_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 0 }, | ||
| 148 | { AU1550_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 0 }, | ||
| 149 | { AU1550_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 150 | { AU1550_CRYPTO_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 151 | { AU1550_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 0 }, | ||
| 152 | { AU1550_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 0 }, | ||
| 153 | { AU1550_PCI_RST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, | ||
| 154 | { AU1550_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 155 | { AU1550_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 156 | { AU1550_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 157 | { AU1550_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 158 | { AU1550_PSC2_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 159 | { AU1550_PSC3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 160 | { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, | ||
| 161 | { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, | ||
| 162 | { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, | ||
| 163 | { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, | ||
| 164 | { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, | ||
| 165 | { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, | ||
| 166 | { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, | ||
| 167 | { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, | ||
| 168 | { AU1550_NAND_INT, IRQ_TYPE_EDGE_RISING, 0 }, | ||
| 169 | { AU1550_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 170 | { AU1550_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 }, | ||
| 171 | { AU1550_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, | ||
| 172 | { AU1550_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 173 | { AU1550_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 174 | |||
| 175 | #elif defined(CONFIG_SOC_AU1200) | ||
| 176 | |||
| 177 | { AU1200_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 178 | { AU1200_SWT_INT, IRQ_TYPE_EDGE_RISING, 0 }, | ||
| 179 | { AU1200_SD_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 180 | { AU1200_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 181 | { AU1200_MAE_BE_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 182 | { AU1200_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 183 | { AU1200_MAE_FE_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 184 | { AU1200_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 185 | { AU1200_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 186 | { AU1200_AES_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 187 | { AU1200_CAMERA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 188 | { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, | ||
| 189 | { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, | ||
| 190 | { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, | ||
| 191 | { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, | ||
| 192 | { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, | ||
| 193 | { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, | ||
| 194 | { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, | ||
| 195 | { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, | ||
| 196 | { AU1200_NAND_INT, IRQ_TYPE_EDGE_RISING, 0 }, | ||
| 197 | { AU1200_USB_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 198 | { AU1200_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 199 | { AU1200_MAE_BOTH_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, | ||
| 200 | |||
| 201 | #else | ||
| 202 | #error "Error: Unknown Alchemy SOC" | ||
| 203 | #endif | ||
| 204 | }; | ||
| 46 | 205 | ||
| 47 | static DEFINE_SPINLOCK(irq_lock); | ||
| 48 | 206 | ||
| 49 | #ifdef CONFIG_PM | 207 | #ifdef CONFIG_PM |
| 50 | 208 | ||
| @@ -130,67 +288,47 @@ void restore_au1xxx_intctl(void) | |||
| 130 | #endif /* CONFIG_PM */ | 288 | #endif /* CONFIG_PM */ |
| 131 | 289 | ||
| 132 | 290 | ||
| 133 | inline void local_enable_irq(unsigned int irq_nr) | 291 | static void au1x_ic0_unmask(unsigned int irq_nr) |
| 134 | { | 292 | { |
| 135 | unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; | 293 | unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; |
| 136 | 294 | au_writel(1 << bit, IC0_MASKSET); | |
| 137 | if (bit >= 32) { | 295 | au_writel(1 << bit, IC0_WAKESET); |
| 138 | au_writel(1 << (bit - 32), IC1_MASKSET); | ||
| 139 | au_writel(1 << (bit - 32), IC1_WAKESET); | ||
| 140 | } else { | ||
| 141 | au_writel(1 << bit, IC0_MASKSET); | ||
| 142 | au_writel(1 << bit, IC0_WAKESET); | ||
| 143 | } | ||
| 144 | au_sync(); | 296 | au_sync(); |
| 145 | } | 297 | } |
| 146 | 298 | ||
| 147 | 299 | static void au1x_ic1_unmask(unsigned int irq_nr) | |
| 148 | inline void local_disable_irq(unsigned int irq_nr) | ||
| 149 | { | 300 | { |
| 150 | unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; | 301 | unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE; |
| 302 | au_writel(1 << bit, IC1_MASKSET); | ||
| 303 | au_writel(1 << bit, IC1_WAKESET); | ||
| 151 | 304 | ||
| 152 | if (bit >= 32) { | 305 | /* very hacky. does the pb1000 cpld auto-disable this int? |
| 153 | au_writel(1 << (bit - 32), IC1_MASKCLR); | 306 | * nowhere in the current kernel sources is it disabled. --mlau |
| 154 | au_writel(1 << (bit - 32), IC1_WAKECLR); | 307 | */ |
| 155 | } else { | 308 | #if defined(CONFIG_MIPS_PB1000) |
| 156 | au_writel(1 << bit, IC0_MASKCLR); | 309 | if (irq_nr == AU1000_GPIO_15) |
| 157 | au_writel(1 << bit, IC0_WAKECLR); | 310 | au_writel(0x4000, PB1000_MDR); /* enable int */ |
| 158 | } | 311 | #endif |
| 159 | au_sync(); | 312 | au_sync(); |
| 160 | } | 313 | } |
| 161 | 314 | ||
| 162 | 315 | static void au1x_ic0_mask(unsigned int irq_nr) | |
| 163 | static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr) | ||
| 164 | { | 316 | { |
| 165 | unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; | 317 | unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; |
| 166 | 318 | au_writel(1 << bit, IC0_MASKCLR); | |
| 167 | if (bit >= 32) { | 319 | au_writel(1 << bit, IC0_WAKECLR); |
| 168 | au_writel(1 << (bit - 32), IC1_RISINGCLR); | ||
| 169 | au_writel(1 << (bit - 32), IC1_MASKCLR); | ||
| 170 | } else { | ||
| 171 | au_writel(1 << bit, IC0_RISINGCLR); | ||
| 172 | au_writel(1 << bit, IC0_MASKCLR); | ||
| 173 | } | ||
| 174 | au_sync(); | 320 | au_sync(); |
| 175 | } | 321 | } |
| 176 | 322 | ||
| 177 | 323 | static void au1x_ic1_mask(unsigned int irq_nr) | |
| 178 | static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr) | ||
| 179 | { | 324 | { |
| 180 | unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; | 325 | unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE; |
| 181 | 326 | au_writel(1 << bit, IC1_MASKCLR); | |
| 182 | if (bit >= 32) { | 327 | au_writel(1 << bit, IC1_WAKECLR); |
| 183 | au_writel(1 << (bit - 32), IC1_FALLINGCLR); | ||
| 184 | au_writel(1 << (bit - 32), IC1_MASKCLR); | ||
| 185 | } else { | ||
| 186 | au_writel(1 << bit, IC0_FALLINGCLR); | ||
| 187 | au_writel(1 << bit, IC0_MASKCLR); | ||
| 188 | } | ||
| 189 | au_sync(); | 328 | au_sync(); |
| 190 | } | 329 | } |
| 191 | 330 | ||
| 192 | 331 | static void au1x_ic0_ack(unsigned int irq_nr) | |
| 193 | static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr) | ||
| 194 | { | 332 | { |
| 195 | unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; | 333 | unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; |
| 196 | 334 | ||
| @@ -198,349 +336,229 @@ static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr) | |||
| 198 | * This may assume that we don't get interrupts from | 336 | * This may assume that we don't get interrupts from |
| 199 | * both edges at once, or if we do, that we don't care. | 337 | * both edges at once, or if we do, that we don't care. |
| 200 | */ | 338 | */ |
| 201 | if (bit >= 32) { | 339 | au_writel(1 << bit, IC0_FALLINGCLR); |
| 202 | au_writel(1 << (bit - 32), IC1_FALLINGCLR); | 340 | au_writel(1 << bit, IC0_RISINGCLR); |
| 203 | au_writel(1 << (bit - 32), IC1_RISINGCLR); | ||
| 204 | au_writel(1 << (bit - 32), IC1_MASKCLR); | ||
| 205 | } else { | ||
| 206 | au_writel(1 << bit, IC0_FALLINGCLR); | ||
| 207 | au_writel(1 << bit, IC0_RISINGCLR); | ||
| 208 | au_writel(1 << bit, IC0_MASKCLR); | ||
| 209 | } | ||
| 210 | au_sync(); | 341 | au_sync(); |
| 211 | } | 342 | } |
| 212 | 343 | ||
| 213 | static inline void mask_and_ack_level_irq(unsigned int irq_nr) | 344 | static void au1x_ic1_ack(unsigned int irq_nr) |
| 214 | { | 345 | { |
| 215 | local_disable_irq(irq_nr); | 346 | unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE; |
| 216 | au_sync(); | ||
| 217 | #if defined(CONFIG_MIPS_PB1000) | ||
| 218 | if (irq_nr == AU1000_GPIO_15) { | ||
| 219 | au_writel(0x8000, PB1000_MDR); /* ack int */ | ||
| 220 | au_sync(); | ||
| 221 | } | ||
| 222 | #endif | ||
| 223 | } | ||
| 224 | |||
| 225 | static void end_irq(unsigned int irq_nr) | ||
| 226 | { | ||
| 227 | if (!(irq_desc[irq_nr].status & (IRQ_DISABLED | IRQ_INPROGRESS))) | ||
| 228 | local_enable_irq(irq_nr); | ||
| 229 | 347 | ||
| 230 | #if defined(CONFIG_MIPS_PB1000) | 348 | /* |
| 231 | if (irq_nr == AU1000_GPIO_15) { | 349 | * This may assume that we don't get interrupts from |
| 232 | au_writel(0x4000, PB1000_MDR); /* enable int */ | 350 | * both edges at once, or if we do, that we don't care. |
| 233 | au_sync(); | 351 | */ |
| 234 | } | 352 | au_writel(1 << bit, IC1_FALLINGCLR); |
| 235 | #endif | 353 | au_writel(1 << bit, IC1_RISINGCLR); |
| 354 | au_sync(); | ||
| 236 | } | 355 | } |
| 237 | 356 | ||
| 238 | unsigned long save_local_and_disable(int controller) | 357 | static int au1x_ic1_setwake(unsigned int irq, unsigned int on) |
| 239 | { | 358 | { |
| 240 | int i; | 359 | unsigned int bit = irq - AU1000_INTC1_INT_BASE; |
| 241 | unsigned long flags, mask; | 360 | unsigned long wakemsk, flags; |
| 242 | |||
| 243 | spin_lock_irqsave(&irq_lock, flags); | ||
| 244 | if (controller) { | ||
| 245 | mask = au_readl(IC1_MASKSET); | ||
| 246 | for (i = 32; i < 64; i++) | ||
| 247 | local_disable_irq(i); | ||
| 248 | } else { | ||
| 249 | mask = au_readl(IC0_MASKSET); | ||
| 250 | for (i = 0; i < 32; i++) | ||
| 251 | local_disable_irq(i); | ||
| 252 | } | ||
| 253 | spin_unlock_irqrestore(&irq_lock, flags); | ||
| 254 | |||
| 255 | return mask; | ||
| 256 | } | ||
| 257 | 361 | ||
| 258 | void restore_local_and_enable(int controller, unsigned long mask) | 362 | /* only GPIO 0-7 can act as wakeup source: */ |
| 259 | { | 363 | if ((irq < AU1000_GPIO_0) || (irq > AU1000_GPIO_7)) |
| 260 | int i; | 364 | return -EINVAL; |
| 261 | unsigned long flags, new_mask; | ||
| 262 | |||
| 263 | spin_lock_irqsave(&irq_lock, flags); | ||
| 264 | for (i = 0; i < 32; i++) | ||
| 265 | if (mask & (1 << i)) { | ||
| 266 | if (controller) | ||
| 267 | local_enable_irq(i + 32); | ||
| 268 | else | ||
| 269 | local_enable_irq(i); | ||
| 270 | } | ||
| 271 | 365 | ||
| 272 | if (controller) | 366 | local_irq_save(flags); |
| 273 | new_mask = au_readl(IC1_MASKSET); | 367 | wakemsk = au_readl(SYS_WAKEMSK); |
| 368 | if (on) | ||
| 369 | wakemsk |= 1 << bit; | ||
| 274 | else | 370 | else |
| 275 | new_mask = au_readl(IC0_MASKSET); | 371 | wakemsk &= ~(1 << bit); |
| 372 | au_writel(wakemsk, SYS_WAKEMSK); | ||
| 373 | au_sync(); | ||
| 374 | local_irq_restore(flags); | ||
| 276 | 375 | ||
| 277 | spin_unlock_irqrestore(&irq_lock, flags); | 376 | return 0; |
| 278 | } | 377 | } |
| 279 | 378 | ||
| 280 | 379 | /* | |
| 281 | static struct irq_chip rise_edge_irq_type = { | 380 | * irq_chips for both ICs; this way the mask handlers can be |
| 282 | .name = "Au1000 Rise Edge", | 381 | * as short as possible. |
| 283 | .ack = mask_and_ack_rise_edge_irq, | 382 | * |
| 284 | .mask = local_disable_irq, | 383 | * NOTE: the ->ack() callback is used by the handle_edge_irq |
| 285 | .mask_ack = mask_and_ack_rise_edge_irq, | 384 | * flowhandler only, the ->mask_ack() one by handle_level_irq, |
| 286 | .unmask = local_enable_irq, | 385 | * so no need for an irq_chip for each type of irq (level/edge). |
| 287 | .end = end_irq, | 386 | */ |
| 288 | }; | 387 | static struct irq_chip au1x_ic0_chip = { |
| 289 | 388 | .name = "Alchemy-IC0", | |
| 290 | static struct irq_chip fall_edge_irq_type = { | 389 | .ack = au1x_ic0_ack, /* edge */ |
| 291 | .name = "Au1000 Fall Edge", | 390 | .mask = au1x_ic0_mask, |
| 292 | .ack = mask_and_ack_fall_edge_irq, | 391 | .mask_ack = au1x_ic0_mask, /* level */ |
| 293 | .mask = local_disable_irq, | 392 | .unmask = au1x_ic0_unmask, |
| 294 | .mask_ack = mask_and_ack_fall_edge_irq, | 393 | .set_type = au1x_ic_settype, |
| 295 | .unmask = local_enable_irq, | ||
| 296 | .end = end_irq, | ||
| 297 | }; | ||
| 298 | |||
| 299 | static struct irq_chip either_edge_irq_type = { | ||
| 300 | .name = "Au1000 Rise or Fall Edge", | ||
| 301 | .ack = mask_and_ack_either_edge_irq, | ||
| 302 | .mask = local_disable_irq, | ||
| 303 | .mask_ack = mask_and_ack_either_edge_irq, | ||
| 304 | .unmask = local_enable_irq, | ||
| 305 | .end = end_irq, | ||
| 306 | }; | 394 | }; |
| 307 | 395 | ||
| 308 | static struct irq_chip level_irq_type = { | 396 | static struct irq_chip au1x_ic1_chip = { |
| 309 | .name = "Au1000 Level", | 397 | .name = "Alchemy-IC1", |
| 310 | .ack = mask_and_ack_level_irq, | 398 | .ack = au1x_ic1_ack, /* edge */ |
| 311 | .mask = local_disable_irq, | 399 | .mask = au1x_ic1_mask, |
| 312 | .mask_ack = mask_and_ack_level_irq, | 400 | .mask_ack = au1x_ic1_mask, /* level */ |
| 313 | .unmask = local_enable_irq, | 401 | .unmask = au1x_ic1_unmask, |
| 314 | .end = end_irq, | 402 | .set_type = au1x_ic_settype, |
| 403 | .set_wake = au1x_ic1_setwake, | ||
| 315 | }; | 404 | }; |
| 316 | 405 | ||
| 317 | static void __init setup_local_irq(unsigned int irq_nr, int type, int int_req) | 406 | static int au1x_ic_settype(unsigned int irq, unsigned int flow_type) |
| 318 | { | 407 | { |
| 319 | unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; | 408 | struct irq_chip *chip; |
| 320 | 409 | unsigned long icr[6]; | |
| 321 | if (irq_nr > AU1000_MAX_INTR) | 410 | unsigned int bit, ic; |
| 322 | return; | 411 | int ret; |
| 323 | 412 | ||
| 324 | /* Config2[n], Config1[n], Config0[n] */ | 413 | if (irq >= AU1000_INTC1_INT_BASE) { |
| 325 | if (bit >= 32) { | 414 | bit = irq - AU1000_INTC1_INT_BASE; |
| 326 | switch (type) { | 415 | chip = &au1x_ic1_chip; |
| 327 | case INTC_INT_RISE_EDGE: /* 0:0:1 */ | 416 | ic = 1; |
| 328 | au_writel(1 << (bit - 32), IC1_CFG2CLR); | ||
| 329 | au_writel(1 << (bit - 32), IC1_CFG1CLR); | ||
| 330 | au_writel(1 << (bit - 32), IC1_CFG0SET); | ||
| 331 | set_irq_chip(irq_nr, &rise_edge_irq_type); | ||
| 332 | break; | ||
| 333 | case INTC_INT_FALL_EDGE: /* 0:1:0 */ | ||
| 334 | au_writel(1 << (bit - 32), IC1_CFG2CLR); | ||
| 335 | au_writel(1 << (bit - 32), IC1_CFG1SET); | ||
| 336 | au_writel(1 << (bit - 32), IC1_CFG0CLR); | ||
| 337 | set_irq_chip(irq_nr, &fall_edge_irq_type); | ||
| 338 | break; | ||
| 339 | case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */ | ||
| 340 | au_writel(1 << (bit - 32), IC1_CFG2CLR); | ||
| 341 | au_writel(1 << (bit - 32), IC1_CFG1SET); | ||
| 342 | au_writel(1 << (bit - 32), IC1_CFG0SET); | ||
| 343 | set_irq_chip(irq_nr, &either_edge_irq_type); | ||
| 344 | break; | ||
| 345 | case INTC_INT_HIGH_LEVEL: /* 1:0:1 */ | ||
| 346 | au_writel(1 << (bit - 32), IC1_CFG2SET); | ||
| 347 | au_writel(1 << (bit - 32), IC1_CFG1CLR); | ||
| 348 | au_writel(1 << (bit - 32), IC1_CFG0SET); | ||
| 349 | set_irq_chip(irq_nr, &level_irq_type); | ||
| 350 | break; | ||
| 351 | case INTC_INT_LOW_LEVEL: /* 1:1:0 */ | ||
| 352 | au_writel(1 << (bit - 32), IC1_CFG2SET); | ||
| 353 | au_writel(1 << (bit - 32), IC1_CFG1SET); | ||
| 354 | au_writel(1 << (bit - 32), IC1_CFG0CLR); | ||
| 355 | set_irq_chip(irq_nr, &level_irq_type); | ||
| 356 | break; | ||
| 357 | case INTC_INT_DISABLED: /* 0:0:0 */ | ||
| 358 | au_writel(1 << (bit - 32), IC1_CFG0CLR); | ||
| 359 | au_writel(1 << (bit - 32), IC1_CFG1CLR); | ||
| 360 | au_writel(1 << (bit - 32), IC1_CFG2CLR); | ||
| 361 | break; | ||
| 362 | default: /* disable the interrupt */ | ||
| 363 | printk(KERN_WARNING "unexpected int type %d (irq %d)\n", | ||
| 364 | type, irq_nr); | ||
| 365 | au_writel(1 << (bit - 32), IC1_CFG0CLR); | ||
| 366 | au_writel(1 << (bit - 32), IC1_CFG1CLR); | ||
| 367 | au_writel(1 << (bit - 32), IC1_CFG2CLR); | ||
| 368 | return; | ||
| 369 | } | ||
| 370 | if (int_req) /* assign to interrupt request 1 */ | ||
| 371 | au_writel(1 << (bit - 32), IC1_ASSIGNCLR); | ||
| 372 | else /* assign to interrupt request 0 */ | ||
| 373 | au_writel(1 << (bit - 32), IC1_ASSIGNSET); | ||
| 374 | au_writel(1 << (bit - 32), IC1_SRCSET); | ||
| 375 | au_writel(1 << (bit - 32), IC1_MASKCLR); | ||
| 376 | au_writel(1 << (bit - 32), IC1_WAKECLR); | ||
| 377 | } else { | 417 | } else { |
| 378 | switch (type) { | 418 | bit = irq - AU1000_INTC0_INT_BASE; |
| 379 | case INTC_INT_RISE_EDGE: /* 0:0:1 */ | 419 | chip = &au1x_ic0_chip; |
| 380 | au_writel(1 << bit, IC0_CFG2CLR); | 420 | ic = 0; |
| 381 | au_writel(1 << bit, IC0_CFG1CLR); | 421 | } |
| 382 | au_writel(1 << bit, IC0_CFG0SET); | 422 | |
| 383 | set_irq_chip(irq_nr, &rise_edge_irq_type); | 423 | if (bit > 31) |
| 384 | break; | 424 | return -EINVAL; |
| 385 | case INTC_INT_FALL_EDGE: /* 0:1:0 */ | 425 | |
| 386 | au_writel(1 << bit, IC0_CFG2CLR); | 426 | icr[0] = ic ? IC1_CFG0SET : IC0_CFG0SET; |
| 387 | au_writel(1 << bit, IC0_CFG1SET); | 427 | icr[1] = ic ? IC1_CFG1SET : IC0_CFG1SET; |
| 388 | au_writel(1 << bit, IC0_CFG0CLR); | 428 | icr[2] = ic ? IC1_CFG2SET : IC0_CFG2SET; |
| 389 | set_irq_chip(irq_nr, &fall_edge_irq_type); | 429 | icr[3] = ic ? IC1_CFG0CLR : IC0_CFG0CLR; |
| 390 | break; | 430 | icr[4] = ic ? IC1_CFG1CLR : IC0_CFG1CLR; |
| 391 | case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */ | 431 | icr[5] = ic ? IC1_CFG2CLR : IC0_CFG2CLR; |
| 392 | au_writel(1 << bit, IC0_CFG2CLR); | 432 | |
| 393 | au_writel(1 << bit, IC0_CFG1SET); | 433 | ret = 0; |
| 394 | au_writel(1 << bit, IC0_CFG0SET); | 434 | |
| 395 | set_irq_chip(irq_nr, &either_edge_irq_type); | 435 | switch (flow_type) { /* cfgregs 2:1:0 */ |
| 396 | break; | 436 | case IRQ_TYPE_EDGE_RISING: /* 0:0:1 */ |
| 397 | case INTC_INT_HIGH_LEVEL: /* 1:0:1 */ | 437 | au_writel(1 << bit, icr[5]); |
| 398 | au_writel(1 << bit, IC0_CFG2SET); | 438 | au_writel(1 << bit, icr[4]); |
| 399 | au_writel(1 << bit, IC0_CFG1CLR); | 439 | au_writel(1 << bit, icr[0]); |
| 400 | au_writel(1 << bit, IC0_CFG0SET); | 440 | set_irq_chip_and_handler_name(irq, chip, |
| 401 | set_irq_chip(irq_nr, &level_irq_type); | 441 | handle_edge_irq, "riseedge"); |
| 402 | break; | 442 | break; |
| 403 | case INTC_INT_LOW_LEVEL: /* 1:1:0 */ | 443 | case IRQ_TYPE_EDGE_FALLING: /* 0:1:0 */ |
| 404 | au_writel(1 << bit, IC0_CFG2SET); | 444 | au_writel(1 << bit, icr[5]); |
| 405 | au_writel(1 << bit, IC0_CFG1SET); | 445 | au_writel(1 << bit, icr[1]); |
| 406 | au_writel(1 << bit, IC0_CFG0CLR); | 446 | au_writel(1 << bit, icr[3]); |
| 407 | set_irq_chip(irq_nr, &level_irq_type); | 447 | set_irq_chip_and_handler_name(irq, chip, |
| 408 | break; | 448 | handle_edge_irq, "falledge"); |
| 409 | case INTC_INT_DISABLED: /* 0:0:0 */ | 449 | break; |
| 410 | au_writel(1 << bit, IC0_CFG0CLR); | 450 | case IRQ_TYPE_EDGE_BOTH: /* 0:1:1 */ |
| 411 | au_writel(1 << bit, IC0_CFG1CLR); | 451 | au_writel(1 << bit, icr[5]); |
| 412 | au_writel(1 << bit, IC0_CFG2CLR); | 452 | au_writel(1 << bit, icr[1]); |
| 413 | break; | 453 | au_writel(1 << bit, icr[0]); |
| 414 | default: /* disable the interrupt */ | 454 | set_irq_chip_and_handler_name(irq, chip, |
| 415 | printk(KERN_WARNING "unexpected int type %d (irq %d)\n", | 455 | handle_edge_irq, "bothedge"); |
| 416 | type, irq_nr); | 456 | break; |
| 417 | au_writel(1 << bit, IC0_CFG0CLR); | 457 | case IRQ_TYPE_LEVEL_HIGH: /* 1:0:1 */ |
| 418 | au_writel(1 << bit, IC0_CFG1CLR); | 458 | au_writel(1 << bit, icr[2]); |
| 419 | au_writel(1 << bit, IC0_CFG2CLR); | 459 | au_writel(1 << bit, icr[4]); |
| 420 | return; | 460 | au_writel(1 << bit, icr[0]); |
| 421 | } | 461 | set_irq_chip_and_handler_name(irq, chip, |
| 422 | if (int_req) /* assign to interrupt request 1 */ | 462 | handle_level_irq, "hilevel"); |
| 423 | au_writel(1 << bit, IC0_ASSIGNCLR); | 463 | break; |
| 424 | else /* assign to interrupt request 0 */ | 464 | case IRQ_TYPE_LEVEL_LOW: /* 1:1:0 */ |
| 425 | au_writel(1 << bit, IC0_ASSIGNSET); | 465 | au_writel(1 << bit, icr[2]); |
| 426 | au_writel(1 << bit, IC0_SRCSET); | 466 | au_writel(1 << bit, icr[1]); |
| 427 | au_writel(1 << bit, IC0_MASKCLR); | 467 | au_writel(1 << bit, icr[3]); |
| 428 | au_writel(1 << bit, IC0_WAKECLR); | 468 | set_irq_chip_and_handler_name(irq, chip, |
| 469 | handle_level_irq, "lowlevel"); | ||
| 470 | break; | ||
| 471 | case IRQ_TYPE_NONE: /* 0:0:0 */ | ||
| 472 | au_writel(1 << bit, icr[5]); | ||
| 473 | au_writel(1 << bit, icr[4]); | ||
| 474 | au_writel(1 << bit, icr[3]); | ||
| 475 | /* set at least chip so we can call set_irq_type() on it */ | ||
| 476 | set_irq_chip(irq, chip); | ||
| 477 | break; | ||
| 478 | default: | ||
| 479 | ret = -EINVAL; | ||
| 429 | } | 480 | } |
| 430 | au_sync(); | 481 | au_sync(); |
| 431 | } | ||
| 432 | 482 | ||
| 433 | /* | 483 | return ret; |
| 434 | * Interrupts are nested. Even if an interrupt handler is registered | 484 | } |
| 435 | * as "fast", we might get another interrupt before we return from | ||
| 436 | * intcX_reqX_irqdispatch(). | ||
| 437 | */ | ||
| 438 | 485 | ||
| 439 | static void intc0_req0_irqdispatch(void) | 486 | asmlinkage void plat_irq_dispatch(void) |
| 440 | { | 487 | { |
| 441 | static unsigned long intc0_req0; | 488 | unsigned int pending = read_c0_status() & read_c0_cause(); |
| 442 | unsigned int bit; | 489 | unsigned long s, off, bit; |
| 443 | |||
| 444 | intc0_req0 |= au_readl(IC0_REQ0INT); | ||
| 445 | 490 | ||
| 446 | if (!intc0_req0) | 491 | if (pending & CAUSEF_IP7) { |
| 492 | do_IRQ(MIPS_CPU_IRQ_BASE + 7); | ||
| 447 | return; | 493 | return; |
| 448 | 494 | } else if (pending & CAUSEF_IP2) { | |
| 495 | s = IC0_REQ0INT; | ||
| 496 | off = AU1000_INTC0_INT_BASE; | ||
| 497 | } else if (pending & CAUSEF_IP3) { | ||
| 498 | s = IC0_REQ1INT; | ||
| 499 | off = AU1000_INTC0_INT_BASE; | ||
| 500 | } else if (pending & CAUSEF_IP4) { | ||
| 501 | s = IC1_REQ0INT; | ||
| 502 | off = AU1000_INTC1_INT_BASE; | ||
| 503 | } else if (pending & CAUSEF_IP5) { | ||
| 504 | s = IC1_REQ1INT; | ||
| 505 | off = AU1000_INTC1_INT_BASE; | ||
| 506 | } else | ||
| 507 | goto spurious; | ||
| 508 | |||
| 509 | bit = 0; | ||
| 510 | s = au_readl(s); | ||
| 511 | if (unlikely(!s)) { | ||
| 512 | spurious: | ||
| 513 | spurious_interrupt(); | ||
| 514 | return; | ||
| 515 | } | ||
| 449 | #ifdef AU1000_USB_DEV_REQ_INT | 516 | #ifdef AU1000_USB_DEV_REQ_INT |
| 450 | /* | 517 | /* |
| 451 | * Because of the tight timing of SETUP token to reply | 518 | * Because of the tight timing of SETUP token to reply |
| 452 | * transactions, the USB devices-side packet complete | 519 | * transactions, the USB devices-side packet complete |
| 453 | * interrupt needs the highest priority. | 520 | * interrupt needs the highest priority. |
| 454 | */ | 521 | */ |
| 455 | if ((intc0_req0 & (1 << AU1000_USB_DEV_REQ_INT))) { | 522 | bit = 1 << (AU1000_USB_DEV_REQ_INT - AU1000_INTC0_INT_BASE); |
| 456 | intc0_req0 &= ~(1 << AU1000_USB_DEV_REQ_INT); | 523 | if ((pending & CAUSEF_IP2) && (s & bit)) { |
| 457 | do_IRQ(AU1000_USB_DEV_REQ_INT); | 524 | do_IRQ(AU1000_USB_DEV_REQ_INT); |
| 458 | return; | 525 | return; |
| 459 | } | 526 | } |
| 460 | #endif | 527 | #endif |
| 461 | bit = __ffs(intc0_req0); | 528 | do_IRQ(__ffs(s) + off); |
| 462 | intc0_req0 &= ~(1 << bit); | ||
| 463 | do_IRQ(AU1000_INTC0_INT_BASE + bit); | ||
| 464 | } | 529 | } |
| 465 | 530 | ||
| 466 | 531 | /* setup edge/level and assign request 0/1 */ | |
| 467 | static void intc0_req1_irqdispatch(void) | 532 | void __init au1xxx_setup_irqmap(struct au1xxx_irqmap *map, int count) |
| 468 | { | ||
| 469 | static unsigned long intc0_req1; | ||
| 470 | unsigned int bit; | ||
| 471 | |||
| 472 | intc0_req1 |= au_readl(IC0_REQ1INT); | ||
| 473 | |||
| 474 | if (!intc0_req1) | ||
| 475 | return; | ||
| 476 | |||
| 477 | bit = __ffs(intc0_req1); | ||
| 478 | intc0_req1 &= ~(1 << bit); | ||
| 479 | do_IRQ(AU1000_INTC0_INT_BASE + bit); | ||
| 480 | } | ||
| 481 | |||
| 482 | |||
| 483 | /* | ||
| 484 | * Interrupt Controller 1: | ||
| 485 | * interrupts 32 - 63 | ||
| 486 | */ | ||
| 487 | static void intc1_req0_irqdispatch(void) | ||
| 488 | { | 533 | { |
| 489 | static unsigned long intc1_req0; | 534 | unsigned int bit, irq_nr; |
| 490 | unsigned int bit; | 535 | |
| 491 | 536 | while (count--) { | |
| 492 | intc1_req0 |= au_readl(IC1_REQ0INT); | 537 | irq_nr = map[count].im_irq; |
| 493 | 538 | ||
| 494 | if (!intc1_req0) | 539 | if (((irq_nr < AU1000_INTC0_INT_BASE) || |
| 495 | return; | 540 | (irq_nr >= AU1000_INTC0_INT_BASE + 32)) && |
| 496 | 541 | ((irq_nr < AU1000_INTC1_INT_BASE) || | |
| 497 | bit = __ffs(intc1_req0); | 542 | (irq_nr >= AU1000_INTC1_INT_BASE + 32))) |
| 498 | intc1_req0 &= ~(1 << bit); | 543 | continue; |
| 499 | do_IRQ(AU1000_INTC1_INT_BASE + bit); | 544 | |
| 500 | } | 545 | if (irq_nr >= AU1000_INTC1_INT_BASE) { |
| 501 | 546 | bit = irq_nr - AU1000_INTC1_INT_BASE; | |
| 502 | 547 | if (map[count].im_request) | |
| 503 | static void intc1_req1_irqdispatch(void) | 548 | au_writel(1 << bit, IC1_ASSIGNCLR); |
| 504 | { | 549 | } else { |
| 505 | static unsigned long intc1_req1; | 550 | bit = irq_nr - AU1000_INTC0_INT_BASE; |
| 506 | unsigned int bit; | 551 | if (map[count].im_request) |
| 507 | 552 | au_writel(1 << bit, IC0_ASSIGNCLR); | |
| 508 | intc1_req1 |= au_readl(IC1_REQ1INT); | 553 | } |
| 509 | |||
| 510 | if (!intc1_req1) | ||
| 511 | return; | ||
| 512 | |||
| 513 | bit = __ffs(intc1_req1); | ||
| 514 | intc1_req1 &= ~(1 << bit); | ||
| 515 | do_IRQ(AU1000_INTC1_INT_BASE + bit); | ||
| 516 | } | ||
| 517 | |||
| 518 | asmlinkage void plat_irq_dispatch(void) | ||
| 519 | { | ||
| 520 | unsigned int pending = read_c0_status() & read_c0_cause(); | ||
| 521 | 554 | ||
| 522 | if (pending & CAUSEF_IP7) | 555 | au1x_ic_settype(irq_nr, map[count].im_type); |
| 523 | do_IRQ(MIPS_CPU_IRQ_BASE + 7); | 556 | } |
| 524 | else if (pending & CAUSEF_IP2) | ||
| 525 | intc0_req0_irqdispatch(); | ||
| 526 | else if (pending & CAUSEF_IP3) | ||
| 527 | intc0_req1_irqdispatch(); | ||
| 528 | else if (pending & CAUSEF_IP4) | ||
| 529 | intc1_req0_irqdispatch(); | ||
| 530 | else if (pending & CAUSEF_IP5) | ||
| 531 | intc1_req1_irqdispatch(); | ||
| 532 | else | ||
| 533 | spurious_interrupt(); | ||
| 534 | } | 557 | } |
| 535 | 558 | ||
| 536 | void __init arch_init_irq(void) | 559 | void __init arch_init_irq(void) |
| 537 | { | 560 | { |
| 538 | int i; | 561 | int i; |
| 539 | struct au1xxx_irqmap *imp; | ||
| 540 | extern struct au1xxx_irqmap au1xxx_irq_map[]; | ||
| 541 | extern struct au1xxx_irqmap au1xxx_ic0_map[]; | ||
| 542 | extern int au1xxx_nr_irqs; | ||
| 543 | extern int au1xxx_ic0_nr_irqs; | ||
| 544 | 562 | ||
| 545 | /* | 563 | /* |
| 546 | * Initialize interrupt controllers to a safe state. | 564 | * Initialize interrupt controllers to a safe state. |
| @@ -569,28 +587,25 @@ void __init arch_init_irq(void) | |||
| 569 | 587 | ||
| 570 | mips_cpu_irq_init(); | 588 | mips_cpu_irq_init(); |
| 571 | 589 | ||
| 572 | /* | 590 | /* register all 64 possible IC0+IC1 irq sources as type "none". |
| 573 | * Initialize IC0, which is fixed per processor. | 591 | * Use set_irq_type() to set edge/level behaviour at runtime. |
| 574 | */ | 592 | */ |
| 575 | imp = au1xxx_ic0_map; | 593 | for (i = AU1000_INTC0_INT_BASE; |
| 576 | for (i = 0; i < au1xxx_ic0_nr_irqs; i++) { | 594 | (i < AU1000_INTC0_INT_BASE + 32); i++) |
| 577 | setup_local_irq(imp->im_irq, imp->im_type, imp->im_request); | 595 | au1x_ic_settype(i, IRQ_TYPE_NONE); |
| 578 | imp++; | 596 | |
| 579 | } | 597 | for (i = AU1000_INTC1_INT_BASE; |
| 598 | (i < AU1000_INTC1_INT_BASE + 32); i++) | ||
| 599 | au1x_ic_settype(i, IRQ_TYPE_NONE); | ||
| 580 | 600 | ||
| 581 | /* | 601 | /* |
| 582 | * Now set up the irq mapping for the board. | 602 | * Initialize IC0, which is fixed per processor. |
| 583 | */ | 603 | */ |
| 584 | imp = au1xxx_irq_map; | 604 | au1xxx_setup_irqmap(au1xxx_ic0_map, ARRAY_SIZE(au1xxx_ic0_map)); |
| 585 | for (i = 0; i < au1xxx_nr_irqs; i++) { | ||
| 586 | setup_local_irq(imp->im_irq, imp->im_type, imp->im_request); | ||
| 587 | imp++; | ||
| 588 | } | ||
| 589 | |||
| 590 | set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4); | ||
| 591 | 605 | ||
| 592 | /* Board specific IRQ initialization. | 606 | /* Boards can register additional (GPIO-based) IRQs. |
| 593 | */ | 607 | */ |
| 594 | if (board_init_irq) | 608 | board_init_irq(); |
| 595 | board_init_irq(); | 609 | |
| 610 | set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3); | ||
| 596 | } | 611 | } |
diff --git a/arch/mips/alchemy/common/power.c b/arch/mips/alchemy/common/power.c index bd854a6d1d89..6ab7b42aa1be 100644 --- a/arch/mips/alchemy/common/power.c +++ b/arch/mips/alchemy/common/power.c | |||
| @@ -35,25 +35,12 @@ | |||
| 35 | #include <linux/jiffies.h> | 35 | #include <linux/jiffies.h> |
| 36 | 36 | ||
| 37 | #include <asm/uaccess.h> | 37 | #include <asm/uaccess.h> |
| 38 | #include <asm/cacheflush.h> | ||
| 39 | #include <asm/mach-au1x00/au1000.h> | 38 | #include <asm/mach-au1x00/au1000.h> |
| 40 | 39 | #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) | |
| 41 | #ifdef CONFIG_PM | 40 | #include <asm/mach-au1x00/au1xxx_dbdma.h> |
| 42 | |||
| 43 | #define DEBUG 1 | ||
| 44 | #ifdef DEBUG | ||
| 45 | #define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __func__, ## args) | ||
| 46 | #else | ||
| 47 | #define DPRINTK(fmt, args...) | ||
| 48 | #endif | 41 | #endif |
| 49 | 42 | ||
| 50 | static void au1000_calibrate_delay(void); | 43 | #ifdef CONFIG_PM |
| 51 | |||
| 52 | extern unsigned long save_local_and_disable(int controller); | ||
| 53 | extern void restore_local_and_enable(int controller, unsigned long mask); | ||
| 54 | extern void local_enable_irq(unsigned int irq_nr); | ||
| 55 | |||
| 56 | static DEFINE_SPINLOCK(pm_lock); | ||
| 57 | 44 | ||
| 58 | /* | 45 | /* |
| 59 | * We need to save/restore a bunch of core registers that are | 46 | * We need to save/restore a bunch of core registers that are |
| @@ -65,29 +52,16 @@ static DEFINE_SPINLOCK(pm_lock); | |||
| 65 | * We only have to save/restore registers that aren't otherwise | 52 | * We only have to save/restore registers that aren't otherwise |
| 66 | * done as part of a driver pm_* function. | 53 | * done as part of a driver pm_* function. |
| 67 | */ | 54 | */ |
| 68 | static unsigned int sleep_aux_pll_cntrl; | 55 | static unsigned int sleep_uart0_inten; |
| 69 | static unsigned int sleep_cpu_pll_cntrl; | 56 | static unsigned int sleep_uart0_fifoctl; |
| 70 | static unsigned int sleep_pin_function; | 57 | static unsigned int sleep_uart0_linectl; |
| 71 | static unsigned int sleep_uart0_inten; | 58 | static unsigned int sleep_uart0_clkdiv; |
| 72 | static unsigned int sleep_uart0_fifoctl; | 59 | static unsigned int sleep_uart0_enable; |
| 73 | static unsigned int sleep_uart0_linectl; | 60 | static unsigned int sleep_usb[2]; |
| 74 | static unsigned int sleep_uart0_clkdiv; | 61 | static unsigned int sleep_sys_clocks[5]; |
| 75 | static unsigned int sleep_uart0_enable; | 62 | static unsigned int sleep_sys_pinfunc; |
| 76 | static unsigned int sleep_usbhost_enable; | 63 | static unsigned int sleep_static_memctlr[4][3]; |
| 77 | static unsigned int sleep_usbdev_enable; | ||
| 78 | static unsigned int sleep_static_memctlr[4][3]; | ||
| 79 | 64 | ||
| 80 | /* | ||
| 81 | * Define this to cause the value you write to /proc/sys/pm/sleep to | ||
| 82 | * set the TOY timer for the amount of time you want to sleep. | ||
| 83 | * This is done mainly for testing, but may be useful in other cases. | ||
| 84 | * The value is number of 32KHz ticks to sleep. | ||
| 85 | */ | ||
| 86 | #define SLEEP_TEST_TIMEOUT 1 | ||
| 87 | #ifdef SLEEP_TEST_TIMEOUT | ||
| 88 | static int sleep_ticks; | ||
| 89 | void wakeup_counter0_set(int ticks); | ||
| 90 | #endif | ||
| 91 | 65 | ||
| 92 | static void save_core_regs(void) | 66 | static void save_core_regs(void) |
| 93 | { | 67 | { |
| @@ -105,31 +79,45 @@ static void save_core_regs(void) | |||
| 105 | sleep_uart0_linectl = au_readl(UART0_ADDR + UART_LCR); | 79 | sleep_uart0_linectl = au_readl(UART0_ADDR + UART_LCR); |
| 106 | sleep_uart0_clkdiv = au_readl(UART0_ADDR + UART_CLK); | 80 | sleep_uart0_clkdiv = au_readl(UART0_ADDR + UART_CLK); |
| 107 | sleep_uart0_enable = au_readl(UART0_ADDR + UART_MOD_CNTRL); | 81 | sleep_uart0_enable = au_readl(UART0_ADDR + UART_MOD_CNTRL); |
| 82 | au_sync(); | ||
| 108 | 83 | ||
| 84 | #ifndef CONFIG_SOC_AU1200 | ||
| 109 | /* Shutdown USB host/device. */ | 85 | /* Shutdown USB host/device. */ |
| 110 | sleep_usbhost_enable = au_readl(USB_HOST_CONFIG); | 86 | sleep_usb[0] = au_readl(USB_HOST_CONFIG); |
| 111 | 87 | ||
| 112 | /* There appears to be some undocumented reset register.... */ | 88 | /* There appears to be some undocumented reset register.... */ |
| 113 | au_writel(0, 0xb0100004); au_sync(); | 89 | au_writel(0, 0xb0100004); |
| 114 | au_writel(0, USB_HOST_CONFIG); au_sync(); | 90 | au_sync(); |
| 91 | au_writel(0, USB_HOST_CONFIG); | ||
| 92 | au_sync(); | ||
| 115 | 93 | ||
| 116 | sleep_usbdev_enable = au_readl(USBD_ENABLE); | 94 | sleep_usb[1] = au_readl(USBD_ENABLE); |
| 117 | au_writel(0, USBD_ENABLE); au_sync(); | 95 | au_writel(0, USBD_ENABLE); |
| 96 | au_sync(); | ||
| 97 | |||
| 98 | #else /* AU1200 */ | ||
| 99 | |||
| 100 | /* enable access to OTG mmio so we can save OTG CAP/MUX. | ||
| 101 | * FIXME: write an OTG driver and move this stuff there! | ||
| 102 | */ | ||
| 103 | au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4); | ||
| 104 | au_sync(); | ||
| 105 | sleep_usb[0] = au_readl(0xb4020020); /* OTG_CAP */ | ||
| 106 | sleep_usb[1] = au_readl(0xb4020024); /* OTG_MUX */ | ||
| 107 | #endif | ||
| 118 | 108 | ||
| 119 | /* Save interrupt controller state. */ | 109 | /* Save interrupt controller state. */ |
| 120 | save_au1xxx_intctl(); | 110 | save_au1xxx_intctl(); |
| 121 | 111 | ||
| 122 | /* Clocks and PLLs. */ | 112 | /* Clocks and PLLs. */ |
| 123 | sleep_aux_pll_cntrl = au_readl(SYS_AUXPLL); | 113 | sleep_sys_clocks[0] = au_readl(SYS_FREQCTRL0); |
| 114 | sleep_sys_clocks[1] = au_readl(SYS_FREQCTRL1); | ||
| 115 | sleep_sys_clocks[2] = au_readl(SYS_CLKSRC); | ||
| 116 | sleep_sys_clocks[3] = au_readl(SYS_CPUPLL); | ||
| 117 | sleep_sys_clocks[4] = au_readl(SYS_AUXPLL); | ||
| 124 | 118 | ||
| 125 | /* | 119 | /* pin mux config */ |
| 126 | * We don't really need to do this one, but unless we | 120 | sleep_sys_pinfunc = au_readl(SYS_PINFUNC); |
| 127 | * write it again it won't have a valid value if we | ||
| 128 | * happen to read it. | ||
| 129 | */ | ||
| 130 | sleep_cpu_pll_cntrl = au_readl(SYS_CPUPLL); | ||
| 131 | |||
| 132 | sleep_pin_function = au_readl(SYS_PINFUNC); | ||
| 133 | 121 | ||
| 134 | /* Save the static memory controller configuration. */ | 122 | /* Save the static memory controller configuration. */ |
| 135 | sleep_static_memctlr[0][0] = au_readl(MEM_STCFG0); | 123 | sleep_static_memctlr[0][0] = au_readl(MEM_STCFG0); |
| @@ -144,16 +132,45 @@ static void save_core_regs(void) | |||
| 144 | sleep_static_memctlr[3][0] = au_readl(MEM_STCFG3); | 132 | sleep_static_memctlr[3][0] = au_readl(MEM_STCFG3); |
| 145 | sleep_static_memctlr[3][1] = au_readl(MEM_STTIME3); | 133 | sleep_static_memctlr[3][1] = au_readl(MEM_STTIME3); |
| 146 | sleep_static_memctlr[3][2] = au_readl(MEM_STADDR3); | 134 | sleep_static_memctlr[3][2] = au_readl(MEM_STADDR3); |
| 135 | |||
| 136 | #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) | ||
| 137 | au1xxx_dbdma_suspend(); | ||
| 138 | #endif | ||
| 147 | } | 139 | } |
| 148 | 140 | ||
| 149 | static void restore_core_regs(void) | 141 | static void restore_core_regs(void) |
| 150 | { | 142 | { |
| 151 | extern void restore_au1xxx_intctl(void); | 143 | /* restore clock configuration. Writing CPUPLL last will |
| 152 | extern void wakeup_counter0_adjust(void); | 144 | * stall a bit and stabilize other clocks (unless this is |
| 145 | * one of those Au1000 with a write-only PLL, where we dont | ||
| 146 | * have a valid value) | ||
| 147 | */ | ||
| 148 | au_writel(sleep_sys_clocks[0], SYS_FREQCTRL0); | ||
| 149 | au_writel(sleep_sys_clocks[1], SYS_FREQCTRL1); | ||
| 150 | au_writel(sleep_sys_clocks[2], SYS_CLKSRC); | ||
| 151 | au_writel(sleep_sys_clocks[4], SYS_AUXPLL); | ||
| 152 | if (!au1xxx_cpu_has_pll_wo()) | ||
| 153 | au_writel(sleep_sys_clocks[3], SYS_CPUPLL); | ||
| 154 | au_sync(); | ||
| 153 | 155 | ||
| 154 | au_writel(sleep_aux_pll_cntrl, SYS_AUXPLL); au_sync(); | 156 | au_writel(sleep_sys_pinfunc, SYS_PINFUNC); |
| 155 | au_writel(sleep_cpu_pll_cntrl, SYS_CPUPLL); au_sync(); | 157 | au_sync(); |
| 156 | au_writel(sleep_pin_function, SYS_PINFUNC); au_sync(); | 158 | |
| 159 | #ifndef CONFIG_SOC_AU1200 | ||
| 160 | au_writel(sleep_usb[0], USB_HOST_CONFIG); | ||
| 161 | au_writel(sleep_usb[1], USBD_ENABLE); | ||
| 162 | au_sync(); | ||
| 163 | #else | ||
| 164 | /* enable accces to OTG memory */ | ||
| 165 | au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4); | ||
| 166 | au_sync(); | ||
| 167 | |||
| 168 | /* restore OTG caps and port mux. */ | ||
| 169 | au_writel(sleep_usb[0], 0xb4020020 + 0); /* OTG_CAP */ | ||
| 170 | au_sync(); | ||
| 171 | au_writel(sleep_usb[1], 0xb4020020 + 4); /* OTG_MUX */ | ||
| 172 | au_sync(); | ||
| 173 | #endif | ||
| 157 | 174 | ||
| 158 | /* Restore the static memory controller configuration. */ | 175 | /* Restore the static memory controller configuration. */ |
| 159 | au_writel(sleep_static_memctlr[0][0], MEM_STCFG0); | 176 | au_writel(sleep_static_memctlr[0][0], MEM_STCFG0); |
| @@ -184,282 +201,17 @@ static void restore_core_regs(void) | |||
| 184 | } | 201 | } |
| 185 | 202 | ||
| 186 | restore_au1xxx_intctl(); | 203 | restore_au1xxx_intctl(); |
| 187 | wakeup_counter0_adjust(); | ||
| 188 | } | ||
| 189 | |||
| 190 | unsigned long suspend_mode; | ||
| 191 | 204 | ||
| 192 | void wakeup_from_suspend(void) | 205 | #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) |
| 193 | { | 206 | au1xxx_dbdma_resume(); |
| 194 | suspend_mode = 0; | 207 | #endif |
| 195 | } | 208 | } |
| 196 | 209 | ||
| 197 | int au_sleep(void) | 210 | void au_sleep(void) |
| 198 | { | 211 | { |
| 199 | unsigned long wakeup, flags; | ||
| 200 | extern void save_and_sleep(void); | ||
| 201 | |||
| 202 | spin_lock_irqsave(&pm_lock, flags); | ||
| 203 | |||
| 204 | save_core_regs(); | 212 | save_core_regs(); |
| 205 | 213 | au1xxx_save_and_sleep(); | |
| 206 | flush_cache_all(); | ||
| 207 | |||
| 208 | /** | ||
| 209 | ** The code below is all system dependent and we should probably | ||
| 210 | ** have a function call out of here to set this up. You need | ||
| 211 | ** to configure the GPIO or timer interrupts that will bring | ||
| 212 | ** you out of sleep. | ||
| 213 | ** For testing, the TOY counter wakeup is useful. | ||
| 214 | **/ | ||
| 215 | #if 0 | ||
| 216 | au_writel(au_readl(SYS_PINSTATERD) & ~(1 << 11), SYS_PINSTATERD); | ||
| 217 | |||
| 218 | /* GPIO 6 can cause a wake up event */ | ||
| 219 | wakeup = au_readl(SYS_WAKEMSK); | ||
| 220 | wakeup &= ~(1 << 8); /* turn off match20 wakeup */ | ||
| 221 | wakeup |= 1 << 6; /* turn on GPIO 6 wakeup */ | ||
| 222 | #else | ||
| 223 | /* For testing, allow match20 to wake us up. */ | ||
| 224 | #ifdef SLEEP_TEST_TIMEOUT | ||
| 225 | wakeup_counter0_set(sleep_ticks); | ||
| 226 | #endif | ||
| 227 | wakeup = 1 << 8; /* turn on match20 wakeup */ | ||
| 228 | wakeup = 0; | ||
| 229 | #endif | ||
| 230 | au_writel(1, SYS_WAKESRC); /* clear cause */ | ||
| 231 | au_sync(); | ||
| 232 | au_writel(wakeup, SYS_WAKEMSK); | ||
| 233 | au_sync(); | ||
| 234 | |||
| 235 | save_and_sleep(); | ||
| 236 | |||
| 237 | /* | ||
| 238 | * After a wakeup, the cpu vectors back to 0x1fc00000, so | ||
| 239 | * it's up to the boot code to get us back here. | ||
| 240 | */ | ||
| 241 | restore_core_regs(); | 214 | restore_core_regs(); |
| 242 | spin_unlock_irqrestore(&pm_lock, flags); | ||
| 243 | return 0; | ||
| 244 | } | ||
| 245 | |||
| 246 | static int pm_do_sleep(ctl_table *ctl, int write, struct file *file, | ||
| 247 | void __user *buffer, size_t *len, loff_t *ppos) | ||
| 248 | { | ||
| 249 | #ifdef SLEEP_TEST_TIMEOUT | ||
| 250 | #define TMPBUFLEN2 16 | ||
| 251 | char buf[TMPBUFLEN2], *p; | ||
| 252 | #endif | ||
| 253 | |||
| 254 | if (!write) | ||
| 255 | *len = 0; | ||
| 256 | else { | ||
| 257 | #ifdef SLEEP_TEST_TIMEOUT | ||
| 258 | if (*len > TMPBUFLEN2 - 1) | ||
| 259 | return -EFAULT; | ||
| 260 | if (copy_from_user(buf, buffer, *len)) | ||
| 261 | return -EFAULT; | ||
| 262 | buf[*len] = 0; | ||
| 263 | p = buf; | ||
| 264 | sleep_ticks = simple_strtoul(p, &p, 0); | ||
| 265 | #endif | ||
| 266 | |||
| 267 | au_sleep(); | ||
| 268 | } | ||
| 269 | return 0; | ||
| 270 | } | ||
| 271 | |||
| 272 | static int pm_do_freq(ctl_table *ctl, int write, struct file *file, | ||
| 273 | void __user *buffer, size_t *len, loff_t *ppos) | ||
| 274 | { | ||
| 275 | int retval = 0, i; | ||
| 276 | unsigned long val, pll; | ||
| 277 | #define TMPBUFLEN 64 | ||
| 278 | #define MAX_CPU_FREQ 396 | ||
| 279 | char buf[TMPBUFLEN], *p; | ||
| 280 | unsigned long flags, intc0_mask, intc1_mask; | ||
| 281 | unsigned long old_baud_base, old_cpu_freq, old_clk, old_refresh; | ||
| 282 | unsigned long new_baud_base, new_cpu_freq, new_clk, new_refresh; | ||
| 283 | unsigned long baud_rate; | ||
| 284 | |||
| 285 | spin_lock_irqsave(&pm_lock, flags); | ||
| 286 | if (!write) | ||
| 287 | *len = 0; | ||
| 288 | else { | ||
| 289 | /* Parse the new frequency */ | ||
| 290 | if (*len > TMPBUFLEN - 1) { | ||
| 291 | spin_unlock_irqrestore(&pm_lock, flags); | ||
| 292 | return -EFAULT; | ||
| 293 | } | ||
| 294 | if (copy_from_user(buf, buffer, *len)) { | ||
| 295 | spin_unlock_irqrestore(&pm_lock, flags); | ||
| 296 | return -EFAULT; | ||
| 297 | } | ||
| 298 | buf[*len] = 0; | ||
| 299 | p = buf; | ||
| 300 | val = simple_strtoul(p, &p, 0); | ||
| 301 | if (val > MAX_CPU_FREQ) { | ||
| 302 | spin_unlock_irqrestore(&pm_lock, flags); | ||
| 303 | return -EFAULT; | ||
| 304 | } | ||
| 305 | |||
| 306 | pll = val / 12; | ||
| 307 | if ((pll > 33) || (pll < 7)) { /* 396 MHz max, 84 MHz min */ | ||
| 308 | /* Revisit this for higher speed CPUs */ | ||
| 309 | spin_unlock_irqrestore(&pm_lock, flags); | ||
| 310 | return -EFAULT; | ||
| 311 | } | ||
| 312 | |||
| 313 | old_baud_base = get_au1x00_uart_baud_base(); | ||
| 314 | old_cpu_freq = get_au1x00_speed(); | ||
| 315 | |||
| 316 | new_cpu_freq = pll * 12 * 1000000; | ||
| 317 | new_baud_base = (new_cpu_freq / (2 * ((int)(au_readl(SYS_POWERCTRL) | ||
| 318 | & 0x03) + 2) * 16)); | ||
| 319 | set_au1x00_speed(new_cpu_freq); | ||
| 320 | set_au1x00_uart_baud_base(new_baud_base); | ||
| 321 | |||
| 322 | old_refresh = au_readl(MEM_SDREFCFG) & 0x1ffffff; | ||
| 323 | new_refresh = ((old_refresh * new_cpu_freq) / old_cpu_freq) | | ||
| 324 | (au_readl(MEM_SDREFCFG) & ~0x1ffffff); | ||
| 325 | |||
| 326 | au_writel(pll, SYS_CPUPLL); | ||
| 327 | au_sync_delay(1); | ||
| 328 | au_writel(new_refresh, MEM_SDREFCFG); | ||
| 329 | au_sync_delay(1); | ||
| 330 | |||
| 331 | for (i = 0; i < 4; i++) | ||
| 332 | if (au_readl(UART_BASE + UART_MOD_CNTRL + | ||
| 333 | i * 0x00100000) == 3) { | ||
| 334 | old_clk = au_readl(UART_BASE + UART_CLK + | ||
| 335 | i * 0x00100000); | ||
| 336 | baud_rate = old_baud_base / old_clk; | ||
| 337 | /* | ||
| 338 | * We won't get an exact baud rate and the error | ||
| 339 | * could be significant enough that our new | ||
| 340 | * calculation will result in a clock that will | ||
| 341 | * give us a baud rate that's too far off from | ||
| 342 | * what we really want. | ||
| 343 | */ | ||
| 344 | if (baud_rate > 100000) | ||
| 345 | baud_rate = 115200; | ||
| 346 | else if (baud_rate > 50000) | ||
| 347 | baud_rate = 57600; | ||
| 348 | else if (baud_rate > 30000) | ||
| 349 | baud_rate = 38400; | ||
| 350 | else if (baud_rate > 17000) | ||
| 351 | baud_rate = 19200; | ||
| 352 | else | ||
| 353 | baud_rate = 9600; | ||
| 354 | new_clk = new_baud_base / baud_rate; | ||
| 355 | au_writel(new_clk, UART_BASE + UART_CLK + | ||
| 356 | i * 0x00100000); | ||
| 357 | au_sync_delay(10); | ||
| 358 | } | ||
| 359 | } | ||
| 360 | |||
| 361 | /* | ||
| 362 | * We don't want _any_ interrupts other than match20. Otherwise our | ||
| 363 | * au1000_calibrate_delay() calculation will be off, potentially a lot. | ||
| 364 | */ | ||
| 365 | intc0_mask = save_local_and_disable(0); | ||
| 366 | intc1_mask = save_local_and_disable(1); | ||
| 367 | local_enable_irq(AU1000_TOY_MATCH2_INT); | ||
| 368 | spin_unlock_irqrestore(&pm_lock, flags); | ||
| 369 | au1000_calibrate_delay(); | ||
| 370 | restore_local_and_enable(0, intc0_mask); | ||
| 371 | restore_local_and_enable(1, intc1_mask); | ||
| 372 | |||
| 373 | return retval; | ||
| 374 | } | 215 | } |
| 375 | 216 | ||
| 376 | |||
| 377 | static struct ctl_table pm_table[] = { | ||
| 378 | { | ||
| 379 | .ctl_name = CTL_UNNUMBERED, | ||
| 380 | .procname = "sleep", | ||
| 381 | .data = NULL, | ||
| 382 | .maxlen = 0, | ||
| 383 | .mode = 0600, | ||
| 384 | .proc_handler = &pm_do_sleep | ||
| 385 | }, | ||
| 386 | { | ||
| 387 | .ctl_name = CTL_UNNUMBERED, | ||
| 388 | .procname = "freq", | ||
| 389 | .data = NULL, | ||
| 390 | .maxlen = 0, | ||
| 391 | .mode = 0600, | ||
| 392 | .proc_handler = &pm_do_freq | ||
| 393 | }, | ||
| 394 | {} | ||
| 395 | }; | ||
| 396 | |||
| 397 | static struct ctl_table pm_dir_table[] = { | ||
| 398 | { | ||
| 399 | .ctl_name = CTL_UNNUMBERED, | ||
| 400 | .procname = "pm", | ||
| 401 | .mode = 0555, | ||
| 402 | .child = pm_table | ||
| 403 | }, | ||
| 404 | {} | ||
| 405 | }; | ||
| 406 | |||
| 407 | /* | ||
| 408 | * Initialize power interface | ||
| 409 | */ | ||
| 410 | static int __init pm_init(void) | ||
| 411 | { | ||
| 412 | register_sysctl_table(pm_dir_table); | ||
| 413 | return 0; | ||
| 414 | } | ||
| 415 | |||
| 416 | __initcall(pm_init); | ||
| 417 | |||
| 418 | /* | ||
| 419 | * This is right out of init/main.c | ||
| 420 | */ | ||
| 421 | |||
| 422 | /* | ||
| 423 | * This is the number of bits of precision for the loops_per_jiffy. | ||
| 424 | * Each bit takes on average 1.5/HZ seconds. This (like the original) | ||
| 425 | * is a little better than 1%. | ||
| 426 | */ | ||
| 427 | #define LPS_PREC 8 | ||
| 428 | |||
| 429 | static void au1000_calibrate_delay(void) | ||
| 430 | { | ||
| 431 | unsigned long ticks, loopbit; | ||
| 432 | int lps_precision = LPS_PREC; | ||
| 433 | |||
| 434 | loops_per_jiffy = 1 << 12; | ||
| 435 | |||
| 436 | while (loops_per_jiffy <<= 1) { | ||
| 437 | /* Wait for "start of" clock tick */ | ||
| 438 | ticks = jiffies; | ||
| 439 | while (ticks == jiffies) | ||
| 440 | /* nothing */ ; | ||
| 441 | /* Go ... */ | ||
| 442 | ticks = jiffies; | ||
| 443 | __delay(loops_per_jiffy); | ||
| 444 | ticks = jiffies - ticks; | ||
| 445 | if (ticks) | ||
| 446 | break; | ||
| 447 | } | ||
| 448 | |||
| 449 | /* | ||
| 450 | * Do a binary approximation to get loops_per_jiffy set to be equal | ||
| 451 | * one clock (up to lps_precision bits) | ||
| 452 | */ | ||
| 453 | loops_per_jiffy >>= 1; | ||
| 454 | loopbit = loops_per_jiffy; | ||
| 455 | while (lps_precision-- && (loopbit >>= 1)) { | ||
| 456 | loops_per_jiffy |= loopbit; | ||
| 457 | ticks = jiffies; | ||
| 458 | while (ticks == jiffies); | ||
| 459 | ticks = jiffies; | ||
| 460 | __delay(loops_per_jiffy); | ||
| 461 | if (jiffies != ticks) /* longer than 1 tick */ | ||
| 462 | loops_per_jiffy &= ~loopbit; | ||
| 463 | } | ||
| 464 | } | ||
| 465 | #endif /* CONFIG_PM */ | 217 | #endif /* CONFIG_PM */ |
diff --git a/arch/mips/alchemy/common/reset.c b/arch/mips/alchemy/common/reset.c index d555429c8d6f..0191c936cb5e 100644 --- a/arch/mips/alchemy/common/reset.c +++ b/arch/mips/alchemy/common/reset.c | |||
| @@ -31,8 +31,6 @@ | |||
| 31 | 31 | ||
| 32 | #include <asm/mach-au1x00/au1000.h> | 32 | #include <asm/mach-au1x00/au1000.h> |
| 33 | 33 | ||
| 34 | extern int au_sleep(void); | ||
| 35 | |||
| 36 | void au1000_restart(char *command) | 34 | void au1000_restart(char *command) |
| 37 | { | 35 | { |
| 38 | /* Set all integrated peripherals to disabled states */ | 36 | /* Set all integrated peripherals to disabled states */ |
diff --git a/arch/mips/alchemy/common/setup.c b/arch/mips/alchemy/common/setup.c index 1ac6b06f42a3..3f036b3d400e 100644 --- a/arch/mips/alchemy/common/setup.c +++ b/arch/mips/alchemy/common/setup.c | |||
| @@ -35,7 +35,6 @@ | |||
| 35 | #include <asm/time.h> | 35 | #include <asm/time.h> |
| 36 | 36 | ||
| 37 | #include <au1000.h> | 37 | #include <au1000.h> |
| 38 | #include <prom.h> | ||
| 39 | 38 | ||
| 40 | extern void __init board_setup(void); | 39 | extern void __init board_setup(void); |
| 41 | extern void au1000_restart(char *); | 40 | extern void au1000_restart(char *); |
| @@ -45,80 +44,34 @@ extern void set_cpuspec(void); | |||
| 45 | 44 | ||
| 46 | void __init plat_mem_setup(void) | 45 | void __init plat_mem_setup(void) |
| 47 | { | 46 | { |
| 48 | struct cpu_spec *sp; | 47 | unsigned long est_freq; |
| 49 | char *argptr; | ||
| 50 | unsigned long prid, cpufreq, bclk; | ||
| 51 | 48 | ||
| 52 | set_cpuspec(); | 49 | /* determine core clock */ |
| 53 | sp = cur_cpu_spec[0]; | 50 | est_freq = au1xxx_calc_clock(); |
| 51 | est_freq += 5000; /* round */ | ||
| 52 | est_freq -= est_freq % 10000; | ||
| 53 | printk(KERN_INFO "(PRId %08x) @ %lu.%02lu MHz\n", read_c0_prid(), | ||
| 54 | est_freq / 1000000, ((est_freq % 1000000) * 100) / 1000000); | ||
| 54 | 55 | ||
| 55 | board_setup(); /* board specific setup */ | 56 | _machine_restart = au1000_restart; |
| 56 | 57 | _machine_halt = au1000_halt; | |
| 57 | prid = read_c0_prid(); | 58 | pm_power_off = au1000_power_off; |
| 58 | if (sp->cpu_pll_wo) | ||
| 59 | #ifdef CONFIG_SOC_AU1000_FREQUENCY | ||
| 60 | cpufreq = CONFIG_SOC_AU1000_FREQUENCY / 1000000; | ||
| 61 | #else | ||
| 62 | cpufreq = 396; | ||
| 63 | #endif | ||
| 64 | else | ||
| 65 | cpufreq = (au_readl(SYS_CPUPLL) & 0x3F) * 12; | ||
| 66 | printk(KERN_INFO "(PRID %08lx) @ %ld MHz\n", prid, cpufreq); | ||
| 67 | 59 | ||
| 68 | if (sp->cpu_bclk) { | 60 | board_setup(); /* board specific setup */ |
| 69 | /* Enable BCLK switching */ | ||
| 70 | bclk = au_readl(SYS_POWERCTRL); | ||
| 71 | au_writel(bclk | 0x60, SYS_POWERCTRL); | ||
| 72 | printk(KERN_INFO "BCLK switching enabled!\n"); | ||
| 73 | } | ||
| 74 | 61 | ||
| 75 | if (sp->cpu_od) | 62 | if (au1xxx_cpu_needs_config_od()) |
| 76 | /* Various early Au1xx0 errata corrected by this */ | 63 | /* Various early Au1xx0 errata corrected by this */ |
| 77 | set_c0_config(1 << 19); /* Set Config[OD] */ | 64 | set_c0_config(1 << 19); /* Set Config[OD] */ |
| 78 | else | 65 | else |
| 79 | /* Clear to obtain best system bus performance */ | 66 | /* Clear to obtain best system bus performance */ |
| 80 | clear_c0_config(1 << 19); /* Clear Config[OD] */ | 67 | clear_c0_config(1 << 19); /* Clear Config[OD] */ |
| 81 | 68 | ||
| 82 | argptr = prom_getcmdline(); | ||
| 83 | |||
| 84 | #ifdef CONFIG_SERIAL_8250_CONSOLE | ||
| 85 | argptr = strstr(argptr, "console="); | ||
| 86 | if (argptr == NULL) { | ||
| 87 | argptr = prom_getcmdline(); | ||
| 88 | strcat(argptr, " console=ttyS0,115200"); | ||
| 89 | } | ||
| 90 | #endif | ||
| 91 | |||
| 92 | #ifdef CONFIG_FB_AU1100 | ||
| 93 | argptr = strstr(argptr, "video="); | ||
| 94 | if (argptr == NULL) { | ||
| 95 | argptr = prom_getcmdline(); | ||
| 96 | /* default panel */ | ||
| 97 | /*strcat(argptr, " video=au1100fb:panel:Sharp_320x240_16");*/ | ||
| 98 | } | ||
| 99 | #endif | ||
| 100 | |||
| 101 | #if defined(CONFIG_SOUND_AU1X00) && !defined(CONFIG_SOC_AU1000) | ||
| 102 | /* au1000 does not support vra, au1500 and au1100 do */ | ||
| 103 | strcat(argptr, " au1000_audio=vra"); | ||
| 104 | argptr = prom_getcmdline(); | ||
| 105 | #endif | ||
| 106 | _machine_restart = au1000_restart; | ||
| 107 | _machine_halt = au1000_halt; | ||
| 108 | pm_power_off = au1000_power_off; | ||
| 109 | |||
| 110 | /* IO/MEM resources. */ | 69 | /* IO/MEM resources. */ |
| 111 | set_io_port_base(0); | 70 | set_io_port_base(0); |
| 112 | ioport_resource.start = IOPORT_RESOURCE_START; | 71 | ioport_resource.start = IOPORT_RESOURCE_START; |
| 113 | ioport_resource.end = IOPORT_RESOURCE_END; | 72 | ioport_resource.end = IOPORT_RESOURCE_END; |
| 114 | iomem_resource.start = IOMEM_RESOURCE_START; | 73 | iomem_resource.start = IOMEM_RESOURCE_START; |
| 115 | iomem_resource.end = IOMEM_RESOURCE_END; | 74 | iomem_resource.end = IOMEM_RESOURCE_END; |
| 116 | |||
| 117 | while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_E0S); | ||
| 118 | au_writel(SYS_CNTRL_E0 | SYS_CNTRL_EN0, SYS_COUNTER_CNTRL); | ||
| 119 | au_sync(); | ||
| 120 | while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T0S); | ||
| 121 | au_writel(0, SYS_TOYTRIM); | ||
| 122 | } | 75 | } |
| 123 | 76 | ||
| 124 | #if defined(CONFIG_64BIT_PHYS_ADDR) | 77 | #if defined(CONFIG_64BIT_PHYS_ADDR) |
diff --git a/arch/mips/alchemy/common/sleeper.S b/arch/mips/alchemy/common/sleeper.S index 3006e270c8bc..4f4b16741d12 100644 --- a/arch/mips/alchemy/common/sleeper.S +++ b/arch/mips/alchemy/common/sleeper.S | |||
| @@ -15,16 +15,17 @@ | |||
| 15 | #include <asm/regdef.h> | 15 | #include <asm/regdef.h> |
| 16 | #include <asm/stackframe.h> | 16 | #include <asm/stackframe.h> |
| 17 | 17 | ||
| 18 | .extern __flush_cache_all | ||
| 19 | |||
| 18 | .text | 20 | .text |
| 19 | .set macro | 21 | .set noreorder |
| 20 | .set noat | 22 | .set noat |
| 21 | .align 5 | 23 | .align 5 |
| 22 | 24 | ||
| 23 | /* Save all of the processor general registers and go to sleep. | 25 | /* Save all of the processor general registers and go to sleep. |
| 24 | * A wakeup condition will get us back here to restore the registers. | 26 | * A wakeup condition will get us back here to restore the registers. |
| 25 | */ | 27 | */ |
| 26 | LEAF(save_and_sleep) | 28 | LEAF(au1xxx_save_and_sleep) |
| 27 | |||
| 28 | subu sp, PT_SIZE | 29 | subu sp, PT_SIZE |
| 29 | sw $1, PT_R1(sp) | 30 | sw $1, PT_R1(sp) |
| 30 | sw $2, PT_R2(sp) | 31 | sw $2, PT_R2(sp) |
| @@ -33,14 +34,6 @@ LEAF(save_and_sleep) | |||
| 33 | sw $5, PT_R5(sp) | 34 | sw $5, PT_R5(sp) |
| 34 | sw $6, PT_R6(sp) | 35 | sw $6, PT_R6(sp) |
| 35 | sw $7, PT_R7(sp) | 36 | sw $7, PT_R7(sp) |
| 36 | sw $8, PT_R8(sp) | ||
| 37 | sw $9, PT_R9(sp) | ||
| 38 | sw $10, PT_R10(sp) | ||
| 39 | sw $11, PT_R11(sp) | ||
| 40 | sw $12, PT_R12(sp) | ||
| 41 | sw $13, PT_R13(sp) | ||
| 42 | sw $14, PT_R14(sp) | ||
| 43 | sw $15, PT_R15(sp) | ||
| 44 | sw $16, PT_R16(sp) | 37 | sw $16, PT_R16(sp) |
| 45 | sw $17, PT_R17(sp) | 38 | sw $17, PT_R17(sp) |
| 46 | sw $18, PT_R18(sp) | 39 | sw $18, PT_R18(sp) |
| @@ -49,12 +42,9 @@ LEAF(save_and_sleep) | |||
| 49 | sw $21, PT_R21(sp) | 42 | sw $21, PT_R21(sp) |
| 50 | sw $22, PT_R22(sp) | 43 | sw $22, PT_R22(sp) |
| 51 | sw $23, PT_R23(sp) | 44 | sw $23, PT_R23(sp) |
| 52 | sw $24, PT_R24(sp) | ||
| 53 | sw $25, PT_R25(sp) | ||
| 54 | sw $26, PT_R26(sp) | 45 | sw $26, PT_R26(sp) |
| 55 | sw $27, PT_R27(sp) | 46 | sw $27, PT_R27(sp) |
| 56 | sw $28, PT_R28(sp) | 47 | sw $28, PT_R28(sp) |
| 57 | sw $29, PT_R29(sp) | ||
| 58 | sw $30, PT_R30(sp) | 48 | sw $30, PT_R30(sp) |
| 59 | sw $31, PT_R31(sp) | 49 | sw $31, PT_R31(sp) |
| 60 | mfc0 k0, CP0_STATUS | 50 | mfc0 k0, CP0_STATUS |
| @@ -66,20 +56,26 @@ LEAF(save_and_sleep) | |||
| 66 | mfc0 k0, CP0_CONFIG | 56 | mfc0 k0, CP0_CONFIG |
| 67 | sw k0, 0x14(sp) | 57 | sw k0, 0x14(sp) |
| 68 | 58 | ||
| 59 | /* flush caches to make sure context is in memory */ | ||
| 60 | la t1, __flush_cache_all | ||
| 61 | lw t0, 0(t1) | ||
| 62 | jalr t0 | ||
| 63 | nop | ||
| 64 | |||
| 69 | /* Now set up the scratch registers so the boot rom will | 65 | /* Now set up the scratch registers so the boot rom will |
| 70 | * return to this point upon wakeup. | 66 | * return to this point upon wakeup. |
| 67 | * sys_scratch0 : SP | ||
| 68 | * sys_scratch1 : RA | ||
| 71 | */ | 69 | */ |
| 72 | la k0, 1f | 70 | lui t3, 0xb190 /* sys_xxx */ |
| 73 | lui k1, 0xb190 | 71 | sw sp, 0x0018(t3) |
| 74 | ori k1, 0x18 | 72 | la k0, 3f /* resume path */ |
| 75 | sw sp, 0(k1) | 73 | sw k0, 0x001c(t3) |
| 76 | ori k1, 0x1c | ||
| 77 | sw k0, 0(k1) | ||
| 78 | 74 | ||
| 79 | /* Put SDRAM into self refresh. Preload instructions into cache, | 75 | /* Put SDRAM into self refresh: Preload instructions into cache, |
| 80 | * issue a precharge, then auto refresh, then sleep commands to it. | 76 | * issue a precharge, auto/self refresh, then sleep commands to it. |
| 81 | */ | 77 | */ |
| 82 | la t0, sdsleep | 78 | la t0, 1f |
| 83 | .set mips3 | 79 | .set mips3 |
| 84 | cache 0x14, 0(t0) | 80 | cache 0x14, 0(t0) |
| 85 | cache 0x14, 32(t0) | 81 | cache 0x14, 32(t0) |
| @@ -87,24 +83,57 @@ LEAF(save_and_sleep) | |||
| 87 | cache 0x14, 96(t0) | 83 | cache 0x14, 96(t0) |
| 88 | .set mips0 | 84 | .set mips0 |
| 89 | 85 | ||
| 90 | sdsleep: | 86 | 1: lui a0, 0xb400 /* mem_xxx */ |
| 91 | lui k0, 0xb400 | 87 | #if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1100) || \ |
| 92 | sw zero, 0x001c(k0) /* Precharge */ | 88 | defined(CONFIG_SOC_AU1500) |
| 93 | sw zero, 0x0020(k0) /* Auto refresh */ | 89 | sw zero, 0x001c(a0) /* Precharge */ |
| 94 | sw zero, 0x0030(k0) /* SDRAM sleep */ | 90 | sync |
| 91 | sw zero, 0x0020(a0) /* Auto Refresh */ | ||
| 92 | sync | ||
| 93 | sw zero, 0x0030(a0) /* Sleep */ | ||
| 94 | sync | ||
| 95 | #endif | ||
| 96 | |||
| 97 | #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) | ||
| 98 | sw zero, 0x08c0(a0) /* Precharge */ | ||
| 95 | sync | 99 | sync |
| 100 | sw zero, 0x08d0(a0) /* Self Refresh */ | ||
| 101 | sync | ||
| 102 | |||
| 103 | /* wait for sdram to enter self-refresh mode */ | ||
| 104 | lui t0, 0x0100 | ||
| 105 | 2: lw t1, 0x0850(a0) /* mem_sdstat */ | ||
| 106 | and t2, t1, t0 | ||
| 107 | beq t2, zero, 2b | ||
| 108 | nop | ||
| 96 | 109 | ||
| 97 | lui k1, 0xb190 | 110 | /* disable SDRAM clocks */ |
| 98 | sw zero, 0x0078(k1) /* get ready to sleep */ | 111 | lui t0, 0xcfff |
| 112 | ori t0, t0, 0xffff | ||
| 113 | lw t1, 0x0840(a0) /* mem_sdconfiga */ | ||
| 114 | and t1, t0, t1 /* clear CE[1:0] */ | ||
| 115 | sw t1, 0x0840(a0) /* mem_sdconfiga */ | ||
| 99 | sync | 116 | sync |
| 100 | sw zero, 0x007c(k1) /* Put processor to sleep */ | 117 | #endif |
| 118 | |||
| 119 | /* put power supply and processor to sleep */ | ||
| 120 | sw zero, 0x0078(t3) /* sys_slppwr */ | ||
| 121 | sync | ||
| 122 | sw zero, 0x007c(t3) /* sys_sleep */ | ||
| 101 | sync | 123 | sync |
| 124 | nop | ||
| 125 | nop | ||
| 126 | nop | ||
| 127 | nop | ||
| 128 | nop | ||
| 129 | nop | ||
| 130 | nop | ||
| 131 | nop | ||
| 102 | 132 | ||
| 103 | /* This is where we return upon wakeup. | 133 | /* This is where we return upon wakeup. |
| 104 | * Reload all of the registers and return. | 134 | * Reload all of the registers and return. |
| 105 | */ | 135 | */ |
| 106 | 1: nop | 136 | 3: lw k0, 0x20(sp) |
| 107 | lw k0, 0x20(sp) | ||
| 108 | mtc0 k0, CP0_STATUS | 137 | mtc0 k0, CP0_STATUS |
| 109 | lw k0, 0x1c(sp) | 138 | lw k0, 0x1c(sp) |
| 110 | mtc0 k0, CP0_CONTEXT | 139 | mtc0 k0, CP0_CONTEXT |
| @@ -113,10 +142,11 @@ sdsleep: | |||
| 113 | lw k0, 0x14(sp) | 142 | lw k0, 0x14(sp) |
| 114 | mtc0 k0, CP0_CONFIG | 143 | mtc0 k0, CP0_CONFIG |
| 115 | 144 | ||
| 116 | /* We need to catch the ealry Alchemy SOCs with | 145 | /* We need to catch the early Alchemy SOCs with |
| 117 | * the write-only Config[OD] bit and set it back to one... | 146 | * the write-only Config[OD] bit and set it back to one... |
| 118 | */ | 147 | */ |
| 119 | jal au1x00_fixup_config_od | 148 | jal au1x00_fixup_config_od |
| 149 | nop | ||
| 120 | lw $1, PT_R1(sp) | 150 | lw $1, PT_R1(sp) |
| 121 | lw $2, PT_R2(sp) | 151 | lw $2, PT_R2(sp) |
| 122 | lw $3, PT_R3(sp) | 152 | lw $3, PT_R3(sp) |
| @@ -124,14 +154,6 @@ sdsleep: | |||
| 124 | lw $5, PT_R5(sp) | 154 | lw $5, PT_R5(sp) |
| 125 | lw $6, PT_R6(sp) | 155 | lw $6, PT_R6(sp) |
| 126 | lw $7, PT_R7(sp) | 156 | lw $7, PT_R7(sp) |
| 127 | lw $8, PT_R8(sp) | ||
| 128 | lw $9, PT_R9(sp) | ||
| 129 | lw $10, PT_R10(sp) | ||
| 130 | lw $11, PT_R11(sp) | ||
| 131 | lw $12, PT_R12(sp) | ||
| 132 | lw $13, PT_R13(sp) | ||
| 133 | lw $14, PT_R14(sp) | ||
| 134 | lw $15, PT_R15(sp) | ||
| 135 | lw $16, PT_R16(sp) | 157 | lw $16, PT_R16(sp) |
| 136 | lw $17, PT_R17(sp) | 158 | lw $17, PT_R17(sp) |
| 137 | lw $18, PT_R18(sp) | 159 | lw $18, PT_R18(sp) |
| @@ -140,15 +162,11 @@ sdsleep: | |||
| 140 | lw $21, PT_R21(sp) | 162 | lw $21, PT_R21(sp) |
| 141 | lw $22, PT_R22(sp) | 163 | lw $22, PT_R22(sp) |
| 142 | lw $23, PT_R23(sp) | 164 | lw $23, PT_R23(sp) |
| 143 | lw $24, PT_R24(sp) | ||
| 144 | lw $25, PT_R25(sp) | ||
| 145 | lw $26, PT_R26(sp) | 165 | lw $26, PT_R26(sp) |
| 146 | lw $27, PT_R27(sp) | 166 | lw $27, PT_R27(sp) |
| 147 | lw $28, PT_R28(sp) | 167 | lw $28, PT_R28(sp) |
| 148 | lw $29, PT_R29(sp) | ||
| 149 | lw $30, PT_R30(sp) | 168 | lw $30, PT_R30(sp) |
| 150 | lw $31, PT_R31(sp) | 169 | lw $31, PT_R31(sp) |
| 151 | addiu sp, PT_SIZE | ||
| 152 | |||
| 153 | jr ra | 170 | jr ra |
| 154 | END(save_and_sleep) | 171 | addiu sp, PT_SIZE |
| 172 | END(au1xxx_save_and_sleep) | ||
diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c index 563d9390a872..32880146cbc1 100644 --- a/arch/mips/alchemy/common/time.c +++ b/arch/mips/alchemy/common/time.c | |||
| @@ -1,5 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright (C) 2008 Manuel Lauss <mano@roarinelk.homelinux.net> | ||
| 2 | * | 3 | * |
| 4 | * Previous incarnations were: | ||
| 3 | * Copyright (C) 2001, 2006, 2008 MontaVista Software, <source@mvista.com> | 5 | * Copyright (C) 2001, 2006, 2008 MontaVista Software, <source@mvista.com> |
| 4 | * Copied and modified Carsten Langgaard's time.c | 6 | * Copied and modified Carsten Langgaard's time.c |
| 5 | * | 7 | * |
| @@ -23,244 +25,141 @@ | |||
| 23 | * | 25 | * |
| 24 | * ######################################################################## | 26 | * ######################################################################## |
| 25 | * | 27 | * |
| 26 | * Setting up the clock on the MIPS boards. | 28 | * Clocksource/event using the 32.768kHz-clocked Counter1 ('RTC' in the |
| 27 | * | 29 | * databooks). Firmware/Board init code must enable the counters in the |
| 28 | * We provide the clock interrupt processing and the timer offset compute | 30 | * counter control register, otherwise the CP0 counter clocksource/event |
| 29 | * functions. If CONFIG_PM is selected, we also ensure the 32KHz timer is | 31 | * will be installed instead (and use of 'wait' instruction is prohibited). |
| 30 | * available. -- Dan | ||
| 31 | */ | 32 | */ |
| 32 | 33 | ||
| 33 | #include <linux/types.h> | 34 | #include <linux/clockchips.h> |
| 34 | #include <linux/init.h> | 35 | #include <linux/clocksource.h> |
| 36 | #include <linux/interrupt.h> | ||
| 35 | #include <linux/spinlock.h> | 37 | #include <linux/spinlock.h> |
| 36 | 38 | ||
| 37 | #include <asm/mipsregs.h> | ||
| 38 | #include <asm/time.h> | 39 | #include <asm/time.h> |
| 39 | #include <asm/mach-au1x00/au1000.h> | 40 | #include <asm/mach-au1x00/au1000.h> |
| 40 | 41 | ||
| 41 | static int no_au1xxx_32khz; | 42 | /* 32kHz clock enabled and detected */ |
| 42 | extern int allow_au1k_wait; /* default off for CP0 Counter */ | 43 | #define CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S) |
| 43 | |||
| 44 | #ifdef CONFIG_PM | ||
| 45 | #if HZ < 100 || HZ > 1000 | ||
| 46 | #error "unsupported HZ value! Must be in [100,1000]" | ||
| 47 | #endif | ||
| 48 | #define MATCH20_INC (328 * 100 / HZ) /* magic number 328 is for HZ=100... */ | ||
| 49 | static unsigned long last_pc0, last_match20; | ||
| 50 | #endif | ||
| 51 | 44 | ||
| 52 | static DEFINE_SPINLOCK(time_lock); | 45 | extern int allow_au1k_wait; /* default off for CP0 Counter */ |
| 53 | |||
| 54 | unsigned long wtimer; | ||
| 55 | 46 | ||
| 56 | #ifdef CONFIG_PM | 47 | static cycle_t au1x_counter1_read(void) |
| 57 | static irqreturn_t counter0_irq(int irq, void *dev_id) | ||
| 58 | { | 48 | { |
| 59 | unsigned long pc0; | 49 | return au_readl(SYS_RTCREAD); |
| 60 | int time_elapsed; | ||
| 61 | static int jiffie_drift; | ||
| 62 | |||
| 63 | if (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20) { | ||
| 64 | /* should never happen! */ | ||
| 65 | printk(KERN_WARNING "counter 0 w status error\n"); | ||
| 66 | return IRQ_NONE; | ||
| 67 | } | ||
| 68 | |||
| 69 | pc0 = au_readl(SYS_TOYREAD); | ||
| 70 | if (pc0 < last_match20) | ||
| 71 | /* counter overflowed */ | ||
| 72 | time_elapsed = (0xffffffff - last_match20) + pc0; | ||
| 73 | else | ||
| 74 | time_elapsed = pc0 - last_match20; | ||
| 75 | |||
| 76 | while (time_elapsed > 0) { | ||
| 77 | do_timer(1); | ||
| 78 | #ifndef CONFIG_SMP | ||
| 79 | update_process_times(user_mode(get_irq_regs())); | ||
| 80 | #endif | ||
| 81 | time_elapsed -= MATCH20_INC; | ||
| 82 | last_match20 += MATCH20_INC; | ||
| 83 | jiffie_drift++; | ||
| 84 | } | ||
| 85 | |||
| 86 | last_pc0 = pc0; | ||
| 87 | au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2); | ||
| 88 | au_sync(); | ||
| 89 | |||
| 90 | /* | ||
| 91 | * Our counter ticks at 10.009765625 ms/tick, we we're running | ||
| 92 | * almost 10 uS too slow per tick. | ||
| 93 | */ | ||
| 94 | |||
| 95 | if (jiffie_drift >= 999) { | ||
| 96 | jiffie_drift -= 999; | ||
| 97 | do_timer(1); /* increment jiffies by one */ | ||
| 98 | #ifndef CONFIG_SMP | ||
| 99 | update_process_times(user_mode(get_irq_regs())); | ||
| 100 | #endif | ||
| 101 | } | ||
| 102 | |||
| 103 | return IRQ_HANDLED; | ||
| 104 | } | 50 | } |
| 105 | 51 | ||
| 106 | struct irqaction counter0_action = { | 52 | static struct clocksource au1x_counter1_clocksource = { |
| 107 | .handler = counter0_irq, | 53 | .name = "alchemy-counter1", |
| 108 | .flags = IRQF_DISABLED, | 54 | .read = au1x_counter1_read, |
| 109 | .name = "alchemy-toy", | 55 | .mask = CLOCKSOURCE_MASK(32), |
| 110 | .dev_id = NULL, | 56 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
| 57 | .rating = 100, | ||
| 111 | }; | 58 | }; |
| 112 | 59 | ||
| 113 | /* When we wakeup from sleep, we have to "catch up" on all of the | 60 | static int au1x_rtcmatch2_set_next_event(unsigned long delta, |
| 114 | * timer ticks we have missed. | 61 | struct clock_event_device *cd) |
| 115 | */ | ||
| 116 | void wakeup_counter0_adjust(void) | ||
| 117 | { | 62 | { |
| 118 | unsigned long pc0; | 63 | delta += au_readl(SYS_RTCREAD); |
| 119 | int time_elapsed; | 64 | /* wait for register access */ |
| 120 | 65 | while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M21) | |
| 121 | pc0 = au_readl(SYS_TOYREAD); | 66 | ; |
| 122 | if (pc0 < last_match20) | 67 | au_writel(delta, SYS_RTCMATCH2); |
| 123 | /* counter overflowed */ | ||
| 124 | time_elapsed = (0xffffffff - last_match20) + pc0; | ||
| 125 | else | ||
| 126 | time_elapsed = pc0 - last_match20; | ||
| 127 | |||
| 128 | while (time_elapsed > 0) { | ||
| 129 | time_elapsed -= MATCH20_INC; | ||
| 130 | last_match20 += MATCH20_INC; | ||
| 131 | } | ||
| 132 | |||
| 133 | last_pc0 = pc0; | ||
| 134 | au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2); | ||
| 135 | au_sync(); | 68 | au_sync(); |
| 136 | 69 | ||
| 70 | return 0; | ||
| 137 | } | 71 | } |
| 138 | 72 | ||
| 139 | /* This is just for debugging to set the timer for a sleep delay. */ | 73 | static void au1x_rtcmatch2_set_mode(enum clock_event_mode mode, |
| 140 | void wakeup_counter0_set(int ticks) | 74 | struct clock_event_device *cd) |
| 141 | { | 75 | { |
| 142 | unsigned long pc0; | ||
| 143 | |||
| 144 | pc0 = au_readl(SYS_TOYREAD); | ||
| 145 | last_pc0 = pc0; | ||
| 146 | au_writel(last_match20 + (MATCH20_INC * ticks), SYS_TOYMATCH2); | ||
| 147 | au_sync(); | ||
| 148 | } | 76 | } |
| 149 | #endif | ||
| 150 | 77 | ||
| 151 | /* | 78 | static irqreturn_t au1x_rtcmatch2_irq(int irq, void *dev_id) |
| 152 | * I haven't found anyone that doesn't use a 12 MHz source clock, | ||
| 153 | * but just in case..... | ||
| 154 | */ | ||
| 155 | #define AU1000_SRC_CLK 12000000 | ||
| 156 | |||
| 157 | /* | ||
| 158 | * We read the real processor speed from the PLL. This is important | ||
| 159 | * because it is more accurate than computing it from the 32 KHz | ||
| 160 | * counter, if it exists. If we don't have an accurate processor | ||
| 161 | * speed, all of the peripherals that derive their clocks based on | ||
| 162 | * this advertised speed will introduce error and sometimes not work | ||
| 163 | * properly. This function is futher convoluted to still allow configurations | ||
| 164 | * to do that in case they have really, really old silicon with a | ||
| 165 | * write-only PLL register, that we need the 32 KHz when power management | ||
| 166 | * "wait" is enabled, and we need to detect if the 32 KHz isn't present | ||
| 167 | * but requested......got it? :-) -- Dan | ||
| 168 | */ | ||
| 169 | unsigned long calc_clock(void) | ||
| 170 | { | 79 | { |
| 171 | unsigned long cpu_speed; | 80 | struct clock_event_device *cd = dev_id; |
| 172 | unsigned long flags; | 81 | cd->event_handler(cd); |
| 173 | unsigned long counter; | 82 | return IRQ_HANDLED; |
| 174 | 83 | } | |
| 175 | spin_lock_irqsave(&time_lock, flags); | ||
| 176 | |||
| 177 | /* Power management cares if we don't have a 32 KHz counter. */ | ||
| 178 | no_au1xxx_32khz = 0; | ||
| 179 | counter = au_readl(SYS_COUNTER_CNTRL); | ||
| 180 | if (counter & SYS_CNTRL_E0) { | ||
| 181 | int trim_divide = 16; | ||
| 182 | |||
| 183 | au_writel(counter | SYS_CNTRL_EN1, SYS_COUNTER_CNTRL); | ||
| 184 | |||
| 185 | while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S); | ||
| 186 | /* RTC now ticks at 32.768/16 kHz */ | ||
| 187 | au_writel(trim_divide - 1, SYS_RTCTRIM); | ||
| 188 | while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S); | ||
| 189 | 84 | ||
| 190 | while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S); | 85 | static struct clock_event_device au1x_rtcmatch2_clockdev = { |
| 191 | au_writel(0, SYS_TOYWRITE); | 86 | .name = "rtcmatch2", |
| 192 | while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S); | 87 | .features = CLOCK_EVT_FEAT_ONESHOT, |
| 193 | } else | 88 | .rating = 100, |
| 194 | no_au1xxx_32khz = 1; | 89 | .irq = AU1000_RTC_MATCH2_INT, |
| 90 | .set_next_event = au1x_rtcmatch2_set_next_event, | ||
| 91 | .set_mode = au1x_rtcmatch2_set_mode, | ||
| 92 | .cpumask = CPU_MASK_ALL, | ||
| 93 | }; | ||
| 195 | 94 | ||
| 196 | /* | 95 | static struct irqaction au1x_rtcmatch2_irqaction = { |
| 197 | * On early Au1000, sys_cpupll was write-only. Since these | 96 | .handler = au1x_rtcmatch2_irq, |
| 198 | * silicon versions of Au1000 are not sold by AMD, we don't bend | 97 | .flags = IRQF_DISABLED | IRQF_TIMER, |
| 199 | * over backwards trying to determine the frequency. | 98 | .name = "timer", |
| 200 | */ | 99 | .dev_id = &au1x_rtcmatch2_clockdev, |
| 201 | if (cur_cpu_spec[0]->cpu_pll_wo) | 100 | }; |
| 202 | #ifdef CONFIG_SOC_AU1000_FREQUENCY | ||
| 203 | cpu_speed = CONFIG_SOC_AU1000_FREQUENCY; | ||
| 204 | #else | ||
| 205 | cpu_speed = 396000000; | ||
| 206 | #endif | ||
| 207 | else | ||
| 208 | cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK; | ||
| 209 | /* On Alchemy CPU:counter ratio is 1:1 */ | ||
| 210 | mips_hpt_frequency = cpu_speed; | ||
| 211 | /* Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16) */ | ||
| 212 | set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL) | ||
| 213 | & 0x03) + 2) * 16)); | ||
| 214 | spin_unlock_irqrestore(&time_lock, flags); | ||
| 215 | return cpu_speed; | ||
| 216 | } | ||
| 217 | 101 | ||
| 218 | void __init plat_time_init(void) | 102 | void __init plat_time_init(void) |
| 219 | { | 103 | { |
| 220 | unsigned int est_freq = calc_clock(); | 104 | struct clock_event_device *cd = &au1x_rtcmatch2_clockdev; |
| 221 | 105 | unsigned long t; | |
| 222 | est_freq += 5000; /* round */ | 106 | |
| 223 | est_freq -= est_freq%10000; | 107 | /* Check if firmware (YAMON, ...) has enabled 32kHz and clock |
| 224 | printk(KERN_INFO "CPU frequency %u.%02u MHz\n", | 108 | * has been detected. If so install the rtcmatch2 clocksource, |
| 225 | est_freq / 1000000, ((est_freq % 1000000) * 100) / 1000000); | 109 | * otherwise don't bother. Note that both bits being set is by |
| 226 | set_au1x00_speed(est_freq); | 110 | * no means a definite guarantee that the counters actually work |
| 227 | set_au1x00_lcd_clock(); /* program the LCD clock */ | 111 | * (the 32S bit seems to be stuck set to 1 once a single clock- |
| 112 | * edge is detected, hence the timeouts). | ||
| 113 | */ | ||
| 114 | if (CNTR_OK != (au_readl(SYS_COUNTER_CNTRL) & CNTR_OK)) | ||
| 115 | goto cntr_err; | ||
| 228 | 116 | ||
| 229 | #ifdef CONFIG_PM | ||
| 230 | /* | 117 | /* |
| 231 | * setup counter 0, since it keeps ticking after a | 118 | * setup counter 1 (RTC) to tick at full speed |
| 232 | * 'wait' instruction has been executed. The CP0 timer and | ||
| 233 | * counter 1 do NOT continue running after 'wait' | ||
| 234 | * | ||
| 235 | * It's too early to call request_irq() here, so we handle | ||
| 236 | * counter 0 interrupt as a special irq and it doesn't show | ||
| 237 | * up under /proc/interrupts. | ||
| 238 | * | ||
| 239 | * Check to ensure we really have a 32 KHz oscillator before | ||
| 240 | * we do this. | ||
| 241 | */ | 119 | */ |
| 242 | if (no_au1xxx_32khz) | 120 | t = 0xffffff; |
| 243 | printk(KERN_WARNING "WARNING: no 32KHz clock found.\n"); | 121 | while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S) && t--) |
| 244 | else { | 122 | asm volatile ("nop"); |
| 245 | while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S); | 123 | if (!t) |
| 246 | au_writel(0, SYS_TOYWRITE); | 124 | goto cntr_err; |
| 247 | while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S); | ||
| 248 | |||
| 249 | au_writel(au_readl(SYS_WAKEMSK) | (1 << 8), SYS_WAKEMSK); | ||
| 250 | au_writel(~0, SYS_WAKESRC); | ||
| 251 | au_sync(); | ||
| 252 | while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20); | ||
| 253 | 125 | ||
| 254 | /* Setup match20 to interrupt once every HZ */ | 126 | au_writel(0, SYS_RTCTRIM); /* 32.768 kHz */ |
| 255 | last_pc0 = last_match20 = au_readl(SYS_TOYREAD); | 127 | au_sync(); |
| 256 | au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2); | ||
| 257 | au_sync(); | ||
| 258 | while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20); | ||
| 259 | setup_irq(AU1000_TOY_MATCH2_INT, &counter0_action); | ||
| 260 | 128 | ||
| 261 | /* We can use the real 'wait' instruction. */ | 129 | t = 0xffffff; |
| 262 | allow_au1k_wait = 1; | 130 | while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S) && t--) |
| 263 | } | 131 | asm volatile ("nop"); |
| 132 | if (!t) | ||
| 133 | goto cntr_err; | ||
| 134 | au_writel(0, SYS_RTCWRITE); | ||
| 135 | au_sync(); | ||
| 264 | 136 | ||
| 265 | #endif | 137 | t = 0xffffff; |
| 138 | while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S) && t--) | ||
| 139 | asm volatile ("nop"); | ||
| 140 | if (!t) | ||
| 141 | goto cntr_err; | ||
| 142 | |||
| 143 | /* register counter1 clocksource and event device */ | ||
| 144 | clocksource_set_clock(&au1x_counter1_clocksource, 32768); | ||
| 145 | clocksource_register(&au1x_counter1_clocksource); | ||
| 146 | |||
| 147 | cd->shift = 32; | ||
| 148 | cd->mult = div_sc(32768, NSEC_PER_SEC, cd->shift); | ||
| 149 | cd->max_delta_ns = clockevent_delta2ns(0xffffffff, cd); | ||
| 150 | cd->min_delta_ns = clockevent_delta2ns(8, cd); /* ~0.25ms */ | ||
| 151 | clockevents_register_device(cd); | ||
| 152 | setup_irq(AU1000_RTC_MATCH2_INT, &au1x_rtcmatch2_irqaction); | ||
| 153 | |||
| 154 | printk(KERN_INFO "Alchemy clocksource installed\n"); | ||
| 155 | |||
| 156 | /* can now use 'wait' */ | ||
| 157 | allow_au1k_wait = 1; | ||
| 158 | return; | ||
| 159 | |||
| 160 | cntr_err: | ||
| 161 | /* counters unusable, use C0 counter */ | ||
| 162 | r4k_clockevent_init(); | ||
| 163 | init_r4k_clocksource(); | ||
| 164 | allow_au1k_wait = 0; | ||
| 266 | } | 165 | } |
diff --git a/arch/mips/alchemy/db1x00/init.c b/arch/mips/alchemy/db1x00/init.c deleted file mode 100644 index 847413514964..000000000000 --- a/arch/mips/alchemy/db1x00/init.c +++ /dev/null | |||
| @@ -1,62 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * BRIEF MODULE DESCRIPTION | ||
| 3 | * PB1000 board setup | ||
| 4 | * | ||
| 5 | * Copyright 2001, 2008 MontaVista Software Inc. | ||
| 6 | * Author: MontaVista Software, Inc. <source@mvista.com> | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify it | ||
| 9 | * under the terms of the GNU General Public License as published by the | ||
| 10 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 11 | * option) any later version. | ||
| 12 | * | ||
| 13 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 14 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 15 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 16 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 17 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 18 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 19 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 20 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 21 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 22 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License along | ||
| 25 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 26 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 27 | */ | ||
| 28 | |||
| 29 | #include <linux/init.h> | ||
| 30 | #include <linux/kernel.h> | ||
| 31 | |||
| 32 | #include <asm/bootinfo.h> | ||
| 33 | |||
| 34 | #include <prom.h> | ||
| 35 | |||
| 36 | const char *get_system_type(void) | ||
| 37 | { | ||
| 38 | #ifdef CONFIG_MIPS_BOSPORUS | ||
| 39 | return "Alchemy Bosporus Gateway Reference"; | ||
| 40 | #else | ||
| 41 | return "Alchemy Db1x00"; | ||
| 42 | #endif | ||
| 43 | } | ||
| 44 | |||
| 45 | void __init prom_init(void) | ||
| 46 | { | ||
| 47 | unsigned char *memsize_str; | ||
| 48 | unsigned long memsize; | ||
| 49 | |||
| 50 | prom_argc = fw_arg0; | ||
| 51 | prom_argv = (char **)fw_arg1; | ||
| 52 | prom_envp = (char **)fw_arg2; | ||
| 53 | |||
| 54 | prom_init_cmdline(); | ||
| 55 | |||
| 56 | memsize_str = prom_getenv("memsize"); | ||
| 57 | if (!memsize_str) | ||
| 58 | memsize = 0x04000000; | ||
| 59 | else | ||
| 60 | strict_strtol(memsize_str, 0, &memsize); | ||
| 61 | add_memory_region(0, memsize, BOOT_MEM_RAM); | ||
| 62 | } | ||
diff --git a/arch/mips/alchemy/devboards/Makefile b/arch/mips/alchemy/devboards/Makefile new file mode 100644 index 000000000000..730f9f2b30e8 --- /dev/null +++ b/arch/mips/alchemy/devboards/Makefile | |||
| @@ -0,0 +1,18 @@ | |||
| 1 | # | ||
| 2 | # Alchemy Develboards | ||
| 3 | # | ||
| 4 | |||
| 5 | obj-y += prom.o | ||
| 6 | obj-$(CONFIG_PM) += pm.o | ||
| 7 | obj-$(CONFIG_MIPS_PB1000) += pb1000/ | ||
| 8 | obj-$(CONFIG_MIPS_PB1100) += pb1100/ | ||
| 9 | obj-$(CONFIG_MIPS_PB1200) += pb1200/ | ||
| 10 | obj-$(CONFIG_MIPS_PB1500) += pb1500/ | ||
| 11 | obj-$(CONFIG_MIPS_PB1550) += pb1550/ | ||
| 12 | obj-$(CONFIG_MIPS_DB1000) += db1x00/ | ||
| 13 | obj-$(CONFIG_MIPS_DB1100) += db1x00/ | ||
| 14 | obj-$(CONFIG_MIPS_DB1200) += pb1200/ | ||
| 15 | obj-$(CONFIG_MIPS_DB1500) += db1x00/ | ||
| 16 | obj-$(CONFIG_MIPS_DB1550) += db1x00/ | ||
| 17 | obj-$(CONFIG_MIPS_BOSPORUS) += db1x00/ | ||
| 18 | obj-$(CONFIG_MIPS_MIRAGE) += db1x00/ | ||
diff --git a/arch/mips/alchemy/db1x00/Makefile b/arch/mips/alchemy/devboards/db1x00/Makefile index 274db3b55d82..432241ab8677 100644 --- a/arch/mips/alchemy/db1x00/Makefile +++ b/arch/mips/alchemy/devboards/db1x00/Makefile | |||
| @@ -5,4 +5,4 @@ | |||
| 5 | # Makefile for the Alchemy Semiconductor DBAu1xx0 boards. | 5 | # Makefile for the Alchemy Semiconductor DBAu1xx0 boards. |
| 6 | # | 6 | # |
| 7 | 7 | ||
| 8 | lib-y := init.o board_setup.o irqmap.o | 8 | obj-y := board_setup.o irqmap.o |
diff --git a/arch/mips/alchemy/db1x00/board_setup.c b/arch/mips/alchemy/devboards/db1x00/board_setup.c index 9e5ccbbfcedd..a75ffbf99f25 100644 --- a/arch/mips/alchemy/db1x00/board_setup.c +++ b/arch/mips/alchemy/devboards/db1x00/board_setup.c | |||
| @@ -32,8 +32,20 @@ | |||
| 32 | #include <asm/mach-au1x00/au1000.h> | 32 | #include <asm/mach-au1x00/au1000.h> |
| 33 | #include <asm/mach-db1x00/db1x00.h> | 33 | #include <asm/mach-db1x00/db1x00.h> |
| 34 | 34 | ||
| 35 | #include <prom.h> | ||
| 36 | |||
| 37 | |||
| 35 | static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; | 38 | static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; |
| 36 | 39 | ||
| 40 | const char *get_system_type(void) | ||
| 41 | { | ||
| 42 | #ifdef CONFIG_MIPS_BOSPORUS | ||
| 43 | return "Alchemy Bosporus Gateway Reference"; | ||
| 44 | #else | ||
| 45 | return "Alchemy Db1x00"; | ||
| 46 | #endif | ||
| 47 | } | ||
| 48 | |||
| 37 | void board_reset(void) | 49 | void board_reset(void) |
| 38 | { | 50 | { |
| 39 | /* Hit BCSR.SW_RESET[RESET] */ | 51 | /* Hit BCSR.SW_RESET[RESET] */ |
| @@ -43,6 +55,31 @@ void board_reset(void) | |||
| 43 | void __init board_setup(void) | 55 | void __init board_setup(void) |
| 44 | { | 56 | { |
| 45 | u32 pin_func = 0; | 57 | u32 pin_func = 0; |
| 58 | char *argptr; | ||
| 59 | |||
| 60 | argptr = prom_getcmdline(); | ||
| 61 | #ifdef CONFIG_SERIAL_8250_CONSOLE | ||
| 62 | argptr = strstr(argptr, "console="); | ||
| 63 | if (argptr == NULL) { | ||
| 64 | argptr = prom_getcmdline(); | ||
| 65 | strcat(argptr, " console=ttyS0,115200"); | ||
| 66 | } | ||
| 67 | #endif | ||
| 68 | |||
| 69 | #ifdef CONFIG_FB_AU1100 | ||
| 70 | argptr = strstr(argptr, "video="); | ||
| 71 | if (argptr == NULL) { | ||
| 72 | argptr = prom_getcmdline(); | ||
| 73 | /* default panel */ | ||
| 74 | /*strcat(argptr, " video=au1100fb:panel:Sharp_320x240_16");*/ | ||
| 75 | } | ||
| 76 | #endif | ||
| 77 | |||
| 78 | #if defined(CONFIG_SOUND_AU1X00) && !defined(CONFIG_SOC_AU1000) | ||
| 79 | /* au1000 does not support vra, au1500 and au1100 do */ | ||
| 80 | strcat(argptr, " au1000_audio=vra"); | ||
| 81 | argptr = prom_getcmdline(); | ||
| 82 | #endif | ||
| 46 | 83 | ||
| 47 | /* Not valid for Au1550 */ | 84 | /* Not valid for Au1550 */ |
| 48 | #if defined(CONFIG_IRDA) && \ | 85 | #if defined(CONFIG_IRDA) && \ |
diff --git a/arch/mips/alchemy/db1x00/irqmap.c b/arch/mips/alchemy/devboards/db1x00/irqmap.c index 94c090e8bf7a..0b09025087c6 100644 --- a/arch/mips/alchemy/db1x00/irqmap.c +++ b/arch/mips/alchemy/devboards/db1x00/irqmap.c | |||
| @@ -27,6 +27,7 @@ | |||
| 27 | */ | 27 | */ |
| 28 | 28 | ||
| 29 | #include <linux/init.h> | 29 | #include <linux/init.h> |
| 30 | #include <linux/interrupt.h> | ||
| 30 | 31 | ||
| 31 | #include <asm/mach-au1x00/au1000.h> | 32 | #include <asm/mach-au1x00/au1000.h> |
| 32 | 33 | ||
| @@ -66,21 +67,24 @@ struct au1xxx_irqmap __initdata au1xxx_irq_map[] = { | |||
| 66 | 67 | ||
| 67 | #ifndef CONFIG_MIPS_MIRAGE | 68 | #ifndef CONFIG_MIPS_MIRAGE |
| 68 | #ifdef CONFIG_MIPS_DB1550 | 69 | #ifdef CONFIG_MIPS_DB1550 |
| 69 | { AU1000_GPIO_3, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card 0 IRQ# */ | 70 | { AU1000_GPIO_3, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 0 IRQ# */ |
| 70 | { AU1000_GPIO_5, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card 1 IRQ# */ | 71 | { AU1000_GPIO_5, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 1 IRQ# */ |
| 71 | #else | 72 | #else |
| 72 | { AU1000_GPIO_0, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card 0 Fully_Interted# */ | 73 | { AU1000_GPIO_0, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 0 Fully_Interted# */ |
| 73 | { AU1000_GPIO_1, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card 0 STSCHG# */ | 74 | { AU1000_GPIO_1, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 0 STSCHG# */ |
| 74 | { AU1000_GPIO_2, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card 0 IRQ# */ | 75 | { AU1000_GPIO_2, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 0 IRQ# */ |
| 75 | 76 | ||
| 76 | { AU1000_GPIO_3, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card 1 Fully_Interted# */ | 77 | { AU1000_GPIO_3, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 1 Fully_Interted# */ |
| 77 | { AU1000_GPIO_4, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card 1 STSCHG# */ | 78 | { AU1000_GPIO_4, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 1 STSCHG# */ |
| 78 | { AU1000_GPIO_5, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card 1 IRQ# */ | 79 | { AU1000_GPIO_5, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 1 IRQ# */ |
| 79 | #endif | 80 | #endif |
| 80 | #else | 81 | #else |
| 81 | { AU1000_GPIO_7, INTC_INT_RISE_EDGE, 0 }, /* touchscreen pen down */ | 82 | { AU1000_GPIO_7, IRQF_TRIGGER_RISING, 0 }, /* touchscreen pen down */ |
| 82 | #endif | 83 | #endif |
| 83 | 84 | ||
| 84 | }; | 85 | }; |
| 85 | 86 | ||
| 86 | int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map); | 87 | void __init board_init_irq(void) |
| 88 | { | ||
| 89 | au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map)); | ||
| 90 | } | ||
diff --git a/arch/mips/alchemy/pb1000/Makefile b/arch/mips/alchemy/devboards/pb1000/Makefile index 99bbec0ca41b..97c6615ba2bb 100644 --- a/arch/mips/alchemy/pb1000/Makefile +++ b/arch/mips/alchemy/devboards/pb1000/Makefile | |||
| @@ -5,4 +5,4 @@ | |||
| 5 | # Makefile for the Alchemy Semiconductor Pb1000 board. | 5 | # Makefile for the Alchemy Semiconductor Pb1000 board. |
| 6 | # | 6 | # |
| 7 | 7 | ||
| 8 | lib-y := init.o board_setup.o irqmap.o | 8 | obj-y := board_setup.o |
diff --git a/arch/mips/alchemy/pb1000/board_setup.c b/arch/mips/alchemy/devboards/pb1000/board_setup.c index 25df167a95b3..aed2fdecc709 100644 --- a/arch/mips/alchemy/pb1000/board_setup.c +++ b/arch/mips/alchemy/devboards/pb1000/board_setup.c | |||
| @@ -23,22 +23,48 @@ | |||
| 23 | * 675 Mass Ave, Cambridge, MA 02139, USA. | 23 | * 675 Mass Ave, Cambridge, MA 02139, USA. |
| 24 | */ | 24 | */ |
| 25 | 25 | ||
| 26 | #include <linux/init.h> | ||
| 27 | #include <linux/delay.h> | 26 | #include <linux/delay.h> |
| 28 | 27 | #include <linux/init.h> | |
| 28 | #include <linux/interrupt.h> | ||
| 29 | #include <asm/mach-au1x00/au1000.h> | 29 | #include <asm/mach-au1x00/au1000.h> |
| 30 | #include <asm/mach-pb1x00/pb1000.h> | 30 | #include <asm/mach-pb1x00/pb1000.h> |
| 31 | #include <prom.h> | ||
| 32 | |||
| 33 | |||
| 34 | struct au1xxx_irqmap __initdata au1xxx_irq_map[] = { | ||
| 35 | { AU1000_GPIO_15, IRQF_TRIGGER_LOW, 0 }, | ||
| 36 | }; | ||
| 37 | |||
| 38 | |||
| 39 | const char *get_system_type(void) | ||
| 40 | { | ||
| 41 | return "Alchemy Pb1000"; | ||
| 42 | } | ||
| 31 | 43 | ||
| 32 | void board_reset(void) | 44 | void board_reset(void) |
| 33 | { | 45 | { |
| 34 | } | 46 | } |
| 35 | 47 | ||
| 48 | void __init board_init_irq(void) | ||
| 49 | { | ||
| 50 | au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map)); | ||
| 51 | } | ||
| 52 | |||
| 36 | void __init board_setup(void) | 53 | void __init board_setup(void) |
| 37 | { | 54 | { |
| 38 | u32 pin_func, static_cfg0; | 55 | u32 pin_func, static_cfg0; |
| 39 | u32 sys_freqctrl, sys_clksrc; | 56 | u32 sys_freqctrl, sys_clksrc; |
| 40 | u32 prid = read_c0_prid(); | 57 | u32 prid = read_c0_prid(); |
| 41 | 58 | ||
| 59 | #ifdef CONFIG_SERIAL_8250_CONSOLE | ||
| 60 | char *argptr = prom_getcmdline(); | ||
| 61 | argptr = strstr(argptr, "console="); | ||
| 62 | if (argptr == NULL) { | ||
| 63 | argptr = prom_getcmdline(); | ||
| 64 | strcat(argptr, " console=ttyS0,115200"); | ||
| 65 | } | ||
| 66 | #endif | ||
| 67 | |||
| 42 | /* Set AUX clock to 12 MHz * 8 = 96 MHz */ | 68 | /* Set AUX clock to 12 MHz * 8 = 96 MHz */ |
| 43 | au_writel(8, SYS_AUXPLL); | 69 | au_writel(8, SYS_AUXPLL); |
| 44 | au_writel(0, SYS_PINSTATERD); | 70 | au_writel(0, SYS_PINSTATERD); |
diff --git a/arch/mips/alchemy/pb1100/Makefile b/arch/mips/alchemy/devboards/pb1100/Makefile index 793e97c49e46..c586dd7e91dc 100644 --- a/arch/mips/alchemy/pb1100/Makefile +++ b/arch/mips/alchemy/devboards/pb1100/Makefile | |||
| @@ -5,4 +5,4 @@ | |||
| 5 | # Makefile for the Alchemy Semiconductor Pb1100 board. | 5 | # Makefile for the Alchemy Semiconductor Pb1100 board. |
| 6 | # | 6 | # |
| 7 | 7 | ||
| 8 | lib-y := init.o board_setup.o irqmap.o | 8 | obj-y := board_setup.o |
diff --git a/arch/mips/alchemy/pb1100/board_setup.c b/arch/mips/alchemy/devboards/pb1100/board_setup.c index c0bfd59a7a36..4df57fae15d4 100644 --- a/arch/mips/alchemy/pb1100/board_setup.c +++ b/arch/mips/alchemy/devboards/pb1100/board_setup.c | |||
| @@ -25,19 +25,66 @@ | |||
| 25 | 25 | ||
| 26 | #include <linux/init.h> | 26 | #include <linux/init.h> |
| 27 | #include <linux/delay.h> | 27 | #include <linux/delay.h> |
| 28 | #include <linux/interrupt.h> | ||
| 28 | 29 | ||
| 29 | #include <asm/mach-au1x00/au1000.h> | 30 | #include <asm/mach-au1x00/au1000.h> |
| 30 | #include <asm/mach-pb1x00/pb1100.h> | 31 | #include <asm/mach-pb1x00/pb1100.h> |
| 31 | 32 | ||
| 33 | #include <prom.h> | ||
| 34 | |||
| 35 | |||
| 36 | struct au1xxx_irqmap __initdata au1xxx_irq_map[] = { | ||
| 37 | { AU1000_GPIO_9, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card Fully_Inserted# */ | ||
| 38 | { AU1000_GPIO_10, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card STSCHG# */ | ||
| 39 | { AU1000_GPIO_11, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card IRQ# */ | ||
| 40 | { AU1000_GPIO_13, IRQF_TRIGGER_LOW, 0 }, /* DC_IRQ# */ | ||
| 41 | }; | ||
| 42 | |||
| 43 | |||
| 44 | const char *get_system_type(void) | ||
| 45 | { | ||
| 46 | return "Alchemy Pb1100"; | ||
| 47 | } | ||
| 48 | |||
| 32 | void board_reset(void) | 49 | void board_reset(void) |
| 33 | { | 50 | { |
| 34 | /* Hit BCSR.RST_VDDI[SOFT_RESET] */ | 51 | /* Hit BCSR.RST_VDDI[SOFT_RESET] */ |
| 35 | au_writel(0x00000000, PB1100_RST_VDDI); | 52 | au_writel(0x00000000, PB1100_RST_VDDI); |
| 36 | } | 53 | } |
| 37 | 54 | ||
| 55 | void __init board_init_irq(void) | ||
| 56 | { | ||
| 57 | au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map)); | ||
| 58 | } | ||
| 59 | |||
| 38 | void __init board_setup(void) | 60 | void __init board_setup(void) |
| 39 | { | 61 | { |
| 40 | volatile void __iomem *base = (volatile void __iomem *)0xac000000UL; | 62 | volatile void __iomem *base = (volatile void __iomem *)0xac000000UL; |
| 63 | char *argptr; | ||
| 64 | |||
| 65 | argptr = prom_getcmdline(); | ||
| 66 | #ifdef CONFIG_SERIAL_8250_CONSOLE | ||
| 67 | argptr = strstr(argptr, "console="); | ||
| 68 | if (argptr == NULL) { | ||
| 69 | argptr = prom_getcmdline(); | ||
| 70 | strcat(argptr, " console=ttyS0,115200"); | ||
| 71 | } | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifdef CONFIG_FB_AU1100 | ||
| 75 | argptr = strstr(argptr, "video="); | ||
| 76 | if (argptr == NULL) { | ||
| 77 | argptr = prom_getcmdline(); | ||
| 78 | /* default panel */ | ||
| 79 | /*strcat(argptr, " video=au1100fb:panel:Sharp_320x240_16");*/ | ||
| 80 | } | ||
| 81 | #endif | ||
| 82 | |||
| 83 | #if defined(CONFIG_SOUND_AU1X00) && !defined(CONFIG_SOC_AU1000) | ||
| 84 | /* au1000 does not support vra, au1500 and au1100 do */ | ||
| 85 | strcat(argptr, " au1000_audio=vra"); | ||
| 86 | argptr = prom_getcmdline(); | ||
| 87 | #endif | ||
| 41 | 88 | ||
| 42 | /* Set AUX clock to 12 MHz * 8 = 96 MHz */ | 89 | /* Set AUX clock to 12 MHz * 8 = 96 MHz */ |
| 43 | au_writel(8, SYS_AUXPLL); | 90 | au_writel(8, SYS_AUXPLL); |
diff --git a/arch/mips/alchemy/pb1200/Makefile b/arch/mips/alchemy/devboards/pb1200/Makefile index d678adf7ce85..c8c3a99fb68a 100644 --- a/arch/mips/alchemy/pb1200/Makefile +++ b/arch/mips/alchemy/devboards/pb1200/Makefile | |||
| @@ -2,7 +2,6 @@ | |||
| 2 | # Makefile for the Alchemy Semiconductor Pb1200/DBAu1200 boards. | 2 | # Makefile for the Alchemy Semiconductor Pb1200/DBAu1200 boards. |
| 3 | # | 3 | # |
| 4 | 4 | ||
| 5 | lib-y := init.o board_setup.o irqmap.o | 5 | obj-y := board_setup.o irqmap.o platform.o |
| 6 | obj-y += platform.o | ||
| 7 | 6 | ||
| 8 | EXTRA_CFLAGS += -Werror | 7 | EXTRA_CFLAGS += -Werror |
diff --git a/arch/mips/alchemy/pb1200/board_setup.c b/arch/mips/alchemy/devboards/pb1200/board_setup.c index 6cb2115059ad..94e6b7e7753d 100644 --- a/arch/mips/alchemy/pb1200/board_setup.c +++ b/arch/mips/alchemy/devboards/pb1200/board_setup.c | |||
| @@ -30,8 +30,11 @@ | |||
| 30 | #include <prom.h> | 30 | #include <prom.h> |
| 31 | #include <au1xxx.h> | 31 | #include <au1xxx.h> |
| 32 | 32 | ||
| 33 | extern void _board_init_irq(void); | 33 | |
| 34 | extern void (*board_init_irq)(void); | 34 | const char *get_system_type(void) |
| 35 | { | ||
| 36 | return "Alchemy Pb1200"; | ||
| 37 | } | ||
| 35 | 38 | ||
| 36 | void board_reset(void) | 39 | void board_reset(void) |
| 37 | { | 40 | { |
| @@ -41,7 +44,19 @@ void board_reset(void) | |||
| 41 | 44 | ||
| 42 | void __init board_setup(void) | 45 | void __init board_setup(void) |
| 43 | { | 46 | { |
| 44 | char *argptr = NULL; | 47 | char *argptr; |
| 48 | |||
| 49 | argptr = prom_getcmdline(); | ||
| 50 | #ifdef CONFIG_SERIAL_8250_CONSOLE | ||
| 51 | argptr = strstr(argptr, "console="); | ||
| 52 | if (argptr == NULL) { | ||
| 53 | argptr = prom_getcmdline(); | ||
| 54 | strcat(argptr, " console=ttyS0,115200"); | ||
| 55 | } | ||
| 56 | #endif | ||
| 57 | #ifdef CONFIG_FB_AU1200 | ||
| 58 | strcat(argptr, " video=au1200fb:panel:bs"); | ||
| 59 | #endif | ||
| 45 | 60 | ||
| 46 | #if 0 | 61 | #if 0 |
| 47 | { | 62 | { |
| @@ -99,16 +114,6 @@ void __init board_setup(void) | |||
| 99 | } | 114 | } |
| 100 | #endif | 115 | #endif |
| 101 | 116 | ||
| 102 | #ifdef CONFIG_FB_AU1200 | ||
| 103 | argptr = prom_getcmdline(); | ||
| 104 | #ifdef CONFIG_MIPS_PB1200 | ||
| 105 | strcat(argptr, " video=au1200fb:panel:bs"); | ||
| 106 | #endif | ||
| 107 | #ifdef CONFIG_MIPS_DB1200 | ||
| 108 | strcat(argptr, " video=au1200fb:panel:bs"); | ||
| 109 | #endif | ||
| 110 | #endif | ||
| 111 | |||
| 112 | /* | 117 | /* |
| 113 | * The Pb1200 development board uses external MUX for PSC0 to | 118 | * The Pb1200 development board uses external MUX for PSC0 to |
| 114 | * support SMB/SPI. bcsr->resets bit 12: 0=SMB 1=SPI | 119 | * support SMB/SPI. bcsr->resets bit 12: 0=SMB 1=SPI |
| @@ -124,9 +129,6 @@ void __init board_setup(void) | |||
| 124 | #ifdef CONFIG_MIPS_DB1200 | 129 | #ifdef CONFIG_MIPS_DB1200 |
| 125 | printk(KERN_INFO "AMD Alchemy Db1200 Board\n"); | 130 | printk(KERN_INFO "AMD Alchemy Db1200 Board\n"); |
| 126 | #endif | 131 | #endif |
| 127 | |||
| 128 | /* Setup Pb1200 External Interrupt Controller */ | ||
| 129 | board_init_irq = _board_init_irq; | ||
| 130 | } | 132 | } |
| 131 | 133 | ||
| 132 | int board_au1200fb_panel(void) | 134 | int board_au1200fb_panel(void) |
diff --git a/arch/mips/alchemy/pb1200/irqmap.c b/arch/mips/alchemy/devboards/pb1200/irqmap.c index 2a505ad8715b..fe47498da280 100644 --- a/arch/mips/alchemy/pb1200/irqmap.c +++ b/arch/mips/alchemy/devboards/pb1200/irqmap.c | |||
| @@ -40,91 +40,65 @@ | |||
| 40 | 40 | ||
| 41 | struct au1xxx_irqmap __initdata au1xxx_irq_map[] = { | 41 | struct au1xxx_irqmap __initdata au1xxx_irq_map[] = { |
| 42 | /* This is external interrupt cascade */ | 42 | /* This is external interrupt cascade */ |
| 43 | { AU1000_GPIO_7, INTC_INT_LOW_LEVEL, 0 }, | 43 | { AU1000_GPIO_7, IRQF_TRIGGER_LOW, 0 }, |
| 44 | }; | 44 | }; |
| 45 | 45 | ||
| 46 | int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map); | ||
| 47 | 46 | ||
| 48 | /* | 47 | /* |
| 49 | * Support for External interrupts on the Pb1200 Development platform. | 48 | * Support for External interrupts on the Pb1200 Development platform. |
| 50 | */ | 49 | */ |
| 51 | static volatile int pb1200_cascade_en; | ||
| 52 | 50 | ||
| 53 | irqreturn_t pb1200_cascade_handler(int irq, void *dev_id) | 51 | static void pb1200_cascade_handler(unsigned int irq, struct irq_desc *d) |
| 54 | { | 52 | { |
| 55 | unsigned short bisr = bcsr->int_status; | 53 | unsigned short bisr = bcsr->int_status; |
| 56 | int extirq_nr = 0; | ||
| 57 | |||
| 58 | /* Clear all the edge interrupts. This has no effect on level. */ | ||
| 59 | bcsr->int_status = bisr; | ||
| 60 | for ( ; bisr; bisr &= bisr - 1) { | ||
| 61 | extirq_nr = PB1200_INT_BEGIN + __ffs(bisr); | ||
| 62 | /* Ack and dispatch IRQ */ | ||
| 63 | do_IRQ(extirq_nr); | ||
| 64 | } | ||
| 65 | |||
| 66 | return IRQ_RETVAL(1); | ||
| 67 | } | ||
| 68 | 54 | ||
| 69 | inline void pb1200_enable_irq(unsigned int irq_nr) | 55 | for ( ; bisr; bisr &= bisr - 1) |
| 70 | { | 56 | generic_handle_irq(PB1200_INT_BEGIN + __ffs(bisr)); |
| 71 | bcsr->intset_mask = 1 << (irq_nr - PB1200_INT_BEGIN); | ||
| 72 | bcsr->intset = 1 << (irq_nr - PB1200_INT_BEGIN); | ||
| 73 | } | 57 | } |
| 74 | 58 | ||
| 75 | inline void pb1200_disable_irq(unsigned int irq_nr) | 59 | /* NOTE: both the enable and mask bits must be cleared, otherwise the |
| 60 | * CPLD generates tons of spurious interrupts (at least on the DB1200). | ||
| 61 | */ | ||
| 62 | static void pb1200_mask_irq(unsigned int irq_nr) | ||
| 76 | { | 63 | { |
| 77 | bcsr->intclr_mask = 1 << (irq_nr - PB1200_INT_BEGIN); | 64 | bcsr->intclr_mask = 1 << (irq_nr - PB1200_INT_BEGIN); |
| 78 | bcsr->intclr = 1 << (irq_nr - PB1200_INT_BEGIN); | 65 | bcsr->intclr = 1 << (irq_nr - PB1200_INT_BEGIN); |
| 66 | au_sync(); | ||
| 79 | } | 67 | } |
| 80 | 68 | ||
| 81 | static unsigned int pb1200_setup_cascade(void) | 69 | static void pb1200_maskack_irq(unsigned int irq_nr) |
| 82 | { | ||
| 83 | return request_irq(AU1000_GPIO_7, &pb1200_cascade_handler, | ||
| 84 | 0, "Pb1200 Cascade", &pb1200_cascade_handler); | ||
| 85 | } | ||
| 86 | |||
| 87 | static unsigned int pb1200_startup_irq(unsigned int irq) | ||
| 88 | { | 70 | { |
| 89 | if (++pb1200_cascade_en == 1) { | 71 | bcsr->intclr_mask = 1 << (irq_nr - PB1200_INT_BEGIN); |
| 90 | int res; | 72 | bcsr->intclr = 1 << (irq_nr - PB1200_INT_BEGIN); |
| 91 | 73 | bcsr->int_status = 1 << (irq_nr - PB1200_INT_BEGIN); /* ack */ | |
| 92 | res = pb1200_setup_cascade(); | 74 | au_sync(); |
| 93 | if (res) | ||
| 94 | return res; | ||
| 95 | } | ||
| 96 | |||
| 97 | pb1200_enable_irq(irq); | ||
| 98 | |||
| 99 | return 0; | ||
| 100 | } | 75 | } |
| 101 | 76 | ||
| 102 | static void pb1200_shutdown_irq(unsigned int irq) | 77 | static void pb1200_unmask_irq(unsigned int irq_nr) |
| 103 | { | 78 | { |
| 104 | pb1200_disable_irq(irq); | 79 | bcsr->intset = 1 << (irq_nr - PB1200_INT_BEGIN); |
| 105 | if (--pb1200_cascade_en == 0) | 80 | bcsr->intset_mask = 1 << (irq_nr - PB1200_INT_BEGIN); |
| 106 | free_irq(AU1000_GPIO_7, &pb1200_cascade_handler); | 81 | au_sync(); |
| 107 | } | 82 | } |
| 108 | 83 | ||
| 109 | static struct irq_chip external_irq_type = { | 84 | static struct irq_chip pb1200_cpld_irq_type = { |
| 110 | #ifdef CONFIG_MIPS_PB1200 | 85 | #ifdef CONFIG_MIPS_PB1200 |
| 111 | .name = "Pb1200 Ext", | 86 | .name = "Pb1200 Ext", |
| 112 | #endif | 87 | #endif |
| 113 | #ifdef CONFIG_MIPS_DB1200 | 88 | #ifdef CONFIG_MIPS_DB1200 |
| 114 | .name = "Db1200 Ext", | 89 | .name = "Db1200 Ext", |
| 115 | #endif | 90 | #endif |
| 116 | .startup = pb1200_startup_irq, | 91 | .mask = pb1200_mask_irq, |
| 117 | .shutdown = pb1200_shutdown_irq, | 92 | .mask_ack = pb1200_maskack_irq, |
| 118 | .ack = pb1200_disable_irq, | 93 | .unmask = pb1200_unmask_irq, |
| 119 | .mask = pb1200_disable_irq, | ||
| 120 | .mask_ack = pb1200_disable_irq, | ||
| 121 | .unmask = pb1200_enable_irq, | ||
| 122 | }; | 94 | }; |
| 123 | 95 | ||
| 124 | void _board_init_irq(void) | 96 | void __init board_init_irq(void) |
| 125 | { | 97 | { |
| 126 | unsigned int irq; | 98 | unsigned int irq; |
| 127 | 99 | ||
| 100 | au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map)); | ||
| 101 | |||
| 128 | #ifdef CONFIG_MIPS_PB1200 | 102 | #ifdef CONFIG_MIPS_PB1200 |
| 129 | /* We have a problem with CPLD rev 3. */ | 103 | /* We have a problem with CPLD rev 3. */ |
| 130 | if (((bcsr->whoami & BCSR_WHOAMI_CPLD) >> 4) <= 3) { | 104 | if (((bcsr->whoami & BCSR_WHOAMI_CPLD) >> 4) <= 3) { |
| @@ -146,15 +120,15 @@ void _board_init_irq(void) | |||
| 146 | panic("Game over. Your score is 0."); | 120 | panic("Game over. Your score is 0."); |
| 147 | } | 121 | } |
| 148 | #endif | 122 | #endif |
| 123 | /* mask & disable & ack all */ | ||
| 124 | bcsr->intclr_mask = 0xffff; | ||
| 125 | bcsr->intclr = 0xffff; | ||
| 126 | bcsr->int_status = 0xffff; | ||
| 127 | au_sync(); | ||
| 149 | 128 | ||
| 150 | for (irq = PB1200_INT_BEGIN; irq <= PB1200_INT_END; irq++) { | 129 | for (irq = PB1200_INT_BEGIN; irq <= PB1200_INT_END; irq++) |
| 151 | set_irq_chip_and_handler(irq, &external_irq_type, | 130 | set_irq_chip_and_handler_name(irq, &pb1200_cpld_irq_type, |
| 152 | handle_level_irq); | 131 | handle_level_irq, "level"); |
| 153 | pb1200_disable_irq(irq); | ||
| 154 | } | ||
| 155 | 132 | ||
| 156 | /* | 133 | set_irq_chained_handler(AU1000_GPIO_7, pb1200_cascade_handler); |
| 157 | * GPIO_7 can not be hooked here, so it is hooked upon first | ||
| 158 | * request of any source attached to the cascade. | ||
| 159 | */ | ||
| 160 | } | 134 | } |
diff --git a/arch/mips/alchemy/pb1200/platform.c b/arch/mips/alchemy/devboards/pb1200/platform.c index 95303297c534..95303297c534 100644 --- a/arch/mips/alchemy/pb1200/platform.c +++ b/arch/mips/alchemy/devboards/pb1200/platform.c | |||
diff --git a/arch/mips/alchemy/pb1500/Makefile b/arch/mips/alchemy/devboards/pb1500/Makefile index 602f38df20bb..173b419a7479 100644 --- a/arch/mips/alchemy/pb1500/Makefile +++ b/arch/mips/alchemy/devboards/pb1500/Makefile | |||
| @@ -5,4 +5,4 @@ | |||
| 5 | # Makefile for the Alchemy Semiconductor Pb1500 board. | 5 | # Makefile for the Alchemy Semiconductor Pb1500 board. |
| 6 | # | 6 | # |
| 7 | 7 | ||
| 8 | lib-y := init.o board_setup.o irqmap.o | 8 | obj-y := board_setup.o |
diff --git a/arch/mips/alchemy/pb1500/board_setup.c b/arch/mips/alchemy/devboards/pb1500/board_setup.c index 035771c6e5b8..fed3b093156a 100644 --- a/arch/mips/alchemy/pb1500/board_setup.c +++ b/arch/mips/alchemy/devboards/pb1500/board_setup.c | |||
| @@ -25,20 +25,64 @@ | |||
| 25 | 25 | ||
| 26 | #include <linux/init.h> | 26 | #include <linux/init.h> |
| 27 | #include <linux/delay.h> | 27 | #include <linux/delay.h> |
| 28 | #include <linux/interrupt.h> | ||
| 28 | 29 | ||
| 29 | #include <asm/mach-au1x00/au1000.h> | 30 | #include <asm/mach-au1x00/au1000.h> |
| 30 | #include <asm/mach-pb1x00/pb1500.h> | 31 | #include <asm/mach-pb1x00/pb1500.h> |
| 31 | 32 | ||
| 33 | #include <prom.h> | ||
| 34 | |||
| 35 | |||
| 36 | char irq_tab_alchemy[][5] __initdata = { | ||
| 37 | [12] = { -1, INTA, INTX, INTX, INTX }, /* IDSEL 12 - HPT370 */ | ||
| 38 | [13] = { -1, INTA, INTB, INTC, INTD }, /* IDSEL 13 - PCI slot */ | ||
| 39 | }; | ||
| 40 | |||
| 41 | struct au1xxx_irqmap __initdata au1xxx_irq_map[] = { | ||
| 42 | { AU1500_GPIO_204, IRQF_TRIGGER_HIGH, 0 }, | ||
| 43 | { AU1500_GPIO_201, IRQF_TRIGGER_LOW, 0 }, | ||
| 44 | { AU1500_GPIO_202, IRQF_TRIGGER_LOW, 0 }, | ||
| 45 | { AU1500_GPIO_203, IRQF_TRIGGER_LOW, 0 }, | ||
| 46 | { AU1500_GPIO_205, IRQF_TRIGGER_LOW, 0 }, | ||
| 47 | }; | ||
| 48 | |||
| 49 | |||
| 50 | const char *get_system_type(void) | ||
| 51 | { | ||
| 52 | return "Alchemy Pb1500"; | ||
| 53 | } | ||
| 54 | |||
| 32 | void board_reset(void) | 55 | void board_reset(void) |
| 33 | { | 56 | { |
| 34 | /* Hit BCSR.RST_VDDI[SOFT_RESET] */ | 57 | /* Hit BCSR.RST_VDDI[SOFT_RESET] */ |
| 35 | au_writel(0x00000000, PB1500_RST_VDDI); | 58 | au_writel(0x00000000, PB1500_RST_VDDI); |
| 36 | } | 59 | } |
| 37 | 60 | ||
| 61 | void __init board_init_irq(void) | ||
| 62 | { | ||
| 63 | au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map)); | ||
| 64 | } | ||
| 65 | |||
| 38 | void __init board_setup(void) | 66 | void __init board_setup(void) |
| 39 | { | 67 | { |
| 40 | u32 pin_func; | 68 | u32 pin_func; |
| 41 | u32 sys_freqctrl, sys_clksrc; | 69 | u32 sys_freqctrl, sys_clksrc; |
| 70 | char *argptr; | ||
| 71 | |||
| 72 | argptr = prom_getcmdline(); | ||
| 73 | #ifdef CONFIG_SERIAL_8250_CONSOLE | ||
| 74 | argptr = strstr(argptr, "console="); | ||
| 75 | if (argptr == NULL) { | ||
| 76 | argptr = prom_getcmdline(); | ||
| 77 | strcat(argptr, " console=ttyS0,115200"); | ||
| 78 | } | ||
| 79 | #endif | ||
| 80 | |||
| 81 | #if defined(CONFIG_SOUND_AU1X00) && !defined(CONFIG_SOC_AU1000) | ||
| 82 | /* au1000 does not support vra, au1500 and au1100 do */ | ||
| 83 | strcat(argptr, " au1000_audio=vra"); | ||
| 84 | argptr = prom_getcmdline(); | ||
| 85 | #endif | ||
| 42 | 86 | ||
| 43 | sys_clksrc = sys_freqctrl = pin_func = 0; | 87 | sys_clksrc = sys_freqctrl = pin_func = 0; |
| 44 | /* Set AUX clock to 12 MHz * 8 = 96 MHz */ | 88 | /* Set AUX clock to 12 MHz * 8 = 96 MHz */ |
diff --git a/arch/mips/alchemy/pb1550/Makefile b/arch/mips/alchemy/devboards/pb1550/Makefile index 7d8beca87fa5..cff95bcdb2ca 100644 --- a/arch/mips/alchemy/pb1550/Makefile +++ b/arch/mips/alchemy/devboards/pb1550/Makefile | |||
| @@ -5,4 +5,4 @@ | |||
| 5 | # Makefile for the Alchemy Semiconductor Pb1550 board. | 5 | # Makefile for the Alchemy Semiconductor Pb1550 board. |
| 6 | # | 6 | # |
| 7 | 7 | ||
| 8 | lib-y := init.o board_setup.o irqmap.o | 8 | obj-y := board_setup.o |
diff --git a/arch/mips/alchemy/pb1550/board_setup.c b/arch/mips/alchemy/devboards/pb1550/board_setup.c index 0ed76b64b6ab..b6e9e7d247a3 100644 --- a/arch/mips/alchemy/pb1550/board_setup.c +++ b/arch/mips/alchemy/devboards/pb1550/board_setup.c | |||
| @@ -28,20 +28,54 @@ | |||
| 28 | */ | 28 | */ |
| 29 | 29 | ||
| 30 | #include <linux/init.h> | 30 | #include <linux/init.h> |
| 31 | #include <linux/interrupt.h> | ||
| 31 | 32 | ||
| 32 | #include <asm/mach-au1x00/au1000.h> | 33 | #include <asm/mach-au1x00/au1000.h> |
| 33 | #include <asm/mach-pb1x00/pb1550.h> | 34 | #include <asm/mach-pb1x00/pb1550.h> |
| 34 | 35 | ||
| 36 | #include <prom.h> | ||
| 37 | |||
| 38 | |||
| 39 | char irq_tab_alchemy[][5] __initdata = { | ||
| 40 | [12] = { -1, INTB, INTC, INTD, INTA }, /* IDSEL 12 - PCI slot 2 (left) */ | ||
| 41 | [13] = { -1, INTA, INTB, INTC, INTD }, /* IDSEL 13 - PCI slot 1 (right) */ | ||
| 42 | }; | ||
| 43 | |||
| 44 | struct au1xxx_irqmap __initdata au1xxx_irq_map[] = { | ||
| 45 | { AU1000_GPIO_0, IRQF_TRIGGER_LOW, 0 }, | ||
| 46 | { AU1000_GPIO_1, IRQF_TRIGGER_LOW, 0 }, | ||
| 47 | }; | ||
| 48 | |||
| 49 | const char *get_system_type(void) | ||
| 50 | { | ||
| 51 | return "Alchemy Pb1550"; | ||
| 52 | } | ||
| 53 | |||
| 35 | void board_reset(void) | 54 | void board_reset(void) |
| 36 | { | 55 | { |
| 37 | /* Hit BCSR.SYSTEM[RESET] */ | 56 | /* Hit BCSR.SYSTEM[RESET] */ |
| 38 | au_writew(au_readw(0xAF00001C) & ~BCSR_SYSTEM_RESET, 0xAF00001C); | 57 | au_writew(au_readw(0xAF00001C) & ~BCSR_SYSTEM_RESET, 0xAF00001C); |
| 39 | } | 58 | } |
| 40 | 59 | ||
| 60 | void __init board_init_irq(void) | ||
| 61 | { | ||
| 62 | au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map)); | ||
| 63 | } | ||
| 64 | |||
| 41 | void __init board_setup(void) | 65 | void __init board_setup(void) |
| 42 | { | 66 | { |
| 43 | u32 pin_func; | 67 | u32 pin_func; |
| 44 | 68 | ||
| 69 | #ifdef CONFIG_SERIAL_8250_CONSOLE | ||
| 70 | char *argptr; | ||
| 71 | argptr = prom_getcmdline(); | ||
| 72 | argptr = strstr(argptr, "console="); | ||
| 73 | if (argptr == NULL) { | ||
| 74 | argptr = prom_getcmdline(); | ||
| 75 | strcat(argptr, " console=ttyS0,115200"); | ||
| 76 | } | ||
| 77 | #endif | ||
| 78 | |||
| 45 | /* | 79 | /* |
| 46 | * Enable PSC1 SYNC for AC'97. Normaly done in audio driver, | 80 | * Enable PSC1 SYNC for AC'97. Normaly done in audio driver, |
| 47 | * but it is board specific code, so put it here. | 81 | * but it is board specific code, so put it here. |
diff --git a/arch/mips/alchemy/devboards/pm.c b/arch/mips/alchemy/devboards/pm.c new file mode 100644 index 000000000000..d5eb9c325ed0 --- /dev/null +++ b/arch/mips/alchemy/devboards/pm.c | |||
| @@ -0,0 +1,229 @@ | |||
| 1 | /* | ||
| 2 | * Alchemy Development Board example suspend userspace interface. | ||
| 3 | * | ||
| 4 | * (c) 2008 Manuel Lauss <mano@roarinelk.homelinux.net> | ||
| 5 | */ | ||
| 6 | |||
| 7 | #include <linux/init.h> | ||
| 8 | #include <linux/kobject.h> | ||
| 9 | #include <linux/suspend.h> | ||
| 10 | #include <linux/sysfs.h> | ||
| 11 | #include <asm/mach-au1x00/au1000.h> | ||
| 12 | |||
| 13 | /* | ||
| 14 | * Generic suspend userspace interface for Alchemy development boards. | ||
| 15 | * This code exports a few sysfs nodes under /sys/power/db1x/ which | ||
| 16 | * can be used by userspace to en/disable all au1x-provided wakeup | ||
| 17 | * sources and configure the timeout after which the the TOYMATCH2 irq | ||
| 18 | * is to trigger a wakeup. | ||
| 19 | */ | ||
| 20 | |||
| 21 | |||
| 22 | static unsigned long db1x_pm_sleep_secs; | ||
| 23 | static unsigned long db1x_pm_wakemsk; | ||
| 24 | static unsigned long db1x_pm_last_wakesrc; | ||
| 25 | |||
| 26 | static int db1x_pm_enter(suspend_state_t state) | ||
| 27 | { | ||
| 28 | /* enable GPIO based wakeup */ | ||
| 29 | au_writel(1, SYS_PININPUTEN); | ||
| 30 | |||
| 31 | /* clear and setup wake cause and source */ | ||
| 32 | au_writel(0, SYS_WAKEMSK); | ||
| 33 | au_sync(); | ||
| 34 | au_writel(0, SYS_WAKESRC); | ||
| 35 | au_sync(); | ||
| 36 | |||
| 37 | au_writel(db1x_pm_wakemsk, SYS_WAKEMSK); | ||
| 38 | au_sync(); | ||
| 39 | |||
| 40 | /* setup 1Hz-timer-based wakeup: wait for reg access */ | ||
| 41 | while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20) | ||
| 42 | asm volatile ("nop"); | ||
| 43 | |||
| 44 | au_writel(au_readl(SYS_TOYREAD) + db1x_pm_sleep_secs, SYS_TOYMATCH2); | ||
| 45 | au_sync(); | ||
| 46 | |||
| 47 | /* wait for value to really hit the register */ | ||
| 48 | while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20) | ||
| 49 | asm volatile ("nop"); | ||
| 50 | |||
| 51 | /* ...and now the sandman can come! */ | ||
| 52 | au_sleep(); | ||
| 53 | |||
| 54 | return 0; | ||
| 55 | } | ||
| 56 | |||
| 57 | static int db1x_pm_begin(suspend_state_t state) | ||
| 58 | { | ||
| 59 | if (!db1x_pm_wakemsk) { | ||
| 60 | printk(KERN_ERR "db1x: no wakeup source activated!\n"); | ||
| 61 | return -EINVAL; | ||
| 62 | } | ||
| 63 | |||
| 64 | return 0; | ||
| 65 | } | ||
| 66 | |||
| 67 | static void db1x_pm_end(void) | ||
| 68 | { | ||
| 69 | /* read and store wakeup source, the clear the register. To | ||
| 70 | * be able to clear it, WAKEMSK must be cleared first. | ||
| 71 | */ | ||
| 72 | db1x_pm_last_wakesrc = au_readl(SYS_WAKESRC); | ||
| 73 | |||
| 74 | au_writel(0, SYS_WAKEMSK); | ||
| 75 | au_writel(0, SYS_WAKESRC); | ||
| 76 | au_sync(); | ||
| 77 | |||
| 78 | } | ||
| 79 | |||
| 80 | static struct platform_suspend_ops db1x_pm_ops = { | ||
| 81 | .valid = suspend_valid_only_mem, | ||
| 82 | .begin = db1x_pm_begin, | ||
| 83 | .enter = db1x_pm_enter, | ||
| 84 | .end = db1x_pm_end, | ||
| 85 | }; | ||
| 86 | |||
| 87 | #define ATTRCMP(x) (0 == strcmp(attr->attr.name, #x)) | ||
| 88 | |||
| 89 | static ssize_t db1x_pmattr_show(struct kobject *kobj, | ||
| 90 | struct kobj_attribute *attr, | ||
| 91 | char *buf) | ||
| 92 | { | ||
| 93 | int idx; | ||
| 94 | |||
| 95 | if (ATTRCMP(timer_timeout)) | ||
| 96 | return sprintf(buf, "%lu\n", db1x_pm_sleep_secs); | ||
| 97 | |||
| 98 | else if (ATTRCMP(timer)) | ||
| 99 | return sprintf(buf, "%u\n", | ||
| 100 | !!(db1x_pm_wakemsk & SYS_WAKEMSK_M2)); | ||
| 101 | |||
| 102 | else if (ATTRCMP(wakesrc)) | ||
| 103 | return sprintf(buf, "%lu\n", db1x_pm_last_wakesrc); | ||
| 104 | |||
| 105 | else if (ATTRCMP(gpio0) || ATTRCMP(gpio1) || ATTRCMP(gpio2) || | ||
| 106 | ATTRCMP(gpio3) || ATTRCMP(gpio4) || ATTRCMP(gpio5) || | ||
| 107 | ATTRCMP(gpio6) || ATTRCMP(gpio7)) { | ||
| 108 | idx = (attr->attr.name)[4] - '0'; | ||
| 109 | return sprintf(buf, "%d\n", | ||
| 110 | !!(db1x_pm_wakemsk & SYS_WAKEMSK_GPIO(idx))); | ||
| 111 | |||
| 112 | } else if (ATTRCMP(wakemsk)) { | ||
| 113 | return sprintf(buf, "%08lx\n", db1x_pm_wakemsk); | ||
| 114 | } | ||
| 115 | |||
| 116 | return -ENOENT; | ||
| 117 | } | ||
| 118 | |||
| 119 | static ssize_t db1x_pmattr_store(struct kobject *kobj, | ||
| 120 | struct kobj_attribute *attr, | ||
| 121 | const char *instr, | ||
| 122 | size_t bytes) | ||
| 123 | { | ||
| 124 | unsigned long l; | ||
| 125 | int tmp; | ||
| 126 | |||
| 127 | if (ATTRCMP(timer_timeout)) { | ||
| 128 | tmp = strict_strtoul(instr, 0, &l); | ||
| 129 | if (tmp) | ||
| 130 | return tmp; | ||
| 131 | |||
| 132 | db1x_pm_sleep_secs = l; | ||
| 133 | |||
| 134 | } else if (ATTRCMP(timer)) { | ||
| 135 | if (instr[0] != '0') | ||
| 136 | db1x_pm_wakemsk |= SYS_WAKEMSK_M2; | ||
| 137 | else | ||
| 138 | db1x_pm_wakemsk &= ~SYS_WAKEMSK_M2; | ||
| 139 | |||
| 140 | } else if (ATTRCMP(gpio0) || ATTRCMP(gpio1) || ATTRCMP(gpio2) || | ||
| 141 | ATTRCMP(gpio3) || ATTRCMP(gpio4) || ATTRCMP(gpio5) || | ||
| 142 | ATTRCMP(gpio6) || ATTRCMP(gpio7)) { | ||
| 143 | tmp = (attr->attr.name)[4] - '0'; | ||
| 144 | if (instr[0] != '0') { | ||
| 145 | db1x_pm_wakemsk |= SYS_WAKEMSK_GPIO(tmp); | ||
| 146 | } else { | ||
| 147 | db1x_pm_wakemsk &= ~SYS_WAKEMSK_GPIO(tmp); | ||
| 148 | } | ||
| 149 | |||
| 150 | } else if (ATTRCMP(wakemsk)) { | ||
| 151 | tmp = strict_strtoul(instr, 0, &l); | ||
| 152 | if (tmp) | ||
| 153 | return tmp; | ||
| 154 | |||
| 155 | db1x_pm_wakemsk = l & 0x0000003f; | ||
| 156 | |||
| 157 | } else | ||
| 158 | bytes = -ENOENT; | ||
| 159 | |||
| 160 | return bytes; | ||
| 161 | } | ||
| 162 | |||
| 163 | #define ATTR(x) \ | ||
| 164 | static struct kobj_attribute x##_attribute = \ | ||
| 165 | __ATTR(x, 0664, db1x_pmattr_show, \ | ||
| 166 | db1x_pmattr_store); | ||
| 167 | |||
| 168 | ATTR(gpio0) /* GPIO-based wakeup enable */ | ||
| 169 | ATTR(gpio1) | ||
| 170 | ATTR(gpio2) | ||
| 171 | ATTR(gpio3) | ||
| 172 | ATTR(gpio4) | ||
| 173 | ATTR(gpio5) | ||
| 174 | ATTR(gpio6) | ||
| 175 | ATTR(gpio7) | ||
| 176 | ATTR(timer) /* TOYMATCH2-based wakeup enable */ | ||
| 177 | ATTR(timer_timeout) /* timer-based wakeup timeout value, in seconds */ | ||
| 178 | ATTR(wakesrc) /* contents of SYS_WAKESRC after last wakeup */ | ||
| 179 | ATTR(wakemsk) /* direct access to SYS_WAKEMSK */ | ||
| 180 | |||
| 181 | #define ATTR_LIST(x) & x ## _attribute.attr | ||
| 182 | static struct attribute *db1x_pmattrs[] = { | ||
| 183 | ATTR_LIST(gpio0), | ||
| 184 | ATTR_LIST(gpio1), | ||
| 185 | ATTR_LIST(gpio2), | ||
| 186 | ATTR_LIST(gpio3), | ||
| 187 | ATTR_LIST(gpio4), | ||
| 188 | ATTR_LIST(gpio5), | ||
| 189 | ATTR_LIST(gpio6), | ||
| 190 | ATTR_LIST(gpio7), | ||
| 191 | ATTR_LIST(timer), | ||
| 192 | ATTR_LIST(timer_timeout), | ||
| 193 | ATTR_LIST(wakesrc), | ||
| 194 | ATTR_LIST(wakemsk), | ||
| 195 | NULL, /* terminator */ | ||
| 196 | }; | ||
| 197 | |||
| 198 | static struct attribute_group db1x_pmattr_group = { | ||
| 199 | .name = "db1x", | ||
| 200 | .attrs = db1x_pmattrs, | ||
| 201 | }; | ||
| 202 | |||
| 203 | /* | ||
| 204 | * Initialize suspend interface | ||
| 205 | */ | ||
| 206 | static int __init pm_init(void) | ||
| 207 | { | ||
| 208 | /* init TOY to tick at 1Hz if not already done. No need to wait | ||
| 209 | * for confirmation since there's plenty of time from here to | ||
| 210 | * the next suspend cycle. | ||
| 211 | */ | ||
| 212 | if (au_readl(SYS_TOYTRIM) != 32767) { | ||
| 213 | au_writel(32767, SYS_TOYTRIM); | ||
| 214 | au_sync(); | ||
| 215 | } | ||
| 216 | |||
| 217 | db1x_pm_last_wakesrc = au_readl(SYS_WAKESRC); | ||
| 218 | |||
| 219 | au_writel(0, SYS_WAKESRC); | ||
| 220 | au_sync(); | ||
| 221 | au_writel(0, SYS_WAKEMSK); | ||
| 222 | au_sync(); | ||
| 223 | |||
| 224 | suspend_set_ops(&db1x_pm_ops); | ||
| 225 | |||
| 226 | return sysfs_create_group(power_kobj, &db1x_pmattr_group); | ||
| 227 | } | ||
| 228 | |||
| 229 | late_initcall(pm_init); | ||
diff --git a/arch/mips/alchemy/pb1550/init.c b/arch/mips/alchemy/devboards/prom.c index e1055a13a1a0..0042bd6b1d7d 100644 --- a/arch/mips/alchemy/pb1550/init.c +++ b/arch/mips/alchemy/devboards/prom.c | |||
| @@ -1,9 +1,9 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Common code used by all Alchemy develboards. | ||
| 2 | * | 3 | * |
| 3 | * BRIEF MODULE DESCRIPTION | 4 | * Extracted from files which had this to say: |
| 4 | * Pb1550 board setup | ||
| 5 | * | 5 | * |
| 6 | * Copyright 2001, 2008 MontaVista Software Inc. | 6 | * Copyright 2000, 2008 MontaVista Software Inc. |
| 7 | * Author: MontaVista Software, Inc. <source@mvista.com> | 7 | * Author: MontaVista Software, Inc. <source@mvista.com> |
| 8 | * | 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify it | 9 | * This program is free software; you can redistribute it and/or modify it |
| @@ -29,15 +29,19 @@ | |||
| 29 | 29 | ||
| 30 | #include <linux/init.h> | 30 | #include <linux/init.h> |
| 31 | #include <linux/kernel.h> | 31 | #include <linux/kernel.h> |
| 32 | |||
| 33 | #include <asm/bootinfo.h> | 32 | #include <asm/bootinfo.h> |
| 34 | 33 | #include <asm/mach-au1x00/au1000.h> | |
| 35 | #include <prom.h> | 34 | #include <prom.h> |
| 36 | 35 | ||
| 37 | const char *get_system_type(void) | 36 | #if defined(CONFIG_MIPS_PB1000) || defined(CONFIG_MIPS_DB1000) || \ |
| 38 | { | 37 | defined(CONFIG_MIPS_PB1100) || defined(CONFIG_MIPS_DB1100) || \ |
| 39 | return "Alchemy Pb1550"; | 38 | defined(CONFIG_MIPS_PB1500) || defined(CONFIG_MIPS_DB1500) || \ |
| 40 | } | 39 | defined(CONFIG_MIPS_BOSPORUS) || defined(CONFIG_MIPS_MIRAGE) |
| 40 | #define ALCHEMY_BOARD_DEFAULT_MEMSIZE 0x04000000 | ||
| 41 | |||
| 42 | #else /* Au1550/Au1200-based develboards */ | ||
| 43 | #define ALCHEMY_BOARD_DEFAULT_MEMSIZE 0x08000000 | ||
| 44 | #endif | ||
| 41 | 45 | ||
| 42 | void __init prom_init(void) | 46 | void __init prom_init(void) |
| 43 | { | 47 | { |
| @@ -51,8 +55,8 @@ void __init prom_init(void) | |||
| 51 | prom_init_cmdline(); | 55 | prom_init_cmdline(); |
| 52 | memsize_str = prom_getenv("memsize"); | 56 | memsize_str = prom_getenv("memsize"); |
| 53 | if (!memsize_str) | 57 | if (!memsize_str) |
| 54 | memsize = 0x08000000; | 58 | memsize = ALCHEMY_BOARD_DEFAULT_MEMSIZE; |
| 55 | else | 59 | else |
| 56 | strict_strtol(memsize_str, 0, &memsize); | 60 | strict_strtoul(memsize_str, 0, &memsize); |
| 57 | add_memory_region(0, memsize, BOOT_MEM_RAM); | 61 | add_memory_region(0, memsize, BOOT_MEM_RAM); |
| 58 | } | 62 | } |
diff --git a/arch/mips/alchemy/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c index 3f8079186cf2..8ed1ae12bc55 100644 --- a/arch/mips/alchemy/mtx-1/board_setup.c +++ b/arch/mips/alchemy/mtx-1/board_setup.c | |||
| @@ -32,6 +32,8 @@ | |||
| 32 | 32 | ||
| 33 | #include <asm/mach-au1x00/au1000.h> | 33 | #include <asm/mach-au1x00/au1000.h> |
| 34 | 34 | ||
| 35 | #include <prom.h> | ||
| 36 | |||
| 35 | extern int (*board_pci_idsel)(unsigned int devsel, int assert); | 37 | extern int (*board_pci_idsel)(unsigned int devsel, int assert); |
| 36 | int mtx1_pci_idsel(unsigned int devsel, int assert); | 38 | int mtx1_pci_idsel(unsigned int devsel, int assert); |
| 37 | 39 | ||
| @@ -43,6 +45,16 @@ void board_reset(void) | |||
| 43 | 45 | ||
| 44 | void __init board_setup(void) | 46 | void __init board_setup(void) |
| 45 | { | 47 | { |
| 48 | #ifdef CONFIG_SERIAL_8250_CONSOLE | ||
| 49 | char *argptr; | ||
| 50 | argptr = prom_getcmdline(); | ||
| 51 | argptr = strstr(argptr, "console="); | ||
| 52 | if (argptr == NULL) { | ||
| 53 | argptr = prom_getcmdline(); | ||
| 54 | strcat(argptr, " console=ttyS0,115200"); | ||
| 55 | } | ||
| 56 | #endif | ||
| 57 | |||
| 46 | #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) | 58 | #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) |
| 47 | /* Enable USB power switch */ | 59 | /* Enable USB power switch */ |
| 48 | au_writel(au_readl(GPIO2_DIR) | 0x10, GPIO2_DIR); | 60 | au_writel(au_readl(GPIO2_DIR) | 0x10, GPIO2_DIR); |
diff --git a/arch/mips/alchemy/mtx-1/init.c b/arch/mips/alchemy/mtx-1/init.c index 3bae13c28954..5e871c8d9e96 100644 --- a/arch/mips/alchemy/mtx-1/init.c +++ b/arch/mips/alchemy/mtx-1/init.c | |||
| @@ -55,6 +55,6 @@ void __init prom_init(void) | |||
| 55 | if (!memsize_str) | 55 | if (!memsize_str) |
| 56 | memsize = 0x04000000; | 56 | memsize = 0x04000000; |
| 57 | else | 57 | else |
| 58 | strict_strtol(memsize_str, 0, &memsize); | 58 | strict_strtoul(memsize_str, 0, &memsize); |
| 59 | add_memory_region(0, memsize, BOOT_MEM_RAM); | 59 | add_memory_region(0, memsize, BOOT_MEM_RAM); |
| 60 | } | 60 | } |
diff --git a/arch/mips/alchemy/mtx-1/irqmap.c b/arch/mips/alchemy/mtx-1/irqmap.c index f2bf02951e9c..f1ab12ab3433 100644 --- a/arch/mips/alchemy/mtx-1/irqmap.c +++ b/arch/mips/alchemy/mtx-1/irqmap.c | |||
| @@ -27,7 +27,7 @@ | |||
| 27 | */ | 27 | */ |
| 28 | 28 | ||
| 29 | #include <linux/init.h> | 29 | #include <linux/init.h> |
| 30 | 30 | #include <linux/interrupt.h> | |
| 31 | #include <asm/mach-au1x00/au1000.h> | 31 | #include <asm/mach-au1x00/au1000.h> |
| 32 | 32 | ||
| 33 | char irq_tab_alchemy[][5] __initdata = { | 33 | char irq_tab_alchemy[][5] __initdata = { |
| @@ -42,11 +42,15 @@ char irq_tab_alchemy[][5] __initdata = { | |||
| 42 | }; | 42 | }; |
| 43 | 43 | ||
| 44 | struct au1xxx_irqmap __initdata au1xxx_irq_map[] = { | 44 | struct au1xxx_irqmap __initdata au1xxx_irq_map[] = { |
| 45 | { AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0 }, | 45 | { AU1500_GPIO_204, IRQF_TRIGGER_HIGH, 0 }, |
| 46 | { AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 }, | 46 | { AU1500_GPIO_201, IRQF_TRIGGER_LOW, 0 }, |
| 47 | { AU1500_GPIO_202, INTC_INT_LOW_LEVEL, 0 }, | 47 | { AU1500_GPIO_202, IRQF_TRIGGER_LOW, 0 }, |
| 48 | { AU1500_GPIO_203, INTC_INT_LOW_LEVEL, 0 }, | 48 | { AU1500_GPIO_203, IRQF_TRIGGER_LOW, 0 }, |
| 49 | { AU1500_GPIO_205, INTC_INT_LOW_LEVEL, 0 }, | 49 | { AU1500_GPIO_205, IRQF_TRIGGER_LOW, 0 }, |
| 50 | }; | 50 | }; |
| 51 | 51 | ||
| 52 | int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map); | 52 | |
| 53 | void __init board_init_irq(void) | ||
| 54 | { | ||
| 55 | au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map)); | ||
| 56 | } | ||
diff --git a/arch/mips/alchemy/pb1000/init.c b/arch/mips/alchemy/pb1000/init.c deleted file mode 100644 index 8a9c7d57208d..000000000000 --- a/arch/mips/alchemy/pb1000/init.c +++ /dev/null | |||
| @@ -1,57 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * BRIEF MODULE DESCRIPTION | ||
| 3 | * Pb1000 board setup | ||
| 4 | * | ||
| 5 | * Copyright 2001, 2008 MontaVista Software Inc. | ||
| 6 | * Author: MontaVista Software, Inc. <source@mvista.com> | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify it | ||
| 9 | * under the terms of the GNU General Public License as published by the | ||
| 10 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 11 | * option) any later version. | ||
| 12 | * | ||
| 13 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 14 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 15 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 16 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 17 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 18 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 19 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 20 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 21 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 22 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License along | ||
| 25 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 26 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 27 | */ | ||
| 28 | |||
| 29 | #include <linux/init.h> | ||
| 30 | #include <linux/kernel.h> | ||
| 31 | |||
| 32 | #include <asm/bootinfo.h> | ||
| 33 | |||
| 34 | #include <prom.h> | ||
| 35 | |||
| 36 | const char *get_system_type(void) | ||
| 37 | { | ||
| 38 | return "Alchemy Pb1000"; | ||
| 39 | } | ||
| 40 | |||
| 41 | void __init prom_init(void) | ||
| 42 | { | ||
| 43 | unsigned char *memsize_str; | ||
| 44 | unsigned long memsize; | ||
| 45 | |||
| 46 | prom_argc = (int)fw_arg0; | ||
| 47 | prom_argv = (char **)fw_arg1; | ||
| 48 | prom_envp = (char **)fw_arg2; | ||
| 49 | |||
| 50 | prom_init_cmdline(); | ||
| 51 | memsize_str = prom_getenv("memsize"); | ||
| 52 | if (!memsize_str) | ||
| 53 | memsize = 0x04000000; | ||
| 54 | else | ||
| 55 | strict_strtol(memsize_str, 0, &memsize); | ||
| 56 | add_memory_region(0, memsize, BOOT_MEM_RAM); | ||
| 57 | } | ||
diff --git a/arch/mips/alchemy/pb1000/irqmap.c b/arch/mips/alchemy/pb1000/irqmap.c deleted file mode 100644 index b3d56b0af321..000000000000 --- a/arch/mips/alchemy/pb1000/irqmap.c +++ /dev/null | |||
| @@ -1,38 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * BRIEF MODULE DESCRIPTION | ||
| 3 | * Au1xxx irq map table | ||
| 4 | * | ||
| 5 | * Copyright 2003 Embedded Edge, LLC | ||
| 6 | * dan@embeddededge.com | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify it | ||
| 9 | * under the terms of the GNU General Public License as published by the | ||
| 10 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 11 | * option) any later version. | ||
| 12 | * | ||
| 13 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 14 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 15 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 16 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 17 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 18 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 19 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 20 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 21 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 22 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License along | ||
| 25 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 26 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 27 | */ | ||
| 28 | |||
| 29 | #include <linux/init.h> | ||
| 30 | #include <linux/interrupt.h> | ||
| 31 | |||
| 32 | #include <asm/mach-au1x00/au1000.h> | ||
| 33 | |||
| 34 | struct au1xxx_irqmap __initdata au1xxx_irq_map[] = { | ||
| 35 | { AU1000_GPIO_15, INTC_INT_LOW_LEVEL, 0 }, | ||
| 36 | }; | ||
| 37 | |||
| 38 | int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map); | ||
diff --git a/arch/mips/alchemy/pb1100/init.c b/arch/mips/alchemy/pb1100/init.c deleted file mode 100644 index 7c6792308bc5..000000000000 --- a/arch/mips/alchemy/pb1100/init.c +++ /dev/null | |||
| @@ -1,60 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * | ||
| 3 | * BRIEF MODULE DESCRIPTION | ||
| 4 | * Pb1100 board setup | ||
| 5 | * | ||
| 6 | * Copyright 2002, 2008 MontaVista Software Inc. | ||
| 7 | * Author: MontaVista Software, Inc. <source@mvista.com> | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify it | ||
| 10 | * under the terms of the GNU General Public License as published by the | ||
| 11 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 12 | * option) any later version. | ||
| 13 | * | ||
| 14 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 15 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 16 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 17 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 18 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 19 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 20 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 21 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 22 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 23 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 24 | * | ||
| 25 | * You should have received a copy of the GNU General Public License along | ||
| 26 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 27 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 28 | */ | ||
| 29 | |||
| 30 | #include <linux/init.h> | ||
| 31 | #include <linux/kernel.h> | ||
| 32 | |||
| 33 | #include <asm/bootinfo.h> | ||
| 34 | |||
| 35 | #include <prom.h> | ||
| 36 | |||
| 37 | const char *get_system_type(void) | ||
| 38 | { | ||
| 39 | return "Alchemy Pb1100"; | ||
| 40 | } | ||
| 41 | |||
| 42 | void __init prom_init(void) | ||
| 43 | { | ||
| 44 | unsigned char *memsize_str; | ||
| 45 | unsigned long memsize; | ||
| 46 | |||
| 47 | prom_argc = fw_arg0; | ||
| 48 | prom_argv = (char **)fw_arg1; | ||
| 49 | prom_envp = (char **)fw_arg3; | ||
| 50 | |||
| 51 | prom_init_cmdline(); | ||
| 52 | |||
| 53 | memsize_str = prom_getenv("memsize"); | ||
| 54 | if (!memsize_str) | ||
| 55 | memsize = 0x04000000; | ||
| 56 | else | ||
| 57 | strict_strtol(memsize_str, 0, &memsize); | ||
| 58 | |||
| 59 | add_memory_region(0, memsize, BOOT_MEM_RAM); | ||
| 60 | } | ||
diff --git a/arch/mips/alchemy/pb1100/irqmap.c b/arch/mips/alchemy/pb1100/irqmap.c deleted file mode 100644 index 9b7dd8b41283..000000000000 --- a/arch/mips/alchemy/pb1100/irqmap.c +++ /dev/null | |||
| @@ -1,40 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * BRIEF MODULE DESCRIPTION | ||
| 3 | * Au1xx0 IRQ map table | ||
| 4 | * | ||
| 5 | * Copyright 2003 Embedded Edge, LLC | ||
| 6 | * dan@embeddededge.com | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify it | ||
| 9 | * under the terms of the GNU General Public License as published by the | ||
| 10 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 11 | * option) any later version. | ||
| 12 | * | ||
| 13 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 14 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 15 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 16 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 17 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 18 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 19 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 20 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 21 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 22 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License along | ||
| 25 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 26 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 27 | */ | ||
| 28 | |||
| 29 | #include <linux/init.h> | ||
| 30 | |||
| 31 | #include <asm/mach-au1x00/au1000.h> | ||
| 32 | |||
| 33 | struct au1xxx_irqmap __initdata au1xxx_irq_map[] = { | ||
| 34 | { AU1000_GPIO_9, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card Fully_Inserted# */ | ||
| 35 | { AU1000_GPIO_10, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card STSCHG# */ | ||
| 36 | { AU1000_GPIO_11, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card IRQ# */ | ||
| 37 | { AU1000_GPIO_13, INTC_INT_LOW_LEVEL, 0 }, /* DC_IRQ# */ | ||
| 38 | }; | ||
| 39 | |||
| 40 | int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map); | ||
diff --git a/arch/mips/alchemy/pb1200/init.c b/arch/mips/alchemy/pb1200/init.c deleted file mode 100644 index e9b2a0fd48ae..000000000000 --- a/arch/mips/alchemy/pb1200/init.c +++ /dev/null | |||
| @@ -1,58 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * | ||
| 3 | * BRIEF MODULE DESCRIPTION | ||
| 4 | * PB1200 board setup | ||
| 5 | * | ||
| 6 | * Copyright 2001, 2008 MontaVista Software Inc. | ||
| 7 | * Author: MontaVista Software, Inc. <source@mvista.com> | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify it | ||
| 10 | * under the terms of the GNU General Public License as published by the | ||
| 11 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 12 | * option) any later version. | ||
| 13 | * | ||
| 14 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 15 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 16 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 17 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 18 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 19 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 20 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 21 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 22 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 23 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 24 | * | ||
| 25 | * You should have received a copy of the GNU General Public License along | ||
| 26 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 27 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 28 | */ | ||
| 29 | |||
| 30 | #include <linux/init.h> | ||
| 31 | #include <linux/kernel.h> | ||
| 32 | |||
| 33 | #include <asm/bootinfo.h> | ||
| 34 | |||
| 35 | #include <prom.h> | ||
| 36 | |||
| 37 | const char *get_system_type(void) | ||
| 38 | { | ||
| 39 | return "Alchemy Pb1200"; | ||
| 40 | } | ||
| 41 | |||
| 42 | void __init prom_init(void) | ||
| 43 | { | ||
| 44 | unsigned char *memsize_str; | ||
| 45 | unsigned long memsize; | ||
| 46 | |||
| 47 | prom_argc = (int)fw_arg0; | ||
| 48 | prom_argv = (char **)fw_arg1; | ||
| 49 | prom_envp = (char **)fw_arg2; | ||
| 50 | |||
| 51 | prom_init_cmdline(); | ||
| 52 | memsize_str = prom_getenv("memsize"); | ||
| 53 | if (!memsize_str) | ||
| 54 | memsize = 0x08000000; | ||
| 55 | else | ||
| 56 | strict_strtol(memsize_str, 0, &memsize); | ||
| 57 | add_memory_region(0, memsize, BOOT_MEM_RAM); | ||
| 58 | } | ||
diff --git a/arch/mips/alchemy/pb1500/init.c b/arch/mips/alchemy/pb1500/init.c deleted file mode 100644 index 3b6e395cf952..000000000000 --- a/arch/mips/alchemy/pb1500/init.c +++ /dev/null | |||
| @@ -1,58 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * | ||
| 3 | * BRIEF MODULE DESCRIPTION | ||
| 4 | * Pb1500 board setup | ||
| 5 | * | ||
| 6 | * Copyright 2001, 2008 MontaVista Software Inc. | ||
| 7 | * Author: MontaVista Software, Inc. <source@mvista.com> | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify it | ||
| 10 | * under the terms of the GNU General Public License as published by the | ||
| 11 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 12 | * option) any later version. | ||
| 13 | * | ||
| 14 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 15 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 16 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 17 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 18 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 19 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 20 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 21 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 22 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 23 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 24 | * | ||
| 25 | * You should have received a copy of the GNU General Public License along | ||
| 26 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 27 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 28 | */ | ||
| 29 | |||
| 30 | #include <linux/init.h> | ||
| 31 | #include <linux/kernel.h> | ||
| 32 | |||
| 33 | #include <asm/bootinfo.h> | ||
| 34 | |||
| 35 | #include <prom.h> | ||
| 36 | |||
| 37 | const char *get_system_type(void) | ||
| 38 | { | ||
| 39 | return "Alchemy Pb1500"; | ||
| 40 | } | ||
| 41 | |||
| 42 | void __init prom_init(void) | ||
| 43 | { | ||
| 44 | unsigned char *memsize_str; | ||
| 45 | unsigned long memsize; | ||
| 46 | |||
| 47 | prom_argc = (int)fw_arg0; | ||
| 48 | prom_argv = (char **)fw_arg1; | ||
| 49 | prom_envp = (char **)fw_arg2; | ||
| 50 | |||
| 51 | prom_init_cmdline(); | ||
| 52 | memsize_str = prom_getenv("memsize"); | ||
| 53 | if (!memsize_str) | ||
| 54 | memsize = 0x04000000; | ||
| 55 | else | ||
| 56 | strict_strtol(memsize_str, 0, &memsize); | ||
| 57 | add_memory_region(0, memsize, BOOT_MEM_RAM); | ||
| 58 | } | ||
diff --git a/arch/mips/alchemy/pb1500/irqmap.c b/arch/mips/alchemy/pb1500/irqmap.c deleted file mode 100644 index 39c4682766a8..000000000000 --- a/arch/mips/alchemy/pb1500/irqmap.c +++ /dev/null | |||
| @@ -1,46 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * BRIEF MODULE DESCRIPTION | ||
| 3 | * Au1xxx irq map table | ||
| 4 | * | ||
| 5 | * Copyright 2003 Embedded Edge, LLC | ||
| 6 | * dan@embeddededge.com | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify it | ||
| 9 | * under the terms of the GNU General Public License as published by the | ||
| 10 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 11 | * option) any later version. | ||
| 12 | * | ||
| 13 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 14 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 15 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 16 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 17 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 18 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 19 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 20 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 21 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 22 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License along | ||
| 25 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 26 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 27 | */ | ||
| 28 | |||
| 29 | #include <linux/init.h> | ||
| 30 | |||
| 31 | #include <asm/mach-au1x00/au1000.h> | ||
| 32 | |||
| 33 | char irq_tab_alchemy[][5] __initdata = { | ||
| 34 | [12] = { -1, INTA, INTX, INTX, INTX }, /* IDSEL 12 - HPT370 */ | ||
| 35 | [13] = { -1, INTA, INTB, INTC, INTD }, /* IDSEL 13 - PCI slot */ | ||
| 36 | }; | ||
| 37 | |||
| 38 | struct au1xxx_irqmap __initdata au1xxx_irq_map[] = { | ||
| 39 | { AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0 }, | ||
| 40 | { AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 }, | ||
| 41 | { AU1500_GPIO_202, INTC_INT_LOW_LEVEL, 0 }, | ||
| 42 | { AU1500_GPIO_203, INTC_INT_LOW_LEVEL, 0 }, | ||
| 43 | { AU1500_GPIO_205, INTC_INT_LOW_LEVEL, 0 }, | ||
| 44 | }; | ||
| 45 | |||
| 46 | int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map); | ||
diff --git a/arch/mips/alchemy/pb1550/irqmap.c b/arch/mips/alchemy/pb1550/irqmap.c deleted file mode 100644 index a02a4d1fa899..000000000000 --- a/arch/mips/alchemy/pb1550/irqmap.c +++ /dev/null | |||
| @@ -1,43 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * BRIEF MODULE DESCRIPTION | ||
| 3 | * Au1xx0 IRQ map table | ||
| 4 | * | ||
| 5 | * Copyright 2003 Embedded Edge, LLC | ||
| 6 | * dan@embeddededge.com | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify it | ||
| 9 | * under the terms of the GNU General Public License as published by the | ||
| 10 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 11 | * option) any later version. | ||
| 12 | * | ||
| 13 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 14 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 15 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 16 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 17 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 18 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 19 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 20 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 21 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 22 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License along | ||
| 25 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 26 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 27 | */ | ||
| 28 | |||
| 29 | #include <linux/init.h> | ||
| 30 | |||
| 31 | #include <asm/mach-au1x00/au1000.h> | ||
| 32 | |||
| 33 | char irq_tab_alchemy[][5] __initdata = { | ||
| 34 | [12] = { -1, INTB, INTC, INTD, INTA }, /* IDSEL 12 - PCI slot 2 (left) */ | ||
| 35 | [13] = { -1, INTA, INTB, INTC, INTD }, /* IDSEL 13 - PCI slot 1 (right) */ | ||
| 36 | }; | ||
| 37 | |||
| 38 | struct au1xxx_irqmap __initdata au1xxx_irq_map[] = { | ||
| 39 | { AU1000_GPIO_0, INTC_INT_LOW_LEVEL, 0 }, | ||
| 40 | { AU1000_GPIO_1, INTC_INT_LOW_LEVEL, 0 }, | ||
| 41 | }; | ||
| 42 | |||
| 43 | int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map); | ||
diff --git a/arch/mips/alchemy/xxs1500/board_setup.c b/arch/mips/alchemy/xxs1500/board_setup.c index 4c587acac5c3..a2634fabc50d 100644 --- a/arch/mips/alchemy/xxs1500/board_setup.c +++ b/arch/mips/alchemy/xxs1500/board_setup.c | |||
| @@ -28,6 +28,8 @@ | |||
| 28 | 28 | ||
| 29 | #include <asm/mach-au1x00/au1000.h> | 29 | #include <asm/mach-au1x00/au1000.h> |
| 30 | 30 | ||
| 31 | #include <prom.h> | ||
| 32 | |||
| 31 | void board_reset(void) | 33 | void board_reset(void) |
| 32 | { | 34 | { |
| 33 | /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */ | 35 | /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */ |
| @@ -38,6 +40,16 @@ void __init board_setup(void) | |||
| 38 | { | 40 | { |
| 39 | u32 pin_func; | 41 | u32 pin_func; |
| 40 | 42 | ||
| 43 | #ifdef CONFIG_SERIAL_8250_CONSOLE | ||
| 44 | char *argptr; | ||
| 45 | argptr = prom_getcmdline(); | ||
| 46 | argptr = strstr(argptr, "console="); | ||
| 47 | if (argptr == NULL) { | ||
| 48 | argptr = prom_getcmdline(); | ||
| 49 | strcat(argptr, " console=ttyS0,115200"); | ||
| 50 | } | ||
| 51 | #endif | ||
| 52 | |||
| 41 | /* Set multiple use pins (UART3/GPIO) to UART (it's used as UART too) */ | 53 | /* Set multiple use pins (UART3/GPIO) to UART (it's used as UART too) */ |
| 42 | pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_UR3; | 54 | pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_UR3; |
| 43 | pin_func |= SYS_PF_UR3; | 55 | pin_func |= SYS_PF_UR3; |
diff --git a/arch/mips/alchemy/xxs1500/init.c b/arch/mips/alchemy/xxs1500/init.c index 7516434760a1..456fa142c093 100644 --- a/arch/mips/alchemy/xxs1500/init.c +++ b/arch/mips/alchemy/xxs1500/init.c | |||
| @@ -53,6 +53,6 @@ void __init prom_init(void) | |||
| 53 | if (!memsize_str) | 53 | if (!memsize_str) |
| 54 | memsize = 0x04000000; | 54 | memsize = 0x04000000; |
| 55 | else | 55 | else |
| 56 | strict_strtol(memsize_str, 0, &memsize); | 56 | strict_strtoul(memsize_str, 0, &memsize); |
| 57 | add_memory_region(0, memsize, BOOT_MEM_RAM); | 57 | add_memory_region(0, memsize, BOOT_MEM_RAM); |
| 58 | } | 58 | } |
diff --git a/arch/mips/alchemy/xxs1500/irqmap.c b/arch/mips/alchemy/xxs1500/irqmap.c index edf06ed11870..0f0f3012e5fd 100644 --- a/arch/mips/alchemy/xxs1500/irqmap.c +++ b/arch/mips/alchemy/xxs1500/irqmap.c | |||
| @@ -27,23 +27,26 @@ | |||
| 27 | */ | 27 | */ |
| 28 | 28 | ||
| 29 | #include <linux/init.h> | 29 | #include <linux/init.h> |
| 30 | 30 | #include <linux/interrupt.h> | |
| 31 | #include <asm/mach-au1x00/au1000.h> | 31 | #include <asm/mach-au1x00/au1000.h> |
| 32 | 32 | ||
| 33 | struct au1xxx_irqmap __initdata au1xxx_irq_map[] = { | 33 | struct au1xxx_irqmap __initdata au1xxx_irq_map[] = { |
| 34 | { AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0 }, | 34 | { AU1500_GPIO_204, IRQF_TRIGGER_HIGH, 0 }, |
| 35 | { AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 }, | 35 | { AU1500_GPIO_201, IRQF_TRIGGER_LOW, 0 }, |
| 36 | { AU1500_GPIO_202, INTC_INT_LOW_LEVEL, 0 }, | 36 | { AU1500_GPIO_202, IRQF_TRIGGER_LOW, 0 }, |
| 37 | { AU1500_GPIO_203, INTC_INT_LOW_LEVEL, 0 }, | 37 | { AU1500_GPIO_203, IRQF_TRIGGER_LOW, 0 }, |
| 38 | { AU1500_GPIO_205, INTC_INT_LOW_LEVEL, 0 }, | 38 | { AU1500_GPIO_205, IRQF_TRIGGER_LOW, 0 }, |
| 39 | { AU1500_GPIO_207, INTC_INT_LOW_LEVEL, 0 }, | 39 | { AU1500_GPIO_207, IRQF_TRIGGER_LOW, 0 }, |
| 40 | 40 | ||
| 41 | { AU1000_GPIO_0, INTC_INT_LOW_LEVEL, 0 }, | 41 | { AU1000_GPIO_0, IRQF_TRIGGER_LOW, 0 }, |
| 42 | { AU1000_GPIO_1, INTC_INT_LOW_LEVEL, 0 }, | 42 | { AU1000_GPIO_1, IRQF_TRIGGER_LOW, 0 }, |
| 43 | { AU1000_GPIO_2, INTC_INT_LOW_LEVEL, 0 }, | 43 | { AU1000_GPIO_2, IRQF_TRIGGER_LOW, 0 }, |
| 44 | { AU1000_GPIO_3, INTC_INT_LOW_LEVEL, 0 }, | 44 | { AU1000_GPIO_3, IRQF_TRIGGER_LOW, 0 }, |
| 45 | { AU1000_GPIO_4, INTC_INT_LOW_LEVEL, 0 }, /* CF interrupt */ | 45 | { AU1000_GPIO_4, IRQF_TRIGGER_LOW, 0 }, /* CF interrupt */ |
| 46 | { AU1000_GPIO_5, INTC_INT_LOW_LEVEL, 0 }, | 46 | { AU1000_GPIO_5, IRQF_TRIGGER_LOW, 0 }, |
| 47 | }; | 47 | }; |
| 48 | 48 | ||
| 49 | int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map); | 49 | void __init board_init_irq(void) |
| 50 | { | ||
| 51 | au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map)); | ||
| 52 | } | ||
diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig new file mode 100644 index 000000000000..094c17e38e16 --- /dev/null +++ b/arch/mips/cavium-octeon/Kconfig | |||
| @@ -0,0 +1,85 @@ | |||
| 1 | config CAVIUM_OCTEON_SPECIFIC_OPTIONS | ||
| 2 | bool "Enable Octeon specific options" | ||
| 3 | depends on CPU_CAVIUM_OCTEON | ||
| 4 | default "y" | ||
| 5 | |||
| 6 | config CAVIUM_OCTEON_2ND_KERNEL | ||
| 7 | bool "Build the kernel to be used as a 2nd kernel on the same chip" | ||
| 8 | depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS | ||
| 9 | default "n" | ||
| 10 | help | ||
| 11 | This option configures this kernel to be linked at a different | ||
| 12 | address and use the 2nd uart for output. This allows a kernel built | ||
| 13 | with this option to be run at the same time as one built without this | ||
| 14 | option. | ||
| 15 | |||
| 16 | config CAVIUM_OCTEON_HW_FIX_UNALIGNED | ||
| 17 | bool "Enable hardware fixups of unaligned loads and stores" | ||
| 18 | depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS | ||
| 19 | default "y" | ||
| 20 | help | ||
| 21 | Configure the Octeon hardware to automatically fix unaligned loads | ||
| 22 | and stores. Normally unaligned accesses are fixed using a kernel | ||
| 23 | exception handler. This option enables the hardware automatic fixups, | ||
| 24 | which requires only an extra 3 cycles. Disable this option if you | ||
| 25 | are running code that relies on address exceptions on unaligned | ||
| 26 | accesses. | ||
| 27 | |||
| 28 | config CAVIUM_OCTEON_CVMSEG_SIZE | ||
| 29 | int "Number of L1 cache lines reserved for CVMSEG memory" | ||
| 30 | depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS | ||
| 31 | range 0 54 | ||
| 32 | default 1 | ||
| 33 | help | ||
| 34 | CVMSEG LM is a segment that accesses portions of the dcache as a | ||
| 35 | local memory; the larger CVMSEG is, the smaller the cache is. | ||
| 36 | This selects the size of CVMSEG LM, which is in cache blocks. The | ||
| 37 | legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is | ||
| 38 | between zero and 6192 bytes). | ||
| 39 | |||
| 40 | config CAVIUM_OCTEON_LOCK_L2 | ||
| 41 | bool "Lock often used kernel code in the L2" | ||
| 42 | depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS | ||
| 43 | default "y" | ||
| 44 | help | ||
| 45 | Enable locking parts of the kernel into the L2 cache. | ||
| 46 | |||
| 47 | config CAVIUM_OCTEON_LOCK_L2_TLB | ||
| 48 | bool "Lock the TLB handler in L2" | ||
| 49 | depends on CAVIUM_OCTEON_LOCK_L2 | ||
| 50 | default "y" | ||
| 51 | help | ||
| 52 | Lock the low level TLB fast path into L2. | ||
| 53 | |||
| 54 | config CAVIUM_OCTEON_LOCK_L2_EXCEPTION | ||
| 55 | bool "Lock the exception handler in L2" | ||
| 56 | depends on CAVIUM_OCTEON_LOCK_L2 | ||
| 57 | default "y" | ||
| 58 | help | ||
| 59 | Lock the low level exception handler into L2. | ||
| 60 | |||
| 61 | config CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT | ||
| 62 | bool "Lock the interrupt handler in L2" | ||
| 63 | depends on CAVIUM_OCTEON_LOCK_L2 | ||
| 64 | default "y" | ||
| 65 | help | ||
| 66 | Lock the low level interrupt handler into L2. | ||
| 67 | |||
| 68 | config CAVIUM_OCTEON_LOCK_L2_INTERRUPT | ||
| 69 | bool "Lock the 2nd level interrupt handler in L2" | ||
| 70 | depends on CAVIUM_OCTEON_LOCK_L2 | ||
| 71 | default "y" | ||
| 72 | help | ||
| 73 | Lock the 2nd level interrupt handler in L2. | ||
| 74 | |||
| 75 | config CAVIUM_OCTEON_LOCK_L2_MEMCPY | ||
| 76 | bool "Lock memcpy() in L2" | ||
| 77 | depends on CAVIUM_OCTEON_LOCK_L2 | ||
| 78 | default "y" | ||
| 79 | help | ||
| 80 | Lock the kernel's implementation of memcpy() into L2. | ||
| 81 | |||
| 82 | config ARCH_SPARSEMEM_ENABLE | ||
| 83 | def_bool y | ||
| 84 | select SPARSEMEM_STATIC | ||
| 85 | depends on CPU_CAVIUM_OCTEON | ||
diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile new file mode 100644 index 000000000000..1c2a7faf5881 --- /dev/null +++ b/arch/mips/cavium-octeon/Makefile | |||
| @@ -0,0 +1,16 @@ | |||
| 1 | # | ||
| 2 | # Makefile for the Cavium Octeon specific kernel interface routines | ||
| 3 | # under Linux. | ||
| 4 | # | ||
| 5 | # This file is subject to the terms and conditions of the GNU General Public | ||
| 6 | # License. See the file "COPYING" in the main directory of this archive | ||
| 7 | # for more details. | ||
| 8 | # | ||
| 9 | # Copyright (C) 2005-2008 Cavium Networks | ||
| 10 | # | ||
| 11 | |||
| 12 | obj-y := setup.o serial.o octeon-irq.o csrc-octeon.o | ||
| 13 | obj-y += dma-octeon.o flash_setup.o | ||
| 14 | obj-y += octeon-memcpy.o | ||
| 15 | |||
| 16 | obj-$(CONFIG_SMP) += smp.o | ||
diff --git a/arch/mips/cavium-octeon/csrc-octeon.c b/arch/mips/cavium-octeon/csrc-octeon.c new file mode 100644 index 000000000000..70fd92c31657 --- /dev/null +++ b/arch/mips/cavium-octeon/csrc-octeon.c | |||
| @@ -0,0 +1,58 @@ | |||
| 1 | /* | ||
| 2 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 3 | * License. See the file "COPYING" in the main directory of this archive | ||
| 4 | * for more details. | ||
| 5 | * | ||
| 6 | * Copyright (C) 2007 by Ralf Baechle | ||
| 7 | */ | ||
| 8 | #include <linux/clocksource.h> | ||
| 9 | #include <linux/init.h> | ||
| 10 | |||
| 11 | #include <asm/time.h> | ||
| 12 | |||
| 13 | #include <asm/octeon/octeon.h> | ||
| 14 | #include <asm/octeon/cvmx-ipd-defs.h> | ||
| 15 | |||
| 16 | /* | ||
| 17 | * Set the current core's cvmcount counter to the value of the | ||
| 18 | * IPD_CLK_COUNT. We do this on all cores as they are brought | ||
| 19 | * on-line. This allows for a read from a local cpu register to | ||
| 20 | * access a synchronized counter. | ||
| 21 | * | ||
| 22 | */ | ||
| 23 | void octeon_init_cvmcount(void) | ||
| 24 | { | ||
| 25 | unsigned long flags; | ||
| 26 | unsigned loops = 2; | ||
| 27 | |||
| 28 | /* Clobber loops so GCC will not unroll the following while loop. */ | ||
| 29 | asm("" : "+r" (loops)); | ||
| 30 | |||
| 31 | local_irq_save(flags); | ||
| 32 | /* | ||
| 33 | * Loop several times so we are executing from the cache, | ||
| 34 | * which should give more deterministic timing. | ||
| 35 | */ | ||
| 36 | while (loops--) | ||
| 37 | write_c0_cvmcount(cvmx_read_csr(CVMX_IPD_CLK_COUNT)); | ||
| 38 | local_irq_restore(flags); | ||
| 39 | } | ||
| 40 | |||
| 41 | static cycle_t octeon_cvmcount_read(void) | ||
| 42 | { | ||
| 43 | return read_c0_cvmcount(); | ||
| 44 | } | ||
| 45 | |||
| 46 | static struct clocksource clocksource_mips = { | ||
| 47 | .name = "OCTEON_CVMCOUNT", | ||
| 48 | .read = octeon_cvmcount_read, | ||
| 49 | .mask = CLOCKSOURCE_MASK(64), | ||
| 50 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | ||
| 51 | }; | ||
| 52 | |||
| 53 | void __init plat_time_init(void) | ||
| 54 | { | ||
| 55 | clocksource_mips.rating = 300; | ||
| 56 | clocksource_set_clock(&clocksource_mips, mips_hpt_frequency); | ||
| 57 | clocksource_register(&clocksource_mips); | ||
| 58 | } | ||
diff --git a/arch/mips/cavium-octeon/dma-octeon.c b/arch/mips/cavium-octeon/dma-octeon.c new file mode 100644 index 000000000000..01b1ef94b361 --- /dev/null +++ b/arch/mips/cavium-octeon/dma-octeon.c | |||
| @@ -0,0 +1,32 @@ | |||
| 1 | /* | ||
| 2 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 3 | * License. See the file "COPYING" in the main directory of this archive | ||
| 4 | * for more details. | ||
| 5 | * | ||
| 6 | * Copyright (C) 2000 Ani Joshi <ajoshi@unixbox.com> | ||
| 7 | * Copyright (C) 2000, 2001 Ralf Baechle <ralf@gnu.org> | ||
| 8 | * Copyright (C) 2005 Ilya A. Volynets-Evenbakh <ilya@total-knowledge.com> | ||
| 9 | * swiped from i386, and cloned for MIPS by Geert, polished by Ralf. | ||
| 10 | * IP32 changes by Ilya. | ||
| 11 | * Cavium Networks: Create new dma setup for Cavium Networks Octeon based on | ||
| 12 | * the kernels original. | ||
| 13 | */ | ||
| 14 | #include <linux/types.h> | ||
| 15 | #include <linux/mm.h> | ||
| 16 | |||
| 17 | #include <dma-coherence.h> | ||
| 18 | |||
| 19 | dma_addr_t octeon_map_dma_mem(struct device *dev, void *ptr, size_t size) | ||
| 20 | { | ||
| 21 | /* Without PCI/PCIe this function can be called for Octeon internal | ||
| 22 | devices such as USB. These devices all support 64bit addressing */ | ||
| 23 | mb(); | ||
| 24 | return virt_to_phys(ptr); | ||
| 25 | } | ||
| 26 | |||
| 27 | void octeon_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr) | ||
| 28 | { | ||
| 29 | /* Without PCI/PCIe this function can be called for Octeon internal | ||
| 30 | * devices such as USB. These devices all support 64bit addressing */ | ||
| 31 | return; | ||
| 32 | } | ||
diff --git a/arch/mips/cavium-octeon/executive/Makefile b/arch/mips/cavium-octeon/executive/Makefile new file mode 100644 index 000000000000..80d6cb26766b --- /dev/null +++ b/arch/mips/cavium-octeon/executive/Makefile | |||
| @@ -0,0 +1,13 @@ | |||
| 1 | # | ||
| 2 | # Makefile for the Cavium Octeon specific kernel interface routines | ||
| 3 | # under Linux. | ||
| 4 | # | ||
| 5 | # This file is subject to the terms and conditions of the GNU General Public | ||
| 6 | # License. See the file "COPYING" in the main directory of this archive | ||
| 7 | # for more details. | ||
| 8 | # | ||
| 9 | # Copyright (C) 2005-2008 Cavium Networks | ||
| 10 | # | ||
| 11 | |||
| 12 | obj-y += cvmx-bootmem.o cvmx-l2c.o cvmx-sysinfo.o octeon-model.o | ||
| 13 | |||
diff --git a/arch/mips/cavium-octeon/executive/cvmx-bootmem.c b/arch/mips/cavium-octeon/executive/cvmx-bootmem.c new file mode 100644 index 000000000000..4f5a08b37ccd --- /dev/null +++ b/arch/mips/cavium-octeon/executive/cvmx-bootmem.c | |||
| @@ -0,0 +1,586 @@ | |||
| 1 | /***********************license start*************** | ||
| 2 | * Author: Cavium Networks | ||
| 3 | * | ||
| 4 | * Contact: support@caviumnetworks.com | ||
| 5 | * This file is part of the OCTEON SDK | ||
| 6 | * | ||
| 7 | * Copyright (c) 2003-2008 Cavium Networks | ||
| 8 | * | ||
| 9 | * This file is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License, Version 2, as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | * | ||
| 13 | * This file is distributed in the hope that it will be useful, but | ||
| 14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
| 15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
| 16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
| 17 | * details. | ||
| 18 | * | ||
| 19 | * You should have received a copy of the GNU General Public License | ||
| 20 | * along with this file; if not, write to the Free Software | ||
| 21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 22 | * or visit http://www.gnu.org/licenses/. | ||
| 23 | * | ||
| 24 | * This file may also be available under a different license from Cavium. | ||
| 25 | * Contact Cavium Networks for more information | ||
| 26 | ***********************license end**************************************/ | ||
| 27 | |||
| 28 | /* | ||
| 29 | * Simple allocate only memory allocator. Used to allocate memory at | ||
| 30 | * application start time. | ||
| 31 | */ | ||
| 32 | |||
| 33 | #include <linux/kernel.h> | ||
| 34 | |||
| 35 | #include <asm/octeon/cvmx.h> | ||
| 36 | #include <asm/octeon/cvmx-spinlock.h> | ||
| 37 | #include <asm/octeon/cvmx-bootmem.h> | ||
| 38 | |||
| 39 | /*#define DEBUG */ | ||
| 40 | |||
| 41 | |||
| 42 | static struct cvmx_bootmem_desc *cvmx_bootmem_desc; | ||
| 43 | |||
| 44 | /* See header file for descriptions of functions */ | ||
| 45 | |||
| 46 | /* | ||
| 47 | * Wrapper functions are provided for reading/writing the size and | ||
| 48 | * next block values as these may not be directly addressible (in 32 | ||
| 49 | * bit applications, for instance.) Offsets of data elements in | ||
| 50 | * bootmem list, must match cvmx_bootmem_block_header_t. | ||
| 51 | */ | ||
| 52 | #define NEXT_OFFSET 0 | ||
| 53 | #define SIZE_OFFSET 8 | ||
| 54 | |||
| 55 | static void cvmx_bootmem_phy_set_size(uint64_t addr, uint64_t size) | ||
| 56 | { | ||
| 57 | cvmx_write64_uint64((addr + SIZE_OFFSET) | (1ull << 63), size); | ||
| 58 | } | ||
| 59 | |||
| 60 | static void cvmx_bootmem_phy_set_next(uint64_t addr, uint64_t next) | ||
| 61 | { | ||
| 62 | cvmx_write64_uint64((addr + NEXT_OFFSET) | (1ull << 63), next); | ||
| 63 | } | ||
| 64 | |||
| 65 | static uint64_t cvmx_bootmem_phy_get_size(uint64_t addr) | ||
| 66 | { | ||
| 67 | return cvmx_read64_uint64((addr + SIZE_OFFSET) | (1ull << 63)); | ||
| 68 | } | ||
| 69 | |||
| 70 | static uint64_t cvmx_bootmem_phy_get_next(uint64_t addr) | ||
| 71 | { | ||
| 72 | return cvmx_read64_uint64((addr + NEXT_OFFSET) | (1ull << 63)); | ||
| 73 | } | ||
| 74 | |||
| 75 | void *cvmx_bootmem_alloc_range(uint64_t size, uint64_t alignment, | ||
| 76 | uint64_t min_addr, uint64_t max_addr) | ||
| 77 | { | ||
| 78 | int64_t address; | ||
| 79 | address = | ||
| 80 | cvmx_bootmem_phy_alloc(size, min_addr, max_addr, alignment, 0); | ||
| 81 | |||
| 82 | if (address > 0) | ||
| 83 | return cvmx_phys_to_ptr(address); | ||
| 84 | else | ||
| 85 | return NULL; | ||
| 86 | } | ||
| 87 | |||
| 88 | void *cvmx_bootmem_alloc_address(uint64_t size, uint64_t address, | ||
| 89 | uint64_t alignment) | ||
| 90 | { | ||
| 91 | return cvmx_bootmem_alloc_range(size, alignment, address, | ||
| 92 | address + size); | ||
| 93 | } | ||
| 94 | |||
| 95 | void *cvmx_bootmem_alloc(uint64_t size, uint64_t alignment) | ||
| 96 | { | ||
| 97 | return cvmx_bootmem_alloc_range(size, alignment, 0, 0); | ||
| 98 | } | ||
| 99 | |||
| 100 | int cvmx_bootmem_free_named(char *name) | ||
| 101 | { | ||
| 102 | return cvmx_bootmem_phy_named_block_free(name, 0); | ||
| 103 | } | ||
| 104 | |||
| 105 | struct cvmx_bootmem_named_block_desc *cvmx_bootmem_find_named_block(char *name) | ||
| 106 | { | ||
| 107 | return cvmx_bootmem_phy_named_block_find(name, 0); | ||
| 108 | } | ||
| 109 | |||
| 110 | void cvmx_bootmem_lock(void) | ||
| 111 | { | ||
| 112 | cvmx_spinlock_lock((cvmx_spinlock_t *) &(cvmx_bootmem_desc->lock)); | ||
| 113 | } | ||
| 114 | |||
| 115 | void cvmx_bootmem_unlock(void) | ||
| 116 | { | ||
| 117 | cvmx_spinlock_unlock((cvmx_spinlock_t *) &(cvmx_bootmem_desc->lock)); | ||
| 118 | } | ||
| 119 | |||
| 120 | int cvmx_bootmem_init(void *mem_desc_ptr) | ||
| 121 | { | ||
| 122 | /* Here we set the global pointer to the bootmem descriptor | ||
| 123 | * block. This pointer will be used directly, so we will set | ||
| 124 | * it up to be directly usable by the application. It is set | ||
| 125 | * up as follows for the various runtime/ABI combinations: | ||
| 126 | * | ||
| 127 | * Linux 64 bit: Set XKPHYS bit | ||
| 128 | * Linux 32 bit: use mmap to create mapping, use virtual address | ||
| 129 | * CVMX 64 bit: use physical address directly | ||
| 130 | * CVMX 32 bit: use physical address directly | ||
| 131 | * | ||
| 132 | * Note that the CVMX environment assumes the use of 1-1 TLB | ||
| 133 | * mappings so that the physical addresses can be used | ||
| 134 | * directly | ||
| 135 | */ | ||
| 136 | if (!cvmx_bootmem_desc) { | ||
| 137 | #if defined(CVMX_ABI_64) | ||
| 138 | /* Set XKPHYS bit */ | ||
| 139 | cvmx_bootmem_desc = cvmx_phys_to_ptr(CAST64(mem_desc_ptr)); | ||
| 140 | #else | ||
| 141 | cvmx_bootmem_desc = (struct cvmx_bootmem_desc *) mem_desc_ptr; | ||
| 142 | #endif | ||
| 143 | } | ||
| 144 | |||
| 145 | return 0; | ||
| 146 | } | ||
| 147 | |||
| 148 | /* | ||
| 149 | * The cvmx_bootmem_phy* functions below return 64 bit physical | ||
| 150 | * addresses, and expose more features that the cvmx_bootmem_functions | ||
| 151 | * above. These are required for full memory space access in 32 bit | ||
| 152 | * applications, as well as for using some advance features. Most | ||
| 153 | * applications should not need to use these. | ||
| 154 | */ | ||
| 155 | |||
| 156 | int64_t cvmx_bootmem_phy_alloc(uint64_t req_size, uint64_t address_min, | ||
| 157 | uint64_t address_max, uint64_t alignment, | ||
| 158 | uint32_t flags) | ||
| 159 | { | ||
| 160 | |||
| 161 | uint64_t head_addr; | ||
| 162 | uint64_t ent_addr; | ||
| 163 | /* points to previous list entry, NULL current entry is head of list */ | ||
| 164 | uint64_t prev_addr = 0; | ||
| 165 | uint64_t new_ent_addr = 0; | ||
| 166 | uint64_t desired_min_addr; | ||
| 167 | |||
| 168 | #ifdef DEBUG | ||
| 169 | cvmx_dprintf("cvmx_bootmem_phy_alloc: req_size: 0x%llx, " | ||
| 170 | "min_addr: 0x%llx, max_addr: 0x%llx, align: 0x%llx\n", | ||
| 171 | (unsigned long long)req_size, | ||
| 172 | (unsigned long long)address_min, | ||
| 173 | (unsigned long long)address_max, | ||
| 174 | (unsigned long long)alignment); | ||
| 175 | #endif | ||
| 176 | |||
| 177 | if (cvmx_bootmem_desc->major_version > 3) { | ||
| 178 | cvmx_dprintf("ERROR: Incompatible bootmem descriptor " | ||
| 179 | "version: %d.%d at addr: %p\n", | ||
| 180 | (int)cvmx_bootmem_desc->major_version, | ||
| 181 | (int)cvmx_bootmem_desc->minor_version, | ||
| 182 | cvmx_bootmem_desc); | ||
| 183 | goto error_out; | ||
| 184 | } | ||
| 185 | |||
| 186 | /* | ||
| 187 | * Do a variety of checks to validate the arguments. The | ||
| 188 | * allocator code will later assume that these checks have | ||
| 189 | * been made. We validate that the requested constraints are | ||
| 190 | * not self-contradictory before we look through the list of | ||
| 191 | * available memory. | ||
| 192 | */ | ||
| 193 | |||
| 194 | /* 0 is not a valid req_size for this allocator */ | ||
| 195 | if (!req_size) | ||
| 196 | goto error_out; | ||
| 197 | |||
| 198 | /* Round req_size up to mult of minimum alignment bytes */ | ||
| 199 | req_size = (req_size + (CVMX_BOOTMEM_ALIGNMENT_SIZE - 1)) & | ||
| 200 | ~(CVMX_BOOTMEM_ALIGNMENT_SIZE - 1); | ||
| 201 | |||
| 202 | /* | ||
| 203 | * Convert !0 address_min and 0 address_max to special case of | ||
| 204 | * range that specifies an exact memory block to allocate. Do | ||
| 205 | * this before other checks and adjustments so that this | ||
| 206 | * tranformation will be validated. | ||
| 207 | */ | ||
| 208 | if (address_min && !address_max) | ||
| 209 | address_max = address_min + req_size; | ||
| 210 | else if (!address_min && !address_max) | ||
| 211 | address_max = ~0ull; /* If no limits given, use max limits */ | ||
| 212 | |||
| 213 | |||
| 214 | /* | ||
| 215 | * Enforce minimum alignment (this also keeps the minimum free block | ||
| 216 | * req_size the same as the alignment req_size. | ||
| 217 | */ | ||
| 218 | if (alignment < CVMX_BOOTMEM_ALIGNMENT_SIZE) | ||
| 219 | alignment = CVMX_BOOTMEM_ALIGNMENT_SIZE; | ||
| 220 | |||
| 221 | /* | ||
| 222 | * Adjust address minimum based on requested alignment (round | ||
| 223 | * up to meet alignment). Do this here so we can reject | ||
| 224 | * impossible requests up front. (NOP for address_min == 0) | ||
| 225 | */ | ||
| 226 | if (alignment) | ||
| 227 | address_min = __ALIGN_MASK(address_min, (alignment - 1)); | ||
| 228 | |||
| 229 | /* | ||
| 230 | * Reject inconsistent args. We have adjusted these, so this | ||
| 231 | * may fail due to our internal changes even if this check | ||
| 232 | * would pass for the values the user supplied. | ||
| 233 | */ | ||
| 234 | if (req_size > address_max - address_min) | ||
| 235 | goto error_out; | ||
| 236 | |||
| 237 | /* Walk through the list entries - first fit found is returned */ | ||
| 238 | |||
| 239 | if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING)) | ||
| 240 | cvmx_bootmem_lock(); | ||
| 241 | head_addr = cvmx_bootmem_desc->head_addr; | ||
| 242 | ent_addr = head_addr; | ||
| 243 | for (; ent_addr; | ||
| 244 | prev_addr = ent_addr, | ||
| 245 | ent_addr = cvmx_bootmem_phy_get_next(ent_addr)) { | ||
| 246 | uint64_t usable_base, usable_max; | ||
| 247 | uint64_t ent_size = cvmx_bootmem_phy_get_size(ent_addr); | ||
| 248 | |||
| 249 | if (cvmx_bootmem_phy_get_next(ent_addr) | ||
| 250 | && ent_addr > cvmx_bootmem_phy_get_next(ent_addr)) { | ||
| 251 | cvmx_dprintf("Internal bootmem_alloc() error: ent: " | ||
| 252 | "0x%llx, next: 0x%llx\n", | ||
| 253 | (unsigned long long)ent_addr, | ||
| 254 | (unsigned long long) | ||
| 255 | cvmx_bootmem_phy_get_next(ent_addr)); | ||
| 256 | goto error_out; | ||
| 257 | } | ||
| 258 | |||
| 259 | /* | ||
| 260 | * Determine if this is an entry that can satisify the | ||
| 261 | * request Check to make sure entry is large enough to | ||
| 262 | * satisfy request. | ||
| 263 | */ | ||
| 264 | usable_base = | ||
| 265 | __ALIGN_MASK(max(address_min, ent_addr), alignment - 1); | ||
| 266 | usable_max = min(address_max, ent_addr + ent_size); | ||
| 267 | /* | ||
| 268 | * We should be able to allocate block at address | ||
| 269 | * usable_base. | ||
| 270 | */ | ||
| 271 | |||
| 272 | desired_min_addr = usable_base; | ||
| 273 | /* | ||
| 274 | * Determine if request can be satisfied from the | ||
| 275 | * current entry. | ||
| 276 | */ | ||
| 277 | if (!((ent_addr + ent_size) > usable_base | ||
| 278 | && ent_addr < address_max | ||
| 279 | && req_size <= usable_max - usable_base)) | ||
| 280 | continue; | ||
| 281 | /* | ||
| 282 | * We have found an entry that has room to satisfy the | ||
| 283 | * request, so allocate it from this entry. If end | ||
| 284 | * CVMX_BOOTMEM_FLAG_END_ALLOC set, then allocate from | ||
| 285 | * the end of this block rather than the beginning. | ||
| 286 | */ | ||
| 287 | if (flags & CVMX_BOOTMEM_FLAG_END_ALLOC) { | ||
| 288 | desired_min_addr = usable_max - req_size; | ||
| 289 | /* | ||
| 290 | * Align desired address down to required | ||
| 291 | * alignment. | ||
| 292 | */ | ||
| 293 | desired_min_addr &= ~(alignment - 1); | ||
| 294 | } | ||
| 295 | |||
| 296 | /* Match at start of entry */ | ||
| 297 | if (desired_min_addr == ent_addr) { | ||
| 298 | if (req_size < ent_size) { | ||
| 299 | /* | ||
| 300 | * big enough to create a new block | ||
| 301 | * from top portion of block. | ||
| 302 | */ | ||
| 303 | new_ent_addr = ent_addr + req_size; | ||
| 304 | cvmx_bootmem_phy_set_next(new_ent_addr, | ||
| 305 | cvmx_bootmem_phy_get_next(ent_addr)); | ||
| 306 | cvmx_bootmem_phy_set_size(new_ent_addr, | ||
| 307 | ent_size - | ||
| 308 | req_size); | ||
| 309 | |||
| 310 | /* | ||
| 311 | * Adjust next pointer as following | ||
| 312 | * code uses this. | ||
| 313 | */ | ||
| 314 | cvmx_bootmem_phy_set_next(ent_addr, | ||
| 315 | new_ent_addr); | ||
| 316 | } | ||
| 317 | |||
| 318 | /* | ||
| 319 | * adjust prev ptr or head to remove this | ||
| 320 | * entry from list. | ||
| 321 | */ | ||
| 322 | if (prev_addr) | ||
| 323 | cvmx_bootmem_phy_set_next(prev_addr, | ||
| 324 | cvmx_bootmem_phy_get_next(ent_addr)); | ||
| 325 | else | ||
| 326 | /* | ||
| 327 | * head of list being returned, so | ||
| 328 | * update head ptr. | ||
| 329 | */ | ||
| 330 | cvmx_bootmem_desc->head_addr = | ||
| 331 | cvmx_bootmem_phy_get_next(ent_addr); | ||
| 332 | |||
| 333 | if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING)) | ||
| 334 | cvmx_bootmem_unlock(); | ||
| 335 | return desired_min_addr; | ||
| 336 | } | ||
| 337 | /* | ||
| 338 | * block returned doesn't start at beginning of entry, | ||
| 339 | * so we know that we will be splitting a block off | ||
| 340 | * the front of this one. Create a new block from the | ||
| 341 | * beginning, add to list, and go to top of loop | ||
| 342 | * again. | ||
| 343 | * | ||
| 344 | * create new block from high portion of | ||
| 345 | * block, so that top block starts at desired | ||
| 346 | * addr. | ||
| 347 | */ | ||
| 348 | new_ent_addr = desired_min_addr; | ||
| 349 | cvmx_bootmem_phy_set_next(new_ent_addr, | ||
| 350 | cvmx_bootmem_phy_get_next | ||
| 351 | (ent_addr)); | ||
| 352 | cvmx_bootmem_phy_set_size(new_ent_addr, | ||
| 353 | cvmx_bootmem_phy_get_size | ||
| 354 | (ent_addr) - | ||
| 355 | (desired_min_addr - | ||
| 356 | ent_addr)); | ||
| 357 | cvmx_bootmem_phy_set_size(ent_addr, | ||
| 358 | desired_min_addr - ent_addr); | ||
| 359 | cvmx_bootmem_phy_set_next(ent_addr, new_ent_addr); | ||
| 360 | /* Loop again to handle actual alloc from new block */ | ||
| 361 | } | ||
| 362 | error_out: | ||
| 363 | /* We didn't find anything, so return error */ | ||
| 364 | if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING)) | ||
| 365 | cvmx_bootmem_unlock(); | ||
| 366 | return -1; | ||
| 367 | } | ||
| 368 | |||
| 369 | int __cvmx_bootmem_phy_free(uint64_t phy_addr, uint64_t size, uint32_t flags) | ||
| 370 | { | ||
| 371 | uint64_t cur_addr; | ||
| 372 | uint64_t prev_addr = 0; /* zero is invalid */ | ||
| 373 | int retval = 0; | ||
| 374 | |||
| 375 | #ifdef DEBUG | ||
| 376 | cvmx_dprintf("__cvmx_bootmem_phy_free addr: 0x%llx, size: 0x%llx\n", | ||
| 377 | (unsigned long long)phy_addr, (unsigned long long)size); | ||
| 378 | #endif | ||
| 379 | if (cvmx_bootmem_desc->major_version > 3) { | ||
| 380 | cvmx_dprintf("ERROR: Incompatible bootmem descriptor " | ||
| 381 | "version: %d.%d at addr: %p\n", | ||
| 382 | (int)cvmx_bootmem_desc->major_version, | ||
| 383 | (int)cvmx_bootmem_desc->minor_version, | ||
| 384 | cvmx_bootmem_desc); | ||
| 385 | return 0; | ||
| 386 | } | ||
| 387 | |||
| 388 | /* 0 is not a valid size for this allocator */ | ||
| 389 | if (!size) | ||
| 390 | return 0; | ||
| 391 | |||
| 392 | if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING)) | ||
| 393 | cvmx_bootmem_lock(); | ||
| 394 | cur_addr = cvmx_bootmem_desc->head_addr; | ||
| 395 | if (cur_addr == 0 || phy_addr < cur_addr) { | ||
| 396 | /* add at front of list - special case with changing head ptr */ | ||
| 397 | if (cur_addr && phy_addr + size > cur_addr) | ||
| 398 | goto bootmem_free_done; /* error, overlapping section */ | ||
| 399 | else if (phy_addr + size == cur_addr) { | ||
| 400 | /* Add to front of existing first block */ | ||
| 401 | cvmx_bootmem_phy_set_next(phy_addr, | ||
| 402 | cvmx_bootmem_phy_get_next | ||
| 403 | (cur_addr)); | ||
| 404 | cvmx_bootmem_phy_set_size(phy_addr, | ||
| 405 | cvmx_bootmem_phy_get_size | ||
| 406 | (cur_addr) + size); | ||
| 407 | cvmx_bootmem_desc->head_addr = phy_addr; | ||
| 408 | |||
| 409 | } else { | ||
| 410 | /* New block before first block. OK if cur_addr is 0 */ | ||
| 411 | cvmx_bootmem_phy_set_next(phy_addr, cur_addr); | ||
| 412 | cvmx_bootmem_phy_set_size(phy_addr, size); | ||
| 413 | cvmx_bootmem_desc->head_addr = phy_addr; | ||
| 414 | } | ||
| 415 | retval = 1; | ||
| 416 | goto bootmem_free_done; | ||
| 417 | } | ||
| 418 | |||
| 419 | /* Find place in list to add block */ | ||
| 420 | while (cur_addr && phy_addr > cur_addr) { | ||
| 421 | prev_addr = cur_addr; | ||
| 422 | cur_addr = cvmx_bootmem_phy_get_next(cur_addr); | ||
| 423 | } | ||
| 424 | |||
| 425 | if (!cur_addr) { | ||
| 426 | /* | ||
| 427 | * We have reached the end of the list, add on to end, | ||
| 428 | * checking to see if we need to combine with last | ||
| 429 | * block | ||
| 430 | */ | ||
| 431 | if (prev_addr + cvmx_bootmem_phy_get_size(prev_addr) == | ||
| 432 | phy_addr) { | ||
| 433 | cvmx_bootmem_phy_set_size(prev_addr, | ||
| 434 | cvmx_bootmem_phy_get_size | ||
| 435 | (prev_addr) + size); | ||
| 436 | } else { | ||
| 437 | cvmx_bootmem_phy_set_next(prev_addr, phy_addr); | ||
| 438 | cvmx_bootmem_phy_set_size(phy_addr, size); | ||
| 439 | cvmx_bootmem_phy_set_next(phy_addr, 0); | ||
| 440 | } | ||
| 441 | retval = 1; | ||
| 442 | goto bootmem_free_done; | ||
| 443 | } else { | ||
| 444 | /* | ||
| 445 | * insert between prev and cur nodes, checking for | ||
| 446 | * merge with either/both. | ||
| 447 | */ | ||
| 448 | if (prev_addr + cvmx_bootmem_phy_get_size(prev_addr) == | ||
| 449 | phy_addr) { | ||
| 450 | /* Merge with previous */ | ||
| 451 | cvmx_bootmem_phy_set_size(prev_addr, | ||
| 452 | cvmx_bootmem_phy_get_size | ||
| 453 | (prev_addr) + size); | ||
| 454 | if (phy_addr + size == cur_addr) { | ||
| 455 | /* Also merge with current */ | ||
| 456 | cvmx_bootmem_phy_set_size(prev_addr, | ||
| 457 | cvmx_bootmem_phy_get_size(cur_addr) + | ||
| 458 | cvmx_bootmem_phy_get_size(prev_addr)); | ||
| 459 | cvmx_bootmem_phy_set_next(prev_addr, | ||
| 460 | cvmx_bootmem_phy_get_next(cur_addr)); | ||
| 461 | } | ||
| 462 | retval = 1; | ||
| 463 | goto bootmem_free_done; | ||
| 464 | } else if (phy_addr + size == cur_addr) { | ||
| 465 | /* Merge with current */ | ||
| 466 | cvmx_bootmem_phy_set_size(phy_addr, | ||
| 467 | cvmx_bootmem_phy_get_size | ||
| 468 | (cur_addr) + size); | ||
| 469 | cvmx_bootmem_phy_set_next(phy_addr, | ||
| 470 | cvmx_bootmem_phy_get_next | ||
| 471 | (cur_addr)); | ||
| 472 | cvmx_bootmem_phy_set_next(prev_addr, phy_addr); | ||
| 473 | retval = 1; | ||
| 474 | goto bootmem_free_done; | ||
| 475 | } | ||
| 476 | |||
| 477 | /* It is a standalone block, add in between prev and cur */ | ||
| 478 | cvmx_bootmem_phy_set_size(phy_addr, size); | ||
| 479 | cvmx_bootmem_phy_set_next(phy_addr, cur_addr); | ||
| 480 | cvmx_bootmem_phy_set_next(prev_addr, phy_addr); | ||
| 481 | |||
| 482 | } | ||
| 483 | retval = 1; | ||
| 484 | |||
| 485 | bootmem_free_done: | ||
| 486 | if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING)) | ||
| 487 | cvmx_bootmem_unlock(); | ||
| 488 | return retval; | ||
| 489 | |||
| 490 | } | ||
| 491 | |||
| 492 | struct cvmx_bootmem_named_block_desc * | ||
| 493 | cvmx_bootmem_phy_named_block_find(char *name, uint32_t flags) | ||
| 494 | { | ||
| 495 | unsigned int i; | ||
| 496 | struct cvmx_bootmem_named_block_desc *named_block_array_ptr; | ||
| 497 | |||
| 498 | #ifdef DEBUG | ||
| 499 | cvmx_dprintf("cvmx_bootmem_phy_named_block_find: %s\n", name); | ||
| 500 | #endif | ||
| 501 | /* | ||
| 502 | * Lock the structure to make sure that it is not being | ||
| 503 | * changed while we are examining it. | ||
| 504 | */ | ||
| 505 | if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING)) | ||
| 506 | cvmx_bootmem_lock(); | ||
| 507 | |||
| 508 | /* Use XKPHYS for 64 bit linux */ | ||
| 509 | named_block_array_ptr = (struct cvmx_bootmem_named_block_desc *) | ||
| 510 | cvmx_phys_to_ptr(cvmx_bootmem_desc->named_block_array_addr); | ||
| 511 | |||
| 512 | #ifdef DEBUG | ||
| 513 | cvmx_dprintf | ||
| 514 | ("cvmx_bootmem_phy_named_block_find: named_block_array_ptr: %p\n", | ||
| 515 | named_block_array_ptr); | ||
| 516 | #endif | ||
| 517 | if (cvmx_bootmem_desc->major_version == 3) { | ||
| 518 | for (i = 0; | ||
| 519 | i < cvmx_bootmem_desc->named_block_num_blocks; i++) { | ||
| 520 | if ((name && named_block_array_ptr[i].size | ||
| 521 | && !strncmp(name, named_block_array_ptr[i].name, | ||
| 522 | cvmx_bootmem_desc->named_block_name_len | ||
| 523 | - 1)) | ||
| 524 | || (!name && !named_block_array_ptr[i].size)) { | ||
| 525 | if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING)) | ||
| 526 | cvmx_bootmem_unlock(); | ||
| 527 | |||
| 528 | return &(named_block_array_ptr[i]); | ||
| 529 | } | ||
| 530 | } | ||
| 531 | } else { | ||
| 532 | cvmx_dprintf("ERROR: Incompatible bootmem descriptor " | ||
| 533 | "version: %d.%d at addr: %p\n", | ||
| 534 | (int)cvmx_bootmem_desc->major_version, | ||
| 535 | (int)cvmx_bootmem_desc->minor_version, | ||
| 536 | cvmx_bootmem_desc); | ||
| 537 | } | ||
| 538 | if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING)) | ||
| 539 | cvmx_bootmem_unlock(); | ||
| 540 | |||
| 541 | return NULL; | ||
| 542 | } | ||
| 543 | |||
| 544 | int cvmx_bootmem_phy_named_block_free(char *name, uint32_t flags) | ||
| 545 | { | ||
| 546 | struct cvmx_bootmem_named_block_desc *named_block_ptr; | ||
| 547 | |||
| 548 | if (cvmx_bootmem_desc->major_version != 3) { | ||
| 549 | cvmx_dprintf("ERROR: Incompatible bootmem descriptor version: " | ||
| 550 | "%d.%d at addr: %p\n", | ||
| 551 | (int)cvmx_bootmem_desc->major_version, | ||
| 552 | (int)cvmx_bootmem_desc->minor_version, | ||
| 553 | cvmx_bootmem_desc); | ||
| 554 | return 0; | ||
| 555 | } | ||
| 556 | #ifdef DEBUG | ||
| 557 | cvmx_dprintf("cvmx_bootmem_phy_named_block_free: %s\n", name); | ||
| 558 | #endif | ||
| 559 | |||
| 560 | /* | ||
| 561 | * Take lock here, as name lookup/block free/name free need to | ||
| 562 | * be atomic. | ||
| 563 | */ | ||
| 564 | cvmx_bootmem_lock(); | ||
| 565 | |||
| 566 | named_block_ptr = | ||
| 567 | cvmx_bootmem_phy_named_block_find(name, | ||
| 568 | CVMX_BOOTMEM_FLAG_NO_LOCKING); | ||
| 569 | if (named_block_ptr) { | ||
| 570 | #ifdef DEBUG | ||
| 571 | cvmx_dprintf("cvmx_bootmem_phy_named_block_free: " | ||
| 572 | "%s, base: 0x%llx, size: 0x%llx\n", | ||
| 573 | name, | ||
| 574 | (unsigned long long)named_block_ptr->base_addr, | ||
| 575 | (unsigned long long)named_block_ptr->size); | ||
| 576 | #endif | ||
| 577 | __cvmx_bootmem_phy_free(named_block_ptr->base_addr, | ||
| 578 | named_block_ptr->size, | ||
| 579 | CVMX_BOOTMEM_FLAG_NO_LOCKING); | ||
| 580 | named_block_ptr->size = 0; | ||
| 581 | /* Set size to zero to indicate block not used. */ | ||
| 582 | } | ||
| 583 | |||
| 584 | cvmx_bootmem_unlock(); | ||
| 585 | return named_block_ptr != NULL; /* 0 on failure, 1 on success */ | ||
| 586 | } | ||
diff --git a/arch/mips/cavium-octeon/executive/cvmx-l2c.c b/arch/mips/cavium-octeon/executive/cvmx-l2c.c new file mode 100644 index 000000000000..6abe56f1e097 --- /dev/null +++ b/arch/mips/cavium-octeon/executive/cvmx-l2c.c | |||
| @@ -0,0 +1,734 @@ | |||
| 1 | /***********************license start*************** | ||
| 2 | * Author: Cavium Networks | ||
| 3 | * | ||
| 4 | * Contact: support@caviumnetworks.com | ||
| 5 | * This file is part of the OCTEON SDK | ||
| 6 | * | ||
| 7 | * Copyright (c) 2003-2008 Cavium Networks | ||
| 8 | * | ||
| 9 | * This file is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License, Version 2, as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | * | ||
| 13 | * This file is distributed in the hope that it will be useful, but | ||
| 14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
| 15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
| 16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
| 17 | * details. | ||
| 18 | * | ||
| 19 | * You should have received a copy of the GNU General Public License | ||
| 20 | * along with this file; if not, write to the Free Software | ||
| 21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 22 | * or visit http://www.gnu.org/licenses/. | ||
| 23 | * | ||
| 24 | * This file may also be available under a different license from Cavium. | ||
| 25 | * Contact Cavium Networks for more information | ||
| 26 | ***********************license end**************************************/ | ||
| 27 | |||
| 28 | /* | ||
| 29 | * Implementation of the Level 2 Cache (L2C) control, measurement, and | ||
| 30 | * debugging facilities. | ||
| 31 | */ | ||
| 32 | |||
| 33 | #include <asm/octeon/cvmx.h> | ||
| 34 | #include <asm/octeon/cvmx-l2c.h> | ||
| 35 | #include <asm/octeon/cvmx-spinlock.h> | ||
| 36 | |||
| 37 | /* | ||
| 38 | * This spinlock is used internally to ensure that only one core is | ||
| 39 | * performing certain L2 operations at a time. | ||
| 40 | * | ||
| 41 | * NOTE: This only protects calls from within a single application - | ||
| 42 | * if multiple applications or operating systems are running, then it | ||
| 43 | * is up to the user program to coordinate between them. | ||
| 44 | */ | ||
| 45 | static cvmx_spinlock_t cvmx_l2c_spinlock; | ||
| 46 | |||
| 47 | static inline int l2_size_half(void) | ||
| 48 | { | ||
| 49 | uint64_t val = cvmx_read_csr(CVMX_L2D_FUS3); | ||
| 50 | return !!(val & (1ull << 34)); | ||
| 51 | } | ||
| 52 | |||
| 53 | int cvmx_l2c_get_core_way_partition(uint32_t core) | ||
| 54 | { | ||
| 55 | uint32_t field; | ||
| 56 | |||
| 57 | /* Validate the core number */ | ||
| 58 | if (core >= cvmx_octeon_num_cores()) | ||
| 59 | return -1; | ||
| 60 | |||
| 61 | /* | ||
| 62 | * Use the lower two bits of the coreNumber to determine the | ||
| 63 | * bit offset of the UMSK[] field in the L2C_SPAR register. | ||
| 64 | */ | ||
| 65 | field = (core & 0x3) * 8; | ||
| 66 | |||
| 67 | /* | ||
| 68 | * Return the UMSK[] field from the appropriate L2C_SPAR | ||
| 69 | * register based on the coreNumber. | ||
| 70 | */ | ||
| 71 | |||
| 72 | switch (core & 0xC) { | ||
| 73 | case 0x0: | ||
| 74 | return (cvmx_read_csr(CVMX_L2C_SPAR0) & (0xFF << field)) >> | ||
| 75 | field; | ||
| 76 | case 0x4: | ||
| 77 | return (cvmx_read_csr(CVMX_L2C_SPAR1) & (0xFF << field)) >> | ||
| 78 | field; | ||
| 79 | case 0x8: | ||
| 80 | return (cvmx_read_csr(CVMX_L2C_SPAR2) & (0xFF << field)) >> | ||
| 81 | field; | ||
| 82 | case 0xC: | ||
| 83 | return (cvmx_read_csr(CVMX_L2C_SPAR3) & (0xFF << field)) >> | ||
| 84 | field; | ||
| 85 | } | ||
| 86 | return 0; | ||
| 87 | } | ||
| 88 | |||
| 89 | int cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask) | ||
| 90 | { | ||
| 91 | uint32_t field; | ||
| 92 | uint32_t valid_mask; | ||
| 93 | |||
| 94 | valid_mask = (0x1 << cvmx_l2c_get_num_assoc()) - 1; | ||
| 95 | |||
| 96 | mask &= valid_mask; | ||
| 97 | |||
| 98 | /* A UMSK setting which blocks all L2C Ways is an error. */ | ||
| 99 | if (mask == valid_mask) | ||
| 100 | return -1; | ||
| 101 | |||
| 102 | /* Validate the core number */ | ||
| 103 | if (core >= cvmx_octeon_num_cores()) | ||
| 104 | return -1; | ||
| 105 | |||
| 106 | /* Check to make sure current mask & new mask don't block all ways */ | ||
| 107 | if (((mask | cvmx_l2c_get_core_way_partition(core)) & valid_mask) == | ||
| 108 | valid_mask) | ||
| 109 | return -1; | ||
| 110 | |||
| 111 | /* Use the lower two bits of core to determine the bit offset of the | ||
| 112 | * UMSK[] field in the L2C_SPAR register. | ||
| 113 | */ | ||
| 114 | field = (core & 0x3) * 8; | ||
| 115 | |||
| 116 | /* Assign the new mask setting to the UMSK[] field in the appropriate | ||
| 117 | * L2C_SPAR register based on the core_num. | ||
| 118 | * | ||
| 119 | */ | ||
| 120 | switch (core & 0xC) { | ||
| 121 | case 0x0: | ||
| 122 | cvmx_write_csr(CVMX_L2C_SPAR0, | ||
| 123 | (cvmx_read_csr(CVMX_L2C_SPAR0) & | ||
| 124 | ~(0xFF << field)) | mask << field); | ||
| 125 | break; | ||
| 126 | case 0x4: | ||
| 127 | cvmx_write_csr(CVMX_L2C_SPAR1, | ||
| 128 | (cvmx_read_csr(CVMX_L2C_SPAR1) & | ||
| 129 | ~(0xFF << field)) | mask << field); | ||
| 130 | break; | ||
| 131 | case 0x8: | ||
| 132 | cvmx_write_csr(CVMX_L2C_SPAR2, | ||
| 133 | (cvmx_read_csr(CVMX_L2C_SPAR2) & | ||
| 134 | ~(0xFF << field)) | mask << field); | ||
| 135 | break; | ||
| 136 | case 0xC: | ||
| 137 | cvmx_write_csr(CVMX_L2C_SPAR3, | ||
| 138 | (cvmx_read_csr(CVMX_L2C_SPAR3) & | ||
| 139 | ~(0xFF << field)) | mask << field); | ||
| 140 | break; | ||
| 141 | } | ||
| 142 | return 0; | ||
| 143 | } | ||
| 144 | |||
| 145 | int cvmx_l2c_set_hw_way_partition(uint32_t mask) | ||
| 146 | { | ||
| 147 | uint32_t valid_mask; | ||
| 148 | |||
| 149 | valid_mask = 0xff; | ||
| 150 | |||
| 151 | if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)) { | ||
| 152 | if (l2_size_half()) | ||
| 153 | valid_mask = 0xf; | ||
| 154 | } else if (l2_size_half()) | ||
| 155 | valid_mask = 0x3; | ||
| 156 | |||
| 157 | mask &= valid_mask; | ||
| 158 | |||
| 159 | /* A UMSK setting which blocks all L2C Ways is an error. */ | ||
| 160 | if (mask == valid_mask) | ||
| 161 | return -1; | ||
| 162 | /* Check to make sure current mask & new mask don't block all ways */ | ||
| 163 | if (((mask | cvmx_l2c_get_hw_way_partition()) & valid_mask) == | ||
| 164 | valid_mask) | ||
| 165 | return -1; | ||
| 166 | |||
| 167 | cvmx_write_csr(CVMX_L2C_SPAR4, | ||
| 168 | (cvmx_read_csr(CVMX_L2C_SPAR4) & ~0xFF) | mask); | ||
| 169 | return 0; | ||
| 170 | } | ||
| 171 | |||
| 172 | int cvmx_l2c_get_hw_way_partition(void) | ||
| 173 | { | ||
| 174 | return cvmx_read_csr(CVMX_L2C_SPAR4) & (0xFF); | ||
| 175 | } | ||
| 176 | |||
| 177 | void cvmx_l2c_config_perf(uint32_t counter, enum cvmx_l2c_event event, | ||
| 178 | uint32_t clear_on_read) | ||
| 179 | { | ||
| 180 | union cvmx_l2c_pfctl pfctl; | ||
| 181 | |||
| 182 | pfctl.u64 = cvmx_read_csr(CVMX_L2C_PFCTL); | ||
| 183 | |||
| 184 | switch (counter) { | ||
| 185 | case 0: | ||
| 186 | pfctl.s.cnt0sel = event; | ||
| 187 | pfctl.s.cnt0ena = 1; | ||
| 188 | if (!cvmx_octeon_is_pass1()) | ||
| 189 | pfctl.s.cnt0rdclr = clear_on_read; | ||
| 190 | break; | ||
| 191 | case 1: | ||
| 192 | pfctl.s.cnt1sel = event; | ||
| 193 | pfctl.s.cnt1ena = 1; | ||
| 194 | if (!cvmx_octeon_is_pass1()) | ||
| 195 | pfctl.s.cnt1rdclr = clear_on_read; | ||
| 196 | break; | ||
| 197 | case 2: | ||
| 198 | pfctl.s.cnt2sel = event; | ||
| 199 | pfctl.s.cnt2ena = 1; | ||
| 200 | if (!cvmx_octeon_is_pass1()) | ||
| 201 | pfctl.s.cnt2rdclr = clear_on_read; | ||
| 202 | break; | ||
| 203 | case 3: | ||
| 204 | default: | ||
| 205 | pfctl.s.cnt3sel = event; | ||
| 206 | pfctl.s.cnt3ena = 1; | ||
| 207 | if (!cvmx_octeon_is_pass1()) | ||
| 208 | pfctl.s.cnt3rdclr = clear_on_read; | ||
| 209 | break; | ||
| 210 | } | ||
| 211 | |||
| 212 | cvmx_write_csr(CVMX_L2C_PFCTL, pfctl.u64); | ||
| 213 | } | ||
| 214 | |||
| 215 | uint64_t cvmx_l2c_read_perf(uint32_t counter) | ||
| 216 | { | ||
| 217 | switch (counter) { | ||
| 218 | case 0: | ||
| 219 | return cvmx_read_csr(CVMX_L2C_PFC0); | ||
| 220 | case 1: | ||
| 221 | return cvmx_read_csr(CVMX_L2C_PFC1); | ||
| 222 | case 2: | ||
| 223 | return cvmx_read_csr(CVMX_L2C_PFC2); | ||
| 224 | case 3: | ||
| 225 | default: | ||
| 226 | return cvmx_read_csr(CVMX_L2C_PFC3); | ||
| 227 | } | ||
| 228 | } | ||
| 229 | |||
| 230 | /** | ||
| 231 | * @INTERNAL | ||
| 232 | * Helper function use to fault in cache lines for L2 cache locking | ||
| 233 | * | ||
| 234 | * @addr: Address of base of memory region to read into L2 cache | ||
| 235 | * @len: Length (in bytes) of region to fault in | ||
| 236 | */ | ||
| 237 | static void fault_in(uint64_t addr, int len) | ||
| 238 | { | ||
| 239 | volatile char *ptr; | ||
| 240 | volatile char dummy; | ||
| 241 | /* | ||
| 242 | * Adjust addr and length so we get all cache lines even for | ||
| 243 | * small ranges spanning two cache lines | ||
| 244 | */ | ||
| 245 | len += addr & CVMX_CACHE_LINE_MASK; | ||
| 246 | addr &= ~CVMX_CACHE_LINE_MASK; | ||
| 247 | ptr = (volatile char *)cvmx_phys_to_ptr(addr); | ||
| 248 | /* | ||
| 249 | * Invalidate L1 cache to make sure all loads result in data | ||
| 250 | * being in L2. | ||
| 251 | */ | ||
| 252 | CVMX_DCACHE_INVALIDATE; | ||
| 253 | while (len > 0) { | ||
| 254 | dummy += *ptr; | ||
| 255 | len -= CVMX_CACHE_LINE_SIZE; | ||
| 256 | ptr += CVMX_CACHE_LINE_SIZE; | ||
| 257 | } | ||
| 258 | } | ||
| 259 | |||
| 260 | int cvmx_l2c_lock_line(uint64_t addr) | ||
| 261 | { | ||
| 262 | int retval = 0; | ||
| 263 | union cvmx_l2c_dbg l2cdbg; | ||
| 264 | union cvmx_l2c_lckbase lckbase; | ||
| 265 | union cvmx_l2c_lckoff lckoff; | ||
| 266 | union cvmx_l2t_err l2t_err; | ||
| 267 | l2cdbg.u64 = 0; | ||
| 268 | lckbase.u64 = 0; | ||
| 269 | lckoff.u64 = 0; | ||
| 270 | |||
| 271 | cvmx_spinlock_lock(&cvmx_l2c_spinlock); | ||
| 272 | |||
| 273 | /* Clear l2t error bits if set */ | ||
| 274 | l2t_err.u64 = cvmx_read_csr(CVMX_L2T_ERR); | ||
| 275 | l2t_err.s.lckerr = 1; | ||
| 276 | l2t_err.s.lckerr2 = 1; | ||
| 277 | cvmx_write_csr(CVMX_L2T_ERR, l2t_err.u64); | ||
| 278 | |||
| 279 | addr &= ~CVMX_CACHE_LINE_MASK; | ||
| 280 | |||
| 281 | /* Set this core as debug core */ | ||
| 282 | l2cdbg.s.ppnum = cvmx_get_core_num(); | ||
| 283 | CVMX_SYNC; | ||
| 284 | cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64); | ||
| 285 | cvmx_read_csr(CVMX_L2C_DBG); | ||
| 286 | |||
| 287 | lckoff.s.lck_offset = 0; /* Only lock 1 line at a time */ | ||
| 288 | cvmx_write_csr(CVMX_L2C_LCKOFF, lckoff.u64); | ||
| 289 | cvmx_read_csr(CVMX_L2C_LCKOFF); | ||
| 290 | |||
| 291 | if (((union cvmx_l2c_cfg) (cvmx_read_csr(CVMX_L2C_CFG))).s.idxalias) { | ||
| 292 | int alias_shift = | ||
| 293 | CVMX_L2C_IDX_ADDR_SHIFT + 2 * CVMX_L2_SET_BITS - 1; | ||
| 294 | uint64_t addr_tmp = | ||
| 295 | addr ^ (addr & ((1 << alias_shift) - 1)) >> | ||
| 296 | CVMX_L2_SET_BITS; | ||
| 297 | lckbase.s.lck_base = addr_tmp >> 7; | ||
| 298 | } else { | ||
| 299 | lckbase.s.lck_base = addr >> 7; | ||
| 300 | } | ||
| 301 | |||
| 302 | lckbase.s.lck_ena = 1; | ||
| 303 | cvmx_write_csr(CVMX_L2C_LCKBASE, lckbase.u64); | ||
| 304 | cvmx_read_csr(CVMX_L2C_LCKBASE); /* Make sure it gets there */ | ||
| 305 | |||
| 306 | fault_in(addr, CVMX_CACHE_LINE_SIZE); | ||
| 307 | |||
| 308 | lckbase.s.lck_ena = 0; | ||
| 309 | cvmx_write_csr(CVMX_L2C_LCKBASE, lckbase.u64); | ||
| 310 | cvmx_read_csr(CVMX_L2C_LCKBASE); /* Make sure it gets there */ | ||
| 311 | |||
| 312 | /* Stop being debug core */ | ||
| 313 | cvmx_write_csr(CVMX_L2C_DBG, 0); | ||
| 314 | cvmx_read_csr(CVMX_L2C_DBG); | ||
| 315 | |||
| 316 | l2t_err.u64 = cvmx_read_csr(CVMX_L2T_ERR); | ||
| 317 | if (l2t_err.s.lckerr || l2t_err.s.lckerr2) | ||
| 318 | retval = 1; /* We were unable to lock the line */ | ||
| 319 | |||
| 320 | cvmx_spinlock_unlock(&cvmx_l2c_spinlock); | ||
| 321 | |||
| 322 | return retval; | ||
| 323 | } | ||
| 324 | |||
| 325 | int cvmx_l2c_lock_mem_region(uint64_t start, uint64_t len) | ||
| 326 | { | ||
| 327 | int retval = 0; | ||
| 328 | |||
| 329 | /* Round start/end to cache line boundaries */ | ||
| 330 | len += start & CVMX_CACHE_LINE_MASK; | ||
| 331 | start &= ~CVMX_CACHE_LINE_MASK; | ||
| 332 | len = (len + CVMX_CACHE_LINE_MASK) & ~CVMX_CACHE_LINE_MASK; | ||
| 333 | |||
| 334 | while (len) { | ||
| 335 | retval += cvmx_l2c_lock_line(start); | ||
| 336 | start += CVMX_CACHE_LINE_SIZE; | ||
| 337 | len -= CVMX_CACHE_LINE_SIZE; | ||
| 338 | } | ||
| 339 | |||
| 340 | return retval; | ||
| 341 | } | ||
| 342 | |||
| 343 | void cvmx_l2c_flush(void) | ||
| 344 | { | ||
| 345 | uint64_t assoc, set; | ||
| 346 | uint64_t n_assoc, n_set; | ||
| 347 | union cvmx_l2c_dbg l2cdbg; | ||
| 348 | |||
| 349 | cvmx_spinlock_lock(&cvmx_l2c_spinlock); | ||
| 350 | |||
| 351 | l2cdbg.u64 = 0; | ||
| 352 | if (!OCTEON_IS_MODEL(OCTEON_CN30XX)) | ||
| 353 | l2cdbg.s.ppnum = cvmx_get_core_num(); | ||
| 354 | l2cdbg.s.finv = 1; | ||
| 355 | n_set = CVMX_L2_SETS; | ||
| 356 | n_assoc = l2_size_half() ? (CVMX_L2_ASSOC / 2) : CVMX_L2_ASSOC; | ||
| 357 | for (set = 0; set < n_set; set++) { | ||
| 358 | for (assoc = 0; assoc < n_assoc; assoc++) { | ||
| 359 | l2cdbg.s.set = assoc; | ||
| 360 | /* Enter debug mode, and make sure all other | ||
| 361 | ** writes complete before we enter debug | ||
| 362 | ** mode */ | ||
| 363 | CVMX_SYNCW; | ||
| 364 | cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64); | ||
| 365 | cvmx_read_csr(CVMX_L2C_DBG); | ||
| 366 | |||
| 367 | CVMX_PREPARE_FOR_STORE(CVMX_ADD_SEG | ||
| 368 | (CVMX_MIPS_SPACE_XKPHYS, | ||
| 369 | set * CVMX_CACHE_LINE_SIZE), 0); | ||
| 370 | CVMX_SYNCW; /* Push STF out to L2 */ | ||
| 371 | /* Exit debug mode */ | ||
| 372 | CVMX_SYNC; | ||
| 373 | cvmx_write_csr(CVMX_L2C_DBG, 0); | ||
| 374 | cvmx_read_csr(CVMX_L2C_DBG); | ||
| 375 | } | ||
| 376 | } | ||
| 377 | |||
| 378 | cvmx_spinlock_unlock(&cvmx_l2c_spinlock); | ||
| 379 | } | ||
| 380 | |||
| 381 | int cvmx_l2c_unlock_line(uint64_t address) | ||
| 382 | { | ||
| 383 | int assoc; | ||
| 384 | union cvmx_l2c_tag tag; | ||
| 385 | union cvmx_l2c_dbg l2cdbg; | ||
| 386 | uint32_t tag_addr; | ||
| 387 | |||
| 388 | uint32_t index = cvmx_l2c_address_to_index(address); | ||
| 389 | |||
| 390 | cvmx_spinlock_lock(&cvmx_l2c_spinlock); | ||
| 391 | /* Compute portion of address that is stored in tag */ | ||
| 392 | tag_addr = | ||
| 393 | ((address >> CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) & | ||
| 394 | ((1 << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) - 1)); | ||
| 395 | for (assoc = 0; assoc < CVMX_L2_ASSOC; assoc++) { | ||
| 396 | tag = cvmx_get_l2c_tag(assoc, index); | ||
| 397 | |||
| 398 | if (tag.s.V && (tag.s.addr == tag_addr)) { | ||
| 399 | l2cdbg.u64 = 0; | ||
| 400 | l2cdbg.s.ppnum = cvmx_get_core_num(); | ||
| 401 | l2cdbg.s.set = assoc; | ||
| 402 | l2cdbg.s.finv = 1; | ||
| 403 | |||
| 404 | CVMX_SYNC; | ||
| 405 | /* Enter debug mode */ | ||
| 406 | cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64); | ||
| 407 | cvmx_read_csr(CVMX_L2C_DBG); | ||
| 408 | |||
| 409 | CVMX_PREPARE_FOR_STORE(CVMX_ADD_SEG | ||
| 410 | (CVMX_MIPS_SPACE_XKPHYS, | ||
| 411 | address), 0); | ||
| 412 | CVMX_SYNC; | ||
| 413 | /* Exit debug mode */ | ||
| 414 | cvmx_write_csr(CVMX_L2C_DBG, 0); | ||
| 415 | cvmx_read_csr(CVMX_L2C_DBG); | ||
| 416 | cvmx_spinlock_unlock(&cvmx_l2c_spinlock); | ||
| 417 | return tag.s.L; | ||
| 418 | } | ||
| 419 | } | ||
| 420 | cvmx_spinlock_unlock(&cvmx_l2c_spinlock); | ||
| 421 | return 0; | ||
| 422 | } | ||
| 423 | |||
| 424 | int cvmx_l2c_unlock_mem_region(uint64_t start, uint64_t len) | ||
| 425 | { | ||
| 426 | int num_unlocked = 0; | ||
| 427 | /* Round start/end to cache line boundaries */ | ||
| 428 | len += start & CVMX_CACHE_LINE_MASK; | ||
| 429 | start &= ~CVMX_CACHE_LINE_MASK; | ||
| 430 | len = (len + CVMX_CACHE_LINE_MASK) & ~CVMX_CACHE_LINE_MASK; | ||
| 431 | while (len > 0) { | ||
| 432 | num_unlocked += cvmx_l2c_unlock_line(start); | ||
| 433 | start += CVMX_CACHE_LINE_SIZE; | ||
| 434 | len -= CVMX_CACHE_LINE_SIZE; | ||
| 435 | } | ||
| 436 | |||
| 437 | return num_unlocked; | ||
| 438 | } | ||
| 439 | |||
| 440 | /* | ||
| 441 | * Internal l2c tag types. These are converted to a generic structure | ||
| 442 | * that can be used on all chips. | ||
| 443 | */ | ||
| 444 | union __cvmx_l2c_tag { | ||
| 445 | uint64_t u64; | ||
| 446 | struct cvmx_l2c_tag_cn50xx { | ||
| 447 | uint64_t reserved:40; | ||
| 448 | uint64_t V:1; /* Line valid */ | ||
| 449 | uint64_t D:1; /* Line dirty */ | ||
| 450 | uint64_t L:1; /* Line locked */ | ||
| 451 | uint64_t U:1; /* Use, LRU eviction */ | ||
| 452 | uint64_t addr:20; /* Phys mem addr (33..14) */ | ||
| 453 | } cn50xx; | ||
| 454 | struct cvmx_l2c_tag_cn30xx { | ||
| 455 | uint64_t reserved:41; | ||
| 456 | uint64_t V:1; /* Line valid */ | ||
| 457 | uint64_t D:1; /* Line dirty */ | ||
| 458 | uint64_t L:1; /* Line locked */ | ||
| 459 | uint64_t U:1; /* Use, LRU eviction */ | ||
| 460 | uint64_t addr:19; /* Phys mem addr (33..15) */ | ||
| 461 | } cn30xx; | ||
| 462 | struct cvmx_l2c_tag_cn31xx { | ||
| 463 | uint64_t reserved:42; | ||
| 464 | uint64_t V:1; /* Line valid */ | ||
| 465 | uint64_t D:1; /* Line dirty */ | ||
| 466 | uint64_t L:1; /* Line locked */ | ||
| 467 | uint64_t U:1; /* Use, LRU eviction */ | ||
| 468 | uint64_t addr:18; /* Phys mem addr (33..16) */ | ||
| 469 | } cn31xx; | ||
| 470 | struct cvmx_l2c_tag_cn38xx { | ||
| 471 | uint64_t reserved:43; | ||
| 472 | uint64_t V:1; /* Line valid */ | ||
| 473 | uint64_t D:1; /* Line dirty */ | ||
| 474 | uint64_t L:1; /* Line locked */ | ||
| 475 | uint64_t U:1; /* Use, LRU eviction */ | ||
| 476 | uint64_t addr:17; /* Phys mem addr (33..17) */ | ||
| 477 | } cn38xx; | ||
| 478 | struct cvmx_l2c_tag_cn58xx { | ||
| 479 | uint64_t reserved:44; | ||
| 480 | uint64_t V:1; /* Line valid */ | ||
| 481 | uint64_t D:1; /* Line dirty */ | ||
| 482 | uint64_t L:1; /* Line locked */ | ||
| 483 | uint64_t U:1; /* Use, LRU eviction */ | ||
| 484 | uint64_t addr:16; /* Phys mem addr (33..18) */ | ||
| 485 | } cn58xx; | ||
| 486 | struct cvmx_l2c_tag_cn58xx cn56xx; /* 2048 sets */ | ||
| 487 | struct cvmx_l2c_tag_cn31xx cn52xx; /* 512 sets */ | ||
| 488 | }; | ||
| 489 | |||
| 490 | /** | ||
| 491 | * @INTERNAL | ||
| 492 | * Function to read a L2C tag. This code make the current core | ||
| 493 | * the 'debug core' for the L2. This code must only be executed by | ||
| 494 | * 1 core at a time. | ||
| 495 | * | ||
| 496 | * @assoc: Association (way) of the tag to dump | ||
| 497 | * @index: Index of the cacheline | ||
| 498 | * | ||
| 499 | * Returns The Octeon model specific tag structure. This is | ||
| 500 | * translated by a wrapper function to a generic form that is | ||
| 501 | * easier for applications to use. | ||
| 502 | */ | ||
| 503 | static union __cvmx_l2c_tag __read_l2_tag(uint64_t assoc, uint64_t index) | ||
| 504 | { | ||
| 505 | |||
| 506 | uint64_t debug_tag_addr = (((1ULL << 63) | (index << 7)) + 96); | ||
| 507 | uint64_t core = cvmx_get_core_num(); | ||
| 508 | union __cvmx_l2c_tag tag_val; | ||
| 509 | uint64_t dbg_addr = CVMX_L2C_DBG; | ||
| 510 | unsigned long flags; | ||
| 511 | |||
| 512 | union cvmx_l2c_dbg debug_val; | ||
| 513 | debug_val.u64 = 0; | ||
| 514 | /* | ||
| 515 | * For low core count parts, the core number is always small enough | ||
| 516 | * to stay in the correct field and not set any reserved bits. | ||
| 517 | */ | ||
| 518 | debug_val.s.ppnum = core; | ||
| 519 | debug_val.s.l2t = 1; | ||
| 520 | debug_val.s.set = assoc; | ||
| 521 | /* | ||
| 522 | * Make sure core is quiet (no prefetches, etc.) before | ||
| 523 | * entering debug mode. | ||
| 524 | */ | ||
| 525 | CVMX_SYNC; | ||
| 526 | /* Flush L1 to make sure debug load misses L1 */ | ||
| 527 | CVMX_DCACHE_INVALIDATE; | ||
| 528 | |||
| 529 | local_irq_save(flags); | ||
| 530 | |||
| 531 | /* | ||
| 532 | * The following must be done in assembly as when in debug | ||
| 533 | * mode all data loads from L2 return special debug data, not | ||
| 534 | * normal memory contents. Also, interrupts must be | ||
| 535 | * disabled, since if an interrupt occurs while in debug mode | ||
| 536 | * the ISR will get debug data from all its memory reads | ||
| 537 | * instead of the contents of memory | ||
| 538 | */ | ||
| 539 | |||
| 540 | asm volatile (".set push \n" | ||
| 541 | " .set mips64 \n" | ||
| 542 | " .set noreorder \n" | ||
| 543 | /* Enter debug mode, wait for store */ | ||
| 544 | " sd %[dbg_val], 0(%[dbg_addr]) \n" | ||
| 545 | " ld $0, 0(%[dbg_addr]) \n" | ||
| 546 | /* Read L2C tag data */ | ||
| 547 | " ld %[tag_val], 0(%[tag_addr]) \n" | ||
| 548 | /* Exit debug mode, wait for store */ | ||
| 549 | " sd $0, 0(%[dbg_addr]) \n" | ||
| 550 | " ld $0, 0(%[dbg_addr]) \n" | ||
| 551 | /* Invalidate dcache to discard debug data */ | ||
| 552 | " cache 9, 0($0) \n" | ||
| 553 | " .set pop" : | ||
| 554 | [tag_val] "=r"(tag_val.u64) : [dbg_addr] "r"(dbg_addr), | ||
| 555 | [dbg_val] "r"(debug_val.u64), | ||
| 556 | [tag_addr] "r"(debug_tag_addr) : "memory"); | ||
| 557 | |||
| 558 | local_irq_restore(flags); | ||
| 559 | return tag_val; | ||
| 560 | |||
| 561 | } | ||
| 562 | |||
| 563 | union cvmx_l2c_tag cvmx_l2c_get_tag(uint32_t association, uint32_t index) | ||
| 564 | { | ||
| 565 | union __cvmx_l2c_tag tmp_tag; | ||
| 566 | union cvmx_l2c_tag tag; | ||
| 567 | tag.u64 = 0; | ||
| 568 | |||
| 569 | if ((int)association >= cvmx_l2c_get_num_assoc()) { | ||
| 570 | cvmx_dprintf | ||
| 571 | ("ERROR: cvmx_get_l2c_tag association out of range\n"); | ||
| 572 | return tag; | ||
| 573 | } | ||
| 574 | if ((int)index >= cvmx_l2c_get_num_sets()) { | ||
| 575 | cvmx_dprintf("ERROR: cvmx_get_l2c_tag " | ||
| 576 | "index out of range (arg: %d, max: %d\n", | ||
| 577 | index, cvmx_l2c_get_num_sets()); | ||
| 578 | return tag; | ||
| 579 | } | ||
| 580 | /* __read_l2_tag is intended for internal use only */ | ||
| 581 | tmp_tag = __read_l2_tag(association, index); | ||
| 582 | |||
| 583 | /* | ||
| 584 | * Convert all tag structure types to generic version, as it | ||
| 585 | * can represent all models. | ||
| 586 | */ | ||
| 587 | if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)) { | ||
| 588 | tag.s.V = tmp_tag.cn58xx.V; | ||
| 589 | tag.s.D = tmp_tag.cn58xx.D; | ||
| 590 | tag.s.L = tmp_tag.cn58xx.L; | ||
| 591 | tag.s.U = tmp_tag.cn58xx.U; | ||
| 592 | tag.s.addr = tmp_tag.cn58xx.addr; | ||
| 593 | } else if (OCTEON_IS_MODEL(OCTEON_CN38XX)) { | ||
| 594 | tag.s.V = tmp_tag.cn38xx.V; | ||
| 595 | tag.s.D = tmp_tag.cn38xx.D; | ||
| 596 | tag.s.L = tmp_tag.cn38xx.L; | ||
| 597 | tag.s.U = tmp_tag.cn38xx.U; | ||
| 598 | tag.s.addr = tmp_tag.cn38xx.addr; | ||
| 599 | } else if (OCTEON_IS_MODEL(OCTEON_CN31XX) | ||
| 600 | || OCTEON_IS_MODEL(OCTEON_CN52XX)) { | ||
| 601 | tag.s.V = tmp_tag.cn31xx.V; | ||
| 602 | tag.s.D = tmp_tag.cn31xx.D; | ||
| 603 | tag.s.L = tmp_tag.cn31xx.L; | ||
| 604 | tag.s.U = tmp_tag.cn31xx.U; | ||
| 605 | tag.s.addr = tmp_tag.cn31xx.addr; | ||
| 606 | } else if (OCTEON_IS_MODEL(OCTEON_CN30XX)) { | ||
| 607 | tag.s.V = tmp_tag.cn30xx.V; | ||
| 608 | tag.s.D = tmp_tag.cn30xx.D; | ||
| 609 | tag.s.L = tmp_tag.cn30xx.L; | ||
| 610 | tag.s.U = tmp_tag.cn30xx.U; | ||
| 611 | tag.s.addr = tmp_tag.cn30xx.addr; | ||
| 612 | } else if (OCTEON_IS_MODEL(OCTEON_CN50XX)) { | ||
| 613 | tag.s.V = tmp_tag.cn50xx.V; | ||
| 614 | tag.s.D = tmp_tag.cn50xx.D; | ||
| 615 | tag.s.L = tmp_tag.cn50xx.L; | ||
| 616 | tag.s.U = tmp_tag.cn50xx.U; | ||
| 617 | tag.s.addr = tmp_tag.cn50xx.addr; | ||
| 618 | } else { | ||
| 619 | cvmx_dprintf("Unsupported OCTEON Model in %s\n", __func__); | ||
| 620 | } | ||
| 621 | |||
| 622 | return tag; | ||
| 623 | } | ||
| 624 | |||
| 625 | uint32_t cvmx_l2c_address_to_index(uint64_t addr) | ||
| 626 | { | ||
| 627 | uint64_t idx = addr >> CVMX_L2C_IDX_ADDR_SHIFT; | ||
| 628 | union cvmx_l2c_cfg l2c_cfg; | ||
| 629 | l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG); | ||
| 630 | |||
| 631 | if (l2c_cfg.s.idxalias) { | ||
| 632 | idx ^= | ||
| 633 | ((addr & CVMX_L2C_ALIAS_MASK) >> | ||
| 634 | CVMX_L2C_TAG_ADDR_ALIAS_SHIFT); | ||
| 635 | } | ||
| 636 | idx &= CVMX_L2C_IDX_MASK; | ||
| 637 | return idx; | ||
| 638 | } | ||
| 639 | |||
| 640 | int cvmx_l2c_get_cache_size_bytes(void) | ||
| 641 | { | ||
| 642 | return cvmx_l2c_get_num_sets() * cvmx_l2c_get_num_assoc() * | ||
| 643 | CVMX_CACHE_LINE_SIZE; | ||
| 644 | } | ||
| 645 | |||
| 646 | /** | ||
| 647 | * Return log base 2 of the number of sets in the L2 cache | ||
| 648 | * Returns | ||
| 649 | */ | ||
| 650 | int cvmx_l2c_get_set_bits(void) | ||
| 651 | { | ||
| 652 | int l2_set_bits; | ||
| 653 | if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)) | ||
| 654 | l2_set_bits = 11; /* 2048 sets */ | ||
| 655 | else if (OCTEON_IS_MODEL(OCTEON_CN38XX)) | ||
| 656 | l2_set_bits = 10; /* 1024 sets */ | ||
| 657 | else if (OCTEON_IS_MODEL(OCTEON_CN31XX) | ||
| 658 | || OCTEON_IS_MODEL(OCTEON_CN52XX)) | ||
| 659 | l2_set_bits = 9; /* 512 sets */ | ||
| 660 | else if (OCTEON_IS_MODEL(OCTEON_CN30XX)) | ||
| 661 | l2_set_bits = 8; /* 256 sets */ | ||
| 662 | else if (OCTEON_IS_MODEL(OCTEON_CN50XX)) | ||
| 663 | l2_set_bits = 7; /* 128 sets */ | ||
| 664 | else { | ||
| 665 | cvmx_dprintf("Unsupported OCTEON Model in %s\n", __func__); | ||
| 666 | l2_set_bits = 11; /* 2048 sets */ | ||
| 667 | } | ||
| 668 | return l2_set_bits; | ||
| 669 | |||
| 670 | } | ||
| 671 | |||
| 672 | /* Return the number of sets in the L2 Cache */ | ||
| 673 | int cvmx_l2c_get_num_sets(void) | ||
| 674 | { | ||
| 675 | return 1 << cvmx_l2c_get_set_bits(); | ||
| 676 | } | ||
| 677 | |||
| 678 | /* Return the number of associations in the L2 Cache */ | ||
| 679 | int cvmx_l2c_get_num_assoc(void) | ||
| 680 | { | ||
| 681 | int l2_assoc; | ||
| 682 | if (OCTEON_IS_MODEL(OCTEON_CN56XX) || | ||
| 683 | OCTEON_IS_MODEL(OCTEON_CN52XX) || | ||
| 684 | OCTEON_IS_MODEL(OCTEON_CN58XX) || | ||
| 685 | OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)) | ||
| 686 | l2_assoc = 8; | ||
| 687 | else if (OCTEON_IS_MODEL(OCTEON_CN31XX) || | ||
| 688 | OCTEON_IS_MODEL(OCTEON_CN30XX)) | ||
| 689 | l2_assoc = 4; | ||
| 690 | else { | ||
| 691 | cvmx_dprintf("Unsupported OCTEON Model in %s\n", __func__); | ||
| 692 | l2_assoc = 8; | ||
| 693 | } | ||
| 694 | |||
| 695 | /* Check to see if part of the cache is disabled */ | ||
| 696 | if (cvmx_fuse_read(265)) | ||
| 697 | l2_assoc = l2_assoc >> 2; | ||
| 698 | else if (cvmx_fuse_read(264)) | ||
| 699 | l2_assoc = l2_assoc >> 1; | ||
| 700 | |||
| 701 | return l2_assoc; | ||
| 702 | } | ||
| 703 | |||
| 704 | /** | ||
| 705 | * Flush a line from the L2 cache | ||
| 706 | * This should only be called from one core at a time, as this routine | ||
| 707 | * sets the core to the 'debug' core in order to flush the line. | ||
| 708 | * | ||
| 709 | * @assoc: Association (or way) to flush | ||
| 710 | * @index: Index to flush | ||
| 711 | */ | ||
| 712 | void cvmx_l2c_flush_line(uint32_t assoc, uint32_t index) | ||
| 713 | { | ||
| 714 | union cvmx_l2c_dbg l2cdbg; | ||
| 715 | |||
| 716 | l2cdbg.u64 = 0; | ||
| 717 | l2cdbg.s.ppnum = cvmx_get_core_num(); | ||
| 718 | l2cdbg.s.finv = 1; | ||
| 719 | |||
| 720 | l2cdbg.s.set = assoc; | ||
| 721 | /* | ||
| 722 | * Enter debug mode, and make sure all other writes complete | ||
| 723 | * before we enter debug mode. | ||
| 724 | */ | ||
| 725 | asm volatile ("sync" : : : "memory"); | ||
| 726 | cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64); | ||
| 727 | cvmx_read_csr(CVMX_L2C_DBG); | ||
| 728 | |||
| 729 | CVMX_PREPARE_FOR_STORE(((1ULL << 63) + (index) * 128), 0); | ||
| 730 | /* Exit debug mode */ | ||
| 731 | asm volatile ("sync" : : : "memory"); | ||
| 732 | cvmx_write_csr(CVMX_L2C_DBG, 0); | ||
| 733 | cvmx_read_csr(CVMX_L2C_DBG); | ||
| 734 | } | ||
diff --git a/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c b/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c new file mode 100644 index 000000000000..4812370706a1 --- /dev/null +++ b/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c | |||
| @@ -0,0 +1,116 @@ | |||
| 1 | /***********************license start*************** | ||
| 2 | * Author: Cavium Networks | ||
| 3 | * | ||
| 4 | * Contact: support@caviumnetworks.com | ||
| 5 | * This file is part of the OCTEON SDK | ||
| 6 | * | ||
| 7 | * Copyright (c) 2003-2008 Cavium Networks | ||
| 8 | * | ||
| 9 | * This file is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License, Version 2, as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | * | ||
| 13 | * This file is distributed in the hope that it will be useful, but | ||
| 14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
| 15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
| 16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
| 17 | * details. | ||
| 18 | * | ||
| 19 | * You should have received a copy of the GNU General Public License | ||
| 20 | * along with this file; if not, write to the Free Software | ||
| 21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 22 | * or visit http://www.gnu.org/licenses/. | ||
| 23 | * | ||
| 24 | * This file may also be available under a different license from Cavium. | ||
| 25 | * Contact Cavium Networks for more information | ||
| 26 | ***********************license end**************************************/ | ||
| 27 | |||
| 28 | /* | ||
| 29 | * This module provides system/board/application information obtained | ||
| 30 | * by the bootloader. | ||
| 31 | */ | ||
| 32 | |||
| 33 | #include <asm/octeon/cvmx.h> | ||
| 34 | #include <asm/octeon/cvmx-spinlock.h> | ||
| 35 | #include <asm/octeon/cvmx-sysinfo.h> | ||
| 36 | |||
| 37 | /** | ||
| 38 | * This structure defines the private state maintained by sysinfo module. | ||
| 39 | * | ||
| 40 | */ | ||
| 41 | static struct { | ||
| 42 | struct cvmx_sysinfo sysinfo; /* system information */ | ||
| 43 | cvmx_spinlock_t lock; /* mutex spinlock */ | ||
| 44 | |||
| 45 | } state = { | ||
| 46 | .lock = CVMX_SPINLOCK_UNLOCKED_INITIALIZER | ||
| 47 | }; | ||
| 48 | |||
| 49 | |||
| 50 | /* | ||
| 51 | * Global variables that define the min/max of the memory region set | ||
| 52 | * up for 32 bit userspace access. | ||
| 53 | */ | ||
| 54 | uint64_t linux_mem32_min; | ||
| 55 | uint64_t linux_mem32_max; | ||
| 56 | uint64_t linux_mem32_wired; | ||
| 57 | uint64_t linux_mem32_offset; | ||
| 58 | |||
| 59 | /** | ||
| 60 | * This function returns the application information as obtained | ||
| 61 | * by the bootloader. This provides the core mask of the cores | ||
| 62 | * running the same application image, as well as the physical | ||
| 63 | * memory regions available to the core. | ||
| 64 | * | ||
| 65 | * Returns Pointer to the boot information structure | ||
| 66 | * | ||
| 67 | */ | ||
| 68 | struct cvmx_sysinfo *cvmx_sysinfo_get(void) | ||
| 69 | { | ||
| 70 | return &(state.sysinfo); | ||
| 71 | } | ||
| 72 | |||
| 73 | /** | ||
| 74 | * This function is used in non-simple executive environments (such as | ||
| 75 | * Linux kernel, u-boot, etc.) to configure the minimal fields that | ||
| 76 | * are required to use simple executive files directly. | ||
| 77 | * | ||
| 78 | * Locking (if required) must be handled outside of this | ||
| 79 | * function | ||
| 80 | * | ||
| 81 | * @phy_mem_desc_ptr: | ||
| 82 | * Pointer to global physical memory descriptor | ||
| 83 | * (bootmem descriptor) @board_type: Octeon board | ||
| 84 | * type enumeration | ||
| 85 | * | ||
| 86 | * @board_rev_major: | ||
| 87 | * Board major revision | ||
| 88 | * @board_rev_minor: | ||
| 89 | * Board minor revision | ||
| 90 | * @cpu_clock_hz: | ||
| 91 | * CPU clock freqency in hertz | ||
| 92 | * | ||
| 93 | * Returns 0: Failure | ||
| 94 | * 1: success | ||
| 95 | */ | ||
| 96 | int cvmx_sysinfo_minimal_initialize(void *phy_mem_desc_ptr, | ||
| 97 | uint16_t board_type, | ||
| 98 | uint8_t board_rev_major, | ||
| 99 | uint8_t board_rev_minor, | ||
| 100 | uint32_t cpu_clock_hz) | ||
| 101 | { | ||
| 102 | |||
| 103 | /* The sysinfo structure was already initialized */ | ||
| 104 | if (state.sysinfo.board_type) | ||
| 105 | return 0; | ||
| 106 | |||
| 107 | memset(&(state.sysinfo), 0x0, sizeof(state.sysinfo)); | ||
| 108 | state.sysinfo.phy_mem_desc_ptr = phy_mem_desc_ptr; | ||
| 109 | state.sysinfo.board_type = board_type; | ||
| 110 | state.sysinfo.board_rev_major = board_rev_major; | ||
| 111 | state.sysinfo.board_rev_minor = board_rev_minor; | ||
| 112 | state.sysinfo.cpu_clock_hz = cpu_clock_hz; | ||
| 113 | |||
| 114 | return 1; | ||
| 115 | } | ||
| 116 | |||
diff --git a/arch/mips/cavium-octeon/executive/octeon-model.c b/arch/mips/cavium-octeon/executive/octeon-model.c new file mode 100644 index 000000000000..9afc3794ed1b --- /dev/null +++ b/arch/mips/cavium-octeon/executive/octeon-model.c | |||
| @@ -0,0 +1,358 @@ | |||
| 1 | /***********************license start*************** | ||
| 2 | * Author: Cavium Networks | ||
| 3 | * | ||
| 4 | * Contact: support@caviumnetworks.com | ||
| 5 | * This file is part of the OCTEON SDK | ||
| 6 | * | ||
| 7 | * Copyright (c) 2003-2008 Cavium Networks | ||
| 8 | * | ||
| 9 | * This file is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License, Version 2, as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | * | ||
| 13 | * This file is distributed in the hope that it will be useful, but | ||
| 14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
| 15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
| 16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
| 17 | * details. | ||
| 18 | * | ||
| 19 | * You should have received a copy of the GNU General Public License | ||
| 20 | * along with this file; if not, write to the Free Software | ||
| 21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 22 | * or visit http://www.gnu.org/licenses/. | ||
| 23 | * | ||
| 24 | * This file may also be available under a different license from Cavium. | ||
| 25 | * Contact Cavium Networks for more information | ||
| 26 | ***********************license end**************************************/ | ||
| 27 | |||
| 28 | /* | ||
| 29 | * File defining functions for working with different Octeon | ||
| 30 | * models. | ||
| 31 | */ | ||
| 32 | #include <asm/octeon/octeon.h> | ||
| 33 | |||
| 34 | /** | ||
| 35 | * Given the chip processor ID from COP0, this function returns a | ||
| 36 | * string representing the chip model number. The string is of the | ||
| 37 | * form CNXXXXpX.X-FREQ-SUFFIX. | ||
| 38 | * - XXXX = The chip model number | ||
| 39 | * - X.X = Chip pass number | ||
| 40 | * - FREQ = Current frequency in Mhz | ||
| 41 | * - SUFFIX = NSP, EXP, SCP, SSP, or CP | ||
| 42 | * | ||
| 43 | * @chip_id: Chip ID | ||
| 44 | * | ||
| 45 | * Returns Model string | ||
| 46 | */ | ||
| 47 | const char *octeon_model_get_string(uint32_t chip_id) | ||
| 48 | { | ||
| 49 | static char buffer[32]; | ||
| 50 | return octeon_model_get_string_buffer(chip_id, buffer); | ||
| 51 | } | ||
| 52 | |||
| 53 | /* | ||
| 54 | * Version of octeon_model_get_string() that takes buffer as argument, | ||
| 55 | * as running early in u-boot static/global variables don't work when | ||
| 56 | * running from flash. | ||
| 57 | */ | ||
| 58 | const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer) | ||
| 59 | { | ||
| 60 | const char *family; | ||
| 61 | const char *core_model; | ||
| 62 | char pass[4]; | ||
| 63 | int clock_mhz; | ||
| 64 | const char *suffix; | ||
| 65 | union cvmx_l2d_fus3 fus3; | ||
| 66 | int num_cores; | ||
| 67 | union cvmx_mio_fus_dat2 fus_dat2; | ||
| 68 | union cvmx_mio_fus_dat3 fus_dat3; | ||
| 69 | char fuse_model[10]; | ||
| 70 | uint32_t fuse_data = 0; | ||
| 71 | |||
| 72 | fus3.u64 = cvmx_read_csr(CVMX_L2D_FUS3); | ||
| 73 | fus_dat2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2); | ||
| 74 | fus_dat3.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT3); | ||
| 75 | |||
| 76 | num_cores = cvmx_octeon_num_cores(); | ||
| 77 | |||
| 78 | /* Make sure the non existant devices look disabled */ | ||
| 79 | switch ((chip_id >> 8) & 0xff) { | ||
| 80 | case 6: /* CN50XX */ | ||
| 81 | case 2: /* CN30XX */ | ||
| 82 | fus_dat3.s.nodfa_dte = 1; | ||
| 83 | fus_dat3.s.nozip = 1; | ||
| 84 | break; | ||
| 85 | case 4: /* CN57XX or CN56XX */ | ||
| 86 | fus_dat3.s.nodfa_dte = 1; | ||
| 87 | break; | ||
| 88 | default: | ||
| 89 | break; | ||
| 90 | } | ||
| 91 | |||
| 92 | /* Make a guess at the suffix */ | ||
| 93 | /* NSP = everything */ | ||
| 94 | /* EXP = No crypto */ | ||
| 95 | /* SCP = No DFA, No zip */ | ||
| 96 | /* CP = No DFA, No crypto, No zip */ | ||
| 97 | if (fus_dat3.s.nodfa_dte) { | ||
| 98 | if (fus_dat2.s.nocrypto) | ||
| 99 | suffix = "CP"; | ||
| 100 | else | ||
| 101 | suffix = "SCP"; | ||
| 102 | } else if (fus_dat2.s.nocrypto) | ||
| 103 | suffix = "EXP"; | ||
| 104 | else | ||
| 105 | suffix = "NSP"; | ||
| 106 | |||
| 107 | /* | ||
| 108 | * Assume pass number is encoded using <5:3><2:0>. Exceptions | ||
| 109 | * will be fixed later. | ||
| 110 | */ | ||
| 111 | sprintf(pass, "%u.%u", ((chip_id >> 3) & 7) + 1, chip_id & 7); | ||
| 112 | |||
| 113 | /* | ||
| 114 | * Use the number of cores to determine the last 2 digits of | ||
| 115 | * the model number. There are some exceptions that are fixed | ||
| 116 | * later. | ||
| 117 | */ | ||
| 118 | switch (num_cores) { | ||
| 119 | case 16: | ||
| 120 | core_model = "60"; | ||
| 121 | break; | ||
| 122 | case 15: | ||
| 123 | core_model = "58"; | ||
| 124 | break; | ||
| 125 | case 14: | ||
| 126 | core_model = "55"; | ||
| 127 | break; | ||
| 128 | case 13: | ||
| 129 | core_model = "52"; | ||
| 130 | break; | ||
| 131 | case 12: | ||
| 132 | core_model = "50"; | ||
| 133 | break; | ||
| 134 | case 11: | ||
| 135 | core_model = "48"; | ||
| 136 | break; | ||
| 137 | case 10: | ||
| 138 | core_model = "45"; | ||
| 139 | break; | ||
| 140 | case 9: | ||
| 141 | core_model = "42"; | ||
| 142 | break; | ||
| 143 | case 8: | ||
| 144 | core_model = "40"; | ||
| 145 | break; | ||
| 146 | case 7: | ||
| 147 | core_model = "38"; | ||
| 148 | break; | ||
| 149 | case 6: | ||
| 150 | core_model = "34"; | ||
| 151 | break; | ||
| 152 | case 5: | ||
| 153 | core_model = "32"; | ||
| 154 | break; | ||
| 155 | case 4: | ||
| 156 | core_model = "30"; | ||
| 157 | break; | ||
| 158 | case 3: | ||
| 159 | core_model = "25"; | ||
| 160 | break; | ||
| 161 | case 2: | ||
| 162 | core_model = "20"; | ||
| 163 | break; | ||
| 164 | case 1: | ||
| 165 | core_model = "10"; | ||
| 166 | break; | ||
| 167 | default: | ||
| 168 | core_model = "XX"; | ||
| 169 | break; | ||
| 170 | } | ||
| 171 | |||
| 172 | /* Now figure out the family, the first two digits */ | ||
| 173 | switch ((chip_id >> 8) & 0xff) { | ||
| 174 | case 0: /* CN38XX, CN37XX or CN36XX */ | ||
| 175 | if (fus3.cn38xx.crip_512k) { | ||
| 176 | /* | ||
| 177 | * For some unknown reason, the 16 core one is | ||
| 178 | * called 37 instead of 36. | ||
| 179 | */ | ||
| 180 | if (num_cores >= 16) | ||
| 181 | family = "37"; | ||
| 182 | else | ||
| 183 | family = "36"; | ||
| 184 | } else | ||
| 185 | family = "38"; | ||
| 186 | /* | ||
| 187 | * This series of chips didn't follow the standard | ||
| 188 | * pass numbering. | ||
| 189 | */ | ||
| 190 | switch (chip_id & 0xf) { | ||
| 191 | case 0: | ||
| 192 | strcpy(pass, "1.X"); | ||
| 193 | break; | ||
| 194 | case 1: | ||
| 195 | strcpy(pass, "2.X"); | ||
| 196 | break; | ||
| 197 | case 3: | ||
| 198 | strcpy(pass, "3.X"); | ||
| 199 | break; | ||
| 200 | default: | ||
| 201 | strcpy(pass, "X.X"); | ||
| 202 | break; | ||
| 203 | } | ||
| 204 | break; | ||
| 205 | case 1: /* CN31XX or CN3020 */ | ||
| 206 | if ((chip_id & 0x10) || fus3.cn31xx.crip_128k) | ||
| 207 | family = "30"; | ||
| 208 | else | ||
| 209 | family = "31"; | ||
| 210 | /* | ||
| 211 | * This series of chips didn't follow the standard | ||
| 212 | * pass numbering. | ||
| 213 | */ | ||
| 214 | switch (chip_id & 0xf) { | ||
| 215 | case 0: | ||
| 216 | strcpy(pass, "1.0"); | ||
| 217 | break; | ||
| 218 | case 2: | ||
| 219 | strcpy(pass, "1.1"); | ||
| 220 | break; | ||
| 221 | default: | ||
| 222 | strcpy(pass, "X.X"); | ||
| 223 | break; | ||
| 224 | } | ||
| 225 | break; | ||
| 226 | case 2: /* CN3010 or CN3005 */ | ||
| 227 | family = "30"; | ||
| 228 | /* A chip with half cache is an 05 */ | ||
| 229 | if (fus3.cn30xx.crip_64k) | ||
| 230 | core_model = "05"; | ||
| 231 | /* | ||
| 232 | * This series of chips didn't follow the standard | ||
| 233 | * pass numbering. | ||
| 234 | */ | ||
| 235 | switch (chip_id & 0xf) { | ||
| 236 | case 0: | ||
| 237 | strcpy(pass, "1.0"); | ||
| 238 | break; | ||
| 239 | case 2: | ||
| 240 | strcpy(pass, "1.1"); | ||
| 241 | break; | ||
| 242 | default: | ||
| 243 | strcpy(pass, "X.X"); | ||
| 244 | break; | ||
| 245 | } | ||
| 246 | break; | ||
| 247 | case 3: /* CN58XX */ | ||
| 248 | family = "58"; | ||
| 249 | /* Special case. 4 core, no crypto */ | ||
| 250 | if ((num_cores == 4) && fus_dat2.cn38xx.nocrypto) | ||
| 251 | core_model = "29"; | ||
| 252 | |||
| 253 | /* Pass 1 uses different encodings for pass numbers */ | ||
| 254 | if ((chip_id & 0xFF) < 0x8) { | ||
| 255 | switch (chip_id & 0x3) { | ||
| 256 | case 0: | ||
| 257 | strcpy(pass, "1.0"); | ||
| 258 | break; | ||
| 259 | case 1: | ||
| 260 | strcpy(pass, "1.1"); | ||
| 261 | break; | ||
| 262 | case 3: | ||
| 263 | strcpy(pass, "1.2"); | ||
| 264 | break; | ||
| 265 | default: | ||
| 266 | strcpy(pass, "1.X"); | ||
| 267 | break; | ||
| 268 | } | ||
| 269 | } | ||
| 270 | break; | ||
| 271 | case 4: /* CN57XX, CN56XX, CN55XX, CN54XX */ | ||
| 272 | if (fus_dat2.cn56xx.raid_en) { | ||
| 273 | if (fus3.cn56xx.crip_1024k) | ||
| 274 | family = "55"; | ||
| 275 | else | ||
| 276 | family = "57"; | ||
| 277 | if (fus_dat2.cn56xx.nocrypto) | ||
| 278 | suffix = "SP"; | ||
| 279 | else | ||
| 280 | suffix = "SSP"; | ||
| 281 | } else { | ||
| 282 | if (fus_dat2.cn56xx.nocrypto) | ||
| 283 | suffix = "CP"; | ||
| 284 | else { | ||
| 285 | suffix = "NSP"; | ||
| 286 | if (fus_dat3.s.nozip) | ||
| 287 | suffix = "SCP"; | ||
| 288 | } | ||
| 289 | if (fus3.cn56xx.crip_1024k) | ||
| 290 | family = "54"; | ||
| 291 | else | ||
| 292 | family = "56"; | ||
| 293 | } | ||
| 294 | break; | ||
| 295 | case 6: /* CN50XX */ | ||
| 296 | family = "50"; | ||
| 297 | break; | ||
| 298 | case 7: /* CN52XX */ | ||
| 299 | if (fus3.cn52xx.crip_256k) | ||
| 300 | family = "51"; | ||
| 301 | else | ||
| 302 | family = "52"; | ||
| 303 | break; | ||
| 304 | default: | ||
| 305 | family = "XX"; | ||
| 306 | core_model = "XX"; | ||
| 307 | strcpy(pass, "X.X"); | ||
| 308 | suffix = "XXX"; | ||
| 309 | break; | ||
| 310 | } | ||
| 311 | |||
| 312 | clock_mhz = octeon_get_clock_rate() / 1000000; | ||
| 313 | |||
| 314 | if (family[0] != '3') { | ||
| 315 | /* Check for model in fuses, overrides normal decode */ | ||
| 316 | /* This is _not_ valid for Octeon CN3XXX models */ | ||
| 317 | fuse_data |= cvmx_fuse_read_byte(51); | ||
| 318 | fuse_data = fuse_data << 8; | ||
| 319 | fuse_data |= cvmx_fuse_read_byte(50); | ||
| 320 | fuse_data = fuse_data << 8; | ||
| 321 | fuse_data |= cvmx_fuse_read_byte(49); | ||
| 322 | fuse_data = fuse_data << 8; | ||
| 323 | fuse_data |= cvmx_fuse_read_byte(48); | ||
| 324 | if (fuse_data & 0x7ffff) { | ||
| 325 | int model = fuse_data & 0x3fff; | ||
| 326 | int suffix = (fuse_data >> 14) & 0x1f; | ||
| 327 | if (suffix && model) { | ||
| 328 | /* | ||
| 329 | * Have both number and suffix in | ||
| 330 | * fuses, so both | ||
| 331 | */ | ||
| 332 | sprintf(fuse_model, "%d%c", | ||
| 333 | model, 'A' + suffix - 1); | ||
| 334 | core_model = ""; | ||
| 335 | family = fuse_model; | ||
| 336 | } else if (suffix && !model) { | ||
| 337 | /* | ||
| 338 | * Only have suffix, so add suffix to | ||
| 339 | * 'normal' model number. | ||
| 340 | */ | ||
| 341 | sprintf(fuse_model, "%s%c", core_model, | ||
| 342 | 'A' + suffix - 1); | ||
| 343 | core_model = fuse_model; | ||
| 344 | } else { | ||
| 345 | /* | ||
| 346 | * Don't have suffix, so just use | ||
| 347 | * model from fuses. | ||
| 348 | */ | ||
| 349 | sprintf(fuse_model, "%d", model); | ||
| 350 | core_model = ""; | ||
| 351 | family = fuse_model; | ||
| 352 | } | ||
| 353 | } | ||
| 354 | } | ||
| 355 | sprintf(buffer, "CN%s%sp%s-%d-%s", | ||
| 356 | family, core_model, pass, clock_mhz, suffix); | ||
| 357 | return buffer; | ||
| 358 | } | ||
diff --git a/arch/mips/cavium-octeon/flash_setup.c b/arch/mips/cavium-octeon/flash_setup.c new file mode 100644 index 000000000000..553d36cbcc42 --- /dev/null +++ b/arch/mips/cavium-octeon/flash_setup.c | |||
| @@ -0,0 +1,84 @@ | |||
| 1 | /* | ||
| 2 | * Octeon Bootbus flash setup | ||
| 3 | * | ||
| 4 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 5 | * License. See the file "COPYING" in the main directory of this archive | ||
| 6 | * for more details. | ||
| 7 | * | ||
| 8 | * Copyright (C) 2007, 2008 Cavium Networks | ||
| 9 | */ | ||
| 10 | #include <linux/kernel.h> | ||
| 11 | #include <linux/mtd/mtd.h> | ||
| 12 | #include <linux/mtd/map.h> | ||
| 13 | #include <linux/mtd/partitions.h> | ||
| 14 | |||
| 15 | #include <asm/octeon/octeon.h> | ||
| 16 | |||
| 17 | static struct map_info flash_map; | ||
| 18 | static struct mtd_info *mymtd; | ||
| 19 | #ifdef CONFIG_MTD_PARTITIONS | ||
| 20 | static int nr_parts; | ||
| 21 | static struct mtd_partition *parts; | ||
| 22 | static const char *part_probe_types[] = { | ||
| 23 | "cmdlinepart", | ||
| 24 | #ifdef CONFIG_MTD_REDBOOT_PARTS | ||
| 25 | "RedBoot", | ||
| 26 | #endif | ||
| 27 | NULL | ||
| 28 | }; | ||
| 29 | #endif | ||
| 30 | |||
| 31 | /** | ||
| 32 | * Module/ driver initialization. | ||
| 33 | * | ||
| 34 | * Returns Zero on success | ||
| 35 | */ | ||
| 36 | static int __init flash_init(void) | ||
| 37 | { | ||
| 38 | /* | ||
| 39 | * Read the bootbus region 0 setup to determine the base | ||
| 40 | * address of the flash. | ||
| 41 | */ | ||
| 42 | union cvmx_mio_boot_reg_cfgx region_cfg; | ||
| 43 | region_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(0)); | ||
| 44 | if (region_cfg.s.en) { | ||
| 45 | /* | ||
| 46 | * The bootloader always takes the flash and sets its | ||
| 47 | * address so the entire flash fits below | ||
| 48 | * 0x1fc00000. This way the flash aliases to | ||
| 49 | * 0x1fc00000 for booting. Software can access the | ||
| 50 | * full flash at the true address, while core boot can | ||
| 51 | * access 4MB. | ||
| 52 | */ | ||
| 53 | /* Use this name so old part lines work */ | ||
| 54 | flash_map.name = "phys_mapped_flash"; | ||
| 55 | flash_map.phys = region_cfg.s.base << 16; | ||
| 56 | flash_map.size = 0x1fc00000 - flash_map.phys; | ||
| 57 | flash_map.bankwidth = 1; | ||
| 58 | flash_map.virt = ioremap(flash_map.phys, flash_map.size); | ||
| 59 | pr_notice("Bootbus flash: Setting flash for %luMB flash at " | ||
| 60 | "0x%08lx\n", flash_map.size >> 20, flash_map.phys); | ||
| 61 | simple_map_init(&flash_map); | ||
| 62 | mymtd = do_map_probe("cfi_probe", &flash_map); | ||
| 63 | if (mymtd) { | ||
| 64 | mymtd->owner = THIS_MODULE; | ||
| 65 | |||
| 66 | #ifdef CONFIG_MTD_PARTITIONS | ||
| 67 | nr_parts = parse_mtd_partitions(mymtd, | ||
| 68 | part_probe_types, | ||
| 69 | &parts, 0); | ||
| 70 | if (nr_parts > 0) | ||
| 71 | add_mtd_partitions(mymtd, parts, nr_parts); | ||
| 72 | else | ||
| 73 | add_mtd_device(mymtd); | ||
| 74 | #else | ||
| 75 | add_mtd_device(mymtd); | ||
| 76 | #endif | ||
| 77 | } else { | ||
| 78 | pr_err("Failed to register MTD device for flash\n"); | ||
| 79 | } | ||
| 80 | } | ||
| 81 | return 0; | ||
| 82 | } | ||
| 83 | |||
| 84 | late_initcall(flash_init); | ||
diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c new file mode 100644 index 000000000000..fc72984a5dae --- /dev/null +++ b/arch/mips/cavium-octeon/octeon-irq.c | |||
| @@ -0,0 +1,497 @@ | |||
| 1 | /* | ||
| 2 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 3 | * License. See the file "COPYING" in the main directory of this archive | ||
| 4 | * for more details. | ||
| 5 | * | ||
| 6 | * Copyright (C) 2004-2008 Cavium Networks | ||
| 7 | */ | ||
| 8 | #include <linux/irq.h> | ||
| 9 | #include <linux/interrupt.h> | ||
| 10 | #include <linux/hardirq.h> | ||
| 11 | |||
| 12 | #include <asm/octeon/octeon.h> | ||
| 13 | |||
| 14 | DEFINE_RWLOCK(octeon_irq_ciu0_rwlock); | ||
| 15 | DEFINE_RWLOCK(octeon_irq_ciu1_rwlock); | ||
| 16 | DEFINE_SPINLOCK(octeon_irq_msi_lock); | ||
| 17 | |||
| 18 | static void octeon_irq_core_ack(unsigned int irq) | ||
| 19 | { | ||
| 20 | unsigned int bit = irq - OCTEON_IRQ_SW0; | ||
| 21 | /* | ||
| 22 | * We don't need to disable IRQs to make these atomic since | ||
| 23 | * they are already disabled earlier in the low level | ||
| 24 | * interrupt code. | ||
| 25 | */ | ||
| 26 | clear_c0_status(0x100 << bit); | ||
| 27 | /* The two user interrupts must be cleared manually. */ | ||
| 28 | if (bit < 2) | ||
| 29 | clear_c0_cause(0x100 << bit); | ||
| 30 | } | ||
| 31 | |||
| 32 | static void octeon_irq_core_eoi(unsigned int irq) | ||
| 33 | { | ||
| 34 | irq_desc_t *desc = irq_desc + irq; | ||
| 35 | unsigned int bit = irq - OCTEON_IRQ_SW0; | ||
| 36 | /* | ||
| 37 | * If an IRQ is being processed while we are disabling it the | ||
| 38 | * handler will attempt to unmask the interrupt after it has | ||
| 39 | * been disabled. | ||
| 40 | */ | ||
| 41 | if (desc->status & IRQ_DISABLED) | ||
| 42 | return; | ||
| 43 | |||
| 44 | /* There is a race here. We should fix it. */ | ||
| 45 | |||
| 46 | /* | ||
| 47 | * We don't need to disable IRQs to make these atomic since | ||
| 48 | * they are already disabled earlier in the low level | ||
| 49 | * interrupt code. | ||
| 50 | */ | ||
| 51 | set_c0_status(0x100 << bit); | ||
| 52 | } | ||
| 53 | |||
| 54 | static void octeon_irq_core_enable(unsigned int irq) | ||
| 55 | { | ||
| 56 | unsigned long flags; | ||
| 57 | unsigned int bit = irq - OCTEON_IRQ_SW0; | ||
| 58 | |||
| 59 | /* | ||
| 60 | * We need to disable interrupts to make sure our updates are | ||
| 61 | * atomic. | ||
| 62 | */ | ||
| 63 | local_irq_save(flags); | ||
| 64 | set_c0_status(0x100 << bit); | ||
| 65 | local_irq_restore(flags); | ||
| 66 | } | ||
| 67 | |||
| 68 | static void octeon_irq_core_disable_local(unsigned int irq) | ||
| 69 | { | ||
| 70 | unsigned long flags; | ||
| 71 | unsigned int bit = irq - OCTEON_IRQ_SW0; | ||
| 72 | /* | ||
| 73 | * We need to disable interrupts to make sure our updates are | ||
| 74 | * atomic. | ||
| 75 | */ | ||
| 76 | local_irq_save(flags); | ||
| 77 | clear_c0_status(0x100 << bit); | ||
| 78 | local_irq_restore(flags); | ||
| 79 | } | ||
| 80 | |||
| 81 | static void octeon_irq_core_disable(unsigned int irq) | ||
| 82 | { | ||
| 83 | #ifdef CONFIG_SMP | ||
| 84 | on_each_cpu((void (*)(void *)) octeon_irq_core_disable_local, | ||
| 85 | (void *) (long) irq, 1); | ||
| 86 | #else | ||
| 87 | octeon_irq_core_disable_local(irq); | ||
| 88 | #endif | ||
| 89 | } | ||
| 90 | |||
| 91 | static struct irq_chip octeon_irq_chip_core = { | ||
| 92 | .name = "Core", | ||
| 93 | .enable = octeon_irq_core_enable, | ||
| 94 | .disable = octeon_irq_core_disable, | ||
| 95 | .ack = octeon_irq_core_ack, | ||
| 96 | .eoi = octeon_irq_core_eoi, | ||
| 97 | }; | ||
| 98 | |||
| 99 | |||
| 100 | static void octeon_irq_ciu0_ack(unsigned int irq) | ||
| 101 | { | ||
| 102 | /* | ||
| 103 | * In order to avoid any locking accessing the CIU, we | ||
| 104 | * acknowledge CIU interrupts by disabling all of them. This | ||
| 105 | * way we can use a per core register and avoid any out of | ||
| 106 | * core locking requirements. This has the side affect that | ||
| 107 | * CIU interrupts can't be processed recursively. | ||
| 108 | * | ||
| 109 | * We don't need to disable IRQs to make these atomic since | ||
| 110 | * they are already disabled earlier in the low level | ||
| 111 | * interrupt code. | ||
| 112 | */ | ||
| 113 | clear_c0_status(0x100 << 2); | ||
| 114 | } | ||
| 115 | |||
| 116 | static void octeon_irq_ciu0_eoi(unsigned int irq) | ||
| 117 | { | ||
| 118 | /* | ||
| 119 | * Enable all CIU interrupts again. We don't need to disable | ||
| 120 | * IRQs to make these atomic since they are already disabled | ||
| 121 | * earlier in the low level interrupt code. | ||
| 122 | */ | ||
| 123 | set_c0_status(0x100 << 2); | ||
| 124 | } | ||
| 125 | |||
| 126 | static void octeon_irq_ciu0_enable(unsigned int irq) | ||
| 127 | { | ||
| 128 | int coreid = cvmx_get_core_num(); | ||
| 129 | unsigned long flags; | ||
| 130 | uint64_t en0; | ||
| 131 | int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */ | ||
| 132 | |||
| 133 | /* | ||
| 134 | * A read lock is used here to make sure only one core is ever | ||
| 135 | * updating the CIU enable bits at a time. During an enable | ||
| 136 | * the cores don't interfere with each other. During a disable | ||
| 137 | * the write lock stops any enables that might cause a | ||
| 138 | * problem. | ||
| 139 | */ | ||
| 140 | read_lock_irqsave(&octeon_irq_ciu0_rwlock, flags); | ||
| 141 | en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); | ||
| 142 | en0 |= 1ull << bit; | ||
| 143 | cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0); | ||
| 144 | cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); | ||
| 145 | read_unlock_irqrestore(&octeon_irq_ciu0_rwlock, flags); | ||
| 146 | } | ||
| 147 | |||
| 148 | static void octeon_irq_ciu0_disable(unsigned int irq) | ||
| 149 | { | ||
| 150 | int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */ | ||
| 151 | unsigned long flags; | ||
| 152 | uint64_t en0; | ||
| 153 | #ifdef CONFIG_SMP | ||
| 154 | int cpu; | ||
| 155 | write_lock_irqsave(&octeon_irq_ciu0_rwlock, flags); | ||
| 156 | for_each_online_cpu(cpu) { | ||
| 157 | int coreid = cpu_logical_map(cpu); | ||
| 158 | en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); | ||
| 159 | en0 &= ~(1ull << bit); | ||
| 160 | cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0); | ||
| 161 | } | ||
| 162 | /* | ||
| 163 | * We need to do a read after the last update to make sure all | ||
| 164 | * of them are done. | ||
| 165 | */ | ||
| 166 | cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2)); | ||
| 167 | write_unlock_irqrestore(&octeon_irq_ciu0_rwlock, flags); | ||
| 168 | #else | ||
| 169 | int coreid = cvmx_get_core_num(); | ||
| 170 | local_irq_save(flags); | ||
| 171 | en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); | ||
| 172 | en0 &= ~(1ull << bit); | ||
| 173 | cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0); | ||
| 174 | cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); | ||
| 175 | local_irq_restore(flags); | ||
| 176 | #endif | ||
| 177 | } | ||
| 178 | |||
| 179 | #ifdef CONFIG_SMP | ||
| 180 | static void octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask *dest) | ||
| 181 | { | ||
| 182 | int cpu; | ||
| 183 | int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */ | ||
| 184 | |||
| 185 | write_lock(&octeon_irq_ciu0_rwlock); | ||
| 186 | for_each_online_cpu(cpu) { | ||
| 187 | int coreid = cpu_logical_map(cpu); | ||
| 188 | uint64_t en0 = | ||
| 189 | cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); | ||
| 190 | if (cpumask_test_cpu(cpu, dest)) | ||
| 191 | en0 |= 1ull << bit; | ||
| 192 | else | ||
| 193 | en0 &= ~(1ull << bit); | ||
| 194 | cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0); | ||
| 195 | } | ||
| 196 | /* | ||
| 197 | * We need to do a read after the last update to make sure all | ||
| 198 | * of them are done. | ||
| 199 | */ | ||
| 200 | cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2)); | ||
| 201 | write_unlock(&octeon_irq_ciu0_rwlock); | ||
| 202 | } | ||
| 203 | #endif | ||
| 204 | |||
| 205 | static struct irq_chip octeon_irq_chip_ciu0 = { | ||
| 206 | .name = "CIU0", | ||
| 207 | .enable = octeon_irq_ciu0_enable, | ||
| 208 | .disable = octeon_irq_ciu0_disable, | ||
| 209 | .ack = octeon_irq_ciu0_ack, | ||
| 210 | .eoi = octeon_irq_ciu0_eoi, | ||
| 211 | #ifdef CONFIG_SMP | ||
| 212 | .set_affinity = octeon_irq_ciu0_set_affinity, | ||
| 213 | #endif | ||
| 214 | }; | ||
| 215 | |||
| 216 | |||
| 217 | static void octeon_irq_ciu1_ack(unsigned int irq) | ||
| 218 | { | ||
| 219 | /* | ||
| 220 | * In order to avoid any locking accessing the CIU, we | ||
| 221 | * acknowledge CIU interrupts by disabling all of them. This | ||
| 222 | * way we can use a per core register and avoid any out of | ||
| 223 | * core locking requirements. This has the side affect that | ||
| 224 | * CIU interrupts can't be processed recursively. We don't | ||
| 225 | * need to disable IRQs to make these atomic since they are | ||
| 226 | * already disabled earlier in the low level interrupt code. | ||
| 227 | */ | ||
| 228 | clear_c0_status(0x100 << 3); | ||
| 229 | } | ||
| 230 | |||
| 231 | static void octeon_irq_ciu1_eoi(unsigned int irq) | ||
| 232 | { | ||
| 233 | /* | ||
| 234 | * Enable all CIU interrupts again. We don't need to disable | ||
| 235 | * IRQs to make these atomic since they are already disabled | ||
| 236 | * earlier in the low level interrupt code. | ||
| 237 | */ | ||
| 238 | set_c0_status(0x100 << 3); | ||
| 239 | } | ||
| 240 | |||
| 241 | static void octeon_irq_ciu1_enable(unsigned int irq) | ||
| 242 | { | ||
| 243 | int coreid = cvmx_get_core_num(); | ||
| 244 | unsigned long flags; | ||
| 245 | uint64_t en1; | ||
| 246 | int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */ | ||
| 247 | |||
| 248 | /* | ||
| 249 | * A read lock is used here to make sure only one core is ever | ||
| 250 | * updating the CIU enable bits at a time. During an enable | ||
| 251 | * the cores don't interfere with each other. During a disable | ||
| 252 | * the write lock stops any enables that might cause a | ||
| 253 | * problem. | ||
| 254 | */ | ||
| 255 | read_lock_irqsave(&octeon_irq_ciu1_rwlock, flags); | ||
| 256 | en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); | ||
| 257 | en1 |= 1ull << bit; | ||
| 258 | cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1); | ||
| 259 | cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); | ||
| 260 | read_unlock_irqrestore(&octeon_irq_ciu1_rwlock, flags); | ||
| 261 | } | ||
| 262 | |||
| 263 | static void octeon_irq_ciu1_disable(unsigned int irq) | ||
| 264 | { | ||
| 265 | int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */ | ||
| 266 | unsigned long flags; | ||
| 267 | uint64_t en1; | ||
| 268 | #ifdef CONFIG_SMP | ||
| 269 | int cpu; | ||
| 270 | write_lock_irqsave(&octeon_irq_ciu1_rwlock, flags); | ||
| 271 | for_each_online_cpu(cpu) { | ||
| 272 | int coreid = cpu_logical_map(cpu); | ||
| 273 | en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); | ||
| 274 | en1 &= ~(1ull << bit); | ||
| 275 | cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1); | ||
| 276 | } | ||
| 277 | /* | ||
| 278 | * We need to do a read after the last update to make sure all | ||
| 279 | * of them are done. | ||
| 280 | */ | ||
| 281 | cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1)); | ||
| 282 | write_unlock_irqrestore(&octeon_irq_ciu1_rwlock, flags); | ||
| 283 | #else | ||
| 284 | int coreid = cvmx_get_core_num(); | ||
| 285 | local_irq_save(flags); | ||
| 286 | en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); | ||
| 287 | en1 &= ~(1ull << bit); | ||
| 288 | cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1); | ||
| 289 | cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); | ||
| 290 | local_irq_restore(flags); | ||
| 291 | #endif | ||
| 292 | } | ||
| 293 | |||
| 294 | #ifdef CONFIG_SMP | ||
| 295 | static void octeon_irq_ciu1_set_affinity(unsigned int irq, const struct cpumask *dest) | ||
| 296 | { | ||
| 297 | int cpu; | ||
| 298 | int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */ | ||
| 299 | |||
| 300 | write_lock(&octeon_irq_ciu1_rwlock); | ||
| 301 | for_each_online_cpu(cpu) { | ||
| 302 | int coreid = cpu_logical_map(cpu); | ||
| 303 | uint64_t en1 = | ||
| 304 | cvmx_read_csr(CVMX_CIU_INTX_EN1 | ||
| 305 | (coreid * 2 + 1)); | ||
| 306 | if (cpumask_test_cpu(cpu, dest)) | ||
| 307 | en1 |= 1ull << bit; | ||
| 308 | else | ||
| 309 | en1 &= ~(1ull << bit); | ||
| 310 | cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1); | ||
| 311 | } | ||
| 312 | /* | ||
| 313 | * We need to do a read after the last update to make sure all | ||
| 314 | * of them are done. | ||
| 315 | */ | ||
| 316 | cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1)); | ||
| 317 | write_unlock(&octeon_irq_ciu1_rwlock); | ||
| 318 | } | ||
| 319 | #endif | ||
| 320 | |||
| 321 | static struct irq_chip octeon_irq_chip_ciu1 = { | ||
| 322 | .name = "CIU1", | ||
| 323 | .enable = octeon_irq_ciu1_enable, | ||
| 324 | .disable = octeon_irq_ciu1_disable, | ||
| 325 | .ack = octeon_irq_ciu1_ack, | ||
| 326 | .eoi = octeon_irq_ciu1_eoi, | ||
| 327 | #ifdef CONFIG_SMP | ||
| 328 | .set_affinity = octeon_irq_ciu1_set_affinity, | ||
| 329 | #endif | ||
| 330 | }; | ||
| 331 | |||
| 332 | #ifdef CONFIG_PCI_MSI | ||
| 333 | |||
| 334 | static void octeon_irq_msi_ack(unsigned int irq) | ||
| 335 | { | ||
| 336 | if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) { | ||
| 337 | /* These chips have PCI */ | ||
| 338 | cvmx_write_csr(CVMX_NPI_NPI_MSI_RCV, | ||
| 339 | 1ull << (irq - OCTEON_IRQ_MSI_BIT0)); | ||
| 340 | } else { | ||
| 341 | /* | ||
| 342 | * These chips have PCIe. Thankfully the ACK doesn't | ||
| 343 | * need any locking. | ||
| 344 | */ | ||
| 345 | cvmx_write_csr(CVMX_PEXP_NPEI_MSI_RCV0, | ||
| 346 | 1ull << (irq - OCTEON_IRQ_MSI_BIT0)); | ||
| 347 | } | ||
| 348 | } | ||
| 349 | |||
| 350 | static void octeon_irq_msi_eoi(unsigned int irq) | ||
| 351 | { | ||
| 352 | /* Nothing needed */ | ||
| 353 | } | ||
| 354 | |||
| 355 | static void octeon_irq_msi_enable(unsigned int irq) | ||
| 356 | { | ||
| 357 | if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) { | ||
| 358 | /* | ||
| 359 | * Octeon PCI doesn't have the ability to mask/unmask | ||
| 360 | * MSI interrupts individually. Instead of | ||
| 361 | * masking/unmasking them in groups of 16, we simple | ||
| 362 | * assume MSI devices are well behaved. MSI | ||
| 363 | * interrupts are always enable and the ACK is assumed | ||
| 364 | * to be enough. | ||
| 365 | */ | ||
| 366 | } else { | ||
| 367 | /* These chips have PCIe. Note that we only support | ||
| 368 | * the first 64 MSI interrupts. Unfortunately all the | ||
| 369 | * MSI enables are in the same register. We use | ||
| 370 | * MSI0's lock to control access to them all. | ||
| 371 | */ | ||
| 372 | uint64_t en; | ||
| 373 | unsigned long flags; | ||
| 374 | spin_lock_irqsave(&octeon_irq_msi_lock, flags); | ||
| 375 | en = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0); | ||
| 376 | en |= 1ull << (irq - OCTEON_IRQ_MSI_BIT0); | ||
| 377 | cvmx_write_csr(CVMX_PEXP_NPEI_MSI_ENB0, en); | ||
| 378 | cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0); | ||
| 379 | spin_unlock_irqrestore(&octeon_irq_msi_lock, flags); | ||
| 380 | } | ||
| 381 | } | ||
| 382 | |||
| 383 | static void octeon_irq_msi_disable(unsigned int irq) | ||
| 384 | { | ||
| 385 | if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) { | ||
| 386 | /* See comment in enable */ | ||
| 387 | } else { | ||
| 388 | /* | ||
| 389 | * These chips have PCIe. Note that we only support | ||
| 390 | * the first 64 MSI interrupts. Unfortunately all the | ||
| 391 | * MSI enables are in the same register. We use | ||
| 392 | * MSI0's lock to control access to them all. | ||
| 393 | */ | ||
| 394 | uint64_t en; | ||
| 395 | unsigned long flags; | ||
| 396 | spin_lock_irqsave(&octeon_irq_msi_lock, flags); | ||
| 397 | en = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0); | ||
| 398 | en &= ~(1ull << (irq - OCTEON_IRQ_MSI_BIT0)); | ||
| 399 | cvmx_write_csr(CVMX_PEXP_NPEI_MSI_ENB0, en); | ||
| 400 | cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0); | ||
| 401 | spin_unlock_irqrestore(&octeon_irq_msi_lock, flags); | ||
| 402 | } | ||
| 403 | } | ||
| 404 | |||
| 405 | static struct irq_chip octeon_irq_chip_msi = { | ||
| 406 | .name = "MSI", | ||
| 407 | .enable = octeon_irq_msi_enable, | ||
| 408 | .disable = octeon_irq_msi_disable, | ||
| 409 | .ack = octeon_irq_msi_ack, | ||
| 410 | .eoi = octeon_irq_msi_eoi, | ||
| 411 | }; | ||
| 412 | #endif | ||
| 413 | |||
| 414 | void __init arch_init_irq(void) | ||
| 415 | { | ||
| 416 | int irq; | ||
| 417 | |||
| 418 | #ifdef CONFIG_SMP | ||
| 419 | /* Set the default affinity to the boot cpu. */ | ||
| 420 | cpumask_clear(irq_default_affinity); | ||
| 421 | cpumask_set_cpu(smp_processor_id(), irq_default_affinity); | ||
| 422 | #endif | ||
| 423 | |||
| 424 | if (NR_IRQS < OCTEON_IRQ_LAST) | ||
| 425 | pr_err("octeon_irq_init: NR_IRQS is set too low\n"); | ||
| 426 | |||
| 427 | /* 0 - 15 reserved for i8259 master and slave controller. */ | ||
| 428 | |||
| 429 | /* 17 - 23 Mips internal */ | ||
| 430 | for (irq = OCTEON_IRQ_SW0; irq <= OCTEON_IRQ_TIMER; irq++) { | ||
| 431 | set_irq_chip_and_handler(irq, &octeon_irq_chip_core, | ||
| 432 | handle_percpu_irq); | ||
| 433 | } | ||
| 434 | |||
| 435 | /* 24 - 87 CIU_INT_SUM0 */ | ||
| 436 | for (irq = OCTEON_IRQ_WORKQ0; irq <= OCTEON_IRQ_BOOTDMA; irq++) { | ||
| 437 | set_irq_chip_and_handler(irq, &octeon_irq_chip_ciu0, | ||
| 438 | handle_percpu_irq); | ||
| 439 | } | ||
| 440 | |||
| 441 | /* 88 - 151 CIU_INT_SUM1 */ | ||
| 442 | for (irq = OCTEON_IRQ_WDOG0; irq <= OCTEON_IRQ_RESERVED151; irq++) { | ||
| 443 | set_irq_chip_and_handler(irq, &octeon_irq_chip_ciu1, | ||
| 444 | handle_percpu_irq); | ||
| 445 | } | ||
| 446 | |||
| 447 | #ifdef CONFIG_PCI_MSI | ||
| 448 | /* 152 - 215 PCI/PCIe MSI interrupts */ | ||
| 449 | for (irq = OCTEON_IRQ_MSI_BIT0; irq <= OCTEON_IRQ_MSI_BIT63; irq++) { | ||
| 450 | set_irq_chip_and_handler(irq, &octeon_irq_chip_msi, | ||
| 451 | handle_percpu_irq); | ||
| 452 | } | ||
| 453 | #endif | ||
| 454 | set_c0_status(0x300 << 2); | ||
| 455 | } | ||
| 456 | |||
| 457 | asmlinkage void plat_irq_dispatch(void) | ||
| 458 | { | ||
| 459 | const unsigned long core_id = cvmx_get_core_num(); | ||
| 460 | const uint64_t ciu_sum0_address = CVMX_CIU_INTX_SUM0(core_id * 2); | ||
| 461 | const uint64_t ciu_en0_address = CVMX_CIU_INTX_EN0(core_id * 2); | ||
| 462 | const uint64_t ciu_sum1_address = CVMX_CIU_INT_SUM1; | ||
| 463 | const uint64_t ciu_en1_address = CVMX_CIU_INTX_EN1(core_id * 2 + 1); | ||
| 464 | unsigned long cop0_cause; | ||
| 465 | unsigned long cop0_status; | ||
| 466 | uint64_t ciu_en; | ||
| 467 | uint64_t ciu_sum; | ||
| 468 | |||
| 469 | while (1) { | ||
| 470 | cop0_cause = read_c0_cause(); | ||
| 471 | cop0_status = read_c0_status(); | ||
| 472 | cop0_cause &= cop0_status; | ||
| 473 | cop0_cause &= ST0_IM; | ||
| 474 | |||
| 475 | if (unlikely(cop0_cause & STATUSF_IP2)) { | ||
| 476 | ciu_sum = cvmx_read_csr(ciu_sum0_address); | ||
| 477 | ciu_en = cvmx_read_csr(ciu_en0_address); | ||
| 478 | ciu_sum &= ciu_en; | ||
| 479 | if (likely(ciu_sum)) | ||
| 480 | do_IRQ(fls64(ciu_sum) + OCTEON_IRQ_WORKQ0 - 1); | ||
| 481 | else | ||
| 482 | spurious_interrupt(); | ||
| 483 | } else if (unlikely(cop0_cause & STATUSF_IP3)) { | ||
| 484 | ciu_sum = cvmx_read_csr(ciu_sum1_address); | ||
| 485 | ciu_en = cvmx_read_csr(ciu_en1_address); | ||
| 486 | ciu_sum &= ciu_en; | ||
| 487 | if (likely(ciu_sum)) | ||
| 488 | do_IRQ(fls64(ciu_sum) + OCTEON_IRQ_WDOG0 - 1); | ||
| 489 | else | ||
| 490 | spurious_interrupt(); | ||
| 491 | } else if (likely(cop0_cause)) { | ||
| 492 | do_IRQ(fls(cop0_cause) - 9 + MIPS_CPU_IRQ_BASE); | ||
| 493 | } else { | ||
| 494 | break; | ||
| 495 | } | ||
| 496 | } | ||
| 497 | } | ||
diff --git a/arch/mips/cavium-octeon/octeon-memcpy.S b/arch/mips/cavium-octeon/octeon-memcpy.S new file mode 100644 index 000000000000..88e0cddca205 --- /dev/null +++ b/arch/mips/cavium-octeon/octeon-memcpy.S | |||
| @@ -0,0 +1,521 @@ | |||
| 1 | /* | ||
| 2 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 3 | * License. See the file "COPYING" in the main directory of this archive | ||
| 4 | * for more details. | ||
| 5 | * | ||
| 6 | * Unified implementation of memcpy, memmove and the __copy_user backend. | ||
| 7 | * | ||
| 8 | * Copyright (C) 1998, 99, 2000, 01, 2002 Ralf Baechle (ralf@gnu.org) | ||
| 9 | * Copyright (C) 1999, 2000, 01, 2002 Silicon Graphics, Inc. | ||
| 10 | * Copyright (C) 2002 Broadcom, Inc. | ||
| 11 | * memcpy/copy_user author: Mark Vandevoorde | ||
| 12 | * | ||
| 13 | * Mnemonic names for arguments to memcpy/__copy_user | ||
| 14 | */ | ||
| 15 | |||
| 16 | #include <asm/asm.h> | ||
| 17 | #include <asm/asm-offsets.h> | ||
| 18 | #include <asm/regdef.h> | ||
| 19 | |||
| 20 | #define dst a0 | ||
| 21 | #define src a1 | ||
| 22 | #define len a2 | ||
| 23 | |||
| 24 | /* | ||
| 25 | * Spec | ||
| 26 | * | ||
| 27 | * memcpy copies len bytes from src to dst and sets v0 to dst. | ||
| 28 | * It assumes that | ||
| 29 | * - src and dst don't overlap | ||
| 30 | * - src is readable | ||
| 31 | * - dst is writable | ||
| 32 | * memcpy uses the standard calling convention | ||
| 33 | * | ||
| 34 | * __copy_user copies up to len bytes from src to dst and sets a2 (len) to | ||
| 35 | * the number of uncopied bytes due to an exception caused by a read or write. | ||
| 36 | * __copy_user assumes that src and dst don't overlap, and that the call is | ||
| 37 | * implementing one of the following: | ||
| 38 | * copy_to_user | ||
| 39 | * - src is readable (no exceptions when reading src) | ||
| 40 | * copy_from_user | ||
| 41 | * - dst is writable (no exceptions when writing dst) | ||
| 42 | * __copy_user uses a non-standard calling convention; see | ||
| 43 | * arch/mips/include/asm/uaccess.h | ||
| 44 | * | ||
| 45 | * When an exception happens on a load, the handler must | ||
| 46 | # ensure that all of the destination buffer is overwritten to prevent | ||
| 47 | * leaking information to user mode programs. | ||
| 48 | */ | ||
| 49 | |||
| 50 | /* | ||
| 51 | * Implementation | ||
| 52 | */ | ||
| 53 | |||
| 54 | /* | ||
| 55 | * The exception handler for loads requires that: | ||
| 56 | * 1- AT contain the address of the byte just past the end of the source | ||
| 57 | * of the copy, | ||
| 58 | * 2- src_entry <= src < AT, and | ||
| 59 | * 3- (dst - src) == (dst_entry - src_entry), | ||
| 60 | * The _entry suffix denotes values when __copy_user was called. | ||
| 61 | * | ||
| 62 | * (1) is set up up by uaccess.h and maintained by not writing AT in copy_user | ||
| 63 | * (2) is met by incrementing src by the number of bytes copied | ||
| 64 | * (3) is met by not doing loads between a pair of increments of dst and src | ||
| 65 | * | ||
| 66 | * The exception handlers for stores adjust len (if necessary) and return. | ||
| 67 | * These handlers do not need to overwrite any data. | ||
| 68 | * | ||
| 69 | * For __rmemcpy and memmove an exception is always a kernel bug, therefore | ||
| 70 | * they're not protected. | ||
| 71 | */ | ||
| 72 | |||
| 73 | #define EXC(inst_reg,addr,handler) \ | ||
| 74 | 9: inst_reg, addr; \ | ||
| 75 | .section __ex_table,"a"; \ | ||
| 76 | PTR 9b, handler; \ | ||
| 77 | .previous | ||
| 78 | |||
| 79 | /* | ||
| 80 | * Only on the 64-bit kernel we can made use of 64-bit registers. | ||
| 81 | */ | ||
| 82 | #ifdef CONFIG_64BIT | ||
| 83 | #define USE_DOUBLE | ||
| 84 | #endif | ||
| 85 | |||
| 86 | #ifdef USE_DOUBLE | ||
| 87 | |||
| 88 | #define LOAD ld | ||
| 89 | #define LOADL ldl | ||
| 90 | #define LOADR ldr | ||
| 91 | #define STOREL sdl | ||
| 92 | #define STORER sdr | ||
| 93 | #define STORE sd | ||
| 94 | #define ADD daddu | ||
| 95 | #define SUB dsubu | ||
| 96 | #define SRL dsrl | ||
| 97 | #define SRA dsra | ||
| 98 | #define SLL dsll | ||
| 99 | #define SLLV dsllv | ||
| 100 | #define SRLV dsrlv | ||
| 101 | #define NBYTES 8 | ||
| 102 | #define LOG_NBYTES 3 | ||
| 103 | |||
| 104 | /* | ||
| 105 | * As we are sharing code base with the mips32 tree (which use the o32 ABI | ||
| 106 | * register definitions). We need to redefine the register definitions from | ||
| 107 | * the n64 ABI register naming to the o32 ABI register naming. | ||
| 108 | */ | ||
| 109 | #undef t0 | ||
| 110 | #undef t1 | ||
| 111 | #undef t2 | ||
| 112 | #undef t3 | ||
| 113 | #define t0 $8 | ||
| 114 | #define t1 $9 | ||
| 115 | #define t2 $10 | ||
| 116 | #define t3 $11 | ||
| 117 | #define t4 $12 | ||
| 118 | #define t5 $13 | ||
| 119 | #define t6 $14 | ||
| 120 | #define t7 $15 | ||
| 121 | |||
| 122 | #else | ||
| 123 | |||
| 124 | #define LOAD lw | ||
| 125 | #define LOADL lwl | ||
| 126 | #define LOADR lwr | ||
| 127 | #define STOREL swl | ||
| 128 | #define STORER swr | ||
| 129 | #define STORE sw | ||
| 130 | #define ADD addu | ||
| 131 | #define SUB subu | ||
| 132 | #define SRL srl | ||
| 133 | #define SLL sll | ||
| 134 | #define SRA sra | ||
| 135 | #define SLLV sllv | ||
| 136 | #define SRLV srlv | ||
| 137 | #define NBYTES 4 | ||
| 138 | #define LOG_NBYTES 2 | ||
| 139 | |||
| 140 | #endif /* USE_DOUBLE */ | ||
| 141 | |||
| 142 | #ifdef CONFIG_CPU_LITTLE_ENDIAN | ||
| 143 | #define LDFIRST LOADR | ||
| 144 | #define LDREST LOADL | ||
| 145 | #define STFIRST STORER | ||
| 146 | #define STREST STOREL | ||
| 147 | #define SHIFT_DISCARD SLLV | ||
| 148 | #else | ||
| 149 | #define LDFIRST LOADL | ||
| 150 | #define LDREST LOADR | ||
| 151 | #define STFIRST STOREL | ||
| 152 | #define STREST STORER | ||
| 153 | #define SHIFT_DISCARD SRLV | ||
| 154 | #endif | ||
| 155 | |||
| 156 | #define FIRST(unit) ((unit)*NBYTES) | ||
| 157 | #define REST(unit) (FIRST(unit)+NBYTES-1) | ||
| 158 | #define UNIT(unit) FIRST(unit) | ||
| 159 | |||
| 160 | #define ADDRMASK (NBYTES-1) | ||
| 161 | |||
| 162 | .text | ||
| 163 | .set noreorder | ||
| 164 | .set noat | ||
| 165 | |||
| 166 | /* | ||
| 167 | * A combined memcpy/__copy_user | ||
| 168 | * __copy_user sets len to 0 for success; else to an upper bound of | ||
| 169 | * the number of uncopied bytes. | ||
| 170 | * memcpy sets v0 to dst. | ||
| 171 | */ | ||
| 172 | .align 5 | ||
| 173 | LEAF(memcpy) /* a0=dst a1=src a2=len */ | ||
| 174 | move v0, dst /* return value */ | ||
| 175 | __memcpy: | ||
| 176 | FEXPORT(__copy_user) | ||
| 177 | /* | ||
| 178 | * Note: dst & src may be unaligned, len may be 0 | ||
| 179 | * Temps | ||
| 180 | */ | ||
| 181 | # | ||
| 182 | # Octeon doesn't care if the destination is unaligned. The hardware | ||
| 183 | # can fix it faster than we can special case the assembly. | ||
| 184 | # | ||
| 185 | pref 0, 0(src) | ||
| 186 | sltu t0, len, NBYTES # Check if < 1 word | ||
| 187 | bnez t0, copy_bytes_checklen | ||
| 188 | and t0, src, ADDRMASK # Check if src unaligned | ||
| 189 | bnez t0, src_unaligned | ||
| 190 | sltu t0, len, 4*NBYTES # Check if < 4 words | ||
| 191 | bnez t0, less_than_4units | ||
| 192 | sltu t0, len, 8*NBYTES # Check if < 8 words | ||
| 193 | bnez t0, less_than_8units | ||
| 194 | sltu t0, len, 16*NBYTES # Check if < 16 words | ||
| 195 | bnez t0, cleanup_both_aligned | ||
| 196 | sltu t0, len, 128+1 # Check if len < 129 | ||
| 197 | bnez t0, 1f # Skip prefetch if len is too short | ||
| 198 | sltu t0, len, 256+1 # Check if len < 257 | ||
| 199 | bnez t0, 1f # Skip prefetch if len is too short | ||
| 200 | pref 0, 128(src) # We must not prefetch invalid addresses | ||
| 201 | # | ||
| 202 | # This is where we loop if there is more than 128 bytes left | ||
| 203 | 2: pref 0, 256(src) # We must not prefetch invalid addresses | ||
| 204 | # | ||
| 205 | # This is where we loop if we can't prefetch anymore | ||
| 206 | 1: | ||
| 207 | EXC( LOAD t0, UNIT(0)(src), l_exc) | ||
| 208 | EXC( LOAD t1, UNIT(1)(src), l_exc_copy) | ||
| 209 | EXC( LOAD t2, UNIT(2)(src), l_exc_copy) | ||
| 210 | EXC( LOAD t3, UNIT(3)(src), l_exc_copy) | ||
| 211 | SUB len, len, 16*NBYTES | ||
| 212 | EXC( STORE t0, UNIT(0)(dst), s_exc_p16u) | ||
| 213 | EXC( STORE t1, UNIT(1)(dst), s_exc_p15u) | ||
| 214 | EXC( STORE t2, UNIT(2)(dst), s_exc_p14u) | ||
| 215 | EXC( STORE t3, UNIT(3)(dst), s_exc_p13u) | ||
| 216 | EXC( LOAD t0, UNIT(4)(src), l_exc_copy) | ||
| 217 | EXC( LOAD t1, UNIT(5)(src), l_exc_copy) | ||
| 218 | EXC( LOAD t2, UNIT(6)(src), l_exc_copy) | ||
| 219 | EXC( LOAD t3, UNIT(7)(src), l_exc_copy) | ||
| 220 | EXC( STORE t0, UNIT(4)(dst), s_exc_p12u) | ||
| 221 | EXC( STORE t1, UNIT(5)(dst), s_exc_p11u) | ||
| 222 | EXC( STORE t2, UNIT(6)(dst), s_exc_p10u) | ||
| 223 | ADD src, src, 16*NBYTES | ||
| 224 | EXC( STORE t3, UNIT(7)(dst), s_exc_p9u) | ||
| 225 | ADD dst, dst, 16*NBYTES | ||
| 226 | EXC( LOAD t0, UNIT(-8)(src), l_exc_copy) | ||
| 227 | EXC( LOAD t1, UNIT(-7)(src), l_exc_copy) | ||
| 228 | EXC( LOAD t2, UNIT(-6)(src), l_exc_copy) | ||
| 229 | EXC( LOAD t3, UNIT(-5)(src), l_exc_copy) | ||
| 230 | EXC( STORE t0, UNIT(-8)(dst), s_exc_p8u) | ||
| 231 | EXC( STORE t1, UNIT(-7)(dst), s_exc_p7u) | ||
| 232 | EXC( STORE t2, UNIT(-6)(dst), s_exc_p6u) | ||
| 233 | EXC( STORE t3, UNIT(-5)(dst), s_exc_p5u) | ||
| 234 | EXC( LOAD t0, UNIT(-4)(src), l_exc_copy) | ||
| 235 | EXC( LOAD t1, UNIT(-3)(src), l_exc_copy) | ||
| 236 | EXC( LOAD t2, UNIT(-2)(src), l_exc_copy) | ||
| 237 | EXC( LOAD t3, UNIT(-1)(src), l_exc_copy) | ||
| 238 | EXC( STORE t0, UNIT(-4)(dst), s_exc_p4u) | ||
| 239 | EXC( STORE t1, UNIT(-3)(dst), s_exc_p3u) | ||
| 240 | EXC( STORE t2, UNIT(-2)(dst), s_exc_p2u) | ||
| 241 | EXC( STORE t3, UNIT(-1)(dst), s_exc_p1u) | ||
| 242 | sltu t0, len, 256+1 # See if we can prefetch more | ||
| 243 | beqz t0, 2b | ||
| 244 | sltu t0, len, 128 # See if we can loop more time | ||
| 245 | beqz t0, 1b | ||
| 246 | nop | ||
| 247 | # | ||
| 248 | # Jump here if there are less than 16*NBYTES left. | ||
| 249 | # | ||
| 250 | cleanup_both_aligned: | ||
| 251 | beqz len, done | ||
| 252 | sltu t0, len, 8*NBYTES | ||
| 253 | bnez t0, less_than_8units | ||
| 254 | nop | ||
| 255 | EXC( LOAD t0, UNIT(0)(src), l_exc) | ||
| 256 | EXC( LOAD t1, UNIT(1)(src), l_exc_copy) | ||
| 257 | EXC( LOAD t2, UNIT(2)(src), l_exc_copy) | ||
| 258 | EXC( LOAD t3, UNIT(3)(src), l_exc_copy) | ||
| 259 | SUB len, len, 8*NBYTES | ||
| 260 | EXC( STORE t0, UNIT(0)(dst), s_exc_p8u) | ||
| 261 | EXC( STORE t1, UNIT(1)(dst), s_exc_p7u) | ||
| 262 | EXC( STORE t2, UNIT(2)(dst), s_exc_p6u) | ||
| 263 | EXC( STORE t3, UNIT(3)(dst), s_exc_p5u) | ||
| 264 | EXC( LOAD t0, UNIT(4)(src), l_exc_copy) | ||
| 265 | EXC( LOAD t1, UNIT(5)(src), l_exc_copy) | ||
| 266 | EXC( LOAD t2, UNIT(6)(src), l_exc_copy) | ||
| 267 | EXC( LOAD t3, UNIT(7)(src), l_exc_copy) | ||
| 268 | EXC( STORE t0, UNIT(4)(dst), s_exc_p4u) | ||
| 269 | EXC( STORE t1, UNIT(5)(dst), s_exc_p3u) | ||
| 270 | EXC( STORE t2, UNIT(6)(dst), s_exc_p2u) | ||
| 271 | EXC( STORE t3, UNIT(7)(dst), s_exc_p1u) | ||
| 272 | ADD src, src, 8*NBYTES | ||
| 273 | beqz len, done | ||
| 274 | ADD dst, dst, 8*NBYTES | ||
| 275 | # | ||
| 276 | # Jump here if there are less than 8*NBYTES left. | ||
| 277 | # | ||
| 278 | less_than_8units: | ||
| 279 | sltu t0, len, 4*NBYTES | ||
| 280 | bnez t0, less_than_4units | ||
| 281 | nop | ||
| 282 | EXC( LOAD t0, UNIT(0)(src), l_exc) | ||
| 283 | EXC( LOAD t1, UNIT(1)(src), l_exc_copy) | ||
| 284 | EXC( LOAD t2, UNIT(2)(src), l_exc_copy) | ||
| 285 | EXC( LOAD t3, UNIT(3)(src), l_exc_copy) | ||
| 286 | SUB len, len, 4*NBYTES | ||
| 287 | EXC( STORE t0, UNIT(0)(dst), s_exc_p4u) | ||
| 288 | EXC( STORE t1, UNIT(1)(dst), s_exc_p3u) | ||
| 289 | EXC( STORE t2, UNIT(2)(dst), s_exc_p2u) | ||
| 290 | EXC( STORE t3, UNIT(3)(dst), s_exc_p1u) | ||
| 291 | ADD src, src, 4*NBYTES | ||
| 292 | beqz len, done | ||
| 293 | ADD dst, dst, 4*NBYTES | ||
| 294 | # | ||
| 295 | # Jump here if there are less than 4*NBYTES left. This means | ||
| 296 | # we may need to copy up to 3 NBYTES words. | ||
| 297 | # | ||
| 298 | less_than_4units: | ||
| 299 | sltu t0, len, 1*NBYTES | ||
| 300 | bnez t0, copy_bytes_checklen | ||
| 301 | nop | ||
| 302 | # | ||
| 303 | # 1) Copy NBYTES, then check length again | ||
| 304 | # | ||
| 305 | EXC( LOAD t0, 0(src), l_exc) | ||
| 306 | SUB len, len, NBYTES | ||
| 307 | sltu t1, len, 8 | ||
| 308 | EXC( STORE t0, 0(dst), s_exc_p1u) | ||
| 309 | ADD src, src, NBYTES | ||
| 310 | bnez t1, copy_bytes_checklen | ||
| 311 | ADD dst, dst, NBYTES | ||
| 312 | # | ||
| 313 | # 2) Copy NBYTES, then check length again | ||
| 314 | # | ||
| 315 | EXC( LOAD t0, 0(src), l_exc) | ||
| 316 | SUB len, len, NBYTES | ||
| 317 | sltu t1, len, 8 | ||
| 318 | EXC( STORE t0, 0(dst), s_exc_p1u) | ||
| 319 | ADD src, src, NBYTES | ||
| 320 | bnez t1, copy_bytes_checklen | ||
| 321 | ADD dst, dst, NBYTES | ||
| 322 | # | ||
| 323 | # 3) Copy NBYTES, then check length again | ||
| 324 | # | ||
| 325 | EXC( LOAD t0, 0(src), l_exc) | ||
| 326 | SUB len, len, NBYTES | ||
| 327 | ADD src, src, NBYTES | ||
| 328 | ADD dst, dst, NBYTES | ||
| 329 | b copy_bytes_checklen | ||
| 330 | EXC( STORE t0, -8(dst), s_exc_p1u) | ||
| 331 | |||
| 332 | src_unaligned: | ||
| 333 | #define rem t8 | ||
| 334 | SRL t0, len, LOG_NBYTES+2 # +2 for 4 units/iter | ||
| 335 | beqz t0, cleanup_src_unaligned | ||
| 336 | and rem, len, (4*NBYTES-1) # rem = len % 4*NBYTES | ||
| 337 | 1: | ||
| 338 | /* | ||
| 339 | * Avoid consecutive LD*'s to the same register since some mips | ||
| 340 | * implementations can't issue them in the same cycle. | ||
| 341 | * It's OK to load FIRST(N+1) before REST(N) because the two addresses | ||
| 342 | * are to the same unit (unless src is aligned, but it's not). | ||
| 343 | */ | ||
| 344 | EXC( LDFIRST t0, FIRST(0)(src), l_exc) | ||
| 345 | EXC( LDFIRST t1, FIRST(1)(src), l_exc_copy) | ||
| 346 | SUB len, len, 4*NBYTES | ||
| 347 | EXC( LDREST t0, REST(0)(src), l_exc_copy) | ||
| 348 | EXC( LDREST t1, REST(1)(src), l_exc_copy) | ||
| 349 | EXC( LDFIRST t2, FIRST(2)(src), l_exc_copy) | ||
| 350 | EXC( LDFIRST t3, FIRST(3)(src), l_exc_copy) | ||
| 351 | EXC( LDREST t2, REST(2)(src), l_exc_copy) | ||
| 352 | EXC( LDREST t3, REST(3)(src), l_exc_copy) | ||
| 353 | ADD src, src, 4*NBYTES | ||
| 354 | EXC( STORE t0, UNIT(0)(dst), s_exc_p4u) | ||
| 355 | EXC( STORE t1, UNIT(1)(dst), s_exc_p3u) | ||
| 356 | EXC( STORE t2, UNIT(2)(dst), s_exc_p2u) | ||
| 357 | EXC( STORE t3, UNIT(3)(dst), s_exc_p1u) | ||
| 358 | bne len, rem, 1b | ||
| 359 | ADD dst, dst, 4*NBYTES | ||
| 360 | |||
| 361 | cleanup_src_unaligned: | ||
| 362 | beqz len, done | ||
| 363 | and rem, len, NBYTES-1 # rem = len % NBYTES | ||
| 364 | beq rem, len, copy_bytes | ||
| 365 | nop | ||
| 366 | 1: | ||
| 367 | EXC( LDFIRST t0, FIRST(0)(src), l_exc) | ||
| 368 | EXC( LDREST t0, REST(0)(src), l_exc_copy) | ||
| 369 | SUB len, len, NBYTES | ||
| 370 | EXC( STORE t0, 0(dst), s_exc_p1u) | ||
| 371 | ADD src, src, NBYTES | ||
| 372 | bne len, rem, 1b | ||
| 373 | ADD dst, dst, NBYTES | ||
| 374 | |||
| 375 | copy_bytes_checklen: | ||
| 376 | beqz len, done | ||
| 377 | nop | ||
| 378 | copy_bytes: | ||
| 379 | /* 0 < len < NBYTES */ | ||
| 380 | #define COPY_BYTE(N) \ | ||
| 381 | EXC( lb t0, N(src), l_exc); \ | ||
| 382 | SUB len, len, 1; \ | ||
| 383 | beqz len, done; \ | ||
| 384 | EXC( sb t0, N(dst), s_exc_p1) | ||
| 385 | |||
| 386 | COPY_BYTE(0) | ||
| 387 | COPY_BYTE(1) | ||
| 388 | #ifdef USE_DOUBLE | ||
| 389 | COPY_BYTE(2) | ||
| 390 | COPY_BYTE(3) | ||
| 391 | COPY_BYTE(4) | ||
| 392 | COPY_BYTE(5) | ||
| 393 | #endif | ||
| 394 | EXC( lb t0, NBYTES-2(src), l_exc) | ||
| 395 | SUB len, len, 1 | ||
| 396 | jr ra | ||
| 397 | EXC( sb t0, NBYTES-2(dst), s_exc_p1) | ||
| 398 | done: | ||
| 399 | jr ra | ||
| 400 | nop | ||
| 401 | END(memcpy) | ||
| 402 | |||
| 403 | l_exc_copy: | ||
| 404 | /* | ||
| 405 | * Copy bytes from src until faulting load address (or until a | ||
| 406 | * lb faults) | ||
| 407 | * | ||
| 408 | * When reached by a faulting LDFIRST/LDREST, THREAD_BUADDR($28) | ||
| 409 | * may be more than a byte beyond the last address. | ||
| 410 | * Hence, the lb below may get an exception. | ||
| 411 | * | ||
| 412 | * Assumes src < THREAD_BUADDR($28) | ||
| 413 | */ | ||
| 414 | LOAD t0, TI_TASK($28) | ||
| 415 | nop | ||
| 416 | LOAD t0, THREAD_BUADDR(t0) | ||
| 417 | 1: | ||
| 418 | EXC( lb t1, 0(src), l_exc) | ||
| 419 | ADD src, src, 1 | ||
| 420 | sb t1, 0(dst) # can't fault -- we're copy_from_user | ||
| 421 | bne src, t0, 1b | ||
| 422 | ADD dst, dst, 1 | ||
| 423 | l_exc: | ||
| 424 | LOAD t0, TI_TASK($28) | ||
| 425 | nop | ||
| 426 | LOAD t0, THREAD_BUADDR(t0) # t0 is just past last good address | ||
| 427 | nop | ||
| 428 | SUB len, AT, t0 # len number of uncopied bytes | ||
| 429 | /* | ||
| 430 | * Here's where we rely on src and dst being incremented in tandem, | ||
| 431 | * See (3) above. | ||
| 432 | * dst += (fault addr - src) to put dst at first byte to clear | ||
| 433 | */ | ||
| 434 | ADD dst, t0 # compute start address in a1 | ||
| 435 | SUB dst, src | ||
| 436 | /* | ||
| 437 | * Clear len bytes starting at dst. Can't call __bzero because it | ||
| 438 | * might modify len. An inefficient loop for these rare times... | ||
| 439 | */ | ||
| 440 | beqz len, done | ||
| 441 | SUB src, len, 1 | ||
| 442 | 1: sb zero, 0(dst) | ||
| 443 | ADD dst, dst, 1 | ||
| 444 | bnez src, 1b | ||
| 445 | SUB src, src, 1 | ||
| 446 | jr ra | ||
| 447 | nop | ||
| 448 | |||
| 449 | |||
| 450 | #define SEXC(n) \ | ||
| 451 | s_exc_p ## n ## u: \ | ||
| 452 | jr ra; \ | ||
| 453 | ADD len, len, n*NBYTES | ||
| 454 | |||
| 455 | SEXC(16) | ||
| 456 | SEXC(15) | ||
| 457 | SEXC(14) | ||
| 458 | SEXC(13) | ||
| 459 | SEXC(12) | ||
| 460 | SEXC(11) | ||
| 461 | SEXC(10) | ||
| 462 | SEXC(9) | ||
| 463 | SEXC(8) | ||
| 464 | SEXC(7) | ||
| 465 | SEXC(6) | ||
| 466 | SEXC(5) | ||
| 467 | SEXC(4) | ||
| 468 | SEXC(3) | ||
| 469 | SEXC(2) | ||
| 470 | SEXC(1) | ||
| 471 | |||
| 472 | s_exc_p1: | ||
| 473 | jr ra | ||
| 474 | ADD len, len, 1 | ||
| 475 | s_exc: | ||
| 476 | jr ra | ||
| 477 | nop | ||
| 478 | |||
| 479 | .align 5 | ||
| 480 | LEAF(memmove) | ||
| 481 | ADD t0, a0, a2 | ||
| 482 | ADD t1, a1, a2 | ||
| 483 | sltu t0, a1, t0 # dst + len <= src -> memcpy | ||
| 484 | sltu t1, a0, t1 # dst >= src + len -> memcpy | ||
| 485 | and t0, t1 | ||
| 486 | beqz t0, __memcpy | ||
| 487 | move v0, a0 /* return value */ | ||
| 488 | beqz a2, r_out | ||
| 489 | END(memmove) | ||
| 490 | |||
| 491 | /* fall through to __rmemcpy */ | ||
| 492 | LEAF(__rmemcpy) /* a0=dst a1=src a2=len */ | ||
| 493 | sltu t0, a1, a0 | ||
| 494 | beqz t0, r_end_bytes_up # src >= dst | ||
| 495 | nop | ||
| 496 | ADD a0, a2 # dst = dst + len | ||
| 497 | ADD a1, a2 # src = src + len | ||
| 498 | |||
| 499 | r_end_bytes: | ||
| 500 | lb t0, -1(a1) | ||
| 501 | SUB a2, a2, 0x1 | ||
| 502 | sb t0, -1(a0) | ||
| 503 | SUB a1, a1, 0x1 | ||
| 504 | bnez a2, r_end_bytes | ||
| 505 | SUB a0, a0, 0x1 | ||
| 506 | |||
| 507 | r_out: | ||
| 508 | jr ra | ||
| 509 | move a2, zero | ||
| 510 | |||
| 511 | r_end_bytes_up: | ||
| 512 | lb t0, (a1) | ||
| 513 | SUB a2, a2, 0x1 | ||
| 514 | sb t0, (a0) | ||
| 515 | ADD a1, a1, 0x1 | ||
| 516 | bnez a2, r_end_bytes_up | ||
| 517 | ADD a0, a0, 0x1 | ||
| 518 | |||
| 519 | jr ra | ||
| 520 | move a2, zero | ||
| 521 | END(__rmemcpy) | ||
diff --git a/arch/mips/cavium-octeon/serial.c b/arch/mips/cavium-octeon/serial.c new file mode 100644 index 000000000000..8240728d485a --- /dev/null +++ b/arch/mips/cavium-octeon/serial.c | |||
| @@ -0,0 +1,136 @@ | |||
| 1 | /* | ||
| 2 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 3 | * License. See the file "COPYING" in the main directory of this archive | ||
| 4 | * for more details. | ||
| 5 | * | ||
| 6 | * Copyright (C) 2004-2007 Cavium Networks | ||
| 7 | */ | ||
| 8 | #include <linux/console.h> | ||
| 9 | #include <linux/module.h> | ||
| 10 | #include <linux/init.h> | ||
| 11 | #include <linux/platform_device.h> | ||
| 12 | #include <linux/serial.h> | ||
| 13 | #include <linux/serial_8250.h> | ||
| 14 | #include <linux/serial_reg.h> | ||
| 15 | #include <linux/tty.h> | ||
| 16 | |||
| 17 | #include <asm/time.h> | ||
| 18 | |||
| 19 | #include <asm/octeon/octeon.h> | ||
| 20 | |||
| 21 | #ifdef CONFIG_GDB_CONSOLE | ||
| 22 | #define DEBUG_UART 0 | ||
| 23 | #else | ||
| 24 | #define DEBUG_UART 1 | ||
| 25 | #endif | ||
| 26 | |||
| 27 | unsigned int octeon_serial_in(struct uart_port *up, int offset) | ||
| 28 | { | ||
| 29 | int rv = cvmx_read_csr((uint64_t)(up->membase + (offset << 3))); | ||
| 30 | if (offset == UART_IIR && (rv & 0xf) == 7) { | ||
| 31 | /* Busy interrupt, read the USR (39) and try again. */ | ||
| 32 | cvmx_read_csr((uint64_t)(up->membase + (39 << 3))); | ||
| 33 | rv = cvmx_read_csr((uint64_t)(up->membase + (offset << 3))); | ||
| 34 | } | ||
| 35 | return rv; | ||
| 36 | } | ||
| 37 | |||
| 38 | void octeon_serial_out(struct uart_port *up, int offset, int value) | ||
| 39 | { | ||
| 40 | /* | ||
| 41 | * If bits 6 or 7 of the OCTEON UART's LCR are set, it quits | ||
| 42 | * working. | ||
| 43 | */ | ||
| 44 | if (offset == UART_LCR) | ||
| 45 | value &= 0x9f; | ||
| 46 | cvmx_write_csr((uint64_t)(up->membase + (offset << 3)), (u8)value); | ||
| 47 | } | ||
| 48 | |||
| 49 | /* | ||
| 50 | * Allocated in .bss, so it is all zeroed. | ||
| 51 | */ | ||
| 52 | #define OCTEON_MAX_UARTS 3 | ||
| 53 | static struct plat_serial8250_port octeon_uart8250_data[OCTEON_MAX_UARTS + 1]; | ||
| 54 | static struct platform_device octeon_uart8250_device = { | ||
| 55 | .name = "serial8250", | ||
| 56 | .id = PLAT8250_DEV_PLATFORM, | ||
| 57 | .dev = { | ||
| 58 | .platform_data = octeon_uart8250_data, | ||
| 59 | }, | ||
| 60 | }; | ||
| 61 | |||
| 62 | static void __init octeon_uart_set_common(struct plat_serial8250_port *p) | ||
| 63 | { | ||
| 64 | p->flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE; | ||
| 65 | p->type = PORT_OCTEON; | ||
| 66 | p->iotype = UPIO_MEM; | ||
| 67 | p->regshift = 3; /* I/O addresses are every 8 bytes */ | ||
| 68 | p->uartclk = mips_hpt_frequency; | ||
| 69 | p->serial_in = octeon_serial_in; | ||
| 70 | p->serial_out = octeon_serial_out; | ||
| 71 | } | ||
| 72 | |||
| 73 | static int __init octeon_serial_init(void) | ||
| 74 | { | ||
| 75 | int enable_uart0; | ||
| 76 | int enable_uart1; | ||
| 77 | int enable_uart2; | ||
| 78 | struct plat_serial8250_port *p; | ||
| 79 | |||
| 80 | #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL | ||
| 81 | /* | ||
| 82 | * If we are configured to run as the second of two kernels, | ||
| 83 | * disable uart0 and enable uart1. Uart0 is owned by the first | ||
| 84 | * kernel | ||
| 85 | */ | ||
| 86 | enable_uart0 = 0; | ||
| 87 | enable_uart1 = 1; | ||
| 88 | #else | ||
| 89 | /* | ||
| 90 | * We are configured for the first kernel. We'll enable uart0 | ||
| 91 | * if the bootloader told us to use 0, otherwise will enable | ||
| 92 | * uart 1. | ||
| 93 | */ | ||
| 94 | enable_uart0 = (octeon_get_boot_uart() == 0); | ||
| 95 | enable_uart1 = (octeon_get_boot_uart() == 1); | ||
| 96 | #ifdef CONFIG_KGDB | ||
| 97 | enable_uart1 = 1; | ||
| 98 | #endif | ||
| 99 | #endif | ||
| 100 | |||
| 101 | /* Right now CN52XX is the only chip with a third uart */ | ||
| 102 | enable_uart2 = OCTEON_IS_MODEL(OCTEON_CN52XX); | ||
| 103 | |||
| 104 | p = octeon_uart8250_data; | ||
| 105 | if (enable_uart0) { | ||
| 106 | /* Add a ttyS device for hardware uart 0 */ | ||
| 107 | octeon_uart_set_common(p); | ||
| 108 | p->membase = (void *) CVMX_MIO_UARTX_RBR(0); | ||
| 109 | p->mapbase = CVMX_MIO_UARTX_RBR(0) & ((1ull << 49) - 1); | ||
| 110 | p->irq = OCTEON_IRQ_UART0; | ||
| 111 | p++; | ||
| 112 | } | ||
| 113 | |||
| 114 | if (enable_uart1) { | ||
| 115 | /* Add a ttyS device for hardware uart 1 */ | ||
| 116 | octeon_uart_set_common(p); | ||
| 117 | p->membase = (void *) CVMX_MIO_UARTX_RBR(1); | ||
| 118 | p->mapbase = CVMX_MIO_UARTX_RBR(1) & ((1ull << 49) - 1); | ||
| 119 | p->irq = OCTEON_IRQ_UART1; | ||
| 120 | p++; | ||
| 121 | } | ||
| 122 | if (enable_uart2) { | ||
| 123 | /* Add a ttyS device for hardware uart 2 */ | ||
| 124 | octeon_uart_set_common(p); | ||
| 125 | p->membase = (void *) CVMX_MIO_UART2_RBR; | ||
| 126 | p->mapbase = CVMX_MIO_UART2_RBR & ((1ull << 49) - 1); | ||
| 127 | p->irq = OCTEON_IRQ_UART2; | ||
| 128 | p++; | ||
| 129 | } | ||
| 130 | |||
| 131 | BUG_ON(p > &octeon_uart8250_data[OCTEON_MAX_UARTS]); | ||
| 132 | |||
| 133 | return platform_device_register(&octeon_uart8250_device); | ||
| 134 | } | ||
| 135 | |||
| 136 | device_initcall(octeon_serial_init); | ||
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c new file mode 100644 index 000000000000..e085feddb4a4 --- /dev/null +++ b/arch/mips/cavium-octeon/setup.c | |||
| @@ -0,0 +1,929 @@ | |||
| 1 | /* | ||
| 2 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 3 | * License. See the file "COPYING" in the main directory of this archive | ||
| 4 | * for more details. | ||
| 5 | * | ||
| 6 | * Copyright (C) 2004-2007 Cavium Networks | ||
| 7 | * Copyright (C) 2008 Wind River Systems | ||
| 8 | */ | ||
| 9 | #include <linux/init.h> | ||
| 10 | #include <linux/console.h> | ||
| 11 | #include <linux/delay.h> | ||
| 12 | #include <linux/interrupt.h> | ||
| 13 | #include <linux/io.h> | ||
| 14 | #include <linux/irq.h> | ||
| 15 | #include <linux/serial.h> | ||
| 16 | #include <linux/types.h> | ||
| 17 | #include <linux/string.h> /* for memset */ | ||
| 18 | #include <linux/serial.h> | ||
| 19 | #include <linux/tty.h> | ||
| 20 | #include <linux/time.h> | ||
| 21 | #include <linux/platform_device.h> | ||
| 22 | #include <linux/serial_core.h> | ||
| 23 | #include <linux/serial_8250.h> | ||
| 24 | #include <linux/string.h> | ||
| 25 | |||
| 26 | #include <asm/processor.h> | ||
| 27 | #include <asm/reboot.h> | ||
| 28 | #include <asm/smp-ops.h> | ||
| 29 | #include <asm/system.h> | ||
| 30 | #include <asm/irq_cpu.h> | ||
| 31 | #include <asm/mipsregs.h> | ||
| 32 | #include <asm/bootinfo.h> | ||
| 33 | #include <asm/sections.h> | ||
| 34 | #include <asm/time.h> | ||
| 35 | |||
| 36 | #include <asm/octeon/octeon.h> | ||
| 37 | |||
| 38 | #ifdef CONFIG_CAVIUM_DECODE_RSL | ||
| 39 | extern void cvmx_interrupt_rsl_decode(void); | ||
| 40 | extern int __cvmx_interrupt_ecc_report_single_bit_errors; | ||
| 41 | extern void cvmx_interrupt_rsl_enable(void); | ||
| 42 | #endif | ||
| 43 | |||
| 44 | extern struct plat_smp_ops octeon_smp_ops; | ||
| 45 | |||
| 46 | #ifdef CONFIG_PCI | ||
| 47 | extern void pci_console_init(const char *arg); | ||
| 48 | #endif | ||
| 49 | |||
| 50 | #ifdef CONFIG_CAVIUM_RESERVE32 | ||
| 51 | extern uint64_t octeon_reserve32_memory; | ||
| 52 | #endif | ||
| 53 | static unsigned long long MAX_MEMORY = 512ull << 20; | ||
| 54 | |||
| 55 | struct octeon_boot_descriptor *octeon_boot_desc_ptr; | ||
| 56 | |||
| 57 | struct cvmx_bootinfo *octeon_bootinfo; | ||
| 58 | EXPORT_SYMBOL(octeon_bootinfo); | ||
| 59 | |||
| 60 | #ifdef CONFIG_CAVIUM_RESERVE32 | ||
| 61 | uint64_t octeon_reserve32_memory; | ||
| 62 | EXPORT_SYMBOL(octeon_reserve32_memory); | ||
| 63 | #endif | ||
| 64 | |||
| 65 | static int octeon_uart; | ||
| 66 | |||
| 67 | extern asmlinkage void handle_int(void); | ||
| 68 | extern asmlinkage void plat_irq_dispatch(void); | ||
| 69 | |||
| 70 | /** | ||
| 71 | * Return non zero if we are currently running in the Octeon simulator | ||
| 72 | * | ||
| 73 | * Returns | ||
| 74 | */ | ||
| 75 | int octeon_is_simulation(void) | ||
| 76 | { | ||
| 77 | return octeon_bootinfo->board_type == CVMX_BOARD_TYPE_SIM; | ||
| 78 | } | ||
| 79 | EXPORT_SYMBOL(octeon_is_simulation); | ||
| 80 | |||
| 81 | /** | ||
| 82 | * Return true if Octeon is in PCI Host mode. This means | ||
| 83 | * Linux can control the PCI bus. | ||
| 84 | * | ||
| 85 | * Returns Non zero if Octeon in host mode. | ||
| 86 | */ | ||
| 87 | int octeon_is_pci_host(void) | ||
| 88 | { | ||
| 89 | #ifdef CONFIG_PCI | ||
| 90 | return octeon_bootinfo->config_flags & CVMX_BOOTINFO_CFG_FLAG_PCI_HOST; | ||
| 91 | #else | ||
| 92 | return 0; | ||
| 93 | #endif | ||
| 94 | } | ||
| 95 | |||
| 96 | /** | ||
| 97 | * Get the clock rate of Octeon | ||
| 98 | * | ||
| 99 | * Returns Clock rate in HZ | ||
| 100 | */ | ||
| 101 | uint64_t octeon_get_clock_rate(void) | ||
| 102 | { | ||
| 103 | if (octeon_is_simulation()) | ||
| 104 | octeon_bootinfo->eclock_hz = 6000000; | ||
| 105 | return octeon_bootinfo->eclock_hz; | ||
| 106 | } | ||
| 107 | EXPORT_SYMBOL(octeon_get_clock_rate); | ||
| 108 | |||
| 109 | /** | ||
| 110 | * Write to the LCD display connected to the bootbus. This display | ||
| 111 | * exists on most Cavium evaluation boards. If it doesn't exist, then | ||
| 112 | * this function doesn't do anything. | ||
| 113 | * | ||
| 114 | * @s: String to write | ||
| 115 | */ | ||
| 116 | void octeon_write_lcd(const char *s) | ||
| 117 | { | ||
| 118 | if (octeon_bootinfo->led_display_base_addr) { | ||
| 119 | void __iomem *lcd_address = | ||
| 120 | ioremap_nocache(octeon_bootinfo->led_display_base_addr, | ||
| 121 | 8); | ||
| 122 | int i; | ||
| 123 | for (i = 0; i < 8; i++, s++) { | ||
| 124 | if (*s) | ||
| 125 | iowrite8(*s, lcd_address + i); | ||
| 126 | else | ||
| 127 | iowrite8(' ', lcd_address + i); | ||
| 128 | } | ||
| 129 | iounmap(lcd_address); | ||
| 130 | } | ||
| 131 | } | ||
| 132 | |||
| 133 | /** | ||
| 134 | * Return the console uart passed by the bootloader | ||
| 135 | * | ||
| 136 | * Returns uart (0 or 1) | ||
| 137 | */ | ||
| 138 | int octeon_get_boot_uart(void) | ||
| 139 | { | ||
| 140 | int uart; | ||
| 141 | #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL | ||
| 142 | uart = 1; | ||
| 143 | #else | ||
| 144 | uart = (octeon_boot_desc_ptr->flags & OCTEON_BL_FLAG_CONSOLE_UART1) ? | ||
| 145 | 1 : 0; | ||
| 146 | #endif | ||
| 147 | return uart; | ||
| 148 | } | ||
| 149 | |||
| 150 | /** | ||
| 151 | * Get the coremask Linux was booted on. | ||
| 152 | * | ||
| 153 | * Returns Core mask | ||
| 154 | */ | ||
| 155 | int octeon_get_boot_coremask(void) | ||
| 156 | { | ||
| 157 | return octeon_boot_desc_ptr->core_mask; | ||
| 158 | } | ||
| 159 | |||
| 160 | /** | ||
| 161 | * Check the hardware BIST results for a CPU | ||
| 162 | */ | ||
| 163 | void octeon_check_cpu_bist(void) | ||
| 164 | { | ||
| 165 | const int coreid = cvmx_get_core_num(); | ||
| 166 | unsigned long long mask; | ||
| 167 | unsigned long long bist_val; | ||
| 168 | |||
| 169 | /* Check BIST results for COP0 registers */ | ||
| 170 | mask = 0x1f00000000ull; | ||
| 171 | bist_val = read_octeon_c0_icacheerr(); | ||
| 172 | if (bist_val & mask) | ||
| 173 | pr_err("Core%d BIST Failure: CacheErr(icache) = 0x%llx\n", | ||
| 174 | coreid, bist_val); | ||
| 175 | |||
| 176 | bist_val = read_octeon_c0_dcacheerr(); | ||
| 177 | if (bist_val & 1) | ||
| 178 | pr_err("Core%d L1 Dcache parity error: " | ||
| 179 | "CacheErr(dcache) = 0x%llx\n", | ||
| 180 | coreid, bist_val); | ||
| 181 | |||
| 182 | mask = 0xfc00000000000000ull; | ||
| 183 | bist_val = read_c0_cvmmemctl(); | ||
| 184 | if (bist_val & mask) | ||
| 185 | pr_err("Core%d BIST Failure: COP0_CVM_MEM_CTL = 0x%llx\n", | ||
| 186 | coreid, bist_val); | ||
| 187 | |||
| 188 | write_octeon_c0_dcacheerr(0); | ||
| 189 | } | ||
| 190 | |||
| 191 | #ifdef CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB | ||
| 192 | /** | ||
| 193 | * Called on every core to setup the wired tlb entry needed | ||
| 194 | * if CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB is set. | ||
| 195 | * | ||
| 196 | */ | ||
| 197 | static void octeon_hal_setup_per_cpu_reserved32(void *unused) | ||
| 198 | { | ||
| 199 | /* | ||
| 200 | * The config has selected to wire the reserve32 memory for all | ||
| 201 | * userspace applications. We need to put a wired TLB entry in for each | ||
| 202 | * 512MB of reserve32 memory. We only handle double 256MB pages here, | ||
| 203 | * so reserve32 must be multiple of 512MB. | ||
| 204 | */ | ||
| 205 | uint32_t size = CONFIG_CAVIUM_RESERVE32; | ||
| 206 | uint32_t entrylo0 = | ||
| 207 | 0x7 | ((octeon_reserve32_memory & ((1ul << 40) - 1)) >> 6); | ||
| 208 | uint32_t entrylo1 = entrylo0 + (256 << 14); | ||
| 209 | uint32_t entryhi = (0x80000000UL - (CONFIG_CAVIUM_RESERVE32 << 20)); | ||
| 210 | while (size >= 512) { | ||
| 211 | #if 0 | ||
| 212 | pr_info("CPU%d: Adding double wired TLB entry for 0x%lx\n", | ||
| 213 | smp_processor_id(), entryhi); | ||
| 214 | #endif | ||
| 215 | add_wired_entry(entrylo0, entrylo1, entryhi, PM_256M); | ||
| 216 | entrylo0 += 512 << 14; | ||
| 217 | entrylo1 += 512 << 14; | ||
| 218 | entryhi += 512 << 20; | ||
| 219 | size -= 512; | ||
| 220 | } | ||
| 221 | } | ||
| 222 | #endif /* CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB */ | ||
| 223 | |||
| 224 | /** | ||
| 225 | * Called to release the named block which was used to made sure | ||
| 226 | * that nobody used the memory for something else during | ||
| 227 | * init. Now we'll free it so userspace apps can use this | ||
| 228 | * memory region with bootmem_alloc. | ||
| 229 | * | ||
| 230 | * This function is called only once from prom_free_prom_memory(). | ||
| 231 | */ | ||
| 232 | void octeon_hal_setup_reserved32(void) | ||
| 233 | { | ||
| 234 | #ifdef CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB | ||
| 235 | on_each_cpu(octeon_hal_setup_per_cpu_reserved32, NULL, 0, 1); | ||
| 236 | #endif | ||
| 237 | } | ||
| 238 | |||
| 239 | /** | ||
| 240 | * Reboot Octeon | ||
| 241 | * | ||
| 242 | * @command: Command to pass to the bootloader. Currently ignored. | ||
| 243 | */ | ||
| 244 | static void octeon_restart(char *command) | ||
| 245 | { | ||
| 246 | /* Disable all watchdogs before soft reset. They don't get cleared */ | ||
| 247 | #ifdef CONFIG_SMP | ||
| 248 | int cpu; | ||
| 249 | for_each_online_cpu(cpu) | ||
| 250 | cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0); | ||
| 251 | #else | ||
| 252 | cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); | ||
| 253 | #endif | ||
| 254 | |||
| 255 | mb(); | ||
| 256 | while (1) | ||
| 257 | cvmx_write_csr(CVMX_CIU_SOFT_RST, 1); | ||
| 258 | } | ||
| 259 | |||
| 260 | |||
| 261 | /** | ||
| 262 | * Permanently stop a core. | ||
| 263 | * | ||
| 264 | * @arg: Ignored. | ||
| 265 | */ | ||
| 266 | static void octeon_kill_core(void *arg) | ||
| 267 | { | ||
| 268 | mb(); | ||
| 269 | if (octeon_is_simulation()) { | ||
| 270 | /* The simulator needs the watchdog to stop for dead cores */ | ||
| 271 | cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); | ||
| 272 | /* A break instruction causes the simulator stop a core */ | ||
| 273 | asm volatile ("sync\nbreak"); | ||
| 274 | } | ||
| 275 | } | ||
| 276 | |||
| 277 | |||
| 278 | /** | ||
| 279 | * Halt the system | ||
| 280 | */ | ||
| 281 | static void octeon_halt(void) | ||
| 282 | { | ||
| 283 | smp_call_function(octeon_kill_core, NULL, 0); | ||
| 284 | |||
| 285 | switch (octeon_bootinfo->board_type) { | ||
| 286 | case CVMX_BOARD_TYPE_NAO38: | ||
| 287 | /* Driving a 1 to GPIO 12 shuts off this board */ | ||
| 288 | cvmx_write_csr(CVMX_GPIO_BIT_CFGX(12), 1); | ||
| 289 | cvmx_write_csr(CVMX_GPIO_TX_SET, 0x1000); | ||
| 290 | break; | ||
| 291 | default: | ||
| 292 | octeon_write_lcd("PowerOff"); | ||
| 293 | break; | ||
| 294 | } | ||
| 295 | |||
| 296 | octeon_kill_core(NULL); | ||
| 297 | } | ||
| 298 | |||
| 299 | #if 0 | ||
| 300 | /** | ||
| 301 | * Platform time init specifics. | ||
| 302 | * Returns | ||
| 303 | */ | ||
| 304 | void __init plat_time_init(void) | ||
| 305 | { | ||
| 306 | /* Nothing special here, but we are required to have one */ | ||
| 307 | } | ||
| 308 | |||
| 309 | #endif | ||
| 310 | |||
| 311 | /** | ||
| 312 | * Handle all the error condition interrupts that might occur. | ||
| 313 | * | ||
| 314 | */ | ||
| 315 | #ifdef CONFIG_CAVIUM_DECODE_RSL | ||
| 316 | static irqreturn_t octeon_rlm_interrupt(int cpl, void *dev_id) | ||
| 317 | { | ||
| 318 | cvmx_interrupt_rsl_decode(); | ||
| 319 | return IRQ_HANDLED; | ||
| 320 | } | ||
| 321 | #endif | ||
| 322 | |||
| 323 | /** | ||
| 324 | * Return a string representing the system type | ||
| 325 | * | ||
| 326 | * Returns | ||
| 327 | */ | ||
| 328 | const char *octeon_board_type_string(void) | ||
| 329 | { | ||
| 330 | static char name[80]; | ||
| 331 | sprintf(name, "%s (%s)", | ||
| 332 | cvmx_board_type_to_string(octeon_bootinfo->board_type), | ||
| 333 | octeon_model_get_string(read_c0_prid())); | ||
| 334 | return name; | ||
| 335 | } | ||
| 336 | |||
| 337 | const char *get_system_type(void) | ||
| 338 | __attribute__ ((alias("octeon_board_type_string"))); | ||
| 339 | |||
| 340 | void octeon_user_io_init(void) | ||
| 341 | { | ||
| 342 | union octeon_cvmemctl cvmmemctl; | ||
| 343 | union cvmx_iob_fau_timeout fau_timeout; | ||
| 344 | union cvmx_pow_nw_tim nm_tim; | ||
| 345 | uint64_t cvmctl; | ||
| 346 | |||
| 347 | /* Get the current settings for CP0_CVMMEMCTL_REG */ | ||
| 348 | cvmmemctl.u64 = read_c0_cvmmemctl(); | ||
| 349 | /* R/W If set, marked write-buffer entries time out the same | ||
| 350 | * as as other entries; if clear, marked write-buffer entries | ||
| 351 | * use the maximum timeout. */ | ||
| 352 | cvmmemctl.s.dismarkwblongto = 1; | ||
| 353 | /* R/W If set, a merged store does not clear the write-buffer | ||
| 354 | * entry timeout state. */ | ||
| 355 | cvmmemctl.s.dismrgclrwbto = 0; | ||
| 356 | /* R/W Two bits that are the MSBs of the resultant CVMSEG LM | ||
| 357 | * word location for an IOBDMA. The other 8 bits come from the | ||
| 358 | * SCRADDR field of the IOBDMA. */ | ||
| 359 | cvmmemctl.s.iobdmascrmsb = 0; | ||
| 360 | /* R/W If set, SYNCWS and SYNCS only order marked stores; if | ||
| 361 | * clear, SYNCWS and SYNCS only order unmarked | ||
| 362 | * stores. SYNCWSMARKED has no effect when DISSYNCWS is | ||
| 363 | * set. */ | ||
| 364 | cvmmemctl.s.syncwsmarked = 0; | ||
| 365 | /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as SYNC. */ | ||
| 366 | cvmmemctl.s.dissyncws = 0; | ||
| 367 | /* R/W If set, no stall happens on write buffer full. */ | ||
| 368 | if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) | ||
| 369 | cvmmemctl.s.diswbfst = 1; | ||
| 370 | else | ||
| 371 | cvmmemctl.s.diswbfst = 0; | ||
| 372 | /* R/W If set (and SX set), supervisor-level loads/stores can | ||
| 373 | * use XKPHYS addresses with <48>==0 */ | ||
| 374 | cvmmemctl.s.xkmemenas = 0; | ||
| 375 | |||
| 376 | /* R/W If set (and UX set), user-level loads/stores can use | ||
| 377 | * XKPHYS addresses with VA<48>==0 */ | ||
| 378 | cvmmemctl.s.xkmemenau = 0; | ||
| 379 | |||
| 380 | /* R/W If set (and SX set), supervisor-level loads/stores can | ||
| 381 | * use XKPHYS addresses with VA<48>==1 */ | ||
| 382 | cvmmemctl.s.xkioenas = 0; | ||
| 383 | |||
| 384 | /* R/W If set (and UX set), user-level loads/stores can use | ||
| 385 | * XKPHYS addresses with VA<48>==1 */ | ||
| 386 | cvmmemctl.s.xkioenau = 0; | ||
| 387 | |||
| 388 | /* R/W If set, all stores act as SYNCW (NOMERGE must be set | ||
| 389 | * when this is set) RW, reset to 0. */ | ||
| 390 | cvmmemctl.s.allsyncw = 0; | ||
| 391 | |||
| 392 | /* R/W If set, no stores merge, and all stores reach the | ||
| 393 | * coherent bus in order. */ | ||
| 394 | cvmmemctl.s.nomerge = 0; | ||
| 395 | /* R/W Selects the bit in the counter used for DID time-outs 0 | ||
| 396 | * = 231, 1 = 230, 2 = 229, 3 = 214. Actual time-out is | ||
| 397 | * between 1x and 2x this interval. For example, with | ||
| 398 | * DIDTTO=3, expiration interval is between 16K and 32K. */ | ||
| 399 | cvmmemctl.s.didtto = 0; | ||
| 400 | /* R/W If set, the (mem) CSR clock never turns off. */ | ||
| 401 | cvmmemctl.s.csrckalwys = 0; | ||
| 402 | /* R/W If set, mclk never turns off. */ | ||
| 403 | cvmmemctl.s.mclkalwys = 0; | ||
| 404 | /* R/W Selects the bit in the counter used for write buffer | ||
| 405 | * flush time-outs (WBFLT+11) is the bit position in an | ||
| 406 | * internal counter used to determine expiration. The write | ||
| 407 | * buffer expires between 1x and 2x this interval. For | ||
| 408 | * example, with WBFLT = 0, a write buffer expires between 2K | ||
| 409 | * and 4K cycles after the write buffer entry is allocated. */ | ||
| 410 | cvmmemctl.s.wbfltime = 0; | ||
| 411 | /* R/W If set, do not put Istream in the L2 cache. */ | ||
| 412 | cvmmemctl.s.istrnol2 = 0; | ||
| 413 | /* R/W The write buffer threshold. */ | ||
| 414 | cvmmemctl.s.wbthresh = 10; | ||
| 415 | /* R/W If set, CVMSEG is available for loads/stores in | ||
| 416 | * kernel/debug mode. */ | ||
| 417 | #if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 | ||
| 418 | cvmmemctl.s.cvmsegenak = 1; | ||
| 419 | #else | ||
| 420 | cvmmemctl.s.cvmsegenak = 0; | ||
| 421 | #endif | ||
| 422 | /* R/W If set, CVMSEG is available for loads/stores in | ||
| 423 | * supervisor mode. */ | ||
| 424 | cvmmemctl.s.cvmsegenas = 0; | ||
| 425 | /* R/W If set, CVMSEG is available for loads/stores in user | ||
| 426 | * mode. */ | ||
| 427 | cvmmemctl.s.cvmsegenau = 0; | ||
| 428 | /* R/W Size of local memory in cache blocks, 54 (6912 bytes) | ||
| 429 | * is max legal value. */ | ||
| 430 | cvmmemctl.s.lmemsz = CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE; | ||
| 431 | |||
| 432 | |||
| 433 | if (smp_processor_id() == 0) | ||
| 434 | pr_notice("CVMSEG size: %d cache lines (%d bytes)\n", | ||
| 435 | CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE, | ||
| 436 | CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128); | ||
| 437 | |||
| 438 | write_c0_cvmmemctl(cvmmemctl.u64); | ||
| 439 | |||
| 440 | /* Move the performance counter interrupts to IRQ 6 */ | ||
| 441 | cvmctl = read_c0_cvmctl(); | ||
| 442 | cvmctl &= ~(7 << 7); | ||
| 443 | cvmctl |= 6 << 7; | ||
| 444 | write_c0_cvmctl(cvmctl); | ||
| 445 | |||
| 446 | /* Set a default for the hardware timeouts */ | ||
| 447 | fau_timeout.u64 = 0; | ||
| 448 | fau_timeout.s.tout_val = 0xfff; | ||
| 449 | /* Disable tagwait FAU timeout */ | ||
| 450 | fau_timeout.s.tout_enb = 0; | ||
| 451 | cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_timeout.u64); | ||
| 452 | |||
| 453 | nm_tim.u64 = 0; | ||
| 454 | /* 4096 cycles */ | ||
| 455 | nm_tim.s.nw_tim = 3; | ||
| 456 | cvmx_write_csr(CVMX_POW_NW_TIM, nm_tim.u64); | ||
| 457 | |||
| 458 | write_octeon_c0_icacheerr(0); | ||
| 459 | write_c0_derraddr1(0); | ||
| 460 | } | ||
| 461 | |||
| 462 | /** | ||
| 463 | * Early entry point for arch setup | ||
| 464 | */ | ||
| 465 | void __init prom_init(void) | ||
| 466 | { | ||
| 467 | struct cvmx_sysinfo *sysinfo; | ||
| 468 | const int coreid = cvmx_get_core_num(); | ||
| 469 | int i; | ||
| 470 | int argc; | ||
| 471 | struct uart_port octeon_port; | ||
| 472 | #ifdef CONFIG_CAVIUM_RESERVE32 | ||
| 473 | int64_t addr = -1; | ||
| 474 | #endif | ||
| 475 | /* | ||
| 476 | * The bootloader passes a pointer to the boot descriptor in | ||
| 477 | * $a3, this is available as fw_arg3. | ||
| 478 | */ | ||
| 479 | octeon_boot_desc_ptr = (struct octeon_boot_descriptor *)fw_arg3; | ||
| 480 | octeon_bootinfo = | ||
| 481 | cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr); | ||
| 482 | cvmx_bootmem_init(cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr)); | ||
| 483 | |||
| 484 | /* | ||
| 485 | * Only enable the LED controller if we're running on a CN38XX, CN58XX, | ||
| 486 | * or CN56XX. The CN30XX and CN31XX don't have an LED controller. | ||
| 487 | */ | ||
| 488 | if (!octeon_is_simulation() && | ||
| 489 | octeon_has_feature(OCTEON_FEATURE_LED_CONTROLLER)) { | ||
| 490 | cvmx_write_csr(CVMX_LED_EN, 0); | ||
| 491 | cvmx_write_csr(CVMX_LED_PRT, 0); | ||
| 492 | cvmx_write_csr(CVMX_LED_DBG, 0); | ||
| 493 | cvmx_write_csr(CVMX_LED_PRT_FMT, 0); | ||
| 494 | cvmx_write_csr(CVMX_LED_UDD_CNTX(0), 32); | ||
| 495 | cvmx_write_csr(CVMX_LED_UDD_CNTX(1), 32); | ||
| 496 | cvmx_write_csr(CVMX_LED_UDD_DATX(0), 0); | ||
| 497 | cvmx_write_csr(CVMX_LED_UDD_DATX(1), 0); | ||
| 498 | cvmx_write_csr(CVMX_LED_EN, 1); | ||
| 499 | } | ||
| 500 | #ifdef CONFIG_CAVIUM_RESERVE32 | ||
| 501 | /* | ||
| 502 | * We need to temporarily allocate all memory in the reserve32 | ||
| 503 | * region. This makes sure the kernel doesn't allocate this | ||
| 504 | * memory when it is getting memory from the | ||
| 505 | * bootloader. Later, after the memory allocations are | ||
| 506 | * complete, the reserve32 will be freed. | ||
| 507 | */ | ||
| 508 | #ifdef CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB | ||
| 509 | if (CONFIG_CAVIUM_RESERVE32 & 0x1ff) | ||
| 510 | pr_err("CAVIUM_RESERVE32 isn't a multiple of 512MB. " | ||
| 511 | "This is required if CAVIUM_RESERVE32_USE_WIRED_TLB " | ||
| 512 | "is set\n"); | ||
| 513 | else | ||
| 514 | addr = cvmx_bootmem_phy_named_block_alloc(CONFIG_CAVIUM_RESERVE32 << 20, | ||
| 515 | 0, 0, 512 << 20, | ||
| 516 | "CAVIUM_RESERVE32", 0); | ||
| 517 | #else | ||
| 518 | /* | ||
| 519 | * Allocate memory for RESERVED32 aligned on 2MB boundary. This | ||
| 520 | * is in case we later use hugetlb entries with it. | ||
| 521 | */ | ||
| 522 | addr = cvmx_bootmem_phy_named_block_alloc(CONFIG_CAVIUM_RESERVE32 << 20, | ||
| 523 | 0, 0, 2 << 20, | ||
| 524 | "CAVIUM_RESERVE32", 0); | ||
| 525 | #endif | ||
| 526 | if (addr < 0) | ||
| 527 | pr_err("Failed to allocate CAVIUM_RESERVE32 memory area\n"); | ||
| 528 | else | ||
| 529 | octeon_reserve32_memory = addr; | ||
| 530 | #endif | ||
| 531 | |||
| 532 | #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2 | ||
| 533 | if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) { | ||
| 534 | pr_info("Skipping L2 locking due to reduced L2 cache size\n"); | ||
| 535 | } else { | ||
| 536 | uint32_t ebase = read_c0_ebase() & 0x3ffff000; | ||
| 537 | #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB | ||
| 538 | /* TLB refill */ | ||
| 539 | cvmx_l2c_lock_mem_region(ebase, 0x100); | ||
| 540 | #endif | ||
| 541 | #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION | ||
| 542 | /* General exception */ | ||
| 543 | cvmx_l2c_lock_mem_region(ebase + 0x180, 0x80); | ||
| 544 | #endif | ||
| 545 | #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT | ||
| 546 | /* Interrupt handler */ | ||
| 547 | cvmx_l2c_lock_mem_region(ebase + 0x200, 0x80); | ||
| 548 | #endif | ||
| 549 | #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT | ||
| 550 | cvmx_l2c_lock_mem_region(__pa_symbol(handle_int), 0x100); | ||
| 551 | cvmx_l2c_lock_mem_region(__pa_symbol(plat_irq_dispatch), 0x80); | ||
| 552 | #endif | ||
| 553 | #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY | ||
| 554 | cvmx_l2c_lock_mem_region(__pa_symbol(memcpy), 0x480); | ||
| 555 | #endif | ||
| 556 | } | ||
| 557 | #endif | ||
| 558 | |||
| 559 | sysinfo = cvmx_sysinfo_get(); | ||
| 560 | memset(sysinfo, 0, sizeof(*sysinfo)); | ||
| 561 | sysinfo->system_dram_size = octeon_bootinfo->dram_size << 20; | ||
| 562 | sysinfo->phy_mem_desc_ptr = | ||
| 563 | cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr); | ||
| 564 | sysinfo->core_mask = octeon_bootinfo->core_mask; | ||
| 565 | sysinfo->exception_base_addr = octeon_bootinfo->exception_base_addr; | ||
| 566 | sysinfo->cpu_clock_hz = octeon_bootinfo->eclock_hz; | ||
| 567 | sysinfo->dram_data_rate_hz = octeon_bootinfo->dclock_hz * 2; | ||
| 568 | sysinfo->board_type = octeon_bootinfo->board_type; | ||
| 569 | sysinfo->board_rev_major = octeon_bootinfo->board_rev_major; | ||
| 570 | sysinfo->board_rev_minor = octeon_bootinfo->board_rev_minor; | ||
| 571 | memcpy(sysinfo->mac_addr_base, octeon_bootinfo->mac_addr_base, | ||
| 572 | sizeof(sysinfo->mac_addr_base)); | ||
| 573 | sysinfo->mac_addr_count = octeon_bootinfo->mac_addr_count; | ||
| 574 | memcpy(sysinfo->board_serial_number, | ||
| 575 | octeon_bootinfo->board_serial_number, | ||
| 576 | sizeof(sysinfo->board_serial_number)); | ||
| 577 | sysinfo->compact_flash_common_base_addr = | ||
| 578 | octeon_bootinfo->compact_flash_common_base_addr; | ||
| 579 | sysinfo->compact_flash_attribute_base_addr = | ||
| 580 | octeon_bootinfo->compact_flash_attribute_base_addr; | ||
| 581 | sysinfo->led_display_base_addr = octeon_bootinfo->led_display_base_addr; | ||
| 582 | sysinfo->dfa_ref_clock_hz = octeon_bootinfo->dfa_ref_clock_hz; | ||
| 583 | sysinfo->bootloader_config_flags = octeon_bootinfo->config_flags; | ||
| 584 | |||
| 585 | |||
| 586 | octeon_check_cpu_bist(); | ||
| 587 | |||
| 588 | octeon_uart = octeon_get_boot_uart(); | ||
| 589 | |||
| 590 | /* | ||
| 591 | * Disable All CIU Interrupts. The ones we need will be | ||
| 592 | * enabled later. Read the SUM register so we know the write | ||
| 593 | * completed. | ||
| 594 | */ | ||
| 595 | cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), 0); | ||
| 596 | cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0); | ||
| 597 | cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0); | ||
| 598 | cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0); | ||
| 599 | cvmx_read_csr(CVMX_CIU_INTX_SUM0((coreid * 2))); | ||
| 600 | |||
| 601 | #ifdef CONFIG_SMP | ||
| 602 | octeon_write_lcd("LinuxSMP"); | ||
| 603 | #else | ||
| 604 | octeon_write_lcd("Linux"); | ||
| 605 | #endif | ||
| 606 | |||
| 607 | #ifdef CONFIG_CAVIUM_GDB | ||
| 608 | /* | ||
| 609 | * When debugging the linux kernel, force the cores to enter | ||
| 610 | * the debug exception handler to break in. | ||
| 611 | */ | ||
| 612 | if (octeon_get_boot_debug_flag()) { | ||
| 613 | cvmx_write_csr(CVMX_CIU_DINT, 1 << cvmx_get_core_num()); | ||
| 614 | cvmx_read_csr(CVMX_CIU_DINT); | ||
| 615 | } | ||
| 616 | #endif | ||
| 617 | |||
| 618 | /* | ||
| 619 | * BIST should always be enabled when doing a soft reset. L2 | ||
| 620 | * Cache locking for instance is not cleared unless BIST is | ||
| 621 | * enabled. Unfortunately due to a chip errata G-200 for | ||
| 622 | * Cn38XX and CN31XX, BIST msut be disabled on these parts. | ||
| 623 | */ | ||
| 624 | if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) || | ||
| 625 | OCTEON_IS_MODEL(OCTEON_CN31XX)) | ||
| 626 | cvmx_write_csr(CVMX_CIU_SOFT_BIST, 0); | ||
| 627 | else | ||
| 628 | cvmx_write_csr(CVMX_CIU_SOFT_BIST, 1); | ||
| 629 | |||
| 630 | /* Default to 64MB in the simulator to speed things up */ | ||
| 631 | if (octeon_is_simulation()) | ||
| 632 | MAX_MEMORY = 64ull << 20; | ||
| 633 | |||
| 634 | arcs_cmdline[0] = 0; | ||
| 635 | argc = octeon_boot_desc_ptr->argc; | ||
| 636 | for (i = 0; i < argc; i++) { | ||
| 637 | const char *arg = | ||
| 638 | cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]); | ||
| 639 | if ((strncmp(arg, "MEM=", 4) == 0) || | ||
| 640 | (strncmp(arg, "mem=", 4) == 0)) { | ||
| 641 | sscanf(arg + 4, "%llu", &MAX_MEMORY); | ||
| 642 | MAX_MEMORY <<= 20; | ||
| 643 | if (MAX_MEMORY == 0) | ||
| 644 | MAX_MEMORY = 32ull << 30; | ||
| 645 | } else if (strcmp(arg, "ecc_verbose") == 0) { | ||
| 646 | #ifdef CONFIG_CAVIUM_REPORT_SINGLE_BIT_ECC | ||
| 647 | __cvmx_interrupt_ecc_report_single_bit_errors = 1; | ||
| 648 | pr_notice("Reporting of single bit ECC errors is " | ||
| 649 | "turned on\n"); | ||
| 650 | #endif | ||
| 651 | } else if (strlen(arcs_cmdline) + strlen(arg) + 1 < | ||
| 652 | sizeof(arcs_cmdline) - 1) { | ||
| 653 | strcat(arcs_cmdline, " "); | ||
| 654 | strcat(arcs_cmdline, arg); | ||
| 655 | } | ||
| 656 | } | ||
| 657 | |||
| 658 | if (strstr(arcs_cmdline, "console=") == NULL) { | ||
| 659 | #ifdef CONFIG_GDB_CONSOLE | ||
| 660 | strcat(arcs_cmdline, " console=gdb"); | ||
| 661 | #else | ||
| 662 | #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL | ||
| 663 | strcat(arcs_cmdline, " console=ttyS0,115200"); | ||
| 664 | #else | ||
| 665 | if (octeon_uart == 1) | ||
| 666 | strcat(arcs_cmdline, " console=ttyS1,115200"); | ||
| 667 | else | ||
| 668 | strcat(arcs_cmdline, " console=ttyS0,115200"); | ||
| 669 | #endif | ||
| 670 | #endif | ||
| 671 | } | ||
| 672 | |||
| 673 | if (octeon_is_simulation()) { | ||
| 674 | /* | ||
| 675 | * The simulator uses a mtdram device pre filled with | ||
| 676 | * the filesystem. Also specify the calibration delay | ||
| 677 | * to avoid calculating it every time. | ||
| 678 | */ | ||
| 679 | strcat(arcs_cmdline, " rw root=1f00" | ||
| 680 | " lpj=60176 slram=root,0x40000000,+1073741824"); | ||
| 681 | } | ||
| 682 | |||
| 683 | mips_hpt_frequency = octeon_get_clock_rate(); | ||
| 684 | |||
| 685 | octeon_init_cvmcount(); | ||
| 686 | |||
| 687 | _machine_restart = octeon_restart; | ||
| 688 | _machine_halt = octeon_halt; | ||
| 689 | |||
| 690 | memset(&octeon_port, 0, sizeof(octeon_port)); | ||
| 691 | /* | ||
| 692 | * For early_serial_setup we don't set the port type or | ||
| 693 | * UPF_FIXED_TYPE. | ||
| 694 | */ | ||
| 695 | octeon_port.flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ; | ||
| 696 | octeon_port.iotype = UPIO_MEM; | ||
| 697 | /* I/O addresses are every 8 bytes */ | ||
| 698 | octeon_port.regshift = 3; | ||
| 699 | /* Clock rate of the chip */ | ||
| 700 | octeon_port.uartclk = mips_hpt_frequency; | ||
| 701 | octeon_port.fifosize = 64; | ||
| 702 | octeon_port.mapbase = 0x0001180000000800ull + (1024 * octeon_uart); | ||
| 703 | octeon_port.membase = cvmx_phys_to_ptr(octeon_port.mapbase); | ||
| 704 | octeon_port.serial_in = octeon_serial_in; | ||
| 705 | octeon_port.serial_out = octeon_serial_out; | ||
| 706 | #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL | ||
| 707 | octeon_port.line = 0; | ||
| 708 | #else | ||
| 709 | octeon_port.line = octeon_uart; | ||
| 710 | #endif | ||
| 711 | octeon_port.irq = 42 + octeon_uart; | ||
| 712 | early_serial_setup(&octeon_port); | ||
| 713 | |||
| 714 | octeon_user_io_init(); | ||
| 715 | register_smp_ops(&octeon_smp_ops); | ||
| 716 | } | ||
| 717 | |||
| 718 | void __init plat_mem_setup(void) | ||
| 719 | { | ||
| 720 | uint64_t mem_alloc_size; | ||
| 721 | uint64_t total; | ||
| 722 | int64_t memory; | ||
| 723 | |||
| 724 | total = 0; | ||
| 725 | |||
| 726 | /* First add the init memory we will be returning. */ | ||
| 727 | memory = __pa_symbol(&__init_begin) & PAGE_MASK; | ||
| 728 | mem_alloc_size = (__pa_symbol(&__init_end) & PAGE_MASK) - memory; | ||
| 729 | if (mem_alloc_size > 0) { | ||
| 730 | add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM); | ||
| 731 | total += mem_alloc_size; | ||
| 732 | } | ||
| 733 | |||
| 734 | /* | ||
| 735 | * The Mips memory init uses the first memory location for | ||
| 736 | * some memory vectors. When SPARSEMEM is in use, it doesn't | ||
| 737 | * verify that the size is big enough for the final | ||
| 738 | * vectors. Making the smallest chuck 4MB seems to be enough | ||
| 739 | * to consistantly work. | ||
| 740 | */ | ||
| 741 | mem_alloc_size = 4 << 20; | ||
| 742 | if (mem_alloc_size > MAX_MEMORY) | ||
| 743 | mem_alloc_size = MAX_MEMORY; | ||
| 744 | |||
| 745 | /* | ||
| 746 | * When allocating memory, we want incrementing addresses from | ||
| 747 | * bootmem_alloc so the code in add_memory_region can merge | ||
| 748 | * regions next to each other. | ||
| 749 | */ | ||
| 750 | cvmx_bootmem_lock(); | ||
| 751 | while ((boot_mem_map.nr_map < BOOT_MEM_MAP_MAX) | ||
| 752 | && (total < MAX_MEMORY)) { | ||
| 753 | #if defined(CONFIG_64BIT) || defined(CONFIG_64BIT_PHYS_ADDR) | ||
| 754 | memory = cvmx_bootmem_phy_alloc(mem_alloc_size, | ||
| 755 | __pa_symbol(&__init_end), -1, | ||
| 756 | 0x100000, | ||
| 757 | CVMX_BOOTMEM_FLAG_NO_LOCKING); | ||
| 758 | #elif defined(CONFIG_HIGHMEM) | ||
| 759 | memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 0, 1ull << 31, | ||
| 760 | 0x100000, | ||
| 761 | CVMX_BOOTMEM_FLAG_NO_LOCKING); | ||
| 762 | #else | ||
| 763 | memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 0, 512 << 20, | ||
| 764 | 0x100000, | ||
| 765 | CVMX_BOOTMEM_FLAG_NO_LOCKING); | ||
| 766 | #endif | ||
| 767 | if (memory >= 0) { | ||
| 768 | /* | ||
| 769 | * This function automatically merges address | ||
| 770 | * regions next to each other if they are | ||
| 771 | * received in incrementing order. | ||
| 772 | */ | ||
| 773 | add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM); | ||
| 774 | total += mem_alloc_size; | ||
| 775 | } else { | ||
| 776 | break; | ||
| 777 | } | ||
| 778 | } | ||
| 779 | cvmx_bootmem_unlock(); | ||
| 780 | |||
| 781 | #ifdef CONFIG_CAVIUM_RESERVE32 | ||
| 782 | /* | ||
| 783 | * Now that we've allocated the kernel memory it is safe to | ||
| 784 | * free the reserved region. We free it here so that builtin | ||
| 785 | * drivers can use the memory. | ||
| 786 | */ | ||
| 787 | if (octeon_reserve32_memory) | ||
| 788 | cvmx_bootmem_free_named("CAVIUM_RESERVE32"); | ||
| 789 | #endif /* CONFIG_CAVIUM_RESERVE32 */ | ||
| 790 | |||
| 791 | if (total == 0) | ||
| 792 | panic("Unable to allocate memory from " | ||
| 793 | "cvmx_bootmem_phy_alloc\n"); | ||
| 794 | } | ||
| 795 | |||
| 796 | |||
| 797 | int prom_putchar(char c) | ||
| 798 | { | ||
| 799 | uint64_t lsrval; | ||
| 800 | |||
| 801 | /* Spin until there is room */ | ||
| 802 | do { | ||
| 803 | lsrval = cvmx_read_csr(CVMX_MIO_UARTX_LSR(octeon_uart)); | ||
| 804 | } while ((lsrval & 0x20) == 0); | ||
| 805 | |||
| 806 | /* Write the byte */ | ||
| 807 | cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c); | ||
| 808 | return 1; | ||
| 809 | } | ||
| 810 | |||
| 811 | void prom_free_prom_memory(void) | ||
| 812 | { | ||
| 813 | #ifdef CONFIG_CAVIUM_DECODE_RSL | ||
| 814 | cvmx_interrupt_rsl_enable(); | ||
| 815 | |||
| 816 | /* Add an interrupt handler for general failures. */ | ||
| 817 | if (request_irq(OCTEON_IRQ_RML, octeon_rlm_interrupt, IRQF_SHARED, | ||
| 818 | "RML/RSL", octeon_rlm_interrupt)) { | ||
| 819 | panic("Unable to request_irq(OCTEON_IRQ_RML)\n"); | ||
| 820 | } | ||
| 821 | #endif | ||
| 822 | |||
| 823 | /* This call is here so that it is performed after any TLB | ||
| 824 | initializations. It needs to be after these in case the | ||
| 825 | CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB option is set */ | ||
| 826 | octeon_hal_setup_reserved32(); | ||
| 827 | } | ||
| 828 | |||
| 829 | static struct octeon_cf_data octeon_cf_data; | ||
| 830 | |||
| 831 | static int __init octeon_cf_device_init(void) | ||
| 832 | { | ||
| 833 | union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg; | ||
| 834 | unsigned long base_ptr, region_base, region_size; | ||
| 835 | struct platform_device *pd; | ||
| 836 | struct resource cf_resources[3]; | ||
| 837 | unsigned int num_resources; | ||
| 838 | int i; | ||
| 839 | int ret = 0; | ||
| 840 | |||
| 841 | /* Setup octeon-cf platform device if present. */ | ||
| 842 | base_ptr = 0; | ||
| 843 | if (octeon_bootinfo->major_version == 1 | ||
| 844 | && octeon_bootinfo->minor_version >= 1) { | ||
| 845 | if (octeon_bootinfo->compact_flash_common_base_addr) | ||
| 846 | base_ptr = | ||
| 847 | octeon_bootinfo->compact_flash_common_base_addr; | ||
| 848 | } else { | ||
| 849 | base_ptr = 0x1d000800; | ||
| 850 | } | ||
| 851 | |||
| 852 | if (!base_ptr) | ||
| 853 | return ret; | ||
| 854 | |||
| 855 | /* Find CS0 region. */ | ||
| 856 | for (i = 0; i < 8; i++) { | ||
| 857 | mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i)); | ||
| 858 | region_base = mio_boot_reg_cfg.s.base << 16; | ||
| 859 | region_size = (mio_boot_reg_cfg.s.size + 1) << 16; | ||
| 860 | if (mio_boot_reg_cfg.s.en && base_ptr >= region_base | ||
| 861 | && base_ptr < region_base + region_size) | ||
| 862 | break; | ||
| 863 | } | ||
| 864 | if (i >= 7) { | ||
| 865 | /* i and i + 1 are CS0 and CS1, both must be less than 8. */ | ||
| 866 | goto out; | ||
| 867 | } | ||
| 868 | octeon_cf_data.base_region = i; | ||
| 869 | octeon_cf_data.is16bit = mio_boot_reg_cfg.s.width; | ||
| 870 | octeon_cf_data.base_region_bias = base_ptr - region_base; | ||
| 871 | memset(cf_resources, 0, sizeof(cf_resources)); | ||
| 872 | num_resources = 0; | ||
| 873 | cf_resources[num_resources].flags = IORESOURCE_MEM; | ||
| 874 | cf_resources[num_resources].start = region_base; | ||
| 875 | cf_resources[num_resources].end = region_base + region_size - 1; | ||
| 876 | num_resources++; | ||
| 877 | |||
| 878 | |||
| 879 | if (!(base_ptr & 0xfffful)) { | ||
| 880 | /* | ||
| 881 | * Boot loader signals availability of DMA (true_ide | ||
| 882 | * mode) by setting low order bits of base_ptr to | ||
| 883 | * zero. | ||
| 884 | */ | ||
| 885 | |||
| 886 | /* Asume that CS1 immediately follows. */ | ||
| 887 | mio_boot_reg_cfg.u64 = | ||
| 888 | cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i + 1)); | ||
| 889 | region_base = mio_boot_reg_cfg.s.base << 16; | ||
| 890 | region_size = (mio_boot_reg_cfg.s.size + 1) << 16; | ||
| 891 | if (!mio_boot_reg_cfg.s.en) | ||
| 892 | goto out; | ||
| 893 | |||
| 894 | cf_resources[num_resources].flags = IORESOURCE_MEM; | ||
| 895 | cf_resources[num_resources].start = region_base; | ||
| 896 | cf_resources[num_resources].end = region_base + region_size - 1; | ||
| 897 | num_resources++; | ||
| 898 | |||
| 899 | octeon_cf_data.dma_engine = 0; | ||
| 900 | cf_resources[num_resources].flags = IORESOURCE_IRQ; | ||
| 901 | cf_resources[num_resources].start = OCTEON_IRQ_BOOTDMA; | ||
| 902 | cf_resources[num_resources].end = OCTEON_IRQ_BOOTDMA; | ||
| 903 | num_resources++; | ||
| 904 | } else { | ||
| 905 | octeon_cf_data.dma_engine = -1; | ||
| 906 | } | ||
| 907 | |||
| 908 | pd = platform_device_alloc("pata_octeon_cf", -1); | ||
| 909 | if (!pd) { | ||
| 910 | ret = -ENOMEM; | ||
| 911 | goto out; | ||
| 912 | } | ||
| 913 | pd->dev.platform_data = &octeon_cf_data; | ||
| 914 | |||
| 915 | ret = platform_device_add_resources(pd, cf_resources, num_resources); | ||
| 916 | if (ret) | ||
| 917 | goto fail; | ||
| 918 | |||
| 919 | ret = platform_device_add(pd); | ||
| 920 | if (ret) | ||
| 921 | goto fail; | ||
| 922 | |||
| 923 | return ret; | ||
| 924 | fail: | ||
| 925 | platform_device_put(pd); | ||
| 926 | out: | ||
| 927 | return ret; | ||
| 928 | } | ||
| 929 | device_initcall(octeon_cf_device_init); | ||
diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c new file mode 100644 index 000000000000..24e0ad63980a --- /dev/null +++ b/arch/mips/cavium-octeon/smp.c | |||
| @@ -0,0 +1,211 @@ | |||
| 1 | /* | ||
| 2 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 3 | * License. See the file "COPYING" in the main directory of this archive | ||
| 4 | * for more details. | ||
| 5 | * | ||
| 6 | * Copyright (C) 2004-2008 Cavium Networks | ||
| 7 | */ | ||
| 8 | #include <linux/init.h> | ||
| 9 | #include <linux/delay.h> | ||
| 10 | #include <linux/smp.h> | ||
| 11 | #include <linux/interrupt.h> | ||
| 12 | #include <linux/kernel_stat.h> | ||
| 13 | #include <linux/sched.h> | ||
| 14 | #include <linux/module.h> | ||
| 15 | |||
| 16 | #include <asm/mmu_context.h> | ||
| 17 | #include <asm/system.h> | ||
| 18 | #include <asm/time.h> | ||
| 19 | |||
| 20 | #include <asm/octeon/octeon.h> | ||
| 21 | |||
| 22 | volatile unsigned long octeon_processor_boot = 0xff; | ||
| 23 | volatile unsigned long octeon_processor_sp; | ||
| 24 | volatile unsigned long octeon_processor_gp; | ||
| 25 | |||
| 26 | static irqreturn_t mailbox_interrupt(int irq, void *dev_id) | ||
| 27 | { | ||
| 28 | const int coreid = cvmx_get_core_num(); | ||
| 29 | uint64_t action; | ||
| 30 | |||
| 31 | /* Load the mailbox register to figure out what we're supposed to do */ | ||
| 32 | action = cvmx_read_csr(CVMX_CIU_MBOX_CLRX(coreid)); | ||
| 33 | |||
| 34 | /* Clear the mailbox to clear the interrupt */ | ||
| 35 | cvmx_write_csr(CVMX_CIU_MBOX_CLRX(coreid), action); | ||
| 36 | |||
| 37 | if (action & SMP_CALL_FUNCTION) | ||
| 38 | smp_call_function_interrupt(); | ||
| 39 | |||
| 40 | /* Check if we've been told to flush the icache */ | ||
| 41 | if (action & SMP_ICACHE_FLUSH) | ||
| 42 | asm volatile ("synci 0($0)\n"); | ||
| 43 | return IRQ_HANDLED; | ||
| 44 | } | ||
| 45 | |||
| 46 | /** | ||
| 47 | * Cause the function described by call_data to be executed on the passed | ||
| 48 | * cpu. When the function has finished, increment the finished field of | ||
| 49 | * call_data. | ||
| 50 | */ | ||
| 51 | void octeon_send_ipi_single(int cpu, unsigned int action) | ||
| 52 | { | ||
| 53 | int coreid = cpu_logical_map(cpu); | ||
| 54 | /* | ||
| 55 | pr_info("SMP: Mailbox send cpu=%d, coreid=%d, action=%u\n", cpu, | ||
| 56 | coreid, action); | ||
| 57 | */ | ||
| 58 | cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action); | ||
| 59 | } | ||
| 60 | |||
| 61 | static inline void octeon_send_ipi_mask(cpumask_t mask, unsigned int action) | ||
| 62 | { | ||
| 63 | unsigned int i; | ||
| 64 | |||
| 65 | for_each_cpu_mask(i, mask) | ||
| 66 | octeon_send_ipi_single(i, action); | ||
| 67 | } | ||
| 68 | |||
| 69 | /** | ||
| 70 | * Detect available CPUs, populate phys_cpu_present_map | ||
| 71 | */ | ||
| 72 | static void octeon_smp_setup(void) | ||
| 73 | { | ||
| 74 | const int coreid = cvmx_get_core_num(); | ||
| 75 | int cpus; | ||
| 76 | int id; | ||
| 77 | |||
| 78 | int core_mask = octeon_get_boot_coremask(); | ||
| 79 | |||
| 80 | cpus_clear(cpu_possible_map); | ||
| 81 | __cpu_number_map[coreid] = 0; | ||
| 82 | __cpu_logical_map[0] = coreid; | ||
| 83 | cpu_set(0, cpu_possible_map); | ||
| 84 | |||
| 85 | cpus = 1; | ||
| 86 | for (id = 0; id < 16; id++) { | ||
| 87 | if ((id != coreid) && (core_mask & (1 << id))) { | ||
| 88 | cpu_set(cpus, cpu_possible_map); | ||
| 89 | __cpu_number_map[id] = cpus; | ||
| 90 | __cpu_logical_map[cpus] = id; | ||
| 91 | cpus++; | ||
| 92 | } | ||
| 93 | } | ||
| 94 | } | ||
| 95 | |||
| 96 | /** | ||
| 97 | * Firmware CPU startup hook | ||
| 98 | * | ||
| 99 | */ | ||
| 100 | static void octeon_boot_secondary(int cpu, struct task_struct *idle) | ||
| 101 | { | ||
| 102 | int count; | ||
| 103 | |||
| 104 | pr_info("SMP: Booting CPU%02d (CoreId %2d)...\n", cpu, | ||
| 105 | cpu_logical_map(cpu)); | ||
| 106 | |||
| 107 | octeon_processor_sp = __KSTK_TOS(idle); | ||
| 108 | octeon_processor_gp = (unsigned long)(task_thread_info(idle)); | ||
| 109 | octeon_processor_boot = cpu_logical_map(cpu); | ||
| 110 | mb(); | ||
| 111 | |||
| 112 | count = 10000; | ||
| 113 | while (octeon_processor_sp && count) { | ||
| 114 | /* Waiting for processor to get the SP and GP */ | ||
| 115 | udelay(1); | ||
| 116 | count--; | ||
| 117 | } | ||
| 118 | if (count == 0) | ||
| 119 | pr_err("Secondary boot timeout\n"); | ||
| 120 | } | ||
| 121 | |||
| 122 | /** | ||
| 123 | * After we've done initial boot, this function is called to allow the | ||
| 124 | * board code to clean up state, if needed | ||
| 125 | */ | ||
| 126 | static void octeon_init_secondary(void) | ||
| 127 | { | ||
| 128 | const int coreid = cvmx_get_core_num(); | ||
| 129 | union cvmx_ciu_intx_sum0 interrupt_enable; | ||
| 130 | |||
| 131 | octeon_check_cpu_bist(); | ||
| 132 | octeon_init_cvmcount(); | ||
| 133 | /* | ||
| 134 | pr_info("SMP: CPU%d (CoreId %lu) started\n", cpu, coreid); | ||
| 135 | */ | ||
| 136 | /* Enable Mailbox interrupts to this core. These are the only | ||
| 137 | interrupts allowed on line 3 */ | ||
| 138 | cvmx_write_csr(CVMX_CIU_MBOX_CLRX(coreid), 0xffffffff); | ||
| 139 | interrupt_enable.u64 = 0; | ||
| 140 | interrupt_enable.s.mbox = 0x3; | ||
| 141 | cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), interrupt_enable.u64); | ||
| 142 | cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0); | ||
| 143 | cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0); | ||
| 144 | cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0); | ||
| 145 | /* Enable core interrupt processing for 2,3 and 7 */ | ||
| 146 | set_c0_status(0x8c01); | ||
| 147 | } | ||
| 148 | |||
| 149 | /** | ||
| 150 | * Callout to firmware before smp_init | ||
| 151 | * | ||
| 152 | */ | ||
| 153 | void octeon_prepare_cpus(unsigned int max_cpus) | ||
| 154 | { | ||
| 155 | cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffffffff); | ||
| 156 | if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, IRQF_SHARED, | ||
| 157 | "mailbox0", mailbox_interrupt)) { | ||
| 158 | panic("Cannot request_irq(OCTEON_IRQ_MBOX0)\n"); | ||
| 159 | } | ||
| 160 | if (request_irq(OCTEON_IRQ_MBOX1, mailbox_interrupt, IRQF_SHARED, | ||
| 161 | "mailbox1", mailbox_interrupt)) { | ||
| 162 | panic("Cannot request_irq(OCTEON_IRQ_MBOX1)\n"); | ||
| 163 | } | ||
| 164 | } | ||
| 165 | |||
| 166 | /** | ||
| 167 | * Last chance for the board code to finish SMP initialization before | ||
| 168 | * the CPU is "online". | ||
| 169 | */ | ||
| 170 | static void octeon_smp_finish(void) | ||
| 171 | { | ||
| 172 | #ifdef CONFIG_CAVIUM_GDB | ||
| 173 | unsigned long tmp; | ||
| 174 | /* Pulse MCD0 signal on Ctrl-C to stop all the cores. Also set the MCD0 | ||
| 175 | to be not masked by this core so we know the signal is received by | ||
| 176 | someone */ | ||
| 177 | asm volatile ("dmfc0 %0, $22\n" | ||
| 178 | "ori %0, %0, 0x9100\n" "dmtc0 %0, $22\n" : "=r" (tmp)); | ||
| 179 | #endif | ||
| 180 | |||
| 181 | octeon_user_io_init(); | ||
| 182 | |||
| 183 | /* to generate the first CPU timer interrupt */ | ||
| 184 | write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ); | ||
| 185 | } | ||
| 186 | |||
| 187 | /** | ||
| 188 | * Hook for after all CPUs are online | ||
| 189 | */ | ||
| 190 | static void octeon_cpus_done(void) | ||
| 191 | { | ||
| 192 | #ifdef CONFIG_CAVIUM_GDB | ||
| 193 | unsigned long tmp; | ||
| 194 | /* Pulse MCD0 signal on Ctrl-C to stop all the cores. Also set the MCD0 | ||
| 195 | to be not masked by this core so we know the signal is received by | ||
| 196 | someone */ | ||
| 197 | asm volatile ("dmfc0 %0, $22\n" | ||
| 198 | "ori %0, %0, 0x9100\n" "dmtc0 %0, $22\n" : "=r" (tmp)); | ||
| 199 | #endif | ||
| 200 | } | ||
| 201 | |||
| 202 | struct plat_smp_ops octeon_smp_ops = { | ||
| 203 | .send_ipi_single = octeon_send_ipi_single, | ||
| 204 | .send_ipi_mask = octeon_send_ipi_mask, | ||
| 205 | .init_secondary = octeon_init_secondary, | ||
| 206 | .smp_finish = octeon_smp_finish, | ||
| 207 | .cpus_done = octeon_cpus_done, | ||
| 208 | .boot_secondary = octeon_boot_secondary, | ||
| 209 | .smp_setup = octeon_smp_setup, | ||
| 210 | .prepare_cpus = octeon_prepare_cpus, | ||
| 211 | }; | ||
diff --git a/arch/mips/configs/cavium-octeon_defconfig b/arch/mips/configs/cavium-octeon_defconfig new file mode 100644 index 000000000000..7afaa28a3768 --- /dev/null +++ b/arch/mips/configs/cavium-octeon_defconfig | |||
| @@ -0,0 +1,943 @@ | |||
| 1 | # | ||
| 2 | # Automatically generated make config: don't edit | ||
| 3 | # Linux kernel version: 2.6.28-rc6 | ||
| 4 | # Wed Dec 3 11:00:58 2008 | ||
| 5 | # | ||
| 6 | CONFIG_MIPS=y | ||
| 7 | |||
| 8 | # | ||
| 9 | # Machine selection | ||
| 10 | # | ||
| 11 | # CONFIG_MACH_ALCHEMY is not set | ||
| 12 | # CONFIG_BASLER_EXCITE is not set | ||
| 13 | # CONFIG_BCM47XX is not set | ||
| 14 | # CONFIG_MIPS_COBALT is not set | ||
| 15 | # CONFIG_MACH_DECSTATION is not set | ||
| 16 | # CONFIG_MACH_JAZZ is not set | ||
| 17 | # CONFIG_LASAT is not set | ||
| 18 | # CONFIG_LEMOTE_FULONG is not set | ||
| 19 | # CONFIG_MIPS_MALTA is not set | ||
| 20 | # CONFIG_MIPS_SIM is not set | ||
| 21 | # CONFIG_MACH_EMMA is not set | ||
| 22 | # CONFIG_MACH_VR41XX is not set | ||
| 23 | # CONFIG_NXP_STB220 is not set | ||
| 24 | # CONFIG_NXP_STB225 is not set | ||
| 25 | # CONFIG_PNX8550_JBS is not set | ||
| 26 | # CONFIG_PNX8550_STB810 is not set | ||
| 27 | # CONFIG_PMC_MSP is not set | ||
| 28 | # CONFIG_PMC_YOSEMITE is not set | ||
| 29 | # CONFIG_SGI_IP22 is not set | ||
| 30 | # CONFIG_SGI_IP27 is not set | ||
| 31 | # CONFIG_SGI_IP28 is not set | ||
| 32 | # CONFIG_SGI_IP32 is not set | ||
| 33 | # CONFIG_SIBYTE_CRHINE is not set | ||
| 34 | # CONFIG_SIBYTE_CARMEL is not set | ||
| 35 | # CONFIG_SIBYTE_CRHONE is not set | ||
| 36 | # CONFIG_SIBYTE_RHONE is not set | ||
| 37 | # CONFIG_SIBYTE_SWARM is not set | ||
| 38 | # CONFIG_SIBYTE_LITTLESUR is not set | ||
| 39 | # CONFIG_SIBYTE_SENTOSA is not set | ||
| 40 | # CONFIG_SIBYTE_BIGSUR is not set | ||
| 41 | # CONFIG_SNI_RM is not set | ||
| 42 | # CONFIG_MACH_TX39XX is not set | ||
| 43 | # CONFIG_MACH_TX49XX is not set | ||
| 44 | # CONFIG_MIKROTIK_RB532 is not set | ||
| 45 | # CONFIG_WR_PPMC is not set | ||
| 46 | # CONFIG_CAVIUM_OCTEON_SIMULATOR is not set | ||
| 47 | CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD=y | ||
| 48 | CONFIG_CAVIUM_OCTEON_SPECIFIC_OPTIONS=y | ||
| 49 | # CONFIG_CAVIUM_OCTEON_2ND_KERNEL is not set | ||
| 50 | CONFIG_CAVIUM_OCTEON_HW_FIX_UNALIGNED=y | ||
| 51 | CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE=2 | ||
| 52 | CONFIG_CAVIUM_OCTEON_LOCK_L2=y | ||
| 53 | CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB=y | ||
| 54 | CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION=y | ||
| 55 | CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT=y | ||
| 56 | CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT=y | ||
| 57 | CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY=y | ||
| 58 | CONFIG_ARCH_SPARSEMEM_ENABLE=y | ||
| 59 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
| 60 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | ||
| 61 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
| 62 | CONFIG_ARCH_SUPPORTS_OPROFILE=y | ||
| 63 | CONFIG_GENERIC_FIND_NEXT_BIT=y | ||
| 64 | CONFIG_GENERIC_HWEIGHT=y | ||
| 65 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
| 66 | CONFIG_GENERIC_CLOCKEVENTS=y | ||
| 67 | CONFIG_GENERIC_TIME=y | ||
| 68 | CONFIG_GENERIC_CMOS_UPDATE=y | ||
| 69 | CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y | ||
| 70 | # CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set | ||
| 71 | CONFIG_CEVT_R4K=y | ||
| 72 | CONFIG_CSRC_R4K=y | ||
| 73 | CONFIG_DMA_COHERENT=y | ||
| 74 | # CONFIG_EARLY_PRINTK is not set | ||
| 75 | CONFIG_SYS_HAS_EARLY_PRINTK=y | ||
| 76 | # CONFIG_HOTPLUG_CPU is not set | ||
| 77 | # CONFIG_NO_IOPORT is not set | ||
| 78 | CONFIG_CPU_BIG_ENDIAN=y | ||
| 79 | # CONFIG_CPU_LITTLE_ENDIAN is not set | ||
| 80 | CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y | ||
| 81 | CONFIG_IRQ_CPU=y | ||
| 82 | CONFIG_IRQ_CPU_OCTEON=y | ||
| 83 | CONFIG_SWAP_IO_SPACE=y | ||
| 84 | CONFIG_MIPS_L1_CACHE_SHIFT=7 | ||
| 85 | |||
| 86 | # | ||
| 87 | # CPU selection | ||
| 88 | # | ||
| 89 | # CONFIG_CPU_LOONGSON2 is not set | ||
| 90 | # CONFIG_CPU_MIPS32_R1 is not set | ||
| 91 | # CONFIG_CPU_MIPS32_R2 is not set | ||
| 92 | # CONFIG_CPU_MIPS64_R1 is not set | ||
| 93 | # CONFIG_CPU_MIPS64_R2 is not set | ||
| 94 | # CONFIG_CPU_R3000 is not set | ||
| 95 | # CONFIG_CPU_TX39XX is not set | ||
| 96 | # CONFIG_CPU_VR41XX is not set | ||
| 97 | # CONFIG_CPU_R4300 is not set | ||
| 98 | # CONFIG_CPU_R4X00 is not set | ||
| 99 | # CONFIG_CPU_TX49XX is not set | ||
| 100 | # CONFIG_CPU_R5000 is not set | ||
| 101 | # CONFIG_CPU_R5432 is not set | ||
| 102 | # CONFIG_CPU_R5500 is not set | ||
| 103 | # CONFIG_CPU_R6000 is not set | ||
| 104 | # CONFIG_CPU_NEVADA is not set | ||
| 105 | # CONFIG_CPU_R8000 is not set | ||
| 106 | # CONFIG_CPU_R10000 is not set | ||
| 107 | # CONFIG_CPU_RM7000 is not set | ||
| 108 | # CONFIG_CPU_RM9000 is not set | ||
| 109 | # CONFIG_CPU_SB1 is not set | ||
| 110 | CONFIG_CPU_CAVIUM_OCTEON=y | ||
| 111 | CONFIG_WEAK_ORDERING=y | ||
| 112 | CONFIG_WEAK_REORDERING_BEYOND_LLSC=y | ||
| 113 | CONFIG_CPU_MIPSR2=y | ||
| 114 | CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y | ||
| 115 | CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y | ||
| 116 | |||
| 117 | # | ||
| 118 | # Kernel type | ||
| 119 | # | ||
| 120 | # CONFIG_32BIT is not set | ||
| 121 | CONFIG_64BIT=y | ||
| 122 | CONFIG_PAGE_SIZE_4KB=y | ||
| 123 | # CONFIG_PAGE_SIZE_8KB is not set | ||
| 124 | # CONFIG_PAGE_SIZE_16KB is not set | ||
| 125 | # CONFIG_PAGE_SIZE_64KB is not set | ||
| 126 | CONFIG_CPU_HAS_PREFETCH=y | ||
| 127 | CONFIG_MIPS_MT_DISABLED=y | ||
| 128 | # CONFIG_MIPS_MT_SMP is not set | ||
| 129 | # CONFIG_MIPS_MT_SMTC is not set | ||
| 130 | CONFIG_64BIT_PHYS_ADDR=y | ||
| 131 | CONFIG_CPU_HAS_SYNC=y | ||
| 132 | CONFIG_GENERIC_HARDIRQS=y | ||
| 133 | CONFIG_GENERIC_IRQ_PROBE=y | ||
| 134 | CONFIG_IRQ_PER_CPU=y | ||
| 135 | CONFIG_CPU_SUPPORTS_HIGHMEM=y | ||
| 136 | CONFIG_SYS_SUPPORTS_HIGHMEM=y | ||
| 137 | CONFIG_ARCH_FLATMEM_ENABLE=y | ||
| 138 | CONFIG_ARCH_POPULATES_NODE_MAP=y | ||
| 139 | CONFIG_SELECT_MEMORY_MODEL=y | ||
| 140 | # CONFIG_FLATMEM_MANUAL is not set | ||
| 141 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
| 142 | CONFIG_SPARSEMEM_MANUAL=y | ||
| 143 | CONFIG_SPARSEMEM=y | ||
| 144 | CONFIG_HAVE_MEMORY_PRESENT=y | ||
| 145 | CONFIG_SPARSEMEM_STATIC=y | ||
| 146 | CONFIG_PAGEFLAGS_EXTENDED=y | ||
| 147 | CONFIG_SPLIT_PTLOCK_CPUS=4 | ||
| 148 | CONFIG_RESOURCES_64BIT=y | ||
| 149 | CONFIG_PHYS_ADDR_T_64BIT=y | ||
| 150 | CONFIG_ZONE_DMA_FLAG=0 | ||
| 151 | CONFIG_VIRT_TO_BUS=y | ||
| 152 | CONFIG_UNEVICTABLE_LRU=y | ||
| 153 | CONFIG_SMP=y | ||
| 154 | CONFIG_SYS_SUPPORTS_SMP=y | ||
| 155 | CONFIG_NR_CPUS_DEFAULT_16=y | ||
| 156 | CONFIG_NR_CPUS=16 | ||
| 157 | # CONFIG_NO_HZ is not set | ||
| 158 | # CONFIG_HIGH_RES_TIMERS is not set | ||
| 159 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | ||
| 160 | # CONFIG_HZ_48 is not set | ||
| 161 | # CONFIG_HZ_100 is not set | ||
| 162 | # CONFIG_HZ_128 is not set | ||
| 163 | CONFIG_HZ_250=y | ||
| 164 | # CONFIG_HZ_256 is not set | ||
| 165 | # CONFIG_HZ_1000 is not set | ||
| 166 | # CONFIG_HZ_1024 is not set | ||
| 167 | CONFIG_SYS_SUPPORTS_ARBIT_HZ=y | ||
| 168 | CONFIG_HZ=250 | ||
| 169 | # CONFIG_PREEMPT_NONE is not set | ||
| 170 | # CONFIG_PREEMPT_VOLUNTARY is not set | ||
| 171 | CONFIG_PREEMPT=y | ||
| 172 | # CONFIG_PREEMPT_RCU is not set | ||
| 173 | # CONFIG_KEXEC is not set | ||
| 174 | CONFIG_SECCOMP=y | ||
| 175 | CONFIG_LOCKDEP_SUPPORT=y | ||
| 176 | CONFIG_STACKTRACE_SUPPORT=y | ||
| 177 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
| 178 | |||
| 179 | # | ||
| 180 | # General setup | ||
| 181 | # | ||
| 182 | CONFIG_EXPERIMENTAL=y | ||
| 183 | CONFIG_LOCK_KERNEL=y | ||
| 184 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
| 185 | CONFIG_LOCALVERSION="" | ||
| 186 | CONFIG_LOCALVERSION_AUTO=y | ||
| 187 | CONFIG_SWAP=y | ||
| 188 | CONFIG_SYSVIPC=y | ||
| 189 | CONFIG_SYSVIPC_SYSCTL=y | ||
| 190 | CONFIG_POSIX_MQUEUE=y | ||
| 191 | CONFIG_BSD_PROCESS_ACCT=y | ||
| 192 | CONFIG_BSD_PROCESS_ACCT_V3=y | ||
| 193 | # CONFIG_TASKSTATS is not set | ||
| 194 | # CONFIG_AUDIT is not set | ||
| 195 | CONFIG_IKCONFIG=y | ||
| 196 | CONFIG_IKCONFIG_PROC=y | ||
| 197 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 198 | # CONFIG_CGROUPS is not set | ||
| 199 | CONFIG_GROUP_SCHED=y | ||
| 200 | CONFIG_FAIR_GROUP_SCHED=y | ||
| 201 | # CONFIG_RT_GROUP_SCHED is not set | ||
| 202 | CONFIG_USER_SCHED=y | ||
| 203 | # CONFIG_CGROUP_SCHED is not set | ||
| 204 | CONFIG_SYSFS_DEPRECATED=y | ||
| 205 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
| 206 | CONFIG_RELAY=y | ||
| 207 | # CONFIG_NAMESPACES is not set | ||
| 208 | CONFIG_BLK_DEV_INITRD=y | ||
| 209 | CONFIG_INITRAMFS_SOURCE="" | ||
| 210 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | ||
| 211 | CONFIG_SYSCTL=y | ||
| 212 | CONFIG_EMBEDDED=y | ||
| 213 | CONFIG_SYSCTL_SYSCALL=y | ||
| 214 | CONFIG_KALLSYMS=y | ||
| 215 | # CONFIG_KALLSYMS_ALL is not set | ||
| 216 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | ||
| 217 | CONFIG_HOTPLUG=y | ||
| 218 | CONFIG_PRINTK=y | ||
| 219 | CONFIG_BUG=y | ||
| 220 | CONFIG_ELF_CORE=y | ||
| 221 | # CONFIG_PCSPKR_PLATFORM is not set | ||
| 222 | CONFIG_COMPAT_BRK=y | ||
| 223 | CONFIG_BASE_FULL=y | ||
| 224 | CONFIG_FUTEX=y | ||
| 225 | CONFIG_ANON_INODES=y | ||
| 226 | CONFIG_EPOLL=y | ||
| 227 | CONFIG_SIGNALFD=y | ||
| 228 | CONFIG_TIMERFD=y | ||
| 229 | CONFIG_EVENTFD=y | ||
| 230 | CONFIG_SHMEM=y | ||
| 231 | CONFIG_AIO=y | ||
| 232 | CONFIG_VM_EVENT_COUNTERS=y | ||
| 233 | CONFIG_SLAB=y | ||
| 234 | # CONFIG_SLUB is not set | ||
| 235 | # CONFIG_SLOB is not set | ||
| 236 | # CONFIG_PROFILING is not set | ||
| 237 | # CONFIG_MARKERS is not set | ||
| 238 | CONFIG_HAVE_OPROFILE=y | ||
| 239 | CONFIG_USE_GENERIC_SMP_HELPERS=y | ||
| 240 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set | ||
| 241 | CONFIG_SLABINFO=y | ||
| 242 | CONFIG_RT_MUTEXES=y | ||
| 243 | # CONFIG_TINY_SHMEM is not set | ||
| 244 | CONFIG_BASE_SMALL=0 | ||
| 245 | CONFIG_MODULES=y | ||
| 246 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 247 | CONFIG_MODULE_UNLOAD=y | ||
| 248 | # CONFIG_MODULE_FORCE_UNLOAD is not set | ||
| 249 | # CONFIG_MODVERSIONS is not set | ||
| 250 | # CONFIG_MODULE_SRCVERSION_ALL is not set | ||
| 251 | CONFIG_KMOD=y | ||
| 252 | CONFIG_STOP_MACHINE=y | ||
| 253 | CONFIG_BLOCK=y | ||
| 254 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 255 | # CONFIG_BLK_DEV_BSG is not set | ||
| 256 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 257 | CONFIG_BLOCK_COMPAT=y | ||
| 258 | |||
| 259 | # | ||
| 260 | # IO Schedulers | ||
| 261 | # | ||
| 262 | CONFIG_IOSCHED_NOOP=y | ||
| 263 | CONFIG_IOSCHED_AS=y | ||
| 264 | CONFIG_IOSCHED_DEADLINE=y | ||
| 265 | CONFIG_IOSCHED_CFQ=y | ||
| 266 | # CONFIG_DEFAULT_AS is not set | ||
| 267 | # CONFIG_DEFAULT_DEADLINE is not set | ||
| 268 | CONFIG_DEFAULT_CFQ=y | ||
| 269 | # CONFIG_DEFAULT_NOOP is not set | ||
| 270 | CONFIG_DEFAULT_IOSCHED="cfq" | ||
| 271 | CONFIG_CLASSIC_RCU=y | ||
| 272 | # CONFIG_PROBE_INITRD_HEADER is not set | ||
| 273 | # CONFIG_FREEZER is not set | ||
| 274 | |||
| 275 | # | ||
| 276 | # Bus options (PCI, PCMCIA, EISA, ISA, TC) | ||
| 277 | # | ||
| 278 | # CONFIG_ARCH_SUPPORTS_MSI is not set | ||
| 279 | CONFIG_MMU=y | ||
| 280 | # CONFIG_PCCARD is not set | ||
| 281 | |||
| 282 | # | ||
| 283 | # Executable file formats | ||
| 284 | # | ||
| 285 | CONFIG_BINFMT_ELF=y | ||
| 286 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
| 287 | # CONFIG_HAVE_AOUT is not set | ||
| 288 | # CONFIG_BINFMT_MISC is not set | ||
| 289 | CONFIG_MIPS32_COMPAT=y | ||
| 290 | CONFIG_COMPAT=y | ||
| 291 | CONFIG_SYSVIPC_COMPAT=y | ||
| 292 | CONFIG_MIPS32_O32=y | ||
| 293 | CONFIG_MIPS32_N32=y | ||
| 294 | CONFIG_BINFMT_ELF32=y | ||
| 295 | |||
| 296 | # | ||
| 297 | # Power management options | ||
| 298 | # | ||
| 299 | # CONFIG_PM is not set | ||
| 300 | CONFIG_NET=y | ||
| 301 | |||
| 302 | # | ||
| 303 | # Networking options | ||
| 304 | # | ||
| 305 | CONFIG_PACKET=y | ||
| 306 | CONFIG_PACKET_MMAP=y | ||
| 307 | CONFIG_UNIX=y | ||
| 308 | CONFIG_XFRM=y | ||
| 309 | # CONFIG_XFRM_USER is not set | ||
| 310 | # CONFIG_XFRM_SUB_POLICY is not set | ||
| 311 | # CONFIG_XFRM_MIGRATE is not set | ||
| 312 | # CONFIG_XFRM_STATISTICS is not set | ||
| 313 | # CONFIG_NET_KEY is not set | ||
| 314 | CONFIG_INET=y | ||
| 315 | CONFIG_IP_MULTICAST=y | ||
| 316 | CONFIG_IP_ADVANCED_ROUTER=y | ||
| 317 | CONFIG_ASK_IP_FIB_HASH=y | ||
| 318 | # CONFIG_IP_FIB_TRIE is not set | ||
| 319 | CONFIG_IP_FIB_HASH=y | ||
| 320 | CONFIG_IP_MULTIPLE_TABLES=y | ||
| 321 | CONFIG_IP_ROUTE_MULTIPATH=y | ||
| 322 | CONFIG_IP_ROUTE_VERBOSE=y | ||
| 323 | CONFIG_IP_PNP=y | ||
| 324 | CONFIG_IP_PNP_DHCP=y | ||
| 325 | CONFIG_IP_PNP_BOOTP=y | ||
| 326 | CONFIG_IP_PNP_RARP=y | ||
| 327 | # CONFIG_NET_IPIP is not set | ||
| 328 | # CONFIG_NET_IPGRE is not set | ||
| 329 | CONFIG_IP_MROUTE=y | ||
| 330 | CONFIG_IP_PIMSM_V1=y | ||
| 331 | CONFIG_IP_PIMSM_V2=y | ||
| 332 | # CONFIG_ARPD is not set | ||
| 333 | CONFIG_SYN_COOKIES=y | ||
| 334 | # CONFIG_INET_AH is not set | ||
| 335 | # CONFIG_INET_ESP is not set | ||
| 336 | # CONFIG_INET_IPCOMP is not set | ||
| 337 | # CONFIG_INET_XFRM_TUNNEL is not set | ||
| 338 | # CONFIG_INET_TUNNEL is not set | ||
| 339 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | ||
| 340 | CONFIG_INET_XFRM_MODE_TUNNEL=y | ||
| 341 | CONFIG_INET_XFRM_MODE_BEET=y | ||
| 342 | # CONFIG_INET_LRO is not set | ||
| 343 | CONFIG_INET_DIAG=y | ||
| 344 | CONFIG_INET_TCP_DIAG=y | ||
| 345 | # CONFIG_TCP_CONG_ADVANCED is not set | ||
| 346 | CONFIG_TCP_CONG_CUBIC=y | ||
| 347 | CONFIG_DEFAULT_TCP_CONG="cubic" | ||
| 348 | # CONFIG_TCP_MD5SIG is not set | ||
| 349 | # CONFIG_IPV6 is not set | ||
| 350 | # CONFIG_NETLABEL is not set | ||
| 351 | # CONFIG_NETWORK_SECMARK is not set | ||
| 352 | # CONFIG_NETFILTER is not set | ||
| 353 | # CONFIG_IP_DCCP is not set | ||
| 354 | # CONFIG_IP_SCTP is not set | ||
| 355 | # CONFIG_TIPC is not set | ||
| 356 | # CONFIG_ATM is not set | ||
| 357 | # CONFIG_BRIDGE is not set | ||
| 358 | # CONFIG_NET_DSA is not set | ||
| 359 | # CONFIG_VLAN_8021Q is not set | ||
| 360 | # CONFIG_DECNET is not set | ||
| 361 | # CONFIG_LLC2 is not set | ||
| 362 | # CONFIG_IPX is not set | ||
| 363 | # CONFIG_ATALK is not set | ||
| 364 | # CONFIG_X25 is not set | ||
| 365 | # CONFIG_LAPB is not set | ||
| 366 | # CONFIG_ECONET is not set | ||
| 367 | # CONFIG_WAN_ROUTER is not set | ||
| 368 | # CONFIG_NET_SCHED is not set | ||
| 369 | |||
| 370 | # | ||
| 371 | # Network testing | ||
| 372 | # | ||
| 373 | # CONFIG_NET_PKTGEN is not set | ||
| 374 | # CONFIG_HAMRADIO is not set | ||
| 375 | # CONFIG_CAN is not set | ||
| 376 | # CONFIG_IRDA is not set | ||
| 377 | # CONFIG_BT is not set | ||
| 378 | # CONFIG_AF_RXRPC is not set | ||
| 379 | # CONFIG_PHONET is not set | ||
| 380 | CONFIG_FIB_RULES=y | ||
| 381 | # CONFIG_WIRELESS is not set | ||
| 382 | # CONFIG_RFKILL is not set | ||
| 383 | # CONFIG_NET_9P is not set | ||
| 384 | |||
| 385 | # | ||
| 386 | # Device Drivers | ||
| 387 | # | ||
| 388 | |||
| 389 | # | ||
| 390 | # Generic Driver Options | ||
| 391 | # | ||
| 392 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 393 | CONFIG_STANDALONE=y | ||
| 394 | CONFIG_PREVENT_FIRMWARE_BUILD=y | ||
| 395 | # CONFIG_FW_LOADER is not set | ||
| 396 | # CONFIG_DEBUG_DRIVER is not set | ||
| 397 | # CONFIG_DEBUG_DEVRES is not set | ||
| 398 | # CONFIG_SYS_HYPERVISOR is not set | ||
| 399 | # CONFIG_CONNECTOR is not set | ||
| 400 | CONFIG_MTD=y | ||
| 401 | # CONFIG_MTD_DEBUG is not set | ||
| 402 | # CONFIG_MTD_CONCAT is not set | ||
| 403 | CONFIG_MTD_PARTITIONS=y | ||
| 404 | # CONFIG_MTD_REDBOOT_PARTS is not set | ||
| 405 | # CONFIG_MTD_CMDLINE_PARTS is not set | ||
| 406 | # CONFIG_MTD_AR7_PARTS is not set | ||
| 407 | |||
| 408 | # | ||
| 409 | # User Modules And Translation Layers | ||
| 410 | # | ||
| 411 | CONFIG_MTD_CHAR=y | ||
| 412 | CONFIG_MTD_BLKDEVS=y | ||
| 413 | CONFIG_MTD_BLOCK=y | ||
| 414 | # CONFIG_FTL is not set | ||
| 415 | # CONFIG_NFTL is not set | ||
| 416 | # CONFIG_INFTL is not set | ||
| 417 | # CONFIG_RFD_FTL is not set | ||
| 418 | # CONFIG_SSFDC is not set | ||
| 419 | # CONFIG_MTD_OOPS is not set | ||
| 420 | |||
| 421 | # | ||
| 422 | # RAM/ROM/Flash chip drivers | ||
| 423 | # | ||
| 424 | CONFIG_MTD_CFI=y | ||
| 425 | # CONFIG_MTD_JEDECPROBE is not set | ||
| 426 | CONFIG_MTD_GEN_PROBE=y | ||
| 427 | # CONFIG_MTD_CFI_ADV_OPTIONS is not set | ||
| 428 | CONFIG_MTD_MAP_BANK_WIDTH_1=y | ||
| 429 | CONFIG_MTD_MAP_BANK_WIDTH_2=y | ||
| 430 | CONFIG_MTD_MAP_BANK_WIDTH_4=y | ||
| 431 | # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set | ||
| 432 | # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set | ||
| 433 | # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set | ||
| 434 | CONFIG_MTD_CFI_I1=y | ||
| 435 | CONFIG_MTD_CFI_I2=y | ||
| 436 | # CONFIG_MTD_CFI_I4 is not set | ||
| 437 | # CONFIG_MTD_CFI_I8 is not set | ||
| 438 | # CONFIG_MTD_CFI_INTELEXT is not set | ||
| 439 | CONFIG_MTD_CFI_AMDSTD=y | ||
| 440 | # CONFIG_MTD_CFI_STAA is not set | ||
| 441 | CONFIG_MTD_CFI_UTIL=y | ||
| 442 | # CONFIG_MTD_RAM is not set | ||
| 443 | # CONFIG_MTD_ROM is not set | ||
| 444 | # CONFIG_MTD_ABSENT is not set | ||
| 445 | |||
| 446 | # | ||
| 447 | # Mapping drivers for chip access | ||
| 448 | # | ||
| 449 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | ||
| 450 | CONFIG_MTD_PHYSMAP=y | ||
| 451 | CONFIG_MTD_PHYSMAP_START=0x8000000 | ||
| 452 | CONFIG_MTD_PHYSMAP_LEN=0x0 | ||
| 453 | CONFIG_MTD_PHYSMAP_BANKWIDTH=2 | ||
| 454 | # CONFIG_MTD_PLATRAM is not set | ||
| 455 | |||
| 456 | # | ||
| 457 | # Self-contained MTD device drivers | ||
| 458 | # | ||
| 459 | # CONFIG_MTD_SLRAM is not set | ||
| 460 | # CONFIG_MTD_PHRAM is not set | ||
| 461 | # CONFIG_MTD_MTDRAM is not set | ||
| 462 | # CONFIG_MTD_BLOCK2MTD is not set | ||
| 463 | |||
| 464 | # | ||
| 465 | # Disk-On-Chip Device Drivers | ||
| 466 | # | ||
| 467 | # CONFIG_MTD_DOC2000 is not set | ||
| 468 | # CONFIG_MTD_DOC2001 is not set | ||
| 469 | # CONFIG_MTD_DOC2001PLUS is not set | ||
| 470 | # CONFIG_MTD_NAND is not set | ||
| 471 | # CONFIG_MTD_ONENAND is not set | ||
| 472 | |||
| 473 | # | ||
| 474 | # UBI - Unsorted block images | ||
| 475 | # | ||
| 476 | # CONFIG_MTD_UBI is not set | ||
| 477 | # CONFIG_PARPORT is not set | ||
| 478 | CONFIG_BLK_DEV=y | ||
| 479 | # CONFIG_BLK_DEV_COW_COMMON is not set | ||
| 480 | CONFIG_BLK_DEV_LOOP=y | ||
| 481 | # CONFIG_BLK_DEV_CRYPTOLOOP is not set | ||
| 482 | # CONFIG_BLK_DEV_NBD is not set | ||
| 483 | # CONFIG_BLK_DEV_RAM is not set | ||
| 484 | # CONFIG_CDROM_PKTCDVD is not set | ||
| 485 | # CONFIG_ATA_OVER_ETH is not set | ||
| 486 | # CONFIG_BLK_DEV_HD is not set | ||
| 487 | # CONFIG_MISC_DEVICES is not set | ||
| 488 | CONFIG_HAVE_IDE=y | ||
| 489 | # CONFIG_IDE is not set | ||
| 490 | |||
| 491 | # | ||
| 492 | # SCSI device support | ||
| 493 | # | ||
| 494 | # CONFIG_RAID_ATTRS is not set | ||
| 495 | # CONFIG_SCSI is not set | ||
| 496 | # CONFIG_SCSI_DMA is not set | ||
| 497 | # CONFIG_SCSI_NETLINK is not set | ||
| 498 | # CONFIG_ATA is not set | ||
| 499 | # CONFIG_MD is not set | ||
| 500 | CONFIG_NETDEVICES=y | ||
| 501 | # CONFIG_DUMMY is not set | ||
| 502 | # CONFIG_BONDING is not set | ||
| 503 | # CONFIG_MACVLAN is not set | ||
| 504 | # CONFIG_EQUALIZER is not set | ||
| 505 | # CONFIG_TUN is not set | ||
| 506 | # CONFIG_VETH is not set | ||
| 507 | # CONFIG_PHYLIB is not set | ||
| 508 | CONFIG_NET_ETHERNET=y | ||
| 509 | CONFIG_MII=y | ||
| 510 | # CONFIG_AX88796 is not set | ||
| 511 | # CONFIG_SMC91X is not set | ||
| 512 | # CONFIG_DM9000 is not set | ||
| 513 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | ||
| 514 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | ||
| 515 | # CONFIG_IBM_NEW_EMAC_TAH is not set | ||
| 516 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | ||
| 517 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set | ||
| 518 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 519 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 520 | # CONFIG_B44 is not set | ||
| 521 | CONFIG_NETDEV_1000=y | ||
| 522 | # CONFIG_NETDEV_10000 is not set | ||
| 523 | |||
| 524 | # | ||
| 525 | # Wireless LAN | ||
| 526 | # | ||
| 527 | # CONFIG_WLAN_PRE80211 is not set | ||
| 528 | # CONFIG_WLAN_80211 is not set | ||
| 529 | # CONFIG_IWLWIFI_LEDS is not set | ||
| 530 | # CONFIG_WAN is not set | ||
| 531 | # CONFIG_PPP is not set | ||
| 532 | # CONFIG_SLIP is not set | ||
| 533 | # CONFIG_NETCONSOLE is not set | ||
| 534 | # CONFIG_NETPOLL is not set | ||
| 535 | # CONFIG_NET_POLL_CONTROLLER is not set | ||
| 536 | # CONFIG_ISDN is not set | ||
| 537 | # CONFIG_PHONE is not set | ||
| 538 | |||
| 539 | # | ||
| 540 | # Input device support | ||
| 541 | # | ||
| 542 | # CONFIG_INPUT is not set | ||
| 543 | |||
| 544 | # | ||
| 545 | # Hardware I/O ports | ||
| 546 | # | ||
| 547 | # CONFIG_SERIO is not set | ||
| 548 | # CONFIG_GAMEPORT is not set | ||
| 549 | |||
| 550 | # | ||
| 551 | # Character devices | ||
| 552 | # | ||
| 553 | # CONFIG_VT is not set | ||
| 554 | CONFIG_DEVKMEM=y | ||
| 555 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
| 556 | |||
| 557 | # | ||
| 558 | # Serial drivers | ||
| 559 | # | ||
| 560 | CONFIG_SERIAL_8250=y | ||
| 561 | CONFIG_SERIAL_8250_CONSOLE=y | ||
| 562 | CONFIG_SERIAL_8250_NR_UARTS=2 | ||
| 563 | CONFIG_SERIAL_8250_RUNTIME_UARTS=2 | ||
| 564 | # CONFIG_SERIAL_8250_EXTENDED is not set | ||
| 565 | |||
| 566 | # | ||
| 567 | # Non-8250 serial port support | ||
| 568 | # | ||
| 569 | CONFIG_SERIAL_CORE=y | ||
| 570 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
| 571 | CONFIG_UNIX98_PTYS=y | ||
| 572 | CONFIG_LEGACY_PTYS=y | ||
| 573 | CONFIG_LEGACY_PTY_COUNT=256 | ||
| 574 | # CONFIG_IPMI_HANDLER is not set | ||
| 575 | # CONFIG_HW_RANDOM is not set | ||
| 576 | # CONFIG_R3964 is not set | ||
| 577 | # CONFIG_RAW_DRIVER is not set | ||
| 578 | # CONFIG_TCG_TPM is not set | ||
| 579 | # CONFIG_I2C is not set | ||
| 580 | # CONFIG_SPI is not set | ||
| 581 | # CONFIG_W1 is not set | ||
| 582 | # CONFIG_POWER_SUPPLY is not set | ||
| 583 | # CONFIG_HWMON is not set | ||
| 584 | # CONFIG_THERMAL is not set | ||
| 585 | # CONFIG_THERMAL_HWMON is not set | ||
| 586 | CONFIG_WATCHDOG=y | ||
| 587 | # CONFIG_WATCHDOG_NOWAYOUT is not set | ||
| 588 | |||
| 589 | # | ||
| 590 | # Watchdog Device Drivers | ||
| 591 | # | ||
| 592 | # CONFIG_SOFT_WATCHDOG is not set | ||
| 593 | CONFIG_SSB_POSSIBLE=y | ||
| 594 | |||
| 595 | # | ||
| 596 | # Sonics Silicon Backplane | ||
| 597 | # | ||
| 598 | # CONFIG_SSB is not set | ||
| 599 | |||
| 600 | # | ||
| 601 | # Multifunction device drivers | ||
| 602 | # | ||
| 603 | # CONFIG_MFD_CORE is not set | ||
| 604 | # CONFIG_MFD_SM501 is not set | ||
| 605 | # CONFIG_HTC_PASIC3 is not set | ||
| 606 | # CONFIG_MFD_TMIO is not set | ||
| 607 | # CONFIG_REGULATOR is not set | ||
| 608 | |||
| 609 | # | ||
| 610 | # Multimedia devices | ||
| 611 | # | ||
| 612 | |||
| 613 | # | ||
| 614 | # Multimedia core support | ||
| 615 | # | ||
| 616 | # CONFIG_VIDEO_DEV is not set | ||
| 617 | # CONFIG_DVB_CORE is not set | ||
| 618 | # CONFIG_VIDEO_MEDIA is not set | ||
| 619 | |||
| 620 | # | ||
| 621 | # Multimedia drivers | ||
| 622 | # | ||
| 623 | # CONFIG_DAB is not set | ||
| 624 | |||
| 625 | # | ||
| 626 | # Graphics support | ||
| 627 | # | ||
| 628 | # CONFIG_VGASTATE is not set | ||
| 629 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 630 | # CONFIG_FB is not set | ||
| 631 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 632 | |||
| 633 | # | ||
| 634 | # Display device support | ||
| 635 | # | ||
| 636 | # CONFIG_DISPLAY_SUPPORT is not set | ||
| 637 | # CONFIG_SOUND is not set | ||
| 638 | # CONFIG_USB_SUPPORT is not set | ||
| 639 | # CONFIG_MMC is not set | ||
| 640 | # CONFIG_MEMSTICK is not set | ||
| 641 | # CONFIG_NEW_LEDS is not set | ||
| 642 | # CONFIG_ACCESSIBILITY is not set | ||
| 643 | CONFIG_RTC_LIB=y | ||
| 644 | # CONFIG_RTC_CLASS is not set | ||
| 645 | # CONFIG_DMADEVICES is not set | ||
| 646 | # CONFIG_UIO is not set | ||
| 647 | # CONFIG_STAGING is not set | ||
| 648 | CONFIG_STAGING_EXCLUDE_BUILD=y | ||
| 649 | |||
| 650 | # | ||
| 651 | # File systems | ||
| 652 | # | ||
| 653 | # CONFIG_EXT2_FS is not set | ||
| 654 | # CONFIG_EXT3_FS is not set | ||
| 655 | # CONFIG_EXT4_FS is not set | ||
| 656 | # CONFIG_REISERFS_FS is not set | ||
| 657 | # CONFIG_JFS_FS is not set | ||
| 658 | # CONFIG_FS_POSIX_ACL is not set | ||
| 659 | CONFIG_FILE_LOCKING=y | ||
| 660 | # CONFIG_XFS_FS is not set | ||
| 661 | # CONFIG_GFS2_FS is not set | ||
| 662 | # CONFIG_OCFS2_FS is not set | ||
| 663 | CONFIG_DNOTIFY=y | ||
| 664 | CONFIG_INOTIFY=y | ||
| 665 | CONFIG_INOTIFY_USER=y | ||
| 666 | # CONFIG_QUOTA is not set | ||
| 667 | # CONFIG_AUTOFS_FS is not set | ||
| 668 | # CONFIG_AUTOFS4_FS is not set | ||
| 669 | # CONFIG_FUSE_FS is not set | ||
| 670 | |||
| 671 | # | ||
| 672 | # CD-ROM/DVD Filesystems | ||
| 673 | # | ||
| 674 | # CONFIG_ISO9660_FS is not set | ||
| 675 | # CONFIG_UDF_FS is not set | ||
| 676 | |||
| 677 | # | ||
| 678 | # DOS/FAT/NT Filesystems | ||
| 679 | # | ||
| 680 | # CONFIG_MSDOS_FS is not set | ||
| 681 | # CONFIG_VFAT_FS is not set | ||
| 682 | # CONFIG_NTFS_FS is not set | ||
| 683 | |||
| 684 | # | ||
| 685 | # Pseudo filesystems | ||
| 686 | # | ||
| 687 | CONFIG_PROC_FS=y | ||
| 688 | CONFIG_PROC_KCORE=y | ||
| 689 | CONFIG_PROC_SYSCTL=y | ||
| 690 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 691 | CONFIG_SYSFS=y | ||
| 692 | CONFIG_TMPFS=y | ||
| 693 | # CONFIG_TMPFS_POSIX_ACL is not set | ||
| 694 | # CONFIG_HUGETLB_PAGE is not set | ||
| 695 | # CONFIG_CONFIGFS_FS is not set | ||
| 696 | |||
| 697 | # | ||
| 698 | # Miscellaneous filesystems | ||
| 699 | # | ||
| 700 | # CONFIG_ADFS_FS is not set | ||
| 701 | # CONFIG_AFFS_FS is not set | ||
| 702 | # CONFIG_HFS_FS is not set | ||
| 703 | # CONFIG_HFSPLUS_FS is not set | ||
| 704 | # CONFIG_BEFS_FS is not set | ||
| 705 | # CONFIG_BFS_FS is not set | ||
| 706 | # CONFIG_EFS_FS is not set | ||
| 707 | # CONFIG_JFFS2_FS is not set | ||
| 708 | # CONFIG_CRAMFS is not set | ||
| 709 | # CONFIG_VXFS_FS is not set | ||
| 710 | # CONFIG_MINIX_FS is not set | ||
| 711 | # CONFIG_OMFS_FS is not set | ||
| 712 | # CONFIG_HPFS_FS is not set | ||
| 713 | # CONFIG_QNX4FS_FS is not set | ||
| 714 | # CONFIG_ROMFS_FS is not set | ||
| 715 | # CONFIG_SYSV_FS is not set | ||
| 716 | # CONFIG_UFS_FS is not set | ||
| 717 | # CONFIG_NETWORK_FILESYSTEMS is not set | ||
| 718 | |||
| 719 | # | ||
| 720 | # Partition Types | ||
| 721 | # | ||
| 722 | # CONFIG_PARTITION_ADVANCED is not set | ||
| 723 | CONFIG_MSDOS_PARTITION=y | ||
| 724 | CONFIG_NLS=y | ||
| 725 | CONFIG_NLS_DEFAULT="iso8859-1" | ||
| 726 | CONFIG_NLS_CODEPAGE_437=y | ||
| 727 | # CONFIG_NLS_CODEPAGE_737 is not set | ||
| 728 | # CONFIG_NLS_CODEPAGE_775 is not set | ||
| 729 | # CONFIG_NLS_CODEPAGE_850 is not set | ||
| 730 | # CONFIG_NLS_CODEPAGE_852 is not set | ||
| 731 | # CONFIG_NLS_CODEPAGE_855 is not set | ||
| 732 | # CONFIG_NLS_CODEPAGE_857 is not set | ||
| 733 | # CONFIG_NLS_CODEPAGE_860 is not set | ||
| 734 | # CONFIG_NLS_CODEPAGE_861 is not set | ||
| 735 | # CONFIG_NLS_CODEPAGE_862 is not set | ||
| 736 | # CONFIG_NLS_CODEPAGE_863 is not set | ||
| 737 | # CONFIG_NLS_CODEPAGE_864 is not set | ||
| 738 | # CONFIG_NLS_CODEPAGE_865 is not set | ||
| 739 | # CONFIG_NLS_CODEPAGE_866 is not set | ||
| 740 | # CONFIG_NLS_CODEPAGE_869 is not set | ||
| 741 | # CONFIG_NLS_CODEPAGE_936 is not set | ||
| 742 | # CONFIG_NLS_CODEPAGE_950 is not set | ||
| 743 | # CONFIG_NLS_CODEPAGE_932 is not set | ||
| 744 | # CONFIG_NLS_CODEPAGE_949 is not set | ||
| 745 | # CONFIG_NLS_CODEPAGE_874 is not set | ||
| 746 | # CONFIG_NLS_ISO8859_8 is not set | ||
| 747 | # CONFIG_NLS_CODEPAGE_1250 is not set | ||
| 748 | # CONFIG_NLS_CODEPAGE_1251 is not set | ||
| 749 | # CONFIG_NLS_ASCII is not set | ||
| 750 | CONFIG_NLS_ISO8859_1=y | ||
| 751 | # CONFIG_NLS_ISO8859_2 is not set | ||
| 752 | # CONFIG_NLS_ISO8859_3 is not set | ||
| 753 | # CONFIG_NLS_ISO8859_4 is not set | ||
| 754 | # CONFIG_NLS_ISO8859_5 is not set | ||
| 755 | # CONFIG_NLS_ISO8859_6 is not set | ||
| 756 | # CONFIG_NLS_ISO8859_7 is not set | ||
| 757 | # CONFIG_NLS_ISO8859_9 is not set | ||
| 758 | # CONFIG_NLS_ISO8859_13 is not set | ||
| 759 | # CONFIG_NLS_ISO8859_14 is not set | ||
| 760 | # CONFIG_NLS_ISO8859_15 is not set | ||
| 761 | # CONFIG_NLS_KOI8_R is not set | ||
| 762 | # CONFIG_NLS_KOI8_U is not set | ||
| 763 | # CONFIG_NLS_UTF8 is not set | ||
| 764 | # CONFIG_DLM is not set | ||
| 765 | |||
| 766 | # | ||
| 767 | # Kernel hacking | ||
| 768 | # | ||
| 769 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
| 770 | # CONFIG_PRINTK_TIME is not set | ||
| 771 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
| 772 | CONFIG_ENABLE_MUST_CHECK=y | ||
| 773 | CONFIG_FRAME_WARN=2048 | ||
| 774 | CONFIG_MAGIC_SYSRQ=y | ||
| 775 | # CONFIG_UNUSED_SYMBOLS is not set | ||
| 776 | CONFIG_DEBUG_FS=y | ||
| 777 | # CONFIG_HEADERS_CHECK is not set | ||
| 778 | CONFIG_DEBUG_KERNEL=y | ||
| 779 | # CONFIG_DEBUG_SHIRQ is not set | ||
| 780 | CONFIG_DETECT_SOFTLOCKUP=y | ||
| 781 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
| 782 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
| 783 | CONFIG_SCHED_DEBUG=y | ||
| 784 | # CONFIG_SCHEDSTATS is not set | ||
| 785 | # CONFIG_TIMER_STATS is not set | ||
| 786 | # CONFIG_DEBUG_OBJECTS is not set | ||
| 787 | # CONFIG_DEBUG_SLAB is not set | ||
| 788 | CONFIG_DEBUG_PREEMPT=y | ||
| 789 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 790 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 791 | CONFIG_DEBUG_SPINLOCK=y | ||
| 792 | # CONFIG_DEBUG_MUTEXES is not set | ||
| 793 | # CONFIG_DEBUG_LOCK_ALLOC is not set | ||
| 794 | # CONFIG_PROVE_LOCKING is not set | ||
| 795 | # CONFIG_LOCK_STAT is not set | ||
| 796 | CONFIG_DEBUG_SPINLOCK_SLEEP=y | ||
| 797 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
| 798 | # CONFIG_DEBUG_KOBJECT is not set | ||
| 799 | CONFIG_DEBUG_INFO=y | ||
| 800 | # CONFIG_DEBUG_VM is not set | ||
| 801 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
| 802 | # CONFIG_DEBUG_MEMORY_INIT is not set | ||
| 803 | # CONFIG_DEBUG_LIST is not set | ||
| 804 | # CONFIG_DEBUG_SG is not set | ||
| 805 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 806 | # CONFIG_RCU_TORTURE_TEST is not set | ||
| 807 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 808 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 809 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
| 810 | # CONFIG_FAULT_INJECTION is not set | ||
| 811 | CONFIG_SYSCTL_SYSCALL_CHECK=y | ||
| 812 | |||
| 813 | # | ||
| 814 | # Tracers | ||
| 815 | # | ||
| 816 | # CONFIG_IRQSOFF_TRACER is not set | ||
| 817 | # CONFIG_PREEMPT_TRACER is not set | ||
| 818 | # CONFIG_SCHED_TRACER is not set | ||
| 819 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | ||
| 820 | # CONFIG_BOOT_TRACER is not set | ||
| 821 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | ||
| 822 | # CONFIG_SAMPLES is not set | ||
| 823 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 824 | # CONFIG_KGDB is not set | ||
| 825 | CONFIG_CMDLINE="" | ||
| 826 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
| 827 | # CONFIG_RUNTIME_DEBUG is not set | ||
| 828 | |||
| 829 | # | ||
| 830 | # Security options | ||
| 831 | # | ||
| 832 | # CONFIG_KEYS is not set | ||
| 833 | CONFIG_SECURITY=y | ||
| 834 | # CONFIG_SECURITYFS is not set | ||
| 835 | CONFIG_SECURITY_NETWORK=y | ||
| 836 | # CONFIG_SECURITY_NETWORK_XFRM is not set | ||
| 837 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | ||
| 838 | CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0 | ||
| 839 | CONFIG_CRYPTO=y | ||
| 840 | |||
| 841 | # | ||
| 842 | # Crypto core or helper | ||
| 843 | # | ||
| 844 | # CONFIG_CRYPTO_FIPS is not set | ||
| 845 | CONFIG_CRYPTO_ALGAPI=y | ||
| 846 | CONFIG_CRYPTO_AEAD=y | ||
| 847 | CONFIG_CRYPTO_BLKCIPHER=y | ||
| 848 | CONFIG_CRYPTO_HASH=y | ||
| 849 | CONFIG_CRYPTO_RNG=y | ||
| 850 | CONFIG_CRYPTO_MANAGER=y | ||
| 851 | # CONFIG_CRYPTO_GF128MUL is not set | ||
| 852 | # CONFIG_CRYPTO_NULL is not set | ||
| 853 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 854 | # CONFIG_CRYPTO_AUTHENC is not set | ||
| 855 | # CONFIG_CRYPTO_TEST is not set | ||
| 856 | |||
| 857 | # | ||
| 858 | # Authenticated Encryption with Associated Data | ||
| 859 | # | ||
| 860 | # CONFIG_CRYPTO_CCM is not set | ||
| 861 | # CONFIG_CRYPTO_GCM is not set | ||
| 862 | # CONFIG_CRYPTO_SEQIV is not set | ||
| 863 | |||
| 864 | # | ||
| 865 | # Block modes | ||
| 866 | # | ||
| 867 | CONFIG_CRYPTO_CBC=y | ||
| 868 | # CONFIG_CRYPTO_CTR is not set | ||
| 869 | # CONFIG_CRYPTO_CTS is not set | ||
| 870 | # CONFIG_CRYPTO_ECB is not set | ||
| 871 | # CONFIG_CRYPTO_LRW is not set | ||
| 872 | # CONFIG_CRYPTO_PCBC is not set | ||
| 873 | # CONFIG_CRYPTO_XTS is not set | ||
| 874 | |||
| 875 | # | ||
| 876 | # Hash modes | ||
| 877 | # | ||
| 878 | CONFIG_CRYPTO_HMAC=y | ||
| 879 | # CONFIG_CRYPTO_XCBC is not set | ||
| 880 | |||
| 881 | # | ||
| 882 | # Digest | ||
| 883 | # | ||
| 884 | # CONFIG_CRYPTO_CRC32C is not set | ||
| 885 | # CONFIG_CRYPTO_MD4 is not set | ||
| 886 | CONFIG_CRYPTO_MD5=y | ||
| 887 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | ||
| 888 | # CONFIG_CRYPTO_RMD128 is not set | ||
| 889 | # CONFIG_CRYPTO_RMD160 is not set | ||
| 890 | # CONFIG_CRYPTO_RMD256 is not set | ||
| 891 | # CONFIG_CRYPTO_RMD320 is not set | ||
| 892 | # CONFIG_CRYPTO_SHA1 is not set | ||
| 893 | # CONFIG_CRYPTO_SHA256 is not set | ||
| 894 | # CONFIG_CRYPTO_SHA512 is not set | ||
| 895 | # CONFIG_CRYPTO_TGR192 is not set | ||
| 896 | # CONFIG_CRYPTO_WP512 is not set | ||
| 897 | |||
| 898 | # | ||
| 899 | # Ciphers | ||
| 900 | # | ||
| 901 | # CONFIG_CRYPTO_AES is not set | ||
| 902 | # CONFIG_CRYPTO_ANUBIS is not set | ||
| 903 | # CONFIG_CRYPTO_ARC4 is not set | ||
| 904 | # CONFIG_CRYPTO_BLOWFISH is not set | ||
| 905 | # CONFIG_CRYPTO_CAMELLIA is not set | ||
| 906 | # CONFIG_CRYPTO_CAST5 is not set | ||
| 907 | # CONFIG_CRYPTO_CAST6 is not set | ||
| 908 | CONFIG_CRYPTO_DES=y | ||
| 909 | # CONFIG_CRYPTO_FCRYPT is not set | ||
| 910 | # CONFIG_CRYPTO_KHAZAD is not set | ||
| 911 | # CONFIG_CRYPTO_SALSA20 is not set | ||
| 912 | # CONFIG_CRYPTO_SEED is not set | ||
| 913 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 914 | # CONFIG_CRYPTO_TEA is not set | ||
| 915 | # CONFIG_CRYPTO_TWOFISH is not set | ||
| 916 | |||
| 917 | # | ||
| 918 | # Compression | ||
| 919 | # | ||
| 920 | # CONFIG_CRYPTO_DEFLATE is not set | ||
| 921 | # CONFIG_CRYPTO_LZO is not set | ||
| 922 | |||
| 923 | # | ||
| 924 | # Random Number Generation | ||
| 925 | # | ||
| 926 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 927 | CONFIG_CRYPTO_HW=y | ||
| 928 | |||
| 929 | # | ||
| 930 | # Library routines | ||
| 931 | # | ||
| 932 | CONFIG_BITREVERSE=y | ||
| 933 | # CONFIG_CRC_CCITT is not set | ||
| 934 | # CONFIG_CRC16 is not set | ||
| 935 | # CONFIG_CRC_T10DIF is not set | ||
| 936 | # CONFIG_CRC_ITU_T is not set | ||
| 937 | CONFIG_CRC32=y | ||
| 938 | # CONFIG_CRC7 is not set | ||
| 939 | # CONFIG_LIBCRC32C is not set | ||
| 940 | CONFIG_PLIST=y | ||
| 941 | CONFIG_HAS_IOMEM=y | ||
| 942 | CONFIG_HAS_IOPORT=y | ||
| 943 | CONFIG_HAS_DMA=y | ||
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index 12d12dfe73c0..a0d14f85b781 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h | |||
| @@ -38,6 +38,9 @@ | |||
| 38 | #ifndef cpu_has_tx39_cache | 38 | #ifndef cpu_has_tx39_cache |
| 39 | #define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE) | 39 | #define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE) |
| 40 | #endif | 40 | #endif |
| 41 | #ifndef cpu_has_octeon_cache | ||
| 42 | #define cpu_has_octeon_cache 0 | ||
| 43 | #endif | ||
| 41 | #ifndef cpu_has_fpu | 44 | #ifndef cpu_has_fpu |
| 42 | #define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU) | 45 | #define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU) |
| 43 | #define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU) | 46 | #define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU) |
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 229a786101d9..c018727c7ddc 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h | |||
| @@ -33,6 +33,7 @@ | |||
| 33 | #define PRID_COMP_TOSHIBA 0x070000 | 33 | #define PRID_COMP_TOSHIBA 0x070000 |
| 34 | #define PRID_COMP_LSI 0x080000 | 34 | #define PRID_COMP_LSI 0x080000 |
| 35 | #define PRID_COMP_LEXRA 0x0b0000 | 35 | #define PRID_COMP_LEXRA 0x0b0000 |
| 36 | #define PRID_COMP_CAVIUM 0x0d0000 | ||
| 36 | 37 | ||
| 37 | 38 | ||
| 38 | /* | 39 | /* |
| @@ -114,6 +115,18 @@ | |||
| 114 | #define PRID_IMP_BCM3302 0x9000 | 115 | #define PRID_IMP_BCM3302 0x9000 |
| 115 | 116 | ||
| 116 | /* | 117 | /* |
| 118 | * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM | ||
| 119 | */ | ||
| 120 | |||
| 121 | #define PRID_IMP_CAVIUM_CN38XX 0x0000 | ||
| 122 | #define PRID_IMP_CAVIUM_CN31XX 0x0100 | ||
| 123 | #define PRID_IMP_CAVIUM_CN30XX 0x0200 | ||
| 124 | #define PRID_IMP_CAVIUM_CN58XX 0x0300 | ||
| 125 | #define PRID_IMP_CAVIUM_CN56XX 0x0400 | ||
| 126 | #define PRID_IMP_CAVIUM_CN50XX 0x0600 | ||
| 127 | #define PRID_IMP_CAVIUM_CN52XX 0x0700 | ||
| 128 | |||
| 129 | /* | ||
| 117 | * Definitions for 7:0 on legacy processors | 130 | * Definitions for 7:0 on legacy processors |
| 118 | */ | 131 | */ |
| 119 | 132 | ||
| @@ -203,6 +216,7 @@ enum cpu_type_enum { | |||
| 203 | * MIPS64 class processors | 216 | * MIPS64 class processors |
| 204 | */ | 217 | */ |
| 205 | CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, | 218 | CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, |
| 219 | CPU_CAVIUM_OCTEON, | ||
| 206 | 220 | ||
| 207 | CPU_LAST | 221 | CPU_LAST |
| 208 | }; | 222 | }; |
diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h index 2de638f84c86..43baed16a109 100644 --- a/arch/mips/include/asm/hazards.h +++ b/arch/mips/include/asm/hazards.h | |||
| @@ -42,7 +42,7 @@ ASMMACRO(_ehb, | |||
| 42 | /* | 42 | /* |
| 43 | * TLB hazards | 43 | * TLB hazards |
| 44 | */ | 44 | */ |
| 45 | #if defined(CONFIG_CPU_MIPSR2) | 45 | #if defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_CPU_CAVIUM_OCTEON) |
| 46 | 46 | ||
| 47 | /* | 47 | /* |
| 48 | * MIPSR2 defines ehb for hazard avoidance | 48 | * MIPSR2 defines ehb for hazard avoidance |
| @@ -138,7 +138,7 @@ do { \ | |||
| 138 | __instruction_hazard(); \ | 138 | __instruction_hazard(); \ |
| 139 | } while (0) | 139 | } while (0) |
| 140 | 140 | ||
| 141 | #elif defined(CONFIG_CPU_R10000) | 141 | #elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON) |
| 142 | 142 | ||
| 143 | /* | 143 | /* |
| 144 | * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. | 144 | * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. |
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index 501a40b9f18d..436878e4e063 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h | |||
| @@ -295,6 +295,12 @@ static inline void iounmap(const volatile void __iomem *addr) | |||
| 295 | #undef __IS_KSEG1 | 295 | #undef __IS_KSEG1 |
| 296 | } | 296 | } |
| 297 | 297 | ||
| 298 | #ifdef CONFIG_CPU_CAVIUM_OCTEON | ||
| 299 | #define war_octeon_io_reorder_wmb() wmb() | ||
| 300 | #else | ||
| 301 | #define war_octeon_io_reorder_wmb() do { } while (0) | ||
| 302 | #endif | ||
| 303 | |||
| 298 | #define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \ | 304 | #define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \ |
| 299 | \ | 305 | \ |
| 300 | static inline void pfx##write##bwlq(type val, \ | 306 | static inline void pfx##write##bwlq(type val, \ |
| @@ -303,6 +309,8 @@ static inline void pfx##write##bwlq(type val, \ | |||
| 303 | volatile type *__mem; \ | 309 | volatile type *__mem; \ |
| 304 | type __val; \ | 310 | type __val; \ |
| 305 | \ | 311 | \ |
| 312 | war_octeon_io_reorder_wmb(); \ | ||
| 313 | \ | ||
| 306 | __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \ | 314 | __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \ |
| 307 | \ | 315 | \ |
| 308 | __val = pfx##ioswab##bwlq(__mem, val); \ | 316 | __val = pfx##ioswab##bwlq(__mem, val); \ |
| @@ -370,6 +378,8 @@ static inline void pfx##out##bwlq##p(type val, unsigned long port) \ | |||
| 370 | volatile type *__addr; \ | 378 | volatile type *__addr; \ |
| 371 | type __val; \ | 379 | type __val; \ |
| 372 | \ | 380 | \ |
| 381 | war_octeon_io_reorder_wmb(); \ | ||
| 382 | \ | ||
| 373 | __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \ | 383 | __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \ |
| 374 | \ | 384 | \ |
| 375 | __val = pfx##ioswab##bwlq(__addr, val); \ | 385 | __val = pfx##ioswab##bwlq(__addr, val); \ |
| @@ -504,8 +514,12 @@ BUILDSTRING(q, u64) | |||
| 504 | #endif | 514 | #endif |
| 505 | 515 | ||
| 506 | 516 | ||
| 517 | #ifdef CONFIG_CPU_CAVIUM_OCTEON | ||
| 518 | #define mmiowb() wmb() | ||
| 519 | #else | ||
| 507 | /* Depends on MIPS II instruction set */ | 520 | /* Depends on MIPS II instruction set */ |
| 508 | #define mmiowb() asm volatile ("sync" ::: "memory") | 521 | #define mmiowb() asm volatile ("sync" ::: "memory") |
| 522 | #endif | ||
| 509 | 523 | ||
| 510 | static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count) | 524 | static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count) |
| 511 | { | 525 | { |
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index 0d302bad4492..62f91f50b5b5 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h | |||
| @@ -91,14 +91,57 @@ static inline u32 au_readl(unsigned long reg) | |||
| 91 | return *(volatile u32 *)reg; | 91 | return *(volatile u32 *)reg; |
| 92 | } | 92 | } |
| 93 | 93 | ||
| 94 | /* Early Au1000 have a write-only SYS_CPUPLL register. */ | ||
| 95 | static inline int au1xxx_cpu_has_pll_wo(void) | ||
| 96 | { | ||
| 97 | switch (read_c0_prid()) { | ||
| 98 | case 0x00030100: /* Au1000 DA */ | ||
| 99 | case 0x00030201: /* Au1000 HA */ | ||
| 100 | case 0x00030202: /* Au1000 HB */ | ||
| 101 | return 1; | ||
| 102 | } | ||
| 103 | return 0; | ||
| 104 | } | ||
| 105 | |||
| 106 | /* does CPU need CONFIG[OD] set to fix tons of errata? */ | ||
| 107 | static inline int au1xxx_cpu_needs_config_od(void) | ||
| 108 | { | ||
| 109 | /* | ||
| 110 | * c0_config.od (bit 19) was write only (and read as 0) on the | ||
| 111 | * early revisions of Alchemy SOCs. It disables the bus trans- | ||
| 112 | * action overlapping and needs to be set to fix various errata. | ||
| 113 | */ | ||
| 114 | switch (read_c0_prid()) { | ||
| 115 | case 0x00030100: /* Au1000 DA */ | ||
| 116 | case 0x00030201: /* Au1000 HA */ | ||
| 117 | case 0x00030202: /* Au1000 HB */ | ||
| 118 | case 0x01030200: /* Au1500 AB */ | ||
| 119 | /* | ||
| 120 | * Au1100/Au1200 errata actually keep silence about this bit, | ||
| 121 | * so we set it just in case for those revisions that require | ||
| 122 | * it to be set according to the (now gone) cpu_table. | ||
| 123 | */ | ||
| 124 | case 0x02030200: /* Au1100 AB */ | ||
| 125 | case 0x02030201: /* Au1100 BA */ | ||
| 126 | case 0x02030202: /* Au1100 BC */ | ||
| 127 | case 0x04030201: /* Au1200 AC */ | ||
| 128 | return 1; | ||
| 129 | } | ||
| 130 | return 0; | ||
| 131 | } | ||
| 94 | 132 | ||
| 95 | /* arch/mips/au1000/common/clocks.c */ | 133 | /* arch/mips/au1000/common/clocks.c */ |
| 96 | extern void set_au1x00_speed(unsigned int new_freq); | 134 | extern void set_au1x00_speed(unsigned int new_freq); |
| 97 | extern unsigned int get_au1x00_speed(void); | 135 | extern unsigned int get_au1x00_speed(void); |
| 98 | extern void set_au1x00_uart_baud_base(unsigned long new_baud_base); | 136 | extern void set_au1x00_uart_baud_base(unsigned long new_baud_base); |
| 99 | extern unsigned long get_au1x00_uart_baud_base(void); | 137 | extern unsigned long get_au1x00_uart_baud_base(void); |
| 100 | extern void set_au1x00_lcd_clock(void); | 138 | extern unsigned long au1xxx_calc_clock(void); |
| 101 | extern unsigned int get_au1x00_lcd_clock(void); | 139 | |
| 140 | /* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */ | ||
| 141 | void au1xxx_save_and_sleep(void); | ||
| 142 | void au_sleep(void); | ||
| 143 | void save_au1xxx_intctl(void); | ||
| 144 | void restore_au1xxx_intctl(void); | ||
| 102 | 145 | ||
| 103 | /* | 146 | /* |
| 104 | * Every board describes its IRQ mapping with this table. | 147 | * Every board describes its IRQ mapping with this table. |
| @@ -109,10 +152,11 @@ struct au1xxx_irqmap { | |||
| 109 | int im_request; | 152 | int im_request; |
| 110 | }; | 153 | }; |
| 111 | 154 | ||
| 112 | /* | 155 | /* core calls this function to let boards initialize other IRQ sources */ |
| 113 | * init_IRQ looks for a table with this name. | 156 | void board_init_irq(void); |
| 114 | */ | 157 | |
| 115 | extern struct au1xxx_irqmap au1xxx_irq_map[]; | 158 | /* boards call this to register additional (GPIO) interrupts */ |
| 159 | void au1xxx_setup_irqmap(struct au1xxx_irqmap *map, int count); | ||
| 116 | 160 | ||
| 117 | #endif /* !defined (_LANGUAGE_ASSEMBLY) */ | 161 | #endif /* !defined (_LANGUAGE_ASSEMBLY) */ |
| 118 | 162 | ||
| @@ -505,15 +549,6 @@ extern struct au1xxx_irqmap au1xxx_irq_map[]; | |||
| 505 | 549 | ||
| 506 | #define IC1_TESTBIT 0xB1800080 | 550 | #define IC1_TESTBIT 0xB1800080 |
| 507 | 551 | ||
| 508 | /* Interrupt Configuration Modes */ | ||
| 509 | #define INTC_INT_DISABLED 0x0 | ||
| 510 | #define INTC_INT_RISE_EDGE 0x1 | ||
| 511 | #define INTC_INT_FALL_EDGE 0x2 | ||
| 512 | #define INTC_INT_RISE_AND_FALL_EDGE 0x3 | ||
| 513 | #define INTC_INT_HIGH_LEVEL 0x5 | ||
| 514 | #define INTC_INT_LOW_LEVEL 0x6 | ||
| 515 | #define INTC_INT_HIGH_AND_LOW_LEVEL 0x7 | ||
| 516 | |||
| 517 | /* Interrupt Numbers */ | 552 | /* Interrupt Numbers */ |
| 518 | /* Au1000 */ | 553 | /* Au1000 */ |
| 519 | #ifdef CONFIG_SOC_AU1000 | 554 | #ifdef CONFIG_SOC_AU1000 |
| @@ -1525,6 +1560,10 @@ enum soc_au1200_ints { | |||
| 1525 | #define SYS_SLPPWR 0xB1900078 | 1560 | #define SYS_SLPPWR 0xB1900078 |
| 1526 | #define SYS_SLEEP 0xB190007C | 1561 | #define SYS_SLEEP 0xB190007C |
| 1527 | 1562 | ||
| 1563 | #define SYS_WAKEMSK_D2 (1 << 9) | ||
| 1564 | #define SYS_WAKEMSK_M2 (1 << 8) | ||
| 1565 | #define SYS_WAKEMSK_GPIO(x) (1 << (x)) | ||
| 1566 | |||
| 1528 | /* Clock Controller */ | 1567 | /* Clock Controller */ |
| 1529 | #define SYS_FREQCTRL0 0xB1900020 | 1568 | #define SYS_FREQCTRL0 0xB1900020 |
| 1530 | # define SYS_FC_FRDIV2_BIT 22 | 1569 | # define SYS_FC_FRDIV2_BIT 22 |
| @@ -1749,24 +1788,4 @@ static AU1X00_SYS * const sys = (AU1X00_SYS *)SYS_BASE; | |||
| 1749 | 1788 | ||
| 1750 | #endif | 1789 | #endif |
| 1751 | 1790 | ||
| 1752 | /* | ||
| 1753 | * Processor information based on PRID. | ||
| 1754 | * Copied from PowerPC. | ||
| 1755 | */ | ||
| 1756 | #ifndef _LANGUAGE_ASSEMBLY | ||
| 1757 | struct cpu_spec { | ||
| 1758 | /* CPU is matched via (PRID & prid_mask) == prid_value */ | ||
| 1759 | unsigned int prid_mask; | ||
| 1760 | unsigned int prid_value; | ||
| 1761 | |||
| 1762 | char *cpu_name; | ||
| 1763 | unsigned char cpu_od; /* Set Config[OD] */ | ||
| 1764 | unsigned char cpu_bclk; /* Enable BCLK switching */ | ||
| 1765 | unsigned char cpu_pll_wo; /* sys_cpupll reg. write-only */ | ||
| 1766 | }; | ||
| 1767 | |||
| 1768 | extern struct cpu_spec cpu_specs[]; | ||
| 1769 | extern struct cpu_spec *cur_cpu_spec[]; | ||
| 1770 | #endif | ||
| 1771 | |||
| 1772 | #endif | 1791 | #endif |
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h index 44a67bf05dc1..06f68f43800a 100644 --- a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h +++ b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h | |||
| @@ -357,6 +357,11 @@ u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr); | |||
| 357 | u32 au1xxx_ddma_add_device(dbdev_tab_t *dev); | 357 | u32 au1xxx_ddma_add_device(dbdev_tab_t *dev); |
| 358 | extern void au1xxx_ddma_del_device(u32 devid); | 358 | extern void au1xxx_ddma_del_device(u32 devid); |
| 359 | void *au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp); | 359 | void *au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp); |
| 360 | #ifdef CONFIG_PM | ||
| 361 | void au1xxx_dbdma_suspend(void); | ||
| 362 | void au1xxx_dbdma_resume(void); | ||
| 363 | #endif | ||
| 364 | |||
| 360 | 365 | ||
| 361 | /* | 366 | /* |
| 362 | * Some compatibilty macros -- needed to make changes to API | 367 | * Some compatibilty macros -- needed to make changes to API |
diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h new file mode 100644 index 000000000000..04ce6e6569da --- /dev/null +++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h | |||
| @@ -0,0 +1,78 @@ | |||
| 1 | /* | ||
| 2 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 3 | * License. See the file "COPYING" in the main directory of this archive | ||
| 4 | * for more details. | ||
| 5 | * | ||
| 6 | * Copyright (C) 2004 Cavium Networks | ||
| 7 | */ | ||
| 8 | #ifndef __ASM_MACH_CAVIUM_OCTEON_CPU_FEATURE_OVERRIDES_H | ||
| 9 | #define __ASM_MACH_CAVIUM_OCTEON_CPU_FEATURE_OVERRIDES_H | ||
| 10 | |||
| 11 | #include <linux/types.h> | ||
| 12 | #include <asm/mipsregs.h> | ||
| 13 | |||
| 14 | /* | ||
| 15 | * Cavium Octeons are MIPS64v2 processors | ||
| 16 | */ | ||
| 17 | #define cpu_dcache_line_size() 128 | ||
| 18 | #define cpu_icache_line_size() 128 | ||
| 19 | |||
| 20 | |||
| 21 | #define cpu_has_4kex 1 | ||
| 22 | #define cpu_has_3k_cache 0 | ||
| 23 | #define cpu_has_4k_cache 0 | ||
| 24 | #define cpu_has_tx39_cache 0 | ||
| 25 | #define cpu_has_fpu 0 | ||
| 26 | #define cpu_has_counter 1 | ||
| 27 | #define cpu_has_watch 1 | ||
| 28 | #define cpu_has_divec 1 | ||
| 29 | #define cpu_has_vce 0 | ||
| 30 | #define cpu_has_cache_cdex_p 0 | ||
| 31 | #define cpu_has_cache_cdex_s 0 | ||
| 32 | #define cpu_has_prefetch 1 | ||
| 33 | |||
| 34 | /* | ||
| 35 | * We should disable LL/SC on non SMP systems as it is faster to | ||
| 36 | * disable interrupts for atomic access than a LL/SC. Unfortunatly we | ||
| 37 | * cannot as this breaks asm/futex.h | ||
| 38 | */ | ||
| 39 | #define cpu_has_llsc 1 | ||
| 40 | #define cpu_has_vtag_icache 1 | ||
| 41 | #define cpu_has_dc_aliases 0 | ||
| 42 | #define cpu_has_ic_fills_f_dc 0 | ||
| 43 | #define cpu_has_64bits 1 | ||
| 44 | #define cpu_has_octeon_cache 1 | ||
| 45 | #define cpu_has_saa octeon_has_saa() | ||
| 46 | #define cpu_has_mips32r1 0 | ||
| 47 | #define cpu_has_mips32r2 0 | ||
| 48 | #define cpu_has_mips64r1 0 | ||
| 49 | #define cpu_has_mips64r2 1 | ||
| 50 | #define cpu_has_dsp 0 | ||
| 51 | #define cpu_has_mipsmt 0 | ||
| 52 | #define cpu_has_userlocal 0 | ||
| 53 | #define cpu_has_vint 0 | ||
| 54 | #define cpu_has_veic 0 | ||
| 55 | #define ARCH_HAS_READ_CURRENT_TIMER 1 | ||
| 56 | #define ARCH_HAS_IRQ_PER_CPU 1 | ||
| 57 | #define ARCH_HAS_SPINLOCK_PREFETCH 1 | ||
| 58 | #define spin_lock_prefetch(x) prefetch(x) | ||
| 59 | #define PREFETCH_STRIDE 128 | ||
| 60 | |||
| 61 | static inline int read_current_timer(unsigned long *result) | ||
| 62 | { | ||
| 63 | asm volatile ("rdhwr %0,$31\n" | ||
| 64 | #ifndef CONFIG_64BIT | ||
| 65 | "\tsll %0, 0" | ||
| 66 | #endif | ||
| 67 | : "=r" (*result)); | ||
| 68 | return 0; | ||
| 69 | } | ||
| 70 | |||
| 71 | static inline int octeon_has_saa(void) | ||
| 72 | { | ||
| 73 | int id; | ||
| 74 | asm volatile ("mfc0 %0, $15,0" : "=r" (id)); | ||
| 75 | return id >= 0x000d0300; | ||
| 76 | } | ||
| 77 | |||
| 78 | #endif | ||
diff --git a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h new file mode 100644 index 000000000000..f30fce92aabb --- /dev/null +++ b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h | |||
| @@ -0,0 +1,64 @@ | |||
| 1 | /* | ||
| 2 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 3 | * License. See the file "COPYING" in the main directory of this archive | ||
| 4 | * for more details. | ||
| 5 | * | ||
| 6 | * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org> | ||
| 7 | * | ||
| 8 | * | ||
| 9 | * Similar to mach-generic/dma-coherence.h except | ||
| 10 | * plat_device_is_coherent hard coded to return 1. | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | #ifndef __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H | ||
| 14 | #define __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H | ||
| 15 | |||
| 16 | struct device; | ||
| 17 | |||
| 18 | dma_addr_t octeon_map_dma_mem(struct device *, void *, size_t); | ||
| 19 | void octeon_unmap_dma_mem(struct device *, dma_addr_t); | ||
| 20 | |||
| 21 | static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, | ||
| 22 | size_t size) | ||
| 23 | { | ||
| 24 | return octeon_map_dma_mem(dev, addr, size); | ||
| 25 | } | ||
| 26 | |||
| 27 | static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, | ||
| 28 | struct page *page) | ||
| 29 | { | ||
| 30 | return octeon_map_dma_mem(dev, page_address(page), PAGE_SIZE); | ||
| 31 | } | ||
| 32 | |||
| 33 | static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) | ||
| 34 | { | ||
| 35 | return dma_addr; | ||
| 36 | } | ||
| 37 | |||
| 38 | static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr) | ||
| 39 | { | ||
| 40 | octeon_unmap_dma_mem(dev, dma_addr); | ||
| 41 | } | ||
| 42 | |||
| 43 | static inline int plat_dma_supported(struct device *dev, u64 mask) | ||
| 44 | { | ||
| 45 | return 1; | ||
| 46 | } | ||
| 47 | |||
| 48 | static inline void plat_extra_sync_for_device(struct device *dev) | ||
| 49 | { | ||
| 50 | mb(); | ||
| 51 | } | ||
| 52 | |||
| 53 | static inline int plat_device_is_coherent(struct device *dev) | ||
| 54 | { | ||
| 55 | return 1; | ||
| 56 | } | ||
| 57 | |||
| 58 | static inline int plat_dma_mapping_error(struct device *dev, | ||
| 59 | dma_addr_t dma_addr) | ||
| 60 | { | ||
| 61 | return dma_addr == -1; | ||
| 62 | } | ||
| 63 | |||
| 64 | #endif /* __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H */ | ||
diff --git a/arch/mips/include/asm/mach-cavium-octeon/irq.h b/arch/mips/include/asm/mach-cavium-octeon/irq.h new file mode 100644 index 000000000000..d32220fbf4f1 --- /dev/null +++ b/arch/mips/include/asm/mach-cavium-octeon/irq.h | |||
| @@ -0,0 +1,244 @@ | |||
| 1 | /* | ||
| 2 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 3 | * License. See the file "COPYING" in the main directory of this archive | ||
| 4 | * for more details. | ||
| 5 | * | ||
| 6 | * Copyright (C) 2004-2008 Cavium Networks | ||
| 7 | */ | ||
| 8 | #ifndef __OCTEON_IRQ_H__ | ||
| 9 | #define __OCTEON_IRQ_H__ | ||
| 10 | |||
| 11 | #define NR_IRQS OCTEON_IRQ_LAST | ||
| 12 | #define MIPS_CPU_IRQ_BASE OCTEON_IRQ_SW0 | ||
| 13 | |||
| 14 | /* 0 - 7 represent the i8259 master */ | ||
| 15 | #define OCTEON_IRQ_I8259M0 0 | ||
| 16 | #define OCTEON_IRQ_I8259M1 1 | ||
| 17 | #define OCTEON_IRQ_I8259M2 2 | ||
| 18 | #define OCTEON_IRQ_I8259M3 3 | ||
| 19 | #define OCTEON_IRQ_I8259M4 4 | ||
| 20 | #define OCTEON_IRQ_I8259M5 5 | ||
| 21 | #define OCTEON_IRQ_I8259M6 6 | ||
| 22 | #define OCTEON_IRQ_I8259M7 7 | ||
| 23 | /* 8 - 15 represent the i8259 slave */ | ||
| 24 | #define OCTEON_IRQ_I8259S0 8 | ||
| 25 | #define OCTEON_IRQ_I8259S1 9 | ||
| 26 | #define OCTEON_IRQ_I8259S2 10 | ||
| 27 | #define OCTEON_IRQ_I8259S3 11 | ||
| 28 | #define OCTEON_IRQ_I8259S4 12 | ||
| 29 | #define OCTEON_IRQ_I8259S5 13 | ||
| 30 | #define OCTEON_IRQ_I8259S6 14 | ||
| 31 | #define OCTEON_IRQ_I8259S7 15 | ||
| 32 | /* 16 - 23 represent the 8 MIPS standard interrupt sources */ | ||
| 33 | #define OCTEON_IRQ_SW0 16 | ||
| 34 | #define OCTEON_IRQ_SW1 17 | ||
| 35 | #define OCTEON_IRQ_CIU0 18 | ||
| 36 | #define OCTEON_IRQ_CIU1 19 | ||
| 37 | #define OCTEON_IRQ_CIU4 20 | ||
| 38 | #define OCTEON_IRQ_5 21 | ||
| 39 | #define OCTEON_IRQ_PERF 22 | ||
| 40 | #define OCTEON_IRQ_TIMER 23 | ||
| 41 | /* 24 - 87 represent the sources in CIU_INTX_EN0 */ | ||
| 42 | #define OCTEON_IRQ_WORKQ0 24 | ||
| 43 | #define OCTEON_IRQ_WORKQ1 25 | ||
| 44 | #define OCTEON_IRQ_WORKQ2 26 | ||
| 45 | #define OCTEON_IRQ_WORKQ3 27 | ||
| 46 | #define OCTEON_IRQ_WORKQ4 28 | ||
| 47 | #define OCTEON_IRQ_WORKQ5 29 | ||
| 48 | #define OCTEON_IRQ_WORKQ6 30 | ||
| 49 | #define OCTEON_IRQ_WORKQ7 31 | ||
| 50 | #define OCTEON_IRQ_WORKQ8 32 | ||
| 51 | #define OCTEON_IRQ_WORKQ9 33 | ||
| 52 | #define OCTEON_IRQ_WORKQ10 34 | ||
| 53 | #define OCTEON_IRQ_WORKQ11 35 | ||
| 54 | #define OCTEON_IRQ_WORKQ12 36 | ||
| 55 | #define OCTEON_IRQ_WORKQ13 37 | ||
| 56 | #define OCTEON_IRQ_WORKQ14 38 | ||
| 57 | #define OCTEON_IRQ_WORKQ15 39 | ||
| 58 | #define OCTEON_IRQ_GPIO0 40 | ||
| 59 | #define OCTEON_IRQ_GPIO1 41 | ||
| 60 | #define OCTEON_IRQ_GPIO2 42 | ||
| 61 | #define OCTEON_IRQ_GPIO3 43 | ||
| 62 | #define OCTEON_IRQ_GPIO4 44 | ||
| 63 | #define OCTEON_IRQ_GPIO5 45 | ||
| 64 | #define OCTEON_IRQ_GPIO6 46 | ||
| 65 | #define OCTEON_IRQ_GPIO7 47 | ||
| 66 | #define OCTEON_IRQ_GPIO8 48 | ||
| 67 | #define OCTEON_IRQ_GPIO9 49 | ||
| 68 | #define OCTEON_IRQ_GPIO10 50 | ||
| 69 | #define OCTEON_IRQ_GPIO11 51 | ||
| 70 | #define OCTEON_IRQ_GPIO12 52 | ||
| 71 | #define OCTEON_IRQ_GPIO13 53 | ||
| 72 | #define OCTEON_IRQ_GPIO14 54 | ||
| 73 | #define OCTEON_IRQ_GPIO15 55 | ||
| 74 | #define OCTEON_IRQ_MBOX0 56 | ||
| 75 | #define OCTEON_IRQ_MBOX1 57 | ||
| 76 | #define OCTEON_IRQ_UART0 58 | ||
| 77 | #define OCTEON_IRQ_UART1 59 | ||
| 78 | #define OCTEON_IRQ_PCI_INT0 60 | ||
| 79 | #define OCTEON_IRQ_PCI_INT1 61 | ||
| 80 | #define OCTEON_IRQ_PCI_INT2 62 | ||
| 81 | #define OCTEON_IRQ_PCI_INT3 63 | ||
| 82 | #define OCTEON_IRQ_PCI_MSI0 64 | ||
| 83 | #define OCTEON_IRQ_PCI_MSI1 65 | ||
| 84 | #define OCTEON_IRQ_PCI_MSI2 66 | ||
| 85 | #define OCTEON_IRQ_PCI_MSI3 67 | ||
| 86 | #define OCTEON_IRQ_RESERVED68 68 /* Summary of CIU_INT_SUM1 */ | ||
| 87 | #define OCTEON_IRQ_TWSI 69 | ||
| 88 | #define OCTEON_IRQ_RML 70 | ||
| 89 | #define OCTEON_IRQ_TRACE 71 | ||
| 90 | #define OCTEON_IRQ_GMX_DRP0 72 | ||
| 91 | #define OCTEON_IRQ_GMX_DRP1 73 | ||
| 92 | #define OCTEON_IRQ_IPD_DRP 74 | ||
| 93 | #define OCTEON_IRQ_KEY_ZERO 75 | ||
| 94 | #define OCTEON_IRQ_TIMER0 76 | ||
| 95 | #define OCTEON_IRQ_TIMER1 77 | ||
| 96 | #define OCTEON_IRQ_TIMER2 78 | ||
| 97 | #define OCTEON_IRQ_TIMER3 79 | ||
| 98 | #define OCTEON_IRQ_USB0 80 | ||
| 99 | #define OCTEON_IRQ_PCM 81 | ||
| 100 | #define OCTEON_IRQ_MPI 82 | ||
| 101 | #define OCTEON_IRQ_TWSI2 83 | ||
| 102 | #define OCTEON_IRQ_POWIQ 84 | ||
| 103 | #define OCTEON_IRQ_IPDPPTHR 85 | ||
| 104 | #define OCTEON_IRQ_MII0 86 | ||
| 105 | #define OCTEON_IRQ_BOOTDMA 87 | ||
| 106 | /* 88 - 151 represent the sources in CIU_INTX_EN1 */ | ||
| 107 | #define OCTEON_IRQ_WDOG0 88 | ||
| 108 | #define OCTEON_IRQ_WDOG1 89 | ||
| 109 | #define OCTEON_IRQ_WDOG2 90 | ||
| 110 | #define OCTEON_IRQ_WDOG3 91 | ||
| 111 | #define OCTEON_IRQ_WDOG4 92 | ||
| 112 | #define OCTEON_IRQ_WDOG5 93 | ||
| 113 | #define OCTEON_IRQ_WDOG6 94 | ||
| 114 | #define OCTEON_IRQ_WDOG7 95 | ||
| 115 | #define OCTEON_IRQ_WDOG8 96 | ||
| 116 | #define OCTEON_IRQ_WDOG9 97 | ||
| 117 | #define OCTEON_IRQ_WDOG10 98 | ||
| 118 | #define OCTEON_IRQ_WDOG11 99 | ||
| 119 | #define OCTEON_IRQ_WDOG12 100 | ||
| 120 | #define OCTEON_IRQ_WDOG13 101 | ||
| 121 | #define OCTEON_IRQ_WDOG14 102 | ||
| 122 | #define OCTEON_IRQ_WDOG15 103 | ||
| 123 | #define OCTEON_IRQ_UART2 104 | ||
| 124 | #define OCTEON_IRQ_USB1 105 | ||
| 125 | #define OCTEON_IRQ_MII1 106 | ||
| 126 | #define OCTEON_IRQ_RESERVED107 107 | ||
| 127 | #define OCTEON_IRQ_RESERVED108 108 | ||
| 128 | #define OCTEON_IRQ_RESERVED109 109 | ||
| 129 | #define OCTEON_IRQ_RESERVED110 110 | ||
| 130 | #define OCTEON_IRQ_RESERVED111 111 | ||
| 131 | #define OCTEON_IRQ_RESERVED112 112 | ||
| 132 | #define OCTEON_IRQ_RESERVED113 113 | ||
| 133 | #define OCTEON_IRQ_RESERVED114 114 | ||
| 134 | #define OCTEON_IRQ_RESERVED115 115 | ||
| 135 | #define OCTEON_IRQ_RESERVED116 116 | ||
| 136 | #define OCTEON_IRQ_RESERVED117 117 | ||
| 137 | #define OCTEON_IRQ_RESERVED118 118 | ||
| 138 | #define OCTEON_IRQ_RESERVED119 119 | ||
| 139 | #define OCTEON_IRQ_RESERVED120 120 | ||
| 140 | #define OCTEON_IRQ_RESERVED121 121 | ||
| 141 | #define OCTEON_IRQ_RESERVED122 122 | ||
| 142 | #define OCTEON_IRQ_RESERVED123 123 | ||
| 143 | #define OCTEON_IRQ_RESERVED124 124 | ||
| 144 | #define OCTEON_IRQ_RESERVED125 125 | ||
| 145 | #define OCTEON_IRQ_RESERVED126 126 | ||
| 146 | #define OCTEON_IRQ_RESERVED127 127 | ||
| 147 | #define OCTEON_IRQ_RESERVED128 128 | ||
| 148 | #define OCTEON_IRQ_RESERVED129 129 | ||
| 149 | #define OCTEON_IRQ_RESERVED130 130 | ||
| 150 | #define OCTEON_IRQ_RESERVED131 131 | ||
| 151 | #define OCTEON_IRQ_RESERVED132 132 | ||
| 152 | #define OCTEON_IRQ_RESERVED133 133 | ||
| 153 | #define OCTEON_IRQ_RESERVED134 134 | ||
| 154 | #define OCTEON_IRQ_RESERVED135 135 | ||
| 155 | #define OCTEON_IRQ_RESERVED136 136 | ||
| 156 | #define OCTEON_IRQ_RESERVED137 137 | ||
| 157 | #define OCTEON_IRQ_RESERVED138 138 | ||
| 158 | #define OCTEON_IRQ_RESERVED139 139 | ||
| 159 | #define OCTEON_IRQ_RESERVED140 140 | ||
| 160 | #define OCTEON_IRQ_RESERVED141 141 | ||
| 161 | #define OCTEON_IRQ_RESERVED142 142 | ||
| 162 | #define OCTEON_IRQ_RESERVED143 143 | ||
| 163 | #define OCTEON_IRQ_RESERVED144 144 | ||
| 164 | #define OCTEON_IRQ_RESERVED145 145 | ||
| 165 | #define OCTEON_IRQ_RESERVED146 146 | ||
| 166 | #define OCTEON_IRQ_RESERVED147 147 | ||
| 167 | #define OCTEON_IRQ_RESERVED148 148 | ||
| 168 | #define OCTEON_IRQ_RESERVED149 149 | ||
| 169 | #define OCTEON_IRQ_RESERVED150 150 | ||
| 170 | #define OCTEON_IRQ_RESERVED151 151 | ||
| 171 | |||
| 172 | #ifdef CONFIG_PCI_MSI | ||
| 173 | /* 152 - 215 represent the MSI interrupts 0-63 */ | ||
| 174 | #define OCTEON_IRQ_MSI_BIT0 152 | ||
| 175 | #define OCTEON_IRQ_MSI_BIT1 153 | ||
| 176 | #define OCTEON_IRQ_MSI_BIT2 154 | ||
| 177 | #define OCTEON_IRQ_MSI_BIT3 155 | ||
| 178 | #define OCTEON_IRQ_MSI_BIT4 156 | ||
| 179 | #define OCTEON_IRQ_MSI_BIT5 157 | ||
| 180 | #define OCTEON_IRQ_MSI_BIT6 158 | ||
| 181 | #define OCTEON_IRQ_MSI_BIT7 159 | ||
| 182 | #define OCTEON_IRQ_MSI_BIT8 160 | ||
| 183 | #define OCTEON_IRQ_MSI_BIT9 161 | ||
| 184 | #define OCTEON_IRQ_MSI_BIT10 162 | ||
| 185 | #define OCTEON_IRQ_MSI_BIT11 163 | ||
| 186 | #define OCTEON_IRQ_MSI_BIT12 164 | ||
| 187 | #define OCTEON_IRQ_MSI_BIT13 165 | ||
| 188 | #define OCTEON_IRQ_MSI_BIT14 166 | ||
| 189 | #define OCTEON_IRQ_MSI_BIT15 167 | ||
| 190 | #define OCTEON_IRQ_MSI_BIT16 168 | ||
| 191 | #define OCTEON_IRQ_MSI_BIT17 169 | ||
| 192 | #define OCTEON_IRQ_MSI_BIT18 170 | ||
| 193 | #define OCTEON_IRQ_MSI_BIT19 171 | ||
| 194 | #define OCTEON_IRQ_MSI_BIT20 172 | ||
| 195 | #define OCTEON_IRQ_MSI_BIT21 173 | ||
| 196 | #define OCTEON_IRQ_MSI_BIT22 174 | ||
| 197 | #define OCTEON_IRQ_MSI_BIT23 175 | ||
| 198 | #define OCTEON_IRQ_MSI_BIT24 176 | ||
| 199 | #define OCTEON_IRQ_MSI_BIT25 177 | ||
| 200 | #define OCTEON_IRQ_MSI_BIT26 178 | ||
| 201 | #define OCTEON_IRQ_MSI_BIT27 179 | ||
| 202 | #define OCTEON_IRQ_MSI_BIT28 180 | ||
| 203 | #define OCTEON_IRQ_MSI_BIT29 181 | ||
| 204 | #define OCTEON_IRQ_MSI_BIT30 182 | ||
| 205 | #define OCTEON_IRQ_MSI_BIT31 183 | ||
| 206 | #define OCTEON_IRQ_MSI_BIT32 184 | ||
| 207 | #define OCTEON_IRQ_MSI_BIT33 185 | ||
| 208 | #define OCTEON_IRQ_MSI_BIT34 186 | ||
| 209 | #define OCTEON_IRQ_MSI_BIT35 187 | ||
| 210 | #define OCTEON_IRQ_MSI_BIT36 188 | ||
| 211 | #define OCTEON_IRQ_MSI_BIT37 189 | ||
| 212 | #define OCTEON_IRQ_MSI_BIT38 190 | ||
| 213 | #define OCTEON_IRQ_MSI_BIT39 191 | ||
| 214 | #define OCTEON_IRQ_MSI_BIT40 192 | ||
| 215 | #define OCTEON_IRQ_MSI_BIT41 193 | ||
| 216 | #define OCTEON_IRQ_MSI_BIT42 194 | ||
| 217 | #define OCTEON_IRQ_MSI_BIT43 195 | ||
| 218 | #define OCTEON_IRQ_MSI_BIT44 196 | ||
| 219 | #define OCTEON_IRQ_MSI_BIT45 197 | ||
| 220 | #define OCTEON_IRQ_MSI_BIT46 198 | ||
| 221 | #define OCTEON_IRQ_MSI_BIT47 199 | ||
| 222 | #define OCTEON_IRQ_MSI_BIT48 200 | ||
| 223 | #define OCTEON_IRQ_MSI_BIT49 201 | ||
| 224 | #define OCTEON_IRQ_MSI_BIT50 202 | ||
| 225 | #define OCTEON_IRQ_MSI_BIT51 203 | ||
| 226 | #define OCTEON_IRQ_MSI_BIT52 204 | ||
| 227 | #define OCTEON_IRQ_MSI_BIT53 205 | ||
| 228 | #define OCTEON_IRQ_MSI_BIT54 206 | ||
| 229 | #define OCTEON_IRQ_MSI_BIT55 207 | ||
| 230 | #define OCTEON_IRQ_MSI_BIT56 208 | ||
| 231 | #define OCTEON_IRQ_MSI_BIT57 209 | ||
| 232 | #define OCTEON_IRQ_MSI_BIT58 210 | ||
| 233 | #define OCTEON_IRQ_MSI_BIT59 211 | ||
| 234 | #define OCTEON_IRQ_MSI_BIT60 212 | ||
| 235 | #define OCTEON_IRQ_MSI_BIT61 213 | ||
| 236 | #define OCTEON_IRQ_MSI_BIT62 214 | ||
| 237 | #define OCTEON_IRQ_MSI_BIT63 215 | ||
| 238 | |||
| 239 | #define OCTEON_IRQ_LAST 216 | ||
| 240 | #else | ||
| 241 | #define OCTEON_IRQ_LAST 152 | ||
| 242 | #endif | ||
| 243 | |||
| 244 | #endif | ||
diff --git a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h new file mode 100644 index 000000000000..0b2b5eb22e9b --- /dev/null +++ b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h | |||
| @@ -0,0 +1,131 @@ | |||
| 1 | /* | ||
| 2 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 3 | * License. See the file "COPYING" in the main directory of this archive | ||
| 4 | * for more details. | ||
| 5 | * | ||
| 6 | * Copyright (C) 2005-2008 Cavium Networks, Inc | ||
| 7 | */ | ||
| 8 | #ifndef __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H | ||
| 9 | #define __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H | ||
| 10 | |||
| 11 | |||
| 12 | #define CP0_CYCLE_COUNTER $9, 6 | ||
| 13 | #define CP0_CVMCTL_REG $9, 7 | ||
| 14 | #define CP0_CVMMEMCTL_REG $11,7 | ||
| 15 | #define CP0_PRID_REG $15, 0 | ||
| 16 | #define CP0_PRID_OCTEON_PASS1 0x000d0000 | ||
| 17 | #define CP0_PRID_OCTEON_CN30XX 0x000d0200 | ||
| 18 | |||
| 19 | .macro kernel_entry_setup | ||
| 20 | # Registers set by bootloader: | ||
| 21 | # (only 32 bits set by bootloader, all addresses are physical | ||
| 22 | # addresses, and need to have the appropriate memory region set | ||
| 23 | # by the kernel | ||
| 24 | # a0 = argc | ||
| 25 | # a1 = argv (kseg0 compat addr) | ||
| 26 | # a2 = 1 if init core, zero otherwise | ||
| 27 | # a3 = address of boot descriptor block | ||
| 28 | .set push | ||
| 29 | .set arch=octeon | ||
| 30 | # Read the cavium mem control register | ||
| 31 | dmfc0 v0, CP0_CVMMEMCTL_REG | ||
| 32 | # Clear the lower 6 bits, the CVMSEG size | ||
| 33 | dins v0, $0, 0, 6 | ||
| 34 | ori v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE | ||
| 35 | dmtc0 v0, CP0_CVMMEMCTL_REG # Write the cavium mem control register | ||
| 36 | dmfc0 v0, CP0_CVMCTL_REG # Read the cavium control register | ||
| 37 | #ifdef CONFIG_CAVIUM_OCTEON_HW_FIX_UNALIGNED | ||
| 38 | # Disable unaligned load/store support but leave HW fixup enabled | ||
| 39 | or v0, v0, 0x5001 | ||
| 40 | xor v0, v0, 0x1001 | ||
| 41 | #else | ||
| 42 | # Disable unaligned load/store and HW fixup support | ||
| 43 | or v0, v0, 0x5001 | ||
| 44 | xor v0, v0, 0x5001 | ||
| 45 | #endif | ||
| 46 | # Read the processor ID register | ||
| 47 | mfc0 v1, CP0_PRID_REG | ||
| 48 | # Disable instruction prefetching (Octeon Pass1 errata) | ||
| 49 | or v0, v0, 0x2000 | ||
| 50 | # Skip reenable of prefetching for Octeon Pass1 | ||
| 51 | beq v1, CP0_PRID_OCTEON_PASS1, skip | ||
| 52 | nop | ||
| 53 | # Reenable instruction prefetching, not on Pass1 | ||
| 54 | xor v0, v0, 0x2000 | ||
| 55 | # Strip off pass number off of processor id | ||
| 56 | srl v1, 8 | ||
| 57 | sll v1, 8 | ||
| 58 | # CN30XX needs some extra stuff turned off for better performance | ||
| 59 | bne v1, CP0_PRID_OCTEON_CN30XX, skip | ||
| 60 | nop | ||
| 61 | # CN30XX Use random Icache replacement | ||
| 62 | or v0, v0, 0x400 | ||
| 63 | # CN30XX Disable instruction prefetching | ||
| 64 | or v0, v0, 0x2000 | ||
| 65 | skip: | ||
| 66 | # Write the cavium control register | ||
| 67 | dmtc0 v0, CP0_CVMCTL_REG | ||
| 68 | sync | ||
| 69 | # Flush dcache after config change | ||
| 70 | cache 9, 0($0) | ||
| 71 | # Get my core id | ||
| 72 | rdhwr v0, $0 | ||
| 73 | # Jump the master to kernel_entry | ||
| 74 | bne a2, zero, octeon_main_processor | ||
| 75 | nop | ||
| 76 | |||
| 77 | #ifdef CONFIG_SMP | ||
| 78 | |||
| 79 | # | ||
| 80 | # All cores other than the master need to wait here for SMP bootstrap | ||
| 81 | # to begin | ||
| 82 | # | ||
| 83 | |||
| 84 | # This is the variable where the next core to boot os stored | ||
| 85 | PTR_LA t0, octeon_processor_boot | ||
| 86 | octeon_spin_wait_boot: | ||
| 87 | # Get the core id of the next to be booted | ||
| 88 | LONG_L t1, (t0) | ||
| 89 | # Keep looping if it isn't me | ||
| 90 | bne t1, v0, octeon_spin_wait_boot | ||
| 91 | nop | ||
| 92 | # Get my GP from the global variable | ||
| 93 | PTR_LA t0, octeon_processor_gp | ||
| 94 | LONG_L gp, (t0) | ||
| 95 | # Get my SP from the global variable | ||
| 96 | PTR_LA t0, octeon_processor_sp | ||
| 97 | LONG_L sp, (t0) | ||
| 98 | # Set the SP global variable to zero so the master knows we've started | ||
| 99 | LONG_S zero, (t0) | ||
| 100 | #ifdef __OCTEON__ | ||
| 101 | syncw | ||
| 102 | syncw | ||
| 103 | #else | ||
| 104 | sync | ||
| 105 | #endif | ||
| 106 | # Jump to the normal Linux SMP entry point | ||
| 107 | j smp_bootstrap | ||
| 108 | nop | ||
| 109 | #else /* CONFIG_SMP */ | ||
| 110 | |||
| 111 | # | ||
| 112 | # Someone tried to boot SMP with a non SMP kernel. All extra cores | ||
| 113 | # will halt here. | ||
| 114 | # | ||
| 115 | octeon_wait_forever: | ||
| 116 | wait | ||
| 117 | b octeon_wait_forever | ||
| 118 | nop | ||
| 119 | |||
| 120 | #endif /* CONFIG_SMP */ | ||
| 121 | octeon_main_processor: | ||
| 122 | .set pop | ||
| 123 | .endm | ||
| 124 | |||
| 125 | /* | ||
| 126 | * Do SMP slave processor setup necessary before we can savely execute C code. | ||
| 127 | */ | ||
| 128 | .macro smp_slave_setup | ||
| 129 | .endm | ||
| 130 | |||
| 131 | #endif /* __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H */ | ||
diff --git a/arch/mips/include/asm/mach-cavium-octeon/war.h b/arch/mips/include/asm/mach-cavium-octeon/war.h new file mode 100644 index 000000000000..c4712d7cc81d --- /dev/null +++ b/arch/mips/include/asm/mach-cavium-octeon/war.h | |||
| @@ -0,0 +1,26 @@ | |||
| 1 | /* | ||
| 2 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 3 | * License. See the file "COPYING" in the main directory of this archive | ||
| 4 | * for more details. | ||
| 5 | * | ||
| 6 | * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> | ||
| 7 | * Copyright (C) 2008 Cavium Networks <support@caviumnetworks.com> | ||
| 8 | */ | ||
| 9 | #ifndef __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H | ||
| 10 | #define __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H | ||
| 11 | |||
| 12 | #define R4600_V1_INDEX_ICACHEOP_WAR 0 | ||
| 13 | #define R4600_V1_HIT_CACHEOP_WAR 0 | ||
| 14 | #define R4600_V2_HIT_CACHEOP_WAR 0 | ||
| 15 | #define R5432_CP0_INTERRUPT_WAR 0 | ||
| 16 | #define BCM1250_M3_WAR 0 | ||
| 17 | #define SIBYTE_1956_WAR 0 | ||
| 18 | #define MIPS4K_ICACHE_REFILL_WAR 0 | ||
| 19 | #define MIPS_CACHE_SYNC_WAR 0 | ||
| 20 | #define TX49XX_ICACHE_INDEX_INV_WAR 0 | ||
| 21 | #define RM9000_CDEX_SMP_WAR 0 | ||
| 22 | #define ICACHE_REFILLS_WORKAROUND_WAR 0 | ||
| 23 | #define R10000_LLSC_WAR 0 | ||
| 24 | #define MIPS34K_MISSED_ITLB_WAR 0 | ||
| 25 | |||
| 26 | #endif /* __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H */ | ||
diff --git a/arch/mips/include/asm/mach-generic/dma-coherence.h b/arch/mips/include/asm/mach-generic/dma-coherence.h index 76e04e7feb84..36c611b6c597 100644 --- a/arch/mips/include/asm/mach-generic/dma-coherence.h +++ b/arch/mips/include/asm/mach-generic/dma-coherence.h | |||
| @@ -28,10 +28,34 @@ static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) | |||
| 28 | return dma_addr; | 28 | return dma_addr; |
| 29 | } | 29 | } |
| 30 | 30 | ||
| 31 | static inline void plat_unmap_dma_mem(dma_addr_t dma_addr) | 31 | static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr) |
| 32 | { | 32 | { |
| 33 | } | 33 | } |
| 34 | 34 | ||
| 35 | static inline int plat_dma_supported(struct device *dev, u64 mask) | ||
| 36 | { | ||
| 37 | /* | ||
| 38 | * we fall back to GFP_DMA when the mask isn't all 1s, | ||
| 39 | * so we can't guarantee allocations that must be | ||
| 40 | * within a tighter range than GFP_DMA.. | ||
| 41 | */ | ||
| 42 | if (mask < DMA_BIT_MASK(24)) | ||
| 43 | return 0; | ||
| 44 | |||
| 45 | return 1; | ||
| 46 | } | ||
| 47 | |||
| 48 | static inline void plat_extra_sync_for_device(struct device *dev) | ||
| 49 | { | ||
| 50 | return; | ||
| 51 | } | ||
| 52 | |||
| 53 | static inline int plat_dma_mapping_error(struct device *dev, | ||
| 54 | dma_addr_t dma_addr) | ||
| 55 | { | ||
| 56 | return 0; | ||
| 57 | } | ||
| 58 | |||
| 35 | static inline int plat_device_is_coherent(struct device *dev) | 59 | static inline int plat_device_is_coherent(struct device *dev) |
| 36 | { | 60 | { |
| 37 | #ifdef CONFIG_DMA_COHERENT | 61 | #ifdef CONFIG_DMA_COHERENT |
diff --git a/arch/mips/include/asm/mach-ip27/dma-coherence.h b/arch/mips/include/asm/mach-ip27/dma-coherence.h index ed7e6222dc15..4c21bfca10c3 100644 --- a/arch/mips/include/asm/mach-ip27/dma-coherence.h +++ b/arch/mips/include/asm/mach-ip27/dma-coherence.h | |||
| @@ -38,10 +38,34 @@ static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) | |||
| 38 | return dma_addr & ~(0xffUL << 56); | 38 | return dma_addr & ~(0xffUL << 56); |
| 39 | } | 39 | } |
| 40 | 40 | ||
| 41 | static inline void plat_unmap_dma_mem(dma_addr_t dma_addr) | 41 | static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr) |
| 42 | { | 42 | { |
| 43 | } | 43 | } |
| 44 | 44 | ||
| 45 | static inline int plat_dma_supported(struct device *dev, u64 mask) | ||
| 46 | { | ||
| 47 | /* | ||
| 48 | * we fall back to GFP_DMA when the mask isn't all 1s, | ||
| 49 | * so we can't guarantee allocations that must be | ||
| 50 | * within a tighter range than GFP_DMA.. | ||
| 51 | */ | ||
| 52 | if (mask < DMA_BIT_MASK(24)) | ||
| 53 | return 0; | ||
| 54 | |||
| 55 | return 1; | ||
| 56 | } | ||
| 57 | |||
| 58 | static inline void plat_extra_sync_for_device(struct device *dev) | ||
| 59 | { | ||
| 60 | return; | ||
| 61 | } | ||
| 62 | |||
| 63 | static inline int plat_dma_mapping_error(struct device *dev, | ||
| 64 | dma_addr_t dma_addr) | ||
| 65 | { | ||
| 66 | return 0; | ||
| 67 | } | ||
| 68 | |||
| 45 | static inline int plat_device_is_coherent(struct device *dev) | 69 | static inline int plat_device_is_coherent(struct device *dev) |
| 46 | { | 70 | { |
| 47 | return 1; /* IP27 non-cohernet mode is unsupported */ | 71 | return 1; /* IP27 non-cohernet mode is unsupported */ |
diff --git a/arch/mips/include/asm/mach-ip32/dma-coherence.h b/arch/mips/include/asm/mach-ip32/dma-coherence.h index a5511ebb2d53..7ae40f4b1c80 100644 --- a/arch/mips/include/asm/mach-ip32/dma-coherence.h +++ b/arch/mips/include/asm/mach-ip32/dma-coherence.h | |||
| @@ -60,10 +60,34 @@ static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) | |||
| 60 | return addr; | 60 | return addr; |
| 61 | } | 61 | } |
| 62 | 62 | ||
| 63 | static inline void plat_unmap_dma_mem(dma_addr_t dma_addr) | 63 | static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr) |
| 64 | { | 64 | { |
| 65 | } | 65 | } |
| 66 | 66 | ||
| 67 | static inline int plat_dma_supported(struct device *dev, u64 mask) | ||
| 68 | { | ||
| 69 | /* | ||
| 70 | * we fall back to GFP_DMA when the mask isn't all 1s, | ||
| 71 | * so we can't guarantee allocations that must be | ||
| 72 | * within a tighter range than GFP_DMA.. | ||
| 73 | */ | ||
| 74 | if (mask < DMA_BIT_MASK(24)) | ||
| 75 | return 0; | ||
| 76 | |||
| 77 | return 1; | ||
| 78 | } | ||
| 79 | |||
| 80 | static inline void plat_extra_sync_for_device(struct device *dev) | ||
| 81 | { | ||
| 82 | return; | ||
| 83 | } | ||
| 84 | |||
| 85 | static inline int plat_dma_mapping_error(struct device *dev, | ||
| 86 | dma_addr_t dma_addr) | ||
| 87 | { | ||
| 88 | return 0; | ||
| 89 | } | ||
| 90 | |||
| 67 | static inline int plat_device_is_coherent(struct device *dev) | 91 | static inline int plat_device_is_coherent(struct device *dev) |
| 68 | { | 92 | { |
| 69 | return 0; /* IP32 is non-cohernet */ | 93 | return 0; /* IP32 is non-cohernet */ |
diff --git a/arch/mips/include/asm/mach-jazz/dma-coherence.h b/arch/mips/include/asm/mach-jazz/dma-coherence.h index d66979a124a8..1c7cd27efa7b 100644 --- a/arch/mips/include/asm/mach-jazz/dma-coherence.h +++ b/arch/mips/include/asm/mach-jazz/dma-coherence.h | |||
| @@ -27,11 +27,35 @@ static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) | |||
| 27 | return vdma_log2phys(dma_addr); | 27 | return vdma_log2phys(dma_addr); |
| 28 | } | 28 | } |
| 29 | 29 | ||
| 30 | static void plat_unmap_dma_mem(dma_addr_t dma_addr) | 30 | static void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr) |
| 31 | { | 31 | { |
| 32 | vdma_free(dma_addr); | 32 | vdma_free(dma_addr); |
| 33 | } | 33 | } |
| 34 | 34 | ||
| 35 | static inline int plat_dma_supported(struct device *dev, u64 mask) | ||
| 36 | { | ||
| 37 | /* | ||
| 38 | * we fall back to GFP_DMA when the mask isn't all 1s, | ||
| 39 | * so we can't guarantee allocations that must be | ||
| 40 | * within a tighter range than GFP_DMA.. | ||
| 41 | */ | ||
| 42 | if (mask < DMA_BIT_MASK(24)) | ||
| 43 | return 0; | ||
| 44 | |||
| 45 | return 1; | ||
| 46 | } | ||
| 47 | |||
| 48 | static inline void plat_extra_sync_for_device(struct device *dev) | ||
| 49 | { | ||
| 50 | return; | ||
| 51 | } | ||
| 52 | |||
| 53 | static inline int plat_dma_mapping_error(struct device *dev, | ||
| 54 | dma_addr_t dma_addr) | ||
| 55 | { | ||
| 56 | return 0; | ||
| 57 | } | ||
| 58 | |||
| 35 | static inline int plat_device_is_coherent(struct device *dev) | 59 | static inline int plat_device_is_coherent(struct device *dev) |
| 36 | { | 60 | { |
| 37 | return 0; | 61 | return 0; |
diff --git a/arch/mips/include/asm/mach-lemote/dma-coherence.h b/arch/mips/include/asm/mach-lemote/dma-coherence.h index 7e914777ebc4..38fad7dfe7da 100644 --- a/arch/mips/include/asm/mach-lemote/dma-coherence.h +++ b/arch/mips/include/asm/mach-lemote/dma-coherence.h | |||
| @@ -30,10 +30,34 @@ static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) | |||
| 30 | return dma_addr & 0x7fffffff; | 30 | return dma_addr & 0x7fffffff; |
| 31 | } | 31 | } |
| 32 | 32 | ||
| 33 | static inline void plat_unmap_dma_mem(dma_addr_t dma_addr) | 33 | static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr) |
| 34 | { | 34 | { |
| 35 | } | 35 | } |
| 36 | 36 | ||
| 37 | static inline int plat_dma_supported(struct device *dev, u64 mask) | ||
| 38 | { | ||
| 39 | /* | ||
| 40 | * we fall back to GFP_DMA when the mask isn't all 1s, | ||
| 41 | * so we can't guarantee allocations that must be | ||
| 42 | * within a tighter range than GFP_DMA.. | ||
| 43 | */ | ||
| 44 | if (mask < DMA_BIT_MASK(24)) | ||
| 45 | return 0; | ||
| 46 | |||
| 47 | return 1; | ||
| 48 | } | ||
| 49 | |||
| 50 | static inline void plat_extra_sync_for_device(struct device *dev) | ||
| 51 | { | ||
| 52 | return; | ||
| 53 | } | ||
| 54 | |||
| 55 | static inline int plat_dma_mapping_error(struct device *dev, | ||
| 56 | dma_addr_t dma_addr) | ||
| 57 | { | ||
| 58 | return 0; | ||
| 59 | } | ||
| 60 | |||
| 37 | static inline int plat_device_is_coherent(struct device *dev) | 61 | static inline int plat_device_is_coherent(struct device *dev) |
| 38 | { | 62 | { |
| 39 | return 0; | 63 | return 0; |
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 9316324d070d..0417516503f6 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h | |||
| @@ -1000,6 +1000,26 @@ do { \ | |||
| 1000 | #define read_c0_ebase() __read_32bit_c0_register($15, 1) | 1000 | #define read_c0_ebase() __read_32bit_c0_register($15, 1) |
| 1001 | #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) | 1001 | #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) |
| 1002 | 1002 | ||
| 1003 | |||
| 1004 | /* Cavium OCTEON (cnMIPS) */ | ||
| 1005 | #define read_c0_cvmcount() __read_ulong_c0_register($9, 6) | ||
| 1006 | #define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val) | ||
| 1007 | |||
| 1008 | #define read_c0_cvmctl() __read_64bit_c0_register($9, 7) | ||
| 1009 | #define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val) | ||
| 1010 | |||
| 1011 | #define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7) | ||
| 1012 | #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val) | ||
| 1013 | /* | ||
| 1014 | * The cacheerr registers are not standardized. On OCTEON, they are | ||
| 1015 | * 64 bits wide. | ||
| 1016 | */ | ||
| 1017 | #define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0) | ||
| 1018 | #define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val) | ||
| 1019 | |||
| 1020 | #define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1) | ||
| 1021 | #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val) | ||
| 1022 | |||
| 1003 | /* | 1023 | /* |
| 1004 | * Macros to access the floating point coprocessor control registers | 1024 | * Macros to access the floating point coprocessor control registers |
| 1005 | */ | 1025 | */ |
| @@ -1008,6 +1028,8 @@ do { \ | |||
| 1008 | __asm__ __volatile__( \ | 1028 | __asm__ __volatile__( \ |
| 1009 | ".set\tpush\n\t" \ | 1029 | ".set\tpush\n\t" \ |
| 1010 | ".set\treorder\n\t" \ | 1030 | ".set\treorder\n\t" \ |
| 1031 | /* gas fails to assemble cfc1 for some archs (octeon).*/ \ | ||
| 1032 | ".set\tmips1\n\t" \ | ||
| 1011 | "cfc1\t%0,"STR(source)"\n\t" \ | 1033 | "cfc1\t%0,"STR(source)"\n\t" \ |
| 1012 | ".set\tpop" \ | 1034 | ".set\tpop" \ |
| 1013 | : "=r" (__res)); \ | 1035 | : "=r" (__res)); \ |
diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h index e2e09b2cd265..d94085a3eafb 100644 --- a/arch/mips/include/asm/module.h +++ b/arch/mips/include/asm/module.h | |||
| @@ -116,6 +116,8 @@ search_module_dbetables(unsigned long addr) | |||
| 116 | #define MODULE_PROC_FAMILY "SB1 " | 116 | #define MODULE_PROC_FAMILY "SB1 " |
| 117 | #elif defined CONFIG_CPU_LOONGSON2 | 117 | #elif defined CONFIG_CPU_LOONGSON2 |
| 118 | #define MODULE_PROC_FAMILY "LOONGSON2 " | 118 | #define MODULE_PROC_FAMILY "LOONGSON2 " |
| 119 | #elif defined CONFIG_CPU_CAVIUM_OCTEON | ||
| 120 | #define MODULE_PROC_FAMILY "OCTEON " | ||
| 119 | #else | 121 | #else |
| 120 | #error MODULE_PROC_FAMILY undefined for your processor configuration | 122 | #error MODULE_PROC_FAMILY undefined for your processor configuration |
| 121 | #endif | 123 | #endif |
diff --git a/arch/mips/include/asm/octeon/cvmx-asm.h b/arch/mips/include/asm/octeon/cvmx-asm.h new file mode 100644 index 000000000000..b21d3fc1ef91 --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-asm.h | |||
| @@ -0,0 +1,128 @@ | |||
| 1 | /***********************license start*************** | ||
| 2 | * Author: Cavium Networks | ||
| 3 | * | ||
| 4 | * Contact: support@caviumnetworks.com | ||
| 5 | * This file is part of the OCTEON SDK | ||
| 6 | * | ||
| 7 | * Copyright (c) 2003-2008 Cavium Networks | ||
| 8 | * | ||
| 9 | * This file is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License, Version 2, as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | * | ||
| 13 | * This file is distributed in the hope that it will be useful, but | ||
| 14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
| 15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
| 16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
| 17 | * details. | ||
| 18 | * | ||
| 19 | * You should have received a copy of the GNU General Public License | ||
| 20 | * along with this file; if not, write to the Free Software | ||
| 21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 22 | * or visit http://www.gnu.org/licenses/. | ||
| 23 | * | ||
| 24 | * This file may also be available under a different license from Cavium. | ||
| 25 | * Contact Cavium Networks for more information | ||
| 26 | ***********************license end**************************************/ | ||
| 27 | |||
| 28 | /* | ||
| 29 | * | ||
| 30 | * This is file defines ASM primitives for the executive. | ||
| 31 | */ | ||
| 32 | #ifndef __CVMX_ASM_H__ | ||
| 33 | #define __CVMX_ASM_H__ | ||
| 34 | |||
| 35 | #include "octeon-model.h" | ||
| 36 | |||
| 37 | /* other useful stuff */ | ||
| 38 | #define CVMX_SYNC asm volatile ("sync" : : : "memory") | ||
| 39 | /* String version of SYNCW macro for using in inline asm constructs */ | ||
| 40 | #define CVMX_SYNCW_STR "syncw\nsyncw\n" | ||
| 41 | #ifdef __OCTEON__ | ||
| 42 | |||
| 43 | /* Deprecated, will be removed in future release */ | ||
| 44 | #define CVMX_SYNCIO asm volatile ("nop") | ||
| 45 | |||
| 46 | #define CVMX_SYNCIOBDMA asm volatile ("synciobdma" : : : "memory") | ||
| 47 | |||
| 48 | /* Deprecated, will be removed in future release */ | ||
| 49 | #define CVMX_SYNCIOALL asm volatile ("nop") | ||
| 50 | |||
| 51 | /* | ||
| 52 | * We actually use two syncw instructions in a row when we need a write | ||
| 53 | * memory barrier. This is because the CN3XXX series of Octeons have | ||
| 54 | * errata Core-401. This can cause a single syncw to not enforce | ||
| 55 | * ordering under very rare conditions. Even if it is rare, better safe | ||
| 56 | * than sorry. | ||
| 57 | */ | ||
| 58 | #define CVMX_SYNCW asm volatile ("syncw\n\tsyncw" : : : "memory") | ||
| 59 | |||
| 60 | /* | ||
| 61 | * Define new sync instructions to be normal SYNC instructions for | ||
| 62 | * operating systems that use threads. | ||
| 63 | */ | ||
| 64 | #define CVMX_SYNCWS CVMX_SYNCW | ||
| 65 | #define CVMX_SYNCS CVMX_SYNC | ||
| 66 | #define CVMX_SYNCWS_STR CVMX_SYNCW_STR | ||
| 67 | #else | ||
| 68 | /* | ||
| 69 | * Not using a Cavium compiler, always use the slower sync so the | ||
| 70 | * assembler stays happy. | ||
| 71 | */ | ||
| 72 | /* Deprecated, will be removed in future release */ | ||
| 73 | #define CVMX_SYNCIO asm volatile ("nop") | ||
| 74 | |||
| 75 | #define CVMX_SYNCIOBDMA asm volatile ("sync" : : : "memory") | ||
| 76 | |||
| 77 | /* Deprecated, will be removed in future release */ | ||
| 78 | #define CVMX_SYNCIOALL asm volatile ("nop") | ||
| 79 | |||
| 80 | #define CVMX_SYNCW asm volatile ("sync" : : : "memory") | ||
| 81 | #define CVMX_SYNCWS CVMX_SYNCW | ||
| 82 | #define CVMX_SYNCS CVMX_SYNC | ||
| 83 | #define CVMX_SYNCWS_STR CVMX_SYNCW_STR | ||
| 84 | #endif | ||
| 85 | |||
| 86 | /* | ||
| 87 | * CVMX_PREPARE_FOR_STORE makes each byte of the block unpredictable | ||
| 88 | * (actually old value or zero) until that byte is stored to (by this or | ||
| 89 | * another processor. Note that the value of each byte is not only | ||
| 90 | * unpredictable, but may also change again - up until the point when one | ||
| 91 | * of the cores stores to the byte. | ||
| 92 | */ | ||
| 93 | #define CVMX_PREPARE_FOR_STORE(address, offset) \ | ||
| 94 | asm volatile ("pref 30, " CVMX_TMP_STR(offset) "(%[rbase])" : : \ | ||
| 95 | [rbase] "d" (address)) | ||
| 96 | /* | ||
| 97 | * This is a command headed to the L2 controller to tell it to clear | ||
| 98 | * its dirty bit for a block. Basically, SW is telling HW that the | ||
| 99 | * current version of the block will not be used. | ||
| 100 | */ | ||
| 101 | #define CVMX_DONT_WRITE_BACK(address, offset) \ | ||
| 102 | asm volatile ("pref 29, " CVMX_TMP_STR(offset) "(%[rbase])" : : \ | ||
| 103 | [rbase] "d" (address)) | ||
| 104 | |||
| 105 | /* flush stores, invalidate entire icache */ | ||
| 106 | #define CVMX_ICACHE_INVALIDATE \ | ||
| 107 | { CVMX_SYNC; asm volatile ("synci 0($0)" : : ); } | ||
| 108 | |||
| 109 | /* flush stores, invalidate entire icache */ | ||
| 110 | #define CVMX_ICACHE_INVALIDATE2 \ | ||
| 111 | { CVMX_SYNC; asm volatile ("cache 0, 0($0)" : : ); } | ||
| 112 | |||
| 113 | /* complete prefetches, invalidate entire dcache */ | ||
| 114 | #define CVMX_DCACHE_INVALIDATE \ | ||
| 115 | { CVMX_SYNC; asm volatile ("cache 9, 0($0)" : : ); } | ||
| 116 | |||
| 117 | |||
| 118 | #define CVMX_POP(result, input) \ | ||
| 119 | asm ("pop %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input)) | ||
| 120 | #define CVMX_DPOP(result, input) \ | ||
| 121 | asm ("dpop %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input)) | ||
| 122 | |||
| 123 | /* some new cop0-like stuff */ | ||
| 124 | #define CVMX_RDHWR(result, regstr) \ | ||
| 125 | asm volatile ("rdhwr %[rt],$" CVMX_TMP_STR(regstr) : [rt] "=d" (result)) | ||
| 126 | #define CVMX_RDHWRNV(result, regstr) \ | ||
| 127 | asm ("rdhwr %[rt],$" CVMX_TMP_STR(regstr) : [rt] "=d" (result)) | ||
| 128 | #endif /* __CVMX_ASM_H__ */ | ||
diff --git a/arch/mips/include/asm/octeon/cvmx-bootinfo.h b/arch/mips/include/asm/octeon/cvmx-bootinfo.h new file mode 100644 index 000000000000..692989acd8a9 --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h | |||
| @@ -0,0 +1,262 @@ | |||
| 1 | /***********************license start*************** | ||
| 2 | * Author: Cavium Networks | ||
| 3 | * | ||
| 4 | * Contact: support@caviumnetworks.com | ||
| 5 | * This file is part of the OCTEON SDK | ||
| 6 | * | ||
| 7 | * Copyright (c) 2003-2008 Cavium Networks | ||
| 8 | * | ||
| 9 | * This file is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License, Version 2, as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | * | ||
| 13 | * This file is distributed in the hope that it will be useful, but | ||
| 14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
| 15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
| 16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
| 17 | * details. | ||
| 18 | * | ||
| 19 | * You should have received a copy of the GNU General Public License | ||
| 20 | * along with this file; if not, write to the Free Software | ||
| 21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 22 | * or visit http://www.gnu.org/licenses/. | ||
| 23 | * | ||
| 24 | * This file may also be available under a different license from Cavium. | ||
| 25 | * Contact Cavium Networks for more information | ||
| 26 | ***********************license end**************************************/ | ||
| 27 | |||
| 28 | /* | ||
| 29 | * Header file containing the ABI with the bootloader. | ||
| 30 | */ | ||
| 31 | |||
| 32 | #ifndef __CVMX_BOOTINFO_H__ | ||
| 33 | #define __CVMX_BOOTINFO_H__ | ||
| 34 | |||
| 35 | /* | ||
| 36 | * Current major and minor versions of the CVMX bootinfo block that is | ||
| 37 | * passed from the bootloader to the application. This is versioned | ||
| 38 | * so that applications can properly handle multiple bootloader | ||
| 39 | * versions. | ||
| 40 | */ | ||
| 41 | #define CVMX_BOOTINFO_MAJ_VER 1 | ||
| 42 | #define CVMX_BOOTINFO_MIN_VER 2 | ||
| 43 | |||
| 44 | #if (CVMX_BOOTINFO_MAJ_VER == 1) | ||
| 45 | #define CVMX_BOOTINFO_OCTEON_SERIAL_LEN 20 | ||
| 46 | /* | ||
| 47 | * This structure is populated by the bootloader. For binary | ||
| 48 | * compatibility the only changes that should be made are | ||
| 49 | * adding members to the end of the structure, and the minor | ||
| 50 | * version should be incremented at that time. | ||
| 51 | * If an incompatible change is made, the major version | ||
| 52 | * must be incremented, and the minor version should be reset | ||
| 53 | * to 0. | ||
| 54 | */ | ||
| 55 | struct cvmx_bootinfo { | ||
| 56 | uint32_t major_version; | ||
| 57 | uint32_t minor_version; | ||
| 58 | |||
| 59 | uint64_t stack_top; | ||
| 60 | uint64_t heap_base; | ||
| 61 | uint64_t heap_end; | ||
| 62 | uint64_t desc_vaddr; | ||
| 63 | |||
| 64 | uint32_t exception_base_addr; | ||
| 65 | uint32_t stack_size; | ||
| 66 | uint32_t flags; | ||
| 67 | uint32_t core_mask; | ||
| 68 | /* DRAM size in megabytes */ | ||
| 69 | uint32_t dram_size; | ||
| 70 | /* physical address of free memory descriptor block*/ | ||
| 71 | uint32_t phy_mem_desc_addr; | ||
| 72 | /* used to pass flags from app to debugger */ | ||
| 73 | uint32_t debugger_flags_base_addr; | ||
| 74 | |||
| 75 | /* CPU clock speed, in hz */ | ||
| 76 | uint32_t eclock_hz; | ||
| 77 | |||
| 78 | /* DRAM clock speed, in hz */ | ||
| 79 | uint32_t dclock_hz; | ||
| 80 | |||
| 81 | uint32_t reserved0; | ||
| 82 | uint16_t board_type; | ||
| 83 | uint8_t board_rev_major; | ||
| 84 | uint8_t board_rev_minor; | ||
| 85 | uint16_t reserved1; | ||
| 86 | uint8_t reserved2; | ||
| 87 | uint8_t reserved3; | ||
| 88 | char board_serial_number[CVMX_BOOTINFO_OCTEON_SERIAL_LEN]; | ||
| 89 | uint8_t mac_addr_base[6]; | ||
| 90 | uint8_t mac_addr_count; | ||
| 91 | #if (CVMX_BOOTINFO_MIN_VER >= 1) | ||
| 92 | /* | ||
| 93 | * Several boards support compact flash on the Octeon boot | ||
| 94 | * bus. The CF memory spaces may be mapped to different | ||
| 95 | * addresses on different boards. These are the physical | ||
| 96 | * addresses, so care must be taken to use the correct | ||
| 97 | * XKPHYS/KSEG0 addressing depending on the application's | ||
| 98 | * ABI. These values will be 0 if CF is not present. | ||
| 99 | */ | ||
| 100 | uint64_t compact_flash_common_base_addr; | ||
| 101 | uint64_t compact_flash_attribute_base_addr; | ||
| 102 | /* | ||
| 103 | * Base address of the LED display (as on EBT3000 board) | ||
| 104 | * This will be 0 if LED display not present. | ||
| 105 | */ | ||
| 106 | uint64_t led_display_base_addr; | ||
| 107 | #endif | ||
| 108 | #if (CVMX_BOOTINFO_MIN_VER >= 2) | ||
| 109 | /* DFA reference clock in hz (if applicable)*/ | ||
| 110 | uint32_t dfa_ref_clock_hz; | ||
| 111 | |||
| 112 | /* | ||
| 113 | * flags indicating various configuration options. These | ||
| 114 | * flags supercede the 'flags' variable and should be used | ||
| 115 | * instead if available. | ||
| 116 | */ | ||
| 117 | uint32_t config_flags; | ||
| 118 | #endif | ||
| 119 | |||
| 120 | }; | ||
| 121 | |||
| 122 | #define CVMX_BOOTINFO_CFG_FLAG_PCI_HOST (1ull << 0) | ||
| 123 | #define CVMX_BOOTINFO_CFG_FLAG_PCI_TARGET (1ull << 1) | ||
| 124 | #define CVMX_BOOTINFO_CFG_FLAG_DEBUG (1ull << 2) | ||
| 125 | #define CVMX_BOOTINFO_CFG_FLAG_NO_MAGIC (1ull << 3) | ||
| 126 | /* This flag is set if the TLB mappings are not contained in the | ||
| 127 | * 0x10000000 - 0x20000000 boot bus region. */ | ||
| 128 | #define CVMX_BOOTINFO_CFG_FLAG_OVERSIZE_TLB_MAPPING (1ull << 4) | ||
| 129 | #define CVMX_BOOTINFO_CFG_FLAG_BREAK (1ull << 5) | ||
| 130 | |||
| 131 | #endif /* (CVMX_BOOTINFO_MAJ_VER == 1) */ | ||
| 132 | |||
| 133 | /* Type defines for board and chip types */ | ||
| 134 | enum cvmx_board_types_enum { | ||
| 135 | CVMX_BOARD_TYPE_NULL = 0, | ||
| 136 | CVMX_BOARD_TYPE_SIM = 1, | ||
| 137 | CVMX_BOARD_TYPE_EBT3000 = 2, | ||
| 138 | CVMX_BOARD_TYPE_KODAMA = 3, | ||
| 139 | CVMX_BOARD_TYPE_NIAGARA = 4, | ||
| 140 | CVMX_BOARD_TYPE_NAC38 = 5, /* formerly NAO38 */ | ||
| 141 | CVMX_BOARD_TYPE_THUNDER = 6, | ||
| 142 | CVMX_BOARD_TYPE_TRANTOR = 7, | ||
| 143 | CVMX_BOARD_TYPE_EBH3000 = 8, | ||
| 144 | CVMX_BOARD_TYPE_EBH3100 = 9, | ||
| 145 | CVMX_BOARD_TYPE_HIKARI = 10, | ||
| 146 | CVMX_BOARD_TYPE_CN3010_EVB_HS5 = 11, | ||
| 147 | CVMX_BOARD_TYPE_CN3005_EVB_HS5 = 12, | ||
| 148 | CVMX_BOARD_TYPE_KBP = 13, | ||
| 149 | /* Deprecated, CVMX_BOARD_TYPE_CN3010_EVB_HS5 supports the CN3020 */ | ||
| 150 | CVMX_BOARD_TYPE_CN3020_EVB_HS5 = 14, | ||
| 151 | CVMX_BOARD_TYPE_EBT5800 = 15, | ||
| 152 | CVMX_BOARD_TYPE_NICPRO2 = 16, | ||
| 153 | CVMX_BOARD_TYPE_EBH5600 = 17, | ||
| 154 | CVMX_BOARD_TYPE_EBH5601 = 18, | ||
| 155 | CVMX_BOARD_TYPE_EBH5200 = 19, | ||
| 156 | CVMX_BOARD_TYPE_BBGW_REF = 20, | ||
| 157 | CVMX_BOARD_TYPE_NIC_XLE_4G = 21, | ||
| 158 | CVMX_BOARD_TYPE_EBT5600 = 22, | ||
| 159 | CVMX_BOARD_TYPE_EBH5201 = 23, | ||
| 160 | CVMX_BOARD_TYPE_MAX, | ||
| 161 | |||
| 162 | /* | ||
| 163 | * The range from CVMX_BOARD_TYPE_MAX to | ||
| 164 | * CVMX_BOARD_TYPE_CUST_DEFINED_MIN is reserved for future | ||
| 165 | * SDK use. | ||
| 166 | */ | ||
| 167 | |||
| 168 | /* | ||
| 169 | * Set aside a range for customer boards. These numbers are managed | ||
| 170 | * by Cavium. | ||
| 171 | */ | ||
| 172 | CVMX_BOARD_TYPE_CUST_DEFINED_MIN = 10000, | ||
| 173 | CVMX_BOARD_TYPE_CUST_WSX16 = 10001, | ||
| 174 | CVMX_BOARD_TYPE_CUST_NS0216 = 10002, | ||
| 175 | CVMX_BOARD_TYPE_CUST_NB5 = 10003, | ||
| 176 | CVMX_BOARD_TYPE_CUST_WMR500 = 10004, | ||
| 177 | CVMX_BOARD_TYPE_CUST_DEFINED_MAX = 20000, | ||
| 178 | |||
| 179 | /* | ||
| 180 | * Set aside a range for customer private use. The SDK won't | ||
| 181 | * use any numbers in this range. | ||
| 182 | */ | ||
| 183 | CVMX_BOARD_TYPE_CUST_PRIVATE_MIN = 20001, | ||
| 184 | CVMX_BOARD_TYPE_CUST_PRIVATE_MAX = 30000, | ||
| 185 | |||
| 186 | /* The remaining range is reserved for future use. */ | ||
| 187 | }; | ||
| 188 | |||
| 189 | enum cvmx_chip_types_enum { | ||
| 190 | CVMX_CHIP_TYPE_NULL = 0, | ||
| 191 | CVMX_CHIP_SIM_TYPE_DEPRECATED = 1, | ||
| 192 | CVMX_CHIP_TYPE_OCTEON_SAMPLE = 2, | ||
| 193 | CVMX_CHIP_TYPE_MAX, | ||
| 194 | }; | ||
| 195 | |||
| 196 | /* Compatability alias for NAC38 name change, planned to be removed | ||
| 197 | * from SDK 1.7 */ | ||
| 198 | #define CVMX_BOARD_TYPE_NAO38 CVMX_BOARD_TYPE_NAC38 | ||
| 199 | |||
| 200 | /* Functions to return string based on type */ | ||
| 201 | #define ENUM_BRD_TYPE_CASE(x) \ | ||
| 202 | case x: return(#x + 16); /* Skip CVMX_BOARD_TYPE_ */ | ||
| 203 | static inline const char *cvmx_board_type_to_string(enum | ||
| 204 | cvmx_board_types_enum type) | ||
| 205 | { | ||
| 206 | switch (type) { | ||
| 207 | ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NULL) | ||
| 208 | ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_SIM) | ||
| 209 | ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT3000) | ||
| 210 | ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_KODAMA) | ||
| 211 | ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIAGARA) | ||
| 212 | ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NAC38) | ||
| 213 | ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_THUNDER) | ||
| 214 | ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_TRANTOR) | ||
| 215 | ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH3000) | ||
| 216 | ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH3100) | ||
| 217 | ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_HIKARI) | ||
| 218 | ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CN3010_EVB_HS5) | ||
| 219 | ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CN3005_EVB_HS5) | ||
| 220 | ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_KBP) | ||
| 221 | ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CN3020_EVB_HS5) | ||
| 222 | ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5800) | ||
| 223 | ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NICPRO2) | ||
| 224 | ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5600) | ||
| 225 | ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5601) | ||
| 226 | ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5200) | ||
| 227 | ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_BBGW_REF) | ||
| 228 | ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC_XLE_4G) | ||
| 229 | ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5600) | ||
| 230 | ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5201) | ||
| 231 | ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MAX) | ||
| 232 | |||
| 233 | /* Customer boards listed here */ | ||
| 234 | ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DEFINED_MIN) | ||
| 235 | ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_WSX16) | ||
| 236 | ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NS0216) | ||
| 237 | ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NB5) | ||
| 238 | ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_WMR500) | ||
| 239 | ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DEFINED_MAX) | ||
| 240 | |||
| 241 | /* Customer private range */ | ||
| 242 | ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MIN) | ||
| 243 | ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MAX) | ||
| 244 | } | ||
| 245 | return "Unsupported Board"; | ||
| 246 | } | ||
| 247 | |||
| 248 | #define ENUM_CHIP_TYPE_CASE(x) \ | ||
| 249 | case x: return(#x + 15); /* Skip CVMX_CHIP_TYPE */ | ||
| 250 | static inline const char *cvmx_chip_type_to_string(enum | ||
| 251 | cvmx_chip_types_enum type) | ||
| 252 | { | ||
| 253 | switch (type) { | ||
| 254 | ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_NULL) | ||
| 255 | ENUM_CHIP_TYPE_CASE(CVMX_CHIP_SIM_TYPE_DEPRECATED) | ||
| 256 | ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_OCTEON_SAMPLE) | ||
| 257 | ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_MAX) | ||
| 258 | } | ||
| 259 | return "Unsupported Chip"; | ||
| 260 | } | ||
| 261 | |||
| 262 | #endif /* __CVMX_BOOTINFO_H__ */ | ||
diff --git a/arch/mips/include/asm/octeon/cvmx-bootmem.h b/arch/mips/include/asm/octeon/cvmx-bootmem.h new file mode 100644 index 000000000000..1cbe4b55889d --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-bootmem.h | |||
| @@ -0,0 +1,288 @@ | |||
| 1 | /***********************license start*************** | ||
| 2 | * Author: Cavium Networks | ||
| 3 | * | ||
| 4 | * Contact: support@caviumnetworks.com | ||
| 5 | * This file is part of the OCTEON SDK | ||
| 6 | * | ||
| 7 | * Copyright (c) 2003-2008 Cavium Networks | ||
| 8 | * | ||
| 9 | * This file is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License, Version 2, as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | * | ||
| 13 | * This file is distributed in the hope that it will be useful, but | ||
| 14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
| 15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
| 16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
| 17 | * details. | ||
| 18 | * | ||
| 19 | * You should have received a copy of the GNU General Public License | ||
| 20 | * along with this file; if not, write to the Free Software | ||
| 21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 22 | * or visit http://www.gnu.org/licenses/. | ||
| 23 | * | ||
| 24 | * This file may also be available under a different license from Cavium. | ||
| 25 | * Contact Cavium Networks for more information | ||
| 26 | ***********************license end**************************************/ | ||
| 27 | |||
| 28 | /* | ||
| 29 | * Simple allocate only memory allocator. Used to allocate memory at | ||
| 30 | * application start time. | ||
| 31 | */ | ||
| 32 | |||
| 33 | #ifndef __CVMX_BOOTMEM_H__ | ||
| 34 | #define __CVMX_BOOTMEM_H__ | ||
| 35 | /* Must be multiple of 8, changing breaks ABI */ | ||
| 36 | #define CVMX_BOOTMEM_NAME_LEN 128 | ||
| 37 | |||
| 38 | /* Can change without breaking ABI */ | ||
| 39 | #define CVMX_BOOTMEM_NUM_NAMED_BLOCKS 64 | ||
| 40 | |||
| 41 | /* minimum alignment of bootmem alloced blocks */ | ||
| 42 | #define CVMX_BOOTMEM_ALIGNMENT_SIZE (16ull) | ||
| 43 | |||
| 44 | /* Flags for cvmx_bootmem_phy_mem* functions */ | ||
| 45 | /* Allocate from end of block instead of beginning */ | ||
| 46 | #define CVMX_BOOTMEM_FLAG_END_ALLOC (1 << 0) | ||
| 47 | |||
| 48 | /* Don't do any locking. */ | ||
| 49 | #define CVMX_BOOTMEM_FLAG_NO_LOCKING (1 << 1) | ||
| 50 | |||
| 51 | /* First bytes of each free physical block of memory contain this structure, | ||
| 52 | * which is used to maintain the free memory list. Since the bootloader is | ||
| 53 | * only 32 bits, there is a union providing 64 and 32 bit versions. The | ||
| 54 | * application init code converts addresses to 64 bit addresses before the | ||
| 55 | * application starts. | ||
| 56 | */ | ||
| 57 | struct cvmx_bootmem_block_header { | ||
| 58 | /* | ||
| 59 | * Note: these are referenced from assembly routines in the | ||
| 60 | * bootloader, so this structure should not be changed | ||
| 61 | * without changing those routines as well. | ||
| 62 | */ | ||
| 63 | uint64_t next_block_addr; | ||
| 64 | uint64_t size; | ||
| 65 | |||
| 66 | }; | ||
| 67 | |||
| 68 | /* | ||
| 69 | * Structure for named memory blocks. Number of descriptors available | ||
| 70 | * can be changed without affecting compatiblity, but name length | ||
| 71 | * changes require a bump in the bootmem descriptor version Note: This | ||
| 72 | * structure must be naturally 64 bit aligned, as a single memory | ||
| 73 | * image will be used by both 32 and 64 bit programs. | ||
| 74 | */ | ||
| 75 | struct cvmx_bootmem_named_block_desc { | ||
| 76 | /* Base address of named block */ | ||
| 77 | uint64_t base_addr; | ||
| 78 | /* | ||
| 79 | * Size actually allocated for named block (may differ from | ||
| 80 | * requested). | ||
| 81 | */ | ||
| 82 | uint64_t size; | ||
| 83 | /* name of named block */ | ||
| 84 | char name[CVMX_BOOTMEM_NAME_LEN]; | ||
| 85 | }; | ||
| 86 | |||
| 87 | /* Current descriptor versions */ | ||
| 88 | /* CVMX bootmem descriptor major version */ | ||
| 89 | #define CVMX_BOOTMEM_DESC_MAJ_VER 3 | ||
| 90 | |||
| 91 | /* CVMX bootmem descriptor minor version */ | ||
| 92 | #define CVMX_BOOTMEM_DESC_MIN_VER 0 | ||
| 93 | |||
| 94 | /* First three members of cvmx_bootmem_desc_t are left in original | ||
| 95 | * positions for backwards compatibility. | ||
| 96 | */ | ||
| 97 | struct cvmx_bootmem_desc { | ||
| 98 | /* spinlock to control access to list */ | ||
| 99 | uint32_t lock; | ||
| 100 | /* flags for indicating various conditions */ | ||
| 101 | uint32_t flags; | ||
| 102 | uint64_t head_addr; | ||
| 103 | |||
| 104 | /* Incremented when incompatible changes made */ | ||
| 105 | uint32_t major_version; | ||
| 106 | |||
| 107 | /* | ||
| 108 | * Incremented changed when compatible changes made, reset to | ||
| 109 | * zero when major incremented. | ||
| 110 | */ | ||
| 111 | uint32_t minor_version; | ||
| 112 | |||
| 113 | uint64_t app_data_addr; | ||
| 114 | uint64_t app_data_size; | ||
| 115 | |||
| 116 | /* number of elements in named blocks array */ | ||
| 117 | uint32_t named_block_num_blocks; | ||
| 118 | |||
| 119 | /* length of name array in bootmem blocks */ | ||
| 120 | uint32_t named_block_name_len; | ||
| 121 | /* address of named memory block descriptors */ | ||
| 122 | uint64_t named_block_array_addr; | ||
| 123 | |||
| 124 | }; | ||
| 125 | |||
| 126 | /** | ||
| 127 | * Initialize the boot alloc memory structures. This is | ||
| 128 | * normally called inside of cvmx_user_app_init() | ||
| 129 | * | ||
| 130 | * @mem_desc_ptr: Address of the free memory list | ||
| 131 | */ | ||
| 132 | extern int cvmx_bootmem_init(void *mem_desc_ptr); | ||
| 133 | |||
| 134 | /** | ||
| 135 | * Allocate a block of memory from the free list that was passed | ||
| 136 | * to the application by the bootloader. | ||
| 137 | * This is an allocate-only algorithm, so freeing memory is not possible. | ||
| 138 | * | ||
| 139 | * @size: Size in bytes of block to allocate | ||
| 140 | * @alignment: Alignment required - must be power of 2 | ||
| 141 | * | ||
| 142 | * Returns pointer to block of memory, NULL on error | ||
| 143 | */ | ||
| 144 | extern void *cvmx_bootmem_alloc(uint64_t size, uint64_t alignment); | ||
| 145 | |||
| 146 | /** | ||
| 147 | * Allocate a block of memory from the free list that was | ||
| 148 | * passed to the application by the bootloader at a specific | ||
| 149 | * address. This is an allocate-only algorithm, so | ||
| 150 | * freeing memory is not possible. Allocation will fail if | ||
| 151 | * memory cannot be allocated at the specified address. | ||
| 152 | * | ||
| 153 | * @size: Size in bytes of block to allocate | ||
| 154 | * @address: Physical address to allocate memory at. If this memory is not | ||
| 155 | * available, the allocation fails. | ||
| 156 | * @alignment: Alignment required - must be power of 2 | ||
| 157 | * Returns pointer to block of memory, NULL on error | ||
| 158 | */ | ||
| 159 | extern void *cvmx_bootmem_alloc_address(uint64_t size, uint64_t address, | ||
| 160 | uint64_t alignment); | ||
| 161 | |||
| 162 | /** | ||
| 163 | * Allocate a block of memory from the free list that was | ||
| 164 | * passed to the application by the bootloader within a specified | ||
| 165 | * address range. This is an allocate-only algorithm, so | ||
| 166 | * freeing memory is not possible. Allocation will fail if | ||
| 167 | * memory cannot be allocated in the requested range. | ||
| 168 | * | ||
| 169 | * @size: Size in bytes of block to allocate | ||
| 170 | * @min_addr: defines the minimum address of the range | ||
| 171 | * @max_addr: defines the maximum address of the range | ||
| 172 | * @alignment: Alignment required - must be power of 2 | ||
| 173 | * Returns pointer to block of memory, NULL on error | ||
| 174 | */ | ||
| 175 | extern void *cvmx_bootmem_alloc_range(uint64_t size, uint64_t alignment, | ||
| 176 | uint64_t min_addr, uint64_t max_addr); | ||
| 177 | |||
| 178 | /** | ||
| 179 | * Frees a previously allocated named bootmem block. | ||
| 180 | * | ||
| 181 | * @name: name of block to free | ||
| 182 | * | ||
| 183 | * Returns 0 on failure, | ||
| 184 | * !0 on success | ||
| 185 | */ | ||
| 186 | extern int cvmx_bootmem_free_named(char *name); | ||
| 187 | |||
| 188 | /** | ||
| 189 | * Finds a named bootmem block by name. | ||
| 190 | * | ||
| 191 | * @name: name of block to free | ||
| 192 | * | ||
| 193 | * Returns pointer to named block descriptor on success | ||
| 194 | * 0 on failure | ||
| 195 | */ | ||
| 196 | struct cvmx_bootmem_named_block_desc *cvmx_bootmem_find_named_block(char *name); | ||
| 197 | |||
| 198 | /** | ||
| 199 | * Allocates a block of physical memory from the free list, at | ||
| 200 | * (optional) requested address and alignment. | ||
| 201 | * | ||
| 202 | * @req_size: size of region to allocate. All requests are rounded up | ||
| 203 | * to be a multiple CVMX_BOOTMEM_ALIGNMENT_SIZE bytes size | ||
| 204 | * | ||
| 205 | * @address_min: Minimum address that block can occupy. | ||
| 206 | * | ||
| 207 | * @address_max: Specifies the maximum address_min (inclusive) that | ||
| 208 | * the allocation can use. | ||
| 209 | * | ||
| 210 | * @alignment: Requested alignment of the block. If this alignment | ||
| 211 | * cannot be met, the allocation fails. This must be a | ||
| 212 | * power of 2. (Note: Alignment of | ||
| 213 | * CVMX_BOOTMEM_ALIGNMENT_SIZE bytes is required, and | ||
| 214 | * internally enforced. Requested alignments of less than | ||
| 215 | * CVMX_BOOTMEM_ALIGNMENT_SIZE are set to | ||
| 216 | * CVMX_BOOTMEM_ALIGNMENT_SIZE.) | ||
| 217 | * | ||
| 218 | * @flags: Flags to control options for the allocation. | ||
| 219 | * | ||
| 220 | * Returns physical address of block allocated, or -1 on failure | ||
| 221 | */ | ||
| 222 | int64_t cvmx_bootmem_phy_alloc(uint64_t req_size, uint64_t address_min, | ||
| 223 | uint64_t address_max, uint64_t alignment, | ||
| 224 | uint32_t flags); | ||
| 225 | |||
| 226 | /** | ||
| 227 | * Finds a named memory block by name. | ||
| 228 | * Also used for finding an unused entry in the named block table. | ||
| 229 | * | ||
| 230 | * @name: Name of memory block to find. If NULL pointer given, then | ||
| 231 | * finds unused descriptor, if available. | ||
| 232 | * | ||
| 233 | * @flags: Flags to control options for the allocation. | ||
| 234 | * | ||
| 235 | * Returns Pointer to memory block descriptor, NULL if not found. | ||
| 236 | * If NULL returned when name parameter is NULL, then no memory | ||
| 237 | * block descriptors are available. | ||
| 238 | */ | ||
| 239 | struct cvmx_bootmem_named_block_desc * | ||
| 240 | cvmx_bootmem_phy_named_block_find(char *name, uint32_t flags); | ||
| 241 | |||
| 242 | /** | ||
| 243 | * Frees a named block. | ||
| 244 | * | ||
| 245 | * @name: name of block to free | ||
| 246 | * @flags: flags for passing options | ||
| 247 | * | ||
| 248 | * Returns 0 on failure | ||
| 249 | * 1 on success | ||
| 250 | */ | ||
| 251 | int cvmx_bootmem_phy_named_block_free(char *name, uint32_t flags); | ||
| 252 | |||
| 253 | /** | ||
| 254 | * Frees a block to the bootmem allocator list. This must | ||
| 255 | * be used with care, as the size provided must match the size | ||
| 256 | * of the block that was allocated, or the list will become | ||
| 257 | * corrupted. | ||
| 258 | * | ||
| 259 | * IMPORTANT: This is only intended to be used as part of named block | ||
| 260 | * frees and initial population of the free memory list. | ||
| 261 | * * | ||
| 262 | * | ||
| 263 | * @phy_addr: physical address of block | ||
| 264 | * @size: size of block in bytes. | ||
| 265 | * @flags: flags for passing options | ||
| 266 | * | ||
| 267 | * Returns 1 on success, | ||
| 268 | * 0 on failure | ||
| 269 | */ | ||
| 270 | int __cvmx_bootmem_phy_free(uint64_t phy_addr, uint64_t size, uint32_t flags); | ||
| 271 | |||
| 272 | /** | ||
| 273 | * Locks the bootmem allocator. This is useful in certain situations | ||
| 274 | * where multiple allocations must be made without being interrupted. | ||
| 275 | * This should be used with the CVMX_BOOTMEM_FLAG_NO_LOCKING flag. | ||
| 276 | * | ||
| 277 | */ | ||
| 278 | void cvmx_bootmem_lock(void); | ||
| 279 | |||
| 280 | /** | ||
| 281 | * Unlocks the bootmem allocator. This is useful in certain situations | ||
| 282 | * where multiple allocations must be made without being interrupted. | ||
| 283 | * This should be used with the CVMX_BOOTMEM_FLAG_NO_LOCKING flag. | ||
| 284 | * | ||
| 285 | */ | ||
| 286 | void cvmx_bootmem_unlock(void); | ||
| 287 | |||
| 288 | #endif /* __CVMX_BOOTMEM_H__ */ | ||
diff --git a/arch/mips/include/asm/octeon/cvmx-ciu-defs.h b/arch/mips/include/asm/octeon/cvmx-ciu-defs.h new file mode 100644 index 000000000000..f8f05b7764b7 --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-ciu-defs.h | |||
| @@ -0,0 +1,1616 @@ | |||
| 1 | /***********************license start*************** | ||
| 2 | * Author: Cavium Networks | ||
| 3 | * | ||
| 4 | * Contact: support@caviumnetworks.com | ||
| 5 | * This file is part of the OCTEON SDK | ||
| 6 | * | ||
| 7 | * Copyright (c) 2003-2008 Cavium Networks | ||
| 8 | * | ||
| 9 | * This file is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License, Version 2, as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | * | ||
| 13 | * This file is distributed in the hope that it will be useful, but | ||
| 14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
| 15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
| 16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
| 17 | * details. | ||
| 18 | * | ||
| 19 | * You should have received a copy of the GNU General Public License | ||
| 20 | * along with this file; if not, write to the Free Software | ||
| 21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 22 | * or visit http://www.gnu.org/licenses/. | ||
| 23 | * | ||
| 24 | * This file may also be available under a different license from Cavium. | ||
| 25 | * Contact Cavium Networks for more information | ||
| 26 | ***********************license end**************************************/ | ||
| 27 | |||
| 28 | #ifndef __CVMX_CIU_DEFS_H__ | ||
| 29 | #define __CVMX_CIU_DEFS_H__ | ||
| 30 | |||
| 31 | #define CVMX_CIU_BIST \ | ||
| 32 | CVMX_ADD_IO_SEG(0x0001070000000730ull) | ||
| 33 | #define CVMX_CIU_DINT \ | ||
| 34 | CVMX_ADD_IO_SEG(0x0001070000000720ull) | ||
| 35 | #define CVMX_CIU_FUSE \ | ||
| 36 | CVMX_ADD_IO_SEG(0x0001070000000728ull) | ||
| 37 | #define CVMX_CIU_GSTOP \ | ||
| 38 | CVMX_ADD_IO_SEG(0x0001070000000710ull) | ||
| 39 | #define CVMX_CIU_INTX_EN0(offset) \ | ||
| 40 | CVMX_ADD_IO_SEG(0x0001070000000200ull + (((offset) & 63) * 16)) | ||
| 41 | #define CVMX_CIU_INTX_EN0_W1C(offset) \ | ||
| 42 | CVMX_ADD_IO_SEG(0x0001070000002200ull + (((offset) & 63) * 16)) | ||
| 43 | #define CVMX_CIU_INTX_EN0_W1S(offset) \ | ||
| 44 | CVMX_ADD_IO_SEG(0x0001070000006200ull + (((offset) & 63) * 16)) | ||
| 45 | #define CVMX_CIU_INTX_EN1(offset) \ | ||
| 46 | CVMX_ADD_IO_SEG(0x0001070000000208ull + (((offset) & 63) * 16)) | ||
| 47 | #define CVMX_CIU_INTX_EN1_W1C(offset) \ | ||
| 48 | CVMX_ADD_IO_SEG(0x0001070000002208ull + (((offset) & 63) * 16)) | ||
| 49 | #define CVMX_CIU_INTX_EN1_W1S(offset) \ | ||
| 50 | CVMX_ADD_IO_SEG(0x0001070000006208ull + (((offset) & 63) * 16)) | ||
| 51 | #define CVMX_CIU_INTX_EN4_0(offset) \ | ||
| 52 | CVMX_ADD_IO_SEG(0x0001070000000C80ull + (((offset) & 15) * 16)) | ||
| 53 | #define CVMX_CIU_INTX_EN4_0_W1C(offset) \ | ||
| 54 | CVMX_ADD_IO_SEG(0x0001070000002C80ull + (((offset) & 15) * 16)) | ||
| 55 | #define CVMX_CIU_INTX_EN4_0_W1S(offset) \ | ||
| 56 | CVMX_ADD_IO_SEG(0x0001070000006C80ull + (((offset) & 15) * 16)) | ||
| 57 | #define CVMX_CIU_INTX_EN4_1(offset) \ | ||
| 58 | CVMX_ADD_IO_SEG(0x0001070000000C88ull + (((offset) & 15) * 16)) | ||
| 59 | #define CVMX_CIU_INTX_EN4_1_W1C(offset) \ | ||
| 60 | CVMX_ADD_IO_SEG(0x0001070000002C88ull + (((offset) & 15) * 16)) | ||
| 61 | #define CVMX_CIU_INTX_EN4_1_W1S(offset) \ | ||
| 62 | CVMX_ADD_IO_SEG(0x0001070000006C88ull + (((offset) & 15) * 16)) | ||
| 63 | #define CVMX_CIU_INTX_SUM0(offset) \ | ||
| 64 | CVMX_ADD_IO_SEG(0x0001070000000000ull + (((offset) & 63) * 8)) | ||
| 65 | #define CVMX_CIU_INTX_SUM4(offset) \ | ||
| 66 | CVMX_ADD_IO_SEG(0x0001070000000C00ull + (((offset) & 15) * 8)) | ||
| 67 | #define CVMX_CIU_INT_SUM1 \ | ||
| 68 | CVMX_ADD_IO_SEG(0x0001070000000108ull) | ||
| 69 | #define CVMX_CIU_MBOX_CLRX(offset) \ | ||
| 70 | CVMX_ADD_IO_SEG(0x0001070000000680ull + (((offset) & 15) * 8)) | ||
| 71 | #define CVMX_CIU_MBOX_SETX(offset) \ | ||
| 72 | CVMX_ADD_IO_SEG(0x0001070000000600ull + (((offset) & 15) * 8)) | ||
| 73 | #define CVMX_CIU_NMI \ | ||
| 74 | CVMX_ADD_IO_SEG(0x0001070000000718ull) | ||
| 75 | #define CVMX_CIU_PCI_INTA \ | ||
| 76 | CVMX_ADD_IO_SEG(0x0001070000000750ull) | ||
| 77 | #define CVMX_CIU_PP_DBG \ | ||
| 78 | CVMX_ADD_IO_SEG(0x0001070000000708ull) | ||
| 79 | #define CVMX_CIU_PP_POKEX(offset) \ | ||
| 80 | CVMX_ADD_IO_SEG(0x0001070000000580ull + (((offset) & 15) * 8)) | ||
| 81 | #define CVMX_CIU_PP_RST \ | ||
| 82 | CVMX_ADD_IO_SEG(0x0001070000000700ull) | ||
| 83 | #define CVMX_CIU_QLM_DCOK \ | ||
| 84 | CVMX_ADD_IO_SEG(0x0001070000000760ull) | ||
| 85 | #define CVMX_CIU_QLM_JTGC \ | ||
| 86 | CVMX_ADD_IO_SEG(0x0001070000000768ull) | ||
| 87 | #define CVMX_CIU_QLM_JTGD \ | ||
| 88 | CVMX_ADD_IO_SEG(0x0001070000000770ull) | ||
| 89 | #define CVMX_CIU_SOFT_BIST \ | ||
| 90 | CVMX_ADD_IO_SEG(0x0001070000000738ull) | ||
| 91 | #define CVMX_CIU_SOFT_PRST \ | ||
| 92 | CVMX_ADD_IO_SEG(0x0001070000000748ull) | ||
| 93 | #define CVMX_CIU_SOFT_PRST1 \ | ||
| 94 | CVMX_ADD_IO_SEG(0x0001070000000758ull) | ||
| 95 | #define CVMX_CIU_SOFT_RST \ | ||
| 96 | CVMX_ADD_IO_SEG(0x0001070000000740ull) | ||
| 97 | #define CVMX_CIU_TIMX(offset) \ | ||
| 98 | CVMX_ADD_IO_SEG(0x0001070000000480ull + (((offset) & 3) * 8)) | ||
| 99 | #define CVMX_CIU_WDOGX(offset) \ | ||
| 100 | CVMX_ADD_IO_SEG(0x0001070000000500ull + (((offset) & 15) * 8)) | ||
| 101 | |||
| 102 | union cvmx_ciu_bist { | ||
| 103 | uint64_t u64; | ||
| 104 | struct cvmx_ciu_bist_s { | ||
| 105 | uint64_t reserved_4_63:60; | ||
| 106 | uint64_t bist:4; | ||
| 107 | } s; | ||
| 108 | struct cvmx_ciu_bist_s cn30xx; | ||
| 109 | struct cvmx_ciu_bist_s cn31xx; | ||
| 110 | struct cvmx_ciu_bist_s cn38xx; | ||
| 111 | struct cvmx_ciu_bist_s cn38xxp2; | ||
| 112 | struct cvmx_ciu_bist_cn50xx { | ||
| 113 | uint64_t reserved_2_63:62; | ||
| 114 | uint64_t bist:2; | ||
| 115 | } cn50xx; | ||
| 116 | struct cvmx_ciu_bist_cn52xx { | ||
| 117 | uint64_t reserved_3_63:61; | ||
| 118 | uint64_t bist:3; | ||
| 119 | } cn52xx; | ||
| 120 | struct cvmx_ciu_bist_cn52xx cn52xxp1; | ||
| 121 | struct cvmx_ciu_bist_s cn56xx; | ||
| 122 | struct cvmx_ciu_bist_s cn56xxp1; | ||
| 123 | struct cvmx_ciu_bist_s cn58xx; | ||
| 124 | struct cvmx_ciu_bist_s cn58xxp1; | ||
| 125 | }; | ||
| 126 | |||
| 127 | union cvmx_ciu_dint { | ||
| 128 | uint64_t u64; | ||
| 129 | struct cvmx_ciu_dint_s { | ||
| 130 | uint64_t reserved_16_63:48; | ||
| 131 | uint64_t dint:16; | ||
| 132 | } s; | ||
| 133 | struct cvmx_ciu_dint_cn30xx { | ||
| 134 | uint64_t reserved_1_63:63; | ||
| 135 | uint64_t dint:1; | ||
| 136 | } cn30xx; | ||
| 137 | struct cvmx_ciu_dint_cn31xx { | ||
| 138 | uint64_t reserved_2_63:62; | ||
| 139 | uint64_t dint:2; | ||
| 140 | } cn31xx; | ||
| 141 | struct cvmx_ciu_dint_s cn38xx; | ||
| 142 | struct cvmx_ciu_dint_s cn38xxp2; | ||
| 143 | struct cvmx_ciu_dint_cn31xx cn50xx; | ||
| 144 | struct cvmx_ciu_dint_cn52xx { | ||
| 145 | uint64_t reserved_4_63:60; | ||
| 146 | uint64_t dint:4; | ||
| 147 | } cn52xx; | ||
| 148 | struct cvmx_ciu_dint_cn52xx cn52xxp1; | ||
| 149 | struct cvmx_ciu_dint_cn56xx { | ||
| 150 | uint64_t reserved_12_63:52; | ||
| 151 | uint64_t dint:12; | ||
| 152 | } cn56xx; | ||
| 153 | struct cvmx_ciu_dint_cn56xx cn56xxp1; | ||
| 154 | struct cvmx_ciu_dint_s cn58xx; | ||
| 155 | struct cvmx_ciu_dint_s cn58xxp1; | ||
| 156 | }; | ||
| 157 | |||
| 158 | union cvmx_ciu_fuse { | ||
| 159 | uint64_t u64; | ||
| 160 | struct cvmx_ciu_fuse_s { | ||
| 161 | uint64_t reserved_16_63:48; | ||
| 162 | uint64_t fuse:16; | ||
| 163 | } s; | ||
| 164 | struct cvmx_ciu_fuse_cn30xx { | ||
| 165 | uint64_t reserved_1_63:63; | ||
| 166 | uint64_t fuse:1; | ||
| 167 | } cn30xx; | ||
| 168 | struct cvmx_ciu_fuse_cn31xx { | ||
| 169 | uint64_t reserved_2_63:62; | ||
| 170 | uint64_t fuse:2; | ||
| 171 | } cn31xx; | ||
| 172 | struct cvmx_ciu_fuse_s cn38xx; | ||
| 173 | struct cvmx_ciu_fuse_s cn38xxp2; | ||
| 174 | struct cvmx_ciu_fuse_cn31xx cn50xx; | ||
| 175 | struct cvmx_ciu_fuse_cn52xx { | ||
| 176 | uint64_t reserved_4_63:60; | ||
| 177 | uint64_t fuse:4; | ||
| 178 | } cn52xx; | ||
| 179 | struct cvmx_ciu_fuse_cn52xx cn52xxp1; | ||
| 180 | struct cvmx_ciu_fuse_cn56xx { | ||
| 181 | uint64_t reserved_12_63:52; | ||
| 182 | uint64_t fuse:12; | ||
| 183 | } cn56xx; | ||
| 184 | struct cvmx_ciu_fuse_cn56xx cn56xxp1; | ||
| 185 | struct cvmx_ciu_fuse_s cn58xx; | ||
| 186 | struct cvmx_ciu_fuse_s cn58xxp1; | ||
| 187 | }; | ||
| 188 | |||
| 189 | union cvmx_ciu_gstop { | ||
| 190 | uint64_t u64; | ||
| 191 | struct cvmx_ciu_gstop_s { | ||
| 192 | uint64_t reserved_1_63:63; | ||
| 193 | uint64_t gstop:1; | ||
| 194 | } s; | ||
| 195 | struct cvmx_ciu_gstop_s cn30xx; | ||
| 196 | struct cvmx_ciu_gstop_s cn31xx; | ||
| 197 | struct cvmx_ciu_gstop_s cn38xx; | ||
| 198 | struct cvmx_ciu_gstop_s cn38xxp2; | ||
| 199 | struct cvmx_ciu_gstop_s cn50xx; | ||
| 200 | struct cvmx_ciu_gstop_s cn52xx; | ||
| 201 | struct cvmx_ciu_gstop_s cn52xxp1; | ||
| 202 | struct cvmx_ciu_gstop_s cn56xx; | ||
| 203 | struct cvmx_ciu_gstop_s cn56xxp1; | ||
| 204 | struct cvmx_ciu_gstop_s cn58xx; | ||
| 205 | struct cvmx_ciu_gstop_s cn58xxp1; | ||
| 206 | }; | ||
| 207 | |||
| 208 | union cvmx_ciu_intx_en0 { | ||
| 209 | uint64_t u64; | ||
| 210 | struct cvmx_ciu_intx_en0_s { | ||
| 211 | uint64_t bootdma:1; | ||
| 212 | uint64_t mii:1; | ||
| 213 | uint64_t ipdppthr:1; | ||
| 214 | uint64_t powiq:1; | ||
| 215 | uint64_t twsi2:1; | ||
| 216 | uint64_t mpi:1; | ||
| 217 | uint64_t pcm:1; | ||
| 218 | uint64_t usb:1; | ||
| 219 | uint64_t timer:4; | ||
| 220 | uint64_t key_zero:1; | ||
| 221 | uint64_t ipd_drp:1; | ||
| 222 | uint64_t gmx_drp:2; | ||
| 223 | uint64_t trace:1; | ||
| 224 | uint64_t rml:1; | ||
| 225 | uint64_t twsi:1; | ||
| 226 | uint64_t reserved_44_44:1; | ||
| 227 | uint64_t pci_msi:4; | ||
| 228 | uint64_t pci_int:4; | ||
| 229 | uint64_t uart:2; | ||
| 230 | uint64_t mbox:2; | ||
| 231 | uint64_t gpio:16; | ||
| 232 | uint64_t workq:16; | ||
| 233 | } s; | ||
| 234 | struct cvmx_ciu_intx_en0_cn30xx { | ||
| 235 | uint64_t reserved_59_63:5; | ||
| 236 | uint64_t mpi:1; | ||
| 237 | uint64_t pcm:1; | ||
| 238 | uint64_t usb:1; | ||
| 239 | uint64_t timer:4; | ||
| 240 | uint64_t reserved_51_51:1; | ||
| 241 | uint64_t ipd_drp:1; | ||
| 242 | uint64_t reserved_49_49:1; | ||
| 243 | uint64_t gmx_drp:1; | ||
| 244 | uint64_t reserved_47_47:1; | ||
| 245 | uint64_t rml:1; | ||
| 246 | uint64_t twsi:1; | ||
| 247 | uint64_t reserved_44_44:1; | ||
| 248 | uint64_t pci_msi:4; | ||
| 249 | uint64_t pci_int:4; | ||
| 250 | uint64_t uart:2; | ||
| 251 | uint64_t mbox:2; | ||
| 252 | uint64_t gpio:16; | ||
| 253 | uint64_t workq:16; | ||
| 254 | } cn30xx; | ||
| 255 | struct cvmx_ciu_intx_en0_cn31xx { | ||
| 256 | uint64_t reserved_59_63:5; | ||
| 257 | uint64_t mpi:1; | ||
| 258 | uint64_t pcm:1; | ||
| 259 | uint64_t usb:1; | ||
| 260 | uint64_t timer:4; | ||
| 261 | uint64_t reserved_51_51:1; | ||
| 262 | uint64_t ipd_drp:1; | ||
| 263 | uint64_t reserved_49_49:1; | ||
| 264 | uint64_t gmx_drp:1; | ||
| 265 | uint64_t trace:1; | ||
| 266 | uint64_t rml:1; | ||
| 267 | uint64_t twsi:1; | ||
| 268 | uint64_t reserved_44_44:1; | ||
| 269 | uint64_t pci_msi:4; | ||
| 270 | uint64_t pci_int:4; | ||
| 271 | uint64_t uart:2; | ||
| 272 | uint64_t mbox:2; | ||
| 273 | uint64_t gpio:16; | ||
| 274 | uint64_t workq:16; | ||
| 275 | } cn31xx; | ||
| 276 | struct cvmx_ciu_intx_en0_cn38xx { | ||
| 277 | uint64_t reserved_56_63:8; | ||
| 278 | uint64_t timer:4; | ||
| 279 | uint64_t key_zero:1; | ||
| 280 | uint64_t ipd_drp:1; | ||
| 281 | uint64_t gmx_drp:2; | ||
| 282 | uint64_t trace:1; | ||
| 283 | uint64_t rml:1; | ||
| 284 | uint64_t twsi:1; | ||
| 285 | uint64_t reserved_44_44:1; | ||
| 286 | uint64_t pci_msi:4; | ||
| 287 | uint64_t pci_int:4; | ||
| 288 | uint64_t uart:2; | ||
| 289 | uint64_t mbox:2; | ||
| 290 | uint64_t gpio:16; | ||
| 291 | uint64_t workq:16; | ||
| 292 | } cn38xx; | ||
| 293 | struct cvmx_ciu_intx_en0_cn38xx cn38xxp2; | ||
| 294 | struct cvmx_ciu_intx_en0_cn30xx cn50xx; | ||
| 295 | struct cvmx_ciu_intx_en0_cn52xx { | ||
| 296 | uint64_t bootdma:1; | ||
| 297 | uint64_t mii:1; | ||
| 298 | uint64_t ipdppthr:1; | ||
| 299 | uint64_t powiq:1; | ||
| 300 | uint64_t twsi2:1; | ||
| 301 | uint64_t reserved_57_58:2; | ||
| 302 | uint64_t usb:1; | ||
| 303 | uint64_t timer:4; | ||
| 304 | uint64_t reserved_51_51:1; | ||
| 305 | uint64_t ipd_drp:1; | ||
| 306 | uint64_t reserved_49_49:1; | ||
| 307 | uint64_t gmx_drp:1; | ||
| 308 | uint64_t trace:1; | ||
| 309 | uint64_t rml:1; | ||
| 310 | uint64_t twsi:1; | ||
| 311 | uint64_t reserved_44_44:1; | ||
| 312 | uint64_t pci_msi:4; | ||
| 313 | uint64_t pci_int:4; | ||
| 314 | uint64_t uart:2; | ||
| 315 | uint64_t mbox:2; | ||
| 316 | uint64_t gpio:16; | ||
| 317 | uint64_t workq:16; | ||
| 318 | } cn52xx; | ||
| 319 | struct cvmx_ciu_intx_en0_cn52xx cn52xxp1; | ||
| 320 | struct cvmx_ciu_intx_en0_cn56xx { | ||
| 321 | uint64_t bootdma:1; | ||
| 322 | uint64_t mii:1; | ||
| 323 | uint64_t ipdppthr:1; | ||
| 324 | uint64_t powiq:1; | ||
| 325 | uint64_t twsi2:1; | ||
| 326 | uint64_t reserved_57_58:2; | ||
| 327 | uint64_t usb:1; | ||
| 328 | uint64_t timer:4; | ||
| 329 | uint64_t key_zero:1; | ||
| 330 | uint64_t ipd_drp:1; | ||
| 331 | uint64_t gmx_drp:2; | ||
| 332 | uint64_t trace:1; | ||
| 333 | uint64_t rml:1; | ||
| 334 | uint64_t twsi:1; | ||
| 335 | uint64_t reserved_44_44:1; | ||
| 336 | uint64_t pci_msi:4; | ||
| 337 | uint64_t pci_int:4; | ||
| 338 | uint64_t uart:2; | ||
| 339 | uint64_t mbox:2; | ||
| 340 | uint64_t gpio:16; | ||
| 341 | uint64_t workq:16; | ||
| 342 | } cn56xx; | ||
| 343 | struct cvmx_ciu_intx_en0_cn56xx cn56xxp1; | ||
| 344 | struct cvmx_ciu_intx_en0_cn38xx cn58xx; | ||
| 345 | struct cvmx_ciu_intx_en0_cn38xx cn58xxp1; | ||
| 346 | }; | ||
| 347 | |||
| 348 | union cvmx_ciu_intx_en0_w1c { | ||
| 349 | uint64_t u64; | ||
| 350 | struct cvmx_ciu_intx_en0_w1c_s { | ||
| 351 | uint64_t bootdma:1; | ||
| 352 | uint64_t mii:1; | ||
| 353 | uint64_t ipdppthr:1; | ||
| 354 | uint64_t powiq:1; | ||
| 355 | uint64_t twsi2:1; | ||
| 356 | uint64_t reserved_57_58:2; | ||
| 357 | uint64_t usb:1; | ||
| 358 | uint64_t timer:4; | ||
| 359 | uint64_t key_zero:1; | ||
| 360 | uint64_t ipd_drp:1; | ||
| 361 | uint64_t gmx_drp:2; | ||
| 362 | uint64_t trace:1; | ||
| 363 | uint64_t rml:1; | ||
| 364 | uint64_t twsi:1; | ||
| 365 | uint64_t reserved_44_44:1; | ||
| 366 | uint64_t pci_msi:4; | ||
| 367 | uint64_t pci_int:4; | ||
| 368 | uint64_t uart:2; | ||
| 369 | uint64_t mbox:2; | ||
| 370 | uint64_t gpio:16; | ||
| 371 | uint64_t workq:16; | ||
| 372 | } s; | ||
| 373 | struct cvmx_ciu_intx_en0_w1c_cn52xx { | ||
| 374 | uint64_t bootdma:1; | ||
| 375 | uint64_t mii:1; | ||
| 376 | uint64_t ipdppthr:1; | ||
| 377 | uint64_t powiq:1; | ||
| 378 | uint64_t twsi2:1; | ||
| 379 | uint64_t reserved_57_58:2; | ||
| 380 | uint64_t usb:1; | ||
| 381 | uint64_t timer:4; | ||
| 382 | uint64_t reserved_51_51:1; | ||
| 383 | uint64_t ipd_drp:1; | ||
| 384 | uint64_t reserved_49_49:1; | ||
| 385 | uint64_t gmx_drp:1; | ||
| 386 | uint64_t trace:1; | ||
| 387 | uint64_t rml:1; | ||
| 388 | uint64_t twsi:1; | ||
| 389 | uint64_t reserved_44_44:1; | ||
| 390 | uint64_t pci_msi:4; | ||
| 391 | uint64_t pci_int:4; | ||
| 392 | uint64_t uart:2; | ||
| 393 | uint64_t mbox:2; | ||
| 394 | uint64_t gpio:16; | ||
| 395 | uint64_t workq:16; | ||
| 396 | } cn52xx; | ||
| 397 | struct cvmx_ciu_intx_en0_w1c_s cn56xx; | ||
| 398 | struct cvmx_ciu_intx_en0_w1c_cn58xx { | ||
| 399 | uint64_t reserved_56_63:8; | ||
| 400 | uint64_t timer:4; | ||
| 401 | uint64_t key_zero:1; | ||
| 402 | uint64_t ipd_drp:1; | ||
| 403 | uint64_t gmx_drp:2; | ||
| 404 | uint64_t trace:1; | ||
| 405 | uint64_t rml:1; | ||
| 406 | uint64_t twsi:1; | ||
| 407 | uint64_t reserved_44_44:1; | ||
| 408 | uint64_t pci_msi:4; | ||
| 409 | uint64_t pci_int:4; | ||
| 410 | uint64_t uart:2; | ||
| 411 | uint64_t mbox:2; | ||
| 412 | uint64_t gpio:16; | ||
| 413 | uint64_t workq:16; | ||
| 414 | } cn58xx; | ||
| 415 | }; | ||
| 416 | |||
| 417 | union cvmx_ciu_intx_en0_w1s { | ||
| 418 | uint64_t u64; | ||
| 419 | struct cvmx_ciu_intx_en0_w1s_s { | ||
| 420 | uint64_t bootdma:1; | ||
| 421 | uint64_t mii:1; | ||
| 422 | uint64_t ipdppthr:1; | ||
| 423 | uint64_t powiq:1; | ||
| 424 | uint64_t twsi2:1; | ||
| 425 | uint64_t reserved_57_58:2; | ||
| 426 | uint64_t usb:1; | ||
| 427 | uint64_t timer:4; | ||
| 428 | uint64_t key_zero:1; | ||
| 429 | uint64_t ipd_drp:1; | ||
| 430 | uint64_t gmx_drp:2; | ||
| 431 | uint64_t trace:1; | ||
| 432 | uint64_t rml:1; | ||
| 433 | uint64_t twsi:1; | ||
| 434 | uint64_t reserved_44_44:1; | ||
| 435 | uint64_t pci_msi:4; | ||
| 436 | uint64_t pci_int:4; | ||
| 437 | uint64_t uart:2; | ||
| 438 | uint64_t mbox:2; | ||
| 439 | uint64_t gpio:16; | ||
| 440 | uint64_t workq:16; | ||
| 441 | } s; | ||
| 442 | struct cvmx_ciu_intx_en0_w1s_cn52xx { | ||
| 443 | uint64_t bootdma:1; | ||
| 444 | uint64_t mii:1; | ||
| 445 | uint64_t ipdppthr:1; | ||
| 446 | uint64_t powiq:1; | ||
| 447 | uint64_t twsi2:1; | ||
| 448 | uint64_t reserved_57_58:2; | ||
| 449 | uint64_t usb:1; | ||
| 450 | uint64_t timer:4; | ||
| 451 | uint64_t reserved_51_51:1; | ||
| 452 | uint64_t ipd_drp:1; | ||
| 453 | uint64_t reserved_49_49:1; | ||
| 454 | uint64_t gmx_drp:1; | ||
| 455 | uint64_t trace:1; | ||
| 456 | uint64_t rml:1; | ||
| 457 | uint64_t twsi:1; | ||
| 458 | uint64_t reserved_44_44:1; | ||
| 459 | uint64_t pci_msi:4; | ||
| 460 | uint64_t pci_int:4; | ||
| 461 | uint64_t uart:2; | ||
| 462 | uint64_t mbox:2; | ||
| 463 | uint64_t gpio:16; | ||
| 464 | uint64_t workq:16; | ||
| 465 | } cn52xx; | ||
| 466 | struct cvmx_ciu_intx_en0_w1s_s cn56xx; | ||
| 467 | struct cvmx_ciu_intx_en0_w1s_cn58xx { | ||
| 468 | uint64_t reserved_56_63:8; | ||
| 469 | uint64_t timer:4; | ||
| 470 | uint64_t key_zero:1; | ||
| 471 | uint64_t ipd_drp:1; | ||
| 472 | uint64_t gmx_drp:2; | ||
| 473 | uint64_t trace:1; | ||
| 474 | uint64_t rml:1; | ||
| 475 | uint64_t twsi:1; | ||
| 476 | uint64_t reserved_44_44:1; | ||
| 477 | uint64_t pci_msi:4; | ||
| 478 | uint64_t pci_int:4; | ||
| 479 | uint64_t uart:2; | ||
| 480 | uint64_t mbox:2; | ||
| 481 | uint64_t gpio:16; | ||
| 482 | uint64_t workq:16; | ||
| 483 | } cn58xx; | ||
| 484 | }; | ||
| 485 | |||
| 486 | union cvmx_ciu_intx_en1 { | ||
| 487 | uint64_t u64; | ||
| 488 | struct cvmx_ciu_intx_en1_s { | ||
| 489 | uint64_t reserved_20_63:44; | ||
| 490 | uint64_t nand:1; | ||
| 491 | uint64_t mii1:1; | ||
| 492 | uint64_t usb1:1; | ||
| 493 | uint64_t uart2:1; | ||
| 494 | uint64_t wdog:16; | ||
| 495 | } s; | ||
| 496 | struct cvmx_ciu_intx_en1_cn30xx { | ||
| 497 | uint64_t reserved_1_63:63; | ||
| 498 | uint64_t wdog:1; | ||
| 499 | } cn30xx; | ||
| 500 | struct cvmx_ciu_intx_en1_cn31xx { | ||
| 501 | uint64_t reserved_2_63:62; | ||
| 502 | uint64_t wdog:2; | ||
| 503 | } cn31xx; | ||
| 504 | struct cvmx_ciu_intx_en1_cn38xx { | ||
| 505 | uint64_t reserved_16_63:48; | ||
| 506 | uint64_t wdog:16; | ||
| 507 | } cn38xx; | ||
| 508 | struct cvmx_ciu_intx_en1_cn38xx cn38xxp2; | ||
| 509 | struct cvmx_ciu_intx_en1_cn31xx cn50xx; | ||
| 510 | struct cvmx_ciu_intx_en1_cn52xx { | ||
| 511 | uint64_t reserved_20_63:44; | ||
| 512 | uint64_t nand:1; | ||
| 513 | uint64_t mii1:1; | ||
| 514 | uint64_t usb1:1; | ||
| 515 | uint64_t uart2:1; | ||
| 516 | uint64_t reserved_4_15:12; | ||
| 517 | uint64_t wdog:4; | ||
| 518 | } cn52xx; | ||
| 519 | struct cvmx_ciu_intx_en1_cn52xxp1 { | ||
| 520 | uint64_t reserved_19_63:45; | ||
| 521 | uint64_t mii1:1; | ||
| 522 | uint64_t usb1:1; | ||
| 523 | uint64_t uart2:1; | ||
| 524 | uint64_t reserved_4_15:12; | ||
| 525 | uint64_t wdog:4; | ||
| 526 | } cn52xxp1; | ||
| 527 | struct cvmx_ciu_intx_en1_cn56xx { | ||
| 528 | uint64_t reserved_12_63:52; | ||
| 529 | uint64_t wdog:12; | ||
| 530 | } cn56xx; | ||
| 531 | struct cvmx_ciu_intx_en1_cn56xx cn56xxp1; | ||
| 532 | struct cvmx_ciu_intx_en1_cn38xx cn58xx; | ||
| 533 | struct cvmx_ciu_intx_en1_cn38xx cn58xxp1; | ||
| 534 | }; | ||
| 535 | |||
| 536 | union cvmx_ciu_intx_en1_w1c { | ||
| 537 | uint64_t u64; | ||
| 538 | struct cvmx_ciu_intx_en1_w1c_s { | ||
| 539 | uint64_t reserved_20_63:44; | ||
| 540 | uint64_t nand:1; | ||
| 541 | uint64_t mii1:1; | ||
| 542 | uint64_t usb1:1; | ||
| 543 | uint64_t uart2:1; | ||
| 544 | uint64_t wdog:16; | ||
| 545 | } s; | ||
| 546 | struct cvmx_ciu_intx_en1_w1c_cn52xx { | ||
| 547 | uint64_t reserved_20_63:44; | ||
| 548 | uint64_t nand:1; | ||
| 549 | uint64_t mii1:1; | ||
| 550 | uint64_t usb1:1; | ||
| 551 | uint64_t uart2:1; | ||
| 552 | uint64_t reserved_4_15:12; | ||
| 553 | uint64_t wdog:4; | ||
| 554 | } cn52xx; | ||
| 555 | struct cvmx_ciu_intx_en1_w1c_cn56xx { | ||
| 556 | uint64_t reserved_12_63:52; | ||
| 557 | uint64_t wdog:12; | ||
| 558 | } cn56xx; | ||
| 559 | struct cvmx_ciu_intx_en1_w1c_cn58xx { | ||
| 560 | uint64_t reserved_16_63:48; | ||
| 561 | uint64_t wdog:16; | ||
| 562 | } cn58xx; | ||
| 563 | }; | ||
| 564 | |||
| 565 | union cvmx_ciu_intx_en1_w1s { | ||
| 566 | uint64_t u64; | ||
| 567 | struct cvmx_ciu_intx_en1_w1s_s { | ||
| 568 | uint64_t reserved_20_63:44; | ||
| 569 | uint64_t nand:1; | ||
| 570 | uint64_t mii1:1; | ||
| 571 | uint64_t usb1:1; | ||
| 572 | uint64_t uart2:1; | ||
| 573 | uint64_t wdog:16; | ||
| 574 | } s; | ||
| 575 | struct cvmx_ciu_intx_en1_w1s_cn52xx { | ||
| 576 | uint64_t reserved_20_63:44; | ||
| 577 | uint64_t nand:1; | ||
| 578 | uint64_t mii1:1; | ||
| 579 | uint64_t usb1:1; | ||
| 580 | uint64_t uart2:1; | ||
| 581 | uint64_t reserved_4_15:12; | ||
| 582 | uint64_t wdog:4; | ||
| 583 | } cn52xx; | ||
| 584 | struct cvmx_ciu_intx_en1_w1s_cn56xx { | ||
| 585 | uint64_t reserved_12_63:52; | ||
| 586 | uint64_t wdog:12; | ||
| 587 | } cn56xx; | ||
| 588 | struct cvmx_ciu_intx_en1_w1s_cn58xx { | ||
| 589 | uint64_t reserved_16_63:48; | ||
| 590 | uint64_t wdog:16; | ||
| 591 | } cn58xx; | ||
| 592 | }; | ||
| 593 | |||
| 594 | union cvmx_ciu_intx_en4_0 { | ||
| 595 | uint64_t u64; | ||
| 596 | struct cvmx_ciu_intx_en4_0_s { | ||
| 597 | uint64_t bootdma:1; | ||
| 598 | uint64_t mii:1; | ||
| 599 | uint64_t ipdppthr:1; | ||
| 600 | uint64_t powiq:1; | ||
| 601 | uint64_t twsi2:1; | ||
| 602 | uint64_t mpi:1; | ||
| 603 | uint64_t pcm:1; | ||
| 604 | uint64_t usb:1; | ||
| 605 | uint64_t timer:4; | ||
| 606 | uint64_t key_zero:1; | ||
| 607 | uint64_t ipd_drp:1; | ||
| 608 | uint64_t gmx_drp:2; | ||
| 609 | uint64_t trace:1; | ||
| 610 | uint64_t rml:1; | ||
| 611 | uint64_t twsi:1; | ||
| 612 | uint64_t reserved_44_44:1; | ||
| 613 | uint64_t pci_msi:4; | ||
| 614 | uint64_t pci_int:4; | ||
| 615 | uint64_t uart:2; | ||
| 616 | uint64_t mbox:2; | ||
| 617 | uint64_t gpio:16; | ||
| 618 | uint64_t workq:16; | ||
| 619 | } s; | ||
| 620 | struct cvmx_ciu_intx_en4_0_cn50xx { | ||
| 621 | uint64_t reserved_59_63:5; | ||
| 622 | uint64_t mpi:1; | ||
| 623 | uint64_t pcm:1; | ||
| 624 | uint64_t usb:1; | ||
| 625 | uint64_t timer:4; | ||
| 626 | uint64_t reserved_51_51:1; | ||
| 627 | uint64_t ipd_drp:1; | ||
| 628 | uint64_t reserved_49_49:1; | ||
| 629 | uint64_t gmx_drp:1; | ||
| 630 | uint64_t reserved_47_47:1; | ||
| 631 | uint64_t rml:1; | ||
| 632 | uint64_t twsi:1; | ||
| 633 | uint64_t reserved_44_44:1; | ||
| 634 | uint64_t pci_msi:4; | ||
| 635 | uint64_t pci_int:4; | ||
| 636 | uint64_t uart:2; | ||
| 637 | uint64_t mbox:2; | ||
| 638 | uint64_t gpio:16; | ||
| 639 | uint64_t workq:16; | ||
| 640 | } cn50xx; | ||
| 641 | struct cvmx_ciu_intx_en4_0_cn52xx { | ||
| 642 | uint64_t bootdma:1; | ||
| 643 | uint64_t mii:1; | ||
| 644 | uint64_t ipdppthr:1; | ||
| 645 | uint64_t powiq:1; | ||
| 646 | uint64_t twsi2:1; | ||
| 647 | uint64_t reserved_57_58:2; | ||
| 648 | uint64_t usb:1; | ||
| 649 | uint64_t timer:4; | ||
| 650 | uint64_t reserved_51_51:1; | ||
| 651 | uint64_t ipd_drp:1; | ||
| 652 | uint64_t reserved_49_49:1; | ||
| 653 | uint64_t gmx_drp:1; | ||
| 654 | uint64_t trace:1; | ||
| 655 | uint64_t rml:1; | ||
| 656 | uint64_t twsi:1; | ||
| 657 | uint64_t reserved_44_44:1; | ||
| 658 | uint64_t pci_msi:4; | ||
| 659 | uint64_t pci_int:4; | ||
| 660 | uint64_t uart:2; | ||
| 661 | uint64_t mbox:2; | ||
| 662 | uint64_t gpio:16; | ||
| 663 | uint64_t workq:16; | ||
| 664 | } cn52xx; | ||
| 665 | struct cvmx_ciu_intx_en4_0_cn52xx cn52xxp1; | ||
| 666 | struct cvmx_ciu_intx_en4_0_cn56xx { | ||
| 667 | uint64_t bootdma:1; | ||
| 668 | uint64_t mii:1; | ||
| 669 | uint64_t ipdppthr:1; | ||
| 670 | uint64_t powiq:1; | ||
| 671 | uint64_t twsi2:1; | ||
| 672 | uint64_t reserved_57_58:2; | ||
| 673 | uint64_t usb:1; | ||
| 674 | uint64_t timer:4; | ||
| 675 | uint64_t key_zero:1; | ||
| 676 | uint64_t ipd_drp:1; | ||
| 677 | uint64_t gmx_drp:2; | ||
| 678 | uint64_t trace:1; | ||
| 679 | uint64_t rml:1; | ||
| 680 | uint64_t twsi:1; | ||
| 681 | uint64_t reserved_44_44:1; | ||
| 682 | uint64_t pci_msi:4; | ||
| 683 | uint64_t pci_int:4; | ||
| 684 | uint64_t uart:2; | ||
| 685 | uint64_t mbox:2; | ||
| 686 | uint64_t gpio:16; | ||
| 687 | uint64_t workq:16; | ||
| 688 | } cn56xx; | ||
| 689 | struct cvmx_ciu_intx_en4_0_cn56xx cn56xxp1; | ||
| 690 | struct cvmx_ciu_intx_en4_0_cn58xx { | ||
| 691 | uint64_t reserved_56_63:8; | ||
| 692 | uint64_t timer:4; | ||
| 693 | uint64_t key_zero:1; | ||
| 694 | uint64_t ipd_drp:1; | ||
| 695 | uint64_t gmx_drp:2; | ||
| 696 | uint64_t trace:1; | ||
| 697 | uint64_t rml:1; | ||
| 698 | uint64_t twsi:1; | ||
| 699 | uint64_t reserved_44_44:1; | ||
| 700 | uint64_t pci_msi:4; | ||
| 701 | uint64_t pci_int:4; | ||
| 702 | uint64_t uart:2; | ||
| 703 | uint64_t mbox:2; | ||
| 704 | uint64_t gpio:16; | ||
| 705 | uint64_t workq:16; | ||
| 706 | } cn58xx; | ||
| 707 | struct cvmx_ciu_intx_en4_0_cn58xx cn58xxp1; | ||
| 708 | }; | ||
| 709 | |||
| 710 | union cvmx_ciu_intx_en4_0_w1c { | ||
| 711 | uint64_t u64; | ||
| 712 | struct cvmx_ciu_intx_en4_0_w1c_s { | ||
| 713 | uint64_t bootdma:1; | ||
| 714 | uint64_t mii:1; | ||
| 715 | uint64_t ipdppthr:1; | ||
| 716 | uint64_t powiq:1; | ||
| 717 | uint64_t twsi2:1; | ||
| 718 | uint64_t reserved_57_58:2; | ||
| 719 | uint64_t usb:1; | ||
| 720 | uint64_t timer:4; | ||
| 721 | uint64_t key_zero:1; | ||
| 722 | uint64_t ipd_drp:1; | ||
| 723 | uint64_t gmx_drp:2; | ||
| 724 | uint64_t trace:1; | ||
| 725 | uint64_t rml:1; | ||
| 726 | uint64_t twsi:1; | ||
| 727 | uint64_t reserved_44_44:1; | ||
| 728 | uint64_t pci_msi:4; | ||
| 729 | uint64_t pci_int:4; | ||
| 730 | uint64_t uart:2; | ||
| 731 | uint64_t mbox:2; | ||
| 732 | uint64_t gpio:16; | ||
| 733 | uint64_t workq:16; | ||
| 734 | } s; | ||
| 735 | struct cvmx_ciu_intx_en4_0_w1c_cn52xx { | ||
| 736 | uint64_t bootdma:1; | ||
| 737 | uint64_t mii:1; | ||
| 738 | uint64_t ipdppthr:1; | ||
| 739 | uint64_t powiq:1; | ||
| 740 | uint64_t twsi2:1; | ||
| 741 | uint64_t reserved_57_58:2; | ||
| 742 | uint64_t usb:1; | ||
| 743 | uint64_t timer:4; | ||
| 744 | uint64_t reserved_51_51:1; | ||
| 745 | uint64_t ipd_drp:1; | ||
| 746 | uint64_t reserved_49_49:1; | ||
| 747 | uint64_t gmx_drp:1; | ||
| 748 | uint64_t trace:1; | ||
| 749 | uint64_t rml:1; | ||
| 750 | uint64_t twsi:1; | ||
| 751 | uint64_t reserved_44_44:1; | ||
| 752 | uint64_t pci_msi:4; | ||
| 753 | uint64_t pci_int:4; | ||
| 754 | uint64_t uart:2; | ||
| 755 | uint64_t mbox:2; | ||
| 756 | uint64_t gpio:16; | ||
| 757 | uint64_t workq:16; | ||
| 758 | } cn52xx; | ||
| 759 | struct cvmx_ciu_intx_en4_0_w1c_s cn56xx; | ||
| 760 | struct cvmx_ciu_intx_en4_0_w1c_cn58xx { | ||
| 761 | uint64_t reserved_56_63:8; | ||
| 762 | uint64_t timer:4; | ||
| 763 | uint64_t key_zero:1; | ||
| 764 | uint64_t ipd_drp:1; | ||
| 765 | uint64_t gmx_drp:2; | ||
| 766 | uint64_t trace:1; | ||
| 767 | uint64_t rml:1; | ||
| 768 | uint64_t twsi:1; | ||
| 769 | uint64_t reserved_44_44:1; | ||
| 770 | uint64_t pci_msi:4; | ||
| 771 | uint64_t pci_int:4; | ||
| 772 | uint64_t uart:2; | ||
| 773 | uint64_t mbox:2; | ||
| 774 | uint64_t gpio:16; | ||
| 775 | uint64_t workq:16; | ||
| 776 | } cn58xx; | ||
| 777 | }; | ||
| 778 | |||
| 779 | union cvmx_ciu_intx_en4_0_w1s { | ||
| 780 | uint64_t u64; | ||
| 781 | struct cvmx_ciu_intx_en4_0_w1s_s { | ||
| 782 | uint64_t bootdma:1; | ||
| 783 | uint64_t mii:1; | ||
| 784 | uint64_t ipdppthr:1; | ||
| 785 | uint64_t powiq:1; | ||
| 786 | uint64_t twsi2:1; | ||
| 787 | uint64_t reserved_57_58:2; | ||
| 788 | uint64_t usb:1; | ||
| 789 | uint64_t timer:4; | ||
| 790 | uint64_t key_zero:1; | ||
| 791 | uint64_t ipd_drp:1; | ||
| 792 | uint64_t gmx_drp:2; | ||
| 793 | uint64_t trace:1; | ||
| 794 | uint64_t rml:1; | ||
| 795 | uint64_t twsi:1; | ||
| 796 | uint64_t reserved_44_44:1; | ||
| 797 | uint64_t pci_msi:4; | ||
| 798 | uint64_t pci_int:4; | ||
| 799 | uint64_t uart:2; | ||
| 800 | uint64_t mbox:2; | ||
| 801 | uint64_t gpio:16; | ||
| 802 | uint64_t workq:16; | ||
| 803 | } s; | ||
| 804 | struct cvmx_ciu_intx_en4_0_w1s_cn52xx { | ||
| 805 | uint64_t bootdma:1; | ||
| 806 | uint64_t mii:1; | ||
| 807 | uint64_t ipdppthr:1; | ||
| 808 | uint64_t powiq:1; | ||
| 809 | uint64_t twsi2:1; | ||
| 810 | uint64_t reserved_57_58:2; | ||
| 811 | uint64_t usb:1; | ||
| 812 | uint64_t timer:4; | ||
| 813 | uint64_t reserved_51_51:1; | ||
| 814 | uint64_t ipd_drp:1; | ||
| 815 | uint64_t reserved_49_49:1; | ||
| 816 | uint64_t gmx_drp:1; | ||
| 817 | uint64_t trace:1; | ||
| 818 | uint64_t rml:1; | ||
| 819 | uint64_t twsi:1; | ||
| 820 | uint64_t reserved_44_44:1; | ||
| 821 | uint64_t pci_msi:4; | ||
| 822 | uint64_t pci_int:4; | ||
| 823 | uint64_t uart:2; | ||
| 824 | uint64_t mbox:2; | ||
| 825 | uint64_t gpio:16; | ||
| 826 | uint64_t workq:16; | ||
| 827 | } cn52xx; | ||
| 828 | struct cvmx_ciu_intx_en4_0_w1s_s cn56xx; | ||
| 829 | struct cvmx_ciu_intx_en4_0_w1s_cn58xx { | ||
| 830 | uint64_t reserved_56_63:8; | ||
| 831 | uint64_t timer:4; | ||
| 832 | uint64_t key_zero:1; | ||
| 833 | uint64_t ipd_drp:1; | ||
| 834 | uint64_t gmx_drp:2; | ||
| 835 | uint64_t trace:1; | ||
| 836 | uint64_t rml:1; | ||
| 837 | uint64_t twsi:1; | ||
| 838 | uint64_t reserved_44_44:1; | ||
| 839 | uint64_t pci_msi:4; | ||
| 840 | uint64_t pci_int:4; | ||
| 841 | uint64_t uart:2; | ||
| 842 | uint64_t mbox:2; | ||
| 843 | uint64_t gpio:16; | ||
| 844 | uint64_t workq:16; | ||
| 845 | } cn58xx; | ||
| 846 | }; | ||
| 847 | |||
| 848 | union cvmx_ciu_intx_en4_1 { | ||
| 849 | uint64_t u64; | ||
| 850 | struct cvmx_ciu_intx_en4_1_s { | ||
| 851 | uint64_t reserved_20_63:44; | ||
| 852 | uint64_t nand:1; | ||
| 853 | uint64_t mii1:1; | ||
| 854 | uint64_t usb1:1; | ||
| 855 | uint64_t uart2:1; | ||
| 856 | uint64_t wdog:16; | ||
| 857 | } s; | ||
| 858 | struct cvmx_ciu_intx_en4_1_cn50xx { | ||
| 859 | uint64_t reserved_2_63:62; | ||
| 860 | uint64_t wdog:2; | ||
| 861 | } cn50xx; | ||
| 862 | struct cvmx_ciu_intx_en4_1_cn52xx { | ||
| 863 | uint64_t reserved_20_63:44; | ||
| 864 | uint64_t nand:1; | ||
| 865 | uint64_t mii1:1; | ||
| 866 | uint64_t usb1:1; | ||
| 867 | uint64_t uart2:1; | ||
| 868 | uint64_t reserved_4_15:12; | ||
| 869 | uint64_t wdog:4; | ||
| 870 | } cn52xx; | ||
| 871 | struct cvmx_ciu_intx_en4_1_cn52xxp1 { | ||
| 872 | uint64_t reserved_19_63:45; | ||
| 873 | uint64_t mii1:1; | ||
| 874 | uint64_t usb1:1; | ||
| 875 | uint64_t uart2:1; | ||
| 876 | uint64_t reserved_4_15:12; | ||
| 877 | uint64_t wdog:4; | ||
| 878 | } cn52xxp1; | ||
| 879 | struct cvmx_ciu_intx_en4_1_cn56xx { | ||
| 880 | uint64_t reserved_12_63:52; | ||
| 881 | uint64_t wdog:12; | ||
| 882 | } cn56xx; | ||
| 883 | struct cvmx_ciu_intx_en4_1_cn56xx cn56xxp1; | ||
| 884 | struct cvmx_ciu_intx_en4_1_cn58xx { | ||
| 885 | uint64_t reserved_16_63:48; | ||
| 886 | uint64_t wdog:16; | ||
| 887 | } cn58xx; | ||
| 888 | struct cvmx_ciu_intx_en4_1_cn58xx cn58xxp1; | ||
| 889 | }; | ||
| 890 | |||
| 891 | union cvmx_ciu_intx_en4_1_w1c { | ||
| 892 | uint64_t u64; | ||
| 893 | struct cvmx_ciu_intx_en4_1_w1c_s { | ||
| 894 | uint64_t reserved_20_63:44; | ||
| 895 | uint64_t nand:1; | ||
| 896 | uint64_t mii1:1; | ||
| 897 | uint64_t usb1:1; | ||
| 898 | uint64_t uart2:1; | ||
| 899 | uint64_t wdog:16; | ||
| 900 | } s; | ||
| 901 | struct cvmx_ciu_intx_en4_1_w1c_cn52xx { | ||
| 902 | uint64_t reserved_20_63:44; | ||
| 903 | uint64_t nand:1; | ||
| 904 | uint64_t mii1:1; | ||
| 905 | uint64_t usb1:1; | ||
| 906 | uint64_t uart2:1; | ||
| 907 | uint64_t reserved_4_15:12; | ||
| 908 | uint64_t wdog:4; | ||
| 909 | } cn52xx; | ||
| 910 | struct cvmx_ciu_intx_en4_1_w1c_cn56xx { | ||
| 911 | uint64_t reserved_12_63:52; | ||
| 912 | uint64_t wdog:12; | ||
| 913 | } cn56xx; | ||
| 914 | struct cvmx_ciu_intx_en4_1_w1c_cn58xx { | ||
| 915 | uint64_t reserved_16_63:48; | ||
| 916 | uint64_t wdog:16; | ||
| 917 | } cn58xx; | ||
| 918 | }; | ||
| 919 | |||
| 920 | union cvmx_ciu_intx_en4_1_w1s { | ||
| 921 | uint64_t u64; | ||
| 922 | struct cvmx_ciu_intx_en4_1_w1s_s { | ||
| 923 | uint64_t reserved_20_63:44; | ||
| 924 | uint64_t nand:1; | ||
| 925 | uint64_t mii1:1; | ||
| 926 | uint64_t usb1:1; | ||
| 927 | uint64_t uart2:1; | ||
| 928 | uint64_t wdog:16; | ||
| 929 | } s; | ||
| 930 | struct cvmx_ciu_intx_en4_1_w1s_cn52xx { | ||
| 931 | uint64_t reserved_20_63:44; | ||
| 932 | uint64_t nand:1; | ||
| 933 | uint64_t mii1:1; | ||
| 934 | uint64_t usb1:1; | ||
| 935 | uint64_t uart2:1; | ||
| 936 | uint64_t reserved_4_15:12; | ||
| 937 | uint64_t wdog:4; | ||
| 938 | } cn52xx; | ||
| 939 | struct cvmx_ciu_intx_en4_1_w1s_cn56xx { | ||
| 940 | uint64_t reserved_12_63:52; | ||
| 941 | uint64_t wdog:12; | ||
| 942 | } cn56xx; | ||
| 943 | struct cvmx_ciu_intx_en4_1_w1s_cn58xx { | ||
| 944 | uint64_t reserved_16_63:48; | ||
| 945 | uint64_t wdog:16; | ||
| 946 | } cn58xx; | ||
| 947 | }; | ||
| 948 | |||
| 949 | union cvmx_ciu_intx_sum0 { | ||
| 950 | uint64_t u64; | ||
| 951 | struct cvmx_ciu_intx_sum0_s { | ||
| 952 | uint64_t bootdma:1; | ||
| 953 | uint64_t mii:1; | ||
| 954 | uint64_t ipdppthr:1; | ||
| 955 | uint64_t powiq:1; | ||
| 956 | uint64_t twsi2:1; | ||
| 957 | uint64_t mpi:1; | ||
| 958 | uint64_t pcm:1; | ||
| 959 | uint64_t usb:1; | ||
| 960 | uint64_t timer:4; | ||
| 961 | uint64_t key_zero:1; | ||
| 962 | uint64_t ipd_drp:1; | ||
| 963 | uint64_t gmx_drp:2; | ||
| 964 | uint64_t trace:1; | ||
| 965 | uint64_t rml:1; | ||
| 966 | uint64_t twsi:1; | ||
| 967 | uint64_t wdog_sum:1; | ||
| 968 | uint64_t pci_msi:4; | ||
| 969 | uint64_t pci_int:4; | ||
| 970 | uint64_t uart:2; | ||
| 971 | uint64_t mbox:2; | ||
| 972 | uint64_t gpio:16; | ||
| 973 | uint64_t workq:16; | ||
| 974 | } s; | ||
| 975 | struct cvmx_ciu_intx_sum0_cn30xx { | ||
| 976 | uint64_t reserved_59_63:5; | ||
| 977 | uint64_t mpi:1; | ||
| 978 | uint64_t pcm:1; | ||
| 979 | uint64_t usb:1; | ||
| 980 | uint64_t timer:4; | ||
| 981 | uint64_t reserved_51_51:1; | ||
| 982 | uint64_t ipd_drp:1; | ||
| 983 | uint64_t reserved_49_49:1; | ||
| 984 | uint64_t gmx_drp:1; | ||
| 985 | uint64_t reserved_47_47:1; | ||
| 986 | uint64_t rml:1; | ||
| 987 | uint64_t twsi:1; | ||
| 988 | uint64_t wdog_sum:1; | ||
| 989 | uint64_t pci_msi:4; | ||
| 990 | uint64_t pci_int:4; | ||
| 991 | uint64_t uart:2; | ||
| 992 | uint64_t mbox:2; | ||
| 993 | uint64_t gpio:16; | ||
| 994 | uint64_t workq:16; | ||
| 995 | } cn30xx; | ||
| 996 | struct cvmx_ciu_intx_sum0_cn31xx { | ||
| 997 | uint64_t reserved_59_63:5; | ||
| 998 | uint64_t mpi:1; | ||
| 999 | uint64_t pcm:1; | ||
| 1000 | uint64_t usb:1; | ||
| 1001 | uint64_t timer:4; | ||
| 1002 | uint64_t reserved_51_51:1; | ||
| 1003 | uint64_t ipd_drp:1; | ||
| 1004 | uint64_t reserved_49_49:1; | ||
| 1005 | uint64_t gmx_drp:1; | ||
| 1006 | uint64_t trace:1; | ||
| 1007 | uint64_t rml:1; | ||
| 1008 | uint64_t twsi:1; | ||
| 1009 | uint64_t wdog_sum:1; | ||
| 1010 | uint64_t pci_msi:4; | ||
| 1011 | uint64_t pci_int:4; | ||
| 1012 | uint64_t uart:2; | ||
| 1013 | uint64_t mbox:2; | ||
| 1014 | uint64_t gpio:16; | ||
| 1015 | uint64_t workq:16; | ||
| 1016 | } cn31xx; | ||
| 1017 | struct cvmx_ciu_intx_sum0_cn38xx { | ||
| 1018 | uint64_t reserved_56_63:8; | ||
| 1019 | uint64_t timer:4; | ||
| 1020 | uint64_t key_zero:1; | ||
| 1021 | uint64_t ipd_drp:1; | ||
| 1022 | uint64_t gmx_drp:2; | ||
| 1023 | uint64_t trace:1; | ||
| 1024 | uint64_t rml:1; | ||
| 1025 | uint64_t twsi:1; | ||
| 1026 | uint64_t wdog_sum:1; | ||
| 1027 | uint64_t pci_msi:4; | ||
| 1028 | uint64_t pci_int:4; | ||
| 1029 | uint64_t uart:2; | ||
| 1030 | uint64_t mbox:2; | ||
| 1031 | uint64_t gpio:16; | ||
| 1032 | uint64_t workq:16; | ||
| 1033 | } cn38xx; | ||
| 1034 | struct cvmx_ciu_intx_sum0_cn38xx cn38xxp2; | ||
| 1035 | struct cvmx_ciu_intx_sum0_cn30xx cn50xx; | ||
| 1036 | struct cvmx_ciu_intx_sum0_cn52xx { | ||
| 1037 | uint64_t bootdma:1; | ||
| 1038 | uint64_t mii:1; | ||
| 1039 | uint64_t ipdppthr:1; | ||
| 1040 | uint64_t powiq:1; | ||
| 1041 | uint64_t twsi2:1; | ||
| 1042 | uint64_t reserved_57_58:2; | ||
| 1043 | uint64_t usb:1; | ||
| 1044 | uint64_t timer:4; | ||
| 1045 | uint64_t reserved_51_51:1; | ||
| 1046 | uint64_t ipd_drp:1; | ||
| 1047 | uint64_t reserved_49_49:1; | ||
| 1048 | uint64_t gmx_drp:1; | ||
| 1049 | uint64_t trace:1; | ||
| 1050 | uint64_t rml:1; | ||
| 1051 | uint64_t twsi:1; | ||
| 1052 | uint64_t wdog_sum:1; | ||
| 1053 | uint64_t pci_msi:4; | ||
| 1054 | uint64_t pci_int:4; | ||
| 1055 | uint64_t uart:2; | ||
| 1056 | uint64_t mbox:2; | ||
| 1057 | uint64_t gpio:16; | ||
| 1058 | uint64_t workq:16; | ||
| 1059 | } cn52xx; | ||
| 1060 | struct cvmx_ciu_intx_sum0_cn52xx cn52xxp1; | ||
| 1061 | struct cvmx_ciu_intx_sum0_cn56xx { | ||
| 1062 | uint64_t bootdma:1; | ||
| 1063 | uint64_t mii:1; | ||
| 1064 | uint64_t ipdppthr:1; | ||
| 1065 | uint64_t powiq:1; | ||
| 1066 | uint64_t twsi2:1; | ||
| 1067 | uint64_t reserved_57_58:2; | ||
| 1068 | uint64_t usb:1; | ||
| 1069 | uint64_t timer:4; | ||
| 1070 | uint64_t key_zero:1; | ||
| 1071 | uint64_t ipd_drp:1; | ||
| 1072 | uint64_t gmx_drp:2; | ||
| 1073 | uint64_t trace:1; | ||
| 1074 | uint64_t rml:1; | ||
| 1075 | uint64_t twsi:1; | ||
| 1076 | uint64_t wdog_sum:1; | ||
| 1077 | uint64_t pci_msi:4; | ||
| 1078 | uint64_t pci_int:4; | ||
| 1079 | uint64_t uart:2; | ||
| 1080 | uint64_t mbox:2; | ||
| 1081 | uint64_t gpio:16; | ||
| 1082 | uint64_t workq:16; | ||
| 1083 | } cn56xx; | ||
| 1084 | struct cvmx_ciu_intx_sum0_cn56xx cn56xxp1; | ||
| 1085 | struct cvmx_ciu_intx_sum0_cn38xx cn58xx; | ||
| 1086 | struct cvmx_ciu_intx_sum0_cn38xx cn58xxp1; | ||
| 1087 | }; | ||
| 1088 | |||
| 1089 | union cvmx_ciu_intx_sum4 { | ||
| 1090 | uint64_t u64; | ||
| 1091 | struct cvmx_ciu_intx_sum4_s { | ||
| 1092 | uint64_t bootdma:1; | ||
| 1093 | uint64_t mii:1; | ||
| 1094 | uint64_t ipdppthr:1; | ||
| 1095 | uint64_t powiq:1; | ||
| 1096 | uint64_t twsi2:1; | ||
| 1097 | uint64_t mpi:1; | ||
| 1098 | uint64_t pcm:1; | ||
| 1099 | uint64_t usb:1; | ||
| 1100 | uint64_t timer:4; | ||
| 1101 | uint64_t key_zero:1; | ||
| 1102 | uint64_t ipd_drp:1; | ||
| 1103 | uint64_t gmx_drp:2; | ||
| 1104 | uint64_t trace:1; | ||
| 1105 | uint64_t rml:1; | ||
| 1106 | uint64_t twsi:1; | ||
| 1107 | uint64_t wdog_sum:1; | ||
| 1108 | uint64_t pci_msi:4; | ||
| 1109 | uint64_t pci_int:4; | ||
| 1110 | uint64_t uart:2; | ||
| 1111 | uint64_t mbox:2; | ||
| 1112 | uint64_t gpio:16; | ||
| 1113 | uint64_t workq:16; | ||
| 1114 | } s; | ||
| 1115 | struct cvmx_ciu_intx_sum4_cn50xx { | ||
| 1116 | uint64_t reserved_59_63:5; | ||
| 1117 | uint64_t mpi:1; | ||
| 1118 | uint64_t pcm:1; | ||
| 1119 | uint64_t usb:1; | ||
| 1120 | uint64_t timer:4; | ||
| 1121 | uint64_t reserved_51_51:1; | ||
| 1122 | uint64_t ipd_drp:1; | ||
| 1123 | uint64_t reserved_49_49:1; | ||
| 1124 | uint64_t gmx_drp:1; | ||
| 1125 | uint64_t reserved_47_47:1; | ||
| 1126 | uint64_t rml:1; | ||
| 1127 | uint64_t twsi:1; | ||
| 1128 | uint64_t wdog_sum:1; | ||
| 1129 | uint64_t pci_msi:4; | ||
| 1130 | uint64_t pci_int:4; | ||
| 1131 | uint64_t uart:2; | ||
| 1132 | uint64_t mbox:2; | ||
| 1133 | uint64_t gpio:16; | ||
| 1134 | uint64_t workq:16; | ||
| 1135 | } cn50xx; | ||
| 1136 | struct cvmx_ciu_intx_sum4_cn52xx { | ||
| 1137 | uint64_t bootdma:1; | ||
| 1138 | uint64_t mii:1; | ||
| 1139 | uint64_t ipdppthr:1; | ||
| 1140 | uint64_t powiq:1; | ||
| 1141 | uint64_t twsi2:1; | ||
| 1142 | uint64_t reserved_57_58:2; | ||
| 1143 | uint64_t usb:1; | ||
| 1144 | uint64_t timer:4; | ||
| 1145 | uint64_t reserved_51_51:1; | ||
| 1146 | uint64_t ipd_drp:1; | ||
| 1147 | uint64_t reserved_49_49:1; | ||
| 1148 | uint64_t gmx_drp:1; | ||
| 1149 | uint64_t trace:1; | ||
| 1150 | uint64_t rml:1; | ||
| 1151 | uint64_t twsi:1; | ||
| 1152 | uint64_t wdog_sum:1; | ||
| 1153 | uint64_t pci_msi:4; | ||
| 1154 | uint64_t pci_int:4; | ||
| 1155 | uint64_t uart:2; | ||
| 1156 | uint64_t mbox:2; | ||
| 1157 | uint64_t gpio:16; | ||
| 1158 | uint64_t workq:16; | ||
| 1159 | } cn52xx; | ||
| 1160 | struct cvmx_ciu_intx_sum4_cn52xx cn52xxp1; | ||
| 1161 | struct cvmx_ciu_intx_sum4_cn56xx { | ||
| 1162 | uint64_t bootdma:1; | ||
| 1163 | uint64_t mii:1; | ||
| 1164 | uint64_t ipdppthr:1; | ||
| 1165 | uint64_t powiq:1; | ||
| 1166 | uint64_t twsi2:1; | ||
| 1167 | uint64_t reserved_57_58:2; | ||
| 1168 | uint64_t usb:1; | ||
| 1169 | uint64_t timer:4; | ||
| 1170 | uint64_t key_zero:1; | ||
| 1171 | uint64_t ipd_drp:1; | ||
| 1172 | uint64_t gmx_drp:2; | ||
| 1173 | uint64_t trace:1; | ||
| 1174 | uint64_t rml:1; | ||
| 1175 | uint64_t twsi:1; | ||
| 1176 | uint64_t wdog_sum:1; | ||
| 1177 | uint64_t pci_msi:4; | ||
| 1178 | uint64_t pci_int:4; | ||
| 1179 | uint64_t uart:2; | ||
| 1180 | uint64_t mbox:2; | ||
| 1181 | uint64_t gpio:16; | ||
| 1182 | uint64_t workq:16; | ||
| 1183 | } cn56xx; | ||
| 1184 | struct cvmx_ciu_intx_sum4_cn56xx cn56xxp1; | ||
| 1185 | struct cvmx_ciu_intx_sum4_cn58xx { | ||
| 1186 | uint64_t reserved_56_63:8; | ||
| 1187 | uint64_t timer:4; | ||
| 1188 | uint64_t key_zero:1; | ||
| 1189 | uint64_t ipd_drp:1; | ||
| 1190 | uint64_t gmx_drp:2; | ||
| 1191 | uint64_t trace:1; | ||
| 1192 | uint64_t rml:1; | ||
| 1193 | uint64_t twsi:1; | ||
| 1194 | uint64_t wdog_sum:1; | ||
| 1195 | uint64_t pci_msi:4; | ||
| 1196 | uint64_t pci_int:4; | ||
| 1197 | uint64_t uart:2; | ||
| 1198 | uint64_t mbox:2; | ||
| 1199 | uint64_t gpio:16; | ||
| 1200 | uint64_t workq:16; | ||
| 1201 | } cn58xx; | ||
| 1202 | struct cvmx_ciu_intx_sum4_cn58xx cn58xxp1; | ||
| 1203 | }; | ||
| 1204 | |||
| 1205 | union cvmx_ciu_int_sum1 { | ||
| 1206 | uint64_t u64; | ||
| 1207 | struct cvmx_ciu_int_sum1_s { | ||
| 1208 | uint64_t reserved_20_63:44; | ||
| 1209 | uint64_t nand:1; | ||
| 1210 | uint64_t mii1:1; | ||
| 1211 | uint64_t usb1:1; | ||
| 1212 | uint64_t uart2:1; | ||
| 1213 | uint64_t wdog:16; | ||
| 1214 | } s; | ||
| 1215 | struct cvmx_ciu_int_sum1_cn30xx { | ||
| 1216 | uint64_t reserved_1_63:63; | ||
| 1217 | uint64_t wdog:1; | ||
| 1218 | } cn30xx; | ||
| 1219 | struct cvmx_ciu_int_sum1_cn31xx { | ||
| 1220 | uint64_t reserved_2_63:62; | ||
| 1221 | uint64_t wdog:2; | ||
| 1222 | } cn31xx; | ||
| 1223 | struct cvmx_ciu_int_sum1_cn38xx { | ||
| 1224 | uint64_t reserved_16_63:48; | ||
| 1225 | uint64_t wdog:16; | ||
| 1226 | } cn38xx; | ||
| 1227 | struct cvmx_ciu_int_sum1_cn38xx cn38xxp2; | ||
| 1228 | struct cvmx_ciu_int_sum1_cn31xx cn50xx; | ||
| 1229 | struct cvmx_ciu_int_sum1_cn52xx { | ||
| 1230 | uint64_t reserved_20_63:44; | ||
| 1231 | uint64_t nand:1; | ||
| 1232 | uint64_t mii1:1; | ||
| 1233 | uint64_t usb1:1; | ||
| 1234 | uint64_t uart2:1; | ||
| 1235 | uint64_t reserved_4_15:12; | ||
| 1236 | uint64_t wdog:4; | ||
| 1237 | } cn52xx; | ||
| 1238 | struct cvmx_ciu_int_sum1_cn52xxp1 { | ||
| 1239 | uint64_t reserved_19_63:45; | ||
| 1240 | uint64_t mii1:1; | ||
| 1241 | uint64_t usb1:1; | ||
| 1242 | uint64_t uart2:1; | ||
| 1243 | uint64_t reserved_4_15:12; | ||
| 1244 | uint64_t wdog:4; | ||
| 1245 | } cn52xxp1; | ||
| 1246 | struct cvmx_ciu_int_sum1_cn56xx { | ||
| 1247 | uint64_t reserved_12_63:52; | ||
| 1248 | uint64_t wdog:12; | ||
| 1249 | } cn56xx; | ||
| 1250 | struct cvmx_ciu_int_sum1_cn56xx cn56xxp1; | ||
| 1251 | struct cvmx_ciu_int_sum1_cn38xx cn58xx; | ||
| 1252 | struct cvmx_ciu_int_sum1_cn38xx cn58xxp1; | ||
| 1253 | }; | ||
| 1254 | |||
| 1255 | union cvmx_ciu_mbox_clrx { | ||
| 1256 | uint64_t u64; | ||
| 1257 | struct cvmx_ciu_mbox_clrx_s { | ||
| 1258 | uint64_t reserved_32_63:32; | ||
| 1259 | uint64_t bits:32; | ||
| 1260 | } s; | ||
| 1261 | struct cvmx_ciu_mbox_clrx_s cn30xx; | ||
| 1262 | struct cvmx_ciu_mbox_clrx_s cn31xx; | ||
| 1263 | struct cvmx_ciu_mbox_clrx_s cn38xx; | ||
| 1264 | struct cvmx_ciu_mbox_clrx_s cn38xxp2; | ||
| 1265 | struct cvmx_ciu_mbox_clrx_s cn50xx; | ||
| 1266 | struct cvmx_ciu_mbox_clrx_s cn52xx; | ||
| 1267 | struct cvmx_ciu_mbox_clrx_s cn52xxp1; | ||
| 1268 | struct cvmx_ciu_mbox_clrx_s cn56xx; | ||
| 1269 | struct cvmx_ciu_mbox_clrx_s cn56xxp1; | ||
| 1270 | struct cvmx_ciu_mbox_clrx_s cn58xx; | ||
| 1271 | struct cvmx_ciu_mbox_clrx_s cn58xxp1; | ||
| 1272 | }; | ||
| 1273 | |||
| 1274 | union cvmx_ciu_mbox_setx { | ||
| 1275 | uint64_t u64; | ||
| 1276 | struct cvmx_ciu_mbox_setx_s { | ||
| 1277 | uint64_t reserved_32_63:32; | ||
| 1278 | uint64_t bits:32; | ||
| 1279 | } s; | ||
| 1280 | struct cvmx_ciu_mbox_setx_s cn30xx; | ||
| 1281 | struct cvmx_ciu_mbox_setx_s cn31xx; | ||
| 1282 | struct cvmx_ciu_mbox_setx_s cn38xx; | ||
| 1283 | struct cvmx_ciu_mbox_setx_s cn38xxp2; | ||
| 1284 | struct cvmx_ciu_mbox_setx_s cn50xx; | ||
| 1285 | struct cvmx_ciu_mbox_setx_s cn52xx; | ||
| 1286 | struct cvmx_ciu_mbox_setx_s cn52xxp1; | ||
| 1287 | struct cvmx_ciu_mbox_setx_s cn56xx; | ||
| 1288 | struct cvmx_ciu_mbox_setx_s cn56xxp1; | ||
| 1289 | struct cvmx_ciu_mbox_setx_s cn58xx; | ||
| 1290 | struct cvmx_ciu_mbox_setx_s cn58xxp1; | ||
| 1291 | }; | ||
| 1292 | |||
| 1293 | union cvmx_ciu_nmi { | ||
| 1294 | uint64_t u64; | ||
| 1295 | struct cvmx_ciu_nmi_s { | ||
| 1296 | uint64_t reserved_16_63:48; | ||
| 1297 | uint64_t nmi:16; | ||
| 1298 | } s; | ||
| 1299 | struct cvmx_ciu_nmi_cn30xx { | ||
| 1300 | uint64_t reserved_1_63:63; | ||
| 1301 | uint64_t nmi:1; | ||
| 1302 | } cn30xx; | ||
| 1303 | struct cvmx_ciu_nmi_cn31xx { | ||
| 1304 | uint64_t reserved_2_63:62; | ||
| 1305 | uint64_t nmi:2; | ||
| 1306 | } cn31xx; | ||
| 1307 | struct cvmx_ciu_nmi_s cn38xx; | ||
| 1308 | struct cvmx_ciu_nmi_s cn38xxp2; | ||
| 1309 | struct cvmx_ciu_nmi_cn31xx cn50xx; | ||
| 1310 | struct cvmx_ciu_nmi_cn52xx { | ||
| 1311 | uint64_t reserved_4_63:60; | ||
| 1312 | uint64_t nmi:4; | ||
| 1313 | } cn52xx; | ||
| 1314 | struct cvmx_ciu_nmi_cn52xx cn52xxp1; | ||
| 1315 | struct cvmx_ciu_nmi_cn56xx { | ||
| 1316 | uint64_t reserved_12_63:52; | ||
| 1317 | uint64_t nmi:12; | ||
| 1318 | } cn56xx; | ||
| 1319 | struct cvmx_ciu_nmi_cn56xx cn56xxp1; | ||
| 1320 | struct cvmx_ciu_nmi_s cn58xx; | ||
| 1321 | struct cvmx_ciu_nmi_s cn58xxp1; | ||
| 1322 | }; | ||
| 1323 | |||
| 1324 | union cvmx_ciu_pci_inta { | ||
| 1325 | uint64_t u64; | ||
| 1326 | struct cvmx_ciu_pci_inta_s { | ||
| 1327 | uint64_t reserved_2_63:62; | ||
| 1328 | uint64_t intr:2; | ||
| 1329 | } s; | ||
| 1330 | struct cvmx_ciu_pci_inta_s cn30xx; | ||
| 1331 | struct cvmx_ciu_pci_inta_s cn31xx; | ||
| 1332 | struct cvmx_ciu_pci_inta_s cn38xx; | ||
| 1333 | struct cvmx_ciu_pci_inta_s cn38xxp2; | ||
| 1334 | struct cvmx_ciu_pci_inta_s cn50xx; | ||
| 1335 | struct cvmx_ciu_pci_inta_s cn52xx; | ||
| 1336 | struct cvmx_ciu_pci_inta_s cn52xxp1; | ||
| 1337 | struct cvmx_ciu_pci_inta_s cn56xx; | ||
| 1338 | struct cvmx_ciu_pci_inta_s cn56xxp1; | ||
| 1339 | struct cvmx_ciu_pci_inta_s cn58xx; | ||
| 1340 | struct cvmx_ciu_pci_inta_s cn58xxp1; | ||
| 1341 | }; | ||
| 1342 | |||
| 1343 | union cvmx_ciu_pp_dbg { | ||
| 1344 | uint64_t u64; | ||
| 1345 | struct cvmx_ciu_pp_dbg_s { | ||
| 1346 | uint64_t reserved_16_63:48; | ||
| 1347 | uint64_t ppdbg:16; | ||
| 1348 | } s; | ||
| 1349 | struct cvmx_ciu_pp_dbg_cn30xx { | ||
| 1350 | uint64_t reserved_1_63:63; | ||
| 1351 | uint64_t ppdbg:1; | ||
| 1352 | } cn30xx; | ||
| 1353 | struct cvmx_ciu_pp_dbg_cn31xx { | ||
| 1354 | uint64_t reserved_2_63:62; | ||
| 1355 | uint64_t ppdbg:2; | ||
| 1356 | } cn31xx; | ||
| 1357 | struct cvmx_ciu_pp_dbg_s cn38xx; | ||
| 1358 | struct cvmx_ciu_pp_dbg_s cn38xxp2; | ||
| 1359 | struct cvmx_ciu_pp_dbg_cn31xx cn50xx; | ||
| 1360 | struct cvmx_ciu_pp_dbg_cn52xx { | ||
| 1361 | uint64_t reserved_4_63:60; | ||
| 1362 | uint64_t ppdbg:4; | ||
| 1363 | } cn52xx; | ||
| 1364 | struct cvmx_ciu_pp_dbg_cn52xx cn52xxp1; | ||
| 1365 | struct cvmx_ciu_pp_dbg_cn56xx { | ||
| 1366 | uint64_t reserved_12_63:52; | ||
| 1367 | uint64_t ppdbg:12; | ||
| 1368 | } cn56xx; | ||
| 1369 | struct cvmx_ciu_pp_dbg_cn56xx cn56xxp1; | ||
| 1370 | struct cvmx_ciu_pp_dbg_s cn58xx; | ||
| 1371 | struct cvmx_ciu_pp_dbg_s cn58xxp1; | ||
| 1372 | }; | ||
| 1373 | |||
| 1374 | union cvmx_ciu_pp_pokex { | ||
| 1375 | uint64_t u64; | ||
| 1376 | struct cvmx_ciu_pp_pokex_s { | ||
| 1377 | uint64_t reserved_0_63:64; | ||
| 1378 | } s; | ||
| 1379 | struct cvmx_ciu_pp_pokex_s cn30xx; | ||
| 1380 | struct cvmx_ciu_pp_pokex_s cn31xx; | ||
| 1381 | struct cvmx_ciu_pp_pokex_s cn38xx; | ||
| 1382 | struct cvmx_ciu_pp_pokex_s cn38xxp2; | ||
| 1383 | struct cvmx_ciu_pp_pokex_s cn50xx; | ||
| 1384 | struct cvmx_ciu_pp_pokex_s cn52xx; | ||
| 1385 | struct cvmx_ciu_pp_pokex_s cn52xxp1; | ||
| 1386 | struct cvmx_ciu_pp_pokex_s cn56xx; | ||
| 1387 | struct cvmx_ciu_pp_pokex_s cn56xxp1; | ||
| 1388 | struct cvmx_ciu_pp_pokex_s cn58xx; | ||
| 1389 | struct cvmx_ciu_pp_pokex_s cn58xxp1; | ||
| 1390 | }; | ||
| 1391 | |||
| 1392 | union cvmx_ciu_pp_rst { | ||
| 1393 | uint64_t u64; | ||
| 1394 | struct cvmx_ciu_pp_rst_s { | ||
| 1395 | uint64_t reserved_16_63:48; | ||
| 1396 | uint64_t rst:15; | ||
| 1397 | uint64_t rst0:1; | ||
| 1398 | } s; | ||
| 1399 | struct cvmx_ciu_pp_rst_cn30xx { | ||
| 1400 | uint64_t reserved_1_63:63; | ||
| 1401 | uint64_t rst0:1; | ||
| 1402 | } cn30xx; | ||
| 1403 | struct cvmx_ciu_pp_rst_cn31xx { | ||
| 1404 | uint64_t reserved_2_63:62; | ||
| 1405 | uint64_t rst:1; | ||
| 1406 | uint64_t rst0:1; | ||
| 1407 | } cn31xx; | ||
| 1408 | struct cvmx_ciu_pp_rst_s cn38xx; | ||
| 1409 | struct cvmx_ciu_pp_rst_s cn38xxp2; | ||
| 1410 | struct cvmx_ciu_pp_rst_cn31xx cn50xx; | ||
| 1411 | struct cvmx_ciu_pp_rst_cn52xx { | ||
| 1412 | uint64_t reserved_4_63:60; | ||
| 1413 | uint64_t rst:3; | ||
| 1414 | uint64_t rst0:1; | ||
| 1415 | } cn52xx; | ||
| 1416 | struct cvmx_ciu_pp_rst_cn52xx cn52xxp1; | ||
| 1417 | struct cvmx_ciu_pp_rst_cn56xx { | ||
| 1418 | uint64_t reserved_12_63:52; | ||
| 1419 | uint64_t rst:11; | ||
| 1420 | uint64_t rst0:1; | ||
| 1421 | } cn56xx; | ||
| 1422 | struct cvmx_ciu_pp_rst_cn56xx cn56xxp1; | ||
| 1423 | struct cvmx_ciu_pp_rst_s cn58xx; | ||
| 1424 | struct cvmx_ciu_pp_rst_s cn58xxp1; | ||
| 1425 | }; | ||
| 1426 | |||
| 1427 | union cvmx_ciu_qlm_dcok { | ||
| 1428 | uint64_t u64; | ||
| 1429 | struct cvmx_ciu_qlm_dcok_s { | ||
| 1430 | uint64_t reserved_4_63:60; | ||
| 1431 | uint64_t qlm_dcok:4; | ||
| 1432 | } s; | ||
| 1433 | struct cvmx_ciu_qlm_dcok_cn52xx { | ||
| 1434 | uint64_t reserved_2_63:62; | ||
| 1435 | uint64_t qlm_dcok:2; | ||
| 1436 | } cn52xx; | ||
| 1437 | struct cvmx_ciu_qlm_dcok_cn52xx cn52xxp1; | ||
| 1438 | struct cvmx_ciu_qlm_dcok_s cn56xx; | ||
| 1439 | struct cvmx_ciu_qlm_dcok_s cn56xxp1; | ||
| 1440 | }; | ||
| 1441 | |||
| 1442 | union cvmx_ciu_qlm_jtgc { | ||
| 1443 | uint64_t u64; | ||
| 1444 | struct cvmx_ciu_qlm_jtgc_s { | ||
| 1445 | uint64_t reserved_11_63:53; | ||
| 1446 | uint64_t clk_div:3; | ||
| 1447 | uint64_t reserved_6_7:2; | ||
| 1448 | uint64_t mux_sel:2; | ||
| 1449 | uint64_t bypass:4; | ||
| 1450 | } s; | ||
| 1451 | struct cvmx_ciu_qlm_jtgc_cn52xx { | ||
| 1452 | uint64_t reserved_11_63:53; | ||
| 1453 | uint64_t clk_div:3; | ||
| 1454 | uint64_t reserved_5_7:3; | ||
| 1455 | uint64_t mux_sel:1; | ||
| 1456 | uint64_t reserved_2_3:2; | ||
| 1457 | uint64_t bypass:2; | ||
| 1458 | } cn52xx; | ||
| 1459 | struct cvmx_ciu_qlm_jtgc_cn52xx cn52xxp1; | ||
| 1460 | struct cvmx_ciu_qlm_jtgc_s cn56xx; | ||
| 1461 | struct cvmx_ciu_qlm_jtgc_s cn56xxp1; | ||
| 1462 | }; | ||
| 1463 | |||
| 1464 | union cvmx_ciu_qlm_jtgd { | ||
| 1465 | uint64_t u64; | ||
| 1466 | struct cvmx_ciu_qlm_jtgd_s { | ||
| 1467 | uint64_t capture:1; | ||
| 1468 | uint64_t shift:1; | ||
| 1469 | uint64_t update:1; | ||
| 1470 | uint64_t reserved_44_60:17; | ||
| 1471 | uint64_t select:4; | ||
| 1472 | uint64_t reserved_37_39:3; | ||
| 1473 | uint64_t shft_cnt:5; | ||
| 1474 | uint64_t shft_reg:32; | ||
| 1475 | } s; | ||
| 1476 | struct cvmx_ciu_qlm_jtgd_cn52xx { | ||
| 1477 | uint64_t capture:1; | ||
| 1478 | uint64_t shift:1; | ||
| 1479 | uint64_t update:1; | ||
| 1480 | uint64_t reserved_42_60:19; | ||
| 1481 | uint64_t select:2; | ||
| 1482 | uint64_t reserved_37_39:3; | ||
| 1483 | uint64_t shft_cnt:5; | ||
| 1484 | uint64_t shft_reg:32; | ||
| 1485 | } cn52xx; | ||
| 1486 | struct cvmx_ciu_qlm_jtgd_cn52xx cn52xxp1; | ||
| 1487 | struct cvmx_ciu_qlm_jtgd_s cn56xx; | ||
| 1488 | struct cvmx_ciu_qlm_jtgd_cn56xxp1 { | ||
| 1489 | uint64_t capture:1; | ||
| 1490 | uint64_t shift:1; | ||
| 1491 | uint64_t update:1; | ||
| 1492 | uint64_t reserved_37_60:24; | ||
| 1493 | uint64_t shft_cnt:5; | ||
| 1494 | uint64_t shft_reg:32; | ||
| 1495 | } cn56xxp1; | ||
| 1496 | }; | ||
| 1497 | |||
| 1498 | union cvmx_ciu_soft_bist { | ||
| 1499 | uint64_t u64; | ||
| 1500 | struct cvmx_ciu_soft_bist_s { | ||
| 1501 | uint64_t reserved_1_63:63; | ||
| 1502 | uint64_t soft_bist:1; | ||
| 1503 | } s; | ||
| 1504 | struct cvmx_ciu_soft_bist_s cn30xx; | ||
| 1505 | struct cvmx_ciu_soft_bist_s cn31xx; | ||
| 1506 | struct cvmx_ciu_soft_bist_s cn38xx; | ||
| 1507 | struct cvmx_ciu_soft_bist_s cn38xxp2; | ||
| 1508 | struct cvmx_ciu_soft_bist_s cn50xx; | ||
| 1509 | struct cvmx_ciu_soft_bist_s cn52xx; | ||
| 1510 | struct cvmx_ciu_soft_bist_s cn52xxp1; | ||
| 1511 | struct cvmx_ciu_soft_bist_s cn56xx; | ||
| 1512 | struct cvmx_ciu_soft_bist_s cn56xxp1; | ||
| 1513 | struct cvmx_ciu_soft_bist_s cn58xx; | ||
| 1514 | struct cvmx_ciu_soft_bist_s cn58xxp1; | ||
| 1515 | }; | ||
| 1516 | |||
| 1517 | union cvmx_ciu_soft_prst { | ||
| 1518 | uint64_t u64; | ||
| 1519 | struct cvmx_ciu_soft_prst_s { | ||
| 1520 | uint64_t reserved_3_63:61; | ||
| 1521 | uint64_t host64:1; | ||
| 1522 | uint64_t npi:1; | ||
| 1523 | uint64_t soft_prst:1; | ||
| 1524 | } s; | ||
| 1525 | struct cvmx_ciu_soft_prst_s cn30xx; | ||
| 1526 | struct cvmx_ciu_soft_prst_s cn31xx; | ||
| 1527 | struct cvmx_ciu_soft_prst_s cn38xx; | ||
| 1528 | struct cvmx_ciu_soft_prst_s cn38xxp2; | ||
| 1529 | struct cvmx_ciu_soft_prst_s cn50xx; | ||
| 1530 | struct cvmx_ciu_soft_prst_cn52xx { | ||
| 1531 | uint64_t reserved_1_63:63; | ||
| 1532 | uint64_t soft_prst:1; | ||
| 1533 | } cn52xx; | ||
| 1534 | struct cvmx_ciu_soft_prst_cn52xx cn52xxp1; | ||
| 1535 | struct cvmx_ciu_soft_prst_cn52xx cn56xx; | ||
| 1536 | struct cvmx_ciu_soft_prst_cn52xx cn56xxp1; | ||
| 1537 | struct cvmx_ciu_soft_prst_s cn58xx; | ||
| 1538 | struct cvmx_ciu_soft_prst_s cn58xxp1; | ||
| 1539 | }; | ||
| 1540 | |||
| 1541 | union cvmx_ciu_soft_prst1 { | ||
| 1542 | uint64_t u64; | ||
| 1543 | struct cvmx_ciu_soft_prst1_s { | ||
| 1544 | uint64_t reserved_1_63:63; | ||
| 1545 | uint64_t soft_prst:1; | ||
| 1546 | } s; | ||
| 1547 | struct cvmx_ciu_soft_prst1_s cn52xx; | ||
| 1548 | struct cvmx_ciu_soft_prst1_s cn52xxp1; | ||
| 1549 | struct cvmx_ciu_soft_prst1_s cn56xx; | ||
| 1550 | struct cvmx_ciu_soft_prst1_s cn56xxp1; | ||
| 1551 | }; | ||
| 1552 | |||
| 1553 | union cvmx_ciu_soft_rst { | ||
| 1554 | uint64_t u64; | ||
| 1555 | struct cvmx_ciu_soft_rst_s { | ||
| 1556 | uint64_t reserved_1_63:63; | ||
| 1557 | uint64_t soft_rst:1; | ||
| 1558 | } s; | ||
| 1559 | struct cvmx_ciu_soft_rst_s cn30xx; | ||
| 1560 | struct cvmx_ciu_soft_rst_s cn31xx; | ||
| 1561 | struct cvmx_ciu_soft_rst_s cn38xx; | ||
| 1562 | struct cvmx_ciu_soft_rst_s cn38xxp2; | ||
| 1563 | struct cvmx_ciu_soft_rst_s cn50xx; | ||
| 1564 | struct cvmx_ciu_soft_rst_s cn52xx; | ||
| 1565 | struct cvmx_ciu_soft_rst_s cn52xxp1; | ||
| 1566 | struct cvmx_ciu_soft_rst_s cn56xx; | ||
| 1567 | struct cvmx_ciu_soft_rst_s cn56xxp1; | ||
| 1568 | struct cvmx_ciu_soft_rst_s cn58xx; | ||
| 1569 | struct cvmx_ciu_soft_rst_s cn58xxp1; | ||
| 1570 | }; | ||
| 1571 | |||
| 1572 | union cvmx_ciu_timx { | ||
| 1573 | uint64_t u64; | ||
| 1574 | struct cvmx_ciu_timx_s { | ||
| 1575 | uint64_t reserved_37_63:27; | ||
| 1576 | uint64_t one_shot:1; | ||
| 1577 | uint64_t len:36; | ||
| 1578 | } s; | ||
| 1579 | struct cvmx_ciu_timx_s cn30xx; | ||
| 1580 | struct cvmx_ciu_timx_s cn31xx; | ||
| 1581 | struct cvmx_ciu_timx_s cn38xx; | ||
| 1582 | struct cvmx_ciu_timx_s cn38xxp2; | ||
| 1583 | struct cvmx_ciu_timx_s cn50xx; | ||
| 1584 | struct cvmx_ciu_timx_s cn52xx; | ||
| 1585 | struct cvmx_ciu_timx_s cn52xxp1; | ||
| 1586 | struct cvmx_ciu_timx_s cn56xx; | ||
| 1587 | struct cvmx_ciu_timx_s cn56xxp1; | ||
| 1588 | struct cvmx_ciu_timx_s cn58xx; | ||
| 1589 | struct cvmx_ciu_timx_s cn58xxp1; | ||
| 1590 | }; | ||
| 1591 | |||
| 1592 | union cvmx_ciu_wdogx { | ||
| 1593 | uint64_t u64; | ||
| 1594 | struct cvmx_ciu_wdogx_s { | ||
| 1595 | uint64_t reserved_46_63:18; | ||
| 1596 | uint64_t gstopen:1; | ||
| 1597 | uint64_t dstop:1; | ||
| 1598 | uint64_t cnt:24; | ||
| 1599 | uint64_t len:16; | ||
| 1600 | uint64_t state:2; | ||
| 1601 | uint64_t mode:2; | ||
| 1602 | } s; | ||
| 1603 | struct cvmx_ciu_wdogx_s cn30xx; | ||
| 1604 | struct cvmx_ciu_wdogx_s cn31xx; | ||
| 1605 | struct cvmx_ciu_wdogx_s cn38xx; | ||
| 1606 | struct cvmx_ciu_wdogx_s cn38xxp2; | ||
| 1607 | struct cvmx_ciu_wdogx_s cn50xx; | ||
| 1608 | struct cvmx_ciu_wdogx_s cn52xx; | ||
| 1609 | struct cvmx_ciu_wdogx_s cn52xxp1; | ||
| 1610 | struct cvmx_ciu_wdogx_s cn56xx; | ||
| 1611 | struct cvmx_ciu_wdogx_s cn56xxp1; | ||
| 1612 | struct cvmx_ciu_wdogx_s cn58xx; | ||
| 1613 | struct cvmx_ciu_wdogx_s cn58xxp1; | ||
| 1614 | }; | ||
| 1615 | |||
| 1616 | #endif | ||
diff --git a/arch/mips/include/asm/octeon/cvmx-gpio-defs.h b/arch/mips/include/asm/octeon/cvmx-gpio-defs.h new file mode 100644 index 000000000000..5fdd6ba48a05 --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-gpio-defs.h | |||
| @@ -0,0 +1,219 @@ | |||
| 1 | /***********************license start*************** | ||
| 2 | * Author: Cavium Networks | ||
| 3 | * | ||
| 4 | * Contact: support@caviumnetworks.com | ||
| 5 | * This file is part of the OCTEON SDK | ||
| 6 | * | ||
| 7 | * Copyright (c) 2003-2008 Cavium Networks | ||
| 8 | * | ||
| 9 | * This file is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License, Version 2, as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | * | ||
| 13 | * This file is distributed in the hope that it will be useful, but | ||
| 14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
| 15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
| 16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
| 17 | * details. | ||
| 18 | * | ||
| 19 | * You should have received a copy of the GNU General Public License | ||
| 20 | * along with this file; if not, write to the Free Software | ||
| 21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 22 | * or visit http://www.gnu.org/licenses/. | ||
| 23 | * | ||
| 24 | * This file may also be available under a different license from Cavium. | ||
| 25 | * Contact Cavium Networks for more information | ||
| 26 | ***********************license end**************************************/ | ||
| 27 | |||
| 28 | #ifndef __CVMX_GPIO_DEFS_H__ | ||
| 29 | #define __CVMX_GPIO_DEFS_H__ | ||
| 30 | |||
| 31 | #define CVMX_GPIO_BIT_CFGX(offset) \ | ||
| 32 | CVMX_ADD_IO_SEG(0x0001070000000800ull + (((offset) & 15) * 8)) | ||
| 33 | #define CVMX_GPIO_BOOT_ENA \ | ||
| 34 | CVMX_ADD_IO_SEG(0x00010700000008A8ull) | ||
| 35 | #define CVMX_GPIO_CLK_GENX(offset) \ | ||
| 36 | CVMX_ADD_IO_SEG(0x00010700000008C0ull + (((offset) & 3) * 8)) | ||
| 37 | #define CVMX_GPIO_DBG_ENA \ | ||
| 38 | CVMX_ADD_IO_SEG(0x00010700000008A0ull) | ||
| 39 | #define CVMX_GPIO_INT_CLR \ | ||
| 40 | CVMX_ADD_IO_SEG(0x0001070000000898ull) | ||
| 41 | #define CVMX_GPIO_RX_DAT \ | ||
| 42 | CVMX_ADD_IO_SEG(0x0001070000000880ull) | ||
| 43 | #define CVMX_GPIO_TX_CLR \ | ||
| 44 | CVMX_ADD_IO_SEG(0x0001070000000890ull) | ||
| 45 | #define CVMX_GPIO_TX_SET \ | ||
| 46 | CVMX_ADD_IO_SEG(0x0001070000000888ull) | ||
| 47 | #define CVMX_GPIO_XBIT_CFGX(offset) \ | ||
| 48 | CVMX_ADD_IO_SEG(0x0001070000000900ull + (((offset) & 31) * 8) - 8 * 16) | ||
| 49 | |||
| 50 | union cvmx_gpio_bit_cfgx { | ||
| 51 | uint64_t u64; | ||
| 52 | struct cvmx_gpio_bit_cfgx_s { | ||
| 53 | uint64_t reserved_15_63:49; | ||
| 54 | uint64_t clk_gen:1; | ||
| 55 | uint64_t clk_sel:2; | ||
| 56 | uint64_t fil_sel:4; | ||
| 57 | uint64_t fil_cnt:4; | ||
| 58 | uint64_t int_type:1; | ||
| 59 | uint64_t int_en:1; | ||
| 60 | uint64_t rx_xor:1; | ||
| 61 | uint64_t tx_oe:1; | ||
| 62 | } s; | ||
| 63 | struct cvmx_gpio_bit_cfgx_cn30xx { | ||
| 64 | uint64_t reserved_12_63:52; | ||
| 65 | uint64_t fil_sel:4; | ||
| 66 | uint64_t fil_cnt:4; | ||
| 67 | uint64_t int_type:1; | ||
| 68 | uint64_t int_en:1; | ||
| 69 | uint64_t rx_xor:1; | ||
| 70 | uint64_t tx_oe:1; | ||
| 71 | } cn30xx; | ||
| 72 | struct cvmx_gpio_bit_cfgx_cn30xx cn31xx; | ||
| 73 | struct cvmx_gpio_bit_cfgx_cn30xx cn38xx; | ||
| 74 | struct cvmx_gpio_bit_cfgx_cn30xx cn38xxp2; | ||
| 75 | struct cvmx_gpio_bit_cfgx_cn30xx cn50xx; | ||
| 76 | struct cvmx_gpio_bit_cfgx_s cn52xx; | ||
| 77 | struct cvmx_gpio_bit_cfgx_s cn52xxp1; | ||
| 78 | struct cvmx_gpio_bit_cfgx_s cn56xx; | ||
| 79 | struct cvmx_gpio_bit_cfgx_s cn56xxp1; | ||
| 80 | struct cvmx_gpio_bit_cfgx_cn30xx cn58xx; | ||
| 81 | struct cvmx_gpio_bit_cfgx_cn30xx cn58xxp1; | ||
| 82 | }; | ||
| 83 | |||
| 84 | union cvmx_gpio_boot_ena { | ||
| 85 | uint64_t u64; | ||
| 86 | struct cvmx_gpio_boot_ena_s { | ||
| 87 | uint64_t reserved_12_63:52; | ||
| 88 | uint64_t boot_ena:4; | ||
| 89 | uint64_t reserved_0_7:8; | ||
| 90 | } s; | ||
| 91 | struct cvmx_gpio_boot_ena_s cn30xx; | ||
| 92 | struct cvmx_gpio_boot_ena_s cn31xx; | ||
| 93 | struct cvmx_gpio_boot_ena_s cn50xx; | ||
| 94 | }; | ||
| 95 | |||
| 96 | union cvmx_gpio_clk_genx { | ||
| 97 | uint64_t u64; | ||
| 98 | struct cvmx_gpio_clk_genx_s { | ||
| 99 | uint64_t reserved_32_63:32; | ||
| 100 | uint64_t n:32; | ||
| 101 | } s; | ||
| 102 | struct cvmx_gpio_clk_genx_s cn52xx; | ||
| 103 | struct cvmx_gpio_clk_genx_s cn52xxp1; | ||
| 104 | struct cvmx_gpio_clk_genx_s cn56xx; | ||
| 105 | struct cvmx_gpio_clk_genx_s cn56xxp1; | ||
| 106 | }; | ||
| 107 | |||
| 108 | union cvmx_gpio_dbg_ena { | ||
| 109 | uint64_t u64; | ||
| 110 | struct cvmx_gpio_dbg_ena_s { | ||
| 111 | uint64_t reserved_21_63:43; | ||
| 112 | uint64_t dbg_ena:21; | ||
| 113 | } s; | ||
| 114 | struct cvmx_gpio_dbg_ena_s cn30xx; | ||
| 115 | struct cvmx_gpio_dbg_ena_s cn31xx; | ||
| 116 | struct cvmx_gpio_dbg_ena_s cn50xx; | ||
| 117 | }; | ||
| 118 | |||
| 119 | union cvmx_gpio_int_clr { | ||
| 120 | uint64_t u64; | ||
| 121 | struct cvmx_gpio_int_clr_s { | ||
| 122 | uint64_t reserved_16_63:48; | ||
| 123 | uint64_t type:16; | ||
| 124 | } s; | ||
| 125 | struct cvmx_gpio_int_clr_s cn30xx; | ||
| 126 | struct cvmx_gpio_int_clr_s cn31xx; | ||
| 127 | struct cvmx_gpio_int_clr_s cn38xx; | ||
| 128 | struct cvmx_gpio_int_clr_s cn38xxp2; | ||
| 129 | struct cvmx_gpio_int_clr_s cn50xx; | ||
| 130 | struct cvmx_gpio_int_clr_s cn52xx; | ||
| 131 | struct cvmx_gpio_int_clr_s cn52xxp1; | ||
| 132 | struct cvmx_gpio_int_clr_s cn56xx; | ||
| 133 | struct cvmx_gpio_int_clr_s cn56xxp1; | ||
| 134 | struct cvmx_gpio_int_clr_s cn58xx; | ||
| 135 | struct cvmx_gpio_int_clr_s cn58xxp1; | ||
| 136 | }; | ||
| 137 | |||
| 138 | union cvmx_gpio_rx_dat { | ||
| 139 | uint64_t u64; | ||
| 140 | struct cvmx_gpio_rx_dat_s { | ||
| 141 | uint64_t reserved_24_63:40; | ||
| 142 | uint64_t dat:24; | ||
| 143 | } s; | ||
| 144 | struct cvmx_gpio_rx_dat_s cn30xx; | ||
| 145 | struct cvmx_gpio_rx_dat_s cn31xx; | ||
| 146 | struct cvmx_gpio_rx_dat_cn38xx { | ||
| 147 | uint64_t reserved_16_63:48; | ||
| 148 | uint64_t dat:16; | ||
| 149 | } cn38xx; | ||
| 150 | struct cvmx_gpio_rx_dat_cn38xx cn38xxp2; | ||
| 151 | struct cvmx_gpio_rx_dat_s cn50xx; | ||
| 152 | struct cvmx_gpio_rx_dat_cn38xx cn52xx; | ||
| 153 | struct cvmx_gpio_rx_dat_cn38xx cn52xxp1; | ||
| 154 | struct cvmx_gpio_rx_dat_cn38xx cn56xx; | ||
| 155 | struct cvmx_gpio_rx_dat_cn38xx cn56xxp1; | ||
| 156 | struct cvmx_gpio_rx_dat_cn38xx cn58xx; | ||
| 157 | struct cvmx_gpio_rx_dat_cn38xx cn58xxp1; | ||
| 158 | }; | ||
| 159 | |||
| 160 | union cvmx_gpio_tx_clr { | ||
| 161 | uint64_t u64; | ||
| 162 | struct cvmx_gpio_tx_clr_s { | ||
| 163 | uint64_t reserved_24_63:40; | ||
| 164 | uint64_t clr:24; | ||
| 165 | } s; | ||
| 166 | struct cvmx_gpio_tx_clr_s cn30xx; | ||
| 167 | struct cvmx_gpio_tx_clr_s cn31xx; | ||
| 168 | struct cvmx_gpio_tx_clr_cn38xx { | ||
| 169 | uint64_t reserved_16_63:48; | ||
| 170 | uint64_t clr:16; | ||
| 171 | } cn38xx; | ||
| 172 | struct cvmx_gpio_tx_clr_cn38xx cn38xxp2; | ||
| 173 | struct cvmx_gpio_tx_clr_s cn50xx; | ||
| 174 | struct cvmx_gpio_tx_clr_cn38xx cn52xx; | ||
| 175 | struct cvmx_gpio_tx_clr_cn38xx cn52xxp1; | ||
| 176 | struct cvmx_gpio_tx_clr_cn38xx cn56xx; | ||
| 177 | struct cvmx_gpio_tx_clr_cn38xx cn56xxp1; | ||
| 178 | struct cvmx_gpio_tx_clr_cn38xx cn58xx; | ||
| 179 | struct cvmx_gpio_tx_clr_cn38xx cn58xxp1; | ||
| 180 | }; | ||
| 181 | |||
| 182 | union cvmx_gpio_tx_set { | ||
| 183 | uint64_t u64; | ||
| 184 | struct cvmx_gpio_tx_set_s { | ||
| 185 | uint64_t reserved_24_63:40; | ||
| 186 | uint64_t set:24; | ||
| 187 | } s; | ||
| 188 | struct cvmx_gpio_tx_set_s cn30xx; | ||
| 189 | struct cvmx_gpio_tx_set_s cn31xx; | ||
| 190 | struct cvmx_gpio_tx_set_cn38xx { | ||
| 191 | uint64_t reserved_16_63:48; | ||
| 192 | uint64_t set:16; | ||
| 193 | } cn38xx; | ||
| 194 | struct cvmx_gpio_tx_set_cn38xx cn38xxp2; | ||
| 195 | struct cvmx_gpio_tx_set_s cn50xx; | ||
| 196 | struct cvmx_gpio_tx_set_cn38xx cn52xx; | ||
| 197 | struct cvmx_gpio_tx_set_cn38xx cn52xxp1; | ||
| 198 | struct cvmx_gpio_tx_set_cn38xx cn56xx; | ||
| 199 | struct cvmx_gpio_tx_set_cn38xx cn56xxp1; | ||
| 200 | struct cvmx_gpio_tx_set_cn38xx cn58xx; | ||
| 201 | struct cvmx_gpio_tx_set_cn38xx cn58xxp1; | ||
| 202 | }; | ||
| 203 | |||
| 204 | union cvmx_gpio_xbit_cfgx { | ||
| 205 | uint64_t u64; | ||
| 206 | struct cvmx_gpio_xbit_cfgx_s { | ||
| 207 | uint64_t reserved_12_63:52; | ||
| 208 | uint64_t fil_sel:4; | ||
| 209 | uint64_t fil_cnt:4; | ||
| 210 | uint64_t reserved_2_3:2; | ||
| 211 | uint64_t rx_xor:1; | ||
| 212 | uint64_t tx_oe:1; | ||
| 213 | } s; | ||
| 214 | struct cvmx_gpio_xbit_cfgx_s cn30xx; | ||
| 215 | struct cvmx_gpio_xbit_cfgx_s cn31xx; | ||
| 216 | struct cvmx_gpio_xbit_cfgx_s cn50xx; | ||
| 217 | }; | ||
| 218 | |||
| 219 | #endif | ||
diff --git a/arch/mips/include/asm/octeon/cvmx-iob-defs.h b/arch/mips/include/asm/octeon/cvmx-iob-defs.h new file mode 100644 index 000000000000..0ee36baec500 --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-iob-defs.h | |||
| @@ -0,0 +1,530 @@ | |||
| 1 | /***********************license start*************** | ||
| 2 | * Author: Cavium Networks | ||
| 3 | * | ||
| 4 | * Contact: support@caviumnetworks.com | ||
| 5 | * This file is part of the OCTEON SDK | ||
| 6 | * | ||
| 7 | * Copyright (c) 2003-2008 Cavium Networks | ||
| 8 | * | ||
| 9 | * This file is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License, Version 2, as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | * | ||
| 13 | * This file is distributed in the hope that it will be useful, but | ||
| 14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
| 15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
| 16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
| 17 | * details. | ||
| 18 | * | ||
| 19 | * You should have received a copy of the GNU General Public License | ||
| 20 | * along with this file; if not, write to the Free Software | ||
| 21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 22 | * or visit http://www.gnu.org/licenses/. | ||
| 23 | * | ||
| 24 | * This file may also be available under a different license from Cavium. | ||
| 25 | * Contact Cavium Networks for more information | ||
| 26 | ***********************license end**************************************/ | ||
| 27 | |||
| 28 | #ifndef __CVMX_IOB_DEFS_H__ | ||
| 29 | #define __CVMX_IOB_DEFS_H__ | ||
| 30 | |||
| 31 | #define CVMX_IOB_BIST_STATUS \ | ||
| 32 | CVMX_ADD_IO_SEG(0x00011800F00007F8ull) | ||
| 33 | #define CVMX_IOB_CTL_STATUS \ | ||
| 34 | CVMX_ADD_IO_SEG(0x00011800F0000050ull) | ||
| 35 | #define CVMX_IOB_DWB_PRI_CNT \ | ||
| 36 | CVMX_ADD_IO_SEG(0x00011800F0000028ull) | ||
| 37 | #define CVMX_IOB_FAU_TIMEOUT \ | ||
| 38 | CVMX_ADD_IO_SEG(0x00011800F0000000ull) | ||
| 39 | #define CVMX_IOB_I2C_PRI_CNT \ | ||
| 40 | CVMX_ADD_IO_SEG(0x00011800F0000010ull) | ||
| 41 | #define CVMX_IOB_INB_CONTROL_MATCH \ | ||
| 42 | CVMX_ADD_IO_SEG(0x00011800F0000078ull) | ||
| 43 | #define CVMX_IOB_INB_CONTROL_MATCH_ENB \ | ||
| 44 | CVMX_ADD_IO_SEG(0x00011800F0000088ull) | ||
| 45 | #define CVMX_IOB_INB_DATA_MATCH \ | ||
| 46 | CVMX_ADD_IO_SEG(0x00011800F0000070ull) | ||
| 47 | #define CVMX_IOB_INB_DATA_MATCH_ENB \ | ||
| 48 | CVMX_ADD_IO_SEG(0x00011800F0000080ull) | ||
| 49 | #define CVMX_IOB_INT_ENB \ | ||
| 50 | CVMX_ADD_IO_SEG(0x00011800F0000060ull) | ||
| 51 | #define CVMX_IOB_INT_SUM \ | ||
| 52 | CVMX_ADD_IO_SEG(0x00011800F0000058ull) | ||
| 53 | #define CVMX_IOB_N2C_L2C_PRI_CNT \ | ||
| 54 | CVMX_ADD_IO_SEG(0x00011800F0000020ull) | ||
| 55 | #define CVMX_IOB_N2C_RSP_PRI_CNT \ | ||
| 56 | CVMX_ADD_IO_SEG(0x00011800F0000008ull) | ||
| 57 | #define CVMX_IOB_OUTB_COM_PRI_CNT \ | ||
| 58 | CVMX_ADD_IO_SEG(0x00011800F0000040ull) | ||
| 59 | #define CVMX_IOB_OUTB_CONTROL_MATCH \ | ||
| 60 | CVMX_ADD_IO_SEG(0x00011800F0000098ull) | ||
| 61 | #define CVMX_IOB_OUTB_CONTROL_MATCH_ENB \ | ||
| 62 | CVMX_ADD_IO_SEG(0x00011800F00000A8ull) | ||
| 63 | #define CVMX_IOB_OUTB_DATA_MATCH \ | ||
| 64 | CVMX_ADD_IO_SEG(0x00011800F0000090ull) | ||
| 65 | #define CVMX_IOB_OUTB_DATA_MATCH_ENB \ | ||
| 66 | CVMX_ADD_IO_SEG(0x00011800F00000A0ull) | ||
| 67 | #define CVMX_IOB_OUTB_FPA_PRI_CNT \ | ||
| 68 | CVMX_ADD_IO_SEG(0x00011800F0000048ull) | ||
| 69 | #define CVMX_IOB_OUTB_REQ_PRI_CNT \ | ||
| 70 | CVMX_ADD_IO_SEG(0x00011800F0000038ull) | ||
| 71 | #define CVMX_IOB_P2C_REQ_PRI_CNT \ | ||
| 72 | CVMX_ADD_IO_SEG(0x00011800F0000018ull) | ||
| 73 | #define CVMX_IOB_PKT_ERR \ | ||
| 74 | CVMX_ADD_IO_SEG(0x00011800F0000068ull) | ||
| 75 | |||
| 76 | union cvmx_iob_bist_status { | ||
| 77 | uint64_t u64; | ||
| 78 | struct cvmx_iob_bist_status_s { | ||
| 79 | uint64_t reserved_18_63:46; | ||
| 80 | uint64_t icnrcb:1; | ||
| 81 | uint64_t icr0:1; | ||
| 82 | uint64_t icr1:1; | ||
| 83 | uint64_t icnr1:1; | ||
| 84 | uint64_t icnr0:1; | ||
| 85 | uint64_t ibdr0:1; | ||
| 86 | uint64_t ibdr1:1; | ||
| 87 | uint64_t ibr0:1; | ||
| 88 | uint64_t ibr1:1; | ||
| 89 | uint64_t icnrt:1; | ||
| 90 | uint64_t ibrq0:1; | ||
| 91 | uint64_t ibrq1:1; | ||
| 92 | uint64_t icrn0:1; | ||
| 93 | uint64_t icrn1:1; | ||
| 94 | uint64_t icrp0:1; | ||
| 95 | uint64_t icrp1:1; | ||
| 96 | uint64_t ibd:1; | ||
| 97 | uint64_t icd:1; | ||
| 98 | } s; | ||
| 99 | struct cvmx_iob_bist_status_s cn30xx; | ||
| 100 | struct cvmx_iob_bist_status_s cn31xx; | ||
| 101 | struct cvmx_iob_bist_status_s cn38xx; | ||
| 102 | struct cvmx_iob_bist_status_s cn38xxp2; | ||
| 103 | struct cvmx_iob_bist_status_s cn50xx; | ||
| 104 | struct cvmx_iob_bist_status_s cn52xx; | ||
| 105 | struct cvmx_iob_bist_status_s cn52xxp1; | ||
| 106 | struct cvmx_iob_bist_status_s cn56xx; | ||
| 107 | struct cvmx_iob_bist_status_s cn56xxp1; | ||
| 108 | struct cvmx_iob_bist_status_s cn58xx; | ||
| 109 | struct cvmx_iob_bist_status_s cn58xxp1; | ||
| 110 | }; | ||
| 111 | |||
| 112 | union cvmx_iob_ctl_status { | ||
| 113 | uint64_t u64; | ||
| 114 | struct cvmx_iob_ctl_status_s { | ||
| 115 | uint64_t reserved_5_63:59; | ||
| 116 | uint64_t outb_mat:1; | ||
| 117 | uint64_t inb_mat:1; | ||
| 118 | uint64_t pko_enb:1; | ||
| 119 | uint64_t dwb_enb:1; | ||
| 120 | uint64_t fau_end:1; | ||
| 121 | } s; | ||
| 122 | struct cvmx_iob_ctl_status_s cn30xx; | ||
| 123 | struct cvmx_iob_ctl_status_s cn31xx; | ||
| 124 | struct cvmx_iob_ctl_status_s cn38xx; | ||
| 125 | struct cvmx_iob_ctl_status_s cn38xxp2; | ||
| 126 | struct cvmx_iob_ctl_status_s cn50xx; | ||
| 127 | struct cvmx_iob_ctl_status_s cn52xx; | ||
| 128 | struct cvmx_iob_ctl_status_s cn52xxp1; | ||
| 129 | struct cvmx_iob_ctl_status_s cn56xx; | ||
| 130 | struct cvmx_iob_ctl_status_s cn56xxp1; | ||
| 131 | struct cvmx_iob_ctl_status_s cn58xx; | ||
| 132 | struct cvmx_iob_ctl_status_s cn58xxp1; | ||
| 133 | }; | ||
| 134 | |||
| 135 | union cvmx_iob_dwb_pri_cnt { | ||
| 136 | uint64_t u64; | ||
| 137 | struct cvmx_iob_dwb_pri_cnt_s { | ||
| 138 | uint64_t reserved_16_63:48; | ||
| 139 | uint64_t cnt_enb:1; | ||
| 140 | uint64_t cnt_val:15; | ||
| 141 | } s; | ||
| 142 | struct cvmx_iob_dwb_pri_cnt_s cn38xx; | ||
| 143 | struct cvmx_iob_dwb_pri_cnt_s cn38xxp2; | ||
| 144 | struct cvmx_iob_dwb_pri_cnt_s cn52xx; | ||
| 145 | struct cvmx_iob_dwb_pri_cnt_s cn52xxp1; | ||
| 146 | struct cvmx_iob_dwb_pri_cnt_s cn56xx; | ||
| 147 | struct cvmx_iob_dwb_pri_cnt_s cn56xxp1; | ||
| 148 | struct cvmx_iob_dwb_pri_cnt_s cn58xx; | ||
| 149 | struct cvmx_iob_dwb_pri_cnt_s cn58xxp1; | ||
| 150 | }; | ||
| 151 | |||
| 152 | union cvmx_iob_fau_timeout { | ||
| 153 | uint64_t u64; | ||
| 154 | struct cvmx_iob_fau_timeout_s { | ||
| 155 | uint64_t reserved_13_63:51; | ||
| 156 | uint64_t tout_enb:1; | ||
| 157 | uint64_t tout_val:12; | ||
| 158 | } s; | ||
| 159 | struct cvmx_iob_fau_timeout_s cn30xx; | ||
| 160 | struct cvmx_iob_fau_timeout_s cn31xx; | ||
| 161 | struct cvmx_iob_fau_timeout_s cn38xx; | ||
| 162 | struct cvmx_iob_fau_timeout_s cn38xxp2; | ||
| 163 | struct cvmx_iob_fau_timeout_s cn50xx; | ||
| 164 | struct cvmx_iob_fau_timeout_s cn52xx; | ||
| 165 | struct cvmx_iob_fau_timeout_s cn52xxp1; | ||
| 166 | struct cvmx_iob_fau_timeout_s cn56xx; | ||
| 167 | struct cvmx_iob_fau_timeout_s cn56xxp1; | ||
| 168 | struct cvmx_iob_fau_timeout_s cn58xx; | ||
| 169 | struct cvmx_iob_fau_timeout_s cn58xxp1; | ||
| 170 | }; | ||
| 171 | |||
| 172 | union cvmx_iob_i2c_pri_cnt { | ||
| 173 | uint64_t u64; | ||
| 174 | struct cvmx_iob_i2c_pri_cnt_s { | ||
| 175 | uint64_t reserved_16_63:48; | ||
| 176 | uint64_t cnt_enb:1; | ||
| 177 | uint64_t cnt_val:15; | ||
| 178 | } s; | ||
| 179 | struct cvmx_iob_i2c_pri_cnt_s cn38xx; | ||
| 180 | struct cvmx_iob_i2c_pri_cnt_s cn38xxp2; | ||
| 181 | struct cvmx_iob_i2c_pri_cnt_s cn52xx; | ||
| 182 | struct cvmx_iob_i2c_pri_cnt_s cn52xxp1; | ||
| 183 | struct cvmx_iob_i2c_pri_cnt_s cn56xx; | ||
| 184 | struct cvmx_iob_i2c_pri_cnt_s cn56xxp1; | ||
| 185 | struct cvmx_iob_i2c_pri_cnt_s cn58xx; | ||
| 186 | struct cvmx_iob_i2c_pri_cnt_s cn58xxp1; | ||
| 187 | }; | ||
| 188 | |||
| 189 | union cvmx_iob_inb_control_match { | ||
| 190 | uint64_t u64; | ||
| 191 | struct cvmx_iob_inb_control_match_s { | ||
| 192 | uint64_t reserved_29_63:35; | ||
| 193 | uint64_t mask:8; | ||
| 194 | uint64_t opc:4; | ||
| 195 | uint64_t dst:9; | ||
| 196 | uint64_t src:8; | ||
| 197 | } s; | ||
| 198 | struct cvmx_iob_inb_control_match_s cn30xx; | ||
| 199 | struct cvmx_iob_inb_control_match_s cn31xx; | ||
| 200 | struct cvmx_iob_inb_control_match_s cn38xx; | ||
| 201 | struct cvmx_iob_inb_control_match_s cn38xxp2; | ||
| 202 | struct cvmx_iob_inb_control_match_s cn50xx; | ||
| 203 | struct cvmx_iob_inb_control_match_s cn52xx; | ||
| 204 | struct cvmx_iob_inb_control_match_s cn52xxp1; | ||
| 205 | struct cvmx_iob_inb_control_match_s cn56xx; | ||
| 206 | struct cvmx_iob_inb_control_match_s cn56xxp1; | ||
| 207 | struct cvmx_iob_inb_control_match_s cn58xx; | ||
| 208 | struct cvmx_iob_inb_control_match_s cn58xxp1; | ||
| 209 | }; | ||
| 210 | |||
| 211 | union cvmx_iob_inb_control_match_enb { | ||
| 212 | uint64_t u64; | ||
| 213 | struct cvmx_iob_inb_control_match_enb_s { | ||
| 214 | uint64_t reserved_29_63:35; | ||
| 215 | uint64_t mask:8; | ||
| 216 | uint64_t opc:4; | ||
| 217 | uint64_t dst:9; | ||
| 218 | uint64_t src:8; | ||
| 219 | } s; | ||
| 220 | struct cvmx_iob_inb_control_match_enb_s cn30xx; | ||
| 221 | struct cvmx_iob_inb_control_match_enb_s cn31xx; | ||
| 222 | struct cvmx_iob_inb_control_match_enb_s cn38xx; | ||
| 223 | struct cvmx_iob_inb_control_match_enb_s cn38xxp2; | ||
| 224 | struct cvmx_iob_inb_control_match_enb_s cn50xx; | ||
| 225 | struct cvmx_iob_inb_control_match_enb_s cn52xx; | ||
| 226 | struct cvmx_iob_inb_control_match_enb_s cn52xxp1; | ||
| 227 | struct cvmx_iob_inb_control_match_enb_s cn56xx; | ||
| 228 | struct cvmx_iob_inb_control_match_enb_s cn56xxp1; | ||
| 229 | struct cvmx_iob_inb_control_match_enb_s cn58xx; | ||
| 230 | struct cvmx_iob_inb_control_match_enb_s cn58xxp1; | ||
| 231 | }; | ||
| 232 | |||
| 233 | union cvmx_iob_inb_data_match { | ||
| 234 | uint64_t u64; | ||
| 235 | struct cvmx_iob_inb_data_match_s { | ||
| 236 | uint64_t data:64; | ||
| 237 | } s; | ||
| 238 | struct cvmx_iob_inb_data_match_s cn30xx; | ||
| 239 | struct cvmx_iob_inb_data_match_s cn31xx; | ||
| 240 | struct cvmx_iob_inb_data_match_s cn38xx; | ||
| 241 | struct cvmx_iob_inb_data_match_s cn38xxp2; | ||
| 242 | struct cvmx_iob_inb_data_match_s cn50xx; | ||
| 243 | struct cvmx_iob_inb_data_match_s cn52xx; | ||
| 244 | struct cvmx_iob_inb_data_match_s cn52xxp1; | ||
| 245 | struct cvmx_iob_inb_data_match_s cn56xx; | ||
| 246 | struct cvmx_iob_inb_data_match_s cn56xxp1; | ||
| 247 | struct cvmx_iob_inb_data_match_s cn58xx; | ||
| 248 | struct cvmx_iob_inb_data_match_s cn58xxp1; | ||
| 249 | }; | ||
| 250 | |||
| 251 | union cvmx_iob_inb_data_match_enb { | ||
| 252 | uint64_t u64; | ||
| 253 | struct cvmx_iob_inb_data_match_enb_s { | ||
| 254 | uint64_t data:64; | ||
| 255 | } s; | ||
| 256 | struct cvmx_iob_inb_data_match_enb_s cn30xx; | ||
| 257 | struct cvmx_iob_inb_data_match_enb_s cn31xx; | ||
| 258 | struct cvmx_iob_inb_data_match_enb_s cn38xx; | ||
| 259 | struct cvmx_iob_inb_data_match_enb_s cn38xxp2; | ||
| 260 | struct cvmx_iob_inb_data_match_enb_s cn50xx; | ||
| 261 | struct cvmx_iob_inb_data_match_enb_s cn52xx; | ||
| 262 | struct cvmx_iob_inb_data_match_enb_s cn52xxp1; | ||
| 263 | struct cvmx_iob_inb_data_match_enb_s cn56xx; | ||
| 264 | struct cvmx_iob_inb_data_match_enb_s cn56xxp1; | ||
| 265 | struct cvmx_iob_inb_data_match_enb_s cn58xx; | ||
| 266 | struct cvmx_iob_inb_data_match_enb_s cn58xxp1; | ||
| 267 | }; | ||
| 268 | |||
| 269 | union cvmx_iob_int_enb { | ||
| 270 | uint64_t u64; | ||
| 271 | struct cvmx_iob_int_enb_s { | ||
| 272 | uint64_t reserved_6_63:58; | ||
| 273 | uint64_t p_dat:1; | ||
| 274 | uint64_t np_dat:1; | ||
| 275 | uint64_t p_eop:1; | ||
| 276 | uint64_t p_sop:1; | ||
| 277 | uint64_t np_eop:1; | ||
| 278 | uint64_t np_sop:1; | ||
| 279 | } s; | ||
| 280 | struct cvmx_iob_int_enb_cn30xx { | ||
| 281 | uint64_t reserved_4_63:60; | ||
| 282 | uint64_t p_eop:1; | ||
| 283 | uint64_t p_sop:1; | ||
| 284 | uint64_t np_eop:1; | ||
| 285 | uint64_t np_sop:1; | ||
| 286 | } cn30xx; | ||
| 287 | struct cvmx_iob_int_enb_cn30xx cn31xx; | ||
| 288 | struct cvmx_iob_int_enb_cn30xx cn38xx; | ||
| 289 | struct cvmx_iob_int_enb_cn30xx cn38xxp2; | ||
| 290 | struct cvmx_iob_int_enb_s cn50xx; | ||
| 291 | struct cvmx_iob_int_enb_s cn52xx; | ||
| 292 | struct cvmx_iob_int_enb_s cn52xxp1; | ||
| 293 | struct cvmx_iob_int_enb_s cn56xx; | ||
| 294 | struct cvmx_iob_int_enb_s cn56xxp1; | ||
| 295 | struct cvmx_iob_int_enb_s cn58xx; | ||
| 296 | struct cvmx_iob_int_enb_s cn58xxp1; | ||
| 297 | }; | ||
| 298 | |||
| 299 | union cvmx_iob_int_sum { | ||
| 300 | uint64_t u64; | ||
| 301 | struct cvmx_iob_int_sum_s { | ||
| 302 | uint64_t reserved_6_63:58; | ||
| 303 | uint64_t p_dat:1; | ||
| 304 | uint64_t np_dat:1; | ||
| 305 | uint64_t p_eop:1; | ||
| 306 | uint64_t p_sop:1; | ||
| 307 | uint64_t np_eop:1; | ||
| 308 | uint64_t np_sop:1; | ||
| 309 | } s; | ||
| 310 | struct cvmx_iob_int_sum_cn30xx { | ||
| 311 | uint64_t reserved_4_63:60; | ||
| 312 | uint64_t p_eop:1; | ||
| 313 | uint64_t p_sop:1; | ||
| 314 | uint64_t np_eop:1; | ||
| 315 | uint64_t np_sop:1; | ||
| 316 | } cn30xx; | ||
| 317 | struct cvmx_iob_int_sum_cn30xx cn31xx; | ||
| 318 | struct cvmx_iob_int_sum_cn30xx cn38xx; | ||
| 319 | struct cvmx_iob_int_sum_cn30xx cn38xxp2; | ||
| 320 | struct cvmx_iob_int_sum_s cn50xx; | ||
| 321 | struct cvmx_iob_int_sum_s cn52xx; | ||
| 322 | struct cvmx_iob_int_sum_s cn52xxp1; | ||
| 323 | struct cvmx_iob_int_sum_s cn56xx; | ||
| 324 | struct cvmx_iob_int_sum_s cn56xxp1; | ||
| 325 | struct cvmx_iob_int_sum_s cn58xx; | ||
| 326 | struct cvmx_iob_int_sum_s cn58xxp1; | ||
| 327 | }; | ||
| 328 | |||
| 329 | union cvmx_iob_n2c_l2c_pri_cnt { | ||
| 330 | uint64_t u64; | ||
| 331 | struct cvmx_iob_n2c_l2c_pri_cnt_s { | ||
| 332 | uint64_t reserved_16_63:48; | ||
| 333 | uint64_t cnt_enb:1; | ||
| 334 | uint64_t cnt_val:15; | ||
| 335 | } s; | ||
| 336 | struct cvmx_iob_n2c_l2c_pri_cnt_s cn38xx; | ||
| 337 | struct cvmx_iob_n2c_l2c_pri_cnt_s cn38xxp2; | ||
| 338 | struct cvmx_iob_n2c_l2c_pri_cnt_s cn52xx; | ||
| 339 | struct cvmx_iob_n2c_l2c_pri_cnt_s cn52xxp1; | ||
| 340 | struct cvmx_iob_n2c_l2c_pri_cnt_s cn56xx; | ||
| 341 | struct cvmx_iob_n2c_l2c_pri_cnt_s cn56xxp1; | ||
| 342 | struct cvmx_iob_n2c_l2c_pri_cnt_s cn58xx; | ||
| 343 | struct cvmx_iob_n2c_l2c_pri_cnt_s cn58xxp1; | ||
| 344 | }; | ||
| 345 | |||
| 346 | union cvmx_iob_n2c_rsp_pri_cnt { | ||
| 347 | uint64_t u64; | ||
| 348 | struct cvmx_iob_n2c_rsp_pri_cnt_s { | ||
| 349 | uint64_t reserved_16_63:48; | ||
| 350 | uint64_t cnt_enb:1; | ||
| 351 | uint64_t cnt_val:15; | ||
| 352 | } s; | ||
| 353 | struct cvmx_iob_n2c_rsp_pri_cnt_s cn38xx; | ||
| 354 | struct cvmx_iob_n2c_rsp_pri_cnt_s cn38xxp2; | ||
| 355 | struct cvmx_iob_n2c_rsp_pri_cnt_s cn52xx; | ||
| 356 | struct cvmx_iob_n2c_rsp_pri_cnt_s cn52xxp1; | ||
| 357 | struct cvmx_iob_n2c_rsp_pri_cnt_s cn56xx; | ||
| 358 | struct cvmx_iob_n2c_rsp_pri_cnt_s cn56xxp1; | ||
| 359 | struct cvmx_iob_n2c_rsp_pri_cnt_s cn58xx; | ||
| 360 | struct cvmx_iob_n2c_rsp_pri_cnt_s cn58xxp1; | ||
| 361 | }; | ||
| 362 | |||
| 363 | union cvmx_iob_outb_com_pri_cnt { | ||
| 364 | uint64_t u64; | ||
| 365 | struct cvmx_iob_outb_com_pri_cnt_s { | ||
| 366 | uint64_t reserved_16_63:48; | ||
| 367 | uint64_t cnt_enb:1; | ||
| 368 | uint64_t cnt_val:15; | ||
| 369 | } s; | ||
| 370 | struct cvmx_iob_outb_com_pri_cnt_s cn38xx; | ||
| 371 | struct cvmx_iob_outb_com_pri_cnt_s cn38xxp2; | ||
| 372 | struct cvmx_iob_outb_com_pri_cnt_s cn52xx; | ||
| 373 | struct cvmx_iob_outb_com_pri_cnt_s cn52xxp1; | ||
| 374 | struct cvmx_iob_outb_com_pri_cnt_s cn56xx; | ||
| 375 | struct cvmx_iob_outb_com_pri_cnt_s cn56xxp1; | ||
| 376 | struct cvmx_iob_outb_com_pri_cnt_s cn58xx; | ||
| 377 | struct cvmx_iob_outb_com_pri_cnt_s cn58xxp1; | ||
| 378 | }; | ||
| 379 | |||
| 380 | union cvmx_iob_outb_control_match { | ||
| 381 | uint64_t u64; | ||
| 382 | struct cvmx_iob_outb_control_match_s { | ||
| 383 | uint64_t reserved_26_63:38; | ||
| 384 | uint64_t mask:8; | ||
| 385 | uint64_t eot:1; | ||
| 386 | uint64_t dst:8; | ||
| 387 | uint64_t src:9; | ||
| 388 | } s; | ||
| 389 | struct cvmx_iob_outb_control_match_s cn30xx; | ||
| 390 | struct cvmx_iob_outb_control_match_s cn31xx; | ||
| 391 | struct cvmx_iob_outb_control_match_s cn38xx; | ||
| 392 | struct cvmx_iob_outb_control_match_s cn38xxp2; | ||
| 393 | struct cvmx_iob_outb_control_match_s cn50xx; | ||
| 394 | struct cvmx_iob_outb_control_match_s cn52xx; | ||
| 395 | struct cvmx_iob_outb_control_match_s cn52xxp1; | ||
| 396 | struct cvmx_iob_outb_control_match_s cn56xx; | ||
| 397 | struct cvmx_iob_outb_control_match_s cn56xxp1; | ||
| 398 | struct cvmx_iob_outb_control_match_s cn58xx; | ||
| 399 | struct cvmx_iob_outb_control_match_s cn58xxp1; | ||
| 400 | }; | ||
| 401 | |||
| 402 | union cvmx_iob_outb_control_match_enb { | ||
| 403 | uint64_t u64; | ||
| 404 | struct cvmx_iob_outb_control_match_enb_s { | ||
| 405 | uint64_t reserved_26_63:38; | ||
| 406 | uint64_t mask:8; | ||
| 407 | uint64_t eot:1; | ||
| 408 | uint64_t dst:8; | ||
| 409 | uint64_t src:9; | ||
| 410 | } s; | ||
| 411 | struct cvmx_iob_outb_control_match_enb_s cn30xx; | ||
| 412 | struct cvmx_iob_outb_control_match_enb_s cn31xx; | ||
| 413 | struct cvmx_iob_outb_control_match_enb_s cn38xx; | ||
| 414 | struct cvmx_iob_outb_control_match_enb_s cn38xxp2; | ||
| 415 | struct cvmx_iob_outb_control_match_enb_s cn50xx; | ||
| 416 | struct cvmx_iob_outb_control_match_enb_s cn52xx; | ||
| 417 | struct cvmx_iob_outb_control_match_enb_s cn52xxp1; | ||
| 418 | struct cvmx_iob_outb_control_match_enb_s cn56xx; | ||
| 419 | struct cvmx_iob_outb_control_match_enb_s cn56xxp1; | ||
| 420 | struct cvmx_iob_outb_control_match_enb_s cn58xx; | ||
| 421 | struct cvmx_iob_outb_control_match_enb_s cn58xxp1; | ||
| 422 | }; | ||
| 423 | |||
| 424 | union cvmx_iob_outb_data_match { | ||
| 425 | uint64_t u64; | ||
| 426 | struct cvmx_iob_outb_data_match_s { | ||
| 427 | uint64_t data:64; | ||
| 428 | } s; | ||
| 429 | struct cvmx_iob_outb_data_match_s cn30xx; | ||
| 430 | struct cvmx_iob_outb_data_match_s cn31xx; | ||
| 431 | struct cvmx_iob_outb_data_match_s cn38xx; | ||
| 432 | struct cvmx_iob_outb_data_match_s cn38xxp2; | ||
| 433 | struct cvmx_iob_outb_data_match_s cn50xx; | ||
| 434 | struct cvmx_iob_outb_data_match_s cn52xx; | ||
| 435 | struct cvmx_iob_outb_data_match_s cn52xxp1; | ||
| 436 | struct cvmx_iob_outb_data_match_s cn56xx; | ||
| 437 | struct cvmx_iob_outb_data_match_s cn56xxp1; | ||
| 438 | struct cvmx_iob_outb_data_match_s cn58xx; | ||
| 439 | struct cvmx_iob_outb_data_match_s cn58xxp1; | ||
| 440 | }; | ||
| 441 | |||
| 442 | union cvmx_iob_outb_data_match_enb { | ||
| 443 | uint64_t u64; | ||
| 444 | struct cvmx_iob_outb_data_match_enb_s { | ||
| 445 | uint64_t data:64; | ||
| 446 | } s; | ||
| 447 | struct cvmx_iob_outb_data_match_enb_s cn30xx; | ||
| 448 | struct cvmx_iob_outb_data_match_enb_s cn31xx; | ||
| 449 | struct cvmx_iob_outb_data_match_enb_s cn38xx; | ||
| 450 | struct cvmx_iob_outb_data_match_enb_s cn38xxp2; | ||
| 451 | struct cvmx_iob_outb_data_match_enb_s cn50xx; | ||
| 452 | struct cvmx_iob_outb_data_match_enb_s cn52xx; | ||
| 453 | struct cvmx_iob_outb_data_match_enb_s cn52xxp1; | ||
| 454 | struct cvmx_iob_outb_data_match_enb_s cn56xx; | ||
| 455 | struct cvmx_iob_outb_data_match_enb_s cn56xxp1; | ||
| 456 | struct cvmx_iob_outb_data_match_enb_s cn58xx; | ||
| 457 | struct cvmx_iob_outb_data_match_enb_s cn58xxp1; | ||
| 458 | }; | ||
| 459 | |||
| 460 | union cvmx_iob_outb_fpa_pri_cnt { | ||
| 461 | uint64_t u64; | ||
| 462 | struct cvmx_iob_outb_fpa_pri_cnt_s { | ||
| 463 | uint64_t reserved_16_63:48; | ||
| 464 | uint64_t cnt_enb:1; | ||
| 465 | uint64_t cnt_val:15; | ||
| 466 | } s; | ||
| 467 | struct cvmx_iob_outb_fpa_pri_cnt_s cn38xx; | ||
| 468 | struct cvmx_iob_outb_fpa_pri_cnt_s cn38xxp2; | ||
| 469 | struct cvmx_iob_outb_fpa_pri_cnt_s cn52xx; | ||
| 470 | struct cvmx_iob_outb_fpa_pri_cnt_s cn52xxp1; | ||
| 471 | struct cvmx_iob_outb_fpa_pri_cnt_s cn56xx; | ||
| 472 | struct cvmx_iob_outb_fpa_pri_cnt_s cn56xxp1; | ||
| 473 | struct cvmx_iob_outb_fpa_pri_cnt_s cn58xx; | ||
| 474 | struct cvmx_iob_outb_fpa_pri_cnt_s cn58xxp1; | ||
| 475 | }; | ||
| 476 | |||
| 477 | union cvmx_iob_outb_req_pri_cnt { | ||
| 478 | uint64_t u64; | ||
| 479 | struct cvmx_iob_outb_req_pri_cnt_s { | ||
| 480 | uint64_t reserved_16_63:48; | ||
| 481 | uint64_t cnt_enb:1; | ||
| 482 | uint64_t cnt_val:15; | ||
| 483 | } s; | ||
| 484 | struct cvmx_iob_outb_req_pri_cnt_s cn38xx; | ||
| 485 | struct cvmx_iob_outb_req_pri_cnt_s cn38xxp2; | ||
| 486 | struct cvmx_iob_outb_req_pri_cnt_s cn52xx; | ||
| 487 | struct cvmx_iob_outb_req_pri_cnt_s cn52xxp1; | ||
| 488 | struct cvmx_iob_outb_req_pri_cnt_s cn56xx; | ||
| 489 | struct cvmx_iob_outb_req_pri_cnt_s cn56xxp1; | ||
| 490 | struct cvmx_iob_outb_req_pri_cnt_s cn58xx; | ||
| 491 | struct cvmx_iob_outb_req_pri_cnt_s cn58xxp1; | ||
| 492 | }; | ||
| 493 | |||
| 494 | union cvmx_iob_p2c_req_pri_cnt { | ||
| 495 | uint64_t u64; | ||
| 496 | struct cvmx_iob_p2c_req_pri_cnt_s { | ||
| 497 | uint64_t reserved_16_63:48; | ||
| 498 | uint64_t cnt_enb:1; | ||
| 499 | uint64_t cnt_val:15; | ||
| 500 | } s; | ||
| 501 | struct cvmx_iob_p2c_req_pri_cnt_s cn38xx; | ||
| 502 | struct cvmx_iob_p2c_req_pri_cnt_s cn38xxp2; | ||
| 503 | struct cvmx_iob_p2c_req_pri_cnt_s cn52xx; | ||
| 504 | struct cvmx_iob_p2c_req_pri_cnt_s cn52xxp1; | ||
| 505 | struct cvmx_iob_p2c_req_pri_cnt_s cn56xx; | ||
| 506 | struct cvmx_iob_p2c_req_pri_cnt_s cn56xxp1; | ||
| 507 | struct cvmx_iob_p2c_req_pri_cnt_s cn58xx; | ||
| 508 | struct cvmx_iob_p2c_req_pri_cnt_s cn58xxp1; | ||
| 509 | }; | ||
| 510 | |||
| 511 | union cvmx_iob_pkt_err { | ||
| 512 | uint64_t u64; | ||
| 513 | struct cvmx_iob_pkt_err_s { | ||
| 514 | uint64_t reserved_6_63:58; | ||
| 515 | uint64_t port:6; | ||
| 516 | } s; | ||
| 517 | struct cvmx_iob_pkt_err_s cn30xx; | ||
| 518 | struct cvmx_iob_pkt_err_s cn31xx; | ||
| 519 | struct cvmx_iob_pkt_err_s cn38xx; | ||
| 520 | struct cvmx_iob_pkt_err_s cn38xxp2; | ||
| 521 | struct cvmx_iob_pkt_err_s cn50xx; | ||
| 522 | struct cvmx_iob_pkt_err_s cn52xx; | ||
| 523 | struct cvmx_iob_pkt_err_s cn52xxp1; | ||
| 524 | struct cvmx_iob_pkt_err_s cn56xx; | ||
| 525 | struct cvmx_iob_pkt_err_s cn56xxp1; | ||
| 526 | struct cvmx_iob_pkt_err_s cn58xx; | ||
| 527 | struct cvmx_iob_pkt_err_s cn58xxp1; | ||
| 528 | }; | ||
| 529 | |||
| 530 | #endif | ||
diff --git a/arch/mips/include/asm/octeon/cvmx-ipd-defs.h b/arch/mips/include/asm/octeon/cvmx-ipd-defs.h new file mode 100644 index 000000000000..f8b8fc657d2c --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-ipd-defs.h | |||
| @@ -0,0 +1,877 @@ | |||
| 1 | /***********************license start*************** | ||
| 2 | * Author: Cavium Networks | ||
| 3 | * | ||
| 4 | * Contact: support@caviumnetworks.com | ||
| 5 | * This file is part of the OCTEON SDK | ||
| 6 | * | ||
| 7 | * Copyright (c) 2003-2008 Cavium Networks | ||
| 8 | * | ||
| 9 | * This file is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License, Version 2, as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | * | ||
| 13 | * This file is distributed in the hope that it will be useful, but | ||
| 14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
| 15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
| 16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
| 17 | * details. | ||
| 18 | * | ||
| 19 | * You should have received a copy of the GNU General Public License | ||
| 20 | * along with this file; if not, write to the Free Software | ||
| 21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 22 | * or visit http://www.gnu.org/licenses/. | ||
| 23 | * | ||
| 24 | * This file may also be available under a different license from Cavium. | ||
| 25 | * Contact Cavium Networks for more information | ||
| 26 | ***********************license end**************************************/ | ||
| 27 | |||
| 28 | #ifndef __CVMX_IPD_DEFS_H__ | ||
| 29 | #define __CVMX_IPD_DEFS_H__ | ||
| 30 | |||
| 31 | #define CVMX_IPD_1ST_MBUFF_SKIP \ | ||
| 32 | CVMX_ADD_IO_SEG(0x00014F0000000000ull) | ||
| 33 | #define CVMX_IPD_1st_NEXT_PTR_BACK \ | ||
| 34 | CVMX_ADD_IO_SEG(0x00014F0000000150ull) | ||
| 35 | #define CVMX_IPD_2nd_NEXT_PTR_BACK \ | ||
| 36 | CVMX_ADD_IO_SEG(0x00014F0000000158ull) | ||
| 37 | #define CVMX_IPD_BIST_STATUS \ | ||
| 38 | CVMX_ADD_IO_SEG(0x00014F00000007F8ull) | ||
| 39 | #define CVMX_IPD_BP_PRT_RED_END \ | ||
| 40 | CVMX_ADD_IO_SEG(0x00014F0000000328ull) | ||
| 41 | #define CVMX_IPD_CLK_COUNT \ | ||
| 42 | CVMX_ADD_IO_SEG(0x00014F0000000338ull) | ||
| 43 | #define CVMX_IPD_CTL_STATUS \ | ||
| 44 | CVMX_ADD_IO_SEG(0x00014F0000000018ull) | ||
| 45 | #define CVMX_IPD_INT_ENB \ | ||
| 46 | CVMX_ADD_IO_SEG(0x00014F0000000160ull) | ||
| 47 | #define CVMX_IPD_INT_SUM \ | ||
| 48 | CVMX_ADD_IO_SEG(0x00014F0000000168ull) | ||
| 49 | #define CVMX_IPD_NOT_1ST_MBUFF_SKIP \ | ||
| 50 | CVMX_ADD_IO_SEG(0x00014F0000000008ull) | ||
| 51 | #define CVMX_IPD_PACKET_MBUFF_SIZE \ | ||
| 52 | CVMX_ADD_IO_SEG(0x00014F0000000010ull) | ||
| 53 | #define CVMX_IPD_PKT_PTR_VALID \ | ||
| 54 | CVMX_ADD_IO_SEG(0x00014F0000000358ull) | ||
| 55 | #define CVMX_IPD_PORTX_BP_PAGE_CNT(offset) \ | ||
| 56 | CVMX_ADD_IO_SEG(0x00014F0000000028ull + (((offset) & 63) * 8)) | ||
| 57 | #define CVMX_IPD_PORTX_BP_PAGE_CNT2(offset) \ | ||
| 58 | CVMX_ADD_IO_SEG(0x00014F0000000368ull + (((offset) & 63) * 8) - 8 * 36) | ||
| 59 | #define CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(offset) \ | ||
| 60 | CVMX_ADD_IO_SEG(0x00014F0000000388ull + (((offset) & 63) * 8) - 8 * 36) | ||
| 61 | #define CVMX_IPD_PORT_BP_COUNTERS_PAIRX(offset) \ | ||
| 62 | CVMX_ADD_IO_SEG(0x00014F00000001B8ull + (((offset) & 63) * 8)) | ||
| 63 | #define CVMX_IPD_PORT_QOS_INTX(offset) \ | ||
| 64 | CVMX_ADD_IO_SEG(0x00014F0000000808ull + (((offset) & 7) * 8)) | ||
| 65 | #define CVMX_IPD_PORT_QOS_INT_ENBX(offset) \ | ||
| 66 | CVMX_ADD_IO_SEG(0x00014F0000000848ull + (((offset) & 7) * 8)) | ||
| 67 | #define CVMX_IPD_PORT_QOS_X_CNT(offset) \ | ||
| 68 | CVMX_ADD_IO_SEG(0x00014F0000000888ull + (((offset) & 511) * 8)) | ||
| 69 | #define CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL \ | ||
| 70 | CVMX_ADD_IO_SEG(0x00014F0000000348ull) | ||
| 71 | #define CVMX_IPD_PRC_PORT_PTR_FIFO_CTL \ | ||
| 72 | CVMX_ADD_IO_SEG(0x00014F0000000350ull) | ||
| 73 | #define CVMX_IPD_PTR_COUNT \ | ||
| 74 | CVMX_ADD_IO_SEG(0x00014F0000000320ull) | ||
| 75 | #define CVMX_IPD_PWP_PTR_FIFO_CTL \ | ||
| 76 | CVMX_ADD_IO_SEG(0x00014F0000000340ull) | ||
| 77 | #define CVMX_IPD_QOS0_RED_MARKS \ | ||
| 78 | CVMX_ADD_IO_SEG(0x00014F0000000178ull) | ||
| 79 | #define CVMX_IPD_QOS1_RED_MARKS \ | ||
| 80 | CVMX_ADD_IO_SEG(0x00014F0000000180ull) | ||
| 81 | #define CVMX_IPD_QOS2_RED_MARKS \ | ||
| 82 | CVMX_ADD_IO_SEG(0x00014F0000000188ull) | ||
| 83 | #define CVMX_IPD_QOS3_RED_MARKS \ | ||
| 84 | CVMX_ADD_IO_SEG(0x00014F0000000190ull) | ||
| 85 | #define CVMX_IPD_QOS4_RED_MARKS \ | ||
| 86 | CVMX_ADD_IO_SEG(0x00014F0000000198ull) | ||
| 87 | #define CVMX_IPD_QOS5_RED_MARKS \ | ||
| 88 | CVMX_ADD_IO_SEG(0x00014F00000001A0ull) | ||
| 89 | #define CVMX_IPD_QOS6_RED_MARKS \ | ||
| 90 | CVMX_ADD_IO_SEG(0x00014F00000001A8ull) | ||
| 91 | #define CVMX_IPD_QOS7_RED_MARKS \ | ||
| 92 | CVMX_ADD_IO_SEG(0x00014F00000001B0ull) | ||
| 93 | #define CVMX_IPD_QOSX_RED_MARKS(offset) \ | ||
| 94 | CVMX_ADD_IO_SEG(0x00014F0000000178ull + (((offset) & 7) * 8)) | ||
| 95 | #define CVMX_IPD_QUE0_FREE_PAGE_CNT \ | ||
| 96 | CVMX_ADD_IO_SEG(0x00014F0000000330ull) | ||
| 97 | #define CVMX_IPD_RED_PORT_ENABLE \ | ||
| 98 | CVMX_ADD_IO_SEG(0x00014F00000002D8ull) | ||
| 99 | #define CVMX_IPD_RED_PORT_ENABLE2 \ | ||
| 100 | CVMX_ADD_IO_SEG(0x00014F00000003A8ull) | ||
| 101 | #define CVMX_IPD_RED_QUE0_PARAM \ | ||
| 102 | CVMX_ADD_IO_SEG(0x00014F00000002E0ull) | ||
| 103 | #define CVMX_IPD_RED_QUE1_PARAM \ | ||
| 104 | CVMX_ADD_IO_SEG(0x00014F00000002E8ull) | ||
| 105 | #define CVMX_IPD_RED_QUE2_PARAM \ | ||
| 106 | CVMX_ADD_IO_SEG(0x00014F00000002F0ull) | ||
| 107 | #define CVMX_IPD_RED_QUE3_PARAM \ | ||
| 108 | CVMX_ADD_IO_SEG(0x00014F00000002F8ull) | ||
| 109 | #define CVMX_IPD_RED_QUE4_PARAM \ | ||
| 110 | CVMX_ADD_IO_SEG(0x00014F0000000300ull) | ||
| 111 | #define CVMX_IPD_RED_QUE5_PARAM \ | ||
| 112 | CVMX_ADD_IO_SEG(0x00014F0000000308ull) | ||
| 113 | #define CVMX_IPD_RED_QUE6_PARAM \ | ||
| 114 | CVMX_ADD_IO_SEG(0x00014F0000000310ull) | ||
| 115 | #define CVMX_IPD_RED_QUE7_PARAM \ | ||
| 116 | CVMX_ADD_IO_SEG(0x00014F0000000318ull) | ||
| 117 | #define CVMX_IPD_RED_QUEX_PARAM(offset) \ | ||
| 118 | CVMX_ADD_IO_SEG(0x00014F00000002E0ull + (((offset) & 7) * 8)) | ||
| 119 | #define CVMX_IPD_SUB_PORT_BP_PAGE_CNT \ | ||
| 120 | CVMX_ADD_IO_SEG(0x00014F0000000148ull) | ||
| 121 | #define CVMX_IPD_SUB_PORT_FCS \ | ||
| 122 | CVMX_ADD_IO_SEG(0x00014F0000000170ull) | ||
| 123 | #define CVMX_IPD_SUB_PORT_QOS_CNT \ | ||
| 124 | CVMX_ADD_IO_SEG(0x00014F0000000800ull) | ||
| 125 | #define CVMX_IPD_WQE_FPA_QUEUE \ | ||
| 126 | CVMX_ADD_IO_SEG(0x00014F0000000020ull) | ||
| 127 | #define CVMX_IPD_WQE_PTR_VALID \ | ||
| 128 | CVMX_ADD_IO_SEG(0x00014F0000000360ull) | ||
| 129 | |||
| 130 | union cvmx_ipd_1st_mbuff_skip { | ||
| 131 | uint64_t u64; | ||
| 132 | struct cvmx_ipd_1st_mbuff_skip_s { | ||
| 133 | uint64_t reserved_6_63:58; | ||
| 134 | uint64_t skip_sz:6; | ||
| 135 | } s; | ||
| 136 | struct cvmx_ipd_1st_mbuff_skip_s cn30xx; | ||
| 137 | struct cvmx_ipd_1st_mbuff_skip_s cn31xx; | ||
| 138 | struct cvmx_ipd_1st_mbuff_skip_s cn38xx; | ||
| 139 | struct cvmx_ipd_1st_mbuff_skip_s cn38xxp2; | ||
| 140 | struct cvmx_ipd_1st_mbuff_skip_s cn50xx; | ||
| 141 | struct cvmx_ipd_1st_mbuff_skip_s cn52xx; | ||
| 142 | struct cvmx_ipd_1st_mbuff_skip_s cn52xxp1; | ||
| 143 | struct cvmx_ipd_1st_mbuff_skip_s cn56xx; | ||
| 144 | struct cvmx_ipd_1st_mbuff_skip_s cn56xxp1; | ||
| 145 | struct cvmx_ipd_1st_mbuff_skip_s cn58xx; | ||
| 146 | struct cvmx_ipd_1st_mbuff_skip_s cn58xxp1; | ||
| 147 | }; | ||
| 148 | |||
| 149 | union cvmx_ipd_1st_next_ptr_back { | ||
| 150 | uint64_t u64; | ||
| 151 | struct cvmx_ipd_1st_next_ptr_back_s { | ||
| 152 | uint64_t reserved_4_63:60; | ||
| 153 | uint64_t back:4; | ||
| 154 | } s; | ||
| 155 | struct cvmx_ipd_1st_next_ptr_back_s cn30xx; | ||
| 156 | struct cvmx_ipd_1st_next_ptr_back_s cn31xx; | ||
| 157 | struct cvmx_ipd_1st_next_ptr_back_s cn38xx; | ||
| 158 | struct cvmx_ipd_1st_next_ptr_back_s cn38xxp2; | ||
| 159 | struct cvmx_ipd_1st_next_ptr_back_s cn50xx; | ||
| 160 | struct cvmx_ipd_1st_next_ptr_back_s cn52xx; | ||
| 161 | struct cvmx_ipd_1st_next_ptr_back_s cn52xxp1; | ||
| 162 | struct cvmx_ipd_1st_next_ptr_back_s cn56xx; | ||
| 163 | struct cvmx_ipd_1st_next_ptr_back_s cn56xxp1; | ||
| 164 | struct cvmx_ipd_1st_next_ptr_back_s cn58xx; | ||
| 165 | struct cvmx_ipd_1st_next_ptr_back_s cn58xxp1; | ||
| 166 | }; | ||
| 167 | |||
| 168 | union cvmx_ipd_2nd_next_ptr_back { | ||
| 169 | uint64_t u64; | ||
| 170 | struct cvmx_ipd_2nd_next_ptr_back_s { | ||
| 171 | uint64_t reserved_4_63:60; | ||
| 172 | uint64_t back:4; | ||
| 173 | } s; | ||
| 174 | struct cvmx_ipd_2nd_next_ptr_back_s cn30xx; | ||
| 175 | struct cvmx_ipd_2nd_next_ptr_back_s cn31xx; | ||
| 176 | struct cvmx_ipd_2nd_next_ptr_back_s cn38xx; | ||
| 177 | struct cvmx_ipd_2nd_next_ptr_back_s cn38xxp2; | ||
| 178 | struct cvmx_ipd_2nd_next_ptr_back_s cn50xx; | ||
| 179 | struct cvmx_ipd_2nd_next_ptr_back_s cn52xx; | ||
| 180 | struct cvmx_ipd_2nd_next_ptr_back_s cn52xxp1; | ||
| 181 | struct cvmx_ipd_2nd_next_ptr_back_s cn56xx; | ||
| 182 | struct cvmx_ipd_2nd_next_ptr_back_s cn56xxp1; | ||
| 183 | struct cvmx_ipd_2nd_next_ptr_back_s cn58xx; | ||
| 184 | struct cvmx_ipd_2nd_next_ptr_back_s cn58xxp1; | ||
| 185 | }; | ||
| 186 | |||
| 187 | union cvmx_ipd_bist_status { | ||
| 188 | uint64_t u64; | ||
| 189 | struct cvmx_ipd_bist_status_s { | ||
| 190 | uint64_t reserved_18_63:46; | ||
| 191 | uint64_t csr_mem:1; | ||
| 192 | uint64_t csr_ncmd:1; | ||
| 193 | uint64_t pwq_wqed:1; | ||
| 194 | uint64_t pwq_wp1:1; | ||
| 195 | uint64_t pwq_pow:1; | ||
| 196 | uint64_t ipq_pbe1:1; | ||
| 197 | uint64_t ipq_pbe0:1; | ||
| 198 | uint64_t pbm3:1; | ||
| 199 | uint64_t pbm2:1; | ||
| 200 | uint64_t pbm1:1; | ||
| 201 | uint64_t pbm0:1; | ||
| 202 | uint64_t pbm_word:1; | ||
| 203 | uint64_t pwq1:1; | ||
| 204 | uint64_t pwq0:1; | ||
| 205 | uint64_t prc_off:1; | ||
| 206 | uint64_t ipd_old:1; | ||
| 207 | uint64_t ipd_new:1; | ||
| 208 | uint64_t pwp:1; | ||
| 209 | } s; | ||
| 210 | struct cvmx_ipd_bist_status_cn30xx { | ||
| 211 | uint64_t reserved_16_63:48; | ||
| 212 | uint64_t pwq_wqed:1; | ||
| 213 | uint64_t pwq_wp1:1; | ||
| 214 | uint64_t pwq_pow:1; | ||
| 215 | uint64_t ipq_pbe1:1; | ||
| 216 | uint64_t ipq_pbe0:1; | ||
| 217 | uint64_t pbm3:1; | ||
| 218 | uint64_t pbm2:1; | ||
| 219 | uint64_t pbm1:1; | ||
| 220 | uint64_t pbm0:1; | ||
| 221 | uint64_t pbm_word:1; | ||
| 222 | uint64_t pwq1:1; | ||
| 223 | uint64_t pwq0:1; | ||
| 224 | uint64_t prc_off:1; | ||
| 225 | uint64_t ipd_old:1; | ||
| 226 | uint64_t ipd_new:1; | ||
| 227 | uint64_t pwp:1; | ||
| 228 | } cn30xx; | ||
| 229 | struct cvmx_ipd_bist_status_cn30xx cn31xx; | ||
| 230 | struct cvmx_ipd_bist_status_cn30xx cn38xx; | ||
| 231 | struct cvmx_ipd_bist_status_cn30xx cn38xxp2; | ||
| 232 | struct cvmx_ipd_bist_status_cn30xx cn50xx; | ||
| 233 | struct cvmx_ipd_bist_status_s cn52xx; | ||
| 234 | struct cvmx_ipd_bist_status_s cn52xxp1; | ||
| 235 | struct cvmx_ipd_bist_status_s cn56xx; | ||
| 236 | struct cvmx_ipd_bist_status_s cn56xxp1; | ||
| 237 | struct cvmx_ipd_bist_status_cn30xx cn58xx; | ||
| 238 | struct cvmx_ipd_bist_status_cn30xx cn58xxp1; | ||
| 239 | }; | ||
| 240 | |||
| 241 | union cvmx_ipd_bp_prt_red_end { | ||
| 242 | uint64_t u64; | ||
| 243 | struct cvmx_ipd_bp_prt_red_end_s { | ||
| 244 | uint64_t reserved_40_63:24; | ||
| 245 | uint64_t prt_enb:40; | ||
| 246 | } s; | ||
| 247 | struct cvmx_ipd_bp_prt_red_end_cn30xx { | ||
| 248 | uint64_t reserved_36_63:28; | ||
| 249 | uint64_t prt_enb:36; | ||
| 250 | } cn30xx; | ||
| 251 | struct cvmx_ipd_bp_prt_red_end_cn30xx cn31xx; | ||
| 252 | struct cvmx_ipd_bp_prt_red_end_cn30xx cn38xx; | ||
| 253 | struct cvmx_ipd_bp_prt_red_end_cn30xx cn38xxp2; | ||
| 254 | struct cvmx_ipd_bp_prt_red_end_cn30xx cn50xx; | ||
| 255 | struct cvmx_ipd_bp_prt_red_end_s cn52xx; | ||
| 256 | struct cvmx_ipd_bp_prt_red_end_s cn52xxp1; | ||
| 257 | struct cvmx_ipd_bp_prt_red_end_s cn56xx; | ||
| 258 | struct cvmx_ipd_bp_prt_red_end_s cn56xxp1; | ||
| 259 | struct cvmx_ipd_bp_prt_red_end_cn30xx cn58xx; | ||
| 260 | struct cvmx_ipd_bp_prt_red_end_cn30xx cn58xxp1; | ||
| 261 | }; | ||
| 262 | |||
| 263 | union cvmx_ipd_clk_count { | ||
| 264 | uint64_t u64; | ||
| 265 | struct cvmx_ipd_clk_count_s { | ||
| 266 | uint64_t clk_cnt:64; | ||
| 267 | } s; | ||
| 268 | struct cvmx_ipd_clk_count_s cn30xx; | ||
| 269 | struct cvmx_ipd_clk_count_s cn31xx; | ||
| 270 | struct cvmx_ipd_clk_count_s cn38xx; | ||
| 271 | struct cvmx_ipd_clk_count_s cn38xxp2; | ||
| 272 | struct cvmx_ipd_clk_count_s cn50xx; | ||
| 273 | struct cvmx_ipd_clk_count_s cn52xx; | ||
| 274 | struct cvmx_ipd_clk_count_s cn52xxp1; | ||
| 275 | struct cvmx_ipd_clk_count_s cn56xx; | ||
| 276 | struct cvmx_ipd_clk_count_s cn56xxp1; | ||
| 277 | struct cvmx_ipd_clk_count_s cn58xx; | ||
| 278 | struct cvmx_ipd_clk_count_s cn58xxp1; | ||
| 279 | }; | ||
| 280 | |||
| 281 | union cvmx_ipd_ctl_status { | ||
| 282 | uint64_t u64; | ||
| 283 | struct cvmx_ipd_ctl_status_s { | ||
| 284 | uint64_t reserved_15_63:49; | ||
| 285 | uint64_t no_wptr:1; | ||
| 286 | uint64_t pq_apkt:1; | ||
| 287 | uint64_t pq_nabuf:1; | ||
| 288 | uint64_t ipd_full:1; | ||
| 289 | uint64_t pkt_off:1; | ||
| 290 | uint64_t len_m8:1; | ||
| 291 | uint64_t reset:1; | ||
| 292 | uint64_t addpkt:1; | ||
| 293 | uint64_t naddbuf:1; | ||
| 294 | uint64_t pkt_lend:1; | ||
| 295 | uint64_t wqe_lend:1; | ||
| 296 | uint64_t pbp_en:1; | ||
| 297 | uint64_t opc_mode:2; | ||
| 298 | uint64_t ipd_en:1; | ||
| 299 | } s; | ||
| 300 | struct cvmx_ipd_ctl_status_cn30xx { | ||
| 301 | uint64_t reserved_10_63:54; | ||
| 302 | uint64_t len_m8:1; | ||
| 303 | uint64_t reset:1; | ||
| 304 | uint64_t addpkt:1; | ||
| 305 | uint64_t naddbuf:1; | ||
| 306 | uint64_t pkt_lend:1; | ||
| 307 | uint64_t wqe_lend:1; | ||
| 308 | uint64_t pbp_en:1; | ||
| 309 | uint64_t opc_mode:2; | ||
| 310 | uint64_t ipd_en:1; | ||
| 311 | } cn30xx; | ||
| 312 | struct cvmx_ipd_ctl_status_cn30xx cn31xx; | ||
| 313 | struct cvmx_ipd_ctl_status_cn30xx cn38xx; | ||
| 314 | struct cvmx_ipd_ctl_status_cn38xxp2 { | ||
| 315 | uint64_t reserved_9_63:55; | ||
| 316 | uint64_t reset:1; | ||
| 317 | uint64_t addpkt:1; | ||
| 318 | uint64_t naddbuf:1; | ||
| 319 | uint64_t pkt_lend:1; | ||
| 320 | uint64_t wqe_lend:1; | ||
| 321 | uint64_t pbp_en:1; | ||
| 322 | uint64_t opc_mode:2; | ||
| 323 | uint64_t ipd_en:1; | ||
| 324 | } cn38xxp2; | ||
| 325 | struct cvmx_ipd_ctl_status_s cn50xx; | ||
| 326 | struct cvmx_ipd_ctl_status_s cn52xx; | ||
| 327 | struct cvmx_ipd_ctl_status_s cn52xxp1; | ||
| 328 | struct cvmx_ipd_ctl_status_s cn56xx; | ||
| 329 | struct cvmx_ipd_ctl_status_s cn56xxp1; | ||
| 330 | struct cvmx_ipd_ctl_status_cn58xx { | ||
| 331 | uint64_t reserved_12_63:52; | ||
| 332 | uint64_t ipd_full:1; | ||
| 333 | uint64_t pkt_off:1; | ||
| 334 | uint64_t len_m8:1; | ||
| 335 | uint64_t reset:1; | ||
| 336 | uint64_t addpkt:1; | ||
| 337 | uint64_t naddbuf:1; | ||
| 338 | uint64_t pkt_lend:1; | ||
| 339 | uint64_t wqe_lend:1; | ||
| 340 | uint64_t pbp_en:1; | ||
| 341 | uint64_t opc_mode:2; | ||
| 342 | uint64_t ipd_en:1; | ||
| 343 | } cn58xx; | ||
| 344 | struct cvmx_ipd_ctl_status_cn58xx cn58xxp1; | ||
| 345 | }; | ||
| 346 | |||
| 347 | union cvmx_ipd_int_enb { | ||
| 348 | uint64_t u64; | ||
| 349 | struct cvmx_ipd_int_enb_s { | ||
| 350 | uint64_t reserved_12_63:52; | ||
| 351 | uint64_t pq_sub:1; | ||
| 352 | uint64_t pq_add:1; | ||
| 353 | uint64_t bc_ovr:1; | ||
| 354 | uint64_t d_coll:1; | ||
| 355 | uint64_t c_coll:1; | ||
| 356 | uint64_t cc_ovr:1; | ||
| 357 | uint64_t dc_ovr:1; | ||
| 358 | uint64_t bp_sub:1; | ||
| 359 | uint64_t prc_par3:1; | ||
| 360 | uint64_t prc_par2:1; | ||
| 361 | uint64_t prc_par1:1; | ||
| 362 | uint64_t prc_par0:1; | ||
| 363 | } s; | ||
| 364 | struct cvmx_ipd_int_enb_cn30xx { | ||
| 365 | uint64_t reserved_5_63:59; | ||
| 366 | uint64_t bp_sub:1; | ||
| 367 | uint64_t prc_par3:1; | ||
| 368 | uint64_t prc_par2:1; | ||
| 369 | uint64_t prc_par1:1; | ||
| 370 | uint64_t prc_par0:1; | ||
| 371 | } cn30xx; | ||
| 372 | struct cvmx_ipd_int_enb_cn30xx cn31xx; | ||
| 373 | struct cvmx_ipd_int_enb_cn38xx { | ||
| 374 | uint64_t reserved_10_63:54; | ||
| 375 | uint64_t bc_ovr:1; | ||
| 376 | uint64_t d_coll:1; | ||
| 377 | uint64_t c_coll:1; | ||
| 378 | uint64_t cc_ovr:1; | ||
| 379 | uint64_t dc_ovr:1; | ||
| 380 | uint64_t bp_sub:1; | ||
| 381 | uint64_t prc_par3:1; | ||
| 382 | uint64_t prc_par2:1; | ||
| 383 | uint64_t prc_par1:1; | ||
| 384 | uint64_t prc_par0:1; | ||
| 385 | } cn38xx; | ||
| 386 | struct cvmx_ipd_int_enb_cn30xx cn38xxp2; | ||
| 387 | struct cvmx_ipd_int_enb_cn38xx cn50xx; | ||
| 388 | struct cvmx_ipd_int_enb_s cn52xx; | ||
| 389 | struct cvmx_ipd_int_enb_s cn52xxp1; | ||
| 390 | struct cvmx_ipd_int_enb_s cn56xx; | ||
| 391 | struct cvmx_ipd_int_enb_s cn56xxp1; | ||
| 392 | struct cvmx_ipd_int_enb_cn38xx cn58xx; | ||
| 393 | struct cvmx_ipd_int_enb_cn38xx cn58xxp1; | ||
| 394 | }; | ||
| 395 | |||
| 396 | union cvmx_ipd_int_sum { | ||
| 397 | uint64_t u64; | ||
| 398 | struct cvmx_ipd_int_sum_s { | ||
| 399 | uint64_t reserved_12_63:52; | ||
| 400 | uint64_t pq_sub:1; | ||
| 401 | uint64_t pq_add:1; | ||
| 402 | uint64_t bc_ovr:1; | ||
| 403 | uint64_t d_coll:1; | ||
| 404 | uint64_t c_coll:1; | ||
| 405 | uint64_t cc_ovr:1; | ||
| 406 | uint64_t dc_ovr:1; | ||
| 407 | uint64_t bp_sub:1; | ||
| 408 | uint64_t prc_par3:1; | ||
| 409 | uint64_t prc_par2:1; | ||
| 410 | uint64_t prc_par1:1; | ||
| 411 | uint64_t prc_par0:1; | ||
| 412 | } s; | ||
| 413 | struct cvmx_ipd_int_sum_cn30xx { | ||
| 414 | uint64_t reserved_5_63:59; | ||
| 415 | uint64_t bp_sub:1; | ||
| 416 | uint64_t prc_par3:1; | ||
| 417 | uint64_t prc_par2:1; | ||
| 418 | uint64_t prc_par1:1; | ||
| 419 | uint64_t prc_par0:1; | ||
| 420 | } cn30xx; | ||
| 421 | struct cvmx_ipd_int_sum_cn30xx cn31xx; | ||
| 422 | struct cvmx_ipd_int_sum_cn38xx { | ||
| 423 | uint64_t reserved_10_63:54; | ||
| 424 | uint64_t bc_ovr:1; | ||
| 425 | uint64_t d_coll:1; | ||
| 426 | uint64_t c_coll:1; | ||
| 427 | uint64_t cc_ovr:1; | ||
| 428 | uint64_t dc_ovr:1; | ||
| 429 | uint64_t bp_sub:1; | ||
| 430 | uint64_t prc_par3:1; | ||
| 431 | uint64_t prc_par2:1; | ||
| 432 | uint64_t prc_par1:1; | ||
| 433 | uint64_t prc_par0:1; | ||
| 434 | } cn38xx; | ||
| 435 | struct cvmx_ipd_int_sum_cn30xx cn38xxp2; | ||
| 436 | struct cvmx_ipd_int_sum_cn38xx cn50xx; | ||
| 437 | struct cvmx_ipd_int_sum_s cn52xx; | ||
| 438 | struct cvmx_ipd_int_sum_s cn52xxp1; | ||
| 439 | struct cvmx_ipd_int_sum_s cn56xx; | ||
| 440 | struct cvmx_ipd_int_sum_s cn56xxp1; | ||
| 441 | struct cvmx_ipd_int_sum_cn38xx cn58xx; | ||
| 442 | struct cvmx_ipd_int_sum_cn38xx cn58xxp1; | ||
| 443 | }; | ||
| 444 | |||
| 445 | union cvmx_ipd_not_1st_mbuff_skip { | ||
| 446 | uint64_t u64; | ||
| 447 | struct cvmx_ipd_not_1st_mbuff_skip_s { | ||
| 448 | uint64_t reserved_6_63:58; | ||
| 449 | uint64_t skip_sz:6; | ||
| 450 | } s; | ||
| 451 | struct cvmx_ipd_not_1st_mbuff_skip_s cn30xx; | ||
| 452 | struct cvmx_ipd_not_1st_mbuff_skip_s cn31xx; | ||
| 453 | struct cvmx_ipd_not_1st_mbuff_skip_s cn38xx; | ||
| 454 | struct cvmx_ipd_not_1st_mbuff_skip_s cn38xxp2; | ||
| 455 | struct cvmx_ipd_not_1st_mbuff_skip_s cn50xx; | ||
| 456 | struct cvmx_ipd_not_1st_mbuff_skip_s cn52xx; | ||
| 457 | struct cvmx_ipd_not_1st_mbuff_skip_s cn52xxp1; | ||
| 458 | struct cvmx_ipd_not_1st_mbuff_skip_s cn56xx; | ||
| 459 | struct cvmx_ipd_not_1st_mbuff_skip_s cn56xxp1; | ||
| 460 | struct cvmx_ipd_not_1st_mbuff_skip_s cn58xx; | ||
| 461 | struct cvmx_ipd_not_1st_mbuff_skip_s cn58xxp1; | ||
| 462 | }; | ||
| 463 | |||
| 464 | union cvmx_ipd_packet_mbuff_size { | ||
| 465 | uint64_t u64; | ||
| 466 | struct cvmx_ipd_packet_mbuff_size_s { | ||
| 467 | uint64_t reserved_12_63:52; | ||
| 468 | uint64_t mb_size:12; | ||
| 469 | } s; | ||
| 470 | struct cvmx_ipd_packet_mbuff_size_s cn30xx; | ||
| 471 | struct cvmx_ipd_packet_mbuff_size_s cn31xx; | ||
| 472 | struct cvmx_ipd_packet_mbuff_size_s cn38xx; | ||
| 473 | struct cvmx_ipd_packet_mbuff_size_s cn38xxp2; | ||
| 474 | struct cvmx_ipd_packet_mbuff_size_s cn50xx; | ||
| 475 | struct cvmx_ipd_packet_mbuff_size_s cn52xx; | ||
| 476 | struct cvmx_ipd_packet_mbuff_size_s cn52xxp1; | ||
| 477 | struct cvmx_ipd_packet_mbuff_size_s cn56xx; | ||
| 478 | struct cvmx_ipd_packet_mbuff_size_s cn56xxp1; | ||
| 479 | struct cvmx_ipd_packet_mbuff_size_s cn58xx; | ||
| 480 | struct cvmx_ipd_packet_mbuff_size_s cn58xxp1; | ||
| 481 | }; | ||
| 482 | |||
| 483 | union cvmx_ipd_pkt_ptr_valid { | ||
| 484 | uint64_t u64; | ||
| 485 | struct cvmx_ipd_pkt_ptr_valid_s { | ||
| 486 | uint64_t reserved_29_63:35; | ||
| 487 | uint64_t ptr:29; | ||
| 488 | } s; | ||
| 489 | struct cvmx_ipd_pkt_ptr_valid_s cn30xx; | ||
| 490 | struct cvmx_ipd_pkt_ptr_valid_s cn31xx; | ||
| 491 | struct cvmx_ipd_pkt_ptr_valid_s cn38xx; | ||
| 492 | struct cvmx_ipd_pkt_ptr_valid_s cn50xx; | ||
| 493 | struct cvmx_ipd_pkt_ptr_valid_s cn52xx; | ||
| 494 | struct cvmx_ipd_pkt_ptr_valid_s cn52xxp1; | ||
| 495 | struct cvmx_ipd_pkt_ptr_valid_s cn56xx; | ||
| 496 | struct cvmx_ipd_pkt_ptr_valid_s cn56xxp1; | ||
| 497 | struct cvmx_ipd_pkt_ptr_valid_s cn58xx; | ||
| 498 | struct cvmx_ipd_pkt_ptr_valid_s cn58xxp1; | ||
| 499 | }; | ||
| 500 | |||
| 501 | union cvmx_ipd_portx_bp_page_cnt { | ||
| 502 | uint64_t u64; | ||
| 503 | struct cvmx_ipd_portx_bp_page_cnt_s { | ||
| 504 | uint64_t reserved_18_63:46; | ||
| 505 | uint64_t bp_enb:1; | ||
| 506 | uint64_t page_cnt:17; | ||
| 507 | } s; | ||
| 508 | struct cvmx_ipd_portx_bp_page_cnt_s cn30xx; | ||
| 509 | struct cvmx_ipd_portx_bp_page_cnt_s cn31xx; | ||
| 510 | struct cvmx_ipd_portx_bp_page_cnt_s cn38xx; | ||
| 511 | struct cvmx_ipd_portx_bp_page_cnt_s cn38xxp2; | ||
| 512 | struct cvmx_ipd_portx_bp_page_cnt_s cn50xx; | ||
| 513 | struct cvmx_ipd_portx_bp_page_cnt_s cn52xx; | ||
| 514 | struct cvmx_ipd_portx_bp_page_cnt_s cn52xxp1; | ||
| 515 | struct cvmx_ipd_portx_bp_page_cnt_s cn56xx; | ||
| 516 | struct cvmx_ipd_portx_bp_page_cnt_s cn56xxp1; | ||
| 517 | struct cvmx_ipd_portx_bp_page_cnt_s cn58xx; | ||
| 518 | struct cvmx_ipd_portx_bp_page_cnt_s cn58xxp1; | ||
| 519 | }; | ||
| 520 | |||
| 521 | union cvmx_ipd_portx_bp_page_cnt2 { | ||
| 522 | uint64_t u64; | ||
| 523 | struct cvmx_ipd_portx_bp_page_cnt2_s { | ||
| 524 | uint64_t reserved_18_63:46; | ||
| 525 | uint64_t bp_enb:1; | ||
| 526 | uint64_t page_cnt:17; | ||
| 527 | } s; | ||
| 528 | struct cvmx_ipd_portx_bp_page_cnt2_s cn52xx; | ||
| 529 | struct cvmx_ipd_portx_bp_page_cnt2_s cn52xxp1; | ||
| 530 | struct cvmx_ipd_portx_bp_page_cnt2_s cn56xx; | ||
| 531 | struct cvmx_ipd_portx_bp_page_cnt2_s cn56xxp1; | ||
| 532 | }; | ||
| 533 | |||
| 534 | union cvmx_ipd_port_bp_counters2_pairx { | ||
| 535 | uint64_t u64; | ||
| 536 | struct cvmx_ipd_port_bp_counters2_pairx_s { | ||
| 537 | uint64_t reserved_25_63:39; | ||
| 538 | uint64_t cnt_val:25; | ||
| 539 | } s; | ||
| 540 | struct cvmx_ipd_port_bp_counters2_pairx_s cn52xx; | ||
| 541 | struct cvmx_ipd_port_bp_counters2_pairx_s cn52xxp1; | ||
| 542 | struct cvmx_ipd_port_bp_counters2_pairx_s cn56xx; | ||
| 543 | struct cvmx_ipd_port_bp_counters2_pairx_s cn56xxp1; | ||
| 544 | }; | ||
| 545 | |||
| 546 | union cvmx_ipd_port_bp_counters_pairx { | ||
| 547 | uint64_t u64; | ||
| 548 | struct cvmx_ipd_port_bp_counters_pairx_s { | ||
| 549 | uint64_t reserved_25_63:39; | ||
| 550 | uint64_t cnt_val:25; | ||
| 551 | } s; | ||
| 552 | struct cvmx_ipd_port_bp_counters_pairx_s cn30xx; | ||
| 553 | struct cvmx_ipd_port_bp_counters_pairx_s cn31xx; | ||
| 554 | struct cvmx_ipd_port_bp_counters_pairx_s cn38xx; | ||
| 555 | struct cvmx_ipd_port_bp_counters_pairx_s cn38xxp2; | ||
| 556 | struct cvmx_ipd_port_bp_counters_pairx_s cn50xx; | ||
| 557 | struct cvmx_ipd_port_bp_counters_pairx_s cn52xx; | ||
| 558 | struct cvmx_ipd_port_bp_counters_pairx_s cn52xxp1; | ||
| 559 | struct cvmx_ipd_port_bp_counters_pairx_s cn56xx; | ||
| 560 | struct cvmx_ipd_port_bp_counters_pairx_s cn56xxp1; | ||
| 561 | struct cvmx_ipd_port_bp_counters_pairx_s cn58xx; | ||
| 562 | struct cvmx_ipd_port_bp_counters_pairx_s cn58xxp1; | ||
| 563 | }; | ||
| 564 | |||
| 565 | union cvmx_ipd_port_qos_x_cnt { | ||
| 566 | uint64_t u64; | ||
| 567 | struct cvmx_ipd_port_qos_x_cnt_s { | ||
| 568 | uint64_t wmark:32; | ||
| 569 | uint64_t cnt:32; | ||
| 570 | } s; | ||
| 571 | struct cvmx_ipd_port_qos_x_cnt_s cn52xx; | ||
| 572 | struct cvmx_ipd_port_qos_x_cnt_s cn52xxp1; | ||
| 573 | struct cvmx_ipd_port_qos_x_cnt_s cn56xx; | ||
| 574 | struct cvmx_ipd_port_qos_x_cnt_s cn56xxp1; | ||
| 575 | }; | ||
| 576 | |||
| 577 | union cvmx_ipd_port_qos_intx { | ||
| 578 | uint64_t u64; | ||
| 579 | struct cvmx_ipd_port_qos_intx_s { | ||
| 580 | uint64_t intr:64; | ||
| 581 | } s; | ||
| 582 | struct cvmx_ipd_port_qos_intx_s cn52xx; | ||
| 583 | struct cvmx_ipd_port_qos_intx_s cn52xxp1; | ||
| 584 | struct cvmx_ipd_port_qos_intx_s cn56xx; | ||
| 585 | struct cvmx_ipd_port_qos_intx_s cn56xxp1; | ||
| 586 | }; | ||
| 587 | |||
| 588 | union cvmx_ipd_port_qos_int_enbx { | ||
| 589 | uint64_t u64; | ||
| 590 | struct cvmx_ipd_port_qos_int_enbx_s { | ||
| 591 | uint64_t enb:64; | ||
| 592 | } s; | ||
| 593 | struct cvmx_ipd_port_qos_int_enbx_s cn52xx; | ||
| 594 | struct cvmx_ipd_port_qos_int_enbx_s cn52xxp1; | ||
| 595 | struct cvmx_ipd_port_qos_int_enbx_s cn56xx; | ||
| 596 | struct cvmx_ipd_port_qos_int_enbx_s cn56xxp1; | ||
| 597 | }; | ||
| 598 | |||
| 599 | union cvmx_ipd_prc_hold_ptr_fifo_ctl { | ||
| 600 | uint64_t u64; | ||
| 601 | struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s { | ||
| 602 | uint64_t reserved_39_63:25; | ||
| 603 | uint64_t max_pkt:3; | ||
| 604 | uint64_t praddr:3; | ||
| 605 | uint64_t ptr:29; | ||
| 606 | uint64_t cena:1; | ||
| 607 | uint64_t raddr:3; | ||
| 608 | } s; | ||
| 609 | struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn30xx; | ||
| 610 | struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn31xx; | ||
| 611 | struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn38xx; | ||
| 612 | struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn50xx; | ||
| 613 | struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn52xx; | ||
| 614 | struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn52xxp1; | ||
| 615 | struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn56xx; | ||
| 616 | struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn56xxp1; | ||
| 617 | struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xx; | ||
| 618 | struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xxp1; | ||
| 619 | }; | ||
| 620 | |||
| 621 | union cvmx_ipd_prc_port_ptr_fifo_ctl { | ||
| 622 | uint64_t u64; | ||
| 623 | struct cvmx_ipd_prc_port_ptr_fifo_ctl_s { | ||
| 624 | uint64_t reserved_44_63:20; | ||
| 625 | uint64_t max_pkt:7; | ||
| 626 | uint64_t ptr:29; | ||
| 627 | uint64_t cena:1; | ||
| 628 | uint64_t raddr:7; | ||
| 629 | } s; | ||
| 630 | struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn30xx; | ||
| 631 | struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn31xx; | ||
| 632 | struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn38xx; | ||
| 633 | struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn50xx; | ||
| 634 | struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn52xx; | ||
| 635 | struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn52xxp1; | ||
| 636 | struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn56xx; | ||
| 637 | struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn56xxp1; | ||
| 638 | struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xx; | ||
| 639 | struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xxp1; | ||
| 640 | }; | ||
| 641 | |||
| 642 | union cvmx_ipd_ptr_count { | ||
| 643 | uint64_t u64; | ||
| 644 | struct cvmx_ipd_ptr_count_s { | ||
| 645 | uint64_t reserved_19_63:45; | ||
| 646 | uint64_t pktv_cnt:1; | ||
| 647 | uint64_t wqev_cnt:1; | ||
| 648 | uint64_t pfif_cnt:3; | ||
| 649 | uint64_t pkt_pcnt:7; | ||
| 650 | uint64_t wqe_pcnt:7; | ||
| 651 | } s; | ||
| 652 | struct cvmx_ipd_ptr_count_s cn30xx; | ||
| 653 | struct cvmx_ipd_ptr_count_s cn31xx; | ||
| 654 | struct cvmx_ipd_ptr_count_s cn38xx; | ||
| 655 | struct cvmx_ipd_ptr_count_s cn38xxp2; | ||
| 656 | struct cvmx_ipd_ptr_count_s cn50xx; | ||
| 657 | struct cvmx_ipd_ptr_count_s cn52xx; | ||
| 658 | struct cvmx_ipd_ptr_count_s cn52xxp1; | ||
| 659 | struct cvmx_ipd_ptr_count_s cn56xx; | ||
| 660 | struct cvmx_ipd_ptr_count_s cn56xxp1; | ||
| 661 | struct cvmx_ipd_ptr_count_s cn58xx; | ||
| 662 | struct cvmx_ipd_ptr_count_s cn58xxp1; | ||
| 663 | }; | ||
| 664 | |||
| 665 | union cvmx_ipd_pwp_ptr_fifo_ctl { | ||
| 666 | uint64_t u64; | ||
| 667 | struct cvmx_ipd_pwp_ptr_fifo_ctl_s { | ||
| 668 | uint64_t reserved_61_63:3; | ||
| 669 | uint64_t max_cnts:7; | ||
| 670 | uint64_t wraddr:8; | ||
| 671 | uint64_t praddr:8; | ||
| 672 | uint64_t ptr:29; | ||
| 673 | uint64_t cena:1; | ||
| 674 | uint64_t raddr:8; | ||
| 675 | } s; | ||
| 676 | struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn30xx; | ||
| 677 | struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn31xx; | ||
| 678 | struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn38xx; | ||
| 679 | struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn50xx; | ||
| 680 | struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn52xx; | ||
| 681 | struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn52xxp1; | ||
| 682 | struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn56xx; | ||
| 683 | struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn56xxp1; | ||
| 684 | struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn58xx; | ||
| 685 | struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn58xxp1; | ||
| 686 | }; | ||
| 687 | |||
| 688 | union cvmx_ipd_qosx_red_marks { | ||
| 689 | uint64_t u64; | ||
| 690 | struct cvmx_ipd_qosx_red_marks_s { | ||
| 691 | uint64_t drop:32; | ||
| 692 | uint64_t pass:32; | ||
| 693 | } s; | ||
| 694 | struct cvmx_ipd_qosx_red_marks_s cn30xx; | ||
| 695 | struct cvmx_ipd_qosx_red_marks_s cn31xx; | ||
| 696 | struct cvmx_ipd_qosx_red_marks_s cn38xx; | ||
| 697 | struct cvmx_ipd_qosx_red_marks_s cn38xxp2; | ||
| 698 | struct cvmx_ipd_qosx_red_marks_s cn50xx; | ||
| 699 | struct cvmx_ipd_qosx_red_marks_s cn52xx; | ||
| 700 | struct cvmx_ipd_qosx_red_marks_s cn52xxp1; | ||
| 701 | struct cvmx_ipd_qosx_red_marks_s cn56xx; | ||
| 702 | struct cvmx_ipd_qosx_red_marks_s cn56xxp1; | ||
| 703 | struct cvmx_ipd_qosx_red_marks_s cn58xx; | ||
| 704 | struct cvmx_ipd_qosx_red_marks_s cn58xxp1; | ||
| 705 | }; | ||
| 706 | |||
| 707 | union cvmx_ipd_que0_free_page_cnt { | ||
| 708 | uint64_t u64; | ||
| 709 | struct cvmx_ipd_que0_free_page_cnt_s { | ||
| 710 | uint64_t reserved_32_63:32; | ||
| 711 | uint64_t q0_pcnt:32; | ||
| 712 | } s; | ||
| 713 | struct cvmx_ipd_que0_free_page_cnt_s cn30xx; | ||
| 714 | struct cvmx_ipd_que0_free_page_cnt_s cn31xx; | ||
| 715 | struct cvmx_ipd_que0_free_page_cnt_s cn38xx; | ||
| 716 | struct cvmx_ipd_que0_free_page_cnt_s cn38xxp2; | ||
| 717 | struct cvmx_ipd_que0_free_page_cnt_s cn50xx; | ||
| 718 | struct cvmx_ipd_que0_free_page_cnt_s cn52xx; | ||
| 719 | struct cvmx_ipd_que0_free_page_cnt_s cn52xxp1; | ||
| 720 | struct cvmx_ipd_que0_free_page_cnt_s cn56xx; | ||
| 721 | struct cvmx_ipd_que0_free_page_cnt_s cn56xxp1; | ||
| 722 | struct cvmx_ipd_que0_free_page_cnt_s cn58xx; | ||
| 723 | struct cvmx_ipd_que0_free_page_cnt_s cn58xxp1; | ||
| 724 | }; | ||
| 725 | |||
| 726 | union cvmx_ipd_red_port_enable { | ||
| 727 | uint64_t u64; | ||
| 728 | struct cvmx_ipd_red_port_enable_s { | ||
| 729 | uint64_t prb_dly:14; | ||
| 730 | uint64_t avg_dly:14; | ||
| 731 | uint64_t prt_enb:36; | ||
| 732 | } s; | ||
| 733 | struct cvmx_ipd_red_port_enable_s cn30xx; | ||
| 734 | struct cvmx_ipd_red_port_enable_s cn31xx; | ||
| 735 | struct cvmx_ipd_red_port_enable_s cn38xx; | ||
| 736 | struct cvmx_ipd_red_port_enable_s cn38xxp2; | ||
| 737 | struct cvmx_ipd_red_port_enable_s cn50xx; | ||
| 738 | struct cvmx_ipd_red_port_enable_s cn52xx; | ||
| 739 | struct cvmx_ipd_red_port_enable_s cn52xxp1; | ||
| 740 | struct cvmx_ipd_red_port_enable_s cn56xx; | ||
| 741 | struct cvmx_ipd_red_port_enable_s cn56xxp1; | ||
| 742 | struct cvmx_ipd_red_port_enable_s cn58xx; | ||
| 743 | struct cvmx_ipd_red_port_enable_s cn58xxp1; | ||
| 744 | }; | ||
| 745 | |||
| 746 | union cvmx_ipd_red_port_enable2 { | ||
| 747 | uint64_t u64; | ||
| 748 | struct cvmx_ipd_red_port_enable2_s { | ||
| 749 | uint64_t reserved_4_63:60; | ||
| 750 | uint64_t prt_enb:4; | ||
| 751 | } s; | ||
| 752 | struct cvmx_ipd_red_port_enable2_s cn52xx; | ||
| 753 | struct cvmx_ipd_red_port_enable2_s cn52xxp1; | ||
| 754 | struct cvmx_ipd_red_port_enable2_s cn56xx; | ||
| 755 | struct cvmx_ipd_red_port_enable2_s cn56xxp1; | ||
| 756 | }; | ||
| 757 | |||
| 758 | union cvmx_ipd_red_quex_param { | ||
| 759 | uint64_t u64; | ||
| 760 | struct cvmx_ipd_red_quex_param_s { | ||
| 761 | uint64_t reserved_49_63:15; | ||
| 762 | uint64_t use_pcnt:1; | ||
| 763 | uint64_t new_con:8; | ||
| 764 | uint64_t avg_con:8; | ||
| 765 | uint64_t prb_con:32; | ||
| 766 | } s; | ||
| 767 | struct cvmx_ipd_red_quex_param_s cn30xx; | ||
| 768 | struct cvmx_ipd_red_quex_param_s cn31xx; | ||
| 769 | struct cvmx_ipd_red_quex_param_s cn38xx; | ||
| 770 | struct cvmx_ipd_red_quex_param_s cn38xxp2; | ||
| 771 | struct cvmx_ipd_red_quex_param_s cn50xx; | ||
| 772 | struct cvmx_ipd_red_quex_param_s cn52xx; | ||
| 773 | struct cvmx_ipd_red_quex_param_s cn52xxp1; | ||
| 774 | struct cvmx_ipd_red_quex_param_s cn56xx; | ||
| 775 | struct cvmx_ipd_red_quex_param_s cn56xxp1; | ||
| 776 | struct cvmx_ipd_red_quex_param_s cn58xx; | ||
| 777 | struct cvmx_ipd_red_quex_param_s cn58xxp1; | ||
| 778 | }; | ||
| 779 | |||
| 780 | union cvmx_ipd_sub_port_bp_page_cnt { | ||
| 781 | uint64_t u64; | ||
| 782 | struct cvmx_ipd_sub_port_bp_page_cnt_s { | ||
| 783 | uint64_t reserved_31_63:33; | ||
| 784 | uint64_t port:6; | ||
| 785 | uint64_t page_cnt:25; | ||
| 786 | } s; | ||
| 787 | struct cvmx_ipd_sub_port_bp_page_cnt_s cn30xx; | ||
| 788 | struct cvmx_ipd_sub_port_bp_page_cnt_s cn31xx; | ||
| 789 | struct cvmx_ipd_sub_port_bp_page_cnt_s cn38xx; | ||
| 790 | struct cvmx_ipd_sub_port_bp_page_cnt_s cn38xxp2; | ||
| 791 | struct cvmx_ipd_sub_port_bp_page_cnt_s cn50xx; | ||
| 792 | struct cvmx_ipd_sub_port_bp_page_cnt_s cn52xx; | ||
| 793 | struct cvmx_ipd_sub_port_bp_page_cnt_s cn52xxp1; | ||
| 794 | struct cvmx_ipd_sub_port_bp_page_cnt_s cn56xx; | ||
| 795 | struct cvmx_ipd_sub_port_bp_page_cnt_s cn56xxp1; | ||
| 796 | struct cvmx_ipd_sub_port_bp_page_cnt_s cn58xx; | ||
| 797 | struct cvmx_ipd_sub_port_bp_page_cnt_s cn58xxp1; | ||
| 798 | }; | ||
| 799 | |||
| 800 | union cvmx_ipd_sub_port_fcs { | ||
| 801 | uint64_t u64; | ||
| 802 | struct cvmx_ipd_sub_port_fcs_s { | ||
| 803 | uint64_t reserved_40_63:24; | ||
| 804 | uint64_t port_bit2:4; | ||
| 805 | uint64_t reserved_32_35:4; | ||
| 806 | uint64_t port_bit:32; | ||
| 807 | } s; | ||
| 808 | struct cvmx_ipd_sub_port_fcs_cn30xx { | ||
| 809 | uint64_t reserved_3_63:61; | ||
| 810 | uint64_t port_bit:3; | ||
| 811 | } cn30xx; | ||
| 812 | struct cvmx_ipd_sub_port_fcs_cn30xx cn31xx; | ||
| 813 | struct cvmx_ipd_sub_port_fcs_cn38xx { | ||
| 814 | uint64_t reserved_32_63:32; | ||
| 815 | uint64_t port_bit:32; | ||
| 816 | } cn38xx; | ||
| 817 | struct cvmx_ipd_sub_port_fcs_cn38xx cn38xxp2; | ||
| 818 | struct cvmx_ipd_sub_port_fcs_cn30xx cn50xx; | ||
| 819 | struct cvmx_ipd_sub_port_fcs_s cn52xx; | ||
| 820 | struct cvmx_ipd_sub_port_fcs_s cn52xxp1; | ||
| 821 | struct cvmx_ipd_sub_port_fcs_s cn56xx; | ||
| 822 | struct cvmx_ipd_sub_port_fcs_s cn56xxp1; | ||
| 823 | struct cvmx_ipd_sub_port_fcs_cn38xx cn58xx; | ||
| 824 | struct cvmx_ipd_sub_port_fcs_cn38xx cn58xxp1; | ||
| 825 | }; | ||
| 826 | |||
| 827 | union cvmx_ipd_sub_port_qos_cnt { | ||
| 828 | uint64_t u64; | ||
| 829 | struct cvmx_ipd_sub_port_qos_cnt_s { | ||
| 830 | uint64_t reserved_41_63:23; | ||
| 831 | uint64_t port_qos:9; | ||
| 832 | uint64_t cnt:32; | ||
| 833 | } s; | ||
| 834 | struct cvmx_ipd_sub_port_qos_cnt_s cn52xx; | ||
| 835 | struct cvmx_ipd_sub_port_qos_cnt_s cn52xxp1; | ||
| 836 | struct cvmx_ipd_sub_port_qos_cnt_s cn56xx; | ||
| 837 | struct cvmx_ipd_sub_port_qos_cnt_s cn56xxp1; | ||
| 838 | }; | ||
| 839 | |||
| 840 | union cvmx_ipd_wqe_fpa_queue { | ||
| 841 | uint64_t u64; | ||
| 842 | struct cvmx_ipd_wqe_fpa_queue_s { | ||
| 843 | uint64_t reserved_3_63:61; | ||
| 844 | uint64_t wqe_pool:3; | ||
| 845 | } s; | ||
| 846 | struct cvmx_ipd_wqe_fpa_queue_s cn30xx; | ||
| 847 | struct cvmx_ipd_wqe_fpa_queue_s cn31xx; | ||
| 848 | struct cvmx_ipd_wqe_fpa_queue_s cn38xx; | ||
| 849 | struct cvmx_ipd_wqe_fpa_queue_s cn38xxp2; | ||
| 850 | struct cvmx_ipd_wqe_fpa_queue_s cn50xx; | ||
| 851 | struct cvmx_ipd_wqe_fpa_queue_s cn52xx; | ||
| 852 | struct cvmx_ipd_wqe_fpa_queue_s cn52xxp1; | ||
| 853 | struct cvmx_ipd_wqe_fpa_queue_s cn56xx; | ||
| 854 | struct cvmx_ipd_wqe_fpa_queue_s cn56xxp1; | ||
| 855 | struct cvmx_ipd_wqe_fpa_queue_s cn58xx; | ||
| 856 | struct cvmx_ipd_wqe_fpa_queue_s cn58xxp1; | ||
| 857 | }; | ||
| 858 | |||
| 859 | union cvmx_ipd_wqe_ptr_valid { | ||
| 860 | uint64_t u64; | ||
| 861 | struct cvmx_ipd_wqe_ptr_valid_s { | ||
| 862 | uint64_t reserved_29_63:35; | ||
| 863 | uint64_t ptr:29; | ||
| 864 | } s; | ||
| 865 | struct cvmx_ipd_wqe_ptr_valid_s cn30xx; | ||
| 866 | struct cvmx_ipd_wqe_ptr_valid_s cn31xx; | ||
| 867 | struct cvmx_ipd_wqe_ptr_valid_s cn38xx; | ||
| 868 | struct cvmx_ipd_wqe_ptr_valid_s cn50xx; | ||
| 869 | struct cvmx_ipd_wqe_ptr_valid_s cn52xx; | ||
| 870 | struct cvmx_ipd_wqe_ptr_valid_s cn52xxp1; | ||
| 871 | struct cvmx_ipd_wqe_ptr_valid_s cn56xx; | ||
| 872 | struct cvmx_ipd_wqe_ptr_valid_s cn56xxp1; | ||
| 873 | struct cvmx_ipd_wqe_ptr_valid_s cn58xx; | ||
| 874 | struct cvmx_ipd_wqe_ptr_valid_s cn58xxp1; | ||
| 875 | }; | ||
| 876 | |||
| 877 | #endif | ||
diff --git a/arch/mips/include/asm/octeon/cvmx-l2c-defs.h b/arch/mips/include/asm/octeon/cvmx-l2c-defs.h new file mode 100644 index 000000000000..337583842b51 --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-l2c-defs.h | |||
| @@ -0,0 +1,963 @@ | |||
| 1 | /***********************license start*************** | ||
| 2 | * Author: Cavium Networks | ||
| 3 | * | ||
| 4 | * Contact: support@caviumnetworks.com | ||
| 5 | * This file is part of the OCTEON SDK | ||
| 6 | * | ||
| 7 | * Copyright (c) 2003-2008 Cavium Networks | ||
| 8 | * | ||
| 9 | * This file is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License, Version 2, as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | * | ||
| 13 | * This file is distributed in the hope that it will be useful, but | ||
| 14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
| 15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
| 16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
| 17 | * details. | ||
| 18 | * | ||
| 19 | * You should have received a copy of the GNU General Public License | ||
| 20 | * along with this file; if not, write to the Free Software | ||
| 21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 22 | * or visit http://www.gnu.org/licenses/. | ||
| 23 | * | ||
| 24 | * This file may also be available under a different license from Cavium. | ||
| 25 | * Contact Cavium Networks for more information | ||
| 26 | ***********************license end**************************************/ | ||
| 27 | |||
| 28 | #ifndef __CVMX_L2C_DEFS_H__ | ||
| 29 | #define __CVMX_L2C_DEFS_H__ | ||
| 30 | |||
| 31 | #define CVMX_L2C_BST0 \ | ||
| 32 | CVMX_ADD_IO_SEG(0x00011800800007F8ull) | ||
| 33 | #define CVMX_L2C_BST1 \ | ||
| 34 | CVMX_ADD_IO_SEG(0x00011800800007F0ull) | ||
| 35 | #define CVMX_L2C_BST2 \ | ||
| 36 | CVMX_ADD_IO_SEG(0x00011800800007E8ull) | ||
| 37 | #define CVMX_L2C_CFG \ | ||
| 38 | CVMX_ADD_IO_SEG(0x0001180080000000ull) | ||
| 39 | #define CVMX_L2C_DBG \ | ||
| 40 | CVMX_ADD_IO_SEG(0x0001180080000030ull) | ||
| 41 | #define CVMX_L2C_DUT \ | ||
| 42 | CVMX_ADD_IO_SEG(0x0001180080000050ull) | ||
| 43 | #define CVMX_L2C_GRPWRR0 \ | ||
| 44 | CVMX_ADD_IO_SEG(0x00011800800000C8ull) | ||
| 45 | #define CVMX_L2C_GRPWRR1 \ | ||
| 46 | CVMX_ADD_IO_SEG(0x00011800800000D0ull) | ||
| 47 | #define CVMX_L2C_INT_EN \ | ||
| 48 | CVMX_ADD_IO_SEG(0x0001180080000100ull) | ||
| 49 | #define CVMX_L2C_INT_STAT \ | ||
| 50 | CVMX_ADD_IO_SEG(0x00011800800000F8ull) | ||
| 51 | #define CVMX_L2C_LCKBASE \ | ||
| 52 | CVMX_ADD_IO_SEG(0x0001180080000058ull) | ||
| 53 | #define CVMX_L2C_LCKOFF \ | ||
| 54 | CVMX_ADD_IO_SEG(0x0001180080000060ull) | ||
| 55 | #define CVMX_L2C_LFB0 \ | ||
| 56 | CVMX_ADD_IO_SEG(0x0001180080000038ull) | ||
| 57 | #define CVMX_L2C_LFB1 \ | ||
| 58 | CVMX_ADD_IO_SEG(0x0001180080000040ull) | ||
| 59 | #define CVMX_L2C_LFB2 \ | ||
| 60 | CVMX_ADD_IO_SEG(0x0001180080000048ull) | ||
| 61 | #define CVMX_L2C_LFB3 \ | ||
| 62 | CVMX_ADD_IO_SEG(0x00011800800000B8ull) | ||
| 63 | #define CVMX_L2C_OOB \ | ||
| 64 | CVMX_ADD_IO_SEG(0x00011800800000D8ull) | ||
| 65 | #define CVMX_L2C_OOB1 \ | ||
| 66 | CVMX_ADD_IO_SEG(0x00011800800000E0ull) | ||
| 67 | #define CVMX_L2C_OOB2 \ | ||
| 68 | CVMX_ADD_IO_SEG(0x00011800800000E8ull) | ||
| 69 | #define CVMX_L2C_OOB3 \ | ||
| 70 | CVMX_ADD_IO_SEG(0x00011800800000F0ull) | ||
| 71 | #define CVMX_L2C_PFC0 \ | ||
| 72 | CVMX_ADD_IO_SEG(0x0001180080000098ull) | ||
| 73 | #define CVMX_L2C_PFC1 \ | ||
| 74 | CVMX_ADD_IO_SEG(0x00011800800000A0ull) | ||
| 75 | #define CVMX_L2C_PFC2 \ | ||
| 76 | CVMX_ADD_IO_SEG(0x00011800800000A8ull) | ||
| 77 | #define CVMX_L2C_PFC3 \ | ||
| 78 | CVMX_ADD_IO_SEG(0x00011800800000B0ull) | ||
| 79 | #define CVMX_L2C_PFCTL \ | ||
| 80 | CVMX_ADD_IO_SEG(0x0001180080000090ull) | ||
| 81 | #define CVMX_L2C_PFCX(offset) \ | ||
| 82 | CVMX_ADD_IO_SEG(0x0001180080000098ull + (((offset) & 3) * 8)) | ||
| 83 | #define CVMX_L2C_PPGRP \ | ||
| 84 | CVMX_ADD_IO_SEG(0x00011800800000C0ull) | ||
| 85 | #define CVMX_L2C_SPAR0 \ | ||
| 86 | CVMX_ADD_IO_SEG(0x0001180080000068ull) | ||
| 87 | #define CVMX_L2C_SPAR1 \ | ||
| 88 | CVMX_ADD_IO_SEG(0x0001180080000070ull) | ||
| 89 | #define CVMX_L2C_SPAR2 \ | ||
| 90 | CVMX_ADD_IO_SEG(0x0001180080000078ull) | ||
| 91 | #define CVMX_L2C_SPAR3 \ | ||
| 92 | CVMX_ADD_IO_SEG(0x0001180080000080ull) | ||
| 93 | #define CVMX_L2C_SPAR4 \ | ||
| 94 | CVMX_ADD_IO_SEG(0x0001180080000088ull) | ||
| 95 | |||
| 96 | union cvmx_l2c_bst0 { | ||
| 97 | uint64_t u64; | ||
| 98 | struct cvmx_l2c_bst0_s { | ||
| 99 | uint64_t reserved_24_63:40; | ||
| 100 | uint64_t dtbnk:1; | ||
| 101 | uint64_t wlb_msk:4; | ||
| 102 | uint64_t dtcnt:13; | ||
| 103 | uint64_t dt:1; | ||
| 104 | uint64_t stin_msk:1; | ||
| 105 | uint64_t wlb_dat:4; | ||
| 106 | } s; | ||
| 107 | struct cvmx_l2c_bst0_cn30xx { | ||
| 108 | uint64_t reserved_23_63:41; | ||
| 109 | uint64_t wlb_msk:4; | ||
| 110 | uint64_t reserved_15_18:4; | ||
| 111 | uint64_t dtcnt:9; | ||
| 112 | uint64_t dt:1; | ||
| 113 | uint64_t reserved_4_4:1; | ||
| 114 | uint64_t wlb_dat:4; | ||
| 115 | } cn30xx; | ||
| 116 | struct cvmx_l2c_bst0_cn31xx { | ||
| 117 | uint64_t reserved_23_63:41; | ||
| 118 | uint64_t wlb_msk:4; | ||
| 119 | uint64_t reserved_16_18:3; | ||
| 120 | uint64_t dtcnt:10; | ||
| 121 | uint64_t dt:1; | ||
| 122 | uint64_t stin_msk:1; | ||
| 123 | uint64_t wlb_dat:4; | ||
| 124 | } cn31xx; | ||
| 125 | struct cvmx_l2c_bst0_cn38xx { | ||
| 126 | uint64_t reserved_19_63:45; | ||
| 127 | uint64_t dtcnt:13; | ||
| 128 | uint64_t dt:1; | ||
| 129 | uint64_t stin_msk:1; | ||
| 130 | uint64_t wlb_dat:4; | ||
| 131 | } cn38xx; | ||
| 132 | struct cvmx_l2c_bst0_cn38xx cn38xxp2; | ||
| 133 | struct cvmx_l2c_bst0_cn50xx { | ||
| 134 | uint64_t reserved_24_63:40; | ||
| 135 | uint64_t dtbnk:1; | ||
| 136 | uint64_t wlb_msk:4; | ||
| 137 | uint64_t reserved_16_18:3; | ||
| 138 | uint64_t dtcnt:10; | ||
| 139 | uint64_t dt:1; | ||
| 140 | uint64_t stin_msk:1; | ||
| 141 | uint64_t wlb_dat:4; | ||
| 142 | } cn50xx; | ||
| 143 | struct cvmx_l2c_bst0_cn50xx cn52xx; | ||
| 144 | struct cvmx_l2c_bst0_cn50xx cn52xxp1; | ||
| 145 | struct cvmx_l2c_bst0_s cn56xx; | ||
| 146 | struct cvmx_l2c_bst0_s cn56xxp1; | ||
| 147 | struct cvmx_l2c_bst0_s cn58xx; | ||
| 148 | struct cvmx_l2c_bst0_s cn58xxp1; | ||
| 149 | }; | ||
| 150 | |||
| 151 | union cvmx_l2c_bst1 { | ||
| 152 | uint64_t u64; | ||
| 153 | struct cvmx_l2c_bst1_s { | ||
| 154 | uint64_t reserved_9_63:55; | ||
| 155 | uint64_t l2t:9; | ||
| 156 | } s; | ||
| 157 | struct cvmx_l2c_bst1_cn30xx { | ||
| 158 | uint64_t reserved_16_63:48; | ||
| 159 | uint64_t vwdf:4; | ||
| 160 | uint64_t lrf:2; | ||
| 161 | uint64_t vab_vwcf:1; | ||
| 162 | uint64_t reserved_5_8:4; | ||
| 163 | uint64_t l2t:5; | ||
| 164 | } cn30xx; | ||
| 165 | struct cvmx_l2c_bst1_cn30xx cn31xx; | ||
| 166 | struct cvmx_l2c_bst1_cn38xx { | ||
| 167 | uint64_t reserved_16_63:48; | ||
| 168 | uint64_t vwdf:4; | ||
| 169 | uint64_t lrf:2; | ||
| 170 | uint64_t vab_vwcf:1; | ||
| 171 | uint64_t l2t:9; | ||
| 172 | } cn38xx; | ||
| 173 | struct cvmx_l2c_bst1_cn38xx cn38xxp2; | ||
| 174 | struct cvmx_l2c_bst1_cn38xx cn50xx; | ||
| 175 | struct cvmx_l2c_bst1_cn52xx { | ||
| 176 | uint64_t reserved_19_63:45; | ||
| 177 | uint64_t plc2:1; | ||
| 178 | uint64_t plc1:1; | ||
| 179 | uint64_t plc0:1; | ||
| 180 | uint64_t vwdf:4; | ||
| 181 | uint64_t reserved_11_11:1; | ||
| 182 | uint64_t ilc:1; | ||
| 183 | uint64_t vab_vwcf:1; | ||
| 184 | uint64_t l2t:9; | ||
| 185 | } cn52xx; | ||
| 186 | struct cvmx_l2c_bst1_cn52xx cn52xxp1; | ||
| 187 | struct cvmx_l2c_bst1_cn56xx { | ||
| 188 | uint64_t reserved_24_63:40; | ||
| 189 | uint64_t plc2:1; | ||
| 190 | uint64_t plc1:1; | ||
| 191 | uint64_t plc0:1; | ||
| 192 | uint64_t ilc:1; | ||
| 193 | uint64_t vwdf1:4; | ||
| 194 | uint64_t vwdf0:4; | ||
| 195 | uint64_t vab_vwcf1:1; | ||
| 196 | uint64_t reserved_10_10:1; | ||
| 197 | uint64_t vab_vwcf0:1; | ||
| 198 | uint64_t l2t:9; | ||
| 199 | } cn56xx; | ||
| 200 | struct cvmx_l2c_bst1_cn56xx cn56xxp1; | ||
| 201 | struct cvmx_l2c_bst1_cn38xx cn58xx; | ||
| 202 | struct cvmx_l2c_bst1_cn38xx cn58xxp1; | ||
| 203 | }; | ||
| 204 | |||
| 205 | union cvmx_l2c_bst2 { | ||
| 206 | uint64_t u64; | ||
| 207 | struct cvmx_l2c_bst2_s { | ||
| 208 | uint64_t reserved_16_63:48; | ||
| 209 | uint64_t mrb:4; | ||
| 210 | uint64_t reserved_4_11:8; | ||
| 211 | uint64_t ipcbst:1; | ||
| 212 | uint64_t picbst:1; | ||
| 213 | uint64_t xrdmsk:1; | ||
| 214 | uint64_t xrddat:1; | ||
| 215 | } s; | ||
| 216 | struct cvmx_l2c_bst2_cn30xx { | ||
| 217 | uint64_t reserved_16_63:48; | ||
| 218 | uint64_t mrb:4; | ||
| 219 | uint64_t rmdf:4; | ||
| 220 | uint64_t reserved_4_7:4; | ||
| 221 | uint64_t ipcbst:1; | ||
| 222 | uint64_t reserved_2_2:1; | ||
| 223 | uint64_t xrdmsk:1; | ||
| 224 | uint64_t xrddat:1; | ||
| 225 | } cn30xx; | ||
| 226 | struct cvmx_l2c_bst2_cn30xx cn31xx; | ||
| 227 | struct cvmx_l2c_bst2_cn38xx { | ||
| 228 | uint64_t reserved_16_63:48; | ||
| 229 | uint64_t mrb:4; | ||
| 230 | uint64_t rmdf:4; | ||
| 231 | uint64_t rhdf:4; | ||
| 232 | uint64_t ipcbst:1; | ||
| 233 | uint64_t picbst:1; | ||
| 234 | uint64_t xrdmsk:1; | ||
| 235 | uint64_t xrddat:1; | ||
| 236 | } cn38xx; | ||
| 237 | struct cvmx_l2c_bst2_cn38xx cn38xxp2; | ||
| 238 | struct cvmx_l2c_bst2_cn30xx cn50xx; | ||
| 239 | struct cvmx_l2c_bst2_cn30xx cn52xx; | ||
| 240 | struct cvmx_l2c_bst2_cn30xx cn52xxp1; | ||
| 241 | struct cvmx_l2c_bst2_cn56xx { | ||
| 242 | uint64_t reserved_16_63:48; | ||
| 243 | uint64_t mrb:4; | ||
| 244 | uint64_t rmdb:4; | ||
| 245 | uint64_t rhdb:4; | ||
| 246 | uint64_t ipcbst:1; | ||
| 247 | uint64_t picbst:1; | ||
| 248 | uint64_t xrdmsk:1; | ||
| 249 | uint64_t xrddat:1; | ||
| 250 | } cn56xx; | ||
| 251 | struct cvmx_l2c_bst2_cn56xx cn56xxp1; | ||
| 252 | struct cvmx_l2c_bst2_cn56xx cn58xx; | ||
| 253 | struct cvmx_l2c_bst2_cn56xx cn58xxp1; | ||
| 254 | }; | ||
| 255 | |||
| 256 | union cvmx_l2c_cfg { | ||
| 257 | uint64_t u64; | ||
| 258 | struct cvmx_l2c_cfg_s { | ||
| 259 | uint64_t reserved_20_63:44; | ||
| 260 | uint64_t bstrun:1; | ||
| 261 | uint64_t lbist:1; | ||
| 262 | uint64_t xor_bank:1; | ||
| 263 | uint64_t dpres1:1; | ||
| 264 | uint64_t dpres0:1; | ||
| 265 | uint64_t dfill_dis:1; | ||
| 266 | uint64_t fpexp:4; | ||
| 267 | uint64_t fpempty:1; | ||
| 268 | uint64_t fpen:1; | ||
| 269 | uint64_t idxalias:1; | ||
| 270 | uint64_t mwf_crd:4; | ||
| 271 | uint64_t rsp_arb_mode:1; | ||
| 272 | uint64_t rfb_arb_mode:1; | ||
| 273 | uint64_t lrf_arb_mode:1; | ||
| 274 | } s; | ||
| 275 | struct cvmx_l2c_cfg_cn30xx { | ||
| 276 | uint64_t reserved_14_63:50; | ||
| 277 | uint64_t fpexp:4; | ||
| 278 | uint64_t fpempty:1; | ||
| 279 | uint64_t fpen:1; | ||
| 280 | uint64_t idxalias:1; | ||
| 281 | uint64_t mwf_crd:4; | ||
| 282 | uint64_t rsp_arb_mode:1; | ||
| 283 | uint64_t rfb_arb_mode:1; | ||
| 284 | uint64_t lrf_arb_mode:1; | ||
| 285 | } cn30xx; | ||
| 286 | struct cvmx_l2c_cfg_cn30xx cn31xx; | ||
| 287 | struct cvmx_l2c_cfg_cn30xx cn38xx; | ||
| 288 | struct cvmx_l2c_cfg_cn30xx cn38xxp2; | ||
| 289 | struct cvmx_l2c_cfg_cn50xx { | ||
| 290 | uint64_t reserved_20_63:44; | ||
| 291 | uint64_t bstrun:1; | ||
| 292 | uint64_t lbist:1; | ||
| 293 | uint64_t reserved_14_17:4; | ||
| 294 | uint64_t fpexp:4; | ||
| 295 | uint64_t fpempty:1; | ||
| 296 | uint64_t fpen:1; | ||
| 297 | uint64_t idxalias:1; | ||
| 298 | uint64_t mwf_crd:4; | ||
| 299 | uint64_t rsp_arb_mode:1; | ||
| 300 | uint64_t rfb_arb_mode:1; | ||
| 301 | uint64_t lrf_arb_mode:1; | ||
| 302 | } cn50xx; | ||
| 303 | struct cvmx_l2c_cfg_cn50xx cn52xx; | ||
| 304 | struct cvmx_l2c_cfg_cn50xx cn52xxp1; | ||
| 305 | struct cvmx_l2c_cfg_s cn56xx; | ||
| 306 | struct cvmx_l2c_cfg_s cn56xxp1; | ||
| 307 | struct cvmx_l2c_cfg_cn58xx { | ||
| 308 | uint64_t reserved_20_63:44; | ||
| 309 | uint64_t bstrun:1; | ||
| 310 | uint64_t lbist:1; | ||
| 311 | uint64_t reserved_15_17:3; | ||
| 312 | uint64_t dfill_dis:1; | ||
| 313 | uint64_t fpexp:4; | ||
| 314 | uint64_t fpempty:1; | ||
| 315 | uint64_t fpen:1; | ||
| 316 | uint64_t idxalias:1; | ||
| 317 | uint64_t mwf_crd:4; | ||
| 318 | uint64_t rsp_arb_mode:1; | ||
| 319 | uint64_t rfb_arb_mode:1; | ||
| 320 | uint64_t lrf_arb_mode:1; | ||
| 321 | } cn58xx; | ||
| 322 | struct cvmx_l2c_cfg_cn58xxp1 { | ||
| 323 | uint64_t reserved_15_63:49; | ||
| 324 | uint64_t dfill_dis:1; | ||
| 325 | uint64_t fpexp:4; | ||
| 326 | uint64_t fpempty:1; | ||
| 327 | uint64_t fpen:1; | ||
| 328 | uint64_t idxalias:1; | ||
| 329 | uint64_t mwf_crd:4; | ||
| 330 | uint64_t rsp_arb_mode:1; | ||
| 331 | uint64_t rfb_arb_mode:1; | ||
| 332 | uint64_t lrf_arb_mode:1; | ||
| 333 | } cn58xxp1; | ||
| 334 | }; | ||
| 335 | |||
| 336 | union cvmx_l2c_dbg { | ||
| 337 | uint64_t u64; | ||
| 338 | struct cvmx_l2c_dbg_s { | ||
| 339 | uint64_t reserved_15_63:49; | ||
| 340 | uint64_t lfb_enum:4; | ||
| 341 | uint64_t lfb_dmp:1; | ||
| 342 | uint64_t ppnum:4; | ||
| 343 | uint64_t set:3; | ||
| 344 | uint64_t finv:1; | ||
| 345 | uint64_t l2d:1; | ||
| 346 | uint64_t l2t:1; | ||
| 347 | } s; | ||
| 348 | struct cvmx_l2c_dbg_cn30xx { | ||
| 349 | uint64_t reserved_13_63:51; | ||
| 350 | uint64_t lfb_enum:2; | ||
| 351 | uint64_t lfb_dmp:1; | ||
| 352 | uint64_t reserved_5_9:5; | ||
| 353 | uint64_t set:2; | ||
| 354 | uint64_t finv:1; | ||
| 355 | uint64_t l2d:1; | ||
| 356 | uint64_t l2t:1; | ||
| 357 | } cn30xx; | ||
| 358 | struct cvmx_l2c_dbg_cn31xx { | ||
| 359 | uint64_t reserved_14_63:50; | ||
| 360 | uint64_t lfb_enum:3; | ||
| 361 | uint64_t lfb_dmp:1; | ||
| 362 | uint64_t reserved_7_9:3; | ||
| 363 | uint64_t ppnum:1; | ||
| 364 | uint64_t reserved_5_5:1; | ||
| 365 | uint64_t set:2; | ||
| 366 | uint64_t finv:1; | ||
| 367 | uint64_t l2d:1; | ||
| 368 | uint64_t l2t:1; | ||
| 369 | } cn31xx; | ||
| 370 | struct cvmx_l2c_dbg_s cn38xx; | ||
| 371 | struct cvmx_l2c_dbg_s cn38xxp2; | ||
| 372 | struct cvmx_l2c_dbg_cn50xx { | ||
| 373 | uint64_t reserved_14_63:50; | ||
| 374 | uint64_t lfb_enum:3; | ||
| 375 | uint64_t lfb_dmp:1; | ||
| 376 | uint64_t reserved_7_9:3; | ||
| 377 | uint64_t ppnum:1; | ||
| 378 | uint64_t set:3; | ||
| 379 | uint64_t finv:1; | ||
| 380 | uint64_t l2d:1; | ||
| 381 | uint64_t l2t:1; | ||
| 382 | } cn50xx; | ||
| 383 | struct cvmx_l2c_dbg_cn52xx { | ||
| 384 | uint64_t reserved_14_63:50; | ||
| 385 | uint64_t lfb_enum:3; | ||
| 386 | uint64_t lfb_dmp:1; | ||
| 387 | uint64_t reserved_8_9:2; | ||
| 388 | uint64_t ppnum:2; | ||
| 389 | uint64_t set:3; | ||
| 390 | uint64_t finv:1; | ||
| 391 | uint64_t l2d:1; | ||
| 392 | uint64_t l2t:1; | ||
| 393 | } cn52xx; | ||
| 394 | struct cvmx_l2c_dbg_cn52xx cn52xxp1; | ||
| 395 | struct cvmx_l2c_dbg_s cn56xx; | ||
| 396 | struct cvmx_l2c_dbg_s cn56xxp1; | ||
| 397 | struct cvmx_l2c_dbg_s cn58xx; | ||
| 398 | struct cvmx_l2c_dbg_s cn58xxp1; | ||
| 399 | }; | ||
| 400 | |||
| 401 | union cvmx_l2c_dut { | ||
| 402 | uint64_t u64; | ||
| 403 | struct cvmx_l2c_dut_s { | ||
| 404 | uint64_t reserved_32_63:32; | ||
| 405 | uint64_t dtena:1; | ||
| 406 | uint64_t reserved_30_30:1; | ||
| 407 | uint64_t dt_vld:1; | ||
| 408 | uint64_t dt_tag:29; | ||
| 409 | } s; | ||
| 410 | struct cvmx_l2c_dut_s cn30xx; | ||
| 411 | struct cvmx_l2c_dut_s cn31xx; | ||
| 412 | struct cvmx_l2c_dut_s cn38xx; | ||
| 413 | struct cvmx_l2c_dut_s cn38xxp2; | ||
| 414 | struct cvmx_l2c_dut_s cn50xx; | ||
| 415 | struct cvmx_l2c_dut_s cn52xx; | ||
| 416 | struct cvmx_l2c_dut_s cn52xxp1; | ||
| 417 | struct cvmx_l2c_dut_s cn56xx; | ||
| 418 | struct cvmx_l2c_dut_s cn56xxp1; | ||
| 419 | struct cvmx_l2c_dut_s cn58xx; | ||
| 420 | struct cvmx_l2c_dut_s cn58xxp1; | ||
| 421 | }; | ||
| 422 | |||
| 423 | union cvmx_l2c_grpwrr0 { | ||
| 424 | uint64_t u64; | ||
| 425 | struct cvmx_l2c_grpwrr0_s { | ||
| 426 | uint64_t plc1rmsk:32; | ||
| 427 | uint64_t plc0rmsk:32; | ||
| 428 | } s; | ||
| 429 | struct cvmx_l2c_grpwrr0_s cn52xx; | ||
| 430 | struct cvmx_l2c_grpwrr0_s cn52xxp1; | ||
| 431 | struct cvmx_l2c_grpwrr0_s cn56xx; | ||
| 432 | struct cvmx_l2c_grpwrr0_s cn56xxp1; | ||
| 433 | }; | ||
| 434 | |||
| 435 | union cvmx_l2c_grpwrr1 { | ||
| 436 | uint64_t u64; | ||
| 437 | struct cvmx_l2c_grpwrr1_s { | ||
| 438 | uint64_t ilcrmsk:32; | ||
| 439 | uint64_t plc2rmsk:32; | ||
| 440 | } s; | ||
| 441 | struct cvmx_l2c_grpwrr1_s cn52xx; | ||
| 442 | struct cvmx_l2c_grpwrr1_s cn52xxp1; | ||
| 443 | struct cvmx_l2c_grpwrr1_s cn56xx; | ||
| 444 | struct cvmx_l2c_grpwrr1_s cn56xxp1; | ||
| 445 | }; | ||
| 446 | |||
| 447 | union cvmx_l2c_int_en { | ||
| 448 | uint64_t u64; | ||
| 449 | struct cvmx_l2c_int_en_s { | ||
| 450 | uint64_t reserved_9_63:55; | ||
| 451 | uint64_t lck2ena:1; | ||
| 452 | uint64_t lckena:1; | ||
| 453 | uint64_t l2ddeden:1; | ||
| 454 | uint64_t l2dsecen:1; | ||
| 455 | uint64_t l2tdeden:1; | ||
| 456 | uint64_t l2tsecen:1; | ||
| 457 | uint64_t oob3en:1; | ||
| 458 | uint64_t oob2en:1; | ||
| 459 | uint64_t oob1en:1; | ||
| 460 | } s; | ||
| 461 | struct cvmx_l2c_int_en_s cn52xx; | ||
| 462 | struct cvmx_l2c_int_en_s cn52xxp1; | ||
| 463 | struct cvmx_l2c_int_en_s cn56xx; | ||
| 464 | struct cvmx_l2c_int_en_s cn56xxp1; | ||
| 465 | }; | ||
| 466 | |||
| 467 | union cvmx_l2c_int_stat { | ||
| 468 | uint64_t u64; | ||
| 469 | struct cvmx_l2c_int_stat_s { | ||
| 470 | uint64_t reserved_9_63:55; | ||
| 471 | uint64_t lck2:1; | ||
| 472 | uint64_t lck:1; | ||
| 473 | uint64_t l2dded:1; | ||
| 474 | uint64_t l2dsec:1; | ||
| 475 | uint64_t l2tded:1; | ||
| 476 | uint64_t l2tsec:1; | ||
| 477 | uint64_t oob3:1; | ||
| 478 | uint64_t oob2:1; | ||
| 479 | uint64_t oob1:1; | ||
| 480 | } s; | ||
| 481 | struct cvmx_l2c_int_stat_s cn52xx; | ||
| 482 | struct cvmx_l2c_int_stat_s cn52xxp1; | ||
| 483 | struct cvmx_l2c_int_stat_s cn56xx; | ||
| 484 | struct cvmx_l2c_int_stat_s cn56xxp1; | ||
| 485 | }; | ||
| 486 | |||
| 487 | union cvmx_l2c_lckbase { | ||
| 488 | uint64_t u64; | ||
| 489 | struct cvmx_l2c_lckbase_s { | ||
| 490 | uint64_t reserved_31_63:33; | ||
| 491 | uint64_t lck_base:27; | ||
| 492 | uint64_t reserved_1_3:3; | ||
| 493 | uint64_t lck_ena:1; | ||
| 494 | } s; | ||
| 495 | struct cvmx_l2c_lckbase_s cn30xx; | ||
| 496 | struct cvmx_l2c_lckbase_s cn31xx; | ||
| 497 | struct cvmx_l2c_lckbase_s cn38xx; | ||
| 498 | struct cvmx_l2c_lckbase_s cn38xxp2; | ||
| 499 | struct cvmx_l2c_lckbase_s cn50xx; | ||
| 500 | struct cvmx_l2c_lckbase_s cn52xx; | ||
| 501 | struct cvmx_l2c_lckbase_s cn52xxp1; | ||
| 502 | struct cvmx_l2c_lckbase_s cn56xx; | ||
| 503 | struct cvmx_l2c_lckbase_s cn56xxp1; | ||
| 504 | struct cvmx_l2c_lckbase_s cn58xx; | ||
| 505 | struct cvmx_l2c_lckbase_s cn58xxp1; | ||
| 506 | }; | ||
| 507 | |||
| 508 | union cvmx_l2c_lckoff { | ||
| 509 | uint64_t u64; | ||
| 510 | struct cvmx_l2c_lckoff_s { | ||
| 511 | uint64_t reserved_10_63:54; | ||
| 512 | uint64_t lck_offset:10; | ||
| 513 | } s; | ||
| 514 | struct cvmx_l2c_lckoff_s cn30xx; | ||
| 515 | struct cvmx_l2c_lckoff_s cn31xx; | ||
| 516 | struct cvmx_l2c_lckoff_s cn38xx; | ||
| 517 | struct cvmx_l2c_lckoff_s cn38xxp2; | ||
| 518 | struct cvmx_l2c_lckoff_s cn50xx; | ||
| 519 | struct cvmx_l2c_lckoff_s cn52xx; | ||
| 520 | struct cvmx_l2c_lckoff_s cn52xxp1; | ||
| 521 | struct cvmx_l2c_lckoff_s cn56xx; | ||
| 522 | struct cvmx_l2c_lckoff_s cn56xxp1; | ||
| 523 | struct cvmx_l2c_lckoff_s cn58xx; | ||
| 524 | struct cvmx_l2c_lckoff_s cn58xxp1; | ||
| 525 | }; | ||
| 526 | |||
| 527 | union cvmx_l2c_lfb0 { | ||
| 528 | uint64_t u64; | ||
| 529 | struct cvmx_l2c_lfb0_s { | ||
| 530 | uint64_t reserved_32_63:32; | ||
| 531 | uint64_t stcpnd:1; | ||
| 532 | uint64_t stpnd:1; | ||
| 533 | uint64_t stinv:1; | ||
| 534 | uint64_t stcfl:1; | ||
| 535 | uint64_t vam:1; | ||
| 536 | uint64_t inxt:4; | ||
| 537 | uint64_t itl:1; | ||
| 538 | uint64_t ihd:1; | ||
| 539 | uint64_t set:3; | ||
| 540 | uint64_t vabnum:4; | ||
| 541 | uint64_t sid:9; | ||
| 542 | uint64_t cmd:4; | ||
| 543 | uint64_t vld:1; | ||
| 544 | } s; | ||
| 545 | struct cvmx_l2c_lfb0_cn30xx { | ||
| 546 | uint64_t reserved_32_63:32; | ||
| 547 | uint64_t stcpnd:1; | ||
| 548 | uint64_t stpnd:1; | ||
| 549 | uint64_t stinv:1; | ||
| 550 | uint64_t stcfl:1; | ||
| 551 | uint64_t vam:1; | ||
| 552 | uint64_t reserved_25_26:2; | ||
| 553 | uint64_t inxt:2; | ||
| 554 | uint64_t itl:1; | ||
| 555 | uint64_t ihd:1; | ||
| 556 | uint64_t reserved_20_20:1; | ||
| 557 | uint64_t set:2; | ||
| 558 | uint64_t reserved_16_17:2; | ||
| 559 | uint64_t vabnum:2; | ||
| 560 | uint64_t sid:9; | ||
| 561 | uint64_t cmd:4; | ||
| 562 | uint64_t vld:1; | ||
| 563 | } cn30xx; | ||
| 564 | struct cvmx_l2c_lfb0_cn31xx { | ||
| 565 | uint64_t reserved_32_63:32; | ||
| 566 | uint64_t stcpnd:1; | ||
| 567 | uint64_t stpnd:1; | ||
| 568 | uint64_t stinv:1; | ||
| 569 | uint64_t stcfl:1; | ||
| 570 | uint64_t vam:1; | ||
| 571 | uint64_t reserved_26_26:1; | ||
| 572 | uint64_t inxt:3; | ||
| 573 | uint64_t itl:1; | ||
| 574 | uint64_t ihd:1; | ||
| 575 | uint64_t reserved_20_20:1; | ||
| 576 | uint64_t set:2; | ||
| 577 | uint64_t reserved_17_17:1; | ||
| 578 | uint64_t vabnum:3; | ||
| 579 | uint64_t sid:9; | ||
| 580 | uint64_t cmd:4; | ||
| 581 | uint64_t vld:1; | ||
| 582 | } cn31xx; | ||
| 583 | struct cvmx_l2c_lfb0_s cn38xx; | ||
| 584 | struct cvmx_l2c_lfb0_s cn38xxp2; | ||
| 585 | struct cvmx_l2c_lfb0_cn50xx { | ||
| 586 | uint64_t reserved_32_63:32; | ||
| 587 | uint64_t stcpnd:1; | ||
| 588 | uint64_t stpnd:1; | ||
| 589 | uint64_t stinv:1; | ||
| 590 | uint64_t stcfl:1; | ||
| 591 | uint64_t vam:1; | ||
| 592 | uint64_t reserved_26_26:1; | ||
| 593 | uint64_t inxt:3; | ||
| 594 | uint64_t itl:1; | ||
| 595 | uint64_t ihd:1; | ||
| 596 | uint64_t set:3; | ||
| 597 | uint64_t reserved_17_17:1; | ||
| 598 | uint64_t vabnum:3; | ||
| 599 | uint64_t sid:9; | ||
| 600 | uint64_t cmd:4; | ||
| 601 | uint64_t vld:1; | ||
| 602 | } cn50xx; | ||
| 603 | struct cvmx_l2c_lfb0_cn50xx cn52xx; | ||
| 604 | struct cvmx_l2c_lfb0_cn50xx cn52xxp1; | ||
| 605 | struct cvmx_l2c_lfb0_s cn56xx; | ||
| 606 | struct cvmx_l2c_lfb0_s cn56xxp1; | ||
| 607 | struct cvmx_l2c_lfb0_s cn58xx; | ||
| 608 | struct cvmx_l2c_lfb0_s cn58xxp1; | ||
| 609 | }; | ||
| 610 | |||
| 611 | union cvmx_l2c_lfb1 { | ||
| 612 | uint64_t u64; | ||
| 613 | struct cvmx_l2c_lfb1_s { | ||
| 614 | uint64_t reserved_19_63:45; | ||
| 615 | uint64_t dsgoing:1; | ||
| 616 | uint64_t bid:2; | ||
| 617 | uint64_t wtrsp:1; | ||
| 618 | uint64_t wtdw:1; | ||
| 619 | uint64_t wtdq:1; | ||
| 620 | uint64_t wtwhp:1; | ||
| 621 | uint64_t wtwhf:1; | ||
| 622 | uint64_t wtwrm:1; | ||
| 623 | uint64_t wtstm:1; | ||
| 624 | uint64_t wtrda:1; | ||
| 625 | uint64_t wtstdt:1; | ||
| 626 | uint64_t wtstrsp:1; | ||
| 627 | uint64_t wtstrsc:1; | ||
| 628 | uint64_t wtvtm:1; | ||
| 629 | uint64_t wtmfl:1; | ||
| 630 | uint64_t prbrty:1; | ||
| 631 | uint64_t wtprb:1; | ||
| 632 | uint64_t vld:1; | ||
| 633 | } s; | ||
| 634 | struct cvmx_l2c_lfb1_s cn30xx; | ||
| 635 | struct cvmx_l2c_lfb1_s cn31xx; | ||
| 636 | struct cvmx_l2c_lfb1_s cn38xx; | ||
| 637 | struct cvmx_l2c_lfb1_s cn38xxp2; | ||
| 638 | struct cvmx_l2c_lfb1_s cn50xx; | ||
| 639 | struct cvmx_l2c_lfb1_s cn52xx; | ||
| 640 | struct cvmx_l2c_lfb1_s cn52xxp1; | ||
| 641 | struct cvmx_l2c_lfb1_s cn56xx; | ||
| 642 | struct cvmx_l2c_lfb1_s cn56xxp1; | ||
| 643 | struct cvmx_l2c_lfb1_s cn58xx; | ||
| 644 | struct cvmx_l2c_lfb1_s cn58xxp1; | ||
| 645 | }; | ||
| 646 | |||
| 647 | union cvmx_l2c_lfb2 { | ||
| 648 | uint64_t u64; | ||
| 649 | struct cvmx_l2c_lfb2_s { | ||
| 650 | uint64_t reserved_0_63:64; | ||
| 651 | } s; | ||
| 652 | struct cvmx_l2c_lfb2_cn30xx { | ||
| 653 | uint64_t reserved_27_63:37; | ||
| 654 | uint64_t lfb_tag:19; | ||
| 655 | uint64_t lfb_idx:8; | ||
| 656 | } cn30xx; | ||
| 657 | struct cvmx_l2c_lfb2_cn31xx { | ||
| 658 | uint64_t reserved_27_63:37; | ||
| 659 | uint64_t lfb_tag:17; | ||
| 660 | uint64_t lfb_idx:10; | ||
| 661 | } cn31xx; | ||
| 662 | struct cvmx_l2c_lfb2_cn31xx cn38xx; | ||
| 663 | struct cvmx_l2c_lfb2_cn31xx cn38xxp2; | ||
| 664 | struct cvmx_l2c_lfb2_cn50xx { | ||
| 665 | uint64_t reserved_27_63:37; | ||
| 666 | uint64_t lfb_tag:20; | ||
| 667 | uint64_t lfb_idx:7; | ||
| 668 | } cn50xx; | ||
| 669 | struct cvmx_l2c_lfb2_cn52xx { | ||
| 670 | uint64_t reserved_27_63:37; | ||
| 671 | uint64_t lfb_tag:18; | ||
| 672 | uint64_t lfb_idx:9; | ||
| 673 | } cn52xx; | ||
| 674 | struct cvmx_l2c_lfb2_cn52xx cn52xxp1; | ||
| 675 | struct cvmx_l2c_lfb2_cn56xx { | ||
| 676 | uint64_t reserved_27_63:37; | ||
| 677 | uint64_t lfb_tag:16; | ||
| 678 | uint64_t lfb_idx:11; | ||
| 679 | } cn56xx; | ||
| 680 | struct cvmx_l2c_lfb2_cn56xx cn56xxp1; | ||
| 681 | struct cvmx_l2c_lfb2_cn56xx cn58xx; | ||
| 682 | struct cvmx_l2c_lfb2_cn56xx cn58xxp1; | ||
| 683 | }; | ||
| 684 | |||
| 685 | union cvmx_l2c_lfb3 { | ||
| 686 | uint64_t u64; | ||
| 687 | struct cvmx_l2c_lfb3_s { | ||
| 688 | uint64_t reserved_5_63:59; | ||
| 689 | uint64_t stpartdis:1; | ||
| 690 | uint64_t lfb_hwm:4; | ||
| 691 | } s; | ||
| 692 | struct cvmx_l2c_lfb3_cn30xx { | ||
| 693 | uint64_t reserved_5_63:59; | ||
| 694 | uint64_t stpartdis:1; | ||
| 695 | uint64_t reserved_2_3:2; | ||
| 696 | uint64_t lfb_hwm:2; | ||
| 697 | } cn30xx; | ||
| 698 | struct cvmx_l2c_lfb3_cn31xx { | ||
| 699 | uint64_t reserved_5_63:59; | ||
| 700 | uint64_t stpartdis:1; | ||
| 701 | uint64_t reserved_3_3:1; | ||
| 702 | uint64_t lfb_hwm:3; | ||
| 703 | } cn31xx; | ||
| 704 | struct cvmx_l2c_lfb3_s cn38xx; | ||
| 705 | struct cvmx_l2c_lfb3_s cn38xxp2; | ||
| 706 | struct cvmx_l2c_lfb3_cn31xx cn50xx; | ||
| 707 | struct cvmx_l2c_lfb3_cn31xx cn52xx; | ||
| 708 | struct cvmx_l2c_lfb3_cn31xx cn52xxp1; | ||
| 709 | struct cvmx_l2c_lfb3_s cn56xx; | ||
| 710 | struct cvmx_l2c_lfb3_s cn56xxp1; | ||
| 711 | struct cvmx_l2c_lfb3_s cn58xx; | ||
| 712 | struct cvmx_l2c_lfb3_s cn58xxp1; | ||
| 713 | }; | ||
| 714 | |||
| 715 | union cvmx_l2c_oob { | ||
| 716 | uint64_t u64; | ||
| 717 | struct cvmx_l2c_oob_s { | ||
| 718 | uint64_t reserved_2_63:62; | ||
| 719 | uint64_t dwbena:1; | ||
| 720 | uint64_t stena:1; | ||
| 721 | } s; | ||
| 722 | struct cvmx_l2c_oob_s cn52xx; | ||
| 723 | struct cvmx_l2c_oob_s cn52xxp1; | ||
| 724 | struct cvmx_l2c_oob_s cn56xx; | ||
| 725 | struct cvmx_l2c_oob_s cn56xxp1; | ||
| 726 | }; | ||
| 727 | |||
| 728 | union cvmx_l2c_oob1 { | ||
| 729 | uint64_t u64; | ||
| 730 | struct cvmx_l2c_oob1_s { | ||
| 731 | uint64_t fadr:27; | ||
| 732 | uint64_t fsrc:1; | ||
| 733 | uint64_t reserved_34_35:2; | ||
| 734 | uint64_t sadr:14; | ||
| 735 | uint64_t reserved_14_19:6; | ||
| 736 | uint64_t size:14; | ||
| 737 | } s; | ||
| 738 | struct cvmx_l2c_oob1_s cn52xx; | ||
| 739 | struct cvmx_l2c_oob1_s cn52xxp1; | ||
| 740 | struct cvmx_l2c_oob1_s cn56xx; | ||
| 741 | struct cvmx_l2c_oob1_s cn56xxp1; | ||
| 742 | }; | ||
| 743 | |||
| 744 | union cvmx_l2c_oob2 { | ||
| 745 | uint64_t u64; | ||
| 746 | struct cvmx_l2c_oob2_s { | ||
| 747 | uint64_t fadr:27; | ||
| 748 | uint64_t fsrc:1; | ||
| 749 | uint64_t reserved_34_35:2; | ||
| 750 | uint64_t sadr:14; | ||
| 751 | uint64_t reserved_14_19:6; | ||
| 752 | uint64_t size:14; | ||
| 753 | } s; | ||
| 754 | struct cvmx_l2c_oob2_s cn52xx; | ||
| 755 | struct cvmx_l2c_oob2_s cn52xxp1; | ||
| 756 | struct cvmx_l2c_oob2_s cn56xx; | ||
| 757 | struct cvmx_l2c_oob2_s cn56xxp1; | ||
| 758 | }; | ||
| 759 | |||
| 760 | union cvmx_l2c_oob3 { | ||
| 761 | uint64_t u64; | ||
| 762 | struct cvmx_l2c_oob3_s { | ||
| 763 | uint64_t fadr:27; | ||
| 764 | uint64_t fsrc:1; | ||
| 765 | uint64_t reserved_34_35:2; | ||
| 766 | uint64_t sadr:14; | ||
| 767 | uint64_t reserved_14_19:6; | ||
| 768 | uint64_t size:14; | ||
| 769 | } s; | ||
| 770 | struct cvmx_l2c_oob3_s cn52xx; | ||
| 771 | struct cvmx_l2c_oob3_s cn52xxp1; | ||
| 772 | struct cvmx_l2c_oob3_s cn56xx; | ||
| 773 | struct cvmx_l2c_oob3_s cn56xxp1; | ||
| 774 | }; | ||
| 775 | |||
| 776 | union cvmx_l2c_pfcx { | ||
| 777 | uint64_t u64; | ||
| 778 | struct cvmx_l2c_pfcx_s { | ||
| 779 | uint64_t reserved_36_63:28; | ||
| 780 | uint64_t pfcnt0:36; | ||
| 781 | } s; | ||
| 782 | struct cvmx_l2c_pfcx_s cn30xx; | ||
| 783 | struct cvmx_l2c_pfcx_s cn31xx; | ||
| 784 | struct cvmx_l2c_pfcx_s cn38xx; | ||
| 785 | struct cvmx_l2c_pfcx_s cn38xxp2; | ||
| 786 | struct cvmx_l2c_pfcx_s cn50xx; | ||
| 787 | struct cvmx_l2c_pfcx_s cn52xx; | ||
| 788 | struct cvmx_l2c_pfcx_s cn52xxp1; | ||
| 789 | struct cvmx_l2c_pfcx_s cn56xx; | ||
| 790 | struct cvmx_l2c_pfcx_s cn56xxp1; | ||
| 791 | struct cvmx_l2c_pfcx_s cn58xx; | ||
| 792 | struct cvmx_l2c_pfcx_s cn58xxp1; | ||
| 793 | }; | ||
| 794 | |||
| 795 | union cvmx_l2c_pfctl { | ||
| 796 | uint64_t u64; | ||
| 797 | struct cvmx_l2c_pfctl_s { | ||
| 798 | uint64_t reserved_36_63:28; | ||
| 799 | uint64_t cnt3rdclr:1; | ||
| 800 | uint64_t cnt2rdclr:1; | ||
| 801 | uint64_t cnt1rdclr:1; | ||
| 802 | uint64_t cnt0rdclr:1; | ||
| 803 | uint64_t cnt3ena:1; | ||
| 804 | uint64_t cnt3clr:1; | ||
| 805 | uint64_t cnt3sel:6; | ||
| 806 | uint64_t cnt2ena:1; | ||
| 807 | uint64_t cnt2clr:1; | ||
| 808 | uint64_t cnt2sel:6; | ||
| 809 | uint64_t cnt1ena:1; | ||
| 810 | uint64_t cnt1clr:1; | ||
| 811 | uint64_t cnt1sel:6; | ||
| 812 | uint64_t cnt0ena:1; | ||
| 813 | uint64_t cnt0clr:1; | ||
| 814 | uint64_t cnt0sel:6; | ||
| 815 | } s; | ||
| 816 | struct cvmx_l2c_pfctl_s cn30xx; | ||
| 817 | struct cvmx_l2c_pfctl_s cn31xx; | ||
| 818 | struct cvmx_l2c_pfctl_s cn38xx; | ||
| 819 | struct cvmx_l2c_pfctl_s cn38xxp2; | ||
| 820 | struct cvmx_l2c_pfctl_s cn50xx; | ||
| 821 | struct cvmx_l2c_pfctl_s cn52xx; | ||
| 822 | struct cvmx_l2c_pfctl_s cn52xxp1; | ||
| 823 | struct cvmx_l2c_pfctl_s cn56xx; | ||
| 824 | struct cvmx_l2c_pfctl_s cn56xxp1; | ||
| 825 | struct cvmx_l2c_pfctl_s cn58xx; | ||
| 826 | struct cvmx_l2c_pfctl_s cn58xxp1; | ||
| 827 | }; | ||
| 828 | |||
| 829 | union cvmx_l2c_ppgrp { | ||
| 830 | uint64_t u64; | ||
| 831 | struct cvmx_l2c_ppgrp_s { | ||
| 832 | uint64_t reserved_24_63:40; | ||
| 833 | uint64_t pp11grp:2; | ||
| 834 | uint64_t pp10grp:2; | ||
| 835 | uint64_t pp9grp:2; | ||
| 836 | uint64_t pp8grp:2; | ||
| 837 | uint64_t pp7grp:2; | ||
| 838 | uint64_t pp6grp:2; | ||
| 839 | uint64_t pp5grp:2; | ||
| 840 | uint64_t pp4grp:2; | ||
| 841 | uint64_t pp3grp:2; | ||
| 842 | uint64_t pp2grp:2; | ||
| 843 | uint64_t pp1grp:2; | ||
| 844 | uint64_t pp0grp:2; | ||
| 845 | } s; | ||
| 846 | struct cvmx_l2c_ppgrp_cn52xx { | ||
| 847 | uint64_t reserved_8_63:56; | ||
| 848 | uint64_t pp3grp:2; | ||
| 849 | uint64_t pp2grp:2; | ||
| 850 | uint64_t pp1grp:2; | ||
| 851 | uint64_t pp0grp:2; | ||
| 852 | } cn52xx; | ||
| 853 | struct cvmx_l2c_ppgrp_cn52xx cn52xxp1; | ||
| 854 | struct cvmx_l2c_ppgrp_s cn56xx; | ||
| 855 | struct cvmx_l2c_ppgrp_s cn56xxp1; | ||
| 856 | }; | ||
| 857 | |||
| 858 | union cvmx_l2c_spar0 { | ||
| 859 | uint64_t u64; | ||
| 860 | struct cvmx_l2c_spar0_s { | ||
| 861 | uint64_t reserved_32_63:32; | ||
| 862 | uint64_t umsk3:8; | ||
| 863 | uint64_t umsk2:8; | ||
| 864 | uint64_t umsk1:8; | ||
| 865 | uint64_t umsk0:8; | ||
| 866 | } s; | ||
| 867 | struct cvmx_l2c_spar0_cn30xx { | ||
| 868 | uint64_t reserved_4_63:60; | ||
| 869 | uint64_t umsk0:4; | ||
| 870 | } cn30xx; | ||
| 871 | struct cvmx_l2c_spar0_cn31xx { | ||
| 872 | uint64_t reserved_12_63:52; | ||
| 873 | uint64_t umsk1:4; | ||
| 874 | uint64_t reserved_4_7:4; | ||
| 875 | uint64_t umsk0:4; | ||
| 876 | } cn31xx; | ||
| 877 | struct cvmx_l2c_spar0_s cn38xx; | ||
| 878 | struct cvmx_l2c_spar0_s cn38xxp2; | ||
| 879 | struct cvmx_l2c_spar0_cn50xx { | ||
| 880 | uint64_t reserved_16_63:48; | ||
| 881 | uint64_t umsk1:8; | ||
| 882 | uint64_t umsk0:8; | ||
| 883 | } cn50xx; | ||
| 884 | struct cvmx_l2c_spar0_s cn52xx; | ||
| 885 | struct cvmx_l2c_spar0_s cn52xxp1; | ||
| 886 | struct cvmx_l2c_spar0_s cn56xx; | ||
| 887 | struct cvmx_l2c_spar0_s cn56xxp1; | ||
| 888 | struct cvmx_l2c_spar0_s cn58xx; | ||
| 889 | struct cvmx_l2c_spar0_s cn58xxp1; | ||
| 890 | }; | ||
| 891 | |||
| 892 | union cvmx_l2c_spar1 { | ||
| 893 | uint64_t u64; | ||
| 894 | struct cvmx_l2c_spar1_s { | ||
| 895 | uint64_t reserved_32_63:32; | ||
| 896 | uint64_t umsk7:8; | ||
| 897 | uint64_t umsk6:8; | ||
| 898 | uint64_t umsk5:8; | ||
| 899 | uint64_t umsk4:8; | ||
| 900 | } s; | ||
| 901 | struct cvmx_l2c_spar1_s cn38xx; | ||
| 902 | struct cvmx_l2c_spar1_s cn38xxp2; | ||
| 903 | struct cvmx_l2c_spar1_s cn56xx; | ||
| 904 | struct cvmx_l2c_spar1_s cn56xxp1; | ||
| 905 | struct cvmx_l2c_spar1_s cn58xx; | ||
| 906 | struct cvmx_l2c_spar1_s cn58xxp1; | ||
| 907 | }; | ||
| 908 | |||
| 909 | union cvmx_l2c_spar2 { | ||
| 910 | uint64_t u64; | ||
| 911 | struct cvmx_l2c_spar2_s { | ||
| 912 | uint64_t reserved_32_63:32; | ||
| 913 | uint64_t umsk11:8; | ||
| 914 | uint64_t umsk10:8; | ||
| 915 | uint64_t umsk9:8; | ||
| 916 | uint64_t umsk8:8; | ||
| 917 | } s; | ||
| 918 | struct cvmx_l2c_spar2_s cn38xx; | ||
| 919 | struct cvmx_l2c_spar2_s cn38xxp2; | ||
| 920 | struct cvmx_l2c_spar2_s cn56xx; | ||
| 921 | struct cvmx_l2c_spar2_s cn56xxp1; | ||
| 922 | struct cvmx_l2c_spar2_s cn58xx; | ||
| 923 | struct cvmx_l2c_spar2_s cn58xxp1; | ||
| 924 | }; | ||
| 925 | |||
| 926 | union cvmx_l2c_spar3 { | ||
| 927 | uint64_t u64; | ||
| 928 | struct cvmx_l2c_spar3_s { | ||
| 929 | uint64_t reserved_32_63:32; | ||
| 930 | uint64_t umsk15:8; | ||
| 931 | uint64_t umsk14:8; | ||
| 932 | uint64_t umsk13:8; | ||
| 933 | uint64_t umsk12:8; | ||
| 934 | } s; | ||
| 935 | struct cvmx_l2c_spar3_s cn38xx; | ||
| 936 | struct cvmx_l2c_spar3_s cn38xxp2; | ||
| 937 | struct cvmx_l2c_spar3_s cn58xx; | ||
| 938 | struct cvmx_l2c_spar3_s cn58xxp1; | ||
| 939 | }; | ||
| 940 | |||
| 941 | union cvmx_l2c_spar4 { | ||
| 942 | uint64_t u64; | ||
| 943 | struct cvmx_l2c_spar4_s { | ||
| 944 | uint64_t reserved_8_63:56; | ||
| 945 | uint64_t umskiob:8; | ||
| 946 | } s; | ||
| 947 | struct cvmx_l2c_spar4_cn30xx { | ||
| 948 | uint64_t reserved_4_63:60; | ||
| 949 | uint64_t umskiob:4; | ||
| 950 | } cn30xx; | ||
| 951 | struct cvmx_l2c_spar4_cn30xx cn31xx; | ||
| 952 | struct cvmx_l2c_spar4_s cn38xx; | ||
| 953 | struct cvmx_l2c_spar4_s cn38xxp2; | ||
| 954 | struct cvmx_l2c_spar4_s cn50xx; | ||
| 955 | struct cvmx_l2c_spar4_s cn52xx; | ||
| 956 | struct cvmx_l2c_spar4_s cn52xxp1; | ||
| 957 | struct cvmx_l2c_spar4_s cn56xx; | ||
| 958 | struct cvmx_l2c_spar4_s cn56xxp1; | ||
| 959 | struct cvmx_l2c_spar4_s cn58xx; | ||
| 960 | struct cvmx_l2c_spar4_s cn58xxp1; | ||
| 961 | }; | ||
| 962 | |||
| 963 | #endif | ||
diff --git a/arch/mips/include/asm/octeon/cvmx-l2c.h b/arch/mips/include/asm/octeon/cvmx-l2c.h new file mode 100644 index 000000000000..2a8c0902ea50 --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-l2c.h | |||
| @@ -0,0 +1,325 @@ | |||
| 1 | /***********************license start*************** | ||
| 2 | * Author: Cavium Networks | ||
| 3 | * | ||
| 4 | * Contact: support@caviumnetworks.com | ||
| 5 | * This file is part of the OCTEON SDK | ||
| 6 | * | ||
| 7 | * Copyright (c) 2003-2008 Cavium Networks | ||
| 8 | * | ||
| 9 | * This file is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License, Version 2, as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | * | ||
| 13 | * This file is distributed in the hope that it will be useful, but | ||
| 14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
| 15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
| 16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
| 17 | * details. | ||
| 18 | * | ||
| 19 | * You should have received a copy of the GNU General Public License | ||
| 20 | * along with this file; if not, write to the Free Software | ||
| 21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 22 | * or visit http://www.gnu.org/licenses/. | ||
| 23 | * | ||
| 24 | * This file may also be available under a different license from Cavium. | ||
| 25 | * Contact Cavium Networks for more information | ||
| 26 | ***********************license end**************************************/ | ||
| 27 | |||
| 28 | /* | ||
| 29 | * | ||
| 30 | * Interface to the Level 2 Cache (L2C) control, measurement, and debugging | ||
| 31 | * facilities. | ||
| 32 | */ | ||
| 33 | |||
| 34 | #ifndef __CVMX_L2C_H__ | ||
| 35 | #define __CVMX_L2C_H__ | ||
| 36 | |||
| 37 | /* Deprecated macro, use function */ | ||
| 38 | #define CVMX_L2_ASSOC cvmx_l2c_get_num_assoc() | ||
| 39 | |||
| 40 | /* Deprecated macro, use function */ | ||
| 41 | #define CVMX_L2_SET_BITS cvmx_l2c_get_set_bits() | ||
| 42 | |||
| 43 | /* Deprecated macro, use function */ | ||
| 44 | #define CVMX_L2_SETS cvmx_l2c_get_num_sets() | ||
| 45 | |||
| 46 | #define CVMX_L2C_IDX_ADDR_SHIFT 7 /* based on 128 byte cache line size */ | ||
| 47 | #define CVMX_L2C_IDX_MASK (cvmx_l2c_get_num_sets() - 1) | ||
| 48 | |||
| 49 | /* Defines for index aliasing computations */ | ||
| 50 | #define CVMX_L2C_TAG_ADDR_ALIAS_SHIFT \ | ||
| 51 | (CVMX_L2C_IDX_ADDR_SHIFT + cvmx_l2c_get_set_bits()) | ||
| 52 | |||
| 53 | #define CVMX_L2C_ALIAS_MASK \ | ||
| 54 | (CVMX_L2C_IDX_MASK << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) | ||
| 55 | |||
| 56 | union cvmx_l2c_tag { | ||
| 57 | uint64_t u64; | ||
| 58 | struct { | ||
| 59 | uint64_t reserved:28; | ||
| 60 | uint64_t V:1; /* Line valid */ | ||
| 61 | uint64_t D:1; /* Line dirty */ | ||
| 62 | uint64_t L:1; /* Line locked */ | ||
| 63 | uint64_t U:1; /* Use, LRU eviction */ | ||
| 64 | uint64_t addr:32; /* Phys mem (not all bits valid) */ | ||
| 65 | } s; | ||
| 66 | }; | ||
| 67 | |||
| 68 | /* L2C Performance Counter events. */ | ||
| 69 | enum cvmx_l2c_event { | ||
| 70 | CVMX_L2C_EVENT_CYCLES = 0, | ||
| 71 | CVMX_L2C_EVENT_INSTRUCTION_MISS = 1, | ||
| 72 | CVMX_L2C_EVENT_INSTRUCTION_HIT = 2, | ||
| 73 | CVMX_L2C_EVENT_DATA_MISS = 3, | ||
| 74 | CVMX_L2C_EVENT_DATA_HIT = 4, | ||
| 75 | CVMX_L2C_EVENT_MISS = 5, | ||
| 76 | CVMX_L2C_EVENT_HIT = 6, | ||
| 77 | CVMX_L2C_EVENT_VICTIM_HIT = 7, | ||
| 78 | CVMX_L2C_EVENT_INDEX_CONFLICT = 8, | ||
| 79 | CVMX_L2C_EVENT_TAG_PROBE = 9, | ||
| 80 | CVMX_L2C_EVENT_TAG_UPDATE = 10, | ||
| 81 | CVMX_L2C_EVENT_TAG_COMPLETE = 11, | ||
| 82 | CVMX_L2C_EVENT_TAG_DIRTY = 12, | ||
| 83 | CVMX_L2C_EVENT_DATA_STORE_NOP = 13, | ||
| 84 | CVMX_L2C_EVENT_DATA_STORE_READ = 14, | ||
| 85 | CVMX_L2C_EVENT_DATA_STORE_WRITE = 15, | ||
| 86 | CVMX_L2C_EVENT_FILL_DATA_VALID = 16, | ||
| 87 | CVMX_L2C_EVENT_WRITE_REQUEST = 17, | ||
| 88 | CVMX_L2C_EVENT_READ_REQUEST = 18, | ||
| 89 | CVMX_L2C_EVENT_WRITE_DATA_VALID = 19, | ||
| 90 | CVMX_L2C_EVENT_XMC_NOP = 20, | ||
| 91 | CVMX_L2C_EVENT_XMC_LDT = 21, | ||
| 92 | CVMX_L2C_EVENT_XMC_LDI = 22, | ||
| 93 | CVMX_L2C_EVENT_XMC_LDD = 23, | ||
| 94 | CVMX_L2C_EVENT_XMC_STF = 24, | ||
| 95 | CVMX_L2C_EVENT_XMC_STT = 25, | ||
| 96 | CVMX_L2C_EVENT_XMC_STP = 26, | ||
| 97 | CVMX_L2C_EVENT_XMC_STC = 27, | ||
| 98 | CVMX_L2C_EVENT_XMC_DWB = 28, | ||
| 99 | CVMX_L2C_EVENT_XMC_PL2 = 29, | ||
| 100 | CVMX_L2C_EVENT_XMC_PSL1 = 30, | ||
| 101 | CVMX_L2C_EVENT_XMC_IOBLD = 31, | ||
| 102 | CVMX_L2C_EVENT_XMC_IOBST = 32, | ||
| 103 | CVMX_L2C_EVENT_XMC_IOBDMA = 33, | ||
| 104 | CVMX_L2C_EVENT_XMC_IOBRSP = 34, | ||
| 105 | CVMX_L2C_EVENT_XMC_BUS_VALID = 35, | ||
| 106 | CVMX_L2C_EVENT_XMC_MEM_DATA = 36, | ||
| 107 | CVMX_L2C_EVENT_XMC_REFL_DATA = 37, | ||
| 108 | CVMX_L2C_EVENT_XMC_IOBRSP_DATA = 38, | ||
| 109 | CVMX_L2C_EVENT_RSC_NOP = 39, | ||
| 110 | CVMX_L2C_EVENT_RSC_STDN = 40, | ||
| 111 | CVMX_L2C_EVENT_RSC_FILL = 41, | ||
| 112 | CVMX_L2C_EVENT_RSC_REFL = 42, | ||
| 113 | CVMX_L2C_EVENT_RSC_STIN = 43, | ||
| 114 | CVMX_L2C_EVENT_RSC_SCIN = 44, | ||
| 115 | CVMX_L2C_EVENT_RSC_SCFL = 45, | ||
| 116 | CVMX_L2C_EVENT_RSC_SCDN = 46, | ||
| 117 | CVMX_L2C_EVENT_RSC_DATA_VALID = 47, | ||
| 118 | CVMX_L2C_EVENT_RSC_VALID_FILL = 48, | ||
| 119 | CVMX_L2C_EVENT_RSC_VALID_STRSP = 49, | ||
| 120 | CVMX_L2C_EVENT_RSC_VALID_REFL = 50, | ||
| 121 | CVMX_L2C_EVENT_LRF_REQ = 51, | ||
| 122 | CVMX_L2C_EVENT_DT_RD_ALLOC = 52, | ||
| 123 | CVMX_L2C_EVENT_DT_WR_INVAL = 53 | ||
| 124 | }; | ||
| 125 | |||
| 126 | /** | ||
| 127 | * Configure one of the four L2 Cache performance counters to capture event | ||
| 128 | * occurences. | ||
| 129 | * | ||
| 130 | * @counter: The counter to configure. Range 0..3. | ||
| 131 | * @event: The type of L2 Cache event occurrence to count. | ||
| 132 | * @clear_on_read: When asserted, any read of the performance counter | ||
| 133 | * clears the counter. | ||
| 134 | * | ||
| 135 | * The routine does not clear the counter. | ||
| 136 | */ | ||
| 137 | void cvmx_l2c_config_perf(uint32_t counter, | ||
| 138 | enum cvmx_l2c_event event, uint32_t clear_on_read); | ||
| 139 | /** | ||
| 140 | * Read the given L2 Cache performance counter. The counter must be configured | ||
| 141 | * before reading, but this routine does not enforce this requirement. | ||
| 142 | * | ||
| 143 | * @counter: The counter to configure. Range 0..3. | ||
| 144 | * | ||
| 145 | * Returns The current counter value. | ||
| 146 | */ | ||
| 147 | uint64_t cvmx_l2c_read_perf(uint32_t counter); | ||
| 148 | |||
| 149 | /** | ||
| 150 | * Return the L2 Cache way partitioning for a given core. | ||
| 151 | * | ||
| 152 | * @core: The core processor of interest. | ||
| 153 | * | ||
| 154 | * Returns The mask specifying the partitioning. 0 bits in mask indicates | ||
| 155 | * the cache 'ways' that a core can evict from. | ||
| 156 | * -1 on error | ||
| 157 | */ | ||
| 158 | int cvmx_l2c_get_core_way_partition(uint32_t core); | ||
| 159 | |||
| 160 | /** | ||
| 161 | * Partitions the L2 cache for a core | ||
| 162 | * | ||
| 163 | * @core: The core that the partitioning applies to. | ||
| 164 | * | ||
| 165 | * @mask: The partitioning of the ways expressed as a binary mask. A 0 | ||
| 166 | * bit allows the core to evict cache lines from a way, while a | ||
| 167 | * 1 bit blocks the core from evicting any lines from that | ||
| 168 | * way. There must be at least one allowed way (0 bit) in the | ||
| 169 | * mask. | ||
| 170 | * | ||
| 171 | * If any ways are blocked for all cores and the HW blocks, then those | ||
| 172 | * ways will never have any cache lines evicted from them. All cores | ||
| 173 | * and the hardware blocks are free to read from all ways regardless | ||
| 174 | * of the partitioning. | ||
| 175 | */ | ||
| 176 | int cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask); | ||
| 177 | |||
| 178 | /** | ||
| 179 | * Return the L2 Cache way partitioning for the hw blocks. | ||
| 180 | * | ||
| 181 | * Returns The mask specifying the reserved way. 0 bits in mask indicates | ||
| 182 | * the cache 'ways' that a core can evict from. | ||
| 183 | * -1 on error | ||
| 184 | */ | ||
| 185 | int cvmx_l2c_get_hw_way_partition(void); | ||
| 186 | |||
| 187 | /** | ||
| 188 | * Partitions the L2 cache for the hardware blocks. | ||
| 189 | * | ||
| 190 | * @mask: The partitioning of the ways expressed as a binary mask. A 0 | ||
| 191 | * bit allows the core to evict cache lines from a way, while a | ||
| 192 | * 1 bit blocks the core from evicting any lines from that | ||
| 193 | * way. There must be at least one allowed way (0 bit) in the | ||
| 194 | * mask. | ||
| 195 | * | ||
| 196 | * If any ways are blocked for all cores and the HW blocks, then those | ||
| 197 | * ways will never have any cache lines evicted from them. All cores | ||
| 198 | * and the hardware blocks are free to read from all ways regardless | ||
| 199 | * of the partitioning. | ||
| 200 | */ | ||
| 201 | int cvmx_l2c_set_hw_way_partition(uint32_t mask); | ||
| 202 | |||
| 203 | /** | ||
| 204 | * Locks a line in the L2 cache at the specified physical address | ||
| 205 | * | ||
| 206 | * @addr: physical address of line to lock | ||
| 207 | * | ||
| 208 | * Returns 0 on success, | ||
| 209 | * 1 if line not locked. | ||
| 210 | */ | ||
| 211 | int cvmx_l2c_lock_line(uint64_t addr); | ||
| 212 | |||
| 213 | /** | ||
| 214 | * Locks a specified memory region in the L2 cache. | ||
| 215 | * | ||
| 216 | * Note that if not all lines can be locked, that means that all | ||
| 217 | * but one of the ways (associations) available to the locking | ||
| 218 | * core are locked. Having only 1 association available for | ||
| 219 | * normal caching may have a significant adverse affect on performance. | ||
| 220 | * Care should be taken to ensure that enough of the L2 cache is left | ||
| 221 | * unlocked to allow for normal caching of DRAM. | ||
| 222 | * | ||
| 223 | * @start: Physical address of the start of the region to lock | ||
| 224 | * @len: Length (in bytes) of region to lock | ||
| 225 | * | ||
| 226 | * Returns Number of requested lines that where not locked. | ||
| 227 | * 0 on success (all locked) | ||
| 228 | */ | ||
| 229 | int cvmx_l2c_lock_mem_region(uint64_t start, uint64_t len); | ||
| 230 | |||
| 231 | /** | ||
| 232 | * Unlock and flush a cache line from the L2 cache. | ||
| 233 | * IMPORTANT: Must only be run by one core at a time due to use | ||
| 234 | * of L2C debug features. | ||
| 235 | * Note that this function will flush a matching but unlocked cache line. | ||
| 236 | * (If address is not in L2, no lines are flushed.) | ||
| 237 | * | ||
| 238 | * @address: Physical address to unlock | ||
| 239 | * | ||
| 240 | * Returns 0: line not unlocked | ||
| 241 | * 1: line unlocked | ||
| 242 | */ | ||
| 243 | int cvmx_l2c_unlock_line(uint64_t address); | ||
| 244 | |||
| 245 | /** | ||
| 246 | * Unlocks a region of memory that is locked in the L2 cache | ||
| 247 | * | ||
| 248 | * @start: start physical address | ||
| 249 | * @len: length (in bytes) to unlock | ||
| 250 | * | ||
| 251 | * Returns Number of locked lines that the call unlocked | ||
| 252 | */ | ||
| 253 | int cvmx_l2c_unlock_mem_region(uint64_t start, uint64_t len); | ||
| 254 | |||
| 255 | /** | ||
| 256 | * Read the L2 controller tag for a given location in L2 | ||
| 257 | * | ||
| 258 | * @association: | ||
| 259 | * Which association to read line from | ||
| 260 | * @index: Which way to read from. | ||
| 261 | * | ||
| 262 | * Returns l2c tag structure for line requested. | ||
| 263 | */ | ||
| 264 | union cvmx_l2c_tag cvmx_l2c_get_tag(uint32_t association, uint32_t index); | ||
| 265 | |||
| 266 | /* Wrapper around deprecated old function name */ | ||
| 267 | static inline union cvmx_l2c_tag cvmx_get_l2c_tag(uint32_t association, | ||
| 268 | uint32_t index) | ||
| 269 | { | ||
| 270 | return cvmx_l2c_get_tag(association, index); | ||
| 271 | } | ||
| 272 | |||
| 273 | /** | ||
| 274 | * Returns the cache index for a given physical address | ||
| 275 | * | ||
| 276 | * @addr: physical address | ||
| 277 | * | ||
| 278 | * Returns L2 cache index | ||
| 279 | */ | ||
| 280 | uint32_t cvmx_l2c_address_to_index(uint64_t addr); | ||
| 281 | |||
| 282 | /** | ||
| 283 | * Flushes (and unlocks) the entire L2 cache. | ||
| 284 | * IMPORTANT: Must only be run by one core at a time due to use | ||
| 285 | * of L2C debug features. | ||
| 286 | */ | ||
| 287 | void cvmx_l2c_flush(void); | ||
| 288 | |||
| 289 | /** | ||
| 290 | * | ||
| 291 | * Returns Returns the size of the L2 cache in bytes, | ||
| 292 | * -1 on error (unrecognized model) | ||
| 293 | */ | ||
| 294 | int cvmx_l2c_get_cache_size_bytes(void); | ||
| 295 | |||
| 296 | /** | ||
| 297 | * Return the number of sets in the L2 Cache | ||
| 298 | * | ||
| 299 | * Returns | ||
| 300 | */ | ||
| 301 | int cvmx_l2c_get_num_sets(void); | ||
| 302 | |||
| 303 | /** | ||
| 304 | * Return log base 2 of the number of sets in the L2 cache | ||
| 305 | * Returns | ||
| 306 | */ | ||
| 307 | int cvmx_l2c_get_set_bits(void); | ||
| 308 | /** | ||
| 309 | * Return the number of associations in the L2 Cache | ||
| 310 | * | ||
| 311 | * Returns | ||
| 312 | */ | ||
| 313 | int cvmx_l2c_get_num_assoc(void); | ||
| 314 | |||
| 315 | /** | ||
| 316 | * Flush a line from the L2 cache | ||
| 317 | * This should only be called from one core at a time, as this routine | ||
| 318 | * sets the core to the 'debug' core in order to flush the line. | ||
| 319 | * | ||
| 320 | * @assoc: Association (or way) to flush | ||
| 321 | * @index: Index to flush | ||
| 322 | */ | ||
| 323 | void cvmx_l2c_flush_line(uint32_t assoc, uint32_t index); | ||
| 324 | |||
| 325 | #endif /* __CVMX_L2C_H__ */ | ||
diff --git a/arch/mips/include/asm/octeon/cvmx-l2d-defs.h b/arch/mips/include/asm/octeon/cvmx-l2d-defs.h new file mode 100644 index 000000000000..d7102d455e1b --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-l2d-defs.h | |||
| @@ -0,0 +1,369 @@ | |||
| 1 | /***********************license start*************** | ||
| 2 | * Author: Cavium Networks | ||
| 3 | * | ||
| 4 | * Contact: support@caviumnetworks.com | ||
| 5 | * This file is part of the OCTEON SDK | ||
| 6 | * | ||
| 7 | * Copyright (c) 2003-2008 Cavium Networks | ||
| 8 | * | ||
| 9 | * This file is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License, Version 2, as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | * | ||
| 13 | * This file is distributed in the hope that it will be useful, but | ||
| 14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
| 15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
| 16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
| 17 | * details. | ||
| 18 | * | ||
| 19 | * You should have received a copy of the GNU General Public License | ||
| 20 | * along with this file; if not, write to the Free Software | ||
| 21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 22 | * or visit http://www.gnu.org/licenses/. | ||
| 23 | * | ||
| 24 | * This file may also be available under a different license from Cavium. | ||
| 25 | * Contact Cavium Networks for more information | ||
| 26 | ***********************license end**************************************/ | ||
| 27 | |||
| 28 | #ifndef __CVMX_L2D_DEFS_H__ | ||
| 29 | #define __CVMX_L2D_DEFS_H__ | ||
| 30 | |||
| 31 | #define CVMX_L2D_BST0 \ | ||
| 32 | CVMX_ADD_IO_SEG(0x0001180080000780ull) | ||
| 33 | #define CVMX_L2D_BST1 \ | ||
| 34 | CVMX_ADD_IO_SEG(0x0001180080000788ull) | ||
| 35 | #define CVMX_L2D_BST2 \ | ||
| 36 | CVMX_ADD_IO_SEG(0x0001180080000790ull) | ||
| 37 | #define CVMX_L2D_BST3 \ | ||
| 38 | CVMX_ADD_IO_SEG(0x0001180080000798ull) | ||
| 39 | #define CVMX_L2D_ERR \ | ||
| 40 | CVMX_ADD_IO_SEG(0x0001180080000010ull) | ||
| 41 | #define CVMX_L2D_FADR \ | ||
| 42 | CVMX_ADD_IO_SEG(0x0001180080000018ull) | ||
| 43 | #define CVMX_L2D_FSYN0 \ | ||
| 44 | CVMX_ADD_IO_SEG(0x0001180080000020ull) | ||
| 45 | #define CVMX_L2D_FSYN1 \ | ||
| 46 | CVMX_ADD_IO_SEG(0x0001180080000028ull) | ||
| 47 | #define CVMX_L2D_FUS0 \ | ||
| 48 | CVMX_ADD_IO_SEG(0x00011800800007A0ull) | ||
| 49 | #define CVMX_L2D_FUS1 \ | ||
| 50 | CVMX_ADD_IO_SEG(0x00011800800007A8ull) | ||
| 51 | #define CVMX_L2D_FUS2 \ | ||
| 52 | CVMX_ADD_IO_SEG(0x00011800800007B0ull) | ||
| 53 | #define CVMX_L2D_FUS3 \ | ||
| 54 | CVMX_ADD_IO_SEG(0x00011800800007B8ull) | ||
| 55 | |||
| 56 | union cvmx_l2d_bst0 { | ||
| 57 | uint64_t u64; | ||
| 58 | struct cvmx_l2d_bst0_s { | ||
| 59 | uint64_t reserved_35_63:29; | ||
| 60 | uint64_t ftl:1; | ||
| 61 | uint64_t q0stat:34; | ||
| 62 | } s; | ||
| 63 | struct cvmx_l2d_bst0_s cn30xx; | ||
| 64 | struct cvmx_l2d_bst0_s cn31xx; | ||
| 65 | struct cvmx_l2d_bst0_s cn38xx; | ||
| 66 | struct cvmx_l2d_bst0_s cn38xxp2; | ||
| 67 | struct cvmx_l2d_bst0_s cn50xx; | ||
| 68 | struct cvmx_l2d_bst0_s cn52xx; | ||
| 69 | struct cvmx_l2d_bst0_s cn52xxp1; | ||
| 70 | struct cvmx_l2d_bst0_s cn56xx; | ||
| 71 | struct cvmx_l2d_bst0_s cn56xxp1; | ||
| 72 | struct cvmx_l2d_bst0_s cn58xx; | ||
| 73 | struct cvmx_l2d_bst0_s cn58xxp1; | ||
| 74 | }; | ||
| 75 | |||
| 76 | union cvmx_l2d_bst1 { | ||
| 77 | uint64_t u64; | ||
| 78 | struct cvmx_l2d_bst1_s { | ||
| 79 | uint64_t reserved_34_63:30; | ||
| 80 | uint64_t q1stat:34; | ||
| 81 | } s; | ||
| 82 | struct cvmx_l2d_bst1_s cn30xx; | ||
| 83 | struct cvmx_l2d_bst1_s cn31xx; | ||
| 84 | struct cvmx_l2d_bst1_s cn38xx; | ||
| 85 | struct cvmx_l2d_bst1_s cn38xxp2; | ||
| 86 | struct cvmx_l2d_bst1_s cn50xx; | ||
| 87 | struct cvmx_l2d_bst1_s cn52xx; | ||
| 88 | struct cvmx_l2d_bst1_s cn52xxp1; | ||
| 89 | struct cvmx_l2d_bst1_s cn56xx; | ||
| 90 | struct cvmx_l2d_bst1_s cn56xxp1; | ||
| 91 | struct cvmx_l2d_bst1_s cn58xx; | ||
| 92 | struct cvmx_l2d_bst1_s cn58xxp1; | ||
| 93 | }; | ||
| 94 | |||
| 95 | union cvmx_l2d_bst2 { | ||
| 96 | uint64_t u64; | ||
| 97 | struct cvmx_l2d_bst2_s { | ||
| 98 | uint64_t reserved_34_63:30; | ||
| 99 | uint64_t q2stat:34; | ||
| 100 | } s; | ||
| 101 | struct cvmx_l2d_bst2_s cn30xx; | ||
| 102 | struct cvmx_l2d_bst2_s cn31xx; | ||
| 103 | struct cvmx_l2d_bst2_s cn38xx; | ||
| 104 | struct cvmx_l2d_bst2_s cn38xxp2; | ||
| 105 | struct cvmx_l2d_bst2_s cn50xx; | ||
| 106 | struct cvmx_l2d_bst2_s cn52xx; | ||
| 107 | struct cvmx_l2d_bst2_s cn52xxp1; | ||
| 108 | struct cvmx_l2d_bst2_s cn56xx; | ||
| 109 | struct cvmx_l2d_bst2_s cn56xxp1; | ||
| 110 | struct cvmx_l2d_bst2_s cn58xx; | ||
| 111 | struct cvmx_l2d_bst2_s cn58xxp1; | ||
| 112 | }; | ||
| 113 | |||
| 114 | union cvmx_l2d_bst3 { | ||
| 115 | uint64_t u64; | ||
| 116 | struct cvmx_l2d_bst3_s { | ||
| 117 | uint64_t reserved_34_63:30; | ||
| 118 | uint64_t q3stat:34; | ||
| 119 | } s; | ||
| 120 | struct cvmx_l2d_bst3_s cn30xx; | ||
| 121 | struct cvmx_l2d_bst3_s cn31xx; | ||
| 122 | struct cvmx_l2d_bst3_s cn38xx; | ||
| 123 | struct cvmx_l2d_bst3_s cn38xxp2; | ||
| 124 | struct cvmx_l2d_bst3_s cn50xx; | ||
| 125 | struct cvmx_l2d_bst3_s cn52xx; | ||
| 126 | struct cvmx_l2d_bst3_s cn52xxp1; | ||
| 127 | struct cvmx_l2d_bst3_s cn56xx; | ||
| 128 | struct cvmx_l2d_bst3_s cn56xxp1; | ||
| 129 | struct cvmx_l2d_bst3_s cn58xx; | ||
| 130 | struct cvmx_l2d_bst3_s cn58xxp1; | ||
| 131 | }; | ||
| 132 | |||
| 133 | union cvmx_l2d_err { | ||
| 134 | uint64_t u64; | ||
| 135 | struct cvmx_l2d_err_s { | ||
| 136 | uint64_t reserved_6_63:58; | ||
| 137 | uint64_t bmhclsel:1; | ||
| 138 | uint64_t ded_err:1; | ||
| 139 | uint64_t sec_err:1; | ||
| 140 | uint64_t ded_intena:1; | ||
| 141 | uint64_t sec_intena:1; | ||
| 142 | uint64_t ecc_ena:1; | ||
| 143 | } s; | ||
| 144 | struct cvmx_l2d_err_s cn30xx; | ||
| 145 | struct cvmx_l2d_err_s cn31xx; | ||
| 146 | struct cvmx_l2d_err_s cn38xx; | ||
| 147 | struct cvmx_l2d_err_s cn38xxp2; | ||
| 148 | struct cvmx_l2d_err_s cn50xx; | ||
| 149 | struct cvmx_l2d_err_s cn52xx; | ||
| 150 | struct cvmx_l2d_err_s cn52xxp1; | ||
| 151 | struct cvmx_l2d_err_s cn56xx; | ||
| 152 | struct cvmx_l2d_err_s cn56xxp1; | ||
| 153 | struct cvmx_l2d_err_s cn58xx; | ||
| 154 | struct cvmx_l2d_err_s cn58xxp1; | ||
| 155 | }; | ||
| 156 | |||
| 157 | union cvmx_l2d_fadr { | ||
| 158 | uint64_t u64; | ||
| 159 | struct cvmx_l2d_fadr_s { | ||
| 160 | uint64_t reserved_19_63:45; | ||
| 161 | uint64_t fadru:1; | ||
| 162 | uint64_t fowmsk:4; | ||
| 163 | uint64_t fset:3; | ||
| 164 | uint64_t fadr:11; | ||
| 165 | } s; | ||
| 166 | struct cvmx_l2d_fadr_cn30xx { | ||
| 167 | uint64_t reserved_18_63:46; | ||
| 168 | uint64_t fowmsk:4; | ||
| 169 | uint64_t reserved_13_13:1; | ||
| 170 | uint64_t fset:2; | ||
| 171 | uint64_t reserved_9_10:2; | ||
| 172 | uint64_t fadr:9; | ||
| 173 | } cn30xx; | ||
| 174 | struct cvmx_l2d_fadr_cn31xx { | ||
| 175 | uint64_t reserved_18_63:46; | ||
| 176 | uint64_t fowmsk:4; | ||
| 177 | uint64_t reserved_13_13:1; | ||
| 178 | uint64_t fset:2; | ||
| 179 | uint64_t reserved_10_10:1; | ||
| 180 | uint64_t fadr:10; | ||
| 181 | } cn31xx; | ||
| 182 | struct cvmx_l2d_fadr_cn38xx { | ||
| 183 | uint64_t reserved_18_63:46; | ||
| 184 | uint64_t fowmsk:4; | ||
| 185 | uint64_t fset:3; | ||
| 186 | uint64_t fadr:11; | ||
| 187 | } cn38xx; | ||
| 188 | struct cvmx_l2d_fadr_cn38xx cn38xxp2; | ||
| 189 | struct cvmx_l2d_fadr_cn50xx { | ||
| 190 | uint64_t reserved_18_63:46; | ||
| 191 | uint64_t fowmsk:4; | ||
| 192 | uint64_t fset:3; | ||
| 193 | uint64_t reserved_8_10:3; | ||
| 194 | uint64_t fadr:8; | ||
| 195 | } cn50xx; | ||
| 196 | struct cvmx_l2d_fadr_cn52xx { | ||
| 197 | uint64_t reserved_18_63:46; | ||
| 198 | uint64_t fowmsk:4; | ||
| 199 | uint64_t fset:3; | ||
| 200 | uint64_t reserved_10_10:1; | ||
| 201 | uint64_t fadr:10; | ||
| 202 | } cn52xx; | ||
| 203 | struct cvmx_l2d_fadr_cn52xx cn52xxp1; | ||
| 204 | struct cvmx_l2d_fadr_s cn56xx; | ||
| 205 | struct cvmx_l2d_fadr_s cn56xxp1; | ||
| 206 | struct cvmx_l2d_fadr_s cn58xx; | ||
| 207 | struct cvmx_l2d_fadr_s cn58xxp1; | ||
| 208 | }; | ||
| 209 | |||
| 210 | union cvmx_l2d_fsyn0 { | ||
| 211 | uint64_t u64; | ||
| 212 | struct cvmx_l2d_fsyn0_s { | ||
| 213 | uint64_t reserved_20_63:44; | ||
| 214 | uint64_t fsyn_ow1:10; | ||
| 215 | uint64_t fsyn_ow0:10; | ||
| 216 | } s; | ||
| 217 | struct cvmx_l2d_fsyn0_s cn30xx; | ||
| 218 | struct cvmx_l2d_fsyn0_s cn31xx; | ||
| 219 | struct cvmx_l2d_fsyn0_s cn38xx; | ||
| 220 | struct cvmx_l2d_fsyn0_s cn38xxp2; | ||
| 221 | struct cvmx_l2d_fsyn0_s cn50xx; | ||
| 222 | struct cvmx_l2d_fsyn0_s cn52xx; | ||
| 223 | struct cvmx_l2d_fsyn0_s cn52xxp1; | ||
| 224 | struct cvmx_l2d_fsyn0_s cn56xx; | ||
| 225 | struct cvmx_l2d_fsyn0_s cn56xxp1; | ||
| 226 | struct cvmx_l2d_fsyn0_s cn58xx; | ||
| 227 | struct cvmx_l2d_fsyn0_s cn58xxp1; | ||
| 228 | }; | ||
| 229 | |||
| 230 | union cvmx_l2d_fsyn1 { | ||
| 231 | uint64_t u64; | ||
| 232 | struct cvmx_l2d_fsyn1_s { | ||
| 233 | uint64_t reserved_20_63:44; | ||
| 234 | uint64_t fsyn_ow3:10; | ||
| 235 | uint64_t fsyn_ow2:10; | ||
| 236 | } s; | ||
| 237 | struct cvmx_l2d_fsyn1_s cn30xx; | ||
| 238 | struct cvmx_l2d_fsyn1_s cn31xx; | ||
| 239 | struct cvmx_l2d_fsyn1_s cn38xx; | ||
| 240 | struct cvmx_l2d_fsyn1_s cn38xxp2; | ||
| 241 | struct cvmx_l2d_fsyn1_s cn50xx; | ||
| 242 | struct cvmx_l2d_fsyn1_s cn52xx; | ||
| 243 | struct cvmx_l2d_fsyn1_s cn52xxp1; | ||
| 244 | struct cvmx_l2d_fsyn1_s cn56xx; | ||
| 245 | struct cvmx_l2d_fsyn1_s cn56xxp1; | ||
| 246 | struct cvmx_l2d_fsyn1_s cn58xx; | ||
| 247 | struct cvmx_l2d_fsyn1_s cn58xxp1; | ||
| 248 | }; | ||
| 249 | |||
| 250 | union cvmx_l2d_fus0 { | ||
| 251 | uint64_t u64; | ||
| 252 | struct cvmx_l2d_fus0_s { | ||
| 253 | uint64_t reserved_34_63:30; | ||
| 254 | uint64_t q0fus:34; | ||
| 255 | } s; | ||
| 256 | struct cvmx_l2d_fus0_s cn30xx; | ||
| 257 | struct cvmx_l2d_fus0_s cn31xx; | ||
| 258 | struct cvmx_l2d_fus0_s cn38xx; | ||
| 259 | struct cvmx_l2d_fus0_s cn38xxp2; | ||
| 260 | struct cvmx_l2d_fus0_s cn50xx; | ||
| 261 | struct cvmx_l2d_fus0_s cn52xx; | ||
| 262 | struct cvmx_l2d_fus0_s cn52xxp1; | ||
| 263 | struct cvmx_l2d_fus0_s cn56xx; | ||
| 264 | struct cvmx_l2d_fus0_s cn56xxp1; | ||
| 265 | struct cvmx_l2d_fus0_s cn58xx; | ||
| 266 | struct cvmx_l2d_fus0_s cn58xxp1; | ||
| 267 | }; | ||
| 268 | |||
| 269 | union cvmx_l2d_fus1 { | ||
| 270 | uint64_t u64; | ||
| 271 | struct cvmx_l2d_fus1_s { | ||
| 272 | uint64_t reserved_34_63:30; | ||
| 273 | uint64_t q1fus:34; | ||
| 274 | } s; | ||
| 275 | struct cvmx_l2d_fus1_s cn30xx; | ||
| 276 | struct cvmx_l2d_fus1_s cn31xx; | ||
| 277 | struct cvmx_l2d_fus1_s cn38xx; | ||
| 278 | struct cvmx_l2d_fus1_s cn38xxp2; | ||
| 279 | struct cvmx_l2d_fus1_s cn50xx; | ||
| 280 | struct cvmx_l2d_fus1_s cn52xx; | ||
| 281 | struct cvmx_l2d_fus1_s cn52xxp1; | ||
| 282 | struct cvmx_l2d_fus1_s cn56xx; | ||
| 283 | struct cvmx_l2d_fus1_s cn56xxp1; | ||
| 284 | struct cvmx_l2d_fus1_s cn58xx; | ||
| 285 | struct cvmx_l2d_fus1_s cn58xxp1; | ||
| 286 | }; | ||
| 287 | |||
| 288 | union cvmx_l2d_fus2 { | ||
| 289 | uint64_t u64; | ||
| 290 | struct cvmx_l2d_fus2_s { | ||
| 291 | uint64_t reserved_34_63:30; | ||
| 292 | uint64_t q2fus:34; | ||
| 293 | } s; | ||
| 294 | struct cvmx_l2d_fus2_s cn30xx; | ||
| 295 | struct cvmx_l2d_fus2_s cn31xx; | ||
| 296 | struct cvmx_l2d_fus2_s cn38xx; | ||
| 297 | struct cvmx_l2d_fus2_s cn38xxp2; | ||
| 298 | struct cvmx_l2d_fus2_s cn50xx; | ||
| 299 | struct cvmx_l2d_fus2_s cn52xx; | ||
| 300 | struct cvmx_l2d_fus2_s cn52xxp1; | ||
| 301 | struct cvmx_l2d_fus2_s cn56xx; | ||
| 302 | struct cvmx_l2d_fus2_s cn56xxp1; | ||
| 303 | struct cvmx_l2d_fus2_s cn58xx; | ||
| 304 | struct cvmx_l2d_fus2_s cn58xxp1; | ||
| 305 | }; | ||
| 306 | |||
| 307 | union cvmx_l2d_fus3 { | ||
| 308 | uint64_t u64; | ||
| 309 | struct cvmx_l2d_fus3_s { | ||
| 310 | uint64_t reserved_40_63:24; | ||
| 311 | uint64_t ema_ctl:3; | ||
| 312 | uint64_t reserved_34_36:3; | ||
| 313 | uint64_t q3fus:34; | ||
| 314 | } s; | ||
| 315 | struct cvmx_l2d_fus3_cn30xx { | ||
| 316 | uint64_t reserved_35_63:29; | ||
| 317 | uint64_t crip_64k:1; | ||
| 318 | uint64_t q3fus:34; | ||
| 319 | } cn30xx; | ||
| 320 | struct cvmx_l2d_fus3_cn31xx { | ||
| 321 | uint64_t reserved_35_63:29; | ||
| 322 | uint64_t crip_128k:1; | ||
| 323 | uint64_t q3fus:34; | ||
| 324 | } cn31xx; | ||
| 325 | struct cvmx_l2d_fus3_cn38xx { | ||
| 326 | uint64_t reserved_36_63:28; | ||
| 327 | uint64_t crip_256k:1; | ||
| 328 | uint64_t crip_512k:1; | ||
| 329 | uint64_t q3fus:34; | ||
| 330 | } cn38xx; | ||
| 331 | struct cvmx_l2d_fus3_cn38xx cn38xxp2; | ||
| 332 | struct cvmx_l2d_fus3_cn50xx { | ||
| 333 | uint64_t reserved_40_63:24; | ||
| 334 | uint64_t ema_ctl:3; | ||
| 335 | uint64_t reserved_36_36:1; | ||
| 336 | uint64_t crip_32k:1; | ||
| 337 | uint64_t crip_64k:1; | ||
| 338 | uint64_t q3fus:34; | ||
| 339 | } cn50xx; | ||
| 340 | struct cvmx_l2d_fus3_cn52xx { | ||
| 341 | uint64_t reserved_40_63:24; | ||
| 342 | uint64_t ema_ctl:3; | ||
| 343 | uint64_t reserved_36_36:1; | ||
| 344 | uint64_t crip_128k:1; | ||
| 345 | uint64_t crip_256k:1; | ||
| 346 | uint64_t q3fus:34; | ||
| 347 | } cn52xx; | ||
| 348 | struct cvmx_l2d_fus3_cn52xx cn52xxp1; | ||
| 349 | struct cvmx_l2d_fus3_cn56xx { | ||
| 350 | uint64_t reserved_40_63:24; | ||
| 351 | uint64_t ema_ctl:3; | ||
| 352 | uint64_t reserved_36_36:1; | ||
| 353 | uint64_t crip_512k:1; | ||
| 354 | uint64_t crip_1024k:1; | ||
| 355 | uint64_t q3fus:34; | ||
| 356 | } cn56xx; | ||
| 357 | struct cvmx_l2d_fus3_cn56xx cn56xxp1; | ||
| 358 | struct cvmx_l2d_fus3_cn58xx { | ||
| 359 | uint64_t reserved_39_63:25; | ||
| 360 | uint64_t ema_ctl:2; | ||
| 361 | uint64_t reserved_36_36:1; | ||
| 362 | uint64_t crip_512k:1; | ||
| 363 | uint64_t crip_1024k:1; | ||
| 364 | uint64_t q3fus:34; | ||
| 365 | } cn58xx; | ||
| 366 | struct cvmx_l2d_fus3_cn58xx cn58xxp1; | ||
| 367 | }; | ||
| 368 | |||
| 369 | #endif | ||
diff --git a/arch/mips/include/asm/octeon/cvmx-l2t-defs.h b/arch/mips/include/asm/octeon/cvmx-l2t-defs.h new file mode 100644 index 000000000000..2639a3f5ffc2 --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-l2t-defs.h | |||
| @@ -0,0 +1,141 @@ | |||
| 1 | /***********************license start*************** | ||
| 2 | * Author: Cavium Networks | ||
| 3 | * | ||
| 4 | * Contact: support@caviumnetworks.com | ||
| 5 | * This file is part of the OCTEON SDK | ||
| 6 | * | ||
| 7 | * Copyright (c) 2003-2008 Cavium Networks | ||
| 8 | * | ||
| 9 | * This file is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License, Version 2, as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | * | ||
| 13 | * This file is distributed in the hope that it will be useful, but | ||
| 14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
| 15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
| 16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
| 17 | * details. | ||
| 18 | * | ||
| 19 | * You should have received a copy of the GNU General Public License | ||
| 20 | * along with this file; if not, write to the Free Software | ||
| 21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 22 | * or visit http://www.gnu.org/licenses/. | ||
| 23 | * | ||
| 24 | * This file may also be available under a different license from Cavium. | ||
| 25 | * Contact Cavium Networks for more information | ||
| 26 | ***********************license end**************************************/ | ||
| 27 | |||
| 28 | #ifndef __CVMX_L2T_DEFS_H__ | ||
| 29 | #define __CVMX_L2T_DEFS_H__ | ||
| 30 | |||
| 31 | #define CVMX_L2T_ERR \ | ||
| 32 | CVMX_ADD_IO_SEG(0x0001180080000008ull) | ||
| 33 | |||
| 34 | union cvmx_l2t_err { | ||
| 35 | uint64_t u64; | ||
| 36 | struct cvmx_l2t_err_s { | ||
| 37 | uint64_t reserved_29_63:35; | ||
| 38 | uint64_t fadru:1; | ||
| 39 | uint64_t lck_intena2:1; | ||
| 40 | uint64_t lckerr2:1; | ||
| 41 | uint64_t lck_intena:1; | ||
| 42 | uint64_t lckerr:1; | ||
| 43 | uint64_t fset:3; | ||
| 44 | uint64_t fadr:10; | ||
| 45 | uint64_t fsyn:6; | ||
| 46 | uint64_t ded_err:1; | ||
| 47 | uint64_t sec_err:1; | ||
| 48 | uint64_t ded_intena:1; | ||
| 49 | uint64_t sec_intena:1; | ||
| 50 | uint64_t ecc_ena:1; | ||
| 51 | } s; | ||
| 52 | struct cvmx_l2t_err_cn30xx { | ||
| 53 | uint64_t reserved_28_63:36; | ||
| 54 | uint64_t lck_intena2:1; | ||
| 55 | uint64_t lckerr2:1; | ||
| 56 | uint64_t lck_intena:1; | ||
| 57 | uint64_t lckerr:1; | ||
| 58 | uint64_t reserved_23_23:1; | ||
| 59 | uint64_t fset:2; | ||
| 60 | uint64_t reserved_19_20:2; | ||
| 61 | uint64_t fadr:8; | ||
| 62 | uint64_t fsyn:6; | ||
| 63 | uint64_t ded_err:1; | ||
| 64 | uint64_t sec_err:1; | ||
| 65 | uint64_t ded_intena:1; | ||
| 66 | uint64_t sec_intena:1; | ||
| 67 | uint64_t ecc_ena:1; | ||
| 68 | } cn30xx; | ||
| 69 | struct cvmx_l2t_err_cn31xx { | ||
| 70 | uint64_t reserved_28_63:36; | ||
| 71 | uint64_t lck_intena2:1; | ||
| 72 | uint64_t lckerr2:1; | ||
| 73 | uint64_t lck_intena:1; | ||
| 74 | uint64_t lckerr:1; | ||
| 75 | uint64_t reserved_23_23:1; | ||
| 76 | uint64_t fset:2; | ||
| 77 | uint64_t reserved_20_20:1; | ||
| 78 | uint64_t fadr:9; | ||
| 79 | uint64_t fsyn:6; | ||
| 80 | uint64_t ded_err:1; | ||
| 81 | uint64_t sec_err:1; | ||
| 82 | uint64_t ded_intena:1; | ||
| 83 | uint64_t sec_intena:1; | ||
| 84 | uint64_t ecc_ena:1; | ||
| 85 | } cn31xx; | ||
| 86 | struct cvmx_l2t_err_cn38xx { | ||
| 87 | uint64_t reserved_28_63:36; | ||
| 88 | uint64_t lck_intena2:1; | ||
| 89 | uint64_t lckerr2:1; | ||
| 90 | uint64_t lck_intena:1; | ||
| 91 | uint64_t lckerr:1; | ||
| 92 | uint64_t fset:3; | ||
| 93 | uint64_t fadr:10; | ||
| 94 | uint64_t fsyn:6; | ||
| 95 | uint64_t ded_err:1; | ||
| 96 | uint64_t sec_err:1; | ||
| 97 | uint64_t ded_intena:1; | ||
| 98 | uint64_t sec_intena:1; | ||
| 99 | uint64_t ecc_ena:1; | ||
| 100 | } cn38xx; | ||
| 101 | struct cvmx_l2t_err_cn38xx cn38xxp2; | ||
| 102 | struct cvmx_l2t_err_cn50xx { | ||
| 103 | uint64_t reserved_28_63:36; | ||
| 104 | uint64_t lck_intena2:1; | ||
| 105 | uint64_t lckerr2:1; | ||
| 106 | uint64_t lck_intena:1; | ||
| 107 | uint64_t lckerr:1; | ||
| 108 | uint64_t fset:3; | ||
| 109 | uint64_t reserved_18_20:3; | ||
| 110 | uint64_t fadr:7; | ||
| 111 | uint64_t fsyn:6; | ||
| 112 | uint64_t ded_err:1; | ||
| 113 | uint64_t sec_err:1; | ||
| 114 | uint64_t ded_intena:1; | ||
| 115 | uint64_t sec_intena:1; | ||
| 116 | uint64_t ecc_ena:1; | ||
| 117 | } cn50xx; | ||
| 118 | struct cvmx_l2t_err_cn52xx { | ||
| 119 | uint64_t reserved_28_63:36; | ||
| 120 | uint64_t lck_intena2:1; | ||
| 121 | uint64_t lckerr2:1; | ||
| 122 | uint64_t lck_intena:1; | ||
| 123 | uint64_t lckerr:1; | ||
| 124 | uint64_t fset:3; | ||
| 125 | uint64_t reserved_20_20:1; | ||
| 126 | uint64_t fadr:9; | ||
| 127 | uint64_t fsyn:6; | ||
| 128 | uint64_t ded_err:1; | ||
| 129 | uint64_t sec_err:1; | ||
| 130 | uint64_t ded_intena:1; | ||
| 131 | uint64_t sec_intena:1; | ||
| 132 | uint64_t ecc_ena:1; | ||
| 133 | } cn52xx; | ||
| 134 | struct cvmx_l2t_err_cn52xx cn52xxp1; | ||
| 135 | struct cvmx_l2t_err_s cn56xx; | ||
| 136 | struct cvmx_l2t_err_s cn56xxp1; | ||
| 137 | struct cvmx_l2t_err_s cn58xx; | ||
| 138 | struct cvmx_l2t_err_s cn58xxp1; | ||
| 139 | }; | ||
| 140 | |||
| 141 | #endif | ||
diff --git a/arch/mips/include/asm/octeon/cvmx-led-defs.h b/arch/mips/include/asm/octeon/cvmx-led-defs.h new file mode 100644 index 000000000000..16f174a4dadf --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-led-defs.h | |||
| @@ -0,0 +1,240 @@ | |||
| 1 | /***********************license start*************** | ||
| 2 | * Author: Cavium Networks | ||
| 3 | * | ||
| 4 | * Contact: support@caviumnetworks.com | ||
| 5 | * This file is part of the OCTEON SDK | ||
| 6 | * | ||
| 7 | * Copyright (c) 2003-2008 Cavium Networks | ||
| 8 | * | ||
| 9 | * This file is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License, Version 2, as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | * | ||
| 13 | * This file is distributed in the hope that it will be useful, but | ||
| 14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
| 15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
| 16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
| 17 | * details. | ||
| 18 | * | ||
| 19 | * You should have received a copy of the GNU General Public License | ||
| 20 | * along with this file; if not, write to the Free Software | ||
| 21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 22 | * or visit http://www.gnu.org/licenses/. | ||
| 23 | * | ||
| 24 | * This file may also be available under a different license from Cavium. | ||
| 25 | * Contact Cavium Networks for more information | ||
| 26 | ***********************license end**************************************/ | ||
| 27 | |||
| 28 | #ifndef __CVMX_LED_DEFS_H__ | ||
| 29 | #define __CVMX_LED_DEFS_H__ | ||
| 30 | |||
| 31 | #define CVMX_LED_BLINK \ | ||
| 32 | CVMX_ADD_IO_SEG(0x0001180000001A48ull) | ||
| 33 | #define CVMX_LED_CLK_PHASE \ | ||
| 34 | CVMX_ADD_IO_SEG(0x0001180000001A08ull) | ||
| 35 | #define CVMX_LED_CYLON \ | ||
| 36 | CVMX_ADD_IO_SEG(0x0001180000001AF8ull) | ||
| 37 | #define CVMX_LED_DBG \ | ||
| 38 | CVMX_ADD_IO_SEG(0x0001180000001A18ull) | ||
| 39 | #define CVMX_LED_EN \ | ||
| 40 | CVMX_ADD_IO_SEG(0x0001180000001A00ull) | ||
| 41 | #define CVMX_LED_POLARITY \ | ||
| 42 | CVMX_ADD_IO_SEG(0x0001180000001A50ull) | ||
| 43 | #define CVMX_LED_PRT \ | ||
| 44 | CVMX_ADD_IO_SEG(0x0001180000001A10ull) | ||
| 45 | #define CVMX_LED_PRT_FMT \ | ||
| 46 | CVMX_ADD_IO_SEG(0x0001180000001A30ull) | ||
| 47 | #define CVMX_LED_PRT_STATUSX(offset) \ | ||
| 48 | CVMX_ADD_IO_SEG(0x0001180000001A80ull + (((offset) & 7) * 8)) | ||
| 49 | #define CVMX_LED_UDD_CNTX(offset) \ | ||
| 50 | CVMX_ADD_IO_SEG(0x0001180000001A20ull + (((offset) & 1) * 8)) | ||
| 51 | #define CVMX_LED_UDD_DATX(offset) \ | ||
| 52 | CVMX_ADD_IO_SEG(0x0001180000001A38ull + (((offset) & 1) * 8)) | ||
| 53 | #define CVMX_LED_UDD_DAT_CLRX(offset) \ | ||
| 54 | CVMX_ADD_IO_SEG(0x0001180000001AC8ull + (((offset) & 1) * 16)) | ||
| 55 | #define CVMX_LED_UDD_DAT_SETX(offset) \ | ||
| 56 | CVMX_ADD_IO_SEG(0x0001180000001AC0ull + (((offset) & 1) * 16)) | ||
| 57 | |||
| 58 | union cvmx_led_blink { | ||
| 59 | uint64_t u64; | ||
| 60 | struct cvmx_led_blink_s { | ||
| 61 | uint64_t reserved_8_63:56; | ||
| 62 | uint64_t rate:8; | ||
| 63 | } s; | ||
| 64 | struct cvmx_led_blink_s cn38xx; | ||
| 65 | struct cvmx_led_blink_s cn38xxp2; | ||
| 66 | struct cvmx_led_blink_s cn56xx; | ||
| 67 | struct cvmx_led_blink_s cn56xxp1; | ||
| 68 | struct cvmx_led_blink_s cn58xx; | ||
| 69 | struct cvmx_led_blink_s cn58xxp1; | ||
| 70 | }; | ||
| 71 | |||
| 72 | union cvmx_led_clk_phase { | ||
| 73 | uint64_t u64; | ||
| 74 | struct cvmx_led_clk_phase_s { | ||
| 75 | uint64_t reserved_7_63:57; | ||
| 76 | uint64_t phase:7; | ||
| 77 | } s; | ||
| 78 | struct cvmx_led_clk_phase_s cn38xx; | ||
| 79 | struct cvmx_led_clk_phase_s cn38xxp2; | ||
| 80 | struct cvmx_led_clk_phase_s cn56xx; | ||
| 81 | struct cvmx_led_clk_phase_s cn56xxp1; | ||
| 82 | struct cvmx_led_clk_phase_s cn58xx; | ||
| 83 | struct cvmx_led_clk_phase_s cn58xxp1; | ||
| 84 | }; | ||
| 85 | |||
| 86 | union cvmx_led_cylon { | ||
| 87 | uint64_t u64; | ||
| 88 | struct cvmx_led_cylon_s { | ||
| 89 | uint64_t reserved_16_63:48; | ||
| 90 | uint64_t rate:16; | ||
| 91 | } s; | ||
| 92 | struct cvmx_led_cylon_s cn38xx; | ||
| 93 | struct cvmx_led_cylon_s cn38xxp2; | ||
| 94 | struct cvmx_led_cylon_s cn56xx; | ||
| 95 | struct cvmx_led_cylon_s cn56xxp1; | ||
| 96 | struct cvmx_led_cylon_s cn58xx; | ||
| 97 | struct cvmx_led_cylon_s cn58xxp1; | ||
| 98 | }; | ||
| 99 | |||
| 100 | union cvmx_led_dbg { | ||
| 101 | uint64_t u64; | ||
| 102 | struct cvmx_led_dbg_s { | ||
| 103 | uint64_t reserved_1_63:63; | ||
| 104 | uint64_t dbg_en:1; | ||
| 105 | } s; | ||
| 106 | struct cvmx_led_dbg_s cn38xx; | ||
| 107 | struct cvmx_led_dbg_s cn38xxp2; | ||
| 108 | struct cvmx_led_dbg_s cn56xx; | ||
| 109 | struct cvmx_led_dbg_s cn56xxp1; | ||
| 110 | struct cvmx_led_dbg_s cn58xx; | ||
| 111 | struct cvmx_led_dbg_s cn58xxp1; | ||
| 112 | }; | ||
| 113 | |||
| 114 | union cvmx_led_en { | ||
| 115 | uint64_t u64; | ||
| 116 | struct cvmx_led_en_s { | ||
| 117 | uint64_t reserved_1_63:63; | ||
| 118 | uint64_t en:1; | ||
| 119 | } s; | ||
| 120 | struct cvmx_led_en_s cn38xx; | ||
| 121 | struct cvmx_led_en_s cn38xxp2; | ||
| 122 | struct cvmx_led_en_s cn56xx; | ||
| 123 | struct cvmx_led_en_s cn56xxp1; | ||
| 124 | struct cvmx_led_en_s cn58xx; | ||
| 125 | struct cvmx_led_en_s cn58xxp1; | ||
| 126 | }; | ||
| 127 | |||
| 128 | union cvmx_led_polarity { | ||
| 129 | uint64_t u64; | ||
| 130 | struct cvmx_led_polarity_s { | ||
| 131 | uint64_t reserved_1_63:63; | ||
| 132 | uint64_t polarity:1; | ||
| 133 | } s; | ||
| 134 | struct cvmx_led_polarity_s cn38xx; | ||
| 135 | struct cvmx_led_polarity_s cn38xxp2; | ||
| 136 | struct cvmx_led_polarity_s cn56xx; | ||
| 137 | struct cvmx_led_polarity_s cn56xxp1; | ||
| 138 | struct cvmx_led_polarity_s cn58xx; | ||
| 139 | struct cvmx_led_polarity_s cn58xxp1; | ||
| 140 | }; | ||
| 141 | |||
| 142 | union cvmx_led_prt { | ||
| 143 | uint64_t u64; | ||
| 144 | struct cvmx_led_prt_s { | ||
| 145 | uint64_t reserved_8_63:56; | ||
| 146 | uint64_t prt_en:8; | ||
| 147 | } s; | ||
| 148 | struct cvmx_led_prt_s cn38xx; | ||
| 149 | struct cvmx_led_prt_s cn38xxp2; | ||
| 150 | struct cvmx_led_prt_s cn56xx; | ||
| 151 | struct cvmx_led_prt_s cn56xxp1; | ||
| 152 | struct cvmx_led_prt_s cn58xx; | ||
| 153 | struct cvmx_led_prt_s cn58xxp1; | ||
| 154 | }; | ||
| 155 | |||
| 156 | union cvmx_led_prt_fmt { | ||
| 157 | uint64_t u64; | ||
| 158 | struct cvmx_led_prt_fmt_s { | ||
| 159 | uint64_t reserved_4_63:60; | ||
| 160 | uint64_t format:4; | ||
| 161 | } s; | ||
| 162 | struct cvmx_led_prt_fmt_s cn38xx; | ||
| 163 | struct cvmx_led_prt_fmt_s cn38xxp2; | ||
| 164 | struct cvmx_led_prt_fmt_s cn56xx; | ||
| 165 | struct cvmx_led_prt_fmt_s cn56xxp1; | ||
| 166 | struct cvmx_led_prt_fmt_s cn58xx; | ||
| 167 | struct cvmx_led_prt_fmt_s cn58xxp1; | ||
| 168 | }; | ||
| 169 | |||
| 170 | union cvmx_led_prt_statusx { | ||
| 171 | uint64_t u64; | ||
| 172 | struct cvmx_led_prt_statusx_s { | ||
| 173 | uint64_t reserved_6_63:58; | ||
| 174 | uint64_t status:6; | ||
| 175 | } s; | ||
| 176 | struct cvmx_led_prt_statusx_s cn38xx; | ||
| 177 | struct cvmx_led_prt_statusx_s cn38xxp2; | ||
| 178 | struct cvmx_led_prt_statusx_s cn56xx; | ||
| 179 | struct cvmx_led_prt_statusx_s cn56xxp1; | ||
| 180 | struct cvmx_led_prt_statusx_s cn58xx; | ||
| 181 | struct cvmx_led_prt_statusx_s cn58xxp1; | ||
| 182 | }; | ||
| 183 | |||
| 184 | union cvmx_led_udd_cntx { | ||
| 185 | uint64_t u64; | ||
| 186 | struct cvmx_led_udd_cntx_s { | ||
| 187 | uint64_t reserved_6_63:58; | ||
| 188 | uint64_t cnt:6; | ||
| 189 | } s; | ||
| 190 | struct cvmx_led_udd_cntx_s cn38xx; | ||
| 191 | struct cvmx_led_udd_cntx_s cn38xxp2; | ||
| 192 | struct cvmx_led_udd_cntx_s cn56xx; | ||
| 193 | struct cvmx_led_udd_cntx_s cn56xxp1; | ||
| 194 | struct cvmx_led_udd_cntx_s cn58xx; | ||
| 195 | struct cvmx_led_udd_cntx_s cn58xxp1; | ||
| 196 | }; | ||
| 197 | |||
| 198 | union cvmx_led_udd_datx { | ||
| 199 | uint64_t u64; | ||
| 200 | struct cvmx_led_udd_datx_s { | ||
| 201 | uint64_t reserved_32_63:32; | ||
| 202 | uint64_t dat:32; | ||
| 203 | } s; | ||
| 204 | struct cvmx_led_udd_datx_s cn38xx; | ||
| 205 | struct cvmx_led_udd_datx_s cn38xxp2; | ||
| 206 | struct cvmx_led_udd_datx_s cn56xx; | ||
| 207 | struct cvmx_led_udd_datx_s cn56xxp1; | ||
| 208 | struct cvmx_led_udd_datx_s cn58xx; | ||
| 209 | struct cvmx_led_udd_datx_s cn58xxp1; | ||
| 210 | }; | ||
| 211 | |||
| 212 | union cvmx_led_udd_dat_clrx { | ||
| 213 | uint64_t u64; | ||
| 214 | struct cvmx_led_udd_dat_clrx_s { | ||
| 215 | uint64_t reserved_32_63:32; | ||
| 216 | uint64_t clr:32; | ||
| 217 | } s; | ||
| 218 | struct cvmx_led_udd_dat_clrx_s cn38xx; | ||
| 219 | struct cvmx_led_udd_dat_clrx_s cn38xxp2; | ||
| 220 | struct cvmx_led_udd_dat_clrx_s cn56xx; | ||
| 221 | struct cvmx_led_udd_dat_clrx_s cn56xxp1; | ||
| 222 | struct cvmx_led_udd_dat_clrx_s cn58xx; | ||
| 223 | struct cvmx_led_udd_dat_clrx_s cn58xxp1; | ||
| 224 | }; | ||
| 225 | |||
| 226 | union cvmx_led_udd_dat_setx { | ||
| 227 | uint64_t u64; | ||
| 228 | struct cvmx_led_udd_dat_setx_s { | ||
| 229 | uint64_t reserved_32_63:32; | ||
| 230 | uint64_t set:32; | ||
| 231 | } s; | ||
| 232 | struct cvmx_led_udd_dat_setx_s cn38xx; | ||
| 233 | struct cvmx_led_udd_dat_setx_s cn38xxp2; | ||
| 234 | struct cvmx_led_udd_dat_setx_s cn56xx; | ||
| 235 | struct cvmx_led_udd_dat_setx_s cn56xxp1; | ||
| 236 | struct cvmx_led_udd_dat_setx_s cn58xx; | ||
| 237 | struct cvmx_led_udd_dat_setx_s cn58xxp1; | ||
| 238 | }; | ||
| 239 | |||
| 240 | #endif | ||
diff --git a/arch/mips/include/asm/octeon/cvmx-mio-defs.h b/arch/mips/include/asm/octeon/cvmx-mio-defs.h new file mode 100644 index 000000000000..6555f0530988 --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-mio-defs.h | |||
| @@ -0,0 +1,2004 @@ | |||
| 1 | /***********************license start*************** | ||
| 2 | * Author: Cavium Networks | ||
| 3 | * | ||
| 4 | * Contact: support@caviumnetworks.com | ||
| 5 | * This file is part of the OCTEON SDK | ||
| 6 | * | ||
| 7 | * Copyright (c) 2003-2008 Cavium Networks | ||
| 8 | * | ||
| 9 | * This file is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License, Version 2, as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | * | ||
| 13 | * This file is distributed in the hope that it will be useful, but | ||
| 14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
| 15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
| 16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
| 17 | * details. | ||
| 18 | * | ||
| 19 | * You should have received a copy of the GNU General Public License | ||
| 20 | * along with this file; if not, write to the Free Software | ||
| 21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 22 | * or visit http://www.gnu.org/licenses/. | ||
| 23 | * | ||
| 24 | * This file may also be available under a different license from Cavium. | ||
| 25 | * Contact Cavium Networks for more information | ||
| 26 | ***********************license end**************************************/ | ||
| 27 | |||
| 28 | #ifndef __CVMX_MIO_DEFS_H__ | ||
| 29 | #define __CVMX_MIO_DEFS_H__ | ||
| 30 | |||
| 31 | #define CVMX_MIO_BOOT_BIST_STAT \ | ||
| 32 | CVMX_ADD_IO_SEG(0x00011800000000F8ull) | ||
| 33 | #define CVMX_MIO_BOOT_COMP \ | ||
| 34 | CVMX_ADD_IO_SEG(0x00011800000000B8ull) | ||
| 35 | #define CVMX_MIO_BOOT_DMA_CFGX(offset) \ | ||
| 36 | CVMX_ADD_IO_SEG(0x0001180000000100ull + (((offset) & 3) * 8)) | ||
| 37 | #define CVMX_MIO_BOOT_DMA_INTX(offset) \ | ||
| 38 | CVMX_ADD_IO_SEG(0x0001180000000138ull + (((offset) & 3) * 8)) | ||
| 39 | #define CVMX_MIO_BOOT_DMA_INT_ENX(offset) \ | ||
| 40 | CVMX_ADD_IO_SEG(0x0001180000000150ull + (((offset) & 3) * 8)) | ||
| 41 | #define CVMX_MIO_BOOT_DMA_TIMX(offset) \ | ||
| 42 | CVMX_ADD_IO_SEG(0x0001180000000120ull + (((offset) & 3) * 8)) | ||
| 43 | #define CVMX_MIO_BOOT_ERR \ | ||
| 44 | CVMX_ADD_IO_SEG(0x00011800000000A0ull) | ||
| 45 | #define CVMX_MIO_BOOT_INT \ | ||
| 46 | CVMX_ADD_IO_SEG(0x00011800000000A8ull) | ||
| 47 | #define CVMX_MIO_BOOT_LOC_ADR \ | ||
| 48 | CVMX_ADD_IO_SEG(0x0001180000000090ull) | ||
| 49 | #define CVMX_MIO_BOOT_LOC_CFGX(offset) \ | ||
| 50 | CVMX_ADD_IO_SEG(0x0001180000000080ull + (((offset) & 1) * 8)) | ||
| 51 | #define CVMX_MIO_BOOT_LOC_DAT \ | ||
| 52 | CVMX_ADD_IO_SEG(0x0001180000000098ull) | ||
| 53 | #define CVMX_MIO_BOOT_PIN_DEFS \ | ||
| 54 | CVMX_ADD_IO_SEG(0x00011800000000C0ull) | ||
| 55 | #define CVMX_MIO_BOOT_REG_CFGX(offset) \ | ||
| 56 | CVMX_ADD_IO_SEG(0x0001180000000000ull + (((offset) & 7) * 8)) | ||
| 57 | #define CVMX_MIO_BOOT_REG_TIMX(offset) \ | ||
| 58 | CVMX_ADD_IO_SEG(0x0001180000000040ull + (((offset) & 7) * 8)) | ||
| 59 | #define CVMX_MIO_BOOT_THR \ | ||
| 60 | CVMX_ADD_IO_SEG(0x00011800000000B0ull) | ||
| 61 | #define CVMX_MIO_FUS_BNK_DATX(offset) \ | ||
| 62 | CVMX_ADD_IO_SEG(0x0001180000001520ull + (((offset) & 3) * 8)) | ||
| 63 | #define CVMX_MIO_FUS_DAT0 \ | ||
| 64 | CVMX_ADD_IO_SEG(0x0001180000001400ull) | ||
| 65 | #define CVMX_MIO_FUS_DAT1 \ | ||
| 66 | CVMX_ADD_IO_SEG(0x0001180000001408ull) | ||
| 67 | #define CVMX_MIO_FUS_DAT2 \ | ||
| 68 | CVMX_ADD_IO_SEG(0x0001180000001410ull) | ||
| 69 | #define CVMX_MIO_FUS_DAT3 \ | ||
| 70 | CVMX_ADD_IO_SEG(0x0001180000001418ull) | ||
| 71 | #define CVMX_MIO_FUS_EMA \ | ||
| 72 | CVMX_ADD_IO_SEG(0x0001180000001550ull) | ||
| 73 | #define CVMX_MIO_FUS_PDF \ | ||
| 74 | CVMX_ADD_IO_SEG(0x0001180000001420ull) | ||
| 75 | #define CVMX_MIO_FUS_PLL \ | ||
| 76 | CVMX_ADD_IO_SEG(0x0001180000001580ull) | ||
| 77 | #define CVMX_MIO_FUS_PROG \ | ||
| 78 | CVMX_ADD_IO_SEG(0x0001180000001510ull) | ||
| 79 | #define CVMX_MIO_FUS_PROG_TIMES \ | ||
| 80 | CVMX_ADD_IO_SEG(0x0001180000001518ull) | ||
| 81 | #define CVMX_MIO_FUS_RCMD \ | ||
| 82 | CVMX_ADD_IO_SEG(0x0001180000001500ull) | ||
| 83 | #define CVMX_MIO_FUS_SPR_REPAIR_RES \ | ||
| 84 | CVMX_ADD_IO_SEG(0x0001180000001548ull) | ||
| 85 | #define CVMX_MIO_FUS_SPR_REPAIR_SUM \ | ||
| 86 | CVMX_ADD_IO_SEG(0x0001180000001540ull) | ||
| 87 | #define CVMX_MIO_FUS_UNLOCK \ | ||
| 88 | CVMX_ADD_IO_SEG(0x0001180000001578ull) | ||
| 89 | #define CVMX_MIO_FUS_WADR \ | ||
| 90 | CVMX_ADD_IO_SEG(0x0001180000001508ull) | ||
| 91 | #define CVMX_MIO_NDF_DMA_CFG \ | ||
| 92 | CVMX_ADD_IO_SEG(0x0001180000000168ull) | ||
| 93 | #define CVMX_MIO_NDF_DMA_INT \ | ||
| 94 | CVMX_ADD_IO_SEG(0x0001180000000170ull) | ||
| 95 | #define CVMX_MIO_NDF_DMA_INT_EN \ | ||
| 96 | CVMX_ADD_IO_SEG(0x0001180000000178ull) | ||
| 97 | #define CVMX_MIO_PLL_CTL \ | ||
| 98 | CVMX_ADD_IO_SEG(0x0001180000001448ull) | ||
| 99 | #define CVMX_MIO_PLL_SETTING \ | ||
| 100 | CVMX_ADD_IO_SEG(0x0001180000001440ull) | ||
| 101 | #define CVMX_MIO_TWSX_INT(offset) \ | ||
| 102 | CVMX_ADD_IO_SEG(0x0001180000001010ull + (((offset) & 1) * 512)) | ||
| 103 | #define CVMX_MIO_TWSX_SW_TWSI(offset) \ | ||
| 104 | CVMX_ADD_IO_SEG(0x0001180000001000ull + (((offset) & 1) * 512)) | ||
| 105 | #define CVMX_MIO_TWSX_SW_TWSI_EXT(offset) \ | ||
| 106 | CVMX_ADD_IO_SEG(0x0001180000001018ull + (((offset) & 1) * 512)) | ||
| 107 | #define CVMX_MIO_TWSX_TWSI_SW(offset) \ | ||
| 108 | CVMX_ADD_IO_SEG(0x0001180000001008ull + (((offset) & 1) * 512)) | ||
| 109 | #define CVMX_MIO_UART2_DLH \ | ||
| 110 | CVMX_ADD_IO_SEG(0x0001180000000488ull) | ||
| 111 | #define CVMX_MIO_UART2_DLL \ | ||
| 112 | CVMX_ADD_IO_SEG(0x0001180000000480ull) | ||
| 113 | #define CVMX_MIO_UART2_FAR \ | ||
| 114 | CVMX_ADD_IO_SEG(0x0001180000000520ull) | ||
| 115 | #define CVMX_MIO_UART2_FCR \ | ||
| 116 | CVMX_ADD_IO_SEG(0x0001180000000450ull) | ||
| 117 | #define CVMX_MIO_UART2_HTX \ | ||
| 118 | CVMX_ADD_IO_SEG(0x0001180000000708ull) | ||
| 119 | #define CVMX_MIO_UART2_IER \ | ||
| 120 | CVMX_ADD_IO_SEG(0x0001180000000408ull) | ||
| 121 | #define CVMX_MIO_UART2_IIR \ | ||
| 122 | CVMX_ADD_IO_SEG(0x0001180000000410ull) | ||
| 123 | #define CVMX_MIO_UART2_LCR \ | ||
| 124 | CVMX_ADD_IO_SEG(0x0001180000000418ull) | ||
| 125 | #define CVMX_MIO_UART2_LSR \ | ||
| 126 | CVMX_ADD_IO_SEG(0x0001180000000428ull) | ||
| 127 | #define CVMX_MIO_UART2_MCR \ | ||
| 128 | CVMX_ADD_IO_SEG(0x0001180000000420ull) | ||
| 129 | #define CVMX_MIO_UART2_MSR \ | ||
| 130 | CVMX_ADD_IO_SEG(0x0001180000000430ull) | ||
| 131 | #define CVMX_MIO_UART2_RBR \ | ||
| 132 | CVMX_ADD_IO_SEG(0x0001180000000400ull) | ||
| 133 | #define CVMX_MIO_UART2_RFL \ | ||
| 134 | CVMX_ADD_IO_SEG(0x0001180000000608ull) | ||
| 135 | #define CVMX_MIO_UART2_RFW \ | ||
| 136 | CVMX_ADD_IO_SEG(0x0001180000000530ull) | ||
| 137 | #define CVMX_MIO_UART2_SBCR \ | ||
| 138 | CVMX_ADD_IO_SEG(0x0001180000000620ull) | ||
| 139 | #define CVMX_MIO_UART2_SCR \ | ||
| 140 | CVMX_ADD_IO_SEG(0x0001180000000438ull) | ||
| 141 | #define CVMX_MIO_UART2_SFE \ | ||
| 142 | CVMX_ADD_IO_SEG(0x0001180000000630ull) | ||
| 143 | #define CVMX_MIO_UART2_SRR \ | ||
| 144 | CVMX_ADD_IO_SEG(0x0001180000000610ull) | ||
| 145 | #define CVMX_MIO_UART2_SRT \ | ||
| 146 | CVMX_ADD_IO_SEG(0x0001180000000638ull) | ||
| 147 | #define CVMX_MIO_UART2_SRTS \ | ||
| 148 | CVMX_ADD_IO_SEG(0x0001180000000618ull) | ||
| 149 | #define CVMX_MIO_UART2_STT \ | ||
| 150 | CVMX_ADD_IO_SEG(0x0001180000000700ull) | ||
| 151 | #define CVMX_MIO_UART2_TFL \ | ||
| 152 | CVMX_ADD_IO_SEG(0x0001180000000600ull) | ||
| 153 | #define CVMX_MIO_UART2_TFR \ | ||
| 154 | CVMX_ADD_IO_SEG(0x0001180000000528ull) | ||
| 155 | #define CVMX_MIO_UART2_THR \ | ||
| 156 | CVMX_ADD_IO_SEG(0x0001180000000440ull) | ||
| 157 | #define CVMX_MIO_UART2_USR \ | ||
| 158 | CVMX_ADD_IO_SEG(0x0001180000000538ull) | ||
| 159 | #define CVMX_MIO_UARTX_DLH(offset) \ | ||
| 160 | CVMX_ADD_IO_SEG(0x0001180000000888ull + (((offset) & 1) * 1024)) | ||
| 161 | #define CVMX_MIO_UARTX_DLL(offset) \ | ||
| 162 | CVMX_ADD_IO_SEG(0x0001180000000880ull + (((offset) & 1) * 1024)) | ||
| 163 | #define CVMX_MIO_UARTX_FAR(offset) \ | ||
| 164 | CVMX_ADD_IO_SEG(0x0001180000000920ull + (((offset) & 1) * 1024)) | ||
| 165 | #define CVMX_MIO_UARTX_FCR(offset) \ | ||
| 166 | CVMX_ADD_IO_SEG(0x0001180000000850ull + (((offset) & 1) * 1024)) | ||
| 167 | #define CVMX_MIO_UARTX_HTX(offset) \ | ||
| 168 | CVMX_ADD_IO_SEG(0x0001180000000B08ull + (((offset) & 1) * 1024)) | ||
| 169 | #define CVMX_MIO_UARTX_IER(offset) \ | ||
| 170 | CVMX_ADD_IO_SEG(0x0001180000000808ull + (((offset) & 1) * 1024)) | ||
| 171 | #define CVMX_MIO_UARTX_IIR(offset) \ | ||
| 172 | CVMX_ADD_IO_SEG(0x0001180000000810ull + (((offset) & 1) * 1024)) | ||
| 173 | #define CVMX_MIO_UARTX_LCR(offset) \ | ||
| 174 | CVMX_ADD_IO_SEG(0x0001180000000818ull + (((offset) & 1) * 1024)) | ||
| 175 | #define CVMX_MIO_UARTX_LSR(offset) \ | ||
| 176 | CVMX_ADD_IO_SEG(0x0001180000000828ull + (((offset) & 1) * 1024)) | ||
| 177 | #define CVMX_MIO_UARTX_MCR(offset) \ | ||
| 178 | CVMX_ADD_IO_SEG(0x0001180000000820ull + (((offset) & 1) * 1024)) | ||
| 179 | #define CVMX_MIO_UARTX_MSR(offset) \ | ||
| 180 | CVMX_ADD_IO_SEG(0x0001180000000830ull + (((offset) & 1) * 1024)) | ||
| 181 | #define CVMX_MIO_UARTX_RBR(offset) \ | ||
| 182 | CVMX_ADD_IO_SEG(0x0001180000000800ull + (((offset) & 1) * 1024)) | ||
| 183 | #define CVMX_MIO_UARTX_RFL(offset) \ | ||
| 184 | CVMX_ADD_IO_SEG(0x0001180000000A08ull + (((offset) & 1) * 1024)) | ||
| 185 | #define CVMX_MIO_UARTX_RFW(offset) \ | ||
| 186 | CVMX_ADD_IO_SEG(0x0001180000000930ull + (((offset) & 1) * 1024)) | ||
| 187 | #define CVMX_MIO_UARTX_SBCR(offset) \ | ||
| 188 | CVMX_ADD_IO_SEG(0x0001180000000A20ull + (((offset) & 1) * 1024)) | ||
| 189 | #define CVMX_MIO_UARTX_SCR(offset) \ | ||
| 190 | CVMX_ADD_IO_SEG(0x0001180000000838ull + (((offset) & 1) * 1024)) | ||
| 191 | #define CVMX_MIO_UARTX_SFE(offset) \ | ||
| 192 | CVMX_ADD_IO_SEG(0x0001180000000A30ull + (((offset) & 1) * 1024)) | ||
| 193 | #define CVMX_MIO_UARTX_SRR(offset) \ | ||
| 194 | CVMX_ADD_IO_SEG(0x0001180000000A10ull + (((offset) & 1) * 1024)) | ||
| 195 | #define CVMX_MIO_UARTX_SRT(offset) \ | ||
| 196 | CVMX_ADD_IO_SEG(0x0001180000000A38ull + (((offset) & 1) * 1024)) | ||
| 197 | #define CVMX_MIO_UARTX_SRTS(offset) \ | ||
| 198 | CVMX_ADD_IO_SEG(0x0001180000000A18ull + (((offset) & 1) * 1024)) | ||
| 199 | #define CVMX_MIO_UARTX_STT(offset) \ | ||
| 200 | CVMX_ADD_IO_SEG(0x0001180000000B00ull + (((offset) & 1) * 1024)) | ||
| 201 | #define CVMX_MIO_UARTX_TFL(offset) \ | ||
| 202 | CVMX_ADD_IO_SEG(0x0001180000000A00ull + (((offset) & 1) * 1024)) | ||
| 203 | #define CVMX_MIO_UARTX_TFR(offset) \ | ||
| 204 | CVMX_ADD_IO_SEG(0x0001180000000928ull + (((offset) & 1) * 1024)) | ||
| 205 | #define CVMX_MIO_UARTX_THR(offset) \ | ||
| 206 | CVMX_ADD_IO_SEG(0x0001180000000840ull + (((offset) & 1) * 1024)) | ||
| 207 | #define CVMX_MIO_UARTX_USR(offset) \ | ||
| 208 | CVMX_ADD_IO_SEG(0x0001180000000938ull + (((offset) & 1) * 1024)) | ||
| 209 | |||
| 210 | union cvmx_mio_boot_bist_stat { | ||
| 211 | uint64_t u64; | ||
| 212 | struct cvmx_mio_boot_bist_stat_s { | ||
| 213 | uint64_t reserved_2_63:62; | ||
| 214 | uint64_t loc:1; | ||
| 215 | uint64_t ncbi:1; | ||
| 216 | } s; | ||
| 217 | struct cvmx_mio_boot_bist_stat_cn30xx { | ||
| 218 | uint64_t reserved_4_63:60; | ||
| 219 | uint64_t ncbo_1:1; | ||
| 220 | uint64_t ncbo_0:1; | ||
| 221 | uint64_t loc:1; | ||
| 222 | uint64_t ncbi:1; | ||
| 223 | } cn30xx; | ||
| 224 | struct cvmx_mio_boot_bist_stat_cn30xx cn31xx; | ||
| 225 | struct cvmx_mio_boot_bist_stat_cn38xx { | ||
| 226 | uint64_t reserved_3_63:61; | ||
| 227 | uint64_t ncbo_0:1; | ||
| 228 | uint64_t loc:1; | ||
| 229 | uint64_t ncbi:1; | ||
| 230 | } cn38xx; | ||
| 231 | struct cvmx_mio_boot_bist_stat_cn38xx cn38xxp2; | ||
| 232 | struct cvmx_mio_boot_bist_stat_cn50xx { | ||
| 233 | uint64_t reserved_6_63:58; | ||
| 234 | uint64_t pcm_1:1; | ||
| 235 | uint64_t pcm_0:1; | ||
| 236 | uint64_t ncbo_1:1; | ||
| 237 | uint64_t ncbo_0:1; | ||
| 238 | uint64_t loc:1; | ||
| 239 | uint64_t ncbi:1; | ||
| 240 | } cn50xx; | ||
| 241 | struct cvmx_mio_boot_bist_stat_cn52xx { | ||
| 242 | uint64_t reserved_6_63:58; | ||
| 243 | uint64_t ndf:2; | ||
| 244 | uint64_t ncbo_0:1; | ||
| 245 | uint64_t dma:1; | ||
| 246 | uint64_t loc:1; | ||
| 247 | uint64_t ncbi:1; | ||
| 248 | } cn52xx; | ||
| 249 | struct cvmx_mio_boot_bist_stat_cn52xxp1 { | ||
| 250 | uint64_t reserved_4_63:60; | ||
| 251 | uint64_t ncbo_0:1; | ||
| 252 | uint64_t dma:1; | ||
| 253 | uint64_t loc:1; | ||
| 254 | uint64_t ncbi:1; | ||
| 255 | } cn52xxp1; | ||
| 256 | struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xx; | ||
| 257 | struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xxp1; | ||
| 258 | struct cvmx_mio_boot_bist_stat_cn38xx cn58xx; | ||
| 259 | struct cvmx_mio_boot_bist_stat_cn38xx cn58xxp1; | ||
| 260 | }; | ||
| 261 | |||
| 262 | union cvmx_mio_boot_comp { | ||
| 263 | uint64_t u64; | ||
| 264 | struct cvmx_mio_boot_comp_s { | ||
| 265 | uint64_t reserved_10_63:54; | ||
| 266 | uint64_t pctl:5; | ||
| 267 | uint64_t nctl:5; | ||
| 268 | } s; | ||
| 269 | struct cvmx_mio_boot_comp_s cn50xx; | ||
| 270 | struct cvmx_mio_boot_comp_s cn52xx; | ||
| 271 | struct cvmx_mio_boot_comp_s cn52xxp1; | ||
| 272 | struct cvmx_mio_boot_comp_s cn56xx; | ||
| 273 | struct cvmx_mio_boot_comp_s cn56xxp1; | ||
| 274 | }; | ||
| 275 | |||
| 276 | union cvmx_mio_boot_dma_cfgx { | ||
| 277 | uint64_t u64; | ||
| 278 | struct cvmx_mio_boot_dma_cfgx_s { | ||
| 279 | uint64_t en:1; | ||
| 280 | uint64_t rw:1; | ||
| 281 | uint64_t clr:1; | ||
| 282 | uint64_t reserved_60_60:1; | ||
| 283 | uint64_t swap32:1; | ||
| 284 | uint64_t swap16:1; | ||
| 285 | uint64_t swap8:1; | ||
| 286 | uint64_t endian:1; | ||
| 287 | uint64_t size:20; | ||
| 288 | uint64_t adr:36; | ||
| 289 | } s; | ||
| 290 | struct cvmx_mio_boot_dma_cfgx_s cn52xx; | ||
| 291 | struct cvmx_mio_boot_dma_cfgx_s cn52xxp1; | ||
| 292 | struct cvmx_mio_boot_dma_cfgx_s cn56xx; | ||
| 293 | struct cvmx_mio_boot_dma_cfgx_s cn56xxp1; | ||
| 294 | }; | ||
| 295 | |||
| 296 | union cvmx_mio_boot_dma_intx { | ||
| 297 | uint64_t u64; | ||
| 298 | struct cvmx_mio_boot_dma_intx_s { | ||
| 299 | uint64_t reserved_2_63:62; | ||
| 300 | uint64_t dmarq:1; | ||
| 301 | uint64_t done:1; | ||
| 302 | } s; | ||
| 303 | struct cvmx_mio_boot_dma_intx_s cn52xx; | ||
| 304 | struct cvmx_mio_boot_dma_intx_s cn52xxp1; | ||
| 305 | struct cvmx_mio_boot_dma_intx_s cn56xx; | ||
| 306 | struct cvmx_mio_boot_dma_intx_s cn56xxp1; | ||
| 307 | }; | ||
| 308 | |||
| 309 | union cvmx_mio_boot_dma_int_enx { | ||
| 310 | uint64_t u64; | ||
| 311 | struct cvmx_mio_boot_dma_int_enx_s { | ||
| 312 | uint64_t reserved_2_63:62; | ||
| 313 | uint64_t dmarq:1; | ||
| 314 | uint64_t done:1; | ||
| 315 | } s; | ||
| 316 | struct cvmx_mio_boot_dma_int_enx_s cn52xx; | ||
| 317 | struct cvmx_mio_boot_dma_int_enx_s cn52xxp1; | ||
| 318 | struct cvmx_mio_boot_dma_int_enx_s cn56xx; | ||
| 319 | struct cvmx_mio_boot_dma_int_enx_s cn56xxp1; | ||
| 320 | }; | ||
| 321 | |||
| 322 | union cvmx_mio_boot_dma_timx { | ||
| 323 | uint64_t u64; | ||
| 324 | struct cvmx_mio_boot_dma_timx_s { | ||
| 325 | uint64_t dmack_pi:1; | ||
| 326 | uint64_t dmarq_pi:1; | ||
| 327 | uint64_t tim_mult:2; | ||
| 328 | uint64_t rd_dly:3; | ||
| 329 | uint64_t ddr:1; | ||
| 330 | uint64_t width:1; | ||
| 331 | uint64_t reserved_48_54:7; | ||
| 332 | uint64_t pause:6; | ||
| 333 | uint64_t dmack_h:6; | ||
| 334 | uint64_t we_n:6; | ||
| 335 | uint64_t we_a:6; | ||
| 336 | uint64_t oe_n:6; | ||
| 337 | uint64_t oe_a:6; | ||
| 338 | uint64_t dmack_s:6; | ||
| 339 | uint64_t dmarq:6; | ||
| 340 | } s; | ||
| 341 | struct cvmx_mio_boot_dma_timx_s cn52xx; | ||
| 342 | struct cvmx_mio_boot_dma_timx_s cn52xxp1; | ||
| 343 | struct cvmx_mio_boot_dma_timx_s cn56xx; | ||
| 344 | struct cvmx_mio_boot_dma_timx_s cn56xxp1; | ||
| 345 | }; | ||
| 346 | |||
| 347 | union cvmx_mio_boot_err { | ||
| 348 | uint64_t u64; | ||
| 349 | struct cvmx_mio_boot_err_s { | ||
| 350 | uint64_t reserved_2_63:62; | ||
| 351 | uint64_t wait_err:1; | ||
| 352 | uint64_t adr_err:1; | ||
| 353 | } s; | ||
| 354 | struct cvmx_mio_boot_err_s cn30xx; | ||
| 355 | struct cvmx_mio_boot_err_s cn31xx; | ||
| 356 | struct cvmx_mio_boot_err_s cn38xx; | ||
| 357 | struct cvmx_mio_boot_err_s cn38xxp2; | ||
| 358 | struct cvmx_mio_boot_err_s cn50xx; | ||
| 359 | struct cvmx_mio_boot_err_s cn52xx; | ||
| 360 | struct cvmx_mio_boot_err_s cn52xxp1; | ||
| 361 | struct cvmx_mio_boot_err_s cn56xx; | ||
| 362 | struct cvmx_mio_boot_err_s cn56xxp1; | ||
| 363 | struct cvmx_mio_boot_err_s cn58xx; | ||
| 364 | struct cvmx_mio_boot_err_s cn58xxp1; | ||
| 365 | }; | ||
| 366 | |||
| 367 | union cvmx_mio_boot_int { | ||
| 368 | uint64_t u64; | ||
| 369 | struct cvmx_mio_boot_int_s { | ||
| 370 | uint64_t reserved_2_63:62; | ||
| 371 | uint64_t wait_int:1; | ||
| 372 | uint64_t adr_int:1; | ||
| 373 | } s; | ||
| 374 | struct cvmx_mio_boot_int_s cn30xx; | ||
| 375 | struct cvmx_mio_boot_int_s cn31xx; | ||
| 376 | struct cvmx_mio_boot_int_s cn38xx; | ||
| 377 | struct cvmx_mio_boot_int_s cn38xxp2; | ||
| 378 | struct cvmx_mio_boot_int_s cn50xx; | ||
| 379 | struct cvmx_mio_boot_int_s cn52xx; | ||
| 380 | struct cvmx_mio_boot_int_s cn52xxp1; | ||
| 381 | struct cvmx_mio_boot_int_s cn56xx; | ||
| 382 | struct cvmx_mio_boot_int_s cn56xxp1; | ||
| 383 | struct cvmx_mio_boot_int_s cn58xx; | ||
| 384 | struct cvmx_mio_boot_int_s cn58xxp1; | ||
| 385 | }; | ||
| 386 | |||
| 387 | union cvmx_mio_boot_loc_adr { | ||
| 388 | uint64_t u64; | ||
| 389 | struct cvmx_mio_boot_loc_adr_s { | ||
| 390 | uint64_t reserved_8_63:56; | ||
| 391 | uint64_t adr:5; | ||
| 392 | uint64_t reserved_0_2:3; | ||
| 393 | } s; | ||
| 394 | struct cvmx_mio_boot_loc_adr_s cn30xx; | ||
| 395 | struct cvmx_mio_boot_loc_adr_s cn31xx; | ||
| 396 | struct cvmx_mio_boot_loc_adr_s cn38xx; | ||
| 397 | struct cvmx_mio_boot_loc_adr_s cn38xxp2; | ||
| 398 | struct cvmx_mio_boot_loc_adr_s cn50xx; | ||
| 399 | struct cvmx_mio_boot_loc_adr_s cn52xx; | ||
| 400 | struct cvmx_mio_boot_loc_adr_s cn52xxp1; | ||
| 401 | struct cvmx_mio_boot_loc_adr_s cn56xx; | ||
| 402 | struct cvmx_mio_boot_loc_adr_s cn56xxp1; | ||
| 403 | struct cvmx_mio_boot_loc_adr_s cn58xx; | ||
| 404 | struct cvmx_mio_boot_loc_adr_s cn58xxp1; | ||
| 405 | }; | ||
| 406 | |||
| 407 | union cvmx_mio_boot_loc_cfgx { | ||
| 408 | uint64_t u64; | ||
| 409 | struct cvmx_mio_boot_loc_cfgx_s { | ||
| 410 | uint64_t reserved_32_63:32; | ||
| 411 | uint64_t en:1; | ||
| 412 | uint64_t reserved_28_30:3; | ||
| 413 | uint64_t base:25; | ||
| 414 | uint64_t reserved_0_2:3; | ||
| 415 | } s; | ||
| 416 | struct cvmx_mio_boot_loc_cfgx_s cn30xx; | ||
| 417 | struct cvmx_mio_boot_loc_cfgx_s cn31xx; | ||
| 418 | struct cvmx_mio_boot_loc_cfgx_s cn38xx; | ||
| 419 | struct cvmx_mio_boot_loc_cfgx_s cn38xxp2; | ||
| 420 | struct cvmx_mio_boot_loc_cfgx_s cn50xx; | ||
| 421 | struct cvmx_mio_boot_loc_cfgx_s cn52xx; | ||
| 422 | struct cvmx_mio_boot_loc_cfgx_s cn52xxp1; | ||
| 423 | struct cvmx_mio_boot_loc_cfgx_s cn56xx; | ||
| 424 | struct cvmx_mio_boot_loc_cfgx_s cn56xxp1; | ||
| 425 | struct cvmx_mio_boot_loc_cfgx_s cn58xx; | ||
| 426 | struct cvmx_mio_boot_loc_cfgx_s cn58xxp1; | ||
| 427 | }; | ||
| 428 | |||
| 429 | union cvmx_mio_boot_loc_dat { | ||
| 430 | uint64_t u64; | ||
| 431 | struct cvmx_mio_boot_loc_dat_s { | ||
| 432 | uint64_t data:64; | ||
| 433 | } s; | ||
| 434 | struct cvmx_mio_boot_loc_dat_s cn30xx; | ||
| 435 | struct cvmx_mio_boot_loc_dat_s cn31xx; | ||
| 436 | struct cvmx_mio_boot_loc_dat_s cn38xx; | ||
| 437 | struct cvmx_mio_boot_loc_dat_s cn38xxp2; | ||
| 438 | struct cvmx_mio_boot_loc_dat_s cn50xx; | ||
| 439 | struct cvmx_mio_boot_loc_dat_s cn52xx; | ||
| 440 | struct cvmx_mio_boot_loc_dat_s cn52xxp1; | ||
| 441 | struct cvmx_mio_boot_loc_dat_s cn56xx; | ||
| 442 | struct cvmx_mio_boot_loc_dat_s cn56xxp1; | ||
| 443 | struct cvmx_mio_boot_loc_dat_s cn58xx; | ||
| 444 | struct cvmx_mio_boot_loc_dat_s cn58xxp1; | ||
| 445 | }; | ||
| 446 | |||
| 447 | union cvmx_mio_boot_pin_defs { | ||
| 448 | uint64_t u64; | ||
| 449 | struct cvmx_mio_boot_pin_defs_s { | ||
| 450 | uint64_t reserved_16_63:48; | ||
| 451 | uint64_t ale:1; | ||
| 452 | uint64_t width:1; | ||
| 453 | uint64_t dmack_p2:1; | ||
| 454 | uint64_t dmack_p1:1; | ||
| 455 | uint64_t dmack_p0:1; | ||
| 456 | uint64_t term:2; | ||
| 457 | uint64_t nand:1; | ||
| 458 | uint64_t reserved_0_7:8; | ||
| 459 | } s; | ||
| 460 | struct cvmx_mio_boot_pin_defs_cn52xx { | ||
| 461 | uint64_t reserved_16_63:48; | ||
| 462 | uint64_t ale:1; | ||
| 463 | uint64_t width:1; | ||
| 464 | uint64_t reserved_13_13:1; | ||
| 465 | uint64_t dmack_p1:1; | ||
| 466 | uint64_t dmack_p0:1; | ||
| 467 | uint64_t term:2; | ||
| 468 | uint64_t nand:1; | ||
| 469 | uint64_t reserved_0_7:8; | ||
| 470 | } cn52xx; | ||
| 471 | struct cvmx_mio_boot_pin_defs_cn56xx { | ||
| 472 | uint64_t reserved_16_63:48; | ||
| 473 | uint64_t ale:1; | ||
| 474 | uint64_t width:1; | ||
| 475 | uint64_t dmack_p2:1; | ||
| 476 | uint64_t dmack_p1:1; | ||
| 477 | uint64_t dmack_p0:1; | ||
| 478 | uint64_t term:2; | ||
| 479 | uint64_t reserved_0_8:9; | ||
| 480 | } cn56xx; | ||
| 481 | }; | ||
| 482 | |||
| 483 | union cvmx_mio_boot_reg_cfgx { | ||
| 484 | uint64_t u64; | ||
| 485 | struct cvmx_mio_boot_reg_cfgx_s { | ||
| 486 | uint64_t reserved_44_63:20; | ||
| 487 | uint64_t dmack:2; | ||
| 488 | uint64_t tim_mult:2; | ||
| 489 | uint64_t rd_dly:3; | ||
| 490 | uint64_t sam:1; | ||
| 491 | uint64_t we_ext:2; | ||
| 492 | uint64_t oe_ext:2; | ||
| 493 | uint64_t en:1; | ||
| 494 | uint64_t orbit:1; | ||
| 495 | uint64_t ale:1; | ||
| 496 | uint64_t width:1; | ||
| 497 | uint64_t size:12; | ||
| 498 | uint64_t base:16; | ||
| 499 | } s; | ||
| 500 | struct cvmx_mio_boot_reg_cfgx_cn30xx { | ||
| 501 | uint64_t reserved_37_63:27; | ||
| 502 | uint64_t sam:1; | ||
| 503 | uint64_t we_ext:2; | ||
| 504 | uint64_t oe_ext:2; | ||
| 505 | uint64_t en:1; | ||
| 506 | uint64_t orbit:1; | ||
| 507 | uint64_t ale:1; | ||
| 508 | uint64_t width:1; | ||
| 509 | uint64_t size:12; | ||
| 510 | uint64_t base:16; | ||
| 511 | } cn30xx; | ||
| 512 | struct cvmx_mio_boot_reg_cfgx_cn30xx cn31xx; | ||
| 513 | struct cvmx_mio_boot_reg_cfgx_cn38xx { | ||
| 514 | uint64_t reserved_32_63:32; | ||
| 515 | uint64_t en:1; | ||
| 516 | uint64_t orbit:1; | ||
| 517 | uint64_t reserved_28_29:2; | ||
| 518 | uint64_t size:12; | ||
| 519 | uint64_t base:16; | ||
| 520 | } cn38xx; | ||
| 521 | struct cvmx_mio_boot_reg_cfgx_cn38xx cn38xxp2; | ||
| 522 | struct cvmx_mio_boot_reg_cfgx_cn50xx { | ||
| 523 | uint64_t reserved_42_63:22; | ||
| 524 | uint64_t tim_mult:2; | ||
| 525 | uint64_t rd_dly:3; | ||
| 526 | uint64_t sam:1; | ||
| 527 | uint64_t we_ext:2; | ||
| 528 | uint64_t oe_ext:2; | ||
| 529 | uint64_t en:1; | ||
| 530 | uint64_t orbit:1; | ||
| 531 | uint64_t ale:1; | ||
| 532 | uint64_t width:1; | ||
| 533 | uint64_t size:12; | ||
| 534 | uint64_t base:16; | ||
| 535 | } cn50xx; | ||
| 536 | struct cvmx_mio_boot_reg_cfgx_s cn52xx; | ||
| 537 | struct cvmx_mio_boot_reg_cfgx_s cn52xxp1; | ||
| 538 | struct cvmx_mio_boot_reg_cfgx_s cn56xx; | ||
| 539 | struct cvmx_mio_boot_reg_cfgx_s cn56xxp1; | ||
| 540 | struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xx; | ||
| 541 | struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xxp1; | ||
| 542 | }; | ||
| 543 | |||
| 544 | union cvmx_mio_boot_reg_timx { | ||
| 545 | uint64_t u64; | ||
| 546 | struct cvmx_mio_boot_reg_timx_s { | ||
| 547 | uint64_t pagem:1; | ||
| 548 | uint64_t waitm:1; | ||
| 549 | uint64_t pages:2; | ||
| 550 | uint64_t ale:6; | ||
| 551 | uint64_t page:6; | ||
| 552 | uint64_t wait:6; | ||
| 553 | uint64_t pause:6; | ||
| 554 | uint64_t wr_hld:6; | ||
| 555 | uint64_t rd_hld:6; | ||
| 556 | uint64_t we:6; | ||
| 557 | uint64_t oe:6; | ||
| 558 | uint64_t ce:6; | ||
| 559 | uint64_t adr:6; | ||
| 560 | } s; | ||
| 561 | struct cvmx_mio_boot_reg_timx_s cn30xx; | ||
| 562 | struct cvmx_mio_boot_reg_timx_s cn31xx; | ||
| 563 | struct cvmx_mio_boot_reg_timx_cn38xx { | ||
| 564 | uint64_t pagem:1; | ||
| 565 | uint64_t waitm:1; | ||
| 566 | uint64_t pages:2; | ||
| 567 | uint64_t reserved_54_59:6; | ||
| 568 | uint64_t page:6; | ||
| 569 | uint64_t wait:6; | ||
| 570 | uint64_t pause:6; | ||
| 571 | uint64_t wr_hld:6; | ||
| 572 | uint64_t rd_hld:6; | ||
| 573 | uint64_t we:6; | ||
| 574 | uint64_t oe:6; | ||
| 575 | uint64_t ce:6; | ||
| 576 | uint64_t adr:6; | ||
| 577 | } cn38xx; | ||
| 578 | struct cvmx_mio_boot_reg_timx_cn38xx cn38xxp2; | ||
| 579 | struct cvmx_mio_boot_reg_timx_s cn50xx; | ||
| 580 | struct cvmx_mio_boot_reg_timx_s cn52xx; | ||
| 581 | struct cvmx_mio_boot_reg_timx_s cn52xxp1; | ||
| 582 | struct cvmx_mio_boot_reg_timx_s cn56xx; | ||
| 583 | struct cvmx_mio_boot_reg_timx_s cn56xxp1; | ||
| 584 | struct cvmx_mio_boot_reg_timx_s cn58xx; | ||
| 585 | struct cvmx_mio_boot_reg_timx_s cn58xxp1; | ||
| 586 | }; | ||
| 587 | |||
| 588 | union cvmx_mio_boot_thr { | ||
| 589 | uint64_t u64; | ||
| 590 | struct cvmx_mio_boot_thr_s { | ||
| 591 | uint64_t reserved_22_63:42; | ||
| 592 | uint64_t dma_thr:6; | ||
| 593 | uint64_t reserved_14_15:2; | ||
| 594 | uint64_t fif_cnt:6; | ||
| 595 | uint64_t reserved_6_7:2; | ||
| 596 | uint64_t fif_thr:6; | ||
| 597 | } s; | ||
| 598 | struct cvmx_mio_boot_thr_cn30xx { | ||
| 599 | uint64_t reserved_14_63:50; | ||
| 600 | uint64_t fif_cnt:6; | ||
| 601 | uint64_t reserved_6_7:2; | ||
| 602 | uint64_t fif_thr:6; | ||
| 603 | } cn30xx; | ||
| 604 | struct cvmx_mio_boot_thr_cn30xx cn31xx; | ||
| 605 | struct cvmx_mio_boot_thr_cn30xx cn38xx; | ||
| 606 | struct cvmx_mio_boot_thr_cn30xx cn38xxp2; | ||
| 607 | struct cvmx_mio_boot_thr_cn30xx cn50xx; | ||
| 608 | struct cvmx_mio_boot_thr_s cn52xx; | ||
| 609 | struct cvmx_mio_boot_thr_s cn52xxp1; | ||
| 610 | struct cvmx_mio_boot_thr_s cn56xx; | ||
| 611 | struct cvmx_mio_boot_thr_s cn56xxp1; | ||
| 612 | struct cvmx_mio_boot_thr_cn30xx cn58xx; | ||
| 613 | struct cvmx_mio_boot_thr_cn30xx cn58xxp1; | ||
| 614 | }; | ||
| 615 | |||
| 616 | union cvmx_mio_fus_bnk_datx { | ||
| 617 | uint64_t u64; | ||
| 618 | struct cvmx_mio_fus_bnk_datx_s { | ||
| 619 | uint64_t dat:64; | ||
| 620 | } s; | ||
| 621 | struct cvmx_mio_fus_bnk_datx_s cn50xx; | ||
| 622 | struct cvmx_mio_fus_bnk_datx_s cn52xx; | ||
| 623 | struct cvmx_mio_fus_bnk_datx_s cn52xxp1; | ||
| 624 | struct cvmx_mio_fus_bnk_datx_s cn56xx; | ||
| 625 | struct cvmx_mio_fus_bnk_datx_s cn56xxp1; | ||
| 626 | struct cvmx_mio_fus_bnk_datx_s cn58xx; | ||
| 627 | struct cvmx_mio_fus_bnk_datx_s cn58xxp1; | ||
| 628 | }; | ||
| 629 | |||
| 630 | union cvmx_mio_fus_dat0 { | ||
| 631 | uint64_t u64; | ||
| 632 | struct cvmx_mio_fus_dat0_s { | ||
| 633 | uint64_t reserved_32_63:32; | ||
| 634 | uint64_t man_info:32; | ||
| 635 | } s; | ||
| 636 | struct cvmx_mio_fus_dat0_s cn30xx; | ||
| 637 | struct cvmx_mio_fus_dat0_s cn31xx; | ||
| 638 | struct cvmx_mio_fus_dat0_s cn38xx; | ||
| 639 | struct cvmx_mio_fus_dat0_s cn38xxp2; | ||
| 640 | struct cvmx_mio_fus_dat0_s cn50xx; | ||
| 641 | struct cvmx_mio_fus_dat0_s cn52xx; | ||
| 642 | struct cvmx_mio_fus_dat0_s cn52xxp1; | ||
| 643 | struct cvmx_mio_fus_dat0_s cn56xx; | ||
| 644 | struct cvmx_mio_fus_dat0_s cn56xxp1; | ||
| 645 | struct cvmx_mio_fus_dat0_s cn58xx; | ||
| 646 | struct cvmx_mio_fus_dat0_s cn58xxp1; | ||
| 647 | }; | ||
| 648 | |||
| 649 | union cvmx_mio_fus_dat1 { | ||
| 650 | uint64_t u64; | ||
| 651 | struct cvmx_mio_fus_dat1_s { | ||
| 652 | uint64_t reserved_32_63:32; | ||
| 653 | uint64_t man_info:32; | ||
| 654 | } s; | ||
| 655 | struct cvmx_mio_fus_dat1_s cn30xx; | ||
| 656 | struct cvmx_mio_fus_dat1_s cn31xx; | ||
| 657 | struct cvmx_mio_fus_dat1_s cn38xx; | ||
| 658 | struct cvmx_mio_fus_dat1_s cn38xxp2; | ||
| 659 | struct cvmx_mio_fus_dat1_s cn50xx; | ||
| 660 | struct cvmx_mio_fus_dat1_s cn52xx; | ||
| 661 | struct cvmx_mio_fus_dat1_s cn52xxp1; | ||
| 662 | struct cvmx_mio_fus_dat1_s cn56xx; | ||
| 663 | struct cvmx_mio_fus_dat1_s cn56xxp1; | ||
| 664 | struct cvmx_mio_fus_dat1_s cn58xx; | ||
| 665 | struct cvmx_mio_fus_dat1_s cn58xxp1; | ||
| 666 | }; | ||
| 667 | |||
| 668 | union cvmx_mio_fus_dat2 { | ||
| 669 | uint64_t u64; | ||
| 670 | struct cvmx_mio_fus_dat2_s { | ||
| 671 | uint64_t reserved_34_63:30; | ||
| 672 | uint64_t fus318:1; | ||
| 673 | uint64_t raid_en:1; | ||
| 674 | uint64_t reserved_30_31:2; | ||
| 675 | uint64_t nokasu:1; | ||
| 676 | uint64_t nodfa_cp2:1; | ||
| 677 | uint64_t nomul:1; | ||
| 678 | uint64_t nocrypto:1; | ||
| 679 | uint64_t rst_sht:1; | ||
| 680 | uint64_t bist_dis:1; | ||
| 681 | uint64_t chip_id:8; | ||
| 682 | uint64_t reserved_0_15:16; | ||
| 683 | } s; | ||
| 684 | struct cvmx_mio_fus_dat2_cn30xx { | ||
| 685 | uint64_t reserved_29_63:35; | ||
| 686 | uint64_t nodfa_cp2:1; | ||
| 687 | uint64_t nomul:1; | ||
| 688 | uint64_t nocrypto:1; | ||
| 689 | uint64_t rst_sht:1; | ||
| 690 | uint64_t bist_dis:1; | ||
| 691 | uint64_t chip_id:8; | ||
| 692 | uint64_t pll_off:4; | ||
| 693 | uint64_t reserved_1_11:11; | ||
| 694 | uint64_t pp_dis:1; | ||
| 695 | } cn30xx; | ||
| 696 | struct cvmx_mio_fus_dat2_cn31xx { | ||
| 697 | uint64_t reserved_29_63:35; | ||
| 698 | uint64_t nodfa_cp2:1; | ||
| 699 | uint64_t nomul:1; | ||
| 700 | uint64_t nocrypto:1; | ||
| 701 | uint64_t rst_sht:1; | ||
| 702 | uint64_t bist_dis:1; | ||
| 703 | uint64_t chip_id:8; | ||
| 704 | uint64_t pll_off:4; | ||
| 705 | uint64_t reserved_2_11:10; | ||
| 706 | uint64_t pp_dis:2; | ||
| 707 | } cn31xx; | ||
| 708 | struct cvmx_mio_fus_dat2_cn38xx { | ||
| 709 | uint64_t reserved_29_63:35; | ||
| 710 | uint64_t nodfa_cp2:1; | ||
| 711 | uint64_t nomul:1; | ||
| 712 | uint64_t nocrypto:1; | ||
| 713 | uint64_t rst_sht:1; | ||
| 714 | uint64_t bist_dis:1; | ||
| 715 | uint64_t chip_id:8; | ||
| 716 | uint64_t pp_dis:16; | ||
| 717 | } cn38xx; | ||
| 718 | struct cvmx_mio_fus_dat2_cn38xx cn38xxp2; | ||
| 719 | struct cvmx_mio_fus_dat2_cn50xx { | ||
| 720 | uint64_t reserved_34_63:30; | ||
| 721 | uint64_t fus318:1; | ||
| 722 | uint64_t raid_en:1; | ||
| 723 | uint64_t reserved_30_31:2; | ||
| 724 | uint64_t nokasu:1; | ||
| 725 | uint64_t nodfa_cp2:1; | ||
| 726 | uint64_t nomul:1; | ||
| 727 | uint64_t nocrypto:1; | ||
| 728 | uint64_t rst_sht:1; | ||
| 729 | uint64_t bist_dis:1; | ||
| 730 | uint64_t chip_id:8; | ||
| 731 | uint64_t reserved_2_15:14; | ||
| 732 | uint64_t pp_dis:2; | ||
| 733 | } cn50xx; | ||
| 734 | struct cvmx_mio_fus_dat2_cn52xx { | ||
| 735 | uint64_t reserved_34_63:30; | ||
| 736 | uint64_t fus318:1; | ||
| 737 | uint64_t raid_en:1; | ||
| 738 | uint64_t reserved_30_31:2; | ||
| 739 | uint64_t nokasu:1; | ||
| 740 | uint64_t nodfa_cp2:1; | ||
| 741 | uint64_t nomul:1; | ||
| 742 | uint64_t nocrypto:1; | ||
| 743 | uint64_t rst_sht:1; | ||
| 744 | uint64_t bist_dis:1; | ||
| 745 | uint64_t chip_id:8; | ||
| 746 | uint64_t reserved_4_15:12; | ||
| 747 | uint64_t pp_dis:4; | ||
| 748 | } cn52xx; | ||
| 749 | struct cvmx_mio_fus_dat2_cn52xx cn52xxp1; | ||
| 750 | struct cvmx_mio_fus_dat2_cn56xx { | ||
| 751 | uint64_t reserved_34_63:30; | ||
| 752 | uint64_t fus318:1; | ||
| 753 | uint64_t raid_en:1; | ||
| 754 | uint64_t reserved_30_31:2; | ||
| 755 | uint64_t nokasu:1; | ||
| 756 | uint64_t nodfa_cp2:1; | ||
| 757 | uint64_t nomul:1; | ||
| 758 | uint64_t nocrypto:1; | ||
| 759 | uint64_t rst_sht:1; | ||
| 760 | uint64_t bist_dis:1; | ||
| 761 | uint64_t chip_id:8; | ||
| 762 | uint64_t reserved_12_15:4; | ||
| 763 | uint64_t pp_dis:12; | ||
| 764 | } cn56xx; | ||
| 765 | struct cvmx_mio_fus_dat2_cn56xx cn56xxp1; | ||
| 766 | struct cvmx_mio_fus_dat2_cn58xx { | ||
| 767 | uint64_t reserved_30_63:34; | ||
| 768 | uint64_t nokasu:1; | ||
| 769 | uint64_t nodfa_cp2:1; | ||
| 770 | uint64_t nomul:1; | ||
| 771 | uint64_t nocrypto:1; | ||
| 772 | uint64_t rst_sht:1; | ||
| 773 | uint64_t bist_dis:1; | ||
| 774 | uint64_t chip_id:8; | ||
| 775 | uint64_t pp_dis:16; | ||
| 776 | } cn58xx; | ||
| 777 | struct cvmx_mio_fus_dat2_cn58xx cn58xxp1; | ||
| 778 | }; | ||
| 779 | |||
| 780 | union cvmx_mio_fus_dat3 { | ||
| 781 | uint64_t u64; | ||
| 782 | struct cvmx_mio_fus_dat3_s { | ||
| 783 | uint64_t reserved_32_63:32; | ||
| 784 | uint64_t pll_div4:1; | ||
| 785 | uint64_t zip_crip:2; | ||
| 786 | uint64_t bar2_en:1; | ||
| 787 | uint64_t efus_lck:1; | ||
| 788 | uint64_t efus_ign:1; | ||
| 789 | uint64_t nozip:1; | ||
| 790 | uint64_t nodfa_dte:1; | ||
| 791 | uint64_t icache:24; | ||
| 792 | } s; | ||
| 793 | struct cvmx_mio_fus_dat3_cn30xx { | ||
| 794 | uint64_t reserved_32_63:32; | ||
| 795 | uint64_t pll_div4:1; | ||
| 796 | uint64_t reserved_29_30:2; | ||
| 797 | uint64_t bar2_en:1; | ||
| 798 | uint64_t efus_lck:1; | ||
| 799 | uint64_t efus_ign:1; | ||
| 800 | uint64_t nozip:1; | ||
| 801 | uint64_t nodfa_dte:1; | ||
| 802 | uint64_t icache:24; | ||
| 803 | } cn30xx; | ||
| 804 | struct cvmx_mio_fus_dat3_s cn31xx; | ||
| 805 | struct cvmx_mio_fus_dat3_cn38xx { | ||
| 806 | uint64_t reserved_31_63:33; | ||
| 807 | uint64_t zip_crip:2; | ||
| 808 | uint64_t bar2_en:1; | ||
| 809 | uint64_t efus_lck:1; | ||
| 810 | uint64_t efus_ign:1; | ||
| 811 | uint64_t nozip:1; | ||
| 812 | uint64_t nodfa_dte:1; | ||
| 813 | uint64_t icache:24; | ||
| 814 | } cn38xx; | ||
| 815 | struct cvmx_mio_fus_dat3_cn38xxp2 { | ||
| 816 | uint64_t reserved_29_63:35; | ||
| 817 | uint64_t bar2_en:1; | ||
| 818 | uint64_t efus_lck:1; | ||
| 819 | uint64_t efus_ign:1; | ||
| 820 | uint64_t nozip:1; | ||
| 821 | uint64_t nodfa_dte:1; | ||
| 822 | uint64_t icache:24; | ||
| 823 | } cn38xxp2; | ||
| 824 | struct cvmx_mio_fus_dat3_cn38xx cn50xx; | ||
| 825 | struct cvmx_mio_fus_dat3_cn38xx cn52xx; | ||
| 826 | struct cvmx_mio_fus_dat3_cn38xx cn52xxp1; | ||
| 827 | struct cvmx_mio_fus_dat3_cn38xx cn56xx; | ||
| 828 | struct cvmx_mio_fus_dat3_cn38xx cn56xxp1; | ||
| 829 | struct cvmx_mio_fus_dat3_cn38xx cn58xx; | ||
| 830 | struct cvmx_mio_fus_dat3_cn38xx cn58xxp1; | ||
| 831 | }; | ||
| 832 | |||
| 833 | union cvmx_mio_fus_ema { | ||
| 834 | uint64_t u64; | ||
| 835 | struct cvmx_mio_fus_ema_s { | ||
| 836 | uint64_t reserved_7_63:57; | ||
| 837 | uint64_t eff_ema:3; | ||
| 838 | uint64_t reserved_3_3:1; | ||
| 839 | uint64_t ema:3; | ||
| 840 | } s; | ||
| 841 | struct cvmx_mio_fus_ema_s cn50xx; | ||
| 842 | struct cvmx_mio_fus_ema_s cn52xx; | ||
| 843 | struct cvmx_mio_fus_ema_s cn52xxp1; | ||
| 844 | struct cvmx_mio_fus_ema_s cn56xx; | ||
| 845 | struct cvmx_mio_fus_ema_s cn56xxp1; | ||
| 846 | struct cvmx_mio_fus_ema_cn58xx { | ||
| 847 | uint64_t reserved_2_63:62; | ||
| 848 | uint64_t ema:2; | ||
| 849 | } cn58xx; | ||
| 850 | struct cvmx_mio_fus_ema_cn58xx cn58xxp1; | ||
| 851 | }; | ||
| 852 | |||
| 853 | union cvmx_mio_fus_pdf { | ||
| 854 | uint64_t u64; | ||
| 855 | struct cvmx_mio_fus_pdf_s { | ||
| 856 | uint64_t pdf:64; | ||
| 857 | } s; | ||
| 858 | struct cvmx_mio_fus_pdf_s cn50xx; | ||
| 859 | struct cvmx_mio_fus_pdf_s cn52xx; | ||
| 860 | struct cvmx_mio_fus_pdf_s cn52xxp1; | ||
| 861 | struct cvmx_mio_fus_pdf_s cn56xx; | ||
| 862 | struct cvmx_mio_fus_pdf_s cn56xxp1; | ||
| 863 | struct cvmx_mio_fus_pdf_s cn58xx; | ||
| 864 | }; | ||
| 865 | |||
| 866 | union cvmx_mio_fus_pll { | ||
| 867 | uint64_t u64; | ||
| 868 | struct cvmx_mio_fus_pll_s { | ||
| 869 | uint64_t reserved_2_63:62; | ||
| 870 | uint64_t rfslip:1; | ||
| 871 | uint64_t fbslip:1; | ||
| 872 | } s; | ||
| 873 | struct cvmx_mio_fus_pll_s cn50xx; | ||
| 874 | struct cvmx_mio_fus_pll_s cn52xx; | ||
| 875 | struct cvmx_mio_fus_pll_s cn52xxp1; | ||
| 876 | struct cvmx_mio_fus_pll_s cn56xx; | ||
| 877 | struct cvmx_mio_fus_pll_s cn56xxp1; | ||
| 878 | struct cvmx_mio_fus_pll_s cn58xx; | ||
| 879 | struct cvmx_mio_fus_pll_s cn58xxp1; | ||
| 880 | }; | ||
| 881 | |||
| 882 | union cvmx_mio_fus_prog { | ||
| 883 | uint64_t u64; | ||
| 884 | struct cvmx_mio_fus_prog_s { | ||
| 885 | uint64_t reserved_1_63:63; | ||
| 886 | uint64_t prog:1; | ||
| 887 | } s; | ||
| 888 | struct cvmx_mio_fus_prog_s cn30xx; | ||
| 889 | struct cvmx_mio_fus_prog_s cn31xx; | ||
| 890 | struct cvmx_mio_fus_prog_s cn38xx; | ||
| 891 | struct cvmx_mio_fus_prog_s cn38xxp2; | ||
| 892 | struct cvmx_mio_fus_prog_s cn50xx; | ||
| 893 | struct cvmx_mio_fus_prog_s cn52xx; | ||
| 894 | struct cvmx_mio_fus_prog_s cn52xxp1; | ||
| 895 | struct cvmx_mio_fus_prog_s cn56xx; | ||
| 896 | struct cvmx_mio_fus_prog_s cn56xxp1; | ||
| 897 | struct cvmx_mio_fus_prog_s cn58xx; | ||
| 898 | struct cvmx_mio_fus_prog_s cn58xxp1; | ||
| 899 | }; | ||
| 900 | |||
| 901 | union cvmx_mio_fus_prog_times { | ||
| 902 | uint64_t u64; | ||
| 903 | struct cvmx_mio_fus_prog_times_s { | ||
| 904 | uint64_t reserved_33_63:31; | ||
| 905 | uint64_t prog_pin:1; | ||
| 906 | uint64_t out:8; | ||
| 907 | uint64_t sclk_lo:4; | ||
| 908 | uint64_t sclk_hi:12; | ||
| 909 | uint64_t setup:8; | ||
| 910 | } s; | ||
| 911 | struct cvmx_mio_fus_prog_times_s cn50xx; | ||
| 912 | struct cvmx_mio_fus_prog_times_s cn52xx; | ||
| 913 | struct cvmx_mio_fus_prog_times_s cn52xxp1; | ||
| 914 | struct cvmx_mio_fus_prog_times_s cn56xx; | ||
| 915 | struct cvmx_mio_fus_prog_times_s cn56xxp1; | ||
| 916 | struct cvmx_mio_fus_prog_times_s cn58xx; | ||
| 917 | struct cvmx_mio_fus_prog_times_s cn58xxp1; | ||
| 918 | }; | ||
| 919 | |||
| 920 | union cvmx_mio_fus_rcmd { | ||
| 921 | uint64_t u64; | ||
| 922 | struct cvmx_mio_fus_rcmd_s { | ||
| 923 | uint64_t reserved_24_63:40; | ||
| 924 | uint64_t dat:8; | ||
| 925 | uint64_t reserved_13_15:3; | ||
| 926 | uint64_t pend:1; | ||
| 927 | uint64_t reserved_9_11:3; | ||
| 928 | uint64_t efuse:1; | ||
| 929 | uint64_t addr:8; | ||
| 930 | } s; | ||
| 931 | struct cvmx_mio_fus_rcmd_cn30xx { | ||
| 932 | uint64_t reserved_24_63:40; | ||
| 933 | uint64_t dat:8; | ||
| 934 | uint64_t reserved_13_15:3; | ||
| 935 | uint64_t pend:1; | ||
| 936 | uint64_t reserved_9_11:3; | ||
| 937 | uint64_t efuse:1; | ||
| 938 | uint64_t reserved_7_7:1; | ||
| 939 | uint64_t addr:7; | ||
| 940 | } cn30xx; | ||
| 941 | struct cvmx_mio_fus_rcmd_cn30xx cn31xx; | ||
| 942 | struct cvmx_mio_fus_rcmd_cn30xx cn38xx; | ||
| 943 | struct cvmx_mio_fus_rcmd_cn30xx cn38xxp2; | ||
| 944 | struct cvmx_mio_fus_rcmd_cn30xx cn50xx; | ||
| 945 | struct cvmx_mio_fus_rcmd_s cn52xx; | ||
| 946 | struct cvmx_mio_fus_rcmd_s cn52xxp1; | ||
| 947 | struct cvmx_mio_fus_rcmd_s cn56xx; | ||
| 948 | struct cvmx_mio_fus_rcmd_s cn56xxp1; | ||
| 949 | struct cvmx_mio_fus_rcmd_cn30xx cn58xx; | ||
| 950 | struct cvmx_mio_fus_rcmd_cn30xx cn58xxp1; | ||
| 951 | }; | ||
| 952 | |||
| 953 | union cvmx_mio_fus_spr_repair_res { | ||
| 954 | uint64_t u64; | ||
| 955 | struct cvmx_mio_fus_spr_repair_res_s { | ||
| 956 | uint64_t reserved_42_63:22; | ||
| 957 | uint64_t repair2:14; | ||
| 958 | uint64_t repair1:14; | ||
| 959 | uint64_t repair0:14; | ||
| 960 | } s; | ||
| 961 | struct cvmx_mio_fus_spr_repair_res_s cn30xx; | ||
| 962 | struct cvmx_mio_fus_spr_repair_res_s cn31xx; | ||
| 963 | struct cvmx_mio_fus_spr_repair_res_s cn38xx; | ||
| 964 | struct cvmx_mio_fus_spr_repair_res_s cn50xx; | ||
| 965 | struct cvmx_mio_fus_spr_repair_res_s cn52xx; | ||
| 966 | struct cvmx_mio_fus_spr_repair_res_s cn52xxp1; | ||
| 967 | struct cvmx_mio_fus_spr_repair_res_s cn56xx; | ||
| 968 | struct cvmx_mio_fus_spr_repair_res_s cn56xxp1; | ||
| 969 | struct cvmx_mio_fus_spr_repair_res_s cn58xx; | ||
| 970 | struct cvmx_mio_fus_spr_repair_res_s cn58xxp1; | ||
| 971 | }; | ||
| 972 | |||
| 973 | union cvmx_mio_fus_spr_repair_sum { | ||
| 974 | uint64_t u64; | ||
| 975 | struct cvmx_mio_fus_spr_repair_sum_s { | ||
| 976 | uint64_t reserved_1_63:63; | ||
| 977 | uint64_t too_many:1; | ||
| 978 | } s; | ||
| 979 | struct cvmx_mio_fus_spr_repair_sum_s cn30xx; | ||
| 980 | struct cvmx_mio_fus_spr_repair_sum_s cn31xx; | ||
| 981 | struct cvmx_mio_fus_spr_repair_sum_s cn38xx; | ||
| 982 | struct cvmx_mio_fus_spr_repair_sum_s cn50xx; | ||
| 983 | struct cvmx_mio_fus_spr_repair_sum_s cn52xx; | ||
| 984 | struct cvmx_mio_fus_spr_repair_sum_s cn52xxp1; | ||
| 985 | struct cvmx_mio_fus_spr_repair_sum_s cn56xx; | ||
| 986 | struct cvmx_mio_fus_spr_repair_sum_s cn56xxp1; | ||
| 987 | struct cvmx_mio_fus_spr_repair_sum_s cn58xx; | ||
| 988 | struct cvmx_mio_fus_spr_repair_sum_s cn58xxp1; | ||
| 989 | }; | ||
| 990 | |||
| 991 | union cvmx_mio_fus_unlock { | ||
| 992 | uint64_t u64; | ||
| 993 | struct cvmx_mio_fus_unlock_s { | ||
| 994 | uint64_t reserved_24_63:40; | ||
| 995 | uint64_t key:24; | ||
| 996 | } s; | ||
| 997 | struct cvmx_mio_fus_unlock_s cn30xx; | ||
| 998 | struct cvmx_mio_fus_unlock_s cn31xx; | ||
| 999 | }; | ||
| 1000 | |||
| 1001 | union cvmx_mio_fus_wadr { | ||
| 1002 | uint64_t u64; | ||
| 1003 | struct cvmx_mio_fus_wadr_s { | ||
| 1004 | uint64_t reserved_10_63:54; | ||
| 1005 | uint64_t addr:10; | ||
| 1006 | } s; | ||
| 1007 | struct cvmx_mio_fus_wadr_s cn30xx; | ||
| 1008 | struct cvmx_mio_fus_wadr_s cn31xx; | ||
| 1009 | struct cvmx_mio_fus_wadr_s cn38xx; | ||
| 1010 | struct cvmx_mio_fus_wadr_s cn38xxp2; | ||
| 1011 | struct cvmx_mio_fus_wadr_cn50xx { | ||
| 1012 | uint64_t reserved_2_63:62; | ||
| 1013 | uint64_t addr:2; | ||
| 1014 | } cn50xx; | ||
| 1015 | struct cvmx_mio_fus_wadr_cn52xx { | ||
| 1016 | uint64_t reserved_3_63:61; | ||
| 1017 | uint64_t addr:3; | ||
| 1018 | } cn52xx; | ||
| 1019 | struct cvmx_mio_fus_wadr_cn52xx cn52xxp1; | ||
| 1020 | struct cvmx_mio_fus_wadr_cn52xx cn56xx; | ||
| 1021 | struct cvmx_mio_fus_wadr_cn52xx cn56xxp1; | ||
| 1022 | struct cvmx_mio_fus_wadr_cn50xx cn58xx; | ||
| 1023 | struct cvmx_mio_fus_wadr_cn50xx cn58xxp1; | ||
| 1024 | }; | ||
| 1025 | |||
| 1026 | union cvmx_mio_ndf_dma_cfg { | ||
| 1027 | uint64_t u64; | ||
| 1028 | struct cvmx_mio_ndf_dma_cfg_s { | ||
| 1029 | uint64_t en:1; | ||
| 1030 | uint64_t rw:1; | ||
| 1031 | uint64_t clr:1; | ||
| 1032 | uint64_t reserved_60_60:1; | ||
| 1033 | uint64_t swap32:1; | ||
| 1034 | uint64_t swap16:1; | ||
| 1035 | uint64_t swap8:1; | ||
| 1036 | uint64_t endian:1; | ||
| 1037 | uint64_t size:20; | ||
| 1038 | uint64_t adr:36; | ||
| 1039 | } s; | ||
| 1040 | struct cvmx_mio_ndf_dma_cfg_s cn52xx; | ||
| 1041 | }; | ||
| 1042 | |||
| 1043 | union cvmx_mio_ndf_dma_int { | ||
| 1044 | uint64_t u64; | ||
| 1045 | struct cvmx_mio_ndf_dma_int_s { | ||
| 1046 | uint64_t reserved_1_63:63; | ||
| 1047 | uint64_t done:1; | ||
| 1048 | } s; | ||
| 1049 | struct cvmx_mio_ndf_dma_int_s cn52xx; | ||
| 1050 | }; | ||
| 1051 | |||
| 1052 | union cvmx_mio_ndf_dma_int_en { | ||
| 1053 | uint64_t u64; | ||
| 1054 | struct cvmx_mio_ndf_dma_int_en_s { | ||
| 1055 | uint64_t reserved_1_63:63; | ||
| 1056 | uint64_t done:1; | ||
| 1057 | } s; | ||
| 1058 | struct cvmx_mio_ndf_dma_int_en_s cn52xx; | ||
| 1059 | }; | ||
| 1060 | |||
| 1061 | union cvmx_mio_pll_ctl { | ||
| 1062 | uint64_t u64; | ||
| 1063 | struct cvmx_mio_pll_ctl_s { | ||
| 1064 | uint64_t reserved_5_63:59; | ||
| 1065 | uint64_t bw_ctl:5; | ||
| 1066 | } s; | ||
| 1067 | struct cvmx_mio_pll_ctl_s cn30xx; | ||
| 1068 | struct cvmx_mio_pll_ctl_s cn31xx; | ||
| 1069 | }; | ||
| 1070 | |||
| 1071 | union cvmx_mio_pll_setting { | ||
| 1072 | uint64_t u64; | ||
| 1073 | struct cvmx_mio_pll_setting_s { | ||
| 1074 | uint64_t reserved_17_63:47; | ||
| 1075 | uint64_t setting:17; | ||
| 1076 | } s; | ||
| 1077 | struct cvmx_mio_pll_setting_s cn30xx; | ||
| 1078 | struct cvmx_mio_pll_setting_s cn31xx; | ||
| 1079 | }; | ||
| 1080 | |||
| 1081 | union cvmx_mio_twsx_int { | ||
| 1082 | uint64_t u64; | ||
| 1083 | struct cvmx_mio_twsx_int_s { | ||
| 1084 | uint64_t reserved_12_63:52; | ||
| 1085 | uint64_t scl:1; | ||
| 1086 | uint64_t sda:1; | ||
| 1087 | uint64_t scl_ovr:1; | ||
| 1088 | uint64_t sda_ovr:1; | ||
| 1089 | uint64_t reserved_7_7:1; | ||
| 1090 | uint64_t core_en:1; | ||
| 1091 | uint64_t ts_en:1; | ||
| 1092 | uint64_t st_en:1; | ||
| 1093 | uint64_t reserved_3_3:1; | ||
| 1094 | uint64_t core_int:1; | ||
| 1095 | uint64_t ts_int:1; | ||
| 1096 | uint64_t st_int:1; | ||
| 1097 | } s; | ||
| 1098 | struct cvmx_mio_twsx_int_s cn30xx; | ||
| 1099 | struct cvmx_mio_twsx_int_s cn31xx; | ||
| 1100 | struct cvmx_mio_twsx_int_s cn38xx; | ||
| 1101 | struct cvmx_mio_twsx_int_cn38xxp2 { | ||
| 1102 | uint64_t reserved_7_63:57; | ||
| 1103 | uint64_t core_en:1; | ||
| 1104 | uint64_t ts_en:1; | ||
| 1105 | uint64_t st_en:1; | ||
| 1106 | uint64_t reserved_3_3:1; | ||
| 1107 | uint64_t core_int:1; | ||
| 1108 | uint64_t ts_int:1; | ||
| 1109 | uint64_t st_int:1; | ||
| 1110 | } cn38xxp2; | ||
| 1111 | struct cvmx_mio_twsx_int_s cn50xx; | ||
| 1112 | struct cvmx_mio_twsx_int_s cn52xx; | ||
| 1113 | struct cvmx_mio_twsx_int_s cn52xxp1; | ||
| 1114 | struct cvmx_mio_twsx_int_s cn56xx; | ||
| 1115 | struct cvmx_mio_twsx_int_s cn56xxp1; | ||
| 1116 | struct cvmx_mio_twsx_int_s cn58xx; | ||
| 1117 | struct cvmx_mio_twsx_int_s cn58xxp1; | ||
| 1118 | }; | ||
| 1119 | |||
| 1120 | union cvmx_mio_twsx_sw_twsi { | ||
| 1121 | uint64_t u64; | ||
| 1122 | struct cvmx_mio_twsx_sw_twsi_s { | ||
| 1123 | uint64_t v:1; | ||
| 1124 | uint64_t slonly:1; | ||
| 1125 | uint64_t eia:1; | ||
| 1126 | uint64_t op:4; | ||
| 1127 | uint64_t r:1; | ||
| 1128 | uint64_t sovr:1; | ||
| 1129 | uint64_t size:3; | ||
| 1130 | uint64_t scr:2; | ||
| 1131 | uint64_t a:10; | ||
| 1132 | uint64_t ia:5; | ||
| 1133 | uint64_t eop_ia:3; | ||
| 1134 | uint64_t d:32; | ||
| 1135 | } s; | ||
| 1136 | struct cvmx_mio_twsx_sw_twsi_s cn30xx; | ||
| 1137 | struct cvmx_mio_twsx_sw_twsi_s cn31xx; | ||
| 1138 | struct cvmx_mio_twsx_sw_twsi_s cn38xx; | ||
| 1139 | struct cvmx_mio_twsx_sw_twsi_s cn38xxp2; | ||
| 1140 | struct cvmx_mio_twsx_sw_twsi_s cn50xx; | ||
| 1141 | struct cvmx_mio_twsx_sw_twsi_s cn52xx; | ||
| 1142 | struct cvmx_mio_twsx_sw_twsi_s cn52xxp1; | ||
| 1143 | struct cvmx_mio_twsx_sw_twsi_s cn56xx; | ||
| 1144 | struct cvmx_mio_twsx_sw_twsi_s cn56xxp1; | ||
| 1145 | struct cvmx_mio_twsx_sw_twsi_s cn58xx; | ||
| 1146 | struct cvmx_mio_twsx_sw_twsi_s cn58xxp1; | ||
| 1147 | }; | ||
| 1148 | |||
| 1149 | union cvmx_mio_twsx_sw_twsi_ext { | ||
| 1150 | uint64_t u64; | ||
| 1151 | struct cvmx_mio_twsx_sw_twsi_ext_s { | ||
| 1152 | uint64_t reserved_40_63:24; | ||
| 1153 | uint64_t ia:8; | ||
| 1154 | uint64_t d:32; | ||
| 1155 | } s; | ||
| 1156 | struct cvmx_mio_twsx_sw_twsi_ext_s cn30xx; | ||
| 1157 | struct cvmx_mio_twsx_sw_twsi_ext_s cn31xx; | ||
| 1158 | struct cvmx_mio_twsx_sw_twsi_ext_s cn38xx; | ||
| 1159 | struct cvmx_mio_twsx_sw_twsi_ext_s cn38xxp2; | ||
| 1160 | struct cvmx_mio_twsx_sw_twsi_ext_s cn50xx; | ||
| 1161 | struct cvmx_mio_twsx_sw_twsi_ext_s cn52xx; | ||
| 1162 | struct cvmx_mio_twsx_sw_twsi_ext_s cn52xxp1; | ||
| 1163 | struct cvmx_mio_twsx_sw_twsi_ext_s cn56xx; | ||
| 1164 | struct cvmx_mio_twsx_sw_twsi_ext_s cn56xxp1; | ||
| 1165 | struct cvmx_mio_twsx_sw_twsi_ext_s cn58xx; | ||
| 1166 | struct cvmx_mio_twsx_sw_twsi_ext_s cn58xxp1; | ||
| 1167 | }; | ||
| 1168 | |||
| 1169 | union cvmx_mio_twsx_twsi_sw { | ||
| 1170 | uint64_t u64; | ||
| 1171 | struct cvmx_mio_twsx_twsi_sw_s { | ||
| 1172 | uint64_t v:2; | ||
| 1173 | uint64_t reserved_32_61:30; | ||
| 1174 | uint64_t d:32; | ||
| 1175 | } s; | ||
| 1176 | struct cvmx_mio_twsx_twsi_sw_s cn30xx; | ||
| 1177 | struct cvmx_mio_twsx_twsi_sw_s cn31xx; | ||
| 1178 | struct cvmx_mio_twsx_twsi_sw_s cn38xx; | ||
| 1179 | struct cvmx_mio_twsx_twsi_sw_s cn38xxp2; | ||
| 1180 | struct cvmx_mio_twsx_twsi_sw_s cn50xx; | ||
| 1181 | struct cvmx_mio_twsx_twsi_sw_s cn52xx; | ||
| 1182 | struct cvmx_mio_twsx_twsi_sw_s cn52xxp1; | ||
| 1183 | struct cvmx_mio_twsx_twsi_sw_s cn56xx; | ||
| 1184 | struct cvmx_mio_twsx_twsi_sw_s cn56xxp1; | ||
| 1185 | struct cvmx_mio_twsx_twsi_sw_s cn58xx; | ||
| 1186 | struct cvmx_mio_twsx_twsi_sw_s cn58xxp1; | ||
| 1187 | }; | ||
| 1188 | |||
| 1189 | union cvmx_mio_uartx_dlh { | ||
| 1190 | uint64_t u64; | ||
| 1191 | struct cvmx_mio_uartx_dlh_s { | ||
| 1192 | uint64_t reserved_8_63:56; | ||
| 1193 | uint64_t dlh:8; | ||
| 1194 | } s; | ||
| 1195 | struct cvmx_mio_uartx_dlh_s cn30xx; | ||
| 1196 | struct cvmx_mio_uartx_dlh_s cn31xx; | ||
| 1197 | struct cvmx_mio_uartx_dlh_s cn38xx; | ||
| 1198 | struct cvmx_mio_uartx_dlh_s cn38xxp2; | ||
| 1199 | struct cvmx_mio_uartx_dlh_s cn50xx; | ||
| 1200 | struct cvmx_mio_uartx_dlh_s cn52xx; | ||
| 1201 | struct cvmx_mio_uartx_dlh_s cn52xxp1; | ||
| 1202 | struct cvmx_mio_uartx_dlh_s cn56xx; | ||
| 1203 | struct cvmx_mio_uartx_dlh_s cn56xxp1; | ||
| 1204 | struct cvmx_mio_uartx_dlh_s cn58xx; | ||
| 1205 | struct cvmx_mio_uartx_dlh_s cn58xxp1; | ||
| 1206 | }; | ||
| 1207 | |||
| 1208 | union cvmx_mio_uartx_dll { | ||
| 1209 | uint64_t u64; | ||
| 1210 | struct cvmx_mio_uartx_dll_s { | ||
| 1211 | uint64_t reserved_8_63:56; | ||
| 1212 | uint64_t dll:8; | ||
| 1213 | } s; | ||
| 1214 | struct cvmx_mio_uartx_dll_s cn30xx; | ||
| 1215 | struct cvmx_mio_uartx_dll_s cn31xx; | ||
| 1216 | struct cvmx_mio_uartx_dll_s cn38xx; | ||
| 1217 | struct cvmx_mio_uartx_dll_s cn38xxp2; | ||
| 1218 | struct cvmx_mio_uartx_dll_s cn50xx; | ||
| 1219 | struct cvmx_mio_uartx_dll_s cn52xx; | ||
| 1220 | struct cvmx_mio_uartx_dll_s cn52xxp1; | ||
| 1221 | struct cvmx_mio_uartx_dll_s cn56xx; | ||
| 1222 | struct cvmx_mio_uartx_dll_s cn56xxp1; | ||
| 1223 | struct cvmx_mio_uartx_dll_s cn58xx; | ||
| 1224 | struct cvmx_mio_uartx_dll_s cn58xxp1; | ||
| 1225 | }; | ||
| 1226 | |||
| 1227 | union cvmx_mio_uartx_far { | ||
| 1228 | uint64_t u64; | ||
| 1229 | struct cvmx_mio_uartx_far_s { | ||
| 1230 | uint64_t reserved_1_63:63; | ||
| 1231 | uint64_t far:1; | ||
| 1232 | } s; | ||
| 1233 | struct cvmx_mio_uartx_far_s cn30xx; | ||
| 1234 | struct cvmx_mio_uartx_far_s cn31xx; | ||
| 1235 | struct cvmx_mio_uartx_far_s cn38xx; | ||
| 1236 | struct cvmx_mio_uartx_far_s cn38xxp2; | ||
| 1237 | struct cvmx_mio_uartx_far_s cn50xx; | ||
| 1238 | struct cvmx_mio_uartx_far_s cn52xx; | ||
| 1239 | struct cvmx_mio_uartx_far_s cn52xxp1; | ||
| 1240 | struct cvmx_mio_uartx_far_s cn56xx; | ||
| 1241 | struct cvmx_mio_uartx_far_s cn56xxp1; | ||
| 1242 | struct cvmx_mio_uartx_far_s cn58xx; | ||
| 1243 | struct cvmx_mio_uartx_far_s cn58xxp1; | ||
| 1244 | }; | ||
| 1245 | |||
| 1246 | union cvmx_mio_uartx_fcr { | ||
| 1247 | uint64_t u64; | ||
| 1248 | struct cvmx_mio_uartx_fcr_s { | ||
| 1249 | uint64_t reserved_8_63:56; | ||
| 1250 | uint64_t rxtrig:2; | ||
| 1251 | uint64_t txtrig:2; | ||
| 1252 | uint64_t reserved_3_3:1; | ||
| 1253 | uint64_t txfr:1; | ||
| 1254 | uint64_t rxfr:1; | ||
| 1255 | uint64_t en:1; | ||
| 1256 | } s; | ||
| 1257 | struct cvmx_mio_uartx_fcr_s cn30xx; | ||
| 1258 | struct cvmx_mio_uartx_fcr_s cn31xx; | ||
| 1259 | struct cvmx_mio_uartx_fcr_s cn38xx; | ||
| 1260 | struct cvmx_mio_uartx_fcr_s cn38xxp2; | ||
| 1261 | struct cvmx_mio_uartx_fcr_s cn50xx; | ||
| 1262 | struct cvmx_mio_uartx_fcr_s cn52xx; | ||
| 1263 | struct cvmx_mio_uartx_fcr_s cn52xxp1; | ||
| 1264 | struct cvmx_mio_uartx_fcr_s cn56xx; | ||
| 1265 | struct cvmx_mio_uartx_fcr_s cn56xxp1; | ||
| 1266 | struct cvmx_mio_uartx_fcr_s cn58xx; | ||
| 1267 | struct cvmx_mio_uartx_fcr_s cn58xxp1; | ||
| 1268 | }; | ||
| 1269 | |||
| 1270 | union cvmx_mio_uartx_htx { | ||
| 1271 | uint64_t u64; | ||
| 1272 | struct cvmx_mio_uartx_htx_s { | ||
| 1273 | uint64_t reserved_1_63:63; | ||
| 1274 | uint64_t htx:1; | ||
| 1275 | } s; | ||
| 1276 | struct cvmx_mio_uartx_htx_s cn30xx; | ||
| 1277 | struct cvmx_mio_uartx_htx_s cn31xx; | ||
| 1278 | struct cvmx_mio_uartx_htx_s cn38xx; | ||
| 1279 | struct cvmx_mio_uartx_htx_s cn38xxp2; | ||
| 1280 | struct cvmx_mio_uartx_htx_s cn50xx; | ||
| 1281 | struct cvmx_mio_uartx_htx_s cn52xx; | ||
| 1282 | struct cvmx_mio_uartx_htx_s cn52xxp1; | ||
| 1283 | struct cvmx_mio_uartx_htx_s cn56xx; | ||
| 1284 | struct cvmx_mio_uartx_htx_s cn56xxp1; | ||
| 1285 | struct cvmx_mio_uartx_htx_s cn58xx; | ||
| 1286 | struct cvmx_mio_uartx_htx_s cn58xxp1; | ||
| 1287 | }; | ||
| 1288 | |||
| 1289 | union cvmx_mio_uartx_ier { | ||
| 1290 | uint64_t u64; | ||
| 1291 | struct cvmx_mio_uartx_ier_s { | ||
| 1292 | uint64_t reserved_8_63:56; | ||
| 1293 | uint64_t ptime:1; | ||
| 1294 | uint64_t reserved_4_6:3; | ||
| 1295 | uint64_t edssi:1; | ||
| 1296 | uint64_t elsi:1; | ||
| 1297 | uint64_t etbei:1; | ||
| 1298 | uint64_t erbfi:1; | ||
| 1299 | } s; | ||
| 1300 | struct cvmx_mio_uartx_ier_s cn30xx; | ||
| 1301 | struct cvmx_mio_uartx_ier_s cn31xx; | ||
| 1302 | struct cvmx_mio_uartx_ier_s cn38xx; | ||
| 1303 | struct cvmx_mio_uartx_ier_s cn38xxp2; | ||
| 1304 | struct cvmx_mio_uartx_ier_s cn50xx; | ||
| 1305 | struct cvmx_mio_uartx_ier_s cn52xx; | ||
| 1306 | struct cvmx_mio_uartx_ier_s cn52xxp1; | ||
| 1307 | struct cvmx_mio_uartx_ier_s cn56xx; | ||
| 1308 | struct cvmx_mio_uartx_ier_s cn56xxp1; | ||
| 1309 | struct cvmx_mio_uartx_ier_s cn58xx; | ||
| 1310 | struct cvmx_mio_uartx_ier_s cn58xxp1; | ||
| 1311 | }; | ||
| 1312 | |||
| 1313 | union cvmx_mio_uartx_iir { | ||
| 1314 | uint64_t u64; | ||
| 1315 | struct cvmx_mio_uartx_iir_s { | ||
| 1316 | uint64_t reserved_8_63:56; | ||
| 1317 | uint64_t fen:2; | ||
| 1318 | uint64_t reserved_4_5:2; | ||
| 1319 | uint64_t iid:4; | ||
| 1320 | } s; | ||
| 1321 | struct cvmx_mio_uartx_iir_s cn30xx; | ||
| 1322 | struct cvmx_mio_uartx_iir_s cn31xx; | ||
| 1323 | struct cvmx_mio_uartx_iir_s cn38xx; | ||
| 1324 | struct cvmx_mio_uartx_iir_s cn38xxp2; | ||
| 1325 | struct cvmx_mio_uartx_iir_s cn50xx; | ||
| 1326 | struct cvmx_mio_uartx_iir_s cn52xx; | ||
| 1327 | struct cvmx_mio_uartx_iir_s cn52xxp1; | ||
| 1328 | struct cvmx_mio_uartx_iir_s cn56xx; | ||
| 1329 | struct cvmx_mio_uartx_iir_s cn56xxp1; | ||
| 1330 | struct cvmx_mio_uartx_iir_s cn58xx; | ||
| 1331 | struct cvmx_mio_uartx_iir_s cn58xxp1; | ||
| 1332 | }; | ||
| 1333 | |||
| 1334 | union cvmx_mio_uartx_lcr { | ||
| 1335 | uint64_t u64; | ||
| 1336 | struct cvmx_mio_uartx_lcr_s { | ||
| 1337 | uint64_t reserved_8_63:56; | ||
| 1338 | uint64_t dlab:1; | ||
| 1339 | uint64_t brk:1; | ||
| 1340 | uint64_t reserved_5_5:1; | ||
| 1341 | uint64_t eps:1; | ||
| 1342 | uint64_t pen:1; | ||
| 1343 | uint64_t stop:1; | ||
| 1344 | uint64_t cls:2; | ||
| 1345 | } s; | ||
| 1346 | struct cvmx_mio_uartx_lcr_s cn30xx; | ||
| 1347 | struct cvmx_mio_uartx_lcr_s cn31xx; | ||
| 1348 | struct cvmx_mio_uartx_lcr_s cn38xx; | ||
| 1349 | struct cvmx_mio_uartx_lcr_s cn38xxp2; | ||
| 1350 | struct cvmx_mio_uartx_lcr_s cn50xx; | ||
| 1351 | struct cvmx_mio_uartx_lcr_s cn52xx; | ||
| 1352 | struct cvmx_mio_uartx_lcr_s cn52xxp1; | ||
| 1353 | struct cvmx_mio_uartx_lcr_s cn56xx; | ||
| 1354 | struct cvmx_mio_uartx_lcr_s cn56xxp1; | ||
| 1355 | struct cvmx_mio_uartx_lcr_s cn58xx; | ||
| 1356 | struct cvmx_mio_uartx_lcr_s cn58xxp1; | ||
| 1357 | }; | ||
| 1358 | |||
| 1359 | union cvmx_mio_uartx_lsr { | ||
| 1360 | uint64_t u64; | ||
| 1361 | struct cvmx_mio_uartx_lsr_s { | ||
| 1362 | uint64_t reserved_8_63:56; | ||
| 1363 | uint64_t ferr:1; | ||
| 1364 | uint64_t temt:1; | ||
| 1365 | uint64_t thre:1; | ||
| 1366 | uint64_t bi:1; | ||
| 1367 | uint64_t fe:1; | ||
| 1368 | uint64_t pe:1; | ||
| 1369 | uint64_t oe:1; | ||
| 1370 | uint64_t dr:1; | ||
| 1371 | } s; | ||
| 1372 | struct cvmx_mio_uartx_lsr_s cn30xx; | ||
| 1373 | struct cvmx_mio_uartx_lsr_s cn31xx; | ||
| 1374 | struct cvmx_mio_uartx_lsr_s cn38xx; | ||
| 1375 | struct cvmx_mio_uartx_lsr_s cn38xxp2; | ||
| 1376 | struct cvmx_mio_uartx_lsr_s cn50xx; | ||
| 1377 | struct cvmx_mio_uartx_lsr_s cn52xx; | ||
| 1378 | struct cvmx_mio_uartx_lsr_s cn52xxp1; | ||
| 1379 | struct cvmx_mio_uartx_lsr_s cn56xx; | ||
| 1380 | struct cvmx_mio_uartx_lsr_s cn56xxp1; | ||
| 1381 | struct cvmx_mio_uartx_lsr_s cn58xx; | ||
| 1382 | struct cvmx_mio_uartx_lsr_s cn58xxp1; | ||
| 1383 | }; | ||
| 1384 | |||
| 1385 | union cvmx_mio_uartx_mcr { | ||
| 1386 | uint64_t u64; | ||
| 1387 | struct cvmx_mio_uartx_mcr_s { | ||
| 1388 | uint64_t reserved_6_63:58; | ||
| 1389 | uint64_t afce:1; | ||
| 1390 | uint64_t loop:1; | ||
| 1391 | uint64_t out2:1; | ||
| 1392 | uint64_t out1:1; | ||
| 1393 | uint64_t rts:1; | ||
| 1394 | uint64_t dtr:1; | ||
| 1395 | } s; | ||
| 1396 | struct cvmx_mio_uartx_mcr_s cn30xx; | ||
| 1397 | struct cvmx_mio_uartx_mcr_s cn31xx; | ||
| 1398 | struct cvmx_mio_uartx_mcr_s cn38xx; | ||
| 1399 | struct cvmx_mio_uartx_mcr_s cn38xxp2; | ||
| 1400 | struct cvmx_mio_uartx_mcr_s cn50xx; | ||
| 1401 | struct cvmx_mio_uartx_mcr_s cn52xx; | ||
| 1402 | struct cvmx_mio_uartx_mcr_s cn52xxp1; | ||
| 1403 | struct cvmx_mio_uartx_mcr_s cn56xx; | ||
| 1404 | struct cvmx_mio_uartx_mcr_s cn56xxp1; | ||
| 1405 | struct cvmx_mio_uartx_mcr_s cn58xx; | ||
| 1406 | struct cvmx_mio_uartx_mcr_s cn58xxp1; | ||
| 1407 | }; | ||
| 1408 | |||
| 1409 | union cvmx_mio_uartx_msr { | ||
| 1410 | uint64_t u64; | ||
| 1411 | struct cvmx_mio_uartx_msr_s { | ||
| 1412 | uint64_t reserved_8_63:56; | ||
| 1413 | uint64_t dcd:1; | ||
| 1414 | uint64_t ri:1; | ||
| 1415 | uint64_t dsr:1; | ||
| 1416 | uint64_t cts:1; | ||
| 1417 | uint64_t ddcd:1; | ||
| 1418 | uint64_t teri:1; | ||
| 1419 | uint64_t ddsr:1; | ||
| 1420 | uint64_t dcts:1; | ||
| 1421 | } s; | ||
| 1422 | struct cvmx_mio_uartx_msr_s cn30xx; | ||
| 1423 | struct cvmx_mio_uartx_msr_s cn31xx; | ||
| 1424 | struct cvmx_mio_uartx_msr_s cn38xx; | ||
| 1425 | struct cvmx_mio_uartx_msr_s cn38xxp2; | ||
| 1426 | struct cvmx_mio_uartx_msr_s cn50xx; | ||
| 1427 | struct cvmx_mio_uartx_msr_s cn52xx; | ||
| 1428 | struct cvmx_mio_uartx_msr_s cn52xxp1; | ||
| 1429 | struct cvmx_mio_uartx_msr_s cn56xx; | ||
| 1430 | struct cvmx_mio_uartx_msr_s cn56xxp1; | ||
| 1431 | struct cvmx_mio_uartx_msr_s cn58xx; | ||
| 1432 | struct cvmx_mio_uartx_msr_s cn58xxp1; | ||
| 1433 | }; | ||
| 1434 | |||
| 1435 | union cvmx_mio_uartx_rbr { | ||
| 1436 | uint64_t u64; | ||
| 1437 | struct cvmx_mio_uartx_rbr_s { | ||
| 1438 | uint64_t reserved_8_63:56; | ||
| 1439 | uint64_t rbr:8; | ||
| 1440 | } s; | ||
| 1441 | struct cvmx_mio_uartx_rbr_s cn30xx; | ||
| 1442 | struct cvmx_mio_uartx_rbr_s cn31xx; | ||
| 1443 | struct cvmx_mio_uartx_rbr_s cn38xx; | ||
| 1444 | struct cvmx_mio_uartx_rbr_s cn38xxp2; | ||
| 1445 | struct cvmx_mio_uartx_rbr_s cn50xx; | ||
| 1446 | struct cvmx_mio_uartx_rbr_s cn52xx; | ||
| 1447 | struct cvmx_mio_uartx_rbr_s cn52xxp1; | ||
| 1448 | struct cvmx_mio_uartx_rbr_s cn56xx; | ||
| 1449 | struct cvmx_mio_uartx_rbr_s cn56xxp1; | ||
| 1450 | struct cvmx_mio_uartx_rbr_s cn58xx; | ||
| 1451 | struct cvmx_mio_uartx_rbr_s cn58xxp1; | ||
| 1452 | }; | ||
| 1453 | |||
| 1454 | union cvmx_mio_uartx_rfl { | ||
| 1455 | uint64_t u64; | ||
| 1456 | struct cvmx_mio_uartx_rfl_s { | ||
| 1457 | uint64_t reserved_7_63:57; | ||
| 1458 | uint64_t rfl:7; | ||
| 1459 | } s; | ||
| 1460 | struct cvmx_mio_uartx_rfl_s cn30xx; | ||
| 1461 | struct cvmx_mio_uartx_rfl_s cn31xx; | ||
| 1462 | struct cvmx_mio_uartx_rfl_s cn38xx; | ||
| 1463 | struct cvmx_mio_uartx_rfl_s cn38xxp2; | ||
| 1464 | struct cvmx_mio_uartx_rfl_s cn50xx; | ||
| 1465 | struct cvmx_mio_uartx_rfl_s cn52xx; | ||
| 1466 | struct cvmx_mio_uartx_rfl_s cn52xxp1; | ||
| 1467 | struct cvmx_mio_uartx_rfl_s cn56xx; | ||
| 1468 | struct cvmx_mio_uartx_rfl_s cn56xxp1; | ||
| 1469 | struct cvmx_mio_uartx_rfl_s cn58xx; | ||
| 1470 | struct cvmx_mio_uartx_rfl_s cn58xxp1; | ||
| 1471 | }; | ||
| 1472 | |||
| 1473 | union cvmx_mio_uartx_rfw { | ||
| 1474 | uint64_t u64; | ||
| 1475 | struct cvmx_mio_uartx_rfw_s { | ||
| 1476 | uint64_t reserved_10_63:54; | ||
| 1477 | uint64_t rffe:1; | ||
| 1478 | uint64_t rfpe:1; | ||
| 1479 | uint64_t rfwd:8; | ||
| 1480 | } s; | ||
| 1481 | struct cvmx_mio_uartx_rfw_s cn30xx; | ||
| 1482 | struct cvmx_mio_uartx_rfw_s cn31xx; | ||
| 1483 | struct cvmx_mio_uartx_rfw_s cn38xx; | ||
| 1484 | struct cvmx_mio_uartx_rfw_s cn38xxp2; | ||
| 1485 | struct cvmx_mio_uartx_rfw_s cn50xx; | ||
| 1486 | struct cvmx_mio_uartx_rfw_s cn52xx; | ||
| 1487 | struct cvmx_mio_uartx_rfw_s cn52xxp1; | ||
| 1488 | struct cvmx_mio_uartx_rfw_s cn56xx; | ||
| 1489 | struct cvmx_mio_uartx_rfw_s cn56xxp1; | ||
| 1490 | struct cvmx_mio_uartx_rfw_s cn58xx; | ||
| 1491 | struct cvmx_mio_uartx_rfw_s cn58xxp1; | ||
| 1492 | }; | ||
| 1493 | |||
| 1494 | union cvmx_mio_uartx_sbcr { | ||
| 1495 | uint64_t u64; | ||
| 1496 | struct cvmx_mio_uartx_sbcr_s { | ||
| 1497 | uint64_t reserved_1_63:63; | ||
| 1498 | uint64_t sbcr:1; | ||
| 1499 | } s; | ||
| 1500 | struct cvmx_mio_uartx_sbcr_s cn30xx; | ||
| 1501 | struct cvmx_mio_uartx_sbcr_s cn31xx; | ||
| 1502 | struct cvmx_mio_uartx_sbcr_s cn38xx; | ||
| 1503 | struct cvmx_mio_uartx_sbcr_s cn38xxp2; | ||
| 1504 | struct cvmx_mio_uartx_sbcr_s cn50xx; | ||
| 1505 | struct cvmx_mio_uartx_sbcr_s cn52xx; | ||
| 1506 | struct cvmx_mio_uartx_sbcr_s cn52xxp1; | ||
| 1507 | struct cvmx_mio_uartx_sbcr_s cn56xx; | ||
| 1508 | struct cvmx_mio_uartx_sbcr_s cn56xxp1; | ||
| 1509 | struct cvmx_mio_uartx_sbcr_s cn58xx; | ||
| 1510 | struct cvmx_mio_uartx_sbcr_s cn58xxp1; | ||
| 1511 | }; | ||
| 1512 | |||
| 1513 | union cvmx_mio_uartx_scr { | ||
| 1514 | uint64_t u64; | ||
| 1515 | struct cvmx_mio_uartx_scr_s { | ||
| 1516 | uint64_t reserved_8_63:56; | ||
| 1517 | uint64_t scr:8; | ||
| 1518 | } s; | ||
| 1519 | struct cvmx_mio_uartx_scr_s cn30xx; | ||
| 1520 | struct cvmx_mio_uartx_scr_s cn31xx; | ||
| 1521 | struct cvmx_mio_uartx_scr_s cn38xx; | ||
| 1522 | struct cvmx_mio_uartx_scr_s cn38xxp2; | ||
| 1523 | struct cvmx_mio_uartx_scr_s cn50xx; | ||
| 1524 | struct cvmx_mio_uartx_scr_s cn52xx; | ||
| 1525 | struct cvmx_mio_uartx_scr_s cn52xxp1; | ||
| 1526 | struct cvmx_mio_uartx_scr_s cn56xx; | ||
| 1527 | struct cvmx_mio_uartx_scr_s cn56xxp1; | ||
| 1528 | struct cvmx_mio_uartx_scr_s cn58xx; | ||
| 1529 | struct cvmx_mio_uartx_scr_s cn58xxp1; | ||
| 1530 | }; | ||
| 1531 | |||
| 1532 | union cvmx_mio_uartx_sfe { | ||
| 1533 | uint64_t u64; | ||
| 1534 | struct cvmx_mio_uartx_sfe_s { | ||
| 1535 | uint64_t reserved_1_63:63; | ||
| 1536 | uint64_t sfe:1; | ||
| 1537 | } s; | ||
| 1538 | struct cvmx_mio_uartx_sfe_s cn30xx; | ||
| 1539 | struct cvmx_mio_uartx_sfe_s cn31xx; | ||
| 1540 | struct cvmx_mio_uartx_sfe_s cn38xx; | ||
| 1541 | struct cvmx_mio_uartx_sfe_s cn38xxp2; | ||
| 1542 | struct cvmx_mio_uartx_sfe_s cn50xx; | ||
| 1543 | struct cvmx_mio_uartx_sfe_s cn52xx; | ||
| 1544 | struct cvmx_mio_uartx_sfe_s cn52xxp1; | ||
| 1545 | struct cvmx_mio_uartx_sfe_s cn56xx; | ||
| 1546 | struct cvmx_mio_uartx_sfe_s cn56xxp1; | ||
| 1547 | struct cvmx_mio_uartx_sfe_s cn58xx; | ||
| 1548 | struct cvmx_mio_uartx_sfe_s cn58xxp1; | ||
| 1549 | }; | ||
| 1550 | |||
| 1551 | union cvmx_mio_uartx_srr { | ||
| 1552 | uint64_t u64; | ||
| 1553 | struct cvmx_mio_uartx_srr_s { | ||
| 1554 | uint64_t reserved_3_63:61; | ||
| 1555 | uint64_t stfr:1; | ||
| 1556 | uint64_t srfr:1; | ||
| 1557 | uint64_t usr:1; | ||
| 1558 | } s; | ||
| 1559 | struct cvmx_mio_uartx_srr_s cn30xx; | ||
| 1560 | struct cvmx_mio_uartx_srr_s cn31xx; | ||
| 1561 | struct cvmx_mio_uartx_srr_s cn38xx; | ||
| 1562 | struct cvmx_mio_uartx_srr_s cn38xxp2; | ||
| 1563 | struct cvmx_mio_uartx_srr_s cn50xx; | ||
| 1564 | struct cvmx_mio_uartx_srr_s cn52xx; | ||
| 1565 | struct cvmx_mio_uartx_srr_s cn52xxp1; | ||
| 1566 | struct cvmx_mio_uartx_srr_s cn56xx; | ||
| 1567 | struct cvmx_mio_uartx_srr_s cn56xxp1; | ||
| 1568 | struct cvmx_mio_uartx_srr_s cn58xx; | ||
| 1569 | struct cvmx_mio_uartx_srr_s cn58xxp1; | ||
| 1570 | }; | ||
| 1571 | |||
| 1572 | union cvmx_mio_uartx_srt { | ||
| 1573 | uint64_t u64; | ||
| 1574 | struct cvmx_mio_uartx_srt_s { | ||
| 1575 | uint64_t reserved_2_63:62; | ||
| 1576 | uint64_t srt:2; | ||
| 1577 | } s; | ||
| 1578 | struct cvmx_mio_uartx_srt_s cn30xx; | ||
| 1579 | struct cvmx_mio_uartx_srt_s cn31xx; | ||
| 1580 | struct cvmx_mio_uartx_srt_s cn38xx; | ||
| 1581 | struct cvmx_mio_uartx_srt_s cn38xxp2; | ||
| 1582 | struct cvmx_mio_uartx_srt_s cn50xx; | ||
| 1583 | struct cvmx_mio_uartx_srt_s cn52xx; | ||
| 1584 | struct cvmx_mio_uartx_srt_s cn52xxp1; | ||
| 1585 | struct cvmx_mio_uartx_srt_s cn56xx; | ||
| 1586 | struct cvmx_mio_uartx_srt_s cn56xxp1; | ||
| 1587 | struct cvmx_mio_uartx_srt_s cn58xx; | ||
| 1588 | struct cvmx_mio_uartx_srt_s cn58xxp1; | ||
| 1589 | }; | ||
| 1590 | |||
| 1591 | union cvmx_mio_uartx_srts { | ||
| 1592 | uint64_t u64; | ||
| 1593 | struct cvmx_mio_uartx_srts_s { | ||
| 1594 | uint64_t reserved_1_63:63; | ||
| 1595 | uint64_t srts:1; | ||
| 1596 | } s; | ||
| 1597 | struct cvmx_mio_uartx_srts_s cn30xx; | ||
| 1598 | struct cvmx_mio_uartx_srts_s cn31xx; | ||
| 1599 | struct cvmx_mio_uartx_srts_s cn38xx; | ||
| 1600 | struct cvmx_mio_uartx_srts_s cn38xxp2; | ||
| 1601 | struct cvmx_mio_uartx_srts_s cn50xx; | ||
| 1602 | struct cvmx_mio_uartx_srts_s cn52xx; | ||
| 1603 | struct cvmx_mio_uartx_srts_s cn52xxp1; | ||
| 1604 | struct cvmx_mio_uartx_srts_s cn56xx; | ||
| 1605 | struct cvmx_mio_uartx_srts_s cn56xxp1; | ||
| 1606 | struct cvmx_mio_uartx_srts_s cn58xx; | ||
| 1607 | struct cvmx_mio_uartx_srts_s cn58xxp1; | ||
| 1608 | }; | ||
| 1609 | |||
| 1610 | union cvmx_mio_uartx_stt { | ||
| 1611 | uint64_t u64; | ||
| 1612 | struct cvmx_mio_uartx_stt_s { | ||
| 1613 | uint64_t reserved_2_63:62; | ||
| 1614 | uint64_t stt:2; | ||
| 1615 | } s; | ||
| 1616 | struct cvmx_mio_uartx_stt_s cn30xx; | ||
| 1617 | struct cvmx_mio_uartx_stt_s cn31xx; | ||
| 1618 | struct cvmx_mio_uartx_stt_s cn38xx; | ||
| 1619 | struct cvmx_mio_uartx_stt_s cn38xxp2; | ||
| 1620 | struct cvmx_mio_uartx_stt_s cn50xx; | ||
| 1621 | struct cvmx_mio_uartx_stt_s cn52xx; | ||
| 1622 | struct cvmx_mio_uartx_stt_s cn52xxp1; | ||
| 1623 | struct cvmx_mio_uartx_stt_s cn56xx; | ||
| 1624 | struct cvmx_mio_uartx_stt_s cn56xxp1; | ||
| 1625 | struct cvmx_mio_uartx_stt_s cn58xx; | ||
| 1626 | struct cvmx_mio_uartx_stt_s cn58xxp1; | ||
| 1627 | }; | ||
| 1628 | |||
| 1629 | union cvmx_mio_uartx_tfl { | ||
| 1630 | uint64_t u64; | ||
| 1631 | struct cvmx_mio_uartx_tfl_s { | ||
| 1632 | uint64_t reserved_7_63:57; | ||
| 1633 | uint64_t tfl:7; | ||
| 1634 | } s; | ||
| 1635 | struct cvmx_mio_uartx_tfl_s cn30xx; | ||
| 1636 | struct cvmx_mio_uartx_tfl_s cn31xx; | ||
| 1637 | struct cvmx_mio_uartx_tfl_s cn38xx; | ||
| 1638 | struct cvmx_mio_uartx_tfl_s cn38xxp2; | ||
| 1639 | struct cvmx_mio_uartx_tfl_s cn50xx; | ||
| 1640 | struct cvmx_mio_uartx_tfl_s cn52xx; | ||
| 1641 | struct cvmx_mio_uartx_tfl_s cn52xxp1; | ||
| 1642 | struct cvmx_mio_uartx_tfl_s cn56xx; | ||
| 1643 | struct cvmx_mio_uartx_tfl_s cn56xxp1; | ||
| 1644 | struct cvmx_mio_uartx_tfl_s cn58xx; | ||
| 1645 | struct cvmx_mio_uartx_tfl_s cn58xxp1; | ||
| 1646 | }; | ||
| 1647 | |||
| 1648 | union cvmx_mio_uartx_tfr { | ||
| 1649 | uint64_t u64; | ||
| 1650 | struct cvmx_mio_uartx_tfr_s { | ||
| 1651 | uint64_t reserved_8_63:56; | ||
| 1652 | uint64_t tfr:8; | ||
| 1653 | } s; | ||
| 1654 | struct cvmx_mio_uartx_tfr_s cn30xx; | ||
| 1655 | struct cvmx_mio_uartx_tfr_s cn31xx; | ||
| 1656 | struct cvmx_mio_uartx_tfr_s cn38xx; | ||
| 1657 | struct cvmx_mio_uartx_tfr_s cn38xxp2; | ||
| 1658 | struct cvmx_mio_uartx_tfr_s cn50xx; | ||
| 1659 | struct cvmx_mio_uartx_tfr_s cn52xx; | ||
| 1660 | struct cvmx_mio_uartx_tfr_s cn52xxp1; | ||
| 1661 | struct cvmx_mio_uartx_tfr_s cn56xx; | ||
| 1662 | struct cvmx_mio_uartx_tfr_s cn56xxp1; | ||
| 1663 | struct cvmx_mio_uartx_tfr_s cn58xx; | ||
| 1664 | struct cvmx_mio_uartx_tfr_s cn58xxp1; | ||
| 1665 | }; | ||
| 1666 | |||
| 1667 | union cvmx_mio_uartx_thr { | ||
| 1668 | uint64_t u64; | ||
| 1669 | struct cvmx_mio_uartx_thr_s { | ||
| 1670 | uint64_t reserved_8_63:56; | ||
| 1671 | uint64_t thr:8; | ||
| 1672 | } s; | ||
| 1673 | struct cvmx_mio_uartx_thr_s cn30xx; | ||
| 1674 | struct cvmx_mio_uartx_thr_s cn31xx; | ||
| 1675 | struct cvmx_mio_uartx_thr_s cn38xx; | ||
| 1676 | struct cvmx_mio_uartx_thr_s cn38xxp2; | ||
| 1677 | struct cvmx_mio_uartx_thr_s cn50xx; | ||
| 1678 | struct cvmx_mio_uartx_thr_s cn52xx; | ||
| 1679 | struct cvmx_mio_uartx_thr_s cn52xxp1; | ||
| 1680 | struct cvmx_mio_uartx_thr_s cn56xx; | ||
| 1681 | struct cvmx_mio_uartx_thr_s cn56xxp1; | ||
| 1682 | struct cvmx_mio_uartx_thr_s cn58xx; | ||
| 1683 | struct cvmx_mio_uartx_thr_s cn58xxp1; | ||
| 1684 | }; | ||
| 1685 | |||
| 1686 | union cvmx_mio_uartx_usr { | ||
| 1687 | uint64_t u64; | ||
| 1688 | struct cvmx_mio_uartx_usr_s { | ||
| 1689 | uint64_t reserved_5_63:59; | ||
| 1690 | uint64_t rff:1; | ||
| 1691 | uint64_t rfne:1; | ||
| 1692 | uint64_t tfe:1; | ||
| 1693 | uint64_t tfnf:1; | ||
| 1694 | uint64_t busy:1; | ||
| 1695 | } s; | ||
| 1696 | struct cvmx_mio_uartx_usr_s cn30xx; | ||
| 1697 | struct cvmx_mio_uartx_usr_s cn31xx; | ||
| 1698 | struct cvmx_mio_uartx_usr_s cn38xx; | ||
| 1699 | struct cvmx_mio_uartx_usr_s cn38xxp2; | ||
| 1700 | struct cvmx_mio_uartx_usr_s cn50xx; | ||
| 1701 | struct cvmx_mio_uartx_usr_s cn52xx; | ||
| 1702 | struct cvmx_mio_uartx_usr_s cn52xxp1; | ||
| 1703 | struct cvmx_mio_uartx_usr_s cn56xx; | ||
| 1704 | struct cvmx_mio_uartx_usr_s cn56xxp1; | ||
| 1705 | struct cvmx_mio_uartx_usr_s cn58xx; | ||
| 1706 | struct cvmx_mio_uartx_usr_s cn58xxp1; | ||
| 1707 | }; | ||
| 1708 | |||
| 1709 | union cvmx_mio_uart2_dlh { | ||
| 1710 | uint64_t u64; | ||
| 1711 | struct cvmx_mio_uart2_dlh_s { | ||
| 1712 | uint64_t reserved_8_63:56; | ||
| 1713 | uint64_t dlh:8; | ||
| 1714 | } s; | ||
| 1715 | struct cvmx_mio_uart2_dlh_s cn52xx; | ||
| 1716 | struct cvmx_mio_uart2_dlh_s cn52xxp1; | ||
| 1717 | }; | ||
| 1718 | |||
| 1719 | union cvmx_mio_uart2_dll { | ||
| 1720 | uint64_t u64; | ||
| 1721 | struct cvmx_mio_uart2_dll_s { | ||
| 1722 | uint64_t reserved_8_63:56; | ||
| 1723 | uint64_t dll:8; | ||
| 1724 | } s; | ||
| 1725 | struct cvmx_mio_uart2_dll_s cn52xx; | ||
| 1726 | struct cvmx_mio_uart2_dll_s cn52xxp1; | ||
| 1727 | }; | ||
| 1728 | |||
| 1729 | union cvmx_mio_uart2_far { | ||
| 1730 | uint64_t u64; | ||
| 1731 | struct cvmx_mio_uart2_far_s { | ||
| 1732 | uint64_t reserved_1_63:63; | ||
| 1733 | uint64_t far:1; | ||
| 1734 | } s; | ||
| 1735 | struct cvmx_mio_uart2_far_s cn52xx; | ||
| 1736 | struct cvmx_mio_uart2_far_s cn52xxp1; | ||
| 1737 | }; | ||
| 1738 | |||
| 1739 | union cvmx_mio_uart2_fcr { | ||
| 1740 | uint64_t u64; | ||
| 1741 | struct cvmx_mio_uart2_fcr_s { | ||
| 1742 | uint64_t reserved_8_63:56; | ||
| 1743 | uint64_t rxtrig:2; | ||
| 1744 | uint64_t txtrig:2; | ||
| 1745 | uint64_t reserved_3_3:1; | ||
| 1746 | uint64_t txfr:1; | ||
| 1747 | uint64_t rxfr:1; | ||
| 1748 | uint64_t en:1; | ||
| 1749 | } s; | ||
| 1750 | struct cvmx_mio_uart2_fcr_s cn52xx; | ||
| 1751 | struct cvmx_mio_uart2_fcr_s cn52xxp1; | ||
| 1752 | }; | ||
| 1753 | |||
| 1754 | union cvmx_mio_uart2_htx { | ||
| 1755 | uint64_t u64; | ||
| 1756 | struct cvmx_mio_uart2_htx_s { | ||
| 1757 | uint64_t reserved_1_63:63; | ||
| 1758 | uint64_t htx:1; | ||
| 1759 | } s; | ||
| 1760 | struct cvmx_mio_uart2_htx_s cn52xx; | ||
| 1761 | struct cvmx_mio_uart2_htx_s cn52xxp1; | ||
| 1762 | }; | ||
| 1763 | |||
| 1764 | union cvmx_mio_uart2_ier { | ||
| 1765 | uint64_t u64; | ||
| 1766 | struct cvmx_mio_uart2_ier_s { | ||
| 1767 | uint64_t reserved_8_63:56; | ||
| 1768 | uint64_t ptime:1; | ||
| 1769 | uint64_t reserved_4_6:3; | ||
| 1770 | uint64_t edssi:1; | ||
| 1771 | uint64_t elsi:1; | ||
| 1772 | uint64_t etbei:1; | ||
| 1773 | uint64_t erbfi:1; | ||
| 1774 | } s; | ||
| 1775 | struct cvmx_mio_uart2_ier_s cn52xx; | ||
| 1776 | struct cvmx_mio_uart2_ier_s cn52xxp1; | ||
| 1777 | }; | ||
| 1778 | |||
| 1779 | union cvmx_mio_uart2_iir { | ||
| 1780 | uint64_t u64; | ||
| 1781 | struct cvmx_mio_uart2_iir_s { | ||
| 1782 | uint64_t reserved_8_63:56; | ||
| 1783 | uint64_t fen:2; | ||
| 1784 | uint64_t reserved_4_5:2; | ||
| 1785 | uint64_t iid:4; | ||
| 1786 | } s; | ||
| 1787 | struct cvmx_mio_uart2_iir_s cn52xx; | ||
| 1788 | struct cvmx_mio_uart2_iir_s cn52xxp1; | ||
| 1789 | }; | ||
| 1790 | |||
| 1791 | union cvmx_mio_uart2_lcr { | ||
| 1792 | uint64_t u64; | ||
| 1793 | struct cvmx_mio_uart2_lcr_s { | ||
| 1794 | uint64_t reserved_8_63:56; | ||
| 1795 | uint64_t dlab:1; | ||
| 1796 | uint64_t brk:1; | ||
| 1797 | uint64_t reserved_5_5:1; | ||
| 1798 | uint64_t eps:1; | ||
| 1799 | uint64_t pen:1; | ||
| 1800 | uint64_t stop:1; | ||
| 1801 | uint64_t cls:2; | ||
| 1802 | } s; | ||
| 1803 | struct cvmx_mio_uart2_lcr_s cn52xx; | ||
| 1804 | struct cvmx_mio_uart2_lcr_s cn52xxp1; | ||
| 1805 | }; | ||
| 1806 | |||
| 1807 | union cvmx_mio_uart2_lsr { | ||
| 1808 | uint64_t u64; | ||
| 1809 | struct cvmx_mio_uart2_lsr_s { | ||
| 1810 | uint64_t reserved_8_63:56; | ||
| 1811 | uint64_t ferr:1; | ||
| 1812 | uint64_t temt:1; | ||
| 1813 | uint64_t thre:1; | ||
| 1814 | uint64_t bi:1; | ||
| 1815 | uint64_t fe:1; | ||
| 1816 | uint64_t pe:1; | ||
| 1817 | uint64_t oe:1; | ||
| 1818 | uint64_t dr:1; | ||
| 1819 | } s; | ||
| 1820 | struct cvmx_mio_uart2_lsr_s cn52xx; | ||
| 1821 | struct cvmx_mio_uart2_lsr_s cn52xxp1; | ||
| 1822 | }; | ||
| 1823 | |||
| 1824 | union cvmx_mio_uart2_mcr { | ||
| 1825 | uint64_t u64; | ||
| 1826 | struct cvmx_mio_uart2_mcr_s { | ||
| 1827 | uint64_t reserved_6_63:58; | ||
| 1828 | uint64_t afce:1; | ||
| 1829 | uint64_t loop:1; | ||
| 1830 | uint64_t out2:1; | ||
| 1831 | uint64_t out1:1; | ||
| 1832 | uint64_t rts:1; | ||
| 1833 | uint64_t dtr:1; | ||
| 1834 | } s; | ||
| 1835 | struct cvmx_mio_uart2_mcr_s cn52xx; | ||
| 1836 | struct cvmx_mio_uart2_mcr_s cn52xxp1; | ||
| 1837 | }; | ||
| 1838 | |||
| 1839 | union cvmx_mio_uart2_msr { | ||
| 1840 | uint64_t u64; | ||
| 1841 | struct cvmx_mio_uart2_msr_s { | ||
| 1842 | uint64_t reserved_8_63:56; | ||
| 1843 | uint64_t dcd:1; | ||
| 1844 | uint64_t ri:1; | ||
| 1845 | uint64_t dsr:1; | ||
| 1846 | uint64_t cts:1; | ||
| 1847 | uint64_t ddcd:1; | ||
| 1848 | uint64_t teri:1; | ||
| 1849 | uint64_t ddsr:1; | ||
| 1850 | uint64_t dcts:1; | ||
| 1851 | } s; | ||
| 1852 | struct cvmx_mio_uart2_msr_s cn52xx; | ||
| 1853 | struct cvmx_mio_uart2_msr_s cn52xxp1; | ||
| 1854 | }; | ||
| 1855 | |||
| 1856 | union cvmx_mio_uart2_rbr { | ||
| 1857 | uint64_t u64; | ||
| 1858 | struct cvmx_mio_uart2_rbr_s { | ||
| 1859 | uint64_t reserved_8_63:56; | ||
| 1860 | uint64_t rbr:8; | ||
| 1861 | } s; | ||
| 1862 | struct cvmx_mio_uart2_rbr_s cn52xx; | ||
| 1863 | struct cvmx_mio_uart2_rbr_s cn52xxp1; | ||
| 1864 | }; | ||
| 1865 | |||
| 1866 | union cvmx_mio_uart2_rfl { | ||
| 1867 | uint64_t u64; | ||
| 1868 | struct cvmx_mio_uart2_rfl_s { | ||
| 1869 | uint64_t reserved_7_63:57; | ||
| 1870 | uint64_t rfl:7; | ||
| 1871 | } s; | ||
| 1872 | struct cvmx_mio_uart2_rfl_s cn52xx; | ||
| 1873 | struct cvmx_mio_uart2_rfl_s cn52xxp1; | ||
| 1874 | }; | ||
| 1875 | |||
| 1876 | union cvmx_mio_uart2_rfw { | ||
| 1877 | uint64_t u64; | ||
| 1878 | struct cvmx_mio_uart2_rfw_s { | ||
| 1879 | uint64_t reserved_10_63:54; | ||
| 1880 | uint64_t rffe:1; | ||
| 1881 | uint64_t rfpe:1; | ||
| 1882 | uint64_t rfwd:8; | ||
| 1883 | } s; | ||
| 1884 | struct cvmx_mio_uart2_rfw_s cn52xx; | ||
| 1885 | struct cvmx_mio_uart2_rfw_s cn52xxp1; | ||
| 1886 | }; | ||
| 1887 | |||
| 1888 | union cvmx_mio_uart2_sbcr { | ||
| 1889 | uint64_t u64; | ||
| 1890 | struct cvmx_mio_uart2_sbcr_s { | ||
| 1891 | uint64_t reserved_1_63:63; | ||
| 1892 | uint64_t sbcr:1; | ||
| 1893 | } s; | ||
| 1894 | struct cvmx_mio_uart2_sbcr_s cn52xx; | ||
| 1895 | struct cvmx_mio_uart2_sbcr_s cn52xxp1; | ||
| 1896 | }; | ||
| 1897 | |||
| 1898 | union cvmx_mio_uart2_scr { | ||
| 1899 | uint64_t u64; | ||
| 1900 | struct cvmx_mio_uart2_scr_s { | ||
| 1901 | uint64_t reserved_8_63:56; | ||
| 1902 | uint64_t scr:8; | ||
| 1903 | } s; | ||
| 1904 | struct cvmx_mio_uart2_scr_s cn52xx; | ||
| 1905 | struct cvmx_mio_uart2_scr_s cn52xxp1; | ||
| 1906 | }; | ||
| 1907 | |||
| 1908 | union cvmx_mio_uart2_sfe { | ||
| 1909 | uint64_t u64; | ||
| 1910 | struct cvmx_mio_uart2_sfe_s { | ||
| 1911 | uint64_t reserved_1_63:63; | ||
| 1912 | uint64_t sfe:1; | ||
| 1913 | } s; | ||
| 1914 | struct cvmx_mio_uart2_sfe_s cn52xx; | ||
| 1915 | struct cvmx_mio_uart2_sfe_s cn52xxp1; | ||
| 1916 | }; | ||
| 1917 | |||
| 1918 | union cvmx_mio_uart2_srr { | ||
| 1919 | uint64_t u64; | ||
| 1920 | struct cvmx_mio_uart2_srr_s { | ||
| 1921 | uint64_t reserved_3_63:61; | ||
| 1922 | uint64_t stfr:1; | ||
| 1923 | uint64_t srfr:1; | ||
| 1924 | uint64_t usr:1; | ||
| 1925 | } s; | ||
| 1926 | struct cvmx_mio_uart2_srr_s cn52xx; | ||
| 1927 | struct cvmx_mio_uart2_srr_s cn52xxp1; | ||
| 1928 | }; | ||
| 1929 | |||
| 1930 | union cvmx_mio_uart2_srt { | ||
| 1931 | uint64_t u64; | ||
| 1932 | struct cvmx_mio_uart2_srt_s { | ||
| 1933 | uint64_t reserved_2_63:62; | ||
| 1934 | uint64_t srt:2; | ||
| 1935 | } s; | ||
| 1936 | struct cvmx_mio_uart2_srt_s cn52xx; | ||
| 1937 | struct cvmx_mio_uart2_srt_s cn52xxp1; | ||
| 1938 | }; | ||
| 1939 | |||
| 1940 | union cvmx_mio_uart2_srts { | ||
| 1941 | uint64_t u64; | ||
| 1942 | struct cvmx_mio_uart2_srts_s { | ||
| 1943 | uint64_t reserved_1_63:63; | ||
| 1944 | uint64_t srts:1; | ||
| 1945 | } s; | ||
| 1946 | struct cvmx_mio_uart2_srts_s cn52xx; | ||
| 1947 | struct cvmx_mio_uart2_srts_s cn52xxp1; | ||
| 1948 | }; | ||
| 1949 | |||
| 1950 | union cvmx_mio_uart2_stt { | ||
| 1951 | uint64_t u64; | ||
| 1952 | struct cvmx_mio_uart2_stt_s { | ||
| 1953 | uint64_t reserved_2_63:62; | ||
| 1954 | uint64_t stt:2; | ||
| 1955 | } s; | ||
| 1956 | struct cvmx_mio_uart2_stt_s cn52xx; | ||
| 1957 | struct cvmx_mio_uart2_stt_s cn52xxp1; | ||
| 1958 | }; | ||
| 1959 | |||
| 1960 | union cvmx_mio_uart2_tfl { | ||
| 1961 | uint64_t u64; | ||
| 1962 | struct cvmx_mio_uart2_tfl_s { | ||
| 1963 | uint64_t reserved_7_63:57; | ||
| 1964 | uint64_t tfl:7; | ||
| 1965 | } s; | ||
| 1966 | struct cvmx_mio_uart2_tfl_s cn52xx; | ||
| 1967 | struct cvmx_mio_uart2_tfl_s cn52xxp1; | ||
| 1968 | }; | ||
| 1969 | |||
| 1970 | union cvmx_mio_uart2_tfr { | ||
| 1971 | uint64_t u64; | ||
| 1972 | struct cvmx_mio_uart2_tfr_s { | ||
| 1973 | uint64_t reserved_8_63:56; | ||
| 1974 | uint64_t tfr:8; | ||
| 1975 | } s; | ||
| 1976 | struct cvmx_mio_uart2_tfr_s cn52xx; | ||
| 1977 | struct cvmx_mio_uart2_tfr_s cn52xxp1; | ||
| 1978 | }; | ||
| 1979 | |||
| 1980 | union cvmx_mio_uart2_thr { | ||
| 1981 | uint64_t u64; | ||
| 1982 | struct cvmx_mio_uart2_thr_s { | ||
| 1983 | uint64_t reserved_8_63:56; | ||
| 1984 | uint64_t thr:8; | ||
| 1985 | } s; | ||
| 1986 | struct cvmx_mio_uart2_thr_s cn52xx; | ||
| 1987 | struct cvmx_mio_uart2_thr_s cn52xxp1; | ||
| 1988 | }; | ||
| 1989 | |||
| 1990 | union cvmx_mio_uart2_usr { | ||
| 1991 | uint64_t u64; | ||
| 1992 | struct cvmx_mio_uart2_usr_s { | ||
| 1993 | uint64_t reserved_5_63:59; | ||
| 1994 | uint64_t rff:1; | ||
| 1995 | uint64_t rfne:1; | ||
| 1996 | uint64_t tfe:1; | ||
| 1997 | uint64_t tfnf:1; | ||
| 1998 | uint64_t busy:1; | ||
| 1999 | } s; | ||
| 2000 | struct cvmx_mio_uart2_usr_s cn52xx; | ||
| 2001 | struct cvmx_mio_uart2_usr_s cn52xxp1; | ||
| 2002 | }; | ||
| 2003 | |||
| 2004 | #endif | ||
diff --git a/arch/mips/include/asm/octeon/cvmx-packet.h b/arch/mips/include/asm/octeon/cvmx-packet.h new file mode 100644 index 000000000000..38aefa1bab9d --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-packet.h | |||
| @@ -0,0 +1,61 @@ | |||
| 1 | /***********************license start*************** | ||
| 2 | * Author: Cavium Networks | ||
| 3 | * | ||
| 4 | * Contact: support@caviumnetworks.com | ||
| 5 | * This file is part of the OCTEON SDK | ||
| 6 | * | ||
| 7 | * Copyright (c) 2003-2008 Cavium Networks | ||
| 8 | * | ||
| 9 | * This file is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License, Version 2, as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | * | ||
| 13 | * This file is distributed in the hope that it will be useful, but | ||
| 14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
| 15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
| 16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
| 17 | * details. | ||
| 18 | * | ||
| 19 | * You should have received a copy of the GNU General Public License | ||
| 20 | * along with this file; if not, write to the Free Software | ||
| 21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 22 | * or visit http://www.gnu.org/licenses/. | ||
| 23 | * | ||
| 24 | * This file may also be available under a different license from Cavium. | ||
| 25 | * Contact Cavium Networks for more information | ||
| 26 | ***********************license end**************************************/ | ||
| 27 | |||
| 28 | /* | ||
| 29 | * Packet buffer defines. | ||
| 30 | */ | ||
| 31 | |||
| 32 | #ifndef __CVMX_PACKET_H__ | ||
| 33 | #define __CVMX_PACKET_H__ | ||
| 34 | |||
| 35 | /** | ||
| 36 | * This structure defines a buffer pointer on Octeon | ||
| 37 | */ | ||
| 38 | union cvmx_buf_ptr { | ||
| 39 | void *ptr; | ||
| 40 | uint64_t u64; | ||
| 41 | struct { | ||
| 42 | /* if set, invert the "free" pick of the overall | ||
| 43 | * packet. HW always sets this bit to 0 on inbound | ||
| 44 | * packet */ | ||
| 45 | uint64_t i:1; | ||
| 46 | |||
| 47 | /* Indicates the amount to back up to get to the | ||
| 48 | * buffer start in cache lines. In most cases this is | ||
| 49 | * less than one complete cache line, so the value is | ||
| 50 | * zero */ | ||
| 51 | uint64_t back:4; | ||
| 52 | /* The pool that the buffer came from / goes to */ | ||
| 53 | uint64_t pool:3; | ||
| 54 | /* The size of the segment pointed to by addr (in bytes) */ | ||
| 55 | uint64_t size:16; | ||
| 56 | /* Pointer to the first byte of the data, NOT buffer */ | ||
| 57 | uint64_t addr:40; | ||
| 58 | } s; | ||
| 59 | }; | ||
| 60 | |||
| 61 | #endif /* __CVMX_PACKET_H__ */ | ||
diff --git a/arch/mips/include/asm/octeon/cvmx-pow-defs.h b/arch/mips/include/asm/octeon/cvmx-pow-defs.h new file mode 100644 index 000000000000..2d82e24be51c --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-pow-defs.h | |||
| @@ -0,0 +1,698 @@ | |||
| 1 | /***********************license start*************** | ||
| 2 | * Author: Cavium Networks | ||
| 3 | * | ||
| 4 | * Contact: support@caviumnetworks.com | ||
| 5 | * This file is part of the OCTEON SDK | ||
| 6 | * | ||
| 7 | * Copyright (c) 2003-2008 Cavium Networks | ||
| 8 | * | ||
| 9 | * This file is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License, Version 2, as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | * | ||
| 13 | * This file is distributed in the hope that it will be useful, but | ||
| 14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
| 15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
| 16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
| 17 | * details. | ||
| 18 | * | ||
| 19 | * You should have received a copy of the GNU General Public License | ||
| 20 | * along with this file; if not, write to the Free Software | ||
| 21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 22 | * or visit http://www.gnu.org/licenses/. | ||
| 23 | * | ||
| 24 | * This file may also be available under a different license from Cavium. | ||
| 25 | * Contact Cavium Networks for more information | ||
| 26 | ***********************license end**************************************/ | ||
| 27 | |||
| 28 | #ifndef __CVMX_POW_DEFS_H__ | ||
| 29 | #define __CVMX_POW_DEFS_H__ | ||
| 30 | |||
| 31 | #define CVMX_POW_BIST_STAT \ | ||
| 32 | CVMX_ADD_IO_SEG(0x00016700000003F8ull) | ||
| 33 | #define CVMX_POW_DS_PC \ | ||
| 34 | CVMX_ADD_IO_SEG(0x0001670000000398ull) | ||
| 35 | #define CVMX_POW_ECC_ERR \ | ||
| 36 | CVMX_ADD_IO_SEG(0x0001670000000218ull) | ||
| 37 | #define CVMX_POW_INT_CTL \ | ||
| 38 | CVMX_ADD_IO_SEG(0x0001670000000220ull) | ||
| 39 | #define CVMX_POW_IQ_CNTX(offset) \ | ||
| 40 | CVMX_ADD_IO_SEG(0x0001670000000340ull + (((offset) & 7) * 8)) | ||
| 41 | #define CVMX_POW_IQ_COM_CNT \ | ||
| 42 | CVMX_ADD_IO_SEG(0x0001670000000388ull) | ||
| 43 | #define CVMX_POW_IQ_INT \ | ||
| 44 | CVMX_ADD_IO_SEG(0x0001670000000238ull) | ||
| 45 | #define CVMX_POW_IQ_INT_EN \ | ||
| 46 | CVMX_ADD_IO_SEG(0x0001670000000240ull) | ||
| 47 | #define CVMX_POW_IQ_THRX(offset) \ | ||
| 48 | CVMX_ADD_IO_SEG(0x00016700000003A0ull + (((offset) & 7) * 8)) | ||
| 49 | #define CVMX_POW_NOS_CNT \ | ||
| 50 | CVMX_ADD_IO_SEG(0x0001670000000228ull) | ||
| 51 | #define CVMX_POW_NW_TIM \ | ||
| 52 | CVMX_ADD_IO_SEG(0x0001670000000210ull) | ||
| 53 | #define CVMX_POW_PF_RST_MSK \ | ||
| 54 | CVMX_ADD_IO_SEG(0x0001670000000230ull) | ||
| 55 | #define CVMX_POW_PP_GRP_MSKX(offset) \ | ||
| 56 | CVMX_ADD_IO_SEG(0x0001670000000000ull + (((offset) & 15) * 8)) | ||
| 57 | #define CVMX_POW_QOS_RNDX(offset) \ | ||
| 58 | CVMX_ADD_IO_SEG(0x00016700000001C0ull + (((offset) & 7) * 8)) | ||
| 59 | #define CVMX_POW_QOS_THRX(offset) \ | ||
| 60 | CVMX_ADD_IO_SEG(0x0001670000000180ull + (((offset) & 7) * 8)) | ||
| 61 | #define CVMX_POW_TS_PC \ | ||
| 62 | CVMX_ADD_IO_SEG(0x0001670000000390ull) | ||
| 63 | #define CVMX_POW_WA_COM_PC \ | ||
| 64 | CVMX_ADD_IO_SEG(0x0001670000000380ull) | ||
| 65 | #define CVMX_POW_WA_PCX(offset) \ | ||
| 66 | CVMX_ADD_IO_SEG(0x0001670000000300ull + (((offset) & 7) * 8)) | ||
| 67 | #define CVMX_POW_WQ_INT \ | ||
| 68 | CVMX_ADD_IO_SEG(0x0001670000000200ull) | ||
| 69 | #define CVMX_POW_WQ_INT_CNTX(offset) \ | ||
| 70 | CVMX_ADD_IO_SEG(0x0001670000000100ull + (((offset) & 15) * 8)) | ||
| 71 | #define CVMX_POW_WQ_INT_PC \ | ||
| 72 | CVMX_ADD_IO_SEG(0x0001670000000208ull) | ||
| 73 | #define CVMX_POW_WQ_INT_THRX(offset) \ | ||
| 74 | CVMX_ADD_IO_SEG(0x0001670000000080ull + (((offset) & 15) * 8)) | ||
| 75 | #define CVMX_POW_WS_PCX(offset) \ | ||
| 76 | CVMX_ADD_IO_SEG(0x0001670000000280ull + (((offset) & 15) * 8)) | ||
| 77 | |||
| 78 | union cvmx_pow_bist_stat { | ||
| 79 | uint64_t u64; | ||
| 80 | struct cvmx_pow_bist_stat_s { | ||
| 81 | uint64_t reserved_32_63:32; | ||
| 82 | uint64_t pp:16; | ||
| 83 | uint64_t reserved_0_15:16; | ||
| 84 | } s; | ||
| 85 | struct cvmx_pow_bist_stat_cn30xx { | ||
| 86 | uint64_t reserved_17_63:47; | ||
| 87 | uint64_t pp:1; | ||
| 88 | uint64_t reserved_9_15:7; | ||
| 89 | uint64_t cam:1; | ||
| 90 | uint64_t nbt1:1; | ||
| 91 | uint64_t nbt0:1; | ||
| 92 | uint64_t index:1; | ||
| 93 | uint64_t fidx:1; | ||
| 94 | uint64_t nbr1:1; | ||
| 95 | uint64_t nbr0:1; | ||
| 96 | uint64_t pend:1; | ||
| 97 | uint64_t adr:1; | ||
| 98 | } cn30xx; | ||
| 99 | struct cvmx_pow_bist_stat_cn31xx { | ||
| 100 | uint64_t reserved_18_63:46; | ||
| 101 | uint64_t pp:2; | ||
| 102 | uint64_t reserved_9_15:7; | ||
| 103 | uint64_t cam:1; | ||
| 104 | uint64_t nbt1:1; | ||
| 105 | uint64_t nbt0:1; | ||
| 106 | uint64_t index:1; | ||
| 107 | uint64_t fidx:1; | ||
| 108 | uint64_t nbr1:1; | ||
| 109 | uint64_t nbr0:1; | ||
| 110 | uint64_t pend:1; | ||
| 111 | uint64_t adr:1; | ||
| 112 | } cn31xx; | ||
| 113 | struct cvmx_pow_bist_stat_cn38xx { | ||
| 114 | uint64_t reserved_32_63:32; | ||
| 115 | uint64_t pp:16; | ||
| 116 | uint64_t reserved_10_15:6; | ||
| 117 | uint64_t cam:1; | ||
| 118 | uint64_t nbt:1; | ||
| 119 | uint64_t index:1; | ||
| 120 | uint64_t fidx:1; | ||
| 121 | uint64_t nbr1:1; | ||
| 122 | uint64_t nbr0:1; | ||
| 123 | uint64_t pend1:1; | ||
| 124 | uint64_t pend0:1; | ||
| 125 | uint64_t adr1:1; | ||
| 126 | uint64_t adr0:1; | ||
| 127 | } cn38xx; | ||
| 128 | struct cvmx_pow_bist_stat_cn38xx cn38xxp2; | ||
| 129 | struct cvmx_pow_bist_stat_cn31xx cn50xx; | ||
| 130 | struct cvmx_pow_bist_stat_cn52xx { | ||
| 131 | uint64_t reserved_20_63:44; | ||
| 132 | uint64_t pp:4; | ||
| 133 | uint64_t reserved_9_15:7; | ||
| 134 | uint64_t cam:1; | ||
| 135 | uint64_t nbt1:1; | ||
| 136 | uint64_t nbt0:1; | ||
| 137 | uint64_t index:1; | ||
| 138 | uint64_t fidx:1; | ||
| 139 | uint64_t nbr1:1; | ||
| 140 | uint64_t nbr0:1; | ||
| 141 | uint64_t pend:1; | ||
| 142 | uint64_t adr:1; | ||
| 143 | } cn52xx; | ||
| 144 | struct cvmx_pow_bist_stat_cn52xx cn52xxp1; | ||
| 145 | struct cvmx_pow_bist_stat_cn56xx { | ||
| 146 | uint64_t reserved_28_63:36; | ||
| 147 | uint64_t pp:12; | ||
| 148 | uint64_t reserved_10_15:6; | ||
| 149 | uint64_t cam:1; | ||
| 150 | uint64_t nbt:1; | ||
| 151 | uint64_t index:1; | ||
| 152 | uint64_t fidx:1; | ||
| 153 | uint64_t nbr1:1; | ||
| 154 | uint64_t nbr0:1; | ||
| 155 | uint64_t pend1:1; | ||
| 156 | uint64_t pend0:1; | ||
| 157 | uint64_t adr1:1; | ||
| 158 | uint64_t adr0:1; | ||
| 159 | } cn56xx; | ||
| 160 | struct cvmx_pow_bist_stat_cn56xx cn56xxp1; | ||
| 161 | struct cvmx_pow_bist_stat_cn38xx cn58xx; | ||
| 162 | struct cvmx_pow_bist_stat_cn38xx cn58xxp1; | ||
| 163 | }; | ||
| 164 | |||
| 165 | union cvmx_pow_ds_pc { | ||
| 166 | uint64_t u64; | ||
| 167 | struct cvmx_pow_ds_pc_s { | ||
| 168 | uint64_t reserved_32_63:32; | ||
| 169 | uint64_t ds_pc:32; | ||
| 170 | } s; | ||
| 171 | struct cvmx_pow_ds_pc_s cn30xx; | ||
| 172 | struct cvmx_pow_ds_pc_s cn31xx; | ||
| 173 | struct cvmx_pow_ds_pc_s cn38xx; | ||
| 174 | struct cvmx_pow_ds_pc_s cn38xxp2; | ||
| 175 | struct cvmx_pow_ds_pc_s cn50xx; | ||
| 176 | struct cvmx_pow_ds_pc_s cn52xx; | ||
| 177 | struct cvmx_pow_ds_pc_s cn52xxp1; | ||
| 178 | struct cvmx_pow_ds_pc_s cn56xx; | ||
| 179 | struct cvmx_pow_ds_pc_s cn56xxp1; | ||
| 180 | struct cvmx_pow_ds_pc_s cn58xx; | ||
| 181 | struct cvmx_pow_ds_pc_s cn58xxp1; | ||
| 182 | }; | ||
| 183 | |||
| 184 | union cvmx_pow_ecc_err { | ||
| 185 | uint64_t u64; | ||
| 186 | struct cvmx_pow_ecc_err_s { | ||
| 187 | uint64_t reserved_45_63:19; | ||
| 188 | uint64_t iop_ie:13; | ||
| 189 | uint64_t reserved_29_31:3; | ||
| 190 | uint64_t iop:13; | ||
| 191 | uint64_t reserved_14_15:2; | ||
| 192 | uint64_t rpe_ie:1; | ||
| 193 | uint64_t rpe:1; | ||
| 194 | uint64_t reserved_9_11:3; | ||
| 195 | uint64_t syn:5; | ||
| 196 | uint64_t dbe_ie:1; | ||
| 197 | uint64_t sbe_ie:1; | ||
| 198 | uint64_t dbe:1; | ||
| 199 | uint64_t sbe:1; | ||
| 200 | } s; | ||
| 201 | struct cvmx_pow_ecc_err_s cn30xx; | ||
| 202 | struct cvmx_pow_ecc_err_cn31xx { | ||
| 203 | uint64_t reserved_14_63:50; | ||
| 204 | uint64_t rpe_ie:1; | ||
| 205 | uint64_t rpe:1; | ||
| 206 | uint64_t reserved_9_11:3; | ||
| 207 | uint64_t syn:5; | ||
| 208 | uint64_t dbe_ie:1; | ||
| 209 | uint64_t sbe_ie:1; | ||
| 210 | uint64_t dbe:1; | ||
| 211 | uint64_t sbe:1; | ||
| 212 | } cn31xx; | ||
| 213 | struct cvmx_pow_ecc_err_s cn38xx; | ||
| 214 | struct cvmx_pow_ecc_err_cn31xx cn38xxp2; | ||
| 215 | struct cvmx_pow_ecc_err_s cn50xx; | ||
| 216 | struct cvmx_pow_ecc_err_s cn52xx; | ||
| 217 | struct cvmx_pow_ecc_err_s cn52xxp1; | ||
| 218 | struct cvmx_pow_ecc_err_s cn56xx; | ||
| 219 | struct cvmx_pow_ecc_err_s cn56xxp1; | ||
| 220 | struct cvmx_pow_ecc_err_s cn58xx; | ||
| 221 | struct cvmx_pow_ecc_err_s cn58xxp1; | ||
| 222 | }; | ||
| 223 | |||
| 224 | union cvmx_pow_int_ctl { | ||
| 225 | uint64_t u64; | ||
| 226 | struct cvmx_pow_int_ctl_s { | ||
| 227 | uint64_t reserved_6_63:58; | ||
| 228 | uint64_t pfr_dis:1; | ||
| 229 | uint64_t nbr_thr:5; | ||
| 230 | } s; | ||
| 231 | struct cvmx_pow_int_ctl_s cn30xx; | ||
| 232 | struct cvmx_pow_int_ctl_s cn31xx; | ||
| 233 | struct cvmx_pow_int_ctl_s cn38xx; | ||
| 234 | struct cvmx_pow_int_ctl_s cn38xxp2; | ||
| 235 | struct cvmx_pow_int_ctl_s cn50xx; | ||
| 236 | struct cvmx_pow_int_ctl_s cn52xx; | ||
| 237 | struct cvmx_pow_int_ctl_s cn52xxp1; | ||
| 238 | struct cvmx_pow_int_ctl_s cn56xx; | ||
| 239 | struct cvmx_pow_int_ctl_s cn56xxp1; | ||
| 240 | struct cvmx_pow_int_ctl_s cn58xx; | ||
| 241 | struct cvmx_pow_int_ctl_s cn58xxp1; | ||
| 242 | }; | ||
| 243 | |||
| 244 | union cvmx_pow_iq_cntx { | ||
| 245 | uint64_t u64; | ||
| 246 | struct cvmx_pow_iq_cntx_s { | ||
| 247 | uint64_t reserved_32_63:32; | ||
| 248 | uint64_t iq_cnt:32; | ||
| 249 | } s; | ||
| 250 | struct cvmx_pow_iq_cntx_s cn30xx; | ||
| 251 | struct cvmx_pow_iq_cntx_s cn31xx; | ||
| 252 | struct cvmx_pow_iq_cntx_s cn38xx; | ||
| 253 | struct cvmx_pow_iq_cntx_s cn38xxp2; | ||
| 254 | struct cvmx_pow_iq_cntx_s cn50xx; | ||
| 255 | struct cvmx_pow_iq_cntx_s cn52xx; | ||
| 256 | struct cvmx_pow_iq_cntx_s cn52xxp1; | ||
| 257 | struct cvmx_pow_iq_cntx_s cn56xx; | ||
| 258 | struct cvmx_pow_iq_cntx_s cn56xxp1; | ||
| 259 | struct cvmx_pow_iq_cntx_s cn58xx; | ||
| 260 | struct cvmx_pow_iq_cntx_s cn58xxp1; | ||
| 261 | }; | ||
| 262 | |||
| 263 | union cvmx_pow_iq_com_cnt { | ||
| 264 | uint64_t u64; | ||
| 265 | struct cvmx_pow_iq_com_cnt_s { | ||
| 266 | uint64_t reserved_32_63:32; | ||
| 267 | uint64_t iq_cnt:32; | ||
| 268 | } s; | ||
| 269 | struct cvmx_pow_iq_com_cnt_s cn30xx; | ||
| 270 | struct cvmx_pow_iq_com_cnt_s cn31xx; | ||
| 271 | struct cvmx_pow_iq_com_cnt_s cn38xx; | ||
| 272 | struct cvmx_pow_iq_com_cnt_s cn38xxp2; | ||
| 273 | struct cvmx_pow_iq_com_cnt_s cn50xx; | ||
| 274 | struct cvmx_pow_iq_com_cnt_s cn52xx; | ||
| 275 | struct cvmx_pow_iq_com_cnt_s cn52xxp1; | ||
| 276 | struct cvmx_pow_iq_com_cnt_s cn56xx; | ||
| 277 | struct cvmx_pow_iq_com_cnt_s cn56xxp1; | ||
| 278 | struct cvmx_pow_iq_com_cnt_s cn58xx; | ||
| 279 | struct cvmx_pow_iq_com_cnt_s cn58xxp1; | ||
| 280 | }; | ||
| 281 | |||
| 282 | union cvmx_pow_iq_int { | ||
| 283 | uint64_t u64; | ||
| 284 | struct cvmx_pow_iq_int_s { | ||
| 285 | uint64_t reserved_8_63:56; | ||
| 286 | uint64_t iq_int:8; | ||
| 287 | } s; | ||
| 288 | struct cvmx_pow_iq_int_s cn52xx; | ||
| 289 | struct cvmx_pow_iq_int_s cn52xxp1; | ||
| 290 | struct cvmx_pow_iq_int_s cn56xx; | ||
| 291 | struct cvmx_pow_iq_int_s cn56xxp1; | ||
| 292 | }; | ||
| 293 | |||
| 294 | union cvmx_pow_iq_int_en { | ||
| 295 | uint64_t u64; | ||
| 296 | struct cvmx_pow_iq_int_en_s { | ||
| 297 | uint64_t reserved_8_63:56; | ||
| 298 | uint64_t int_en:8; | ||
| 299 | } s; | ||
| 300 | struct cvmx_pow_iq_int_en_s cn52xx; | ||
| 301 | struct cvmx_pow_iq_int_en_s cn52xxp1; | ||
| 302 | struct cvmx_pow_iq_int_en_s cn56xx; | ||
| 303 | struct cvmx_pow_iq_int_en_s cn56xxp1; | ||
| 304 | }; | ||
| 305 | |||
| 306 | union cvmx_pow_iq_thrx { | ||
| 307 | uint64_t u64; | ||
| 308 | struct cvmx_pow_iq_thrx_s { | ||
| 309 | uint64_t reserved_32_63:32; | ||
| 310 | uint64_t iq_thr:32; | ||
| 311 | } s; | ||
| 312 | struct cvmx_pow_iq_thrx_s cn52xx; | ||
| 313 | struct cvmx_pow_iq_thrx_s cn52xxp1; | ||
| 314 | struct cvmx_pow_iq_thrx_s cn56xx; | ||
| 315 | struct cvmx_pow_iq_thrx_s cn56xxp1; | ||
| 316 | }; | ||
| 317 | |||
| 318 | union cvmx_pow_nos_cnt { | ||
| 319 | uint64_t u64; | ||
| 320 | struct cvmx_pow_nos_cnt_s { | ||
| 321 | uint64_t reserved_12_63:52; | ||
| 322 | uint64_t nos_cnt:12; | ||
| 323 | } s; | ||
| 324 | struct cvmx_pow_nos_cnt_cn30xx { | ||
| 325 | uint64_t reserved_7_63:57; | ||
| 326 | uint64_t nos_cnt:7; | ||
| 327 | } cn30xx; | ||
| 328 | struct cvmx_pow_nos_cnt_cn31xx { | ||
| 329 | uint64_t reserved_9_63:55; | ||
| 330 | uint64_t nos_cnt:9; | ||
| 331 | } cn31xx; | ||
| 332 | struct cvmx_pow_nos_cnt_s cn38xx; | ||
| 333 | struct cvmx_pow_nos_cnt_s cn38xxp2; | ||
| 334 | struct cvmx_pow_nos_cnt_cn31xx cn50xx; | ||
| 335 | struct cvmx_pow_nos_cnt_cn52xx { | ||
| 336 | uint64_t reserved_10_63:54; | ||
| 337 | uint64_t nos_cnt:10; | ||
| 338 | } cn52xx; | ||
| 339 | struct cvmx_pow_nos_cnt_cn52xx cn52xxp1; | ||
| 340 | struct cvmx_pow_nos_cnt_s cn56xx; | ||
| 341 | struct cvmx_pow_nos_cnt_s cn56xxp1; | ||
| 342 | struct cvmx_pow_nos_cnt_s cn58xx; | ||
| 343 | struct cvmx_pow_nos_cnt_s cn58xxp1; | ||
| 344 | }; | ||
| 345 | |||
| 346 | union cvmx_pow_nw_tim { | ||
| 347 | uint64_t u64; | ||
| 348 | struct cvmx_pow_nw_tim_s { | ||
| 349 | uint64_t reserved_10_63:54; | ||
| 350 | uint64_t nw_tim:10; | ||
| 351 | } s; | ||
| 352 | struct cvmx_pow_nw_tim_s cn30xx; | ||
| 353 | struct cvmx_pow_nw_tim_s cn31xx; | ||
| 354 | struct cvmx_pow_nw_tim_s cn38xx; | ||
| 355 | struct cvmx_pow_nw_tim_s cn38xxp2; | ||
| 356 | struct cvmx_pow_nw_tim_s cn50xx; | ||
| 357 | struct cvmx_pow_nw_tim_s cn52xx; | ||
| 358 | struct cvmx_pow_nw_tim_s cn52xxp1; | ||
| 359 | struct cvmx_pow_nw_tim_s cn56xx; | ||
| 360 | struct cvmx_pow_nw_tim_s cn56xxp1; | ||
| 361 | struct cvmx_pow_nw_tim_s cn58xx; | ||
| 362 | struct cvmx_pow_nw_tim_s cn58xxp1; | ||
| 363 | }; | ||
| 364 | |||
| 365 | union cvmx_pow_pf_rst_msk { | ||
| 366 | uint64_t u64; | ||
| 367 | struct cvmx_pow_pf_rst_msk_s { | ||
| 368 | uint64_t reserved_8_63:56; | ||
| 369 | uint64_t rst_msk:8; | ||
| 370 | } s; | ||
| 371 | struct cvmx_pow_pf_rst_msk_s cn50xx; | ||
| 372 | struct cvmx_pow_pf_rst_msk_s cn52xx; | ||
| 373 | struct cvmx_pow_pf_rst_msk_s cn52xxp1; | ||
| 374 | struct cvmx_pow_pf_rst_msk_s cn56xx; | ||
| 375 | struct cvmx_pow_pf_rst_msk_s cn56xxp1; | ||
| 376 | struct cvmx_pow_pf_rst_msk_s cn58xx; | ||
| 377 | struct cvmx_pow_pf_rst_msk_s cn58xxp1; | ||
| 378 | }; | ||
| 379 | |||
| 380 | union cvmx_pow_pp_grp_mskx { | ||
| 381 | uint64_t u64; | ||
| 382 | struct cvmx_pow_pp_grp_mskx_s { | ||
| 383 | uint64_t reserved_48_63:16; | ||
| 384 | uint64_t qos7_pri:4; | ||
| 385 | uint64_t qos6_pri:4; | ||
| 386 | uint64_t qos5_pri:4; | ||
| 387 | uint64_t qos4_pri:4; | ||
| 388 | uint64_t qos3_pri:4; | ||
| 389 | uint64_t qos2_pri:4; | ||
| 390 | uint64_t qos1_pri:4; | ||
| 391 | uint64_t qos0_pri:4; | ||
| 392 | uint64_t grp_msk:16; | ||
| 393 | } s; | ||
| 394 | struct cvmx_pow_pp_grp_mskx_cn30xx { | ||
| 395 | uint64_t reserved_16_63:48; | ||
| 396 | uint64_t grp_msk:16; | ||
| 397 | } cn30xx; | ||
| 398 | struct cvmx_pow_pp_grp_mskx_cn30xx cn31xx; | ||
| 399 | struct cvmx_pow_pp_grp_mskx_cn30xx cn38xx; | ||
| 400 | struct cvmx_pow_pp_grp_mskx_cn30xx cn38xxp2; | ||
| 401 | struct cvmx_pow_pp_grp_mskx_s cn50xx; | ||
| 402 | struct cvmx_pow_pp_grp_mskx_s cn52xx; | ||
| 403 | struct cvmx_pow_pp_grp_mskx_s cn52xxp1; | ||
| 404 | struct cvmx_pow_pp_grp_mskx_s cn56xx; | ||
| 405 | struct cvmx_pow_pp_grp_mskx_s cn56xxp1; | ||
| 406 | struct cvmx_pow_pp_grp_mskx_s cn58xx; | ||
| 407 | struct cvmx_pow_pp_grp_mskx_s cn58xxp1; | ||
| 408 | }; | ||
| 409 | |||
| 410 | union cvmx_pow_qos_rndx { | ||
| 411 | uint64_t u64; | ||
| 412 | struct cvmx_pow_qos_rndx_s { | ||
| 413 | uint64_t reserved_32_63:32; | ||
| 414 | uint64_t rnd_p3:8; | ||
| 415 | uint64_t rnd_p2:8; | ||
| 416 | uint64_t rnd_p1:8; | ||
| 417 | uint64_t rnd:8; | ||
| 418 | } s; | ||
| 419 | struct cvmx_pow_qos_rndx_s cn30xx; | ||
| 420 | struct cvmx_pow_qos_rndx_s cn31xx; | ||
| 421 | struct cvmx_pow_qos_rndx_s cn38xx; | ||
| 422 | struct cvmx_pow_qos_rndx_s cn38xxp2; | ||
| 423 | struct cvmx_pow_qos_rndx_s cn50xx; | ||
| 424 | struct cvmx_pow_qos_rndx_s cn52xx; | ||
| 425 | struct cvmx_pow_qos_rndx_s cn52xxp1; | ||
| 426 | struct cvmx_pow_qos_rndx_s cn56xx; | ||
| 427 | struct cvmx_pow_qos_rndx_s cn56xxp1; | ||
| 428 | struct cvmx_pow_qos_rndx_s cn58xx; | ||
| 429 | struct cvmx_pow_qos_rndx_s cn58xxp1; | ||
| 430 | }; | ||
| 431 | |||
| 432 | union cvmx_pow_qos_thrx { | ||
| 433 | uint64_t u64; | ||
| 434 | struct cvmx_pow_qos_thrx_s { | ||
| 435 | uint64_t reserved_60_63:4; | ||
| 436 | uint64_t des_cnt:12; | ||
| 437 | uint64_t buf_cnt:12; | ||
| 438 | uint64_t free_cnt:12; | ||
| 439 | uint64_t reserved_23_23:1; | ||
| 440 | uint64_t max_thr:11; | ||
| 441 | uint64_t reserved_11_11:1; | ||
| 442 | uint64_t min_thr:11; | ||
| 443 | } s; | ||
| 444 | struct cvmx_pow_qos_thrx_cn30xx { | ||
| 445 | uint64_t reserved_55_63:9; | ||
| 446 | uint64_t des_cnt:7; | ||
| 447 | uint64_t reserved_43_47:5; | ||
| 448 | uint64_t buf_cnt:7; | ||
| 449 | uint64_t reserved_31_35:5; | ||
| 450 | uint64_t free_cnt:7; | ||
| 451 | uint64_t reserved_18_23:6; | ||
| 452 | uint64_t max_thr:6; | ||
| 453 | uint64_t reserved_6_11:6; | ||
| 454 | uint64_t min_thr:6; | ||
| 455 | } cn30xx; | ||
| 456 | struct cvmx_pow_qos_thrx_cn31xx { | ||
| 457 | uint64_t reserved_57_63:7; | ||
| 458 | uint64_t des_cnt:9; | ||
| 459 | uint64_t reserved_45_47:3; | ||
| 460 | uint64_t buf_cnt:9; | ||
| 461 | uint64_t reserved_33_35:3; | ||
| 462 | uint64_t free_cnt:9; | ||
| 463 | uint64_t reserved_20_23:4; | ||
| 464 | uint64_t max_thr:8; | ||
| 465 | uint64_t reserved_8_11:4; | ||
| 466 | uint64_t min_thr:8; | ||
| 467 | } cn31xx; | ||
| 468 | struct cvmx_pow_qos_thrx_s cn38xx; | ||
| 469 | struct cvmx_pow_qos_thrx_s cn38xxp2; | ||
| 470 | struct cvmx_pow_qos_thrx_cn31xx cn50xx; | ||
| 471 | struct cvmx_pow_qos_thrx_cn52xx { | ||
| 472 | uint64_t reserved_58_63:6; | ||
| 473 | uint64_t des_cnt:10; | ||
| 474 | uint64_t reserved_46_47:2; | ||
| 475 | uint64_t buf_cnt:10; | ||
| 476 | uint64_t reserved_34_35:2; | ||
| 477 | uint64_t free_cnt:10; | ||
| 478 | uint64_t reserved_21_23:3; | ||
| 479 | uint64_t max_thr:9; | ||
| 480 | uint64_t reserved_9_11:3; | ||
| 481 | uint64_t min_thr:9; | ||
| 482 | } cn52xx; | ||
| 483 | struct cvmx_pow_qos_thrx_cn52xx cn52xxp1; | ||
| 484 | struct cvmx_pow_qos_thrx_s cn56xx; | ||
| 485 | struct cvmx_pow_qos_thrx_s cn56xxp1; | ||
| 486 | struct cvmx_pow_qos_thrx_s cn58xx; | ||
| 487 | struct cvmx_pow_qos_thrx_s cn58xxp1; | ||
| 488 | }; | ||
| 489 | |||
| 490 | union cvmx_pow_ts_pc { | ||
| 491 | uint64_t u64; | ||
| 492 | struct cvmx_pow_ts_pc_s { | ||
| 493 | uint64_t reserved_32_63:32; | ||
| 494 | uint64_t ts_pc:32; | ||
| 495 | } s; | ||
| 496 | struct cvmx_pow_ts_pc_s cn30xx; | ||
| 497 | struct cvmx_pow_ts_pc_s cn31xx; | ||
| 498 | struct cvmx_pow_ts_pc_s cn38xx; | ||
| 499 | struct cvmx_pow_ts_pc_s cn38xxp2; | ||
| 500 | struct cvmx_pow_ts_pc_s cn50xx; | ||
| 501 | struct cvmx_pow_ts_pc_s cn52xx; | ||
| 502 | struct cvmx_pow_ts_pc_s cn52xxp1; | ||
| 503 | struct cvmx_pow_ts_pc_s cn56xx; | ||
| 504 | struct cvmx_pow_ts_pc_s cn56xxp1; | ||
| 505 | struct cvmx_pow_ts_pc_s cn58xx; | ||
| 506 | struct cvmx_pow_ts_pc_s cn58xxp1; | ||
| 507 | }; | ||
| 508 | |||
| 509 | union cvmx_pow_wa_com_pc { | ||
| 510 | uint64_t u64; | ||
| 511 | struct cvmx_pow_wa_com_pc_s { | ||
| 512 | uint64_t reserved_32_63:32; | ||
| 513 | uint64_t wa_pc:32; | ||
| 514 | } s; | ||
| 515 | struct cvmx_pow_wa_com_pc_s cn30xx; | ||
| 516 | struct cvmx_pow_wa_com_pc_s cn31xx; | ||
| 517 | struct cvmx_pow_wa_com_pc_s cn38xx; | ||
| 518 | struct cvmx_pow_wa_com_pc_s cn38xxp2; | ||
| 519 | struct cvmx_pow_wa_com_pc_s cn50xx; | ||
| 520 | struct cvmx_pow_wa_com_pc_s cn52xx; | ||
| 521 | struct cvmx_pow_wa_com_pc_s cn52xxp1; | ||
| 522 | struct cvmx_pow_wa_com_pc_s cn56xx; | ||
| 523 | struct cvmx_pow_wa_com_pc_s cn56xxp1; | ||
| 524 | struct cvmx_pow_wa_com_pc_s cn58xx; | ||
| 525 | struct cvmx_pow_wa_com_pc_s cn58xxp1; | ||
| 526 | }; | ||
| 527 | |||
| 528 | union cvmx_pow_wa_pcx { | ||
| 529 | uint64_t u64; | ||
| 530 | struct cvmx_pow_wa_pcx_s { | ||
| 531 | uint64_t reserved_32_63:32; | ||
| 532 | uint64_t wa_pc:32; | ||
| 533 | } s; | ||
| 534 | struct cvmx_pow_wa_pcx_s cn30xx; | ||
| 535 | struct cvmx_pow_wa_pcx_s cn31xx; | ||
| 536 | struct cvmx_pow_wa_pcx_s cn38xx; | ||
| 537 | struct cvmx_pow_wa_pcx_s cn38xxp2; | ||
| 538 | struct cvmx_pow_wa_pcx_s cn50xx; | ||
| 539 | struct cvmx_pow_wa_pcx_s cn52xx; | ||
| 540 | struct cvmx_pow_wa_pcx_s cn52xxp1; | ||
| 541 | struct cvmx_pow_wa_pcx_s cn56xx; | ||
| 542 | struct cvmx_pow_wa_pcx_s cn56xxp1; | ||
| 543 | struct cvmx_pow_wa_pcx_s cn58xx; | ||
| 544 | struct cvmx_pow_wa_pcx_s cn58xxp1; | ||
| 545 | }; | ||
| 546 | |||
| 547 | union cvmx_pow_wq_int { | ||
| 548 | uint64_t u64; | ||
| 549 | struct cvmx_pow_wq_int_s { | ||
| 550 | uint64_t reserved_32_63:32; | ||
| 551 | uint64_t iq_dis:16; | ||
| 552 | uint64_t wq_int:16; | ||
| 553 | } s; | ||
| 554 | struct cvmx_pow_wq_int_s cn30xx; | ||
| 555 | struct cvmx_pow_wq_int_s cn31xx; | ||
| 556 | struct cvmx_pow_wq_int_s cn38xx; | ||
| 557 | struct cvmx_pow_wq_int_s cn38xxp2; | ||
| 558 | struct cvmx_pow_wq_int_s cn50xx; | ||
| 559 | struct cvmx_pow_wq_int_s cn52xx; | ||
| 560 | struct cvmx_pow_wq_int_s cn52xxp1; | ||
| 561 | struct cvmx_pow_wq_int_s cn56xx; | ||
| 562 | struct cvmx_pow_wq_int_s cn56xxp1; | ||
| 563 | struct cvmx_pow_wq_int_s cn58xx; | ||
| 564 | struct cvmx_pow_wq_int_s cn58xxp1; | ||
| 565 | }; | ||
| 566 | |||
| 567 | union cvmx_pow_wq_int_cntx { | ||
| 568 | uint64_t u64; | ||
| 569 | struct cvmx_pow_wq_int_cntx_s { | ||
| 570 | uint64_t reserved_28_63:36; | ||
| 571 | uint64_t tc_cnt:4; | ||
| 572 | uint64_t ds_cnt:12; | ||
| 573 | uint64_t iq_cnt:12; | ||
| 574 | } s; | ||
| 575 | struct cvmx_pow_wq_int_cntx_cn30xx { | ||
| 576 | uint64_t reserved_28_63:36; | ||
| 577 | uint64_t tc_cnt:4; | ||
| 578 | uint64_t reserved_19_23:5; | ||
| 579 | uint64_t ds_cnt:7; | ||
| 580 | uint64_t reserved_7_11:5; | ||
| 581 | uint64_t iq_cnt:7; | ||
| 582 | } cn30xx; | ||
| 583 | struct cvmx_pow_wq_int_cntx_cn31xx { | ||
| 584 | uint64_t reserved_28_63:36; | ||
| 585 | uint64_t tc_cnt:4; | ||
| 586 | uint64_t reserved_21_23:3; | ||
| 587 | uint64_t ds_cnt:9; | ||
| 588 | uint64_t reserved_9_11:3; | ||
| 589 | uint64_t iq_cnt:9; | ||
| 590 | } cn31xx; | ||
| 591 | struct cvmx_pow_wq_int_cntx_s cn38xx; | ||
| 592 | struct cvmx_pow_wq_int_cntx_s cn38xxp2; | ||
| 593 | struct cvmx_pow_wq_int_cntx_cn31xx cn50xx; | ||
| 594 | struct cvmx_pow_wq_int_cntx_cn52xx { | ||
| 595 | uint64_t reserved_28_63:36; | ||
| 596 | uint64_t tc_cnt:4; | ||
| 597 | uint64_t reserved_22_23:2; | ||
| 598 | uint64_t ds_cnt:10; | ||
| 599 | uint64_t reserved_10_11:2; | ||
| 600 | uint64_t iq_cnt:10; | ||
| 601 | } cn52xx; | ||
| 602 | struct cvmx_pow_wq_int_cntx_cn52xx cn52xxp1; | ||
| 603 | struct cvmx_pow_wq_int_cntx_s cn56xx; | ||
| 604 | struct cvmx_pow_wq_int_cntx_s cn56xxp1; | ||
| 605 | struct cvmx_pow_wq_int_cntx_s cn58xx; | ||
| 606 | struct cvmx_pow_wq_int_cntx_s cn58xxp1; | ||
| 607 | }; | ||
| 608 | |||
| 609 | union cvmx_pow_wq_int_pc { | ||
| 610 | uint64_t u64; | ||
| 611 | struct cvmx_pow_wq_int_pc_s { | ||
| 612 | uint64_t reserved_60_63:4; | ||
| 613 | uint64_t pc:28; | ||
| 614 | uint64_t reserved_28_31:4; | ||
| 615 | uint64_t pc_thr:20; | ||
| 616 | uint64_t reserved_0_7:8; | ||
| 617 | } s; | ||
| 618 | struct cvmx_pow_wq_int_pc_s cn30xx; | ||
| 619 | struct cvmx_pow_wq_int_pc_s cn31xx; | ||
| 620 | struct cvmx_pow_wq_int_pc_s cn38xx; | ||
| 621 | struct cvmx_pow_wq_int_pc_s cn38xxp2; | ||
| 622 | struct cvmx_pow_wq_int_pc_s cn50xx; | ||
| 623 | struct cvmx_pow_wq_int_pc_s cn52xx; | ||
| 624 | struct cvmx_pow_wq_int_pc_s cn52xxp1; | ||
| 625 | struct cvmx_pow_wq_int_pc_s cn56xx; | ||
| 626 | struct cvmx_pow_wq_int_pc_s cn56xxp1; | ||
| 627 | struct cvmx_pow_wq_int_pc_s cn58xx; | ||
| 628 | struct cvmx_pow_wq_int_pc_s cn58xxp1; | ||
| 629 | }; | ||
| 630 | |||
| 631 | union cvmx_pow_wq_int_thrx { | ||
| 632 | uint64_t u64; | ||
| 633 | struct cvmx_pow_wq_int_thrx_s { | ||
| 634 | uint64_t reserved_29_63:35; | ||
| 635 | uint64_t tc_en:1; | ||
| 636 | uint64_t tc_thr:4; | ||
| 637 | uint64_t reserved_23_23:1; | ||
| 638 | uint64_t ds_thr:11; | ||
| 639 | uint64_t reserved_11_11:1; | ||
| 640 | uint64_t iq_thr:11; | ||
| 641 | } s; | ||
| 642 | struct cvmx_pow_wq_int_thrx_cn30xx { | ||
| 643 | uint64_t reserved_29_63:35; | ||
| 644 | uint64_t tc_en:1; | ||
| 645 | uint64_t tc_thr:4; | ||
| 646 | uint64_t reserved_18_23:6; | ||
| 647 | uint64_t ds_thr:6; | ||
| 648 | uint64_t reserved_6_11:6; | ||
| 649 | uint64_t iq_thr:6; | ||
| 650 | } cn30xx; | ||
| 651 | struct cvmx_pow_wq_int_thrx_cn31xx { | ||
| 652 | uint64_t reserved_29_63:35; | ||
| 653 | uint64_t tc_en:1; | ||
| 654 | uint64_t tc_thr:4; | ||
| 655 | uint64_t reserved_20_23:4; | ||
| 656 | uint64_t ds_thr:8; | ||
| 657 | uint64_t reserved_8_11:4; | ||
| 658 | uint64_t iq_thr:8; | ||
| 659 | } cn31xx; | ||
| 660 | struct cvmx_pow_wq_int_thrx_s cn38xx; | ||
| 661 | struct cvmx_pow_wq_int_thrx_s cn38xxp2; | ||
| 662 | struct cvmx_pow_wq_int_thrx_cn31xx cn50xx; | ||
| 663 | struct cvmx_pow_wq_int_thrx_cn52xx { | ||
| 664 | uint64_t reserved_29_63:35; | ||
| 665 | uint64_t tc_en:1; | ||
| 666 | uint64_t tc_thr:4; | ||
| 667 | uint64_t reserved_21_23:3; | ||
| 668 | uint64_t ds_thr:9; | ||
| 669 | uint64_t reserved_9_11:3; | ||
| 670 | uint64_t iq_thr:9; | ||
| 671 | } cn52xx; | ||
| 672 | struct cvmx_pow_wq_int_thrx_cn52xx cn52xxp1; | ||
| 673 | struct cvmx_pow_wq_int_thrx_s cn56xx; | ||
| 674 | struct cvmx_pow_wq_int_thrx_s cn56xxp1; | ||
| 675 | struct cvmx_pow_wq_int_thrx_s cn58xx; | ||
| 676 | struct cvmx_pow_wq_int_thrx_s cn58xxp1; | ||
| 677 | }; | ||
| 678 | |||
| 679 | union cvmx_pow_ws_pcx { | ||
| 680 | uint64_t u64; | ||
| 681 | struct cvmx_pow_ws_pcx_s { | ||
| 682 | uint64_t reserved_32_63:32; | ||
| 683 | uint64_t ws_pc:32; | ||
| 684 | } s; | ||
| 685 | struct cvmx_pow_ws_pcx_s cn30xx; | ||
| 686 | struct cvmx_pow_ws_pcx_s cn31xx; | ||
| 687 | struct cvmx_pow_ws_pcx_s cn38xx; | ||
| 688 | struct cvmx_pow_ws_pcx_s cn38xxp2; | ||
| 689 | struct cvmx_pow_ws_pcx_s cn50xx; | ||
| 690 | struct cvmx_pow_ws_pcx_s cn52xx; | ||
| 691 | struct cvmx_pow_ws_pcx_s cn52xxp1; | ||
| 692 | struct cvmx_pow_ws_pcx_s cn56xx; | ||
| 693 | struct cvmx_pow_ws_pcx_s cn56xxp1; | ||
| 694 | struct cvmx_pow_ws_pcx_s cn58xx; | ||
| 695 | struct cvmx_pow_ws_pcx_s cn58xxp1; | ||
| 696 | }; | ||
| 697 | |||
| 698 | #endif | ||
diff --git a/arch/mips/include/asm/octeon/cvmx-spinlock.h b/arch/mips/include/asm/octeon/cvmx-spinlock.h new file mode 100644 index 000000000000..2fbf0871df11 --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-spinlock.h | |||
| @@ -0,0 +1,232 @@ | |||
| 1 | /***********************license start*************** | ||
| 2 | * Author: Cavium Networks | ||
| 3 | * | ||
| 4 | * Contact: support@caviumnetworks.com | ||
| 5 | * This file is part of the OCTEON SDK | ||
| 6 | * | ||
| 7 | * Copyright (c) 2003-2008 Cavium Networks | ||
| 8 | * | ||
| 9 | * This file is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License, Version 2, as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | * | ||
| 13 | * This file is distributed in the hope that it will be useful, but | ||
| 14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
| 15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
| 16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
| 17 | * details. | ||
| 18 | * | ||
| 19 | * You should have received a copy of the GNU General Public License | ||
| 20 | * along with this file; if not, write to the Free Software | ||
| 21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 22 | * or visit http://www.gnu.org/licenses/. | ||
| 23 | * | ||
| 24 | * This file may also be available under a different license from Cavium. | ||
| 25 | * Contact Cavium Networks for more information | ||
| 26 | ***********************license end**************************************/ | ||
| 27 | |||
| 28 | /** | ||
| 29 | * Implementation of spinlocks for Octeon CVMX. Although similar in | ||
| 30 | * function to Linux kernel spinlocks, they are not compatible. | ||
| 31 | * Octeon CVMX spinlocks are only used to synchronize with the boot | ||
| 32 | * monitor and other non-Linux programs running in the system. | ||
| 33 | */ | ||
| 34 | |||
| 35 | #ifndef __CVMX_SPINLOCK_H__ | ||
| 36 | #define __CVMX_SPINLOCK_H__ | ||
| 37 | |||
| 38 | #include "cvmx-asm.h" | ||
| 39 | |||
| 40 | /* Spinlocks for Octeon */ | ||
| 41 | |||
| 42 | /* define these to enable recursive spinlock debugging */ | ||
| 43 | /*#define CVMX_SPINLOCK_DEBUG */ | ||
| 44 | |||
| 45 | /** | ||
| 46 | * Spinlocks for Octeon CVMX | ||
| 47 | */ | ||
| 48 | typedef struct { | ||
| 49 | volatile uint32_t value; | ||
| 50 | } cvmx_spinlock_t; | ||
| 51 | |||
| 52 | /* note - macros not expanded in inline ASM, so values hardcoded */ | ||
| 53 | #define CVMX_SPINLOCK_UNLOCKED_VAL 0 | ||
| 54 | #define CVMX_SPINLOCK_LOCKED_VAL 1 | ||
| 55 | |||
| 56 | #define CVMX_SPINLOCK_UNLOCKED_INITIALIZER {CVMX_SPINLOCK_UNLOCKED_VAL} | ||
| 57 | |||
| 58 | /** | ||
| 59 | * Initialize a spinlock | ||
| 60 | * | ||
| 61 | * @lock: Lock to initialize | ||
| 62 | */ | ||
| 63 | static inline void cvmx_spinlock_init(cvmx_spinlock_t *lock) | ||
| 64 | { | ||
| 65 | lock->value = CVMX_SPINLOCK_UNLOCKED_VAL; | ||
| 66 | } | ||
| 67 | |||
| 68 | /** | ||
| 69 | * Return non-zero if the spinlock is currently locked | ||
| 70 | * | ||
| 71 | * @lock: Lock to check | ||
| 72 | * Returns Non-zero if locked | ||
| 73 | */ | ||
| 74 | static inline int cvmx_spinlock_locked(cvmx_spinlock_t *lock) | ||
| 75 | { | ||
| 76 | return lock->value != CVMX_SPINLOCK_UNLOCKED_VAL; | ||
| 77 | } | ||
| 78 | |||
| 79 | /** | ||
| 80 | * Releases lock | ||
| 81 | * | ||
| 82 | * @lock: pointer to lock structure | ||
| 83 | */ | ||
| 84 | static inline void cvmx_spinlock_unlock(cvmx_spinlock_t *lock) | ||
| 85 | { | ||
| 86 | CVMX_SYNCWS; | ||
| 87 | lock->value = 0; | ||
| 88 | CVMX_SYNCWS; | ||
| 89 | } | ||
| 90 | |||
| 91 | /** | ||
| 92 | * Attempts to take the lock, but does not spin if lock is not available. | ||
| 93 | * May take some time to acquire the lock even if it is available | ||
| 94 | * due to the ll/sc not succeeding. | ||
| 95 | * | ||
| 96 | * @lock: pointer to lock structure | ||
| 97 | * | ||
| 98 | * Returns 0: lock successfully taken | ||
| 99 | * 1: lock not taken, held by someone else | ||
| 100 | * These return values match the Linux semantics. | ||
| 101 | */ | ||
| 102 | |||
| 103 | static inline unsigned int cvmx_spinlock_trylock(cvmx_spinlock_t *lock) | ||
| 104 | { | ||
| 105 | unsigned int tmp; | ||
| 106 | |||
| 107 | __asm__ __volatile__(".set noreorder \n" | ||
| 108 | "1: ll %[tmp], %[val] \n" | ||
| 109 | /* if lock held, fail immediately */ | ||
| 110 | " bnez %[tmp], 2f \n" | ||
| 111 | " li %[tmp], 1 \n" | ||
| 112 | " sc %[tmp], %[val] \n" | ||
| 113 | " beqz %[tmp], 1b \n" | ||
| 114 | " li %[tmp], 0 \n" | ||
| 115 | "2: \n" | ||
| 116 | ".set reorder \n" : | ||
| 117 | [val] "+m"(lock->value), [tmp] "=&r"(tmp) | ||
| 118 | : : "memory"); | ||
| 119 | |||
| 120 | return tmp != 0; /* normalize to 0 or 1 */ | ||
| 121 | } | ||
| 122 | |||
| 123 | /** | ||
| 124 | * Gets lock, spins until lock is taken | ||
| 125 | * | ||
| 126 | * @lock: pointer to lock structure | ||
| 127 | */ | ||
| 128 | static inline void cvmx_spinlock_lock(cvmx_spinlock_t *lock) | ||
| 129 | { | ||
| 130 | unsigned int tmp; | ||
| 131 | |||
| 132 | __asm__ __volatile__(".set noreorder \n" | ||
| 133 | "1: ll %[tmp], %[val] \n" | ||
| 134 | " bnez %[tmp], 1b \n" | ||
| 135 | " li %[tmp], 1 \n" | ||
| 136 | " sc %[tmp], %[val] \n" | ||
| 137 | " beqz %[tmp], 1b \n" | ||
| 138 | " nop \n" | ||
| 139 | ".set reorder \n" : | ||
| 140 | [val] "+m"(lock->value), [tmp] "=&r"(tmp) | ||
| 141 | : : "memory"); | ||
| 142 | |||
| 143 | } | ||
| 144 | |||
| 145 | /** ******************************************************************** | ||
| 146 | * Bit spinlocks | ||
| 147 | * These spinlocks use a single bit (bit 31) of a 32 bit word for locking. | ||
| 148 | * The rest of the bits in the word are left undisturbed. This enables more | ||
| 149 | * compact data structures as only 1 bit is consumed for the lock. | ||
| 150 | * | ||
| 151 | */ | ||
| 152 | |||
| 153 | /** | ||
| 154 | * Gets lock, spins until lock is taken | ||
| 155 | * Preserves the low 31 bits of the 32 bit | ||
| 156 | * word used for the lock. | ||
| 157 | * | ||
| 158 | * | ||
| 159 | * @word: word to lock bit 31 of | ||
| 160 | */ | ||
| 161 | static inline void cvmx_spinlock_bit_lock(uint32_t *word) | ||
| 162 | { | ||
| 163 | unsigned int tmp; | ||
| 164 | unsigned int sav; | ||
| 165 | |||
| 166 | __asm__ __volatile__(".set noreorder \n" | ||
| 167 | ".set noat \n" | ||
| 168 | "1: ll %[tmp], %[val] \n" | ||
| 169 | " bbit1 %[tmp], 31, 1b \n" | ||
| 170 | " li $at, 1 \n" | ||
| 171 | " ins %[tmp], $at, 31, 1 \n" | ||
| 172 | " sc %[tmp], %[val] \n" | ||
| 173 | " beqz %[tmp], 1b \n" | ||
| 174 | " nop \n" | ||
| 175 | ".set at \n" | ||
| 176 | ".set reorder \n" : | ||
| 177 | [val] "+m"(*word), [tmp] "=&r"(tmp), [sav] "=&r"(sav) | ||
| 178 | : : "memory"); | ||
| 179 | |||
| 180 | } | ||
| 181 | |||
| 182 | /** | ||
| 183 | * Attempts to get lock, returns immediately with success/failure | ||
| 184 | * Preserves the low 31 bits of the 32 bit | ||
| 185 | * word used for the lock. | ||
| 186 | * | ||
| 187 | * | ||
| 188 | * @word: word to lock bit 31 of | ||
| 189 | * Returns 0: lock successfully taken | ||
| 190 | * 1: lock not taken, held by someone else | ||
| 191 | * These return values match the Linux semantics. | ||
| 192 | */ | ||
| 193 | static inline unsigned int cvmx_spinlock_bit_trylock(uint32_t *word) | ||
| 194 | { | ||
| 195 | unsigned int tmp; | ||
| 196 | |||
| 197 | __asm__ __volatile__(".set noreorder\n\t" | ||
| 198 | ".set noat\n" | ||
| 199 | "1: ll %[tmp], %[val] \n" | ||
| 200 | /* if lock held, fail immediately */ | ||
| 201 | " bbit1 %[tmp], 31, 2f \n" | ||
| 202 | " li $at, 1 \n" | ||
| 203 | " ins %[tmp], $at, 31, 1 \n" | ||
| 204 | " sc %[tmp], %[val] \n" | ||
| 205 | " beqz %[tmp], 1b \n" | ||
| 206 | " li %[tmp], 0 \n" | ||
| 207 | "2: \n" | ||
| 208 | ".set at \n" | ||
| 209 | ".set reorder \n" : | ||
| 210 | [val] "+m"(*word), [tmp] "=&r"(tmp) | ||
| 211 | : : "memory"); | ||
| 212 | |||
| 213 | return tmp != 0; /* normalize to 0 or 1 */ | ||
| 214 | } | ||
| 215 | |||
| 216 | /** | ||
| 217 | * Releases bit lock | ||
| 218 | * | ||
| 219 | * Unconditionally clears bit 31 of the lock word. Note that this is | ||
| 220 | * done non-atomically, as this implementation assumes that the rest | ||
| 221 | * of the bits in the word are protected by the lock. | ||
| 222 | * | ||
| 223 | * @word: word to unlock bit 31 in | ||
| 224 | */ | ||
| 225 | static inline void cvmx_spinlock_bit_unlock(uint32_t *word) | ||
| 226 | { | ||
| 227 | CVMX_SYNCWS; | ||
| 228 | *word &= ~(1UL << 31); | ||
| 229 | CVMX_SYNCWS; | ||
| 230 | } | ||
| 231 | |||
| 232 | #endif /* __CVMX_SPINLOCK_H__ */ | ||
diff --git a/arch/mips/include/asm/octeon/cvmx-sysinfo.h b/arch/mips/include/asm/octeon/cvmx-sysinfo.h new file mode 100644 index 000000000000..61dd5741afe4 --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-sysinfo.h | |||
| @@ -0,0 +1,152 @@ | |||
| 1 | /***********************license start*************** | ||
| 2 | * Author: Cavium Networks | ||
| 3 | * | ||
| 4 | * Contact: support@caviumnetworks.com | ||
| 5 | * This file is part of the OCTEON SDK | ||
| 6 | * | ||
| 7 | * Copyright (c) 2003-2008 Cavium Networks | ||
| 8 | * | ||
| 9 | * This file is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License, Version 2, as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | * | ||
| 13 | * This file is distributed in the hope that it will be useful, but | ||
| 14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
| 15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
| 16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
| 17 | * details. | ||
| 18 | * | ||
| 19 | * You should have received a copy of the GNU General Public License | ||
| 20 | * along with this file; if not, write to the Free Software | ||
| 21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 22 | * or visit http://www.gnu.org/licenses/. | ||
| 23 | * | ||
| 24 | * This file may also be available under a different license from Cavium. | ||
| 25 | * Contact Cavium Networks for more information | ||
| 26 | ***********************license end**************************************/ | ||
| 27 | |||
| 28 | /* | ||
| 29 | * This module provides system/board information obtained by the bootloader. | ||
| 30 | */ | ||
| 31 | |||
| 32 | #ifndef __CVMX_SYSINFO_H__ | ||
| 33 | #define __CVMX_SYSINFO_H__ | ||
| 34 | |||
| 35 | #define OCTEON_SERIAL_LEN 20 | ||
| 36 | /** | ||
| 37 | * Structure describing application specific information. | ||
| 38 | * __cvmx_app_init() populates this from the cvmx boot descriptor. | ||
| 39 | * This structure is private to simple executive applications, so | ||
| 40 | * no versioning is required. | ||
| 41 | * | ||
| 42 | * This structure must be provided with some fields set in order to | ||
| 43 | * use simple executive functions in other applications (Linux kernel, | ||
| 44 | * u-boot, etc.) The cvmx_sysinfo_minimal_initialize() function is | ||
| 45 | * provided to set the required values in these cases. | ||
| 46 | */ | ||
| 47 | struct cvmx_sysinfo { | ||
| 48 | /* System wide variables */ | ||
| 49 | /* installed DRAM in system, in bytes */ | ||
| 50 | uint64_t system_dram_size; | ||
| 51 | |||
| 52 | /* ptr to memory descriptor block */ | ||
| 53 | void *phy_mem_desc_ptr; | ||
| 54 | |||
| 55 | |||
| 56 | /* Application image specific variables */ | ||
| 57 | /* stack top address (virtual) */ | ||
| 58 | uint64_t stack_top; | ||
| 59 | /* heap base address (virtual) */ | ||
| 60 | uint64_t heap_base; | ||
| 61 | /* stack size in bytes */ | ||
| 62 | uint32_t stack_size; | ||
| 63 | /* heap size in bytes */ | ||
| 64 | uint32_t heap_size; | ||
| 65 | /* coremask defining cores running application */ | ||
| 66 | uint32_t core_mask; | ||
| 67 | /* Deprecated, use cvmx_coremask_first_core() to select init core */ | ||
| 68 | uint32_t init_core; | ||
| 69 | |||
| 70 | /* exception base address, as set by bootloader */ | ||
| 71 | uint64_t exception_base_addr; | ||
| 72 | |||
| 73 | /* cpu clock speed in hz */ | ||
| 74 | uint32_t cpu_clock_hz; | ||
| 75 | |||
| 76 | /* dram data rate in hz (data rate = 2 * clock rate */ | ||
| 77 | uint32_t dram_data_rate_hz; | ||
| 78 | |||
| 79 | |||
| 80 | uint16_t board_type; | ||
| 81 | uint8_t board_rev_major; | ||
| 82 | uint8_t board_rev_minor; | ||
| 83 | uint8_t mac_addr_base[6]; | ||
| 84 | uint8_t mac_addr_count; | ||
| 85 | char board_serial_number[OCTEON_SERIAL_LEN]; | ||
| 86 | /* | ||
| 87 | * Several boards support compact flash on the Octeon boot | ||
| 88 | * bus. The CF memory spaces may be mapped to different | ||
| 89 | * addresses on different boards. These values will be 0 if | ||
| 90 | * CF is not present. Note that these addresses are physical | ||
| 91 | * addresses, and it is up to the application to use the | ||
| 92 | * proper addressing mode (XKPHYS, KSEG0, etc.) | ||
| 93 | */ | ||
| 94 | uint64_t compact_flash_common_base_addr; | ||
| 95 | uint64_t compact_flash_attribute_base_addr; | ||
| 96 | /* | ||
| 97 | * Base address of the LED display (as on EBT3000 board) This | ||
| 98 | * will be 0 if LED display not present. Note that this | ||
| 99 | * address is a physical address, and it is up to the | ||
| 100 | * application to use the proper addressing mode (XKPHYS, | ||
| 101 | * KSEG0, etc.) | ||
| 102 | */ | ||
| 103 | uint64_t led_display_base_addr; | ||
| 104 | /* DFA reference clock in hz (if applicable)*/ | ||
| 105 | uint32_t dfa_ref_clock_hz; | ||
| 106 | /* configuration flags from bootloader */ | ||
| 107 | uint32_t bootloader_config_flags; | ||
| 108 | |||
| 109 | /* Uart number used for console */ | ||
| 110 | uint8_t console_uart_num; | ||
| 111 | }; | ||
| 112 | |||
| 113 | /** | ||
| 114 | * This function returns the system/board information as obtained | ||
| 115 | * by the bootloader. | ||
| 116 | * | ||
| 117 | * | ||
| 118 | * Returns Pointer to the boot information structure | ||
| 119 | * | ||
| 120 | */ | ||
| 121 | |||
| 122 | extern struct cvmx_sysinfo *cvmx_sysinfo_get(void); | ||
| 123 | |||
| 124 | /** | ||
| 125 | * This function is used in non-simple executive environments (such as | ||
| 126 | * Linux kernel, u-boot, etc.) to configure the minimal fields that | ||
| 127 | * are required to use simple executive files directly. | ||
| 128 | * | ||
| 129 | * Locking (if required) must be handled outside of this | ||
| 130 | * function | ||
| 131 | * | ||
| 132 | * @phy_mem_desc_ptr: Pointer to global physical memory descriptor | ||
| 133 | * (bootmem descriptor) @board_type: Octeon board | ||
| 134 | * type enumeration | ||
| 135 | * | ||
| 136 | * @board_rev_major: | ||
| 137 | * Board major revision | ||
| 138 | * @board_rev_minor: | ||
| 139 | * Board minor revision | ||
| 140 | * @cpu_clock_hz: | ||
| 141 | * CPU clock freqency in hertz | ||
| 142 | * | ||
| 143 | * Returns 0: Failure | ||
| 144 | * 1: success | ||
| 145 | */ | ||
| 146 | extern int cvmx_sysinfo_minimal_initialize(void *phy_mem_desc_ptr, | ||
| 147 | uint16_t board_type, | ||
| 148 | uint8_t board_rev_major, | ||
| 149 | uint8_t board_rev_minor, | ||
| 150 | uint32_t cpu_clock_hz); | ||
| 151 | |||
| 152 | #endif /* __CVMX_SYSINFO_H__ */ | ||
diff --git a/arch/mips/include/asm/octeon/cvmx.h b/arch/mips/include/asm/octeon/cvmx.h new file mode 100644 index 000000000000..03fddfa3e928 --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx.h | |||
| @@ -0,0 +1,505 @@ | |||
| 1 | /***********************license start*************** | ||
| 2 | * Author: Cavium Networks | ||
| 3 | * | ||
| 4 | * Contact: support@caviumnetworks.com | ||
| 5 | * This file is part of the OCTEON SDK | ||
| 6 | * | ||
| 7 | * Copyright (c) 2003-2008 Cavium Networks | ||
| 8 | * | ||
| 9 | * This file is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License, Version 2, as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | * | ||
| 13 | * This file is distributed in the hope that it will be useful, but | ||
| 14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
| 15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
| 16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
| 17 | * details. | ||
| 18 | * | ||
| 19 | * You should have received a copy of the GNU General Public License | ||
| 20 | * along with this file; if not, write to the Free Software | ||
| 21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 22 | * or visit http://www.gnu.org/licenses/. | ||
| 23 | * | ||
| 24 | * This file may also be available under a different license from Cavium. | ||
| 25 | * Contact Cavium Networks for more information | ||
| 26 | ***********************license end**************************************/ | ||
| 27 | |||
| 28 | #ifndef __CVMX_H__ | ||
| 29 | #define __CVMX_H__ | ||
| 30 | |||
| 31 | #include <linux/kernel.h> | ||
| 32 | #include <linux/string.h> | ||
| 33 | |||
| 34 | #include "cvmx-asm.h" | ||
| 35 | #include "cvmx-packet.h" | ||
| 36 | #include "cvmx-sysinfo.h" | ||
| 37 | |||
| 38 | #include "cvmx-ciu-defs.h" | ||
| 39 | #include "cvmx-gpio-defs.h" | ||
| 40 | #include "cvmx-iob-defs.h" | ||
| 41 | #include "cvmx-ipd-defs.h" | ||
| 42 | #include "cvmx-l2c-defs.h" | ||
| 43 | #include "cvmx-l2d-defs.h" | ||
| 44 | #include "cvmx-l2t-defs.h" | ||
| 45 | #include "cvmx-led-defs.h" | ||
| 46 | #include "cvmx-mio-defs.h" | ||
| 47 | #include "cvmx-pow-defs.h" | ||
| 48 | |||
| 49 | #include "cvmx-bootinfo.h" | ||
| 50 | #include "cvmx-bootmem.h" | ||
| 51 | #include "cvmx-l2c.h" | ||
| 52 | |||
| 53 | #ifndef CVMX_ENABLE_DEBUG_PRINTS | ||
| 54 | #define CVMX_ENABLE_DEBUG_PRINTS 1 | ||
| 55 | #endif | ||
| 56 | |||
| 57 | #if CVMX_ENABLE_DEBUG_PRINTS | ||
| 58 | #define cvmx_dprintf printk | ||
| 59 | #else | ||
| 60 | #define cvmx_dprintf(...) {} | ||
| 61 | #endif | ||
| 62 | |||
| 63 | #define CVMX_MAX_CORES (16) | ||
| 64 | #define CVMX_CACHE_LINE_SIZE (128) /* In bytes */ | ||
| 65 | #define CVMX_CACHE_LINE_MASK (CVMX_CACHE_LINE_SIZE - 1) /* In bytes */ | ||
| 66 | #define CVMX_CACHE_LINE_ALIGNED __attribute__ ((aligned(CVMX_CACHE_LINE_SIZE))) | ||
| 67 | #define CAST64(v) ((long long)(long)(v)) | ||
| 68 | #define CASTPTR(type, v) ((type *)(long)(v)) | ||
| 69 | |||
| 70 | /* | ||
| 71 | * Returns processor ID, different Linux and simple exec versions | ||
| 72 | * provided in the cvmx-app-init*.c files. | ||
| 73 | */ | ||
| 74 | static inline uint32_t cvmx_get_proc_id(void) __attribute__ ((pure)); | ||
| 75 | static inline uint32_t cvmx_get_proc_id(void) | ||
| 76 | { | ||
| 77 | uint32_t id; | ||
| 78 | asm("mfc0 %0, $15,0" : "=r"(id)); | ||
| 79 | return id; | ||
| 80 | } | ||
| 81 | |||
| 82 | /* turn the variable name into a string */ | ||
| 83 | #define CVMX_TMP_STR(x) CVMX_TMP_STR2(x) | ||
| 84 | #define CVMX_TMP_STR2(x) #x | ||
| 85 | |||
| 86 | /** | ||
| 87 | * Builds a bit mask given the required size in bits. | ||
| 88 | * | ||
| 89 | * @bits: Number of bits in the mask | ||
| 90 | * Returns The mask | ||
| 91 | */ static inline uint64_t cvmx_build_mask(uint64_t bits) | ||
| 92 | { | ||
| 93 | return ~((~0x0ull) << bits); | ||
| 94 | } | ||
| 95 | |||
| 96 | /** | ||
| 97 | * Builds a memory address for I/O based on the Major and Sub DID. | ||
| 98 | * | ||
| 99 | * @major_did: 5 bit major did | ||
| 100 | * @sub_did: 3 bit sub did | ||
| 101 | * Returns I/O base address | ||
| 102 | */ | ||
| 103 | static inline uint64_t cvmx_build_io_address(uint64_t major_did, | ||
| 104 | uint64_t sub_did) | ||
| 105 | { | ||
| 106 | return (0x1ull << 48) | (major_did << 43) | (sub_did << 40); | ||
| 107 | } | ||
| 108 | |||
| 109 | /** | ||
| 110 | * Perform mask and shift to place the supplied value into | ||
| 111 | * the supplied bit rage. | ||
| 112 | * | ||
| 113 | * Example: cvmx_build_bits(39,24,value) | ||
| 114 | * <pre> | ||
| 115 | * 6 5 4 3 3 2 1 | ||
| 116 | * 3 5 7 9 1 3 5 7 0 | ||
| 117 | * +-------+-------+-------+-------+-------+-------+-------+------+ | ||
| 118 | * 000000000000000000000000___________value000000000000000000000000 | ||
| 119 | * </pre> | ||
| 120 | * | ||
| 121 | * @high_bit: Highest bit value can occupy (inclusive) 0-63 | ||
| 122 | * @low_bit: Lowest bit value can occupy inclusive 0-high_bit | ||
| 123 | * @value: Value to use | ||
| 124 | * Returns Value masked and shifted | ||
| 125 | */ | ||
| 126 | static inline uint64_t cvmx_build_bits(uint64_t high_bit, | ||
| 127 | uint64_t low_bit, uint64_t value) | ||
| 128 | { | ||
| 129 | return (value & cvmx_build_mask(high_bit - low_bit + 1)) << low_bit; | ||
| 130 | } | ||
| 131 | |||
| 132 | enum cvmx_mips_space { | ||
| 133 | CVMX_MIPS_SPACE_XKSEG = 3LL, | ||
| 134 | CVMX_MIPS_SPACE_XKPHYS = 2LL, | ||
| 135 | CVMX_MIPS_SPACE_XSSEG = 1LL, | ||
| 136 | CVMX_MIPS_SPACE_XUSEG = 0LL | ||
| 137 | }; | ||
| 138 | |||
| 139 | /* These macros for use when using 32 bit pointers. */ | ||
| 140 | #define CVMX_MIPS32_SPACE_KSEG0 1l | ||
| 141 | #define CVMX_ADD_SEG32(segment, add) \ | ||
| 142 | (((int32_t)segment << 31) | (int32_t)(add)) | ||
| 143 | |||
| 144 | #define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS | ||
| 145 | |||
| 146 | /* These macros simplify the process of creating common IO addresses */ | ||
| 147 | #define CVMX_ADD_SEG(segment, add) \ | ||
| 148 | ((((uint64_t)segment) << 62) | (add)) | ||
| 149 | #ifndef CVMX_ADD_IO_SEG | ||
| 150 | #define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add)) | ||
| 151 | #endif | ||
| 152 | |||
| 153 | /** | ||
| 154 | * Convert a memory pointer (void*) into a hardware compatable | ||
| 155 | * memory address (uint64_t). Octeon hardware widgets don't | ||
| 156 | * understand logical addresses. | ||
| 157 | * | ||
| 158 | * @ptr: C style memory pointer | ||
| 159 | * Returns Hardware physical address | ||
| 160 | */ | ||
| 161 | static inline uint64_t cvmx_ptr_to_phys(void *ptr) | ||
| 162 | { | ||
| 163 | if (sizeof(void *) == 8) { | ||
| 164 | /* | ||
| 165 | * We're running in 64 bit mode. Normally this means | ||
| 166 | * that we can use 40 bits of address space (the | ||
| 167 | * hardware limit). Unfortunately there is one case | ||
| 168 | * were we need to limit this to 30 bits, sign | ||
| 169 | * extended 32 bit. Although these are 64 bits wide, | ||
| 170 | * only 30 bits can be used. | ||
| 171 | */ | ||
| 172 | if ((CAST64(ptr) >> 62) == 3) | ||
| 173 | return CAST64(ptr) & cvmx_build_mask(30); | ||
| 174 | else | ||
| 175 | return CAST64(ptr) & cvmx_build_mask(40); | ||
| 176 | } else { | ||
| 177 | return (long)(ptr) & 0x1fffffff; | ||
| 178 | } | ||
| 179 | } | ||
| 180 | |||
| 181 | /** | ||
| 182 | * Convert a hardware physical address (uint64_t) into a | ||
| 183 | * memory pointer (void *). | ||
| 184 | * | ||
| 185 | * @physical_address: | ||
| 186 | * Hardware physical address to memory | ||
| 187 | * Returns Pointer to memory | ||
| 188 | */ | ||
| 189 | static inline void *cvmx_phys_to_ptr(uint64_t physical_address) | ||
| 190 | { | ||
| 191 | if (sizeof(void *) == 8) { | ||
| 192 | /* Just set the top bit, avoiding any TLB uglyness */ | ||
| 193 | return CASTPTR(void, | ||
| 194 | CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, | ||
| 195 | physical_address)); | ||
| 196 | } else { | ||
| 197 | return CASTPTR(void, | ||
| 198 | CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, | ||
| 199 | physical_address)); | ||
| 200 | } | ||
| 201 | } | ||
| 202 | |||
| 203 | /* The following #if controls the definition of the macro | ||
| 204 | CVMX_BUILD_WRITE64. This macro is used to build a store operation to | ||
| 205 | a full 64bit address. With a 64bit ABI, this can be done with a simple | ||
| 206 | pointer access. 32bit ABIs require more complicated assembly */ | ||
| 207 | |||
| 208 | /* We have a full 64bit ABI. Writing to a 64bit address can be done with | ||
| 209 | a simple volatile pointer */ | ||
| 210 | #define CVMX_BUILD_WRITE64(TYPE, ST) \ | ||
| 211 | static inline void cvmx_write64_##TYPE(uint64_t addr, TYPE##_t val) \ | ||
| 212 | { \ | ||
| 213 | *CASTPTR(volatile TYPE##_t, addr) = val; \ | ||
| 214 | } | ||
| 215 | |||
| 216 | |||
| 217 | /* The following #if controls the definition of the macro | ||
| 218 | CVMX_BUILD_READ64. This macro is used to build a load operation from | ||
| 219 | a full 64bit address. With a 64bit ABI, this can be done with a simple | ||
| 220 | pointer access. 32bit ABIs require more complicated assembly */ | ||
| 221 | |||
| 222 | /* We have a full 64bit ABI. Writing to a 64bit address can be done with | ||
| 223 | a simple volatile pointer */ | ||
| 224 | #define CVMX_BUILD_READ64(TYPE, LT) \ | ||
| 225 | static inline TYPE##_t cvmx_read64_##TYPE(uint64_t addr) \ | ||
| 226 | { \ | ||
| 227 | return *CASTPTR(volatile TYPE##_t, addr); \ | ||
| 228 | } | ||
| 229 | |||
| 230 | |||
| 231 | /* The following defines 8 functions for writing to a 64bit address. Each | ||
| 232 | takes two arguments, the address and the value to write. | ||
| 233 | cvmx_write64_int64 cvmx_write64_uint64 | ||
| 234 | cvmx_write64_int32 cvmx_write64_uint32 | ||
| 235 | cvmx_write64_int16 cvmx_write64_uint16 | ||
| 236 | cvmx_write64_int8 cvmx_write64_uint8 */ | ||
| 237 | CVMX_BUILD_WRITE64(int64, "sd"); | ||
| 238 | CVMX_BUILD_WRITE64(int32, "sw"); | ||
| 239 | CVMX_BUILD_WRITE64(int16, "sh"); | ||
| 240 | CVMX_BUILD_WRITE64(int8, "sb"); | ||
| 241 | CVMX_BUILD_WRITE64(uint64, "sd"); | ||
| 242 | CVMX_BUILD_WRITE64(uint32, "sw"); | ||
| 243 | CVMX_BUILD_WRITE64(uint16, "sh"); | ||
| 244 | CVMX_BUILD_WRITE64(uint8, "sb"); | ||
| 245 | #define cvmx_write64 cvmx_write64_uint64 | ||
| 246 | |||
| 247 | /* The following defines 8 functions for reading from a 64bit address. Each | ||
| 248 | takes the address as the only argument | ||
| 249 | cvmx_read64_int64 cvmx_read64_uint64 | ||
| 250 | cvmx_read64_int32 cvmx_read64_uint32 | ||
| 251 | cvmx_read64_int16 cvmx_read64_uint16 | ||
| 252 | cvmx_read64_int8 cvmx_read64_uint8 */ | ||
| 253 | CVMX_BUILD_READ64(int64, "ld"); | ||
| 254 | CVMX_BUILD_READ64(int32, "lw"); | ||
| 255 | CVMX_BUILD_READ64(int16, "lh"); | ||
| 256 | CVMX_BUILD_READ64(int8, "lb"); | ||
| 257 | CVMX_BUILD_READ64(uint64, "ld"); | ||
| 258 | CVMX_BUILD_READ64(uint32, "lw"); | ||
| 259 | CVMX_BUILD_READ64(uint16, "lhu"); | ||
| 260 | CVMX_BUILD_READ64(uint8, "lbu"); | ||
| 261 | #define cvmx_read64 cvmx_read64_uint64 | ||
| 262 | |||
| 263 | |||
| 264 | static inline void cvmx_write_csr(uint64_t csr_addr, uint64_t val) | ||
| 265 | { | ||
| 266 | cvmx_write64(csr_addr, val); | ||
| 267 | |||
| 268 | /* | ||
| 269 | * Perform an immediate read after every write to an RSL | ||
| 270 | * register to force the write to complete. It doesn't matter | ||
| 271 | * what RSL read we do, so we choose CVMX_MIO_BOOT_BIST_STAT | ||
| 272 | * because it is fast and harmless. | ||
| 273 | */ | ||
| 274 | if ((csr_addr >> 40) == (0x800118)) | ||
| 275 | cvmx_read64(CVMX_MIO_BOOT_BIST_STAT); | ||
| 276 | } | ||
| 277 | |||
| 278 | static inline void cvmx_write_io(uint64_t io_addr, uint64_t val) | ||
| 279 | { | ||
| 280 | cvmx_write64(io_addr, val); | ||
| 281 | |||
| 282 | } | ||
| 283 | |||
| 284 | static inline uint64_t cvmx_read_csr(uint64_t csr_addr) | ||
| 285 | { | ||
| 286 | uint64_t val = cvmx_read64(csr_addr); | ||
| 287 | return val; | ||
| 288 | } | ||
| 289 | |||
| 290 | |||
| 291 | static inline void cvmx_send_single(uint64_t data) | ||
| 292 | { | ||
| 293 | const uint64_t CVMX_IOBDMA_SENDSINGLE = 0xffffffffffffa200ull; | ||
| 294 | cvmx_write64(CVMX_IOBDMA_SENDSINGLE, data); | ||
| 295 | } | ||
| 296 | |||
| 297 | static inline void cvmx_read_csr_async(uint64_t scraddr, uint64_t csr_addr) | ||
| 298 | { | ||
| 299 | union { | ||
| 300 | uint64_t u64; | ||
| 301 | struct { | ||
| 302 | uint64_t scraddr:8; | ||
| 303 | uint64_t len:8; | ||
| 304 | uint64_t addr:48; | ||
| 305 | } s; | ||
| 306 | } addr; | ||
| 307 | addr.u64 = csr_addr; | ||
| 308 | addr.s.scraddr = scraddr >> 3; | ||
| 309 | addr.s.len = 1; | ||
| 310 | cvmx_send_single(addr.u64); | ||
| 311 | } | ||
| 312 | |||
| 313 | /* Return true if Octeon is CN38XX pass 1 */ | ||
| 314 | static inline int cvmx_octeon_is_pass1(void) | ||
| 315 | { | ||
| 316 | #if OCTEON_IS_COMMON_BINARY() | ||
| 317 | return 0; /* Pass 1 isn't supported for common binaries */ | ||
| 318 | #else | ||
| 319 | /* Now that we know we're built for a specific model, only check CN38XX */ | ||
| 320 | #if OCTEON_IS_MODEL(OCTEON_CN38XX) | ||
| 321 | return cvmx_get_proc_id() == OCTEON_CN38XX_PASS1; | ||
| 322 | #else | ||
| 323 | return 0; /* Built for non CN38XX chip, we're not CN38XX pass1 */ | ||
| 324 | #endif | ||
| 325 | #endif | ||
| 326 | } | ||
| 327 | |||
| 328 | static inline unsigned int cvmx_get_core_num(void) | ||
| 329 | { | ||
| 330 | unsigned int core_num; | ||
| 331 | CVMX_RDHWRNV(core_num, 0); | ||
| 332 | return core_num; | ||
| 333 | } | ||
| 334 | |||
| 335 | /** | ||
| 336 | * Returns the number of bits set in the provided value. | ||
| 337 | * Simple wrapper for POP instruction. | ||
| 338 | * | ||
| 339 | * @val: 32 bit value to count set bits in | ||
| 340 | * | ||
| 341 | * Returns Number of bits set | ||
| 342 | */ | ||
| 343 | static inline uint32_t cvmx_pop(uint32_t val) | ||
| 344 | { | ||
| 345 | uint32_t pop; | ||
| 346 | CVMX_POP(pop, val); | ||
| 347 | return pop; | ||
| 348 | } | ||
| 349 | |||
| 350 | /** | ||
| 351 | * Returns the number of bits set in the provided value. | ||
| 352 | * Simple wrapper for DPOP instruction. | ||
| 353 | * | ||
| 354 | * @val: 64 bit value to count set bits in | ||
| 355 | * | ||
| 356 | * Returns Number of bits set | ||
| 357 | */ | ||
| 358 | static inline int cvmx_dpop(uint64_t val) | ||
| 359 | { | ||
| 360 | int pop; | ||
| 361 | CVMX_DPOP(pop, val); | ||
| 362 | return pop; | ||
| 363 | } | ||
| 364 | |||
| 365 | /** | ||
| 366 | * Provide current cycle counter as a return value | ||
| 367 | * | ||
| 368 | * Returns current cycle counter | ||
| 369 | */ | ||
| 370 | |||
| 371 | static inline uint64_t cvmx_get_cycle(void) | ||
| 372 | { | ||
| 373 | uint64_t cycle; | ||
| 374 | CVMX_RDHWR(cycle, 31); | ||
| 375 | return cycle; | ||
| 376 | } | ||
| 377 | |||
| 378 | /** | ||
| 379 | * Reads a chip global cycle counter. This counts CPU cycles since | ||
| 380 | * chip reset. The counter is 64 bit. | ||
| 381 | * This register does not exist on CN38XX pass 1 silicion | ||
| 382 | * | ||
| 383 | * Returns Global chip cycle count since chip reset. | ||
| 384 | */ | ||
| 385 | static inline uint64_t cvmx_get_cycle_global(void) | ||
| 386 | { | ||
| 387 | if (cvmx_octeon_is_pass1()) | ||
| 388 | return 0; | ||
| 389 | else | ||
| 390 | return cvmx_read64(CVMX_IPD_CLK_COUNT); | ||
| 391 | } | ||
| 392 | |||
| 393 | /** | ||
| 394 | * This macro spins on a field waiting for it to reach a value. It | ||
| 395 | * is common in code to need to wait for a specific field in a CSR | ||
| 396 | * to match a specific value. Conceptually this macro expands to: | ||
| 397 | * | ||
| 398 | * 1) read csr at "address" with a csr typedef of "type" | ||
| 399 | * 2) Check if ("type".s."field" "op" "value") | ||
| 400 | * 3) If #2 isn't true loop to #1 unless too much time has passed. | ||
| 401 | */ | ||
| 402 | #define CVMX_WAIT_FOR_FIELD64(address, type, field, op, value, timeout_usec)\ | ||
| 403 | ( \ | ||
| 404 | { \ | ||
| 405 | int result; \ | ||
| 406 | do { \ | ||
| 407 | uint64_t done = cvmx_get_cycle() + (uint64_t)timeout_usec * \ | ||
| 408 | cvmx_sysinfo_get()->cpu_clock_hz / 1000000; \ | ||
| 409 | type c; \ | ||
| 410 | while (1) { \ | ||
| 411 | c.u64 = cvmx_read_csr(address); \ | ||
| 412 | if ((c.s.field) op(value)) { \ | ||
| 413 | result = 0; \ | ||
| 414 | break; \ | ||
| 415 | } else if (cvmx_get_cycle() > done) { \ | ||
| 416 | result = -1; \ | ||
| 417 | break; \ | ||
| 418 | } else \ | ||
| 419 | cvmx_wait(100); \ | ||
| 420 | } \ | ||
| 421 | } while (0); \ | ||
| 422 | result; \ | ||
| 423 | }) | ||
| 424 | |||
| 425 | /***************************************************************************/ | ||
| 426 | |||
| 427 | static inline void cvmx_reset_octeon(void) | ||
| 428 | { | ||
| 429 | union cvmx_ciu_soft_rst ciu_soft_rst; | ||
| 430 | ciu_soft_rst.u64 = 0; | ||
| 431 | ciu_soft_rst.s.soft_rst = 1; | ||
| 432 | cvmx_write_csr(CVMX_CIU_SOFT_RST, ciu_soft_rst.u64); | ||
| 433 | } | ||
| 434 | |||
| 435 | /* Return the number of cores available in the chip */ | ||
| 436 | static inline uint32_t cvmx_octeon_num_cores(void) | ||
| 437 | { | ||
| 438 | uint32_t ciu_fuse = (uint32_t) cvmx_read_csr(CVMX_CIU_FUSE) & 0xffff; | ||
| 439 | return cvmx_pop(ciu_fuse); | ||
| 440 | } | ||
| 441 | |||
| 442 | /** | ||
| 443 | * Read a byte of fuse data | ||
| 444 | * @byte_addr: address to read | ||
| 445 | * | ||
| 446 | * Returns fuse value: 0 or 1 | ||
| 447 | */ | ||
| 448 | static uint8_t cvmx_fuse_read_byte(int byte_addr) | ||
| 449 | { | ||
| 450 | union cvmx_mio_fus_rcmd read_cmd; | ||
| 451 | |||
| 452 | read_cmd.u64 = 0; | ||
| 453 | read_cmd.s.addr = byte_addr; | ||
| 454 | read_cmd.s.pend = 1; | ||
| 455 | cvmx_write_csr(CVMX_MIO_FUS_RCMD, read_cmd.u64); | ||
| 456 | while ((read_cmd.u64 = cvmx_read_csr(CVMX_MIO_FUS_RCMD)) | ||
| 457 | && read_cmd.s.pend) | ||
| 458 | ; | ||
| 459 | return read_cmd.s.dat; | ||
| 460 | } | ||
| 461 | |||
| 462 | /** | ||
| 463 | * Read a single fuse bit | ||
| 464 | * | ||
| 465 | * @fuse: Fuse number (0-1024) | ||
| 466 | * | ||
| 467 | * Returns fuse value: 0 or 1 | ||
| 468 | */ | ||
| 469 | static inline int cvmx_fuse_read(int fuse) | ||
| 470 | { | ||
| 471 | return (cvmx_fuse_read_byte(fuse >> 3) >> (fuse & 0x7)) & 1; | ||
| 472 | } | ||
| 473 | |||
| 474 | static inline int cvmx_octeon_model_CN36XX(void) | ||
| 475 | { | ||
| 476 | return OCTEON_IS_MODEL(OCTEON_CN38XX) | ||
| 477 | && !cvmx_octeon_is_pass1() | ||
| 478 | && cvmx_fuse_read(264); | ||
| 479 | } | ||
| 480 | |||
| 481 | static inline int cvmx_octeon_zip_present(void) | ||
| 482 | { | ||
| 483 | return octeon_has_feature(OCTEON_FEATURE_ZIP); | ||
| 484 | } | ||
| 485 | |||
| 486 | static inline int cvmx_octeon_dfa_present(void) | ||
| 487 | { | ||
| 488 | if (!OCTEON_IS_MODEL(OCTEON_CN38XX) | ||
| 489 | && !OCTEON_IS_MODEL(OCTEON_CN31XX) | ||
| 490 | && !OCTEON_IS_MODEL(OCTEON_CN58XX)) | ||
| 491 | return 0; | ||
| 492 | else if (OCTEON_IS_MODEL(OCTEON_CN3020)) | ||
| 493 | return 0; | ||
| 494 | else if (cvmx_octeon_is_pass1()) | ||
| 495 | return 1; | ||
| 496 | else | ||
| 497 | return !cvmx_fuse_read(120); | ||
| 498 | } | ||
| 499 | |||
| 500 | static inline int cvmx_octeon_crypto_present(void) | ||
| 501 | { | ||
| 502 | return octeon_has_feature(OCTEON_FEATURE_CRYPTO); | ||
| 503 | } | ||
| 504 | |||
| 505 | #endif /* __CVMX_H__ */ | ||
diff --git a/arch/mips/include/asm/octeon/octeon-feature.h b/arch/mips/include/asm/octeon/octeon-feature.h new file mode 100644 index 000000000000..04fac684069c --- /dev/null +++ b/arch/mips/include/asm/octeon/octeon-feature.h | |||
| @@ -0,0 +1,119 @@ | |||
| 1 | /***********************license start*************** | ||
| 2 | * Author: Cavium Networks | ||
| 3 | * | ||
| 4 | * Contact: support@caviumnetworks.com | ||
| 5 | * This file is part of the OCTEON SDK | ||
| 6 | * | ||
| 7 | * Copyright (c) 2003-2008 Cavium Networks | ||
| 8 | * | ||
| 9 | * This file is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License, Version 2, as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | * | ||
| 13 | * This file is distributed in the hope that it will be useful, but | ||
| 14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
| 15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
| 16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
| 17 | * details. | ||
| 18 | * | ||
| 19 | * You should have received a copy of the GNU General Public License | ||
| 20 | * along with this file; if not, write to the Free Software | ||
| 21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 22 | * or visit http://www.gnu.org/licenses/. | ||
| 23 | * | ||
| 24 | * This file may also be available under a different license from Cavium. | ||
| 25 | * Contact Cavium Networks for more information | ||
| 26 | ***********************license end**************************************/ | ||
| 27 | |||
| 28 | /* | ||
| 29 | * File defining checks for different Octeon features. | ||
| 30 | */ | ||
| 31 | |||
| 32 | #ifndef __OCTEON_FEATURE_H__ | ||
| 33 | #define __OCTEON_FEATURE_H__ | ||
| 34 | |||
| 35 | enum octeon_feature { | ||
| 36 | /* | ||
| 37 | * Octeon models in the CN5XXX family and higher support | ||
| 38 | * atomic add instructions to memory (saa/saad). | ||
| 39 | */ | ||
| 40 | OCTEON_FEATURE_SAAD, | ||
| 41 | /* Does this Octeon support the ZIP offload engine? */ | ||
| 42 | OCTEON_FEATURE_ZIP, | ||
| 43 | /* Does this Octeon support crypto acceleration using COP2? */ | ||
| 44 | OCTEON_FEATURE_CRYPTO, | ||
| 45 | /* Does this Octeon support PCI express? */ | ||
| 46 | OCTEON_FEATURE_PCIE, | ||
| 47 | /* Some Octeon models support internal memory for storing | ||
| 48 | * cryptographic keys */ | ||
| 49 | OCTEON_FEATURE_KEY_MEMORY, | ||
| 50 | /* Octeon has a LED controller for banks of external LEDs */ | ||
| 51 | OCTEON_FEATURE_LED_CONTROLLER, | ||
| 52 | /* Octeon has a trace buffer */ | ||
| 53 | OCTEON_FEATURE_TRA, | ||
| 54 | /* Octeon has a management port */ | ||
| 55 | OCTEON_FEATURE_MGMT_PORT, | ||
| 56 | /* Octeon has a raid unit */ | ||
| 57 | OCTEON_FEATURE_RAID, | ||
| 58 | /* Octeon has a builtin USB */ | ||
| 59 | OCTEON_FEATURE_USB, | ||
| 60 | }; | ||
| 61 | |||
| 62 | static inline int cvmx_fuse_read(int fuse); | ||
| 63 | |||
| 64 | /** | ||
| 65 | * Determine if the current Octeon supports a specific feature. These | ||
| 66 | * checks have been optimized to be fairly quick, but they should still | ||
| 67 | * be kept out of fast path code. | ||
| 68 | * | ||
| 69 | * @feature: Feature to check for. This should always be a constant so the | ||
| 70 | * compiler can remove the switch statement through optimization. | ||
| 71 | * | ||
| 72 | * Returns Non zero if the feature exists. Zero if the feature does not | ||
| 73 | * exist. | ||
| 74 | */ | ||
| 75 | static inline int octeon_has_feature(enum octeon_feature feature) | ||
| 76 | { | ||
| 77 | switch (feature) { | ||
| 78 | case OCTEON_FEATURE_SAAD: | ||
| 79 | return !OCTEON_IS_MODEL(OCTEON_CN3XXX); | ||
| 80 | |||
| 81 | case OCTEON_FEATURE_ZIP: | ||
| 82 | if (OCTEON_IS_MODEL(OCTEON_CN30XX) | ||
| 83 | || OCTEON_IS_MODEL(OCTEON_CN50XX) | ||
| 84 | || OCTEON_IS_MODEL(OCTEON_CN52XX)) | ||
| 85 | return 0; | ||
| 86 | else if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1)) | ||
| 87 | return 1; | ||
| 88 | else | ||
| 89 | return !cvmx_fuse_read(121); | ||
| 90 | |||
| 91 | case OCTEON_FEATURE_CRYPTO: | ||
| 92 | return !cvmx_fuse_read(90); | ||
| 93 | |||
| 94 | case OCTEON_FEATURE_PCIE: | ||
| 95 | return OCTEON_IS_MODEL(OCTEON_CN56XX) | ||
| 96 | || OCTEON_IS_MODEL(OCTEON_CN52XX); | ||
| 97 | |||
| 98 | case OCTEON_FEATURE_KEY_MEMORY: | ||
| 99 | case OCTEON_FEATURE_LED_CONTROLLER: | ||
| 100 | return OCTEON_IS_MODEL(OCTEON_CN38XX) | ||
| 101 | || OCTEON_IS_MODEL(OCTEON_CN58XX) | ||
| 102 | || OCTEON_IS_MODEL(OCTEON_CN56XX); | ||
| 103 | case OCTEON_FEATURE_TRA: | ||
| 104 | return !(OCTEON_IS_MODEL(OCTEON_CN30XX) | ||
| 105 | || OCTEON_IS_MODEL(OCTEON_CN50XX)); | ||
| 106 | case OCTEON_FEATURE_MGMT_PORT: | ||
| 107 | return OCTEON_IS_MODEL(OCTEON_CN56XX) | ||
| 108 | || OCTEON_IS_MODEL(OCTEON_CN52XX); | ||
| 109 | case OCTEON_FEATURE_RAID: | ||
| 110 | return OCTEON_IS_MODEL(OCTEON_CN56XX) | ||
| 111 | || OCTEON_IS_MODEL(OCTEON_CN52XX); | ||
| 112 | case OCTEON_FEATURE_USB: | ||
| 113 | return !(OCTEON_IS_MODEL(OCTEON_CN38XX) | ||
| 114 | || OCTEON_IS_MODEL(OCTEON_CN58XX)); | ||
| 115 | } | ||
| 116 | return 0; | ||
| 117 | } | ||
| 118 | |||
| 119 | #endif /* __OCTEON_FEATURE_H__ */ | ||
diff --git a/arch/mips/include/asm/octeon/octeon-model.h b/arch/mips/include/asm/octeon/octeon-model.h new file mode 100644 index 000000000000..cf50336eca2e --- /dev/null +++ b/arch/mips/include/asm/octeon/octeon-model.h | |||
| @@ -0,0 +1,321 @@ | |||
| 1 | /***********************license start*************** | ||
| 2 | * Author: Cavium Networks | ||
| 3 | * | ||
| 4 | * Contact: support@caviumnetworks.com | ||
| 5 | * This file is part of the OCTEON SDK | ||
| 6 | * | ||
| 7 | * Copyright (c) 2003-2008 Cavium Networks | ||
| 8 | * | ||
| 9 | * This file is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License, Version 2, as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | * | ||
| 13 | * This file is distributed in the hope that it will be useful, but | ||
| 14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
| 15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
| 16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
| 17 | * details. | ||
| 18 | * | ||
| 19 | * You should have received a copy of the GNU General Public License | ||
| 20 | * along with this file; if not, write to the Free Software | ||
| 21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 22 | * or visit http://www.gnu.org/licenses/. | ||
| 23 | * | ||
| 24 | * This file may also be available under a different license from Cavium. | ||
| 25 | * Contact Cavium Networks for more information | ||
| 26 | ***********************license end**************************************/ | ||
| 27 | |||
| 28 | /* | ||
| 29 | * | ||
| 30 | * File defining different Octeon model IDs and macros to | ||
| 31 | * compare them. | ||
| 32 | * | ||
| 33 | */ | ||
| 34 | |||
| 35 | #ifndef __OCTEON_MODEL_H__ | ||
| 36 | #define __OCTEON_MODEL_H__ | ||
| 37 | |||
| 38 | /* NOTE: These must match what is checked in common-config.mk */ | ||
| 39 | /* Defines to represent the different versions of Octeon. */ | ||
| 40 | |||
| 41 | /* | ||
| 42 | * IMPORTANT: When the default pass is updated for an Octeon Model, | ||
| 43 | * the corresponding change must also be made in the oct-sim script. | ||
| 44 | */ | ||
| 45 | |||
| 46 | /* | ||
| 47 | * The defines below should be used with the OCTEON_IS_MODEL() macro | ||
| 48 | * to determine what model of chip the software is running on. Models | ||
| 49 | * ending in 'XX' match multiple models (families), while specific | ||
| 50 | * models match only that model. If a pass (revision) is specified, | ||
| 51 | * then only that revision will be matched. Care should be taken when | ||
| 52 | * checking for both specific models and families that the specific | ||
| 53 | * models are checked for first. While these defines are similar to | ||
| 54 | * the processor ID, they are not intended to be used by anything | ||
| 55 | * other that the OCTEON_IS_MODEL framework, and the values are | ||
| 56 | * subject to change at anytime without notice. | ||
| 57 | * | ||
| 58 | * NOTE: only the OCTEON_IS_MODEL() macro/function and the OCTEON_CN* | ||
| 59 | * macros should be used outside of this file. All other macros are | ||
| 60 | * for internal use only, and may change without notice. | ||
| 61 | */ | ||
| 62 | |||
| 63 | /* Flag bits in top byte */ | ||
| 64 | /* Ignores revision in model checks */ | ||
| 65 | #define OM_IGNORE_REVISION 0x01000000 | ||
| 66 | /* Check submodels */ | ||
| 67 | #define OM_CHECK_SUBMODEL 0x02000000 | ||
| 68 | /* Match all models previous than the one specified */ | ||
| 69 | #define OM_MATCH_PREVIOUS_MODELS 0x04000000 | ||
| 70 | /* Ignores the minor revison on newer parts */ | ||
| 71 | #define OM_IGNORE_MINOR_REVISION 0x08000000 | ||
| 72 | #define OM_FLAG_MASK 0xff000000 | ||
| 73 | |||
| 74 | /* | ||
| 75 | * CN5XXX models with new revision encoding | ||
| 76 | */ | ||
| 77 | #define OCTEON_CN58XX_PASS1_0 0x000d0300 | ||
| 78 | #define OCTEON_CN58XX_PASS1_1 0x000d0301 | ||
| 79 | #define OCTEON_CN58XX_PASS1_2 0x000d0303 | ||
| 80 | #define OCTEON_CN58XX_PASS2_0 0x000d0308 | ||
| 81 | #define OCTEON_CN58XX_PASS2_1 0x000d0309 | ||
| 82 | #define OCTEON_CN58XX_PASS2_2 0x000d030a | ||
| 83 | #define OCTEON_CN58XX_PASS2_3 0x000d030b | ||
| 84 | |||
| 85 | #define OCTEON_CN58XX (OCTEON_CN58XX_PASS1_0 | OM_IGNORE_REVISION) | ||
| 86 | #define OCTEON_CN58XX_PASS1_X (OCTEON_CN58XX_PASS1_0 \ | ||
| 87 | | OM_IGNORE_MINOR_REVISION) | ||
| 88 | #define OCTEON_CN58XX_PASS2_X (OCTEON_CN58XX_PASS2_0 \ | ||
| 89 | | OM_IGNORE_MINOR_REVISION) | ||
| 90 | #define OCTEON_CN58XX_PASS1 OCTEON_CN58XX_PASS1_X | ||
| 91 | #define OCTEON_CN58XX_PASS2 OCTEON_CN58XX_PASS2_X | ||
| 92 | |||
| 93 | #define OCTEON_CN56XX_PASS1_0 0x000d0400 | ||
| 94 | #define OCTEON_CN56XX_PASS1_1 0x000d0401 | ||
| 95 | #define OCTEON_CN56XX_PASS2_0 0x000d0408 | ||
| 96 | #define OCTEON_CN56XX_PASS2_1 0x000d0409 | ||
| 97 | |||
| 98 | #define OCTEON_CN56XX (OCTEON_CN56XX_PASS2_0 | OM_IGNORE_REVISION) | ||
| 99 | #define OCTEON_CN56XX_PASS1_X (OCTEON_CN56XX_PASS1_0 \ | ||
| 100 | | OM_IGNORE_MINOR_REVISION) | ||
| 101 | #define OCTEON_CN56XX_PASS2_X (OCTEON_CN56XX_PASS2_0 \ | ||
| 102 | | OM_IGNORE_MINOR_REVISION) | ||
| 103 | #define OCTEON_CN56XX_PASS1 OCTEON_CN56XX_PASS1_X | ||
| 104 | #define OCTEON_CN56XX_PASS2 OCTEON_CN56XX_PASS2_X | ||
| 105 | |||
| 106 | #define OCTEON_CN57XX OCTEON_CN56XX | ||
| 107 | #define OCTEON_CN57XX_PASS1 OCTEON_CN56XX_PASS1 | ||
| 108 | #define OCTEON_CN57XX_PASS2 OCTEON_CN56XX_PASS2 | ||
| 109 | |||
| 110 | #define OCTEON_CN55XX OCTEON_CN56XX | ||
| 111 | #define OCTEON_CN55XX_PASS1 OCTEON_CN56XX_PASS1 | ||
| 112 | #define OCTEON_CN55XX_PASS2 OCTEON_CN56XX_PASS2 | ||
| 113 | |||
| 114 | #define OCTEON_CN54XX OCTEON_CN56XX | ||
| 115 | #define OCTEON_CN54XX_PASS1 OCTEON_CN56XX_PASS1 | ||
| 116 | #define OCTEON_CN54XX_PASS2 OCTEON_CN56XX_PASS2 | ||
| 117 | |||
| 118 | #define OCTEON_CN50XX_PASS1_0 0x000d0600 | ||
| 119 | |||
| 120 | #define OCTEON_CN50XX (OCTEON_CN50XX_PASS1_0 | OM_IGNORE_REVISION) | ||
| 121 | #define OCTEON_CN50XX_PASS1_X (OCTEON_CN50XX_PASS1_0 \ | ||
| 122 | | OM_IGNORE_MINOR_REVISION) | ||
| 123 | #define OCTEON_CN50XX_PASS1 OCTEON_CN50XX_PASS1_X | ||
| 124 | |||
| 125 | /* | ||
| 126 | * NOTE: Octeon CN5000F model is not identifiable using the | ||
| 127 | * OCTEON_IS_MODEL() functions, but are treated as CN50XX. | ||
| 128 | */ | ||
| 129 | |||
| 130 | #define OCTEON_CN52XX_PASS1_0 0x000d0700 | ||
| 131 | #define OCTEON_CN52XX_PASS2_0 0x000d0708 | ||
| 132 | |||
| 133 | #define OCTEON_CN52XX (OCTEON_CN52XX_PASS2_0 | OM_IGNORE_REVISION) | ||
| 134 | #define OCTEON_CN52XX_PASS1_X (OCTEON_CN52XX_PASS1_0 \ | ||
| 135 | | OM_IGNORE_MINOR_REVISION) | ||
| 136 | #define OCTEON_CN52XX_PASS2_X (OCTEON_CN52XX_PASS2_0 \ | ||
| 137 | | OM_IGNORE_MINOR_REVISION) | ||
| 138 | #define OCTEON_CN52XX_PASS1 OCTEON_CN52XX_PASS1_X | ||
| 139 | #define OCTEON_CN52XX_PASS2 OCTEON_CN52XX_PASS2_X | ||
| 140 | |||
| 141 | /* | ||
| 142 | * CN3XXX models with old revision enconding | ||
| 143 | */ | ||
| 144 | #define OCTEON_CN38XX_PASS1 0x000d0000 | ||
| 145 | #define OCTEON_CN38XX_PASS2 0x000d0001 | ||
| 146 | #define OCTEON_CN38XX_PASS3 0x000d0003 | ||
| 147 | #define OCTEON_CN38XX (OCTEON_CN38XX_PASS3 | OM_IGNORE_REVISION) | ||
| 148 | |||
| 149 | #define OCTEON_CN36XX OCTEON_CN38XX | ||
| 150 | #define OCTEON_CN36XX_PASS2 OCTEON_CN38XX_PASS2 | ||
| 151 | #define OCTEON_CN36XX_PASS3 OCTEON_CN38XX_PASS3 | ||
| 152 | |||
| 153 | /* The OCTEON_CN31XX matches CN31XX models and the CN3020 */ | ||
| 154 | #define OCTEON_CN31XX_PASS1 0x000d0100 | ||
| 155 | #define OCTEON_CN31XX_PASS1_1 0x000d0102 | ||
| 156 | #define OCTEON_CN31XX (OCTEON_CN31XX_PASS1 | OM_IGNORE_REVISION) | ||
| 157 | |||
| 158 | /* | ||
| 159 | * This model is only used for internal checks, it is not a valid | ||
| 160 | * model for the OCTEON_MODEL environment variable. This matches the | ||
| 161 | * CN3010 and CN3005 but NOT the CN3020. | ||
| 162 | */ | ||
| 163 | #define OCTEON_CN30XX_PASS1 0x000d0200 | ||
| 164 | #define OCTEON_CN30XX_PASS1_1 0x000d0202 | ||
| 165 | #define OCTEON_CN30XX (OCTEON_CN30XX_PASS1 | OM_IGNORE_REVISION) | ||
| 166 | |||
| 167 | #define OCTEON_CN3005_PASS1 (0x000d0210 | OM_CHECK_SUBMODEL) | ||
| 168 | #define OCTEON_CN3005_PASS1_0 (0x000d0210 | OM_CHECK_SUBMODEL) | ||
| 169 | #define OCTEON_CN3005_PASS1_1 (0x000d0212 | OM_CHECK_SUBMODEL) | ||
| 170 | #define OCTEON_CN3005 (OCTEON_CN3005_PASS1 | OM_IGNORE_REVISION \ | ||
| 171 | | OM_CHECK_SUBMODEL) | ||
| 172 | |||
| 173 | #define OCTEON_CN3010_PASS1 (0x000d0200 | OM_CHECK_SUBMODEL) | ||
| 174 | #define OCTEON_CN3010_PASS1_0 (0x000d0200 | OM_CHECK_SUBMODEL) | ||
| 175 | #define OCTEON_CN3010_PASS1_1 (0x000d0202 | OM_CHECK_SUBMODEL) | ||
| 176 | #define OCTEON_CN3010 (OCTEON_CN3010_PASS1 | OM_IGNORE_REVISION \ | ||
| 177 | | OM_CHECK_SUBMODEL) | ||
| 178 | |||
| 179 | #define OCTEON_CN3020_PASS1 (0x000d0110 | OM_CHECK_SUBMODEL) | ||
| 180 | #define OCTEON_CN3020_PASS1_0 (0x000d0110 | OM_CHECK_SUBMODEL) | ||
| 181 | #define OCTEON_CN3020_PASS1_1 (0x000d0112 | OM_CHECK_SUBMODEL) | ||
| 182 | #define OCTEON_CN3020 (OCTEON_CN3020_PASS1 | OM_IGNORE_REVISION \ | ||
| 183 | | OM_CHECK_SUBMODEL) | ||
| 184 | |||
| 185 | |||
| 186 | |||
| 187 | /* This matches the complete family of CN3xxx CPUs, and not subsequent models */ | ||
| 188 | #define OCTEON_CN3XXX (OCTEON_CN58XX_PASS1_0 \ | ||
| 189 | | OM_MATCH_PREVIOUS_MODELS \ | ||
| 190 | | OM_IGNORE_REVISION) | ||
| 191 | |||
| 192 | /* The revision byte (low byte) has two different encodings. | ||
| 193 | * CN3XXX: | ||
| 194 | * | ||
| 195 | * bits | ||
| 196 | * <7:5>: reserved (0) | ||
| 197 | * <4>: alternate package | ||
| 198 | * <3:0>: revision | ||
| 199 | * | ||
| 200 | * CN5XXX: | ||
| 201 | * | ||
| 202 | * bits | ||
| 203 | * <7>: reserved (0) | ||
| 204 | * <6>: alternate package | ||
| 205 | * <5:3>: major revision | ||
| 206 | * <2:0>: minor revision | ||
| 207 | * | ||
| 208 | */ | ||
| 209 | |||
| 210 | /* Masks used for the various types of model/family/revision matching */ | ||
| 211 | #define OCTEON_38XX_FAMILY_MASK 0x00ffff00 | ||
| 212 | #define OCTEON_38XX_FAMILY_REV_MASK 0x00ffff0f | ||
| 213 | #define OCTEON_38XX_MODEL_MASK 0x00ffff10 | ||
| 214 | #define OCTEON_38XX_MODEL_REV_MASK (OCTEON_38XX_FAMILY_REV_MASK \ | ||
| 215 | | OCTEON_38XX_MODEL_MASK) | ||
| 216 | |||
| 217 | /* CN5XXX and later use different layout of bits in the revision ID field */ | ||
| 218 | #define OCTEON_58XX_FAMILY_MASK OCTEON_38XX_FAMILY_MASK | ||
| 219 | #define OCTEON_58XX_FAMILY_REV_MASK 0x00ffff3f | ||
| 220 | #define OCTEON_58XX_MODEL_MASK 0x00ffffc0 | ||
| 221 | #define OCTEON_58XX_MODEL_REV_MASK (OCTEON_58XX_FAMILY_REV_MASK \ | ||
| 222 | | OCTEON_58XX_MODEL_MASK) | ||
| 223 | #define OCTEON_58XX_MODEL_MINOR_REV_MASK (OCTEON_58XX_MODEL_REV_MASK \ | ||
| 224 | & 0x00fffff8) | ||
| 225 | |||
| 226 | #define __OCTEON_MATCH_MASK__(x, y, z) (((x) & (z)) == ((y) & (z))) | ||
| 227 | |||
| 228 | /* NOTE: This is for internal (to this file) use only. */ | ||
| 229 | static inline int __OCTEON_IS_MODEL_COMPILE__(uint32_t arg_model, | ||
| 230 | uint32_t chip_model) | ||
| 231 | { | ||
| 232 | uint32_t rev_and_sub = OM_IGNORE_REVISION | OM_CHECK_SUBMODEL; | ||
| 233 | |||
| 234 | if ((arg_model & OCTEON_38XX_FAMILY_MASK) < OCTEON_CN58XX_PASS1_0) { | ||
| 235 | if (((arg_model & OM_FLAG_MASK) == rev_and_sub) && | ||
| 236 | __OCTEON_MATCH_MASK__(chip_model, arg_model, | ||
| 237 | OCTEON_38XX_MODEL_MASK)) | ||
| 238 | return 1; | ||
| 239 | if (((arg_model & OM_FLAG_MASK) == 0) && | ||
| 240 | __OCTEON_MATCH_MASK__(chip_model, arg_model, | ||
| 241 | OCTEON_38XX_FAMILY_REV_MASK)) | ||
| 242 | return 1; | ||
| 243 | if (((arg_model & OM_FLAG_MASK) == OM_IGNORE_REVISION) && | ||
| 244 | __OCTEON_MATCH_MASK__(chip_model, arg_model, | ||
| 245 | OCTEON_38XX_FAMILY_MASK)) | ||
| 246 | return 1; | ||
| 247 | if (((arg_model & OM_FLAG_MASK) == OM_CHECK_SUBMODEL) && | ||
| 248 | __OCTEON_MATCH_MASK__((chip_model), (arg_model), | ||
| 249 | OCTEON_38XX_MODEL_REV_MASK)) | ||
| 250 | return 1; | ||
| 251 | if ((arg_model & OM_MATCH_PREVIOUS_MODELS) && | ||
| 252 | ((chip_model & OCTEON_38XX_MODEL_MASK) < | ||
| 253 | (arg_model & OCTEON_38XX_MODEL_MASK))) | ||
| 254 | return 1; | ||
| 255 | } else { | ||
| 256 | if (((arg_model & OM_FLAG_MASK) == rev_and_sub) && | ||
| 257 | __OCTEON_MATCH_MASK__((chip_model), (arg_model), | ||
| 258 | OCTEON_58XX_MODEL_MASK)) | ||
| 259 | return 1; | ||
| 260 | if (((arg_model & OM_FLAG_MASK) == 0) && | ||
| 261 | __OCTEON_MATCH_MASK__((chip_model), (arg_model), | ||
| 262 | OCTEON_58XX_FAMILY_REV_MASK)) | ||
| 263 | return 1; | ||
| 264 | if (((arg_model & OM_FLAG_MASK) == OM_IGNORE_MINOR_REVISION) && | ||
| 265 | __OCTEON_MATCH_MASK__((chip_model), (arg_model), | ||
| 266 | OCTEON_58XX_MODEL_MINOR_REV_MASK)) | ||
| 267 | return 1; | ||
| 268 | if (((arg_model & OM_FLAG_MASK) == OM_IGNORE_REVISION) && | ||
| 269 | __OCTEON_MATCH_MASK__((chip_model), (arg_model), | ||
| 270 | OCTEON_58XX_FAMILY_MASK)) | ||
| 271 | return 1; | ||
| 272 | if (((arg_model & OM_FLAG_MASK) == OM_CHECK_SUBMODEL) && | ||
| 273 | __OCTEON_MATCH_MASK__((chip_model), (arg_model), | ||
| 274 | OCTEON_58XX_MODEL_REV_MASK)) | ||
| 275 | return 1; | ||
| 276 | if ((arg_model & OM_MATCH_PREVIOUS_MODELS) && | ||
| 277 | ((chip_model & OCTEON_58XX_MODEL_MASK) < | ||
| 278 | (arg_model & OCTEON_58XX_MODEL_MASK))) | ||
| 279 | return 1; | ||
| 280 | } | ||
| 281 | return 0; | ||
| 282 | } | ||
| 283 | |||
| 284 | /* forward declarations */ | ||
| 285 | static inline uint32_t cvmx_get_proc_id(void) __attribute__ ((pure)); | ||
| 286 | static inline uint64_t cvmx_read_csr(uint64_t csr_addr); | ||
| 287 | |||
| 288 | /* NOTE: This for internal use only!!!!! */ | ||
| 289 | static inline int __octeon_is_model_runtime__(uint32_t model) | ||
| 290 | { | ||
| 291 | uint32_t cpuid = cvmx_get_proc_id(); | ||
| 292 | |||
| 293 | /* | ||
| 294 | * Check for special case of mismarked 3005 samples. We only | ||
| 295 | * need to check if the sub model isn't being ignored. | ||
| 296 | */ | ||
| 297 | if ((model & OM_CHECK_SUBMODEL) == OM_CHECK_SUBMODEL) { | ||
| 298 | if (cpuid == OCTEON_CN3010_PASS1 \ | ||
| 299 | && (cvmx_read_csr(0x80011800800007B8ull) & (1ull << 34))) | ||
| 300 | cpuid |= 0x10; | ||
| 301 | } | ||
| 302 | return __OCTEON_IS_MODEL_COMPILE__(model, cpuid); | ||
| 303 | } | ||
| 304 | |||
| 305 | /* | ||
| 306 | * The OCTEON_IS_MODEL macro should be used for all Octeon model | ||
| 307 | * checking done in a program. This should be kept runtime if at all | ||
| 308 | * possible. Any compile time (#if OCTEON_IS_MODEL) usage must be | ||
| 309 | * condtionalized with OCTEON_IS_COMMON_BINARY() if runtime checking | ||
| 310 | * support is required. | ||
| 311 | */ | ||
| 312 | #define OCTEON_IS_MODEL(x) __octeon_is_model_runtime__(x) | ||
| 313 | #define OCTEON_IS_COMMON_BINARY() 1 | ||
| 314 | #undef OCTEON_MODEL | ||
| 315 | |||
| 316 | const char *octeon_model_get_string(uint32_t chip_id); | ||
| 317 | const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer); | ||
| 318 | |||
| 319 | #include "octeon-feature.h" | ||
| 320 | |||
| 321 | #endif /* __OCTEON_MODEL_H__ */ | ||
diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h new file mode 100644 index 000000000000..edc676084cda --- /dev/null +++ b/arch/mips/include/asm/octeon/octeon.h | |||
| @@ -0,0 +1,248 @@ | |||
| 1 | /* | ||
| 2 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 3 | * License. See the file "COPYING" in the main directory of this archive | ||
| 4 | * for more details. | ||
| 5 | * | ||
| 6 | * Copyright (C) 2004-2008 Cavium Networks | ||
| 7 | */ | ||
| 8 | #ifndef __ASM_OCTEON_OCTEON_H | ||
| 9 | #define __ASM_OCTEON_OCTEON_H | ||
| 10 | |||
| 11 | #include "cvmx.h" | ||
| 12 | |||
| 13 | extern uint64_t octeon_bootmem_alloc_range_phys(uint64_t size, | ||
| 14 | uint64_t alignment, | ||
| 15 | uint64_t min_addr, | ||
| 16 | uint64_t max_addr, | ||
| 17 | int do_locking); | ||
| 18 | extern void *octeon_bootmem_alloc(uint64_t size, uint64_t alignment, | ||
| 19 | int do_locking); | ||
| 20 | extern void *octeon_bootmem_alloc_range(uint64_t size, uint64_t alignment, | ||
| 21 | uint64_t min_addr, uint64_t max_addr, | ||
| 22 | int do_locking); | ||
| 23 | extern void *octeon_bootmem_alloc_named(uint64_t size, uint64_t alignment, | ||
| 24 | char *name); | ||
| 25 | extern void *octeon_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr, | ||
| 26 | uint64_t max_addr, uint64_t align, | ||
| 27 | char *name); | ||
| 28 | extern void *octeon_bootmem_alloc_named_address(uint64_t size, uint64_t address, | ||
| 29 | char *name); | ||
| 30 | extern int octeon_bootmem_free_named(char *name); | ||
| 31 | extern void octeon_bootmem_lock(void); | ||
| 32 | extern void octeon_bootmem_unlock(void); | ||
| 33 | |||
| 34 | extern int octeon_is_simulation(void); | ||
| 35 | extern int octeon_is_pci_host(void); | ||
| 36 | extern int octeon_usb_is_ref_clk(void); | ||
| 37 | extern uint64_t octeon_get_clock_rate(void); | ||
| 38 | extern const char *octeon_board_type_string(void); | ||
| 39 | extern const char *octeon_get_pci_interrupts(void); | ||
| 40 | extern int octeon_get_southbridge_interrupt(void); | ||
| 41 | extern int octeon_get_boot_coremask(void); | ||
| 42 | extern int octeon_get_boot_num_arguments(void); | ||
| 43 | extern const char *octeon_get_boot_argument(int arg); | ||
| 44 | extern void octeon_hal_setup_reserved32(void); | ||
| 45 | extern void octeon_user_io_init(void); | ||
| 46 | struct octeon_cop2_state; | ||
| 47 | extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *state); | ||
| 48 | extern void octeon_crypto_disable(struct octeon_cop2_state *state, | ||
| 49 | unsigned long flags); | ||
| 50 | |||
| 51 | extern void octeon_init_cvmcount(void); | ||
| 52 | |||
| 53 | #define OCTEON_ARGV_MAX_ARGS 64 | ||
| 54 | #define OCTOEN_SERIAL_LEN 20 | ||
| 55 | |||
| 56 | struct octeon_boot_descriptor { | ||
| 57 | /* Start of block referenced by assembly code - do not change! */ | ||
| 58 | uint32_t desc_version; | ||
| 59 | uint32_t desc_size; | ||
| 60 | uint64_t stack_top; | ||
| 61 | uint64_t heap_base; | ||
| 62 | uint64_t heap_end; | ||
| 63 | /* Only used by bootloader */ | ||
| 64 | uint64_t entry_point; | ||
| 65 | uint64_t desc_vaddr; | ||
| 66 | /* End of This block referenced by assembly code - do not change! */ | ||
| 67 | uint32_t exception_base_addr; | ||
| 68 | uint32_t stack_size; | ||
| 69 | uint32_t heap_size; | ||
| 70 | /* Argc count for application. */ | ||
| 71 | uint32_t argc; | ||
| 72 | uint32_t argv[OCTEON_ARGV_MAX_ARGS]; | ||
| 73 | |||
| 74 | #define BOOT_FLAG_INIT_CORE (1 << 0) | ||
| 75 | #define OCTEON_BL_FLAG_DEBUG (1 << 1) | ||
| 76 | #define OCTEON_BL_FLAG_NO_MAGIC (1 << 2) | ||
| 77 | /* If set, use uart1 for console */ | ||
| 78 | #define OCTEON_BL_FLAG_CONSOLE_UART1 (1 << 3) | ||
| 79 | /* If set, use PCI console */ | ||
| 80 | #define OCTEON_BL_FLAG_CONSOLE_PCI (1 << 4) | ||
| 81 | /* Call exit on break on serial port */ | ||
| 82 | #define OCTEON_BL_FLAG_BREAK (1 << 5) | ||
| 83 | |||
| 84 | uint32_t flags; | ||
| 85 | uint32_t core_mask; | ||
| 86 | /* DRAM size in megabyes. */ | ||
| 87 | uint32_t dram_size; | ||
| 88 | /* physical address of free memory descriptor block. */ | ||
| 89 | uint32_t phy_mem_desc_addr; | ||
| 90 | /* used to pass flags from app to debugger. */ | ||
| 91 | uint32_t debugger_flags_base_addr; | ||
| 92 | /* CPU clock speed, in hz. */ | ||
| 93 | uint32_t eclock_hz; | ||
| 94 | /* DRAM clock speed, in hz. */ | ||
| 95 | uint32_t dclock_hz; | ||
| 96 | /* SPI4 clock in hz. */ | ||
| 97 | uint32_t spi_clock_hz; | ||
| 98 | uint16_t board_type; | ||
| 99 | uint8_t board_rev_major; | ||
| 100 | uint8_t board_rev_minor; | ||
| 101 | uint16_t chip_type; | ||
| 102 | uint8_t chip_rev_major; | ||
| 103 | uint8_t chip_rev_minor; | ||
| 104 | char board_serial_number[OCTOEN_SERIAL_LEN]; | ||
| 105 | uint8_t mac_addr_base[6]; | ||
| 106 | uint8_t mac_addr_count; | ||
| 107 | uint64_t cvmx_desc_vaddr; | ||
| 108 | }; | ||
| 109 | |||
| 110 | union octeon_cvmemctl { | ||
| 111 | uint64_t u64; | ||
| 112 | struct { | ||
| 113 | /* RO 1 = BIST fail, 0 = BIST pass */ | ||
| 114 | uint64_t tlbbist:1; | ||
| 115 | /* RO 1 = BIST fail, 0 = BIST pass */ | ||
| 116 | uint64_t l1cbist:1; | ||
| 117 | /* RO 1 = BIST fail, 0 = BIST pass */ | ||
| 118 | uint64_t l1dbist:1; | ||
| 119 | /* RO 1 = BIST fail, 0 = BIST pass */ | ||
| 120 | uint64_t dcmbist:1; | ||
| 121 | /* RO 1 = BIST fail, 0 = BIST pass */ | ||
| 122 | uint64_t ptgbist:1; | ||
| 123 | /* RO 1 = BIST fail, 0 = BIST pass */ | ||
| 124 | uint64_t wbfbist:1; | ||
| 125 | /* Reserved */ | ||
| 126 | uint64_t reserved:22; | ||
| 127 | /* R/W If set, marked write-buffer entries time out | ||
| 128 | * the same as as other entries; if clear, marked | ||
| 129 | * write-buffer entries use the maximum timeout. */ | ||
| 130 | uint64_t dismarkwblongto:1; | ||
| 131 | /* R/W If set, a merged store does not clear the | ||
| 132 | * write-buffer entry timeout state. */ | ||
| 133 | uint64_t dismrgclrwbto:1; | ||
| 134 | /* R/W Two bits that are the MSBs of the resultant | ||
| 135 | * CVMSEG LM word location for an IOBDMA. The other 8 | ||
| 136 | * bits come from the SCRADDR field of the IOBDMA. */ | ||
| 137 | uint64_t iobdmascrmsb:2; | ||
| 138 | /* R/W If set, SYNCWS and SYNCS only order marked | ||
| 139 | * stores; if clear, SYNCWS and SYNCS only order | ||
| 140 | * unmarked stores. SYNCWSMARKED has no effect when | ||
| 141 | * DISSYNCWS is set. */ | ||
| 142 | uint64_t syncwsmarked:1; | ||
| 143 | /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as | ||
| 144 | * SYNC. */ | ||
| 145 | uint64_t dissyncws:1; | ||
| 146 | /* R/W If set, no stall happens on write buffer | ||
| 147 | * full. */ | ||
| 148 | uint64_t diswbfst:1; | ||
| 149 | /* R/W If set (and SX set), supervisor-level | ||
| 150 | * loads/stores can use XKPHYS addresses with | ||
| 151 | * VA<48>==0 */ | ||
| 152 | uint64_t xkmemenas:1; | ||
| 153 | /* R/W If set (and UX set), user-level loads/stores | ||
| 154 | * can use XKPHYS addresses with VA<48>==0 */ | ||
| 155 | uint64_t xkmemenau:1; | ||
| 156 | /* R/W If set (and SX set), supervisor-level | ||
| 157 | * loads/stores can use XKPHYS addresses with | ||
| 158 | * VA<48>==1 */ | ||
| 159 | uint64_t xkioenas:1; | ||
| 160 | /* R/W If set (and UX set), user-level loads/stores | ||
| 161 | * can use XKPHYS addresses with VA<48>==1 */ | ||
| 162 | uint64_t xkioenau:1; | ||
| 163 | /* R/W If set, all stores act as SYNCW (NOMERGE must | ||
| 164 | * be set when this is set) RW, reset to 0. */ | ||
| 165 | uint64_t allsyncw:1; | ||
| 166 | /* R/W If set, no stores merge, and all stores reach | ||
| 167 | * the coherent bus in order. */ | ||
| 168 | uint64_t nomerge:1; | ||
| 169 | /* R/W Selects the bit in the counter used for DID | ||
| 170 | * time-outs 0 = 231, 1 = 230, 2 = 229, 3 = | ||
| 171 | * 214. Actual time-out is between 1x and 2x this | ||
| 172 | * interval. For example, with DIDTTO=3, expiration | ||
| 173 | * interval is between 16K and 32K. */ | ||
| 174 | uint64_t didtto:2; | ||
| 175 | /* R/W If set, the (mem) CSR clock never turns off. */ | ||
| 176 | uint64_t csrckalwys:1; | ||
| 177 | /* R/W If set, mclk never turns off. */ | ||
| 178 | uint64_t mclkalwys:1; | ||
| 179 | /* R/W Selects the bit in the counter used for write | ||
| 180 | * buffer flush time-outs (WBFLT+11) is the bit | ||
| 181 | * position in an internal counter used to determine | ||
| 182 | * expiration. The write buffer expires between 1x and | ||
| 183 | * 2x this interval. For example, with WBFLT = 0, a | ||
| 184 | * write buffer expires between 2K and 4K cycles after | ||
| 185 | * the write buffer entry is allocated. */ | ||
| 186 | uint64_t wbfltime:3; | ||
| 187 | /* R/W If set, do not put Istream in the L2 cache. */ | ||
| 188 | uint64_t istrnol2:1; | ||
| 189 | /* R/W The write buffer threshold. */ | ||
| 190 | uint64_t wbthresh:4; | ||
| 191 | /* Reserved */ | ||
| 192 | uint64_t reserved2:2; | ||
| 193 | /* R/W If set, CVMSEG is available for loads/stores in | ||
| 194 | * kernel/debug mode. */ | ||
| 195 | uint64_t cvmsegenak:1; | ||
| 196 | /* R/W If set, CVMSEG is available for loads/stores in | ||
| 197 | * supervisor mode. */ | ||
| 198 | uint64_t cvmsegenas:1; | ||
| 199 | /* R/W If set, CVMSEG is available for loads/stores in | ||
| 200 | * user mode. */ | ||
| 201 | uint64_t cvmsegenau:1; | ||
| 202 | /* R/W Size of local memory in cache blocks, 54 (6912 | ||
| 203 | * bytes) is max legal value. */ | ||
| 204 | uint64_t lmemsz:6; | ||
| 205 | } s; | ||
| 206 | }; | ||
| 207 | |||
| 208 | struct octeon_cf_data { | ||
| 209 | unsigned long base_region_bias; | ||
| 210 | unsigned int base_region; /* The chip select region used by CF */ | ||
| 211 | int is16bit; /* 0 - 8bit, !0 - 16bit */ | ||
| 212 | int dma_engine; /* -1 for no DMA */ | ||
| 213 | }; | ||
| 214 | |||
| 215 | extern void octeon_write_lcd(const char *s); | ||
| 216 | extern void octeon_check_cpu_bist(void); | ||
| 217 | extern int octeon_get_boot_debug_flag(void); | ||
| 218 | extern int octeon_get_boot_uart(void); | ||
| 219 | |||
| 220 | struct uart_port; | ||
| 221 | extern unsigned int octeon_serial_in(struct uart_port *, int); | ||
| 222 | extern void octeon_serial_out(struct uart_port *, int, int); | ||
| 223 | |||
| 224 | /** | ||
| 225 | * Write a 32bit value to the Octeon NPI register space | ||
| 226 | * | ||
| 227 | * @address: Address to write to | ||
| 228 | * @val: Value to write | ||
| 229 | */ | ||
| 230 | static inline void octeon_npi_write32(uint64_t address, uint32_t val) | ||
| 231 | { | ||
| 232 | cvmx_write64_uint32(address ^ 4, val); | ||
| 233 | cvmx_read64_uint32(address ^ 4); | ||
| 234 | } | ||
| 235 | |||
| 236 | |||
| 237 | /** | ||
| 238 | * Read a 32bit value from the Octeon NPI register space | ||
| 239 | * | ||
| 240 | * @address: Address to read | ||
| 241 | * Returns The result | ||
| 242 | */ | ||
| 243 | static inline uint32_t octeon_npi_read32(uint64_t address) | ||
| 244 | { | ||
| 245 | return cvmx_read64_uint32(address ^ 4); | ||
| 246 | } | ||
| 247 | |||
| 248 | #endif /* __ASM_OCTEON_OCTEON_H */ | ||
diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h index 18ee58e39445..0f926aa0cb47 100644 --- a/arch/mips/include/asm/processor.h +++ b/arch/mips/include/asm/processor.h | |||
| @@ -118,6 +118,60 @@ union mips_watch_reg_state { | |||
| 118 | struct mips3264_watch_reg_state mips3264; | 118 | struct mips3264_watch_reg_state mips3264; |
| 119 | }; | 119 | }; |
| 120 | 120 | ||
| 121 | #ifdef CONFIG_CPU_CAVIUM_OCTEON | ||
| 122 | |||
| 123 | struct octeon_cop2_state { | ||
| 124 | /* DMFC2 rt, 0x0201 */ | ||
| 125 | unsigned long cop2_crc_iv; | ||
| 126 | /* DMFC2 rt, 0x0202 (Set with DMTC2 rt, 0x1202) */ | ||
| 127 | unsigned long cop2_crc_length; | ||
| 128 | /* DMFC2 rt, 0x0200 (set with DMTC2 rt, 0x4200) */ | ||
| 129 | unsigned long cop2_crc_poly; | ||
| 130 | /* DMFC2 rt, 0x0402; DMFC2 rt, 0x040A */ | ||
| 131 | unsigned long cop2_llm_dat[2]; | ||
| 132 | /* DMFC2 rt, 0x0084 */ | ||
| 133 | unsigned long cop2_3des_iv; | ||
| 134 | /* DMFC2 rt, 0x0080; DMFC2 rt, 0x0081; DMFC2 rt, 0x0082 */ | ||
| 135 | unsigned long cop2_3des_key[3]; | ||
| 136 | /* DMFC2 rt, 0x0088 (Set with DMTC2 rt, 0x0098) */ | ||
| 137 | unsigned long cop2_3des_result; | ||
| 138 | /* DMFC2 rt, 0x0111 (FIXME: Read Pass1 Errata) */ | ||
| 139 | unsigned long cop2_aes_inp0; | ||
| 140 | /* DMFC2 rt, 0x0102; DMFC2 rt, 0x0103 */ | ||
| 141 | unsigned long cop2_aes_iv[2]; | ||
| 142 | /* DMFC2 rt, 0x0104; DMFC2 rt, 0x0105; DMFC2 rt, 0x0106; DMFC2 | ||
| 143 | * rt, 0x0107 */ | ||
| 144 | unsigned long cop2_aes_key[4]; | ||
| 145 | /* DMFC2 rt, 0x0110 */ | ||
| 146 | unsigned long cop2_aes_keylen; | ||
| 147 | /* DMFC2 rt, 0x0100; DMFC2 rt, 0x0101 */ | ||
| 148 | unsigned long cop2_aes_result[2]; | ||
| 149 | /* DMFC2 rt, 0x0240; DMFC2 rt, 0x0241; DMFC2 rt, 0x0242; DMFC2 | ||
| 150 | * rt, 0x0243; DMFC2 rt, 0x0244; DMFC2 rt, 0x0245; DMFC2 rt, | ||
| 151 | * 0x0246; DMFC2 rt, 0x0247; DMFC2 rt, 0x0248; DMFC2 rt, | ||
| 152 | * 0x0249; DMFC2 rt, 0x024A; DMFC2 rt, 0x024B; DMFC2 rt, | ||
| 153 | * 0x024C; DMFC2 rt, 0x024D; DMFC2 rt, 0x024E - Pass2 */ | ||
| 154 | unsigned long cop2_hsh_datw[15]; | ||
| 155 | /* DMFC2 rt, 0x0250; DMFC2 rt, 0x0251; DMFC2 rt, 0x0252; DMFC2 | ||
| 156 | * rt, 0x0253; DMFC2 rt, 0x0254; DMFC2 rt, 0x0255; DMFC2 rt, | ||
| 157 | * 0x0256; DMFC2 rt, 0x0257 - Pass2 */ | ||
| 158 | unsigned long cop2_hsh_ivw[8]; | ||
| 159 | /* DMFC2 rt, 0x0258; DMFC2 rt, 0x0259 - Pass2 */ | ||
| 160 | unsigned long cop2_gfm_mult[2]; | ||
| 161 | /* DMFC2 rt, 0x025E - Pass2 */ | ||
| 162 | unsigned long cop2_gfm_poly; | ||
| 163 | /* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */ | ||
| 164 | unsigned long cop2_gfm_result[2]; | ||
| 165 | }; | ||
| 166 | #define INIT_OCTEON_COP2 {0,} | ||
| 167 | |||
| 168 | struct octeon_cvmseg_state { | ||
| 169 | unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE] | ||
| 170 | [cpu_dcache_line_size() / sizeof(unsigned long)]; | ||
| 171 | }; | ||
| 172 | |||
| 173 | #endif | ||
| 174 | |||
| 121 | typedef struct { | 175 | typedef struct { |
| 122 | unsigned long seg; | 176 | unsigned long seg; |
| 123 | } mm_segment_t; | 177 | } mm_segment_t; |
| @@ -160,6 +214,10 @@ struct thread_struct { | |||
| 160 | unsigned long trap_no; | 214 | unsigned long trap_no; |
| 161 | unsigned long irix_trampoline; /* Wheee... */ | 215 | unsigned long irix_trampoline; /* Wheee... */ |
| 162 | unsigned long irix_oldctx; | 216 | unsigned long irix_oldctx; |
| 217 | #ifdef CONFIG_CPU_CAVIUM_OCTEON | ||
| 218 | struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128))); | ||
| 219 | struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128))); | ||
| 220 | #endif | ||
| 163 | struct mips_abi *abi; | 221 | struct mips_abi *abi; |
| 164 | }; | 222 | }; |
| 165 | 223 | ||
| @@ -171,6 +229,13 @@ struct thread_struct { | |||
| 171 | #define FPAFF_INIT | 229 | #define FPAFF_INIT |
| 172 | #endif /* CONFIG_MIPS_MT_FPAFF */ | 230 | #endif /* CONFIG_MIPS_MT_FPAFF */ |
| 173 | 231 | ||
| 232 | #ifdef CONFIG_CPU_CAVIUM_OCTEON | ||
| 233 | #define OCTEON_INIT \ | ||
| 234 | .cp2 = INIT_OCTEON_COP2, | ||
| 235 | #else | ||
| 236 | #define OCTEON_INIT | ||
| 237 | #endif /* CONFIG_CPU_CAVIUM_OCTEON */ | ||
| 238 | |||
| 174 | #define INIT_THREAD { \ | 239 | #define INIT_THREAD { \ |
| 175 | /* \ | 240 | /* \ |
| 176 | * Saved main processor registers \ | 241 | * Saved main processor registers \ |
| @@ -221,6 +286,10 @@ struct thread_struct { | |||
| 221 | .trap_no = 0, \ | 286 | .trap_no = 0, \ |
| 222 | .irix_trampoline = 0, \ | 287 | .irix_trampoline = 0, \ |
| 223 | .irix_oldctx = 0, \ | 288 | .irix_oldctx = 0, \ |
| 289 | /* \ | ||
| 290 | * Cavium Octeon specifics (null if not Octeon) \ | ||
| 291 | */ \ | ||
| 292 | OCTEON_INIT \ | ||
| 224 | } | 293 | } |
| 225 | 294 | ||
| 226 | struct task_struct; | 295 | struct task_struct; |
diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h index c2c8bac43307..1f30d16d4669 100644 --- a/arch/mips/include/asm/ptrace.h +++ b/arch/mips/include/asm/ptrace.h | |||
| @@ -48,6 +48,10 @@ struct pt_regs { | |||
| 48 | #ifdef CONFIG_MIPS_MT_SMTC | 48 | #ifdef CONFIG_MIPS_MT_SMTC |
| 49 | unsigned long cp0_tcstatus; | 49 | unsigned long cp0_tcstatus; |
| 50 | #endif /* CONFIG_MIPS_MT_SMTC */ | 50 | #endif /* CONFIG_MIPS_MT_SMTC */ |
| 51 | #ifdef CONFIG_CPU_CAVIUM_OCTEON | ||
| 52 | unsigned long long mpl[3]; /* MTM{0,1,2} */ | ||
| 53 | unsigned long long mtp[3]; /* MTP{0,1,2} */ | ||
| 54 | #endif | ||
| 51 | } __attribute__ ((aligned (8))); | 55 | } __attribute__ ((aligned (8))); |
| 52 | 56 | ||
| 53 | /* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ | 57 | /* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ |
diff --git a/arch/mips/include/asm/smp.h b/arch/mips/include/asm/smp.h index 86557b5d1b3f..40e5ef1d4d26 100644 --- a/arch/mips/include/asm/smp.h +++ b/arch/mips/include/asm/smp.h | |||
| @@ -37,6 +37,9 @@ extern int __cpu_logical_map[NR_CPUS]; | |||
| 37 | 37 | ||
| 38 | #define SMP_RESCHEDULE_YOURSELF 0x1 /* XXX braindead */ | 38 | #define SMP_RESCHEDULE_YOURSELF 0x1 /* XXX braindead */ |
| 39 | #define SMP_CALL_FUNCTION 0x2 | 39 | #define SMP_CALL_FUNCTION 0x2 |
| 40 | /* Octeon - Tell another core to flush its icache */ | ||
| 41 | #define SMP_ICACHE_FLUSH 0x4 | ||
| 42 | |||
| 40 | 43 | ||
| 41 | extern void asmlinkage smp_bootstrap(void); | 44 | extern void asmlinkage smp_bootstrap(void); |
| 42 | 45 | ||
diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h index 4c37c4e5f72e..db0fa7b5aeaf 100644 --- a/arch/mips/include/asm/stackframe.h +++ b/arch/mips/include/asm/stackframe.h | |||
| @@ -194,6 +194,19 @@ | |||
| 194 | LONG_S $31, PT_R31(sp) | 194 | LONG_S $31, PT_R31(sp) |
| 195 | ori $28, sp, _THREAD_MASK | 195 | ori $28, sp, _THREAD_MASK |
| 196 | xori $28, _THREAD_MASK | 196 | xori $28, _THREAD_MASK |
| 197 | #ifdef CONFIG_CPU_CAVIUM_OCTEON | ||
| 198 | .set mips64 | ||
| 199 | pref 0, 0($28) /* Prefetch the current pointer */ | ||
| 200 | pref 0, PT_R31(sp) /* Prefetch the $31(ra) */ | ||
| 201 | /* The Octeon multiplier state is affected by general multiply | ||
| 202 | instructions. It must be saved before and kernel code might | ||
| 203 | corrupt it */ | ||
| 204 | jal octeon_mult_save | ||
| 205 | LONG_L v1, 0($28) /* Load the current pointer */ | ||
| 206 | /* Restore $31(ra) that was changed by the jal */ | ||
| 207 | LONG_L ra, PT_R31(sp) | ||
| 208 | pref 0, 0(v1) /* Prefetch the current thread */ | ||
| 209 | #endif | ||
| 197 | .set pop | 210 | .set pop |
| 198 | .endm | 211 | .endm |
| 199 | 212 | ||
| @@ -324,6 +337,10 @@ | |||
| 324 | DVPE 5 # dvpe a1 | 337 | DVPE 5 # dvpe a1 |
| 325 | jal mips_ihb | 338 | jal mips_ihb |
| 326 | #endif /* CONFIG_MIPS_MT_SMTC */ | 339 | #endif /* CONFIG_MIPS_MT_SMTC */ |
| 340 | #ifdef CONFIG_CPU_CAVIUM_OCTEON | ||
| 341 | /* Restore the Octeon multiplier state */ | ||
| 342 | jal octeon_mult_restore | ||
| 343 | #endif | ||
| 327 | mfc0 a0, CP0_STATUS | 344 | mfc0 a0, CP0_STATUS |
| 328 | ori a0, STATMASK | 345 | ori a0, STATMASK |
| 329 | xori a0, STATMASK | 346 | xori a0, STATMASK |
diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h index 9601ea950542..38a30d2ee959 100644 --- a/arch/mips/include/asm/time.h +++ b/arch/mips/include/asm/time.h | |||
| @@ -50,27 +50,35 @@ extern int (*perf_irq)(void); | |||
| 50 | /* | 50 | /* |
| 51 | * Initialize the calling CPU's compare interrupt as clockevent device | 51 | * Initialize the calling CPU's compare interrupt as clockevent device |
| 52 | */ | 52 | */ |
| 53 | #ifdef CONFIG_CEVT_R4K | 53 | #ifdef CONFIG_CEVT_R4K_LIB |
| 54 | extern int mips_clockevent_init(void); | ||
| 55 | extern unsigned int __weak get_c0_compare_int(void); | 54 | extern unsigned int __weak get_c0_compare_int(void); |
| 56 | #else | 55 | extern int r4k_clockevent_init(void); |
| 56 | #endif | ||
| 57 | |||
| 57 | static inline int mips_clockevent_init(void) | 58 | static inline int mips_clockevent_init(void) |
| 58 | { | 59 | { |
| 60 | #ifdef CONFIG_CEVT_R4K | ||
| 61 | return r4k_clockevent_init(); | ||
| 62 | #else | ||
| 59 | return -ENXIO; | 63 | return -ENXIO; |
| 60 | } | ||
| 61 | #endif | 64 | #endif |
| 65 | } | ||
| 62 | 66 | ||
| 63 | /* | 67 | /* |
| 64 | * Initialize the count register as a clocksource | 68 | * Initialize the count register as a clocksource |
| 65 | */ | 69 | */ |
| 66 | #ifdef CONFIG_CSRC_R4K | 70 | #ifdef CONFIG_CSRC_R4K_LIB |
| 67 | extern int init_mips_clocksource(void); | 71 | extern int init_r4k_clocksource(void); |
| 68 | #else | 72 | #endif |
| 73 | |||
| 69 | static inline int init_mips_clocksource(void) | 74 | static inline int init_mips_clocksource(void) |
| 70 | { | 75 | { |
| 76 | #ifdef CONFIG_CSRC_R4K | ||
| 77 | return init_r4k_clocksource(); | ||
| 78 | #else | ||
| 71 | return 0; | 79 | return 0; |
| 72 | } | ||
| 73 | #endif | 80 | #endif |
| 81 | } | ||
| 74 | 82 | ||
| 75 | extern void clocksource_set_clock(struct clocksource *cs, unsigned int clock); | 83 | extern void clocksource_set_clock(struct clocksource *cs, unsigned int clock); |
| 76 | extern void clockevent_set_clock(struct clock_event_device *cd, | 84 | extern void clockevent_set_clock(struct clock_event_device *cd, |
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index b1372c27f136..e96122159928 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile | |||
| @@ -9,7 +9,7 @@ obj-y += cpu-probe.o branch.o entry.o genex.o irq.o process.o \ | |||
| 9 | time.o topology.o traps.o unaligned.o watch.o | 9 | time.o topology.o traps.o unaligned.o watch.o |
| 10 | 10 | ||
| 11 | obj-$(CONFIG_CEVT_BCM1480) += cevt-bcm1480.o | 11 | obj-$(CONFIG_CEVT_BCM1480) += cevt-bcm1480.o |
| 12 | obj-$(CONFIG_CEVT_R4K) += cevt-r4k.o | 12 | obj-$(CONFIG_CEVT_R4K_LIB) += cevt-r4k.o |
| 13 | obj-$(CONFIG_MIPS_MT_SMTC) += cevt-smtc.o | 13 | obj-$(CONFIG_MIPS_MT_SMTC) += cevt-smtc.o |
| 14 | obj-$(CONFIG_CEVT_DS1287) += cevt-ds1287.o | 14 | obj-$(CONFIG_CEVT_DS1287) += cevt-ds1287.o |
| 15 | obj-$(CONFIG_CEVT_GT641XX) += cevt-gt641xx.o | 15 | obj-$(CONFIG_CEVT_GT641XX) += cevt-gt641xx.o |
| @@ -17,7 +17,7 @@ obj-$(CONFIG_CEVT_SB1250) += cevt-sb1250.o | |||
| 17 | obj-$(CONFIG_CEVT_TXX9) += cevt-txx9.o | 17 | obj-$(CONFIG_CEVT_TXX9) += cevt-txx9.o |
| 18 | obj-$(CONFIG_CSRC_BCM1480) += csrc-bcm1480.o | 18 | obj-$(CONFIG_CSRC_BCM1480) += csrc-bcm1480.o |
| 19 | obj-$(CONFIG_CSRC_IOASIC) += csrc-ioasic.o | 19 | obj-$(CONFIG_CSRC_IOASIC) += csrc-ioasic.o |
| 20 | obj-$(CONFIG_CSRC_R4K) += csrc-r4k.o | 20 | obj-$(CONFIG_CSRC_R4K_LIB) += csrc-r4k.o |
| 21 | obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o | 21 | obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o |
| 22 | obj-$(CONFIG_SYNC_R4K) += sync-r4k.o | 22 | obj-$(CONFIG_SYNC_R4K) += sync-r4k.o |
| 23 | 23 | ||
| @@ -43,6 +43,7 @@ obj-$(CONFIG_CPU_SB1) += r4k_fpu.o r4k_switch.o | |||
| 43 | obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o | 43 | obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o |
| 44 | obj-$(CONFIG_CPU_TX49XX) += r4k_fpu.o r4k_switch.o | 44 | obj-$(CONFIG_CPU_TX49XX) += r4k_fpu.o r4k_switch.o |
| 45 | obj-$(CONFIG_CPU_VR41XX) += r4k_fpu.o r4k_switch.o | 45 | obj-$(CONFIG_CPU_VR41XX) += r4k_fpu.o r4k_switch.o |
| 46 | obj-$(CONFIG_CPU_CAVIUM_OCTEON) += octeon_switch.o | ||
| 46 | 47 | ||
| 47 | obj-$(CONFIG_SMP) += smp.o | 48 | obj-$(CONFIG_SMP) += smp.o |
| 48 | obj-$(CONFIG_SMP_UP) += smp-up.o | 49 | obj-$(CONFIG_SMP_UP) += smp-up.o |
diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c index 72942226fcdd..c901c22d7ad0 100644 --- a/arch/mips/kernel/asm-offsets.c +++ b/arch/mips/kernel/asm-offsets.c | |||
| @@ -64,6 +64,10 @@ void output_ptreg_defines(void) | |||
| 64 | #ifdef CONFIG_MIPS_MT_SMTC | 64 | #ifdef CONFIG_MIPS_MT_SMTC |
| 65 | OFFSET(PT_TCSTATUS, pt_regs, cp0_tcstatus); | 65 | OFFSET(PT_TCSTATUS, pt_regs, cp0_tcstatus); |
| 66 | #endif /* CONFIG_MIPS_MT_SMTC */ | 66 | #endif /* CONFIG_MIPS_MT_SMTC */ |
| 67 | #ifdef CONFIG_CPU_CAVIUM_OCTEON | ||
| 68 | OFFSET(PT_MPL, pt_regs, mpl); | ||
| 69 | OFFSET(PT_MTP, pt_regs, mtp); | ||
| 70 | #endif /* CONFIG_CPU_CAVIUM_OCTEON */ | ||
| 67 | DEFINE(PT_SIZE, sizeof(struct pt_regs)); | 71 | DEFINE(PT_SIZE, sizeof(struct pt_regs)); |
| 68 | BLANK(); | 72 | BLANK(); |
| 69 | } | 73 | } |
| @@ -295,3 +299,30 @@ void output_irq_cpustat_t_defines(void) | |||
| 295 | DEFINE(IC_IRQ_CPUSTAT_T, sizeof(irq_cpustat_t)); | 299 | DEFINE(IC_IRQ_CPUSTAT_T, sizeof(irq_cpustat_t)); |
| 296 | BLANK(); | 300 | BLANK(); |
| 297 | } | 301 | } |
| 302 | |||
| 303 | #ifdef CONFIG_CPU_CAVIUM_OCTEON | ||
| 304 | void output_octeon_cop2_state_defines(void) | ||
| 305 | { | ||
| 306 | COMMENT("Octeon specific octeon_cop2_state offsets."); | ||
| 307 | OFFSET(OCTEON_CP2_CRC_IV, octeon_cop2_state, cop2_crc_iv); | ||
| 308 | OFFSET(OCTEON_CP2_CRC_LENGTH, octeon_cop2_state, cop2_crc_length); | ||
| 309 | OFFSET(OCTEON_CP2_CRC_POLY, octeon_cop2_state, cop2_crc_poly); | ||
| 310 | OFFSET(OCTEON_CP2_LLM_DAT, octeon_cop2_state, cop2_llm_dat); | ||
| 311 | OFFSET(OCTEON_CP2_3DES_IV, octeon_cop2_state, cop2_3des_iv); | ||
| 312 | OFFSET(OCTEON_CP2_3DES_KEY, octeon_cop2_state, cop2_3des_key); | ||
| 313 | OFFSET(OCTEON_CP2_3DES_RESULT, octeon_cop2_state, cop2_3des_result); | ||
| 314 | OFFSET(OCTEON_CP2_AES_INP0, octeon_cop2_state, cop2_aes_inp0); | ||
| 315 | OFFSET(OCTEON_CP2_AES_IV, octeon_cop2_state, cop2_aes_iv); | ||
| 316 | OFFSET(OCTEON_CP2_AES_KEY, octeon_cop2_state, cop2_aes_key); | ||
| 317 | OFFSET(OCTEON_CP2_AES_KEYLEN, octeon_cop2_state, cop2_aes_keylen); | ||
| 318 | OFFSET(OCTEON_CP2_AES_RESULT, octeon_cop2_state, cop2_aes_result); | ||
| 319 | OFFSET(OCTEON_CP2_GFM_MULT, octeon_cop2_state, cop2_gfm_mult); | ||
| 320 | OFFSET(OCTEON_CP2_GFM_POLY, octeon_cop2_state, cop2_gfm_poly); | ||
| 321 | OFFSET(OCTEON_CP2_GFM_RESULT, octeon_cop2_state, cop2_gfm_result); | ||
| 322 | OFFSET(OCTEON_CP2_HSH_DATW, octeon_cop2_state, cop2_hsh_datw); | ||
| 323 | OFFSET(OCTEON_CP2_HSH_IVW, octeon_cop2_state, cop2_hsh_ivw); | ||
| 324 | OFFSET(THREAD_CP2, task_struct, thread.cp2); | ||
| 325 | OFFSET(THREAD_CVMSEG, task_struct, thread.cvmseg.cvmseg); | ||
| 326 | BLANK(); | ||
| 327 | } | ||
| 328 | #endif | ||
diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c index 6b5df8bfab85..0176ed015c89 100644 --- a/arch/mips/kernel/branch.c +++ b/arch/mips/kernel/branch.c | |||
| @@ -205,6 +205,39 @@ int __compute_return_epc(struct pt_regs *regs) | |||
| 205 | break; | 205 | break; |
| 206 | } | 206 | } |
| 207 | break; | 207 | break; |
| 208 | #ifdef CONFIG_CPU_CAVIUM_OCTEON | ||
| 209 | case lwc2_op: /* This is bbit0 on Octeon */ | ||
| 210 | if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) | ||
| 211 | == 0) | ||
| 212 | epc = epc + 4 + (insn.i_format.simmediate << 2); | ||
| 213 | else | ||
| 214 | epc += 8; | ||
| 215 | regs->cp0_epc = epc; | ||
| 216 | break; | ||
| 217 | case ldc2_op: /* This is bbit032 on Octeon */ | ||
| 218 | if ((regs->regs[insn.i_format.rs] & | ||
| 219 | (1ull<<(insn.i_format.rt+32))) == 0) | ||
| 220 | epc = epc + 4 + (insn.i_format.simmediate << 2); | ||
| 221 | else | ||
| 222 | epc += 8; | ||
| 223 | regs->cp0_epc = epc; | ||
| 224 | break; | ||
| 225 | case swc2_op: /* This is bbit1 on Octeon */ | ||
| 226 | if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) | ||
| 227 | epc = epc + 4 + (insn.i_format.simmediate << 2); | ||
| 228 | else | ||
| 229 | epc += 8; | ||
| 230 | regs->cp0_epc = epc; | ||
| 231 | break; | ||
| 232 | case sdc2_op: /* This is bbit132 on Octeon */ | ||
| 233 | if (regs->regs[insn.i_format.rs] & | ||
| 234 | (1ull<<(insn.i_format.rt+32))) | ||
| 235 | epc = epc + 4 + (insn.i_format.simmediate << 2); | ||
| 236 | else | ||
| 237 | epc += 8; | ||
| 238 | regs->cp0_epc = epc; | ||
| 239 | break; | ||
| 240 | #endif | ||
| 208 | } | 241 | } |
| 209 | 242 | ||
| 210 | return 0; | 243 | return 0; |
diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c index e1ec83b68031..0015e442572b 100644 --- a/arch/mips/kernel/cevt-r4k.c +++ b/arch/mips/kernel/cevt-r4k.c | |||
| @@ -160,7 +160,7 @@ int c0_compare_int_usable(void) | |||
| 160 | 160 | ||
| 161 | #ifndef CONFIG_MIPS_MT_SMTC | 161 | #ifndef CONFIG_MIPS_MT_SMTC |
| 162 | 162 | ||
| 163 | int __cpuinit mips_clockevent_init(void) | 163 | int __cpuinit r4k_clockevent_init(void) |
| 164 | { | 164 | { |
| 165 | uint64_t mips_freq = mips_hpt_frequency; | 165 | uint64_t mips_freq = mips_hpt_frequency; |
| 166 | unsigned int cpu = smp_processor_id(); | 166 | unsigned int cpu = smp_processor_id(); |
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index c9207b5fd923..a7162a4484cf 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c | |||
| @@ -96,6 +96,9 @@ int allow_au1k_wait; | |||
| 96 | 96 | ||
| 97 | static void au1k_wait(void) | 97 | static void au1k_wait(void) |
| 98 | { | 98 | { |
| 99 | if (!allow_au1k_wait) | ||
| 100 | return; | ||
| 101 | |||
| 99 | /* using the wait instruction makes CP0 counter unusable */ | 102 | /* using the wait instruction makes CP0 counter unusable */ |
| 100 | __asm__(" .set mips3 \n" | 103 | __asm__(" .set mips3 \n" |
| 101 | " cache 0x14, 0(%0) \n" | 104 | " cache 0x14, 0(%0) \n" |
| @@ -154,6 +157,7 @@ void __init check_wait(void) | |||
| 154 | case CPU_25KF: | 157 | case CPU_25KF: |
| 155 | case CPU_PR4450: | 158 | case CPU_PR4450: |
| 156 | case CPU_BCM3302: | 159 | case CPU_BCM3302: |
| 160 | case CPU_CAVIUM_OCTEON: | ||
| 157 | cpu_wait = r4k_wait; | 161 | cpu_wait = r4k_wait; |
| 158 | break; | 162 | break; |
| 159 | 163 | ||
| @@ -185,8 +189,7 @@ void __init check_wait(void) | |||
| 185 | case CPU_AU1200: | 189 | case CPU_AU1200: |
| 186 | case CPU_AU1210: | 190 | case CPU_AU1210: |
| 187 | case CPU_AU1250: | 191 | case CPU_AU1250: |
| 188 | if (allow_au1k_wait) | 192 | cpu_wait = au1k_wait; |
| 189 | cpu_wait = au1k_wait; | ||
| 190 | break; | 193 | break; |
| 191 | case CPU_20KC: | 194 | case CPU_20KC: |
| 192 | /* | 195 | /* |
| @@ -875,6 +878,27 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) | |||
| 875 | } | 878 | } |
| 876 | } | 879 | } |
| 877 | 880 | ||
| 881 | static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) | ||
| 882 | { | ||
| 883 | decode_configs(c); | ||
| 884 | switch (c->processor_id & 0xff00) { | ||
| 885 | case PRID_IMP_CAVIUM_CN38XX: | ||
| 886 | case PRID_IMP_CAVIUM_CN31XX: | ||
| 887 | case PRID_IMP_CAVIUM_CN30XX: | ||
| 888 | case PRID_IMP_CAVIUM_CN58XX: | ||
| 889 | case PRID_IMP_CAVIUM_CN56XX: | ||
| 890 | case PRID_IMP_CAVIUM_CN50XX: | ||
| 891 | case PRID_IMP_CAVIUM_CN52XX: | ||
| 892 | c->cputype = CPU_CAVIUM_OCTEON; | ||
| 893 | __cpu_name[cpu] = "Cavium Octeon"; | ||
| 894 | break; | ||
| 895 | default: | ||
| 896 | printk(KERN_INFO "Unknown Octeon chip!\n"); | ||
| 897 | c->cputype = CPU_UNKNOWN; | ||
| 898 | break; | ||
| 899 | } | ||
| 900 | } | ||
| 901 | |||
| 878 | const char *__cpu_name[NR_CPUS]; | 902 | const char *__cpu_name[NR_CPUS]; |
| 879 | 903 | ||
| 880 | __cpuinit void cpu_probe(void) | 904 | __cpuinit void cpu_probe(void) |
| @@ -909,6 +933,9 @@ __cpuinit void cpu_probe(void) | |||
| 909 | case PRID_COMP_NXP: | 933 | case PRID_COMP_NXP: |
| 910 | cpu_probe_nxp(c, cpu); | 934 | cpu_probe_nxp(c, cpu); |
| 911 | break; | 935 | break; |
| 936 | case PRID_COMP_CAVIUM: | ||
| 937 | cpu_probe_cavium(c, cpu); | ||
| 938 | break; | ||
| 912 | } | 939 | } |
| 913 | 940 | ||
| 914 | BUG_ON(!__cpu_name[cpu]); | 941 | BUG_ON(!__cpu_name[cpu]); |
diff --git a/arch/mips/kernel/csrc-r4k.c b/arch/mips/kernel/csrc-r4k.c index 74fb74583b4e..f1a2893931ed 100644 --- a/arch/mips/kernel/csrc-r4k.c +++ b/arch/mips/kernel/csrc-r4k.c | |||
| @@ -22,7 +22,7 @@ static struct clocksource clocksource_mips = { | |||
| 22 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | 22 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
| 23 | }; | 23 | }; |
| 24 | 24 | ||
| 25 | int __init init_mips_clocksource(void) | 25 | int __init init_r4k_clocksource(void) |
| 26 | { | 26 | { |
| 27 | if (!cpu_has_counter || !mips_hpt_frequency) | 27 | if (!cpu_has_counter || !mips_hpt_frequency) |
| 28 | return -ENXIO; | 28 | return -ENXIO; |
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index 757d48f0d80f..fb6f73148df2 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S | |||
| @@ -385,10 +385,14 @@ NESTED(nmi_handler, PT_SIZE, sp) | |||
| 385 | .endm | 385 | .endm |
| 386 | 386 | ||
| 387 | .macro __build_clear_fpe | 387 | .macro __build_clear_fpe |
| 388 | .set push | ||
| 389 | /* gas fails to assemble cfc1 for some archs (octeon).*/ \ | ||
| 390 | .set mips1 | ||
| 388 | cfc1 a1, fcr31 | 391 | cfc1 a1, fcr31 |
| 389 | li a2, ~(0x3f << 12) | 392 | li a2, ~(0x3f << 12) |
| 390 | and a2, a1 | 393 | and a2, a1 |
| 391 | ctc1 a2, fcr31 | 394 | ctc1 a2, fcr31 |
| 395 | .set pop | ||
| 392 | TRACE_IRQS_ON | 396 | TRACE_IRQS_ON |
| 393 | STI | 397 | STI |
| 394 | .endm | 398 | .endm |
diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c index 4b4007b3083a..a0ff2b66e22b 100644 --- a/arch/mips/kernel/irq.c +++ b/arch/mips/kernel/irq.c | |||
| @@ -111,6 +111,7 @@ int show_interrupts(struct seq_file *p, void *v) | |||
| 111 | seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); | 111 | seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); |
| 112 | #endif | 112 | #endif |
| 113 | seq_printf(p, " %14s", irq_desc[i].chip->name); | 113 | seq_printf(p, " %14s", irq_desc[i].chip->name); |
| 114 | seq_printf(p, "-%-8s", irq_desc[i].name); | ||
| 114 | seq_printf(p, " %s", action->name); | 115 | seq_printf(p, " %s", action->name); |
| 115 | 116 | ||
| 116 | for (action=action->next; action; action = action->next) | 117 | for (action=action->next; action; action = action->next) |
diff --git a/arch/mips/kernel/octeon_switch.S b/arch/mips/kernel/octeon_switch.S new file mode 100644 index 000000000000..d52389672b06 --- /dev/null +++ b/arch/mips/kernel/octeon_switch.S | |||
| @@ -0,0 +1,506 @@ | |||
| 1 | /* | ||
| 2 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 3 | * License. See the file "COPYING" in the main directory of this archive | ||
| 4 | * for more details. | ||
| 5 | * | ||
| 6 | * Copyright (C) 1994, 1995, 1996, 1998, 1999, 2002, 2003 Ralf Baechle | ||
| 7 | * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) | ||
| 8 | * Copyright (C) 1994, 1995, 1996, by Andreas Busse | ||
| 9 | * Copyright (C) 1999 Silicon Graphics, Inc. | ||
| 10 | * Copyright (C) 2000 MIPS Technologies, Inc. | ||
| 11 | * written by Carsten Langgaard, carstenl@mips.com | ||
| 12 | */ | ||
| 13 | #include <asm/asm.h> | ||
| 14 | #include <asm/cachectl.h> | ||
| 15 | #include <asm/fpregdef.h> | ||
| 16 | #include <asm/mipsregs.h> | ||
| 17 | #include <asm/asm-offsets.h> | ||
| 18 | #include <asm/page.h> | ||
| 19 | #include <asm/pgtable-bits.h> | ||
| 20 | #include <asm/regdef.h> | ||
| 21 | #include <asm/stackframe.h> | ||
| 22 | #include <asm/thread_info.h> | ||
| 23 | |||
| 24 | #include <asm/asmmacro.h> | ||
| 25 | |||
| 26 | /* | ||
| 27 | * Offset to the current process status flags, the first 32 bytes of the | ||
| 28 | * stack are not used. | ||
| 29 | */ | ||
| 30 | #define ST_OFF (_THREAD_SIZE - 32 - PT_SIZE + PT_STATUS) | ||
| 31 | |||
| 32 | /* | ||
| 33 | * task_struct *resume(task_struct *prev, task_struct *next, | ||
| 34 | * struct thread_info *next_ti) | ||
| 35 | */ | ||
| 36 | .align 7 | ||
| 37 | LEAF(resume) | ||
| 38 | .set arch=octeon | ||
| 39 | #ifndef CONFIG_CPU_HAS_LLSC | ||
| 40 | sw zero, ll_bit | ||
| 41 | #endif | ||
| 42 | mfc0 t1, CP0_STATUS | ||
| 43 | LONG_S t1, THREAD_STATUS(a0) | ||
| 44 | cpu_save_nonscratch a0 | ||
| 45 | LONG_S ra, THREAD_REG31(a0) | ||
| 46 | |||
| 47 | /* check if we need to save COP2 registers */ | ||
| 48 | PTR_L t2, TASK_THREAD_INFO(a0) | ||
| 49 | LONG_L t0, ST_OFF(t2) | ||
| 50 | bbit0 t0, 30, 1f | ||
| 51 | |||
| 52 | /* Disable COP2 in the stored process state */ | ||
| 53 | li t1, ST0_CU2 | ||
| 54 | xor t0, t1 | ||
| 55 | LONG_S t0, ST_OFF(t2) | ||
| 56 | |||
| 57 | /* Enable COP2 so we can save it */ | ||
| 58 | mfc0 t0, CP0_STATUS | ||
| 59 | or t0, t1 | ||
| 60 | mtc0 t0, CP0_STATUS | ||
| 61 | |||
| 62 | /* Save COP2 */ | ||
| 63 | daddu a0, THREAD_CP2 | ||
| 64 | jal octeon_cop2_save | ||
| 65 | dsubu a0, THREAD_CP2 | ||
| 66 | |||
| 67 | /* Disable COP2 now that we are done */ | ||
| 68 | mfc0 t0, CP0_STATUS | ||
| 69 | li t1, ST0_CU2 | ||
| 70 | xor t0, t1 | ||
| 71 | mtc0 t0, CP0_STATUS | ||
| 72 | |||
| 73 | 1: | ||
| 74 | #if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 | ||
| 75 | /* Check if we need to store CVMSEG state */ | ||
| 76 | mfc0 t0, $11,7 /* CvmMemCtl */ | ||
| 77 | bbit0 t0, 6, 3f /* Is user access enabled? */ | ||
| 78 | |||
| 79 | /* Store the CVMSEG state */ | ||
| 80 | /* Extract the size of CVMSEG */ | ||
| 81 | andi t0, 0x3f | ||
| 82 | /* Multiply * (cache line size/sizeof(long)/2) */ | ||
| 83 | sll t0, 7-LONGLOG-1 | ||
| 84 | li t1, -32768 /* Base address of CVMSEG */ | ||
| 85 | LONG_ADDI t2, a0, THREAD_CVMSEG /* Where to store CVMSEG to */ | ||
| 86 | synciobdma | ||
| 87 | 2: | ||
| 88 | .set noreorder | ||
| 89 | LONG_L t8, 0(t1) /* Load from CVMSEG */ | ||
| 90 | subu t0, 1 /* Decrement loop var */ | ||
| 91 | LONG_L t9, LONGSIZE(t1)/* Load from CVMSEG */ | ||
| 92 | LONG_ADDU t1, LONGSIZE*2 /* Increment loc in CVMSEG */ | ||
| 93 | LONG_S t8, 0(t2) /* Store CVMSEG to thread storage */ | ||
| 94 | LONG_ADDU t2, LONGSIZE*2 /* Increment loc in thread storage */ | ||
| 95 | bnez t0, 2b /* Loop until we've copied it all */ | ||
| 96 | LONG_S t9, -LONGSIZE(t2)/* Store CVMSEG to thread storage */ | ||
| 97 | .set reorder | ||
| 98 | |||
| 99 | /* Disable access to CVMSEG */ | ||
| 100 | mfc0 t0, $11,7 /* CvmMemCtl */ | ||
| 101 | xori t0, t0, 0x40 /* Bit 6 is CVMSEG user enable */ | ||
| 102 | mtc0 t0, $11,7 /* CvmMemCtl */ | ||
| 103 | #endif | ||
| 104 | 3: | ||
| 105 | /* | ||
| 106 | * The order of restoring the registers takes care of the race | ||
| 107 | * updating $28, $29 and kernelsp without disabling ints. | ||
| 108 | */ | ||
| 109 | move $28, a2 | ||
| 110 | cpu_restore_nonscratch a1 | ||
| 111 | |||
| 112 | #if (_THREAD_SIZE - 32) < 0x8000 | ||
| 113 | PTR_ADDIU t0, $28, _THREAD_SIZE - 32 | ||
| 114 | #else | ||
| 115 | PTR_LI t0, _THREAD_SIZE - 32 | ||
| 116 | PTR_ADDU t0, $28 | ||
| 117 | #endif | ||
| 118 | set_saved_sp t0, t1, t2 | ||
| 119 | |||
| 120 | mfc0 t1, CP0_STATUS /* Do we really need this? */ | ||
| 121 | li a3, 0xff01 | ||
| 122 | and t1, a3 | ||
| 123 | LONG_L a2, THREAD_STATUS(a1) | ||
| 124 | nor a3, $0, a3 | ||
| 125 | and a2, a3 | ||
| 126 | or a2, t1 | ||
| 127 | mtc0 a2, CP0_STATUS | ||
| 128 | move v0, a0 | ||
| 129 | jr ra | ||
| 130 | END(resume) | ||
| 131 | |||
| 132 | /* | ||
| 133 | * void octeon_cop2_save(struct octeon_cop2_state *a0) | ||
| 134 | */ | ||
| 135 | .align 7 | ||
| 136 | LEAF(octeon_cop2_save) | ||
| 137 | |||
| 138 | dmfc0 t9, $9,7 /* CvmCtl register. */ | ||
| 139 | |||
| 140 | /* Save the COP2 CRC state */ | ||
| 141 | dmfc2 t0, 0x0201 | ||
| 142 | dmfc2 t1, 0x0202 | ||
| 143 | dmfc2 t2, 0x0200 | ||
| 144 | sd t0, OCTEON_CP2_CRC_IV(a0) | ||
| 145 | sd t1, OCTEON_CP2_CRC_LENGTH(a0) | ||
| 146 | sd t2, OCTEON_CP2_CRC_POLY(a0) | ||
| 147 | /* Skip next instructions if CvmCtl[NODFA_CP2] set */ | ||
| 148 | bbit1 t9, 28, 1f | ||
| 149 | |||
| 150 | /* Save the LLM state */ | ||
| 151 | dmfc2 t0, 0x0402 | ||
| 152 | dmfc2 t1, 0x040A | ||
| 153 | sd t0, OCTEON_CP2_LLM_DAT(a0) | ||
| 154 | sd t1, OCTEON_CP2_LLM_DAT+8(a0) | ||
| 155 | |||
| 156 | 1: bbit1 t9, 26, 3f /* done if CvmCtl[NOCRYPTO] set */ | ||
| 157 | |||
| 158 | /* Save the COP2 crypto state */ | ||
| 159 | /* this part is mostly common to both pass 1 and later revisions */ | ||
| 160 | dmfc2 t0, 0x0084 | ||
| 161 | dmfc2 t1, 0x0080 | ||
| 162 | dmfc2 t2, 0x0081 | ||
| 163 | dmfc2 t3, 0x0082 | ||
| 164 | sd t0, OCTEON_CP2_3DES_IV(a0) | ||
| 165 | dmfc2 t0, 0x0088 | ||
| 166 | sd t1, OCTEON_CP2_3DES_KEY(a0) | ||
| 167 | dmfc2 t1, 0x0111 /* only necessary for pass 1 */ | ||
| 168 | sd t2, OCTEON_CP2_3DES_KEY+8(a0) | ||
| 169 | dmfc2 t2, 0x0102 | ||
| 170 | sd t3, OCTEON_CP2_3DES_KEY+16(a0) | ||
| 171 | dmfc2 t3, 0x0103 | ||
| 172 | sd t0, OCTEON_CP2_3DES_RESULT(a0) | ||
| 173 | dmfc2 t0, 0x0104 | ||
| 174 | sd t1, OCTEON_CP2_AES_INP0(a0) /* only necessary for pass 1 */ | ||
| 175 | dmfc2 t1, 0x0105 | ||
| 176 | sd t2, OCTEON_CP2_AES_IV(a0) | ||
| 177 | dmfc2 t2, 0x0106 | ||
| 178 | sd t3, OCTEON_CP2_AES_IV+8(a0) | ||
| 179 | dmfc2 t3, 0x0107 | ||
| 180 | sd t0, OCTEON_CP2_AES_KEY(a0) | ||
| 181 | dmfc2 t0, 0x0110 | ||
| 182 | sd t1, OCTEON_CP2_AES_KEY+8(a0) | ||
| 183 | dmfc2 t1, 0x0100 | ||
| 184 | sd t2, OCTEON_CP2_AES_KEY+16(a0) | ||
| 185 | dmfc2 t2, 0x0101 | ||
| 186 | sd t3, OCTEON_CP2_AES_KEY+24(a0) | ||
| 187 | mfc0 t3, $15,0 /* Get the processor ID register */ | ||
| 188 | sd t0, OCTEON_CP2_AES_KEYLEN(a0) | ||
| 189 | li t0, 0x000d0000 /* This is the processor ID of Octeon Pass1 */ | ||
| 190 | sd t1, OCTEON_CP2_AES_RESULT(a0) | ||
| 191 | sd t2, OCTEON_CP2_AES_RESULT+8(a0) | ||
| 192 | /* Skip to the Pass1 version of the remainder of the COP2 state */ | ||
| 193 | beq t3, t0, 2f | ||
| 194 | |||
| 195 | /* the non-pass1 state when !CvmCtl[NOCRYPTO] */ | ||
| 196 | dmfc2 t1, 0x0240 | ||
| 197 | dmfc2 t2, 0x0241 | ||
| 198 | dmfc2 t3, 0x0242 | ||
| 199 | dmfc2 t0, 0x0243 | ||
| 200 | sd t1, OCTEON_CP2_HSH_DATW(a0) | ||
| 201 | dmfc2 t1, 0x0244 | ||
| 202 | sd t2, OCTEON_CP2_HSH_DATW+8(a0) | ||
| 203 | dmfc2 t2, 0x0245 | ||
| 204 | sd t3, OCTEON_CP2_HSH_DATW+16(a0) | ||
| 205 | dmfc2 t3, 0x0246 | ||
| 206 | sd t0, OCTEON_CP2_HSH_DATW+24(a0) | ||
| 207 | dmfc2 t0, 0x0247 | ||
| 208 | sd t1, OCTEON_CP2_HSH_DATW+32(a0) | ||
| 209 | dmfc2 t1, 0x0248 | ||
| 210 | sd t2, OCTEON_CP2_HSH_DATW+40(a0) | ||
| 211 | dmfc2 t2, 0x0249 | ||
| 212 | sd t3, OCTEON_CP2_HSH_DATW+48(a0) | ||
| 213 | dmfc2 t3, 0x024A | ||
| 214 | sd t0, OCTEON_CP2_HSH_DATW+56(a0) | ||
| 215 | dmfc2 t0, 0x024B | ||
| 216 | sd t1, OCTEON_CP2_HSH_DATW+64(a0) | ||
| 217 | dmfc2 t1, 0x024C | ||
| 218 | sd t2, OCTEON_CP2_HSH_DATW+72(a0) | ||
| 219 | dmfc2 t2, 0x024D | ||
| 220 | sd t3, OCTEON_CP2_HSH_DATW+80(a0) | ||
| 221 | dmfc2 t3, 0x024E | ||
| 222 | sd t0, OCTEON_CP2_HSH_DATW+88(a0) | ||
| 223 | dmfc2 t0, 0x0250 | ||
| 224 | sd t1, OCTEON_CP2_HSH_DATW+96(a0) | ||
| 225 | dmfc2 t1, 0x0251 | ||
| 226 | sd t2, OCTEON_CP2_HSH_DATW+104(a0) | ||
| 227 | dmfc2 t2, 0x0252 | ||
| 228 | sd t3, OCTEON_CP2_HSH_DATW+112(a0) | ||
| 229 | dmfc2 t3, 0x0253 | ||
| 230 | sd t0, OCTEON_CP2_HSH_IVW(a0) | ||
| 231 | dmfc2 t0, 0x0254 | ||
| 232 | sd t1, OCTEON_CP2_HSH_IVW+8(a0) | ||
| 233 | dmfc2 t1, 0x0255 | ||
| 234 | sd t2, OCTEON_CP2_HSH_IVW+16(a0) | ||
| 235 | dmfc2 t2, 0x0256 | ||
| 236 | sd t3, OCTEON_CP2_HSH_IVW+24(a0) | ||
| 237 | dmfc2 t3, 0x0257 | ||
| 238 | sd t0, OCTEON_CP2_HSH_IVW+32(a0) | ||
| 239 | dmfc2 t0, 0x0258 | ||
| 240 | sd t1, OCTEON_CP2_HSH_IVW+40(a0) | ||
| 241 | dmfc2 t1, 0x0259 | ||
| 242 | sd t2, OCTEON_CP2_HSH_IVW+48(a0) | ||
| 243 | dmfc2 t2, 0x025E | ||
| 244 | sd t3, OCTEON_CP2_HSH_IVW+56(a0) | ||
| 245 | dmfc2 t3, 0x025A | ||
| 246 | sd t0, OCTEON_CP2_GFM_MULT(a0) | ||
| 247 | dmfc2 t0, 0x025B | ||
| 248 | sd t1, OCTEON_CP2_GFM_MULT+8(a0) | ||
| 249 | sd t2, OCTEON_CP2_GFM_POLY(a0) | ||
| 250 | sd t3, OCTEON_CP2_GFM_RESULT(a0) | ||
| 251 | sd t0, OCTEON_CP2_GFM_RESULT+8(a0) | ||
| 252 | jr ra | ||
| 253 | |||
| 254 | 2: /* pass 1 special stuff when !CvmCtl[NOCRYPTO] */ | ||
| 255 | dmfc2 t3, 0x0040 | ||
| 256 | dmfc2 t0, 0x0041 | ||
| 257 | dmfc2 t1, 0x0042 | ||
| 258 | dmfc2 t2, 0x0043 | ||
| 259 | sd t3, OCTEON_CP2_HSH_DATW(a0) | ||
| 260 | dmfc2 t3, 0x0044 | ||
| 261 | sd t0, OCTEON_CP2_HSH_DATW+8(a0) | ||
| 262 | dmfc2 t0, 0x0045 | ||
| 263 | sd t1, OCTEON_CP2_HSH_DATW+16(a0) | ||
| 264 | dmfc2 t1, 0x0046 | ||
| 265 | sd t2, OCTEON_CP2_HSH_DATW+24(a0) | ||
| 266 | dmfc2 t2, 0x0048 | ||
| 267 | sd t3, OCTEON_CP2_HSH_DATW+32(a0) | ||
| 268 | dmfc2 t3, 0x0049 | ||
| 269 | sd t0, OCTEON_CP2_HSH_DATW+40(a0) | ||
| 270 | dmfc2 t0, 0x004A | ||
| 271 | sd t1, OCTEON_CP2_HSH_DATW+48(a0) | ||
| 272 | sd t2, OCTEON_CP2_HSH_IVW(a0) | ||
| 273 | sd t3, OCTEON_CP2_HSH_IVW+8(a0) | ||
| 274 | sd t0, OCTEON_CP2_HSH_IVW+16(a0) | ||
| 275 | |||
| 276 | 3: /* pass 1 or CvmCtl[NOCRYPTO] set */ | ||
| 277 | jr ra | ||
| 278 | END(octeon_cop2_save) | ||
| 279 | |||
| 280 | /* | ||
| 281 | * void octeon_cop2_restore(struct octeon_cop2_state *a0) | ||
| 282 | */ | ||
| 283 | .align 7 | ||
| 284 | .set push | ||
| 285 | .set noreorder | ||
| 286 | LEAF(octeon_cop2_restore) | ||
| 287 | /* First cache line was prefetched before the call */ | ||
| 288 | pref 4, 128(a0) | ||
| 289 | dmfc0 t9, $9,7 /* CvmCtl register. */ | ||
| 290 | |||
| 291 | pref 4, 256(a0) | ||
| 292 | ld t0, OCTEON_CP2_CRC_IV(a0) | ||
| 293 | pref 4, 384(a0) | ||
| 294 | ld t1, OCTEON_CP2_CRC_LENGTH(a0) | ||
| 295 | ld t2, OCTEON_CP2_CRC_POLY(a0) | ||
| 296 | |||
| 297 | /* Restore the COP2 CRC state */ | ||
| 298 | dmtc2 t0, 0x0201 | ||
| 299 | dmtc2 t1, 0x1202 | ||
| 300 | bbit1 t9, 28, 2f /* Skip LLM if CvmCtl[NODFA_CP2] is set */ | ||
| 301 | dmtc2 t2, 0x4200 | ||
| 302 | |||
| 303 | /* Restore the LLM state */ | ||
| 304 | ld t0, OCTEON_CP2_LLM_DAT(a0) | ||
| 305 | ld t1, OCTEON_CP2_LLM_DAT+8(a0) | ||
| 306 | dmtc2 t0, 0x0402 | ||
| 307 | dmtc2 t1, 0x040A | ||
| 308 | |||
| 309 | 2: | ||
| 310 | bbit1 t9, 26, done_restore /* done if CvmCtl[NOCRYPTO] set */ | ||
| 311 | nop | ||
| 312 | |||
| 313 | /* Restore the COP2 crypto state common to pass 1 and pass 2 */ | ||
| 314 | ld t0, OCTEON_CP2_3DES_IV(a0) | ||
| 315 | ld t1, OCTEON_CP2_3DES_KEY(a0) | ||
| 316 | ld t2, OCTEON_CP2_3DES_KEY+8(a0) | ||
| 317 | dmtc2 t0, 0x0084 | ||
| 318 | ld t0, OCTEON_CP2_3DES_KEY+16(a0) | ||
| 319 | dmtc2 t1, 0x0080 | ||
| 320 | ld t1, OCTEON_CP2_3DES_RESULT(a0) | ||
| 321 | dmtc2 t2, 0x0081 | ||
| 322 | ld t2, OCTEON_CP2_AES_INP0(a0) /* only really needed for pass 1 */ | ||
| 323 | dmtc2 t0, 0x0082 | ||
| 324 | ld t0, OCTEON_CP2_AES_IV(a0) | ||
| 325 | dmtc2 t1, 0x0098 | ||
| 326 | ld t1, OCTEON_CP2_AES_IV+8(a0) | ||
| 327 | dmtc2 t2, 0x010A /* only really needed for pass 1 */ | ||
| 328 | ld t2, OCTEON_CP2_AES_KEY(a0) | ||
| 329 | dmtc2 t0, 0x0102 | ||
| 330 | ld t0, OCTEON_CP2_AES_KEY+8(a0) | ||
| 331 | dmtc2 t1, 0x0103 | ||
| 332 | ld t1, OCTEON_CP2_AES_KEY+16(a0) | ||
| 333 | dmtc2 t2, 0x0104 | ||
| 334 | ld t2, OCTEON_CP2_AES_KEY+24(a0) | ||
| 335 | dmtc2 t0, 0x0105 | ||
| 336 | ld t0, OCTEON_CP2_AES_KEYLEN(a0) | ||
| 337 | dmtc2 t1, 0x0106 | ||
| 338 | ld t1, OCTEON_CP2_AES_RESULT(a0) | ||
| 339 | dmtc2 t2, 0x0107 | ||
| 340 | ld t2, OCTEON_CP2_AES_RESULT+8(a0) | ||
| 341 | mfc0 t3, $15,0 /* Get the processor ID register */ | ||
| 342 | dmtc2 t0, 0x0110 | ||
| 343 | li t0, 0x000d0000 /* This is the processor ID of Octeon Pass1 */ | ||
| 344 | dmtc2 t1, 0x0100 | ||
| 345 | bne t0, t3, 3f /* Skip the next stuff for non-pass1 */ | ||
| 346 | dmtc2 t2, 0x0101 | ||
| 347 | |||
| 348 | /* this code is specific for pass 1 */ | ||
| 349 | ld t0, OCTEON_CP2_HSH_DATW(a0) | ||
| 350 | ld t1, OCTEON_CP2_HSH_DATW+8(a0) | ||
| 351 | ld t2, OCTEON_CP2_HSH_DATW+16(a0) | ||
| 352 | dmtc2 t0, 0x0040 | ||
| 353 | ld t0, OCTEON_CP2_HSH_DATW+24(a0) | ||
| 354 | dmtc2 t1, 0x0041 | ||
| 355 | ld t1, OCTEON_CP2_HSH_DATW+32(a0) | ||
| 356 | dmtc2 t2, 0x0042 | ||
| 357 | ld t2, OCTEON_CP2_HSH_DATW+40(a0) | ||
| 358 | dmtc2 t0, 0x0043 | ||
| 359 | ld t0, OCTEON_CP2_HSH_DATW+48(a0) | ||
| 360 | dmtc2 t1, 0x0044 | ||
| 361 | ld t1, OCTEON_CP2_HSH_IVW(a0) | ||
| 362 | dmtc2 t2, 0x0045 | ||
| 363 | ld t2, OCTEON_CP2_HSH_IVW+8(a0) | ||
| 364 | dmtc2 t0, 0x0046 | ||
| 365 | ld t0, OCTEON_CP2_HSH_IVW+16(a0) | ||
| 366 | dmtc2 t1, 0x0048 | ||
| 367 | dmtc2 t2, 0x0049 | ||
| 368 | b done_restore /* unconditional branch */ | ||
| 369 | dmtc2 t0, 0x004A | ||
| 370 | |||
| 371 | 3: /* this is post-pass1 code */ | ||
| 372 | ld t2, OCTEON_CP2_HSH_DATW(a0) | ||
| 373 | ld t0, OCTEON_CP2_HSH_DATW+8(a0) | ||
| 374 | ld t1, OCTEON_CP2_HSH_DATW+16(a0) | ||
| 375 | dmtc2 t2, 0x0240 | ||
| 376 | ld t2, OCTEON_CP2_HSH_DATW+24(a0) | ||
| 377 | dmtc2 t0, 0x0241 | ||
| 378 | ld t0, OCTEON_CP2_HSH_DATW+32(a0) | ||
| 379 | dmtc2 t1, 0x0242 | ||
| 380 | ld t1, OCTEON_CP2_HSH_DATW+40(a0) | ||
| 381 | dmtc2 t2, 0x0243 | ||
| 382 | ld t2, OCTEON_CP2_HSH_DATW+48(a0) | ||
| 383 | dmtc2 t0, 0x0244 | ||
| 384 | ld t0, OCTEON_CP2_HSH_DATW+56(a0) | ||
| 385 | dmtc2 t1, 0x0245 | ||
| 386 | ld t1, OCTEON_CP2_HSH_DATW+64(a0) | ||
| 387 | dmtc2 t2, 0x0246 | ||
| 388 | ld t2, OCTEON_CP2_HSH_DATW+72(a0) | ||
| 389 | dmtc2 t0, 0x0247 | ||
| 390 | ld t0, OCTEON_CP2_HSH_DATW+80(a0) | ||
| 391 | dmtc2 t1, 0x0248 | ||
| 392 | ld t1, OCTEON_CP2_HSH_DATW+88(a0) | ||
| 393 | dmtc2 t2, 0x0249 | ||
| 394 | ld t2, OCTEON_CP2_HSH_DATW+96(a0) | ||
| 395 | dmtc2 t0, 0x024A | ||
| 396 | ld t0, OCTEON_CP2_HSH_DATW+104(a0) | ||
| 397 | dmtc2 t1, 0x024B | ||
| 398 | ld t1, OCTEON_CP2_HSH_DATW+112(a0) | ||
| 399 | dmtc2 t2, 0x024C | ||
| 400 | ld t2, OCTEON_CP2_HSH_IVW(a0) | ||
| 401 | dmtc2 t0, 0x024D | ||
| 402 | ld t0, OCTEON_CP2_HSH_IVW+8(a0) | ||
| 403 | dmtc2 t1, 0x024E | ||
| 404 | ld t1, OCTEON_CP2_HSH_IVW+16(a0) | ||
| 405 | dmtc2 t2, 0x0250 | ||
| 406 | ld t2, OCTEON_CP2_HSH_IVW+24(a0) | ||
| 407 | dmtc2 t0, 0x0251 | ||
| 408 | ld t0, OCTEON_CP2_HSH_IVW+32(a0) | ||
| 409 | dmtc2 t1, 0x0252 | ||
| 410 | ld t1, OCTEON_CP2_HSH_IVW+40(a0) | ||
| 411 | dmtc2 t2, 0x0253 | ||
| 412 | ld t2, OCTEON_CP2_HSH_IVW+48(a0) | ||
| 413 | dmtc2 t0, 0x0254 | ||
| 414 | ld t0, OCTEON_CP2_HSH_IVW+56(a0) | ||
| 415 | dmtc2 t1, 0x0255 | ||
| 416 | ld t1, OCTEON_CP2_GFM_MULT(a0) | ||
| 417 | dmtc2 t2, 0x0256 | ||
| 418 | ld t2, OCTEON_CP2_GFM_MULT+8(a0) | ||
| 419 | dmtc2 t0, 0x0257 | ||
| 420 | ld t0, OCTEON_CP2_GFM_POLY(a0) | ||
| 421 | dmtc2 t1, 0x0258 | ||
| 422 | ld t1, OCTEON_CP2_GFM_RESULT(a0) | ||
| 423 | dmtc2 t2, 0x0259 | ||
| 424 | ld t2, OCTEON_CP2_GFM_RESULT+8(a0) | ||
| 425 | dmtc2 t0, 0x025E | ||
| 426 | dmtc2 t1, 0x025A | ||
| 427 | dmtc2 t2, 0x025B | ||
| 428 | |||
| 429 | done_restore: | ||
| 430 | jr ra | ||
| 431 | nop | ||
| 432 | END(octeon_cop2_restore) | ||
| 433 | .set pop | ||
| 434 | |||
| 435 | /* | ||
| 436 | * void octeon_mult_save() | ||
| 437 | * sp is assumed to point to a struct pt_regs | ||
| 438 | * | ||
| 439 | * NOTE: This is called in SAVE_SOME in stackframe.h. It can only | ||
| 440 | * safely modify k0 and k1. | ||
| 441 | */ | ||
| 442 | .align 7 | ||
| 443 | .set push | ||
| 444 | .set noreorder | ||
| 445 | LEAF(octeon_mult_save) | ||
| 446 | dmfc0 k0, $9,7 /* CvmCtl register. */ | ||
| 447 | bbit1 k0, 27, 1f /* Skip CvmCtl[NOMUL] */ | ||
| 448 | nop | ||
| 449 | |||
| 450 | /* Save the multiplier state */ | ||
| 451 | v3mulu k0, $0, $0 | ||
| 452 | v3mulu k1, $0, $0 | ||
| 453 | sd k0, PT_MTP(sp) /* PT_MTP has P0 */ | ||
| 454 | v3mulu k0, $0, $0 | ||
| 455 | sd k1, PT_MTP+8(sp) /* PT_MTP+8 has P1 */ | ||
| 456 | ori k1, $0, 1 | ||
| 457 | v3mulu k1, k1, $0 | ||
| 458 | sd k0, PT_MTP+16(sp) /* PT_MTP+16 has P2 */ | ||
| 459 | v3mulu k0, $0, $0 | ||
| 460 | sd k1, PT_MPL(sp) /* PT_MPL has MPL0 */ | ||
| 461 | v3mulu k1, $0, $0 | ||
| 462 | sd k0, PT_MPL+8(sp) /* PT_MPL+8 has MPL1 */ | ||
| 463 | jr ra | ||
| 464 | sd k1, PT_MPL+16(sp) /* PT_MPL+16 has MPL2 */ | ||
| 465 | |||
| 466 | 1: /* Resume here if CvmCtl[NOMUL] */ | ||
| 467 | jr ra | ||
| 468 | END(octeon_mult_save) | ||
| 469 | .set pop | ||
| 470 | |||
| 471 | /* | ||
| 472 | * void octeon_mult_restore() | ||
| 473 | * sp is assumed to point to a struct pt_regs | ||
| 474 | * | ||
| 475 | * NOTE: This is called in RESTORE_SOME in stackframe.h. | ||
| 476 | */ | ||
| 477 | .align 7 | ||
| 478 | .set push | ||
| 479 | .set noreorder | ||
| 480 | LEAF(octeon_mult_restore) | ||
| 481 | dmfc0 k1, $9,7 /* CvmCtl register. */ | ||
| 482 | ld v0, PT_MPL(sp) /* MPL0 */ | ||
| 483 | ld v1, PT_MPL+8(sp) /* MPL1 */ | ||
| 484 | ld k0, PT_MPL+16(sp) /* MPL2 */ | ||
| 485 | bbit1 k1, 27, 1f /* Skip CvmCtl[NOMUL] */ | ||
| 486 | /* Normally falls through, so no time wasted here */ | ||
| 487 | nop | ||
| 488 | |||
| 489 | /* Restore the multiplier state */ | ||
| 490 | ld k1, PT_MTP+16(sp) /* P2 */ | ||
| 491 | MTM0 v0 /* MPL0 */ | ||
| 492 | ld v0, PT_MTP+8(sp) /* P1 */ | ||
| 493 | MTM1 v1 /* MPL1 */ | ||
| 494 | ld v1, PT_MTP(sp) /* P0 */ | ||
| 495 | MTM2 k0 /* MPL2 */ | ||
| 496 | MTP2 k1 /* P2 */ | ||
| 497 | MTP1 v0 /* P1 */ | ||
| 498 | jr ra | ||
| 499 | MTP0 v1 /* P0 */ | ||
| 500 | |||
| 501 | 1: /* Resume here if CvmCtl[NOMUL] */ | ||
| 502 | jr ra | ||
| 503 | nop | ||
| 504 | END(octeon_mult_restore) | ||
| 505 | .set pop | ||
| 506 | |||
diff --git a/arch/mips/kernel/ptrace32.c b/arch/mips/kernel/ptrace32.c index 1ca34104e593..c4f9ac17474a 100644 --- a/arch/mips/kernel/ptrace32.c +++ b/arch/mips/kernel/ptrace32.c | |||
| @@ -49,19 +49,6 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request, | |||
| 49 | int ret; | 49 | int ret; |
| 50 | 50 | ||
| 51 | switch (request) { | 51 | switch (request) { |
| 52 | /* when I and D space are separate, these will need to be fixed. */ | ||
| 53 | case PTRACE_PEEKTEXT: /* read word at location addr. */ | ||
| 54 | case PTRACE_PEEKDATA: { | ||
| 55 | unsigned int tmp; | ||
| 56 | int copied; | ||
| 57 | |||
| 58 | copied = access_process_vm(child, addr, &tmp, sizeof(tmp), 0); | ||
| 59 | ret = -EIO; | ||
| 60 | if (copied != sizeof(tmp)) | ||
| 61 | break; | ||
| 62 | ret = put_user(tmp, (unsigned int __user *) (unsigned long) data); | ||
| 63 | break; | ||
| 64 | } | ||
| 65 | 52 | ||
| 66 | /* | 53 | /* |
| 67 | * Read 4 bytes of the other process' storage | 54 | * Read 4 bytes of the other process' storage |
| @@ -208,16 +195,6 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request, | |||
| 208 | break; | 195 | break; |
| 209 | } | 196 | } |
| 210 | 197 | ||
| 211 | /* when I and D space are separate, this will have to be fixed. */ | ||
| 212 | case PTRACE_POKETEXT: /* write the word at location addr. */ | ||
| 213 | case PTRACE_POKEDATA: | ||
| 214 | ret = 0; | ||
| 215 | if (access_process_vm(child, addr, &data, sizeof(data), 1) | ||
| 216 | == sizeof(data)) | ||
| 217 | break; | ||
| 218 | ret = -EIO; | ||
| 219 | break; | ||
| 220 | |||
| 221 | /* | 198 | /* |
| 222 | * Write 4 bytes into the other process' storage | 199 | * Write 4 bytes into the other process' storage |
| 223 | * data is the 4 bytes that the user wants written | 200 | * data is the 4 bytes that the user wants written |
| @@ -332,50 +309,11 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request, | |||
| 332 | ret = ptrace_setfpregs(child, (__u32 __user *) (__u64) data); | 309 | ret = ptrace_setfpregs(child, (__u32 __user *) (__u64) data); |
| 333 | break; | 310 | break; |
| 334 | 311 | ||
| 335 | case PTRACE_SYSCALL: /* continue and stop at next (return from) syscall */ | ||
| 336 | case PTRACE_CONT: { /* restart after signal. */ | ||
| 337 | ret = -EIO; | ||
| 338 | if (!valid_signal(data)) | ||
| 339 | break; | ||
| 340 | if (request == PTRACE_SYSCALL) { | ||
| 341 | set_tsk_thread_flag(child, TIF_SYSCALL_TRACE); | ||
| 342 | } | ||
| 343 | else { | ||
| 344 | clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE); | ||
| 345 | } | ||
| 346 | child->exit_code = data; | ||
| 347 | wake_up_process(child); | ||
| 348 | ret = 0; | ||
| 349 | break; | ||
| 350 | } | ||
| 351 | |||
| 352 | /* | ||
| 353 | * make the child exit. Best I can do is send it a sigkill. | ||
| 354 | * perhaps it should be put in the status that it wants to | ||
| 355 | * exit. | ||
| 356 | */ | ||
| 357 | case PTRACE_KILL: | ||
| 358 | ret = 0; | ||
| 359 | if (child->exit_state == EXIT_ZOMBIE) /* already dead */ | ||
| 360 | break; | ||
| 361 | child->exit_code = SIGKILL; | ||
| 362 | wake_up_process(child); | ||
| 363 | break; | ||
| 364 | |||
| 365 | case PTRACE_GET_THREAD_AREA: | 312 | case PTRACE_GET_THREAD_AREA: |
| 366 | ret = put_user(task_thread_info(child)->tp_value, | 313 | ret = put_user(task_thread_info(child)->tp_value, |
| 367 | (unsigned int __user *) (unsigned long) data); | 314 | (unsigned int __user *) (unsigned long) data); |
| 368 | break; | 315 | break; |
| 369 | 316 | ||
| 370 | case PTRACE_DETACH: /* detach a process that was attached. */ | ||
| 371 | ret = ptrace_detach(child, data); | ||
| 372 | break; | ||
| 373 | |||
| 374 | case PTRACE_GETEVENTMSG: | ||
| 375 | ret = put_user(child->ptrace_message, | ||
| 376 | (unsigned int __user *) (unsigned long) data); | ||
| 377 | break; | ||
| 378 | |||
| 379 | case PTRACE_GET_THREAD_AREA_3264: | 317 | case PTRACE_GET_THREAD_AREA_3264: |
| 380 | ret = put_user(task_thread_info(child)->tp_value, | 318 | ret = put_user(task_thread_info(child)->tp_value, |
| 381 | (unsigned long __user *) (unsigned long) data); | 319 | (unsigned long __user *) (unsigned long) data); |
| @@ -392,7 +330,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request, | |||
| 392 | break; | 330 | break; |
| 393 | 331 | ||
| 394 | default: | 332 | default: |
| 395 | ret = ptrace_request(child, request, addr, data); | 333 | ret = compat_ptrace_request(child, request, addr, data); |
| 396 | break; | 334 | break; |
| 397 | } | 335 | } |
| 398 | out: | 336 | out: |
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 353056110f2b..f6083c6bfaa4 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c | |||
| @@ -47,6 +47,7 @@ | |||
| 47 | #include <asm/mmu_context.h> | 47 | #include <asm/mmu_context.h> |
| 48 | #include <asm/types.h> | 48 | #include <asm/types.h> |
| 49 | #include <asm/stacktrace.h> | 49 | #include <asm/stacktrace.h> |
| 50 | #include <asm/irq.h> | ||
| 50 | 51 | ||
| 51 | extern void check_wait(void); | 52 | extern void check_wait(void); |
| 52 | extern asmlinkage void r4k_wait(void); | 53 | extern asmlinkage void r4k_wait(void); |
| @@ -78,6 +79,10 @@ extern asmlinkage void handle_reserved(void); | |||
| 78 | extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, | 79 | extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, |
| 79 | struct mips_fpu_struct *ctx, int has_fpu); | 80 | struct mips_fpu_struct *ctx, int has_fpu); |
| 80 | 81 | ||
| 82 | #ifdef CONFIG_CPU_CAVIUM_OCTEON | ||
| 83 | extern asmlinkage void octeon_cop2_restore(struct octeon_cop2_state *task); | ||
| 84 | #endif | ||
| 85 | |||
| 81 | void (*board_be_init)(void); | 86 | void (*board_be_init)(void); |
| 82 | int (*board_be_handler)(struct pt_regs *regs, int is_fixup); | 87 | int (*board_be_handler)(struct pt_regs *regs, int is_fixup); |
| 83 | void (*board_nmi_handler_setup)(void); | 88 | void (*board_nmi_handler_setup)(void); |
| @@ -860,6 +865,7 @@ asmlinkage void do_cpu(struct pt_regs *regs) | |||
| 860 | unsigned int opcode; | 865 | unsigned int opcode; |
| 861 | unsigned int cpid; | 866 | unsigned int cpid; |
| 862 | int status; | 867 | int status; |
| 868 | unsigned long __maybe_unused flags; | ||
| 863 | 869 | ||
| 864 | die_if_kernel("do_cpu invoked from kernel context!", regs); | 870 | die_if_kernel("do_cpu invoked from kernel context!", regs); |
| 865 | 871 | ||
| @@ -915,6 +921,17 @@ asmlinkage void do_cpu(struct pt_regs *regs) | |||
| 915 | return; | 921 | return; |
| 916 | 922 | ||
| 917 | case 2: | 923 | case 2: |
| 924 | #ifdef CONFIG_CPU_CAVIUM_OCTEON | ||
| 925 | prefetch(¤t->thread.cp2); | ||
| 926 | local_irq_save(flags); | ||
| 927 | KSTK_STATUS(current) |= ST0_CU2; | ||
| 928 | status = read_c0_status(); | ||
| 929 | write_c0_status(status | ST0_CU2); | ||
| 930 | octeon_cop2_restore(&(current->thread.cp2)); | ||
| 931 | write_c0_status(status & ~ST0_CU2); | ||
| 932 | local_irq_restore(flags); | ||
| 933 | return; | ||
| 934 | #endif | ||
| 918 | case 3: | 935 | case 3: |
| 919 | break; | 936 | break; |
| 920 | } | 937 | } |
| @@ -1488,6 +1505,10 @@ void __cpuinit per_cpu_trap_init(void) | |||
| 1488 | write_c0_hwrena(enable); | 1505 | write_c0_hwrena(enable); |
| 1489 | } | 1506 | } |
| 1490 | 1507 | ||
| 1508 | #ifdef CONFIG_CPU_CAVIUM_OCTEON | ||
| 1509 | write_c0_hwrena(0xc000000f); /* Octeon has register 30 and 31 */ | ||
| 1510 | #endif | ||
| 1511 | |||
| 1491 | #ifdef CONFIG_MIPS_MT_SMTC | 1512 | #ifdef CONFIG_MIPS_MT_SMTC |
| 1492 | if (!secondaryTC) { | 1513 | if (!secondaryTC) { |
| 1493 | #endif /* CONFIG_MIPS_MT_SMTC */ | 1514 | #endif /* CONFIG_MIPS_MT_SMTC */ |
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index dbcf6511b74e..c13c7ad2cdae 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile | |||
| @@ -27,6 +27,7 @@ obj-$(CONFIG_CPU_SB1) += dump_tlb.o | |||
| 27 | obj-$(CONFIG_CPU_TX39XX) += r3k_dump_tlb.o | 27 | obj-$(CONFIG_CPU_TX39XX) += r3k_dump_tlb.o |
| 28 | obj-$(CONFIG_CPU_TX49XX) += dump_tlb.o | 28 | obj-$(CONFIG_CPU_TX49XX) += dump_tlb.o |
| 29 | obj-$(CONFIG_CPU_VR41XX) += dump_tlb.o | 29 | obj-$(CONFIG_CPU_VR41XX) += dump_tlb.o |
| 30 | obj-$(CONFIG_CPU_CAVIUM_OCTEON) += dump_tlb.o | ||
| 30 | 31 | ||
| 31 | # libgcc-style stuff needed in the kernel | 32 | # libgcc-style stuff needed in the kernel |
| 32 | obj-y += ashldi3.o ashrdi3.o cmpdi2.o lshrdi3.o ucmpdi2.o | 33 | obj-y += ashldi3.o ashrdi3.o cmpdi2.o lshrdi3.o ucmpdi2.o |
diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile index 95ba32b5b720..d7ec95522292 100644 --- a/arch/mips/mm/Makefile +++ b/arch/mips/mm/Makefile | |||
| @@ -27,6 +27,7 @@ obj-$(CONFIG_CPU_SB1) += c-r4k.o cerr-sb1.o cex-sb1.o tlb-r4k.o | |||
| 27 | obj-$(CONFIG_CPU_TX39XX) += c-tx39.o tlb-r3k.o | 27 | obj-$(CONFIG_CPU_TX39XX) += c-tx39.o tlb-r3k.o |
| 28 | obj-$(CONFIG_CPU_TX49XX) += c-r4k.o cex-gen.o tlb-r4k.o | 28 | obj-$(CONFIG_CPU_TX49XX) += c-r4k.o cex-gen.o tlb-r4k.o |
| 29 | obj-$(CONFIG_CPU_VR41XX) += c-r4k.o cex-gen.o tlb-r4k.o | 29 | obj-$(CONFIG_CPU_VR41XX) += c-r4k.o cex-gen.o tlb-r4k.o |
| 30 | obj-$(CONFIG_CPU_CAVIUM_OCTEON) += c-octeon.o cex-oct.o tlb-r4k.o | ||
| 30 | 31 | ||
| 31 | obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o | 32 | obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o |
| 32 | obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o | 33 | obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o |
diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c new file mode 100644 index 000000000000..44d01a0a8490 --- /dev/null +++ b/arch/mips/mm/c-octeon.c | |||
| @@ -0,0 +1,307 @@ | |||
| 1 | /* | ||
| 2 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 3 | * License. See the file "COPYING" in the main directory of this archive | ||
| 4 | * for more details. | ||
| 5 | * | ||
| 6 | * Copyright (C) 2005-2007 Cavium Networks | ||
| 7 | */ | ||
| 8 | #include <linux/init.h> | ||
| 9 | #include <linux/kernel.h> | ||
| 10 | #include <linux/sched.h> | ||
| 11 | #include <linux/mm.h> | ||
| 12 | #include <linux/bitops.h> | ||
| 13 | #include <linux/cpu.h> | ||
| 14 | #include <linux/io.h> | ||
| 15 | |||
| 16 | #include <asm/bcache.h> | ||
| 17 | #include <asm/bootinfo.h> | ||
| 18 | #include <asm/cacheops.h> | ||
| 19 | #include <asm/cpu-features.h> | ||
| 20 | #include <asm/page.h> | ||
| 21 | #include <asm/pgtable.h> | ||
| 22 | #include <asm/r4kcache.h> | ||
| 23 | #include <asm/system.h> | ||
| 24 | #include <asm/mmu_context.h> | ||
| 25 | #include <asm/war.h> | ||
| 26 | |||
| 27 | #include <asm/octeon/octeon.h> | ||
| 28 | |||
| 29 | unsigned long long cache_err_dcache[NR_CPUS]; | ||
| 30 | |||
| 31 | /** | ||
| 32 | * Octeon automatically flushes the dcache on tlb changes, so | ||
| 33 | * from Linux's viewpoint it acts much like a physically | ||
| 34 | * tagged cache. No flushing is needed | ||
| 35 | * | ||
| 36 | */ | ||
| 37 | static void octeon_flush_data_cache_page(unsigned long addr) | ||
| 38 | { | ||
| 39 | /* Nothing to do */ | ||
| 40 | } | ||
| 41 | |||
| 42 | static inline void octeon_local_flush_icache(void) | ||
| 43 | { | ||
| 44 | asm volatile ("synci 0($0)"); | ||
| 45 | } | ||
| 46 | |||
| 47 | /* | ||
| 48 | * Flush local I-cache for the specified range. | ||
| 49 | */ | ||
| 50 | static void local_octeon_flush_icache_range(unsigned long start, | ||
| 51 | unsigned long end) | ||
| 52 | { | ||
| 53 | octeon_local_flush_icache(); | ||
| 54 | } | ||
| 55 | |||
| 56 | /** | ||
| 57 | * Flush caches as necessary for all cores affected by a | ||
| 58 | * vma. If no vma is supplied, all cores are flushed. | ||
| 59 | * | ||
| 60 | * @vma: VMA to flush or NULL to flush all icaches. | ||
| 61 | */ | ||
| 62 | static void octeon_flush_icache_all_cores(struct vm_area_struct *vma) | ||
| 63 | { | ||
| 64 | extern void octeon_send_ipi_single(int cpu, unsigned int action); | ||
| 65 | #ifdef CONFIG_SMP | ||
| 66 | int cpu; | ||
| 67 | cpumask_t mask; | ||
| 68 | #endif | ||
| 69 | |||
| 70 | mb(); | ||
| 71 | octeon_local_flush_icache(); | ||
| 72 | #ifdef CONFIG_SMP | ||
| 73 | preempt_disable(); | ||
| 74 | cpu = smp_processor_id(); | ||
| 75 | |||
| 76 | /* | ||
| 77 | * If we have a vma structure, we only need to worry about | ||
| 78 | * cores it has been used on | ||
| 79 | */ | ||
| 80 | if (vma) | ||
| 81 | mask = vma->vm_mm->cpu_vm_mask; | ||
| 82 | else | ||
| 83 | mask = cpu_online_map; | ||
| 84 | cpu_clear(cpu, mask); | ||
| 85 | for_each_cpu_mask(cpu, mask) | ||
| 86 | octeon_send_ipi_single(cpu, SMP_ICACHE_FLUSH); | ||
| 87 | |||
| 88 | preempt_enable(); | ||
| 89 | #endif | ||
| 90 | } | ||
| 91 | |||
| 92 | |||
| 93 | /** | ||
| 94 | * Called to flush the icache on all cores | ||
| 95 | */ | ||
| 96 | static void octeon_flush_icache_all(void) | ||
| 97 | { | ||
| 98 | octeon_flush_icache_all_cores(NULL); | ||
| 99 | } | ||
| 100 | |||
| 101 | |||
| 102 | /** | ||
| 103 | * Called to flush all memory associated with a memory | ||
| 104 | * context. | ||
| 105 | * | ||
| 106 | * @mm: Memory context to flush | ||
| 107 | */ | ||
| 108 | static void octeon_flush_cache_mm(struct mm_struct *mm) | ||
| 109 | { | ||
| 110 | /* | ||
| 111 | * According to the R4K version of this file, CPUs without | ||
| 112 | * dcache aliases don't need to do anything here | ||
| 113 | */ | ||
| 114 | } | ||
| 115 | |||
| 116 | |||
| 117 | /** | ||
| 118 | * Flush a range of kernel addresses out of the icache | ||
| 119 | * | ||
| 120 | */ | ||
| 121 | static void octeon_flush_icache_range(unsigned long start, unsigned long end) | ||
| 122 | { | ||
| 123 | octeon_flush_icache_all_cores(NULL); | ||
| 124 | } | ||
| 125 | |||
| 126 | |||
| 127 | /** | ||
| 128 | * Flush the icache for a trampoline. These are used for interrupt | ||
| 129 | * and exception hooking. | ||
| 130 | * | ||
| 131 | * @addr: Address to flush | ||
| 132 | */ | ||
| 133 | static void octeon_flush_cache_sigtramp(unsigned long addr) | ||
| 134 | { | ||
| 135 | struct vm_area_struct *vma; | ||
| 136 | |||
| 137 | vma = find_vma(current->mm, addr); | ||
| 138 | octeon_flush_icache_all_cores(vma); | ||
| 139 | } | ||
| 140 | |||
| 141 | |||
| 142 | /** | ||
| 143 | * Flush a range out of a vma | ||
| 144 | * | ||
| 145 | * @vma: VMA to flush | ||
| 146 | * @start: | ||
| 147 | * @end: | ||
| 148 | */ | ||
| 149 | static void octeon_flush_cache_range(struct vm_area_struct *vma, | ||
| 150 | unsigned long start, unsigned long end) | ||
| 151 | { | ||
| 152 | if (vma->vm_flags & VM_EXEC) | ||
| 153 | octeon_flush_icache_all_cores(vma); | ||
| 154 | } | ||
| 155 | |||
| 156 | |||
| 157 | /** | ||
| 158 | * Flush a specific page of a vma | ||
| 159 | * | ||
| 160 | * @vma: VMA to flush page for | ||
| 161 | * @page: Page to flush | ||
| 162 | * @pfn: | ||
| 163 | */ | ||
| 164 | static void octeon_flush_cache_page(struct vm_area_struct *vma, | ||
| 165 | unsigned long page, unsigned long pfn) | ||
| 166 | { | ||
| 167 | if (vma->vm_flags & VM_EXEC) | ||
| 168 | octeon_flush_icache_all_cores(vma); | ||
| 169 | } | ||
| 170 | |||
| 171 | |||
| 172 | /** | ||
| 173 | * Probe Octeon's caches | ||
| 174 | * | ||
| 175 | */ | ||
| 176 | static void __devinit probe_octeon(void) | ||
| 177 | { | ||
| 178 | unsigned long icache_size; | ||
| 179 | unsigned long dcache_size; | ||
| 180 | unsigned int config1; | ||
| 181 | struct cpuinfo_mips *c = ¤t_cpu_data; | ||
| 182 | |||
| 183 | switch (c->cputype) { | ||
| 184 | case CPU_CAVIUM_OCTEON: | ||
| 185 | config1 = read_c0_config1(); | ||
| 186 | c->icache.linesz = 2 << ((config1 >> 19) & 7); | ||
| 187 | c->icache.sets = 64 << ((config1 >> 22) & 7); | ||
| 188 | c->icache.ways = 1 + ((config1 >> 16) & 7); | ||
| 189 | c->icache.flags |= MIPS_CACHE_VTAG; | ||
| 190 | icache_size = | ||
| 191 | c->icache.sets * c->icache.ways * c->icache.linesz; | ||
| 192 | c->icache.waybit = ffs(icache_size / c->icache.ways) - 1; | ||
| 193 | c->dcache.linesz = 128; | ||
| 194 | if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) | ||
| 195 | c->dcache.sets = 1; /* CN3XXX has one Dcache set */ | ||
| 196 | else | ||
| 197 | c->dcache.sets = 2; /* CN5XXX has two Dcache sets */ | ||
| 198 | c->dcache.ways = 64; | ||
| 199 | dcache_size = | ||
| 200 | c->dcache.sets * c->dcache.ways * c->dcache.linesz; | ||
| 201 | c->dcache.waybit = ffs(dcache_size / c->dcache.ways) - 1; | ||
| 202 | c->options |= MIPS_CPU_PREFETCH; | ||
| 203 | break; | ||
| 204 | |||
| 205 | default: | ||
| 206 | panic("Unsupported Cavium Networks CPU type\n"); | ||
| 207 | break; | ||
| 208 | } | ||
| 209 | |||
| 210 | /* compute a couple of other cache variables */ | ||
| 211 | c->icache.waysize = icache_size / c->icache.ways; | ||
| 212 | c->dcache.waysize = dcache_size / c->dcache.ways; | ||
| 213 | |||
| 214 | c->icache.sets = icache_size / (c->icache.linesz * c->icache.ways); | ||
| 215 | c->dcache.sets = dcache_size / (c->dcache.linesz * c->dcache.ways); | ||
| 216 | |||
| 217 | if (smp_processor_id() == 0) { | ||
| 218 | pr_notice("Primary instruction cache %ldkB, %s, %d way, " | ||
| 219 | "%d sets, linesize %d bytes.\n", | ||
| 220 | icache_size >> 10, | ||
| 221 | cpu_has_vtag_icache ? | ||
| 222 | "virtually tagged" : "physically tagged", | ||
| 223 | c->icache.ways, c->icache.sets, c->icache.linesz); | ||
| 224 | |||
| 225 | pr_notice("Primary data cache %ldkB, %d-way, %d sets, " | ||
| 226 | "linesize %d bytes.\n", | ||
| 227 | dcache_size >> 10, c->dcache.ways, | ||
| 228 | c->dcache.sets, c->dcache.linesz); | ||
| 229 | } | ||
| 230 | } | ||
| 231 | |||
| 232 | |||
| 233 | /** | ||
| 234 | * Setup the Octeon cache flush routines | ||
| 235 | * | ||
| 236 | */ | ||
| 237 | void __devinit octeon_cache_init(void) | ||
| 238 | { | ||
| 239 | extern unsigned long ebase; | ||
| 240 | extern char except_vec2_octeon; | ||
| 241 | |||
| 242 | memcpy((void *)(ebase + 0x100), &except_vec2_octeon, 0x80); | ||
| 243 | octeon_flush_cache_sigtramp(ebase + 0x100); | ||
| 244 | |||
| 245 | probe_octeon(); | ||
| 246 | |||
| 247 | shm_align_mask = PAGE_SIZE - 1; | ||
| 248 | |||
| 249 | flush_cache_all = octeon_flush_icache_all; | ||
| 250 | __flush_cache_all = octeon_flush_icache_all; | ||
| 251 | flush_cache_mm = octeon_flush_cache_mm; | ||
| 252 | flush_cache_page = octeon_flush_cache_page; | ||
| 253 | flush_cache_range = octeon_flush_cache_range; | ||
| 254 | flush_cache_sigtramp = octeon_flush_cache_sigtramp; | ||
| 255 | flush_icache_all = octeon_flush_icache_all; | ||
| 256 | flush_data_cache_page = octeon_flush_data_cache_page; | ||
| 257 | flush_icache_range = octeon_flush_icache_range; | ||
| 258 | local_flush_icache_range = local_octeon_flush_icache_range; | ||
| 259 | |||
| 260 | build_clear_page(); | ||
| 261 | build_copy_page(); | ||
| 262 | } | ||
| 263 | |||
| 264 | /** | ||
| 265 | * Handle a cache error exception | ||
| 266 | */ | ||
| 267 | |||
| 268 | static void cache_parity_error_octeon(int non_recoverable) | ||
| 269 | { | ||
| 270 | unsigned long coreid = cvmx_get_core_num(); | ||
| 271 | uint64_t icache_err = read_octeon_c0_icacheerr(); | ||
| 272 | |||
| 273 | pr_err("Cache error exception:\n"); | ||
| 274 | pr_err("cp0_errorepc == %lx\n", read_c0_errorepc()); | ||
| 275 | if (icache_err & 1) { | ||
| 276 | pr_err("CacheErr (Icache) == %llx\n", | ||
| 277 | (unsigned long long)icache_err); | ||
| 278 | write_octeon_c0_icacheerr(0); | ||
| 279 | } | ||
| 280 | if (cache_err_dcache[coreid] & 1) { | ||
| 281 | pr_err("CacheErr (Dcache) == %llx\n", | ||
| 282 | (unsigned long long)cache_err_dcache[coreid]); | ||
| 283 | cache_err_dcache[coreid] = 0; | ||
| 284 | } | ||
| 285 | |||
| 286 | if (non_recoverable) | ||
| 287 | panic("Can't handle cache error: nested exception"); | ||
| 288 | } | ||
| 289 | |||
| 290 | /** | ||
| 291 | * Called when the the exception is not recoverable | ||
| 292 | */ | ||
| 293 | |||
| 294 | asmlinkage void cache_parity_error_octeon_recoverable(void) | ||
| 295 | { | ||
| 296 | cache_parity_error_octeon(0); | ||
| 297 | } | ||
| 298 | |||
| 299 | /** | ||
| 300 | * Called when the the exception is recoverable | ||
| 301 | */ | ||
| 302 | |||
| 303 | asmlinkage void cache_parity_error_octeon_non_recoverable(void) | ||
| 304 | { | ||
| 305 | cache_parity_error_octeon(1); | ||
| 306 | } | ||
| 307 | |||
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c index 1eb7c71e3d6a..98ad0a82c29e 100644 --- a/arch/mips/mm/cache.c +++ b/arch/mips/mm/cache.c | |||
| @@ -182,6 +182,12 @@ void __devinit cpu_cache_init(void) | |||
| 182 | tx39_cache_init(); | 182 | tx39_cache_init(); |
| 183 | } | 183 | } |
| 184 | 184 | ||
| 185 | if (cpu_has_octeon_cache) { | ||
| 186 | extern void __weak octeon_cache_init(void); | ||
| 187 | |||
| 188 | octeon_cache_init(); | ||
| 189 | } | ||
| 190 | |||
| 185 | setup_protection_map(); | 191 | setup_protection_map(); |
| 186 | } | 192 | } |
| 187 | 193 | ||
diff --git a/arch/mips/mm/cex-oct.S b/arch/mips/mm/cex-oct.S new file mode 100644 index 000000000000..3db8553fcd34 --- /dev/null +++ b/arch/mips/mm/cex-oct.S | |||
| @@ -0,0 +1,70 @@ | |||
| 1 | /* | ||
| 2 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 3 | * License. See the file "COPYING" in the main directory of this archive | ||
| 4 | * for more details. | ||
| 5 | * | ||
| 6 | * Copyright (C) 2006 Cavium Networks | ||
| 7 | * Cache error handler | ||
| 8 | */ | ||
| 9 | |||
| 10 | #include <asm/asm.h> | ||
| 11 | #include <asm/regdef.h> | ||
| 12 | #include <asm/mipsregs.h> | ||
| 13 | #include <asm/stackframe.h> | ||
| 14 | |||
| 15 | /* | ||
| 16 | * Handle cache error. Indicate to the second level handler whether | ||
| 17 | * the exception is recoverable. | ||
| 18 | */ | ||
| 19 | LEAF(except_vec2_octeon) | ||
| 20 | |||
| 21 | .set push | ||
| 22 | .set mips64r2 | ||
| 23 | .set noreorder | ||
| 24 | .set noat | ||
| 25 | |||
| 26 | |||
| 27 | /* due to an errata we need to read the COP0 CacheErr (Dcache) | ||
| 28 | * before any cache/DRAM access */ | ||
| 29 | |||
| 30 | rdhwr k0, $0 /* get core_id */ | ||
| 31 | PTR_LA k1, cache_err_dcache | ||
| 32 | sll k0, k0, 3 | ||
| 33 | PTR_ADDU k1, k0, k1 /* k1 = &cache_err_dcache[core_id] */ | ||
| 34 | |||
| 35 | dmfc0 k0, CP0_CACHEERR, 1 | ||
| 36 | sd k0, (k1) | ||
| 37 | dmtc0 $0, CP0_CACHEERR, 1 | ||
| 38 | |||
| 39 | /* check whether this is a nested exception */ | ||
| 40 | mfc0 k1, CP0_STATUS | ||
| 41 | andi k1, k1, ST0_EXL | ||
| 42 | beqz k1, 1f | ||
| 43 | nop | ||
| 44 | j cache_parity_error_octeon_non_recoverable | ||
| 45 | nop | ||
| 46 | |||
| 47 | /* exception is recoverable */ | ||
| 48 | 1: j handle_cache_err | ||
| 49 | nop | ||
| 50 | |||
| 51 | .set pop | ||
| 52 | END(except_vec2_octeon) | ||
| 53 | |||
| 54 | /* We need to jump to handle_cache_err so that the previous handler | ||
| 55 | * can fit within 0x80 bytes. We also move from 0xFFFFFFFFAXXXXXXX | ||
| 56 | * space (uncached) to the 0xFFFFFFFF8XXXXXXX space (cached). */ | ||
| 57 | LEAF(handle_cache_err) | ||
| 58 | .set push | ||
| 59 | .set noreorder | ||
| 60 | .set noat | ||
| 61 | |||
| 62 | SAVE_ALL | ||
| 63 | KMODE | ||
| 64 | jal cache_parity_error_octeon_recoverable | ||
| 65 | nop | ||
| 66 | j ret_from_exception | ||
| 67 | nop | ||
| 68 | |||
| 69 | .set pop | ||
| 70 | END(handle_cache_err) | ||
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c index e6708b3ad343..546e6977d4ff 100644 --- a/arch/mips/mm/dma-default.c +++ b/arch/mips/mm/dma-default.c | |||
| @@ -111,7 +111,7 @@ EXPORT_SYMBOL(dma_alloc_coherent); | |||
| 111 | void dma_free_noncoherent(struct device *dev, size_t size, void *vaddr, | 111 | void dma_free_noncoherent(struct device *dev, size_t size, void *vaddr, |
| 112 | dma_addr_t dma_handle) | 112 | dma_addr_t dma_handle) |
| 113 | { | 113 | { |
| 114 | plat_unmap_dma_mem(dma_handle); | 114 | plat_unmap_dma_mem(dev, dma_handle); |
| 115 | free_pages((unsigned long) vaddr, get_order(size)); | 115 | free_pages((unsigned long) vaddr, get_order(size)); |
| 116 | } | 116 | } |
| 117 | 117 | ||
| @@ -122,7 +122,7 @@ void dma_free_coherent(struct device *dev, size_t size, void *vaddr, | |||
| 122 | { | 122 | { |
| 123 | unsigned long addr = (unsigned long) vaddr; | 123 | unsigned long addr = (unsigned long) vaddr; |
| 124 | 124 | ||
| 125 | plat_unmap_dma_mem(dma_handle); | 125 | plat_unmap_dma_mem(dev, dma_handle); |
| 126 | 126 | ||
| 127 | if (!plat_device_is_coherent(dev)) | 127 | if (!plat_device_is_coherent(dev)) |
| 128 | addr = CAC_ADDR(addr); | 128 | addr = CAC_ADDR(addr); |
| @@ -173,7 +173,7 @@ void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, | |||
| 173 | __dma_sync(dma_addr_to_virt(dma_addr), size, | 173 | __dma_sync(dma_addr_to_virt(dma_addr), size, |
| 174 | direction); | 174 | direction); |
| 175 | 175 | ||
| 176 | plat_unmap_dma_mem(dma_addr); | 176 | plat_unmap_dma_mem(dev, dma_addr); |
| 177 | } | 177 | } |
| 178 | 178 | ||
| 179 | EXPORT_SYMBOL(dma_unmap_single); | 179 | EXPORT_SYMBOL(dma_unmap_single); |
| @@ -229,7 +229,7 @@ void dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size, | |||
| 229 | dma_cache_wback_inv(addr, size); | 229 | dma_cache_wback_inv(addr, size); |
| 230 | } | 230 | } |
| 231 | 231 | ||
| 232 | plat_unmap_dma_mem(dma_address); | 232 | plat_unmap_dma_mem(dev, dma_address); |
| 233 | } | 233 | } |
| 234 | 234 | ||
| 235 | EXPORT_SYMBOL(dma_unmap_page); | 235 | EXPORT_SYMBOL(dma_unmap_page); |
| @@ -249,7 +249,7 @@ void dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries, | |||
| 249 | if (addr) | 249 | if (addr) |
| 250 | __dma_sync(addr, sg->length, direction); | 250 | __dma_sync(addr, sg->length, direction); |
| 251 | } | 251 | } |
| 252 | plat_unmap_dma_mem(sg->dma_address); | 252 | plat_unmap_dma_mem(dev, sg->dma_address); |
| 253 | } | 253 | } |
| 254 | } | 254 | } |
| 255 | 255 | ||
| @@ -275,6 +275,7 @@ void dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle, | |||
| 275 | { | 275 | { |
| 276 | BUG_ON(direction == DMA_NONE); | 276 | BUG_ON(direction == DMA_NONE); |
| 277 | 277 | ||
| 278 | plat_extra_sync_for_device(dev); | ||
| 278 | if (!plat_device_is_coherent(dev)) { | 279 | if (!plat_device_is_coherent(dev)) { |
| 279 | unsigned long addr; | 280 | unsigned long addr; |
| 280 | 281 | ||
| @@ -305,6 +306,7 @@ void dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle, | |||
| 305 | { | 306 | { |
| 306 | BUG_ON(direction == DMA_NONE); | 307 | BUG_ON(direction == DMA_NONE); |
| 307 | 308 | ||
| 309 | plat_extra_sync_for_device(dev); | ||
| 308 | if (!plat_device_is_coherent(dev)) { | 310 | if (!plat_device_is_coherent(dev)) { |
| 309 | unsigned long addr; | 311 | unsigned long addr; |
| 310 | 312 | ||
| @@ -351,22 +353,14 @@ EXPORT_SYMBOL(dma_sync_sg_for_device); | |||
| 351 | 353 | ||
| 352 | int dma_mapping_error(struct device *dev, dma_addr_t dma_addr) | 354 | int dma_mapping_error(struct device *dev, dma_addr_t dma_addr) |
| 353 | { | 355 | { |
| 354 | return 0; | 356 | return plat_dma_mapping_error(dev, dma_addr); |
| 355 | } | 357 | } |
| 356 | 358 | ||
| 357 | EXPORT_SYMBOL(dma_mapping_error); | 359 | EXPORT_SYMBOL(dma_mapping_error); |
| 358 | 360 | ||
| 359 | int dma_supported(struct device *dev, u64 mask) | 361 | int dma_supported(struct device *dev, u64 mask) |
| 360 | { | 362 | { |
| 361 | /* | 363 | return plat_dma_supported(dev, mask); |
| 362 | * we fall back to GFP_DMA when the mask isn't all 1s, | ||
| 363 | * so we can't guarantee allocations that must be | ||
| 364 | * within a tighter range than GFP_DMA.. | ||
| 365 | */ | ||
| 366 | if (mask < DMA_BIT_MASK(24)) | ||
| 367 | return 0; | ||
| 368 | |||
| 369 | return 1; | ||
| 370 | } | 364 | } |
| 371 | 365 | ||
| 372 | EXPORT_SYMBOL(dma_supported); | 366 | EXPORT_SYMBOL(dma_supported); |
| @@ -383,6 +377,7 @@ void dma_cache_sync(struct device *dev, void *vaddr, size_t size, | |||
| 383 | { | 377 | { |
| 384 | BUG_ON(direction == DMA_NONE); | 378 | BUG_ON(direction == DMA_NONE); |
| 385 | 379 | ||
| 380 | plat_extra_sync_for_device(dev); | ||
| 386 | if (!plat_device_is_coherent(dev)) | 381 | if (!plat_device_is_coherent(dev)) |
| 387 | __dma_sync((unsigned long)vaddr, size, direction); | 382 | __dma_sync((unsigned long)vaddr, size, direction); |
| 388 | } | 383 | } |
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index 5ce2fa745626..9619f66e531e 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c | |||
| @@ -478,7 +478,10 @@ void __cpuinit tlb_init(void) | |||
| 478 | probe_tlb(config); | 478 | probe_tlb(config); |
| 479 | write_c0_pagemask(PM_DEFAULT_MASK); | 479 | write_c0_pagemask(PM_DEFAULT_MASK); |
| 480 | write_c0_wired(0); | 480 | write_c0_wired(0); |
| 481 | write_c0_framemask(0); | 481 | if (current_cpu_type() == CPU_R10000 || |
| 482 | current_cpu_type() == CPU_R12000 || | ||
| 483 | current_cpu_type() == CPU_R14000) | ||
| 484 | write_c0_framemask(0); | ||
| 482 | temp_tlb_entry = current_cpu_data.tlbsize - 1; | 485 | temp_tlb_entry = current_cpu_data.tlbsize - 1; |
| 483 | 486 | ||
| 484 | /* From this point on the ARC firmware is dead. */ | 487 | /* From this point on the ARC firmware is dead. */ |
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 979cf9197282..42942038d0fd 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c | |||
| @@ -317,6 +317,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, | |||
| 317 | case CPU_BCM3302: | 317 | case CPU_BCM3302: |
| 318 | case CPU_BCM4710: | 318 | case CPU_BCM4710: |
| 319 | case CPU_LOONGSON2: | 319 | case CPU_LOONGSON2: |
| 320 | case CPU_CAVIUM_OCTEON: | ||
| 320 | if (m4kc_tlbp_war()) | 321 | if (m4kc_tlbp_war()) |
| 321 | uasm_i_nop(p); | 322 | uasm_i_nop(p); |
| 322 | tlbw(p); | 323 | tlbw(p); |
diff --git a/arch/powerpc/boot/dts/gef_sbc610.dts b/arch/powerpc/boot/dts/gef_sbc610.dts index 9708b3423bbd..e78c355c7bac 100644 --- a/arch/powerpc/boot/dts/gef_sbc610.dts +++ b/arch/powerpc/boot/dts/gef_sbc610.dts | |||
| @@ -88,6 +88,21 @@ | |||
| 88 | compatible = "gef,fpga-regs"; | 88 | compatible = "gef,fpga-regs"; |
| 89 | reg = <0x4 0x0 0x40>; | 89 | reg = <0x4 0x0 0x40>; |
| 90 | }; | 90 | }; |
| 91 | |||
| 92 | wdt@4,2000 { | ||
| 93 | compatible = "gef,fpga-wdt"; | ||
| 94 | reg = <0x4 0x2000 0x8>; | ||
| 95 | interrupts = <0x1a 0x4>; | ||
| 96 | interrupt-parent = <&gef_pic>; | ||
| 97 | }; | ||
| 98 | /* Second watchdog available, driver currently supports one. | ||
| 99 | wdt@4,2010 { | ||
| 100 | compatible = "gef,fpga-wdt"; | ||
| 101 | reg = <0x4 0x2010 0x8>; | ||
| 102 | interrupts = <0x1b 0x4>; | ||
| 103 | interrupt-parent = <&gef_pic>; | ||
| 104 | }; | ||
| 105 | */ | ||
| 91 | gef_pic: pic@4,4000 { | 106 | gef_pic: pic@4,4000 { |
| 92 | #interrupt-cells = <1>; | 107 | #interrupt-cells = <1>; |
| 93 | interrupt-controller; | 108 | interrupt-controller; |
diff --git a/arch/powerpc/configs/86xx/gef_sbc610_defconfig b/arch/powerpc/configs/86xx/gef_sbc610_defconfig index cd1ffa449327..391874c7b436 100644 --- a/arch/powerpc/configs/86xx/gef_sbc610_defconfig +++ b/arch/powerpc/configs/86xx/gef_sbc610_defconfig | |||
| @@ -1164,6 +1164,7 @@ CONFIG_WATCHDOG=y | |||
| 1164 | # CONFIG_SOFT_WATCHDOG is not set | 1164 | # CONFIG_SOFT_WATCHDOG is not set |
| 1165 | # CONFIG_ALIM7101_WDT is not set | 1165 | # CONFIG_ALIM7101_WDT is not set |
| 1166 | # CONFIG_8xxx_WDT is not set | 1166 | # CONFIG_8xxx_WDT is not set |
| 1167 | CONFIG_GEF_WDT=y | ||
| 1167 | 1168 | ||
| 1168 | # | 1169 | # |
| 1169 | # PCI-based Watchdog Cards | 1170 | # PCI-based Watchdog Cards |
diff --git a/arch/powerpc/platforms/cell/cbe_cpufreq.c b/arch/powerpc/platforms/cell/cbe_cpufreq.c index ec7c8f45a215..e6506cd0ff94 100644 --- a/arch/powerpc/platforms/cell/cbe_cpufreq.c +++ b/arch/powerpc/platforms/cell/cbe_cpufreq.c | |||
| @@ -118,7 +118,7 @@ static int cbe_cpufreq_cpu_init(struct cpufreq_policy *policy) | |||
| 118 | policy->cur = cbe_freqs[cur_pmode].frequency; | 118 | policy->cur = cbe_freqs[cur_pmode].frequency; |
| 119 | 119 | ||
| 120 | #ifdef CONFIG_SMP | 120 | #ifdef CONFIG_SMP |
| 121 | policy->cpus = per_cpu(cpu_sibling_map, policy->cpu); | 121 | cpumask_copy(policy->cpus, &per_cpu(cpu_sibling_map, policy->cpu)); |
| 122 | #endif | 122 | #endif |
| 123 | 123 | ||
| 124 | cpufreq_frequency_table_get_attr(cbe_freqs, policy->cpu); | 124 | cpufreq_frequency_table_get_attr(cbe_freqs, policy->cpu); |
diff --git a/arch/powerpc/platforms/cell/cpufreq_spudemand.c b/arch/powerpc/platforms/cell/cpufreq_spudemand.c index a3c6c01bd6db..968c1c0b4d5b 100644 --- a/arch/powerpc/platforms/cell/cpufreq_spudemand.c +++ b/arch/powerpc/platforms/cell/cpufreq_spudemand.c | |||
| @@ -110,7 +110,7 @@ static int spu_gov_govern(struct cpufreq_policy *policy, unsigned int event) | |||
| 110 | } | 110 | } |
| 111 | 111 | ||
| 112 | /* initialize spu_gov_info for all affected cpus */ | 112 | /* initialize spu_gov_info for all affected cpus */ |
| 113 | for_each_cpu_mask(i, policy->cpus) { | 113 | for_each_cpu(i, policy->cpus) { |
| 114 | affected_info = &per_cpu(spu_gov_info, i); | 114 | affected_info = &per_cpu(spu_gov_info, i); |
| 115 | affected_info->policy = policy; | 115 | affected_info->policy = policy; |
| 116 | } | 116 | } |
| @@ -127,7 +127,7 @@ static int spu_gov_govern(struct cpufreq_policy *policy, unsigned int event) | |||
| 127 | spu_gov_cancel_work(info); | 127 | spu_gov_cancel_work(info); |
| 128 | 128 | ||
| 129 | /* clean spu_gov_info for all affected cpus */ | 129 | /* clean spu_gov_info for all affected cpus */ |
| 130 | for_each_cpu_mask (i, policy->cpus) { | 130 | for_each_cpu (i, policy->cpus) { |
| 131 | info = &per_cpu(spu_gov_info, i); | 131 | info = &per_cpu(spu_gov_info, i); |
| 132 | info->policy = NULL; | 132 | info->policy = NULL; |
| 133 | } | 133 | } |
diff --git a/arch/powerpc/platforms/pasemi/cpufreq.c b/arch/powerpc/platforms/pasemi/cpufreq.c index 86db47c1b665..be2527a516ea 100644 --- a/arch/powerpc/platforms/pasemi/cpufreq.c +++ b/arch/powerpc/platforms/pasemi/cpufreq.c | |||
| @@ -213,7 +213,7 @@ static int pas_cpufreq_cpu_init(struct cpufreq_policy *policy) | |||
| 213 | pr_debug("current astate is at %d\n",cur_astate); | 213 | pr_debug("current astate is at %d\n",cur_astate); |
| 214 | 214 | ||
| 215 | policy->cur = pas_freqs[cur_astate].frequency; | 215 | policy->cur = pas_freqs[cur_astate].frequency; |
| 216 | policy->cpus = cpu_online_map; | 216 | cpumask_copy(policy->cpus, &cpu_online_map); |
| 217 | 217 | ||
| 218 | ppc_proc_freq = policy->cur * 1000ul; | 218 | ppc_proc_freq = policy->cur * 1000ul; |
| 219 | 219 | ||
diff --git a/arch/powerpc/platforms/powermac/cpufreq_64.c b/arch/powerpc/platforms/powermac/cpufreq_64.c index 4dfb4bc242b5..beb38333b6d2 100644 --- a/arch/powerpc/platforms/powermac/cpufreq_64.c +++ b/arch/powerpc/platforms/powermac/cpufreq_64.c | |||
| @@ -362,7 +362,7 @@ static int g5_cpufreq_cpu_init(struct cpufreq_policy *policy) | |||
| 362 | /* secondary CPUs are tied to the primary one by the | 362 | /* secondary CPUs are tied to the primary one by the |
| 363 | * cpufreq core if in the secondary policy we tell it that | 363 | * cpufreq core if in the secondary policy we tell it that |
| 364 | * it actually must be one policy together with all others. */ | 364 | * it actually must be one policy together with all others. */ |
| 365 | policy->cpus = cpu_online_map; | 365 | cpumask_copy(policy->cpus, &cpu_online_map); |
| 366 | cpufreq_frequency_table_get_attr(g5_cpu_freqs, policy->cpu); | 366 | cpufreq_frequency_table_get_attr(g5_cpu_freqs, policy->cpu); |
| 367 | 367 | ||
| 368 | return cpufreq_frequency_table_cpuinfo(policy, | 368 | return cpufreq_frequency_table_cpuinfo(policy, |
diff --git a/arch/sparc/configs/sparc32_defconfig b/arch/sparc/configs/sparc32_defconfig index 2e3a149ea0e7..09ab46e4c59d 100644 --- a/arch/sparc/configs/sparc32_defconfig +++ b/arch/sparc/configs/sparc32_defconfig | |||
| @@ -1,15 +1,21 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.25 | 3 | # Linux kernel version: 2.6.28 |
| 4 | # Tue Apr 29 01:28:58 2008 | 4 | # Thu Jan 8 16:45:44 2009 |
| 5 | # | 5 | # |
| 6 | # CONFIG_64BIT is not set | ||
| 7 | CONFIG_SPARC=y | ||
| 8 | CONFIG_SPARC32=y | ||
| 9 | # CONFIG_SPARC64 is not set | ||
| 10 | CONFIG_ARCH_DEFCONFIG="arch/sparc/configs/sparc32_defconfig" | ||
| 11 | CONFIG_BITS=32 | ||
| 12 | CONFIG_AUDIT_ARCH=y | ||
| 6 | CONFIG_MMU=y | 13 | CONFIG_MMU=y |
| 7 | CONFIG_HIGHMEM=y | 14 | CONFIG_HIGHMEM=y |
| 8 | CONFIG_ZONE_DMA=y | 15 | CONFIG_ZONE_DMA=y |
| 9 | CONFIG_GENERIC_ISA_DMA=y | 16 | CONFIG_GENERIC_ISA_DMA=y |
| 10 | CONFIG_ARCH_NO_VIRT_TO_BUS=y | 17 | CONFIG_ARCH_NO_VIRT_TO_BUS=y |
| 11 | CONFIG_OF=y | 18 | CONFIG_OF=y |
| 12 | CONFIG_HZ=100 | ||
| 13 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | 19 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" |
| 14 | 20 | ||
| 15 | # | 21 | # |
| @@ -66,31 +72,30 @@ CONFIG_SIGNALFD=y | |||
| 66 | CONFIG_TIMERFD=y | 72 | CONFIG_TIMERFD=y |
| 67 | CONFIG_EVENTFD=y | 73 | CONFIG_EVENTFD=y |
| 68 | CONFIG_SHMEM=y | 74 | CONFIG_SHMEM=y |
| 75 | CONFIG_AIO=y | ||
| 69 | CONFIG_VM_EVENT_COUNTERS=y | 76 | CONFIG_VM_EVENT_COUNTERS=y |
| 77 | CONFIG_PCI_QUIRKS=y | ||
| 70 | CONFIG_SLAB=y | 78 | CONFIG_SLAB=y |
| 71 | # CONFIG_SLUB is not set | 79 | # CONFIG_SLUB is not set |
| 72 | # CONFIG_SLOB is not set | 80 | # CONFIG_SLOB is not set |
| 73 | # CONFIG_PROFILING is not set | 81 | # CONFIG_PROFILING is not set |
| 74 | # CONFIG_MARKERS is not set | ||
| 75 | CONFIG_HAVE_OPROFILE=y | 82 | CONFIG_HAVE_OPROFILE=y |
| 76 | # CONFIG_HAVE_KPROBES is not set | 83 | CONFIG_HAVE_ARCH_TRACEHOOK=y |
| 77 | # CONFIG_HAVE_KRETPROBES is not set | 84 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set |
| 78 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 79 | CONFIG_SLABINFO=y | 85 | CONFIG_SLABINFO=y |
| 80 | CONFIG_RT_MUTEXES=y | 86 | CONFIG_RT_MUTEXES=y |
| 81 | # CONFIG_TINY_SHMEM is not set | ||
| 82 | CONFIG_BASE_SMALL=0 | 87 | CONFIG_BASE_SMALL=0 |
| 83 | CONFIG_MODULES=y | 88 | CONFIG_MODULES=y |
| 89 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 84 | CONFIG_MODULE_UNLOAD=y | 90 | CONFIG_MODULE_UNLOAD=y |
| 85 | # CONFIG_MODULE_FORCE_UNLOAD is not set | 91 | # CONFIG_MODULE_FORCE_UNLOAD is not set |
| 86 | # CONFIG_MODVERSIONS is not set | 92 | # CONFIG_MODVERSIONS is not set |
| 87 | # CONFIG_MODULE_SRCVERSION_ALL is not set | 93 | # CONFIG_MODULE_SRCVERSION_ALL is not set |
| 88 | CONFIG_KMOD=y | ||
| 89 | CONFIG_BLOCK=y | 94 | CONFIG_BLOCK=y |
| 90 | # CONFIG_LBD is not set | 95 | # CONFIG_LBD is not set |
| 91 | # CONFIG_BLK_DEV_IO_TRACE is not set | 96 | # CONFIG_BLK_DEV_IO_TRACE is not set |
| 92 | # CONFIG_LSF is not set | ||
| 93 | # CONFIG_BLK_DEV_BSG is not set | 97 | # CONFIG_BLK_DEV_BSG is not set |
| 98 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 94 | 99 | ||
| 95 | # | 100 | # |
| 96 | # IO Schedulers | 101 | # IO Schedulers |
| @@ -105,59 +110,73 @@ CONFIG_DEFAULT_CFQ=y | |||
| 105 | # CONFIG_DEFAULT_NOOP is not set | 110 | # CONFIG_DEFAULT_NOOP is not set |
| 106 | CONFIG_DEFAULT_IOSCHED="cfq" | 111 | CONFIG_DEFAULT_IOSCHED="cfq" |
| 107 | CONFIG_CLASSIC_RCU=y | 112 | CONFIG_CLASSIC_RCU=y |
| 113 | # CONFIG_TREE_RCU is not set | ||
| 114 | # CONFIG_PREEMPT_RCU is not set | ||
| 115 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 116 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 117 | # CONFIG_FREEZER is not set | ||
| 108 | 118 | ||
| 109 | # | 119 | # |
| 110 | # General machine setup | 120 | # Processor type and features |
| 111 | # | 121 | # |
| 112 | # CONFIG_SMP is not set | 122 | # CONFIG_SMP is not set |
| 113 | CONFIG_SPARC=y | 123 | # CONFIG_HZ_100 is not set |
| 114 | CONFIG_SPARC32=y | 124 | CONFIG_HZ_250=y |
| 115 | CONFIG_SBUS=y | 125 | # CONFIG_HZ_300 is not set |
| 116 | CONFIG_SBUSCHAR=y | 126 | # CONFIG_HZ_1000 is not set |
| 117 | CONFIG_SERIAL_CONSOLE=y | 127 | CONFIG_HZ=250 |
| 118 | CONFIG_SUN_AUXIO=y | 128 | # CONFIG_SCHED_HRTICK is not set |
| 119 | CONFIG_SUN_IO=y | ||
| 120 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | 129 | CONFIG_RWSEM_GENERIC_SPINLOCK=y |
| 121 | CONFIG_GENERIC_FIND_NEXT_BIT=y | 130 | CONFIG_GENERIC_FIND_NEXT_BIT=y |
| 122 | CONFIG_GENERIC_HWEIGHT=y | 131 | CONFIG_GENERIC_HWEIGHT=y |
| 123 | CONFIG_GENERIC_CALIBRATE_DELAY=y | 132 | CONFIG_GENERIC_CALIBRATE_DELAY=y |
| 124 | CONFIG_ARCH_MAY_HAVE_PC_FDC=y | 133 | CONFIG_ARCH_MAY_HAVE_PC_FDC=y |
| 125 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | ||
| 126 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
| 127 | CONFIG_EMULATED_CMPXCHG=y | 134 | CONFIG_EMULATED_CMPXCHG=y |
| 128 | CONFIG_SUN_PM=y | ||
| 129 | # CONFIG_SUN4 is not set | ||
| 130 | CONFIG_PCI=y | ||
| 131 | CONFIG_PCI_SYSCALL=y | ||
| 132 | # CONFIG_ARCH_SUPPORTS_MSI is not set | ||
| 133 | CONFIG_PCI_LEGACY=y | ||
| 134 | # CONFIG_PCI_DEBUG is not set | ||
| 135 | # CONFIG_NO_DMA is not set | ||
| 136 | CONFIG_SUN_OPENPROMFS=m | ||
| 137 | # CONFIG_SPARC_LED is not set | ||
| 138 | CONFIG_BINFMT_ELF=y | ||
| 139 | CONFIG_BINFMT_MISC=m | ||
| 140 | CONFIG_SELECT_MEMORY_MODEL=y | 135 | CONFIG_SELECT_MEMORY_MODEL=y |
| 141 | CONFIG_FLATMEM_MANUAL=y | 136 | CONFIG_FLATMEM_MANUAL=y |
| 142 | # CONFIG_DISCONTIGMEM_MANUAL is not set | 137 | # CONFIG_DISCONTIGMEM_MANUAL is not set |
| 143 | # CONFIG_SPARSEMEM_MANUAL is not set | 138 | # CONFIG_SPARSEMEM_MANUAL is not set |
| 144 | CONFIG_FLATMEM=y | 139 | CONFIG_FLATMEM=y |
| 145 | CONFIG_FLAT_NODE_MEM_MAP=y | 140 | CONFIG_FLAT_NODE_MEM_MAP=y |
| 146 | # CONFIG_SPARSEMEM_STATIC is not set | 141 | CONFIG_PAGEFLAGS_EXTENDED=y |
| 147 | # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set | ||
| 148 | CONFIG_SPLIT_PTLOCK_CPUS=4 | 142 | CONFIG_SPLIT_PTLOCK_CPUS=4 |
| 149 | # CONFIG_RESOURCES_64BIT is not set | 143 | # CONFIG_PHYS_ADDR_T_64BIT is not set |
| 150 | CONFIG_ZONE_DMA_FLAG=1 | 144 | CONFIG_ZONE_DMA_FLAG=1 |
| 151 | CONFIG_BOUNCE=y | 145 | CONFIG_BOUNCE=y |
| 146 | CONFIG_UNEVICTABLE_LRU=y | ||
| 147 | CONFIG_SUN_PM=y | ||
| 148 | # CONFIG_SPARC_LED is not set | ||
| 149 | CONFIG_SERIAL_CONSOLE=y | ||
| 152 | 150 | ||
| 153 | # | 151 | # |
| 154 | # Networking | 152 | # Bus options (PCI etc.) |
| 155 | # | 153 | # |
| 154 | CONFIG_SBUS=y | ||
| 155 | CONFIG_SBUSCHAR=y | ||
| 156 | CONFIG_PCI=y | ||
| 157 | CONFIG_PCI_SYSCALL=y | ||
| 158 | # CONFIG_ARCH_SUPPORTS_MSI is not set | ||
| 159 | CONFIG_PCI_LEGACY=y | ||
| 160 | # CONFIG_PCI_DEBUG is not set | ||
| 161 | # CONFIG_PCI_STUB is not set | ||
| 162 | # CONFIG_PCCARD is not set | ||
| 163 | CONFIG_SUN_OPENPROMFS=m | ||
| 164 | CONFIG_SPARC32_PCI=y | ||
| 165 | |||
| 166 | # | ||
| 167 | # Executable file formats | ||
| 168 | # | ||
| 169 | CONFIG_BINFMT_ELF=y | ||
| 170 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
| 171 | # CONFIG_HAVE_AOUT is not set | ||
| 172 | CONFIG_BINFMT_MISC=m | ||
| 156 | CONFIG_NET=y | 173 | CONFIG_NET=y |
| 157 | 174 | ||
| 158 | # | 175 | # |
| 159 | # Networking options | 176 | # Networking options |
| 160 | # | 177 | # |
| 178 | # CONFIG_NET_NS is not set | ||
| 179 | CONFIG_COMPAT_NET_DEV_OPS=y | ||
| 161 | CONFIG_PACKET=y | 180 | CONFIG_PACKET=y |
| 162 | # CONFIG_PACKET_MMAP is not set | 181 | # CONFIG_PACKET_MMAP is not set |
| 163 | CONFIG_UNIX=y | 182 | CONFIG_UNIX=y |
| @@ -166,6 +185,7 @@ CONFIG_XFRM_USER=m | |||
| 166 | # CONFIG_XFRM_SUB_POLICY is not set | 185 | # CONFIG_XFRM_SUB_POLICY is not set |
| 167 | # CONFIG_XFRM_MIGRATE is not set | 186 | # CONFIG_XFRM_MIGRATE is not set |
| 168 | # CONFIG_XFRM_STATISTICS is not set | 187 | # CONFIG_XFRM_STATISTICS is not set |
| 188 | CONFIG_XFRM_IPCOMP=y | ||
| 169 | CONFIG_NET_KEY=m | 189 | CONFIG_NET_KEY=m |
| 170 | # CONFIG_NET_KEY_MIGRATE is not set | 190 | # CONFIG_NET_KEY_MIGRATE is not set |
| 171 | CONFIG_INET=y | 191 | CONFIG_INET=y |
| @@ -221,6 +241,7 @@ CONFIG_IPV6_TUNNEL=m | |||
| 221 | # CONFIG_TIPC is not set | 241 | # CONFIG_TIPC is not set |
| 222 | # CONFIG_ATM is not set | 242 | # CONFIG_ATM is not set |
| 223 | # CONFIG_BRIDGE is not set | 243 | # CONFIG_BRIDGE is not set |
| 244 | # CONFIG_NET_DSA is not set | ||
| 224 | # CONFIG_VLAN_8021Q is not set | 245 | # CONFIG_VLAN_8021Q is not set |
| 225 | # CONFIG_DECNET is not set | 246 | # CONFIG_DECNET is not set |
| 226 | # CONFIG_LLC2 is not set | 247 | # CONFIG_LLC2 is not set |
| @@ -231,6 +252,7 @@ CONFIG_IPV6_TUNNEL=m | |||
| 231 | # CONFIG_ECONET is not set | 252 | # CONFIG_ECONET is not set |
| 232 | # CONFIG_WAN_ROUTER is not set | 253 | # CONFIG_WAN_ROUTER is not set |
| 233 | # CONFIG_NET_SCHED is not set | 254 | # CONFIG_NET_SCHED is not set |
| 255 | # CONFIG_DCB is not set | ||
| 234 | 256 | ||
| 235 | # | 257 | # |
| 236 | # Network testing | 258 | # Network testing |
| @@ -241,14 +263,14 @@ CONFIG_NET_PKTGEN=m | |||
| 241 | # CONFIG_IRDA is not set | 263 | # CONFIG_IRDA is not set |
| 242 | # CONFIG_BT is not set | 264 | # CONFIG_BT is not set |
| 243 | # CONFIG_AF_RXRPC is not set | 265 | # CONFIG_AF_RXRPC is not set |
| 244 | 266 | # CONFIG_PHONET is not set | |
| 245 | # | 267 | CONFIG_WIRELESS=y |
| 246 | # Wireless | ||
| 247 | # | ||
| 248 | # CONFIG_CFG80211 is not set | 268 | # CONFIG_CFG80211 is not set |
| 269 | CONFIG_WIRELESS_OLD_REGULATORY=y | ||
| 249 | # CONFIG_WIRELESS_EXT is not set | 270 | # CONFIG_WIRELESS_EXT is not set |
| 271 | # CONFIG_LIB80211 is not set | ||
| 250 | # CONFIG_MAC80211 is not set | 272 | # CONFIG_MAC80211 is not set |
| 251 | # CONFIG_IEEE80211 is not set | 273 | # CONFIG_WIMAX is not set |
| 252 | # CONFIG_RFKILL is not set | 274 | # CONFIG_RFKILL is not set |
| 253 | # CONFIG_NET_9P is not set | 275 | # CONFIG_NET_9P is not set |
| 254 | 276 | ||
| @@ -262,7 +284,9 @@ CONFIG_NET_PKTGEN=m | |||
| 262 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | 284 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" |
| 263 | CONFIG_STANDALONE=y | 285 | CONFIG_STANDALONE=y |
| 264 | CONFIG_PREVENT_FIRMWARE_BUILD=y | 286 | CONFIG_PREVENT_FIRMWARE_BUILD=y |
| 265 | # CONFIG_FW_LOADER is not set | 287 | CONFIG_FW_LOADER=y |
| 288 | CONFIG_FIRMWARE_IN_KERNEL=y | ||
| 289 | CONFIG_EXTRA_FIRMWARE="" | ||
| 266 | # CONFIG_DEBUG_DRIVER is not set | 290 | # CONFIG_DEBUG_DRIVER is not set |
| 267 | # CONFIG_DEBUG_DEVRES is not set | 291 | # CONFIG_DEBUG_DEVRES is not set |
| 268 | # CONFIG_SYS_HYPERVISOR is not set | 292 | # CONFIG_SYS_HYPERVISOR is not set |
| @@ -286,12 +310,15 @@ CONFIG_BLK_DEV_RAM_SIZE=4096 | |||
| 286 | # CONFIG_BLK_DEV_XIP is not set | 310 | # CONFIG_BLK_DEV_XIP is not set |
| 287 | # CONFIG_CDROM_PKTCDVD is not set | 311 | # CONFIG_CDROM_PKTCDVD is not set |
| 288 | # CONFIG_ATA_OVER_ETH is not set | 312 | # CONFIG_ATA_OVER_ETH is not set |
| 313 | # CONFIG_BLK_DEV_HD is not set | ||
| 289 | CONFIG_MISC_DEVICES=y | 314 | CONFIG_MISC_DEVICES=y |
| 290 | # CONFIG_PHANTOM is not set | 315 | # CONFIG_PHANTOM is not set |
| 291 | # CONFIG_EEPROM_93CX6 is not set | 316 | # CONFIG_EEPROM_93CX6 is not set |
| 292 | # CONFIG_SGI_IOC4 is not set | 317 | # CONFIG_SGI_IOC4 is not set |
| 293 | # CONFIG_TIFM_CORE is not set | 318 | # CONFIG_TIFM_CORE is not set |
| 294 | # CONFIG_ENCLOSURE_SERVICES is not set | 319 | # CONFIG_ENCLOSURE_SERVICES is not set |
| 320 | # CONFIG_HP_ILO is not set | ||
| 321 | # CONFIG_C2PORT is not set | ||
| 295 | CONFIG_HAVE_IDE=y | 322 | CONFIG_HAVE_IDE=y |
| 296 | # CONFIG_IDE is not set | 323 | # CONFIG_IDE is not set |
| 297 | 324 | ||
| @@ -335,6 +362,7 @@ CONFIG_SCSI_SPI_ATTRS=y | |||
| 335 | # CONFIG_SCSI_SRP_ATTRS is not set | 362 | # CONFIG_SCSI_SRP_ATTRS is not set |
| 336 | CONFIG_SCSI_LOWLEVEL=y | 363 | CONFIG_SCSI_LOWLEVEL=y |
| 337 | # CONFIG_ISCSI_TCP is not set | 364 | # CONFIG_ISCSI_TCP is not set |
| 365 | # CONFIG_SCSI_CXGB3_ISCSI is not set | ||
| 338 | # CONFIG_BLK_DEV_3W_XXXX_RAID is not set | 366 | # CONFIG_BLK_DEV_3W_XXXX_RAID is not set |
| 339 | # CONFIG_SCSI_3W_9XXX is not set | 367 | # CONFIG_SCSI_3W_9XXX is not set |
| 340 | # CONFIG_SCSI_ACARD is not set | 368 | # CONFIG_SCSI_ACARD is not set |
| @@ -348,6 +376,8 @@ CONFIG_SCSI_LOWLEVEL=y | |||
| 348 | # CONFIG_MEGARAID_LEGACY is not set | 376 | # CONFIG_MEGARAID_LEGACY is not set |
| 349 | # CONFIG_MEGARAID_SAS is not set | 377 | # CONFIG_MEGARAID_SAS is not set |
| 350 | # CONFIG_SCSI_HPTIOP is not set | 378 | # CONFIG_SCSI_HPTIOP is not set |
| 379 | # CONFIG_LIBFC is not set | ||
| 380 | # CONFIG_FCOE is not set | ||
| 351 | # CONFIG_SCSI_DMX3191D is not set | 381 | # CONFIG_SCSI_DMX3191D is not set |
| 352 | # CONFIG_SCSI_FUTURE_DOMAIN is not set | 382 | # CONFIG_SCSI_FUTURE_DOMAIN is not set |
| 353 | # CONFIG_SCSI_IPS is not set | 383 | # CONFIG_SCSI_IPS is not set |
| @@ -367,6 +397,7 @@ CONFIG_SCSI_QLOGICPTI=m | |||
| 367 | # CONFIG_SCSI_DEBUG is not set | 397 | # CONFIG_SCSI_DEBUG is not set |
| 368 | CONFIG_SCSI_SUNESP=y | 398 | CONFIG_SCSI_SUNESP=y |
| 369 | # CONFIG_SCSI_SRP is not set | 399 | # CONFIG_SCSI_SRP is not set |
| 400 | # CONFIG_SCSI_DH is not set | ||
| 370 | # CONFIG_ATA is not set | 401 | # CONFIG_ATA is not set |
| 371 | # CONFIG_MD is not set | 402 | # CONFIG_MD is not set |
| 372 | # CONFIG_FUSION is not set | 403 | # CONFIG_FUSION is not set |
| @@ -374,11 +405,14 @@ CONFIG_SCSI_SUNESP=y | |||
| 374 | # | 405 | # |
| 375 | # IEEE 1394 (FireWire) support | 406 | # IEEE 1394 (FireWire) support |
| 376 | # | 407 | # |
| 408 | |||
| 409 | # | ||
| 410 | # Enable only one of the two stacks, unless you know what you are doing | ||
| 411 | # | ||
| 377 | # CONFIG_FIREWIRE is not set | 412 | # CONFIG_FIREWIRE is not set |
| 378 | # CONFIG_IEEE1394 is not set | 413 | # CONFIG_IEEE1394 is not set |
| 379 | # CONFIG_I2O is not set | 414 | # CONFIG_I2O is not set |
| 380 | CONFIG_NETDEVICES=y | 415 | CONFIG_NETDEVICES=y |
| 381 | # CONFIG_NETDEVICES_MULTIQUEUE is not set | ||
| 382 | CONFIG_DUMMY=m | 416 | CONFIG_DUMMY=m |
| 383 | # CONFIG_BONDING is not set | 417 | # CONFIG_BONDING is not set |
| 384 | # CONFIG_MACVLAN is not set | 418 | # CONFIG_MACVLAN is not set |
| @@ -402,14 +436,16 @@ CONFIG_SUNQE=m | |||
| 402 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | 436 | # CONFIG_IBM_NEW_EMAC_RGMII is not set |
| 403 | # CONFIG_IBM_NEW_EMAC_TAH is not set | 437 | # CONFIG_IBM_NEW_EMAC_TAH is not set |
| 404 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | 438 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set |
| 439 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set | ||
| 440 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 441 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 405 | # CONFIG_NET_PCI is not set | 442 | # CONFIG_NET_PCI is not set |
| 406 | # CONFIG_B44 is not set | 443 | # CONFIG_B44 is not set |
| 444 | # CONFIG_ATL2 is not set | ||
| 407 | CONFIG_NETDEV_1000=y | 445 | CONFIG_NETDEV_1000=y |
| 408 | # CONFIG_ACENIC is not set | 446 | # CONFIG_ACENIC is not set |
| 409 | # CONFIG_DL2K is not set | 447 | # CONFIG_DL2K is not set |
| 410 | # CONFIG_E1000 is not set | 448 | # CONFIG_E1000 is not set |
| 411 | # CONFIG_E1000E is not set | ||
| 412 | # CONFIG_E1000E_ENABLED is not set | ||
| 413 | # CONFIG_IP1000 is not set | 449 | # CONFIG_IP1000 is not set |
| 414 | # CONFIG_IGB is not set | 450 | # CONFIG_IGB is not set |
| 415 | # CONFIG_MYRI_SBUS is not set | 451 | # CONFIG_MYRI_SBUS is not set |
| @@ -425,18 +461,25 @@ CONFIG_NETDEV_1000=y | |||
| 425 | # CONFIG_BNX2 is not set | 461 | # CONFIG_BNX2 is not set |
| 426 | # CONFIG_QLA3XXX is not set | 462 | # CONFIG_QLA3XXX is not set |
| 427 | # CONFIG_ATL1 is not set | 463 | # CONFIG_ATL1 is not set |
| 464 | # CONFIG_ATL1E is not set | ||
| 465 | # CONFIG_JME is not set | ||
| 428 | CONFIG_NETDEV_10000=y | 466 | CONFIG_NETDEV_10000=y |
| 429 | # CONFIG_CHELSIO_T1 is not set | 467 | # CONFIG_CHELSIO_T1 is not set |
| 468 | CONFIG_CHELSIO_T3_DEPENDS=y | ||
| 430 | # CONFIG_CHELSIO_T3 is not set | 469 | # CONFIG_CHELSIO_T3 is not set |
| 470 | # CONFIG_ENIC is not set | ||
| 431 | # CONFIG_IXGBE is not set | 471 | # CONFIG_IXGBE is not set |
| 432 | # CONFIG_IXGB is not set | 472 | # CONFIG_IXGB is not set |
| 433 | # CONFIG_S2IO is not set | 473 | # CONFIG_S2IO is not set |
| 434 | # CONFIG_MYRI10GE is not set | 474 | # CONFIG_MYRI10GE is not set |
| 435 | # CONFIG_NETXEN_NIC is not set | 475 | # CONFIG_NETXEN_NIC is not set |
| 436 | # CONFIG_NIU is not set | 476 | # CONFIG_NIU is not set |
| 477 | # CONFIG_MLX4_EN is not set | ||
| 437 | # CONFIG_MLX4_CORE is not set | 478 | # CONFIG_MLX4_CORE is not set |
| 438 | # CONFIG_TEHUTI is not set | 479 | # CONFIG_TEHUTI is not set |
| 439 | # CONFIG_BNX2X is not set | 480 | # CONFIG_BNX2X is not set |
| 481 | # CONFIG_QLGE is not set | ||
| 482 | # CONFIG_SFC is not set | ||
| 440 | # CONFIG_TR is not set | 483 | # CONFIG_TR is not set |
| 441 | 484 | ||
| 442 | # | 485 | # |
| @@ -445,6 +488,10 @@ CONFIG_NETDEV_10000=y | |||
| 445 | # CONFIG_WLAN_PRE80211 is not set | 488 | # CONFIG_WLAN_PRE80211 is not set |
| 446 | # CONFIG_WLAN_80211 is not set | 489 | # CONFIG_WLAN_80211 is not set |
| 447 | # CONFIG_IWLWIFI_LEDS is not set | 490 | # CONFIG_IWLWIFI_LEDS is not set |
| 491 | |||
| 492 | # | ||
| 493 | # Enable WiMAX (Networking options) to see the WiMAX drivers | ||
| 494 | # | ||
| 448 | # CONFIG_WAN is not set | 495 | # CONFIG_WAN is not set |
| 449 | # CONFIG_FDDI is not set | 496 | # CONFIG_FDDI is not set |
| 450 | # CONFIG_HIPPI is not set | 497 | # CONFIG_HIPPI is not set |
| @@ -492,9 +539,11 @@ CONFIG_MOUSE_PS2_LOGIPS2PP=y | |||
| 492 | CONFIG_MOUSE_PS2_SYNAPTICS=y | 539 | CONFIG_MOUSE_PS2_SYNAPTICS=y |
| 493 | CONFIG_MOUSE_PS2_LIFEBOOK=y | 540 | CONFIG_MOUSE_PS2_LIFEBOOK=y |
| 494 | CONFIG_MOUSE_PS2_TRACKPOINT=y | 541 | CONFIG_MOUSE_PS2_TRACKPOINT=y |
| 542 | # CONFIG_MOUSE_PS2_ELANTECH is not set | ||
| 495 | # CONFIG_MOUSE_PS2_TOUCHKIT is not set | 543 | # CONFIG_MOUSE_PS2_TOUCHKIT is not set |
| 496 | CONFIG_MOUSE_SERIAL=m | 544 | CONFIG_MOUSE_SERIAL=m |
| 497 | # CONFIG_MOUSE_APPLETOUCH is not set | 545 | # CONFIG_MOUSE_APPLETOUCH is not set |
| 546 | # CONFIG_MOUSE_BCM5974 is not set | ||
| 498 | # CONFIG_MOUSE_VSXXXAA is not set | 547 | # CONFIG_MOUSE_VSXXXAA is not set |
| 499 | # CONFIG_INPUT_JOYSTICK is not set | 548 | # CONFIG_INPUT_JOYSTICK is not set |
| 500 | # CONFIG_INPUT_TABLET is not set | 549 | # CONFIG_INPUT_TABLET is not set |
| @@ -516,15 +565,18 @@ CONFIG_SERIO_LIBPS2=m | |||
| 516 | # Character devices | 565 | # Character devices |
| 517 | # | 566 | # |
| 518 | CONFIG_VT=y | 567 | CONFIG_VT=y |
| 568 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
| 519 | CONFIG_VT_CONSOLE=y | 569 | CONFIG_VT_CONSOLE=y |
| 520 | CONFIG_HW_CONSOLE=y | 570 | CONFIG_HW_CONSOLE=y |
| 521 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | 571 | # CONFIG_VT_HW_CONSOLE_BINDING is not set |
| 572 | CONFIG_DEVKMEM=y | ||
| 522 | # CONFIG_SERIAL_NONSTANDARD is not set | 573 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 523 | # CONFIG_NOZOMI is not set | 574 | # CONFIG_NOZOMI is not set |
| 524 | 575 | ||
| 525 | # | 576 | # |
| 526 | # Serial drivers | 577 | # Serial drivers |
| 527 | # | 578 | # |
| 579 | # CONFIG_SERIAL_8250 is not set | ||
| 528 | 580 | ||
| 529 | # | 581 | # |
| 530 | # Non-8250 serial port support | 582 | # Non-8250 serial port support |
| @@ -540,23 +592,20 @@ CONFIG_SERIAL_CORE_CONSOLE=y | |||
| 540 | CONFIG_CONSOLE_POLL=y | 592 | CONFIG_CONSOLE_POLL=y |
| 541 | # CONFIG_SERIAL_JSM is not set | 593 | # CONFIG_SERIAL_JSM is not set |
| 542 | CONFIG_UNIX98_PTYS=y | 594 | CONFIG_UNIX98_PTYS=y |
| 595 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | ||
| 543 | CONFIG_LEGACY_PTYS=y | 596 | CONFIG_LEGACY_PTYS=y |
| 544 | CONFIG_LEGACY_PTY_COUNT=256 | 597 | CONFIG_LEGACY_PTY_COUNT=256 |
| 545 | # CONFIG_IPMI_HANDLER is not set | 598 | # CONFIG_IPMI_HANDLER is not set |
| 546 | CONFIG_HW_RANDOM=m | 599 | CONFIG_HW_RANDOM=m |
| 547 | CONFIG_JS_RTC=m | ||
| 548 | # CONFIG_R3964 is not set | 600 | # CONFIG_R3964 is not set |
| 549 | # CONFIG_APPLICOM is not set | 601 | # CONFIG_APPLICOM is not set |
| 550 | # CONFIG_RAW_DRIVER is not set | 602 | # CONFIG_RAW_DRIVER is not set |
| 551 | # CONFIG_TCG_TPM is not set | 603 | # CONFIG_TCG_TPM is not set |
| 552 | CONFIG_DEVPORT=y | 604 | CONFIG_DEVPORT=y |
| 553 | # CONFIG_I2C is not set | 605 | # CONFIG_I2C is not set |
| 554 | |||
| 555 | # | ||
| 556 | # SPI support | ||
| 557 | # | ||
| 558 | # CONFIG_SPI is not set | 606 | # CONFIG_SPI is not set |
| 559 | # CONFIG_SPI_MASTER is not set | 607 | CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y |
| 608 | # CONFIG_GPIOLIB is not set | ||
| 560 | # CONFIG_W1 is not set | 609 | # CONFIG_W1 is not set |
| 561 | # CONFIG_POWER_SUPPLY is not set | 610 | # CONFIG_POWER_SUPPLY is not set |
| 562 | CONFIG_HWMON=y | 611 | CONFIG_HWMON=y |
| @@ -577,25 +626,38 @@ CONFIG_HWMON=y | |||
| 577 | # CONFIG_SENSORS_W83627EHF is not set | 626 | # CONFIG_SENSORS_W83627EHF is not set |
| 578 | # CONFIG_HWMON_DEBUG_CHIP is not set | 627 | # CONFIG_HWMON_DEBUG_CHIP is not set |
| 579 | # CONFIG_THERMAL is not set | 628 | # CONFIG_THERMAL is not set |
| 629 | # CONFIG_THERMAL_HWMON is not set | ||
| 580 | # CONFIG_WATCHDOG is not set | 630 | # CONFIG_WATCHDOG is not set |
| 631 | CONFIG_SSB_POSSIBLE=y | ||
| 581 | 632 | ||
| 582 | # | 633 | # |
| 583 | # Sonics Silicon Backplane | 634 | # Sonics Silicon Backplane |
| 584 | # | 635 | # |
| 585 | CONFIG_SSB_POSSIBLE=y | ||
| 586 | # CONFIG_SSB is not set | 636 | # CONFIG_SSB is not set |
| 587 | 637 | ||
| 588 | # | 638 | # |
| 589 | # Multifunction device drivers | 639 | # Multifunction device drivers |
| 590 | # | 640 | # |
| 641 | # CONFIG_MFD_CORE is not set | ||
| 591 | # CONFIG_MFD_SM501 is not set | 642 | # CONFIG_MFD_SM501 is not set |
| 592 | # CONFIG_HTC_PASIC3 is not set | 643 | # CONFIG_HTC_PASIC3 is not set |
| 644 | # CONFIG_MFD_TMIO is not set | ||
| 645 | # CONFIG_REGULATOR is not set | ||
| 593 | 646 | ||
| 594 | # | 647 | # |
| 595 | # Multimedia devices | 648 | # Multimedia devices |
| 596 | # | 649 | # |
| 650 | |||
| 651 | # | ||
| 652 | # Multimedia core support | ||
| 653 | # | ||
| 597 | # CONFIG_VIDEO_DEV is not set | 654 | # CONFIG_VIDEO_DEV is not set |
| 598 | # CONFIG_DVB_CORE is not set | 655 | # CONFIG_DVB_CORE is not set |
| 656 | # CONFIG_VIDEO_MEDIA is not set | ||
| 657 | |||
| 658 | # | ||
| 659 | # Multimedia drivers | ||
| 660 | # | ||
| 599 | # CONFIG_DAB is not set | 661 | # CONFIG_DAB is not set |
| 600 | 662 | ||
| 601 | # | 663 | # |
| @@ -616,15 +678,17 @@ CONFIG_SSB_POSSIBLE=y | |||
| 616 | # | 678 | # |
| 617 | # CONFIG_PROM_CONSOLE is not set | 679 | # CONFIG_PROM_CONSOLE is not set |
| 618 | CONFIG_DUMMY_CONSOLE=y | 680 | CONFIG_DUMMY_CONSOLE=y |
| 619 | |||
| 620 | # | ||
| 621 | # Sound | ||
| 622 | # | ||
| 623 | # CONFIG_SOUND is not set | 681 | # CONFIG_SOUND is not set |
| 624 | CONFIG_HID_SUPPORT=y | 682 | CONFIG_HID_SUPPORT=y |
| 625 | CONFIG_HID=y | 683 | CONFIG_HID=y |
| 626 | # CONFIG_HID_DEBUG is not set | 684 | # CONFIG_HID_DEBUG is not set |
| 627 | # CONFIG_HIDRAW is not set | 685 | # CONFIG_HIDRAW is not set |
| 686 | # CONFIG_HID_PID is not set | ||
| 687 | |||
| 688 | # | ||
| 689 | # Special HID drivers | ||
| 690 | # | ||
| 691 | CONFIG_HID_COMPAT=y | ||
| 628 | CONFIG_USB_SUPPORT=y | 692 | CONFIG_USB_SUPPORT=y |
| 629 | CONFIG_USB_ARCH_HAS_HCD=y | 693 | CONFIG_USB_ARCH_HAS_HCD=y |
| 630 | CONFIG_USB_ARCH_HAS_OHCI=y | 694 | CONFIG_USB_ARCH_HAS_OHCI=y |
| @@ -632,32 +696,71 @@ CONFIG_USB_ARCH_HAS_EHCI=y | |||
| 632 | # CONFIG_USB is not set | 696 | # CONFIG_USB is not set |
| 633 | 697 | ||
| 634 | # | 698 | # |
| 635 | # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' | 699 | # Enable Host or Gadget support to see Inventra options |
| 700 | # | ||
| 701 | |||
| 702 | # | ||
| 703 | # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; | ||
| 636 | # | 704 | # |
| 637 | # CONFIG_USB_GADGET is not set | 705 | # CONFIG_USB_GADGET is not set |
| 706 | |||
| 707 | # | ||
| 708 | # OTG and related infrastructure | ||
| 709 | # | ||
| 710 | # CONFIG_UWB is not set | ||
| 638 | # CONFIG_MMC is not set | 711 | # CONFIG_MMC is not set |
| 639 | # CONFIG_MEMSTICK is not set | 712 | # CONFIG_MEMSTICK is not set |
| 640 | # CONFIG_NEW_LEDS is not set | 713 | # CONFIG_NEW_LEDS is not set |
| 714 | # CONFIG_ACCESSIBILITY is not set | ||
| 641 | # CONFIG_INFINIBAND is not set | 715 | # CONFIG_INFINIBAND is not set |
| 642 | # CONFIG_RTC_CLASS is not set | 716 | CONFIG_RTC_LIB=y |
| 717 | CONFIG_RTC_CLASS=y | ||
| 718 | CONFIG_RTC_HCTOSYS=y | ||
| 719 | CONFIG_RTC_HCTOSYS_DEVICE="rtc0" | ||
| 720 | # CONFIG_RTC_DEBUG is not set | ||
| 721 | |||
| 722 | # | ||
| 723 | # RTC interfaces | ||
| 724 | # | ||
| 725 | CONFIG_RTC_INTF_SYSFS=y | ||
| 726 | CONFIG_RTC_INTF_PROC=y | ||
| 727 | CONFIG_RTC_INTF_DEV=y | ||
| 728 | # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set | ||
| 729 | # CONFIG_RTC_DRV_TEST is not set | ||
| 730 | |||
| 731 | # | ||
| 732 | # SPI RTC drivers | ||
| 733 | # | ||
| 734 | |||
| 735 | # | ||
| 736 | # Platform RTC drivers | ||
| 737 | # | ||
| 738 | # CONFIG_RTC_DRV_DS1286 is not set | ||
| 739 | # CONFIG_RTC_DRV_DS1511 is not set | ||
| 740 | # CONFIG_RTC_DRV_DS1553 is not set | ||
| 741 | # CONFIG_RTC_DRV_DS1742 is not set | ||
| 742 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 743 | # CONFIG_RTC_DRV_M48T86 is not set | ||
| 744 | # CONFIG_RTC_DRV_M48T35 is not set | ||
| 745 | CONFIG_RTC_DRV_M48T59=y | ||
| 746 | # CONFIG_RTC_DRV_BQ4802 is not set | ||
| 747 | # CONFIG_RTC_DRV_V3020 is not set | ||
| 748 | |||
| 749 | # | ||
| 750 | # on-CPU RTC drivers | ||
| 751 | # | ||
| 752 | # CONFIG_DMADEVICES is not set | ||
| 643 | # CONFIG_UIO is not set | 753 | # CONFIG_UIO is not set |
| 754 | # CONFIG_STAGING is not set | ||
| 644 | 755 | ||
| 645 | # | 756 | # |
| 646 | # Misc Linux/SPARC drivers | 757 | # Misc Linux/SPARC drivers |
| 647 | # | 758 | # |
| 648 | CONFIG_SUN_OPENPROMIO=m | 759 | CONFIG_SUN_OPENPROMIO=m |
| 649 | CONFIG_SUN_MOSTEK_RTC=m | ||
| 650 | # CONFIG_SUN_BPP is not set | ||
| 651 | # CONFIG_SUN_VIDEOPIX is not set | ||
| 652 | # CONFIG_TADPOLE_TS102_UCTRL is not set | 760 | # CONFIG_TADPOLE_TS102_UCTRL is not set |
| 653 | # CONFIG_SUN_JSFLASH is not set | 761 | # CONFIG_SUN_JSFLASH is not set |
| 654 | 762 | ||
| 655 | # | 763 | # |
| 656 | # Unix98 PTY support | ||
| 657 | # | ||
| 658 | CONFIG_UNIX98_PTY_COUNT=256 | ||
| 659 | |||
| 660 | # | ||
| 661 | # File systems | 764 | # File systems |
| 662 | # | 765 | # |
| 663 | CONFIG_EXT2_FS=y | 766 | CONFIG_EXT2_FS=y |
| @@ -666,11 +769,12 @@ CONFIG_EXT2_FS_POSIX_ACL=y | |||
| 666 | CONFIG_EXT2_FS_SECURITY=y | 769 | CONFIG_EXT2_FS_SECURITY=y |
| 667 | # CONFIG_EXT2_FS_XIP is not set | 770 | # CONFIG_EXT2_FS_XIP is not set |
| 668 | # CONFIG_EXT3_FS is not set | 771 | # CONFIG_EXT3_FS is not set |
| 669 | # CONFIG_EXT4DEV_FS is not set | 772 | # CONFIG_EXT4_FS is not set |
| 670 | CONFIG_FS_MBCACHE=y | 773 | CONFIG_FS_MBCACHE=y |
| 671 | # CONFIG_REISERFS_FS is not set | 774 | # CONFIG_REISERFS_FS is not set |
| 672 | # CONFIG_JFS_FS is not set | 775 | # CONFIG_JFS_FS is not set |
| 673 | CONFIG_FS_POSIX_ACL=y | 776 | CONFIG_FS_POSIX_ACL=y |
| 777 | CONFIG_FILE_LOCKING=y | ||
| 674 | # CONFIG_XFS_FS is not set | 778 | # CONFIG_XFS_FS is not set |
| 675 | # CONFIG_OCFS2_FS is not set | 779 | # CONFIG_OCFS2_FS is not set |
| 676 | CONFIG_DNOTIFY=y | 780 | CONFIG_DNOTIFY=y |
| @@ -702,14 +806,12 @@ CONFIG_ISO9660_FS=m | |||
| 702 | CONFIG_PROC_FS=y | 806 | CONFIG_PROC_FS=y |
| 703 | CONFIG_PROC_KCORE=y | 807 | CONFIG_PROC_KCORE=y |
| 704 | CONFIG_PROC_SYSCTL=y | 808 | CONFIG_PROC_SYSCTL=y |
| 809 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 705 | CONFIG_SYSFS=y | 810 | CONFIG_SYSFS=y |
| 706 | # CONFIG_TMPFS is not set | 811 | # CONFIG_TMPFS is not set |
| 707 | # CONFIG_HUGETLB_PAGE is not set | 812 | # CONFIG_HUGETLB_PAGE is not set |
| 708 | # CONFIG_CONFIGFS_FS is not set | 813 | # CONFIG_CONFIGFS_FS is not set |
| 709 | 814 | CONFIG_MISC_FILESYSTEMS=y | |
| 710 | # | ||
| 711 | # Miscellaneous filesystems | ||
| 712 | # | ||
| 713 | # CONFIG_ADFS_FS is not set | 815 | # CONFIG_ADFS_FS is not set |
| 714 | # CONFIG_AFFS_FS is not set | 816 | # CONFIG_AFFS_FS is not set |
| 715 | # CONFIG_HFS_FS is not set | 817 | # CONFIG_HFS_FS is not set |
| @@ -720,6 +822,7 @@ CONFIG_SYSFS=y | |||
| 720 | # CONFIG_CRAMFS is not set | 822 | # CONFIG_CRAMFS is not set |
| 721 | # CONFIG_VXFS_FS is not set | 823 | # CONFIG_VXFS_FS is not set |
| 722 | # CONFIG_MINIX_FS is not set | 824 | # CONFIG_MINIX_FS is not set |
| 825 | # CONFIG_OMFS_FS is not set | ||
| 723 | # CONFIG_HPFS_FS is not set | 826 | # CONFIG_HPFS_FS is not set |
| 724 | # CONFIG_QNX4FS_FS is not set | 827 | # CONFIG_QNX4FS_FS is not set |
| 725 | CONFIG_ROMFS_FS=m | 828 | CONFIG_ROMFS_FS=m |
| @@ -729,13 +832,13 @@ CONFIG_NETWORK_FILESYSTEMS=y | |||
| 729 | CONFIG_NFS_FS=y | 832 | CONFIG_NFS_FS=y |
| 730 | # CONFIG_NFS_V3 is not set | 833 | # CONFIG_NFS_V3 is not set |
| 731 | # CONFIG_NFS_V4 is not set | 834 | # CONFIG_NFS_V4 is not set |
| 732 | # CONFIG_NFSD is not set | ||
| 733 | CONFIG_ROOT_NFS=y | 835 | CONFIG_ROOT_NFS=y |
| 836 | # CONFIG_NFSD is not set | ||
| 734 | CONFIG_LOCKD=y | 837 | CONFIG_LOCKD=y |
| 735 | CONFIG_NFS_COMMON=y | 838 | CONFIG_NFS_COMMON=y |
| 736 | CONFIG_SUNRPC=y | 839 | CONFIG_SUNRPC=y |
| 737 | CONFIG_SUNRPC_GSS=m | 840 | CONFIG_SUNRPC_GSS=m |
| 738 | # CONFIG_SUNRPC_BIND34 is not set | 841 | # CONFIG_SUNRPC_REGISTER_V4 is not set |
| 739 | CONFIG_RPCSEC_GSS_KRB5=m | 842 | CONFIG_RPCSEC_GSS_KRB5=m |
| 740 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | 843 | # CONFIG_RPCSEC_GSS_SPKM3 is not set |
| 741 | # CONFIG_SMB_FS is not set | 844 | # CONFIG_SMB_FS is not set |
| @@ -806,9 +909,12 @@ CONFIG_MAGIC_SYSRQ=y | |||
| 806 | # CONFIG_HEADERS_CHECK is not set | 909 | # CONFIG_HEADERS_CHECK is not set |
| 807 | CONFIG_DEBUG_KERNEL=y | 910 | CONFIG_DEBUG_KERNEL=y |
| 808 | CONFIG_DETECT_SOFTLOCKUP=y | 911 | CONFIG_DETECT_SOFTLOCKUP=y |
| 912 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
| 913 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
| 809 | # CONFIG_SCHED_DEBUG is not set | 914 | # CONFIG_SCHED_DEBUG is not set |
| 810 | # CONFIG_SCHEDSTATS is not set | 915 | # CONFIG_SCHEDSTATS is not set |
| 811 | # CONFIG_TIMER_STATS is not set | 916 | # CONFIG_TIMER_STATS is not set |
| 917 | # CONFIG_DEBUG_OBJECTS is not set | ||
| 812 | # CONFIG_DEBUG_SLAB is not set | 918 | # CONFIG_DEBUG_SLAB is not set |
| 813 | # CONFIG_DEBUG_RT_MUTEXES is not set | 919 | # CONFIG_DEBUG_RT_MUTEXES is not set |
| 814 | # CONFIG_RT_MUTEX_TESTER is not set | 920 | # CONFIG_RT_MUTEX_TESTER is not set |
| @@ -822,37 +928,59 @@ CONFIG_DEBUG_BUGVERBOSE=y | |||
| 822 | # CONFIG_DEBUG_INFO is not set | 928 | # CONFIG_DEBUG_INFO is not set |
| 823 | # CONFIG_DEBUG_VM is not set | 929 | # CONFIG_DEBUG_VM is not set |
| 824 | # CONFIG_DEBUG_WRITECOUNT is not set | 930 | # CONFIG_DEBUG_WRITECOUNT is not set |
| 931 | CONFIG_DEBUG_MEMORY_INIT=y | ||
| 825 | # CONFIG_DEBUG_LIST is not set | 932 | # CONFIG_DEBUG_LIST is not set |
| 826 | # CONFIG_DEBUG_SG is not set | 933 | # CONFIG_DEBUG_SG is not set |
| 827 | CONFIG_FRAME_POINTER=y | 934 | # CONFIG_DEBUG_NOTIFIERS is not set |
| 828 | # CONFIG_BOOT_PRINTK_DELAY is not set | 935 | # CONFIG_BOOT_PRINTK_DELAY is not set |
| 829 | # CONFIG_RCU_TORTURE_TEST is not set | 936 | # CONFIG_RCU_TORTURE_TEST is not set |
| 937 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 830 | # CONFIG_BACKTRACE_SELF_TEST is not set | 938 | # CONFIG_BACKTRACE_SELF_TEST is not set |
| 939 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
| 831 | # CONFIG_FAULT_INJECTION is not set | 940 | # CONFIG_FAULT_INJECTION is not set |
| 941 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 942 | |||
| 943 | # | ||
| 944 | # Tracers | ||
| 945 | # | ||
| 946 | # CONFIG_SCHED_TRACER is not set | ||
| 947 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | ||
| 948 | # CONFIG_BOOT_TRACER is not set | ||
| 949 | # CONFIG_TRACE_BRANCH_PROFILING is not set | ||
| 950 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | ||
| 832 | # CONFIG_SAMPLES is not set | 951 | # CONFIG_SAMPLES is not set |
| 833 | CONFIG_KGDB=y | ||
| 834 | CONFIG_HAVE_ARCH_KGDB=y | 952 | CONFIG_HAVE_ARCH_KGDB=y |
| 953 | CONFIG_KGDB=y | ||
| 835 | CONFIG_KGDB_SERIAL_CONSOLE=y | 954 | CONFIG_KGDB_SERIAL_CONSOLE=y |
| 836 | CONFIG_KGDB_TESTS=y | 955 | CONFIG_KGDB_TESTS=y |
| 837 | # CONFIG_KGDB_TESTS_ON_BOOT is not set | 956 | # CONFIG_KGDB_TESTS_ON_BOOT is not set |
| 838 | # CONFIG_DEBUG_STACK_USAGE is not set | 957 | # CONFIG_DEBUG_STACK_USAGE is not set |
| 958 | # CONFIG_STACK_DEBUG is not set | ||
| 839 | 959 | ||
| 840 | # | 960 | # |
| 841 | # Security options | 961 | # Security options |
| 842 | # | 962 | # |
| 843 | # CONFIG_KEYS is not set | 963 | # CONFIG_KEYS is not set |
| 844 | # CONFIG_SECURITY is not set | 964 | # CONFIG_SECURITY is not set |
| 965 | # CONFIG_SECURITYFS is not set | ||
| 845 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | 966 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set |
| 846 | CONFIG_CRYPTO=y | 967 | CONFIG_CRYPTO=y |
| 847 | 968 | ||
| 848 | # | 969 | # |
| 849 | # Crypto core or helper | 970 | # Crypto core or helper |
| 850 | # | 971 | # |
| 972 | # CONFIG_CRYPTO_FIPS is not set | ||
| 851 | CONFIG_CRYPTO_ALGAPI=y | 973 | CONFIG_CRYPTO_ALGAPI=y |
| 974 | CONFIG_CRYPTO_ALGAPI2=y | ||
| 852 | CONFIG_CRYPTO_AEAD=y | 975 | CONFIG_CRYPTO_AEAD=y |
| 976 | CONFIG_CRYPTO_AEAD2=y | ||
| 853 | CONFIG_CRYPTO_BLKCIPHER=y | 977 | CONFIG_CRYPTO_BLKCIPHER=y |
| 978 | CONFIG_CRYPTO_BLKCIPHER2=y | ||
| 854 | CONFIG_CRYPTO_HASH=y | 979 | CONFIG_CRYPTO_HASH=y |
| 980 | CONFIG_CRYPTO_HASH2=y | ||
| 981 | CONFIG_CRYPTO_RNG2=y | ||
| 855 | CONFIG_CRYPTO_MANAGER=y | 982 | CONFIG_CRYPTO_MANAGER=y |
| 983 | CONFIG_CRYPTO_MANAGER2=y | ||
| 856 | # CONFIG_CRYPTO_GF128MUL is not set | 984 | # CONFIG_CRYPTO_GF128MUL is not set |
| 857 | CONFIG_CRYPTO_NULL=m | 985 | CONFIG_CRYPTO_NULL=m |
| 858 | # CONFIG_CRYPTO_CRYPTD is not set | 986 | # CONFIG_CRYPTO_CRYPTD is not set |
| @@ -890,6 +1018,10 @@ CONFIG_CRYPTO_CRC32C=m | |||
| 890 | CONFIG_CRYPTO_MD4=y | 1018 | CONFIG_CRYPTO_MD4=y |
| 891 | CONFIG_CRYPTO_MD5=y | 1019 | CONFIG_CRYPTO_MD5=y |
| 892 | CONFIG_CRYPTO_MICHAEL_MIC=m | 1020 | CONFIG_CRYPTO_MICHAEL_MIC=m |
| 1021 | # CONFIG_CRYPTO_RMD128 is not set | ||
| 1022 | # CONFIG_CRYPTO_RMD160 is not set | ||
| 1023 | # CONFIG_CRYPTO_RMD256 is not set | ||
| 1024 | # CONFIG_CRYPTO_RMD320 is not set | ||
| 893 | CONFIG_CRYPTO_SHA1=y | 1025 | CONFIG_CRYPTO_SHA1=y |
| 894 | CONFIG_CRYPTO_SHA256=m | 1026 | CONFIG_CRYPTO_SHA256=m |
| 895 | CONFIG_CRYPTO_SHA512=m | 1027 | CONFIG_CRYPTO_SHA512=m |
| @@ -921,15 +1053,21 @@ CONFIG_CRYPTO_TWOFISH_COMMON=m | |||
| 921 | # | 1053 | # |
| 922 | CONFIG_CRYPTO_DEFLATE=y | 1054 | CONFIG_CRYPTO_DEFLATE=y |
| 923 | # CONFIG_CRYPTO_LZO is not set | 1055 | # CONFIG_CRYPTO_LZO is not set |
| 1056 | |||
| 1057 | # | ||
| 1058 | # Random Number Generation | ||
| 1059 | # | ||
| 1060 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 924 | # CONFIG_CRYPTO_HW is not set | 1061 | # CONFIG_CRYPTO_HW is not set |
| 925 | 1062 | ||
| 926 | # | 1063 | # |
| 927 | # Library routines | 1064 | # Library routines |
| 928 | # | 1065 | # |
| 929 | CONFIG_BITREVERSE=y | 1066 | CONFIG_BITREVERSE=y |
| 930 | # CONFIG_GENERIC_FIND_FIRST_BIT is not set | 1067 | CONFIG_GENERIC_FIND_LAST_BIT=y |
| 931 | # CONFIG_CRC_CCITT is not set | 1068 | # CONFIG_CRC_CCITT is not set |
| 932 | # CONFIG_CRC16 is not set | 1069 | # CONFIG_CRC16 is not set |
| 1070 | # CONFIG_CRC_T10DIF is not set | ||
| 933 | # CONFIG_CRC_ITU_T is not set | 1071 | # CONFIG_CRC_ITU_T is not set |
| 934 | CONFIG_CRC32=y | 1072 | CONFIG_CRC32=y |
| 935 | # CONFIG_CRC7 is not set | 1073 | # CONFIG_CRC7 is not set |
diff --git a/arch/sparc/include/asm/oplib_32.h b/arch/sparc/include/asm/oplib_32.h index 73d45521db04..33e31ce6b31f 100644 --- a/arch/sparc/include/asm/oplib_32.h +++ b/arch/sparc/include/asm/oplib_32.h | |||
| @@ -177,17 +177,6 @@ extern void prom_putsegment(int context, unsigned long virt_addr, | |||
| 177 | 177 | ||
| 178 | /* PROM device tree traversal functions... */ | 178 | /* PROM device tree traversal functions... */ |
| 179 | 179 | ||
| 180 | #ifdef PROMLIB_INTERNAL | ||
| 181 | |||
| 182 | /* Internal version of prom_getchild. */ | ||
| 183 | extern int __prom_getchild(int parent_node); | ||
| 184 | |||
| 185 | /* Internal version of prom_getsibling. */ | ||
| 186 | extern int __prom_getsibling(int node); | ||
| 187 | |||
| 188 | #endif | ||
| 189 | |||
| 190 | |||
| 191 | /* Get the child node of the given node, or zero if no child exists. */ | 180 | /* Get the child node of the given node, or zero if no child exists. */ |
| 192 | extern int prom_getchild(int parent_node); | 181 | extern int prom_getchild(int parent_node); |
| 193 | 182 | ||
diff --git a/arch/sparc/include/asm/oplib_64.h b/arch/sparc/include/asm/oplib_64.h index 6d2c2ca98039..a5db0317b5fb 100644 --- a/arch/sparc/include/asm/oplib_64.h +++ b/arch/sparc/include/asm/oplib_64.h | |||
| @@ -218,16 +218,6 @@ extern void prom_unmap(unsigned long size, unsigned long vaddr); | |||
| 218 | 218 | ||
| 219 | /* PROM device tree traversal functions... */ | 219 | /* PROM device tree traversal functions... */ |
| 220 | 220 | ||
| 221 | #ifdef PROMLIB_INTERNAL | ||
| 222 | |||
| 223 | /* Internal version of prom_getchild. */ | ||
| 224 | extern int __prom_getchild(int parent_node); | ||
| 225 | |||
| 226 | /* Internal version of prom_getsibling. */ | ||
| 227 | extern int __prom_getsibling(int node); | ||
| 228 | |||
| 229 | #endif | ||
| 230 | |||
| 231 | /* Get the child node of the given node, or zero if no child exists. */ | 221 | /* Get the child node of the given node, or zero if no child exists. */ |
| 232 | extern int prom_getchild(int parent_node); | 222 | extern int prom_getchild(int parent_node); |
| 233 | 223 | ||
diff --git a/arch/sparc/include/asm/signal.h b/arch/sparc/include/asm/signal.h index 41535e77b255..cba45206b7f2 100644 --- a/arch/sparc/include/asm/signal.h +++ b/arch/sparc/include/asm/signal.h | |||
| @@ -84,7 +84,11 @@ | |||
| 84 | 84 | ||
| 85 | #define __OLD_NSIG 32 | 85 | #define __OLD_NSIG 32 |
| 86 | #define __NEW_NSIG 64 | 86 | #define __NEW_NSIG 64 |
| 87 | #ifdef __arch64__ | ||
| 87 | #define _NSIG_BPW 64 | 88 | #define _NSIG_BPW 64 |
| 89 | #else | ||
| 90 | #define _NSIG_BPW 32 | ||
| 91 | #endif | ||
| 88 | #define _NSIG_WORDS (__NEW_NSIG / _NSIG_BPW) | 92 | #define _NSIG_WORDS (__NEW_NSIG / _NSIG_BPW) |
| 89 | 93 | ||
| 90 | #define SIGRTMIN 32 | 94 | #define SIGRTMIN 32 |
diff --git a/arch/sparc/kernel/auxio_32.c b/arch/sparc/kernel/auxio_32.c index 09c857215a52..45c41232fc4c 100644 --- a/arch/sparc/kernel/auxio_32.c +++ b/arch/sparc/kernel/auxio_32.c | |||
| @@ -76,6 +76,7 @@ unsigned char get_auxio(void) | |||
| 76 | return sbus_readb(auxio_register); | 76 | return sbus_readb(auxio_register); |
| 77 | return 0; | 77 | return 0; |
| 78 | } | 78 | } |
| 79 | EXPORT_SYMBOL(get_auxio); | ||
| 79 | 80 | ||
| 80 | void set_auxio(unsigned char bits_on, unsigned char bits_off) | 81 | void set_auxio(unsigned char bits_on, unsigned char bits_off) |
| 81 | { | 82 | { |
| @@ -102,7 +103,7 @@ void set_auxio(unsigned char bits_on, unsigned char bits_off) | |||
| 102 | }; | 103 | }; |
| 103 | spin_unlock_irqrestore(&auxio_lock, flags); | 104 | spin_unlock_irqrestore(&auxio_lock, flags); |
| 104 | } | 105 | } |
| 105 | 106 | EXPORT_SYMBOL(set_auxio); | |
| 106 | 107 | ||
| 107 | /* sun4m power control register (AUXIO2) */ | 108 | /* sun4m power control register (AUXIO2) */ |
| 108 | 109 | ||
diff --git a/arch/sparc/kernel/auxio_64.c b/arch/sparc/kernel/auxio_64.c index 8b67347d4221..9f52db2d441c 100644 --- a/arch/sparc/kernel/auxio_64.c +++ b/arch/sparc/kernel/auxio_64.c | |||
| @@ -72,6 +72,7 @@ void auxio_set_led(int on) | |||
| 72 | bit = (ebus ? AUXIO_PCIO_LED : AUXIO_AUX1_LED); | 72 | bit = (ebus ? AUXIO_PCIO_LED : AUXIO_AUX1_LED); |
| 73 | __auxio_set_bit(bit, on, ebus); | 73 | __auxio_set_bit(bit, on, ebus); |
| 74 | } | 74 | } |
| 75 | EXPORT_SYMBOL(auxio_set_led); | ||
| 75 | 76 | ||
| 76 | static void __auxio_sbus_set_lte(int on) | 77 | static void __auxio_sbus_set_lte(int on) |
| 77 | { | 78 | { |
| @@ -90,6 +91,7 @@ void auxio_set_lte(int on) | |||
| 90 | break; | 91 | break; |
| 91 | } | 92 | } |
| 92 | } | 93 | } |
| 94 | EXPORT_SYMBOL(auxio_set_lte); | ||
| 93 | 95 | ||
| 94 | static struct of_device_id __initdata auxio_match[] = { | 96 | static struct of_device_id __initdata auxio_match[] = { |
| 95 | { | 97 | { |
diff --git a/arch/sparc/kernel/cpu.c b/arch/sparc/kernel/cpu.c index 6c2da2420f76..f0b825505da5 100644 --- a/arch/sparc/kernel/cpu.c +++ b/arch/sparc/kernel/cpu.c | |||
| @@ -5,6 +5,7 @@ | |||
| 5 | */ | 5 | */ |
| 6 | 6 | ||
| 7 | #include <linux/kernel.h> | 7 | #include <linux/kernel.h> |
| 8 | #include <linux/module.h> | ||
| 8 | #include <linux/init.h> | 9 | #include <linux/init.h> |
| 9 | #include <linux/smp.h> | 10 | #include <linux/smp.h> |
| 10 | #include <linux/threads.h> | 11 | #include <linux/threads.h> |
| @@ -20,6 +21,7 @@ | |||
| 20 | #include "kernel.h" | 21 | #include "kernel.h" |
| 21 | 22 | ||
| 22 | DEFINE_PER_CPU(cpuinfo_sparc, __cpu_data) = { 0 }; | 23 | DEFINE_PER_CPU(cpuinfo_sparc, __cpu_data) = { 0 }; |
| 24 | EXPORT_PER_CPU_SYMBOL(__cpu_data); | ||
| 23 | 25 | ||
| 24 | struct cpu_info { | 26 | struct cpu_info { |
| 25 | int psr_vers; | 27 | int psr_vers; |
diff --git a/arch/sparc/kernel/idprom.c b/arch/sparc/kernel/idprom.c index c16135e0c151..57922f69c3f7 100644 --- a/arch/sparc/kernel/idprom.c +++ b/arch/sparc/kernel/idprom.c | |||
| @@ -8,11 +8,14 @@ | |||
| 8 | #include <linux/kernel.h> | 8 | #include <linux/kernel.h> |
| 9 | #include <linux/types.h> | 9 | #include <linux/types.h> |
| 10 | #include <linux/init.h> | 10 | #include <linux/init.h> |
| 11 | #include <linux/module.h> | ||
| 11 | 12 | ||
| 12 | #include <asm/oplib.h> | 13 | #include <asm/oplib.h> |
| 13 | #include <asm/idprom.h> | 14 | #include <asm/idprom.h> |
| 14 | 15 | ||
| 15 | struct idprom *idprom; | 16 | struct idprom *idprom; |
| 17 | EXPORT_SYMBOL(idprom); | ||
| 18 | |||
| 16 | static struct idprom idprom_buffer; | 19 | static struct idprom idprom_buffer; |
| 17 | 20 | ||
| 18 | #ifdef CONFIG_SPARC32 | 21 | #ifdef CONFIG_SPARC32 |
diff --git a/arch/sparc/kernel/ioport.c b/arch/sparc/kernel/ioport.c index 7ce14f05eb48..87ea0d03d975 100644 --- a/arch/sparc/kernel/ioport.c +++ b/arch/sparc/kernel/ioport.c | |||
| @@ -120,6 +120,7 @@ void __iomem *ioremap(unsigned long offset, unsigned long size) | |||
| 120 | sprintf(name, "phys_%08x", (u32)offset); | 120 | sprintf(name, "phys_%08x", (u32)offset); |
| 121 | return _sparc_alloc_io(0, offset, size, name); | 121 | return _sparc_alloc_io(0, offset, size, name); |
| 122 | } | 122 | } |
| 123 | EXPORT_SYMBOL(ioremap); | ||
| 123 | 124 | ||
| 124 | /* | 125 | /* |
| 125 | * Comlimentary to ioremap(). | 126 | * Comlimentary to ioremap(). |
| @@ -141,6 +142,7 @@ void iounmap(volatile void __iomem *virtual) | |||
| 141 | kfree(res); | 142 | kfree(res); |
| 142 | } | 143 | } |
| 143 | } | 144 | } |
| 145 | EXPORT_SYMBOL(iounmap); | ||
| 144 | 146 | ||
| 145 | void __iomem *of_ioremap(struct resource *res, unsigned long offset, | 147 | void __iomem *of_ioremap(struct resource *res, unsigned long offset, |
| 146 | unsigned long size, char *name) | 148 | unsigned long size, char *name) |
| @@ -237,6 +239,7 @@ void sbus_set_sbus64(struct device *dev, int x) | |||
| 237 | { | 239 | { |
| 238 | printk("sbus_set_sbus64: unsupported\n"); | 240 | printk("sbus_set_sbus64: unsupported\n"); |
| 239 | } | 241 | } |
| 242 | EXPORT_SYMBOL(sbus_set_sbus64); | ||
| 240 | 243 | ||
| 241 | /* | 244 | /* |
| 242 | * Allocate a chunk of memory suitable for DMA. | 245 | * Allocate a chunk of memory suitable for DMA. |
| @@ -436,6 +439,7 @@ void *pci_alloc_consistent(struct pci_dev *pdev, size_t len, dma_addr_t *pba) | |||
| 436 | *pba = virt_to_phys(va); /* equals virt_to_bus (R.I.P.) for us. */ | 439 | *pba = virt_to_phys(va); /* equals virt_to_bus (R.I.P.) for us. */ |
| 437 | return (void *) res->start; | 440 | return (void *) res->start; |
| 438 | } | 441 | } |
| 442 | EXPORT_SYMBOL(pci_alloc_consistent); | ||
| 439 | 443 | ||
| 440 | /* Free and unmap a consistent DMA buffer. | 444 | /* Free and unmap a consistent DMA buffer. |
| 441 | * cpu_addr is what was returned from pci_alloc_consistent, | 445 | * cpu_addr is what was returned from pci_alloc_consistent, |
| @@ -477,6 +481,7 @@ void pci_free_consistent(struct pci_dev *pdev, size_t n, void *p, dma_addr_t ba) | |||
| 477 | 481 | ||
| 478 | free_pages(pgp, get_order(n)); | 482 | free_pages(pgp, get_order(n)); |
| 479 | } | 483 | } |
| 484 | EXPORT_SYMBOL(pci_free_consistent); | ||
| 480 | 485 | ||
| 481 | /* Map a single buffer of the indicated size for DMA in streaming mode. | 486 | /* Map a single buffer of the indicated size for DMA in streaming mode. |
| 482 | * The 32-bit bus address to use is returned. | 487 | * The 32-bit bus address to use is returned. |
| @@ -491,6 +496,7 @@ dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr, size_t size, | |||
| 491 | /* IIep is write-through, not flushing. */ | 496 | /* IIep is write-through, not flushing. */ |
| 492 | return virt_to_phys(ptr); | 497 | return virt_to_phys(ptr); |
| 493 | } | 498 | } |
| 499 | EXPORT_SYMBOL(pci_map_single); | ||
| 494 | 500 | ||
| 495 | /* Unmap a single streaming mode DMA translation. The dma_addr and size | 501 | /* Unmap a single streaming mode DMA translation. The dma_addr and size |
| 496 | * must match what was provided for in a previous pci_map_single call. All | 502 | * must match what was provided for in a previous pci_map_single call. All |
| @@ -508,6 +514,7 @@ void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t ba, size_t size, | |||
| 508 | (size + PAGE_SIZE-1) & PAGE_MASK); | 514 | (size + PAGE_SIZE-1) & PAGE_MASK); |
| 509 | } | 515 | } |
| 510 | } | 516 | } |
| 517 | EXPORT_SYMBOL(pci_unmap_single); | ||
| 511 | 518 | ||
| 512 | /* | 519 | /* |
| 513 | * Same as pci_map_single, but with pages. | 520 | * Same as pci_map_single, but with pages. |
| @@ -519,6 +526,7 @@ dma_addr_t pci_map_page(struct pci_dev *hwdev, struct page *page, | |||
| 519 | /* IIep is write-through, not flushing. */ | 526 | /* IIep is write-through, not flushing. */ |
| 520 | return page_to_phys(page) + offset; | 527 | return page_to_phys(page) + offset; |
| 521 | } | 528 | } |
| 529 | EXPORT_SYMBOL(pci_map_page); | ||
| 522 | 530 | ||
| 523 | void pci_unmap_page(struct pci_dev *hwdev, | 531 | void pci_unmap_page(struct pci_dev *hwdev, |
| 524 | dma_addr_t dma_address, size_t size, int direction) | 532 | dma_addr_t dma_address, size_t size, int direction) |
| @@ -526,6 +534,7 @@ void pci_unmap_page(struct pci_dev *hwdev, | |||
| 526 | BUG_ON(direction == PCI_DMA_NONE); | 534 | BUG_ON(direction == PCI_DMA_NONE); |
| 527 | /* mmu_inval_dma_area XXX */ | 535 | /* mmu_inval_dma_area XXX */ |
| 528 | } | 536 | } |
| 537 | EXPORT_SYMBOL(pci_unmap_page); | ||
| 529 | 538 | ||
| 530 | /* Map a set of buffers described by scatterlist in streaming | 539 | /* Map a set of buffers described by scatterlist in streaming |
| 531 | * mode for DMA. This is the scather-gather version of the | 540 | * mode for DMA. This is the scather-gather version of the |
| @@ -557,6 +566,7 @@ int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sgl, int nents, | |||
| 557 | } | 566 | } |
| 558 | return nents; | 567 | return nents; |
| 559 | } | 568 | } |
| 569 | EXPORT_SYMBOL(pci_map_sg); | ||
| 560 | 570 | ||
| 561 | /* Unmap a set of streaming mode DMA translations. | 571 | /* Unmap a set of streaming mode DMA translations. |
| 562 | * Again, cpu read rules concerning calls here are the same as for | 572 | * Again, cpu read rules concerning calls here are the same as for |
| @@ -578,6 +588,7 @@ void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sgl, int nents, | |||
| 578 | } | 588 | } |
| 579 | } | 589 | } |
| 580 | } | 590 | } |
| 591 | EXPORT_SYMBOL(pci_unmap_sg); | ||
| 581 | 592 | ||
| 582 | /* Make physical memory consistent for a single | 593 | /* Make physical memory consistent for a single |
| 583 | * streaming mode DMA translation before or after a transfer. | 594 | * streaming mode DMA translation before or after a transfer. |
| @@ -597,6 +608,7 @@ void pci_dma_sync_single_for_cpu(struct pci_dev *hwdev, dma_addr_t ba, size_t si | |||
| 597 | (size + PAGE_SIZE-1) & PAGE_MASK); | 608 | (size + PAGE_SIZE-1) & PAGE_MASK); |
| 598 | } | 609 | } |
| 599 | } | 610 | } |
| 611 | EXPORT_SYMBOL(pci_dma_sync_single_for_cpu); | ||
| 600 | 612 | ||
| 601 | void pci_dma_sync_single_for_device(struct pci_dev *hwdev, dma_addr_t ba, size_t size, int direction) | 613 | void pci_dma_sync_single_for_device(struct pci_dev *hwdev, dma_addr_t ba, size_t size, int direction) |
| 602 | { | 614 | { |
| @@ -606,6 +618,7 @@ void pci_dma_sync_single_for_device(struct pci_dev *hwdev, dma_addr_t ba, size_t | |||
| 606 | (size + PAGE_SIZE-1) & PAGE_MASK); | 618 | (size + PAGE_SIZE-1) & PAGE_MASK); |
| 607 | } | 619 | } |
| 608 | } | 620 | } |
| 621 | EXPORT_SYMBOL(pci_dma_sync_single_for_device); | ||
| 609 | 622 | ||
| 610 | /* Make physical memory consistent for a set of streaming | 623 | /* Make physical memory consistent for a set of streaming |
| 611 | * mode DMA translations after a transfer. | 624 | * mode DMA translations after a transfer. |
| @@ -628,6 +641,7 @@ void pci_dma_sync_sg_for_cpu(struct pci_dev *hwdev, struct scatterlist *sgl, int | |||
| 628 | } | 641 | } |
| 629 | } | 642 | } |
| 630 | } | 643 | } |
| 644 | EXPORT_SYMBOL(pci_dma_sync_sg_for_cpu); | ||
| 631 | 645 | ||
| 632 | void pci_dma_sync_sg_for_device(struct pci_dev *hwdev, struct scatterlist *sgl, int nents, int direction) | 646 | void pci_dma_sync_sg_for_device(struct pci_dev *hwdev, struct scatterlist *sgl, int nents, int direction) |
| 633 | { | 647 | { |
| @@ -644,6 +658,7 @@ void pci_dma_sync_sg_for_device(struct pci_dev *hwdev, struct scatterlist *sgl, | |||
| 644 | } | 658 | } |
| 645 | } | 659 | } |
| 646 | } | 660 | } |
| 661 | EXPORT_SYMBOL(pci_dma_sync_sg_for_device); | ||
| 647 | #endif /* CONFIG_PCI */ | 662 | #endif /* CONFIG_PCI */ |
| 648 | 663 | ||
| 649 | #ifdef CONFIG_PROC_FS | 664 | #ifdef CONFIG_PROC_FS |
diff --git a/arch/sparc/kernel/irq_32.c b/arch/sparc/kernel/irq_32.c index 1eff942fe22f..44dd5ee64339 100644 --- a/arch/sparc/kernel/irq_32.c +++ b/arch/sparc/kernel/irq_32.c | |||
| @@ -294,6 +294,7 @@ void synchronize_irq(unsigned int irq) | |||
| 294 | while (sparc_irq[cpu_irq].flags & SPARC_IRQ_INPROGRESS) | 294 | while (sparc_irq[cpu_irq].flags & SPARC_IRQ_INPROGRESS) |
| 295 | cpu_relax(); | 295 | cpu_relax(); |
| 296 | } | 296 | } |
| 297 | EXPORT_SYMBOL(synchronize_irq); | ||
| 297 | #endif /* SMP */ | 298 | #endif /* SMP */ |
| 298 | 299 | ||
| 299 | void unexpected_irq(int irq, void *dev_id, struct pt_regs * regs) | 300 | void unexpected_irq(int irq, void *dev_id, struct pt_regs * regs) |
diff --git a/arch/sparc/kernel/pci.c b/arch/sparc/kernel/pci.c index 923e9bbb9fe2..4638fba799e4 100644 --- a/arch/sparc/kernel/pci.c +++ b/arch/sparc/kernel/pci.c | |||
| @@ -1077,6 +1077,7 @@ int pci_dma_supported(struct pci_dev *pdev, u64 device_mask) | |||
| 1077 | 1077 | ||
| 1078 | return (device_mask & dma_addr_mask) == dma_addr_mask; | 1078 | return (device_mask & dma_addr_mask) == dma_addr_mask; |
| 1079 | } | 1079 | } |
| 1080 | EXPORT_SYMBOL(pci_dma_supported); | ||
| 1080 | 1081 | ||
| 1081 | void pci_resource_to_user(const struct pci_dev *pdev, int bar, | 1082 | void pci_resource_to_user(const struct pci_dev *pdev, int bar, |
| 1082 | const struct resource *rp, resource_size_t *start, | 1083 | const struct resource *rp, resource_size_t *start, |
diff --git a/arch/sparc/kernel/pcic.c b/arch/sparc/kernel/pcic.c index 75ed98be3edf..85e7037429b9 100644 --- a/arch/sparc/kernel/pcic.c +++ b/arch/sparc/kernel/pcic.c | |||
| @@ -956,6 +956,7 @@ void outsb(unsigned long addr, const void *src, unsigned long count) | |||
| 956 | /* addr += 1; */ | 956 | /* addr += 1; */ |
| 957 | } | 957 | } |
| 958 | } | 958 | } |
| 959 | EXPORT_SYMBOL(outsb); | ||
| 959 | 960 | ||
| 960 | void outsw(unsigned long addr, const void *src, unsigned long count) | 961 | void outsw(unsigned long addr, const void *src, unsigned long count) |
| 961 | { | 962 | { |
| @@ -966,6 +967,7 @@ void outsw(unsigned long addr, const void *src, unsigned long count) | |||
| 966 | /* addr += 2; */ | 967 | /* addr += 2; */ |
| 967 | } | 968 | } |
| 968 | } | 969 | } |
| 970 | EXPORT_SYMBOL(outsw); | ||
| 969 | 971 | ||
| 970 | void outsl(unsigned long addr, const void *src, unsigned long count) | 972 | void outsl(unsigned long addr, const void *src, unsigned long count) |
| 971 | { | 973 | { |
| @@ -976,6 +978,7 @@ void outsl(unsigned long addr, const void *src, unsigned long count) | |||
| 976 | /* addr += 4; */ | 978 | /* addr += 4; */ |
| 977 | } | 979 | } |
| 978 | } | 980 | } |
| 981 | EXPORT_SYMBOL(outsl); | ||
| 979 | 982 | ||
| 980 | void insb(unsigned long addr, void *dst, unsigned long count) | 983 | void insb(unsigned long addr, void *dst, unsigned long count) |
| 981 | { | 984 | { |
| @@ -986,6 +989,7 @@ void insb(unsigned long addr, void *dst, unsigned long count) | |||
| 986 | /* addr += 1; */ | 989 | /* addr += 1; */ |
| 987 | } | 990 | } |
| 988 | } | 991 | } |
| 992 | EXPORT_SYMBOL(insb); | ||
| 989 | 993 | ||
| 990 | void insw(unsigned long addr, void *dst, unsigned long count) | 994 | void insw(unsigned long addr, void *dst, unsigned long count) |
| 991 | { | 995 | { |
| @@ -996,6 +1000,7 @@ void insw(unsigned long addr, void *dst, unsigned long count) | |||
| 996 | /* addr += 2; */ | 1000 | /* addr += 2; */ |
| 997 | } | 1001 | } |
| 998 | } | 1002 | } |
| 1003 | EXPORT_SYMBOL(insw); | ||
| 999 | 1004 | ||
| 1000 | void insl(unsigned long addr, void *dst, unsigned long count) | 1005 | void insl(unsigned long addr, void *dst, unsigned long count) |
| 1001 | { | 1006 | { |
| @@ -1009,5 +1014,6 @@ void insl(unsigned long addr, void *dst, unsigned long count) | |||
| 1009 | /* addr += 4; */ | 1014 | /* addr += 4; */ |
| 1010 | } | 1015 | } |
| 1011 | } | 1016 | } |
| 1017 | EXPORT_SYMBOL(insl); | ||
| 1012 | 1018 | ||
| 1013 | subsys_initcall(pcic_init); | 1019 | subsys_initcall(pcic_init); |
diff --git a/arch/sparc/kernel/process_32.c b/arch/sparc/kernel/process_32.c index 5a8d8ced33da..f4bee35a1b46 100644 --- a/arch/sparc/kernel/process_32.c +++ b/arch/sparc/kernel/process_32.c | |||
| @@ -44,6 +44,7 @@ | |||
| 44 | * Set in pm platform drivers (apc.c and pmc.c) | 44 | * Set in pm platform drivers (apc.c and pmc.c) |
| 45 | */ | 45 | */ |
| 46 | void (*pm_idle)(void); | 46 | void (*pm_idle)(void); |
| 47 | EXPORT_SYMBOL(pm_idle); | ||
| 47 | 48 | ||
| 48 | /* | 49 | /* |
| 49 | * Power-off handler instantiation for pm.h compliance | 50 | * Power-off handler instantiation for pm.h compliance |
| @@ -673,6 +674,7 @@ pid_t kernel_thread(int (*fn)(void *), void * arg, unsigned long flags) | |||
| 673 | "g1", "g2", "g3", "o0", "o1", "memory", "cc"); | 674 | "g1", "g2", "g3", "o0", "o1", "memory", "cc"); |
| 674 | return retval; | 675 | return retval; |
| 675 | } | 676 | } |
| 677 | EXPORT_SYMBOL(kernel_thread); | ||
| 676 | 678 | ||
| 677 | unsigned long get_wchan(struct task_struct *task) | 679 | unsigned long get_wchan(struct task_struct *task) |
| 678 | { | 680 | { |
diff --git a/arch/sparc/kernel/process_64.c b/arch/sparc/kernel/process_64.c index d5e2acef9877..cc8b5604442c 100644 --- a/arch/sparc/kernel/process_64.c +++ b/arch/sparc/kernel/process_64.c | |||
| @@ -678,6 +678,7 @@ pid_t kernel_thread(int (*fn)(void *), void * arg, unsigned long flags) | |||
| 678 | "g1", "g2", "g3", "o0", "o1", "memory", "cc"); | 678 | "g1", "g2", "g3", "o0", "o1", "memory", "cc"); |
| 679 | return retval; | 679 | return retval; |
| 680 | } | 680 | } |
| 681 | EXPORT_SYMBOL(kernel_thread); | ||
| 681 | 682 | ||
| 682 | typedef struct { | 683 | typedef struct { |
| 683 | union { | 684 | union { |
| @@ -743,6 +744,7 @@ int dump_fpu (struct pt_regs * regs, elf_fpregset_t * fpregs) | |||
| 743 | } | 744 | } |
| 744 | return 1; | 745 | return 1; |
| 745 | } | 746 | } |
| 747 | EXPORT_SYMBOL(dump_fpu); | ||
| 746 | 748 | ||
| 747 | /* | 749 | /* |
| 748 | * sparc_execve() executes a new program after the asm stub has set | 750 | * sparc_execve() executes a new program after the asm stub has set |
diff --git a/arch/sparc/kernel/psycho_common.c b/arch/sparc/kernel/psycho_common.c index 40689ae3c9b0..8f1478475421 100644 --- a/arch/sparc/kernel/psycho_common.c +++ b/arch/sparc/kernel/psycho_common.c | |||
| @@ -11,19 +11,19 @@ | |||
| 11 | #include "iommu_common.h" | 11 | #include "iommu_common.h" |
| 12 | #include "psycho_common.h" | 12 | #include "psycho_common.h" |
| 13 | 13 | ||
| 14 | #define PSYCHO_STRBUF_CTRL_DENAB 0x0000000000000002UL | 14 | #define PSYCHO_STRBUF_CTRL_DENAB 0x0000000000000002ULL |
| 15 | #define PSYCHO_STCERR_WRITE 0x0000000000000002UL | 15 | #define PSYCHO_STCERR_WRITE 0x0000000000000002ULL |
| 16 | #define PSYCHO_STCERR_READ 0x0000000000000001UL | 16 | #define PSYCHO_STCERR_READ 0x0000000000000001ULL |
| 17 | #define PSYCHO_STCTAG_PPN 0x0fffffff00000000UL | 17 | #define PSYCHO_STCTAG_PPN 0x0fffffff00000000ULL |
| 18 | #define PSYCHO_STCTAG_VPN 0x00000000ffffe000UL | 18 | #define PSYCHO_STCTAG_VPN 0x00000000ffffe000ULL |
| 19 | #define PSYCHO_STCTAG_VALID 0x0000000000000002UL | 19 | #define PSYCHO_STCTAG_VALID 0x0000000000000002ULL |
| 20 | #define PSYCHO_STCTAG_WRITE 0x0000000000000001UL | 20 | #define PSYCHO_STCTAG_WRITE 0x0000000000000001ULL |
| 21 | #define PSYCHO_STCLINE_LINDX 0x0000000001e00000UL | 21 | #define PSYCHO_STCLINE_LINDX 0x0000000001e00000ULL |
| 22 | #define PSYCHO_STCLINE_SPTR 0x00000000001f8000UL | 22 | #define PSYCHO_STCLINE_SPTR 0x00000000001f8000ULL |
| 23 | #define PSYCHO_STCLINE_LADDR 0x0000000000007f00UL | 23 | #define PSYCHO_STCLINE_LADDR 0x0000000000007f00ULL |
| 24 | #define PSYCHO_STCLINE_EPTR 0x00000000000000fcUL | 24 | #define PSYCHO_STCLINE_EPTR 0x00000000000000fcULL |
| 25 | #define PSYCHO_STCLINE_VALID 0x0000000000000002UL | 25 | #define PSYCHO_STCLINE_VALID 0x0000000000000002ULL |
| 26 | #define PSYCHO_STCLINE_FOFN 0x0000000000000001UL | 26 | #define PSYCHO_STCLINE_FOFN 0x0000000000000001ULL |
| 27 | 27 | ||
| 28 | static DEFINE_SPINLOCK(stc_buf_lock); | 28 | static DEFINE_SPINLOCK(stc_buf_lock); |
| 29 | static unsigned long stc_error_buf[128]; | 29 | static unsigned long stc_error_buf[128]; |
| @@ -144,10 +144,10 @@ static void psycho_record_iommu_tags_and_data(struct pci_pbm_info *pbm, | |||
| 144 | #define PSYCHO_IOMMU_TAG_WRITE (0x1UL << 21UL) | 144 | #define PSYCHO_IOMMU_TAG_WRITE (0x1UL << 21UL) |
| 145 | #define PSYCHO_IOMMU_TAG_STREAM (0x1UL << 20UL) | 145 | #define PSYCHO_IOMMU_TAG_STREAM (0x1UL << 20UL) |
| 146 | #define PSYCHO_IOMMU_TAG_SIZE (0x1UL << 19UL) | 146 | #define PSYCHO_IOMMU_TAG_SIZE (0x1UL << 19UL) |
| 147 | #define PSYCHO_IOMMU_TAG_VPAGE 0x7ffffUL | 147 | #define PSYCHO_IOMMU_TAG_VPAGE 0x7ffffULL |
| 148 | #define PSYCHO_IOMMU_DATA_VALID (1UL << 30UL) | 148 | #define PSYCHO_IOMMU_DATA_VALID (1UL << 30UL) |
| 149 | #define PSYCHO_IOMMU_DATA_CACHE (1UL << 28UL) | 149 | #define PSYCHO_IOMMU_DATA_CACHE (1UL << 28UL) |
| 150 | #define PSYCHO_IOMMU_DATA_PPAGE 0xfffffffUL | 150 | #define PSYCHO_IOMMU_DATA_PPAGE 0xfffffffULL |
| 151 | 151 | ||
| 152 | static void psycho_dump_iommu_tags_and_data(struct pci_pbm_info *pbm, | 152 | static void psycho_dump_iommu_tags_and_data(struct pci_pbm_info *pbm, |
| 153 | u64 *tag, u64 *data) | 153 | u64 *tag, u64 *data) |
| @@ -190,7 +190,7 @@ static void psycho_dump_iommu_tags_and_data(struct pci_pbm_info *pbm, | |||
| 190 | pbm->name, i, | 190 | pbm->name, i, |
| 191 | ((data_val & PSYCHO_IOMMU_DATA_VALID) ? 1 : 0), | 191 | ((data_val & PSYCHO_IOMMU_DATA_VALID) ? 1 : 0), |
| 192 | ((data_val & PSYCHO_IOMMU_DATA_CACHE) ? 1 : 0), | 192 | ((data_val & PSYCHO_IOMMU_DATA_CACHE) ? 1 : 0), |
| 193 | (data_val & PSYCHO_IOMMU_DATA_PPAGE)<<IOMMU_PAGE_SHIFT); | 193 | (data_val & PSYCHO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT); |
| 194 | } | 194 | } |
| 195 | } | 195 | } |
| 196 | 196 | ||
| @@ -285,20 +285,20 @@ static irqreturn_t psycho_pcierr_intr_other(struct pci_pbm_info *pbm) | |||
| 285 | return ret; | 285 | return ret; |
| 286 | } | 286 | } |
| 287 | 287 | ||
| 288 | #define PSYCHO_PCIAFSR_PMA 0x8000000000000000UL | 288 | #define PSYCHO_PCIAFSR_PMA 0x8000000000000000ULL |
| 289 | #define PSYCHO_PCIAFSR_PTA 0x4000000000000000UL | 289 | #define PSYCHO_PCIAFSR_PTA 0x4000000000000000ULL |
| 290 | #define PSYCHO_PCIAFSR_PRTRY 0x2000000000000000UL | 290 | #define PSYCHO_PCIAFSR_PRTRY 0x2000000000000000ULL |
| 291 | #define PSYCHO_PCIAFSR_PPERR 0x1000000000000000UL | 291 | #define PSYCHO_PCIAFSR_PPERR 0x1000000000000000ULL |
| 292 | #define PSYCHO_PCIAFSR_SMA 0x0800000000000000UL | 292 | #define PSYCHO_PCIAFSR_SMA 0x0800000000000000ULL |
| 293 | #define PSYCHO_PCIAFSR_STA 0x0400000000000000UL | 293 | #define PSYCHO_PCIAFSR_STA 0x0400000000000000ULL |
| 294 | #define PSYCHO_PCIAFSR_SRTRY 0x0200000000000000UL | 294 | #define PSYCHO_PCIAFSR_SRTRY 0x0200000000000000ULL |
| 295 | #define PSYCHO_PCIAFSR_SPERR 0x0100000000000000UL | 295 | #define PSYCHO_PCIAFSR_SPERR 0x0100000000000000ULL |
| 296 | #define PSYCHO_PCIAFSR_RESV1 0x00ff000000000000UL | 296 | #define PSYCHO_PCIAFSR_RESV1 0x00ff000000000000ULL |
| 297 | #define PSYCHO_PCIAFSR_BMSK 0x0000ffff00000000UL | 297 | #define PSYCHO_PCIAFSR_BMSK 0x0000ffff00000000ULL |
| 298 | #define PSYCHO_PCIAFSR_BLK 0x0000000080000000UL | 298 | #define PSYCHO_PCIAFSR_BLK 0x0000000080000000ULL |
| 299 | #define PSYCHO_PCIAFSR_RESV2 0x0000000040000000UL | 299 | #define PSYCHO_PCIAFSR_RESV2 0x0000000040000000ULL |
| 300 | #define PSYCHO_PCIAFSR_MID 0x000000003e000000UL | 300 | #define PSYCHO_PCIAFSR_MID 0x000000003e000000ULL |
| 301 | #define PSYCHO_PCIAFSR_RESV3 0x0000000001ffffffUL | 301 | #define PSYCHO_PCIAFSR_RESV3 0x0000000001ffffffULL |
| 302 | 302 | ||
| 303 | irqreturn_t psycho_pcierr_intr(int irq, void *dev_id) | 303 | irqreturn_t psycho_pcierr_intr(int irq, void *dev_id) |
| 304 | { | 304 | { |
diff --git a/arch/sparc/kernel/sbus.c b/arch/sparc/kernel/sbus.c index 2ead310066d1..406e0872504e 100644 --- a/arch/sparc/kernel/sbus.c +++ b/arch/sparc/kernel/sbus.c | |||
| @@ -117,6 +117,7 @@ void sbus_set_sbus64(struct device *dev, int bursts) | |||
| 117 | val |= (1UL << 4UL); | 117 | val |= (1UL << 4UL); |
| 118 | upa_writeq(val, cfg_reg); | 118 | upa_writeq(val, cfg_reg); |
| 119 | } | 119 | } |
| 120 | EXPORT_SYMBOL(sbus_set_sbus64); | ||
| 120 | 121 | ||
| 121 | /* INO number to IMAP register offset for SYSIO external IRQ's. | 122 | /* INO number to IMAP register offset for SYSIO external IRQ's. |
| 122 | * This should conform to both Sunfire/Wildfire server and Fusion | 123 | * This should conform to both Sunfire/Wildfire server and Fusion |
diff --git a/arch/sparc/kernel/setup_32.c b/arch/sparc/kernel/setup_32.c index c96c65d1b58b..998cadb4e7f2 100644 --- a/arch/sparc/kernel/setup_32.c +++ b/arch/sparc/kernel/setup_32.c | |||
| @@ -199,7 +199,9 @@ extern unsigned short ram_flags; | |||
| 199 | extern int root_mountflags; | 199 | extern int root_mountflags; |
| 200 | 200 | ||
| 201 | char reboot_command[COMMAND_LINE_SIZE]; | 201 | char reboot_command[COMMAND_LINE_SIZE]; |
| 202 | |||
| 202 | enum sparc_cpu sparc_cpu_model; | 203 | enum sparc_cpu sparc_cpu_model; |
| 204 | EXPORT_SYMBOL(sparc_cpu_model); | ||
| 203 | 205 | ||
| 204 | struct tt_entry *sparc_ttable; | 206 | struct tt_entry *sparc_ttable; |
| 205 | 207 | ||
| @@ -391,6 +393,7 @@ void sun_do_break(void) | |||
| 391 | 393 | ||
| 392 | prom_cmdline(); | 394 | prom_cmdline(); |
| 393 | } | 395 | } |
| 396 | EXPORT_SYMBOL(sun_do_break); | ||
| 394 | 397 | ||
| 395 | int stop_a_enabled = 1; | 398 | int stop_a_enabled = 1; |
| 396 | 399 | ||
diff --git a/arch/sparc/kernel/setup_64.c b/arch/sparc/kernel/setup_64.c index 555db7452ebe..49d061f4ae9d 100644 --- a/arch/sparc/kernel/setup_64.c +++ b/arch/sparc/kernel/setup_64.c | |||
| @@ -58,6 +58,7 @@ | |||
| 58 | * operations in asm/ns87303.h | 58 | * operations in asm/ns87303.h |
| 59 | */ | 59 | */ |
| 60 | DEFINE_SPINLOCK(ns87303_lock); | 60 | DEFINE_SPINLOCK(ns87303_lock); |
| 61 | EXPORT_SYMBOL(ns87303_lock); | ||
| 61 | 62 | ||
| 62 | struct screen_info screen_info = { | 63 | struct screen_info screen_info = { |
| 63 | 0, 0, /* orig-x, orig-y */ | 64 | 0, 0, /* orig-x, orig-y */ |
| @@ -425,5 +426,7 @@ void sun_do_break(void) | |||
| 425 | 426 | ||
| 426 | prom_cmdline(); | 427 | prom_cmdline(); |
| 427 | } | 428 | } |
| 429 | EXPORT_SYMBOL(sun_do_break); | ||
| 428 | 430 | ||
| 429 | int stop_a_enabled = 1; | 431 | int stop_a_enabled = 1; |
| 432 | EXPORT_SYMBOL(stop_a_enabled); | ||
diff --git a/arch/sparc/kernel/sparc_ksyms_32.c b/arch/sparc/kernel/sparc_ksyms_32.c index e1e97639231b..baeab8720237 100644 --- a/arch/sparc/kernel/sparc_ksyms_32.c +++ b/arch/sparc/kernel/sparc_ksyms_32.c | |||
| @@ -5,49 +5,14 @@ | |||
| 5 | * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be) | 5 | * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be) |
| 6 | */ | 6 | */ |
| 7 | 7 | ||
| 8 | /* Tell string.h we don't want memcpy etc. as cpp defines */ | ||
| 9 | #define EXPORT_SYMTAB_STROPS | ||
| 10 | #define PROMLIB_INTERNAL | ||
| 11 | |||
| 12 | #include <linux/module.h> | 8 | #include <linux/module.h> |
| 13 | #include <linux/init.h> | 9 | #include <linux/init.h> |
| 14 | #include <linux/smp.h> | ||
| 15 | #include <linux/types.h> | ||
| 16 | #include <linux/string.h> | ||
| 17 | #include <linux/sched.h> | ||
| 18 | #include <linux/interrupt.h> | ||
| 19 | #include <linux/in6.h> | ||
| 20 | #include <linux/spinlock.h> | ||
| 21 | #include <linux/mm.h> | ||
| 22 | #include <linux/syscalls.h> | ||
| 23 | #ifdef CONFIG_PCI | ||
| 24 | #include <linux/pci.h> | ||
| 25 | #endif | ||
| 26 | #include <linux/pm.h> | ||
| 27 | #ifdef CONFIG_HIGHMEM | ||
| 28 | #include <linux/highmem.h> | ||
| 29 | #endif | ||
| 30 | 10 | ||
| 31 | #include <asm/oplib.h> | ||
| 32 | #include <asm/delay.h> | ||
| 33 | #include <asm/system.h> | ||
| 34 | #include <asm/auxio.h> | ||
| 35 | #include <asm/pgtable.h> | 11 | #include <asm/pgtable.h> |
| 36 | #include <asm/io.h> | ||
| 37 | #include <asm/irq.h> | ||
| 38 | #include <asm/idprom.h> | ||
| 39 | #include <asm/head.h> | ||
| 40 | #include <asm/smp.h> | ||
| 41 | #include <asm/ptrace.h> | ||
| 42 | #include <asm/uaccess.h> | 12 | #include <asm/uaccess.h> |
| 43 | #include <asm/checksum.h> | 13 | #include <asm/delay.h> |
| 44 | #ifdef CONFIG_SBUS | 14 | #include <asm/head.h> |
| 45 | #include <asm/dma.h> | 15 | #include <asm/dma.h> |
| 46 | #endif | ||
| 47 | #include <asm/io-unit.h> | ||
| 48 | #include <asm/bug.h> | ||
| 49 | |||
| 50 | extern spinlock_t rtc_lock; | ||
| 51 | 16 | ||
| 52 | struct poll { | 17 | struct poll { |
| 53 | int fd; | 18 | int fd; |
| @@ -55,72 +20,15 @@ struct poll { | |||
| 55 | short revents; | 20 | short revents; |
| 56 | }; | 21 | }; |
| 57 | 22 | ||
| 58 | extern void (*__copy_1page)(void *, const void *); | 23 | /* from entry.S */ |
| 59 | extern void __memmove(void *, const void *, __kernel_size_t); | ||
| 60 | extern void (*bzero_1page)(void *); | ||
| 61 | extern void *__bzero(void *, size_t); | ||
| 62 | extern void *__memscan_zero(void *, size_t); | ||
| 63 | extern void *__memscan_generic(void *, int, size_t); | ||
| 64 | extern int __strncmp(const char *, const char *, __kernel_size_t); | ||
| 65 | |||
| 66 | extern int __ashrdi3(int, int); | ||
| 67 | extern int __ashldi3(int, int); | ||
| 68 | extern int __lshrdi3(int, int); | ||
| 69 | extern int __muldi3(int, int); | ||
| 70 | extern int __divdi3(int, int); | ||
| 71 | |||
| 72 | /* Private functions with odd calling conventions. */ | ||
| 73 | extern void ___atomic24_add(void); | ||
| 74 | extern void ___atomic24_sub(void); | ||
| 75 | extern void ___rw_read_enter(void); | ||
| 76 | extern void ___rw_read_try(void); | ||
| 77 | extern void ___rw_read_exit(void); | ||
| 78 | extern void ___rw_write_enter(void); | ||
| 79 | |||
| 80 | /* Alias functions whose names begin with "." and export the aliases. | ||
| 81 | * The module references will be fixed up by module_frob_arch_sections. | ||
| 82 | */ | ||
| 83 | extern int _Div(int, int); | ||
| 84 | extern int _Mul(int, int); | ||
| 85 | extern int _Rem(int, int); | ||
| 86 | extern unsigned _Udiv(unsigned, unsigned); | ||
| 87 | extern unsigned _Umul(unsigned, unsigned); | ||
| 88 | extern unsigned _Urem(unsigned, unsigned); | ||
| 89 | |||
| 90 | /* used by various drivers */ | ||
| 91 | EXPORT_SYMBOL(sparc_cpu_model); | ||
| 92 | EXPORT_SYMBOL(kernel_thread); | ||
| 93 | #ifdef CONFIG_SMP | ||
| 94 | // XXX find what uses (or used) these. AV: see asm/spinlock.h | ||
| 95 | EXPORT_SYMBOL(___rw_read_enter); | ||
| 96 | EXPORT_SYMBOL(___rw_read_try); | ||
| 97 | EXPORT_SYMBOL(___rw_read_exit); | ||
| 98 | EXPORT_SYMBOL(___rw_write_enter); | ||
| 99 | #endif | ||
| 100 | |||
| 101 | EXPORT_SYMBOL(sparc_valid_addr_bitmap); | ||
| 102 | EXPORT_SYMBOL(phys_base); | ||
| 103 | EXPORT_SYMBOL(pfn_base); | ||
| 104 | |||
| 105 | /* Atomic operations. */ | ||
| 106 | EXPORT_SYMBOL(___atomic24_add); | ||
| 107 | EXPORT_SYMBOL(___atomic24_sub); | ||
| 108 | |||
| 109 | /* Per-CPU information table */ | ||
| 110 | EXPORT_PER_CPU_SYMBOL(__cpu_data); | ||
| 111 | |||
| 112 | #ifdef CONFIG_SMP | ||
| 113 | /* IRQ implementation. */ | ||
| 114 | EXPORT_SYMBOL(synchronize_irq); | ||
| 115 | #endif | ||
| 116 | |||
| 117 | EXPORT_SYMBOL(__udelay); | 24 | EXPORT_SYMBOL(__udelay); |
| 118 | EXPORT_SYMBOL(__ndelay); | 25 | EXPORT_SYMBOL(__ndelay); |
| 119 | EXPORT_SYMBOL(rtc_lock); | ||
| 120 | EXPORT_SYMBOL(set_auxio); | ||
| 121 | EXPORT_SYMBOL(get_auxio); | ||
| 122 | EXPORT_SYMBOL(io_remap_pfn_range); | ||
| 123 | 26 | ||
| 27 | /* from head_32.S */ | ||
| 28 | EXPORT_SYMBOL(__ret_efault); | ||
| 29 | EXPORT_SYMBOL(empty_zero_page); | ||
| 30 | |||
| 31 | /* Defined using magic */ | ||
| 124 | #ifndef CONFIG_SMP | 32 | #ifndef CONFIG_SMP |
| 125 | EXPORT_SYMBOL(BTFIXUP_CALL(___xchg32)); | 33 | EXPORT_SYMBOL(BTFIXUP_CALL(___xchg32)); |
| 126 | #else | 34 | #else |
| @@ -132,122 +40,7 @@ EXPORT_SYMBOL(BTFIXUP_CALL(mmu_get_scsi_sgl)); | |||
| 132 | EXPORT_SYMBOL(BTFIXUP_CALL(mmu_get_scsi_one)); | 40 | EXPORT_SYMBOL(BTFIXUP_CALL(mmu_get_scsi_one)); |
| 133 | EXPORT_SYMBOL(BTFIXUP_CALL(mmu_release_scsi_sgl)); | 41 | EXPORT_SYMBOL(BTFIXUP_CALL(mmu_release_scsi_sgl)); |
| 134 | EXPORT_SYMBOL(BTFIXUP_CALL(mmu_release_scsi_one)); | 42 | EXPORT_SYMBOL(BTFIXUP_CALL(mmu_release_scsi_one)); |
| 135 | |||
| 136 | EXPORT_SYMBOL(BTFIXUP_CALL(pgprot_noncached)); | 43 | EXPORT_SYMBOL(BTFIXUP_CALL(pgprot_noncached)); |
| 137 | 44 | ||
| 138 | #ifdef CONFIG_SBUS | 45 | /* Exporting a symbol from /init/main.c */ |
| 139 | EXPORT_SYMBOL(sbus_set_sbus64); | ||
| 140 | #endif | ||
| 141 | #ifdef CONFIG_PCI | ||
| 142 | EXPORT_SYMBOL(insb); | ||
| 143 | EXPORT_SYMBOL(outsb); | ||
| 144 | EXPORT_SYMBOL(insw); | ||
| 145 | EXPORT_SYMBOL(outsw); | ||
| 146 | EXPORT_SYMBOL(insl); | ||
| 147 | EXPORT_SYMBOL(outsl); | ||
| 148 | EXPORT_SYMBOL(pci_alloc_consistent); | ||
| 149 | EXPORT_SYMBOL(pci_free_consistent); | ||
| 150 | EXPORT_SYMBOL(pci_map_single); | ||
| 151 | EXPORT_SYMBOL(pci_unmap_single); | ||
| 152 | EXPORT_SYMBOL(pci_dma_sync_single_for_cpu); | ||
| 153 | EXPORT_SYMBOL(pci_dma_sync_single_for_device); | ||
| 154 | EXPORT_SYMBOL(pci_dma_sync_sg_for_cpu); | ||
| 155 | EXPORT_SYMBOL(pci_dma_sync_sg_for_device); | ||
| 156 | EXPORT_SYMBOL(pci_map_sg); | ||
| 157 | EXPORT_SYMBOL(pci_unmap_sg); | ||
| 158 | EXPORT_SYMBOL(pci_map_page); | ||
| 159 | EXPORT_SYMBOL(pci_unmap_page); | ||
| 160 | /* Actually, ioremap/iounmap are not PCI specific. But it is ok for drivers. */ | ||
| 161 | EXPORT_SYMBOL(ioremap); | ||
| 162 | EXPORT_SYMBOL(iounmap); | ||
| 163 | #endif | ||
| 164 | |||
| 165 | /* in arch/sparc/mm/highmem.c */ | ||
| 166 | #ifdef CONFIG_HIGHMEM | ||
| 167 | EXPORT_SYMBOL(kmap_atomic); | ||
| 168 | EXPORT_SYMBOL(kunmap_atomic); | ||
| 169 | #endif | ||
| 170 | |||
| 171 | /* prom symbols */ | ||
| 172 | EXPORT_SYMBOL(idprom); | ||
| 173 | EXPORT_SYMBOL(prom_root_node); | ||
| 174 | EXPORT_SYMBOL(prom_getchild); | ||
| 175 | EXPORT_SYMBOL(prom_getsibling); | ||
| 176 | EXPORT_SYMBOL(prom_searchsiblings); | ||
| 177 | EXPORT_SYMBOL(prom_firstprop); | ||
| 178 | EXPORT_SYMBOL(prom_nextprop); | ||
| 179 | EXPORT_SYMBOL(prom_getproplen); | ||
| 180 | EXPORT_SYMBOL(prom_getproperty); | ||
| 181 | EXPORT_SYMBOL(prom_node_has_property); | ||
| 182 | EXPORT_SYMBOL(prom_setprop); | ||
| 183 | EXPORT_SYMBOL(saved_command_line); | 46 | EXPORT_SYMBOL(saved_command_line); |
| 184 | EXPORT_SYMBOL(prom_apply_obio_ranges); | ||
| 185 | EXPORT_SYMBOL(prom_feval); | ||
| 186 | EXPORT_SYMBOL(prom_getbool); | ||
| 187 | EXPORT_SYMBOL(prom_getstring); | ||
| 188 | EXPORT_SYMBOL(prom_getint); | ||
| 189 | EXPORT_SYMBOL(prom_getintdefault); | ||
| 190 | EXPORT_SYMBOL(prom_finddevice); | ||
| 191 | EXPORT_SYMBOL(romvec); | ||
| 192 | EXPORT_SYMBOL(__prom_getchild); | ||
| 193 | EXPORT_SYMBOL(__prom_getsibling); | ||
| 194 | |||
| 195 | /* sparc library symbols */ | ||
| 196 | EXPORT_SYMBOL(memscan); | ||
| 197 | EXPORT_SYMBOL(strlen); | ||
| 198 | EXPORT_SYMBOL(strncmp); | ||
| 199 | EXPORT_SYMBOL(page_kernel); | ||
| 200 | |||
| 201 | /* Special internal versions of library functions. */ | ||
| 202 | EXPORT_SYMBOL(__copy_1page); | ||
| 203 | EXPORT_SYMBOL(__memcpy); | ||
| 204 | EXPORT_SYMBOL(__memset); | ||
| 205 | EXPORT_SYMBOL(bzero_1page); | ||
| 206 | EXPORT_SYMBOL(__bzero); | ||
| 207 | EXPORT_SYMBOL(__memscan_zero); | ||
| 208 | EXPORT_SYMBOL(__memscan_generic); | ||
| 209 | EXPORT_SYMBOL(__strncmp); | ||
| 210 | EXPORT_SYMBOL(__memmove); | ||
| 211 | |||
| 212 | /* Moving data to/from userspace. */ | ||
| 213 | EXPORT_SYMBOL(__copy_user); | ||
| 214 | EXPORT_SYMBOL(__strncpy_from_user); | ||
| 215 | EXPORT_SYMBOL(__strnlen_user); | ||
| 216 | |||
| 217 | /* Networking helper routines. */ | ||
| 218 | EXPORT_SYMBOL(__csum_partial_copy_sparc_generic); | ||
| 219 | EXPORT_SYMBOL(csum_partial); | ||
| 220 | |||
| 221 | /* Cache flushing. */ | ||
| 222 | EXPORT_SYMBOL(sparc_flush_page_to_ram); | ||
| 223 | |||
| 224 | /* For when serial stuff is built as modules. */ | ||
| 225 | EXPORT_SYMBOL(sun_do_break); | ||
| 226 | |||
| 227 | EXPORT_SYMBOL(__ret_efault); | ||
| 228 | |||
| 229 | EXPORT_SYMBOL(memcmp); | ||
| 230 | EXPORT_SYMBOL(memcpy); | ||
| 231 | EXPORT_SYMBOL(memset); | ||
| 232 | EXPORT_SYMBOL(memmove); | ||
| 233 | EXPORT_SYMBOL(__ashrdi3); | ||
| 234 | EXPORT_SYMBOL(__ashldi3); | ||
| 235 | EXPORT_SYMBOL(__lshrdi3); | ||
| 236 | EXPORT_SYMBOL(__muldi3); | ||
| 237 | EXPORT_SYMBOL(__divdi3); | ||
| 238 | |||
| 239 | EXPORT_SYMBOL(_Rem); | ||
| 240 | EXPORT_SYMBOL(_Urem); | ||
| 241 | EXPORT_SYMBOL(_Mul); | ||
| 242 | EXPORT_SYMBOL(_Umul); | ||
| 243 | EXPORT_SYMBOL(_Div); | ||
| 244 | EXPORT_SYMBOL(_Udiv); | ||
| 245 | |||
| 246 | #ifdef CONFIG_DEBUG_BUGVERBOSE | ||
| 247 | EXPORT_SYMBOL(do_BUG); | ||
| 248 | #endif | ||
| 249 | |||
| 250 | /* Sun Power Management Idle Handler */ | ||
| 251 | EXPORT_SYMBOL(pm_idle); | ||
| 252 | |||
| 253 | EXPORT_SYMBOL(empty_zero_page); | ||
diff --git a/arch/sparc/kernel/sparc_ksyms_64.c b/arch/sparc/kernel/sparc_ksyms_64.c index 0133211ab634..da8f804feb49 100644 --- a/arch/sparc/kernel/sparc_ksyms_64.c +++ b/arch/sparc/kernel/sparc_ksyms_64.c | |||
| @@ -5,50 +5,16 @@ | |||
| 5 | * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz) | 5 | * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz) |
| 6 | */ | 6 | */ |
| 7 | 7 | ||
| 8 | /* Tell string.h we don't want memcpy etc. as cpp defines */ | ||
| 9 | #define EXPORT_SYMTAB_STROPS | ||
| 10 | #define PROMLIB_INTERNAL | ||
| 11 | |||
| 12 | #include <linux/module.h> | 8 | #include <linux/module.h> |
| 13 | #include <linux/types.h> | ||
| 14 | #include <linux/string.h> | ||
| 15 | #include <linux/sched.h> | ||
| 16 | #include <linux/in6.h> | ||
| 17 | #include <linux/pci.h> | 9 | #include <linux/pci.h> |
| 18 | #include <linux/interrupt.h> | ||
| 19 | #include <linux/fs_struct.h> | ||
| 20 | #include <linux/fs.h> | ||
| 21 | #include <linux/mm.h> | ||
| 22 | #include <linux/socket.h> | ||
| 23 | #include <linux/syscalls.h> | ||
| 24 | #include <linux/percpu.h> | ||
| 25 | #include <linux/init.h> | 10 | #include <linux/init.h> |
| 26 | #include <linux/rwsem.h> | ||
| 27 | #include <net/compat.h> | ||
| 28 | 11 | ||
| 29 | #include <asm/oplib.h> | 12 | #include <asm/spinlock.h> |
| 30 | #include <asm/system.h> | 13 | #include <asm/system.h> |
| 31 | #include <asm/auxio.h> | ||
| 32 | #include <asm/pgtable.h> | ||
| 33 | #include <asm/io.h> | ||
| 34 | #include <asm/irq.h> | ||
| 35 | #include <asm/idprom.h> | ||
| 36 | #include <asm/elf.h> | ||
| 37 | #include <asm/head.h> | ||
| 38 | #include <asm/smp.h> | ||
| 39 | #include <asm/ptrace.h> | ||
| 40 | #include <asm/uaccess.h> | ||
| 41 | #include <asm/checksum.h> | ||
| 42 | #include <asm/fpumacro.h> | ||
| 43 | #include <asm/pgalloc.h> | ||
| 44 | #include <asm/cacheflush.h> | ||
| 45 | #ifdef CONFIG_SBUS | ||
| 46 | #include <asm/dma.h> | ||
| 47 | #endif | ||
| 48 | #include <asm/ns87303.h> | ||
| 49 | #include <asm/timer.h> | ||
| 50 | #include <asm/cpudata.h> | 14 | #include <asm/cpudata.h> |
| 51 | #include <asm/ftrace.h> | 15 | #include <asm/uaccess.h> |
| 16 | #include <asm/spitfire.h> | ||
| 17 | #include <asm/oplib.h> | ||
| 52 | #include <asm/hypervisor.h> | 18 | #include <asm/hypervisor.h> |
| 53 | 19 | ||
| 54 | struct poll { | 20 | struct poll { |
| @@ -57,42 +23,6 @@ struct poll { | |||
| 57 | short revents; | 23 | short revents; |
| 58 | }; | 24 | }; |
| 59 | 25 | ||
| 60 | extern void die_if_kernel(char *str, struct pt_regs *regs); | ||
| 61 | extern pid_t kernel_thread(int (*fn)(void *), void * arg, unsigned long flags); | ||
| 62 | extern void *__bzero(void *, size_t); | ||
| 63 | extern void *__memscan_zero(void *, size_t); | ||
| 64 | extern void *__memscan_generic(void *, int, size_t); | ||
| 65 | extern __kernel_size_t strlen(const char *); | ||
| 66 | extern void sys_sigsuspend(void); | ||
| 67 | extern int compat_sys_ioctl(unsigned int fd, unsigned int cmd, u32 arg); | ||
| 68 | extern int (*handle_mathemu)(struct pt_regs *, struct fpustate *); | ||
| 69 | extern long sparc32_open(const char __user * filename, int flags, int mode); | ||
| 70 | extern int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long from, | ||
| 71 | unsigned long pfn, unsigned long size, pgprot_t prot); | ||
| 72 | |||
| 73 | extern int __ashrdi3(int, int); | ||
| 74 | |||
| 75 | extern int dump_fpu (struct pt_regs * regs, elf_fpregset_t * fpregs); | ||
| 76 | |||
| 77 | extern void xor_vis_2(unsigned long, unsigned long *, unsigned long *); | ||
| 78 | extern void xor_vis_3(unsigned long, unsigned long *, unsigned long *, | ||
| 79 | unsigned long *); | ||
| 80 | extern void xor_vis_4(unsigned long, unsigned long *, unsigned long *, | ||
| 81 | unsigned long *, unsigned long *); | ||
| 82 | extern void xor_vis_5(unsigned long, unsigned long *, unsigned long *, | ||
| 83 | unsigned long *, unsigned long *, unsigned long *); | ||
| 84 | |||
| 85 | extern void xor_niagara_2(unsigned long, unsigned long *, unsigned long *); | ||
| 86 | extern void xor_niagara_3(unsigned long, unsigned long *, unsigned long *, | ||
| 87 | unsigned long *); | ||
| 88 | extern void xor_niagara_4(unsigned long, unsigned long *, unsigned long *, | ||
| 89 | unsigned long *, unsigned long *); | ||
| 90 | extern void xor_niagara_5(unsigned long, unsigned long *, unsigned long *, | ||
| 91 | unsigned long *, unsigned long *, unsigned long *); | ||
| 92 | |||
| 93 | /* Per-CPU information table */ | ||
| 94 | EXPORT_PER_CPU_SYMBOL(__cpu_data); | ||
| 95 | |||
| 96 | /* used by various drivers */ | 26 | /* used by various drivers */ |
| 97 | #ifdef CONFIG_SMP | 27 | #ifdef CONFIG_SMP |
| 98 | /* Out of line rw-locking implementation. */ | 28 | /* Out of line rw-locking implementation. */ |
| @@ -103,68 +33,24 @@ EXPORT_SYMBOL(__write_unlock); | |||
| 103 | EXPORT_SYMBOL(__write_trylock); | 33 | EXPORT_SYMBOL(__write_trylock); |
| 104 | #endif /* CONFIG_SMP */ | 34 | #endif /* CONFIG_SMP */ |
| 105 | 35 | ||
| 106 | #ifdef CONFIG_MCOUNT | 36 | /* from helpers.S */ |
| 107 | EXPORT_SYMBOL(_mcount); | ||
| 108 | #endif | ||
| 109 | |||
| 110 | EXPORT_SYMBOL(sparc64_get_clock_tick); | ||
| 111 | |||
| 112 | /* RW semaphores */ | ||
| 113 | EXPORT_SYMBOL(__down_read); | ||
| 114 | EXPORT_SYMBOL(__down_read_trylock); | ||
| 115 | EXPORT_SYMBOL(__down_write); | ||
| 116 | EXPORT_SYMBOL(__down_write_trylock); | ||
| 117 | EXPORT_SYMBOL(__up_read); | ||
| 118 | EXPORT_SYMBOL(__up_write); | ||
| 119 | EXPORT_SYMBOL(__downgrade_write); | ||
| 120 | |||
| 121 | /* Atomic counter implementation. */ | ||
| 122 | EXPORT_SYMBOL(atomic_add); | ||
| 123 | EXPORT_SYMBOL(atomic_add_ret); | ||
| 124 | EXPORT_SYMBOL(atomic_sub); | ||
| 125 | EXPORT_SYMBOL(atomic_sub_ret); | ||
| 126 | EXPORT_SYMBOL(atomic64_add); | ||
| 127 | EXPORT_SYMBOL(atomic64_add_ret); | ||
| 128 | EXPORT_SYMBOL(atomic64_sub); | ||
| 129 | EXPORT_SYMBOL(atomic64_sub_ret); | ||
| 130 | |||
| 131 | /* Atomic bit operations. */ | ||
| 132 | EXPORT_SYMBOL(test_and_set_bit); | ||
| 133 | EXPORT_SYMBOL(test_and_clear_bit); | ||
| 134 | EXPORT_SYMBOL(test_and_change_bit); | ||
| 135 | EXPORT_SYMBOL(set_bit); | ||
| 136 | EXPORT_SYMBOL(clear_bit); | ||
| 137 | EXPORT_SYMBOL(change_bit); | ||
| 138 | |||
| 139 | EXPORT_SYMBOL(__flushw_user); | 37 | EXPORT_SYMBOL(__flushw_user); |
| 38 | EXPORT_SYMBOL_GPL(real_hard_smp_processor_id); | ||
| 140 | 39 | ||
| 40 | /* from head_64.S */ | ||
| 41 | EXPORT_SYMBOL(__ret_efault); | ||
| 141 | EXPORT_SYMBOL(tlb_type); | 42 | EXPORT_SYMBOL(tlb_type); |
| 142 | EXPORT_SYMBOL(sun4v_chip_type); | 43 | EXPORT_SYMBOL(sun4v_chip_type); |
| 143 | EXPORT_SYMBOL(get_fb_unmapped_area); | 44 | EXPORT_SYMBOL(prom_root_node); |
| 144 | EXPORT_SYMBOL(flush_icache_range); | ||
| 145 | |||
| 146 | EXPORT_SYMBOL(flush_dcache_page); | ||
| 147 | #ifdef DCACHE_ALIASING_POSSIBLE | ||
| 148 | EXPORT_SYMBOL(__flush_dcache_range); | ||
| 149 | #endif | ||
| 150 | 45 | ||
| 46 | /* from hvcalls.S */ | ||
| 151 | EXPORT_SYMBOL(sun4v_niagara_getperf); | 47 | EXPORT_SYMBOL(sun4v_niagara_getperf); |
| 152 | EXPORT_SYMBOL(sun4v_niagara_setperf); | 48 | EXPORT_SYMBOL(sun4v_niagara_setperf); |
| 153 | EXPORT_SYMBOL(sun4v_niagara2_getperf); | 49 | EXPORT_SYMBOL(sun4v_niagara2_getperf); |
| 154 | EXPORT_SYMBOL(sun4v_niagara2_setperf); | 50 | EXPORT_SYMBOL(sun4v_niagara2_setperf); |
| 155 | 51 | ||
| 156 | EXPORT_SYMBOL(auxio_set_led); | ||
| 157 | EXPORT_SYMBOL(auxio_set_lte); | ||
| 158 | #ifdef CONFIG_SBUS | ||
| 159 | EXPORT_SYMBOL(sbus_set_sbus64); | ||
| 160 | #endif | ||
| 161 | EXPORT_SYMBOL(outsb); | ||
| 162 | EXPORT_SYMBOL(outsw); | ||
| 163 | EXPORT_SYMBOL(outsl); | ||
| 164 | EXPORT_SYMBOL(insb); | ||
| 165 | EXPORT_SYMBOL(insw); | ||
| 166 | EXPORT_SYMBOL(insl); | ||
| 167 | #ifdef CONFIG_PCI | 52 | #ifdef CONFIG_PCI |
| 53 | /* inline functions in asm/pci_64.h */ | ||
| 168 | EXPORT_SYMBOL(pci_alloc_consistent); | 54 | EXPORT_SYMBOL(pci_alloc_consistent); |
| 169 | EXPORT_SYMBOL(pci_free_consistent); | 55 | EXPORT_SYMBOL(pci_free_consistent); |
| 170 | EXPORT_SYMBOL(pci_map_single); | 56 | EXPORT_SYMBOL(pci_map_single); |
| @@ -173,112 +59,7 @@ EXPORT_SYMBOL(pci_map_sg); | |||
| 173 | EXPORT_SYMBOL(pci_unmap_sg); | 59 | EXPORT_SYMBOL(pci_unmap_sg); |
| 174 | EXPORT_SYMBOL(pci_dma_sync_single_for_cpu); | 60 | EXPORT_SYMBOL(pci_dma_sync_single_for_cpu); |
| 175 | EXPORT_SYMBOL(pci_dma_sync_sg_for_cpu); | 61 | EXPORT_SYMBOL(pci_dma_sync_sg_for_cpu); |
| 176 | EXPORT_SYMBOL(pci_dma_supported); | ||
| 177 | #endif | 62 | #endif |
| 178 | 63 | ||
| 179 | /* I/O device mmaping on Sparc64. */ | 64 | /* Exporting a symbol from /init/main.c */ |
| 180 | EXPORT_SYMBOL(io_remap_pfn_range); | ||
| 181 | |||
| 182 | EXPORT_SYMBOL(dump_fpu); | ||
| 183 | |||
| 184 | /* math-emu wants this */ | ||
| 185 | EXPORT_SYMBOL(die_if_kernel); | ||
| 186 | |||
| 187 | /* Kernel thread creation. */ | ||
| 188 | EXPORT_SYMBOL(kernel_thread); | ||
| 189 | |||
| 190 | /* prom symbols */ | ||
| 191 | EXPORT_SYMBOL(idprom); | ||
| 192 | EXPORT_SYMBOL(prom_root_node); | ||
| 193 | EXPORT_SYMBOL(prom_getchild); | ||
| 194 | EXPORT_SYMBOL(prom_getsibling); | ||
| 195 | EXPORT_SYMBOL(prom_searchsiblings); | ||
| 196 | EXPORT_SYMBOL(prom_firstprop); | ||
| 197 | EXPORT_SYMBOL(prom_nextprop); | ||
| 198 | EXPORT_SYMBOL(prom_getproplen); | ||
| 199 | EXPORT_SYMBOL(prom_getproperty); | ||
| 200 | EXPORT_SYMBOL(prom_node_has_property); | ||
| 201 | EXPORT_SYMBOL(prom_setprop); | ||
| 202 | EXPORT_SYMBOL(saved_command_line); | 65 | EXPORT_SYMBOL(saved_command_line); |
| 203 | EXPORT_SYMBOL(prom_finddevice); | ||
| 204 | EXPORT_SYMBOL(prom_feval); | ||
| 205 | EXPORT_SYMBOL(prom_getbool); | ||
| 206 | EXPORT_SYMBOL(prom_getstring); | ||
| 207 | EXPORT_SYMBOL(prom_getint); | ||
| 208 | EXPORT_SYMBOL(prom_getintdefault); | ||
| 209 | EXPORT_SYMBOL(__prom_getchild); | ||
| 210 | EXPORT_SYMBOL(__prom_getsibling); | ||
| 211 | |||
| 212 | /* sparc library symbols */ | ||
| 213 | EXPORT_SYMBOL(strlen); | ||
| 214 | EXPORT_SYMBOL(__strlen_user); | ||
| 215 | EXPORT_SYMBOL(__strnlen_user); | ||
| 216 | |||
| 217 | /* Special internal versions of library functions. */ | ||
| 218 | EXPORT_SYMBOL(_clear_page); | ||
| 219 | EXPORT_SYMBOL(clear_user_page); | ||
| 220 | EXPORT_SYMBOL(copy_user_page); | ||
| 221 | EXPORT_SYMBOL(__bzero); | ||
| 222 | EXPORT_SYMBOL(__memscan_zero); | ||
| 223 | EXPORT_SYMBOL(__memscan_generic); | ||
| 224 | EXPORT_SYMBOL(__memset); | ||
| 225 | |||
| 226 | EXPORT_SYMBOL(csum_partial); | ||
| 227 | EXPORT_SYMBOL(csum_partial_copy_nocheck); | ||
| 228 | EXPORT_SYMBOL(__csum_partial_copy_from_user); | ||
| 229 | EXPORT_SYMBOL(__csum_partial_copy_to_user); | ||
| 230 | EXPORT_SYMBOL(ip_fast_csum); | ||
| 231 | |||
| 232 | /* Moving data to/from/in userspace. */ | ||
| 233 | EXPORT_SYMBOL(___copy_to_user); | ||
| 234 | EXPORT_SYMBOL(___copy_from_user); | ||
| 235 | EXPORT_SYMBOL(___copy_in_user); | ||
| 236 | EXPORT_SYMBOL(copy_to_user_fixup); | ||
| 237 | EXPORT_SYMBOL(copy_from_user_fixup); | ||
| 238 | EXPORT_SYMBOL(copy_in_user_fixup); | ||
| 239 | EXPORT_SYMBOL(__strncpy_from_user); | ||
| 240 | EXPORT_SYMBOL(__clear_user); | ||
| 241 | |||
| 242 | /* Various address conversion macros use this. */ | ||
| 243 | EXPORT_SYMBOL(sparc64_valid_addr_bitmap); | ||
| 244 | |||
| 245 | /* No version information on this, heavily used in inline asm, | ||
| 246 | * and will always be 'void __ret_efault(void)'. | ||
| 247 | */ | ||
| 248 | EXPORT_SYMBOL(__ret_efault); | ||
| 249 | |||
| 250 | /* No version information on these, as gcc produces such symbols. */ | ||
| 251 | EXPORT_SYMBOL(memcmp); | ||
| 252 | EXPORT_SYMBOL(memcpy); | ||
| 253 | EXPORT_SYMBOL(memset); | ||
| 254 | EXPORT_SYMBOL(memmove); | ||
| 255 | EXPORT_SYMBOL(strncmp); | ||
| 256 | |||
| 257 | void VISenter(void); | ||
| 258 | /* RAID code needs this */ | ||
| 259 | EXPORT_SYMBOL(VISenter); | ||
| 260 | |||
| 261 | /* for input/keybdev */ | ||
| 262 | EXPORT_SYMBOL(sun_do_break); | ||
| 263 | EXPORT_SYMBOL(stop_a_enabled); | ||
| 264 | |||
| 265 | #ifdef CONFIG_DEBUG_BUGVERBOSE | ||
| 266 | EXPORT_SYMBOL(do_BUG); | ||
| 267 | #endif | ||
| 268 | |||
| 269 | /* for ns8703 */ | ||
| 270 | EXPORT_SYMBOL(ns87303_lock); | ||
| 271 | |||
| 272 | EXPORT_SYMBOL(tick_ops); | ||
| 273 | |||
| 274 | EXPORT_SYMBOL(xor_vis_2); | ||
| 275 | EXPORT_SYMBOL(xor_vis_3); | ||
| 276 | EXPORT_SYMBOL(xor_vis_4); | ||
| 277 | EXPORT_SYMBOL(xor_vis_5); | ||
| 278 | |||
| 279 | EXPORT_SYMBOL(xor_niagara_2); | ||
| 280 | EXPORT_SYMBOL(xor_niagara_3); | ||
| 281 | EXPORT_SYMBOL(xor_niagara_4); | ||
| 282 | EXPORT_SYMBOL(xor_niagara_5); | ||
| 283 | |||
| 284 | EXPORT_SYMBOL_GPL(real_hard_smp_processor_id); | ||
diff --git a/arch/sparc/kernel/sun4d_smp.c b/arch/sparc/kernel/sun4d_smp.c index 16ab0cb731c5..50afaed99c8a 100644 --- a/arch/sparc/kernel/sun4d_smp.c +++ b/arch/sparc/kernel/sun4d_smp.c | |||
| @@ -60,7 +60,7 @@ extern int __smp4d_processor_id(void); | |||
| 60 | #define SMP_PRINTK(x) | 60 | #define SMP_PRINTK(x) |
| 61 | #endif | 61 | #endif |
| 62 | 62 | ||
| 63 | static inline unsigned long swap(volatile unsigned long *ptr, unsigned long val) | 63 | static inline unsigned long sun4d_swap(volatile unsigned long *ptr, unsigned long val) |
| 64 | { | 64 | { |
| 65 | __asm__ __volatile__("swap [%1], %0\n\t" : | 65 | __asm__ __volatile__("swap [%1], %0\n\t" : |
| 66 | "=&r" (val), "=&r" (ptr) : | 66 | "=&r" (val), "=&r" (ptr) : |
| @@ -115,7 +115,7 @@ void __cpuinit smp4d_callin(void) | |||
| 115 | local_flush_tlb_all(); | 115 | local_flush_tlb_all(); |
| 116 | 116 | ||
| 117 | /* Allow master to continue. */ | 117 | /* Allow master to continue. */ |
| 118 | swap((unsigned long *)&cpu_callin_map[cpuid], 1); | 118 | sun4d_swap((unsigned long *)&cpu_callin_map[cpuid], 1); |
| 119 | local_flush_cache_all(); | 119 | local_flush_cache_all(); |
| 120 | local_flush_tlb_all(); | 120 | local_flush_tlb_all(); |
| 121 | 121 | ||
diff --git a/arch/sparc/kernel/sys_sparc_64.c b/arch/sparc/kernel/sys_sparc_64.c index 39749e32dc7e..09058fc39e73 100644 --- a/arch/sparc/kernel/sys_sparc_64.c +++ b/arch/sparc/kernel/sys_sparc_64.c | |||
| @@ -23,6 +23,7 @@ | |||
| 23 | #include <linux/ipc.h> | 23 | #include <linux/ipc.h> |
| 24 | #include <linux/personality.h> | 24 | #include <linux/personality.h> |
| 25 | #include <linux/random.h> | 25 | #include <linux/random.h> |
| 26 | #include <linux/module.h> | ||
| 26 | 27 | ||
| 27 | #include <asm/uaccess.h> | 28 | #include <asm/uaccess.h> |
| 28 | #include <asm/utrap.h> | 29 | #include <asm/utrap.h> |
| @@ -354,6 +355,7 @@ unsigned long get_fb_unmapped_area(struct file *filp, unsigned long orig_addr, u | |||
| 354 | 355 | ||
| 355 | return addr; | 356 | return addr; |
| 356 | } | 357 | } |
| 358 | EXPORT_SYMBOL(get_fb_unmapped_area); | ||
| 357 | 359 | ||
| 358 | /* Essentially the same as PowerPC... */ | 360 | /* Essentially the same as PowerPC... */ |
| 359 | void arch_pick_mmap_layout(struct mm_struct *mm) | 361 | void arch_pick_mmap_layout(struct mm_struct *mm) |
diff --git a/arch/sparc/kernel/time_32.c b/arch/sparc/kernel/time_32.c index 00f7383c7657..614ac7b4a9dd 100644 --- a/arch/sparc/kernel/time_32.c +++ b/arch/sparc/kernel/time_32.c | |||
| @@ -48,6 +48,8 @@ | |||
| 48 | #include "irq.h" | 48 | #include "irq.h" |
| 49 | 49 | ||
| 50 | DEFINE_SPINLOCK(rtc_lock); | 50 | DEFINE_SPINLOCK(rtc_lock); |
| 51 | EXPORT_SYMBOL(rtc_lock); | ||
| 52 | |||
| 51 | static int set_rtc_mmss(unsigned long); | 53 | static int set_rtc_mmss(unsigned long); |
| 52 | static int sbus_do_settimeofday(struct timespec *tv); | 54 | static int sbus_do_settimeofday(struct timespec *tv); |
| 53 | 55 | ||
diff --git a/arch/sparc/kernel/time_64.c b/arch/sparc/kernel/time_64.c index 54405d362148..2db3c2229b95 100644 --- a/arch/sparc/kernel/time_64.c +++ b/arch/sparc/kernel/time_64.c | |||
| @@ -176,6 +176,7 @@ static struct sparc64_tick_ops tick_operations __read_mostly = { | |||
| 176 | }; | 176 | }; |
| 177 | 177 | ||
| 178 | struct sparc64_tick_ops *tick_ops __read_mostly = &tick_operations; | 178 | struct sparc64_tick_ops *tick_ops __read_mostly = &tick_operations; |
| 179 | EXPORT_SYMBOL(tick_ops); | ||
| 179 | 180 | ||
| 180 | static void stick_disable_irq(void) | 181 | static void stick_disable_irq(void) |
| 181 | { | 182 | { |
| @@ -639,6 +640,7 @@ unsigned long sparc64_get_clock_tick(unsigned int cpu) | |||
| 639 | return ft->clock_tick_ref; | 640 | return ft->clock_tick_ref; |
| 640 | return cpu_data(cpu).clock_tick; | 641 | return cpu_data(cpu).clock_tick; |
| 641 | } | 642 | } |
| 643 | EXPORT_SYMBOL(sparc64_get_clock_tick); | ||
| 642 | 644 | ||
| 643 | #ifdef CONFIG_CPU_FREQ | 645 | #ifdef CONFIG_CPU_FREQ |
| 644 | 646 | ||
diff --git a/arch/sparc/kernel/traps_32.c b/arch/sparc/kernel/traps_32.c index 213645be6e92..358283341b47 100644 --- a/arch/sparc/kernel/traps_32.c +++ b/arch/sparc/kernel/traps_32.c | |||
| @@ -424,6 +424,7 @@ void do_BUG(const char *file, int line) | |||
| 424 | // bust_spinlocks(1); XXX Not in our original BUG() | 424 | // bust_spinlocks(1); XXX Not in our original BUG() |
| 425 | printk("kernel BUG at %s:%d!\n", file, line); | 425 | printk("kernel BUG at %s:%d!\n", file, line); |
| 426 | } | 426 | } |
| 427 | EXPORT_SYMBOL(do_BUG); | ||
| 427 | #endif | 428 | #endif |
| 428 | 429 | ||
| 429 | /* Since we have our mappings set up, on multiprocessors we can spin them | 430 | /* Since we have our mappings set up, on multiprocessors we can spin them |
diff --git a/arch/sparc/kernel/traps_64.c b/arch/sparc/kernel/traps_64.c index bca3b4e09c41..c2d153d46586 100644 --- a/arch/sparc/kernel/traps_64.c +++ b/arch/sparc/kernel/traps_64.c | |||
| @@ -128,6 +128,7 @@ void do_BUG(const char *file, int line) | |||
| 128 | bust_spinlocks(1); | 128 | bust_spinlocks(1); |
| 129 | printk("kernel BUG at %s:%d!\n", file, line); | 129 | printk("kernel BUG at %s:%d!\n", file, line); |
| 130 | } | 130 | } |
| 131 | EXPORT_SYMBOL(do_BUG); | ||
| 131 | #endif | 132 | #endif |
| 132 | 133 | ||
| 133 | static DEFINE_SPINLOCK(dimm_handler_lock); | 134 | static DEFINE_SPINLOCK(dimm_handler_lock); |
| @@ -2261,6 +2262,7 @@ void die_if_kernel(char *str, struct pt_regs *regs) | |||
| 2261 | do_exit(SIGKILL); | 2262 | do_exit(SIGKILL); |
| 2262 | do_exit(SIGSEGV); | 2263 | do_exit(SIGSEGV); |
| 2263 | } | 2264 | } |
| 2265 | EXPORT_SYMBOL(die_if_kernel); | ||
| 2264 | 2266 | ||
| 2265 | #define VIS_OPCODE_MASK ((0x3 << 30) | (0x3f << 19)) | 2267 | #define VIS_OPCODE_MASK ((0x3 << 30) | (0x3f << 19)) |
| 2266 | #define VIS_OPCODE_VAL ((0x2 << 30) | (0x36 << 19)) | 2268 | #define VIS_OPCODE_VAL ((0x2 << 30) | (0x36 << 19)) |
diff --git a/arch/sparc/kernel/unaligned_64.c b/arch/sparc/kernel/unaligned_64.c index f164d5a850f9..379209982a07 100644 --- a/arch/sparc/kernel/unaligned_64.c +++ b/arch/sparc/kernel/unaligned_64.c | |||
| @@ -589,7 +589,6 @@ void handle_lddfmna(struct pt_regs *regs, unsigned long sfar, unsigned long sfsr | |||
| 589 | unsigned long pc = regs->tpc; | 589 | unsigned long pc = regs->tpc; |
| 590 | unsigned long tstate = regs->tstate; | 590 | unsigned long tstate = regs->tstate; |
| 591 | u32 insn; | 591 | u32 insn; |
| 592 | u32 first, second; | ||
| 593 | u64 value; | 592 | u64 value; |
| 594 | u8 freg; | 593 | u8 freg; |
| 595 | int flag; | 594 | int flag; |
| @@ -601,19 +600,20 @@ void handle_lddfmna(struct pt_regs *regs, unsigned long sfar, unsigned long sfsr | |||
| 601 | pc = (u32)pc; | 600 | pc = (u32)pc; |
| 602 | if (get_user(insn, (u32 __user *) pc) != -EFAULT) { | 601 | if (get_user(insn, (u32 __user *) pc) != -EFAULT) { |
| 603 | int asi = decode_asi(insn, regs); | 602 | int asi = decode_asi(insn, regs); |
| 603 | u32 first, second; | ||
| 604 | int err; | 604 | int err; |
| 605 | 605 | ||
| 606 | if ((asi > ASI_SNFL) || | 606 | if ((asi > ASI_SNFL) || |
| 607 | (asi < ASI_P)) | 607 | (asi < ASI_P)) |
| 608 | goto daex; | 608 | goto daex; |
| 609 | first = second = 0; | ||
| 609 | err = get_user(first, (u32 __user *)sfar); | 610 | err = get_user(first, (u32 __user *)sfar); |
| 610 | if (!err) | 611 | if (!err) |
| 611 | err = get_user(second, (u32 __user *)(sfar + 4)); | 612 | err = get_user(second, (u32 __user *)(sfar + 4)); |
| 612 | if (err) { | 613 | if (err) { |
| 613 | if (asi & 0x2) /* NF */ { | 614 | if (!(asi & 0x2)) |
| 614 | first = 0; second = 0; | ||
| 615 | } else | ||
| 616 | goto daex; | 615 | goto daex; |
| 616 | first = second = 0; | ||
| 617 | } | 617 | } |
| 618 | save_and_clear_fpu(); | 618 | save_and_clear_fpu(); |
| 619 | freg = ((insn >> 25) & 0x1e) | ((insn >> 20) & 0x20); | 619 | freg = ((insn >> 25) & 0x1e) | ((insn >> 20) & 0x20); |
diff --git a/arch/sparc/lib/Makefile b/arch/sparc/lib/Makefile index 375016e19144..273fc85269fc 100644 --- a/arch/sparc/lib/Makefile +++ b/arch/sparc/lib/Makefile | |||
| @@ -42,3 +42,4 @@ lib-$(CONFIG_SPARC64) += mcount.o ipcsum.o xor.o | |||
| 42 | 42 | ||
| 43 | obj-y += iomap.o | 43 | obj-y += iomap.o |
| 44 | obj-$(CONFIG_SPARC32) += atomic32.o | 44 | obj-$(CONFIG_SPARC32) += atomic32.o |
| 45 | obj-y += ksyms.o | ||
diff --git a/arch/sparc/lib/PeeCeeI.c b/arch/sparc/lib/PeeCeeI.c index 46053e6ddd7b..6529f8657597 100644 --- a/arch/sparc/lib/PeeCeeI.c +++ b/arch/sparc/lib/PeeCeeI.c | |||
| @@ -4,6 +4,8 @@ | |||
| 4 | * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu) | 4 | * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu) |
| 5 | */ | 5 | */ |
| 6 | 6 | ||
| 7 | #include <linux/module.h> | ||
| 8 | |||
| 7 | #include <asm/io.h> | 9 | #include <asm/io.h> |
| 8 | #include <asm/byteorder.h> | 10 | #include <asm/byteorder.h> |
| 9 | 11 | ||
| @@ -15,6 +17,7 @@ void outsb(unsigned long __addr, const void *src, unsigned long count) | |||
| 15 | while (count--) | 17 | while (count--) |
| 16 | outb(*p++, addr); | 18 | outb(*p++, addr); |
| 17 | } | 19 | } |
| 20 | EXPORT_SYMBOL(outsb); | ||
| 18 | 21 | ||
| 19 | void outsw(unsigned long __addr, const void *src, unsigned long count) | 22 | void outsw(unsigned long __addr, const void *src, unsigned long count) |
| 20 | { | 23 | { |
| @@ -25,6 +28,7 @@ void outsw(unsigned long __addr, const void *src, unsigned long count) | |||
| 25 | src += sizeof(u16); | 28 | src += sizeof(u16); |
| 26 | } | 29 | } |
| 27 | } | 30 | } |
| 31 | EXPORT_SYMBOL(outsw); | ||
| 28 | 32 | ||
| 29 | void outsl(unsigned long __addr, const void *src, unsigned long count) | 33 | void outsl(unsigned long __addr, const void *src, unsigned long count) |
| 30 | { | 34 | { |
| @@ -78,6 +82,7 @@ void outsl(unsigned long __addr, const void *src, unsigned long count) | |||
| 78 | break; | 82 | break; |
| 79 | } | 83 | } |
| 80 | } | 84 | } |
| 85 | EXPORT_SYMBOL(outsl); | ||
| 81 | 86 | ||
| 82 | void insb(unsigned long __addr, void *dst, unsigned long count) | 87 | void insb(unsigned long __addr, void *dst, unsigned long count) |
| 83 | { | 88 | { |
| @@ -105,6 +110,7 @@ void insb(unsigned long __addr, void *dst, unsigned long count) | |||
| 105 | *pb++ = inb(addr); | 110 | *pb++ = inb(addr); |
| 106 | } | 111 | } |
| 107 | } | 112 | } |
| 113 | EXPORT_SYMBOL(insb); | ||
| 108 | 114 | ||
| 109 | void insw(unsigned long __addr, void *dst, unsigned long count) | 115 | void insw(unsigned long __addr, void *dst, unsigned long count) |
| 110 | { | 116 | { |
| @@ -132,6 +138,7 @@ void insw(unsigned long __addr, void *dst, unsigned long count) | |||
| 132 | *ps = le16_to_cpu(inw(addr)); | 138 | *ps = le16_to_cpu(inw(addr)); |
| 133 | } | 139 | } |
| 134 | } | 140 | } |
| 141 | EXPORT_SYMBOL(insw); | ||
| 135 | 142 | ||
| 136 | void insl(unsigned long __addr, void *dst, unsigned long count) | 143 | void insl(unsigned long __addr, void *dst, unsigned long count) |
| 137 | { | 144 | { |
| @@ -200,4 +207,5 @@ void insl(unsigned long __addr, void *dst, unsigned long count) | |||
| 200 | } | 207 | } |
| 201 | } | 208 | } |
| 202 | } | 209 | } |
| 210 | EXPORT_SYMBOL(insl); | ||
| 203 | 211 | ||
diff --git a/arch/sparc/lib/ksyms.c b/arch/sparc/lib/ksyms.c new file mode 100644 index 000000000000..704b12668388 --- /dev/null +++ b/arch/sparc/lib/ksyms.c | |||
| @@ -0,0 +1,196 @@ | |||
| 1 | /* | ||
| 2 | * Export of symbols defined in assembler | ||
| 3 | */ | ||
| 4 | |||
| 5 | /* Tell string.h we don't want memcpy etc. as cpp defines */ | ||
| 6 | #define EXPORT_SYMTAB_STROPS | ||
| 7 | |||
| 8 | #include <linux/module.h> | ||
| 9 | #include <linux/string.h> | ||
| 10 | #include <linux/types.h> | ||
| 11 | |||
| 12 | #include <asm/checksum.h> | ||
| 13 | #include <asm/uaccess.h> | ||
| 14 | #include <asm/ftrace.h> | ||
| 15 | |||
| 16 | /* string functions */ | ||
| 17 | EXPORT_SYMBOL(strlen); | ||
| 18 | EXPORT_SYMBOL(__strlen_user); | ||
| 19 | EXPORT_SYMBOL(__strnlen_user); | ||
| 20 | EXPORT_SYMBOL(strncmp); | ||
| 21 | |||
| 22 | /* mem* functions */ | ||
| 23 | extern void *__memscan_zero(void *, size_t); | ||
| 24 | extern void *__memscan_generic(void *, int, size_t); | ||
| 25 | extern void *__bzero(void *, size_t); | ||
| 26 | |||
| 27 | EXPORT_SYMBOL(memscan); | ||
| 28 | EXPORT_SYMBOL(__memscan_zero); | ||
| 29 | EXPORT_SYMBOL(__memscan_generic); | ||
| 30 | EXPORT_SYMBOL(memcmp); | ||
| 31 | EXPORT_SYMBOL(memcpy); | ||
| 32 | EXPORT_SYMBOL(memset); | ||
| 33 | EXPORT_SYMBOL(__memset); | ||
| 34 | EXPORT_SYMBOL(memmove); | ||
| 35 | EXPORT_SYMBOL(__bzero); | ||
| 36 | |||
| 37 | /* Moving data to/from/in userspace. */ | ||
| 38 | EXPORT_SYMBOL(__strncpy_from_user); | ||
| 39 | |||
| 40 | /* Networking helper routines. */ | ||
| 41 | EXPORT_SYMBOL(csum_partial); | ||
| 42 | |||
| 43 | #ifdef CONFIG_MCOUNT | ||
| 44 | EXPORT_SYMBOL(_mcount); | ||
| 45 | #endif | ||
| 46 | |||
| 47 | /* | ||
| 48 | * sparc | ||
| 49 | */ | ||
| 50 | #ifdef CONFIG_SPARC32 | ||
| 51 | extern int __ashrdi3(int, int); | ||
| 52 | extern int __ashldi3(int, int); | ||
| 53 | extern int __lshrdi3(int, int); | ||
| 54 | extern int __muldi3(int, int); | ||
| 55 | extern int __divdi3(int, int); | ||
| 56 | |||
| 57 | extern void (*__copy_1page)(void *, const void *); | ||
| 58 | extern void (*bzero_1page)(void *); | ||
| 59 | |||
| 60 | extern int __strncmp(const char *, const char *, __kernel_size_t); | ||
| 61 | |||
| 62 | extern void ___rw_read_enter(void); | ||
| 63 | extern void ___rw_read_try(void); | ||
| 64 | extern void ___rw_read_exit(void); | ||
| 65 | extern void ___rw_write_enter(void); | ||
| 66 | extern void ___atomic24_add(void); | ||
| 67 | extern void ___atomic24_sub(void); | ||
| 68 | |||
| 69 | /* Alias functions whose names begin with "." and export the aliases. | ||
| 70 | * The module references will be fixed up by module_frob_arch_sections. | ||
| 71 | */ | ||
| 72 | extern int _Div(int, int); | ||
| 73 | extern int _Mul(int, int); | ||
| 74 | extern int _Rem(int, int); | ||
| 75 | extern unsigned _Udiv(unsigned, unsigned); | ||
| 76 | extern unsigned _Umul(unsigned, unsigned); | ||
| 77 | extern unsigned _Urem(unsigned, unsigned); | ||
| 78 | |||
| 79 | /* Networking helper routines. */ | ||
| 80 | EXPORT_SYMBOL(__csum_partial_copy_sparc_generic); | ||
| 81 | |||
| 82 | /* Special internal versions of library functions. */ | ||
| 83 | EXPORT_SYMBOL(__copy_1page); | ||
| 84 | EXPORT_SYMBOL(__memcpy); | ||
| 85 | EXPORT_SYMBOL(__memmove); | ||
| 86 | EXPORT_SYMBOL(bzero_1page); | ||
| 87 | |||
| 88 | /* string functions */ | ||
| 89 | EXPORT_SYMBOL(__strncmp); | ||
| 90 | |||
| 91 | /* Moving data to/from/in userspace. */ | ||
| 92 | EXPORT_SYMBOL(__copy_user); | ||
| 93 | |||
| 94 | /* Used by asm/spinlock.h */ | ||
| 95 | #ifdef CONFIG_SMP | ||
| 96 | EXPORT_SYMBOL(___rw_read_enter); | ||
| 97 | EXPORT_SYMBOL(___rw_read_try); | ||
| 98 | EXPORT_SYMBOL(___rw_read_exit); | ||
| 99 | EXPORT_SYMBOL(___rw_write_enter); | ||
| 100 | #endif | ||
| 101 | |||
| 102 | /* Atomic operations. */ | ||
| 103 | EXPORT_SYMBOL(___atomic24_add); | ||
| 104 | EXPORT_SYMBOL(___atomic24_sub); | ||
| 105 | |||
| 106 | EXPORT_SYMBOL(__ashrdi3); | ||
| 107 | EXPORT_SYMBOL(__ashldi3); | ||
| 108 | EXPORT_SYMBOL(__lshrdi3); | ||
| 109 | EXPORT_SYMBOL(__muldi3); | ||
| 110 | EXPORT_SYMBOL(__divdi3); | ||
| 111 | |||
| 112 | EXPORT_SYMBOL(_Rem); | ||
| 113 | EXPORT_SYMBOL(_Urem); | ||
| 114 | EXPORT_SYMBOL(_Mul); | ||
| 115 | EXPORT_SYMBOL(_Umul); | ||
| 116 | EXPORT_SYMBOL(_Div); | ||
| 117 | EXPORT_SYMBOL(_Udiv); | ||
| 118 | #endif | ||
| 119 | |||
| 120 | /* | ||
| 121 | * sparc64 | ||
| 122 | */ | ||
| 123 | #ifdef CONFIG_SPARC64 | ||
| 124 | /* Networking helper routines. */ | ||
| 125 | EXPORT_SYMBOL(csum_partial_copy_nocheck); | ||
| 126 | EXPORT_SYMBOL(__csum_partial_copy_from_user); | ||
| 127 | EXPORT_SYMBOL(__csum_partial_copy_to_user); | ||
| 128 | EXPORT_SYMBOL(ip_fast_csum); | ||
| 129 | |||
| 130 | /* Moving data to/from/in userspace. */ | ||
| 131 | EXPORT_SYMBOL(___copy_to_user); | ||
| 132 | EXPORT_SYMBOL(___copy_from_user); | ||
| 133 | EXPORT_SYMBOL(___copy_in_user); | ||
| 134 | EXPORT_SYMBOL(__clear_user); | ||
| 135 | |||
| 136 | /* RW semaphores */ | ||
| 137 | EXPORT_SYMBOL(__down_read); | ||
| 138 | EXPORT_SYMBOL(__down_read_trylock); | ||
| 139 | EXPORT_SYMBOL(__down_write); | ||
| 140 | EXPORT_SYMBOL(__down_write_trylock); | ||
| 141 | EXPORT_SYMBOL(__up_read); | ||
| 142 | EXPORT_SYMBOL(__up_write); | ||
| 143 | EXPORT_SYMBOL(__downgrade_write); | ||
| 144 | |||
| 145 | /* Atomic counter implementation. */ | ||
| 146 | EXPORT_SYMBOL(atomic_add); | ||
| 147 | EXPORT_SYMBOL(atomic_add_ret); | ||
| 148 | EXPORT_SYMBOL(atomic_sub); | ||
| 149 | EXPORT_SYMBOL(atomic_sub_ret); | ||
| 150 | EXPORT_SYMBOL(atomic64_add); | ||
| 151 | EXPORT_SYMBOL(atomic64_add_ret); | ||
| 152 | EXPORT_SYMBOL(atomic64_sub); | ||
| 153 | EXPORT_SYMBOL(atomic64_sub_ret); | ||
| 154 | |||
| 155 | /* Atomic bit operations. */ | ||
| 156 | EXPORT_SYMBOL(test_and_set_bit); | ||
| 157 | EXPORT_SYMBOL(test_and_clear_bit); | ||
| 158 | EXPORT_SYMBOL(test_and_change_bit); | ||
| 159 | EXPORT_SYMBOL(set_bit); | ||
| 160 | EXPORT_SYMBOL(clear_bit); | ||
| 161 | EXPORT_SYMBOL(change_bit); | ||
| 162 | |||
| 163 | /* Special internal versions of library functions. */ | ||
| 164 | EXPORT_SYMBOL(_clear_page); | ||
| 165 | EXPORT_SYMBOL(clear_user_page); | ||
| 166 | EXPORT_SYMBOL(copy_user_page); | ||
| 167 | |||
| 168 | /* RAID code needs this */ | ||
| 169 | void VISenter(void); | ||
| 170 | EXPORT_SYMBOL(VISenter); | ||
| 171 | |||
| 172 | extern void xor_vis_2(unsigned long, unsigned long *, unsigned long *); | ||
| 173 | extern void xor_vis_3(unsigned long, unsigned long *, unsigned long *, | ||
| 174 | unsigned long *); | ||
| 175 | extern void xor_vis_4(unsigned long, unsigned long *, unsigned long *, | ||
| 176 | unsigned long *, unsigned long *); | ||
| 177 | extern void xor_vis_5(unsigned long, unsigned long *, unsigned long *, | ||
| 178 | unsigned long *, unsigned long *, unsigned long *); | ||
| 179 | EXPORT_SYMBOL(xor_vis_2); | ||
| 180 | EXPORT_SYMBOL(xor_vis_3); | ||
| 181 | EXPORT_SYMBOL(xor_vis_4); | ||
| 182 | EXPORT_SYMBOL(xor_vis_5); | ||
| 183 | |||
| 184 | extern void xor_niagara_2(unsigned long, unsigned long *, unsigned long *); | ||
| 185 | extern void xor_niagara_3(unsigned long, unsigned long *, unsigned long *, | ||
| 186 | unsigned long *); | ||
| 187 | extern void xor_niagara_4(unsigned long, unsigned long *, unsigned long *, | ||
| 188 | unsigned long *, unsigned long *); | ||
| 189 | extern void xor_niagara_5(unsigned long, unsigned long *, unsigned long *, | ||
| 190 | unsigned long *, unsigned long *, unsigned long *); | ||
| 191 | |||
| 192 | EXPORT_SYMBOL(xor_niagara_2); | ||
| 193 | EXPORT_SYMBOL(xor_niagara_3); | ||
| 194 | EXPORT_SYMBOL(xor_niagara_4); | ||
| 195 | EXPORT_SYMBOL(xor_niagara_5); | ||
| 196 | #endif | ||
diff --git a/arch/sparc/lib/user_fixup.c b/arch/sparc/lib/user_fixup.c index 05a361b0a1a4..ac96ae236709 100644 --- a/arch/sparc/lib/user_fixup.c +++ b/arch/sparc/lib/user_fixup.c | |||
| @@ -7,6 +7,8 @@ | |||
| 7 | #include <linux/kernel.h> | 7 | #include <linux/kernel.h> |
| 8 | #include <linux/string.h> | 8 | #include <linux/string.h> |
| 9 | #include <linux/errno.h> | 9 | #include <linux/errno.h> |
| 10 | #include <linux/module.h> | ||
| 11 | |||
| 10 | #include <asm/uaccess.h> | 12 | #include <asm/uaccess.h> |
| 11 | 13 | ||
| 12 | /* Calculating the exact fault address when using | 14 | /* Calculating the exact fault address when using |
| @@ -40,6 +42,7 @@ unsigned long copy_from_user_fixup(void *to, const void __user *from, unsigned l | |||
| 40 | 42 | ||
| 41 | return size; | 43 | return size; |
| 42 | } | 44 | } |
| 45 | EXPORT_SYMBOL(copy_from_user_fixup); | ||
| 43 | 46 | ||
| 44 | unsigned long copy_to_user_fixup(void __user *to, const void *from, unsigned long size) | 47 | unsigned long copy_to_user_fixup(void __user *to, const void *from, unsigned long size) |
| 45 | { | 48 | { |
| @@ -47,6 +50,7 @@ unsigned long copy_to_user_fixup(void __user *to, const void *from, unsigned lon | |||
| 47 | 50 | ||
| 48 | return compute_size((unsigned long) to, size, &offset); | 51 | return compute_size((unsigned long) to, size, &offset); |
| 49 | } | 52 | } |
| 53 | EXPORT_SYMBOL(copy_to_user_fixup); | ||
| 50 | 54 | ||
| 51 | unsigned long copy_in_user_fixup(void __user *to, void __user *from, unsigned long size) | 55 | unsigned long copy_in_user_fixup(void __user *to, void __user *from, unsigned long size) |
| 52 | { | 56 | { |
| @@ -64,3 +68,4 @@ unsigned long copy_in_user_fixup(void __user *to, void __user *from, unsigned lo | |||
| 64 | 68 | ||
| 65 | return size; | 69 | return size; |
| 66 | } | 70 | } |
| 71 | EXPORT_SYMBOL(copy_in_user_fixup); | ||
diff --git a/arch/sparc/mm/generic_32.c b/arch/sparc/mm/generic_32.c index a289261da9fd..5edcac184eaf 100644 --- a/arch/sparc/mm/generic_32.c +++ b/arch/sparc/mm/generic_32.c | |||
| @@ -95,3 +95,4 @@ int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long from, | |||
| 95 | flush_tlb_range(vma, beg, end); | 95 | flush_tlb_range(vma, beg, end); |
| 96 | return error; | 96 | return error; |
| 97 | } | 97 | } |
| 98 | EXPORT_SYMBOL(io_remap_pfn_range); | ||
diff --git a/arch/sparc/mm/generic_64.c b/arch/sparc/mm/generic_64.c index f362c2037013..04f2bf4cd571 100644 --- a/arch/sparc/mm/generic_64.c +++ b/arch/sparc/mm/generic_64.c | |||
| @@ -161,3 +161,4 @@ int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long from, | |||
| 161 | flush_tlb_range(vma, beg, end); | 161 | flush_tlb_range(vma, beg, end); |
| 162 | return error; | 162 | return error; |
| 163 | } | 163 | } |
| 164 | EXPORT_SYMBOL(io_remap_pfn_range); | ||
diff --git a/arch/sparc/mm/highmem.c b/arch/sparc/mm/highmem.c index 01fc6c254292..752d0c9fb544 100644 --- a/arch/sparc/mm/highmem.c +++ b/arch/sparc/mm/highmem.c | |||
| @@ -62,6 +62,7 @@ void *kmap_atomic(struct page *page, enum km_type type) | |||
| 62 | 62 | ||
| 63 | return (void*) vaddr; | 63 | return (void*) vaddr; |
| 64 | } | 64 | } |
| 65 | EXPORT_SYMBOL(kmap_atomic); | ||
| 65 | 66 | ||
| 66 | void kunmap_atomic(void *kvaddr, enum km_type type) | 67 | void kunmap_atomic(void *kvaddr, enum km_type type) |
| 67 | { | 68 | { |
| @@ -98,6 +99,7 @@ void kunmap_atomic(void *kvaddr, enum km_type type) | |||
| 98 | 99 | ||
| 99 | pagefault_enable(); | 100 | pagefault_enable(); |
| 100 | } | 101 | } |
| 102 | EXPORT_SYMBOL(kunmap_atomic); | ||
| 101 | 103 | ||
| 102 | /* We may be fed a pagetable here by ptep_to_xxx and others. */ | 104 | /* We may be fed a pagetable here by ptep_to_xxx and others. */ |
| 103 | struct page *kmap_atomic_to_page(void *ptr) | 105 | struct page *kmap_atomic_to_page(void *ptr) |
diff --git a/arch/sparc/mm/init_32.c b/arch/sparc/mm/init_32.c index fec926021f49..cbb282dab5a7 100644 --- a/arch/sparc/mm/init_32.c +++ b/arch/sparc/mm/init_32.c | |||
| @@ -38,11 +38,16 @@ | |||
| 38 | DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); | 38 | DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); |
| 39 | 39 | ||
| 40 | unsigned long *sparc_valid_addr_bitmap; | 40 | unsigned long *sparc_valid_addr_bitmap; |
| 41 | EXPORT_SYMBOL(sparc_valid_addr_bitmap); | ||
| 41 | 42 | ||
| 42 | unsigned long phys_base; | 43 | unsigned long phys_base; |
| 44 | EXPORT_SYMBOL(phys_base); | ||
| 45 | |||
| 43 | unsigned long pfn_base; | 46 | unsigned long pfn_base; |
| 47 | EXPORT_SYMBOL(pfn_base); | ||
| 44 | 48 | ||
| 45 | unsigned long page_kernel; | 49 | unsigned long page_kernel; |
| 50 | EXPORT_SYMBOL(page_kernel); | ||
| 46 | 51 | ||
| 47 | struct sparc_phys_banks sp_banks[SPARC_PHYS_BANKS+1]; | 52 | struct sparc_phys_banks sp_banks[SPARC_PHYS_BANKS+1]; |
| 48 | unsigned long sparc_unmapped_base; | 53 | unsigned long sparc_unmapped_base; |
| @@ -522,3 +527,4 @@ void sparc_flush_page_to_ram(struct page *page) | |||
| 522 | if (vaddr) | 527 | if (vaddr) |
| 523 | __flush_page_to_ram(vaddr); | 528 | __flush_page_to_ram(vaddr); |
| 524 | } | 529 | } |
| 530 | EXPORT_SYMBOL(sparc_flush_page_to_ram); | ||
diff --git a/arch/sparc/mm/init_64.c b/arch/sparc/mm/init_64.c index c77c7ef5d5d4..00373ce2d8fb 100644 --- a/arch/sparc/mm/init_64.c +++ b/arch/sparc/mm/init_64.c | |||
| @@ -146,6 +146,7 @@ static void __init read_obp_memory(const char *property, | |||
| 146 | } | 146 | } |
| 147 | 147 | ||
| 148 | unsigned long *sparc64_valid_addr_bitmap __read_mostly; | 148 | unsigned long *sparc64_valid_addr_bitmap __read_mostly; |
| 149 | EXPORT_SYMBOL(sparc64_valid_addr_bitmap); | ||
| 149 | 150 | ||
| 150 | /* Kernel physical address base and size in bytes. */ | 151 | /* Kernel physical address base and size in bytes. */ |
| 151 | unsigned long kern_base __read_mostly; | 152 | unsigned long kern_base __read_mostly; |
| @@ -369,6 +370,7 @@ void flush_dcache_page(struct page *page) | |||
| 369 | out: | 370 | out: |
| 370 | put_cpu(); | 371 | put_cpu(); |
| 371 | } | 372 | } |
| 373 | EXPORT_SYMBOL(flush_dcache_page); | ||
| 372 | 374 | ||
| 373 | void __kprobes flush_icache_range(unsigned long start, unsigned long end) | 375 | void __kprobes flush_icache_range(unsigned long start, unsigned long end) |
| 374 | { | 376 | { |
| @@ -396,6 +398,7 @@ void __kprobes flush_icache_range(unsigned long start, unsigned long end) | |||
| 396 | } | 398 | } |
| 397 | } | 399 | } |
| 398 | } | 400 | } |
| 401 | EXPORT_SYMBOL(flush_icache_range); | ||
| 399 | 402 | ||
| 400 | void mmu_info(struct seq_file *m) | 403 | void mmu_info(struct seq_file *m) |
| 401 | { | 404 | { |
| @@ -599,6 +602,7 @@ void __flush_dcache_range(unsigned long start, unsigned long end) | |||
| 599 | "i" (ASI_DCACHE_INVALIDATE)); | 602 | "i" (ASI_DCACHE_INVALIDATE)); |
| 600 | } | 603 | } |
| 601 | } | 604 | } |
| 605 | EXPORT_SYMBOL(__flush_dcache_range); | ||
| 602 | 606 | ||
| 603 | /* get_new_mmu_context() uses "cache + 1". */ | 607 | /* get_new_mmu_context() uses "cache + 1". */ |
| 604 | DEFINE_SPINLOCK(ctx_alloc_lock); | 608 | DEFINE_SPINLOCK(ctx_alloc_lock); |
diff --git a/arch/sparc/prom/init_32.c b/arch/sparc/prom/init_32.c index 873217c6d823..6193c33ed4d4 100644 --- a/arch/sparc/prom/init_32.c +++ b/arch/sparc/prom/init_32.c | |||
| @@ -8,16 +8,20 @@ | |||
| 8 | 8 | ||
| 9 | #include <linux/kernel.h> | 9 | #include <linux/kernel.h> |
| 10 | #include <linux/init.h> | 10 | #include <linux/init.h> |
| 11 | #include <linux/module.h> | ||
| 11 | 12 | ||
| 12 | #include <asm/openprom.h> | 13 | #include <asm/openprom.h> |
| 13 | #include <asm/oplib.h> | 14 | #include <asm/oplib.h> |
| 14 | 15 | ||
| 15 | struct linux_romvec *romvec; | 16 | struct linux_romvec *romvec; |
| 17 | EXPORT_SYMBOL(romvec); | ||
| 18 | |||
| 16 | enum prom_major_version prom_vers; | 19 | enum prom_major_version prom_vers; |
| 17 | unsigned int prom_rev, prom_prev; | 20 | unsigned int prom_rev, prom_prev; |
| 18 | 21 | ||
| 19 | /* The root node of the prom device tree. */ | 22 | /* The root node of the prom device tree. */ |
| 20 | int prom_root_node; | 23 | int prom_root_node; |
| 24 | EXPORT_SYMBOL(prom_root_node); | ||
| 21 | 25 | ||
| 22 | /* Pointer to the device tree operations structure. */ | 26 | /* Pointer to the device tree operations structure. */ |
| 23 | struct linux_nodeops *prom_nodeops; | 27 | struct linux_nodeops *prom_nodeops; |
diff --git a/arch/sparc/prom/misc_32.c b/arch/sparc/prom/misc_32.c index cf6c3f6d36c3..4d61c540bb3d 100644 --- a/arch/sparc/prom/misc_32.c +++ b/arch/sparc/prom/misc_32.c | |||
| @@ -8,6 +8,8 @@ | |||
| 8 | #include <linux/types.h> | 8 | #include <linux/types.h> |
| 9 | #include <linux/kernel.h> | 9 | #include <linux/kernel.h> |
| 10 | #include <linux/sched.h> | 10 | #include <linux/sched.h> |
| 11 | #include <linux/module.h> | ||
| 12 | |||
| 11 | #include <asm/openprom.h> | 13 | #include <asm/openprom.h> |
| 12 | #include <asm/oplib.h> | 14 | #include <asm/oplib.h> |
| 13 | #include <asm/auxio.h> | 15 | #include <asm/auxio.h> |
| @@ -44,6 +46,7 @@ prom_feval(char *fstring) | |||
| 44 | restore_current(); | 46 | restore_current(); |
| 45 | spin_unlock_irqrestore(&prom_lock, flags); | 47 | spin_unlock_irqrestore(&prom_lock, flags); |
| 46 | } | 48 | } |
| 49 | EXPORT_SYMBOL(prom_feval); | ||
| 47 | 50 | ||
| 48 | /* Drop into the prom, with the chance to continue with the 'go' | 51 | /* Drop into the prom, with the chance to continue with the 'go' |
| 49 | * prom command. | 52 | * prom command. |
diff --git a/arch/sparc/prom/misc_64.c b/arch/sparc/prom/misc_64.c index 9b0c0760901e..eedffb4fec2d 100644 --- a/arch/sparc/prom/misc_64.c +++ b/arch/sparc/prom/misc_64.c | |||
| @@ -11,6 +11,8 @@ | |||
| 11 | #include <linux/sched.h> | 11 | #include <linux/sched.h> |
| 12 | #include <linux/interrupt.h> | 12 | #include <linux/interrupt.h> |
| 13 | #include <linux/delay.h> | 13 | #include <linux/delay.h> |
| 14 | #include <linux/module.h> | ||
| 15 | |||
| 14 | #include <asm/openprom.h> | 16 | #include <asm/openprom.h> |
| 15 | #include <asm/oplib.h> | 17 | #include <asm/oplib.h> |
| 16 | #include <asm/system.h> | 18 | #include <asm/system.h> |
| @@ -54,6 +56,7 @@ void prom_feval(const char *fstring) | |||
| 54 | p1275_cmd("interpret", P1275_ARG(0, P1275_ARG_IN_STRING) | | 56 | p1275_cmd("interpret", P1275_ARG(0, P1275_ARG_IN_STRING) | |
| 55 | P1275_INOUT(1, 1), fstring); | 57 | P1275_INOUT(1, 1), fstring); |
| 56 | } | 58 | } |
| 59 | EXPORT_SYMBOL(prom_feval); | ||
| 57 | 60 | ||
| 58 | #ifdef CONFIG_SMP | 61 | #ifdef CONFIG_SMP |
| 59 | extern void smp_capture(void); | 62 | extern void smp_capture(void); |
diff --git a/arch/sparc/prom/ranges.c b/arch/sparc/prom/ranges.c index 64579a376419..cd5790853ff6 100644 --- a/arch/sparc/prom/ranges.c +++ b/arch/sparc/prom/ranges.c | |||
| @@ -6,6 +6,8 @@ | |||
| 6 | */ | 6 | */ |
| 7 | 7 | ||
| 8 | #include <linux/init.h> | 8 | #include <linux/init.h> |
| 9 | #include <linux/module.h> | ||
| 10 | |||
| 9 | #include <asm/openprom.h> | 11 | #include <asm/openprom.h> |
| 10 | #include <asm/oplib.h> | 12 | #include <asm/oplib.h> |
| 11 | #include <asm/types.h> | 13 | #include <asm/types.h> |
| @@ -62,6 +64,7 @@ prom_apply_obio_ranges(struct linux_prom_registers *regs, int nregs) | |||
| 62 | if(num_obio_ranges) | 64 | if(num_obio_ranges) |
| 63 | prom_adjust_regs(regs, nregs, promlib_obio_ranges, num_obio_ranges); | 65 | prom_adjust_regs(regs, nregs, promlib_obio_ranges, num_obio_ranges); |
| 64 | } | 66 | } |
| 67 | EXPORT_SYMBOL(prom_apply_obio_ranges); | ||
| 65 | 68 | ||
| 66 | void __init prom_ranges_init(void) | 69 | void __init prom_ranges_init(void) |
| 67 | { | 70 | { |
diff --git a/arch/sparc/prom/tree_32.c b/arch/sparc/prom/tree_32.c index 6d8187357331..646d244b1fdb 100644 --- a/arch/sparc/prom/tree_32.c +++ b/arch/sparc/prom/tree_32.c | |||
| @@ -5,13 +5,12 @@ | |||
| 5 | * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) | 5 | * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) |
| 6 | */ | 6 | */ |
| 7 | 7 | ||
| 8 | #define PROMLIB_INTERNAL | ||
| 9 | |||
| 10 | #include <linux/string.h> | 8 | #include <linux/string.h> |
| 11 | #include <linux/types.h> | 9 | #include <linux/types.h> |
| 12 | #include <linux/kernel.h> | 10 | #include <linux/kernel.h> |
| 13 | #include <linux/sched.h> | 11 | #include <linux/sched.h> |
| 14 | #include <linux/ctype.h> | 12 | #include <linux/ctype.h> |
| 13 | #include <linux/module.h> | ||
| 15 | 14 | ||
| 16 | #include <asm/openprom.h> | 15 | #include <asm/openprom.h> |
| 17 | #include <asm/oplib.h> | 16 | #include <asm/oplib.h> |
| @@ -50,6 +49,7 @@ int prom_getchild(int node) | |||
| 50 | 49 | ||
| 51 | return cnode; | 50 | return cnode; |
| 52 | } | 51 | } |
| 52 | EXPORT_SYMBOL(prom_getchild); | ||
| 53 | 53 | ||
| 54 | /* Internal version of prom_getsibling that does not alter return values. */ | 54 | /* Internal version of prom_getsibling that does not alter return values. */ |
| 55 | int __prom_getsibling(int node) | 55 | int __prom_getsibling(int node) |
| @@ -81,6 +81,7 @@ int prom_getsibling(int node) | |||
| 81 | 81 | ||
| 82 | return sibnode; | 82 | return sibnode; |
| 83 | } | 83 | } |
| 84 | EXPORT_SYMBOL(prom_getsibling); | ||
| 84 | 85 | ||
| 85 | /* Return the length in bytes of property 'prop' at node 'node'. | 86 | /* Return the length in bytes of property 'prop' at node 'node'. |
| 86 | * Return -1 on error. | 87 | * Return -1 on error. |
| @@ -99,6 +100,7 @@ int prom_getproplen(int node, const char *prop) | |||
| 99 | spin_unlock_irqrestore(&prom_lock, flags); | 100 | spin_unlock_irqrestore(&prom_lock, flags); |
| 100 | return ret; | 101 | return ret; |
| 101 | } | 102 | } |
| 103 | EXPORT_SYMBOL(prom_getproplen); | ||
| 102 | 104 | ||
| 103 | /* Acquire a property 'prop' at node 'node' and place it in | 105 | /* Acquire a property 'prop' at node 'node' and place it in |
| 104 | * 'buffer' which has a size of 'bufsize'. If the acquisition | 106 | * 'buffer' which has a size of 'bufsize'. If the acquisition |
| @@ -119,6 +121,7 @@ int prom_getproperty(int node, const char *prop, char *buffer, int bufsize) | |||
| 119 | spin_unlock_irqrestore(&prom_lock, flags); | 121 | spin_unlock_irqrestore(&prom_lock, flags); |
| 120 | return ret; | 122 | return ret; |
| 121 | } | 123 | } |
| 124 | EXPORT_SYMBOL(prom_getproperty); | ||
| 122 | 125 | ||
| 123 | /* Acquire an integer property and return its value. Returns -1 | 126 | /* Acquire an integer property and return its value. Returns -1 |
| 124 | * on failure. | 127 | * on failure. |
| @@ -132,6 +135,7 @@ int prom_getint(int node, char *prop) | |||
| 132 | 135 | ||
| 133 | return -1; | 136 | return -1; |
| 134 | } | 137 | } |
| 138 | EXPORT_SYMBOL(prom_getint); | ||
| 135 | 139 | ||
| 136 | /* Acquire an integer property, upon error return the passed default | 140 | /* Acquire an integer property, upon error return the passed default |
| 137 | * integer. | 141 | * integer. |
| @@ -145,6 +149,7 @@ int prom_getintdefault(int node, char *property, int deflt) | |||
| 145 | 149 | ||
| 146 | return retval; | 150 | return retval; |
| 147 | } | 151 | } |
| 152 | EXPORT_SYMBOL(prom_getintdefault); | ||
| 148 | 153 | ||
| 149 | /* Acquire a boolean property, 1=TRUE 0=FALSE. */ | 154 | /* Acquire a boolean property, 1=TRUE 0=FALSE. */ |
| 150 | int prom_getbool(int node, char *prop) | 155 | int prom_getbool(int node, char *prop) |
| @@ -155,6 +160,7 @@ int prom_getbool(int node, char *prop) | |||
| 155 | if(retval == -1) return 0; | 160 | if(retval == -1) return 0; |
| 156 | return 1; | 161 | return 1; |
| 157 | } | 162 | } |
| 163 | EXPORT_SYMBOL(prom_getbool); | ||
| 158 | 164 | ||
| 159 | /* Acquire a property whose value is a string, returns a null | 165 | /* Acquire a property whose value is a string, returns a null |
| 160 | * string on error. The char pointer is the user supplied string | 166 | * string on error. The char pointer is the user supplied string |
| @@ -169,6 +175,7 @@ void prom_getstring(int node, char *prop, char *user_buf, int ubuf_size) | |||
| 169 | user_buf[0] = 0; | 175 | user_buf[0] = 0; |
| 170 | return; | 176 | return; |
| 171 | } | 177 | } |
| 178 | EXPORT_SYMBOL(prom_getstring); | ||
| 172 | 179 | ||
| 173 | 180 | ||
| 174 | /* Does the device at node 'node' have name 'name'? | 181 | /* Does the device at node 'node' have name 'name'? |
| @@ -204,6 +211,7 @@ int prom_searchsiblings(int node_start, char *nodename) | |||
| 204 | 211 | ||
| 205 | return 0; | 212 | return 0; |
| 206 | } | 213 | } |
| 214 | EXPORT_SYMBOL(prom_searchsiblings); | ||
| 207 | 215 | ||
| 208 | /* Interal version of nextprop that does not alter return values. */ | 216 | /* Interal version of nextprop that does not alter return values. */ |
| 209 | char * __prom_nextprop(int node, char * oprop) | 217 | char * __prom_nextprop(int node, char * oprop) |
| @@ -228,6 +236,7 @@ char * prom_firstprop(int node, char *bufer) | |||
| 228 | 236 | ||
| 229 | return __prom_nextprop(node, ""); | 237 | return __prom_nextprop(node, ""); |
| 230 | } | 238 | } |
| 239 | EXPORT_SYMBOL(prom_firstprop); | ||
| 231 | 240 | ||
| 232 | /* Return the property type string after property type 'oprop' | 241 | /* Return the property type string after property type 'oprop' |
| 233 | * at node 'node' . Returns empty string if no more | 242 | * at node 'node' . Returns empty string if no more |
| @@ -240,6 +249,7 @@ char * prom_nextprop(int node, char *oprop, char *buffer) | |||
| 240 | 249 | ||
| 241 | return __prom_nextprop(node, oprop); | 250 | return __prom_nextprop(node, oprop); |
| 242 | } | 251 | } |
| 252 | EXPORT_SYMBOL(prom_nextprop); | ||
| 243 | 253 | ||
| 244 | int prom_finddevice(char *name) | 254 | int prom_finddevice(char *name) |
| 245 | { | 255 | { |
| @@ -287,6 +297,7 @@ int prom_finddevice(char *name) | |||
| 287 | } | 297 | } |
| 288 | return node; | 298 | return node; |
| 289 | } | 299 | } |
| 300 | EXPORT_SYMBOL(prom_finddevice); | ||
| 290 | 301 | ||
| 291 | int prom_node_has_property(int node, char *prop) | 302 | int prom_node_has_property(int node, char *prop) |
| 292 | { | 303 | { |
| @@ -299,6 +310,7 @@ int prom_node_has_property(int node, char *prop) | |||
| 299 | } while (*current_property); | 310 | } while (*current_property); |
| 300 | return 0; | 311 | return 0; |
| 301 | } | 312 | } |
| 313 | EXPORT_SYMBOL(prom_node_has_property); | ||
| 302 | 314 | ||
| 303 | /* Set property 'pname' at node 'node' to value 'value' which has a length | 315 | /* Set property 'pname' at node 'node' to value 'value' which has a length |
| 304 | * of 'size' bytes. Return the number of bytes the prom accepted. | 316 | * of 'size' bytes. Return the number of bytes the prom accepted. |
| @@ -316,6 +328,7 @@ int prom_setprop(int node, const char *pname, char *value, int size) | |||
| 316 | spin_unlock_irqrestore(&prom_lock, flags); | 328 | spin_unlock_irqrestore(&prom_lock, flags); |
| 317 | return ret; | 329 | return ret; |
| 318 | } | 330 | } |
| 331 | EXPORT_SYMBOL(prom_setprop); | ||
| 319 | 332 | ||
| 320 | int prom_inst2pkg(int inst) | 333 | int prom_inst2pkg(int inst) |
| 321 | { | 334 | { |
diff --git a/arch/sparc/prom/tree_64.c b/arch/sparc/prom/tree_64.c index 281aea44790b..8ea73ddc61dc 100644 --- a/arch/sparc/prom/tree_64.c +++ b/arch/sparc/prom/tree_64.c | |||
| @@ -10,6 +10,7 @@ | |||
| 10 | #include <linux/types.h> | 10 | #include <linux/types.h> |
| 11 | #include <linux/kernel.h> | 11 | #include <linux/kernel.h> |
| 12 | #include <linux/sched.h> | 12 | #include <linux/sched.h> |
| 13 | #include <linux/module.h> | ||
| 13 | 14 | ||
| 14 | #include <asm/openprom.h> | 15 | #include <asm/openprom.h> |
| 15 | #include <asm/oplib.h> | 16 | #include <asm/oplib.h> |
| @@ -32,6 +33,7 @@ inline int prom_getchild(int node) | |||
| 32 | if(cnode == -1) return 0; | 33 | if(cnode == -1) return 0; |
| 33 | return (int)cnode; | 34 | return (int)cnode; |
| 34 | } | 35 | } |
| 36 | EXPORT_SYMBOL(prom_getchild); | ||
| 35 | 37 | ||
| 36 | inline int prom_getparent(int node) | 38 | inline int prom_getparent(int node) |
| 37 | { | 39 | { |
| @@ -63,6 +65,7 @@ inline int prom_getsibling(int node) | |||
| 63 | 65 | ||
| 64 | return sibnode; | 66 | return sibnode; |
| 65 | } | 67 | } |
| 68 | EXPORT_SYMBOL(prom_getsibling); | ||
| 66 | 69 | ||
| 67 | /* Return the length in bytes of property 'prop' at node 'node'. | 70 | /* Return the length in bytes of property 'prop' at node 'node'. |
| 68 | * Return -1 on error. | 71 | * Return -1 on error. |
| @@ -75,6 +78,7 @@ inline int prom_getproplen(int node, const char *prop) | |||
| 75 | P1275_INOUT(2, 1), | 78 | P1275_INOUT(2, 1), |
| 76 | node, prop); | 79 | node, prop); |
| 77 | } | 80 | } |
| 81 | EXPORT_SYMBOL(prom_getproplen); | ||
| 78 | 82 | ||
| 79 | /* Acquire a property 'prop' at node 'node' and place it in | 83 | /* Acquire a property 'prop' at node 'node' and place it in |
| 80 | * 'buffer' which has a size of 'bufsize'. If the acquisition | 84 | * 'buffer' which has a size of 'bufsize'. If the acquisition |
| @@ -97,6 +101,7 @@ inline int prom_getproperty(int node, const char *prop, | |||
| 97 | node, prop, buffer, P1275_SIZE(plen)); | 101 | node, prop, buffer, P1275_SIZE(plen)); |
| 98 | } | 102 | } |
| 99 | } | 103 | } |
| 104 | EXPORT_SYMBOL(prom_getproperty); | ||
| 100 | 105 | ||
| 101 | /* Acquire an integer property and return its value. Returns -1 | 106 | /* Acquire an integer property and return its value. Returns -1 |
| 102 | * on failure. | 107 | * on failure. |
| @@ -110,6 +115,7 @@ inline int prom_getint(int node, const char *prop) | |||
| 110 | 115 | ||
| 111 | return -1; | 116 | return -1; |
| 112 | } | 117 | } |
| 118 | EXPORT_SYMBOL(prom_getint); | ||
| 113 | 119 | ||
| 114 | /* Acquire an integer property, upon error return the passed default | 120 | /* Acquire an integer property, upon error return the passed default |
| 115 | * integer. | 121 | * integer. |
| @@ -124,6 +130,7 @@ int prom_getintdefault(int node, const char *property, int deflt) | |||
| 124 | 130 | ||
| 125 | return retval; | 131 | return retval; |
| 126 | } | 132 | } |
| 133 | EXPORT_SYMBOL(prom_getintdefault); | ||
| 127 | 134 | ||
| 128 | /* Acquire a boolean property, 1=TRUE 0=FALSE. */ | 135 | /* Acquire a boolean property, 1=TRUE 0=FALSE. */ |
| 129 | int prom_getbool(int node, const char *prop) | 136 | int prom_getbool(int node, const char *prop) |
| @@ -134,6 +141,7 @@ int prom_getbool(int node, const char *prop) | |||
| 134 | if(retval == -1) return 0; | 141 | if(retval == -1) return 0; |
| 135 | return 1; | 142 | return 1; |
| 136 | } | 143 | } |
| 144 | EXPORT_SYMBOL(prom_getbool); | ||
| 137 | 145 | ||
| 138 | /* Acquire a property whose value is a string, returns a null | 146 | /* Acquire a property whose value is a string, returns a null |
| 139 | * string on error. The char pointer is the user supplied string | 147 | * string on error. The char pointer is the user supplied string |
| @@ -148,7 +156,7 @@ void prom_getstring(int node, const char *prop, char *user_buf, int ubuf_size) | |||
| 148 | user_buf[0] = 0; | 156 | user_buf[0] = 0; |
| 149 | return; | 157 | return; |
| 150 | } | 158 | } |
| 151 | 159 | EXPORT_SYMBOL(prom_getstring); | |
| 152 | 160 | ||
| 153 | /* Does the device at node 'node' have name 'name'? | 161 | /* Does the device at node 'node' have name 'name'? |
| 154 | * YES = 1 NO = 0 | 162 | * YES = 1 NO = 0 |
| @@ -181,6 +189,7 @@ int prom_searchsiblings(int node_start, const char *nodename) | |||
| 181 | 189 | ||
| 182 | return 0; | 190 | return 0; |
| 183 | } | 191 | } |
| 192 | EXPORT_SYMBOL(prom_searchsiblings); | ||
| 184 | 193 | ||
| 185 | /* Return the first property type for node 'node'. | 194 | /* Return the first property type for node 'node'. |
| 186 | * buffer should be at least 32B in length | 195 | * buffer should be at least 32B in length |
| @@ -194,6 +203,7 @@ inline char *prom_firstprop(int node, char *buffer) | |||
| 194 | node, (char *) 0x0, buffer); | 203 | node, (char *) 0x0, buffer); |
| 195 | return buffer; | 204 | return buffer; |
| 196 | } | 205 | } |
| 206 | EXPORT_SYMBOL(prom_firstprop); | ||
| 197 | 207 | ||
| 198 | /* Return the property type string after property type 'oprop' | 208 | /* Return the property type string after property type 'oprop' |
| 199 | * at node 'node' . Returns NULL string if no more | 209 | * at node 'node' . Returns NULL string if no more |
| @@ -217,6 +227,7 @@ inline char *prom_nextprop(int node, const char *oprop, char *buffer) | |||
| 217 | node, oprop, buffer); | 227 | node, oprop, buffer); |
| 218 | return buffer; | 228 | return buffer; |
| 219 | } | 229 | } |
| 230 | EXPORT_SYMBOL(prom_nextprop); | ||
| 220 | 231 | ||
| 221 | int | 232 | int |
| 222 | prom_finddevice(const char *name) | 233 | prom_finddevice(const char *name) |
| @@ -228,6 +239,7 @@ prom_finddevice(const char *name) | |||
| 228 | P1275_INOUT(1, 1), | 239 | P1275_INOUT(1, 1), |
| 229 | name); | 240 | name); |
| 230 | } | 241 | } |
| 242 | EXPORT_SYMBOL(prom_finddevice); | ||
| 231 | 243 | ||
| 232 | int prom_node_has_property(int node, const char *prop) | 244 | int prom_node_has_property(int node, const char *prop) |
| 233 | { | 245 | { |
| @@ -241,7 +253,8 @@ int prom_node_has_property(int node, const char *prop) | |||
| 241 | } while (*buf); | 253 | } while (*buf); |
| 242 | return 0; | 254 | return 0; |
| 243 | } | 255 | } |
| 244 | 256 | EXPORT_SYMBOL(prom_node_has_property); | |
| 257 | |||
| 245 | /* Set property 'pname' at node 'node' to value 'value' which has a length | 258 | /* Set property 'pname' at node 'node' to value 'value' which has a length |
| 246 | * of 'size' bytes. Return the number of bytes the prom accepted. | 259 | * of 'size' bytes. Return the number of bytes the prom accepted. |
| 247 | */ | 260 | */ |
| @@ -264,6 +277,7 @@ prom_setprop(int node, const char *pname, char *value, int size) | |||
| 264 | P1275_INOUT(4, 1), | 277 | P1275_INOUT(4, 1), |
| 265 | node, pname, value, P1275_SIZE(size)); | 278 | node, pname, value, P1275_SIZE(size)); |
| 266 | } | 279 | } |
| 280 | EXPORT_SYMBOL(prom_setprop); | ||
| 267 | 281 | ||
| 268 | inline int prom_inst2pkg(int inst) | 282 | inline int prom_inst2pkg(int inst) |
| 269 | { | 283 | { |
diff --git a/arch/x86/include/asm/mach-default/mach_wakecpu.h b/arch/x86/include/asm/mach-default/mach_wakecpu.h index ceb013660146..89897a6a65b9 100644 --- a/arch/x86/include/asm/mach-default/mach_wakecpu.h +++ b/arch/x86/include/asm/mach-default/mach_wakecpu.h | |||
| @@ -24,7 +24,13 @@ static inline void restore_NMI_vector(unsigned short *high, unsigned short *low) | |||
| 24 | { | 24 | { |
| 25 | } | 25 | } |
| 26 | 26 | ||
| 27 | #ifdef CONFIG_SMP | ||
| 27 | extern void __inquire_remote_apic(int apicid); | 28 | extern void __inquire_remote_apic(int apicid); |
| 29 | #else /* CONFIG_SMP */ | ||
| 30 | static inline void __inquire_remote_apic(int apicid) | ||
| 31 | { | ||
| 32 | } | ||
| 33 | #endif /* CONFIG_SMP */ | ||
| 28 | 34 | ||
| 29 | static inline void inquire_remote_apic(int apicid) | 35 | static inline void inquire_remote_apic(int apicid) |
| 30 | { | 36 | { |
diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h index cb988aab716d..14080d22edb3 100644 --- a/arch/x86/include/asm/mtrr.h +++ b/arch/x86/include/asm/mtrr.h | |||
| @@ -58,15 +58,15 @@ struct mtrr_gentry { | |||
| 58 | #endif /* !__i386__ */ | 58 | #endif /* !__i386__ */ |
| 59 | 59 | ||
| 60 | struct mtrr_var_range { | 60 | struct mtrr_var_range { |
| 61 | u32 base_lo; | 61 | __u32 base_lo; |
| 62 | u32 base_hi; | 62 | __u32 base_hi; |
| 63 | u32 mask_lo; | 63 | __u32 mask_lo; |
| 64 | u32 mask_hi; | 64 | __u32 mask_hi; |
| 65 | }; | 65 | }; |
| 66 | 66 | ||
| 67 | /* In the Intel processor's MTRR interface, the MTRR type is always held in | 67 | /* In the Intel processor's MTRR interface, the MTRR type is always held in |
| 68 | an 8 bit field: */ | 68 | an 8 bit field: */ |
| 69 | typedef u8 mtrr_type; | 69 | typedef __u8 mtrr_type; |
| 70 | 70 | ||
| 71 | #define MTRR_NUM_FIXED_RANGES 88 | 71 | #define MTRR_NUM_FIXED_RANGES 88 |
| 72 | #define MTRR_MAX_VAR_RANGES 256 | 72 | #define MTRR_MAX_VAR_RANGES 256 |
diff --git a/arch/x86/kernel/apic.c b/arch/x86/kernel/apic.c index 566a08466b19..0f830e4f5675 100644 --- a/arch/x86/kernel/apic.c +++ b/arch/x86/kernel/apic.c | |||
| @@ -47,6 +47,7 @@ | |||
| 47 | #include <asm/proto.h> | 47 | #include <asm/proto.h> |
| 48 | #include <asm/apic.h> | 48 | #include <asm/apic.h> |
| 49 | #include <asm/i8259.h> | 49 | #include <asm/i8259.h> |
| 50 | #include <asm/smp.h> | ||
| 50 | 51 | ||
| 51 | #include <mach_apic.h> | 52 | #include <mach_apic.h> |
| 52 | #include <mach_apicdef.h> | 53 | #include <mach_apicdef.h> |
diff --git a/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c b/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c index 06fcd8f9323c..6f11e029e8c5 100644 --- a/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c +++ b/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c | |||
| @@ -150,9 +150,8 @@ struct drv_cmd { | |||
| 150 | u32 val; | 150 | u32 val; |
| 151 | }; | 151 | }; |
| 152 | 152 | ||
| 153 | static long do_drv_read(void *_cmd) | 153 | static void do_drv_read(struct drv_cmd *cmd) |
| 154 | { | 154 | { |
| 155 | struct drv_cmd *cmd = _cmd; | ||
| 156 | u32 h; | 155 | u32 h; |
| 157 | 156 | ||
| 158 | switch (cmd->type) { | 157 | switch (cmd->type) { |
| @@ -167,12 +166,10 @@ static long do_drv_read(void *_cmd) | |||
| 167 | default: | 166 | default: |
| 168 | break; | 167 | break; |
| 169 | } | 168 | } |
| 170 | return 0; | ||
| 171 | } | 169 | } |
| 172 | 170 | ||
| 173 | static long do_drv_write(void *_cmd) | 171 | static void do_drv_write(struct drv_cmd *cmd) |
| 174 | { | 172 | { |
| 175 | struct drv_cmd *cmd = _cmd; | ||
| 176 | u32 lo, hi; | 173 | u32 lo, hi; |
| 177 | 174 | ||
| 178 | switch (cmd->type) { | 175 | switch (cmd->type) { |
| @@ -189,23 +186,30 @@ static long do_drv_write(void *_cmd) | |||
| 189 | default: | 186 | default: |
| 190 | break; | 187 | break; |
| 191 | } | 188 | } |
| 192 | return 0; | ||
| 193 | } | 189 | } |
| 194 | 190 | ||
| 195 | static void drv_read(struct drv_cmd *cmd) | 191 | static void drv_read(struct drv_cmd *cmd) |
| 196 | { | 192 | { |
| 193 | cpumask_t saved_mask = current->cpus_allowed; | ||
| 197 | cmd->val = 0; | 194 | cmd->val = 0; |
| 198 | 195 | ||
| 199 | work_on_cpu(cpumask_any(cmd->mask), do_drv_read, cmd); | 196 | set_cpus_allowed_ptr(current, cmd->mask); |
| 197 | do_drv_read(cmd); | ||
| 198 | set_cpus_allowed_ptr(current, &saved_mask); | ||
| 200 | } | 199 | } |
| 201 | 200 | ||
| 202 | static void drv_write(struct drv_cmd *cmd) | 201 | static void drv_write(struct drv_cmd *cmd) |
| 203 | { | 202 | { |
| 203 | cpumask_t saved_mask = current->cpus_allowed; | ||
| 204 | unsigned int i; | 204 | unsigned int i; |
| 205 | 205 | ||
| 206 | for_each_cpu(i, cmd->mask) { | 206 | for_each_cpu(i, cmd->mask) { |
| 207 | work_on_cpu(i, do_drv_write, cmd); | 207 | set_cpus_allowed_ptr(current, cpumask_of(i)); |
| 208 | do_drv_write(cmd); | ||
| 208 | } | 209 | } |
| 210 | |||
| 211 | set_cpus_allowed_ptr(current, &saved_mask); | ||
| 212 | return; | ||
| 209 | } | 213 | } |
| 210 | 214 | ||
| 211 | static u32 get_cur_val(const struct cpumask *mask) | 215 | static u32 get_cur_val(const struct cpumask *mask) |
| @@ -231,15 +235,10 @@ static u32 get_cur_val(const struct cpumask *mask) | |||
| 231 | return 0; | 235 | return 0; |
| 232 | } | 236 | } |
| 233 | 237 | ||
| 234 | if (unlikely(!alloc_cpumask_var(&cmd.mask, GFP_KERNEL))) | ||
| 235 | return 0; | ||
| 236 | |||
| 237 | cpumask_copy(cmd.mask, mask); | 238 | cpumask_copy(cmd.mask, mask); |
| 238 | 239 | ||
| 239 | drv_read(&cmd); | 240 | drv_read(&cmd); |
| 240 | 241 | ||
| 241 | free_cpumask_var(cmd.mask); | ||
| 242 | |||
| 243 | dprintk("get_cur_val = %u\n", cmd.val); | 242 | dprintk("get_cur_val = %u\n", cmd.val); |
| 244 | 243 | ||
| 245 | return cmd.val; | 244 | return cmd.val; |
diff --git a/arch/x86/kernel/mpparse.c b/arch/x86/kernel/mpparse.c index c0601c2848a1..a649a4ccad43 100644 --- a/arch/x86/kernel/mpparse.c +++ b/arch/x86/kernel/mpparse.c | |||
| @@ -27,6 +27,7 @@ | |||
| 27 | #include <asm/e820.h> | 27 | #include <asm/e820.h> |
| 28 | #include <asm/trampoline.h> | 28 | #include <asm/trampoline.h> |
| 29 | #include <asm/setup.h> | 29 | #include <asm/setup.h> |
| 30 | #include <asm/smp.h> | ||
| 30 | 31 | ||
| 31 | #include <mach_apic.h> | 32 | #include <mach_apic.h> |
| 32 | #ifdef CONFIG_X86_32 | 33 | #ifdef CONFIG_X86_32 |
diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c index 9e268b6b204e..90dfae511a41 100644 --- a/arch/x86/mm/fault.c +++ b/arch/x86/mm/fault.c | |||
| @@ -534,7 +534,7 @@ static int vmalloc_fault(unsigned long address) | |||
| 534 | happen within a race in page table update. In the later | 534 | happen within a race in page table update. In the later |
| 535 | case just flush. */ | 535 | case just flush. */ |
| 536 | 536 | ||
| 537 | pgd = pgd_offset(current->mm ?: &init_mm, address); | 537 | pgd = pgd_offset(current->active_mm, address); |
| 538 | pgd_ref = pgd_offset_k(address); | 538 | pgd_ref = pgd_offset_k(address); |
| 539 | if (pgd_none(*pgd_ref)) | 539 | if (pgd_none(*pgd_ref)) |
| 540 | return -1; | 540 | return -1; |
diff --git a/drivers/ata/libata-sff.c b/drivers/ata/libata-sff.c index 0eae9b453556..5a4aad123c42 100644 --- a/drivers/ata/libata-sff.c +++ b/drivers/ata/libata-sff.c | |||
| @@ -1013,9 +1013,12 @@ next_sg: | |||
| 1013 | qc->cursg_ofs = 0; | 1013 | qc->cursg_ofs = 0; |
| 1014 | } | 1014 | } |
| 1015 | 1015 | ||
| 1016 | /* consumed can be larger than count only for the last transfer */ | 1016 | /* |
| 1017 | WARN_ON_ONCE(qc->cursg && count != consumed); | 1017 | * There used to be a WARN_ON_ONCE(qc->cursg && count != consumed); |
| 1018 | 1018 | * Unfortunately __atapi_pio_bytes doesn't know enough to do the WARN | |
| 1019 | * check correctly as it doesn't know if it is the last request being | ||
| 1020 | * made. Somebody should implement a proper sanity check. | ||
| 1021 | */ | ||
| 1019 | if (bytes) | 1022 | if (bytes) |
| 1020 | goto next_sg; | 1023 | goto next_sg; |
| 1021 | return 0; | 1024 | return 0; |
diff --git a/drivers/ata/pata_it821x.c b/drivers/ata/pata_it821x.c index f828a29d7756..f1bb2f9fecbf 100644 --- a/drivers/ata/pata_it821x.c +++ b/drivers/ata/pata_it821x.c | |||
| @@ -80,7 +80,7 @@ | |||
| 80 | 80 | ||
| 81 | 81 | ||
| 82 | #define DRV_NAME "pata_it821x" | 82 | #define DRV_NAME "pata_it821x" |
| 83 | #define DRV_VERSION "0.4.0" | 83 | #define DRV_VERSION "0.4.2" |
| 84 | 84 | ||
| 85 | struct it821x_dev | 85 | struct it821x_dev |
| 86 | { | 86 | { |
| @@ -494,8 +494,6 @@ static int it821x_smart_set_mode(struct ata_link *link, struct ata_device **unus | |||
| 494 | * special. In our case we need to lock the sector count to avoid | 494 | * special. In our case we need to lock the sector count to avoid |
| 495 | * blowing the brains out of the firmware with large LBA48 requests | 495 | * blowing the brains out of the firmware with large LBA48 requests |
| 496 | * | 496 | * |
| 497 | * FIXME: When FUA appears we need to block FUA too. And SMART and | ||
| 498 | * basically we need to filter commands for this chip. | ||
| 499 | */ | 497 | */ |
| 500 | 498 | ||
| 501 | static void it821x_dev_config(struct ata_device *adev) | 499 | static void it821x_dev_config(struct ata_device *adev) |
| @@ -890,6 +888,13 @@ static int it821x_init_one(struct pci_dev *pdev, const struct pci_device_id *id) | |||
| 890 | .flags = ATA_FLAG_SLAVE_POSS, | 888 | .flags = ATA_FLAG_SLAVE_POSS, |
| 891 | .pio_mask = 0x1f, | 889 | .pio_mask = 0x1f, |
| 892 | .mwdma_mask = 0x07, | 890 | .mwdma_mask = 0x07, |
| 891 | .udma_mask = ATA_UDMA6, | ||
| 892 | .port_ops = &it821x_rdc_port_ops | ||
| 893 | }; | ||
| 894 | static const struct ata_port_info info_rdc_11 = { | ||
| 895 | .flags = ATA_FLAG_SLAVE_POSS, | ||
| 896 | .pio_mask = 0x1f, | ||
| 897 | .mwdma_mask = 0x07, | ||
| 893 | /* No UDMA */ | 898 | /* No UDMA */ |
| 894 | .port_ops = &it821x_rdc_port_ops | 899 | .port_ops = &it821x_rdc_port_ops |
| 895 | }; | 900 | }; |
| @@ -903,7 +908,11 @@ static int it821x_init_one(struct pci_dev *pdev, const struct pci_device_id *id) | |||
| 903 | return rc; | 908 | return rc; |
| 904 | 909 | ||
| 905 | if (pdev->vendor == PCI_VENDOR_ID_RDC) { | 910 | if (pdev->vendor == PCI_VENDOR_ID_RDC) { |
| 906 | ppi[0] = &info_rdc; | 911 | /* Deal with Vortex86SX */ |
| 912 | if (pdev->revision == 0x11) | ||
| 913 | ppi[0] = &info_rdc_11; | ||
| 914 | else | ||
| 915 | ppi[0] = &info_rdc; | ||
| 907 | } else { | 916 | } else { |
| 908 | /* Force the card into bypass mode if so requested */ | 917 | /* Force the card into bypass mode if so requested */ |
| 909 | if (it8212_noraid) { | 918 | if (it8212_noraid) { |
diff --git a/drivers/block/amiflop.c b/drivers/block/amiflop.c index 4b1d4ac960f1..8df436ff7068 100644 --- a/drivers/block/amiflop.c +++ b/drivers/block/amiflop.c | |||
| @@ -156,7 +156,7 @@ static volatile int fdc_busy = -1; | |||
| 156 | static volatile int fdc_nested; | 156 | static volatile int fdc_nested; |
| 157 | static DECLARE_WAIT_QUEUE_HEAD(fdc_wait); | 157 | static DECLARE_WAIT_QUEUE_HEAD(fdc_wait); |
| 158 | 158 | ||
| 159 | static DECLARE_WAIT_QUEUE_HEAD(motor_wait); | 159 | static DECLARE_COMPLETION(motor_on_completion); |
| 160 | 160 | ||
| 161 | static volatile int selected = -1; /* currently selected drive */ | 161 | static volatile int selected = -1; /* currently selected drive */ |
| 162 | 162 | ||
| @@ -184,8 +184,7 @@ static unsigned char mfmencode[16]={ | |||
| 184 | static unsigned char mfmdecode[128]; | 184 | static unsigned char mfmdecode[128]; |
| 185 | 185 | ||
| 186 | /* floppy internal millisecond timer stuff */ | 186 | /* floppy internal millisecond timer stuff */ |
| 187 | static volatile int ms_busy = -1; | 187 | static DECLARE_COMPLETION(ms_wait_completion); |
| 188 | static DECLARE_WAIT_QUEUE_HEAD(ms_wait); | ||
| 189 | #define MS_TICKS ((amiga_eclock+50)/1000) | 188 | #define MS_TICKS ((amiga_eclock+50)/1000) |
| 190 | 189 | ||
| 191 | /* | 190 | /* |
| @@ -211,8 +210,7 @@ static int fd_device[4] = { 0, 0, 0, 0 }; | |||
| 211 | 210 | ||
| 212 | static irqreturn_t ms_isr(int irq, void *dummy) | 211 | static irqreturn_t ms_isr(int irq, void *dummy) |
| 213 | { | 212 | { |
| 214 | ms_busy = -1; | 213 | complete(&ms_wait_completion); |
| 215 | wake_up(&ms_wait); | ||
| 216 | return IRQ_HANDLED; | 214 | return IRQ_HANDLED; |
| 217 | } | 215 | } |
| 218 | 216 | ||
| @@ -220,19 +218,17 @@ static irqreturn_t ms_isr(int irq, void *dummy) | |||
| 220 | A more generic routine would do a schedule a la timer.device */ | 218 | A more generic routine would do a schedule a la timer.device */ |
| 221 | static void ms_delay(int ms) | 219 | static void ms_delay(int ms) |
| 222 | { | 220 | { |
| 223 | unsigned long flags; | ||
| 224 | int ticks; | 221 | int ticks; |
| 222 | static DEFINE_MUTEX(mutex); | ||
| 223 | |||
| 225 | if (ms > 0) { | 224 | if (ms > 0) { |
| 226 | local_irq_save(flags); | 225 | mutex_lock(&mutex); |
| 227 | while (ms_busy == 0) | ||
| 228 | sleep_on(&ms_wait); | ||
| 229 | ms_busy = 0; | ||
| 230 | local_irq_restore(flags); | ||
| 231 | ticks = MS_TICKS*ms-1; | 226 | ticks = MS_TICKS*ms-1; |
| 232 | ciaa.tblo=ticks%256; | 227 | ciaa.tblo=ticks%256; |
| 233 | ciaa.tbhi=ticks/256; | 228 | ciaa.tbhi=ticks/256; |
| 234 | ciaa.crb=0x19; /*count eclock, force load, one-shoot, start */ | 229 | ciaa.crb=0x19; /*count eclock, force load, one-shoot, start */ |
| 235 | sleep_on(&ms_wait); | 230 | wait_for_completion(&ms_wait_completion); |
| 231 | mutex_unlock(&mutex); | ||
| 236 | } | 232 | } |
| 237 | } | 233 | } |
| 238 | 234 | ||
| @@ -254,8 +250,7 @@ static void get_fdc(int drive) | |||
| 254 | printk("get_fdc: drive %d fdc_busy %d fdc_nested %d\n",drive,fdc_busy,fdc_nested); | 250 | printk("get_fdc: drive %d fdc_busy %d fdc_nested %d\n",drive,fdc_busy,fdc_nested); |
| 255 | #endif | 251 | #endif |
| 256 | local_irq_save(flags); | 252 | local_irq_save(flags); |
| 257 | while (!try_fdc(drive)) | 253 | wait_event(fdc_wait, try_fdc(drive)); |
| 258 | sleep_on(&fdc_wait); | ||
| 259 | fdc_busy = drive; | 254 | fdc_busy = drive; |
| 260 | fdc_nested++; | 255 | fdc_nested++; |
| 261 | local_irq_restore(flags); | 256 | local_irq_restore(flags); |
| @@ -330,7 +325,7 @@ static void fd_deselect (int drive) | |||
| 330 | static void motor_on_callback(unsigned long nr) | 325 | static void motor_on_callback(unsigned long nr) |
| 331 | { | 326 | { |
| 332 | if (!(ciaa.pra & DSKRDY) || --on_attempts == 0) { | 327 | if (!(ciaa.pra & DSKRDY) || --on_attempts == 0) { |
| 333 | wake_up (&motor_wait); | 328 | complete_all(&motor_on_completion); |
| 334 | } else { | 329 | } else { |
| 335 | motor_on_timer.expires = jiffies + HZ/10; | 330 | motor_on_timer.expires = jiffies + HZ/10; |
| 336 | add_timer(&motor_on_timer); | 331 | add_timer(&motor_on_timer); |
| @@ -347,11 +342,12 @@ static int fd_motor_on(int nr) | |||
| 347 | unit[nr].motor = 1; | 342 | unit[nr].motor = 1; |
| 348 | fd_select(nr); | 343 | fd_select(nr); |
| 349 | 344 | ||
| 345 | INIT_COMPLETION(motor_on_completion); | ||
| 350 | motor_on_timer.data = nr; | 346 | motor_on_timer.data = nr; |
| 351 | mod_timer(&motor_on_timer, jiffies + HZ/2); | 347 | mod_timer(&motor_on_timer, jiffies + HZ/2); |
| 352 | 348 | ||
| 353 | on_attempts = 10; | 349 | on_attempts = 10; |
| 354 | sleep_on (&motor_wait); | 350 | wait_for_completion(&motor_on_completion); |
| 355 | fd_deselect(nr); | 351 | fd_deselect(nr); |
| 356 | } | 352 | } |
| 357 | 353 | ||
| @@ -582,8 +578,7 @@ static void raw_read(int drive) | |||
| 582 | { | 578 | { |
| 583 | drive&=3; | 579 | drive&=3; |
| 584 | get_fdc(drive); | 580 | get_fdc(drive); |
| 585 | while (block_flag) | 581 | wait_event(wait_fd_block, !block_flag); |
| 586 | sleep_on(&wait_fd_block); | ||
| 587 | fd_select(drive); | 582 | fd_select(drive); |
| 588 | /* setup adkcon bits correctly */ | 583 | /* setup adkcon bits correctly */ |
| 589 | custom.adkcon = ADK_MSBSYNC; | 584 | custom.adkcon = ADK_MSBSYNC; |
| @@ -598,8 +593,7 @@ static void raw_read(int drive) | |||
| 598 | 593 | ||
| 599 | block_flag = 1; | 594 | block_flag = 1; |
| 600 | 595 | ||
| 601 | while (block_flag) | 596 | wait_event(wait_fd_block, !block_flag); |
| 602 | sleep_on (&wait_fd_block); | ||
| 603 | 597 | ||
| 604 | custom.dsklen = 0; | 598 | custom.dsklen = 0; |
| 605 | fd_deselect(drive); | 599 | fd_deselect(drive); |
| @@ -616,8 +610,7 @@ static int raw_write(int drive) | |||
| 616 | rel_fdc(); | 610 | rel_fdc(); |
| 617 | return 0; | 611 | return 0; |
| 618 | } | 612 | } |
| 619 | while (block_flag) | 613 | wait_event(wait_fd_block, !block_flag); |
| 620 | sleep_on(&wait_fd_block); | ||
| 621 | fd_select(drive); | 614 | fd_select(drive); |
| 622 | /* clear adkcon bits */ | 615 | /* clear adkcon bits */ |
| 623 | custom.adkcon = ADK_PRECOMP1|ADK_PRECOMP0|ADK_WORDSYNC|ADK_MSBSYNC; | 616 | custom.adkcon = ADK_PRECOMP1|ADK_PRECOMP0|ADK_WORDSYNC|ADK_MSBSYNC; |
| @@ -1294,8 +1287,7 @@ static int non_int_flush_track (unsigned long nr) | |||
| 1294 | writepending = 0; | 1287 | writepending = 0; |
| 1295 | return 0; | 1288 | return 0; |
| 1296 | } | 1289 | } |
| 1297 | while (block_flag == 2) | 1290 | wait_event(wait_fd_block, block_flag != 2); |
| 1298 | sleep_on (&wait_fd_block); | ||
| 1299 | } | 1291 | } |
| 1300 | else { | 1292 | else { |
| 1301 | local_irq_restore(flags); | 1293 | local_irq_restore(flags); |
diff --git a/drivers/char/amiserial.c b/drivers/char/amiserial.c index 4e0cfdeab146..a58869ea8513 100644 --- a/drivers/char/amiserial.c +++ b/drivers/char/amiserial.c | |||
| @@ -1963,6 +1963,7 @@ static int __init rs_init(void) | |||
| 1963 | { | 1963 | { |
| 1964 | unsigned long flags; | 1964 | unsigned long flags; |
| 1965 | struct serial_state * state; | 1965 | struct serial_state * state; |
| 1966 | int error; | ||
| 1966 | 1967 | ||
| 1967 | if (!MACH_IS_AMIGA || !AMIGAHW_PRESENT(AMI_SERIAL)) | 1968 | if (!MACH_IS_AMIGA || !AMIGAHW_PRESENT(AMI_SERIAL)) |
| 1968 | return -ENODEV; | 1969 | return -ENODEV; |
| @@ -1975,8 +1976,11 @@ static int __init rs_init(void) | |||
| 1975 | * We request SERDAT and SERPER only, because the serial registers are | 1976 | * We request SERDAT and SERPER only, because the serial registers are |
| 1976 | * too spreaded over the custom register space | 1977 | * too spreaded over the custom register space |
| 1977 | */ | 1978 | */ |
| 1978 | if (!request_mem_region(CUSTOM_PHYSADDR+0x30, 4, "amiserial [Paula]")) | 1979 | if (!request_mem_region(CUSTOM_PHYSADDR+0x30, 4, |
| 1979 | return -EBUSY; | 1980 | "amiserial [Paula]")) { |
| 1981 | error = -EBUSY; | ||
| 1982 | goto fail_put_tty_driver; | ||
| 1983 | } | ||
| 1980 | 1984 | ||
| 1981 | IRQ_ports = NULL; | 1985 | IRQ_ports = NULL; |
| 1982 | 1986 | ||
| @@ -1997,8 +2001,9 @@ static int __init rs_init(void) | |||
| 1997 | serial_driver->flags = TTY_DRIVER_REAL_RAW; | 2001 | serial_driver->flags = TTY_DRIVER_REAL_RAW; |
| 1998 | tty_set_operations(serial_driver, &serial_ops); | 2002 | tty_set_operations(serial_driver, &serial_ops); |
| 1999 | 2003 | ||
| 2000 | if (tty_register_driver(serial_driver)) | 2004 | error = tty_register_driver(serial_driver); |
| 2001 | panic("Couldn't register serial driver\n"); | 2005 | if (error) |
| 2006 | goto fail_release_mem_region; | ||
| 2002 | 2007 | ||
| 2003 | state = rs_table; | 2008 | state = rs_table; |
| 2004 | state->magic = SSTATE_MAGIC; | 2009 | state->magic = SSTATE_MAGIC; |
| @@ -2024,8 +2029,14 @@ static int __init rs_init(void) | |||
| 2024 | local_irq_save(flags); | 2029 | local_irq_save(flags); |
| 2025 | 2030 | ||
| 2026 | /* set ISRs, and then disable the rx interrupts */ | 2031 | /* set ISRs, and then disable the rx interrupts */ |
| 2027 | request_irq(IRQ_AMIGA_TBE, ser_tx_int, 0, "serial TX", state); | 2032 | error = request_irq(IRQ_AMIGA_TBE, ser_tx_int, 0, "serial TX", state); |
| 2028 | request_irq(IRQ_AMIGA_RBF, ser_rx_int, IRQF_DISABLED, "serial RX", state); | 2033 | if (error) |
| 2034 | goto fail_unregister; | ||
| 2035 | |||
| 2036 | error = request_irq(IRQ_AMIGA_RBF, ser_rx_int, IRQF_DISABLED, | ||
| 2037 | "serial RX", state); | ||
| 2038 | if (error) | ||
| 2039 | goto fail_free_irq; | ||
| 2029 | 2040 | ||
| 2030 | /* turn off Rx and Tx interrupts */ | 2041 | /* turn off Rx and Tx interrupts */ |
| 2031 | custom.intena = IF_RBF | IF_TBE; | 2042 | custom.intena = IF_RBF | IF_TBE; |
| @@ -2045,6 +2056,16 @@ static int __init rs_init(void) | |||
| 2045 | ciab.ddra &= ~(SER_DCD | SER_CTS | SER_DSR); /* inputs */ | 2056 | ciab.ddra &= ~(SER_DCD | SER_CTS | SER_DSR); /* inputs */ |
| 2046 | 2057 | ||
| 2047 | return 0; | 2058 | return 0; |
| 2059 | |||
| 2060 | fail_free_irq: | ||
| 2061 | free_irq(IRQ_AMIGA_TBE, state); | ||
| 2062 | fail_unregister: | ||
| 2063 | tty_unregister_driver(serial_driver); | ||
| 2064 | fail_release_mem_region: | ||
| 2065 | release_mem_region(CUSTOM_PHYSADDR+0x30, 4); | ||
| 2066 | fail_put_tty_driver: | ||
| 2067 | put_tty_driver(serial_driver); | ||
| 2068 | return error; | ||
| 2048 | } | 2069 | } |
| 2049 | 2070 | ||
| 2050 | static __exit void rs_exit(void) | 2071 | static __exit void rs_exit(void) |
| @@ -2064,6 +2085,9 @@ static __exit void rs_exit(void) | |||
| 2064 | kfree(info); | 2085 | kfree(info); |
| 2065 | } | 2086 | } |
| 2066 | 2087 | ||
| 2088 | free_irq(IRQ_AMIGA_TBE, rs_table); | ||
| 2089 | free_irq(IRQ_AMIGA_RBF, rs_table); | ||
| 2090 | |||
| 2067 | release_mem_region(CUSTOM_PHYSADDR+0x30, 4); | 2091 | release_mem_region(CUSTOM_PHYSADDR+0x30, 4); |
| 2068 | } | 2092 | } |
| 2069 | 2093 | ||
diff --git a/drivers/char/pty.c b/drivers/char/pty.c index 146c97613da0..31038a0052a2 100644 --- a/drivers/char/pty.c +++ b/drivers/char/pty.c | |||
| @@ -230,9 +230,7 @@ static void pty_set_termios(struct tty_struct *tty, | |||
| 230 | /** | 230 | /** |
| 231 | * pty_do_resize - resize event | 231 | * pty_do_resize - resize event |
| 232 | * @tty: tty being resized | 232 | * @tty: tty being resized |
| 233 | * @real_tty: real tty (not the same as tty if using a pty/tty pair) | 233 | * @ws: window size being set. |
| 234 | * @rows: rows (character) | ||
| 235 | * @cols: cols (character) | ||
| 236 | * | 234 | * |
| 237 | * Update the termios variables and send the neccessary signals to | 235 | * Update the termios variables and send the neccessary signals to |
| 238 | * peform a terminal resize correctly | 236 | * peform a terminal resize correctly |
diff --git a/drivers/char/ser_a2232.c b/drivers/char/ser_a2232.c index 33872a219df6..33a2b531802e 100644 --- a/drivers/char/ser_a2232.c +++ b/drivers/char/ser_a2232.c | |||
| @@ -718,6 +718,7 @@ static int __init a2232board_init(void) | |||
| 718 | u_char *from; | 718 | u_char *from; |
| 719 | volatile u_char *to; | 719 | volatile u_char *to; |
| 720 | volatile struct a2232memory *mem; | 720 | volatile struct a2232memory *mem; |
| 721 | int error, i; | ||
| 721 | 722 | ||
| 722 | #ifdef CONFIG_SMP | 723 | #ifdef CONFIG_SMP |
| 723 | return -ENODEV; /* This driver is not SMP aware. Is there an SMP ZorroII-bus-machine? */ | 724 | return -ENODEV; /* This driver is not SMP aware. Is there an SMP ZorroII-bus-machine? */ |
| @@ -797,8 +798,15 @@ static int __init a2232board_init(void) | |||
| 797 | */ | 798 | */ |
| 798 | if (a2232_init_drivers()) return -ENODEV; // maybe we should use a different -Exxx? | 799 | if (a2232_init_drivers()) return -ENODEV; // maybe we should use a different -Exxx? |
| 799 | 800 | ||
| 800 | request_irq(IRQ_AMIGA_VERTB, a2232_vbl_inter, 0, "A2232 serial VBL", a2232_driver_ID); | 801 | error = request_irq(IRQ_AMIGA_VERTB, a2232_vbl_inter, 0, |
| 801 | return 0; | 802 | "A2232 serial VBL", a2232_driver_ID); |
| 803 | if (error) { | ||
| 804 | for (i = 0; i < nr_a2232; i++) | ||
| 805 | zorro_release_device(zd_a2232[i]); | ||
| 806 | tty_unregister_driver(a2232_driver); | ||
| 807 | put_tty_driver(a2232_driver); | ||
| 808 | } | ||
| 809 | return error; | ||
| 802 | } | 810 | } |
| 803 | 811 | ||
| 804 | static void __exit a2232board_exit(void) | 812 | static void __exit a2232board_exit(void) |
diff --git a/drivers/char/vme_scc.c b/drivers/char/vme_scc.c index 0e8234bd0e19..994e1a58b987 100644 --- a/drivers/char/vme_scc.c +++ b/drivers/char/vme_scc.c | |||
| @@ -198,6 +198,7 @@ static void scc_init_portstructs(void) | |||
| 198 | static int mvme147_scc_init(void) | 198 | static int mvme147_scc_init(void) |
| 199 | { | 199 | { |
| 200 | struct scc_port *port; | 200 | struct scc_port *port; |
| 201 | int error; | ||
| 201 | 202 | ||
| 202 | printk(KERN_INFO "SCC: MVME147 Serial Driver\n"); | 203 | printk(KERN_INFO "SCC: MVME147 Serial Driver\n"); |
| 203 | /* Init channel A */ | 204 | /* Init channel A */ |
| @@ -207,14 +208,23 @@ static int mvme147_scc_init(void) | |||
| 207 | port->datap = port->ctrlp + 1; | 208 | port->datap = port->ctrlp + 1; |
| 208 | port->port_a = &scc_ports[0]; | 209 | port->port_a = &scc_ports[0]; |
| 209 | port->port_b = &scc_ports[1]; | 210 | port->port_b = &scc_ports[1]; |
| 210 | request_irq(MVME147_IRQ_SCCA_TX, scc_tx_int, IRQF_DISABLED, | 211 | error = request_irq(MVME147_IRQ_SCCA_TX, scc_tx_int, IRQF_DISABLED, |
| 211 | "SCC-A TX", port); | 212 | "SCC-A TX", port); |
| 212 | request_irq(MVME147_IRQ_SCCA_STAT, scc_stat_int, IRQF_DISABLED, | 213 | if (error) |
| 214 | goto fail; | ||
| 215 | error = request_irq(MVME147_IRQ_SCCA_STAT, scc_stat_int, IRQF_DISABLED, | ||
| 213 | "SCC-A status", port); | 216 | "SCC-A status", port); |
| 214 | request_irq(MVME147_IRQ_SCCA_RX, scc_rx_int, IRQF_DISABLED, | 217 | if (error) |
| 218 | goto fail_free_a_tx; | ||
| 219 | error = request_irq(MVME147_IRQ_SCCA_RX, scc_rx_int, IRQF_DISABLED, | ||
| 215 | "SCC-A RX", port); | 220 | "SCC-A RX", port); |
| 216 | request_irq(MVME147_IRQ_SCCA_SPCOND, scc_spcond_int, IRQF_DISABLED, | 221 | if (error) |
| 217 | "SCC-A special cond", port); | 222 | goto fail_free_a_stat; |
| 223 | error = request_irq(MVME147_IRQ_SCCA_SPCOND, scc_spcond_int, | ||
| 224 | IRQF_DISABLED, "SCC-A special cond", port); | ||
| 225 | if (error) | ||
| 226 | goto fail_free_a_rx; | ||
| 227 | |||
| 218 | { | 228 | { |
| 219 | SCC_ACCESS_INIT(port); | 229 | SCC_ACCESS_INIT(port); |
| 220 | 230 | ||
| @@ -234,14 +244,23 @@ static int mvme147_scc_init(void) | |||
| 234 | port->datap = port->ctrlp + 1; | 244 | port->datap = port->ctrlp + 1; |
| 235 | port->port_a = &scc_ports[0]; | 245 | port->port_a = &scc_ports[0]; |
| 236 | port->port_b = &scc_ports[1]; | 246 | port->port_b = &scc_ports[1]; |
| 237 | request_irq(MVME147_IRQ_SCCB_TX, scc_tx_int, IRQF_DISABLED, | 247 | error = request_irq(MVME147_IRQ_SCCB_TX, scc_tx_int, IRQF_DISABLED, |
| 238 | "SCC-B TX", port); | 248 | "SCC-B TX", port); |
| 239 | request_irq(MVME147_IRQ_SCCB_STAT, scc_stat_int, IRQF_DISABLED, | 249 | if (error) |
| 250 | goto fail_free_a_spcond; | ||
| 251 | error = request_irq(MVME147_IRQ_SCCB_STAT, scc_stat_int, IRQF_DISABLED, | ||
| 240 | "SCC-B status", port); | 252 | "SCC-B status", port); |
| 241 | request_irq(MVME147_IRQ_SCCB_RX, scc_rx_int, IRQF_DISABLED, | 253 | if (error) |
| 254 | goto fail_free_b_tx; | ||
| 255 | error = request_irq(MVME147_IRQ_SCCB_RX, scc_rx_int, IRQF_DISABLED, | ||
| 242 | "SCC-B RX", port); | 256 | "SCC-B RX", port); |
| 243 | request_irq(MVME147_IRQ_SCCB_SPCOND, scc_spcond_int, IRQF_DISABLED, | 257 | if (error) |
| 244 | "SCC-B special cond", port); | 258 | goto fail_free_b_stat; |
| 259 | error = request_irq(MVME147_IRQ_SCCB_SPCOND, scc_spcond_int, | ||
| 260 | IRQF_DISABLED, "SCC-B special cond", port); | ||
| 261 | if (error) | ||
| 262 | goto fail_free_b_rx; | ||
| 263 | |||
| 245 | { | 264 | { |
| 246 | SCC_ACCESS_INIT(port); | 265 | SCC_ACCESS_INIT(port); |
| 247 | 266 | ||
| @@ -257,6 +276,23 @@ static int mvme147_scc_init(void) | |||
| 257 | scc_init_drivers(); | 276 | scc_init_drivers(); |
| 258 | 277 | ||
| 259 | return 0; | 278 | return 0; |
| 279 | |||
| 280 | fail_free_b_rx: | ||
| 281 | free_irq(MVME147_IRQ_SCCB_RX, port); | ||
| 282 | fail_free_b_stat: | ||
| 283 | free_irq(MVME147_IRQ_SCCB_STAT, port); | ||
| 284 | fail_free_b_tx: | ||
| 285 | free_irq(MVME147_IRQ_SCCB_TX, port); | ||
| 286 | fail_free_a_spcond: | ||
| 287 | free_irq(MVME147_IRQ_SCCA_SPCOND, port); | ||
| 288 | fail_free_a_rx: | ||
| 289 | free_irq(MVME147_IRQ_SCCA_RX, port); | ||
| 290 | fail_free_a_stat: | ||
| 291 | free_irq(MVME147_IRQ_SCCA_STAT, port); | ||
| 292 | fail_free_a_tx: | ||
| 293 | free_irq(MVME147_IRQ_SCCA_TX, port); | ||
| 294 | fail: | ||
| 295 | return error; | ||
| 260 | } | 296 | } |
| 261 | #endif | 297 | #endif |
| 262 | 298 | ||
| @@ -265,6 +301,7 @@ static int mvme147_scc_init(void) | |||
| 265 | static int mvme162_scc_init(void) | 301 | static int mvme162_scc_init(void) |
| 266 | { | 302 | { |
| 267 | struct scc_port *port; | 303 | struct scc_port *port; |
| 304 | int error; | ||
| 268 | 305 | ||
| 269 | if (!(mvme16x_config & MVME16x_CONFIG_GOT_SCCA)) | 306 | if (!(mvme16x_config & MVME16x_CONFIG_GOT_SCCA)) |
| 270 | return (-ENODEV); | 307 | return (-ENODEV); |
| @@ -277,14 +314,23 @@ static int mvme162_scc_init(void) | |||
| 277 | port->datap = port->ctrlp + 2; | 314 | port->datap = port->ctrlp + 2; |
| 278 | port->port_a = &scc_ports[0]; | 315 | port->port_a = &scc_ports[0]; |
| 279 | port->port_b = &scc_ports[1]; | 316 | port->port_b = &scc_ports[1]; |
| 280 | request_irq(MVME162_IRQ_SCCA_TX, scc_tx_int, IRQF_DISABLED, | 317 | error = request_irq(MVME162_IRQ_SCCA_TX, scc_tx_int, IRQF_DISABLED, |
| 281 | "SCC-A TX", port); | 318 | "SCC-A TX", port); |
| 282 | request_irq(MVME162_IRQ_SCCA_STAT, scc_stat_int, IRQF_DISABLED, | 319 | if (error) |
| 320 | goto fail; | ||
| 321 | error = request_irq(MVME162_IRQ_SCCA_STAT, scc_stat_int, IRQF_DISABLED, | ||
| 283 | "SCC-A status", port); | 322 | "SCC-A status", port); |
| 284 | request_irq(MVME162_IRQ_SCCA_RX, scc_rx_int, IRQF_DISABLED, | 323 | if (error) |
| 324 | goto fail_free_a_tx; | ||
| 325 | error = request_irq(MVME162_IRQ_SCCA_RX, scc_rx_int, IRQF_DISABLED, | ||
| 285 | "SCC-A RX", port); | 326 | "SCC-A RX", port); |
| 286 | request_irq(MVME162_IRQ_SCCA_SPCOND, scc_spcond_int, IRQF_DISABLED, | 327 | if (error) |
| 287 | "SCC-A special cond", port); | 328 | goto fail_free_a_stat; |
| 329 | error = request_irq(MVME162_IRQ_SCCA_SPCOND, scc_spcond_int, | ||
| 330 | IRQF_DISABLED, "SCC-A special cond", port); | ||
| 331 | if (error) | ||
| 332 | goto fail_free_a_rx; | ||
| 333 | |||
| 288 | { | 334 | { |
| 289 | SCC_ACCESS_INIT(port); | 335 | SCC_ACCESS_INIT(port); |
| 290 | 336 | ||
| @@ -304,14 +350,22 @@ static int mvme162_scc_init(void) | |||
| 304 | port->datap = port->ctrlp + 2; | 350 | port->datap = port->ctrlp + 2; |
| 305 | port->port_a = &scc_ports[0]; | 351 | port->port_a = &scc_ports[0]; |
| 306 | port->port_b = &scc_ports[1]; | 352 | port->port_b = &scc_ports[1]; |
| 307 | request_irq(MVME162_IRQ_SCCB_TX, scc_tx_int, IRQF_DISABLED, | 353 | error = request_irq(MVME162_IRQ_SCCB_TX, scc_tx_int, IRQF_DISABLED, |
| 308 | "SCC-B TX", port); | 354 | "SCC-B TX", port); |
| 309 | request_irq(MVME162_IRQ_SCCB_STAT, scc_stat_int, IRQF_DISABLED, | 355 | if (error) |
| 356 | goto fail_free_a_spcond; | ||
| 357 | error = request_irq(MVME162_IRQ_SCCB_STAT, scc_stat_int, IRQF_DISABLED, | ||
| 310 | "SCC-B status", port); | 358 | "SCC-B status", port); |
| 311 | request_irq(MVME162_IRQ_SCCB_RX, scc_rx_int, IRQF_DISABLED, | 359 | if (error) |
| 360 | goto fail_free_b_tx; | ||
| 361 | error = request_irq(MVME162_IRQ_SCCB_RX, scc_rx_int, IRQF_DISABLED, | ||
| 312 | "SCC-B RX", port); | 362 | "SCC-B RX", port); |
| 313 | request_irq(MVME162_IRQ_SCCB_SPCOND, scc_spcond_int, IRQF_DISABLED, | 363 | if (error) |
| 314 | "SCC-B special cond", port); | 364 | goto fail_free_b_stat; |
| 365 | error = request_irq(MVME162_IRQ_SCCB_SPCOND, scc_spcond_int, | ||
| 366 | IRQF_DISABLED, "SCC-B special cond", port); | ||
| 367 | if (error) | ||
| 368 | goto fail_free_b_rx; | ||
| 315 | 369 | ||
| 316 | { | 370 | { |
| 317 | SCC_ACCESS_INIT(port); /* Either channel will do */ | 371 | SCC_ACCESS_INIT(port); /* Either channel will do */ |
| @@ -328,6 +382,23 @@ static int mvme162_scc_init(void) | |||
| 328 | scc_init_drivers(); | 382 | scc_init_drivers(); |
| 329 | 383 | ||
| 330 | return 0; | 384 | return 0; |
| 385 | |||
| 386 | fail_free_b_rx: | ||
| 387 | free_irq(MVME162_IRQ_SCCB_RX, port); | ||
| 388 | fail_free_b_stat: | ||
| 389 | free_irq(MVME162_IRQ_SCCB_STAT, port); | ||
| 390 | fail_free_b_tx: | ||
| 391 | free_irq(MVME162_IRQ_SCCB_TX, port); | ||
| 392 | fail_free_a_spcond: | ||
| 393 | free_irq(MVME162_IRQ_SCCA_SPCOND, port); | ||
| 394 | fail_free_a_rx: | ||
| 395 | free_irq(MVME162_IRQ_SCCA_RX, port); | ||
| 396 | fail_free_a_stat: | ||
| 397 | free_irq(MVME162_IRQ_SCCA_STAT, port); | ||
| 398 | fail_free_a_tx: | ||
| 399 | free_irq(MVME162_IRQ_SCCA_TX, port); | ||
| 400 | fail: | ||
| 401 | return error; | ||
| 331 | } | 402 | } |
| 332 | #endif | 403 | #endif |
| 333 | 404 | ||
| @@ -336,6 +407,7 @@ static int mvme162_scc_init(void) | |||
| 336 | static int bvme6000_scc_init(void) | 407 | static int bvme6000_scc_init(void) |
| 337 | { | 408 | { |
| 338 | struct scc_port *port; | 409 | struct scc_port *port; |
| 410 | int error; | ||
| 339 | 411 | ||
| 340 | printk(KERN_INFO "SCC: BVME6000 Serial Driver\n"); | 412 | printk(KERN_INFO "SCC: BVME6000 Serial Driver\n"); |
| 341 | /* Init channel A */ | 413 | /* Init channel A */ |
| @@ -345,14 +417,23 @@ static int bvme6000_scc_init(void) | |||
| 345 | port->datap = port->ctrlp + 4; | 417 | port->datap = port->ctrlp + 4; |
| 346 | port->port_a = &scc_ports[0]; | 418 | port->port_a = &scc_ports[0]; |
| 347 | port->port_b = &scc_ports[1]; | 419 | port->port_b = &scc_ports[1]; |
| 348 | request_irq(BVME_IRQ_SCCA_TX, scc_tx_int, IRQF_DISABLED, | 420 | error = request_irq(BVME_IRQ_SCCA_TX, scc_tx_int, IRQF_DISABLED, |
| 349 | "SCC-A TX", port); | 421 | "SCC-A TX", port); |
| 350 | request_irq(BVME_IRQ_SCCA_STAT, scc_stat_int, IRQF_DISABLED, | 422 | if (error) |
| 423 | goto fail; | ||
| 424 | error = request_irq(BVME_IRQ_SCCA_STAT, scc_stat_int, IRQF_DISABLED, | ||
| 351 | "SCC-A status", port); | 425 | "SCC-A status", port); |
| 352 | request_irq(BVME_IRQ_SCCA_RX, scc_rx_int, IRQF_DISABLED, | 426 | if (error) |
| 427 | goto fail_free_a_tx; | ||
| 428 | error = request_irq(BVME_IRQ_SCCA_RX, scc_rx_int, IRQF_DISABLED, | ||
| 353 | "SCC-A RX", port); | 429 | "SCC-A RX", port); |
| 354 | request_irq(BVME_IRQ_SCCA_SPCOND, scc_spcond_int, IRQF_DISABLED, | 430 | if (error) |
| 355 | "SCC-A special cond", port); | 431 | goto fail_free_a_stat; |
| 432 | error = request_irq(BVME_IRQ_SCCA_SPCOND, scc_spcond_int, | ||
| 433 | IRQF_DISABLED, "SCC-A special cond", port); | ||
| 434 | if (error) | ||
| 435 | goto fail_free_a_rx; | ||
| 436 | |||
| 356 | { | 437 | { |
| 357 | SCC_ACCESS_INIT(port); | 438 | SCC_ACCESS_INIT(port); |
| 358 | 439 | ||
| @@ -372,14 +453,22 @@ static int bvme6000_scc_init(void) | |||
| 372 | port->datap = port->ctrlp + 4; | 453 | port->datap = port->ctrlp + 4; |
| 373 | port->port_a = &scc_ports[0]; | 454 | port->port_a = &scc_ports[0]; |
| 374 | port->port_b = &scc_ports[1]; | 455 | port->port_b = &scc_ports[1]; |
| 375 | request_irq(BVME_IRQ_SCCB_TX, scc_tx_int, IRQF_DISABLED, | 456 | error = request_irq(BVME_IRQ_SCCB_TX, scc_tx_int, IRQF_DISABLED, |
| 376 | "SCC-B TX", port); | 457 | "SCC-B TX", port); |
| 377 | request_irq(BVME_IRQ_SCCB_STAT, scc_stat_int, IRQF_DISABLED, | 458 | if (error) |
| 459 | goto fail_free_a_spcond; | ||
| 460 | error = request_irq(BVME_IRQ_SCCB_STAT, scc_stat_int, IRQF_DISABLED, | ||
| 378 | "SCC-B status", port); | 461 | "SCC-B status", port); |
| 379 | request_irq(BVME_IRQ_SCCB_RX, scc_rx_int, IRQF_DISABLED, | 462 | if (error) |
| 463 | goto fail_free_b_tx; | ||
| 464 | error = request_irq(BVME_IRQ_SCCB_RX, scc_rx_int, IRQF_DISABLED, | ||
| 380 | "SCC-B RX", port); | 465 | "SCC-B RX", port); |
| 381 | request_irq(BVME_IRQ_SCCB_SPCOND, scc_spcond_int, IRQF_DISABLED, | 466 | if (error) |
| 382 | "SCC-B special cond", port); | 467 | goto fail_free_b_stat; |
| 468 | error = request_irq(BVME_IRQ_SCCB_SPCOND, scc_spcond_int, | ||
| 469 | IRQF_DISABLED, "SCC-B special cond", port); | ||
| 470 | if (error) | ||
| 471 | goto fail_free_b_rx; | ||
| 383 | 472 | ||
| 384 | { | 473 | { |
| 385 | SCC_ACCESS_INIT(port); /* Either channel will do */ | 474 | SCC_ACCESS_INIT(port); /* Either channel will do */ |
| @@ -393,6 +482,23 @@ static int bvme6000_scc_init(void) | |||
| 393 | scc_init_drivers(); | 482 | scc_init_drivers(); |
| 394 | 483 | ||
| 395 | return 0; | 484 | return 0; |
| 485 | |||
| 486 | fail: | ||
| 487 | free_irq(BVME_IRQ_SCCA_STAT, port); | ||
| 488 | fail_free_a_tx: | ||
| 489 | free_irq(BVME_IRQ_SCCA_RX, port); | ||
| 490 | fail_free_a_stat: | ||
| 491 | free_irq(BVME_IRQ_SCCA_SPCOND, port); | ||
| 492 | fail_free_a_rx: | ||
| 493 | free_irq(BVME_IRQ_SCCB_TX, port); | ||
| 494 | fail_free_a_spcond: | ||
| 495 | free_irq(BVME_IRQ_SCCB_STAT, port); | ||
| 496 | fail_free_b_tx: | ||
| 497 | free_irq(BVME_IRQ_SCCB_RX, port); | ||
| 498 | fail_free_b_stat: | ||
| 499 | free_irq(BVME_IRQ_SCCB_SPCOND, port); | ||
| 500 | fail_free_b_rx: | ||
| 501 | return error; | ||
| 396 | } | 502 | } |
| 397 | #endif | 503 | #endif |
| 398 | 504 | ||
diff --git a/drivers/dio/dio-sysfs.c b/drivers/dio/dio-sysfs.c index f46463038847..ee1a3b59bd4e 100644 --- a/drivers/dio/dio-sysfs.c +++ b/drivers/dio/dio-sysfs.c | |||
| @@ -58,20 +58,25 @@ static ssize_t dio_show_resource(struct device *dev, struct device_attribute *at | |||
| 58 | struct dio_dev *d = to_dio_dev(dev); | 58 | struct dio_dev *d = to_dio_dev(dev); |
| 59 | 59 | ||
| 60 | return sprintf(buf, "0x%08lx 0x%08lx 0x%08lx\n", | 60 | return sprintf(buf, "0x%08lx 0x%08lx 0x%08lx\n", |
| 61 | dio_resource_start(d), dio_resource_end(d), | 61 | (unsigned long)dio_resource_start(d), |
| 62 | (unsigned long)dio_resource_end(d), | ||
| 62 | dio_resource_flags(d)); | 63 | dio_resource_flags(d)); |
| 63 | } | 64 | } |
| 64 | static DEVICE_ATTR(resource, S_IRUGO, dio_show_resource, NULL); | 65 | static DEVICE_ATTR(resource, S_IRUGO, dio_show_resource, NULL); |
| 65 | 66 | ||
| 66 | void dio_create_sysfs_dev_files(struct dio_dev *d) | 67 | int dio_create_sysfs_dev_files(struct dio_dev *d) |
| 67 | { | 68 | { |
| 68 | struct device *dev = &d->dev; | 69 | struct device *dev = &d->dev; |
| 70 | int error; | ||
| 69 | 71 | ||
| 70 | /* current configuration's attributes */ | 72 | /* current configuration's attributes */ |
| 71 | device_create_file(dev, &dev_attr_id); | 73 | if ((error = device_create_file(dev, &dev_attr_id)) || |
| 72 | device_create_file(dev, &dev_attr_ipl); | 74 | (error = device_create_file(dev, &dev_attr_ipl)) || |
| 73 | device_create_file(dev, &dev_attr_secid); | 75 | (error = device_create_file(dev, &dev_attr_secid)) || |
| 74 | device_create_file(dev, &dev_attr_name); | 76 | (error = device_create_file(dev, &dev_attr_name)) || |
| 75 | device_create_file(dev, &dev_attr_resource); | 77 | (error = device_create_file(dev, &dev_attr_resource))) |
| 78 | return error; | ||
| 79 | |||
| 80 | return 0; | ||
| 76 | } | 81 | } |
| 77 | 82 | ||
diff --git a/drivers/dio/dio.c b/drivers/dio/dio.c index 07f274f853d9..10c3c498358c 100644 --- a/drivers/dio/dio.c +++ b/drivers/dio/dio.c | |||
| @@ -173,6 +173,7 @@ static int __init dio_init(void) | |||
| 173 | mm_segment_t fs; | 173 | mm_segment_t fs; |
| 174 | int i; | 174 | int i; |
| 175 | struct dio_dev *dev; | 175 | struct dio_dev *dev; |
| 176 | int error; | ||
| 176 | 177 | ||
| 177 | if (!MACH_IS_HP300) | 178 | if (!MACH_IS_HP300) |
| 178 | return 0; | 179 | return 0; |
| @@ -182,7 +183,11 @@ static int __init dio_init(void) | |||
| 182 | /* Initialize the DIO bus */ | 183 | /* Initialize the DIO bus */ |
| 183 | INIT_LIST_HEAD(&dio_bus.devices); | 184 | INIT_LIST_HEAD(&dio_bus.devices); |
| 184 | strcpy(dio_bus.dev.bus_id, "dio"); | 185 | strcpy(dio_bus.dev.bus_id, "dio"); |
| 185 | device_register(&dio_bus.dev); | 186 | error = device_register(&dio_bus.dev); |
| 187 | if (error) { | ||
| 188 | pr_err("DIO: Error registering dio_bus\n"); | ||
| 189 | return error; | ||
| 190 | } | ||
| 186 | 191 | ||
| 187 | /* Request all resources */ | 192 | /* Request all resources */ |
| 188 | dio_bus.num_resources = (hp300_model == HP_320 ? 1 : 2); | 193 | dio_bus.num_resources = (hp300_model == HP_320 ? 1 : 2); |
| @@ -252,8 +257,15 @@ static int __init dio_init(void) | |||
| 252 | 257 | ||
| 253 | if (scode >= DIOII_SCBASE) | 258 | if (scode >= DIOII_SCBASE) |
| 254 | iounmap(va); | 259 | iounmap(va); |
| 255 | device_register(&dev->dev); | 260 | error = device_register(&dev->dev); |
| 256 | dio_create_sysfs_dev_files(dev); | 261 | if (error) { |
| 262 | pr_err("DIO: Error registering device %s\n", | ||
| 263 | dev->name); | ||
| 264 | continue; | ||
| 265 | } | ||
| 266 | error = dio_create_sysfs_dev_files(dev); | ||
| 267 | if (error) | ||
| 268 | dev_err(&dev->dev, "Error creating sysfs files\n"); | ||
| 257 | } | 269 | } |
| 258 | return 0; | 270 | return 0; |
| 259 | } | 271 | } |
diff --git a/drivers/infiniband/hw/ehca/ehca_main.c b/drivers/infiniband/hw/ehca/ehca_main.c index 3b77b674cbf6..c7b8a506af65 100644 --- a/drivers/infiniband/hw/ehca/ehca_main.c +++ b/drivers/infiniband/hw/ehca/ehca_main.c | |||
| @@ -955,7 +955,7 @@ void ehca_poll_eqs(unsigned long data) | |||
| 955 | struct ehca_eq *eq = &shca->eq; | 955 | struct ehca_eq *eq = &shca->eq; |
| 956 | int max = 3; | 956 | int max = 3; |
| 957 | volatile u64 q_ofs, q_ofs2; | 957 | volatile u64 q_ofs, q_ofs2; |
| 958 | u64 flags; | 958 | unsigned long flags; |
| 959 | spin_lock_irqsave(&eq->spinlock, flags); | 959 | spin_lock_irqsave(&eq->spinlock, flags); |
| 960 | q_ofs = eq->ipz_queue.current_q_offset; | 960 | q_ofs = eq->ipz_queue.current_q_offset; |
| 961 | spin_unlock_irqrestore(&eq->spinlock, flags); | 961 | spin_unlock_irqrestore(&eq->spinlock, flags); |
diff --git a/drivers/infiniband/hw/mlx4/main.c b/drivers/infiniband/hw/mlx4/main.c index dcefe1fceb5c..61588bd273bd 100644 --- a/drivers/infiniband/hw/mlx4/main.c +++ b/drivers/infiniband/hw/mlx4/main.c | |||
| @@ -543,14 +543,21 @@ static void *mlx4_ib_add(struct mlx4_dev *dev) | |||
| 543 | { | 543 | { |
| 544 | static int mlx4_ib_version_printed; | 544 | static int mlx4_ib_version_printed; |
| 545 | struct mlx4_ib_dev *ibdev; | 545 | struct mlx4_ib_dev *ibdev; |
| 546 | int num_ports = 0; | ||
| 546 | int i; | 547 | int i; |
| 547 | 548 | ||
| 548 | |||
| 549 | if (!mlx4_ib_version_printed) { | 549 | if (!mlx4_ib_version_printed) { |
| 550 | printk(KERN_INFO "%s", mlx4_ib_version); | 550 | printk(KERN_INFO "%s", mlx4_ib_version); |
| 551 | ++mlx4_ib_version_printed; | 551 | ++mlx4_ib_version_printed; |
| 552 | } | 552 | } |
| 553 | 553 | ||
| 554 | mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) | ||
| 555 | num_ports++; | ||
| 556 | |||
| 557 | /* No point in registering a device with no ports... */ | ||
| 558 | if (num_ports == 0) | ||
| 559 | return NULL; | ||
| 560 | |||
| 554 | ibdev = (struct mlx4_ib_dev *) ib_alloc_device(sizeof *ibdev); | 561 | ibdev = (struct mlx4_ib_dev *) ib_alloc_device(sizeof *ibdev); |
| 555 | if (!ibdev) { | 562 | if (!ibdev) { |
| 556 | dev_err(&dev->pdev->dev, "Device struct alloc failed\n"); | 563 | dev_err(&dev->pdev->dev, "Device struct alloc failed\n"); |
| @@ -574,9 +581,7 @@ static void *mlx4_ib_add(struct mlx4_dev *dev) | |||
| 574 | ibdev->ib_dev.owner = THIS_MODULE; | 581 | ibdev->ib_dev.owner = THIS_MODULE; |
| 575 | ibdev->ib_dev.node_type = RDMA_NODE_IB_CA; | 582 | ibdev->ib_dev.node_type = RDMA_NODE_IB_CA; |
| 576 | ibdev->ib_dev.local_dma_lkey = dev->caps.reserved_lkey; | 583 | ibdev->ib_dev.local_dma_lkey = dev->caps.reserved_lkey; |
| 577 | ibdev->num_ports = 0; | 584 | ibdev->num_ports = num_ports; |
| 578 | mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) | ||
| 579 | ibdev->num_ports++; | ||
| 580 | ibdev->ib_dev.phys_port_cnt = ibdev->num_ports; | 585 | ibdev->ib_dev.phys_port_cnt = ibdev->num_ports; |
| 581 | ibdev->ib_dev.num_comp_vectors = dev->caps.num_comp_vectors; | 586 | ibdev->ib_dev.num_comp_vectors = dev->caps.num_comp_vectors; |
| 582 | ibdev->ib_dev.dma_device = &dev->pdev->dev; | 587 | ibdev->ib_dev.dma_device = &dev->pdev->dev; |
diff --git a/drivers/infiniband/hw/nes/nes_cm.c b/drivers/infiniband/hw/nes/nes_cm.c index 6ba57e91d7ab..a01b4488208b 100644 --- a/drivers/infiniband/hw/nes/nes_cm.c +++ b/drivers/infiniband/hw/nes/nes_cm.c | |||
| @@ -778,12 +778,13 @@ static struct nes_cm_node *find_node(struct nes_cm_core *cm_core, | |||
| 778 | unsigned long flags; | 778 | unsigned long flags; |
| 779 | struct list_head *hte; | 779 | struct list_head *hte; |
| 780 | struct nes_cm_node *cm_node; | 780 | struct nes_cm_node *cm_node; |
| 781 | __be32 tmp_addr = cpu_to_be32(loc_addr); | ||
| 781 | 782 | ||
| 782 | /* get a handle on the hte */ | 783 | /* get a handle on the hte */ |
| 783 | hte = &cm_core->connected_nodes; | 784 | hte = &cm_core->connected_nodes; |
| 784 | 785 | ||
| 785 | nes_debug(NES_DBG_CM, "Searching for an owner node: %pI4:%x from core %p->%p\n", | 786 | nes_debug(NES_DBG_CM, "Searching for an owner node: %pI4:%x from core %p->%p\n", |
| 786 | &loc_addr, loc_port, cm_core, hte); | 787 | &tmp_addr, loc_port, cm_core, hte); |
| 787 | 788 | ||
| 788 | /* walk list and find cm_node associated with this session ID */ | 789 | /* walk list and find cm_node associated with this session ID */ |
| 789 | spin_lock_irqsave(&cm_core->ht_lock, flags); | 790 | spin_lock_irqsave(&cm_core->ht_lock, flags); |
| @@ -816,6 +817,7 @@ static struct nes_cm_listener *find_listener(struct nes_cm_core *cm_core, | |||
| 816 | { | 817 | { |
| 817 | unsigned long flags; | 818 | unsigned long flags; |
| 818 | struct nes_cm_listener *listen_node; | 819 | struct nes_cm_listener *listen_node; |
| 820 | __be32 tmp_addr = cpu_to_be32(dst_addr); | ||
| 819 | 821 | ||
| 820 | /* walk list and find cm_node associated with this session ID */ | 822 | /* walk list and find cm_node associated with this session ID */ |
| 821 | spin_lock_irqsave(&cm_core->listen_list_lock, flags); | 823 | spin_lock_irqsave(&cm_core->listen_list_lock, flags); |
| @@ -833,7 +835,7 @@ static struct nes_cm_listener *find_listener(struct nes_cm_core *cm_core, | |||
| 833 | spin_unlock_irqrestore(&cm_core->listen_list_lock, flags); | 835 | spin_unlock_irqrestore(&cm_core->listen_list_lock, flags); |
| 834 | 836 | ||
| 835 | nes_debug(NES_DBG_CM, "Unable to find listener for %pI4:%x\n", | 837 | nes_debug(NES_DBG_CM, "Unable to find listener for %pI4:%x\n", |
| 836 | &dst_addr, dst_port); | 838 | &tmp_addr, dst_port); |
| 837 | 839 | ||
| 838 | /* no listener */ | 840 | /* no listener */ |
| 839 | return NULL; | 841 | return NULL; |
| @@ -2059,6 +2061,7 @@ static int mini_cm_recv_pkt(struct nes_cm_core *cm_core, | |||
| 2059 | struct tcphdr *tcph; | 2061 | struct tcphdr *tcph; |
| 2060 | struct nes_cm_info nfo; | 2062 | struct nes_cm_info nfo; |
| 2061 | int skb_handled = 1; | 2063 | int skb_handled = 1; |
| 2064 | __be32 tmp_daddr, tmp_saddr; | ||
| 2062 | 2065 | ||
| 2063 | if (!skb) | 2066 | if (!skb) |
| 2064 | return 0; | 2067 | return 0; |
| @@ -2074,8 +2077,11 @@ static int mini_cm_recv_pkt(struct nes_cm_core *cm_core, | |||
| 2074 | nfo.rem_addr = ntohl(iph->saddr); | 2077 | nfo.rem_addr = ntohl(iph->saddr); |
| 2075 | nfo.rem_port = ntohs(tcph->source); | 2078 | nfo.rem_port = ntohs(tcph->source); |
| 2076 | 2079 | ||
| 2080 | tmp_daddr = cpu_to_be32(iph->daddr); | ||
| 2081 | tmp_saddr = cpu_to_be32(iph->saddr); | ||
| 2082 | |||
| 2077 | nes_debug(NES_DBG_CM, "Received packet: dest=%pI4:0x%04X src=%pI4:0x%04X\n", | 2083 | nes_debug(NES_DBG_CM, "Received packet: dest=%pI4:0x%04X src=%pI4:0x%04X\n", |
| 2078 | &iph->daddr, tcph->dest, &iph->saddr, tcph->source); | 2084 | &tmp_daddr, tcph->dest, &tmp_saddr, tcph->source); |
| 2079 | 2085 | ||
| 2080 | do { | 2086 | do { |
| 2081 | cm_node = find_node(cm_core, | 2087 | cm_node = find_node(cm_core, |
diff --git a/drivers/infiniband/hw/nes/nes_utils.c b/drivers/infiniband/hw/nes/nes_utils.c index aa9b7348c728..6f3bc1b6bf22 100644 --- a/drivers/infiniband/hw/nes/nes_utils.c +++ b/drivers/infiniband/hw/nes/nes_utils.c | |||
| @@ -655,6 +655,7 @@ int nes_arp_table(struct nes_device *nesdev, u32 ip_addr, u8 *mac_addr, u32 acti | |||
| 655 | struct nes_adapter *nesadapter = nesdev->nesadapter; | 655 | struct nes_adapter *nesadapter = nesdev->nesadapter; |
| 656 | int arp_index; | 656 | int arp_index; |
| 657 | int err = 0; | 657 | int err = 0; |
| 658 | __be32 tmp_addr; | ||
| 658 | 659 | ||
| 659 | for (arp_index = 0; (u32) arp_index < nesadapter->arp_table_size; arp_index++) { | 660 | for (arp_index = 0; (u32) arp_index < nesadapter->arp_table_size; arp_index++) { |
| 660 | if (nesadapter->arp_table[arp_index].ip_addr == ip_addr) | 661 | if (nesadapter->arp_table[arp_index].ip_addr == ip_addr) |
| @@ -682,8 +683,9 @@ int nes_arp_table(struct nes_device *nesdev, u32 ip_addr, u8 *mac_addr, u32 acti | |||
| 682 | 683 | ||
| 683 | /* DELETE or RESOLVE */ | 684 | /* DELETE or RESOLVE */ |
| 684 | if (arp_index == nesadapter->arp_table_size) { | 685 | if (arp_index == nesadapter->arp_table_size) { |
| 686 | tmp_addr = cpu_to_be32(ip_addr); | ||
| 685 | nes_debug(NES_DBG_NETDEV, "MAC for %pI4 not in ARP table - cannot %s\n", | 687 | nes_debug(NES_DBG_NETDEV, "MAC for %pI4 not in ARP table - cannot %s\n", |
| 686 | &ip_addr, action == NES_ARP_RESOLVE ? "resolve" : "delete"); | 688 | &tmp_addr, action == NES_ARP_RESOLVE ? "resolve" : "delete"); |
| 687 | return -1; | 689 | return -1; |
| 688 | } | 690 | } |
| 689 | 691 | ||
diff --git a/drivers/infiniband/ulp/ipoib/ipoib_main.c b/drivers/infiniband/ulp/ipoib/ipoib_main.c index 19e06bc38b39..dce0443f9d69 100644 --- a/drivers/infiniband/ulp/ipoib/ipoib_main.c +++ b/drivers/infiniband/ulp/ipoib/ipoib_main.c | |||
| @@ -711,26 +711,26 @@ static int ipoib_start_xmit(struct sk_buff *skb, struct net_device *dev) | |||
| 711 | 711 | ||
| 712 | neigh = *to_ipoib_neigh(skb->dst->neighbour); | 712 | neigh = *to_ipoib_neigh(skb->dst->neighbour); |
| 713 | 713 | ||
| 714 | if (neigh->ah) | 714 | if (unlikely((memcmp(&neigh->dgid.raw, |
| 715 | if (unlikely((memcmp(&neigh->dgid.raw, | 715 | skb->dst->neighbour->ha + 4, |
| 716 | skb->dst->neighbour->ha + 4, | 716 | sizeof(union ib_gid))) || |
| 717 | sizeof(union ib_gid))) || | 717 | (neigh->dev != dev))) { |
| 718 | (neigh->dev != dev))) { | 718 | spin_lock_irqsave(&priv->lock, flags); |
| 719 | spin_lock_irqsave(&priv->lock, flags); | 719 | /* |
| 720 | /* | 720 | * It's safe to call ipoib_put_ah() inside |
| 721 | * It's safe to call ipoib_put_ah() inside | 721 | * priv->lock here, because we know that |
| 722 | * priv->lock here, because we know that | 722 | * path->ah will always hold one more reference, |
| 723 | * path->ah will always hold one more reference, | 723 | * so ipoib_put_ah() will never do more than |
| 724 | * so ipoib_put_ah() will never do more than | 724 | * decrement the ref count. |
| 725 | * decrement the ref count. | 725 | */ |
| 726 | */ | 726 | if (neigh->ah) |
| 727 | ipoib_put_ah(neigh->ah); | 727 | ipoib_put_ah(neigh->ah); |
| 728 | list_del(&neigh->list); | 728 | list_del(&neigh->list); |
| 729 | ipoib_neigh_free(dev, neigh); | 729 | ipoib_neigh_free(dev, neigh); |
| 730 | spin_unlock_irqrestore(&priv->lock, flags); | 730 | spin_unlock_irqrestore(&priv->lock, flags); |
| 731 | ipoib_path_lookup(skb, dev); | 731 | ipoib_path_lookup(skb, dev); |
| 732 | return NETDEV_TX_OK; | 732 | return NETDEV_TX_OK; |
| 733 | } | 733 | } |
| 734 | 734 | ||
| 735 | if (ipoib_cm_get(neigh)) { | 735 | if (ipoib_cm_get(neigh)) { |
| 736 | if (ipoib_cm_up(neigh)) { | 736 | if (ipoib_cm_up(neigh)) { |
diff --git a/drivers/infiniband/ulp/ipoib/ipoib_multicast.c b/drivers/infiniband/ulp/ipoib/ipoib_multicast.c index a2eb3b9789eb..59d02e0b8df1 100644 --- a/drivers/infiniband/ulp/ipoib/ipoib_multicast.c +++ b/drivers/infiniband/ulp/ipoib/ipoib_multicast.c | |||
| @@ -529,6 +529,9 @@ void ipoib_mcast_join_task(struct work_struct *work) | |||
| 529 | if (!priv->broadcast) { | 529 | if (!priv->broadcast) { |
| 530 | struct ipoib_mcast *broadcast; | 530 | struct ipoib_mcast *broadcast; |
| 531 | 531 | ||
| 532 | if (!test_bit(IPOIB_FLAG_ADMIN_UP, &priv->flags)) | ||
| 533 | return; | ||
| 534 | |||
| 532 | broadcast = ipoib_mcast_alloc(dev, 1); | 535 | broadcast = ipoib_mcast_alloc(dev, 1); |
| 533 | if (!broadcast) { | 536 | if (!broadcast) { |
| 534 | ipoib_warn(priv, "failed to allocate broadcast group\n"); | 537 | ipoib_warn(priv, "failed to allocate broadcast group\n"); |
diff --git a/drivers/infiniband/ulp/iser/Kconfig b/drivers/infiniband/ulp/iser/Kconfig index 77dedba829e6..b411c51842da 100644 --- a/drivers/infiniband/ulp/iser/Kconfig +++ b/drivers/infiniband/ulp/iser/Kconfig | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | config INFINIBAND_ISER | 1 | config INFINIBAND_ISER |
| 2 | tristate "iSCSI Extensions for RDMA (iSER)" | 2 | tristate "iSCSI Extensions for RDMA (iSER)" |
| 3 | depends on SCSI && INET | 3 | depends on SCSI && INET && INFINIBAND_ADDR_TRANS |
| 4 | select SCSI_ISCSI_ATTRS | 4 | select SCSI_ISCSI_ATTRS |
| 5 | ---help--- | 5 | ---help--- |
| 6 | Support for the iSCSI Extensions for RDMA (iSER) Protocol | 6 | Support for the iSCSI Extensions for RDMA (iSER) Protocol |
diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig index 199055db5082..67e5553f699a 100644 --- a/drivers/input/misc/Kconfig +++ b/drivers/input/misc/Kconfig | |||
| @@ -220,4 +220,11 @@ config HP_SDC_RTC | |||
| 220 | Say Y here if you want to support the built-in real time clock | 220 | Say Y here if you want to support the built-in real time clock |
| 221 | of the HP SDC controller. | 221 | of the HP SDC controller. |
| 222 | 222 | ||
| 223 | config INPUT_PCF50633_PMU | ||
| 224 | tristate "PCF50633 PMU events" | ||
| 225 | depends on MFD_PCF50633 | ||
| 226 | help | ||
| 227 | Say Y to include support for delivering PMU events via input | ||
| 228 | layer on NXP PCF50633. | ||
| 229 | |||
| 223 | endif | 230 | endif |
diff --git a/drivers/input/misc/Makefile b/drivers/input/misc/Makefile index d7db2aeb8a98..bb62e6efacf3 100644 --- a/drivers/input/misc/Makefile +++ b/drivers/input/misc/Makefile | |||
| @@ -21,3 +21,4 @@ obj-$(CONFIG_HP_SDC_RTC) += hp_sdc_rtc.o | |||
| 21 | obj-$(CONFIG_INPUT_UINPUT) += uinput.o | 21 | obj-$(CONFIG_INPUT_UINPUT) += uinput.o |
| 22 | obj-$(CONFIG_INPUT_APANEL) += apanel.o | 22 | obj-$(CONFIG_INPUT_APANEL) += apanel.o |
| 23 | obj-$(CONFIG_INPUT_SGI_BTNS) += sgi_btns.o | 23 | obj-$(CONFIG_INPUT_SGI_BTNS) += sgi_btns.o |
| 24 | obj-$(CONFIG_INPUT_PCF50633_PMU) += pcf50633-input.o | ||
diff --git a/drivers/input/misc/pcf50633-input.c b/drivers/input/misc/pcf50633-input.c new file mode 100644 index 000000000000..039dcb00ebd9 --- /dev/null +++ b/drivers/input/misc/pcf50633-input.c | |||
| @@ -0,0 +1,132 @@ | |||
| 1 | /* NXP PCF50633 Input Driver | ||
| 2 | * | ||
| 3 | * (C) 2006-2008 by Openmoko, Inc. | ||
| 4 | * Author: Balaji Rao <balajirrao@openmoko.org> | ||
| 5 | * All rights reserved. | ||
| 6 | * | ||
| 7 | * Broken down from monstrous PCF50633 driver mainly by | ||
| 8 | * Harald Welte, Andy Green and Werner Almesberger | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify it | ||
| 11 | * under the terms of the GNU General Public License as published by the | ||
| 12 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 13 | * option) any later version. | ||
| 14 | * | ||
| 15 | */ | ||
| 16 | |||
| 17 | #include <linux/kernel.h> | ||
| 18 | #include <linux/module.h> | ||
| 19 | #include <linux/init.h> | ||
| 20 | #include <linux/device.h> | ||
| 21 | #include <linux/platform_device.h> | ||
| 22 | #include <linux/input.h> | ||
| 23 | |||
| 24 | #include <linux/mfd/pcf50633/core.h> | ||
| 25 | |||
| 26 | #define PCF50633_OOCSTAT_ONKEY 0x01 | ||
| 27 | #define PCF50633_REG_OOCSTAT 0x12 | ||
| 28 | #define PCF50633_REG_OOCMODE 0x10 | ||
| 29 | |||
| 30 | struct pcf50633_input { | ||
| 31 | struct pcf50633 *pcf; | ||
| 32 | struct input_dev *input_dev; | ||
| 33 | }; | ||
| 34 | |||
| 35 | static void | ||
| 36 | pcf50633_input_irq(int irq, void *data) | ||
| 37 | { | ||
| 38 | struct pcf50633_input *input; | ||
| 39 | int onkey_released; | ||
| 40 | |||
| 41 | input = data; | ||
| 42 | |||
| 43 | /* We report only one event depending on the key press status */ | ||
| 44 | onkey_released = pcf50633_reg_read(input->pcf, PCF50633_REG_OOCSTAT) | ||
| 45 | & PCF50633_OOCSTAT_ONKEY; | ||
| 46 | |||
| 47 | if (irq == PCF50633_IRQ_ONKEYF && !onkey_released) | ||
| 48 | input_report_key(input->input_dev, KEY_POWER, 1); | ||
| 49 | else if (irq == PCF50633_IRQ_ONKEYR && onkey_released) | ||
| 50 | input_report_key(input->input_dev, KEY_POWER, 0); | ||
| 51 | |||
| 52 | input_sync(input->input_dev); | ||
| 53 | } | ||
| 54 | |||
| 55 | static int __devinit pcf50633_input_probe(struct platform_device *pdev) | ||
| 56 | { | ||
| 57 | struct pcf50633_input *input; | ||
| 58 | struct pcf50633_subdev_pdata *pdata = pdev->dev.platform_data; | ||
| 59 | struct input_dev *input_dev; | ||
| 60 | int ret; | ||
| 61 | |||
| 62 | |||
| 63 | input = kzalloc(sizeof(*input), GFP_KERNEL); | ||
| 64 | if (!input) | ||
| 65 | return -ENOMEM; | ||
| 66 | |||
| 67 | input_dev = input_allocate_device(); | ||
| 68 | if (!input_dev) { | ||
| 69 | kfree(input); | ||
| 70 | return -ENOMEM; | ||
| 71 | } | ||
| 72 | |||
| 73 | platform_set_drvdata(pdev, input); | ||
| 74 | input->pcf = pdata->pcf; | ||
| 75 | input->input_dev = input_dev; | ||
| 76 | |||
| 77 | input_dev->name = "PCF50633 PMU events"; | ||
| 78 | input_dev->id.bustype = BUS_I2C; | ||
| 79 | input_dev->evbit[0] = BIT(EV_KEY) | BIT(EV_PWR); | ||
| 80 | set_bit(KEY_POWER, input_dev->keybit); | ||
| 81 | |||
| 82 | ret = input_register_device(input_dev); | ||
| 83 | if (ret) { | ||
| 84 | input_free_device(input_dev); | ||
| 85 | kfree(input); | ||
| 86 | return ret; | ||
| 87 | } | ||
| 88 | pcf50633_register_irq(pdata->pcf, PCF50633_IRQ_ONKEYR, | ||
| 89 | pcf50633_input_irq, input); | ||
| 90 | pcf50633_register_irq(pdata->pcf, PCF50633_IRQ_ONKEYF, | ||
| 91 | pcf50633_input_irq, input); | ||
| 92 | |||
| 93 | return 0; | ||
| 94 | } | ||
| 95 | |||
| 96 | static int __devexit pcf50633_input_remove(struct platform_device *pdev) | ||
| 97 | { | ||
| 98 | struct pcf50633_input *input = platform_get_drvdata(pdev); | ||
| 99 | |||
| 100 | pcf50633_free_irq(input->pcf, PCF50633_IRQ_ONKEYR); | ||
| 101 | pcf50633_free_irq(input->pcf, PCF50633_IRQ_ONKEYF); | ||
| 102 | |||
| 103 | input_unregister_device(input->input_dev); | ||
| 104 | kfree(input); | ||
| 105 | |||
| 106 | return 0; | ||
| 107 | } | ||
| 108 | |||
| 109 | static struct platform_driver pcf50633_input_driver = { | ||
| 110 | .driver = { | ||
| 111 | .name = "pcf50633-input", | ||
| 112 | }, | ||
| 113 | .probe = pcf50633_input_probe, | ||
| 114 | .remove = __devexit_p(pcf50633_input_remove), | ||
| 115 | }; | ||
| 116 | |||
| 117 | static int __init pcf50633_input_init(void) | ||
| 118 | { | ||
| 119 | return platform_driver_register(&pcf50633_input_driver); | ||
| 120 | } | ||
| 121 | module_init(pcf50633_input_init); | ||
| 122 | |||
| 123 | static void __exit pcf50633_input_exit(void) | ||
| 124 | { | ||
| 125 | platform_driver_unregister(&pcf50633_input_driver); | ||
| 126 | } | ||
| 127 | module_exit(pcf50633_input_exit); | ||
| 128 | |||
| 129 | MODULE_AUTHOR("Balaji Rao <balajirrao@openmoko.org>"); | ||
| 130 | MODULE_DESCRIPTION("PCF50633 input driver"); | ||
| 131 | MODULE_LICENSE("GPL"); | ||
| 132 | MODULE_ALIAS("platform:pcf50633-input"); | ||
diff --git a/drivers/isdn/hardware/mISDN/hfcmulti.c b/drivers/isdn/hardware/mISDN/hfcmulti.c index 97f4708b3879..595ba8eb4a07 100644 --- a/drivers/isdn/hardware/mISDN/hfcmulti.c +++ b/drivers/isdn/hardware/mISDN/hfcmulti.c | |||
| @@ -3615,7 +3615,7 @@ hfcm_bctrl(struct mISDNchannel *ch, u_int cmd, void *arg) | |||
| 3615 | static void | 3615 | static void |
| 3616 | ph_state_change(struct dchannel *dch) | 3616 | ph_state_change(struct dchannel *dch) |
| 3617 | { | 3617 | { |
| 3618 | struct hfc_multi *hc = dch->hw; | 3618 | struct hfc_multi *hc; |
| 3619 | int ch, i; | 3619 | int ch, i; |
| 3620 | 3620 | ||
| 3621 | if (!dch) { | 3621 | if (!dch) { |
| @@ -3623,6 +3623,7 @@ ph_state_change(struct dchannel *dch) | |||
| 3623 | __func__); | 3623 | __func__); |
| 3624 | return; | 3624 | return; |
| 3625 | } | 3625 | } |
| 3626 | hc = dch->hw; | ||
| 3626 | ch = dch->slot; | 3627 | ch = dch->slot; |
| 3627 | 3628 | ||
| 3628 | if (hc->type == 1) { | 3629 | if (hc->type == 1) { |
diff --git a/drivers/isdn/hardware/mISDN/hfcpci.c b/drivers/isdn/hardware/mISDN/hfcpci.c index 917bf41a293b..f0e14dfcf71d 100644 --- a/drivers/isdn/hardware/mISDN/hfcpci.c +++ b/drivers/isdn/hardware/mISDN/hfcpci.c | |||
| @@ -61,7 +61,7 @@ u32 hfc_jiffies; | |||
| 61 | 61 | ||
| 62 | MODULE_AUTHOR("Karsten Keil"); | 62 | MODULE_AUTHOR("Karsten Keil"); |
| 63 | MODULE_LICENSE("GPL"); | 63 | MODULE_LICENSE("GPL"); |
| 64 | module_param(debug, uint, 0); | 64 | module_param(debug, uint, S_IRUGO | S_IWUSR); |
| 65 | module_param(poll, uint, S_IRUGO | S_IWUSR); | 65 | module_param(poll, uint, S_IRUGO | S_IWUSR); |
| 66 | 66 | ||
| 67 | enum { | 67 | enum { |
diff --git a/drivers/isdn/mISDN/dsp_cmx.c b/drivers/isdn/mISDN/dsp_cmx.c index 0ac67bff303a..58c43e429f73 100644 --- a/drivers/isdn/mISDN/dsp_cmx.c +++ b/drivers/isdn/mISDN/dsp_cmx.c | |||
| @@ -1579,7 +1579,7 @@ send_packet: | |||
| 1579 | schedule_work(&dsp->workq); | 1579 | schedule_work(&dsp->workq); |
| 1580 | } | 1580 | } |
| 1581 | 1581 | ||
| 1582 | static u32 jittercount; /* counter for jitter check */; | 1582 | static u32 jittercount; /* counter for jitter check */ |
| 1583 | struct timer_list dsp_spl_tl; | 1583 | struct timer_list dsp_spl_tl; |
| 1584 | u32 dsp_spl_jiffies; /* calculate the next time to fire */ | 1584 | u32 dsp_spl_jiffies; /* calculate the next time to fire */ |
| 1585 | static u16 dsp_count; /* last sample count */ | 1585 | static u16 dsp_count; /* last sample count */ |
| @@ -1893,7 +1893,7 @@ dsp_cmx_hdlc(struct dsp *dsp, struct sk_buff *skb) | |||
| 1893 | /* in case of hardware (echo) */ | 1893 | /* in case of hardware (echo) */ |
| 1894 | if (dsp->pcm_slot_tx >= 0) | 1894 | if (dsp->pcm_slot_tx >= 0) |
| 1895 | return; | 1895 | return; |
| 1896 | if (dsp->echo) | 1896 | if (dsp->echo) { |
| 1897 | nskb = skb_clone(skb, GFP_ATOMIC); | 1897 | nskb = skb_clone(skb, GFP_ATOMIC); |
| 1898 | if (nskb) { | 1898 | if (nskb) { |
| 1899 | hh = mISDN_HEAD_P(nskb); | 1899 | hh = mISDN_HEAD_P(nskb); |
| @@ -1902,6 +1902,7 @@ dsp_cmx_hdlc(struct dsp *dsp, struct sk_buff *skb) | |||
| 1902 | skb_queue_tail(&dsp->sendq, nskb); | 1902 | skb_queue_tail(&dsp->sendq, nskb); |
| 1903 | schedule_work(&dsp->workq); | 1903 | schedule_work(&dsp->workq); |
| 1904 | } | 1904 | } |
| 1905 | } | ||
| 1905 | return; | 1906 | return; |
| 1906 | } | 1907 | } |
| 1907 | /* in case of hardware conference */ | 1908 | /* in case of hardware conference */ |
diff --git a/drivers/isdn/mISDN/dsp_pipeline.c b/drivers/isdn/mISDN/dsp_pipeline.c index bf999bdc41c3..18cf87c113e7 100644 --- a/drivers/isdn/mISDN/dsp_pipeline.c +++ b/drivers/isdn/mISDN/dsp_pipeline.c | |||
| @@ -110,8 +110,7 @@ int mISDN_dsp_element_register(struct mISDN_dsp_element *elem) | |||
| 110 | } | 110 | } |
| 111 | list_add_tail(&entry->list, &dsp_elements); | 111 | list_add_tail(&entry->list, &dsp_elements); |
| 112 | 112 | ||
| 113 | for (i = 0; i < (sizeof(element_attributes) | 113 | for (i = 0; i < ARRAY_SIZE(element_attributes); ++i) { |
| 114 | / sizeof(struct device_attribute)); ++i) | ||
| 115 | ret = device_create_file(&entry->dev, | 114 | ret = device_create_file(&entry->dev, |
| 116 | &element_attributes[i]); | 115 | &element_attributes[i]); |
| 117 | if (ret) { | 116 | if (ret) { |
| @@ -119,6 +118,7 @@ int mISDN_dsp_element_register(struct mISDN_dsp_element *elem) | |||
| 119 | __func__); | 118 | __func__); |
| 120 | goto err2; | 119 | goto err2; |
| 121 | } | 120 | } |
| 121 | } | ||
| 122 | 122 | ||
| 123 | #ifdef PIPELINE_DEBUG | 123 | #ifdef PIPELINE_DEBUG |
| 124 | printk(KERN_DEBUG "%s: %s registered\n", __func__, elem->name); | 124 | printk(KERN_DEBUG "%s: %s registered\n", __func__, elem->name); |
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 416f9e7286ba..06a2b0f7737c 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig | |||
| @@ -217,6 +217,29 @@ config MFD_WM8350_I2C | |||
| 217 | I2C as the control interface. Additional options must be | 217 | I2C as the control interface. Additional options must be |
| 218 | selected to enable support for the functionality of the chip. | 218 | selected to enable support for the functionality of the chip. |
| 219 | 219 | ||
| 220 | config MFD_PCF50633 | ||
| 221 | tristate "Support for NXP PCF50633" | ||
| 222 | depends on I2C | ||
| 223 | help | ||
| 224 | Say yes here if you have NXP PCF50633 chip on your board. | ||
| 225 | This core driver provides register access and IRQ handling | ||
| 226 | facilities, and registers devices for the various functions | ||
| 227 | so that function-specific drivers can bind to them. | ||
| 228 | |||
| 229 | config PCF50633_ADC | ||
| 230 | tristate "Support for NXP PCF50633 ADC" | ||
| 231 | depends on MFD_PCF50633 | ||
| 232 | help | ||
| 233 | Say yes here if you want to include support for ADC in the | ||
| 234 | NXP PCF50633 chip. | ||
| 235 | |||
| 236 | config PCF50633_GPIO | ||
| 237 | tristate "Support for NXP PCF50633 GPIO" | ||
| 238 | depends on MFD_PCF50633 | ||
| 239 | help | ||
| 240 | Say yes here if you want to include support GPIO for pins on | ||
| 241 | the PCF50633 chip. | ||
| 242 | |||
| 220 | endmenu | 243 | endmenu |
| 221 | 244 | ||
| 222 | menu "Multimedia Capabilities Port drivers" | 245 | menu "Multimedia Capabilities Port drivers" |
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 0c9418b36c26..3afb5192e4da 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile | |||
| @@ -37,3 +37,7 @@ endif | |||
| 37 | obj-$(CONFIG_UCB1400_CORE) += ucb1400_core.o | 37 | obj-$(CONFIG_UCB1400_CORE) += ucb1400_core.o |
| 38 | 38 | ||
| 39 | obj-$(CONFIG_PMIC_DA903X) += da903x.o | 39 | obj-$(CONFIG_PMIC_DA903X) += da903x.o |
| 40 | |||
| 41 | obj-$(CONFIG_MFD_PCF50633) += pcf50633-core.o | ||
| 42 | obj-$(CONFIG_PCF50633_ADC) += pcf50633-adc.o | ||
| 43 | obj-$(CONFIG_PCF50633_GPIO) += pcf50633-gpio.o \ No newline at end of file | ||
diff --git a/drivers/mfd/dm355evm_msp.c b/drivers/mfd/dm355evm_msp.c index 4214b3f72426..7ac12cb0be4a 100644 --- a/drivers/mfd/dm355evm_msp.c +++ b/drivers/mfd/dm355evm_msp.c | |||
| @@ -107,6 +107,9 @@ static const u8 msp_gpios[] = { | |||
| 107 | MSP_GPIO(0, SWITCH1), MSP_GPIO(1, SWITCH1), | 107 | MSP_GPIO(0, SWITCH1), MSP_GPIO(1, SWITCH1), |
| 108 | MSP_GPIO(2, SWITCH1), MSP_GPIO(3, SWITCH1), | 108 | MSP_GPIO(2, SWITCH1), MSP_GPIO(3, SWITCH1), |
| 109 | MSP_GPIO(4, SWITCH1), | 109 | MSP_GPIO(4, SWITCH1), |
| 110 | /* switches on MMC/SD sockets */ | ||
| 111 | MSP_GPIO(1, SDMMC), MSP_GPIO(2, SDMMC), /* mmc0 WP, nCD */ | ||
| 112 | MSP_GPIO(3, SDMMC), MSP_GPIO(4, SDMMC), /* mmc1 WP, nCD */ | ||
| 110 | }; | 113 | }; |
| 111 | 114 | ||
| 112 | #define MSP_GPIO_REG(offset) (msp_gpios[(offset)] >> 3) | 115 | #define MSP_GPIO_REG(offset) (msp_gpios[(offset)] >> 3) |
| @@ -304,6 +307,13 @@ static int add_children(struct i2c_client *client) | |||
| 304 | gpio_export(gpio, false); | 307 | gpio_export(gpio, false); |
| 305 | } | 308 | } |
| 306 | 309 | ||
| 310 | /* MMC/SD inputs -- right after the last config input */ | ||
| 311 | if (client->dev.platform_data) { | ||
| 312 | void (*mmcsd_setup)(unsigned) = client->dev.platform_data; | ||
| 313 | |||
| 314 | mmcsd_setup(dm355evm_msp_gpio.base + 8 + 5); | ||
| 315 | } | ||
| 316 | |||
| 307 | /* RTC is a 32 bit counter, no alarm */ | 317 | /* RTC is a 32 bit counter, no alarm */ |
| 308 | if (msp_has_rtc()) { | 318 | if (msp_has_rtc()) { |
| 309 | child = add_child(client, "rtc-dm355evm", | 319 | child = add_child(client, "rtc-dm355evm", |
diff --git a/drivers/mfd/pcf50633-adc.c b/drivers/mfd/pcf50633-adc.c new file mode 100644 index 000000000000..c2d05becfa97 --- /dev/null +++ b/drivers/mfd/pcf50633-adc.c | |||
| @@ -0,0 +1,277 @@ | |||
| 1 | /* NXP PCF50633 ADC Driver | ||
| 2 | * | ||
| 3 | * (C) 2006-2008 by Openmoko, Inc. | ||
| 4 | * Author: Balaji Rao <balajirrao@openmoko.org> | ||
| 5 | * All rights reserved. | ||
| 6 | * | ||
| 7 | * Broken down from monstrous PCF50633 driver mainly by | ||
| 8 | * Harald Welte, Andy Green and Werner Almesberger | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify it | ||
| 11 | * under the terms of the GNU General Public License as published by the | ||
| 12 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 13 | * option) any later version. | ||
| 14 | * | ||
| 15 | * NOTE: This driver does not yet support subtractive ADC mode, which means | ||
| 16 | * you can do only one measurement per read request. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #include <linux/kernel.h> | ||
| 20 | #include <linux/module.h> | ||
| 21 | #include <linux/init.h> | ||
| 22 | #include <linux/device.h> | ||
| 23 | #include <linux/platform_device.h> | ||
| 24 | #include <linux/completion.h> | ||
| 25 | |||
| 26 | #include <linux/mfd/pcf50633/core.h> | ||
| 27 | #include <linux/mfd/pcf50633/adc.h> | ||
| 28 | |||
| 29 | struct pcf50633_adc_request { | ||
| 30 | int mux; | ||
| 31 | int avg; | ||
| 32 | int result; | ||
| 33 | void (*callback)(struct pcf50633 *, void *, int); | ||
| 34 | void *callback_param; | ||
| 35 | |||
| 36 | /* Used in case of sync requests */ | ||
| 37 | struct completion completion; | ||
| 38 | |||
| 39 | }; | ||
| 40 | |||
| 41 | #define PCF50633_MAX_ADC_FIFO_DEPTH 8 | ||
| 42 | |||
| 43 | struct pcf50633_adc { | ||
| 44 | struct pcf50633 *pcf; | ||
| 45 | |||
| 46 | /* Private stuff */ | ||
| 47 | struct pcf50633_adc_request *queue[PCF50633_MAX_ADC_FIFO_DEPTH]; | ||
| 48 | int queue_head; | ||
| 49 | int queue_tail; | ||
| 50 | struct mutex queue_mutex; | ||
| 51 | }; | ||
| 52 | |||
| 53 | static inline struct pcf50633_adc *__to_adc(struct pcf50633 *pcf) | ||
| 54 | { | ||
| 55 | return platform_get_drvdata(pcf->adc_pdev); | ||
| 56 | } | ||
| 57 | |||
| 58 | static void adc_setup(struct pcf50633 *pcf, int channel, int avg) | ||
| 59 | { | ||
| 60 | channel &= PCF50633_ADCC1_ADCMUX_MASK; | ||
| 61 | |||
| 62 | /* kill ratiometric, but enable ACCSW biasing */ | ||
| 63 | pcf50633_reg_write(pcf, PCF50633_REG_ADCC2, 0x00); | ||
| 64 | pcf50633_reg_write(pcf, PCF50633_REG_ADCC3, 0x01); | ||
| 65 | |||
| 66 | /* start ADC conversion on selected channel */ | ||
| 67 | pcf50633_reg_write(pcf, PCF50633_REG_ADCC1, channel | avg | | ||
| 68 | PCF50633_ADCC1_ADCSTART | PCF50633_ADCC1_RES_10BIT); | ||
| 69 | } | ||
| 70 | |||
| 71 | static void trigger_next_adc_job_if_any(struct pcf50633 *pcf) | ||
| 72 | { | ||
| 73 | struct pcf50633_adc *adc = __to_adc(pcf); | ||
| 74 | int head; | ||
| 75 | |||
| 76 | mutex_lock(&adc->queue_mutex); | ||
| 77 | |||
| 78 | head = adc->queue_head; | ||
| 79 | |||
| 80 | if (!adc->queue[head]) { | ||
| 81 | mutex_unlock(&adc->queue_mutex); | ||
| 82 | return; | ||
| 83 | } | ||
| 84 | mutex_unlock(&adc->queue_mutex); | ||
| 85 | |||
| 86 | adc_setup(pcf, adc->queue[head]->mux, adc->queue[head]->avg); | ||
| 87 | } | ||
| 88 | |||
| 89 | static int | ||
| 90 | adc_enqueue_request(struct pcf50633 *pcf, struct pcf50633_adc_request *req) | ||
| 91 | { | ||
| 92 | struct pcf50633_adc *adc = __to_adc(pcf); | ||
| 93 | int head, tail; | ||
| 94 | |||
| 95 | mutex_lock(&adc->queue_mutex); | ||
| 96 | |||
| 97 | head = adc->queue_head; | ||
| 98 | tail = adc->queue_tail; | ||
| 99 | |||
| 100 | if (adc->queue[tail]) { | ||
| 101 | mutex_unlock(&adc->queue_mutex); | ||
| 102 | return -EBUSY; | ||
| 103 | } | ||
| 104 | |||
| 105 | adc->queue[tail] = req; | ||
| 106 | adc->queue_tail = (tail + 1) & (PCF50633_MAX_ADC_FIFO_DEPTH - 1); | ||
| 107 | |||
| 108 | mutex_unlock(&adc->queue_mutex); | ||
| 109 | |||
| 110 | trigger_next_adc_job_if_any(pcf); | ||
| 111 | |||
| 112 | return 0; | ||
| 113 | } | ||
| 114 | |||
| 115 | static void | ||
| 116 | pcf50633_adc_sync_read_callback(struct pcf50633 *pcf, void *param, int result) | ||
| 117 | { | ||
| 118 | struct pcf50633_adc_request *req = param; | ||
| 119 | |||
| 120 | req->result = result; | ||
| 121 | complete(&req->completion); | ||
| 122 | } | ||
| 123 | |||
| 124 | int pcf50633_adc_sync_read(struct pcf50633 *pcf, int mux, int avg) | ||
| 125 | { | ||
| 126 | struct pcf50633_adc_request *req; | ||
| 127 | |||
| 128 | /* req is freed when the result is ready, in interrupt handler */ | ||
| 129 | req = kzalloc(sizeof(*req), GFP_KERNEL); | ||
| 130 | if (!req) | ||
| 131 | return -ENOMEM; | ||
| 132 | |||
| 133 | req->mux = mux; | ||
| 134 | req->avg = avg; | ||
| 135 | req->callback = pcf50633_adc_sync_read_callback; | ||
| 136 | req->callback_param = req; | ||
| 137 | |||
| 138 | init_completion(&req->completion); | ||
| 139 | adc_enqueue_request(pcf, req); | ||
| 140 | wait_for_completion(&req->completion); | ||
| 141 | |||
| 142 | return req->result; | ||
| 143 | } | ||
| 144 | EXPORT_SYMBOL_GPL(pcf50633_adc_sync_read); | ||
| 145 | |||
| 146 | int pcf50633_adc_async_read(struct pcf50633 *pcf, int mux, int avg, | ||
| 147 | void (*callback)(struct pcf50633 *, void *, int), | ||
| 148 | void *callback_param) | ||
| 149 | { | ||
| 150 | struct pcf50633_adc_request *req; | ||
| 151 | |||
| 152 | /* req is freed when the result is ready, in interrupt handler */ | ||
| 153 | req = kmalloc(sizeof(*req), GFP_KERNEL); | ||
| 154 | if (!req) | ||
| 155 | return -ENOMEM; | ||
| 156 | |||
| 157 | req->mux = mux; | ||
| 158 | req->avg = avg; | ||
| 159 | req->callback = callback; | ||
| 160 | req->callback_param = callback_param; | ||
| 161 | |||
| 162 | adc_enqueue_request(pcf, req); | ||
| 163 | |||
| 164 | return 0; | ||
| 165 | } | ||
| 166 | EXPORT_SYMBOL_GPL(pcf50633_adc_async_read); | ||
| 167 | |||
| 168 | static int adc_result(struct pcf50633 *pcf) | ||
| 169 | { | ||
| 170 | u8 adcs1, adcs3; | ||
| 171 | u16 result; | ||
| 172 | |||
| 173 | adcs1 = pcf50633_reg_read(pcf, PCF50633_REG_ADCS1); | ||
| 174 | adcs3 = pcf50633_reg_read(pcf, PCF50633_REG_ADCS3); | ||
| 175 | result = (adcs1 << 2) | (adcs3 & PCF50633_ADCS3_ADCDAT1L_MASK); | ||
| 176 | |||
| 177 | dev_dbg(pcf->dev, "adc result = %d\n", result); | ||
| 178 | |||
| 179 | return result; | ||
| 180 | } | ||
| 181 | |||
| 182 | static void pcf50633_adc_irq(int irq, void *data) | ||
| 183 | { | ||
| 184 | struct pcf50633_adc *adc = data; | ||
| 185 | struct pcf50633 *pcf = adc->pcf; | ||
| 186 | struct pcf50633_adc_request *req; | ||
| 187 | int head; | ||
| 188 | |||
| 189 | mutex_lock(&adc->queue_mutex); | ||
| 190 | head = adc->queue_head; | ||
| 191 | |||
| 192 | req = adc->queue[head]; | ||
| 193 | if (WARN_ON(!req)) { | ||
| 194 | dev_err(pcf->dev, "pcf50633-adc irq: ADC queue empty!\n"); | ||
| 195 | mutex_unlock(&adc->queue_mutex); | ||
| 196 | return; | ||
| 197 | } | ||
| 198 | adc->queue[head] = NULL; | ||
| 199 | adc->queue_head = (head + 1) & | ||
| 200 | (PCF50633_MAX_ADC_FIFO_DEPTH - 1); | ||
| 201 | |||
| 202 | mutex_unlock(&adc->queue_mutex); | ||
| 203 | |||
| 204 | req->callback(pcf, req->callback_param, adc_result(pcf)); | ||
| 205 | kfree(req); | ||
| 206 | |||
| 207 | trigger_next_adc_job_if_any(pcf); | ||
| 208 | } | ||
| 209 | |||
| 210 | static int __devinit pcf50633_adc_probe(struct platform_device *pdev) | ||
| 211 | { | ||
| 212 | struct pcf50633_subdev_pdata *pdata = pdev->dev.platform_data; | ||
| 213 | struct pcf50633_adc *adc; | ||
| 214 | |||
| 215 | adc = kzalloc(sizeof(*adc), GFP_KERNEL); | ||
| 216 | if (!adc) | ||
| 217 | return -ENOMEM; | ||
| 218 | |||
| 219 | adc->pcf = pdata->pcf; | ||
| 220 | platform_set_drvdata(pdev, adc); | ||
| 221 | |||
| 222 | pcf50633_register_irq(pdata->pcf, PCF50633_IRQ_ADCRDY, | ||
| 223 | pcf50633_adc_irq, adc); | ||
| 224 | |||
| 225 | mutex_init(&adc->queue_mutex); | ||
| 226 | |||
| 227 | return 0; | ||
| 228 | } | ||
| 229 | |||
| 230 | static int __devexit pcf50633_adc_remove(struct platform_device *pdev) | ||
| 231 | { | ||
| 232 | struct pcf50633_adc *adc = platform_get_drvdata(pdev); | ||
| 233 | int i, head; | ||
| 234 | |||
| 235 | pcf50633_free_irq(adc->pcf, PCF50633_IRQ_ADCRDY); | ||
| 236 | |||
| 237 | mutex_lock(&adc->queue_mutex); | ||
| 238 | head = adc->queue_head; | ||
| 239 | |||
| 240 | if (WARN_ON(adc->queue[head])) | ||
| 241 | dev_err(adc->pcf->dev, | ||
| 242 | "adc driver removed with request pending\n"); | ||
| 243 | |||
| 244 | for (i = 0; i < PCF50633_MAX_ADC_FIFO_DEPTH; i++) | ||
| 245 | kfree(adc->queue[i]); | ||
| 246 | |||
| 247 | mutex_unlock(&adc->queue_mutex); | ||
| 248 | kfree(adc); | ||
| 249 | |||
| 250 | return 0; | ||
| 251 | } | ||
| 252 | |||
| 253 | static struct platform_driver pcf50633_adc_driver = { | ||
| 254 | .driver = { | ||
| 255 | .name = "pcf50633-adc", | ||
| 256 | }, | ||
| 257 | .probe = pcf50633_adc_probe, | ||
| 258 | .remove = __devexit_p(pcf50633_adc_remove), | ||
| 259 | }; | ||
| 260 | |||
| 261 | static int __init pcf50633_adc_init(void) | ||
| 262 | { | ||
| 263 | return platform_driver_register(&pcf50633_adc_driver); | ||
| 264 | } | ||
| 265 | module_init(pcf50633_adc_init); | ||
| 266 | |||
| 267 | static void __exit pcf50633_adc_exit(void) | ||
| 268 | { | ||
| 269 | platform_driver_unregister(&pcf50633_adc_driver); | ||
| 270 | } | ||
| 271 | module_exit(pcf50633_adc_exit); | ||
| 272 | |||
| 273 | MODULE_AUTHOR("Balaji Rao <balajirrao@openmoko.org>"); | ||
| 274 | MODULE_DESCRIPTION("PCF50633 adc driver"); | ||
| 275 | MODULE_LICENSE("GPL"); | ||
| 276 | MODULE_ALIAS("platform:pcf50633-adc"); | ||
| 277 | |||
diff --git a/drivers/mfd/pcf50633-core.c b/drivers/mfd/pcf50633-core.c new file mode 100644 index 000000000000..24508e28e3fb --- /dev/null +++ b/drivers/mfd/pcf50633-core.c | |||
| @@ -0,0 +1,710 @@ | |||
| 1 | /* NXP PCF50633 Power Management Unit (PMU) driver | ||
| 2 | * | ||
| 3 | * (C) 2006-2008 by Openmoko, Inc. | ||
| 4 | * Author: Harald Welte <laforge@openmoko.org> | ||
| 5 | * Balaji Rao <balajirrao@openmoko.org> | ||
| 6 | * All rights reserved. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify it | ||
| 9 | * under the terms of the GNU General Public License as published by the | ||
| 10 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 11 | * option) any later version. | ||
| 12 | * | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include <linux/kernel.h> | ||
| 16 | #include <linux/device.h> | ||
| 17 | #include <linux/sysfs.h> | ||
| 18 | #include <linux/device.h> | ||
| 19 | #include <linux/module.h> | ||
| 20 | #include <linux/types.h> | ||
| 21 | #include <linux/interrupt.h> | ||
| 22 | #include <linux/workqueue.h> | ||
| 23 | #include <linux/platform_device.h> | ||
| 24 | #include <linux/i2c.h> | ||
| 25 | #include <linux/irq.h> | ||
| 26 | |||
| 27 | #include <linux/mfd/pcf50633/core.h> | ||
| 28 | |||
| 29 | /* Two MBCS registers used during cold start */ | ||
| 30 | #define PCF50633_REG_MBCS1 0x4b | ||
| 31 | #define PCF50633_REG_MBCS2 0x4c | ||
| 32 | #define PCF50633_MBCS1_USBPRES 0x01 | ||
| 33 | #define PCF50633_MBCS1_ADAPTPRES 0x01 | ||
| 34 | |||
| 35 | static int __pcf50633_read(struct pcf50633 *pcf, u8 reg, int num, u8 *data) | ||
| 36 | { | ||
| 37 | int ret; | ||
| 38 | |||
| 39 | ret = i2c_smbus_read_i2c_block_data(pcf->i2c_client, reg, | ||
| 40 | num, data); | ||
| 41 | if (ret < 0) | ||
| 42 | dev_err(pcf->dev, "Error reading %d regs at %d\n", num, reg); | ||
| 43 | |||
| 44 | return ret; | ||
| 45 | } | ||
| 46 | |||
| 47 | static int __pcf50633_write(struct pcf50633 *pcf, u8 reg, int num, u8 *data) | ||
| 48 | { | ||
| 49 | int ret; | ||
| 50 | |||
| 51 | ret = i2c_smbus_write_i2c_block_data(pcf->i2c_client, reg, | ||
| 52 | num, data); | ||
| 53 | if (ret < 0) | ||
| 54 | dev_err(pcf->dev, "Error writing %d regs at %d\n", num, reg); | ||
| 55 | |||
| 56 | return ret; | ||
| 57 | |||
| 58 | } | ||
| 59 | |||
| 60 | /* Read a block of upto 32 regs */ | ||
| 61 | int pcf50633_read_block(struct pcf50633 *pcf, u8 reg, | ||
| 62 | int nr_regs, u8 *data) | ||
| 63 | { | ||
| 64 | int ret; | ||
| 65 | |||
| 66 | mutex_lock(&pcf->lock); | ||
| 67 | ret = __pcf50633_read(pcf, reg, nr_regs, data); | ||
| 68 | mutex_unlock(&pcf->lock); | ||
| 69 | |||
| 70 | return ret; | ||
| 71 | } | ||
| 72 | EXPORT_SYMBOL_GPL(pcf50633_read_block); | ||
| 73 | |||
| 74 | /* Write a block of upto 32 regs */ | ||
| 75 | int pcf50633_write_block(struct pcf50633 *pcf , u8 reg, | ||
| 76 | int nr_regs, u8 *data) | ||
| 77 | { | ||
| 78 | int ret; | ||
| 79 | |||
| 80 | mutex_lock(&pcf->lock); | ||
| 81 | ret = __pcf50633_write(pcf, reg, nr_regs, data); | ||
| 82 | mutex_unlock(&pcf->lock); | ||
| 83 | |||
| 84 | return ret; | ||
| 85 | } | ||
| 86 | EXPORT_SYMBOL_GPL(pcf50633_write_block); | ||
| 87 | |||
| 88 | u8 pcf50633_reg_read(struct pcf50633 *pcf, u8 reg) | ||
| 89 | { | ||
| 90 | u8 val; | ||
| 91 | |||
| 92 | mutex_lock(&pcf->lock); | ||
| 93 | __pcf50633_read(pcf, reg, 1, &val); | ||
| 94 | mutex_unlock(&pcf->lock); | ||
| 95 | |||
| 96 | return val; | ||
| 97 | } | ||
| 98 | EXPORT_SYMBOL_GPL(pcf50633_reg_read); | ||
| 99 | |||
| 100 | int pcf50633_reg_write(struct pcf50633 *pcf, u8 reg, u8 val) | ||
| 101 | { | ||
| 102 | int ret; | ||
| 103 | |||
| 104 | mutex_lock(&pcf->lock); | ||
| 105 | ret = __pcf50633_write(pcf, reg, 1, &val); | ||
| 106 | mutex_unlock(&pcf->lock); | ||
| 107 | |||
| 108 | return ret; | ||
| 109 | } | ||
| 110 | EXPORT_SYMBOL_GPL(pcf50633_reg_write); | ||
| 111 | |||
| 112 | int pcf50633_reg_set_bit_mask(struct pcf50633 *pcf, u8 reg, u8 mask, u8 val) | ||
| 113 | { | ||
| 114 | int ret; | ||
| 115 | u8 tmp; | ||
| 116 | |||
| 117 | val &= mask; | ||
| 118 | |||
| 119 | mutex_lock(&pcf->lock); | ||
| 120 | ret = __pcf50633_read(pcf, reg, 1, &tmp); | ||
| 121 | if (ret < 0) | ||
| 122 | goto out; | ||
| 123 | |||
| 124 | tmp &= ~mask; | ||
| 125 | tmp |= val; | ||
| 126 | ret = __pcf50633_write(pcf, reg, 1, &tmp); | ||
| 127 | |||
| 128 | out: | ||
| 129 | mutex_unlock(&pcf->lock); | ||
| 130 | |||
| 131 | return ret; | ||
| 132 | } | ||
| 133 | EXPORT_SYMBOL_GPL(pcf50633_reg_set_bit_mask); | ||
| 134 | |||
| 135 | int pcf50633_reg_clear_bits(struct pcf50633 *pcf, u8 reg, u8 val) | ||
| 136 | { | ||
| 137 | int ret; | ||
| 138 | u8 tmp; | ||
| 139 | |||
| 140 | mutex_lock(&pcf->lock); | ||
| 141 | ret = __pcf50633_read(pcf, reg, 1, &tmp); | ||
| 142 | if (ret < 0) | ||
| 143 | goto out; | ||
| 144 | |||
| 145 | tmp &= ~val; | ||
| 146 | ret = __pcf50633_write(pcf, reg, 1, &tmp); | ||
| 147 | |||
| 148 | out: | ||
| 149 | mutex_unlock(&pcf->lock); | ||
| 150 | |||
| 151 | return ret; | ||
| 152 | } | ||
| 153 | EXPORT_SYMBOL_GPL(pcf50633_reg_clear_bits); | ||
| 154 | |||
| 155 | /* sysfs attributes */ | ||
| 156 | static ssize_t show_dump_regs(struct device *dev, struct device_attribute *attr, | ||
| 157 | char *buf) | ||
| 158 | { | ||
| 159 | struct pcf50633 *pcf = dev_get_drvdata(dev); | ||
| 160 | u8 dump[16]; | ||
| 161 | int n, n1, idx = 0; | ||
| 162 | char *buf1 = buf; | ||
| 163 | static u8 address_no_read[] = { /* must be ascending */ | ||
| 164 | PCF50633_REG_INT1, | ||
| 165 | PCF50633_REG_INT2, | ||
| 166 | PCF50633_REG_INT3, | ||
| 167 | PCF50633_REG_INT4, | ||
| 168 | PCF50633_REG_INT5, | ||
| 169 | 0 /* terminator */ | ||
| 170 | }; | ||
| 171 | |||
| 172 | for (n = 0; n < 256; n += sizeof(dump)) { | ||
| 173 | for (n1 = 0; n1 < sizeof(dump); n1++) | ||
| 174 | if (n == address_no_read[idx]) { | ||
| 175 | idx++; | ||
| 176 | dump[n1] = 0x00; | ||
| 177 | } else | ||
| 178 | dump[n1] = pcf50633_reg_read(pcf, n + n1); | ||
| 179 | |||
| 180 | hex_dump_to_buffer(dump, sizeof(dump), 16, 1, buf1, 128, 0); | ||
| 181 | buf1 += strlen(buf1); | ||
| 182 | *buf1++ = '\n'; | ||
| 183 | *buf1 = '\0'; | ||
| 184 | } | ||
| 185 | |||
| 186 | return buf1 - buf; | ||
| 187 | } | ||
| 188 | static DEVICE_ATTR(dump_regs, 0400, show_dump_regs, NULL); | ||
| 189 | |||
| 190 | static ssize_t show_resume_reason(struct device *dev, | ||
| 191 | struct device_attribute *attr, char *buf) | ||
| 192 | { | ||
| 193 | struct pcf50633 *pcf = dev_get_drvdata(dev); | ||
| 194 | int n; | ||
| 195 | |||
| 196 | n = sprintf(buf, "%02x%02x%02x%02x%02x\n", | ||
| 197 | pcf->resume_reason[0], | ||
| 198 | pcf->resume_reason[1], | ||
| 199 | pcf->resume_reason[2], | ||
| 200 | pcf->resume_reason[3], | ||
| 201 | pcf->resume_reason[4]); | ||
| 202 | |||
| 203 | return n; | ||
| 204 | } | ||
| 205 | static DEVICE_ATTR(resume_reason, 0400, show_resume_reason, NULL); | ||
| 206 | |||
| 207 | static struct attribute *pcf_sysfs_entries[] = { | ||
| 208 | &dev_attr_dump_regs.attr, | ||
| 209 | &dev_attr_resume_reason.attr, | ||
| 210 | NULL, | ||
| 211 | }; | ||
| 212 | |||
| 213 | static struct attribute_group pcf_attr_group = { | ||
| 214 | .name = NULL, /* put in device directory */ | ||
| 215 | .attrs = pcf_sysfs_entries, | ||
| 216 | }; | ||
| 217 | |||
| 218 | int pcf50633_register_irq(struct pcf50633 *pcf, int irq, | ||
| 219 | void (*handler) (int, void *), void *data) | ||
| 220 | { | ||
| 221 | if (irq < 0 || irq > PCF50633_NUM_IRQ || !handler) | ||
| 222 | return -EINVAL; | ||
| 223 | |||
| 224 | if (WARN_ON(pcf->irq_handler[irq].handler)) | ||
| 225 | return -EBUSY; | ||
| 226 | |||
| 227 | mutex_lock(&pcf->lock); | ||
| 228 | pcf->irq_handler[irq].handler = handler; | ||
| 229 | pcf->irq_handler[irq].data = data; | ||
| 230 | mutex_unlock(&pcf->lock); | ||
| 231 | |||
| 232 | return 0; | ||
| 233 | } | ||
| 234 | EXPORT_SYMBOL_GPL(pcf50633_register_irq); | ||
| 235 | |||
| 236 | int pcf50633_free_irq(struct pcf50633 *pcf, int irq) | ||
| 237 | { | ||
| 238 | if (irq < 0 || irq > PCF50633_NUM_IRQ) | ||
| 239 | return -EINVAL; | ||
| 240 | |||
| 241 | mutex_lock(&pcf->lock); | ||
| 242 | pcf->irq_handler[irq].handler = NULL; | ||
| 243 | mutex_unlock(&pcf->lock); | ||
| 244 | |||
| 245 | return 0; | ||
| 246 | } | ||
| 247 | EXPORT_SYMBOL_GPL(pcf50633_free_irq); | ||
| 248 | |||
| 249 | static int __pcf50633_irq_mask_set(struct pcf50633 *pcf, int irq, u8 mask) | ||
| 250 | { | ||
| 251 | u8 reg, bits, tmp; | ||
| 252 | int ret = 0, idx; | ||
| 253 | |||
| 254 | idx = irq >> 3; | ||
| 255 | reg = PCF50633_REG_INT1M + idx; | ||
| 256 | bits = 1 << (irq & 0x07); | ||
| 257 | |||
| 258 | mutex_lock(&pcf->lock); | ||
| 259 | |||
| 260 | if (mask) { | ||
| 261 | ret = __pcf50633_read(pcf, reg, 1, &tmp); | ||
| 262 | if (ret < 0) | ||
| 263 | goto out; | ||
| 264 | |||
| 265 | tmp |= bits; | ||
| 266 | |||
| 267 | ret = __pcf50633_write(pcf, reg, 1, &tmp); | ||
| 268 | if (ret < 0) | ||
| 269 | goto out; | ||
| 270 | |||
| 271 | pcf->mask_regs[idx] &= ~bits; | ||
| 272 | pcf->mask_regs[idx] |= bits; | ||
| 273 | } else { | ||
| 274 | ret = __pcf50633_read(pcf, reg, 1, &tmp); | ||
| 275 | if (ret < 0) | ||
| 276 | goto out; | ||
| 277 | |||
| 278 | tmp &= ~bits; | ||
| 279 | |||
| 280 | ret = __pcf50633_write(pcf, reg, 1, &tmp); | ||
| 281 | if (ret < 0) | ||
| 282 | goto out; | ||
| 283 | |||
| 284 | pcf->mask_regs[idx] &= ~bits; | ||
| 285 | } | ||
| 286 | out: | ||
| 287 | mutex_unlock(&pcf->lock); | ||
| 288 | |||
| 289 | return ret; | ||
| 290 | } | ||
| 291 | |||
| 292 | int pcf50633_irq_mask(struct pcf50633 *pcf, int irq) | ||
| 293 | { | ||
| 294 | dev_info(pcf->dev, "Masking IRQ %d\n", irq); | ||
| 295 | |||
| 296 | return __pcf50633_irq_mask_set(pcf, irq, 1); | ||
| 297 | } | ||
| 298 | EXPORT_SYMBOL_GPL(pcf50633_irq_mask); | ||
| 299 | |||
| 300 | int pcf50633_irq_unmask(struct pcf50633 *pcf, int irq) | ||
| 301 | { | ||
| 302 | dev_info(pcf->dev, "Unmasking IRQ %d\n", irq); | ||
| 303 | |||
| 304 | return __pcf50633_irq_mask_set(pcf, irq, 0); | ||
| 305 | } | ||
| 306 | EXPORT_SYMBOL_GPL(pcf50633_irq_unmask); | ||
| 307 | |||
| 308 | int pcf50633_irq_mask_get(struct pcf50633 *pcf, int irq) | ||
| 309 | { | ||
| 310 | u8 reg, bits; | ||
| 311 | |||
| 312 | reg = irq >> 3; | ||
| 313 | bits = 1 << (irq & 0x07); | ||
| 314 | |||
| 315 | return pcf->mask_regs[reg] & bits; | ||
| 316 | } | ||
| 317 | EXPORT_SYMBOL_GPL(pcf50633_irq_mask_get); | ||
| 318 | |||
| 319 | static void pcf50633_irq_call_handler(struct pcf50633 *pcf, int irq) | ||
| 320 | { | ||
| 321 | if (pcf->irq_handler[irq].handler) | ||
| 322 | pcf->irq_handler[irq].handler(irq, pcf->irq_handler[irq].data); | ||
| 323 | } | ||
| 324 | |||
| 325 | /* Maximum amount of time ONKEY is held before emergency action is taken */ | ||
| 326 | #define PCF50633_ONKEY1S_TIMEOUT 8 | ||
| 327 | |||
| 328 | static void pcf50633_irq_worker(struct work_struct *work) | ||
| 329 | { | ||
| 330 | struct pcf50633 *pcf; | ||
| 331 | int ret, i, j; | ||
| 332 | u8 pcf_int[5], chgstat; | ||
| 333 | |||
| 334 | pcf = container_of(work, struct pcf50633, irq_work); | ||
| 335 | |||
| 336 | /* Read the 5 INT regs in one transaction */ | ||
| 337 | ret = pcf50633_read_block(pcf, PCF50633_REG_INT1, | ||
| 338 | ARRAY_SIZE(pcf_int), pcf_int); | ||
| 339 | if (ret != ARRAY_SIZE(pcf_int)) { | ||
| 340 | dev_err(pcf->dev, "Error reading INT registers\n"); | ||
| 341 | |||
| 342 | /* | ||
| 343 | * If this doesn't ACK the interrupt to the chip, we'll be | ||
| 344 | * called once again as we're level triggered. | ||
| 345 | */ | ||
| 346 | goto out; | ||
| 347 | } | ||
| 348 | |||
| 349 | /* We immediately read the usb and adapter status. We thus make sure | ||
| 350 | * only of USBINS/USBREM IRQ handlers are called */ | ||
| 351 | if (pcf_int[0] & (PCF50633_INT1_USBINS | PCF50633_INT1_USBREM)) { | ||
| 352 | chgstat = pcf50633_reg_read(pcf, PCF50633_REG_MBCS2); | ||
| 353 | if (chgstat & (0x3 << 4)) | ||
| 354 | pcf_int[0] &= ~(1 << PCF50633_INT1_USBREM); | ||
| 355 | else | ||
| 356 | pcf_int[0] &= ~(1 << PCF50633_INT1_USBINS); | ||
| 357 | } | ||
| 358 | |||
| 359 | /* Make sure only one of ADPINS or ADPREM is set */ | ||
| 360 | if (pcf_int[0] & (PCF50633_INT1_ADPINS | PCF50633_INT1_ADPREM)) { | ||
| 361 | chgstat = pcf50633_reg_read(pcf, PCF50633_REG_MBCS2); | ||
| 362 | if (chgstat & (0x3 << 4)) | ||
| 363 | pcf_int[0] &= ~(1 << PCF50633_INT1_ADPREM); | ||
| 364 | else | ||
| 365 | pcf_int[0] &= ~(1 << PCF50633_INT1_ADPINS); | ||
| 366 | } | ||
| 367 | |||
| 368 | dev_dbg(pcf->dev, "INT1=0x%02x INT2=0x%02x INT3=0x%02x " | ||
| 369 | "INT4=0x%02x INT5=0x%02x\n", pcf_int[0], | ||
| 370 | pcf_int[1], pcf_int[2], pcf_int[3], pcf_int[4]); | ||
| 371 | |||
| 372 | /* Some revisions of the chip don't have a 8s standby mode on | ||
| 373 | * ONKEY1S press. We try to manually do it in such cases. */ | ||
| 374 | if ((pcf_int[0] & PCF50633_INT1_SECOND) && pcf->onkey1s_held) { | ||
| 375 | dev_info(pcf->dev, "ONKEY1S held for %d secs\n", | ||
| 376 | pcf->onkey1s_held); | ||
| 377 | if (pcf->onkey1s_held++ == PCF50633_ONKEY1S_TIMEOUT) | ||
| 378 | if (pcf->pdata->force_shutdown) | ||
| 379 | pcf->pdata->force_shutdown(pcf); | ||
| 380 | } | ||
| 381 | |||
| 382 | if (pcf_int[2] & PCF50633_INT3_ONKEY1S) { | ||
| 383 | dev_info(pcf->dev, "ONKEY1S held\n"); | ||
| 384 | pcf->onkey1s_held = 1 ; | ||
| 385 | |||
| 386 | /* Unmask IRQ_SECOND */ | ||
| 387 | pcf50633_reg_clear_bits(pcf, PCF50633_REG_INT1M, | ||
| 388 | PCF50633_INT1_SECOND); | ||
| 389 | |||
| 390 | /* Unmask IRQ_ONKEYR */ | ||
| 391 | pcf50633_reg_clear_bits(pcf, PCF50633_REG_INT2M, | ||
| 392 | PCF50633_INT2_ONKEYR); | ||
| 393 | } | ||
| 394 | |||
| 395 | if ((pcf_int[1] & PCF50633_INT2_ONKEYR) && pcf->onkey1s_held) { | ||
| 396 | pcf->onkey1s_held = 0; | ||
| 397 | |||
| 398 | /* Mask SECOND and ONKEYR interrupts */ | ||
| 399 | if (pcf->mask_regs[0] & PCF50633_INT1_SECOND) | ||
| 400 | pcf50633_reg_set_bit_mask(pcf, | ||
| 401 | PCF50633_REG_INT1M, | ||
| 402 | PCF50633_INT1_SECOND, | ||
| 403 | PCF50633_INT1_SECOND); | ||
| 404 | |||
| 405 | if (pcf->mask_regs[1] & PCF50633_INT2_ONKEYR) | ||
| 406 | pcf50633_reg_set_bit_mask(pcf, | ||
| 407 | PCF50633_REG_INT2M, | ||
| 408 | PCF50633_INT2_ONKEYR, | ||
| 409 | PCF50633_INT2_ONKEYR); | ||
| 410 | } | ||
| 411 | |||
| 412 | /* Have we just resumed ? */ | ||
| 413 | if (pcf->is_suspended) { | ||
| 414 | pcf->is_suspended = 0; | ||
| 415 | |||
| 416 | /* Set the resume reason filtering out non resumers */ | ||
| 417 | for (i = 0; i < ARRAY_SIZE(pcf_int); i++) | ||
| 418 | pcf->resume_reason[i] = pcf_int[i] & | ||
| 419 | pcf->pdata->resumers[i]; | ||
| 420 | |||
| 421 | /* Make sure we don't pass on any ONKEY events to | ||
| 422 | * userspace now */ | ||
| 423 | pcf_int[1] &= ~(PCF50633_INT2_ONKEYR | PCF50633_INT2_ONKEYF); | ||
| 424 | } | ||
| 425 | |||
| 426 | for (i = 0; i < ARRAY_SIZE(pcf_int); i++) { | ||
| 427 | /* Unset masked interrupts */ | ||
| 428 | pcf_int[i] &= ~pcf->mask_regs[i]; | ||
| 429 | |||
| 430 | for (j = 0; j < 8 ; j++) | ||
| 431 | if (pcf_int[i] & (1 << j)) | ||
| 432 | pcf50633_irq_call_handler(pcf, (i * 8) + j); | ||
| 433 | } | ||
| 434 | |||
| 435 | out: | ||
| 436 | put_device(pcf->dev); | ||
| 437 | enable_irq(pcf->irq); | ||
| 438 | } | ||
| 439 | |||
| 440 | static irqreturn_t pcf50633_irq(int irq, void *data) | ||
| 441 | { | ||
| 442 | struct pcf50633 *pcf = data; | ||
| 443 | |||
| 444 | dev_dbg(pcf->dev, "pcf50633_irq\n"); | ||
| 445 | |||
| 446 | get_device(pcf->dev); | ||
| 447 | disable_irq(pcf->irq); | ||
| 448 | schedule_work(&pcf->irq_work); | ||
| 449 | |||
| 450 | return IRQ_HANDLED; | ||
| 451 | } | ||
| 452 | |||
| 453 | static void | ||
| 454 | pcf50633_client_dev_register(struct pcf50633 *pcf, const char *name, | ||
| 455 | struct platform_device **pdev) | ||
| 456 | { | ||
| 457 | struct pcf50633_subdev_pdata *subdev_pdata; | ||
| 458 | int ret; | ||
| 459 | |||
| 460 | *pdev = platform_device_alloc(name, -1); | ||
| 461 | if (!*pdev) { | ||
| 462 | dev_err(pcf->dev, "Falied to allocate %s\n", name); | ||
| 463 | return; | ||
| 464 | } | ||
| 465 | |||
| 466 | subdev_pdata = kmalloc(sizeof(*subdev_pdata), GFP_KERNEL); | ||
| 467 | if (!subdev_pdata) { | ||
| 468 | dev_err(pcf->dev, "Error allocating subdev pdata\n"); | ||
| 469 | platform_device_put(*pdev); | ||
| 470 | } | ||
| 471 | |||
| 472 | subdev_pdata->pcf = pcf; | ||
| 473 | platform_device_add_data(*pdev, subdev_pdata, sizeof(*subdev_pdata)); | ||
| 474 | |||
| 475 | (*pdev)->dev.parent = pcf->dev; | ||
| 476 | |||
| 477 | ret = platform_device_add(*pdev); | ||
| 478 | if (ret) { | ||
| 479 | dev_err(pcf->dev, "Failed to register %s: %d\n", name, ret); | ||
| 480 | platform_device_put(*pdev); | ||
| 481 | *pdev = NULL; | ||
| 482 | } | ||
| 483 | } | ||
| 484 | |||
| 485 | #ifdef CONFIG_PM | ||
| 486 | static int pcf50633_suspend(struct device *dev, pm_message_t state) | ||
| 487 | { | ||
| 488 | struct pcf50633 *pcf; | ||
| 489 | int ret = 0, i; | ||
| 490 | u8 res[5]; | ||
| 491 | |||
| 492 | pcf = dev_get_drvdata(dev); | ||
| 493 | |||
| 494 | /* Make sure our interrupt handlers are not called | ||
| 495 | * henceforth */ | ||
| 496 | disable_irq(pcf->irq); | ||
| 497 | |||
| 498 | /* Make sure that any running IRQ worker has quit */ | ||
| 499 | cancel_work_sync(&pcf->irq_work); | ||
| 500 | |||
| 501 | /* Save the masks */ | ||
| 502 | ret = pcf50633_read_block(pcf, PCF50633_REG_INT1M, | ||
| 503 | ARRAY_SIZE(pcf->suspend_irq_masks), | ||
| 504 | pcf->suspend_irq_masks); | ||
| 505 | if (ret < 0) { | ||
| 506 | dev_err(pcf->dev, "error saving irq masks\n"); | ||
| 507 | goto out; | ||
| 508 | } | ||
| 509 | |||
| 510 | /* Write wakeup irq masks */ | ||
| 511 | for (i = 0; i < ARRAY_SIZE(res); i++) | ||
| 512 | res[i] = ~pcf->pdata->resumers[i]; | ||
| 513 | |||
| 514 | ret = pcf50633_write_block(pcf, PCF50633_REG_INT1M, | ||
| 515 | ARRAY_SIZE(res), &res[0]); | ||
| 516 | if (ret < 0) { | ||
| 517 | dev_err(pcf->dev, "error writing wakeup irq masks\n"); | ||
| 518 | goto out; | ||
| 519 | } | ||
| 520 | |||
| 521 | pcf->is_suspended = 1; | ||
| 522 | |||
| 523 | out: | ||
| 524 | return ret; | ||
| 525 | } | ||
| 526 | |||
| 527 | static int pcf50633_resume(struct device *dev) | ||
| 528 | { | ||
| 529 | struct pcf50633 *pcf; | ||
| 530 | int ret; | ||
| 531 | |||
| 532 | pcf = dev_get_drvdata(dev); | ||
| 533 | |||
| 534 | /* Write the saved mask registers */ | ||
| 535 | ret = pcf50633_write_block(pcf, PCF50633_REG_INT1M, | ||
| 536 | ARRAY_SIZE(pcf->suspend_irq_masks), | ||
| 537 | pcf->suspend_irq_masks); | ||
| 538 | if (ret < 0) | ||
| 539 | dev_err(pcf->dev, "Error restoring saved suspend masks\n"); | ||
| 540 | |||
| 541 | /* Restore regulators' state */ | ||
| 542 | |||
| 543 | |||
| 544 | get_device(pcf->dev); | ||
| 545 | |||
| 546 | /* | ||
| 547 | * Clear any pending interrupts and set resume reason if any. | ||
| 548 | * This will leave with enable_irq() | ||
| 549 | */ | ||
| 550 | pcf50633_irq_worker(&pcf->irq_work); | ||
| 551 | |||
| 552 | return 0; | ||
| 553 | } | ||
| 554 | #else | ||
| 555 | #define pcf50633_suspend NULL | ||
| 556 | #define pcf50633_resume NULL | ||
| 557 | #endif | ||
| 558 | |||
| 559 | static int __devinit pcf50633_probe(struct i2c_client *client, | ||
| 560 | const struct i2c_device_id *ids) | ||
| 561 | { | ||
| 562 | struct pcf50633 *pcf; | ||
| 563 | struct pcf50633_platform_data *pdata = client->dev.platform_data; | ||
| 564 | int i, ret = 0; | ||
| 565 | int version, variant; | ||
| 566 | |||
| 567 | pcf = kzalloc(sizeof(*pcf), GFP_KERNEL); | ||
| 568 | if (!pcf) | ||
| 569 | return -ENOMEM; | ||
| 570 | |||
| 571 | pcf->pdata = pdata; | ||
| 572 | |||
| 573 | mutex_init(&pcf->lock); | ||
| 574 | |||
| 575 | i2c_set_clientdata(client, pcf); | ||
| 576 | pcf->dev = &client->dev; | ||
| 577 | pcf->i2c_client = client; | ||
| 578 | pcf->irq = client->irq; | ||
| 579 | |||
| 580 | INIT_WORK(&pcf->irq_work, pcf50633_irq_worker); | ||
| 581 | |||
| 582 | version = pcf50633_reg_read(pcf, 0); | ||
| 583 | variant = pcf50633_reg_read(pcf, 1); | ||
| 584 | if (version < 0 || variant < 0) { | ||
| 585 | dev_err(pcf->dev, "Unable to probe pcf50633\n"); | ||
| 586 | ret = -ENODEV; | ||
| 587 | goto err; | ||
| 588 | } | ||
| 589 | |||
| 590 | dev_info(pcf->dev, "Probed device version %d variant %d\n", | ||
| 591 | version, variant); | ||
| 592 | |||
| 593 | /* Enable all interrupts except RTC SECOND */ | ||
| 594 | pcf->mask_regs[0] = 0x80; | ||
| 595 | pcf50633_reg_write(pcf, PCF50633_REG_INT1M, pcf->mask_regs[0]); | ||
| 596 | pcf50633_reg_write(pcf, PCF50633_REG_INT2M, 0x00); | ||
| 597 | pcf50633_reg_write(pcf, PCF50633_REG_INT3M, 0x00); | ||
| 598 | pcf50633_reg_write(pcf, PCF50633_REG_INT4M, 0x00); | ||
| 599 | pcf50633_reg_write(pcf, PCF50633_REG_INT5M, 0x00); | ||
| 600 | |||
| 601 | /* Create sub devices */ | ||
| 602 | pcf50633_client_dev_register(pcf, "pcf50633-input", | ||
| 603 | &pcf->input_pdev); | ||
| 604 | pcf50633_client_dev_register(pcf, "pcf50633-rtc", | ||
| 605 | &pcf->rtc_pdev); | ||
| 606 | pcf50633_client_dev_register(pcf, "pcf50633-mbc", | ||
| 607 | &pcf->mbc_pdev); | ||
| 608 | pcf50633_client_dev_register(pcf, "pcf50633-adc", | ||
| 609 | &pcf->adc_pdev); | ||
| 610 | |||
| 611 | for (i = 0; i < PCF50633_NUM_REGULATORS; i++) { | ||
| 612 | struct platform_device *pdev; | ||
| 613 | |||
| 614 | pdev = platform_device_alloc("pcf50633-regltr", i); | ||
| 615 | if (!pdev) { | ||
| 616 | dev_err(pcf->dev, "Cannot create regulator\n"); | ||
| 617 | continue; | ||
| 618 | } | ||
| 619 | |||
| 620 | pdev->dev.parent = pcf->dev; | ||
| 621 | pdev->dev.platform_data = &pdata->reg_init_data[i]; | ||
| 622 | pdev->dev.driver_data = pcf; | ||
| 623 | pcf->regulator_pdev[i] = pdev; | ||
| 624 | |||
| 625 | platform_device_add(pdev); | ||
| 626 | } | ||
| 627 | |||
| 628 | if (client->irq) { | ||
| 629 | set_irq_handler(client->irq, handle_level_irq); | ||
| 630 | ret = request_irq(client->irq, pcf50633_irq, | ||
| 631 | IRQF_TRIGGER_LOW, "pcf50633", pcf); | ||
| 632 | |||
| 633 | if (ret) { | ||
| 634 | dev_err(pcf->dev, "Failed to request IRQ %d\n", ret); | ||
| 635 | goto err; | ||
| 636 | } | ||
| 637 | } else { | ||
| 638 | dev_err(pcf->dev, "No IRQ configured\n"); | ||
| 639 | goto err; | ||
| 640 | } | ||
| 641 | |||
| 642 | if (enable_irq_wake(client->irq) < 0) | ||
| 643 | dev_err(pcf->dev, "IRQ %u cannot be enabled as wake-up source" | ||
| 644 | "in this hardware revision", client->irq); | ||
| 645 | |||
| 646 | ret = sysfs_create_group(&client->dev.kobj, &pcf_attr_group); | ||
| 647 | if (ret) | ||
| 648 | dev_err(pcf->dev, "error creating sysfs entries\n"); | ||
| 649 | |||
| 650 | if (pdata->probe_done) | ||
| 651 | pdata->probe_done(pcf); | ||
| 652 | |||
| 653 | return 0; | ||
| 654 | |||
| 655 | err: | ||
| 656 | kfree(pcf); | ||
| 657 | return ret; | ||
| 658 | } | ||
| 659 | |||
| 660 | static int __devexit pcf50633_remove(struct i2c_client *client) | ||
| 661 | { | ||
| 662 | struct pcf50633 *pcf = i2c_get_clientdata(client); | ||
| 663 | int i; | ||
| 664 | |||
| 665 | free_irq(pcf->irq, pcf); | ||
| 666 | |||
| 667 | platform_device_unregister(pcf->input_pdev); | ||
| 668 | platform_device_unregister(pcf->rtc_pdev); | ||
| 669 | platform_device_unregister(pcf->mbc_pdev); | ||
| 670 | platform_device_unregister(pcf->adc_pdev); | ||
| 671 | |||
| 672 | for (i = 0; i < PCF50633_NUM_REGULATORS; i++) | ||
| 673 | platform_device_unregister(pcf->regulator_pdev[i]); | ||
| 674 | |||
| 675 | kfree(pcf); | ||
| 676 | |||
| 677 | return 0; | ||
| 678 | } | ||
| 679 | |||
| 680 | static struct i2c_device_id pcf50633_id_table[] = { | ||
| 681 | {"pcf50633", 0x73}, | ||
| 682 | }; | ||
| 683 | |||
| 684 | static struct i2c_driver pcf50633_driver = { | ||
| 685 | .driver = { | ||
| 686 | .name = "pcf50633", | ||
| 687 | .suspend = pcf50633_suspend, | ||
| 688 | .resume = pcf50633_resume, | ||
| 689 | }, | ||
| 690 | .id_table = pcf50633_id_table, | ||
| 691 | .probe = pcf50633_probe, | ||
| 692 | .remove = __devexit_p(pcf50633_remove), | ||
| 693 | }; | ||
| 694 | |||
| 695 | static int __init pcf50633_init(void) | ||
| 696 | { | ||
| 697 | return i2c_add_driver(&pcf50633_driver); | ||
| 698 | } | ||
| 699 | |||
| 700 | static void __exit pcf50633_exit(void) | ||
| 701 | { | ||
| 702 | i2c_del_driver(&pcf50633_driver); | ||
| 703 | } | ||
| 704 | |||
| 705 | MODULE_DESCRIPTION("I2C chip driver for NXP PCF50633 PMU"); | ||
| 706 | MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>"); | ||
| 707 | MODULE_LICENSE("GPL"); | ||
| 708 | |||
| 709 | module_init(pcf50633_init); | ||
| 710 | module_exit(pcf50633_exit); | ||
diff --git a/drivers/mfd/pcf50633-gpio.c b/drivers/mfd/pcf50633-gpio.c new file mode 100644 index 000000000000..2fa2eca5c9cc --- /dev/null +++ b/drivers/mfd/pcf50633-gpio.c | |||
| @@ -0,0 +1,118 @@ | |||
| 1 | /* NXP PCF50633 GPIO Driver | ||
| 2 | * | ||
| 3 | * (C) 2006-2008 by Openmoko, Inc. | ||
| 4 | * Author: Balaji Rao <balajirrao@openmoko.org> | ||
| 5 | * All rights reserved. | ||
| 6 | * | ||
| 7 | * Broken down from monstrous PCF50633 driver mainly by | ||
| 8 | * Harald Welte, Andy Green and Werner Almesberger | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify it | ||
| 11 | * under the terms of the GNU General Public License as published by the | ||
| 12 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 13 | * option) any later version. | ||
| 14 | * | ||
| 15 | */ | ||
| 16 | |||
| 17 | #include <linux/kernel.h> | ||
| 18 | |||
| 19 | #include <linux/mfd/pcf50633/core.h> | ||
| 20 | #include <linux/mfd/pcf50633/gpio.h> | ||
| 21 | |||
| 22 | enum pcf50633_regulator_id { | ||
| 23 | PCF50633_REGULATOR_AUTO, | ||
| 24 | PCF50633_REGULATOR_DOWN1, | ||
| 25 | PCF50633_REGULATOR_DOWN2, | ||
| 26 | PCF50633_REGULATOR_LDO1, | ||
| 27 | PCF50633_REGULATOR_LDO2, | ||
| 28 | PCF50633_REGULATOR_LDO3, | ||
| 29 | PCF50633_REGULATOR_LDO4, | ||
| 30 | PCF50633_REGULATOR_LDO5, | ||
| 31 | PCF50633_REGULATOR_LDO6, | ||
| 32 | PCF50633_REGULATOR_HCLDO, | ||
| 33 | PCF50633_REGULATOR_MEMLDO, | ||
| 34 | }; | ||
| 35 | |||
| 36 | #define PCF50633_REG_AUTOOUT 0x1a | ||
| 37 | #define PCF50633_REG_DOWN1OUT 0x1e | ||
| 38 | #define PCF50633_REG_DOWN2OUT 0x22 | ||
| 39 | #define PCF50633_REG_MEMLDOOUT 0x26 | ||
| 40 | #define PCF50633_REG_LDO1OUT 0x2d | ||
| 41 | #define PCF50633_REG_LDO2OUT 0x2f | ||
| 42 | #define PCF50633_REG_LDO3OUT 0x31 | ||
| 43 | #define PCF50633_REG_LDO4OUT 0x33 | ||
| 44 | #define PCF50633_REG_LDO5OUT 0x35 | ||
| 45 | #define PCF50633_REG_LDO6OUT 0x37 | ||
| 46 | #define PCF50633_REG_HCLDOOUT 0x39 | ||
| 47 | |||
| 48 | static const u8 pcf50633_regulator_registers[PCF50633_NUM_REGULATORS] = { | ||
| 49 | [PCF50633_REGULATOR_AUTO] = PCF50633_REG_AUTOOUT, | ||
| 50 | [PCF50633_REGULATOR_DOWN1] = PCF50633_REG_DOWN1OUT, | ||
| 51 | [PCF50633_REGULATOR_DOWN2] = PCF50633_REG_DOWN2OUT, | ||
| 52 | [PCF50633_REGULATOR_MEMLDO] = PCF50633_REG_MEMLDOOUT, | ||
| 53 | [PCF50633_REGULATOR_LDO1] = PCF50633_REG_LDO1OUT, | ||
| 54 | [PCF50633_REGULATOR_LDO2] = PCF50633_REG_LDO2OUT, | ||
| 55 | [PCF50633_REGULATOR_LDO3] = PCF50633_REG_LDO3OUT, | ||
| 56 | [PCF50633_REGULATOR_LDO4] = PCF50633_REG_LDO4OUT, | ||
| 57 | [PCF50633_REGULATOR_LDO5] = PCF50633_REG_LDO5OUT, | ||
| 58 | [PCF50633_REGULATOR_LDO6] = PCF50633_REG_LDO6OUT, | ||
| 59 | [PCF50633_REGULATOR_HCLDO] = PCF50633_REG_HCLDOOUT, | ||
| 60 | }; | ||
| 61 | |||
| 62 | int pcf50633_gpio_set(struct pcf50633 *pcf, int gpio, u8 val) | ||
| 63 | { | ||
| 64 | u8 reg; | ||
| 65 | |||
| 66 | reg = gpio - PCF50633_GPIO1 + PCF50633_REG_GPIO1CFG; | ||
| 67 | |||
| 68 | return pcf50633_reg_set_bit_mask(pcf, reg, 0x07, val); | ||
| 69 | } | ||
| 70 | EXPORT_SYMBOL_GPL(pcf50633_gpio_set); | ||
| 71 | |||
| 72 | u8 pcf50633_gpio_get(struct pcf50633 *pcf, int gpio) | ||
| 73 | { | ||
| 74 | u8 reg, val; | ||
| 75 | |||
| 76 | reg = gpio - PCF50633_GPIO1 + PCF50633_REG_GPIO1CFG; | ||
| 77 | val = pcf50633_reg_read(pcf, reg) & 0x07; | ||
| 78 | |||
| 79 | return val; | ||
| 80 | } | ||
| 81 | EXPORT_SYMBOL_GPL(pcf50633_gpio_get); | ||
| 82 | |||
| 83 | int pcf50633_gpio_invert_set(struct pcf50633 *pcf, int gpio, int invert) | ||
| 84 | { | ||
| 85 | u8 val, reg; | ||
| 86 | |||
| 87 | reg = gpio - PCF50633_GPIO1 + PCF50633_REG_GPIO1CFG; | ||
| 88 | val = !!invert << 3; | ||
| 89 | |||
| 90 | return pcf50633_reg_set_bit_mask(pcf, reg, 1 << 3, val); | ||
| 91 | } | ||
| 92 | EXPORT_SYMBOL_GPL(pcf50633_gpio_invert_set); | ||
| 93 | |||
| 94 | int pcf50633_gpio_invert_get(struct pcf50633 *pcf, int gpio) | ||
| 95 | { | ||
| 96 | u8 reg, val; | ||
| 97 | |||
| 98 | reg = gpio - PCF50633_GPIO1 + PCF50633_REG_GPIO1CFG; | ||
| 99 | val = pcf50633_reg_read(pcf, reg); | ||
| 100 | |||
| 101 | return val & (1 << 3); | ||
| 102 | } | ||
| 103 | EXPORT_SYMBOL_GPL(pcf50633_gpio_invert_get); | ||
| 104 | |||
| 105 | int pcf50633_gpio_power_supply_set(struct pcf50633 *pcf, | ||
| 106 | int gpio, int regulator, int on) | ||
| 107 | { | ||
| 108 | u8 reg, val, mask; | ||
| 109 | |||
| 110 | /* the *ENA register is always one after the *OUT register */ | ||
| 111 | reg = pcf50633_regulator_registers[regulator] + 1; | ||
| 112 | |||
| 113 | val = !!on << (gpio - PCF50633_GPIO1); | ||
| 114 | mask = 1 << (gpio - PCF50633_GPIO1); | ||
| 115 | |||
| 116 | return pcf50633_reg_set_bit_mask(pcf, reg, mask, val); | ||
| 117 | } | ||
| 118 | EXPORT_SYMBOL_GPL(pcf50633_gpio_power_supply_set); | ||
diff --git a/drivers/mfd/sm501.c b/drivers/mfd/sm501.c index 170f9d47c2f9..0e5761f12634 100644 --- a/drivers/mfd/sm501.c +++ b/drivers/mfd/sm501.c | |||
| @@ -41,6 +41,7 @@ struct sm501_gpio_chip { | |||
| 41 | struct gpio_chip gpio; | 41 | struct gpio_chip gpio; |
| 42 | struct sm501_gpio *ourgpio; /* to get back to parent. */ | 42 | struct sm501_gpio *ourgpio; /* to get back to parent. */ |
| 43 | void __iomem *regbase; | 43 | void __iomem *regbase; |
| 44 | void __iomem *control; /* address of control reg. */ | ||
| 44 | }; | 45 | }; |
| 45 | 46 | ||
| 46 | struct sm501_gpio { | 47 | struct sm501_gpio { |
| @@ -908,6 +909,25 @@ static int sm501_gpio_get(struct gpio_chip *chip, unsigned offset) | |||
| 908 | return result & 1UL; | 909 | return result & 1UL; |
| 909 | } | 910 | } |
| 910 | 911 | ||
| 912 | static void sm501_gpio_ensure_gpio(struct sm501_gpio_chip *smchip, | ||
| 913 | unsigned long bit) | ||
| 914 | { | ||
| 915 | unsigned long ctrl; | ||
| 916 | |||
| 917 | /* check and modify if this pin is not set as gpio. */ | ||
| 918 | |||
| 919 | if (readl(smchip->control) & bit) { | ||
| 920 | dev_info(sm501_gpio_to_dev(smchip->ourgpio)->dev, | ||
| 921 | "changing mode of gpio, bit %08lx\n", bit); | ||
| 922 | |||
| 923 | ctrl = readl(smchip->control); | ||
| 924 | ctrl &= ~bit; | ||
| 925 | writel(ctrl, smchip->control); | ||
| 926 | |||
| 927 | sm501_sync_regs(sm501_gpio_to_dev(smchip->ourgpio)); | ||
| 928 | } | ||
| 929 | } | ||
| 930 | |||
| 911 | static void sm501_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | 931 | static void sm501_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
| 912 | 932 | ||
| 913 | { | 933 | { |
| @@ -929,6 +949,8 @@ static void sm501_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |||
| 929 | writel(val, regs); | 949 | writel(val, regs); |
| 930 | 950 | ||
| 931 | sm501_sync_regs(sm501_gpio_to_dev(smgpio)); | 951 | sm501_sync_regs(sm501_gpio_to_dev(smgpio)); |
| 952 | sm501_gpio_ensure_gpio(smchip, bit); | ||
| 953 | |||
| 932 | spin_unlock_irqrestore(&smgpio->lock, save); | 954 | spin_unlock_irqrestore(&smgpio->lock, save); |
| 933 | } | 955 | } |
| 934 | 956 | ||
| @@ -941,8 +963,8 @@ static int sm501_gpio_input(struct gpio_chip *chip, unsigned offset) | |||
| 941 | unsigned long save; | 963 | unsigned long save; |
| 942 | unsigned long ddr; | 964 | unsigned long ddr; |
| 943 | 965 | ||
| 944 | dev_info(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n", | 966 | dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n", |
| 945 | __func__, chip, offset); | 967 | __func__, chip, offset); |
| 946 | 968 | ||
| 947 | spin_lock_irqsave(&smgpio->lock, save); | 969 | spin_lock_irqsave(&smgpio->lock, save); |
| 948 | 970 | ||
| @@ -950,6 +972,8 @@ static int sm501_gpio_input(struct gpio_chip *chip, unsigned offset) | |||
| 950 | writel(ddr & ~bit, regs + SM501_GPIO_DDR_LOW); | 972 | writel(ddr & ~bit, regs + SM501_GPIO_DDR_LOW); |
| 951 | 973 | ||
| 952 | sm501_sync_regs(sm501_gpio_to_dev(smgpio)); | 974 | sm501_sync_regs(sm501_gpio_to_dev(smgpio)); |
| 975 | sm501_gpio_ensure_gpio(smchip, bit); | ||
| 976 | |||
| 953 | spin_unlock_irqrestore(&smgpio->lock, save); | 977 | spin_unlock_irqrestore(&smgpio->lock, save); |
| 954 | 978 | ||
| 955 | return 0; | 979 | return 0; |
| @@ -1012,9 +1036,11 @@ static int __devinit sm501_gpio_register_chip(struct sm501_devdata *sm, | |||
| 1012 | if (base > 0) | 1036 | if (base > 0) |
| 1013 | base += 32; | 1037 | base += 32; |
| 1014 | chip->regbase = gpio->regs + SM501_GPIO_DATA_HIGH; | 1038 | chip->regbase = gpio->regs + SM501_GPIO_DATA_HIGH; |
| 1039 | chip->control = sm->regs + SM501_GPIO63_32_CONTROL; | ||
| 1015 | gchip->label = "SM501-HIGH"; | 1040 | gchip->label = "SM501-HIGH"; |
| 1016 | } else { | 1041 | } else { |
| 1017 | chip->regbase = gpio->regs + SM501_GPIO_DATA_LOW; | 1042 | chip->regbase = gpio->regs + SM501_GPIO_DATA_LOW; |
| 1043 | chip->control = sm->regs + SM501_GPIO31_0_CONTROL; | ||
| 1018 | gchip->label = "SM501-LOW"; | 1044 | gchip->label = "SM501-LOW"; |
| 1019 | } | 1045 | } |
| 1020 | 1046 | ||
diff --git a/drivers/mfd/twl4030-core.c b/drivers/mfd/twl4030-core.c index b59c385cbc12..074b11ffbf41 100644 --- a/drivers/mfd/twl4030-core.c +++ b/drivers/mfd/twl4030-core.c | |||
| @@ -38,6 +38,9 @@ | |||
| 38 | #include <linux/i2c.h> | 38 | #include <linux/i2c.h> |
| 39 | #include <linux/i2c/twl4030.h> | 39 | #include <linux/i2c/twl4030.h> |
| 40 | 40 | ||
| 41 | #ifdef CONFIG_ARM | ||
| 42 | #include <mach/cpu.h> | ||
| 43 | #endif | ||
| 41 | 44 | ||
| 42 | /* | 45 | /* |
| 43 | * The TWL4030 "Triton 2" is one of a family of a multi-function "Power | 46 | * The TWL4030 "Triton 2" is one of a family of a multi-function "Power |
diff --git a/drivers/net/3c503.c b/drivers/net/3c503.c index c092c3929224..5b91a85fe107 100644 --- a/drivers/net/3c503.c +++ b/drivers/net/3c503.c | |||
| @@ -177,6 +177,7 @@ static const struct net_device_ops el2_netdev_ops = { | |||
| 177 | .ndo_get_stats = eip_get_stats, | 177 | .ndo_get_stats = eip_get_stats, |
| 178 | .ndo_set_multicast_list = eip_set_multicast_list, | 178 | .ndo_set_multicast_list = eip_set_multicast_list, |
| 179 | .ndo_validate_addr = eth_validate_addr, | 179 | .ndo_validate_addr = eth_validate_addr, |
| 180 | .ndo_set_mac_address = eth_mac_addr, | ||
| 180 | .ndo_change_mtu = eth_change_mtu, | 181 | .ndo_change_mtu = eth_change_mtu, |
| 181 | #ifdef CONFIG_NET_POLL_CONTROLLER | 182 | #ifdef CONFIG_NET_POLL_CONTROLLER |
| 182 | .ndo_poll_controller = eip_poll, | 183 | .ndo_poll_controller = eip_poll, |
diff --git a/drivers/net/3c59x.c b/drivers/net/3c59x.c index 665e7fdf27a1..cdbbb6226fc5 100644 --- a/drivers/net/3c59x.c +++ b/drivers/net/3c59x.c | |||
| @@ -3109,6 +3109,8 @@ static void acpi_set_WOL(struct net_device *dev) | |||
| 3109 | struct vortex_private *vp = netdev_priv(dev); | 3109 | struct vortex_private *vp = netdev_priv(dev); |
| 3110 | void __iomem *ioaddr = vp->ioaddr; | 3110 | void __iomem *ioaddr = vp->ioaddr; |
| 3111 | 3111 | ||
| 3112 | device_set_wakeup_enable(vp->gendev, vp->enable_wol); | ||
| 3113 | |||
| 3112 | if (vp->enable_wol) { | 3114 | if (vp->enable_wol) { |
| 3113 | /* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */ | 3115 | /* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */ |
| 3114 | EL3WINDOW(7); | 3116 | EL3WINDOW(7); |
diff --git a/drivers/net/8139cp.c b/drivers/net/8139cp.c index dd7ac8290aec..4e19ae3ce6be 100644 --- a/drivers/net/8139cp.c +++ b/drivers/net/8139cp.c | |||
| @@ -1821,6 +1821,7 @@ static const struct net_device_ops cp_netdev_ops = { | |||
| 1821 | .ndo_open = cp_open, | 1821 | .ndo_open = cp_open, |
| 1822 | .ndo_stop = cp_close, | 1822 | .ndo_stop = cp_close, |
| 1823 | .ndo_validate_addr = eth_validate_addr, | 1823 | .ndo_validate_addr = eth_validate_addr, |
| 1824 | .ndo_set_mac_address = eth_mac_addr, | ||
| 1824 | .ndo_set_multicast_list = cp_set_rx_mode, | 1825 | .ndo_set_multicast_list = cp_set_rx_mode, |
| 1825 | .ndo_get_stats = cp_get_stats, | 1826 | .ndo_get_stats = cp_get_stats, |
| 1826 | .ndo_do_ioctl = cp_ioctl, | 1827 | .ndo_do_ioctl = cp_ioctl, |
| @@ -1832,6 +1833,7 @@ static const struct net_device_ops cp_netdev_ops = { | |||
| 1832 | #ifdef BROKEN | 1833 | #ifdef BROKEN |
| 1833 | .ndo_change_mtu = cp_change_mtu, | 1834 | .ndo_change_mtu = cp_change_mtu, |
| 1834 | #endif | 1835 | #endif |
| 1836 | |||
| 1835 | #ifdef CONFIG_NET_POLL_CONTROLLER | 1837 | #ifdef CONFIG_NET_POLL_CONTROLLER |
| 1836 | .ndo_poll_controller = cp_poll_controller, | 1838 | .ndo_poll_controller = cp_poll_controller, |
| 1837 | #endif | 1839 | #endif |
diff --git a/drivers/net/8139too.c b/drivers/net/8139too.c index fe370f805793..a5b24202d564 100644 --- a/drivers/net/8139too.c +++ b/drivers/net/8139too.c | |||
| @@ -917,6 +917,7 @@ static const struct net_device_ops rtl8139_netdev_ops = { | |||
| 917 | .ndo_stop = rtl8139_close, | 917 | .ndo_stop = rtl8139_close, |
| 918 | .ndo_get_stats = rtl8139_get_stats, | 918 | .ndo_get_stats = rtl8139_get_stats, |
| 919 | .ndo_validate_addr = eth_validate_addr, | 919 | .ndo_validate_addr = eth_validate_addr, |
| 920 | .ndo_set_mac_address = eth_mac_addr, | ||
| 920 | .ndo_start_xmit = rtl8139_start_xmit, | 921 | .ndo_start_xmit = rtl8139_start_xmit, |
| 921 | .ndo_set_multicast_list = rtl8139_set_rx_mode, | 922 | .ndo_set_multicast_list = rtl8139_set_rx_mode, |
| 922 | .ndo_do_ioctl = netdev_ioctl, | 923 | .ndo_do_ioctl = netdev_ioctl, |
| @@ -924,7 +925,6 @@ static const struct net_device_ops rtl8139_netdev_ops = { | |||
| 924 | #ifdef CONFIG_NET_POLL_CONTROLLER | 925 | #ifdef CONFIG_NET_POLL_CONTROLLER |
| 925 | .ndo_poll_controller = rtl8139_poll_controller, | 926 | .ndo_poll_controller = rtl8139_poll_controller, |
| 926 | #endif | 927 | #endif |
| 927 | |||
| 928 | }; | 928 | }; |
| 929 | 929 | ||
| 930 | static int __devinit rtl8139_init_one (struct pci_dev *pdev, | 930 | static int __devinit rtl8139_init_one (struct pci_dev *pdev, |
diff --git a/drivers/net/8390.c b/drivers/net/8390.c index fbe609a51e02..ec3e22e6306f 100644 --- a/drivers/net/8390.c +++ b/drivers/net/8390.c | |||
| @@ -63,6 +63,7 @@ const struct net_device_ops ei_netdev_ops = { | |||
| 63 | .ndo_get_stats = ei_get_stats, | 63 | .ndo_get_stats = ei_get_stats, |
| 64 | .ndo_set_multicast_list = ei_set_multicast_list, | 64 | .ndo_set_multicast_list = ei_set_multicast_list, |
| 65 | .ndo_validate_addr = eth_validate_addr, | 65 | .ndo_validate_addr = eth_validate_addr, |
| 66 | .ndo_set_mac_address = eth_mac_addr, | ||
| 66 | .ndo_change_mtu = eth_change_mtu, | 67 | .ndo_change_mtu = eth_change_mtu, |
| 67 | #ifdef CONFIG_NET_POLL_CONTROLLER | 68 | #ifdef CONFIG_NET_POLL_CONTROLLER |
| 68 | .ndo_poll_controller = ei_poll, | 69 | .ndo_poll_controller = ei_poll, |
diff --git a/drivers/net/8390p.c b/drivers/net/8390p.c index ee70b358a816..da863c91d1d0 100644 --- a/drivers/net/8390p.c +++ b/drivers/net/8390p.c | |||
| @@ -68,6 +68,7 @@ const struct net_device_ops eip_netdev_ops = { | |||
| 68 | .ndo_get_stats = eip_get_stats, | 68 | .ndo_get_stats = eip_get_stats, |
| 69 | .ndo_set_multicast_list = eip_set_multicast_list, | 69 | .ndo_set_multicast_list = eip_set_multicast_list, |
| 70 | .ndo_validate_addr = eth_validate_addr, | 70 | .ndo_validate_addr = eth_validate_addr, |
| 71 | .ndo_set_mac_address = eth_mac_addr, | ||
| 71 | .ndo_change_mtu = eth_change_mtu, | 72 | .ndo_change_mtu = eth_change_mtu, |
| 72 | #ifdef CONFIG_NET_POLL_CONTROLLER | 73 | #ifdef CONFIG_NET_POLL_CONTROLLER |
| 73 | .ndo_poll_controller = eip_poll, | 74 | .ndo_poll_controller = eip_poll, |
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 65afda4a62d9..9fe8cb7d43ac 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig | |||
| @@ -1600,7 +1600,7 @@ config 8139_OLD_RX_RESET | |||
| 1600 | old RX-reset behavior. If unsure, say N. | 1600 | old RX-reset behavior. If unsure, say N. |
| 1601 | 1601 | ||
| 1602 | config R6040 | 1602 | config R6040 |
| 1603 | tristate "RDC R6040 Fast Ethernet Adapter support (EXPERIMENTAL)" | 1603 | tristate "RDC R6040 Fast Ethernet Adapter support" |
| 1604 | depends on NET_PCI && PCI | 1604 | depends on NET_PCI && PCI |
| 1605 | select CRC32 | 1605 | select CRC32 |
| 1606 | select MII | 1606 | select MII |
diff --git a/drivers/net/acenic.c b/drivers/net/acenic.c index 5b396ff6c83f..9589d620639d 100644 --- a/drivers/net/acenic.c +++ b/drivers/net/acenic.c | |||
| @@ -460,6 +460,7 @@ static const struct net_device_ops ace_netdev_ops = { | |||
| 460 | .ndo_get_stats = ace_get_stats, | 460 | .ndo_get_stats = ace_get_stats, |
| 461 | .ndo_start_xmit = ace_start_xmit, | 461 | .ndo_start_xmit = ace_start_xmit, |
| 462 | .ndo_set_multicast_list = ace_set_multicast_list, | 462 | .ndo_set_multicast_list = ace_set_multicast_list, |
| 463 | .ndo_validate_addr = eth_validate_addr, | ||
| 463 | .ndo_set_mac_address = ace_set_mac_addr, | 464 | .ndo_set_mac_address = ace_set_mac_addr, |
| 464 | .ndo_change_mtu = ace_change_mtu, | 465 | .ndo_change_mtu = ace_change_mtu, |
| 465 | #if ACENIC_DO_VLAN | 466 | #if ACENIC_DO_VLAN |
diff --git a/drivers/net/arm/etherh.c b/drivers/net/arm/etherh.c index 6278606d1049..745ac188babe 100644 --- a/drivers/net/arm/etherh.c +++ b/drivers/net/arm/etherh.c | |||
| @@ -646,6 +646,7 @@ static const struct net_device_ops etherh_netdev_ops = { | |||
| 646 | .ndo_get_stats = ei_get_stats, | 646 | .ndo_get_stats = ei_get_stats, |
| 647 | .ndo_set_multicast_list = ei_set_multicast_list, | 647 | .ndo_set_multicast_list = ei_set_multicast_list, |
| 648 | .ndo_validate_addr = eth_validate_addr, | 648 | .ndo_validate_addr = eth_validate_addr, |
| 649 | .ndo_set_mac_addr = eth_set_mac_addr, | ||
| 649 | .ndo_change_mtu = eth_change_mtu, | 650 | .ndo_change_mtu = eth_change_mtu, |
| 650 | #ifdef CONFIG_NET_POLL_CONTROLLER | 651 | #ifdef CONFIG_NET_POLL_CONTROLLER |
| 651 | .ndo_poll_controller = ei_poll, | 652 | .ndo_poll_controller = ei_poll, |
diff --git a/drivers/net/arm/ks8695net.c b/drivers/net/arm/ks8695net.c index 9ad22d1b00fd..1cf2f949c0b4 100644 --- a/drivers/net/arm/ks8695net.c +++ b/drivers/net/arm/ks8695net.c | |||
| @@ -1357,6 +1357,7 @@ static const struct net_device_ops ks8695_netdev_ops = { | |||
| 1357 | .ndo_start_xmit = ks8695_start_xmit, | 1357 | .ndo_start_xmit = ks8695_start_xmit, |
| 1358 | .ndo_tx_timeout = ks8695_timeout, | 1358 | .ndo_tx_timeout = ks8695_timeout, |
| 1359 | .ndo_set_mac_address = ks8695_set_mac, | 1359 | .ndo_set_mac_address = ks8695_set_mac, |
| 1360 | .ndo_validate_addr = eth_validate_addr, | ||
| 1360 | .ndo_set_multicast_list = ks8695_set_multicast, | 1361 | .ndo_set_multicast_list = ks8695_set_multicast, |
| 1361 | }; | 1362 | }; |
| 1362 | 1363 | ||
diff --git a/drivers/net/b44.c b/drivers/net/b44.c index 6926ebedfdc9..5ae131c147f9 100644 --- a/drivers/net/b44.c +++ b/drivers/net/b44.c | |||
| @@ -73,8 +73,8 @@ | |||
| 73 | (BP)->tx_cons - (BP)->tx_prod - TX_RING_GAP(BP)) | 73 | (BP)->tx_cons - (BP)->tx_prod - TX_RING_GAP(BP)) |
| 74 | #define NEXT_TX(N) (((N) + 1) & (B44_TX_RING_SIZE - 1)) | 74 | #define NEXT_TX(N) (((N) + 1) & (B44_TX_RING_SIZE - 1)) |
| 75 | 75 | ||
| 76 | #define RX_PKT_OFFSET 30 | 76 | #define RX_PKT_OFFSET (RX_HEADER_LEN + 2) |
| 77 | #define RX_PKT_BUF_SZ (1536 + RX_PKT_OFFSET + 64) | 77 | #define RX_PKT_BUF_SZ (1536 + RX_PKT_OFFSET) |
| 78 | 78 | ||
| 79 | /* minimum number of free TX descriptors required to wake up TX process */ | 79 | /* minimum number of free TX descriptors required to wake up TX process */ |
| 80 | #define B44_TX_WAKEUP_THRESH (B44_TX_RING_SIZE / 4) | 80 | #define B44_TX_WAKEUP_THRESH (B44_TX_RING_SIZE / 4) |
| @@ -682,7 +682,6 @@ static int b44_alloc_rx_skb(struct b44 *bp, int src_idx, u32 dest_idx_unmasked) | |||
| 682 | } | 682 | } |
| 683 | 683 | ||
| 684 | rh = (struct rx_header *) skb->data; | 684 | rh = (struct rx_header *) skb->data; |
| 685 | skb_reserve(skb, RX_PKT_OFFSET); | ||
| 686 | 685 | ||
| 687 | rh->len = 0; | 686 | rh->len = 0; |
| 688 | rh->flags = 0; | 687 | rh->flags = 0; |
| @@ -693,13 +692,13 @@ static int b44_alloc_rx_skb(struct b44 *bp, int src_idx, u32 dest_idx_unmasked) | |||
| 693 | if (src_map != NULL) | 692 | if (src_map != NULL) |
| 694 | src_map->skb = NULL; | 693 | src_map->skb = NULL; |
| 695 | 694 | ||
| 696 | ctrl = (DESC_CTRL_LEN & (RX_PKT_BUF_SZ - RX_PKT_OFFSET)); | 695 | ctrl = (DESC_CTRL_LEN & RX_PKT_BUF_SZ); |
| 697 | if (dest_idx == (B44_RX_RING_SIZE - 1)) | 696 | if (dest_idx == (B44_RX_RING_SIZE - 1)) |
| 698 | ctrl |= DESC_CTRL_EOT; | 697 | ctrl |= DESC_CTRL_EOT; |
| 699 | 698 | ||
| 700 | dp = &bp->rx_ring[dest_idx]; | 699 | dp = &bp->rx_ring[dest_idx]; |
| 701 | dp->ctrl = cpu_to_le32(ctrl); | 700 | dp->ctrl = cpu_to_le32(ctrl); |
| 702 | dp->addr = cpu_to_le32((u32) mapping + RX_PKT_OFFSET + bp->dma_offset); | 701 | dp->addr = cpu_to_le32((u32) mapping + bp->dma_offset); |
| 703 | 702 | ||
| 704 | if (bp->flags & B44_FLAG_RX_RING_HACK) | 703 | if (bp->flags & B44_FLAG_RX_RING_HACK) |
| 705 | b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma, | 704 | b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma, |
| @@ -809,8 +808,8 @@ static int b44_rx(struct b44 *bp, int budget) | |||
| 809 | ssb_dma_unmap_single(bp->sdev, map, | 808 | ssb_dma_unmap_single(bp->sdev, map, |
| 810 | skb_size, DMA_FROM_DEVICE); | 809 | skb_size, DMA_FROM_DEVICE); |
| 811 | /* Leave out rx_header */ | 810 | /* Leave out rx_header */ |
| 812 | skb_put(skb, len + RX_PKT_OFFSET); | 811 | skb_put(skb, len + RX_PKT_OFFSET); |
| 813 | skb_pull(skb, RX_PKT_OFFSET); | 812 | skb_pull(skb, RX_PKT_OFFSET); |
| 814 | } else { | 813 | } else { |
| 815 | struct sk_buff *copy_skb; | 814 | struct sk_buff *copy_skb; |
| 816 | 815 | ||
diff --git a/drivers/net/cxgb3/adapter.h b/drivers/net/cxgb3/adapter.h index 5b346f9eaa8b..a89d8cc51205 100644 --- a/drivers/net/cxgb3/adapter.h +++ b/drivers/net/cxgb3/adapter.h | |||
| @@ -50,12 +50,17 @@ struct vlan_group; | |||
| 50 | struct adapter; | 50 | struct adapter; |
| 51 | struct sge_qset; | 51 | struct sge_qset; |
| 52 | 52 | ||
| 53 | enum { /* rx_offload flags */ | ||
| 54 | T3_RX_CSUM = 1 << 0, | ||
| 55 | T3_LRO = 1 << 1, | ||
| 56 | }; | ||
| 57 | |||
| 53 | struct port_info { | 58 | struct port_info { |
| 54 | struct adapter *adapter; | 59 | struct adapter *adapter; |
| 55 | struct vlan_group *vlan_grp; | 60 | struct vlan_group *vlan_grp; |
| 56 | struct sge_qset *qs; | 61 | struct sge_qset *qs; |
| 57 | u8 port_id; | 62 | u8 port_id; |
| 58 | u8 rx_csum_offload; | 63 | u8 rx_offload; |
| 59 | u8 nqsets; | 64 | u8 nqsets; |
| 60 | u8 first_qset; | 65 | u8 first_qset; |
| 61 | struct cphy phy; | 66 | struct cphy phy; |
diff --git a/drivers/net/cxgb3/cxgb3_main.c b/drivers/net/cxgb3/cxgb3_main.c index 2847f947499d..0089746b8d02 100644 --- a/drivers/net/cxgb3/cxgb3_main.c +++ b/drivers/net/cxgb3/cxgb3_main.c | |||
| @@ -546,7 +546,7 @@ static int setup_sge_qsets(struct adapter *adap) | |||
| 546 | pi->qs = &adap->sge.qs[pi->first_qset]; | 546 | pi->qs = &adap->sge.qs[pi->first_qset]; |
| 547 | for (j = pi->first_qset; j < pi->first_qset + pi->nqsets; | 547 | for (j = pi->first_qset; j < pi->first_qset + pi->nqsets; |
| 548 | ++j, ++qset_idx) { | 548 | ++j, ++qset_idx) { |
| 549 | set_qset_lro(dev, qset_idx, pi->rx_csum_offload); | 549 | set_qset_lro(dev, qset_idx, pi->rx_offload & T3_LRO); |
| 550 | err = t3_sge_alloc_qset(adap, qset_idx, 1, | 550 | err = t3_sge_alloc_qset(adap, qset_idx, 1, |
| 551 | (adap->flags & USING_MSIX) ? qset_idx + 1 : | 551 | (adap->flags & USING_MSIX) ? qset_idx + 1 : |
| 552 | irq_idx, | 552 | irq_idx, |
| @@ -1657,17 +1657,19 @@ static u32 get_rx_csum(struct net_device *dev) | |||
| 1657 | { | 1657 | { |
| 1658 | struct port_info *p = netdev_priv(dev); | 1658 | struct port_info *p = netdev_priv(dev); |
| 1659 | 1659 | ||
| 1660 | return p->rx_csum_offload; | 1660 | return p->rx_offload & T3_RX_CSUM; |
| 1661 | } | 1661 | } |
| 1662 | 1662 | ||
| 1663 | static int set_rx_csum(struct net_device *dev, u32 data) | 1663 | static int set_rx_csum(struct net_device *dev, u32 data) |
| 1664 | { | 1664 | { |
| 1665 | struct port_info *p = netdev_priv(dev); | 1665 | struct port_info *p = netdev_priv(dev); |
| 1666 | 1666 | ||
| 1667 | p->rx_csum_offload = data; | 1667 | if (data) { |
| 1668 | if (!data) { | 1668 | p->rx_offload |= T3_RX_CSUM; |
| 1669 | } else { | ||
| 1669 | int i; | 1670 | int i; |
| 1670 | 1671 | ||
| 1672 | p->rx_offload &= ~(T3_RX_CSUM | T3_LRO); | ||
| 1671 | for (i = p->first_qset; i < p->first_qset + p->nqsets; i++) | 1673 | for (i = p->first_qset; i < p->first_qset + p->nqsets; i++) |
| 1672 | set_qset_lro(dev, i, 0); | 1674 | set_qset_lro(dev, i, 0); |
| 1673 | } | 1675 | } |
| @@ -1830,15 +1832,18 @@ static int cxgb3_set_flags(struct net_device *dev, u32 data) | |||
| 1830 | int i; | 1832 | int i; |
| 1831 | 1833 | ||
| 1832 | if (data & ETH_FLAG_LRO) { | 1834 | if (data & ETH_FLAG_LRO) { |
| 1833 | if (!pi->rx_csum_offload) | 1835 | if (!(pi->rx_offload & T3_RX_CSUM)) |
| 1834 | return -EINVAL; | 1836 | return -EINVAL; |
| 1835 | 1837 | ||
| 1838 | pi->rx_offload |= T3_LRO; | ||
| 1836 | for (i = pi->first_qset; i < pi->first_qset + pi->nqsets; i++) | 1839 | for (i = pi->first_qset; i < pi->first_qset + pi->nqsets; i++) |
| 1837 | set_qset_lro(dev, i, 1); | 1840 | set_qset_lro(dev, i, 1); |
| 1838 | 1841 | ||
| 1839 | } else | 1842 | } else { |
| 1843 | pi->rx_offload &= ~T3_LRO; | ||
| 1840 | for (i = pi->first_qset; i < pi->first_qset + pi->nqsets; i++) | 1844 | for (i = pi->first_qset; i < pi->first_qset + pi->nqsets; i++) |
| 1841 | set_qset_lro(dev, i, 0); | 1845 | set_qset_lro(dev, i, 0); |
| 1846 | } | ||
| 1842 | 1847 | ||
| 1843 | return 0; | 1848 | return 0; |
| 1844 | } | 1849 | } |
| @@ -1926,7 +1931,7 @@ static int cxgb_extension_ioctl(struct net_device *dev, void __user *useraddr) | |||
| 1926 | pi = adap2pinfo(adapter, i); | 1931 | pi = adap2pinfo(adapter, i); |
| 1927 | if (t.qset_idx >= pi->first_qset && | 1932 | if (t.qset_idx >= pi->first_qset && |
| 1928 | t.qset_idx < pi->first_qset + pi->nqsets && | 1933 | t.qset_idx < pi->first_qset + pi->nqsets && |
| 1929 | !pi->rx_csum_offload) | 1934 | !(pi->rx_offload & T3_RX_CSUM)) |
| 1930 | return -EINVAL; | 1935 | return -EINVAL; |
| 1931 | } | 1936 | } |
| 1932 | 1937 | ||
| @@ -2946,7 +2951,7 @@ static int __devinit init_one(struct pci_dev *pdev, | |||
| 2946 | adapter->port[i] = netdev; | 2951 | adapter->port[i] = netdev; |
| 2947 | pi = netdev_priv(netdev); | 2952 | pi = netdev_priv(netdev); |
| 2948 | pi->adapter = adapter; | 2953 | pi->adapter = adapter; |
| 2949 | pi->rx_csum_offload = 1; | 2954 | pi->rx_offload = T3_RX_CSUM | T3_LRO; |
| 2950 | pi->port_id = i; | 2955 | pi->port_id = i; |
| 2951 | netif_carrier_off(netdev); | 2956 | netif_carrier_off(netdev); |
| 2952 | netif_tx_stop_all_queues(netdev); | 2957 | netif_tx_stop_all_queues(netdev); |
| @@ -2955,6 +2960,7 @@ static int __devinit init_one(struct pci_dev *pdev, | |||
| 2955 | netdev->mem_end = mmio_start + mmio_len - 1; | 2960 | netdev->mem_end = mmio_start + mmio_len - 1; |
| 2956 | netdev->features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; | 2961 | netdev->features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; |
| 2957 | netdev->features |= NETIF_F_LLTX; | 2962 | netdev->features |= NETIF_F_LLTX; |
| 2963 | netdev->features |= NETIF_F_LRO; | ||
| 2958 | if (pci_using_dac) | 2964 | if (pci_using_dac) |
| 2959 | netdev->features |= NETIF_F_HIGHDMA; | 2965 | netdev->features |= NETIF_F_HIGHDMA; |
| 2960 | 2966 | ||
diff --git a/drivers/net/cxgb3/sge.c b/drivers/net/cxgb3/sge.c index 6c641a889471..14f9fb3e8795 100644 --- a/drivers/net/cxgb3/sge.c +++ b/drivers/net/cxgb3/sge.c | |||
| @@ -1932,7 +1932,7 @@ static void rx_eth(struct adapter *adap, struct sge_rspq *rq, | |||
| 1932 | skb_pull(skb, sizeof(*p) + pad); | 1932 | skb_pull(skb, sizeof(*p) + pad); |
| 1933 | skb->protocol = eth_type_trans(skb, adap->port[p->iff]); | 1933 | skb->protocol = eth_type_trans(skb, adap->port[p->iff]); |
| 1934 | pi = netdev_priv(skb->dev); | 1934 | pi = netdev_priv(skb->dev); |
| 1935 | if (pi->rx_csum_offload && p->csum_valid && p->csum == htons(0xffff) && | 1935 | if ((pi->rx_offload & T3_RX_CSUM) && p->csum_valid && p->csum == htons(0xffff) && |
| 1936 | !p->fragment) { | 1936 | !p->fragment) { |
| 1937 | qs->port_stats[SGE_PSTAT_RX_CSUM_GOOD]++; | 1937 | qs->port_stats[SGE_PSTAT_RX_CSUM_GOOD]++; |
| 1938 | skb->ip_summed = CHECKSUM_UNNECESSARY; | 1938 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
diff --git a/drivers/net/e1000e/ich8lan.c b/drivers/net/e1000e/ich8lan.c index f2a5963b5a95..e415e81ecd3e 100644 --- a/drivers/net/e1000e/ich8lan.c +++ b/drivers/net/e1000e/ich8lan.c | |||
| @@ -390,7 +390,8 @@ static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter) | |||
| 390 | } | 390 | } |
| 391 | 391 | ||
| 392 | static DEFINE_MUTEX(nvm_mutex); | 392 | static DEFINE_MUTEX(nvm_mutex); |
| 393 | static pid_t nvm_owner = -1; | 393 | static pid_t nvm_owner_pid = -1; |
| 394 | static char nvm_owner_name[TASK_COMM_LEN] = ""; | ||
| 394 | 395 | ||
| 395 | /** | 396 | /** |
| 396 | * e1000_acquire_swflag_ich8lan - Acquire software control flag | 397 | * e1000_acquire_swflag_ich8lan - Acquire software control flag |
| @@ -408,11 +409,15 @@ static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) | |||
| 408 | might_sleep(); | 409 | might_sleep(); |
| 409 | 410 | ||
| 410 | if (!mutex_trylock(&nvm_mutex)) { | 411 | if (!mutex_trylock(&nvm_mutex)) { |
| 411 | WARN(1, KERN_ERR "e1000e mutex contention. Owned by pid %d\n", | 412 | WARN(1, KERN_ERR "e1000e mutex contention. Owned by process " |
| 412 | nvm_owner); | 413 | "%s (pid %d), required by process %s (pid %d)\n", |
| 414 | nvm_owner_name, nvm_owner_pid, | ||
| 415 | current->comm, current->pid); | ||
| 416 | |||
| 413 | mutex_lock(&nvm_mutex); | 417 | mutex_lock(&nvm_mutex); |
| 414 | } | 418 | } |
| 415 | nvm_owner = current->pid; | 419 | nvm_owner_pid = current->pid; |
| 420 | strncpy(nvm_owner_name, current->comm, TASK_COMM_LEN); | ||
| 416 | 421 | ||
| 417 | while (timeout) { | 422 | while (timeout) { |
| 418 | extcnf_ctrl = er32(EXTCNF_CTRL); | 423 | extcnf_ctrl = er32(EXTCNF_CTRL); |
| @@ -430,7 +435,8 @@ static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) | |||
| 430 | hw_dbg(hw, "FW or HW has locked the resource for too long.\n"); | 435 | hw_dbg(hw, "FW or HW has locked the resource for too long.\n"); |
| 431 | extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; | 436 | extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; |
| 432 | ew32(EXTCNF_CTRL, extcnf_ctrl); | 437 | ew32(EXTCNF_CTRL, extcnf_ctrl); |
| 433 | nvm_owner = -1; | 438 | nvm_owner_pid = -1; |
| 439 | strcpy(nvm_owner_name, ""); | ||
| 434 | mutex_unlock(&nvm_mutex); | 440 | mutex_unlock(&nvm_mutex); |
| 435 | return -E1000_ERR_CONFIG; | 441 | return -E1000_ERR_CONFIG; |
| 436 | } | 442 | } |
| @@ -454,7 +460,8 @@ static void e1000_release_swflag_ich8lan(struct e1000_hw *hw) | |||
| 454 | extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; | 460 | extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; |
| 455 | ew32(EXTCNF_CTRL, extcnf_ctrl); | 461 | ew32(EXTCNF_CTRL, extcnf_ctrl); |
| 456 | 462 | ||
| 457 | nvm_owner = -1; | 463 | nvm_owner_pid = -1; |
| 464 | strcpy(nvm_owner_name, ""); | ||
| 458 | mutex_unlock(&nvm_mutex); | 465 | mutex_unlock(&nvm_mutex); |
| 459 | } | 466 | } |
| 460 | 467 | ||
diff --git a/drivers/net/e2100.c b/drivers/net/e2100.c index 20eb05cddb83..b07ba1924de0 100644 --- a/drivers/net/e2100.c +++ b/drivers/net/e2100.c | |||
| @@ -169,6 +169,7 @@ static const struct net_device_ops e21_netdev_ops = { | |||
| 169 | .ndo_get_stats = ei_get_stats, | 169 | .ndo_get_stats = ei_get_stats, |
| 170 | .ndo_set_multicast_list = ei_set_multicast_list, | 170 | .ndo_set_multicast_list = ei_set_multicast_list, |
| 171 | .ndo_validate_addr = eth_validate_addr, | 171 | .ndo_validate_addr = eth_validate_addr, |
| 172 | .ndo_set_mac_address = eth_mac_addr, | ||
| 172 | .ndo_change_mtu = eth_change_mtu, | 173 | .ndo_change_mtu = eth_change_mtu, |
| 173 | #ifdef CONFIG_NET_POLL_CONTROLLER | 174 | #ifdef CONFIG_NET_POLL_CONTROLLER |
| 174 | .ndo_poll_controller = ei_poll, | 175 | .ndo_poll_controller = ei_poll, |
diff --git a/drivers/net/enic/enic_main.c b/drivers/net/enic/enic_main.c index d039e16f2763..7d60551d538f 100644 --- a/drivers/net/enic/enic_main.c +++ b/drivers/net/enic/enic_main.c | |||
| @@ -1599,6 +1599,7 @@ static const struct net_device_ops enic_netdev_ops = { | |||
| 1599 | .ndo_start_xmit = enic_hard_start_xmit, | 1599 | .ndo_start_xmit = enic_hard_start_xmit, |
| 1600 | .ndo_get_stats = enic_get_stats, | 1600 | .ndo_get_stats = enic_get_stats, |
| 1601 | .ndo_validate_addr = eth_validate_addr, | 1601 | .ndo_validate_addr = eth_validate_addr, |
| 1602 | .ndo_set_mac_address = eth_mac_addr, | ||
| 1602 | .ndo_set_multicast_list = enic_set_multicast_list, | 1603 | .ndo_set_multicast_list = enic_set_multicast_list, |
| 1603 | .ndo_change_mtu = enic_change_mtu, | 1604 | .ndo_change_mtu = enic_change_mtu, |
| 1604 | .ndo_vlan_rx_register = enic_vlan_rx_register, | 1605 | .ndo_vlan_rx_register = enic_vlan_rx_register, |
diff --git a/drivers/net/forcedeth.c b/drivers/net/forcedeth.c index 5b68dc20168d..5b910cf63740 100644 --- a/drivers/net/forcedeth.c +++ b/drivers/net/forcedeth.c | |||
| @@ -13,7 +13,7 @@ | |||
| 13 | * Copyright (C) 2004 Andrew de Quincey (wol support) | 13 | * Copyright (C) 2004 Andrew de Quincey (wol support) |
| 14 | * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane | 14 | * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane |
| 15 | * IRQ rate fixes, bigendian fixes, cleanups, verification) | 15 | * IRQ rate fixes, bigendian fixes, cleanups, verification) |
| 16 | * Copyright (c) 2004,2005,2006,2007,2008 NVIDIA Corporation | 16 | * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation |
| 17 | * | 17 | * |
| 18 | * This program is free software; you can redistribute it and/or modify | 18 | * This program is free software; you can redistribute it and/or modify |
| 19 | * it under the terms of the GNU General Public License as published by | 19 | * it under the terms of the GNU General Public License as published by |
| @@ -39,7 +39,7 @@ | |||
| 39 | * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few | 39 | * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few |
| 40 | * superfluous timer interrupts from the nic. | 40 | * superfluous timer interrupts from the nic. |
| 41 | */ | 41 | */ |
| 42 | #define FORCEDETH_VERSION "0.61" | 42 | #define FORCEDETH_VERSION "0.62" |
| 43 | #define DRV_NAME "forcedeth" | 43 | #define DRV_NAME "forcedeth" |
| 44 | 44 | ||
| 45 | #include <linux/module.h> | 45 | #include <linux/module.h> |
| @@ -2096,14 +2096,15 @@ static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev) | |||
| 2096 | ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); | 2096 | ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); |
| 2097 | } | 2097 | } |
| 2098 | 2098 | ||
| 2099 | spin_lock_irqsave(&np->lock, flags); | ||
| 2099 | empty_slots = nv_get_empty_tx_slots(np); | 2100 | empty_slots = nv_get_empty_tx_slots(np); |
| 2100 | if (unlikely(empty_slots <= entries)) { | 2101 | if (unlikely(empty_slots <= entries)) { |
| 2101 | spin_lock_irqsave(&np->lock, flags); | ||
| 2102 | netif_stop_queue(dev); | 2102 | netif_stop_queue(dev); |
| 2103 | np->tx_stop = 1; | 2103 | np->tx_stop = 1; |
| 2104 | spin_unlock_irqrestore(&np->lock, flags); | 2104 | spin_unlock_irqrestore(&np->lock, flags); |
| 2105 | return NETDEV_TX_BUSY; | 2105 | return NETDEV_TX_BUSY; |
| 2106 | } | 2106 | } |
| 2107 | spin_unlock_irqrestore(&np->lock, flags); | ||
| 2107 | 2108 | ||
| 2108 | start_tx = put_tx = np->put_tx.orig; | 2109 | start_tx = put_tx = np->put_tx.orig; |
| 2109 | 2110 | ||
| @@ -2214,14 +2215,15 @@ static int nv_start_xmit_optimized(struct sk_buff *skb, struct net_device *dev) | |||
| 2214 | ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); | 2215 | ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); |
| 2215 | } | 2216 | } |
| 2216 | 2217 | ||
| 2218 | spin_lock_irqsave(&np->lock, flags); | ||
| 2217 | empty_slots = nv_get_empty_tx_slots(np); | 2219 | empty_slots = nv_get_empty_tx_slots(np); |
| 2218 | if (unlikely(empty_slots <= entries)) { | 2220 | if (unlikely(empty_slots <= entries)) { |
| 2219 | spin_lock_irqsave(&np->lock, flags); | ||
| 2220 | netif_stop_queue(dev); | 2221 | netif_stop_queue(dev); |
| 2221 | np->tx_stop = 1; | 2222 | np->tx_stop = 1; |
| 2222 | spin_unlock_irqrestore(&np->lock, flags); | 2223 | spin_unlock_irqrestore(&np->lock, flags); |
| 2223 | return NETDEV_TX_BUSY; | 2224 | return NETDEV_TX_BUSY; |
| 2224 | } | 2225 | } |
| 2226 | spin_unlock_irqrestore(&np->lock, flags); | ||
| 2225 | 2227 | ||
| 2226 | start_tx = put_tx = np->put_tx.ex; | 2228 | start_tx = put_tx = np->put_tx.ex; |
| 2227 | start_tx_ctx = np->put_tx_ctx; | 2229 | start_tx_ctx = np->put_tx_ctx; |
| @@ -3403,10 +3405,10 @@ static irqreturn_t nv_nic_irq(int foo, void *data) | |||
| 3403 | 3405 | ||
| 3404 | #ifdef CONFIG_FORCEDETH_NAPI | 3406 | #ifdef CONFIG_FORCEDETH_NAPI |
| 3405 | if (events & NVREG_IRQ_RX_ALL) { | 3407 | if (events & NVREG_IRQ_RX_ALL) { |
| 3408 | spin_lock(&np->lock); | ||
| 3406 | netif_rx_schedule(&np->napi); | 3409 | netif_rx_schedule(&np->napi); |
| 3407 | 3410 | ||
| 3408 | /* Disable furthur receive irq's */ | 3411 | /* Disable furthur receive irq's */ |
| 3409 | spin_lock(&np->lock); | ||
| 3410 | np->irqmask &= ~NVREG_IRQ_RX_ALL; | 3412 | np->irqmask &= ~NVREG_IRQ_RX_ALL; |
| 3411 | 3413 | ||
| 3412 | if (np->msi_flags & NV_MSI_X_ENABLED) | 3414 | if (np->msi_flags & NV_MSI_X_ENABLED) |
| @@ -3520,10 +3522,10 @@ static irqreturn_t nv_nic_irq_optimized(int foo, void *data) | |||
| 3520 | 3522 | ||
| 3521 | #ifdef CONFIG_FORCEDETH_NAPI | 3523 | #ifdef CONFIG_FORCEDETH_NAPI |
| 3522 | if (events & NVREG_IRQ_RX_ALL) { | 3524 | if (events & NVREG_IRQ_RX_ALL) { |
| 3525 | spin_lock(&np->lock); | ||
| 3523 | netif_rx_schedule(&np->napi); | 3526 | netif_rx_schedule(&np->napi); |
| 3524 | 3527 | ||
| 3525 | /* Disable furthur receive irq's */ | 3528 | /* Disable furthur receive irq's */ |
| 3526 | spin_lock(&np->lock); | ||
| 3527 | np->irqmask &= ~NVREG_IRQ_RX_ALL; | 3529 | np->irqmask &= ~NVREG_IRQ_RX_ALL; |
| 3528 | 3530 | ||
| 3529 | if (np->msi_flags & NV_MSI_X_ENABLED) | 3531 | if (np->msi_flags & NV_MSI_X_ENABLED) |
| @@ -6167,19 +6169,19 @@ static struct pci_device_id pci_tbl[] = { | |||
| 6167 | }, | 6169 | }, |
| 6168 | { /* MCP79 Ethernet Controller */ | 6170 | { /* MCP79 Ethernet Controller */ |
| 6169 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_36), | 6171 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_36), |
| 6170 | .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, | 6172 | .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, |
| 6171 | }, | 6173 | }, |
| 6172 | { /* MCP79 Ethernet Controller */ | 6174 | { /* MCP79 Ethernet Controller */ |
| 6173 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_37), | 6175 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_37), |
| 6174 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, | 6176 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, |
| 6175 | }, | 6177 | }, |
| 6176 | { /* MCP79 Ethernet Controller */ | 6178 | { /* MCP79 Ethernet Controller */ |
| 6177 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_38), | 6179 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_38), |
| 6178 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, | 6180 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, |
| 6179 | }, | 6181 | }, |
| 6180 | { /* MCP79 Ethernet Controller */ | 6182 | { /* MCP79 Ethernet Controller */ |
| 6181 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_39), | 6183 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_39), |
| 6182 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, | 6184 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, |
| 6183 | }, | 6185 | }, |
| 6184 | {0,}, | 6186 | {0,}, |
| 6185 | }; | 6187 | }; |
diff --git a/drivers/net/gianfar.c b/drivers/net/gianfar.c index 1b8deca8b9f8..efcbeb6c8673 100644 --- a/drivers/net/gianfar.c +++ b/drivers/net/gianfar.c | |||
| @@ -296,6 +296,20 @@ err_out: | |||
| 296 | return err; | 296 | return err; |
| 297 | } | 297 | } |
| 298 | 298 | ||
| 299 | /* Ioctl MII Interface */ | ||
| 300 | static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | ||
| 301 | { | ||
| 302 | struct gfar_private *priv = netdev_priv(dev); | ||
| 303 | |||
| 304 | if (!netif_running(dev)) | ||
| 305 | return -EINVAL; | ||
| 306 | |||
| 307 | if (!priv->phydev) | ||
| 308 | return -ENODEV; | ||
| 309 | |||
| 310 | return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd); | ||
| 311 | } | ||
| 312 | |||
| 299 | /* Set up the ethernet device structure, private data, | 313 | /* Set up the ethernet device structure, private data, |
| 300 | * and anything else we need before we start */ | 314 | * and anything else we need before we start */ |
| 301 | static int gfar_probe(struct of_device *ofdev, | 315 | static int gfar_probe(struct of_device *ofdev, |
| @@ -366,6 +380,7 @@ static int gfar_probe(struct of_device *ofdev, | |||
| 366 | dev->set_multicast_list = gfar_set_multi; | 380 | dev->set_multicast_list = gfar_set_multi; |
| 367 | 381 | ||
| 368 | dev->ethtool_ops = &gfar_ethtool_ops; | 382 | dev->ethtool_ops = &gfar_ethtool_ops; |
| 383 | dev->do_ioctl = gfar_ioctl; | ||
| 369 | 384 | ||
| 370 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) { | 385 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) { |
| 371 | priv->rx_csum_enable = 1; | 386 | priv->rx_csum_enable = 1; |
diff --git a/drivers/net/hamachi.c b/drivers/net/hamachi.c index 32200227c923..7e8b3c59a7d6 100644 --- a/drivers/net/hamachi.c +++ b/drivers/net/hamachi.c | |||
| @@ -576,6 +576,7 @@ static const struct net_device_ops hamachi_netdev_ops = { | |||
| 576 | .ndo_set_multicast_list = set_rx_mode, | 576 | .ndo_set_multicast_list = set_rx_mode, |
| 577 | .ndo_change_mtu = eth_change_mtu, | 577 | .ndo_change_mtu = eth_change_mtu, |
| 578 | .ndo_validate_addr = eth_validate_addr, | 578 | .ndo_validate_addr = eth_validate_addr, |
| 579 | .ndo_set_mac_address = eth_mac_addr, | ||
| 579 | .ndo_tx_timeout = hamachi_tx_timeout, | 580 | .ndo_tx_timeout = hamachi_tx_timeout, |
| 580 | .ndo_do_ioctl = netdev_ioctl, | 581 | .ndo_do_ioctl = netdev_ioctl, |
| 581 | }; | 582 | }; |
diff --git a/drivers/net/hamradio/6pack.c b/drivers/net/hamradio/6pack.c index 50f1e172ee8f..2d4089894ec7 100644 --- a/drivers/net/hamradio/6pack.c +++ b/drivers/net/hamradio/6pack.c | |||
| @@ -717,11 +717,12 @@ static int sixpack_ioctl(struct tty_struct *tty, struct file *file, | |||
| 717 | unsigned int cmd, unsigned long arg) | 717 | unsigned int cmd, unsigned long arg) |
| 718 | { | 718 | { |
| 719 | struct sixpack *sp = sp_get(tty); | 719 | struct sixpack *sp = sp_get(tty); |
| 720 | struct net_device *dev = sp->dev; | 720 | struct net_device *dev; |
| 721 | unsigned int tmp, err; | 721 | unsigned int tmp, err; |
| 722 | 722 | ||
| 723 | if (!sp) | 723 | if (!sp) |
| 724 | return -ENXIO; | 724 | return -ENXIO; |
| 725 | dev = sp->dev; | ||
| 725 | 726 | ||
| 726 | switch(cmd) { | 727 | switch(cmd) { |
| 727 | case SIOCGIFNAME: | 728 | case SIOCGIFNAME: |
diff --git a/drivers/net/hp-plus.c b/drivers/net/hp-plus.c index b507dbc16e62..5e070f446635 100644 --- a/drivers/net/hp-plus.c +++ b/drivers/net/hp-plus.c | |||
| @@ -166,6 +166,7 @@ static const struct net_device_ops hpp_netdev_ops = { | |||
| 166 | .ndo_get_stats = eip_get_stats, | 166 | .ndo_get_stats = eip_get_stats, |
| 167 | .ndo_set_multicast_list = eip_set_multicast_list, | 167 | .ndo_set_multicast_list = eip_set_multicast_list, |
| 168 | .ndo_validate_addr = eth_validate_addr, | 168 | .ndo_validate_addr = eth_validate_addr, |
| 169 | .ndo_set_mac_address = eth_mac_addr, | ||
| 169 | .ndo_change_mtu = eth_change_mtu, | 170 | .ndo_change_mtu = eth_change_mtu, |
| 170 | #ifdef CONFIG_NET_POLL_CONTROLLER | 171 | #ifdef CONFIG_NET_POLL_CONTROLLER |
| 171 | .ndo_poll_controller = eip_poll, | 172 | .ndo_poll_controller = eip_poll, |
diff --git a/drivers/net/hydra.c b/drivers/net/hydra.c index 9cb38a8d4387..8ac0930c183c 100644 --- a/drivers/net/hydra.c +++ b/drivers/net/hydra.c | |||
| @@ -103,6 +103,7 @@ static const struct net_device_ops hydra_netdev_ops = { | |||
| 103 | .ndo_get_stats = ei_get_stats, | 103 | .ndo_get_stats = ei_get_stats, |
| 104 | .ndo_set_multicast_list = ei_set_multicast_list, | 104 | .ndo_set_multicast_list = ei_set_multicast_list, |
| 105 | .ndo_validate_addr = eth_validate_addr, | 105 | .ndo_validate_addr = eth_validate_addr, |
| 106 | .ndo_set_mac_address = eth_mac_addr, | ||
| 106 | .ndo_change_mtu = eth_change_mtu, | 107 | .ndo_change_mtu = eth_change_mtu, |
| 107 | #ifdef CONFIG_NET_POLL_CONTROLLER | 108 | #ifdef CONFIG_NET_POLL_CONTROLLER |
| 108 | .ndo_poll_controller = ei_poll, | 109 | .ndo_poll_controller = ei_poll, |
diff --git a/drivers/net/irda/au1k_ir.c b/drivers/net/irda/au1k_ir.c index 75a1d0a86dee..941164076a2b 100644 --- a/drivers/net/irda/au1k_ir.c +++ b/drivers/net/irda/au1k_ir.c | |||
| @@ -594,7 +594,7 @@ static int au1k_irda_rx(struct net_device *dev) | |||
| 594 | update_rx_stats(dev, flags, count); | 594 | update_rx_stats(dev, flags, count); |
| 595 | skb=alloc_skb(count+1,GFP_ATOMIC); | 595 | skb=alloc_skb(count+1,GFP_ATOMIC); |
| 596 | if (skb == NULL) { | 596 | if (skb == NULL) { |
| 597 | aup->stats.rx_dropped++; | 597 | aup->netdev->stats.rx_dropped++; |
| 598 | continue; | 598 | continue; |
| 599 | } | 599 | } |
| 600 | skb_reserve(skb, 1); | 600 | skb_reserve(skb, 1); |
diff --git a/drivers/net/irda/donauboe.c b/drivers/net/irda/donauboe.c index 687c2d53d4d2..6f3e7f71658d 100644 --- a/drivers/net/irda/donauboe.c +++ b/drivers/net/irda/donauboe.c | |||
| @@ -1194,13 +1194,13 @@ toshoboe_interrupt (int irq, void *dev_id) | |||
| 1194 | txp = txpc; | 1194 | txp = txpc; |
| 1195 | txpc++; | 1195 | txpc++; |
| 1196 | txpc %= TX_SLOTS; | 1196 | txpc %= TX_SLOTS; |
| 1197 | self->stats.tx_packets++; | 1197 | self->netdev->stats.tx_packets++; |
| 1198 | if (self->ring->tx[txpc].control & OBOE_CTL_TX_HW_OWNS) | 1198 | if (self->ring->tx[txpc].control & OBOE_CTL_TX_HW_OWNS) |
| 1199 | self->ring->tx[txp].control &= ~OBOE_CTL_TX_RTCENTX; | 1199 | self->ring->tx[txp].control &= ~OBOE_CTL_TX_RTCENTX; |
| 1200 | } | 1200 | } |
| 1201 | self->stats.tx_packets--; | 1201 | self->netdev->stats.tx_packets--; |
| 1202 | #else | 1202 | #else |
| 1203 | self->stats.tx_packets++; | 1203 | self->netdev->stats.tx_packets++; |
| 1204 | #endif | 1204 | #endif |
| 1205 | toshoboe_start_DMA(self, OBOE_CONFIG0H_ENTX); | 1205 | toshoboe_start_DMA(self, OBOE_CONFIG0H_ENTX); |
| 1206 | } | 1206 | } |
| @@ -1280,7 +1280,7 @@ dumpbufs(self->rx_bufs[self->rxs],len,'<'); | |||
| 1280 | skb_put (skb, len); | 1280 | skb_put (skb, len); |
| 1281 | skb_copy_to_linear_data(skb, self->rx_bufs[self->rxs], | 1281 | skb_copy_to_linear_data(skb, self->rx_bufs[self->rxs], |
| 1282 | len); | 1282 | len); |
| 1283 | self->stats.rx_packets++; | 1283 | self->netdev->stats.rx_packets++; |
| 1284 | skb->dev = self->netdev; | 1284 | skb->dev = self->netdev; |
| 1285 | skb_reset_mac_header(skb); | 1285 | skb_reset_mac_header(skb); |
| 1286 | skb->protocol = htons (ETH_P_IRDA); | 1286 | skb->protocol = htons (ETH_P_IRDA); |
diff --git a/drivers/net/mac8390.c b/drivers/net/mac8390.c index 57716e22660c..8e884869a05b 100644 --- a/drivers/net/mac8390.c +++ b/drivers/net/mac8390.c | |||
| @@ -486,6 +486,7 @@ static const struct net_device_ops mac8390_netdev_ops = { | |||
| 486 | .ndo_get_stats = ei_get_stats, | 486 | .ndo_get_stats = ei_get_stats, |
| 487 | .ndo_set_multicast_list = ei_set_multicast_list, | 487 | .ndo_set_multicast_list = ei_set_multicast_list, |
| 488 | .ndo_validate_addr = eth_validate_addr, | 488 | .ndo_validate_addr = eth_validate_addr, |
| 489 | .ndo_set_mac_address = eth_mac_addr, | ||
| 489 | .ndo_change_mtu = eth_change_mtu, | 490 | .ndo_change_mtu = eth_change_mtu, |
| 490 | #ifdef CONFIG_NET_POLL_CONTROLLER | 491 | #ifdef CONFIG_NET_POLL_CONTROLLER |
| 491 | .ndo_poll_controller = ei_poll, | 492 | .ndo_poll_controller = ei_poll, |
diff --git a/drivers/net/mlx4/en_netdev.c b/drivers/net/mlx4/en_netdev.c index 15bb38d99304..9f6644a44030 100644 --- a/drivers/net/mlx4/en_netdev.c +++ b/drivers/net/mlx4/en_netdev.c | |||
| @@ -952,6 +952,7 @@ static const struct net_device_ops mlx4_netdev_ops = { | |||
| 952 | .ndo_get_stats = mlx4_en_get_stats, | 952 | .ndo_get_stats = mlx4_en_get_stats, |
| 953 | .ndo_set_multicast_list = mlx4_en_set_multicast, | 953 | .ndo_set_multicast_list = mlx4_en_set_multicast, |
| 954 | .ndo_set_mac_address = mlx4_en_set_mac, | 954 | .ndo_set_mac_address = mlx4_en_set_mac, |
| 955 | .ndo_validate_addr = eth_validate_addr, | ||
| 955 | .ndo_change_mtu = mlx4_en_change_mtu, | 956 | .ndo_change_mtu = mlx4_en_change_mtu, |
| 956 | .ndo_tx_timeout = mlx4_en_tx_timeout, | 957 | .ndo_tx_timeout = mlx4_en_tx_timeout, |
| 957 | .ndo_vlan_rx_register = mlx4_en_vlan_rx_register, | 958 | .ndo_vlan_rx_register = mlx4_en_vlan_rx_register, |
diff --git a/drivers/net/mlx4/main.c b/drivers/net/mlx4/main.c index 710c79e7a2db..6ef2490d5c3e 100644 --- a/drivers/net/mlx4/main.c +++ b/drivers/net/mlx4/main.c | |||
| @@ -912,8 +912,8 @@ static void mlx4_enable_msi_x(struct mlx4_dev *dev) | |||
| 912 | int i; | 912 | int i; |
| 913 | 913 | ||
| 914 | if (msi_x) { | 914 | if (msi_x) { |
| 915 | nreq = min(dev->caps.num_eqs - dev->caps.reserved_eqs, | 915 | nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs, |
| 916 | num_possible_cpus() + 1); | 916 | num_possible_cpus() + 1); |
| 917 | entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL); | 917 | entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL); |
| 918 | if (!entries) | 918 | if (!entries) |
| 919 | goto no_msi; | 919 | goto no_msi; |
diff --git a/drivers/net/ne-h8300.c b/drivers/net/ne-h8300.c index b57239171046..7bd6662d5b04 100644 --- a/drivers/net/ne-h8300.c +++ b/drivers/net/ne-h8300.c | |||
| @@ -202,6 +202,7 @@ static const struct net_device_ops ne_netdev_ops = { | |||
| 202 | .ndo_get_stats = ei_get_stats, | 202 | .ndo_get_stats = ei_get_stats, |
| 203 | .ndo_set_multicast_list = ei_set_multicast_list, | 203 | .ndo_set_multicast_list = ei_set_multicast_list, |
| 204 | .ndo_validate_addr = eth_validate_addr, | 204 | .ndo_validate_addr = eth_validate_addr, |
| 205 | .ndo_set_mac_address = eth_mac_addr, | ||
| 205 | .ndo_change_mtu = eth_change_mtu, | 206 | .ndo_change_mtu = eth_change_mtu, |
| 206 | #ifdef CONFIG_NET_POLL_CONTROLLER | 207 | #ifdef CONFIG_NET_POLL_CONTROLLER |
| 207 | .ndo_poll_controller = ei_poll, | 208 | .ndo_poll_controller = ei_poll, |
diff --git a/drivers/net/ne2k-pci.c b/drivers/net/ne2k-pci.c index 62f20ba211cb..f090d3b9ec94 100644 --- a/drivers/net/ne2k-pci.c +++ b/drivers/net/ne2k-pci.c | |||
| @@ -208,6 +208,7 @@ static const struct net_device_ops ne2k_netdev_ops = { | |||
| 208 | .ndo_get_stats = ei_get_stats, | 208 | .ndo_get_stats = ei_get_stats, |
| 209 | .ndo_set_multicast_list = ei_set_multicast_list, | 209 | .ndo_set_multicast_list = ei_set_multicast_list, |
| 210 | .ndo_validate_addr = eth_validate_addr, | 210 | .ndo_validate_addr = eth_validate_addr, |
| 211 | .ndo_set_mac_address = eth_mac_addr, | ||
| 211 | .ndo_change_mtu = eth_change_mtu, | 212 | .ndo_change_mtu = eth_change_mtu, |
| 212 | #ifdef CONFIG_NET_POLL_CONTROLLER | 213 | #ifdef CONFIG_NET_POLL_CONTROLLER |
| 213 | .ndo_poll_controller = ei_poll, | 214 | .ndo_poll_controller = ei_poll, |
diff --git a/drivers/net/ns83820.c b/drivers/net/ns83820.c index 42021aca1ddd..e80294d8cc19 100644 --- a/drivers/net/ns83820.c +++ b/drivers/net/ns83820.c | |||
| @@ -1956,6 +1956,7 @@ static const struct net_device_ops netdev_ops = { | |||
| 1956 | .ndo_change_mtu = ns83820_change_mtu, | 1956 | .ndo_change_mtu = ns83820_change_mtu, |
| 1957 | .ndo_set_multicast_list = ns83820_set_multicast, | 1957 | .ndo_set_multicast_list = ns83820_set_multicast, |
| 1958 | .ndo_validate_addr = eth_validate_addr, | 1958 | .ndo_validate_addr = eth_validate_addr, |
| 1959 | .ndo_set_mac_address = eth_mac_addr, | ||
| 1959 | .ndo_tx_timeout = ns83820_tx_timeout, | 1960 | .ndo_tx_timeout = ns83820_tx_timeout, |
| 1960 | #ifdef NS83820_VLAN_ACCEL_SUPPORT | 1961 | #ifdef NS83820_VLAN_ACCEL_SUPPORT |
| 1961 | .ndo_vlan_rx_register = ns83820_vlan_rx_register, | 1962 | .ndo_vlan_rx_register = ns83820_vlan_rx_register, |
diff --git a/drivers/net/qlge/qlge.h b/drivers/net/qlge/qlge.h index 459663a4023d..c1dadadfab18 100644 --- a/drivers/net/qlge/qlge.h +++ b/drivers/net/qlge/qlge.h | |||
| @@ -28,11 +28,11 @@ | |||
| 28 | } while (0) | 28 | } while (0) |
| 29 | 29 | ||
| 30 | #define QLGE_VENDOR_ID 0x1077 | 30 | #define QLGE_VENDOR_ID 0x1077 |
| 31 | #define QLGE_DEVICE_ID1 0x8012 | 31 | #define QLGE_DEVICE_ID 0x8012 |
| 32 | #define QLGE_DEVICE_ID 0x8000 | ||
| 33 | 32 | ||
| 34 | #define MAX_RX_RINGS 128 | 33 | #define MAX_CPUS 8 |
| 35 | #define MAX_TX_RINGS 128 | 34 | #define MAX_TX_RINGS MAX_CPUS |
| 35 | #define MAX_RX_RINGS ((MAX_CPUS * 2) + 1) | ||
| 36 | 36 | ||
| 37 | #define NUM_TX_RING_ENTRIES 256 | 37 | #define NUM_TX_RING_ENTRIES 256 |
| 38 | #define NUM_RX_RING_ENTRIES 256 | 38 | #define NUM_RX_RING_ENTRIES 256 |
| @@ -45,6 +45,7 @@ | |||
| 45 | #define MAX_SPLIT_SIZE 1023 | 45 | #define MAX_SPLIT_SIZE 1023 |
| 46 | #define QLGE_SB_PAD 32 | 46 | #define QLGE_SB_PAD 32 |
| 47 | 47 | ||
| 48 | #define MAX_CQ 128 | ||
| 48 | #define DFLT_COALESCE_WAIT 100 /* 100 usec wait for coalescing */ | 49 | #define DFLT_COALESCE_WAIT 100 /* 100 usec wait for coalescing */ |
| 49 | #define MAX_INTER_FRAME_WAIT 10 /* 10 usec max interframe-wait for coalescing */ | 50 | #define MAX_INTER_FRAME_WAIT 10 /* 10 usec max interframe-wait for coalescing */ |
| 50 | #define DFLT_INTER_FRAME_WAIT (MAX_INTER_FRAME_WAIT/2) | 51 | #define DFLT_INTER_FRAME_WAIT (MAX_INTER_FRAME_WAIT/2) |
| @@ -961,8 +962,7 @@ struct ib_mac_iocb_rsp { | |||
| 961 | #define IB_MAC_IOCB_RSP_DS 0x40 /* data is in small buffer */ | 962 | #define IB_MAC_IOCB_RSP_DS 0x40 /* data is in small buffer */ |
| 962 | #define IB_MAC_IOCB_RSP_DL 0x80 /* data is in large buffer */ | 963 | #define IB_MAC_IOCB_RSP_DL 0x80 /* data is in large buffer */ |
| 963 | __le32 data_len; /* */ | 964 | __le32 data_len; /* */ |
| 964 | __le32 data_addr_lo; /* */ | 965 | __le64 data_addr; /* */ |
| 965 | __le32 data_addr_hi; /* */ | ||
| 966 | __le32 rss; /* */ | 966 | __le32 rss; /* */ |
| 967 | __le16 vlan_id; /* 12 bits */ | 967 | __le16 vlan_id; /* 12 bits */ |
| 968 | #define IB_MAC_IOCB_RSP_C 0x1000 /* VLAN CFI bit */ | 968 | #define IB_MAC_IOCB_RSP_C 0x1000 /* VLAN CFI bit */ |
| @@ -976,8 +976,7 @@ struct ib_mac_iocb_rsp { | |||
| 976 | #define IB_MAC_IOCB_RSP_HS 0x40 | 976 | #define IB_MAC_IOCB_RSP_HS 0x40 |
| 977 | #define IB_MAC_IOCB_RSP_HL 0x80 | 977 | #define IB_MAC_IOCB_RSP_HL 0x80 |
| 978 | __le32 hdr_len; /* */ | 978 | __le32 hdr_len; /* */ |
| 979 | __le32 hdr_addr_lo; /* */ | 979 | __le64 hdr_addr; /* */ |
| 980 | __le32 hdr_addr_hi; /* */ | ||
| 981 | } __attribute((packed)); | 980 | } __attribute((packed)); |
| 982 | 981 | ||
| 983 | struct ib_ae_iocb_rsp { | 982 | struct ib_ae_iocb_rsp { |
| @@ -1042,10 +1041,8 @@ struct wqicb { | |||
| 1042 | __le16 cq_id_rss; | 1041 | __le16 cq_id_rss; |
| 1043 | #define Q_CQ_ID_RSS_RV 0x8000 | 1042 | #define Q_CQ_ID_RSS_RV 0x8000 |
| 1044 | __le16 rid; | 1043 | __le16 rid; |
| 1045 | __le32 addr_lo; | 1044 | __le64 addr; |
| 1046 | __le32 addr_hi; | 1045 | __le64 cnsmr_idx_addr; |
| 1047 | __le32 cnsmr_idx_addr_lo; | ||
| 1048 | __le32 cnsmr_idx_addr_hi; | ||
| 1049 | } __attribute((packed)); | 1046 | } __attribute((packed)); |
| 1050 | 1047 | ||
| 1051 | /* | 1048 | /* |
| @@ -1070,18 +1067,14 @@ struct cqicb { | |||
| 1070 | #define LEN_CPP_64 0x0002 | 1067 | #define LEN_CPP_64 0x0002 |
| 1071 | #define LEN_CPP_128 0x0003 | 1068 | #define LEN_CPP_128 0x0003 |
| 1072 | __le16 rid; | 1069 | __le16 rid; |
| 1073 | __le32 addr_lo; | 1070 | __le64 addr; |
| 1074 | __le32 addr_hi; | 1071 | __le64 prod_idx_addr; |
| 1075 | __le32 prod_idx_addr_lo; | ||
| 1076 | __le32 prod_idx_addr_hi; | ||
| 1077 | __le16 pkt_delay; | 1072 | __le16 pkt_delay; |
| 1078 | __le16 irq_delay; | 1073 | __le16 irq_delay; |
| 1079 | __le32 lbq_addr_lo; | 1074 | __le64 lbq_addr; |
| 1080 | __le32 lbq_addr_hi; | ||
| 1081 | __le16 lbq_buf_size; | 1075 | __le16 lbq_buf_size; |
| 1082 | __le16 lbq_len; /* entry count */ | 1076 | __le16 lbq_len; /* entry count */ |
| 1083 | __le32 sbq_addr_lo; | 1077 | __le64 sbq_addr; |
| 1084 | __le32 sbq_addr_hi; | ||
| 1085 | __le16 sbq_buf_size; | 1078 | __le16 sbq_buf_size; |
| 1086 | __le16 sbq_len; /* entry count */ | 1079 | __le16 sbq_len; /* entry count */ |
| 1087 | } __attribute((packed)); | 1080 | } __attribute((packed)); |
| @@ -1145,7 +1138,7 @@ struct tx_ring { | |||
| 1145 | struct wqicb wqicb; /* structure used to inform chip of new queue */ | 1138 | struct wqicb wqicb; /* structure used to inform chip of new queue */ |
| 1146 | void *wq_base; /* pci_alloc:virtual addr for tx */ | 1139 | void *wq_base; /* pci_alloc:virtual addr for tx */ |
| 1147 | dma_addr_t wq_base_dma; /* pci_alloc:dma addr for tx */ | 1140 | dma_addr_t wq_base_dma; /* pci_alloc:dma addr for tx */ |
| 1148 | u32 *cnsmr_idx_sh_reg; /* shadow copy of consumer idx */ | 1141 | __le32 *cnsmr_idx_sh_reg; /* shadow copy of consumer idx */ |
| 1149 | dma_addr_t cnsmr_idx_sh_reg_dma; /* dma-shadow copy of consumer */ | 1142 | dma_addr_t cnsmr_idx_sh_reg_dma; /* dma-shadow copy of consumer */ |
| 1150 | u32 wq_size; /* size in bytes of queue area */ | 1143 | u32 wq_size; /* size in bytes of queue area */ |
| 1151 | u32 wq_len; /* number of entries in queue */ | 1144 | u32 wq_len; /* number of entries in queue */ |
| @@ -1181,7 +1174,7 @@ struct rx_ring { | |||
| 1181 | u32 cq_size; | 1174 | u32 cq_size; |
| 1182 | u32 cq_len; | 1175 | u32 cq_len; |
| 1183 | u16 cq_id; | 1176 | u16 cq_id; |
| 1184 | volatile __le32 *prod_idx_sh_reg; /* Shadowed producer register. */ | 1177 | __le32 *prod_idx_sh_reg; /* Shadowed producer register. */ |
| 1185 | dma_addr_t prod_idx_sh_reg_dma; | 1178 | dma_addr_t prod_idx_sh_reg_dma; |
| 1186 | void __iomem *cnsmr_idx_db_reg; /* PCI doorbell mem area + 0 */ | 1179 | void __iomem *cnsmr_idx_db_reg; /* PCI doorbell mem area + 0 */ |
| 1187 | u32 cnsmr_idx; /* current sw idx */ | 1180 | u32 cnsmr_idx; /* current sw idx */ |
| @@ -1402,9 +1395,11 @@ struct ql_adapter { | |||
| 1402 | int rx_ring_count; | 1395 | int rx_ring_count; |
| 1403 | int ring_mem_size; | 1396 | int ring_mem_size; |
| 1404 | void *ring_mem; | 1397 | void *ring_mem; |
| 1405 | struct rx_ring *rx_ring; | 1398 | |
| 1399 | struct rx_ring rx_ring[MAX_RX_RINGS]; | ||
| 1400 | struct tx_ring tx_ring[MAX_TX_RINGS]; | ||
| 1401 | |||
| 1406 | int rx_csum; | 1402 | int rx_csum; |
| 1407 | struct tx_ring *tx_ring; | ||
| 1408 | u32 default_rx_queue; | 1403 | u32 default_rx_queue; |
| 1409 | 1404 | ||
| 1410 | u16 rx_coalesce_usecs; /* cqicb->int_delay */ | 1405 | u16 rx_coalesce_usecs; /* cqicb->int_delay */ |
| @@ -1459,6 +1454,24 @@ static inline void ql_write_db_reg(u32 val, void __iomem *addr) | |||
| 1459 | mmiowb(); | 1454 | mmiowb(); |
| 1460 | } | 1455 | } |
| 1461 | 1456 | ||
| 1457 | /* | ||
| 1458 | * Shadow Registers: | ||
| 1459 | * Outbound queues have a consumer index that is maintained by the chip. | ||
| 1460 | * Inbound queues have a producer index that is maintained by the chip. | ||
| 1461 | * For lower overhead, these registers are "shadowed" to host memory | ||
| 1462 | * which allows the device driver to track the queue progress without | ||
| 1463 | * PCI reads. When an entry is placed on an inbound queue, the chip will | ||
| 1464 | * update the relevant index register and then copy the value to the | ||
| 1465 | * shadow register in host memory. | ||
| 1466 | */ | ||
| 1467 | static inline u32 ql_read_sh_reg(__le32 *addr) | ||
| 1468 | { | ||
| 1469 | u32 reg; | ||
| 1470 | reg = le32_to_cpu(*addr); | ||
| 1471 | rmb(); | ||
| 1472 | return reg; | ||
| 1473 | } | ||
| 1474 | |||
| 1462 | extern char qlge_driver_name[]; | 1475 | extern char qlge_driver_name[]; |
| 1463 | extern const char qlge_driver_version[]; | 1476 | extern const char qlge_driver_version[]; |
| 1464 | extern const struct ethtool_ops qlge_ethtool_ops; | 1477 | extern const struct ethtool_ops qlge_ethtool_ops; |
diff --git a/drivers/net/qlge/qlge_dbg.c b/drivers/net/qlge/qlge_dbg.c index 3f5e02d2e4a9..379b895ed6e6 100644 --- a/drivers/net/qlge/qlge_dbg.c +++ b/drivers/net/qlge/qlge_dbg.c | |||
| @@ -435,14 +435,10 @@ void ql_dump_wqicb(struct wqicb *wqicb) | |||
| 435 | printk(KERN_ERR PFX "wqicb->cq_id_rss = %d.\n", | 435 | printk(KERN_ERR PFX "wqicb->cq_id_rss = %d.\n", |
| 436 | le16_to_cpu(wqicb->cq_id_rss)); | 436 | le16_to_cpu(wqicb->cq_id_rss)); |
| 437 | printk(KERN_ERR PFX "wqicb->rid = 0x%x.\n", le16_to_cpu(wqicb->rid)); | 437 | printk(KERN_ERR PFX "wqicb->rid = 0x%x.\n", le16_to_cpu(wqicb->rid)); |
| 438 | printk(KERN_ERR PFX "wqicb->wq_addr_lo = 0x%.08x.\n", | 438 | printk(KERN_ERR PFX "wqicb->wq_addr = 0x%llx.\n", |
| 439 | le32_to_cpu(wqicb->addr_lo)); | 439 | (unsigned long long) le64_to_cpu(wqicb->addr)); |
| 440 | printk(KERN_ERR PFX "wqicb->wq_addr_hi = 0x%.08x.\n", | 440 | printk(KERN_ERR PFX "wqicb->wq_cnsmr_idx_addr = 0x%llx.\n", |
| 441 | le32_to_cpu(wqicb->addr_hi)); | 441 | (unsigned long long) le64_to_cpu(wqicb->cnsmr_idx_addr)); |
| 442 | printk(KERN_ERR PFX "wqicb->wq_cnsmr_idx_addr_lo = 0x%.08x.\n", | ||
| 443 | le32_to_cpu(wqicb->cnsmr_idx_addr_lo)); | ||
| 444 | printk(KERN_ERR PFX "wqicb->wq_cnsmr_idx_addr_hi = 0x%.08x.\n", | ||
| 445 | le32_to_cpu(wqicb->cnsmr_idx_addr_hi)); | ||
| 446 | } | 442 | } |
| 447 | 443 | ||
| 448 | void ql_dump_tx_ring(struct tx_ring *tx_ring) | 444 | void ql_dump_tx_ring(struct tx_ring *tx_ring) |
| @@ -455,10 +451,11 @@ void ql_dump_tx_ring(struct tx_ring *tx_ring) | |||
| 455 | printk(KERN_ERR PFX "tx_ring->base = %p.\n", tx_ring->wq_base); | 451 | printk(KERN_ERR PFX "tx_ring->base = %p.\n", tx_ring->wq_base); |
| 456 | printk(KERN_ERR PFX "tx_ring->base_dma = 0x%llx.\n", | 452 | printk(KERN_ERR PFX "tx_ring->base_dma = 0x%llx.\n", |
| 457 | (unsigned long long) tx_ring->wq_base_dma); | 453 | (unsigned long long) tx_ring->wq_base_dma); |
| 458 | printk(KERN_ERR PFX "tx_ring->cnsmr_idx_sh_reg = %p.\n", | 454 | printk(KERN_ERR PFX |
| 459 | tx_ring->cnsmr_idx_sh_reg); | 455 | "tx_ring->cnsmr_idx_sh_reg, addr = 0x%p, value = %d.\n", |
| 460 | printk(KERN_ERR PFX "tx_ring->cnsmr_idx_sh_reg_dma = 0x%llx.\n", | 456 | tx_ring->cnsmr_idx_sh_reg, |
| 461 | (unsigned long long) tx_ring->cnsmr_idx_sh_reg_dma); | 457 | tx_ring->cnsmr_idx_sh_reg |
| 458 | ? ql_read_sh_reg(tx_ring->cnsmr_idx_sh_reg) : 0); | ||
| 462 | printk(KERN_ERR PFX "tx_ring->size = %d.\n", tx_ring->wq_size); | 459 | printk(KERN_ERR PFX "tx_ring->size = %d.\n", tx_ring->wq_size); |
| 463 | printk(KERN_ERR PFX "tx_ring->len = %d.\n", tx_ring->wq_len); | 460 | printk(KERN_ERR PFX "tx_ring->len = %d.\n", tx_ring->wq_len); |
| 464 | printk(KERN_ERR PFX "tx_ring->prod_idx_db_reg = %p.\n", | 461 | printk(KERN_ERR PFX "tx_ring->prod_idx_db_reg = %p.\n", |
| @@ -510,30 +507,22 @@ void ql_dump_cqicb(struct cqicb *cqicb) | |||
| 510 | printk(KERN_ERR PFX "cqicb->msix_vect = %d.\n", cqicb->msix_vect); | 507 | printk(KERN_ERR PFX "cqicb->msix_vect = %d.\n", cqicb->msix_vect); |
| 511 | printk(KERN_ERR PFX "cqicb->flags = %x.\n", cqicb->flags); | 508 | printk(KERN_ERR PFX "cqicb->flags = %x.\n", cqicb->flags); |
| 512 | printk(KERN_ERR PFX "cqicb->len = %d.\n", le16_to_cpu(cqicb->len)); | 509 | printk(KERN_ERR PFX "cqicb->len = %d.\n", le16_to_cpu(cqicb->len)); |
| 513 | printk(KERN_ERR PFX "cqicb->addr_lo = %x.\n", | 510 | printk(KERN_ERR PFX "cqicb->addr = 0x%llx.\n", |
| 514 | le32_to_cpu(cqicb->addr_lo)); | 511 | (unsigned long long) le64_to_cpu(cqicb->addr)); |
| 515 | printk(KERN_ERR PFX "cqicb->addr_hi = %x.\n", | 512 | printk(KERN_ERR PFX "cqicb->prod_idx_addr = 0x%llx.\n", |
| 516 | le32_to_cpu(cqicb->addr_hi)); | 513 | (unsigned long long) le64_to_cpu(cqicb->prod_idx_addr)); |
| 517 | printk(KERN_ERR PFX "cqicb->prod_idx_addr_lo = %x.\n", | ||
| 518 | le32_to_cpu(cqicb->prod_idx_addr_lo)); | ||
| 519 | printk(KERN_ERR PFX "cqicb->prod_idx_addr_hi = %x.\n", | ||
| 520 | le32_to_cpu(cqicb->prod_idx_addr_hi)); | ||
| 521 | printk(KERN_ERR PFX "cqicb->pkt_delay = 0x%.04x.\n", | 514 | printk(KERN_ERR PFX "cqicb->pkt_delay = 0x%.04x.\n", |
| 522 | le16_to_cpu(cqicb->pkt_delay)); | 515 | le16_to_cpu(cqicb->pkt_delay)); |
| 523 | printk(KERN_ERR PFX "cqicb->irq_delay = 0x%.04x.\n", | 516 | printk(KERN_ERR PFX "cqicb->irq_delay = 0x%.04x.\n", |
| 524 | le16_to_cpu(cqicb->irq_delay)); | 517 | le16_to_cpu(cqicb->irq_delay)); |
| 525 | printk(KERN_ERR PFX "cqicb->lbq_addr_lo = %x.\n", | 518 | printk(KERN_ERR PFX "cqicb->lbq_addr = 0x%llx.\n", |
| 526 | le32_to_cpu(cqicb->lbq_addr_lo)); | 519 | (unsigned long long) le64_to_cpu(cqicb->lbq_addr)); |
| 527 | printk(KERN_ERR PFX "cqicb->lbq_addr_hi = %x.\n", | ||
| 528 | le32_to_cpu(cqicb->lbq_addr_hi)); | ||
| 529 | printk(KERN_ERR PFX "cqicb->lbq_buf_size = 0x%.04x.\n", | 520 | printk(KERN_ERR PFX "cqicb->lbq_buf_size = 0x%.04x.\n", |
| 530 | le16_to_cpu(cqicb->lbq_buf_size)); | 521 | le16_to_cpu(cqicb->lbq_buf_size)); |
| 531 | printk(KERN_ERR PFX "cqicb->lbq_len = 0x%.04x.\n", | 522 | printk(KERN_ERR PFX "cqicb->lbq_len = 0x%.04x.\n", |
| 532 | le16_to_cpu(cqicb->lbq_len)); | 523 | le16_to_cpu(cqicb->lbq_len)); |
| 533 | printk(KERN_ERR PFX "cqicb->sbq_addr_lo = %x.\n", | 524 | printk(KERN_ERR PFX "cqicb->sbq_addr = 0x%llx.\n", |
| 534 | le32_to_cpu(cqicb->sbq_addr_lo)); | 525 | (unsigned long long) le64_to_cpu(cqicb->sbq_addr)); |
| 535 | printk(KERN_ERR PFX "cqicb->sbq_addr_hi = %x.\n", | ||
| 536 | le32_to_cpu(cqicb->sbq_addr_hi)); | ||
| 537 | printk(KERN_ERR PFX "cqicb->sbq_buf_size = 0x%.04x.\n", | 526 | printk(KERN_ERR PFX "cqicb->sbq_buf_size = 0x%.04x.\n", |
| 538 | le16_to_cpu(cqicb->sbq_buf_size)); | 527 | le16_to_cpu(cqicb->sbq_buf_size)); |
| 539 | printk(KERN_ERR PFX "cqicb->sbq_len = 0x%.04x.\n", | 528 | printk(KERN_ERR PFX "cqicb->sbq_len = 0x%.04x.\n", |
| @@ -558,9 +547,10 @@ void ql_dump_rx_ring(struct rx_ring *rx_ring) | |||
| 558 | printk(KERN_ERR PFX "rx_ring->cq_size = %d.\n", rx_ring->cq_size); | 547 | printk(KERN_ERR PFX "rx_ring->cq_size = %d.\n", rx_ring->cq_size); |
| 559 | printk(KERN_ERR PFX "rx_ring->cq_len = %d.\n", rx_ring->cq_len); | 548 | printk(KERN_ERR PFX "rx_ring->cq_len = %d.\n", rx_ring->cq_len); |
| 560 | printk(KERN_ERR PFX | 549 | printk(KERN_ERR PFX |
| 561 | "rx_ring->prod_idx_sh_reg, addr = %p, value = %d.\n", | 550 | "rx_ring->prod_idx_sh_reg, addr = 0x%p, value = %d.\n", |
| 562 | rx_ring->prod_idx_sh_reg, | 551 | rx_ring->prod_idx_sh_reg, |
| 563 | rx_ring->prod_idx_sh_reg ? *(rx_ring->prod_idx_sh_reg) : 0); | 552 | rx_ring->prod_idx_sh_reg |
| 553 | ? ql_read_sh_reg(rx_ring->prod_idx_sh_reg) : 0); | ||
| 564 | printk(KERN_ERR PFX "rx_ring->prod_idx_sh_reg_dma = %llx.\n", | 554 | printk(KERN_ERR PFX "rx_ring->prod_idx_sh_reg_dma = %llx.\n", |
| 565 | (unsigned long long) rx_ring->prod_idx_sh_reg_dma); | 555 | (unsigned long long) rx_ring->prod_idx_sh_reg_dma); |
| 566 | printk(KERN_ERR PFX "rx_ring->cnsmr_idx_db_reg = %p.\n", | 556 | printk(KERN_ERR PFX "rx_ring->cnsmr_idx_db_reg = %p.\n", |
| @@ -809,10 +799,8 @@ void ql_dump_ib_mac_rsp(struct ib_mac_iocb_rsp *ib_mac_rsp) | |||
| 809 | 799 | ||
| 810 | printk(KERN_ERR PFX "data_len = %d\n", | 800 | printk(KERN_ERR PFX "data_len = %d\n", |
| 811 | le32_to_cpu(ib_mac_rsp->data_len)); | 801 | le32_to_cpu(ib_mac_rsp->data_len)); |
| 812 | printk(KERN_ERR PFX "data_addr_hi = 0x%x\n", | 802 | printk(KERN_ERR PFX "data_addr = 0x%llx\n", |
| 813 | le32_to_cpu(ib_mac_rsp->data_addr_hi)); | 803 | (unsigned long long) le64_to_cpu(ib_mac_rsp->data_addr)); |
| 814 | printk(KERN_ERR PFX "data_addr_lo = 0x%x\n", | ||
| 815 | le32_to_cpu(ib_mac_rsp->data_addr_lo)); | ||
| 816 | if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_RSS_MASK) | 804 | if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_RSS_MASK) |
| 817 | printk(KERN_ERR PFX "rss = %x\n", | 805 | printk(KERN_ERR PFX "rss = %x\n", |
| 818 | le32_to_cpu(ib_mac_rsp->rss)); | 806 | le32_to_cpu(ib_mac_rsp->rss)); |
| @@ -828,10 +816,8 @@ void ql_dump_ib_mac_rsp(struct ib_mac_iocb_rsp *ib_mac_rsp) | |||
| 828 | if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV) { | 816 | if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV) { |
| 829 | printk(KERN_ERR PFX "hdr length = %d.\n", | 817 | printk(KERN_ERR PFX "hdr length = %d.\n", |
| 830 | le32_to_cpu(ib_mac_rsp->hdr_len)); | 818 | le32_to_cpu(ib_mac_rsp->hdr_len)); |
| 831 | printk(KERN_ERR PFX "hdr addr_hi = 0x%x.\n", | 819 | printk(KERN_ERR PFX "hdr addr = 0x%llx.\n", |
| 832 | le32_to_cpu(ib_mac_rsp->hdr_addr_hi)); | 820 | (unsigned long long) le64_to_cpu(ib_mac_rsp->hdr_addr)); |
| 833 | printk(KERN_ERR PFX "hdr addr_lo = 0x%x.\n", | ||
| 834 | le32_to_cpu(ib_mac_rsp->hdr_addr_lo)); | ||
| 835 | } | 821 | } |
| 836 | } | 822 | } |
| 837 | #endif | 823 | #endif |
diff --git a/drivers/net/qlge/qlge_main.c b/drivers/net/qlge/qlge_main.c index f4c016012f18..45421c8b6010 100644 --- a/drivers/net/qlge/qlge_main.c +++ b/drivers/net/qlge/qlge_main.c | |||
| @@ -76,7 +76,6 @@ MODULE_PARM_DESC(irq_type, "0 = MSI-X, 1 = MSI, 2 = Legacy."); | |||
| 76 | 76 | ||
| 77 | static struct pci_device_id qlge_pci_tbl[] __devinitdata = { | 77 | static struct pci_device_id qlge_pci_tbl[] __devinitdata = { |
| 78 | {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID)}, | 78 | {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID)}, |
| 79 | {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID1)}, | ||
| 80 | /* required last entry */ | 79 | /* required last entry */ |
| 81 | {0,} | 80 | {0,} |
| 82 | }; | 81 | }; |
| @@ -127,12 +126,12 @@ static int ql_sem_trylock(struct ql_adapter *qdev, u32 sem_mask) | |||
| 127 | 126 | ||
| 128 | int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask) | 127 | int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask) |
| 129 | { | 128 | { |
| 130 | unsigned int seconds = 3; | 129 | unsigned int wait_count = 30; |
| 131 | do { | 130 | do { |
| 132 | if (!ql_sem_trylock(qdev, sem_mask)) | 131 | if (!ql_sem_trylock(qdev, sem_mask)) |
| 133 | return 0; | 132 | return 0; |
| 134 | ssleep(1); | 133 | udelay(100); |
| 135 | } while (--seconds); | 134 | } while (--wait_count); |
| 136 | return -ETIMEDOUT; | 135 | return -ETIMEDOUT; |
| 137 | } | 136 | } |
| 138 | 137 | ||
| @@ -1545,7 +1544,7 @@ static void ql_process_chip_ae_intr(struct ql_adapter *qdev, | |||
| 1545 | static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring) | 1544 | static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring) |
| 1546 | { | 1545 | { |
| 1547 | struct ql_adapter *qdev = rx_ring->qdev; | 1546 | struct ql_adapter *qdev = rx_ring->qdev; |
| 1548 | u32 prod = le32_to_cpu(*rx_ring->prod_idx_sh_reg); | 1547 | u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg); |
| 1549 | struct ob_mac_iocb_rsp *net_rsp = NULL; | 1548 | struct ob_mac_iocb_rsp *net_rsp = NULL; |
| 1550 | int count = 0; | 1549 | int count = 0; |
| 1551 | 1550 | ||
| @@ -1571,7 +1570,7 @@ static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring) | |||
| 1571 | } | 1570 | } |
| 1572 | count++; | 1571 | count++; |
| 1573 | ql_update_cq(rx_ring); | 1572 | ql_update_cq(rx_ring); |
| 1574 | prod = le32_to_cpu(*rx_ring->prod_idx_sh_reg); | 1573 | prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg); |
| 1575 | } | 1574 | } |
| 1576 | ql_write_cq_idx(rx_ring); | 1575 | ql_write_cq_idx(rx_ring); |
| 1577 | if (netif_queue_stopped(qdev->ndev) && net_rsp != NULL) { | 1576 | if (netif_queue_stopped(qdev->ndev) && net_rsp != NULL) { |
| @@ -1591,7 +1590,7 @@ static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring) | |||
| 1591 | static int ql_clean_inbound_rx_ring(struct rx_ring *rx_ring, int budget) | 1590 | static int ql_clean_inbound_rx_ring(struct rx_ring *rx_ring, int budget) |
| 1592 | { | 1591 | { |
| 1593 | struct ql_adapter *qdev = rx_ring->qdev; | 1592 | struct ql_adapter *qdev = rx_ring->qdev; |
| 1594 | u32 prod = le32_to_cpu(*rx_ring->prod_idx_sh_reg); | 1593 | u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg); |
| 1595 | struct ql_net_rsp_iocb *net_rsp; | 1594 | struct ql_net_rsp_iocb *net_rsp; |
| 1596 | int count = 0; | 1595 | int count = 0; |
| 1597 | 1596 | ||
| @@ -1624,7 +1623,7 @@ static int ql_clean_inbound_rx_ring(struct rx_ring *rx_ring, int budget) | |||
| 1624 | } | 1623 | } |
| 1625 | count++; | 1624 | count++; |
| 1626 | ql_update_cq(rx_ring); | 1625 | ql_update_cq(rx_ring); |
| 1627 | prod = le32_to_cpu(*rx_ring->prod_idx_sh_reg); | 1626 | prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg); |
| 1628 | if (count == budget) | 1627 | if (count == budget) |
| 1629 | break; | 1628 | break; |
| 1630 | } | 1629 | } |
| @@ -1787,7 +1786,7 @@ static irqreturn_t qlge_isr(int irq, void *dev_id) | |||
| 1787 | * Check the default queue and wake handler if active. | 1786 | * Check the default queue and wake handler if active. |
| 1788 | */ | 1787 | */ |
| 1789 | rx_ring = &qdev->rx_ring[0]; | 1788 | rx_ring = &qdev->rx_ring[0]; |
| 1790 | if (le32_to_cpu(*rx_ring->prod_idx_sh_reg) != rx_ring->cnsmr_idx) { | 1789 | if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) != rx_ring->cnsmr_idx) { |
| 1791 | QPRINTK(qdev, INTR, INFO, "Waking handler for rx_ring[0].\n"); | 1790 | QPRINTK(qdev, INTR, INFO, "Waking handler for rx_ring[0].\n"); |
| 1792 | ql_disable_completion_interrupt(qdev, intr_context->intr); | 1791 | ql_disable_completion_interrupt(qdev, intr_context->intr); |
| 1793 | queue_delayed_work_on(smp_processor_id(), qdev->q_workqueue, | 1792 | queue_delayed_work_on(smp_processor_id(), qdev->q_workqueue, |
| @@ -1801,7 +1800,7 @@ static irqreturn_t qlge_isr(int irq, void *dev_id) | |||
| 1801 | */ | 1800 | */ |
| 1802 | for (i = 1; i < qdev->rx_ring_count; i++) { | 1801 | for (i = 1; i < qdev->rx_ring_count; i++) { |
| 1803 | rx_ring = &qdev->rx_ring[i]; | 1802 | rx_ring = &qdev->rx_ring[i]; |
| 1804 | if (le32_to_cpu(*rx_ring->prod_idx_sh_reg) != | 1803 | if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) != |
| 1805 | rx_ring->cnsmr_idx) { | 1804 | rx_ring->cnsmr_idx) { |
| 1806 | QPRINTK(qdev, INTR, INFO, | 1805 | QPRINTK(qdev, INTR, INFO, |
| 1807 | "Waking handler for rx_ring[%d].\n", i); | 1806 | "Waking handler for rx_ring[%d].\n", i); |
| @@ -2356,28 +2355,6 @@ static void ql_tx_ring_clean(struct ql_adapter *qdev) | |||
| 2356 | } | 2355 | } |
| 2357 | } | 2356 | } |
| 2358 | 2357 | ||
| 2359 | static void ql_free_ring_cb(struct ql_adapter *qdev) | ||
| 2360 | { | ||
| 2361 | kfree(qdev->ring_mem); | ||
| 2362 | } | ||
| 2363 | |||
| 2364 | static int ql_alloc_ring_cb(struct ql_adapter *qdev) | ||
| 2365 | { | ||
| 2366 | /* Allocate space for tx/rx ring control blocks. */ | ||
| 2367 | qdev->ring_mem_size = | ||
| 2368 | (qdev->tx_ring_count * sizeof(struct tx_ring)) + | ||
| 2369 | (qdev->rx_ring_count * sizeof(struct rx_ring)); | ||
| 2370 | qdev->ring_mem = kmalloc(qdev->ring_mem_size, GFP_KERNEL); | ||
| 2371 | if (qdev->ring_mem == NULL) { | ||
| 2372 | return -ENOMEM; | ||
| 2373 | } else { | ||
| 2374 | qdev->rx_ring = qdev->ring_mem; | ||
| 2375 | qdev->tx_ring = qdev->ring_mem + | ||
| 2376 | (qdev->rx_ring_count * sizeof(struct rx_ring)); | ||
| 2377 | } | ||
| 2378 | return 0; | ||
| 2379 | } | ||
| 2380 | |||
| 2381 | static void ql_free_mem_resources(struct ql_adapter *qdev) | 2358 | static void ql_free_mem_resources(struct ql_adapter *qdev) |
| 2382 | { | 2359 | { |
| 2383 | int i; | 2360 | int i; |
| @@ -2467,12 +2444,9 @@ static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring) | |||
| 2467 | bq_len = (rx_ring->cq_len == 65536) ? 0 : (u16) rx_ring->cq_len; | 2444 | bq_len = (rx_ring->cq_len == 65536) ? 0 : (u16) rx_ring->cq_len; |
| 2468 | cqicb->len = cpu_to_le16(bq_len | LEN_V | LEN_CPP_CONT); | 2445 | cqicb->len = cpu_to_le16(bq_len | LEN_V | LEN_CPP_CONT); |
| 2469 | 2446 | ||
| 2470 | cqicb->addr_lo = cpu_to_le32(rx_ring->cq_base_dma); | 2447 | cqicb->addr = cpu_to_le64(rx_ring->cq_base_dma); |
| 2471 | cqicb->addr_hi = cpu_to_le32((u64) rx_ring->cq_base_dma >> 32); | ||
| 2472 | 2448 | ||
| 2473 | cqicb->prod_idx_addr_lo = cpu_to_le32(rx_ring->prod_idx_sh_reg_dma); | 2449 | cqicb->prod_idx_addr = cpu_to_le64(rx_ring->prod_idx_sh_reg_dma); |
| 2474 | cqicb->prod_idx_addr_hi = | ||
| 2475 | cpu_to_le32((u64) rx_ring->prod_idx_sh_reg_dma >> 32); | ||
| 2476 | 2450 | ||
| 2477 | /* | 2451 | /* |
| 2478 | * Set up the control block load flags. | 2452 | * Set up the control block load flags. |
| @@ -2483,10 +2457,8 @@ static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring) | |||
| 2483 | if (rx_ring->lbq_len) { | 2457 | if (rx_ring->lbq_len) { |
| 2484 | cqicb->flags |= FLAGS_LL; /* Load lbq values */ | 2458 | cqicb->flags |= FLAGS_LL; /* Load lbq values */ |
| 2485 | *((u64 *) rx_ring->lbq_base_indirect) = rx_ring->lbq_base_dma; | 2459 | *((u64 *) rx_ring->lbq_base_indirect) = rx_ring->lbq_base_dma; |
| 2486 | cqicb->lbq_addr_lo = | 2460 | cqicb->lbq_addr = |
| 2487 | cpu_to_le32(rx_ring->lbq_base_indirect_dma); | 2461 | cpu_to_le64(rx_ring->lbq_base_indirect_dma); |
| 2488 | cqicb->lbq_addr_hi = | ||
| 2489 | cpu_to_le32((u64) rx_ring->lbq_base_indirect_dma >> 32); | ||
| 2490 | bq_len = (rx_ring->lbq_buf_size == 65536) ? 0 : | 2462 | bq_len = (rx_ring->lbq_buf_size == 65536) ? 0 : |
| 2491 | (u16) rx_ring->lbq_buf_size; | 2463 | (u16) rx_ring->lbq_buf_size; |
| 2492 | cqicb->lbq_buf_size = cpu_to_le16(bq_len); | 2464 | cqicb->lbq_buf_size = cpu_to_le16(bq_len); |
| @@ -2501,10 +2473,8 @@ static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring) | |||
| 2501 | if (rx_ring->sbq_len) { | 2473 | if (rx_ring->sbq_len) { |
| 2502 | cqicb->flags |= FLAGS_LS; /* Load sbq values */ | 2474 | cqicb->flags |= FLAGS_LS; /* Load sbq values */ |
| 2503 | *((u64 *) rx_ring->sbq_base_indirect) = rx_ring->sbq_base_dma; | 2475 | *((u64 *) rx_ring->sbq_base_indirect) = rx_ring->sbq_base_dma; |
| 2504 | cqicb->sbq_addr_lo = | 2476 | cqicb->sbq_addr = |
| 2505 | cpu_to_le32(rx_ring->sbq_base_indirect_dma); | 2477 | cpu_to_le64(rx_ring->sbq_base_indirect_dma); |
| 2506 | cqicb->sbq_addr_hi = | ||
| 2507 | cpu_to_le32((u64) rx_ring->sbq_base_indirect_dma >> 32); | ||
| 2508 | cqicb->sbq_buf_size = | 2478 | cqicb->sbq_buf_size = |
| 2509 | cpu_to_le16(((rx_ring->sbq_buf_size / 2) + 8) & 0xfffffff8); | 2479 | cpu_to_le16(((rx_ring->sbq_buf_size / 2) + 8) & 0xfffffff8); |
| 2510 | bq_len = (rx_ring->sbq_len == 65536) ? 0 : | 2480 | bq_len = (rx_ring->sbq_len == 65536) ? 0 : |
| @@ -2611,12 +2581,9 @@ static int ql_start_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring) | |||
| 2611 | Q_FLAGS_LB | Q_FLAGS_LI | Q_FLAGS_LO); | 2581 | Q_FLAGS_LB | Q_FLAGS_LI | Q_FLAGS_LO); |
| 2612 | wqicb->cq_id_rss = cpu_to_le16(tx_ring->cq_id); | 2582 | wqicb->cq_id_rss = cpu_to_le16(tx_ring->cq_id); |
| 2613 | wqicb->rid = 0; | 2583 | wqicb->rid = 0; |
| 2614 | wqicb->addr_lo = cpu_to_le32(tx_ring->wq_base_dma); | 2584 | wqicb->addr = cpu_to_le64(tx_ring->wq_base_dma); |
| 2615 | wqicb->addr_hi = cpu_to_le32((u64) tx_ring->wq_base_dma >> 32); | ||
| 2616 | 2585 | ||
| 2617 | wqicb->cnsmr_idx_addr_lo = cpu_to_le32(tx_ring->cnsmr_idx_sh_reg_dma); | 2586 | wqicb->cnsmr_idx_addr = cpu_to_le64(tx_ring->cnsmr_idx_sh_reg_dma); |
| 2618 | wqicb->cnsmr_idx_addr_hi = | ||
| 2619 | cpu_to_le32((u64) tx_ring->cnsmr_idx_sh_reg_dma >> 32); | ||
| 2620 | 2587 | ||
| 2621 | ql_init_tx_ring(qdev, tx_ring); | 2588 | ql_init_tx_ring(qdev, tx_ring); |
| 2622 | 2589 | ||
| @@ -2746,14 +2713,14 @@ static void ql_resolve_queues_to_irqs(struct ql_adapter *qdev) | |||
| 2746 | * Outbound queue is for outbound completions only. | 2713 | * Outbound queue is for outbound completions only. |
| 2747 | */ | 2714 | */ |
| 2748 | intr_context->handler = qlge_msix_tx_isr; | 2715 | intr_context->handler = qlge_msix_tx_isr; |
| 2749 | sprintf(intr_context->name, "%s-txq-%d", | 2716 | sprintf(intr_context->name, "%s-tx-%d", |
| 2750 | qdev->ndev->name, i); | 2717 | qdev->ndev->name, i); |
| 2751 | } else { | 2718 | } else { |
| 2752 | /* | 2719 | /* |
| 2753 | * Inbound queues handle unicast frames only. | 2720 | * Inbound queues handle unicast frames only. |
| 2754 | */ | 2721 | */ |
| 2755 | intr_context->handler = qlge_msix_rx_isr; | 2722 | intr_context->handler = qlge_msix_rx_isr; |
| 2756 | sprintf(intr_context->name, "%s-rxq-%d", | 2723 | sprintf(intr_context->name, "%s-rx-%d", |
| 2757 | qdev->ndev->name, i); | 2724 | qdev->ndev->name, i); |
| 2758 | } | 2725 | } |
| 2759 | } | 2726 | } |
| @@ -3247,7 +3214,6 @@ static int qlge_close(struct net_device *ndev) | |||
| 3247 | msleep(1); | 3214 | msleep(1); |
| 3248 | ql_adapter_down(qdev); | 3215 | ql_adapter_down(qdev); |
| 3249 | ql_release_adapter_resources(qdev); | 3216 | ql_release_adapter_resources(qdev); |
| 3250 | ql_free_ring_cb(qdev); | ||
| 3251 | return 0; | 3217 | return 0; |
| 3252 | } | 3218 | } |
| 3253 | 3219 | ||
| @@ -3273,8 +3239,8 @@ static int ql_configure_rings(struct ql_adapter *qdev) | |||
| 3273 | * This limitation can be removed when requested. | 3239 | * This limitation can be removed when requested. |
| 3274 | */ | 3240 | */ |
| 3275 | 3241 | ||
| 3276 | if (cpu_cnt > 8) | 3242 | if (cpu_cnt > MAX_CPUS) |
| 3277 | cpu_cnt = 8; | 3243 | cpu_cnt = MAX_CPUS; |
| 3278 | 3244 | ||
| 3279 | /* | 3245 | /* |
| 3280 | * rx_ring[0] is always the default queue. | 3246 | * rx_ring[0] is always the default queue. |
| @@ -3294,9 +3260,6 @@ static int ql_configure_rings(struct ql_adapter *qdev) | |||
| 3294 | */ | 3260 | */ |
| 3295 | qdev->rx_ring_count = qdev->tx_ring_count + qdev->rss_ring_count + 1; | 3261 | qdev->rx_ring_count = qdev->tx_ring_count + qdev->rss_ring_count + 1; |
| 3296 | 3262 | ||
| 3297 | if (ql_alloc_ring_cb(qdev)) | ||
| 3298 | return -ENOMEM; | ||
| 3299 | |||
| 3300 | for (i = 0; i < qdev->tx_ring_count; i++) { | 3263 | for (i = 0; i < qdev->tx_ring_count; i++) { |
| 3301 | tx_ring = &qdev->tx_ring[i]; | 3264 | tx_ring = &qdev->tx_ring[i]; |
| 3302 | memset((void *)tx_ring, 0, sizeof(tx_ring)); | 3265 | memset((void *)tx_ring, 0, sizeof(tx_ring)); |
| @@ -3393,7 +3356,6 @@ static int qlge_open(struct net_device *ndev) | |||
| 3393 | 3356 | ||
| 3394 | error_up: | 3357 | error_up: |
| 3395 | ql_release_adapter_resources(qdev); | 3358 | ql_release_adapter_resources(qdev); |
| 3396 | ql_free_ring_cb(qdev); | ||
| 3397 | return err; | 3359 | return err; |
| 3398 | } | 3360 | } |
| 3399 | 3361 | ||
diff --git a/drivers/net/r6040.c b/drivers/net/r6040.c index cf3a082bc89d..72fd9e97c190 100644 --- a/drivers/net/r6040.c +++ b/drivers/net/r6040.c | |||
| @@ -49,8 +49,8 @@ | |||
| 49 | #include <asm/processor.h> | 49 | #include <asm/processor.h> |
| 50 | 50 | ||
| 51 | #define DRV_NAME "r6040" | 51 | #define DRV_NAME "r6040" |
| 52 | #define DRV_VERSION "0.20" | 52 | #define DRV_VERSION "0.21" |
| 53 | #define DRV_RELDATE "07Jan2009" | 53 | #define DRV_RELDATE "09Jan2009" |
| 54 | 54 | ||
| 55 | /* PHY CHIP Address */ | 55 | /* PHY CHIP Address */ |
| 56 | #define PHY1_ADDR 1 /* For MAC1 */ | 56 | #define PHY1_ADDR 1 /* For MAC1 */ |
| @@ -457,22 +457,12 @@ static void r6040_down(struct net_device *dev) | |||
| 457 | iowrite16(adrp[0], ioaddr + MID_0L); | 457 | iowrite16(adrp[0], ioaddr + MID_0L); |
| 458 | iowrite16(adrp[1], ioaddr + MID_0M); | 458 | iowrite16(adrp[1], ioaddr + MID_0M); |
| 459 | iowrite16(adrp[2], ioaddr + MID_0H); | 459 | iowrite16(adrp[2], ioaddr + MID_0H); |
| 460 | free_irq(dev->irq, dev); | ||
| 461 | |||
| 462 | /* Free RX buffer */ | ||
| 463 | r6040_free_rxbufs(dev); | ||
| 464 | |||
| 465 | /* Free TX buffer */ | ||
| 466 | r6040_free_txbufs(dev); | ||
| 467 | |||
| 468 | /* Free Descriptor memory */ | ||
| 469 | pci_free_consistent(pdev, RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma); | ||
| 470 | pci_free_consistent(pdev, TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma); | ||
| 471 | } | 460 | } |
| 472 | 461 | ||
| 473 | static int r6040_close(struct net_device *dev) | 462 | static int r6040_close(struct net_device *dev) |
| 474 | { | 463 | { |
| 475 | struct r6040_private *lp = netdev_priv(dev); | 464 | struct r6040_private *lp = netdev_priv(dev); |
| 465 | struct pci_dev *pdev = lp->pdev; | ||
| 476 | 466 | ||
| 477 | /* deleted timer */ | 467 | /* deleted timer */ |
| 478 | del_timer_sync(&lp->timer); | 468 | del_timer_sync(&lp->timer); |
| @@ -481,8 +471,28 @@ static int r6040_close(struct net_device *dev) | |||
| 481 | napi_disable(&lp->napi); | 471 | napi_disable(&lp->napi); |
| 482 | netif_stop_queue(dev); | 472 | netif_stop_queue(dev); |
| 483 | r6040_down(dev); | 473 | r6040_down(dev); |
| 474 | |||
| 475 | free_irq(dev->irq, dev); | ||
| 476 | |||
| 477 | /* Free RX buffer */ | ||
| 478 | r6040_free_rxbufs(dev); | ||
| 479 | |||
| 480 | /* Free TX buffer */ | ||
| 481 | r6040_free_txbufs(dev); | ||
| 482 | |||
| 484 | spin_unlock_irq(&lp->lock); | 483 | spin_unlock_irq(&lp->lock); |
| 485 | 484 | ||
| 485 | /* Free Descriptor memory */ | ||
| 486 | if (lp->rx_ring) { | ||
| 487 | pci_free_consistent(pdev, RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma); | ||
| 488 | lp->rx_ring = 0; | ||
| 489 | } | ||
| 490 | |||
| 491 | if (lp->tx_ring) { | ||
| 492 | pci_free_consistent(pdev, TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma); | ||
| 493 | lp->tx_ring = 0; | ||
| 494 | } | ||
| 495 | |||
| 486 | return 0; | 496 | return 0; |
| 487 | } | 497 | } |
| 488 | 498 | ||
| @@ -1049,6 +1059,7 @@ static const struct net_device_ops r6040_netdev_ops = { | |||
| 1049 | .ndo_set_multicast_list = r6040_multicast_list, | 1059 | .ndo_set_multicast_list = r6040_multicast_list, |
| 1050 | .ndo_change_mtu = eth_change_mtu, | 1060 | .ndo_change_mtu = eth_change_mtu, |
| 1051 | .ndo_validate_addr = eth_validate_addr, | 1061 | .ndo_validate_addr = eth_validate_addr, |
| 1062 | .ndo_set_mac_address = eth_mac_addr, | ||
| 1052 | .ndo_do_ioctl = r6040_ioctl, | 1063 | .ndo_do_ioctl = r6040_ioctl, |
| 1053 | .ndo_tx_timeout = r6040_tx_timeout, | 1064 | .ndo_tx_timeout = r6040_tx_timeout, |
| 1054 | #ifdef CONFIG_NET_POLL_CONTROLLER | 1065 | #ifdef CONFIG_NET_POLL_CONTROLLER |
| @@ -1143,8 +1154,10 @@ static int __devinit r6040_init_one(struct pci_dev *pdev, | |||
| 1143 | 1154 | ||
| 1144 | /* Some bootloader/BIOSes do not initialize | 1155 | /* Some bootloader/BIOSes do not initialize |
| 1145 | * MAC address, warn about that */ | 1156 | * MAC address, warn about that */ |
| 1146 | if (!(adrp[0] || adrp[1] || adrp[2])) | 1157 | if (!(adrp[0] || adrp[1] || adrp[2])) { |
| 1147 | printk(KERN_WARNING DRV_NAME ": MAC address not initialized\n"); | 1158 | printk(KERN_WARNING DRV_NAME ": MAC address not initialized, generating random\n"); |
| 1159 | random_ether_addr(dev->dev_addr); | ||
| 1160 | } | ||
| 1148 | 1161 | ||
| 1149 | /* Link new device into r6040_root_dev */ | 1162 | /* Link new device into r6040_root_dev */ |
| 1150 | lp->pdev = pdev; | 1163 | lp->pdev = pdev; |
diff --git a/drivers/net/sc92031.c b/drivers/net/sc92031.c index 42fd31276602..8b75bef4a841 100644 --- a/drivers/net/sc92031.c +++ b/drivers/net/sc92031.c | |||
| @@ -1408,6 +1408,7 @@ static const struct net_device_ops sc92031_netdev_ops = { | |||
| 1408 | .ndo_set_multicast_list = sc92031_set_multicast_list, | 1408 | .ndo_set_multicast_list = sc92031_set_multicast_list, |
| 1409 | .ndo_change_mtu = eth_change_mtu, | 1409 | .ndo_change_mtu = eth_change_mtu, |
| 1410 | .ndo_validate_addr = eth_validate_addr, | 1410 | .ndo_validate_addr = eth_validate_addr, |
| 1411 | .ndo_set_mac_address = eth_mac_addr, | ||
| 1411 | .ndo_tx_timeout = sc92031_tx_timeout, | 1412 | .ndo_tx_timeout = sc92031_tx_timeout, |
| 1412 | #ifdef CONFIG_NET_POLL_CONTROLLER | 1413 | #ifdef CONFIG_NET_POLL_CONTROLLER |
| 1413 | .ndo_poll_controller = sc92031_poll_controller, | 1414 | .ndo_poll_controller = sc92031_poll_controller, |
diff --git a/drivers/net/sfc/tenxpress.c b/drivers/net/sfc/tenxpress.c index b9768760fae7..9ecb77da9545 100644 --- a/drivers/net/sfc/tenxpress.c +++ b/drivers/net/sfc/tenxpress.c | |||
| @@ -636,10 +636,11 @@ static void tenxpress_phy_fini(struct efx_nic *efx) | |||
| 636 | { | 636 | { |
| 637 | int reg; | 637 | int reg; |
| 638 | 638 | ||
| 639 | if (efx->phy_type == PHY_TYPE_SFT9001B) { | 639 | if (efx->phy_type == PHY_TYPE_SFT9001B) |
| 640 | device_remove_file(&efx->pci_dev->dev, | 640 | device_remove_file(&efx->pci_dev->dev, |
| 641 | &dev_attr_phy_short_reach); | 641 | &dev_attr_phy_short_reach); |
| 642 | } else { | 642 | |
| 643 | if (efx->phy_type == PHY_TYPE_SFX7101) { | ||
| 643 | /* Power down the LNPGA */ | 644 | /* Power down the LNPGA */ |
| 644 | reg = (1 << PMA_PMD_LNPGA_POWERDOWN_LBN); | 645 | reg = (1 << PMA_PMD_LNPGA_POWERDOWN_LBN); |
| 645 | mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD, | 646 | mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD, |
diff --git a/drivers/net/sis900.c b/drivers/net/sis900.c index 4acd41a093ad..6cbefcae9ac2 100644 --- a/drivers/net/sis900.c +++ b/drivers/net/sis900.c | |||
| @@ -389,6 +389,7 @@ static const struct net_device_ops sis900_netdev_ops = { | |||
| 389 | .ndo_set_multicast_list = set_rx_mode, | 389 | .ndo_set_multicast_list = set_rx_mode, |
| 390 | .ndo_change_mtu = eth_change_mtu, | 390 | .ndo_change_mtu = eth_change_mtu, |
| 391 | .ndo_validate_addr = eth_validate_addr, | 391 | .ndo_validate_addr = eth_validate_addr, |
| 392 | .ndo_set_mac_address = eth_mac_addr, | ||
| 392 | .ndo_do_ioctl = mii_ioctl, | 393 | .ndo_do_ioctl = mii_ioctl, |
| 393 | .ndo_tx_timeout = sis900_tx_timeout, | 394 | .ndo_tx_timeout = sis900_tx_timeout, |
| 394 | #ifdef CONFIG_NET_POLL_CONTROLLER | 395 | #ifdef CONFIG_NET_POLL_CONTROLLER |
diff --git a/drivers/net/smc-mca.c b/drivers/net/smc-mca.c index 404b80e5ba11..8d36d40649ef 100644 --- a/drivers/net/smc-mca.c +++ b/drivers/net/smc-mca.c | |||
| @@ -192,6 +192,7 @@ static const struct net_device_ops ultramca_netdev_ops = { | |||
| 192 | .ndo_get_stats = ei_get_stats, | 192 | .ndo_get_stats = ei_get_stats, |
| 193 | .ndo_set_multicast_list = ei_set_multicast_list, | 193 | .ndo_set_multicast_list = ei_set_multicast_list, |
| 194 | .ndo_validate_addr = eth_validate_addr, | 194 | .ndo_validate_addr = eth_validate_addr, |
| 195 | .ndo_set_mac_address = eth_mac_addr, | ||
| 195 | .ndo_change_mtu = eth_change_mtu, | 196 | .ndo_change_mtu = eth_change_mtu, |
| 196 | #ifdef CONFIG_NET_POLL_CONTROLLER | 197 | #ifdef CONFIG_NET_POLL_CONTROLLER |
| 197 | .ndo_poll_controller = ei_poll, | 198 | .ndo_poll_controller = ei_poll, |
diff --git a/drivers/net/smc-ultra.c b/drivers/net/smc-ultra.c index b3866089a206..2033fee3143a 100644 --- a/drivers/net/smc-ultra.c +++ b/drivers/net/smc-ultra.c | |||
| @@ -196,6 +196,7 @@ static const struct net_device_ops ultra_netdev_ops = { | |||
| 196 | .ndo_get_stats = ei_get_stats, | 196 | .ndo_get_stats = ei_get_stats, |
| 197 | .ndo_set_multicast_list = ei_set_multicast_list, | 197 | .ndo_set_multicast_list = ei_set_multicast_list, |
| 198 | .ndo_validate_addr = eth_validate_addr, | 198 | .ndo_validate_addr = eth_validate_addr, |
| 199 | .ndo_set_mac_address = eth_mac_addr, | ||
| 199 | .ndo_change_mtu = eth_change_mtu, | 200 | .ndo_change_mtu = eth_change_mtu, |
| 200 | #ifdef CONFIG_NET_POLL_CONTROLLER | 201 | #ifdef CONFIG_NET_POLL_CONTROLLER |
| 201 | .ndo_poll_controller = ei_poll, | 202 | .ndo_poll_controller = ei_poll, |
diff --git a/drivers/net/smsc911x.c b/drivers/net/smsc911x.c index dc3f1108884d..f513bdf1c887 100644 --- a/drivers/net/smsc911x.c +++ b/drivers/net/smsc911x.c | |||
| @@ -144,6 +144,7 @@ static inline u32 smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg) | |||
| 144 | } | 144 | } |
| 145 | 145 | ||
| 146 | BUG(); | 146 | BUG(); |
| 147 | return 0; | ||
| 147 | } | 148 | } |
| 148 | 149 | ||
| 149 | static inline void smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg, | 150 | static inline void smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg, |
| @@ -1740,6 +1741,7 @@ static const struct net_device_ops smsc911x_netdev_ops = { | |||
| 1740 | .ndo_set_multicast_list = smsc911x_set_multicast_list, | 1741 | .ndo_set_multicast_list = smsc911x_set_multicast_list, |
| 1741 | .ndo_do_ioctl = smsc911x_do_ioctl, | 1742 | .ndo_do_ioctl = smsc911x_do_ioctl, |
| 1742 | .ndo_validate_addr = eth_validate_addr, | 1743 | .ndo_validate_addr = eth_validate_addr, |
| 1744 | .ndo_set_mac_address = eth_mac_addr, | ||
| 1743 | #ifdef CONFIG_NET_POLL_CONTROLLER | 1745 | #ifdef CONFIG_NET_POLL_CONTROLLER |
| 1744 | .ndo_poll_controller = smsc911x_poll_controller, | 1746 | .ndo_poll_controller = smsc911x_poll_controller, |
| 1745 | #endif | 1747 | #endif |
| @@ -1967,7 +1969,7 @@ static int __devinit smsc911x_drv_probe(struct platform_device *pdev) | |||
| 1967 | smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF); | 1969 | smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF); |
| 1968 | 1970 | ||
| 1969 | retval = request_irq(dev->irq, smsc911x_irqhandler, IRQF_DISABLED, | 1971 | retval = request_irq(dev->irq, smsc911x_irqhandler, IRQF_DISABLED, |
| 1970 | SMSC_CHIPNAME, dev); | 1972 | dev->name, dev); |
| 1971 | if (retval) { | 1973 | if (retval) { |
| 1972 | SMSC_WARNING(PROBE, | 1974 | SMSC_WARNING(PROBE, |
| 1973 | "Unable to claim requested irq: %d", dev->irq); | 1975 | "Unable to claim requested irq: %d", dev->irq); |
diff --git a/drivers/net/smsc9420.c b/drivers/net/smsc9420.c index 27e017d96966..c14a4c6452c7 100644 --- a/drivers/net/smsc9420.c +++ b/drivers/net/smsc9420.c | |||
| @@ -1551,6 +1551,7 @@ static const struct net_device_ops smsc9420_netdev_ops = { | |||
| 1551 | .ndo_set_multicast_list = smsc9420_set_multicast_list, | 1551 | .ndo_set_multicast_list = smsc9420_set_multicast_list, |
| 1552 | .ndo_do_ioctl = smsc9420_do_ioctl, | 1552 | .ndo_do_ioctl = smsc9420_do_ioctl, |
| 1553 | .ndo_validate_addr = eth_validate_addr, | 1553 | .ndo_validate_addr = eth_validate_addr, |
| 1554 | .ndo_set_mac_address = eth_mac_addr, | ||
| 1554 | #ifdef CONFIG_NET_POLL_CONTROLLER | 1555 | #ifdef CONFIG_NET_POLL_CONTROLLER |
| 1555 | .ndo_poll_controller = smsc9420_poll_controller, | 1556 | .ndo_poll_controller = smsc9420_poll_controller, |
| 1556 | #endif /* CONFIG_NET_POLL_CONTROLLER */ | 1557 | #endif /* CONFIG_NET_POLL_CONTROLLER */ |
diff --git a/drivers/net/ucc_geth.c b/drivers/net/ucc_geth.c index 7d5a1303e30d..11441225bf41 100644 --- a/drivers/net/ucc_geth.c +++ b/drivers/net/ucc_geth.c | |||
| @@ -442,40 +442,30 @@ static void magic_packet_detection_enable(struct ucc_geth_private *ugeth) | |||
| 442 | { | 442 | { |
| 443 | struct ucc_fast_private *uccf; | 443 | struct ucc_fast_private *uccf; |
| 444 | struct ucc_geth __iomem *ug_regs; | 444 | struct ucc_geth __iomem *ug_regs; |
| 445 | u32 maccfg2, uccm; | ||
| 446 | 445 | ||
| 447 | uccf = ugeth->uccf; | 446 | uccf = ugeth->uccf; |
| 448 | ug_regs = ugeth->ug_regs; | 447 | ug_regs = ugeth->ug_regs; |
| 449 | 448 | ||
| 450 | /* Enable interrupts for magic packet detection */ | 449 | /* Enable interrupts for magic packet detection */ |
| 451 | uccm = in_be32(uccf->p_uccm); | 450 | setbits32(uccf->p_uccm, UCC_GETH_UCCE_MPD); |
| 452 | uccm |= UCCE_MPD; | ||
| 453 | out_be32(uccf->p_uccm, uccm); | ||
| 454 | 451 | ||
| 455 | /* Enable magic packet detection */ | 452 | /* Enable magic packet detection */ |
| 456 | maccfg2 = in_be32(&ug_regs->maccfg2); | 453 | setbits32(&ug_regs->maccfg2, MACCFG2_MPE); |
| 457 | maccfg2 |= MACCFG2_MPE; | ||
| 458 | out_be32(&ug_regs->maccfg2, maccfg2); | ||
| 459 | } | 454 | } |
| 460 | 455 | ||
| 461 | static void magic_packet_detection_disable(struct ucc_geth_private *ugeth) | 456 | static void magic_packet_detection_disable(struct ucc_geth_private *ugeth) |
| 462 | { | 457 | { |
| 463 | struct ucc_fast_private *uccf; | 458 | struct ucc_fast_private *uccf; |
| 464 | struct ucc_geth __iomem *ug_regs; | 459 | struct ucc_geth __iomem *ug_regs; |
| 465 | u32 maccfg2, uccm; | ||
| 466 | 460 | ||
| 467 | uccf = ugeth->uccf; | 461 | uccf = ugeth->uccf; |
| 468 | ug_regs = ugeth->ug_regs; | 462 | ug_regs = ugeth->ug_regs; |
| 469 | 463 | ||
| 470 | /* Disable interrupts for magic packet detection */ | 464 | /* Disable interrupts for magic packet detection */ |
| 471 | uccm = in_be32(uccf->p_uccm); | 465 | clrbits32(uccf->p_uccm, UCC_GETH_UCCE_MPD); |
| 472 | uccm &= ~UCCE_MPD; | ||
| 473 | out_be32(uccf->p_uccm, uccm); | ||
| 474 | 466 | ||
| 475 | /* Disable magic packet detection */ | 467 | /* Disable magic packet detection */ |
| 476 | maccfg2 = in_be32(&ug_regs->maccfg2); | 468 | clrbits32(&ug_regs->maccfg2, MACCFG2_MPE); |
| 477 | maccfg2 &= ~MACCFG2_MPE; | ||
| 478 | out_be32(&ug_regs->maccfg2, maccfg2); | ||
| 479 | } | 469 | } |
| 480 | #endif /* MAGIC_PACKET */ | 470 | #endif /* MAGIC_PACKET */ |
| 481 | 471 | ||
| @@ -585,7 +575,8 @@ static void get_statistics(struct ucc_geth_private *ugeth, | |||
| 585 | 575 | ||
| 586 | /* Hardware only if user handed pointer and driver actually | 576 | /* Hardware only if user handed pointer and driver actually |
| 587 | gathers hardware statistics */ | 577 | gathers hardware statistics */ |
| 588 | if (hardware_statistics && (in_be32(&uf_regs->upsmr) & UPSMR_HSE)) { | 578 | if (hardware_statistics && |
| 579 | (in_be32(&uf_regs->upsmr) & UCC_GETH_UPSMR_HSE)) { | ||
| 589 | hardware_statistics->tx64 = in_be32(&ug_regs->tx64); | 580 | hardware_statistics->tx64 = in_be32(&ug_regs->tx64); |
| 590 | hardware_statistics->tx127 = in_be32(&ug_regs->tx127); | 581 | hardware_statistics->tx127 = in_be32(&ug_regs->tx127); |
| 591 | hardware_statistics->tx255 = in_be32(&ug_regs->tx255); | 582 | hardware_statistics->tx255 = in_be32(&ug_regs->tx255); |
| @@ -1181,9 +1172,7 @@ int init_flow_control_params(u32 automatic_flow_control_mode, | |||
| 1181 | out_be32(uempr_register, value); | 1172 | out_be32(uempr_register, value); |
| 1182 | 1173 | ||
| 1183 | /* Set UPSMR register */ | 1174 | /* Set UPSMR register */ |
| 1184 | value = in_be32(upsmr_register); | 1175 | setbits32(upsmr_register, automatic_flow_control_mode); |
| 1185 | value |= automatic_flow_control_mode; | ||
| 1186 | out_be32(upsmr_register, value); | ||
| 1187 | 1176 | ||
| 1188 | value = in_be32(maccfg1_register); | 1177 | value = in_be32(maccfg1_register); |
| 1189 | if (rx_flow_control_enable) | 1178 | if (rx_flow_control_enable) |
| @@ -1200,14 +1189,11 @@ static int init_hw_statistics_gathering_mode(int enable_hardware_statistics, | |||
| 1200 | u32 __iomem *upsmr_register, | 1189 | u32 __iomem *upsmr_register, |
| 1201 | u16 __iomem *uescr_register) | 1190 | u16 __iomem *uescr_register) |
| 1202 | { | 1191 | { |
| 1203 | u32 upsmr_value = 0; | ||
| 1204 | u16 uescr_value = 0; | 1192 | u16 uescr_value = 0; |
| 1193 | |||
| 1205 | /* Enable hardware statistics gathering if requested */ | 1194 | /* Enable hardware statistics gathering if requested */ |
| 1206 | if (enable_hardware_statistics) { | 1195 | if (enable_hardware_statistics) |
| 1207 | upsmr_value = in_be32(upsmr_register); | 1196 | setbits32(upsmr_register, UCC_GETH_UPSMR_HSE); |
| 1208 | upsmr_value |= UPSMR_HSE; | ||
| 1209 | out_be32(upsmr_register, upsmr_value); | ||
| 1210 | } | ||
| 1211 | 1197 | ||
| 1212 | /* Clear hardware statistics counters */ | 1198 | /* Clear hardware statistics counters */ |
| 1213 | uescr_value = in_be16(uescr_register); | 1199 | uescr_value = in_be16(uescr_register); |
| @@ -1233,23 +1219,17 @@ static int init_firmware_statistics_gathering_mode(int | |||
| 1233 | { | 1219 | { |
| 1234 | /* Note: this function does not check if */ | 1220 | /* Note: this function does not check if */ |
| 1235 | /* the parameters it receives are NULL */ | 1221 | /* the parameters it receives are NULL */ |
| 1236 | u16 temoder_value; | ||
| 1237 | u32 remoder_value; | ||
| 1238 | 1222 | ||
| 1239 | if (enable_tx_firmware_statistics) { | 1223 | if (enable_tx_firmware_statistics) { |
| 1240 | out_be32(tx_rmon_base_ptr, | 1224 | out_be32(tx_rmon_base_ptr, |
| 1241 | tx_firmware_statistics_structure_address); | 1225 | tx_firmware_statistics_structure_address); |
| 1242 | temoder_value = in_be16(temoder_register); | 1226 | setbits16(temoder_register, TEMODER_TX_RMON_STATISTICS_ENABLE); |
| 1243 | temoder_value |= TEMODER_TX_RMON_STATISTICS_ENABLE; | ||
| 1244 | out_be16(temoder_register, temoder_value); | ||
| 1245 | } | 1227 | } |
| 1246 | 1228 | ||
| 1247 | if (enable_rx_firmware_statistics) { | 1229 | if (enable_rx_firmware_statistics) { |
| 1248 | out_be32(rx_rmon_base_ptr, | 1230 | out_be32(rx_rmon_base_ptr, |
| 1249 | rx_firmware_statistics_structure_address); | 1231 | rx_firmware_statistics_structure_address); |
| 1250 | remoder_value = in_be32(remoder_register); | 1232 | setbits32(remoder_register, REMODER_RX_RMON_STATISTICS_ENABLE); |
| 1251 | remoder_value |= REMODER_RX_RMON_STATISTICS_ENABLE; | ||
| 1252 | out_be32(remoder_register, remoder_value); | ||
| 1253 | } | 1233 | } |
| 1254 | 1234 | ||
| 1255 | return 0; | 1235 | return 0; |
| @@ -1316,15 +1296,12 @@ static int init_check_frame_length_mode(int length_check, | |||
| 1316 | static int init_preamble_length(u8 preamble_length, | 1296 | static int init_preamble_length(u8 preamble_length, |
| 1317 | u32 __iomem *maccfg2_register) | 1297 | u32 __iomem *maccfg2_register) |
| 1318 | { | 1298 | { |
| 1319 | u32 value = 0; | ||
| 1320 | |||
| 1321 | if ((preamble_length < 3) || (preamble_length > 7)) | 1299 | if ((preamble_length < 3) || (preamble_length > 7)) |
| 1322 | return -EINVAL; | 1300 | return -EINVAL; |
| 1323 | 1301 | ||
| 1324 | value = in_be32(maccfg2_register); | 1302 | clrsetbits_be32(maccfg2_register, MACCFG2_PREL_MASK, |
| 1325 | value &= ~MACCFG2_PREL_MASK; | 1303 | preamble_length << MACCFG2_PREL_SHIFT); |
| 1326 | value |= (preamble_length << MACCFG2_PREL_SHIFT); | 1304 | |
| 1327 | out_be32(maccfg2_register, value); | ||
| 1328 | return 0; | 1305 | return 0; |
| 1329 | } | 1306 | } |
| 1330 | 1307 | ||
| @@ -1337,19 +1314,19 @@ static int init_rx_parameters(int reject_broadcast, | |||
| 1337 | value = in_be32(upsmr_register); | 1314 | value = in_be32(upsmr_register); |
| 1338 | 1315 | ||
| 1339 | if (reject_broadcast) | 1316 | if (reject_broadcast) |
| 1340 | value |= UPSMR_BRO; | 1317 | value |= UCC_GETH_UPSMR_BRO; |
| 1341 | else | 1318 | else |
| 1342 | value &= ~UPSMR_BRO; | 1319 | value &= ~UCC_GETH_UPSMR_BRO; |
| 1343 | 1320 | ||
| 1344 | if (receive_short_frames) | 1321 | if (receive_short_frames) |
| 1345 | value |= UPSMR_RSH; | 1322 | value |= UCC_GETH_UPSMR_RSH; |
| 1346 | else | 1323 | else |
| 1347 | value &= ~UPSMR_RSH; | 1324 | value &= ~UCC_GETH_UPSMR_RSH; |
| 1348 | 1325 | ||
| 1349 | if (promiscuous) | 1326 | if (promiscuous) |
| 1350 | value |= UPSMR_PRO; | 1327 | value |= UCC_GETH_UPSMR_PRO; |
| 1351 | else | 1328 | else |
| 1352 | value &= ~UPSMR_PRO; | 1329 | value &= ~UCC_GETH_UPSMR_PRO; |
| 1353 | 1330 | ||
| 1354 | out_be32(upsmr_register, value); | 1331 | out_be32(upsmr_register, value); |
| 1355 | 1332 | ||
| @@ -1410,26 +1387,27 @@ static int adjust_enet_interface(struct ucc_geth_private *ugeth) | |||
| 1410 | 1387 | ||
| 1411 | /* Set UPSMR */ | 1388 | /* Set UPSMR */ |
| 1412 | upsmr = in_be32(&uf_regs->upsmr); | 1389 | upsmr = in_be32(&uf_regs->upsmr); |
| 1413 | upsmr &= ~(UPSMR_RPM | UPSMR_R10M | UPSMR_TBIM | UPSMR_RMM); | 1390 | upsmr &= ~(UCC_GETH_UPSMR_RPM | UCC_GETH_UPSMR_R10M | |
| 1391 | UCC_GETH_UPSMR_TBIM | UCC_GETH_UPSMR_RMM); | ||
| 1414 | if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) || | 1392 | if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) || |
| 1415 | (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) || | 1393 | (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) || |
| 1416 | (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) || | 1394 | (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) || |
| 1417 | (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) || | 1395 | (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) || |
| 1418 | (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) || | 1396 | (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) || |
| 1419 | (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) { | 1397 | (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) { |
| 1420 | upsmr |= UPSMR_RPM; | 1398 | upsmr |= UCC_GETH_UPSMR_RPM; |
| 1421 | switch (ugeth->max_speed) { | 1399 | switch (ugeth->max_speed) { |
| 1422 | case SPEED_10: | 1400 | case SPEED_10: |
| 1423 | upsmr |= UPSMR_R10M; | 1401 | upsmr |= UCC_GETH_UPSMR_R10M; |
| 1424 | /* FALLTHROUGH */ | 1402 | /* FALLTHROUGH */ |
| 1425 | case SPEED_100: | 1403 | case SPEED_100: |
| 1426 | if (ugeth->phy_interface != PHY_INTERFACE_MODE_RTBI) | 1404 | if (ugeth->phy_interface != PHY_INTERFACE_MODE_RTBI) |
| 1427 | upsmr |= UPSMR_RMM; | 1405 | upsmr |= UCC_GETH_UPSMR_RMM; |
| 1428 | } | 1406 | } |
| 1429 | } | 1407 | } |
| 1430 | if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) || | 1408 | if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) || |
| 1431 | (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) { | 1409 | (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) { |
| 1432 | upsmr |= UPSMR_TBIM; | 1410 | upsmr |= UCC_GETH_UPSMR_TBIM; |
| 1433 | } | 1411 | } |
| 1434 | out_be32(&uf_regs->upsmr, upsmr); | 1412 | out_be32(&uf_regs->upsmr, upsmr); |
| 1435 | 1413 | ||
| @@ -1517,9 +1495,9 @@ static void adjust_link(struct net_device *dev) | |||
| 1517 | (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) || | 1495 | (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) || |
| 1518 | (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) { | 1496 | (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) { |
| 1519 | if (phydev->speed == SPEED_10) | 1497 | if (phydev->speed == SPEED_10) |
| 1520 | upsmr |= UPSMR_R10M; | 1498 | upsmr |= UCC_GETH_UPSMR_R10M; |
| 1521 | else | 1499 | else |
| 1522 | upsmr &= ~(UPSMR_R10M); | 1500 | upsmr &= ~UCC_GETH_UPSMR_R10M; |
| 1523 | } | 1501 | } |
| 1524 | break; | 1502 | break; |
| 1525 | default: | 1503 | default: |
| @@ -1602,10 +1580,8 @@ static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth) | |||
| 1602 | uccf = ugeth->uccf; | 1580 | uccf = ugeth->uccf; |
| 1603 | 1581 | ||
| 1604 | /* Mask GRACEFUL STOP TX interrupt bit and clear it */ | 1582 | /* Mask GRACEFUL STOP TX interrupt bit and clear it */ |
| 1605 | temp = in_be32(uccf->p_uccm); | 1583 | clrbits32(uccf->p_uccm, UCC_GETH_UCCE_GRA); |
| 1606 | temp &= ~UCCE_GRA; | 1584 | out_be32(uccf->p_ucce, UCC_GETH_UCCE_GRA); /* clear by writing 1 */ |
| 1607 | out_be32(uccf->p_uccm, temp); | ||
| 1608 | out_be32(uccf->p_ucce, UCCE_GRA); /* clear by writing 1 */ | ||
| 1609 | 1585 | ||
| 1610 | /* Issue host command */ | 1586 | /* Issue host command */ |
| 1611 | cecr_subblock = | 1587 | cecr_subblock = |
| @@ -1617,7 +1593,7 @@ static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth) | |||
| 1617 | do { | 1593 | do { |
| 1618 | msleep(10); | 1594 | msleep(10); |
| 1619 | temp = in_be32(uccf->p_ucce); | 1595 | temp = in_be32(uccf->p_ucce); |
| 1620 | } while (!(temp & UCCE_GRA) && --i); | 1596 | } while (!(temp & UCC_GETH_UCCE_GRA) && --i); |
| 1621 | 1597 | ||
| 1622 | uccf->stopped_tx = 1; | 1598 | uccf->stopped_tx = 1; |
| 1623 | 1599 | ||
| @@ -1975,12 +1951,9 @@ static void ucc_geth_set_multi(struct net_device *dev) | |||
| 1975 | uf_regs = ugeth->uccf->uf_regs; | 1951 | uf_regs = ugeth->uccf->uf_regs; |
| 1976 | 1952 | ||
| 1977 | if (dev->flags & IFF_PROMISC) { | 1953 | if (dev->flags & IFF_PROMISC) { |
| 1978 | 1954 | setbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO); | |
| 1979 | out_be32(&uf_regs->upsmr, in_be32(&uf_regs->upsmr) | UPSMR_PRO); | ||
| 1980 | |||
| 1981 | } else { | 1955 | } else { |
| 1982 | 1956 | clrbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO); | |
| 1983 | out_be32(&uf_regs->upsmr, in_be32(&uf_regs->upsmr)&~UPSMR_PRO); | ||
| 1984 | 1957 | ||
| 1985 | p_82xx_addr_filt = | 1958 | p_82xx_addr_filt = |
| 1986 | (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth-> | 1959 | (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth-> |
| @@ -2020,7 +1993,6 @@ static void ucc_geth_stop(struct ucc_geth_private *ugeth) | |||
| 2020 | { | 1993 | { |
| 2021 | struct ucc_geth __iomem *ug_regs = ugeth->ug_regs; | 1994 | struct ucc_geth __iomem *ug_regs = ugeth->ug_regs; |
| 2022 | struct phy_device *phydev = ugeth->phydev; | 1995 | struct phy_device *phydev = ugeth->phydev; |
| 2023 | u32 tempval; | ||
| 2024 | 1996 | ||
| 2025 | ugeth_vdbg("%s: IN", __func__); | 1997 | ugeth_vdbg("%s: IN", __func__); |
| 2026 | 1998 | ||
| @@ -2037,9 +2009,7 @@ static void ucc_geth_stop(struct ucc_geth_private *ugeth) | |||
| 2037 | out_be32(ugeth->uccf->p_ucce, 0xffffffff); | 2009 | out_be32(ugeth->uccf->p_ucce, 0xffffffff); |
| 2038 | 2010 | ||
| 2039 | /* Disable Rx and Tx */ | 2011 | /* Disable Rx and Tx */ |
| 2040 | tempval = in_be32(&ug_regs->maccfg1); | 2012 | clrbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX); |
| 2041 | tempval &= ~(MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX); | ||
| 2042 | out_be32(&ug_regs->maccfg1, tempval); | ||
| 2043 | 2013 | ||
| 2044 | ucc_geth_memclean(ugeth); | 2014 | ucc_geth_memclean(ugeth); |
| 2045 | } | 2015 | } |
| @@ -2153,10 +2123,10 @@ static int ucc_struct_init(struct ucc_geth_private *ugeth) | |||
| 2153 | /* Generate uccm_mask for receive */ | 2123 | /* Generate uccm_mask for receive */ |
| 2154 | uf_info->uccm_mask = ug_info->eventRegMask & UCCE_OTHER;/* Errors */ | 2124 | uf_info->uccm_mask = ug_info->eventRegMask & UCCE_OTHER;/* Errors */ |
| 2155 | for (i = 0; i < ug_info->numQueuesRx; i++) | 2125 | for (i = 0; i < ug_info->numQueuesRx; i++) |
| 2156 | uf_info->uccm_mask |= (UCCE_RXBF_SINGLE_MASK << i); | 2126 | uf_info->uccm_mask |= (UCC_GETH_UCCE_RXF0 << i); |
| 2157 | 2127 | ||
| 2158 | for (i = 0; i < ug_info->numQueuesTx; i++) | 2128 | for (i = 0; i < ug_info->numQueuesTx; i++) |
| 2159 | uf_info->uccm_mask |= (UCCE_TXBF_SINGLE_MASK << i); | 2129 | uf_info->uccm_mask |= (UCC_GETH_UCCE_TXB0 << i); |
| 2160 | /* Initialize the general fast UCC block. */ | 2130 | /* Initialize the general fast UCC block. */ |
| 2161 | if (ucc_fast_init(uf_info, &ugeth->uccf)) { | 2131 | if (ucc_fast_init(uf_info, &ugeth->uccf)) { |
| 2162 | if (netif_msg_probe(ugeth)) | 2132 | if (netif_msg_probe(ugeth)) |
| @@ -2185,7 +2155,7 @@ static int ucc_geth_startup(struct ucc_geth_private *ugeth) | |||
| 2185 | struct ucc_geth __iomem *ug_regs; | 2155 | struct ucc_geth __iomem *ug_regs; |
| 2186 | int ret_val = -EINVAL; | 2156 | int ret_val = -EINVAL; |
| 2187 | u32 remoder = UCC_GETH_REMODER_INIT; | 2157 | u32 remoder = UCC_GETH_REMODER_INIT; |
| 2188 | u32 init_enet_pram_offset, cecr_subblock, command, maccfg1; | 2158 | u32 init_enet_pram_offset, cecr_subblock, command; |
| 2189 | u32 ifstat, i, j, size, l2qt, l3qt, length; | 2159 | u32 ifstat, i, j, size, l2qt, l3qt, length; |
| 2190 | u16 temoder = UCC_GETH_TEMODER_INIT; | 2160 | u16 temoder = UCC_GETH_TEMODER_INIT; |
| 2191 | u16 test; | 2161 | u16 test; |
| @@ -2281,10 +2251,7 @@ static int ucc_geth_startup(struct ucc_geth_private *ugeth) | |||
| 2281 | &uf_regs->upsmr, | 2251 | &uf_regs->upsmr, |
| 2282 | &ug_regs->uempr, &ug_regs->maccfg1); | 2252 | &ug_regs->uempr, &ug_regs->maccfg1); |
| 2283 | 2253 | ||
| 2284 | maccfg1 = in_be32(&ug_regs->maccfg1); | 2254 | setbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX); |
| 2285 | maccfg1 |= MACCFG1_ENABLE_RX; | ||
| 2286 | maccfg1 |= MACCFG1_ENABLE_TX; | ||
| 2287 | out_be32(&ug_regs->maccfg1, maccfg1); | ||
| 2288 | 2255 | ||
| 2289 | /* Set IPGIFG */ | 2256 | /* Set IPGIFG */ |
| 2290 | /* For more details see the hardware spec. */ | 2257 | /* For more details see the hardware spec. */ |
| @@ -3274,7 +3241,6 @@ static int ucc_geth_tx(struct net_device *dev, u8 txQ) | |||
| 3274 | static int ucc_geth_poll(struct napi_struct *napi, int budget) | 3241 | static int ucc_geth_poll(struct napi_struct *napi, int budget) |
| 3275 | { | 3242 | { |
| 3276 | struct ucc_geth_private *ugeth = container_of(napi, struct ucc_geth_private, napi); | 3243 | struct ucc_geth_private *ugeth = container_of(napi, struct ucc_geth_private, napi); |
| 3277 | struct net_device *dev = ugeth->dev; | ||
| 3278 | struct ucc_geth_info *ug_info; | 3244 | struct ucc_geth_info *ug_info; |
| 3279 | int howmany, i; | 3245 | int howmany, i; |
| 3280 | 3246 | ||
| @@ -3285,14 +3251,8 @@ static int ucc_geth_poll(struct napi_struct *napi, int budget) | |||
| 3285 | howmany += ucc_geth_rx(ugeth, i, budget - howmany); | 3251 | howmany += ucc_geth_rx(ugeth, i, budget - howmany); |
| 3286 | 3252 | ||
| 3287 | if (howmany < budget) { | 3253 | if (howmany < budget) { |
| 3288 | struct ucc_fast_private *uccf; | ||
| 3289 | u32 uccm; | ||
| 3290 | |||
| 3291 | netif_rx_complete(napi); | 3254 | netif_rx_complete(napi); |
| 3292 | uccf = ugeth->uccf; | 3255 | setbits32(ugeth->uccf->p_uccm, UCCE_RX_EVENTS); |
| 3293 | uccm = in_be32(uccf->p_uccm); | ||
| 3294 | uccm |= UCCE_RX_EVENTS; | ||
| 3295 | out_be32(uccf->p_uccm, uccm); | ||
| 3296 | } | 3256 | } |
| 3297 | 3257 | ||
| 3298 | return howmany; | 3258 | return howmany; |
| @@ -3332,7 +3292,7 @@ static irqreturn_t ucc_geth_irq_handler(int irq, void *info) | |||
| 3332 | /* Tx event processing */ | 3292 | /* Tx event processing */ |
| 3333 | if (ucce & UCCE_TX_EVENTS) { | 3293 | if (ucce & UCCE_TX_EVENTS) { |
| 3334 | spin_lock(&ugeth->lock); | 3294 | spin_lock(&ugeth->lock); |
| 3335 | tx_mask = UCCE_TXBF_SINGLE_MASK; | 3295 | tx_mask = UCC_GETH_UCCE_TXB0; |
| 3336 | for (i = 0; i < ug_info->numQueuesTx; i++) { | 3296 | for (i = 0; i < ug_info->numQueuesTx; i++) { |
| 3337 | if (ucce & tx_mask) | 3297 | if (ucce & tx_mask) |
| 3338 | ucc_geth_tx(dev, i); | 3298 | ucc_geth_tx(dev, i); |
| @@ -3344,12 +3304,10 @@ static irqreturn_t ucc_geth_irq_handler(int irq, void *info) | |||
| 3344 | 3304 | ||
| 3345 | /* Errors and other events */ | 3305 | /* Errors and other events */ |
| 3346 | if (ucce & UCCE_OTHER) { | 3306 | if (ucce & UCCE_OTHER) { |
| 3347 | if (ucce & UCCE_BSY) { | 3307 | if (ucce & UCC_GETH_UCCE_BSY) |
| 3348 | dev->stats.rx_errors++; | 3308 | dev->stats.rx_errors++; |
| 3349 | } | 3309 | if (ucce & UCC_GETH_UCCE_TXE) |
| 3350 | if (ucce & UCCE_TXE) { | ||
| 3351 | dev->stats.tx_errors++; | 3310 | dev->stats.tx_errors++; |
| 3352 | } | ||
| 3353 | } | 3311 | } |
| 3354 | 3312 | ||
| 3355 | return IRQ_HANDLED; | 3313 | return IRQ_HANDLED; |
diff --git a/drivers/net/ucc_geth.h b/drivers/net/ucc_geth.h index d74d2f7cb739..8f699cb773ee 100644 --- a/drivers/net/ucc_geth.h +++ b/drivers/net/ucc_geth.h | |||
| @@ -162,92 +162,27 @@ struct ucc_geth { | |||
| 162 | boundary */ | 162 | boundary */ |
| 163 | 163 | ||
| 164 | /* UCC GETH Event Register */ | 164 | /* UCC GETH Event Register */ |
| 165 | #define UCCE_MPD 0x80000000 /* Magic packet | 165 | #define UCCE_TXB (UCC_GETH_UCCE_TXB7 | UCC_GETH_UCCE_TXB6 | \ |
| 166 | detection */ | 166 | UCC_GETH_UCCE_TXB5 | UCC_GETH_UCCE_TXB4 | \ |
| 167 | #define UCCE_SCAR 0x40000000 | 167 | UCC_GETH_UCCE_TXB3 | UCC_GETH_UCCE_TXB2 | \ |
| 168 | #define UCCE_GRA 0x20000000 /* Tx graceful | 168 | UCC_GETH_UCCE_TXB1 | UCC_GETH_UCCE_TXB0) |
| 169 | stop | 169 | |
| 170 | complete */ | 170 | #define UCCE_RXB (UCC_GETH_UCCE_RXB7 | UCC_GETH_UCCE_RXB6 | \ |
| 171 | #define UCCE_CBPR 0x10000000 | 171 | UCC_GETH_UCCE_RXB5 | UCC_GETH_UCCE_RXB4 | \ |
| 172 | #define UCCE_BSY 0x08000000 | 172 | UCC_GETH_UCCE_RXB3 | UCC_GETH_UCCE_RXB2 | \ |
| 173 | #define UCCE_RXC 0x04000000 | 173 | UCC_GETH_UCCE_RXB1 | UCC_GETH_UCCE_RXB0) |
| 174 | #define UCCE_TXC 0x02000000 | 174 | |
| 175 | #define UCCE_TXE 0x01000000 | 175 | #define UCCE_RXF (UCC_GETH_UCCE_RXF7 | UCC_GETH_UCCE_RXF6 | \ |
| 176 | #define UCCE_TXB7 0x00800000 | 176 | UCC_GETH_UCCE_RXF5 | UCC_GETH_UCCE_RXF4 | \ |
| 177 | #define UCCE_TXB6 0x00400000 | 177 | UCC_GETH_UCCE_RXF3 | UCC_GETH_UCCE_RXF2 | \ |
| 178 | #define UCCE_TXB5 0x00200000 | 178 | UCC_GETH_UCCE_RXF1 | UCC_GETH_UCCE_RXF0) |
| 179 | #define UCCE_TXB4 0x00100000 | 179 | |
| 180 | #define UCCE_TXB3 0x00080000 | 180 | #define UCCE_OTHER (UCC_GETH_UCCE_SCAR | UCC_GETH_UCCE_GRA | \ |
| 181 | #define UCCE_TXB2 0x00040000 | 181 | UCC_GETH_UCCE_CBPR | UCC_GETH_UCCE_BSY | \ |
| 182 | #define UCCE_TXB1 0x00020000 | 182 | UCC_GETH_UCCE_RXC | UCC_GETH_UCCE_TXC | UCC_GETH_UCCE_TXE) |
| 183 | #define UCCE_TXB0 0x00010000 | 183 | |
| 184 | #define UCCE_RXB7 0x00008000 | 184 | #define UCCE_RX_EVENTS (UCCE_RXF | UCC_GETH_UCCE_BSY) |
| 185 | #define UCCE_RXB6 0x00004000 | 185 | #define UCCE_TX_EVENTS (UCCE_TXB | UCC_GETH_UCCE_TXE) |
| 186 | #define UCCE_RXB5 0x00002000 | ||
| 187 | #define UCCE_RXB4 0x00001000 | ||
| 188 | #define UCCE_RXB3 0x00000800 | ||
| 189 | #define UCCE_RXB2 0x00000400 | ||
| 190 | #define UCCE_RXB1 0x00000200 | ||
| 191 | #define UCCE_RXB0 0x00000100 | ||
| 192 | #define UCCE_RXF7 0x00000080 | ||
| 193 | #define UCCE_RXF6 0x00000040 | ||
| 194 | #define UCCE_RXF5 0x00000020 | ||
| 195 | #define UCCE_RXF4 0x00000010 | ||
| 196 | #define UCCE_RXF3 0x00000008 | ||
| 197 | #define UCCE_RXF2 0x00000004 | ||
| 198 | #define UCCE_RXF1 0x00000002 | ||
| 199 | #define UCCE_RXF0 0x00000001 | ||
| 200 | |||
| 201 | #define UCCE_RXBF_SINGLE_MASK (UCCE_RXF0) | ||
| 202 | #define UCCE_TXBF_SINGLE_MASK (UCCE_TXB0) | ||
| 203 | |||
| 204 | #define UCCE_TXB (UCCE_TXB7 | UCCE_TXB6 | UCCE_TXB5 | UCCE_TXB4 |\ | ||
| 205 | UCCE_TXB3 | UCCE_TXB2 | UCCE_TXB1 | UCCE_TXB0) | ||
| 206 | #define UCCE_RXB (UCCE_RXB7 | UCCE_RXB6 | UCCE_RXB5 | UCCE_RXB4 |\ | ||
| 207 | UCCE_RXB3 | UCCE_RXB2 | UCCE_RXB1 | UCCE_RXB0) | ||
| 208 | #define UCCE_RXF (UCCE_RXF7 | UCCE_RXF6 | UCCE_RXF5 | UCCE_RXF4 |\ | ||
| 209 | UCCE_RXF3 | UCCE_RXF2 | UCCE_RXF1 | UCCE_RXF0) | ||
| 210 | #define UCCE_OTHER (UCCE_SCAR | UCCE_GRA | UCCE_CBPR | UCCE_BSY |\ | ||
| 211 | UCCE_RXC | UCCE_TXC | UCCE_TXE) | ||
| 212 | |||
| 213 | #define UCCE_RX_EVENTS (UCCE_RXF | UCCE_BSY) | ||
| 214 | #define UCCE_TX_EVENTS (UCCE_TXB | UCCE_TXE) | ||
| 215 | |||
| 216 | /* UCC GETH UPSMR (Protocol Specific Mode Register) */ | ||
| 217 | #define UPSMR_ECM 0x04000000 /* Enable CAM | ||
| 218 | Miss or | ||
| 219 | Enable | ||
| 220 | Filtering | ||
| 221 | Miss */ | ||
| 222 | #define UPSMR_HSE 0x02000000 /* Hardware | ||
| 223 | Statistics | ||
| 224 | Enable */ | ||
| 225 | #define UPSMR_PRO 0x00400000 /* Promiscuous*/ | ||
| 226 | #define UPSMR_CAP 0x00200000 /* CAM polarity | ||
| 227 | */ | ||
| 228 | #define UPSMR_RSH 0x00100000 /* Receive | ||
| 229 | Short Frames | ||
| 230 | */ | ||
| 231 | #define UPSMR_RPM 0x00080000 /* Reduced Pin | ||
| 232 | Mode | ||
| 233 | interfaces */ | ||
| 234 | #define UPSMR_R10M 0x00040000 /* RGMII/RMII | ||
| 235 | 10 Mode */ | ||
| 236 | #define UPSMR_RLPB 0x00020000 /* RMII | ||
| 237 | Loopback | ||
| 238 | Mode */ | ||
| 239 | #define UPSMR_TBIM 0x00010000 /* Ten-bit | ||
| 240 | Interface | ||
| 241 | Mode */ | ||
| 242 | #define UPSMR_RMM 0x00001000 /* RMII/RGMII | ||
| 243 | Mode */ | ||
| 244 | #define UPSMR_CAM 0x00000400 /* CAM Address | ||
| 245 | Matching */ | ||
| 246 | #define UPSMR_BRO 0x00000200 /* Broadcast | ||
| 247 | Address */ | ||
| 248 | #define UPSMR_RES1 0x00002000 /* Reserved | ||
| 249 | feild - must | ||
| 250 | be 1 */ | ||
| 251 | 186 | ||
| 252 | /* UCC GETH MACCFG1 (MAC Configuration 1 Register) */ | 187 | /* UCC GETH MACCFG1 (MAC Configuration 1 Register) */ |
| 253 | #define MACCFG1_FLOW_RX 0x00000020 /* Flow Control | 188 | #define MACCFG1_FLOW_RX 0x00000020 /* Flow Control |
| @@ -945,9 +880,10 @@ struct ucc_geth_hardware_statistics { | |||
| 945 | #define UCC_GETH_REMODER_INIT 0 /* bits that must be | 880 | #define UCC_GETH_REMODER_INIT 0 /* bits that must be |
| 946 | set */ | 881 | set */ |
| 947 | #define UCC_GETH_TEMODER_INIT 0xC000 /* bits that must */ | 882 | #define UCC_GETH_TEMODER_INIT 0xC000 /* bits that must */ |
| 948 | #define UCC_GETH_UPSMR_INIT (UPSMR_RES1) /* Start value | 883 | |
| 949 | for this | 884 | /* Initial value for UPSMR */ |
| 950 | register */ | 885 | #define UCC_GETH_UPSMR_INIT UCC_GETH_UPSMR_RES1 |
| 886 | |||
| 951 | #define UCC_GETH_MACCFG1_INIT 0 | 887 | #define UCC_GETH_MACCFG1_INIT 0 |
| 952 | #define UCC_GETH_MACCFG2_INIT (MACCFG2_RESERVED_1) | 888 | #define UCC_GETH_MACCFG2_INIT (MACCFG2_RESERVED_1) |
| 953 | 889 | ||
diff --git a/drivers/net/via-rhine.c b/drivers/net/via-rhine.c index ac07cc6e3cb2..3b8e63254277 100644 --- a/drivers/net/via-rhine.c +++ b/drivers/net/via-rhine.c | |||
| @@ -622,6 +622,7 @@ static const struct net_device_ops rhine_netdev_ops = { | |||
| 622 | .ndo_get_stats = rhine_get_stats, | 622 | .ndo_get_stats = rhine_get_stats, |
| 623 | .ndo_set_multicast_list = rhine_set_rx_mode, | 623 | .ndo_set_multicast_list = rhine_set_rx_mode, |
| 624 | .ndo_validate_addr = eth_validate_addr, | 624 | .ndo_validate_addr = eth_validate_addr, |
| 625 | .ndo_set_mac_address = eth_mac_addr, | ||
| 625 | .ndo_do_ioctl = netdev_ioctl, | 626 | .ndo_do_ioctl = netdev_ioctl, |
| 626 | .ndo_tx_timeout = rhine_tx_timeout, | 627 | .ndo_tx_timeout = rhine_tx_timeout, |
| 627 | #ifdef CONFIG_NET_POLL_CONTROLLER | 628 | #ifdef CONFIG_NET_POLL_CONTROLLER |
diff --git a/drivers/net/via-velocity.c b/drivers/net/via-velocity.c index 58e25d090ae0..a75f91dc3153 100644 --- a/drivers/net/via-velocity.c +++ b/drivers/net/via-velocity.c | |||
| @@ -855,6 +855,7 @@ static const struct net_device_ops velocity_netdev_ops = { | |||
| 855 | .ndo_start_xmit = velocity_xmit, | 855 | .ndo_start_xmit = velocity_xmit, |
| 856 | .ndo_get_stats = velocity_get_stats, | 856 | .ndo_get_stats = velocity_get_stats, |
| 857 | .ndo_validate_addr = eth_validate_addr, | 857 | .ndo_validate_addr = eth_validate_addr, |
| 858 | .ndo_set_mac_address = eth_mac_addr, | ||
| 858 | .ndo_set_multicast_list = velocity_set_multi, | 859 | .ndo_set_multicast_list = velocity_set_multi, |
| 859 | .ndo_change_mtu = velocity_change_mtu, | 860 | .ndo_change_mtu = velocity_change_mtu, |
| 860 | .ndo_do_ioctl = velocity_ioctl, | 861 | .ndo_do_ioctl = velocity_ioctl, |
diff --git a/drivers/net/wd.c b/drivers/net/wd.c index 3c1edda08d3d..d8322d2d1e29 100644 --- a/drivers/net/wd.c +++ b/drivers/net/wd.c | |||
| @@ -155,6 +155,7 @@ static const struct net_device_ops wd_netdev_ops = { | |||
| 155 | .ndo_get_stats = ei_get_stats, | 155 | .ndo_get_stats = ei_get_stats, |
| 156 | .ndo_set_multicast_list = ei_set_multicast_list, | 156 | .ndo_set_multicast_list = ei_set_multicast_list, |
| 157 | .ndo_validate_addr = eth_validate_addr, | 157 | .ndo_validate_addr = eth_validate_addr, |
| 158 | .ndo_set_mac_address = eth_mac_addr, | ||
| 158 | .ndo_change_mtu = eth_change_mtu, | 159 | .ndo_change_mtu = eth_change_mtu, |
| 159 | #ifdef CONFIG_NET_POLL_CONTROLLER | 160 | #ifdef CONFIG_NET_POLL_CONTROLLER |
| 160 | .ndo_poll_controller = ei_poll, | 161 | .ndo_poll_controller = ei_poll, |
diff --git a/drivers/net/wireless/libertas/main.c b/drivers/net/wireless/libertas/main.c index 3dba83679444..4e0007d20030 100644 --- a/drivers/net/wireless/libertas/main.c +++ b/drivers/net/wireless/libertas/main.c | |||
| @@ -1369,7 +1369,7 @@ EXPORT_SYMBOL_GPL(lbs_start_card); | |||
| 1369 | 1369 | ||
| 1370 | void lbs_stop_card(struct lbs_private *priv) | 1370 | void lbs_stop_card(struct lbs_private *priv) |
| 1371 | { | 1371 | { |
| 1372 | struct net_device *dev = priv->dev; | 1372 | struct net_device *dev; |
| 1373 | struct cmd_ctrl_node *cmdnode; | 1373 | struct cmd_ctrl_node *cmdnode; |
| 1374 | unsigned long flags; | 1374 | unsigned long flags; |
| 1375 | 1375 | ||
| @@ -1377,9 +1377,10 @@ void lbs_stop_card(struct lbs_private *priv) | |||
| 1377 | 1377 | ||
| 1378 | if (!priv) | 1378 | if (!priv) |
| 1379 | goto out; | 1379 | goto out; |
| 1380 | dev = priv->dev; | ||
| 1380 | 1381 | ||
| 1381 | netif_stop_queue(priv->dev); | 1382 | netif_stop_queue(dev); |
| 1382 | netif_carrier_off(priv->dev); | 1383 | netif_carrier_off(dev); |
| 1383 | 1384 | ||
| 1384 | lbs_debugfs_remove_one(priv); | 1385 | lbs_debugfs_remove_one(priv); |
| 1385 | if (priv->mesh_tlv) { | 1386 | if (priv->mesh_tlv) { |
diff --git a/drivers/net/yellowfin.c b/drivers/net/yellowfin.c index cf9712922778..2f1645dcb8c8 100644 --- a/drivers/net/yellowfin.c +++ b/drivers/net/yellowfin.c | |||
| @@ -362,6 +362,7 @@ static const struct net_device_ops netdev_ops = { | |||
| 362 | .ndo_set_multicast_list = set_rx_mode, | 362 | .ndo_set_multicast_list = set_rx_mode, |
| 363 | .ndo_change_mtu = eth_change_mtu, | 363 | .ndo_change_mtu = eth_change_mtu, |
| 364 | .ndo_validate_addr = eth_validate_addr, | 364 | .ndo_validate_addr = eth_validate_addr, |
| 365 | .ndo_set_mac_address = eth_mac_addr, | ||
| 365 | .ndo_do_ioctl = netdev_ioctl, | 366 | .ndo_do_ioctl = netdev_ioctl, |
| 366 | .ndo_tx_timeout = yellowfin_tx_timeout, | 367 | .ndo_tx_timeout = yellowfin_tx_timeout, |
| 367 | }; | 368 | }; |
diff --git a/drivers/net/zorro8390.c b/drivers/net/zorro8390.c index affd904deafc..37c84e3b8be0 100644 --- a/drivers/net/zorro8390.c +++ b/drivers/net/zorro8390.c | |||
| @@ -147,6 +147,7 @@ static const struct net_device_ops zorro8390_netdev_ops = { | |||
| 147 | .ndo_get_stats = ei_get_stats, | 147 | .ndo_get_stats = ei_get_stats, |
| 148 | .ndo_set_multicast_list = ei_set_multicast_list, | 148 | .ndo_set_multicast_list = ei_set_multicast_list, |
| 149 | .ndo_validate_addr = eth_validate_addr, | 149 | .ndo_validate_addr = eth_validate_addr, |
| 150 | .ndo_set_mac_address = eth_mac_addr, | ||
| 150 | .ndo_change_mtu = eth_change_mtu, | 151 | .ndo_change_mtu = eth_change_mtu, |
| 151 | #ifdef CONFIG_NET_POLL_CONTROLLER | 152 | #ifdef CONFIG_NET_POLL_CONTROLLER |
| 152 | .ndo_poll_controller = ei_poll, | 153 | .ndo_poll_controller = ei_poll, |
diff --git a/drivers/pci/intel-iommu.c b/drivers/pci/intel-iommu.c index 235fb7a5a8a5..3dfecb20d5e7 100644 --- a/drivers/pci/intel-iommu.c +++ b/drivers/pci/intel-iommu.c | |||
| @@ -438,7 +438,8 @@ static struct intel_iommu *device_to_iommu(u8 bus, u8 devfn) | |||
| 438 | continue; | 438 | continue; |
| 439 | 439 | ||
| 440 | for (i = 0; i < drhd->devices_cnt; i++) | 440 | for (i = 0; i < drhd->devices_cnt; i++) |
| 441 | if (drhd->devices[i]->bus->number == bus && | 441 | if (drhd->devices[i] && |
| 442 | drhd->devices[i]->bus->number == bus && | ||
| 442 | drhd->devices[i]->devfn == devfn) | 443 | drhd->devices[i]->devfn == devfn) |
| 443 | return drhd->iommu; | 444 | return drhd->iommu; |
| 444 | 445 | ||
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index 668472405a57..33da1127992a 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig | |||
| @@ -82,4 +82,10 @@ config BATTERY_DA9030 | |||
| 82 | Say Y here to enable support for batteries charger integrated into | 82 | Say Y here to enable support for batteries charger integrated into |
| 83 | DA9030 PMIC. | 83 | DA9030 PMIC. |
| 84 | 84 | ||
| 85 | config CHARGER_PCF50633 | ||
| 86 | tristate "NXP PCF50633 MBC" | ||
| 87 | depends on MFD_PCF50633 | ||
| 88 | help | ||
| 89 | Say Y to include support for NXP PCF50633 Main Battery Charger. | ||
| 90 | |||
| 85 | endif # POWER_SUPPLY | 91 | endif # POWER_SUPPLY |
diff --git a/drivers/power/Makefile b/drivers/power/Makefile index eebb15505a40..2fcf41d13e5c 100644 --- a/drivers/power/Makefile +++ b/drivers/power/Makefile | |||
| @@ -25,3 +25,4 @@ obj-$(CONFIG_BATTERY_TOSA) += tosa_battery.o | |||
| 25 | obj-$(CONFIG_BATTERY_WM97XX) += wm97xx_battery.o | 25 | obj-$(CONFIG_BATTERY_WM97XX) += wm97xx_battery.o |
| 26 | obj-$(CONFIG_BATTERY_BQ27x00) += bq27x00_battery.o | 26 | obj-$(CONFIG_BATTERY_BQ27x00) += bq27x00_battery.o |
| 27 | obj-$(CONFIG_BATTERY_DA9030) += da9030_battery.o | 27 | obj-$(CONFIG_BATTERY_DA9030) += da9030_battery.o |
| 28 | obj-$(CONFIG_CHARGER_PCF50633) += pcf50633-charger.o \ No newline at end of file | ||
diff --git a/drivers/power/pcf50633-charger.c b/drivers/power/pcf50633-charger.c new file mode 100644 index 000000000000..e988ec130fcd --- /dev/null +++ b/drivers/power/pcf50633-charger.c | |||
| @@ -0,0 +1,358 @@ | |||
| 1 | /* NXP PCF50633 Main Battery Charger Driver | ||
| 2 | * | ||
| 3 | * (C) 2006-2008 by Openmoko, Inc. | ||
| 4 | * Author: Balaji Rao <balajirrao@openmoko.org> | ||
| 5 | * All rights reserved. | ||
| 6 | * | ||
| 7 | * Broken down from monstrous PCF50633 driver mainly by | ||
| 8 | * Harald Welte, Andy Green and Werner Almesberger | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify it | ||
| 11 | * under the terms of the GNU General Public License as published by the | ||
| 12 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 13 | * option) any later version. | ||
| 14 | * | ||
| 15 | */ | ||
| 16 | |||
| 17 | #include <linux/kernel.h> | ||
| 18 | #include <linux/module.h> | ||
| 19 | #include <linux/init.h> | ||
| 20 | #include <linux/types.h> | ||
| 21 | #include <linux/device.h> | ||
| 22 | #include <linux/sysfs.h> | ||
| 23 | #include <linux/platform_device.h> | ||
| 24 | #include <linux/power_supply.h> | ||
| 25 | |||
| 26 | #include <linux/mfd/pcf50633/core.h> | ||
| 27 | #include <linux/mfd/pcf50633/mbc.h> | ||
| 28 | |||
| 29 | struct pcf50633_mbc { | ||
| 30 | struct pcf50633 *pcf; | ||
| 31 | |||
| 32 | int adapter_active; | ||
| 33 | int adapter_online; | ||
| 34 | int usb_active; | ||
| 35 | int usb_online; | ||
| 36 | |||
| 37 | struct power_supply usb; | ||
| 38 | struct power_supply adapter; | ||
| 39 | }; | ||
| 40 | |||
| 41 | int pcf50633_mbc_usb_curlim_set(struct pcf50633 *pcf, int ma) | ||
| 42 | { | ||
| 43 | struct pcf50633_mbc *mbc = platform_get_drvdata(pcf->mbc_pdev); | ||
| 44 | int ret = 0; | ||
| 45 | u8 bits; | ||
| 46 | |||
| 47 | if (ma >= 1000) | ||
| 48 | bits = PCF50633_MBCC7_USB_1000mA; | ||
| 49 | else if (ma >= 500) | ||
| 50 | bits = PCF50633_MBCC7_USB_500mA; | ||
| 51 | else if (ma >= 100) | ||
| 52 | bits = PCF50633_MBCC7_USB_100mA; | ||
| 53 | else | ||
| 54 | bits = PCF50633_MBCC7_USB_SUSPEND; | ||
| 55 | |||
| 56 | ret = pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_MBCC7, | ||
| 57 | PCF50633_MBCC7_USB_MASK, bits); | ||
| 58 | if (ret) | ||
| 59 | dev_err(pcf->dev, "error setting usb curlim to %d mA\n", ma); | ||
| 60 | else | ||
| 61 | dev_info(pcf->dev, "usb curlim to %d mA\n", ma); | ||
| 62 | |||
| 63 | power_supply_changed(&mbc->usb); | ||
| 64 | |||
| 65 | return ret; | ||
| 66 | } | ||
| 67 | EXPORT_SYMBOL_GPL(pcf50633_mbc_usb_curlim_set); | ||
| 68 | |||
| 69 | int pcf50633_mbc_get_status(struct pcf50633 *pcf) | ||
| 70 | { | ||
| 71 | struct pcf50633_mbc *mbc = platform_get_drvdata(pcf->mbc_pdev); | ||
| 72 | int status = 0; | ||
| 73 | |||
| 74 | if (mbc->usb_online) | ||
| 75 | status |= PCF50633_MBC_USB_ONLINE; | ||
| 76 | if (mbc->usb_active) | ||
| 77 | status |= PCF50633_MBC_USB_ACTIVE; | ||
| 78 | if (mbc->adapter_online) | ||
| 79 | status |= PCF50633_MBC_ADAPTER_ONLINE; | ||
| 80 | if (mbc->adapter_active) | ||
| 81 | status |= PCF50633_MBC_ADAPTER_ACTIVE; | ||
| 82 | |||
| 83 | return status; | ||
| 84 | } | ||
| 85 | EXPORT_SYMBOL_GPL(pcf50633_mbc_get_status); | ||
| 86 | |||
| 87 | void pcf50633_mbc_set_status(struct pcf50633 *pcf, int what, int status) | ||
| 88 | { | ||
| 89 | struct pcf50633_mbc *mbc = platform_get_drvdata(pcf->mbc_pdev); | ||
| 90 | |||
| 91 | if (what & PCF50633_MBC_USB_ONLINE) | ||
| 92 | mbc->usb_online = !!status; | ||
| 93 | if (what & PCF50633_MBC_USB_ACTIVE) | ||
| 94 | mbc->usb_active = !!status; | ||
| 95 | if (what & PCF50633_MBC_ADAPTER_ONLINE) | ||
| 96 | mbc->adapter_online = !!status; | ||
| 97 | if (what & PCF50633_MBC_ADAPTER_ACTIVE) | ||
| 98 | mbc->adapter_active = !!status; | ||
| 99 | } | ||
| 100 | EXPORT_SYMBOL_GPL(pcf50633_mbc_set_status); | ||
| 101 | |||
| 102 | static ssize_t | ||
| 103 | show_chgmode(struct device *dev, struct device_attribute *attr, char *buf) | ||
| 104 | { | ||
| 105 | struct pcf50633_mbc *mbc = dev_get_drvdata(dev); | ||
| 106 | |||
| 107 | u8 mbcs2 = pcf50633_reg_read(mbc->pcf, PCF50633_REG_MBCS2); | ||
| 108 | u8 chgmod = (mbcs2 & PCF50633_MBCS2_MBC_MASK); | ||
| 109 | |||
| 110 | return sprintf(buf, "%d\n", chgmod); | ||
| 111 | } | ||
| 112 | static DEVICE_ATTR(chgmode, S_IRUGO, show_chgmode, NULL); | ||
| 113 | |||
| 114 | static ssize_t | ||
| 115 | show_usblim(struct device *dev, struct device_attribute *attr, char *buf) | ||
| 116 | { | ||
| 117 | struct pcf50633_mbc *mbc = dev_get_drvdata(dev); | ||
| 118 | u8 usblim = pcf50633_reg_read(mbc->pcf, PCF50633_REG_MBCC7) & | ||
| 119 | PCF50633_MBCC7_USB_MASK; | ||
| 120 | unsigned int ma; | ||
| 121 | |||
| 122 | if (usblim == PCF50633_MBCC7_USB_1000mA) | ||
| 123 | ma = 1000; | ||
| 124 | else if (usblim == PCF50633_MBCC7_USB_500mA) | ||
| 125 | ma = 500; | ||
| 126 | else if (usblim == PCF50633_MBCC7_USB_100mA) | ||
| 127 | ma = 100; | ||
| 128 | else | ||
| 129 | ma = 0; | ||
| 130 | |||
| 131 | return sprintf(buf, "%u\n", ma); | ||
| 132 | } | ||
| 133 | |||
| 134 | static ssize_t set_usblim(struct device *dev, | ||
| 135 | struct device_attribute *attr, const char *buf, size_t count) | ||
| 136 | { | ||
| 137 | struct pcf50633_mbc *mbc = dev_get_drvdata(dev); | ||
| 138 | unsigned long ma; | ||
| 139 | int ret; | ||
| 140 | |||
| 141 | ret = strict_strtoul(buf, 10, &ma); | ||
| 142 | if (ret) | ||
| 143 | return -EINVAL; | ||
| 144 | |||
| 145 | pcf50633_mbc_usb_curlim_set(mbc->pcf, ma); | ||
| 146 | |||
| 147 | return count; | ||
| 148 | } | ||
| 149 | |||
| 150 | static DEVICE_ATTR(usb_curlim, S_IRUGO | S_IWUSR, show_usblim, set_usblim); | ||
| 151 | |||
| 152 | static struct attribute *pcf50633_mbc_sysfs_entries[] = { | ||
| 153 | &dev_attr_chgmode.attr, | ||
| 154 | &dev_attr_usb_curlim.attr, | ||
| 155 | NULL, | ||
| 156 | }; | ||
| 157 | |||
| 158 | static struct attribute_group mbc_attr_group = { | ||
| 159 | .name = NULL, /* put in device directory */ | ||
| 160 | .attrs = pcf50633_mbc_sysfs_entries, | ||
| 161 | }; | ||
| 162 | |||
| 163 | static void | ||
| 164 | pcf50633_mbc_irq_handler(int irq, void *data) | ||
| 165 | { | ||
| 166 | struct pcf50633_mbc *mbc = data; | ||
| 167 | |||
| 168 | /* USB */ | ||
| 169 | if (irq == PCF50633_IRQ_USBINS) { | ||
| 170 | mbc->usb_online = 1; | ||
| 171 | } else if (irq == PCF50633_IRQ_USBREM) { | ||
| 172 | mbc->usb_online = 0; | ||
| 173 | mbc->usb_active = 0; | ||
| 174 | pcf50633_mbc_usb_curlim_set(mbc->pcf, 0); | ||
| 175 | } | ||
| 176 | |||
| 177 | /* Adapter */ | ||
| 178 | if (irq == PCF50633_IRQ_ADPINS) { | ||
| 179 | mbc->adapter_online = 1; | ||
| 180 | mbc->adapter_active = 1; | ||
| 181 | } else if (irq == PCF50633_IRQ_ADPREM) { | ||
| 182 | mbc->adapter_online = 0; | ||
| 183 | mbc->adapter_active = 0; | ||
| 184 | } | ||
| 185 | |||
| 186 | if (irq == PCF50633_IRQ_BATFULL) { | ||
| 187 | mbc->usb_active = 0; | ||
| 188 | mbc->adapter_active = 0; | ||
| 189 | } | ||
| 190 | |||
| 191 | power_supply_changed(&mbc->usb); | ||
| 192 | power_supply_changed(&mbc->adapter); | ||
| 193 | |||
| 194 | if (mbc->pcf->pdata->mbc_event_callback) | ||
| 195 | mbc->pcf->pdata->mbc_event_callback(mbc->pcf, irq); | ||
| 196 | } | ||
| 197 | |||
| 198 | static int adapter_get_property(struct power_supply *psy, | ||
| 199 | enum power_supply_property psp, | ||
| 200 | union power_supply_propval *val) | ||
| 201 | { | ||
| 202 | struct pcf50633_mbc *mbc = container_of(psy, struct pcf50633_mbc, usb); | ||
| 203 | int ret = 0; | ||
| 204 | |||
| 205 | switch (psp) { | ||
| 206 | case POWER_SUPPLY_PROP_ONLINE: | ||
| 207 | val->intval = mbc->adapter_online; | ||
| 208 | break; | ||
| 209 | default: | ||
| 210 | ret = -EINVAL; | ||
| 211 | break; | ||
| 212 | } | ||
| 213 | return ret; | ||
| 214 | } | ||
| 215 | |||
| 216 | static int usb_get_property(struct power_supply *psy, | ||
| 217 | enum power_supply_property psp, | ||
| 218 | union power_supply_propval *val) | ||
| 219 | { | ||
| 220 | struct pcf50633_mbc *mbc = container_of(psy, struct pcf50633_mbc, usb); | ||
| 221 | int ret = 0; | ||
| 222 | |||
| 223 | switch (psp) { | ||
| 224 | case POWER_SUPPLY_PROP_ONLINE: | ||
| 225 | val->intval = mbc->usb_online; | ||
| 226 | break; | ||
| 227 | default: | ||
| 228 | ret = -EINVAL; | ||
| 229 | break; | ||
| 230 | } | ||
| 231 | return ret; | ||
| 232 | } | ||
| 233 | |||
| 234 | static enum power_supply_property power_props[] = { | ||
| 235 | POWER_SUPPLY_PROP_ONLINE, | ||
| 236 | }; | ||
| 237 | |||
| 238 | static const u8 mbc_irq_handlers[] = { | ||
| 239 | PCF50633_IRQ_ADPINS, | ||
| 240 | PCF50633_IRQ_ADPREM, | ||
| 241 | PCF50633_IRQ_USBINS, | ||
| 242 | PCF50633_IRQ_USBREM, | ||
| 243 | PCF50633_IRQ_BATFULL, | ||
| 244 | PCF50633_IRQ_CHGHALT, | ||
| 245 | PCF50633_IRQ_THLIMON, | ||
| 246 | PCF50633_IRQ_THLIMOFF, | ||
| 247 | PCF50633_IRQ_USBLIMON, | ||
| 248 | PCF50633_IRQ_USBLIMOFF, | ||
| 249 | PCF50633_IRQ_LOWSYS, | ||
| 250 | PCF50633_IRQ_LOWBAT, | ||
| 251 | }; | ||
| 252 | |||
| 253 | static int __devinit pcf50633_mbc_probe(struct platform_device *pdev) | ||
| 254 | { | ||
| 255 | struct pcf50633_mbc *mbc; | ||
| 256 | struct pcf50633_subdev_pdata *pdata = pdev->dev.platform_data; | ||
| 257 | int ret; | ||
| 258 | int i; | ||
| 259 | u8 mbcs1; | ||
| 260 | |||
| 261 | mbc = kzalloc(sizeof(*mbc), GFP_KERNEL); | ||
| 262 | if (!mbc) | ||
| 263 | return -ENOMEM; | ||
| 264 | |||
| 265 | platform_set_drvdata(pdev, mbc); | ||
| 266 | mbc->pcf = pdata->pcf; | ||
| 267 | |||
| 268 | /* Set up IRQ handlers */ | ||
| 269 | for (i = 0; i < ARRAY_SIZE(mbc_irq_handlers); i++) | ||
| 270 | pcf50633_register_irq(mbc->pcf, mbc_irq_handlers[i], | ||
| 271 | pcf50633_mbc_irq_handler, mbc); | ||
| 272 | |||
| 273 | /* Create power supplies */ | ||
| 274 | mbc->adapter.name = "adapter"; | ||
| 275 | mbc->adapter.type = POWER_SUPPLY_TYPE_MAINS; | ||
| 276 | mbc->adapter.properties = power_props; | ||
| 277 | mbc->adapter.num_properties = ARRAY_SIZE(power_props); | ||
| 278 | mbc->adapter.get_property = &adapter_get_property; | ||
| 279 | mbc->adapter.supplied_to = mbc->pcf->pdata->batteries; | ||
| 280 | mbc->adapter.num_supplicants = mbc->pcf->pdata->num_batteries; | ||
| 281 | |||
| 282 | mbc->usb.name = "usb"; | ||
| 283 | mbc->usb.type = POWER_SUPPLY_TYPE_USB; | ||
| 284 | mbc->usb.properties = power_props; | ||
| 285 | mbc->usb.num_properties = ARRAY_SIZE(power_props); | ||
| 286 | mbc->usb.get_property = usb_get_property; | ||
| 287 | mbc->usb.supplied_to = mbc->pcf->pdata->batteries; | ||
| 288 | mbc->usb.num_supplicants = mbc->pcf->pdata->num_batteries; | ||
| 289 | |||
| 290 | ret = power_supply_register(&pdev->dev, &mbc->adapter); | ||
| 291 | if (ret) { | ||
| 292 | dev_err(mbc->pcf->dev, "failed to register adapter\n"); | ||
| 293 | kfree(mbc); | ||
| 294 | return ret; | ||
| 295 | } | ||
| 296 | |||
| 297 | ret = power_supply_register(&pdev->dev, &mbc->usb); | ||
| 298 | if (ret) { | ||
| 299 | dev_err(mbc->pcf->dev, "failed to register usb\n"); | ||
| 300 | power_supply_unregister(&mbc->adapter); | ||
| 301 | kfree(mbc); | ||
| 302 | return ret; | ||
| 303 | } | ||
| 304 | |||
| 305 | ret = sysfs_create_group(&pdev->dev.kobj, &mbc_attr_group); | ||
| 306 | if (ret) | ||
| 307 | dev_err(mbc->pcf->dev, "failed to create sysfs entries\n"); | ||
| 308 | |||
| 309 | mbcs1 = pcf50633_reg_read(mbc->pcf, PCF50633_REG_MBCS1); | ||
| 310 | if (mbcs1 & PCF50633_MBCS1_USBPRES) | ||
| 311 | pcf50633_mbc_irq_handler(PCF50633_IRQ_USBINS, mbc); | ||
| 312 | if (mbcs1 & PCF50633_MBCS1_ADAPTPRES) | ||
| 313 | pcf50633_mbc_irq_handler(PCF50633_IRQ_ADPINS, mbc); | ||
| 314 | |||
| 315 | return 0; | ||
| 316 | } | ||
| 317 | |||
| 318 | static int __devexit pcf50633_mbc_remove(struct platform_device *pdev) | ||
| 319 | { | ||
| 320 | struct pcf50633_mbc *mbc = platform_get_drvdata(pdev); | ||
| 321 | int i; | ||
| 322 | |||
| 323 | /* Remove IRQ handlers */ | ||
| 324 | for (i = 0; i < ARRAY_SIZE(mbc_irq_handlers); i++) | ||
| 325 | pcf50633_free_irq(mbc->pcf, mbc_irq_handlers[i]); | ||
| 326 | |||
| 327 | power_supply_unregister(&mbc->usb); | ||
| 328 | power_supply_unregister(&mbc->adapter); | ||
| 329 | |||
| 330 | kfree(mbc); | ||
| 331 | |||
| 332 | return 0; | ||
| 333 | } | ||
| 334 | |||
| 335 | static struct platform_driver pcf50633_mbc_driver = { | ||
| 336 | .driver = { | ||
| 337 | .name = "pcf50633-mbc", | ||
| 338 | }, | ||
| 339 | .probe = pcf50633_mbc_probe, | ||
| 340 | .remove = __devexit_p(pcf50633_mbc_remove), | ||
| 341 | }; | ||
| 342 | |||
| 343 | static int __init pcf50633_mbc_init(void) | ||
| 344 | { | ||
| 345 | return platform_driver_register(&pcf50633_mbc_driver); | ||
| 346 | } | ||
| 347 | module_init(pcf50633_mbc_init); | ||
| 348 | |||
| 349 | static void __exit pcf50633_mbc_exit(void) | ||
| 350 | { | ||
| 351 | platform_driver_unregister(&pcf50633_mbc_driver); | ||
| 352 | } | ||
| 353 | module_exit(pcf50633_mbc_exit); | ||
| 354 | |||
| 355 | MODULE_AUTHOR("Balaji Rao <balajirrao@openmoko.org>"); | ||
| 356 | MODULE_DESCRIPTION("PCF50633 mbc driver"); | ||
| 357 | MODULE_LICENSE("GPL"); | ||
| 358 | MODULE_ALIAS("platform:pcf50633-mbc"); | ||
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig index 39360e2a4540..e7e0cf102d6d 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig | |||
| @@ -73,4 +73,11 @@ config REGULATOR_DA903X | |||
| 73 | Say y here to support the BUCKs and LDOs regulators found on | 73 | Say y here to support the BUCKs and LDOs regulators found on |
| 74 | Dialog Semiconductor DA9030/DA9034 PMIC. | 74 | Dialog Semiconductor DA9030/DA9034 PMIC. |
| 75 | 75 | ||
| 76 | config REGULATOR_PCF50633 | ||
| 77 | tristate "PCF50633 regulator driver" | ||
| 78 | depends on MFD_PCF50633 | ||
| 79 | help | ||
| 80 | Say Y here to support the voltage regulators and convertors | ||
| 81 | on PCF50633 | ||
| 82 | |||
| 76 | endif | 83 | endif |
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile index 254d40c02ee8..61b30c6ddecc 100644 --- a/drivers/regulator/Makefile +++ b/drivers/regulator/Makefile | |||
| @@ -11,5 +11,6 @@ obj-$(CONFIG_REGULATOR_BQ24022) += bq24022.o | |||
| 11 | obj-$(CONFIG_REGULATOR_WM8350) += wm8350-regulator.o | 11 | obj-$(CONFIG_REGULATOR_WM8350) += wm8350-regulator.o |
| 12 | obj-$(CONFIG_REGULATOR_WM8400) += wm8400-regulator.o | 12 | obj-$(CONFIG_REGULATOR_WM8400) += wm8400-regulator.o |
| 13 | obj-$(CONFIG_REGULATOR_DA903X) += da903x.o | 13 | obj-$(CONFIG_REGULATOR_DA903X) += da903x.o |
| 14 | obj-$(CONFIG_REGULATOR_PCF50633) += pcf50633-regulator.o | ||
| 14 | 15 | ||
| 15 | ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG | 16 | ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG |
diff --git a/drivers/regulator/pcf50633-regulator.c b/drivers/regulator/pcf50633-regulator.c new file mode 100644 index 000000000000..4cc85ec6e120 --- /dev/null +++ b/drivers/regulator/pcf50633-regulator.c | |||
| @@ -0,0 +1,329 @@ | |||
| 1 | /* NXP PCF50633 PMIC Driver | ||
| 2 | * | ||
| 3 | * (C) 2006-2008 by Openmoko, Inc. | ||
| 4 | * Author: Balaji Rao <balajirrao@openmoko.org> | ||
| 5 | * All rights reserved. | ||
| 6 | * | ||
| 7 | * Broken down from monstrous PCF50633 driver mainly by | ||
| 8 | * Harald Welte and Andy Green and Werner Almesberger | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify it | ||
| 11 | * under the terms of the GNU General Public License as published by the | ||
| 12 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 13 | * option) any later version. | ||
| 14 | * | ||
| 15 | */ | ||
| 16 | |||
| 17 | #include <linux/kernel.h> | ||
| 18 | #include <linux/module.h> | ||
| 19 | #include <linux/init.h> | ||
| 20 | #include <linux/device.h> | ||
| 21 | #include <linux/err.h> | ||
| 22 | #include <linux/platform_device.h> | ||
| 23 | |||
| 24 | #include <linux/mfd/pcf50633/core.h> | ||
| 25 | #include <linux/mfd/pcf50633/pmic.h> | ||
| 26 | |||
| 27 | #define PCF50633_REGULATOR(_name, _id) \ | ||
| 28 | { \ | ||
| 29 | .name = _name, \ | ||
| 30 | .id = _id, \ | ||
| 31 | .ops = &pcf50633_regulator_ops, \ | ||
| 32 | .type = REGULATOR_VOLTAGE, \ | ||
| 33 | .owner = THIS_MODULE, \ | ||
| 34 | } | ||
| 35 | |||
| 36 | static const u8 pcf50633_regulator_registers[PCF50633_NUM_REGULATORS] = { | ||
| 37 | [PCF50633_REGULATOR_AUTO] = PCF50633_REG_AUTOOUT, | ||
| 38 | [PCF50633_REGULATOR_DOWN1] = PCF50633_REG_DOWN1OUT, | ||
| 39 | [PCF50633_REGULATOR_DOWN2] = PCF50633_REG_DOWN2OUT, | ||
| 40 | [PCF50633_REGULATOR_MEMLDO] = PCF50633_REG_MEMLDOOUT, | ||
| 41 | [PCF50633_REGULATOR_LDO1] = PCF50633_REG_LDO1OUT, | ||
| 42 | [PCF50633_REGULATOR_LDO2] = PCF50633_REG_LDO2OUT, | ||
| 43 | [PCF50633_REGULATOR_LDO3] = PCF50633_REG_LDO3OUT, | ||
| 44 | [PCF50633_REGULATOR_LDO4] = PCF50633_REG_LDO4OUT, | ||
| 45 | [PCF50633_REGULATOR_LDO5] = PCF50633_REG_LDO5OUT, | ||
| 46 | [PCF50633_REGULATOR_LDO6] = PCF50633_REG_LDO6OUT, | ||
| 47 | [PCF50633_REGULATOR_HCLDO] = PCF50633_REG_HCLDOOUT, | ||
| 48 | }; | ||
| 49 | |||
| 50 | /* Bits from voltage value */ | ||
| 51 | static u8 auto_voltage_bits(unsigned int millivolts) | ||
| 52 | { | ||
| 53 | if (millivolts < 1800) | ||
| 54 | return 0; | ||
| 55 | if (millivolts > 3800) | ||
| 56 | return 0xff; | ||
| 57 | |||
| 58 | millivolts -= 625; | ||
| 59 | |||
| 60 | return millivolts / 25; | ||
| 61 | } | ||
| 62 | |||
| 63 | static u8 down_voltage_bits(unsigned int millivolts) | ||
| 64 | { | ||
| 65 | if (millivolts < 625) | ||
| 66 | return 0; | ||
| 67 | else if (millivolts > 3000) | ||
| 68 | return 0xff; | ||
| 69 | |||
| 70 | millivolts -= 625; | ||
| 71 | |||
| 72 | return millivolts / 25; | ||
| 73 | } | ||
| 74 | |||
| 75 | static u8 ldo_voltage_bits(unsigned int millivolts) | ||
| 76 | { | ||
| 77 | if (millivolts < 900) | ||
| 78 | return 0; | ||
| 79 | else if (millivolts > 3600) | ||
| 80 | return 0x1f; | ||
| 81 | |||
| 82 | millivolts -= 900; | ||
| 83 | return millivolts / 100; | ||
| 84 | } | ||
| 85 | |||
| 86 | /* Obtain voltage value from bits */ | ||
| 87 | static unsigned int auto_voltage_value(u8 bits) | ||
| 88 | { | ||
| 89 | if (bits < 0x2f) | ||
| 90 | return 0; | ||
| 91 | |||
| 92 | return 625 + (bits * 25); | ||
| 93 | } | ||
| 94 | |||
| 95 | |||
| 96 | static unsigned int down_voltage_value(u8 bits) | ||
| 97 | { | ||
| 98 | return 625 + (bits * 25); | ||
| 99 | } | ||
| 100 | |||
| 101 | |||
| 102 | static unsigned int ldo_voltage_value(u8 bits) | ||
| 103 | { | ||
| 104 | bits &= 0x1f; | ||
| 105 | |||
| 106 | return 900 + (bits * 100); | ||
| 107 | } | ||
| 108 | |||
| 109 | static int pcf50633_regulator_set_voltage(struct regulator_dev *rdev, | ||
| 110 | int min_uV, int max_uV) | ||
| 111 | { | ||
| 112 | struct pcf50633 *pcf; | ||
| 113 | int regulator_id, millivolts; | ||
| 114 | u8 volt_bits, regnr; | ||
| 115 | |||
| 116 | pcf = rdev_get_drvdata(rdev); | ||
| 117 | |||
| 118 | regulator_id = rdev_get_id(rdev); | ||
| 119 | if (regulator_id >= PCF50633_NUM_REGULATORS) | ||
| 120 | return -EINVAL; | ||
| 121 | |||
| 122 | millivolts = min_uV / 1000; | ||
| 123 | |||
| 124 | regnr = pcf50633_regulator_registers[regulator_id]; | ||
| 125 | |||
| 126 | switch (regulator_id) { | ||
| 127 | case PCF50633_REGULATOR_AUTO: | ||
| 128 | volt_bits = auto_voltage_bits(millivolts); | ||
| 129 | break; | ||
| 130 | case PCF50633_REGULATOR_DOWN1: | ||
| 131 | volt_bits = down_voltage_bits(millivolts); | ||
| 132 | break; | ||
| 133 | case PCF50633_REGULATOR_DOWN2: | ||
| 134 | volt_bits = down_voltage_bits(millivolts); | ||
| 135 | break; | ||
| 136 | case PCF50633_REGULATOR_LDO1: | ||
| 137 | case PCF50633_REGULATOR_LDO2: | ||
| 138 | case PCF50633_REGULATOR_LDO3: | ||
| 139 | case PCF50633_REGULATOR_LDO4: | ||
| 140 | case PCF50633_REGULATOR_LDO5: | ||
| 141 | case PCF50633_REGULATOR_LDO6: | ||
| 142 | case PCF50633_REGULATOR_HCLDO: | ||
| 143 | volt_bits = ldo_voltage_bits(millivolts); | ||
| 144 | break; | ||
| 145 | default: | ||
| 146 | return -EINVAL; | ||
| 147 | } | ||
| 148 | |||
| 149 | return pcf50633_reg_write(pcf, regnr, volt_bits); | ||
| 150 | } | ||
| 151 | |||
| 152 | static int pcf50633_regulator_get_voltage(struct regulator_dev *rdev) | ||
| 153 | { | ||
| 154 | struct pcf50633 *pcf; | ||
| 155 | int regulator_id, millivolts, volt_bits; | ||
| 156 | u8 regnr; | ||
| 157 | |||
| 158 | pcf = rdev_get_drvdata(rdev);; | ||
| 159 | |||
| 160 | regulator_id = rdev_get_id(rdev); | ||
| 161 | if (regulator_id >= PCF50633_NUM_REGULATORS) | ||
| 162 | return -EINVAL; | ||
| 163 | |||
| 164 | regnr = pcf50633_regulator_registers[regulator_id]; | ||
| 165 | |||
| 166 | volt_bits = pcf50633_reg_read(pcf, regnr); | ||
| 167 | if (volt_bits < 0) | ||
| 168 | return -1; | ||
| 169 | |||
| 170 | switch (regulator_id) { | ||
| 171 | case PCF50633_REGULATOR_AUTO: | ||
| 172 | millivolts = auto_voltage_value(volt_bits); | ||
| 173 | break; | ||
| 174 | case PCF50633_REGULATOR_DOWN1: | ||
| 175 | millivolts = down_voltage_value(volt_bits); | ||
| 176 | break; | ||
| 177 | case PCF50633_REGULATOR_DOWN2: | ||
| 178 | millivolts = down_voltage_value(volt_bits); | ||
| 179 | break; | ||
| 180 | case PCF50633_REGULATOR_LDO1: | ||
| 181 | case PCF50633_REGULATOR_LDO2: | ||
| 182 | case PCF50633_REGULATOR_LDO3: | ||
| 183 | case PCF50633_REGULATOR_LDO4: | ||
| 184 | case PCF50633_REGULATOR_LDO5: | ||
| 185 | case PCF50633_REGULATOR_LDO6: | ||
| 186 | case PCF50633_REGULATOR_HCLDO: | ||
| 187 | millivolts = ldo_voltage_value(volt_bits); | ||
| 188 | break; | ||
| 189 | default: | ||
| 190 | return -EINVAL; | ||
| 191 | } | ||
| 192 | |||
| 193 | return millivolts * 1000; | ||
| 194 | } | ||
| 195 | |||
| 196 | static int pcf50633_regulator_enable(struct regulator_dev *rdev) | ||
| 197 | { | ||
| 198 | struct pcf50633 *pcf = rdev_get_drvdata(rdev); | ||
| 199 | int regulator_id; | ||
| 200 | u8 regnr; | ||
| 201 | |||
| 202 | regulator_id = rdev_get_id(rdev); | ||
| 203 | if (regulator_id >= PCF50633_NUM_REGULATORS) | ||
| 204 | return -EINVAL; | ||
| 205 | |||
| 206 | /* The *ENA register is always one after the *OUT register */ | ||
| 207 | regnr = pcf50633_regulator_registers[regulator_id] + 1; | ||
| 208 | |||
| 209 | return pcf50633_reg_set_bit_mask(pcf, regnr, PCF50633_REGULATOR_ON, | ||
| 210 | PCF50633_REGULATOR_ON); | ||
| 211 | } | ||
| 212 | |||
| 213 | static int pcf50633_regulator_disable(struct regulator_dev *rdev) | ||
| 214 | { | ||
| 215 | struct pcf50633 *pcf = rdev_get_drvdata(rdev); | ||
| 216 | int regulator_id; | ||
| 217 | u8 regnr; | ||
| 218 | |||
| 219 | regulator_id = rdev_get_id(rdev); | ||
| 220 | if (regulator_id >= PCF50633_NUM_REGULATORS) | ||
| 221 | return -EINVAL; | ||
| 222 | |||
| 223 | /* the *ENA register is always one after the *OUT register */ | ||
| 224 | regnr = pcf50633_regulator_registers[regulator_id] + 1; | ||
| 225 | |||
| 226 | return pcf50633_reg_set_bit_mask(pcf, regnr, | ||
| 227 | PCF50633_REGULATOR_ON, 0); | ||
| 228 | } | ||
| 229 | |||
| 230 | static int pcf50633_regulator_is_enabled(struct regulator_dev *rdev) | ||
| 231 | { | ||
| 232 | struct pcf50633 *pcf = rdev_get_drvdata(rdev); | ||
| 233 | int regulator_id = rdev_get_id(rdev); | ||
| 234 | u8 regnr; | ||
| 235 | |||
| 236 | regulator_id = rdev_get_id(rdev); | ||
| 237 | if (regulator_id >= PCF50633_NUM_REGULATORS) | ||
| 238 | return -EINVAL; | ||
| 239 | |||
| 240 | /* the *ENA register is always one after the *OUT register */ | ||
| 241 | regnr = pcf50633_regulator_registers[regulator_id] + 1; | ||
| 242 | |||
| 243 | return pcf50633_reg_read(pcf, regnr) & PCF50633_REGULATOR_ON; | ||
| 244 | } | ||
| 245 | |||
| 246 | static struct regulator_ops pcf50633_regulator_ops = { | ||
| 247 | .set_voltage = pcf50633_regulator_set_voltage, | ||
| 248 | .get_voltage = pcf50633_regulator_get_voltage, | ||
| 249 | .enable = pcf50633_regulator_enable, | ||
| 250 | .disable = pcf50633_regulator_disable, | ||
| 251 | .is_enabled = pcf50633_regulator_is_enabled, | ||
| 252 | }; | ||
| 253 | |||
| 254 | static struct regulator_desc regulators[] = { | ||
| 255 | [PCF50633_REGULATOR_AUTO] = | ||
| 256 | PCF50633_REGULATOR("auto", PCF50633_REGULATOR_AUTO), | ||
| 257 | [PCF50633_REGULATOR_DOWN1] = | ||
| 258 | PCF50633_REGULATOR("down1", PCF50633_REGULATOR_DOWN1), | ||
| 259 | [PCF50633_REGULATOR_DOWN2] = | ||
| 260 | PCF50633_REGULATOR("down2", PCF50633_REGULATOR_DOWN2), | ||
| 261 | [PCF50633_REGULATOR_LDO1] = | ||
| 262 | PCF50633_REGULATOR("ldo1", PCF50633_REGULATOR_LDO1), | ||
| 263 | [PCF50633_REGULATOR_LDO2] = | ||
| 264 | PCF50633_REGULATOR("ldo2", PCF50633_REGULATOR_LDO2), | ||
| 265 | [PCF50633_REGULATOR_LDO3] = | ||
| 266 | PCF50633_REGULATOR("ldo3", PCF50633_REGULATOR_LDO3), | ||
| 267 | [PCF50633_REGULATOR_LDO4] = | ||
| 268 | PCF50633_REGULATOR("ldo4", PCF50633_REGULATOR_LDO4), | ||
| 269 | [PCF50633_REGULATOR_LDO5] = | ||
| 270 | PCF50633_REGULATOR("ldo5", PCF50633_REGULATOR_LDO5), | ||
| 271 | [PCF50633_REGULATOR_LDO6] = | ||
| 272 | PCF50633_REGULATOR("ldo6", PCF50633_REGULATOR_LDO6), | ||
| 273 | [PCF50633_REGULATOR_HCLDO] = | ||
| 274 | PCF50633_REGULATOR("hcldo", PCF50633_REGULATOR_HCLDO), | ||
| 275 | [PCF50633_REGULATOR_MEMLDO] = | ||
| 276 | PCF50633_REGULATOR("memldo", PCF50633_REGULATOR_MEMLDO), | ||
| 277 | }; | ||
| 278 | |||
| 279 | static int __devinit pcf50633_regulator_probe(struct platform_device *pdev) | ||
| 280 | { | ||
| 281 | struct regulator_dev *rdev; | ||
| 282 | struct pcf50633 *pcf; | ||
| 283 | |||
| 284 | /* Already set by core driver */ | ||
| 285 | pcf = platform_get_drvdata(pdev); | ||
| 286 | |||
| 287 | rdev = regulator_register(®ulators[pdev->id], &pdev->dev, pcf); | ||
| 288 | if (IS_ERR(rdev)) | ||
| 289 | return PTR_ERR(rdev); | ||
| 290 | |||
| 291 | if (pcf->pdata->regulator_registered) | ||
| 292 | pcf->pdata->regulator_registered(pcf, pdev->id); | ||
| 293 | |||
| 294 | return 0; | ||
| 295 | } | ||
| 296 | |||
| 297 | static int __devexit pcf50633_regulator_remove(struct platform_device *pdev) | ||
| 298 | { | ||
| 299 | struct regulator_dev *rdev = platform_get_drvdata(pdev); | ||
| 300 | |||
| 301 | regulator_unregister(rdev); | ||
| 302 | |||
| 303 | return 0; | ||
| 304 | } | ||
| 305 | |||
| 306 | static struct platform_driver pcf50633_regulator_driver = { | ||
| 307 | .driver = { | ||
| 308 | .name = "pcf50633-regltr", | ||
| 309 | }, | ||
| 310 | .probe = pcf50633_regulator_probe, | ||
| 311 | .remove = __devexit_p(pcf50633_regulator_remove), | ||
| 312 | }; | ||
| 313 | |||
| 314 | static int __init pcf50633_regulator_init(void) | ||
| 315 | { | ||
| 316 | return platform_driver_register(&pcf50633_regulator_driver); | ||
| 317 | } | ||
| 318 | module_init(pcf50633_regulator_init); | ||
| 319 | |||
| 320 | static void __exit pcf50633_regulator_exit(void) | ||
| 321 | { | ||
| 322 | platform_driver_unregister(&pcf50633_regulator_driver); | ||
| 323 | } | ||
| 324 | module_exit(pcf50633_regulator_exit); | ||
| 325 | |||
| 326 | MODULE_AUTHOR("Balaji Rao <balajirrao@openmoko.org>"); | ||
| 327 | MODULE_DESCRIPTION("PCF50633 regulator driver"); | ||
| 328 | MODULE_LICENSE("GPL"); | ||
| 329 | MODULE_ALIAS("platform:pcf50633-regulator"); | ||
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 4ad831de41ad..cced4d108319 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig | |||
| @@ -502,6 +502,13 @@ config RTC_DRV_WM8350 | |||
| 502 | This driver can also be built as a module. If so, the module | 502 | This driver can also be built as a module. If so, the module |
| 503 | will be called "rtc-wm8350". | 503 | will be called "rtc-wm8350". |
| 504 | 504 | ||
| 505 | config RTC_DRV_PCF50633 | ||
| 506 | depends on MFD_PCF50633 | ||
| 507 | tristate "NXP PCF50633 RTC" | ||
| 508 | help | ||
| 509 | If you say yes here you get support for the RTC subsystem of the | ||
| 510 | NXP PCF50633 used in embedded systems. | ||
| 511 | |||
| 505 | comment "on-CPU RTC drivers" | 512 | comment "on-CPU RTC drivers" |
| 506 | 513 | ||
| 507 | config RTC_DRV_OMAP | 514 | config RTC_DRV_OMAP |
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 9a4340d48f26..6e28021abb9d 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile | |||
| @@ -74,3 +74,4 @@ obj-$(CONFIG_RTC_DRV_V3020) += rtc-v3020.o | |||
| 74 | obj-$(CONFIG_RTC_DRV_VR41XX) += rtc-vr41xx.o | 74 | obj-$(CONFIG_RTC_DRV_VR41XX) += rtc-vr41xx.o |
| 75 | obj-$(CONFIG_RTC_DRV_WM8350) += rtc-wm8350.o | 75 | obj-$(CONFIG_RTC_DRV_WM8350) += rtc-wm8350.o |
| 76 | obj-$(CONFIG_RTC_DRV_X1205) += rtc-x1205.o | 76 | obj-$(CONFIG_RTC_DRV_X1205) += rtc-x1205.o |
| 77 | obj-$(CONFIG_RTC_DRV_PCF50633) += rtc-pcf50633.o | ||
diff --git a/drivers/rtc/rtc-pcf50633.c b/drivers/rtc/rtc-pcf50633.c new file mode 100644 index 000000000000..f4dd87e29075 --- /dev/null +++ b/drivers/rtc/rtc-pcf50633.c | |||
| @@ -0,0 +1,344 @@ | |||
| 1 | /* NXP PCF50633 RTC Driver | ||
| 2 | * | ||
| 3 | * (C) 2006-2008 by Openmoko, Inc. | ||
| 4 | * Author: Balaji Rao <balajirrao@openmoko.org> | ||
| 5 | * All rights reserved. | ||
| 6 | * | ||
| 7 | * Broken down from monstrous PCF50633 driver mainly by | ||
| 8 | * Harald Welte, Andy Green and Werner Almesberger | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify it | ||
| 11 | * under the terms of the GNU General Public License as published by the | ||
| 12 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 13 | * option) any later version. | ||
| 14 | * | ||
| 15 | */ | ||
| 16 | |||
| 17 | #include <linux/kernel.h> | ||
| 18 | #include <linux/module.h> | ||
| 19 | #include <linux/init.h> | ||
| 20 | #include <linux/device.h> | ||
| 21 | #include <linux/platform_device.h> | ||
| 22 | #include <linux/rtc.h> | ||
| 23 | #include <linux/bcd.h> | ||
| 24 | #include <linux/err.h> | ||
| 25 | |||
| 26 | #include <linux/mfd/pcf50633/core.h> | ||
| 27 | |||
| 28 | #define PCF50633_REG_RTCSC 0x59 /* Second */ | ||
| 29 | #define PCF50633_REG_RTCMN 0x5a /* Minute */ | ||
| 30 | #define PCF50633_REG_RTCHR 0x5b /* Hour */ | ||
| 31 | #define PCF50633_REG_RTCWD 0x5c /* Weekday */ | ||
| 32 | #define PCF50633_REG_RTCDT 0x5d /* Day */ | ||
| 33 | #define PCF50633_REG_RTCMT 0x5e /* Month */ | ||
| 34 | #define PCF50633_REG_RTCYR 0x5f /* Year */ | ||
| 35 | #define PCF50633_REG_RTCSCA 0x60 /* Alarm Second */ | ||
| 36 | #define PCF50633_REG_RTCMNA 0x61 /* Alarm Minute */ | ||
| 37 | #define PCF50633_REG_RTCHRA 0x62 /* Alarm Hour */ | ||
| 38 | #define PCF50633_REG_RTCWDA 0x63 /* Alarm Weekday */ | ||
| 39 | #define PCF50633_REG_RTCDTA 0x64 /* Alarm Day */ | ||
| 40 | #define PCF50633_REG_RTCMTA 0x65 /* Alarm Month */ | ||
| 41 | #define PCF50633_REG_RTCYRA 0x66 /* Alarm Year */ | ||
| 42 | |||
| 43 | enum pcf50633_time_indexes { | ||
| 44 | PCF50633_TI_SEC, | ||
| 45 | PCF50633_TI_MIN, | ||
| 46 | PCF50633_TI_HOUR, | ||
| 47 | PCF50633_TI_WKDAY, | ||
| 48 | PCF50633_TI_DAY, | ||
| 49 | PCF50633_TI_MONTH, | ||
| 50 | PCF50633_TI_YEAR, | ||
| 51 | PCF50633_TI_EXTENT /* always last */ | ||
| 52 | }; | ||
| 53 | |||
| 54 | struct pcf50633_time { | ||
| 55 | u_int8_t time[PCF50633_TI_EXTENT]; | ||
| 56 | }; | ||
| 57 | |||
| 58 | struct pcf50633_rtc { | ||
| 59 | int alarm_enabled; | ||
| 60 | int second_enabled; | ||
| 61 | |||
| 62 | struct pcf50633 *pcf; | ||
| 63 | struct rtc_device *rtc_dev; | ||
| 64 | }; | ||
| 65 | |||
| 66 | static void pcf2rtc_time(struct rtc_time *rtc, struct pcf50633_time *pcf) | ||
| 67 | { | ||
| 68 | rtc->tm_sec = bcd2bin(pcf->time[PCF50633_TI_SEC]); | ||
| 69 | rtc->tm_min = bcd2bin(pcf->time[PCF50633_TI_MIN]); | ||
| 70 | rtc->tm_hour = bcd2bin(pcf->time[PCF50633_TI_HOUR]); | ||
| 71 | rtc->tm_wday = bcd2bin(pcf->time[PCF50633_TI_WKDAY]); | ||
| 72 | rtc->tm_mday = bcd2bin(pcf->time[PCF50633_TI_DAY]); | ||
| 73 | rtc->tm_mon = bcd2bin(pcf->time[PCF50633_TI_MONTH]); | ||
| 74 | rtc->tm_year = bcd2bin(pcf->time[PCF50633_TI_YEAR]) + 100; | ||
| 75 | } | ||
| 76 | |||
| 77 | static void rtc2pcf_time(struct pcf50633_time *pcf, struct rtc_time *rtc) | ||
| 78 | { | ||
| 79 | pcf->time[PCF50633_TI_SEC] = bin2bcd(rtc->tm_sec); | ||
| 80 | pcf->time[PCF50633_TI_MIN] = bin2bcd(rtc->tm_min); | ||
| 81 | pcf->time[PCF50633_TI_HOUR] = bin2bcd(rtc->tm_hour); | ||
| 82 | pcf->time[PCF50633_TI_WKDAY] = bin2bcd(rtc->tm_wday); | ||
| 83 | pcf->time[PCF50633_TI_DAY] = bin2bcd(rtc->tm_mday); | ||
| 84 | pcf->time[PCF50633_TI_MONTH] = bin2bcd(rtc->tm_mon); | ||
| 85 | pcf->time[PCF50633_TI_YEAR] = bin2bcd(rtc->tm_year % 100); | ||
| 86 | } | ||
| 87 | |||
| 88 | static int | ||
| 89 | pcf50633_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) | ||
| 90 | { | ||
| 91 | struct pcf50633_rtc *rtc = dev_get_drvdata(dev); | ||
| 92 | int err; | ||
| 93 | |||
| 94 | if (enabled) | ||
| 95 | err = pcf50633_irq_unmask(rtc->pcf, PCF50633_IRQ_ALARM); | ||
| 96 | else | ||
| 97 | err = pcf50633_irq_mask(rtc->pcf, PCF50633_IRQ_ALARM); | ||
| 98 | |||
| 99 | if (err < 0) | ||
| 100 | return err; | ||
| 101 | |||
| 102 | rtc->alarm_enabled = enabled; | ||
| 103 | |||
| 104 | return 0; | ||
| 105 | } | ||
| 106 | |||
| 107 | static int | ||
| 108 | pcf50633_rtc_update_irq_enable(struct device *dev, unsigned int enabled) | ||
| 109 | { | ||
| 110 | struct pcf50633_rtc *rtc = dev_get_drvdata(dev); | ||
| 111 | int err; | ||
| 112 | |||
| 113 | if (enabled) | ||
| 114 | err = pcf50633_irq_unmask(rtc->pcf, PCF50633_IRQ_SECOND); | ||
| 115 | else | ||
| 116 | err = pcf50633_irq_mask(rtc->pcf, PCF50633_IRQ_SECOND); | ||
| 117 | |||
| 118 | if (err < 0) | ||
| 119 | return err; | ||
| 120 | |||
| 121 | rtc->second_enabled = enabled; | ||
| 122 | |||
| 123 | return 0; | ||
| 124 | } | ||
| 125 | |||
| 126 | static int pcf50633_rtc_read_time(struct device *dev, struct rtc_time *tm) | ||
| 127 | { | ||
| 128 | struct pcf50633_rtc *rtc; | ||
| 129 | struct pcf50633_time pcf_tm; | ||
| 130 | int ret; | ||
| 131 | |||
| 132 | rtc = dev_get_drvdata(dev); | ||
| 133 | |||
| 134 | ret = pcf50633_read_block(rtc->pcf, PCF50633_REG_RTCSC, | ||
| 135 | PCF50633_TI_EXTENT, | ||
| 136 | &pcf_tm.time[0]); | ||
| 137 | if (ret != PCF50633_TI_EXTENT) { | ||
| 138 | dev_err(dev, "Failed to read time\n"); | ||
| 139 | return -EIO; | ||
| 140 | } | ||
| 141 | |||
| 142 | dev_dbg(dev, "PCF_TIME: %02x.%02x.%02x %02x:%02x:%02x\n", | ||
| 143 | pcf_tm.time[PCF50633_TI_DAY], | ||
| 144 | pcf_tm.time[PCF50633_TI_MONTH], | ||
| 145 | pcf_tm.time[PCF50633_TI_YEAR], | ||
| 146 | pcf_tm.time[PCF50633_TI_HOUR], | ||
| 147 | pcf_tm.time[PCF50633_TI_MIN], | ||
| 148 | pcf_tm.time[PCF50633_TI_SEC]); | ||
| 149 | |||
| 150 | pcf2rtc_time(tm, &pcf_tm); | ||
| 151 | |||
| 152 | dev_dbg(dev, "RTC_TIME: %u.%u.%u %u:%u:%u\n", | ||
| 153 | tm->tm_mday, tm->tm_mon, tm->tm_year, | ||
| 154 | tm->tm_hour, tm->tm_min, tm->tm_sec); | ||
| 155 | |||
| 156 | return rtc_valid_tm(tm); | ||
| 157 | } | ||
| 158 | |||
| 159 | static int pcf50633_rtc_set_time(struct device *dev, struct rtc_time *tm) | ||
| 160 | { | ||
| 161 | struct pcf50633_rtc *rtc; | ||
| 162 | struct pcf50633_time pcf_tm; | ||
| 163 | int second_masked, alarm_masked, ret = 0; | ||
| 164 | |||
| 165 | rtc = dev_get_drvdata(dev); | ||
| 166 | |||
| 167 | dev_dbg(dev, "RTC_TIME: %u.%u.%u %u:%u:%u\n", | ||
| 168 | tm->tm_mday, tm->tm_mon, tm->tm_year, | ||
| 169 | tm->tm_hour, tm->tm_min, tm->tm_sec); | ||
| 170 | |||
| 171 | rtc2pcf_time(&pcf_tm, tm); | ||
| 172 | |||
| 173 | dev_dbg(dev, "PCF_TIME: %02x.%02x.%02x %02x:%02x:%02x\n", | ||
| 174 | pcf_tm.time[PCF50633_TI_DAY], | ||
| 175 | pcf_tm.time[PCF50633_TI_MONTH], | ||
| 176 | pcf_tm.time[PCF50633_TI_YEAR], | ||
| 177 | pcf_tm.time[PCF50633_TI_HOUR], | ||
| 178 | pcf_tm.time[PCF50633_TI_MIN], | ||
| 179 | pcf_tm.time[PCF50633_TI_SEC]); | ||
| 180 | |||
| 181 | |||
| 182 | second_masked = pcf50633_irq_mask_get(rtc->pcf, PCF50633_IRQ_SECOND); | ||
| 183 | alarm_masked = pcf50633_irq_mask_get(rtc->pcf, PCF50633_IRQ_ALARM); | ||
| 184 | |||
| 185 | if (!second_masked) | ||
| 186 | pcf50633_irq_mask(rtc->pcf, PCF50633_IRQ_SECOND); | ||
| 187 | if (!alarm_masked) | ||
| 188 | pcf50633_irq_mask(rtc->pcf, PCF50633_IRQ_ALARM); | ||
| 189 | |||
| 190 | /* Returns 0 on success */ | ||
| 191 | ret = pcf50633_write_block(rtc->pcf, PCF50633_REG_RTCSC, | ||
| 192 | PCF50633_TI_EXTENT, | ||
| 193 | &pcf_tm.time[0]); | ||
| 194 | |||
| 195 | if (!second_masked) | ||
| 196 | pcf50633_irq_unmask(rtc->pcf, PCF50633_IRQ_SECOND); | ||
| 197 | if (!alarm_masked) | ||
| 198 | pcf50633_irq_unmask(rtc->pcf, PCF50633_IRQ_ALARM); | ||
| 199 | |||
| 200 | return ret; | ||
| 201 | } | ||
| 202 | |||
| 203 | static int pcf50633_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) | ||
| 204 | { | ||
| 205 | struct pcf50633_rtc *rtc; | ||
| 206 | struct pcf50633_time pcf_tm; | ||
| 207 | int ret = 0; | ||
| 208 | |||
| 209 | rtc = dev_get_drvdata(dev); | ||
| 210 | |||
| 211 | alrm->enabled = rtc->alarm_enabled; | ||
| 212 | |||
| 213 | ret = pcf50633_read_block(rtc->pcf, PCF50633_REG_RTCSCA, | ||
| 214 | PCF50633_TI_EXTENT, &pcf_tm.time[0]); | ||
| 215 | if (ret != PCF50633_TI_EXTENT) { | ||
| 216 | dev_err(dev, "Failed to read time\n"); | ||
| 217 | return -EIO; | ||
| 218 | } | ||
| 219 | |||
| 220 | pcf2rtc_time(&alrm->time, &pcf_tm); | ||
| 221 | |||
| 222 | return rtc_valid_tm(&alrm->time); | ||
| 223 | } | ||
| 224 | |||
| 225 | static int pcf50633_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) | ||
| 226 | { | ||
| 227 | struct pcf50633_rtc *rtc; | ||
| 228 | struct pcf50633_time pcf_tm; | ||
| 229 | int alarm_masked, ret = 0; | ||
| 230 | |||
| 231 | rtc = dev_get_drvdata(dev); | ||
| 232 | |||
| 233 | rtc2pcf_time(&pcf_tm, &alrm->time); | ||
| 234 | |||
| 235 | /* do like mktime does and ignore tm_wday */ | ||
| 236 | pcf_tm.time[PCF50633_TI_WKDAY] = 7; | ||
| 237 | |||
| 238 | alarm_masked = pcf50633_irq_mask_get(rtc->pcf, PCF50633_IRQ_ALARM); | ||
| 239 | |||
| 240 | /* disable alarm interrupt */ | ||
| 241 | if (!alarm_masked) | ||
| 242 | pcf50633_irq_mask(rtc->pcf, PCF50633_IRQ_ALARM); | ||
| 243 | |||
| 244 | /* Returns 0 on success */ | ||
| 245 | ret = pcf50633_write_block(rtc->pcf, PCF50633_REG_RTCSCA, | ||
| 246 | PCF50633_TI_EXTENT, &pcf_tm.time[0]); | ||
| 247 | |||
| 248 | if (!alarm_masked) | ||
| 249 | pcf50633_irq_unmask(rtc->pcf, PCF50633_IRQ_ALARM); | ||
| 250 | |||
| 251 | return ret; | ||
| 252 | } | ||
| 253 | |||
| 254 | static struct rtc_class_ops pcf50633_rtc_ops = { | ||
| 255 | .read_time = pcf50633_rtc_read_time, | ||
| 256 | .set_time = pcf50633_rtc_set_time, | ||
| 257 | .read_alarm = pcf50633_rtc_read_alarm, | ||
| 258 | .set_alarm = pcf50633_rtc_set_alarm, | ||
| 259 | .alarm_irq_enable = pcf50633_rtc_alarm_irq_enable, | ||
| 260 | .update_irq_enable = pcf50633_rtc_update_irq_enable, | ||
| 261 | }; | ||
| 262 | |||
| 263 | static void pcf50633_rtc_irq(int irq, void *data) | ||
| 264 | { | ||
| 265 | struct pcf50633_rtc *rtc = data; | ||
| 266 | |||
| 267 | switch (irq) { | ||
| 268 | case PCF50633_IRQ_ALARM: | ||
| 269 | rtc_update_irq(rtc->rtc_dev, 1, RTC_AF | RTC_IRQF); | ||
| 270 | break; | ||
| 271 | case PCF50633_IRQ_SECOND: | ||
| 272 | rtc_update_irq(rtc->rtc_dev, 1, RTC_UF | RTC_IRQF); | ||
| 273 | break; | ||
| 274 | } | ||
| 275 | } | ||
| 276 | |||
| 277 | static int __devinit pcf50633_rtc_probe(struct platform_device *pdev) | ||
| 278 | { | ||
| 279 | struct pcf50633_subdev_pdata *pdata; | ||
| 280 | struct pcf50633_rtc *rtc; | ||
| 281 | |||
| 282 | |||
| 283 | rtc = kzalloc(sizeof(*rtc), GFP_KERNEL); | ||
| 284 | if (!rtc) | ||
| 285 | return -ENOMEM; | ||
| 286 | |||
| 287 | pdata = pdev->dev.platform_data; | ||
| 288 | rtc->pcf = pdata->pcf; | ||
| 289 | platform_set_drvdata(pdev, rtc); | ||
| 290 | rtc->rtc_dev = rtc_device_register("pcf50633-rtc", &pdev->dev, | ||
| 291 | &pcf50633_rtc_ops, THIS_MODULE); | ||
| 292 | |||
| 293 | if (IS_ERR(rtc->rtc_dev)) { | ||
| 294 | kfree(rtc); | ||
| 295 | return PTR_ERR(rtc->rtc_dev); | ||
| 296 | } | ||
| 297 | |||
| 298 | pcf50633_register_irq(rtc->pcf, PCF50633_IRQ_ALARM, | ||
| 299 | pcf50633_rtc_irq, rtc); | ||
| 300 | pcf50633_register_irq(rtc->pcf, PCF50633_IRQ_SECOND, | ||
| 301 | pcf50633_rtc_irq, rtc); | ||
| 302 | |||
| 303 | return 0; | ||
| 304 | } | ||
| 305 | |||
| 306 | static int __devexit pcf50633_rtc_remove(struct platform_device *pdev) | ||
| 307 | { | ||
| 308 | struct pcf50633_rtc *rtc; | ||
| 309 | |||
| 310 | rtc = platform_get_drvdata(pdev); | ||
| 311 | |||
| 312 | pcf50633_free_irq(rtc->pcf, PCF50633_IRQ_ALARM); | ||
| 313 | pcf50633_free_irq(rtc->pcf, PCF50633_IRQ_SECOND); | ||
| 314 | |||
| 315 | rtc_device_unregister(rtc->rtc_dev); | ||
| 316 | kfree(rtc); | ||
| 317 | |||
| 318 | return 0; | ||
| 319 | } | ||
| 320 | |||
| 321 | static struct platform_driver pcf50633_rtc_driver = { | ||
| 322 | .driver = { | ||
| 323 | .name = "pcf50633-rtc", | ||
| 324 | }, | ||
| 325 | .probe = pcf50633_rtc_probe, | ||
| 326 | .remove = __devexit_p(pcf50633_rtc_remove), | ||
| 327 | }; | ||
| 328 | |||
| 329 | static int __init pcf50633_rtc_init(void) | ||
| 330 | { | ||
| 331 | return platform_driver_register(&pcf50633_rtc_driver); | ||
| 332 | } | ||
| 333 | module_init(pcf50633_rtc_init); | ||
| 334 | |||
| 335 | static void __exit pcf50633_rtc_exit(void) | ||
| 336 | { | ||
| 337 | platform_driver_unregister(&pcf50633_rtc_driver); | ||
| 338 | } | ||
| 339 | module_exit(pcf50633_rtc_exit); | ||
| 340 | |||
| 341 | MODULE_DESCRIPTION("PCF50633 RTC driver"); | ||
| 342 | MODULE_AUTHOR("Balaji Rao <balajirrao@openmoko.org>"); | ||
| 343 | MODULE_LICENSE("GPL"); | ||
| 344 | |||
diff --git a/drivers/s390/net/qeth_l2_main.c b/drivers/s390/net/qeth_l2_main.c index c4f1b046c3b1..07ab8a5c1c46 100644 --- a/drivers/s390/net/qeth_l2_main.c +++ b/drivers/s390/net/qeth_l2_main.c | |||
| @@ -916,7 +916,7 @@ static struct ethtool_ops qeth_l2_osn_ops = { | |||
| 916 | .get_drvinfo = qeth_core_get_drvinfo, | 916 | .get_drvinfo = qeth_core_get_drvinfo, |
| 917 | }; | 917 | }; |
| 918 | 918 | ||
| 919 | static struct net_device_ops qeth_l2_netdev_ops = { | 919 | static const struct net_device_ops qeth_l2_netdev_ops = { |
| 920 | .ndo_open = qeth_l2_open, | 920 | .ndo_open = qeth_l2_open, |
| 921 | .ndo_stop = qeth_l2_stop, | 921 | .ndo_stop = qeth_l2_stop, |
| 922 | .ndo_get_stats = qeth_get_stats, | 922 | .ndo_get_stats = qeth_get_stats, |
diff --git a/drivers/s390/net/qeth_l3_main.c b/drivers/s390/net/qeth_l3_main.c index 68d623ab7e6e..3d04920b9bb9 100644 --- a/drivers/s390/net/qeth_l3_main.c +++ b/drivers/s390/net/qeth_l3_main.c | |||
| @@ -2894,7 +2894,7 @@ qeth_l3_neigh_setup(struct net_device *dev, struct neigh_parms *np) | |||
| 2894 | return 0; | 2894 | return 0; |
| 2895 | } | 2895 | } |
| 2896 | 2896 | ||
| 2897 | static struct net_device_ops qeth_l3_netdev_ops = { | 2897 | static const struct net_device_ops qeth_l3_netdev_ops = { |
| 2898 | .ndo_open = qeth_l3_open, | 2898 | .ndo_open = qeth_l3_open, |
| 2899 | .ndo_stop = qeth_l3_stop, | 2899 | .ndo_stop = qeth_l3_stop, |
| 2900 | .ndo_get_stats = qeth_get_stats, | 2900 | .ndo_get_stats = qeth_get_stats, |
| @@ -2909,6 +2909,22 @@ static struct net_device_ops qeth_l3_netdev_ops = { | |||
| 2909 | .ndo_tx_timeout = qeth_tx_timeout, | 2909 | .ndo_tx_timeout = qeth_tx_timeout, |
| 2910 | }; | 2910 | }; |
| 2911 | 2911 | ||
| 2912 | static const struct net_device_ops qeth_l3_osa_netdev_ops = { | ||
| 2913 | .ndo_open = qeth_l3_open, | ||
| 2914 | .ndo_stop = qeth_l3_stop, | ||
| 2915 | .ndo_get_stats = qeth_get_stats, | ||
| 2916 | .ndo_start_xmit = qeth_l3_hard_start_xmit, | ||
| 2917 | .ndo_validate_addr = eth_validate_addr, | ||
| 2918 | .ndo_set_multicast_list = qeth_l3_set_multicast_list, | ||
| 2919 | .ndo_do_ioctl = qeth_l3_do_ioctl, | ||
| 2920 | .ndo_change_mtu = qeth_change_mtu, | ||
| 2921 | .ndo_vlan_rx_register = qeth_l3_vlan_rx_register, | ||
| 2922 | .ndo_vlan_rx_add_vid = qeth_l3_vlan_rx_add_vid, | ||
| 2923 | .ndo_vlan_rx_kill_vid = qeth_l3_vlan_rx_kill_vid, | ||
| 2924 | .ndo_tx_timeout = qeth_tx_timeout, | ||
| 2925 | .ndo_neigh_setup = qeth_l3_neigh_setup, | ||
| 2926 | }; | ||
| 2927 | |||
| 2912 | static int qeth_l3_setup_netdev(struct qeth_card *card) | 2928 | static int qeth_l3_setup_netdev(struct qeth_card *card) |
| 2913 | { | 2929 | { |
| 2914 | if (card->info.type == QETH_CARD_TYPE_OSAE) { | 2930 | if (card->info.type == QETH_CARD_TYPE_OSAE) { |
| @@ -2919,12 +2935,12 @@ static int qeth_l3_setup_netdev(struct qeth_card *card) | |||
| 2919 | #endif | 2935 | #endif |
| 2920 | if (!card->dev) | 2936 | if (!card->dev) |
| 2921 | return -ENODEV; | 2937 | return -ENODEV; |
| 2938 | card->dev->netdev_ops = &qeth_l3_netdev_ops; | ||
| 2922 | } else { | 2939 | } else { |
| 2923 | card->dev = alloc_etherdev(0); | 2940 | card->dev = alloc_etherdev(0); |
| 2924 | if (!card->dev) | 2941 | if (!card->dev) |
| 2925 | return -ENODEV; | 2942 | return -ENODEV; |
| 2926 | qeth_l3_netdev_ops.ndo_neigh_setup = | 2943 | card->dev->netdev_ops = &qeth_l3_osa_netdev_ops; |
| 2927 | qeth_l3_neigh_setup; | ||
| 2928 | 2944 | ||
| 2929 | /*IPv6 address autoconfiguration stuff*/ | 2945 | /*IPv6 address autoconfiguration stuff*/ |
| 2930 | qeth_l3_get_unique_id(card); | 2946 | qeth_l3_get_unique_id(card); |
| @@ -2937,6 +2953,7 @@ static int qeth_l3_setup_netdev(struct qeth_card *card) | |||
| 2937 | if (!card->dev) | 2953 | if (!card->dev) |
| 2938 | return -ENODEV; | 2954 | return -ENODEV; |
| 2939 | card->dev->flags |= IFF_NOARP; | 2955 | card->dev->flags |= IFF_NOARP; |
| 2956 | card->dev->netdev_ops = &qeth_l3_netdev_ops; | ||
| 2940 | qeth_l3_iqd_read_initial_mac(card); | 2957 | qeth_l3_iqd_read_initial_mac(card); |
| 2941 | } else | 2958 | } else |
| 2942 | return -ENODEV; | 2959 | return -ENODEV; |
| @@ -2944,7 +2961,6 @@ static int qeth_l3_setup_netdev(struct qeth_card *card) | |||
| 2944 | card->dev->ml_priv = card; | 2961 | card->dev->ml_priv = card; |
| 2945 | card->dev->watchdog_timeo = QETH_TX_TIMEOUT; | 2962 | card->dev->watchdog_timeo = QETH_TX_TIMEOUT; |
| 2946 | card->dev->mtu = card->info.initial_mtu; | 2963 | card->dev->mtu = card->info.initial_mtu; |
| 2947 | card->dev->netdev_ops = &qeth_l3_netdev_ops; | ||
| 2948 | SET_ETHTOOL_OPS(card->dev, &qeth_l3_ethtool_ops); | 2964 | SET_ETHTOOL_OPS(card->dev, &qeth_l3_ethtool_ops); |
| 2949 | card->dev->features |= NETIF_F_HW_VLAN_TX | | 2965 | card->dev->features |= NETIF_F_HW_VLAN_TX | |
| 2950 | NETIF_F_HW_VLAN_RX | | 2966 | NETIF_F_HW_VLAN_RX | |
diff --git a/drivers/serial/jsm/jsm_neo.c b/drivers/serial/jsm/jsm_neo.c index b7584ca55ade..e6390d023634 100644 --- a/drivers/serial/jsm/jsm_neo.c +++ b/drivers/serial/jsm/jsm_neo.c | |||
| @@ -577,9 +577,6 @@ static void neo_parse_modem(struct jsm_channel *ch, u8 signals) | |||
| 577 | jsm_printk(MSIGS, INFO, &ch->ch_bd->pci_dev, | 577 | jsm_printk(MSIGS, INFO, &ch->ch_bd->pci_dev, |
| 578 | "neo_parse_modem: port: %d msignals: %x\n", ch->ch_portnum, msignals); | 578 | "neo_parse_modem: port: %d msignals: %x\n", ch->ch_portnum, msignals); |
| 579 | 579 | ||
| 580 | if (!ch) | ||
| 581 | return; | ||
| 582 | |||
| 583 | /* Scrub off lower bits. They signify delta's, which I don't care about */ | 580 | /* Scrub off lower bits. They signify delta's, which I don't care about */ |
| 584 | /* Keep DDCD and DDSR though */ | 581 | /* Keep DDCD and DDSR though */ |
| 585 | msignals &= 0xf8; | 582 | msignals &= 0xf8; |
diff --git a/drivers/usb/serial/ti_usb_3410_5052.c b/drivers/usb/serial/ti_usb_3410_5052.c index 01d0c70d60e9..3cf41df302d7 100644 --- a/drivers/usb/serial/ti_usb_3410_5052.c +++ b/drivers/usb/serial/ti_usb_3410_5052.c | |||
| @@ -145,7 +145,7 @@ static int ti_command_in_sync(struct ti_device *tdev, __u8 command, | |||
| 145 | static int ti_write_byte(struct ti_device *tdev, unsigned long addr, | 145 | static int ti_write_byte(struct ti_device *tdev, unsigned long addr, |
| 146 | __u8 mask, __u8 byte); | 146 | __u8 mask, __u8 byte); |
| 147 | 147 | ||
| 148 | static int ti_download_firmware(struct ti_device *tdev, int type); | 148 | static int ti_download_firmware(struct ti_device *tdev); |
| 149 | 149 | ||
| 150 | /* circular buffer */ | 150 | /* circular buffer */ |
| 151 | static struct circ_buf *ti_buf_alloc(void); | 151 | static struct circ_buf *ti_buf_alloc(void); |
| @@ -176,9 +176,14 @@ static unsigned int product_5052_count; | |||
| 176 | /* the array dimension is the number of default entries plus */ | 176 | /* the array dimension is the number of default entries plus */ |
| 177 | /* TI_EXTRA_VID_PID_COUNT user defined entries plus 1 terminating */ | 177 | /* TI_EXTRA_VID_PID_COUNT user defined entries plus 1 terminating */ |
| 178 | /* null entry */ | 178 | /* null entry */ |
| 179 | static struct usb_device_id ti_id_table_3410[1+TI_EXTRA_VID_PID_COUNT+1] = { | 179 | static struct usb_device_id ti_id_table_3410[7+TI_EXTRA_VID_PID_COUNT+1] = { |
| 180 | { USB_DEVICE(TI_VENDOR_ID, TI_3410_PRODUCT_ID) }, | 180 | { USB_DEVICE(TI_VENDOR_ID, TI_3410_PRODUCT_ID) }, |
| 181 | { USB_DEVICE(TI_VENDOR_ID, TI_3410_EZ430_ID) }, | 181 | { USB_DEVICE(TI_VENDOR_ID, TI_3410_EZ430_ID) }, |
| 182 | { USB_DEVICE(MTS_VENDOR_ID, MTS_GSM_NO_FW_PRODUCT_ID) }, | ||
| 183 | { USB_DEVICE(MTS_VENDOR_ID, MTS_CDMA_NO_FW_PRODUCT_ID) }, | ||
| 184 | { USB_DEVICE(MTS_VENDOR_ID, MTS_CDMA_PRODUCT_ID) }, | ||
| 185 | { USB_DEVICE(MTS_VENDOR_ID, MTS_GSM_PRODUCT_ID) }, | ||
| 186 | { USB_DEVICE(MTS_VENDOR_ID, MTS_EDGE_PRODUCT_ID) }, | ||
| 182 | }; | 187 | }; |
| 183 | 188 | ||
| 184 | static struct usb_device_id ti_id_table_5052[4+TI_EXTRA_VID_PID_COUNT+1] = { | 189 | static struct usb_device_id ti_id_table_5052[4+TI_EXTRA_VID_PID_COUNT+1] = { |
| @@ -188,9 +193,14 @@ static struct usb_device_id ti_id_table_5052[4+TI_EXTRA_VID_PID_COUNT+1] = { | |||
| 188 | { USB_DEVICE(TI_VENDOR_ID, TI_5052_FIRMWARE_PRODUCT_ID) }, | 193 | { USB_DEVICE(TI_VENDOR_ID, TI_5052_FIRMWARE_PRODUCT_ID) }, |
| 189 | }; | 194 | }; |
| 190 | 195 | ||
| 191 | static struct usb_device_id ti_id_table_combined[] = { | 196 | static struct usb_device_id ti_id_table_combined[6+2*TI_EXTRA_VID_PID_COUNT+1] = { |
| 192 | { USB_DEVICE(TI_VENDOR_ID, TI_3410_PRODUCT_ID) }, | 197 | { USB_DEVICE(TI_VENDOR_ID, TI_3410_PRODUCT_ID) }, |
| 193 | { USB_DEVICE(TI_VENDOR_ID, TI_3410_EZ430_ID) }, | 198 | { USB_DEVICE(TI_VENDOR_ID, TI_3410_EZ430_ID) }, |
| 199 | { USB_DEVICE(MTS_VENDOR_ID, MTS_GSM_NO_FW_PRODUCT_ID) }, | ||
| 200 | { USB_DEVICE(MTS_VENDOR_ID, MTS_CDMA_NO_FW_PRODUCT_ID) }, | ||
| 201 | { USB_DEVICE(MTS_VENDOR_ID, MTS_CDMA_PRODUCT_ID) }, | ||
| 202 | { USB_DEVICE(MTS_VENDOR_ID, MTS_GSM_PRODUCT_ID) }, | ||
| 203 | { USB_DEVICE(MTS_VENDOR_ID, MTS_EDGE_PRODUCT_ID) }, | ||
| 194 | { USB_DEVICE(TI_VENDOR_ID, TI_5052_BOOT_PRODUCT_ID) }, | 204 | { USB_DEVICE(TI_VENDOR_ID, TI_5052_BOOT_PRODUCT_ID) }, |
| 195 | { USB_DEVICE(TI_VENDOR_ID, TI_5152_BOOT_PRODUCT_ID) }, | 205 | { USB_DEVICE(TI_VENDOR_ID, TI_5152_BOOT_PRODUCT_ID) }, |
| 196 | { USB_DEVICE(TI_VENDOR_ID, TI_5052_EEPROM_PRODUCT_ID) }, | 206 | { USB_DEVICE(TI_VENDOR_ID, TI_5052_EEPROM_PRODUCT_ID) }, |
| @@ -272,6 +282,9 @@ MODULE_LICENSE("GPL"); | |||
| 272 | 282 | ||
| 273 | MODULE_FIRMWARE("ti_3410.fw"); | 283 | MODULE_FIRMWARE("ti_3410.fw"); |
| 274 | MODULE_FIRMWARE("ti_5052.fw"); | 284 | MODULE_FIRMWARE("ti_5052.fw"); |
| 285 | MODULE_FIRMWARE("mts_cdma.fw"); | ||
| 286 | MODULE_FIRMWARE("mts_gsm.fw"); | ||
| 287 | MODULE_FIRMWARE("mts_edge.fw"); | ||
| 275 | 288 | ||
| 276 | module_param(debug, bool, S_IRUGO | S_IWUSR); | 289 | module_param(debug, bool, S_IRUGO | S_IWUSR); |
| 277 | MODULE_PARM_DESC(debug, "Enable debugging, 0=no, 1=yes"); | 290 | MODULE_PARM_DESC(debug, "Enable debugging, 0=no, 1=yes"); |
| @@ -304,21 +317,28 @@ MODULE_DEVICE_TABLE(usb, ti_id_table_combined); | |||
| 304 | 317 | ||
| 305 | static int __init ti_init(void) | 318 | static int __init ti_init(void) |
| 306 | { | 319 | { |
| 307 | int i, j; | 320 | int i, j, c; |
| 308 | int ret; | 321 | int ret; |
| 309 | 322 | ||
| 310 | /* insert extra vendor and product ids */ | 323 | /* insert extra vendor and product ids */ |
| 324 | c = ARRAY_SIZE(ti_id_table_combined) - 2 * TI_EXTRA_VID_PID_COUNT - 1; | ||
| 311 | j = ARRAY_SIZE(ti_id_table_3410) - TI_EXTRA_VID_PID_COUNT - 1; | 325 | j = ARRAY_SIZE(ti_id_table_3410) - TI_EXTRA_VID_PID_COUNT - 1; |
| 312 | for (i = 0; i < min(vendor_3410_count, product_3410_count); i++, j++) { | 326 | for (i = 0; i < min(vendor_3410_count, product_3410_count); i++, j++, c++) { |
| 313 | ti_id_table_3410[j].idVendor = vendor_3410[i]; | 327 | ti_id_table_3410[j].idVendor = vendor_3410[i]; |
| 314 | ti_id_table_3410[j].idProduct = product_3410[i]; | 328 | ti_id_table_3410[j].idProduct = product_3410[i]; |
| 315 | ti_id_table_3410[j].match_flags = USB_DEVICE_ID_MATCH_DEVICE; | 329 | ti_id_table_3410[j].match_flags = USB_DEVICE_ID_MATCH_DEVICE; |
| 330 | ti_id_table_combined[c].idVendor = vendor_3410[i]; | ||
| 331 | ti_id_table_combined[c].idProduct = product_3410[i]; | ||
| 332 | ti_id_table_combined[c].match_flags = USB_DEVICE_ID_MATCH_DEVICE; | ||
| 316 | } | 333 | } |
| 317 | j = ARRAY_SIZE(ti_id_table_5052) - TI_EXTRA_VID_PID_COUNT - 1; | 334 | j = ARRAY_SIZE(ti_id_table_5052) - TI_EXTRA_VID_PID_COUNT - 1; |
| 318 | for (i = 0; i < min(vendor_5052_count, product_5052_count); i++, j++) { | 335 | for (i = 0; i < min(vendor_5052_count, product_5052_count); i++, j++, c++) { |
| 319 | ti_id_table_5052[j].idVendor = vendor_5052[i]; | 336 | ti_id_table_5052[j].idVendor = vendor_5052[i]; |
| 320 | ti_id_table_5052[j].idProduct = product_5052[i]; | 337 | ti_id_table_5052[j].idProduct = product_5052[i]; |
| 321 | ti_id_table_5052[j].match_flags = USB_DEVICE_ID_MATCH_DEVICE; | 338 | ti_id_table_5052[j].match_flags = USB_DEVICE_ID_MATCH_DEVICE; |
| 339 | ti_id_table_combined[c].idVendor = vendor_5052[i]; | ||
| 340 | ti_id_table_combined[c].idProduct = product_5052[i]; | ||
| 341 | ti_id_table_combined[c].match_flags = USB_DEVICE_ID_MATCH_DEVICE; | ||
| 322 | } | 342 | } |
| 323 | 343 | ||
| 324 | ret = usb_serial_register(&ti_1port_device); | 344 | ret = usb_serial_register(&ti_1port_device); |
| @@ -390,11 +410,7 @@ static int ti_startup(struct usb_serial *serial) | |||
| 390 | 410 | ||
| 391 | /* if we have only 1 configuration, download firmware */ | 411 | /* if we have only 1 configuration, download firmware */ |
| 392 | if (dev->descriptor.bNumConfigurations == 1) { | 412 | if (dev->descriptor.bNumConfigurations == 1) { |
| 393 | if (tdev->td_is_3410) | 413 | if ((status = ti_download_firmware(tdev)) != 0) |
| 394 | status = ti_download_firmware(tdev, 3410); | ||
| 395 | else | ||
| 396 | status = ti_download_firmware(tdev, 5052); | ||
| 397 | if (status) | ||
| 398 | goto free_tdev; | 414 | goto free_tdev; |
| 399 | 415 | ||
| 400 | /* 3410 must be reset, 5052 resets itself */ | 416 | /* 3410 must be reset, 5052 resets itself */ |
| @@ -1671,9 +1687,9 @@ static int ti_do_download(struct usb_device *dev, int pipe, | |||
| 1671 | return status; | 1687 | return status; |
| 1672 | } | 1688 | } |
| 1673 | 1689 | ||
| 1674 | static int ti_download_firmware(struct ti_device *tdev, int type) | 1690 | static int ti_download_firmware(struct ti_device *tdev) |
| 1675 | { | 1691 | { |
| 1676 | int status = -ENOMEM; | 1692 | int status; |
| 1677 | int buffer_size; | 1693 | int buffer_size; |
| 1678 | __u8 *buffer; | 1694 | __u8 *buffer; |
| 1679 | struct usb_device *dev = tdev->td_serial->dev; | 1695 | struct usb_device *dev = tdev->td_serial->dev; |
| @@ -1681,9 +1697,34 @@ static int ti_download_firmware(struct ti_device *tdev, int type) | |||
| 1681 | tdev->td_serial->port[0]->bulk_out_endpointAddress); | 1697 | tdev->td_serial->port[0]->bulk_out_endpointAddress); |
| 1682 | const struct firmware *fw_p; | 1698 | const struct firmware *fw_p; |
| 1683 | char buf[32]; | 1699 | char buf[32]; |
| 1684 | sprintf(buf, "ti_usb-%d.bin", type); | ||
| 1685 | 1700 | ||
| 1686 | if (request_firmware(&fw_p, buf, &dev->dev)) { | 1701 | /* try ID specific firmware first, then try generic firmware */ |
| 1702 | sprintf(buf, "ti_usb-v%04x-p%04x.fw", dev->descriptor.idVendor, | ||
| 1703 | dev->descriptor.idProduct); | ||
| 1704 | if ((status = request_firmware(&fw_p, buf, &dev->dev)) != 0) { | ||
| 1705 | buf[0] = '\0'; | ||
| 1706 | if (dev->descriptor.idVendor == MTS_VENDOR_ID) { | ||
| 1707 | switch (dev->descriptor.idProduct) { | ||
| 1708 | case MTS_CDMA_PRODUCT_ID: | ||
| 1709 | strcpy(buf, "mts_cdma.fw"); | ||
| 1710 | break; | ||
| 1711 | case MTS_GSM_PRODUCT_ID: | ||
| 1712 | strcpy(buf, "mts_gsm.fw"); | ||
| 1713 | break; | ||
| 1714 | case MTS_EDGE_PRODUCT_ID: | ||
| 1715 | strcpy(buf, "mts_edge.fw"); | ||
| 1716 | break; | ||
| 1717 | } | ||
| 1718 | } | ||
| 1719 | if (buf[0] == '\0') { | ||
| 1720 | if (tdev->td_is_3410) | ||
| 1721 | strcpy(buf, "ti_3410.fw"); | ||
| 1722 | else | ||
| 1723 | strcpy(buf, "ti_5052.fw"); | ||
| 1724 | } | ||
| 1725 | status = request_firmware(&fw_p, buf, &dev->dev); | ||
| 1726 | } | ||
| 1727 | if (status) { | ||
| 1687 | dev_err(&dev->dev, "%s - firmware not found\n", __func__); | 1728 | dev_err(&dev->dev, "%s - firmware not found\n", __func__); |
| 1688 | return -ENOENT; | 1729 | return -ENOENT; |
| 1689 | } | 1730 | } |
| @@ -1699,6 +1740,8 @@ static int ti_download_firmware(struct ti_device *tdev, int type) | |||
| 1699 | memset(buffer + fw_p->size, 0xff, buffer_size - fw_p->size); | 1740 | memset(buffer + fw_p->size, 0xff, buffer_size - fw_p->size); |
| 1700 | status = ti_do_download(dev, pipe, buffer, fw_p->size); | 1741 | status = ti_do_download(dev, pipe, buffer, fw_p->size); |
| 1701 | kfree(buffer); | 1742 | kfree(buffer); |
| 1743 | } else { | ||
| 1744 | status = -ENOMEM; | ||
| 1702 | } | 1745 | } |
| 1703 | release_firmware(fw_p); | 1746 | release_firmware(fw_p); |
| 1704 | if (status) { | 1747 | if (status) { |
diff --git a/drivers/usb/serial/ti_usb_3410_5052.h b/drivers/usb/serial/ti_usb_3410_5052.h index b5541bf991ba..7e4752fbf232 100644 --- a/drivers/usb/serial/ti_usb_3410_5052.h +++ b/drivers/usb/serial/ti_usb_3410_5052.h | |||
| @@ -34,6 +34,14 @@ | |||
| 34 | #define TI_5052_EEPROM_PRODUCT_ID 0x505A /* EEPROM, no firmware */ | 34 | #define TI_5052_EEPROM_PRODUCT_ID 0x505A /* EEPROM, no firmware */ |
| 35 | #define TI_5052_FIRMWARE_PRODUCT_ID 0x505F /* firmware is running */ | 35 | #define TI_5052_FIRMWARE_PRODUCT_ID 0x505F /* firmware is running */ |
| 36 | 36 | ||
| 37 | /* Multi-Tech vendor and product ids */ | ||
| 38 | #define MTS_VENDOR_ID 0x06E0 | ||
| 39 | #define MTS_GSM_NO_FW_PRODUCT_ID 0xF108 | ||
| 40 | #define MTS_CDMA_NO_FW_PRODUCT_ID 0xF109 | ||
| 41 | #define MTS_CDMA_PRODUCT_ID 0xF110 | ||
| 42 | #define MTS_GSM_PRODUCT_ID 0xF111 | ||
| 43 | #define MTS_EDGE_PRODUCT_ID 0xF112 | ||
| 44 | |||
| 37 | /* Commands */ | 45 | /* Commands */ |
| 38 | #define TI_GET_VERSION 0x01 | 46 | #define TI_GET_VERSION 0x01 |
| 39 | #define TI_GET_PORT_STATUS 0x02 | 47 | #define TI_GET_PORT_STATUS 0x02 |
diff --git a/drivers/usb/serial/usb-serial.c b/drivers/usb/serial/usb-serial.c index 080ade223d53..cfcfd5ab06ce 100644 --- a/drivers/usb/serial/usb-serial.c +++ b/drivers/usb/serial/usb-serial.c | |||
| @@ -511,9 +511,6 @@ static void usb_serial_port_work(struct work_struct *work) | |||
| 511 | 511 | ||
| 512 | dbg("%s - port %d", __func__, port->number); | 512 | dbg("%s - port %d", __func__, port->number); |
| 513 | 513 | ||
| 514 | if (!port) | ||
| 515 | return; | ||
| 516 | |||
| 517 | tty = tty_port_tty_get(&port->port); | 514 | tty = tty_port_tty_get(&port->port); |
| 518 | if (!tty) | 515 | if (!tty) |
| 519 | return; | 516 | return; |
diff --git a/drivers/video/Makefile b/drivers/video/Makefile index e39e33e797da..be2b657546ef 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile | |||
| @@ -28,7 +28,7 @@ obj-$(CONFIG_FB_DDC) += fb_ddc.o | |||
| 28 | obj-$(CONFIG_FB_DEFERRED_IO) += fb_defio.o | 28 | obj-$(CONFIG_FB_DEFERRED_IO) += fb_defio.o |
| 29 | 29 | ||
| 30 | # Hardware specific drivers go first | 30 | # Hardware specific drivers go first |
| 31 | obj-$(CONFIG_FB_AMIGA) += amifb.o c2p.o | 31 | obj-$(CONFIG_FB_AMIGA) += amifb.o c2p_planar.o |
| 32 | obj-$(CONFIG_FB_ARC) += arcfb.o | 32 | obj-$(CONFIG_FB_ARC) += arcfb.o |
| 33 | obj-$(CONFIG_FB_CLPS711X) += clps711xfb.o | 33 | obj-$(CONFIG_FB_CLPS711X) += clps711xfb.o |
| 34 | obj-$(CONFIG_FB_CYBER2000) += cyber2000fb.o | 34 | obj-$(CONFIG_FB_CYBER2000) += cyber2000fb.o |
| @@ -72,7 +72,7 @@ obj-$(CONFIG_FB_TCX) += tcx.o sbuslib.o | |||
| 72 | obj-$(CONFIG_FB_LEO) += leo.o sbuslib.o | 72 | obj-$(CONFIG_FB_LEO) += leo.o sbuslib.o |
| 73 | obj-$(CONFIG_FB_SGIVW) += sgivwfb.o | 73 | obj-$(CONFIG_FB_SGIVW) += sgivwfb.o |
| 74 | obj-$(CONFIG_FB_ACORN) += acornfb.o | 74 | obj-$(CONFIG_FB_ACORN) += acornfb.o |
| 75 | obj-$(CONFIG_FB_ATARI) += atafb.o c2p.o atafb_mfb.o \ | 75 | obj-$(CONFIG_FB_ATARI) += atafb.o c2p_iplan2.o atafb_mfb.o \ |
| 76 | atafb_iplan2p2.o atafb_iplan2p4.o atafb_iplan2p8.o | 76 | atafb_iplan2p2.o atafb_iplan2p4.o atafb_iplan2p8.o |
| 77 | obj-$(CONFIG_FB_MAC) += macfb.o | 77 | obj-$(CONFIG_FB_MAC) += macfb.o |
| 78 | obj-$(CONFIG_FB_HECUBA) += hecubafb.o | 78 | obj-$(CONFIG_FB_HECUBA) += hecubafb.o |
diff --git a/drivers/video/amifb.c b/drivers/video/amifb.c index b8e9a8682f2d..100f23661465 100644 --- a/drivers/video/amifb.c +++ b/drivers/video/amifb.c | |||
| @@ -2159,9 +2159,9 @@ static void amifb_imageblit(struct fb_info *info, const struct fb_image *image) | |||
| 2159 | src += pitch; | 2159 | src += pitch; |
| 2160 | } | 2160 | } |
| 2161 | } else { | 2161 | } else { |
| 2162 | c2p(info->screen_base, image->data, dx, dy, width, height, | 2162 | c2p_planar(info->screen_base, image->data, dx, dy, width, |
| 2163 | par->next_line, par->next_plane, image->width, | 2163 | height, par->next_line, par->next_plane, |
| 2164 | info->var.bits_per_pixel); | 2164 | image->width, info->var.bits_per_pixel); |
| 2165 | } | 2165 | } |
| 2166 | } | 2166 | } |
| 2167 | 2167 | ||
diff --git a/drivers/video/atafb.c b/drivers/video/atafb.c index 77eb8b34fbfa..8058572a7428 100644 --- a/drivers/video/atafb.c +++ b/drivers/video/atafb.c | |||
| @@ -122,7 +122,6 @@ static struct atafb_par { | |||
| 122 | void *screen_base; | 122 | void *screen_base; |
| 123 | int yres_virtual; | 123 | int yres_virtual; |
| 124 | u_long next_line; | 124 | u_long next_line; |
| 125 | u_long next_plane; | ||
| 126 | #if defined ATAFB_TT || defined ATAFB_STE | 125 | #if defined ATAFB_TT || defined ATAFB_STE |
| 127 | union { | 126 | union { |
| 128 | struct { | 127 | struct { |
| @@ -149,6 +148,7 @@ static struct atafb_par { | |||
| 149 | short mono; | 148 | short mono; |
| 150 | short ste_mode; | 149 | short ste_mode; |
| 151 | short bpp; | 150 | short bpp; |
| 151 | u32 pseudo_palette[16]; | ||
| 152 | } falcon; | 152 | } falcon; |
| 153 | #endif | 153 | #endif |
| 154 | /* Nothing needed for external mode */ | 154 | /* Nothing needed for external mode */ |
| @@ -614,7 +614,7 @@ static int tt_encode_fix(struct fb_fix_screeninfo *fix, struct atafb_par *par) | |||
| 614 | fix->xpanstep = 0; | 614 | fix->xpanstep = 0; |
| 615 | fix->ypanstep = 1; | 615 | fix->ypanstep = 1; |
| 616 | fix->ywrapstep = 0; | 616 | fix->ywrapstep = 0; |
| 617 | fix->line_length = 0; | 617 | fix->line_length = par->next_line; |
| 618 | fix->accel = FB_ACCEL_ATARIBLITT; | 618 | fix->accel = FB_ACCEL_ATARIBLITT; |
| 619 | return 0; | 619 | return 0; |
| 620 | } | 620 | } |
| @@ -691,6 +691,7 @@ static int tt_decode_var(struct fb_var_screeninfo *var, struct atafb_par *par) | |||
| 691 | return -EINVAL; | 691 | return -EINVAL; |
| 692 | par->yres_virtual = yres_virtual; | 692 | par->yres_virtual = yres_virtual; |
| 693 | par->screen_base = screen_base + var->yoffset * linelen; | 693 | par->screen_base = screen_base + var->yoffset * linelen; |
| 694 | par->next_line = linelen; | ||
| 694 | return 0; | 695 | return 0; |
| 695 | } | 696 | } |
| 696 | 697 | ||
| @@ -884,10 +885,6 @@ static int vdl_prescale[4][3] = { | |||
| 884 | /* Default hsync timing [mon_type] in picoseconds */ | 885 | /* Default hsync timing [mon_type] in picoseconds */ |
| 885 | static long h_syncs[4] = { 3000000, 4875000, 4000000, 4875000 }; | 886 | static long h_syncs[4] = { 3000000, 4875000, 4000000, 4875000 }; |
| 886 | 887 | ||
| 887 | #ifdef FBCON_HAS_CFB16 | ||
| 888 | static u16 fbcon_cfb16_cmap[16]; | ||
| 889 | #endif | ||
| 890 | |||
| 891 | static inline int hxx_prescale(struct falcon_hw *hw) | 888 | static inline int hxx_prescale(struct falcon_hw *hw) |
| 892 | { | 889 | { |
| 893 | return hw->ste_mode ? 16 | 890 | return hw->ste_mode ? 16 |
| @@ -918,7 +915,7 @@ static int falcon_encode_fix(struct fb_fix_screeninfo *fix, | |||
| 918 | fix->visual = FB_VISUAL_TRUECOLOR; | 915 | fix->visual = FB_VISUAL_TRUECOLOR; |
| 919 | fix->xpanstep = 2; | 916 | fix->xpanstep = 2; |
| 920 | } | 917 | } |
| 921 | fix->line_length = 0; | 918 | fix->line_length = par->next_line; |
| 922 | fix->accel = FB_ACCEL_ATARIBLITT; | 919 | fix->accel = FB_ACCEL_ATARIBLITT; |
| 923 | return 0; | 920 | return 0; |
| 924 | } | 921 | } |
| @@ -1394,14 +1391,7 @@ set_screen_base: | |||
| 1394 | par->screen_base = screen_base + var->yoffset * linelen; | 1391 | par->screen_base = screen_base + var->yoffset * linelen; |
| 1395 | par->hw.falcon.xoffset = 0; | 1392 | par->hw.falcon.xoffset = 0; |
| 1396 | 1393 | ||
| 1397 | // FIXME!!! sort of works, no crash | ||
| 1398 | //par->next_line = linelen; | ||
| 1399 | //par->next_plane = yres_virtual * linelen; | ||
| 1400 | par->next_line = linelen; | 1394 | par->next_line = linelen; |
| 1401 | par->next_plane = 2; | ||
| 1402 | // crashes | ||
| 1403 | //par->next_plane = linelen; | ||
| 1404 | //par->next_line = yres_virtual * linelen; | ||
| 1405 | 1395 | ||
| 1406 | return 0; | 1396 | return 0; |
| 1407 | } | 1397 | } |
| @@ -1735,10 +1725,10 @@ static int falcon_setcolreg(unsigned int regno, unsigned int red, | |||
| 1735 | (((red & 0xe000) >> 13) | ((red & 0x1000) >> 12) << 8) | | 1725 | (((red & 0xe000) >> 13) | ((red & 0x1000) >> 12) << 8) | |
| 1736 | (((green & 0xe000) >> 13) | ((green & 0x1000) >> 12) << 4) | | 1726 | (((green & 0xe000) >> 13) | ((green & 0x1000) >> 12) << 4) | |
| 1737 | ((blue & 0xe000) >> 13) | ((blue & 0x1000) >> 12); | 1727 | ((blue & 0xe000) >> 13) | ((blue & 0x1000) >> 12); |
| 1738 | #ifdef FBCON_HAS_CFB16 | 1728 | #ifdef ATAFB_FALCON |
| 1739 | fbcon_cfb16_cmap[regno] = ((red & 0xf800) | | 1729 | ((u32 *)info->pseudo_palette)[regno] = ((red & 0xf800) | |
| 1740 | ((green & 0xfc00) >> 5) | | 1730 | ((green & 0xfc00) >> 5) | |
| 1741 | ((blue & 0xf800) >> 11)); | 1731 | ((blue & 0xf800) >> 11)); |
| 1742 | #endif | 1732 | #endif |
| 1743 | } | 1733 | } |
| 1744 | return 0; | 1734 | return 0; |
| @@ -1852,7 +1842,7 @@ static int stste_encode_fix(struct fb_fix_screeninfo *fix, | |||
| 1852 | fix->ypanstep = 0; | 1842 | fix->ypanstep = 0; |
| 1853 | } | 1843 | } |
| 1854 | fix->ywrapstep = 0; | 1844 | fix->ywrapstep = 0; |
| 1855 | fix->line_length = 0; | 1845 | fix->line_length = par->next_line; |
| 1856 | fix->accel = FB_ACCEL_ATARIBLITT; | 1846 | fix->accel = FB_ACCEL_ATARIBLITT; |
| 1857 | return 0; | 1847 | return 0; |
| 1858 | } | 1848 | } |
| @@ -1910,6 +1900,7 @@ static int stste_decode_var(struct fb_var_screeninfo *var, | |||
| 1910 | return -EINVAL; | 1900 | return -EINVAL; |
| 1911 | par->yres_virtual = yres_virtual; | 1901 | par->yres_virtual = yres_virtual; |
| 1912 | par->screen_base = screen_base + var->yoffset * linelen; | 1902 | par->screen_base = screen_base + var->yoffset * linelen; |
| 1903 | par->next_line = linelen; | ||
| 1913 | return 0; | 1904 | return 0; |
| 1914 | } | 1905 | } |
| 1915 | 1906 | ||
| @@ -2169,7 +2160,7 @@ static int ext_encode_fix(struct fb_fix_screeninfo *fix, struct atafb_par *par) | |||
| 2169 | fix->xpanstep = 0; | 2160 | fix->xpanstep = 0; |
| 2170 | fix->ypanstep = 0; | 2161 | fix->ypanstep = 0; |
| 2171 | fix->ywrapstep = 0; | 2162 | fix->ywrapstep = 0; |
| 2172 | fix->line_length = 0; | 2163 | fix->line_length = par->next_line; |
| 2173 | return 0; | 2164 | return 0; |
| 2174 | } | 2165 | } |
| 2175 | 2166 | ||
| @@ -2184,6 +2175,8 @@ static int ext_decode_var(struct fb_var_screeninfo *var, struct atafb_par *par) | |||
| 2184 | var->xoffset > 0 || | 2175 | var->xoffset > 0 || |
| 2185 | var->yoffset > 0) | 2176 | var->yoffset > 0) |
| 2186 | return -EINVAL; | 2177 | return -EINVAL; |
| 2178 | |||
| 2179 | par->next_line = external_xres_virtual * external_depth / 8; | ||
| 2187 | return 0; | 2180 | return 0; |
| 2188 | } | 2181 | } |
| 2189 | 2182 | ||
| @@ -2443,42 +2436,6 @@ static void atafb_set_disp(struct fb_info *info) | |||
| 2443 | atafb_get_fix(&info->fix, info); | 2436 | atafb_get_fix(&info->fix, info); |
| 2444 | 2437 | ||
| 2445 | info->screen_base = (void *)info->fix.smem_start; | 2438 | info->screen_base = (void *)info->fix.smem_start; |
| 2446 | |||
| 2447 | switch (info->fix.type) { | ||
| 2448 | case FB_TYPE_INTERLEAVED_PLANES: | ||
| 2449 | switch (info->var.bits_per_pixel) { | ||
| 2450 | case 2: | ||
| 2451 | // display->dispsw = &fbcon_iplan2p2; | ||
| 2452 | break; | ||
| 2453 | case 4: | ||
| 2454 | // display->dispsw = &fbcon_iplan2p4; | ||
| 2455 | break; | ||
| 2456 | case 8: | ||
| 2457 | // display->dispsw = &fbcon_iplan2p8; | ||
| 2458 | break; | ||
| 2459 | } | ||
| 2460 | break; | ||
| 2461 | case FB_TYPE_PACKED_PIXELS: | ||
| 2462 | switch (info->var.bits_per_pixel) { | ||
| 2463 | #ifdef FBCON_HAS_MFB | ||
| 2464 | case 1: | ||
| 2465 | // display->dispsw = &fbcon_mfb; | ||
| 2466 | break; | ||
| 2467 | #endif | ||
| 2468 | #ifdef FBCON_HAS_CFB8 | ||
| 2469 | case 8: | ||
| 2470 | // display->dispsw = &fbcon_cfb8; | ||
| 2471 | break; | ||
| 2472 | #endif | ||
| 2473 | #ifdef FBCON_HAS_CFB16 | ||
| 2474 | case 16: | ||
| 2475 | // display->dispsw = &fbcon_cfb16; | ||
| 2476 | // display->dispsw_data = fbcon_cfb16_cmap; | ||
| 2477 | break; | ||
| 2478 | #endif | ||
| 2479 | } | ||
| 2480 | break; | ||
| 2481 | } | ||
| 2482 | } | 2439 | } |
| 2483 | 2440 | ||
| 2484 | static int atafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, | 2441 | static int atafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, |
| @@ -2549,6 +2506,13 @@ static void atafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) | |||
| 2549 | if (!rect->width || !rect->height) | 2506 | if (!rect->width || !rect->height) |
| 2550 | return; | 2507 | return; |
| 2551 | 2508 | ||
| 2509 | #ifdef ATAFB_FALCON | ||
| 2510 | if (info->var.bits_per_pixel == 16) { | ||
| 2511 | cfb_fillrect(info, rect); | ||
| 2512 | return; | ||
| 2513 | } | ||
| 2514 | #endif | ||
| 2515 | |||
| 2552 | /* | 2516 | /* |
| 2553 | * We could use hardware clipping but on many cards you get around | 2517 | * We could use hardware clipping but on many cards you get around |
| 2554 | * hardware clipping by writing to framebuffer directly. | 2518 | * hardware clipping by writing to framebuffer directly. |
| @@ -2583,6 +2547,13 @@ static void atafb_copyarea(struct fb_info *info, const struct fb_copyarea *area) | |||
| 2583 | u32 dx, dy, sx, sy, width, height; | 2547 | u32 dx, dy, sx, sy, width, height; |
| 2584 | int rev_copy = 0; | 2548 | int rev_copy = 0; |
| 2585 | 2549 | ||
| 2550 | #ifdef ATAFB_FALCON | ||
| 2551 | if (info->var.bits_per_pixel == 16) { | ||
| 2552 | cfb_copyarea(info, area); | ||
| 2553 | return; | ||
| 2554 | } | ||
| 2555 | #endif | ||
| 2556 | |||
| 2586 | /* clip the destination */ | 2557 | /* clip the destination */ |
| 2587 | x2 = area->dx + area->width; | 2558 | x2 = area->dx + area->width; |
| 2588 | y2 = area->dy + area->height; | 2559 | y2 = area->dy + area->height; |
| @@ -2632,6 +2603,13 @@ static void atafb_imageblit(struct fb_info *info, const struct fb_image *image) | |||
| 2632 | const char *src; | 2603 | const char *src; |
| 2633 | u32 dx, dy, width, height, pitch; | 2604 | u32 dx, dy, width, height, pitch; |
| 2634 | 2605 | ||
| 2606 | #ifdef ATAFB_FALCON | ||
| 2607 | if (info->var.bits_per_pixel == 16) { | ||
| 2608 | cfb_imageblit(info, image); | ||
| 2609 | return; | ||
| 2610 | } | ||
| 2611 | #endif | ||
| 2612 | |||
| 2635 | /* | 2613 | /* |
| 2636 | * We could use hardware clipping but on many cards you get around | 2614 | * We could use hardware clipping but on many cards you get around |
| 2637 | * hardware clipping by writing to framebuffer directly like we are | 2615 | * hardware clipping by writing to framebuffer directly like we are |
| @@ -2676,10 +2654,9 @@ static void atafb_imageblit(struct fb_info *info, const struct fb_image *image) | |||
| 2676 | src += pitch; | 2654 | src += pitch; |
| 2677 | } | 2655 | } |
| 2678 | } else { | 2656 | } else { |
| 2679 | // only used for logo; broken | 2657 | c2p_iplan2(info->screen_base, image->data, dx, dy, width, |
| 2680 | c2p(info->screen_base, image->data, dx, dy, width, height, | 2658 | height, par->next_line, image->width, |
| 2681 | par->next_line, par->next_plane, image->width, | 2659 | info->var.bits_per_pixel); |
| 2682 | info->var.bits_per_pixel); | ||
| 2683 | } | 2660 | } |
| 2684 | } | 2661 | } |
| 2685 | 2662 | ||
| @@ -3098,8 +3075,7 @@ int __init atafb_setup(char *options) | |||
| 3098 | 3075 | ||
| 3099 | int __init atafb_init(void) | 3076 | int __init atafb_init(void) |
| 3100 | { | 3077 | { |
| 3101 | int pad; | 3078 | int pad, detected_mode, error; |
| 3102 | int detected_mode; | ||
| 3103 | unsigned int defmode = 0; | 3079 | unsigned int defmode = 0; |
| 3104 | unsigned long mem_req; | 3080 | unsigned long mem_req; |
| 3105 | 3081 | ||
| @@ -3139,8 +3115,12 @@ int __init atafb_init(void) | |||
| 3139 | printk("atafb_init: initializing Falcon hw\n"); | 3115 | printk("atafb_init: initializing Falcon hw\n"); |
| 3140 | fbhw = &falcon_switch; | 3116 | fbhw = &falcon_switch; |
| 3141 | atafb_ops.fb_setcolreg = &falcon_setcolreg; | 3117 | atafb_ops.fb_setcolreg = &falcon_setcolreg; |
| 3142 | request_irq(IRQ_AUTO_4, falcon_vbl_switcher, IRQ_TYPE_PRIO, | 3118 | error = request_irq(IRQ_AUTO_4, falcon_vbl_switcher, |
| 3143 | "framebuffer/modeswitch", falcon_vbl_switcher); | 3119 | IRQ_TYPE_PRIO, |
| 3120 | "framebuffer/modeswitch", | ||
| 3121 | falcon_vbl_switcher); | ||
| 3122 | if (error) | ||
| 3123 | return error; | ||
| 3144 | defmode = DEFMODE_F30; | 3124 | defmode = DEFMODE_F30; |
| 3145 | break; | 3125 | break; |
| 3146 | } | 3126 | } |
| @@ -3225,6 +3205,10 @@ int __init atafb_init(void) | |||
| 3225 | // tries to read from HW which may not be initialized yet | 3205 | // tries to read from HW which may not be initialized yet |
| 3226 | // so set sane var first, then call atafb_set_par | 3206 | // so set sane var first, then call atafb_set_par |
| 3227 | atafb_get_var(&fb_info.var, &fb_info); | 3207 | atafb_get_var(&fb_info.var, &fb_info); |
| 3208 | |||
| 3209 | #ifdef ATAFB_FALCON | ||
| 3210 | fb_info.pseudo_palette = current_par.hw.falcon.pseudo_palette; | ||
| 3211 | #endif | ||
| 3228 | fb_info.flags = FBINFO_FLAG_DEFAULT; | 3212 | fb_info.flags = FBINFO_FLAG_DEFAULT; |
| 3229 | 3213 | ||
| 3230 | if (!fb_find_mode(&fb_info.var, &fb_info, mode_option, atafb_modedb, | 3214 | if (!fb_find_mode(&fb_info.var, &fb_info, mode_option, atafb_modedb, |
diff --git a/drivers/video/c2p.c b/drivers/video/c2p.c deleted file mode 100644 index 376bc07ff952..000000000000 --- a/drivers/video/c2p.c +++ /dev/null | |||
| @@ -1,232 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Fast C2P (Chunky-to-Planar) Conversion | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003 Geert Uytterhoeven | ||
| 5 | * | ||
| 6 | * NOTES: | ||
| 7 | * - This code was inspired by Scout's C2P tutorial | ||
| 8 | * - It assumes to run on a big endian system | ||
| 9 | * | ||
| 10 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 11 | * License. See the file COPYING in the main directory of this archive | ||
| 12 | * for more details. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include <linux/module.h> | ||
| 16 | #include <linux/string.h> | ||
| 17 | #include "c2p.h" | ||
| 18 | |||
| 19 | |||
| 20 | /* | ||
| 21 | * Basic transpose step | ||
| 22 | */ | ||
| 23 | |||
| 24 | #define _transp(d, i1, i2, shift, mask) \ | ||
| 25 | do { \ | ||
| 26 | u32 t = (d[i1] ^ (d[i2] >> shift)) & mask; \ | ||
| 27 | d[i1] ^= t; \ | ||
| 28 | d[i2] ^= t << shift; \ | ||
| 29 | } while (0) | ||
| 30 | |||
| 31 | static inline u32 get_mask(int n) | ||
| 32 | { | ||
| 33 | switch (n) { | ||
| 34 | case 1: | ||
| 35 | return 0x55555555; | ||
| 36 | break; | ||
| 37 | |||
| 38 | case 2: | ||
| 39 | return 0x33333333; | ||
| 40 | break; | ||
| 41 | |||
| 42 | case 4: | ||
| 43 | return 0x0f0f0f0f; | ||
| 44 | break; | ||
| 45 | |||
| 46 | case 8: | ||
| 47 | return 0x00ff00ff; | ||
| 48 | break; | ||
| 49 | |||
| 50 | case 16: | ||
| 51 | return 0x0000ffff; | ||
| 52 | break; | ||
| 53 | } | ||
| 54 | return 0; | ||
| 55 | } | ||
| 56 | |||
| 57 | #define transp_nx1(d, n) \ | ||
| 58 | do { \ | ||
| 59 | u32 mask = get_mask(n); \ | ||
| 60 | /* First block */ \ | ||
| 61 | _transp(d, 0, 1, n, mask); \ | ||
| 62 | /* Second block */ \ | ||
| 63 | _transp(d, 2, 3, n, mask); \ | ||
| 64 | /* Third block */ \ | ||
| 65 | _transp(d, 4, 5, n, mask); \ | ||
| 66 | /* Fourth block */ \ | ||
| 67 | _transp(d, 6, 7, n, mask); \ | ||
| 68 | } while (0) | ||
| 69 | |||
| 70 | #define transp_nx2(d, n) \ | ||
| 71 | do { \ | ||
| 72 | u32 mask = get_mask(n); \ | ||
| 73 | /* First block */ \ | ||
| 74 | _transp(d, 0, 2, n, mask); \ | ||
| 75 | _transp(d, 1, 3, n, mask); \ | ||
| 76 | /* Second block */ \ | ||
| 77 | _transp(d, 4, 6, n, mask); \ | ||
| 78 | _transp(d, 5, 7, n, mask); \ | ||
| 79 | } while (0) | ||
| 80 | |||
| 81 | #define transp_nx4(d, n) \ | ||
| 82 | do { \ | ||
| 83 | u32 mask = get_mask(n); \ | ||
| 84 | _transp(d, 0, 4, n, mask); \ | ||
| 85 | _transp(d, 1, 5, n, mask); \ | ||
| 86 | _transp(d, 2, 6, n, mask); \ | ||
| 87 | _transp(d, 3, 7, n, mask); \ | ||
| 88 | } while (0) | ||
| 89 | |||
| 90 | #define transp(d, n, m) transp_nx ## m(d, n) | ||
| 91 | |||
| 92 | |||
| 93 | /* | ||
| 94 | * Perform a full C2P step on 32 8-bit pixels, stored in 8 32-bit words | ||
| 95 | * containing | ||
| 96 | * - 32 8-bit chunky pixels on input | ||
| 97 | * - permuted planar data on output | ||
| 98 | */ | ||
| 99 | |||
| 100 | static void c2p_8bpp(u32 d[8]) | ||
| 101 | { | ||
| 102 | transp(d, 16, 4); | ||
| 103 | transp(d, 8, 2); | ||
| 104 | transp(d, 4, 1); | ||
| 105 | transp(d, 2, 4); | ||
| 106 | transp(d, 1, 2); | ||
| 107 | } | ||
| 108 | |||
| 109 | |||
| 110 | /* | ||
| 111 | * Array containing the permution indices of the planar data after c2p | ||
| 112 | */ | ||
| 113 | |||
| 114 | static const int perm_c2p_8bpp[8] = { 7, 5, 3, 1, 6, 4, 2, 0 }; | ||
| 115 | |||
| 116 | |||
| 117 | /* | ||
| 118 | * Compose two values, using a bitmask as decision value | ||
| 119 | * This is equivalent to (a & mask) | (b & ~mask) | ||
| 120 | */ | ||
| 121 | |||
| 122 | static inline unsigned long comp(unsigned long a, unsigned long b, | ||
| 123 | unsigned long mask) | ||
| 124 | { | ||
| 125 | return ((a ^ b) & mask) ^ b; | ||
| 126 | } | ||
| 127 | |||
| 128 | |||
| 129 | /* | ||
| 130 | * Store a full block of planar data after c2p conversion | ||
| 131 | */ | ||
| 132 | |||
| 133 | static inline void store_planar(char *dst, u32 dst_inc, u32 bpp, u32 d[8]) | ||
| 134 | { | ||
| 135 | int i; | ||
| 136 | |||
| 137 | for (i = 0; i < bpp; i++, dst += dst_inc) | ||
| 138 | *(u32 *)dst = d[perm_c2p_8bpp[i]]; | ||
| 139 | } | ||
| 140 | |||
| 141 | |||
| 142 | /* | ||
| 143 | * Store a partial block of planar data after c2p conversion | ||
| 144 | */ | ||
| 145 | |||
| 146 | static inline void store_planar_masked(char *dst, u32 dst_inc, u32 bpp, | ||
| 147 | u32 d[8], u32 mask) | ||
| 148 | { | ||
| 149 | int i; | ||
| 150 | |||
| 151 | for (i = 0; i < bpp; i++, dst += dst_inc) | ||
| 152 | *(u32 *)dst = comp(d[perm_c2p_8bpp[i]], *(u32 *)dst, mask); | ||
| 153 | } | ||
| 154 | |||
| 155 | |||
| 156 | /* | ||
| 157 | * c2p - Copy 8-bit chunky image data to a planar frame buffer | ||
| 158 | * @dst: Starting address of the planar frame buffer | ||
| 159 | * @dx: Horizontal destination offset (in pixels) | ||
| 160 | * @dy: Vertical destination offset (in pixels) | ||
| 161 | * @width: Image width (in pixels) | ||
| 162 | * @height: Image height (in pixels) | ||
| 163 | * @dst_nextline: Frame buffer offset to the next line (in bytes) | ||
| 164 | * @dst_nextplane: Frame buffer offset to the next plane (in bytes) | ||
| 165 | * @src_nextline: Image offset to the next line (in bytes) | ||
| 166 | * @bpp: Bits per pixel of the planar frame buffer (1-8) | ||
| 167 | */ | ||
| 168 | |||
| 169 | void c2p(u8 *dst, const u8 *src, u32 dx, u32 dy, u32 width, u32 height, | ||
| 170 | u32 dst_nextline, u32 dst_nextplane, u32 src_nextline, u32 bpp) | ||
| 171 | { | ||
| 172 | int dst_idx; | ||
| 173 | u32 d[8], first, last, w; | ||
| 174 | const u8 *c; | ||
| 175 | u8 *p; | ||
| 176 | |||
| 177 | dst += dy*dst_nextline+(dx & ~31); | ||
| 178 | dst_idx = dx % 32; | ||
| 179 | first = ~0UL >> dst_idx; | ||
| 180 | last = ~(~0UL >> ((dst_idx+width) % 32)); | ||
| 181 | while (height--) { | ||
| 182 | c = src; | ||
| 183 | p = dst; | ||
| 184 | w = width; | ||
| 185 | if (dst_idx+width <= 32) { | ||
| 186 | /* Single destination word */ | ||
| 187 | first &= last; | ||
| 188 | memset(d, 0, sizeof(d)); | ||
| 189 | memcpy((u8 *)d+dst_idx, c, width); | ||
| 190 | c += width; | ||
| 191 | c2p_8bpp(d); | ||
| 192 | store_planar_masked(p, dst_nextplane, bpp, d, first); | ||
| 193 | p += 4; | ||
| 194 | } else { | ||
| 195 | /* Multiple destination words */ | ||
| 196 | w = width; | ||
| 197 | /* Leading bits */ | ||
| 198 | if (dst_idx) { | ||
| 199 | w = 32 - dst_idx; | ||
| 200 | memset(d, 0, dst_idx); | ||
| 201 | memcpy((u8 *)d+dst_idx, c, w); | ||
| 202 | c += w; | ||
| 203 | c2p_8bpp(d); | ||
| 204 | store_planar_masked(p, dst_nextplane, bpp, d, first); | ||
| 205 | p += 4; | ||
| 206 | w = width-w; | ||
| 207 | } | ||
| 208 | /* Main chunk */ | ||
| 209 | while (w >= 32) { | ||
| 210 | memcpy(d, c, 32); | ||
| 211 | c += 32; | ||
| 212 | c2p_8bpp(d); | ||
| 213 | store_planar(p, dst_nextplane, bpp, d); | ||
| 214 | p += 4; | ||
| 215 | w -= 32; | ||
| 216 | } | ||
| 217 | /* Trailing bits */ | ||
| 218 | w %= 32; | ||
| 219 | if (w > 0) { | ||
| 220 | memcpy(d, c, w); | ||
| 221 | memset((u8 *)d+w, 0, 32-w); | ||
| 222 | c2p_8bpp(d); | ||
| 223 | store_planar_masked(p, dst_nextplane, bpp, d, last); | ||
| 224 | } | ||
| 225 | } | ||
| 226 | src += src_nextline; | ||
| 227 | dst += dst_nextline; | ||
| 228 | } | ||
| 229 | } | ||
| 230 | EXPORT_SYMBOL_GPL(c2p); | ||
| 231 | |||
| 232 | MODULE_LICENSE("GPL"); | ||
diff --git a/drivers/video/c2p.h b/drivers/video/c2p.h index c77cbf17e043..6c38d40427d8 100644 --- a/drivers/video/c2p.h +++ b/drivers/video/c2p.h | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Fast C2P (Chunky-to-Planar) Conversion | 2 | * Fast C2P (Chunky-to-Planar) Conversion |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2003 Geert Uytterhoeven | 4 | * Copyright (C) 2003-2008 Geert Uytterhoeven |
| 5 | * | 5 | * |
| 6 | * This file is subject to the terms and conditions of the GNU General Public | 6 | * This file is subject to the terms and conditions of the GNU General Public |
| 7 | * License. See the file COPYING in the main directory of this archive | 7 | * License. See the file COPYING in the main directory of this archive |
| @@ -10,7 +10,10 @@ | |||
| 10 | 10 | ||
| 11 | #include <linux/types.h> | 11 | #include <linux/types.h> |
| 12 | 12 | ||
| 13 | extern void c2p(u8 *dst, const u8 *src, u32 dx, u32 dy, u32 width, u32 height, | 13 | extern void c2p_planar(void *dst, const void *src, u32 dx, u32 dy, u32 width, |
| 14 | u32 dst_nextline, u32 dst_nextplane, u32 src_nextline, | 14 | u32 height, u32 dst_nextline, u32 dst_nextplane, |
| 15 | u32 bpp); | 15 | u32 src_nextline, u32 bpp); |
| 16 | 16 | ||
| 17 | extern void c2p_iplan2(void *dst, const void *src, u32 dx, u32 dy, u32 width, | ||
| 18 | u32 height, u32 dst_nextline, u32 src_nextline, | ||
| 19 | u32 bpp); | ||
diff --git a/drivers/video/c2p_core.h b/drivers/video/c2p_core.h new file mode 100644 index 000000000000..e1035a865fb9 --- /dev/null +++ b/drivers/video/c2p_core.h | |||
| @@ -0,0 +1,153 @@ | |||
| 1 | /* | ||
| 2 | * Fast C2P (Chunky-to-Planar) Conversion | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003-2008 Geert Uytterhoeven | ||
| 5 | * | ||
| 6 | * NOTES: | ||
| 7 | * - This code was inspired by Scout's C2P tutorial | ||
| 8 | * - It assumes to run on a big endian system | ||
| 9 | * | ||
| 10 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 11 | * License. See the file COPYING in the main directory of this archive | ||
| 12 | * for more details. | ||
| 13 | */ | ||
| 14 | |||
| 15 | |||
| 16 | /* | ||
| 17 | * Basic transpose step | ||
| 18 | */ | ||
| 19 | |||
| 20 | static inline void _transp(u32 d[], unsigned int i1, unsigned int i2, | ||
| 21 | unsigned int shift, u32 mask) | ||
| 22 | { | ||
| 23 | u32 t = (d[i1] ^ (d[i2] >> shift)) & mask; | ||
| 24 | |||
| 25 | d[i1] ^= t; | ||
| 26 | d[i2] ^= t << shift; | ||
| 27 | } | ||
| 28 | |||
| 29 | |||
| 30 | extern void c2p_unsupported(void); | ||
| 31 | |||
| 32 | static inline u32 get_mask(unsigned int n) | ||
| 33 | { | ||
| 34 | switch (n) { | ||
| 35 | case 1: | ||
| 36 | return 0x55555555; | ||
| 37 | |||
| 38 | case 2: | ||
| 39 | return 0x33333333; | ||
| 40 | |||
| 41 | case 4: | ||
| 42 | return 0x0f0f0f0f; | ||
| 43 | |||
| 44 | case 8: | ||
| 45 | return 0x00ff00ff; | ||
| 46 | |||
| 47 | case 16: | ||
| 48 | return 0x0000ffff; | ||
| 49 | } | ||
| 50 | |||
| 51 | c2p_unsupported(); | ||
| 52 | return 0; | ||
| 53 | } | ||
| 54 | |||
| 55 | |||
| 56 | /* | ||
| 57 | * Transpose operations on 8 32-bit words | ||
| 58 | */ | ||
| 59 | |||
| 60 | static inline void transp8(u32 d[], unsigned int n, unsigned int m) | ||
| 61 | { | ||
| 62 | u32 mask = get_mask(n); | ||
| 63 | |||
| 64 | switch (m) { | ||
| 65 | case 1: | ||
| 66 | /* First n x 1 block */ | ||
| 67 | _transp(d, 0, 1, n, mask); | ||
| 68 | /* Second n x 1 block */ | ||
| 69 | _transp(d, 2, 3, n, mask); | ||
| 70 | /* Third n x 1 block */ | ||
| 71 | _transp(d, 4, 5, n, mask); | ||
| 72 | /* Fourth n x 1 block */ | ||
| 73 | _transp(d, 6, 7, n, mask); | ||
| 74 | return; | ||
| 75 | |||
| 76 | case 2: | ||
| 77 | /* First n x 2 block */ | ||
| 78 | _transp(d, 0, 2, n, mask); | ||
| 79 | _transp(d, 1, 3, n, mask); | ||
| 80 | /* Second n x 2 block */ | ||
| 81 | _transp(d, 4, 6, n, mask); | ||
| 82 | _transp(d, 5, 7, n, mask); | ||
| 83 | return; | ||
| 84 | |||
| 85 | case 4: | ||
| 86 | /* Single n x 4 block */ | ||
| 87 | _transp(d, 0, 4, n, mask); | ||
| 88 | _transp(d, 1, 5, n, mask); | ||
| 89 | _transp(d, 2, 6, n, mask); | ||
| 90 | _transp(d, 3, 7, n, mask); | ||
| 91 | return; | ||
| 92 | } | ||
| 93 | |||
| 94 | c2p_unsupported(); | ||
| 95 | } | ||
| 96 | |||
| 97 | |||
| 98 | /* | ||
| 99 | * Transpose operations on 4 32-bit words | ||
| 100 | */ | ||
| 101 | |||
| 102 | static inline void transp4(u32 d[], unsigned int n, unsigned int m) | ||
| 103 | { | ||
| 104 | u32 mask = get_mask(n); | ||
| 105 | |||
| 106 | switch (m) { | ||
| 107 | case 1: | ||
| 108 | /* First n x 1 block */ | ||
| 109 | _transp(d, 0, 1, n, mask); | ||
| 110 | /* Second n x 1 block */ | ||
| 111 | _transp(d, 2, 3, n, mask); | ||
| 112 | return; | ||
| 113 | |||
| 114 | case 2: | ||
| 115 | /* Single n x 2 block */ | ||
| 116 | _transp(d, 0, 2, n, mask); | ||
| 117 | _transp(d, 1, 3, n, mask); | ||
| 118 | return; | ||
| 119 | } | ||
| 120 | |||
| 121 | c2p_unsupported(); | ||
| 122 | } | ||
| 123 | |||
| 124 | |||
| 125 | /* | ||
| 126 | * Transpose operations on 4 32-bit words (reverse order) | ||
| 127 | */ | ||
| 128 | |||
| 129 | static inline void transp4x(u32 d[], unsigned int n, unsigned int m) | ||
| 130 | { | ||
| 131 | u32 mask = get_mask(n); | ||
| 132 | |||
| 133 | switch (m) { | ||
| 134 | case 2: | ||
| 135 | /* Single n x 2 block */ | ||
| 136 | _transp(d, 2, 0, n, mask); | ||
| 137 | _transp(d, 3, 1, n, mask); | ||
| 138 | return; | ||
| 139 | } | ||
| 140 | |||
| 141 | c2p_unsupported(); | ||
| 142 | } | ||
| 143 | |||
| 144 | |||
| 145 | /* | ||
| 146 | * Compose two values, using a bitmask as decision value | ||
| 147 | * This is equivalent to (a & mask) | (b & ~mask) | ||
| 148 | */ | ||
| 149 | |||
| 150 | static inline u32 comp(u32 a, u32 b, u32 mask) | ||
| 151 | { | ||
| 152 | return ((a ^ b) & mask) ^ b; | ||
| 153 | } | ||
diff --git a/drivers/video/c2p_iplan2.c b/drivers/video/c2p_iplan2.c new file mode 100644 index 000000000000..19156dc6158c --- /dev/null +++ b/drivers/video/c2p_iplan2.c | |||
| @@ -0,0 +1,153 @@ | |||
| 1 | /* | ||
| 2 | * Fast C2P (Chunky-to-Planar) Conversion | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003-2008 Geert Uytterhoeven | ||
| 5 | * | ||
| 6 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 7 | * License. See the file COPYING in the main directory of this archive | ||
| 8 | * for more details. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/module.h> | ||
| 12 | #include <linux/string.h> | ||
| 13 | |||
| 14 | #include <asm/unaligned.h> | ||
| 15 | |||
| 16 | #include "c2p.h" | ||
| 17 | #include "c2p_core.h" | ||
| 18 | |||
| 19 | |||
| 20 | /* | ||
| 21 | * Perform a full C2P step on 16 8-bit pixels, stored in 4 32-bit words | ||
| 22 | * containing | ||
| 23 | * - 16 8-bit chunky pixels on input | ||
| 24 | * - permutated planar data (2 planes per 32-bit word) on output | ||
| 25 | */ | ||
| 26 | |||
| 27 | static void c2p_16x8(u32 d[4]) | ||
| 28 | { | ||
| 29 | transp4(d, 8, 2); | ||
| 30 | transp4(d, 1, 2); | ||
| 31 | transp4x(d, 16, 2); | ||
| 32 | transp4x(d, 2, 2); | ||
| 33 | transp4(d, 4, 1); | ||
| 34 | } | ||
| 35 | |||
| 36 | |||
| 37 | /* | ||
| 38 | * Array containing the permutation indices of the planar data after c2p | ||
| 39 | */ | ||
| 40 | |||
| 41 | static const int perm_c2p_16x8[4] = { 1, 3, 0, 2 }; | ||
| 42 | |||
| 43 | |||
| 44 | /* | ||
| 45 | * Store a full block of iplan2 data after c2p conversion | ||
| 46 | */ | ||
| 47 | |||
| 48 | static inline void store_iplan2(void *dst, u32 bpp, u32 d[4]) | ||
| 49 | { | ||
| 50 | int i; | ||
| 51 | |||
| 52 | for (i = 0; i < bpp/2; i++, dst += 4) | ||
| 53 | put_unaligned_be32(d[perm_c2p_16x8[i]], dst); | ||
| 54 | } | ||
| 55 | |||
| 56 | |||
| 57 | /* | ||
| 58 | * Store a partial block of iplan2 data after c2p conversion | ||
| 59 | */ | ||
| 60 | |||
| 61 | static inline void store_iplan2_masked(void *dst, u32 bpp, u32 d[4], u32 mask) | ||
| 62 | { | ||
| 63 | int i; | ||
| 64 | |||
| 65 | for (i = 0; i < bpp/2; i++, dst += 4) | ||
| 66 | put_unaligned_be32(comp(d[perm_c2p_16x8[i]], | ||
| 67 | get_unaligned_be32(dst), mask), | ||
| 68 | dst); | ||
| 69 | } | ||
| 70 | |||
| 71 | |||
| 72 | /* | ||
| 73 | * c2p_iplan2 - Copy 8-bit chunky image data to an interleaved planar | ||
| 74 | * frame buffer with 2 bytes of interleave | ||
| 75 | * @dst: Starting address of the planar frame buffer | ||
| 76 | * @dx: Horizontal destination offset (in pixels) | ||
| 77 | * @dy: Vertical destination offset (in pixels) | ||
| 78 | * @width: Image width (in pixels) | ||
| 79 | * @height: Image height (in pixels) | ||
| 80 | * @dst_nextline: Frame buffer offset to the next line (in bytes) | ||
| 81 | * @src_nextline: Image offset to the next line (in bytes) | ||
| 82 | * @bpp: Bits per pixel of the planar frame buffer (2, 4, or 8) | ||
| 83 | */ | ||
| 84 | |||
| 85 | void c2p_iplan2(void *dst, const void *src, u32 dx, u32 dy, u32 width, | ||
| 86 | u32 height, u32 dst_nextline, u32 src_nextline, u32 bpp) | ||
| 87 | { | ||
| 88 | union { | ||
| 89 | u8 pixels[16]; | ||
| 90 | u32 words[4]; | ||
| 91 | } d; | ||
| 92 | u32 dst_idx, first, last, w; | ||
| 93 | const u8 *c; | ||
| 94 | void *p; | ||
| 95 | |||
| 96 | dst += dy*dst_nextline+(dx & ~15)*bpp; | ||
| 97 | dst_idx = dx % 16; | ||
| 98 | first = 0xffffU >> dst_idx; | ||
| 99 | first |= first << 16; | ||
| 100 | last = 0xffffU ^ (0xffffU >> ((dst_idx+width) % 16)); | ||
| 101 | last |= last << 16; | ||
| 102 | while (height--) { | ||
| 103 | c = src; | ||
| 104 | p = dst; | ||
| 105 | w = width; | ||
| 106 | if (dst_idx+width <= 16) { | ||
| 107 | /* Single destination word */ | ||
| 108 | first &= last; | ||
| 109 | memset(d.pixels, 0, sizeof(d)); | ||
| 110 | memcpy(d.pixels+dst_idx, c, width); | ||
| 111 | c += width; | ||
| 112 | c2p_16x8(d.words); | ||
| 113 | store_iplan2_masked(p, bpp, d.words, first); | ||
| 114 | p += bpp*2; | ||
| 115 | } else { | ||
| 116 | /* Multiple destination words */ | ||
| 117 | w = width; | ||
| 118 | /* Leading bits */ | ||
| 119 | if (dst_idx) { | ||
| 120 | w = 16 - dst_idx; | ||
| 121 | memset(d.pixels, 0, dst_idx); | ||
| 122 | memcpy(d.pixels+dst_idx, c, w); | ||
| 123 | c += w; | ||
| 124 | c2p_16x8(d.words); | ||
| 125 | store_iplan2_masked(p, bpp, d.words, first); | ||
| 126 | p += bpp*2; | ||
| 127 | w = width-w; | ||
| 128 | } | ||
| 129 | /* Main chunk */ | ||
| 130 | while (w >= 16) { | ||
| 131 | memcpy(d.pixels, c, 16); | ||
| 132 | c += 16; | ||
| 133 | c2p_16x8(d.words); | ||
| 134 | store_iplan2(p, bpp, d.words); | ||
| 135 | p += bpp*2; | ||
| 136 | w -= 16; | ||
| 137 | } | ||
| 138 | /* Trailing bits */ | ||
| 139 | w %= 16; | ||
| 140 | if (w > 0) { | ||
| 141 | memcpy(d.pixels, c, w); | ||
| 142 | memset(d.pixels+w, 0, 16-w); | ||
| 143 | c2p_16x8(d.words); | ||
| 144 | store_iplan2_masked(p, bpp, d.words, last); | ||
| 145 | } | ||
| 146 | } | ||
| 147 | src += src_nextline; | ||
| 148 | dst += dst_nextline; | ||
| 149 | } | ||
| 150 | } | ||
| 151 | EXPORT_SYMBOL_GPL(c2p_iplan2); | ||
| 152 | |||
| 153 | MODULE_LICENSE("GPL"); | ||
diff --git a/drivers/video/c2p_planar.c b/drivers/video/c2p_planar.c new file mode 100644 index 000000000000..ec7ac8526f06 --- /dev/null +++ b/drivers/video/c2p_planar.c | |||
| @@ -0,0 +1,156 @@ | |||
| 1 | /* | ||
| 2 | * Fast C2P (Chunky-to-Planar) Conversion | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003-2008 Geert Uytterhoeven | ||
| 5 | * | ||
| 6 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 7 | * License. See the file COPYING in the main directory of this archive | ||
| 8 | * for more details. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/module.h> | ||
| 12 | #include <linux/string.h> | ||
| 13 | |||
| 14 | #include <asm/unaligned.h> | ||
| 15 | |||
| 16 | #include "c2p.h" | ||
| 17 | #include "c2p_core.h" | ||
| 18 | |||
| 19 | |||
| 20 | /* | ||
| 21 | * Perform a full C2P step on 32 8-bit pixels, stored in 8 32-bit words | ||
| 22 | * containing | ||
| 23 | * - 32 8-bit chunky pixels on input | ||
| 24 | * - permutated planar data (1 plane per 32-bit word) on output | ||
| 25 | */ | ||
| 26 | |||
| 27 | static void c2p_32x8(u32 d[8]) | ||
| 28 | { | ||
| 29 | transp8(d, 16, 4); | ||
| 30 | transp8(d, 8, 2); | ||
| 31 | transp8(d, 4, 1); | ||
| 32 | transp8(d, 2, 4); | ||
| 33 | transp8(d, 1, 2); | ||
| 34 | } | ||
| 35 | |||
| 36 | |||
| 37 | /* | ||
| 38 | * Array containing the permutation indices of the planar data after c2p | ||
| 39 | */ | ||
| 40 | |||
| 41 | static const int perm_c2p_32x8[8] = { 7, 5, 3, 1, 6, 4, 2, 0 }; | ||
| 42 | |||
| 43 | |||
| 44 | /* | ||
| 45 | * Store a full block of planar data after c2p conversion | ||
| 46 | */ | ||
| 47 | |||
| 48 | static inline void store_planar(void *dst, u32 dst_inc, u32 bpp, u32 d[8]) | ||
| 49 | { | ||
| 50 | int i; | ||
| 51 | |||
| 52 | for (i = 0; i < bpp; i++, dst += dst_inc) | ||
| 53 | put_unaligned_be32(d[perm_c2p_32x8[i]], dst); | ||
| 54 | } | ||
| 55 | |||
| 56 | |||
| 57 | /* | ||
| 58 | * Store a partial block of planar data after c2p conversion | ||
| 59 | */ | ||
| 60 | |||
| 61 | static inline void store_planar_masked(void *dst, u32 dst_inc, u32 bpp, | ||
| 62 | u32 d[8], u32 mask) | ||
| 63 | { | ||
| 64 | int i; | ||
| 65 | |||
| 66 | for (i = 0; i < bpp; i++, dst += dst_inc) | ||
| 67 | put_unaligned_be32(comp(d[perm_c2p_32x8[i]], | ||
| 68 | get_unaligned_be32(dst), mask), | ||
| 69 | dst); | ||
| 70 | } | ||
| 71 | |||
| 72 | |||
| 73 | /* | ||
| 74 | * c2p_planar - Copy 8-bit chunky image data to a planar frame buffer | ||
| 75 | * @dst: Starting address of the planar frame buffer | ||
| 76 | * @dx: Horizontal destination offset (in pixels) | ||
| 77 | * @dy: Vertical destination offset (in pixels) | ||
| 78 | * @width: Image width (in pixels) | ||
| 79 | * @height: Image height (in pixels) | ||
| 80 | * @dst_nextline: Frame buffer offset to the next line (in bytes) | ||
| 81 | * @dst_nextplane: Frame buffer offset to the next plane (in bytes) | ||
| 82 | * @src_nextline: Image offset to the next line (in bytes) | ||
| 83 | * @bpp: Bits per pixel of the planar frame buffer (1-8) | ||
| 84 | */ | ||
| 85 | |||
| 86 | void c2p_planar(void *dst, const void *src, u32 dx, u32 dy, u32 width, | ||
| 87 | u32 height, u32 dst_nextline, u32 dst_nextplane, | ||
| 88 | u32 src_nextline, u32 bpp) | ||
| 89 | { | ||
| 90 | union { | ||
| 91 | u8 pixels[32]; | ||
| 92 | u32 words[8]; | ||
| 93 | } d; | ||
| 94 | u32 dst_idx, first, last, w; | ||
| 95 | const u8 *c; | ||
| 96 | void *p; | ||
| 97 | |||
| 98 | dst += dy*dst_nextline+(dx & ~31); | ||
| 99 | dst_idx = dx % 32; | ||
| 100 | first = 0xffffffffU >> dst_idx; | ||
| 101 | last = ~(0xffffffffU >> ((dst_idx+width) % 32)); | ||
| 102 | while (height--) { | ||
| 103 | c = src; | ||
| 104 | p = dst; | ||
| 105 | w = width; | ||
| 106 | if (dst_idx+width <= 32) { | ||
| 107 | /* Single destination word */ | ||
| 108 | first &= last; | ||
| 109 | memset(d.pixels, 0, sizeof(d)); | ||
| 110 | memcpy(d.pixels+dst_idx, c, width); | ||
| 111 | c += width; | ||
| 112 | c2p_32x8(d.words); | ||
| 113 | store_planar_masked(p, dst_nextplane, bpp, d.words, | ||
| 114 | first); | ||
| 115 | p += 4; | ||
| 116 | } else { | ||
| 117 | /* Multiple destination words */ | ||
| 118 | w = width; | ||
| 119 | /* Leading bits */ | ||
| 120 | if (dst_idx) { | ||
| 121 | w = 32 - dst_idx; | ||
| 122 | memset(d.pixels, 0, dst_idx); | ||
| 123 | memcpy(d.pixels+dst_idx, c, w); | ||
| 124 | c += w; | ||
| 125 | c2p_32x8(d.words); | ||
| 126 | store_planar_masked(p, dst_nextplane, bpp, | ||
| 127 | d.words, first); | ||
| 128 | p += 4; | ||
| 129 | w = width-w; | ||
| 130 | } | ||
| 131 | /* Main chunk */ | ||
| 132 | while (w >= 32) { | ||
| 133 | memcpy(d.pixels, c, 32); | ||
| 134 | c += 32; | ||
| 135 | c2p_32x8(d.words); | ||
| 136 | store_planar(p, dst_nextplane, bpp, d.words); | ||
| 137 | p += 4; | ||
| 138 | w -= 32; | ||
| 139 | } | ||
| 140 | /* Trailing bits */ | ||
| 141 | w %= 32; | ||
| 142 | if (w > 0) { | ||
| 143 | memcpy(d.pixels, c, w); | ||
| 144 | memset(d.pixels+w, 0, 32-w); | ||
| 145 | c2p_32x8(d.words); | ||
| 146 | store_planar_masked(p, dst_nextplane, bpp, | ||
| 147 | d.words, last); | ||
| 148 | } | ||
| 149 | } | ||
| 150 | src += src_nextline; | ||
| 151 | dst += dst_nextline; | ||
| 152 | } | ||
| 153 | } | ||
| 154 | EXPORT_SYMBOL_GPL(c2p_planar); | ||
| 155 | |||
| 156 | MODULE_LICENSE("GPL"); | ||
diff --git a/drivers/video/console/fbcon.c b/drivers/video/console/fbcon.c index 4bcff81b50e0..1657b9608b04 100644 --- a/drivers/video/console/fbcon.c +++ b/drivers/video/console/fbcon.c | |||
| @@ -78,13 +78,6 @@ | |||
| 78 | #include <asm/fb.h> | 78 | #include <asm/fb.h> |
| 79 | #include <asm/irq.h> | 79 | #include <asm/irq.h> |
| 80 | #include <asm/system.h> | 80 | #include <asm/system.h> |
| 81 | #ifdef CONFIG_ATARI | ||
| 82 | #include <asm/atariints.h> | ||
| 83 | #endif | ||
| 84 | #if defined(__mc68000__) | ||
| 85 | #include <asm/machdep.h> | ||
| 86 | #include <asm/setup.h> | ||
| 87 | #endif | ||
| 88 | 81 | ||
| 89 | #include "fbcon.h" | 82 | #include "fbcon.h" |
| 90 | 83 | ||
| @@ -155,9 +148,6 @@ static int fbcon_set_origin(struct vc_data *); | |||
| 155 | 148 | ||
| 156 | #define CURSOR_DRAW_DELAY (1) | 149 | #define CURSOR_DRAW_DELAY (1) |
| 157 | 150 | ||
| 158 | /* # VBL ints between cursor state changes */ | ||
| 159 | #define ATARI_CURSOR_BLINK_RATE (42) | ||
| 160 | |||
| 161 | static int vbl_cursor_cnt; | 151 | static int vbl_cursor_cnt; |
| 162 | static int fbcon_cursor_noblink; | 152 | static int fbcon_cursor_noblink; |
| 163 | 153 | ||
| @@ -403,20 +393,6 @@ static void fb_flashcursor(struct work_struct *work) | |||
| 403 | release_console_sem(); | 393 | release_console_sem(); |
| 404 | } | 394 | } |
| 405 | 395 | ||
| 406 | #ifdef CONFIG_ATARI | ||
| 407 | static int cursor_blink_rate; | ||
| 408 | static irqreturn_t fb_vbl_handler(int irq, void *dev_id) | ||
| 409 | { | ||
| 410 | struct fb_info *info = dev_id; | ||
| 411 | |||
| 412 | if (vbl_cursor_cnt && --vbl_cursor_cnt == 0) { | ||
| 413 | schedule_work(&info->queue); | ||
| 414 | vbl_cursor_cnt = cursor_blink_rate; | ||
| 415 | } | ||
| 416 | return IRQ_HANDLED; | ||
| 417 | } | ||
| 418 | #endif | ||
| 419 | |||
| 420 | static void cursor_timer_handler(unsigned long dev_addr) | 396 | static void cursor_timer_handler(unsigned long dev_addr) |
| 421 | { | 397 | { |
| 422 | struct fb_info *info = (struct fb_info *) dev_addr; | 398 | struct fb_info *info = (struct fb_info *) dev_addr; |
| @@ -1017,15 +993,6 @@ static const char *fbcon_startup(void) | |||
| 1017 | info->var.yres, | 993 | info->var.yres, |
| 1018 | info->var.bits_per_pixel); | 994 | info->var.bits_per_pixel); |
| 1019 | 995 | ||
| 1020 | #ifdef CONFIG_ATARI | ||
| 1021 | if (MACH_IS_ATARI) { | ||
| 1022 | cursor_blink_rate = ATARI_CURSOR_BLINK_RATE; | ||
| 1023 | (void)request_irq(IRQ_AUTO_4, fb_vbl_handler, | ||
| 1024 | IRQ_TYPE_PRIO, "framebuffer vbl", | ||
| 1025 | info); | ||
| 1026 | } | ||
| 1027 | #endif /* CONFIG_ATARI */ | ||
| 1028 | |||
| 1029 | fbcon_add_cursor_timer(info); | 996 | fbcon_add_cursor_timer(info); |
| 1030 | fbcon_has_exited = 0; | 997 | fbcon_has_exited = 0; |
| 1031 | return display_desc; | 998 | return display_desc; |
| @@ -3454,11 +3421,6 @@ static void fbcon_exit(void) | |||
| 3454 | if (fbcon_has_exited) | 3421 | if (fbcon_has_exited) |
| 3455 | return; | 3422 | return; |
| 3456 | 3423 | ||
| 3457 | #ifdef CONFIG_ATARI | ||
| 3458 | if (MACH_IS_ATARI) | ||
| 3459 | free_irq(IRQ_AUTO_4, fb_vbl_handler); | ||
| 3460 | #endif | ||
| 3461 | |||
| 3462 | kfree((void *)softback_buf); | 3424 | kfree((void *)softback_buf); |
| 3463 | softback_buf = 0UL; | 3425 | softback_buf = 0UL; |
| 3464 | 3426 | ||
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index ec68c741b564..3efa12f9ee50 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig | |||
| @@ -770,6 +770,12 @@ config TXX9_WDT | |||
| 770 | 770 | ||
| 771 | # POWERPC Architecture | 771 | # POWERPC Architecture |
| 772 | 772 | ||
| 773 | config GEF_WDT | ||
| 774 | tristate "GE Fanuc Watchdog Timer" | ||
| 775 | depends on GEF_SBC610 | ||
| 776 | ---help--- | ||
| 777 | Watchdog timer found in a number of GE Fanuc single board computers. | ||
| 778 | |||
| 773 | config MPC5200_WDT | 779 | config MPC5200_WDT |
| 774 | tristate "MPC5200 Watchdog Timer" | 780 | tristate "MPC5200 Watchdog Timer" |
| 775 | depends on PPC_MPC52xx | 781 | depends on PPC_MPC52xx |
| @@ -790,6 +796,14 @@ config MV64X60_WDT | |||
| 790 | tristate "MV64X60 (Marvell Discovery) Watchdog Timer" | 796 | tristate "MV64X60 (Marvell Discovery) Watchdog Timer" |
| 791 | depends on MV64X60 | 797 | depends on MV64X60 |
| 792 | 798 | ||
| 799 | config PIKA_WDT | ||
| 800 | tristate "PIKA FPGA Watchdog" | ||
| 801 | depends on WARP | ||
| 802 | default y | ||
| 803 | help | ||
| 804 | This enables the watchdog in the PIKA FPGA. Currently used on | ||
| 805 | the Warp platform. | ||
| 806 | |||
| 793 | config BOOKE_WDT | 807 | config BOOKE_WDT |
| 794 | bool "PowerPC Book-E Watchdog Timer" | 808 | bool "PowerPC Book-E Watchdog Timer" |
| 795 | depends on BOOKE || 4xx | 809 | depends on BOOKE || 4xx |
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index c19b866f5ed1..806b3eb08536 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile | |||
| @@ -111,9 +111,11 @@ obj-$(CONFIG_TXX9_WDT) += txx9wdt.o | |||
| 111 | # PARISC Architecture | 111 | # PARISC Architecture |
| 112 | 112 | ||
| 113 | # POWERPC Architecture | 113 | # POWERPC Architecture |
| 114 | obj-$(CONFIG_GEF_WDT) += gef_wdt.o | ||
| 114 | obj-$(CONFIG_MPC5200_WDT) += mpc5200_wdt.o | 115 | obj-$(CONFIG_MPC5200_WDT) += mpc5200_wdt.o |
| 115 | obj-$(CONFIG_8xxx_WDT) += mpc8xxx_wdt.o | 116 | obj-$(CONFIG_8xxx_WDT) += mpc8xxx_wdt.o |
| 116 | obj-$(CONFIG_MV64X60_WDT) += mv64x60_wdt.o | 117 | obj-$(CONFIG_MV64X60_WDT) += mv64x60_wdt.o |
| 118 | obj-$(CONFIG_PIKA_WDT) += pika_wdt.o | ||
| 117 | obj-$(CONFIG_BOOKE_WDT) += booke_wdt.o | 119 | obj-$(CONFIG_BOOKE_WDT) += booke_wdt.o |
| 118 | 120 | ||
| 119 | # PPC64 Architecture | 121 | # PPC64 Architecture |
diff --git a/drivers/watchdog/gef_wdt.c b/drivers/watchdog/gef_wdt.c new file mode 100644 index 000000000000..f0c2b7a1a175 --- /dev/null +++ b/drivers/watchdog/gef_wdt.c | |||
| @@ -0,0 +1,330 @@ | |||
| 1 | /* | ||
| 2 | * GE Fanuc watchdog userspace interface | ||
| 3 | * | ||
| 4 | * Author: Martyn Welch <martyn.welch@gefanuc.com> | ||
| 5 | * | ||
| 6 | * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify it | ||
| 9 | * under the terms of the GNU General Public License as published by the | ||
| 10 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 11 | * option) any later version. | ||
| 12 | * | ||
| 13 | * Based on: mv64x60_wdt.c (MV64X60 watchdog userspace interface) | ||
| 14 | * Author: James Chapman <jchapman@katalix.com> | ||
| 15 | */ | ||
| 16 | |||
| 17 | /* TODO: | ||
| 18 | * This driver does not provide support for the hardwares capability of sending | ||
| 19 | * an interrupt at a programmable threshold. | ||
| 20 | * | ||
| 21 | * This driver currently can only support 1 watchdog - there are 2 in the | ||
| 22 | * hardware that this driver supports. Thus one could be configured as a | ||
| 23 | * process-based watchdog (via /dev/watchdog), the second (using the interrupt | ||
| 24 | * capabilities) a kernel-based watchdog. | ||
| 25 | */ | ||
| 26 | |||
| 27 | #include <linux/kernel.h> | ||
| 28 | #include <linux/compiler.h> | ||
| 29 | #include <linux/init.h> | ||
| 30 | #include <linux/module.h> | ||
| 31 | #include <linux/miscdevice.h> | ||
| 32 | #include <linux/watchdog.h> | ||
| 33 | #include <linux/of.h> | ||
| 34 | #include <linux/of_platform.h> | ||
| 35 | #include <linux/io.h> | ||
| 36 | #include <linux/uaccess.h> | ||
| 37 | |||
| 38 | #include <sysdev/fsl_soc.h> | ||
| 39 | |||
| 40 | /* | ||
| 41 | * The watchdog configuration register contains a pair of 2-bit fields, | ||
| 42 | * 1. a reload field, bits 27-26, which triggers a reload of | ||
| 43 | * the countdown register, and | ||
| 44 | * 2. an enable field, bits 25-24, which toggles between | ||
| 45 | * enabling and disabling the watchdog timer. | ||
| 46 | * Bit 31 is a read-only field which indicates whether the | ||
| 47 | * watchdog timer is currently enabled. | ||
| 48 | * | ||
| 49 | * The low 24 bits contain the timer reload value. | ||
| 50 | */ | ||
| 51 | #define GEF_WDC_ENABLE_SHIFT 24 | ||
| 52 | #define GEF_WDC_SERVICE_SHIFT 26 | ||
| 53 | #define GEF_WDC_ENABLED_SHIFT 31 | ||
| 54 | |||
| 55 | #define GEF_WDC_ENABLED_TRUE 1 | ||
| 56 | #define GEF_WDC_ENABLED_FALSE 0 | ||
| 57 | |||
| 58 | /* Flags bits */ | ||
| 59 | #define GEF_WDOG_FLAG_OPENED 0 | ||
| 60 | |||
| 61 | static unsigned long wdt_flags; | ||
| 62 | static int wdt_status; | ||
| 63 | static void __iomem *gef_wdt_regs; | ||
| 64 | static int gef_wdt_timeout; | ||
| 65 | static int gef_wdt_count; | ||
| 66 | static unsigned int bus_clk; | ||
| 67 | static char expect_close; | ||
| 68 | static DEFINE_SPINLOCK(gef_wdt_spinlock); | ||
| 69 | |||
| 70 | static int nowayout = WATCHDOG_NOWAYOUT; | ||
| 71 | module_param(nowayout, int, 0); | ||
| 72 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" | ||
| 73 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | ||
| 74 | |||
| 75 | |||
| 76 | static int gef_wdt_toggle_wdc(int enabled_predicate, int field_shift) | ||
| 77 | { | ||
| 78 | u32 data; | ||
| 79 | u32 enabled; | ||
| 80 | int ret = 0; | ||
| 81 | |||
| 82 | spin_lock(&gef_wdt_spinlock); | ||
| 83 | data = ioread32be(gef_wdt_regs); | ||
| 84 | enabled = (data >> GEF_WDC_ENABLED_SHIFT) & 1; | ||
| 85 | |||
| 86 | /* only toggle the requested field if enabled state matches predicate */ | ||
| 87 | if ((enabled ^ enabled_predicate) == 0) { | ||
| 88 | /* We write a 1, then a 2 -- to the appropriate field */ | ||
| 89 | data = (1 << field_shift) | gef_wdt_count; | ||
| 90 | iowrite32be(data, gef_wdt_regs); | ||
| 91 | |||
| 92 | data = (2 << field_shift) | gef_wdt_count; | ||
| 93 | iowrite32be(data, gef_wdt_regs); | ||
| 94 | ret = 1; | ||
| 95 | } | ||
| 96 | spin_unlock(&gef_wdt_spinlock); | ||
| 97 | |||
| 98 | return ret; | ||
| 99 | } | ||
| 100 | |||
| 101 | static void gef_wdt_service(void) | ||
| 102 | { | ||
| 103 | gef_wdt_toggle_wdc(GEF_WDC_ENABLED_TRUE, | ||
| 104 | GEF_WDC_SERVICE_SHIFT); | ||
| 105 | } | ||
| 106 | |||
| 107 | static void gef_wdt_handler_enable(void) | ||
| 108 | { | ||
| 109 | if (gef_wdt_toggle_wdc(GEF_WDC_ENABLED_FALSE, | ||
| 110 | GEF_WDC_ENABLE_SHIFT)) { | ||
| 111 | gef_wdt_service(); | ||
| 112 | printk(KERN_NOTICE "gef_wdt: watchdog activated\n"); | ||
| 113 | } | ||
| 114 | } | ||
| 115 | |||
| 116 | static void gef_wdt_handler_disable(void) | ||
| 117 | { | ||
| 118 | if (gef_wdt_toggle_wdc(GEF_WDC_ENABLED_TRUE, | ||
| 119 | GEF_WDC_ENABLE_SHIFT)) | ||
| 120 | printk(KERN_NOTICE "gef_wdt: watchdog deactivated\n"); | ||
| 121 | } | ||
| 122 | |||
| 123 | static void gef_wdt_set_timeout(unsigned int timeout) | ||
| 124 | { | ||
| 125 | /* maximum bus cycle count is 0xFFFFFFFF */ | ||
| 126 | if (timeout > 0xFFFFFFFF / bus_clk) | ||
| 127 | timeout = 0xFFFFFFFF / bus_clk; | ||
| 128 | |||
| 129 | /* Register only holds upper 24 bits, bit shifted into lower 24 */ | ||
| 130 | gef_wdt_count = (timeout * bus_clk) >> 8; | ||
| 131 | gef_wdt_timeout = timeout; | ||
| 132 | } | ||
| 133 | |||
| 134 | |||
| 135 | static ssize_t gef_wdt_write(struct file *file, const char __user *data, | ||
| 136 | size_t len, loff_t *ppos) | ||
| 137 | { | ||
| 138 | if (len) { | ||
| 139 | if (!nowayout) { | ||
| 140 | size_t i; | ||
| 141 | |||
| 142 | expect_close = 0; | ||
| 143 | |||
| 144 | for (i = 0; i != len; i++) { | ||
| 145 | char c; | ||
| 146 | if (get_user(c, data + i)) | ||
| 147 | return -EFAULT; | ||
| 148 | if (c == 'V') | ||
| 149 | expect_close = 42; | ||
| 150 | } | ||
| 151 | } | ||
| 152 | gef_wdt_service(); | ||
| 153 | } | ||
| 154 | |||
| 155 | return len; | ||
| 156 | } | ||
| 157 | |||
| 158 | static long gef_wdt_ioctl(struct file *file, unsigned int cmd, | ||
| 159 | unsigned long arg) | ||
| 160 | { | ||
| 161 | int timeout; | ||
| 162 | int options; | ||
| 163 | void __user *argp = (void __user *)arg; | ||
| 164 | static struct watchdog_info info = { | ||
| 165 | .options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | | ||
| 166 | WDIOF_KEEPALIVEPING, | ||
| 167 | .firmware_version = 0, | ||
| 168 | .identity = "GE Fanuc watchdog", | ||
| 169 | }; | ||
| 170 | |||
| 171 | switch (cmd) { | ||
| 172 | case WDIOC_GETSUPPORT: | ||
| 173 | if (copy_to_user(argp, &info, sizeof(info))) | ||
| 174 | return -EFAULT; | ||
| 175 | break; | ||
| 176 | |||
| 177 | case WDIOC_GETSTATUS: | ||
| 178 | case WDIOC_GETBOOTSTATUS: | ||
| 179 | if (put_user(wdt_status, (int __user *)argp)) | ||
| 180 | return -EFAULT; | ||
| 181 | wdt_status &= ~WDIOF_KEEPALIVEPING; | ||
| 182 | break; | ||
| 183 | |||
| 184 | case WDIOC_SETOPTIONS: | ||
| 185 | if (get_user(options, (int __user *)argp)) | ||
| 186 | return -EFAULT; | ||
| 187 | |||
| 188 | if (options & WDIOS_DISABLECARD) | ||
| 189 | gef_wdt_handler_disable(); | ||
| 190 | |||
| 191 | if (options & WDIOS_ENABLECARD) | ||
| 192 | gef_wdt_handler_enable(); | ||
| 193 | break; | ||
| 194 | |||
| 195 | case WDIOC_KEEPALIVE: | ||
| 196 | gef_wdt_service(); | ||
| 197 | wdt_status |= WDIOF_KEEPALIVEPING; | ||
| 198 | break; | ||
| 199 | |||
| 200 | case WDIOC_SETTIMEOUT: | ||
| 201 | if (get_user(timeout, (int __user *)argp)) | ||
| 202 | return -EFAULT; | ||
| 203 | gef_wdt_set_timeout(timeout); | ||
| 204 | /* Fall through */ | ||
| 205 | |||
| 206 | case WDIOC_GETTIMEOUT: | ||
| 207 | if (put_user(gef_wdt_timeout, (int __user *)argp)) | ||
| 208 | return -EFAULT; | ||
| 209 | break; | ||
| 210 | |||
| 211 | default: | ||
| 212 | return -ENOTTY; | ||
| 213 | } | ||
| 214 | |||
| 215 | return 0; | ||
| 216 | } | ||
| 217 | |||
| 218 | static int gef_wdt_open(struct inode *inode, struct file *file) | ||
| 219 | { | ||
| 220 | if (test_and_set_bit(GEF_WDOG_FLAG_OPENED, &wdt_flags)) | ||
| 221 | return -EBUSY; | ||
| 222 | |||
| 223 | if (nowayout) | ||
| 224 | __module_get(THIS_MODULE); | ||
| 225 | |||
| 226 | gef_wdt_handler_enable(); | ||
| 227 | |||
| 228 | return nonseekable_open(inode, file); | ||
| 229 | } | ||
| 230 | |||
| 231 | static int gef_wdt_release(struct inode *inode, struct file *file) | ||
| 232 | { | ||
| 233 | if (expect_close == 42) | ||
| 234 | gef_wdt_handler_disable(); | ||
| 235 | else { | ||
| 236 | printk(KERN_CRIT | ||
| 237 | "gef_wdt: unexpected close, not stopping timer!\n"); | ||
| 238 | gef_wdt_service(); | ||
| 239 | } | ||
| 240 | expect_close = 0; | ||
| 241 | |||
| 242 | clear_bit(GEF_WDOG_FLAG_OPENED, &wdt_flags); | ||
| 243 | |||
| 244 | return 0; | ||
| 245 | } | ||
| 246 | |||
| 247 | static const struct file_operations gef_wdt_fops = { | ||
| 248 | .owner = THIS_MODULE, | ||
| 249 | .llseek = no_llseek, | ||
| 250 | .write = gef_wdt_write, | ||
| 251 | .unlocked_ioctl = gef_wdt_ioctl, | ||
| 252 | .open = gef_wdt_open, | ||
| 253 | .release = gef_wdt_release, | ||
| 254 | }; | ||
| 255 | |||
| 256 | static struct miscdevice gef_wdt_miscdev = { | ||
| 257 | .minor = WATCHDOG_MINOR, | ||
| 258 | .name = "watchdog", | ||
| 259 | .fops = &gef_wdt_fops, | ||
| 260 | }; | ||
| 261 | |||
| 262 | |||
| 263 | static int __devinit gef_wdt_probe(struct of_device *dev, | ||
| 264 | const struct of_device_id *match) | ||
| 265 | { | ||
| 266 | int timeout = 10; | ||
| 267 | u32 freq; | ||
| 268 | |||
| 269 | bus_clk = 133; /* in MHz */ | ||
| 270 | |||
| 271 | freq = fsl_get_sys_freq(); | ||
| 272 | if (freq > 0) | ||
| 273 | bus_clk = freq; | ||
| 274 | |||
| 275 | /* Map devices registers into memory */ | ||
| 276 | gef_wdt_regs = of_iomap(dev->node, 0); | ||
| 277 | if (gef_wdt_regs == NULL) | ||
| 278 | return -ENOMEM; | ||
| 279 | |||
| 280 | gef_wdt_set_timeout(timeout); | ||
| 281 | |||
| 282 | gef_wdt_handler_disable(); /* in case timer was already running */ | ||
| 283 | |||
| 284 | return misc_register(&gef_wdt_miscdev); | ||
| 285 | } | ||
| 286 | |||
| 287 | static int __devexit gef_wdt_remove(struct platform_device *dev) | ||
| 288 | { | ||
| 289 | misc_deregister(&gef_wdt_miscdev); | ||
| 290 | |||
| 291 | gef_wdt_handler_disable(); | ||
| 292 | |||
| 293 | iounmap(gef_wdt_regs); | ||
| 294 | |||
| 295 | return 0; | ||
| 296 | } | ||
| 297 | |||
| 298 | static const struct of_device_id gef_wdt_ids[] = { | ||
| 299 | { | ||
| 300 | .compatible = "gef,fpga-wdt", | ||
| 301 | }, | ||
| 302 | {}, | ||
| 303 | }; | ||
| 304 | |||
| 305 | static struct of_platform_driver gef_wdt_driver = { | ||
| 306 | .owner = THIS_MODULE, | ||
| 307 | .name = "gef_wdt", | ||
| 308 | .match_table = gef_wdt_ids, | ||
| 309 | .probe = gef_wdt_probe, | ||
| 310 | }; | ||
| 311 | |||
| 312 | static int __init gef_wdt_init(void) | ||
| 313 | { | ||
| 314 | printk(KERN_INFO "GE Fanuc watchdog driver\n"); | ||
| 315 | return of_register_platform_driver(&gef_wdt_driver); | ||
| 316 | } | ||
| 317 | |||
| 318 | static void __exit gef_wdt_exit(void) | ||
| 319 | { | ||
| 320 | of_unregister_platform_driver(&gef_wdt_driver); | ||
| 321 | } | ||
| 322 | |||
| 323 | module_init(gef_wdt_init); | ||
| 324 | module_exit(gef_wdt_exit); | ||
| 325 | |||
| 326 | MODULE_AUTHOR("Martyn Welch <martyn.welch@gefanuc.com>"); | ||
| 327 | MODULE_DESCRIPTION("GE Fanuc watchdog driver"); | ||
| 328 | MODULE_LICENSE("GPL"); | ||
| 329 | MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); | ||
| 330 | MODULE_ALIAS("platform: gef_wdt"); | ||
diff --git a/drivers/watchdog/pika_wdt.c b/drivers/watchdog/pika_wdt.c new file mode 100644 index 000000000000..2d22e996e996 --- /dev/null +++ b/drivers/watchdog/pika_wdt.c | |||
| @@ -0,0 +1,301 @@ | |||
| 1 | /* | ||
| 2 | * PIKA FPGA based Watchdog Timer | ||
| 3 | * | ||
| 4 | * Copyright (c) 2008 PIKA Technologies | ||
| 5 | * Sean MacLennan <smaclennan@pikatech.com> | ||
| 6 | */ | ||
| 7 | |||
| 8 | #include <linux/init.h> | ||
| 9 | #include <linux/errno.h> | ||
| 10 | #include <linux/module.h> | ||
| 11 | #include <linux/moduleparam.h> | ||
| 12 | #include <linux/types.h> | ||
| 13 | #include <linux/kernel.h> | ||
| 14 | #include <linux/fs.h> | ||
| 15 | #include <linux/miscdevice.h> | ||
| 16 | #include <linux/watchdog.h> | ||
| 17 | #include <linux/reboot.h> | ||
| 18 | #include <linux/jiffies.h> | ||
| 19 | #include <linux/timer.h> | ||
| 20 | #include <linux/bitops.h> | ||
| 21 | #include <linux/uaccess.h> | ||
| 22 | #include <linux/io.h> | ||
| 23 | #include <linux/of_platform.h> | ||
| 24 | |||
| 25 | #define DRV_NAME "PIKA-WDT" | ||
| 26 | #define PFX DRV_NAME ": " | ||
| 27 | |||
| 28 | /* Hardware timeout in seconds */ | ||
| 29 | #define WDT_HW_TIMEOUT 2 | ||
| 30 | |||
| 31 | /* Timer heartbeat (500ms) */ | ||
| 32 | #define WDT_TIMEOUT (HZ/2) | ||
| 33 | |||
| 34 | /* User land timeout */ | ||
| 35 | #define WDT_HEARTBEAT 15 | ||
| 36 | static int heartbeat = WDT_HEARTBEAT; | ||
| 37 | module_param(heartbeat, int, 0); | ||
| 38 | MODULE_PARM_DESC(heartbeat, "Watchdog heartbeats in seconds. " | ||
| 39 | "(default = " __MODULE_STRING(WDT_HEARTBEAT) ")"); | ||
| 40 | |||
| 41 | static int nowayout = WATCHDOG_NOWAYOUT; | ||
| 42 | module_param(nowayout, int, 0); | ||
| 43 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started " | ||
| 44 | "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | ||
| 45 | |||
| 46 | static struct { | ||
| 47 | void __iomem *fpga; | ||
| 48 | unsigned long next_heartbeat; /* the next_heartbeat for the timer */ | ||
| 49 | unsigned long open; | ||
| 50 | char expect_close; | ||
| 51 | int bootstatus; | ||
| 52 | struct timer_list timer; /* The timer that pings the watchdog */ | ||
| 53 | } pikawdt_private; | ||
| 54 | |||
| 55 | static struct watchdog_info ident = { | ||
| 56 | .identity = DRV_NAME, | ||
| 57 | .options = WDIOF_CARDRESET | | ||
| 58 | WDIOF_SETTIMEOUT | | ||
| 59 | WDIOF_KEEPALIVEPING | | ||
| 60 | WDIOF_MAGICCLOSE, | ||
| 61 | }; | ||
| 62 | |||
| 63 | /* | ||
| 64 | * Reload the watchdog timer. (ie, pat the watchdog) | ||
| 65 | */ | ||
| 66 | static inline void pikawdt_reset(void) | ||
| 67 | { | ||
| 68 | /* -- FPGA: Reset Control Register (32bit R/W) (Offset: 0x14) -- | ||
| 69 | * Bit 7, WTCHDG_EN: When set to 1, the watchdog timer is enabled. | ||
| 70 | * Once enabled, it cannot be disabled. The watchdog can be | ||
| 71 | * kicked by performing any write access to the reset | ||
| 72 | * control register (this register). | ||
| 73 | * Bit 8-11, WTCHDG_TIMEOUT_SEC: Sets the watchdog timeout value in | ||
| 74 | * seconds. Valid ranges are 1 to 15 seconds. The value can | ||
| 75 | * be modified dynamically. | ||
| 76 | */ | ||
| 77 | unsigned reset = in_be32(pikawdt_private.fpga + 0x14); | ||
| 78 | /* enable with max timeout - 15 seconds */ | ||
| 79 | reset |= (1 << 7) + (WDT_HW_TIMEOUT << 8); | ||
| 80 | out_be32(pikawdt_private.fpga + 0x14, reset); | ||
| 81 | } | ||
| 82 | |||
| 83 | /* | ||
| 84 | * Timer tick | ||
| 85 | */ | ||
| 86 | static void pikawdt_ping(unsigned long data) | ||
| 87 | { | ||
| 88 | if (time_before(jiffies, pikawdt_private.next_heartbeat) || | ||
| 89 | (!nowayout && !pikawdt_private.open)) { | ||
| 90 | pikawdt_reset(); | ||
| 91 | mod_timer(&pikawdt_private.timer, jiffies + WDT_TIMEOUT); | ||
| 92 | } else | ||
| 93 | printk(KERN_CRIT PFX "I will reset your machine !\n"); | ||
| 94 | } | ||
| 95 | |||
| 96 | |||
| 97 | static void pikawdt_keepalive(void) | ||
| 98 | { | ||
| 99 | pikawdt_private.next_heartbeat = jiffies + heartbeat * HZ; | ||
| 100 | } | ||
| 101 | |||
| 102 | static void pikawdt_start(void) | ||
| 103 | { | ||
| 104 | pikawdt_keepalive(); | ||
| 105 | mod_timer(&pikawdt_private.timer, jiffies + WDT_TIMEOUT); | ||
| 106 | } | ||
| 107 | |||
| 108 | /* | ||
| 109 | * Watchdog device is opened, and watchdog starts running. | ||
| 110 | */ | ||
| 111 | static int pikawdt_open(struct inode *inode, struct file *file) | ||
| 112 | { | ||
| 113 | /* /dev/watchdog can only be opened once */ | ||
| 114 | if (test_and_set_bit(0, &pikawdt_private.open)) | ||
| 115 | return -EBUSY; | ||
| 116 | |||
| 117 | pikawdt_start(); | ||
| 118 | |||
| 119 | return nonseekable_open(inode, file); | ||
| 120 | } | ||
| 121 | |||
| 122 | /* | ||
| 123 | * Close the watchdog device. | ||
| 124 | */ | ||
| 125 | static int pikawdt_release(struct inode *inode, struct file *file) | ||
| 126 | { | ||
| 127 | /* stop internal ping */ | ||
| 128 | if (!pikawdt_private.expect_close) | ||
| 129 | del_timer(&pikawdt_private.timer); | ||
| 130 | |||
| 131 | clear_bit(0, &pikawdt_private.open); | ||
| 132 | pikawdt_private.expect_close = 0; | ||
| 133 | return 0; | ||
| 134 | } | ||
| 135 | |||
| 136 | /* | ||
| 137 | * Pat the watchdog whenever device is written to. | ||
| 138 | */ | ||
| 139 | static ssize_t pikawdt_write(struct file *file, const char __user *data, | ||
| 140 | size_t len, loff_t *ppos) | ||
| 141 | { | ||
| 142 | if (!len) | ||
| 143 | return 0; | ||
| 144 | |||
| 145 | /* Scan for magic character */ | ||
| 146 | if (!nowayout) { | ||
| 147 | size_t i; | ||
| 148 | |||
| 149 | pikawdt_private.expect_close = 0; | ||
| 150 | |||
| 151 | for (i = 0; i < len; i++) { | ||
| 152 | char c; | ||
| 153 | if (get_user(c, data + i)) | ||
| 154 | return -EFAULT; | ||
| 155 | if (c == 'V') { | ||
| 156 | pikawdt_private.expect_close = 42; | ||
| 157 | break; | ||
| 158 | } | ||
| 159 | } | ||
| 160 | } | ||
| 161 | |||
| 162 | pikawdt_keepalive(); | ||
| 163 | |||
| 164 | return len; | ||
| 165 | } | ||
| 166 | |||
| 167 | /* | ||
| 168 | * Handle commands from user-space. | ||
| 169 | */ | ||
| 170 | static long pikawdt_ioctl(struct file *file, | ||
| 171 | unsigned int cmd, unsigned long arg) | ||
| 172 | { | ||
| 173 | void __user *argp = (void __user *)arg; | ||
| 174 | int __user *p = argp; | ||
| 175 | int new_value; | ||
| 176 | |||
| 177 | switch (cmd) { | ||
| 178 | case WDIOC_GETSUPPORT: | ||
| 179 | return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; | ||
| 180 | |||
| 181 | case WDIOC_GETSTATUS: | ||
| 182 | return put_user(0, p); | ||
| 183 | |||
| 184 | case WDIOC_GETBOOTSTATUS: | ||
| 185 | return put_user(pikawdt_private.bootstatus, p); | ||
| 186 | |||
| 187 | case WDIOC_KEEPALIVE: | ||
| 188 | pikawdt_keepalive(); | ||
| 189 | return 0; | ||
| 190 | |||
| 191 | case WDIOC_SETTIMEOUT: | ||
| 192 | if (get_user(new_value, p)) | ||
| 193 | return -EFAULT; | ||
| 194 | |||
| 195 | heartbeat = new_value; | ||
| 196 | pikawdt_keepalive(); | ||
| 197 | |||
| 198 | return put_user(new_value, p); /* return current value */ | ||
| 199 | |||
| 200 | case WDIOC_GETTIMEOUT: | ||
| 201 | return put_user(heartbeat, p); | ||
| 202 | } | ||
| 203 | return -ENOTTY; | ||
| 204 | } | ||
| 205 | |||
| 206 | |||
| 207 | static const struct file_operations pikawdt_fops = { | ||
| 208 | .owner = THIS_MODULE, | ||
| 209 | .llseek = no_llseek, | ||
| 210 | .open = pikawdt_open, | ||
| 211 | .release = pikawdt_release, | ||
| 212 | .write = pikawdt_write, | ||
| 213 | .unlocked_ioctl = pikawdt_ioctl, | ||
| 214 | }; | ||
| 215 | |||
| 216 | static struct miscdevice pikawdt_miscdev = { | ||
| 217 | .minor = WATCHDOG_MINOR, | ||
| 218 | .name = "watchdog", | ||
| 219 | .fops = &pikawdt_fops, | ||
| 220 | }; | ||
| 221 | |||
| 222 | static int __init pikawdt_init(void) | ||
| 223 | { | ||
| 224 | struct device_node *np; | ||
| 225 | void __iomem *fpga; | ||
| 226 | static u32 post1; | ||
| 227 | int ret; | ||
| 228 | |||
| 229 | np = of_find_compatible_node(NULL, NULL, "pika,fpga"); | ||
| 230 | if (np == NULL) { | ||
| 231 | printk(KERN_ERR PFX "Unable to find fpga.\n"); | ||
| 232 | return -ENOENT; | ||
| 233 | } | ||
| 234 | |||
| 235 | pikawdt_private.fpga = of_iomap(np, 0); | ||
| 236 | of_node_put(np); | ||
| 237 | if (pikawdt_private.fpga == NULL) { | ||
| 238 | printk(KERN_ERR PFX "Unable to map fpga.\n"); | ||
| 239 | return -ENOMEM; | ||
| 240 | } | ||
| 241 | |||
| 242 | ident.firmware_version = in_be32(pikawdt_private.fpga + 0x1c) & 0xffff; | ||
| 243 | |||
| 244 | /* POST information is in the sd area. */ | ||
| 245 | np = of_find_compatible_node(NULL, NULL, "pika,fpga-sd"); | ||
| 246 | if (np == NULL) { | ||
| 247 | printk(KERN_ERR PFX "Unable to find fpga-sd.\n"); | ||
| 248 | ret = -ENOENT; | ||
| 249 | goto out; | ||
| 250 | } | ||
| 251 | |||
| 252 | fpga = of_iomap(np, 0); | ||
| 253 | of_node_put(np); | ||
| 254 | if (fpga == NULL) { | ||
| 255 | printk(KERN_ERR PFX "Unable to map fpga-sd.\n"); | ||
| 256 | ret = -ENOMEM; | ||
| 257 | goto out; | ||
| 258 | } | ||
| 259 | |||
| 260 | /* -- FPGA: POST Test Results Register 1 (32bit R/W) (Offset: 0x4040) -- | ||
| 261 | * Bit 31, WDOG: Set to 1 when the last reset was caused by a watchdog | ||
| 262 | * timeout. | ||
| 263 | */ | ||
| 264 | post1 = in_be32(fpga + 0x40); | ||
| 265 | if (post1 & 0x80000000) | ||
| 266 | pikawdt_private.bootstatus = WDIOF_CARDRESET; | ||
| 267 | |||
| 268 | iounmap(fpga); | ||
| 269 | |||
| 270 | setup_timer(&pikawdt_private.timer, pikawdt_ping, 0); | ||
| 271 | |||
| 272 | ret = misc_register(&pikawdt_miscdev); | ||
| 273 | if (ret) { | ||
| 274 | printk(KERN_ERR PFX "Unable to register miscdev.\n"); | ||
| 275 | goto out; | ||
| 276 | } | ||
| 277 | |||
| 278 | printk(KERN_INFO PFX "initialized. heartbeat=%d sec (nowayout=%d)\n", | ||
| 279 | heartbeat, nowayout); | ||
| 280 | return 0; | ||
| 281 | |||
| 282 | out: | ||
| 283 | iounmap(pikawdt_private.fpga); | ||
| 284 | return ret; | ||
| 285 | } | ||
| 286 | |||
| 287 | static void __exit pikawdt_exit(void) | ||
| 288 | { | ||
| 289 | misc_deregister(&pikawdt_miscdev); | ||
| 290 | |||
| 291 | iounmap(pikawdt_private.fpga); | ||
| 292 | } | ||
| 293 | |||
| 294 | module_init(pikawdt_init); | ||
| 295 | module_exit(pikawdt_exit); | ||
| 296 | |||
| 297 | MODULE_AUTHOR("Sean MacLennan <smaclennan@pikatech.com>"); | ||
| 298 | MODULE_DESCRIPTION("PIKA FPGA based Watchdog Timer"); | ||
| 299 | MODULE_LICENSE("GPL"); | ||
| 300 | MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); | ||
| 301 | |||
diff --git a/drivers/watchdog/wm8350_wdt.c b/drivers/watchdog/wm8350_wdt.c index 2bc0d4d4b415..a2d2e8eb2282 100644 --- a/drivers/watchdog/wm8350_wdt.c +++ b/drivers/watchdog/wm8350_wdt.c | |||
| @@ -279,7 +279,7 @@ static struct miscdevice wm8350_wdt_miscdev = { | |||
| 279 | .fops = &wm8350_wdt_fops, | 279 | .fops = &wm8350_wdt_fops, |
| 280 | }; | 280 | }; |
| 281 | 281 | ||
| 282 | static int wm8350_wdt_probe(struct platform_device *pdev) | 282 | static int __devinit wm8350_wdt_probe(struct platform_device *pdev) |
| 283 | { | 283 | { |
| 284 | struct wm8350 *wm8350 = platform_get_drvdata(pdev); | 284 | struct wm8350 *wm8350 = platform_get_drvdata(pdev); |
| 285 | 285 | ||
| @@ -296,7 +296,7 @@ static int wm8350_wdt_probe(struct platform_device *pdev) | |||
| 296 | return misc_register(&wm8350_wdt_miscdev); | 296 | return misc_register(&wm8350_wdt_miscdev); |
| 297 | } | 297 | } |
| 298 | 298 | ||
| 299 | static int __exit wm8350_wdt_remove(struct platform_device *pdev) | 299 | static int __devexit wm8350_wdt_remove(struct platform_device *pdev) |
| 300 | { | 300 | { |
| 301 | misc_deregister(&wm8350_wdt_miscdev); | 301 | misc_deregister(&wm8350_wdt_miscdev); |
| 302 | 302 | ||
| @@ -305,7 +305,7 @@ static int __exit wm8350_wdt_remove(struct platform_device *pdev) | |||
| 305 | 305 | ||
| 306 | static struct platform_driver wm8350_wdt_driver = { | 306 | static struct platform_driver wm8350_wdt_driver = { |
| 307 | .probe = wm8350_wdt_probe, | 307 | .probe = wm8350_wdt_probe, |
| 308 | .remove = wm8350_wdt_remove, | 308 | .remove = __devexit_p(wm8350_wdt_remove), |
| 309 | .driver = { | 309 | .driver = { |
| 310 | .name = "wm8350-wdt", | 310 | .name = "wm8350-wdt", |
| 311 | }, | 311 | }, |
diff --git a/drivers/zorro/.gitignore b/drivers/zorro/.gitignore new file mode 100644 index 000000000000..34f980bd8ff6 --- /dev/null +++ b/drivers/zorro/.gitignore | |||
| @@ -0,0 +1,2 @@ | |||
| 1 | devlist.h | ||
| 2 | gen-devlist | ||
diff --git a/drivers/zorro/zorro-sysfs.c b/drivers/zorro/zorro-sysfs.c index 5290552d2ef7..1d2a772ea14c 100644 --- a/drivers/zorro/zorro-sysfs.c +++ b/drivers/zorro/zorro-sysfs.c | |||
| @@ -77,17 +77,21 @@ static struct bin_attribute zorro_config_attr = { | |||
| 77 | .read = zorro_read_config, | 77 | .read = zorro_read_config, |
| 78 | }; | 78 | }; |
| 79 | 79 | ||
| 80 | void zorro_create_sysfs_dev_files(struct zorro_dev *z) | 80 | int zorro_create_sysfs_dev_files(struct zorro_dev *z) |
| 81 | { | 81 | { |
| 82 | struct device *dev = &z->dev; | 82 | struct device *dev = &z->dev; |
| 83 | int error; | ||
| 83 | 84 | ||
| 84 | /* current configuration's attributes */ | 85 | /* current configuration's attributes */ |
| 85 | device_create_file(dev, &dev_attr_id); | 86 | if ((error = device_create_file(dev, &dev_attr_id)) || |
| 86 | device_create_file(dev, &dev_attr_type); | 87 | (error = device_create_file(dev, &dev_attr_type)) || |
| 87 | device_create_file(dev, &dev_attr_serial); | 88 | (error = device_create_file(dev, &dev_attr_serial)) || |
| 88 | device_create_file(dev, &dev_attr_slotaddr); | 89 | (error = device_create_file(dev, &dev_attr_slotaddr)) || |
| 89 | device_create_file(dev, &dev_attr_slotsize); | 90 | (error = device_create_file(dev, &dev_attr_slotsize)) || |
| 90 | device_create_file(dev, &dev_attr_resource); | 91 | (error = device_create_file(dev, &dev_attr_resource)) || |
| 91 | sysfs_create_bin_file(&dev->kobj, &zorro_config_attr); | 92 | (error = sysfs_create_bin_file(&dev->kobj, &zorro_config_attr))) |
| 93 | return error; | ||
| 94 | |||
| 95 | return 0; | ||
| 92 | } | 96 | } |
| 93 | 97 | ||
diff --git a/drivers/zorro/zorro.c b/drivers/zorro/zorro.c index dff16d9767d8..a1585d6f6486 100644 --- a/drivers/zorro/zorro.c +++ b/drivers/zorro/zorro.c | |||
| @@ -130,6 +130,7 @@ static int __init zorro_init(void) | |||
| 130 | { | 130 | { |
| 131 | struct zorro_dev *z; | 131 | struct zorro_dev *z; |
| 132 | unsigned int i; | 132 | unsigned int i; |
| 133 | int error; | ||
| 133 | 134 | ||
| 134 | if (!MACH_IS_AMIGA || !AMIGAHW_PRESENT(ZORRO)) | 135 | if (!MACH_IS_AMIGA || !AMIGAHW_PRESENT(ZORRO)) |
| 135 | return 0; | 136 | return 0; |
| @@ -140,7 +141,11 @@ static int __init zorro_init(void) | |||
| 140 | /* Initialize the Zorro bus */ | 141 | /* Initialize the Zorro bus */ |
| 141 | INIT_LIST_HEAD(&zorro_bus.devices); | 142 | INIT_LIST_HEAD(&zorro_bus.devices); |
| 142 | strcpy(zorro_bus.dev.bus_id, "zorro"); | 143 | strcpy(zorro_bus.dev.bus_id, "zorro"); |
| 143 | device_register(&zorro_bus.dev); | 144 | error = device_register(&zorro_bus.dev); |
| 145 | if (error) { | ||
| 146 | pr_err("Zorro: Error registering zorro_bus\n"); | ||
| 147 | return error; | ||
| 148 | } | ||
| 144 | 149 | ||
| 145 | /* Request the resources */ | 150 | /* Request the resources */ |
| 146 | zorro_bus.num_resources = AMIGAHW_PRESENT(ZORRO3) ? 4 : 2; | 151 | zorro_bus.num_resources = AMIGAHW_PRESENT(ZORRO3) ? 4 : 2; |
| @@ -160,15 +165,19 @@ static int __init zorro_init(void) | |||
| 160 | zorro_name_device(z); | 165 | zorro_name_device(z); |
| 161 | z->resource.name = z->name; | 166 | z->resource.name = z->name; |
| 162 | if (request_resource(zorro_find_parent_resource(z), &z->resource)) | 167 | if (request_resource(zorro_find_parent_resource(z), &z->resource)) |
| 163 | printk(KERN_ERR "Zorro: Address space collision on device %s " | 168 | pr_err("Zorro: Address space collision on device %s %pR\n", |
| 164 | "[%lx:%lx]\n", | 169 | z->name, &z->resource); |
| 165 | z->name, (unsigned long)zorro_resource_start(z), | ||
| 166 | (unsigned long)zorro_resource_end(z)); | ||
| 167 | sprintf(z->dev.bus_id, "%02x", i); | 170 | sprintf(z->dev.bus_id, "%02x", i); |
| 168 | z->dev.parent = &zorro_bus.dev; | 171 | z->dev.parent = &zorro_bus.dev; |
| 169 | z->dev.bus = &zorro_bus_type; | 172 | z->dev.bus = &zorro_bus_type; |
| 170 | device_register(&z->dev); | 173 | error = device_register(&z->dev); |
| 171 | zorro_create_sysfs_dev_files(z); | 174 | if (error) { |
| 175 | pr_err("Zorro: Error registering device %s\n", z->name); | ||
| 176 | continue; | ||
| 177 | } | ||
| 178 | error = zorro_create_sysfs_dev_files(z); | ||
| 179 | if (error) | ||
| 180 | dev_err(&z->dev, "Error creating sysfs files\n"); | ||
| 172 | } | 181 | } |
| 173 | 182 | ||
| 174 | /* Mark all available Zorro II memory */ | 183 | /* Mark all available Zorro II memory */ |
diff --git a/drivers/zorro/zorro.h b/drivers/zorro/zorro.h index 5c91adac4df1..b682d5ccd63f 100644 --- a/drivers/zorro/zorro.h +++ b/drivers/zorro/zorro.h | |||
| @@ -1,4 +1,4 @@ | |||
| 1 | 1 | ||
| 2 | extern void zorro_name_device(struct zorro_dev *z); | 2 | extern void zorro_name_device(struct zorro_dev *z); |
| 3 | extern void zorro_create_sysfs_dev_files(struct zorro_dev *z); | 3 | extern int zorro_create_sysfs_dev_files(struct zorro_dev *z); |
| 4 | 4 | ||
diff --git a/firmware/Makefile b/firmware/Makefile index ea1d28f9b44c..466106fa2146 100644 --- a/firmware/Makefile +++ b/firmware/Makefile | |||
| @@ -78,7 +78,8 @@ fw-shipped- += keyspan/mpr.fw keyspan/usa18x.fw keyspan/usa19.fw \ | |||
| 78 | keyspan/usa28.fw keyspan/usa28xa.fw keyspan/usa28xb.fw \ | 78 | keyspan/usa28.fw keyspan/usa28xa.fw keyspan/usa28xb.fw \ |
| 79 | keyspan/usa28x.fw keyspan/usa49w.fw keyspan/usa49wlc.fw | 79 | keyspan/usa28x.fw keyspan/usa49w.fw keyspan/usa49wlc.fw |
| 80 | endif | 80 | endif |
| 81 | fw-shipped-$(CONFIG_USB_SERIAL_TI) += ti_3410.fw ti_5052.fw | 81 | fw-shipped-$(CONFIG_USB_SERIAL_TI) += ti_3410.fw ti_5052.fw \ |
| 82 | mts_cdma.fw mts_gsm.fw mts_edge.fw | ||
| 82 | fw-shipped-$(CONFIG_USB_SERIAL_EDGEPORT) += edgeport/boot.fw edgeport/boot2.fw \ | 83 | fw-shipped-$(CONFIG_USB_SERIAL_EDGEPORT) += edgeport/boot.fw edgeport/boot2.fw \ |
| 83 | edgeport/down.fw edgeport/down2.fw | 84 | edgeport/down.fw edgeport/down2.fw |
| 84 | fw-shipped-$(CONFIG_USB_SERIAL_EDGEPORT_TI) += edgeport/down3.bin | 85 | fw-shipped-$(CONFIG_USB_SERIAL_EDGEPORT_TI) += edgeport/down3.bin |
diff --git a/firmware/WHENCE b/firmware/WHENCE index 8b5651347791..524113f9bea3 100644 --- a/firmware/WHENCE +++ b/firmware/WHENCE | |||
| @@ -191,7 +191,7 @@ Original licence information: None | |||
| 191 | 191 | ||
| 192 | -------------------------------------------------------------------------- | 192 | -------------------------------------------------------------------------- |
| 193 | 193 | ||
| 194 | Driver: tu_usb_3410_5052 -- USB TI 3410/5052 serial device | 194 | Driver: ti_usb_3410_5052 -- USB TI 3410/5052 serial device |
| 195 | 195 | ||
| 196 | File: ti_3410.fw | 196 | File: ti_3410.fw |
| 197 | Info: firmware 9/10/04 FW3410_Special_StartWdogOnStartPort | 197 | Info: firmware 9/10/04 FW3410_Special_StartWdogOnStartPort |
| @@ -206,6 +206,20 @@ Found in hex form in kernel source. | |||
| 206 | 206 | ||
| 207 | -------------------------------------------------------------------------- | 207 | -------------------------------------------------------------------------- |
| 208 | 208 | ||
| 209 | Driver: ti_usb_3410_5052 -- Multi-Tech USB cell modems | ||
| 210 | |||
| 211 | File: mts_cdma.fw | ||
| 212 | File: mts_gsm.fw | ||
| 213 | File: mts_edge.fw | ||
| 214 | |||
| 215 | Licence: "all firmware components are redistributable in binary form" | ||
| 216 | per support@multitech.com | ||
| 217 | Copyright (C) 2005 Multi-Tech Systems, Inc. | ||
| 218 | |||
| 219 | Found in hex form in ftp://ftp.multitech.com/wireless/wireless_linux.zip | ||
| 220 | |||
| 221 | -------------------------------------------------------------------------- | ||
| 222 | |||
| 209 | Driver: whiteheat -- USB ConnectTech WhiteHEAT serial device | 223 | Driver: whiteheat -- USB ConnectTech WhiteHEAT serial device |
| 210 | 224 | ||
| 211 | File: whiteheat.fw | 225 | File: whiteheat.fw |
diff --git a/firmware/mts_cdma.fw.ihex b/firmware/mts_cdma.fw.ihex new file mode 100644 index 000000000000..f6ad0cbd30cb --- /dev/null +++ b/firmware/mts_cdma.fw.ihex | |||
| @@ -0,0 +1,867 @@ | |||
| 1 | :1000000014360002001E021AF9FFFFFFFFFF023341 | ||
| 2 | :100010001DFFFFFFFFFFFFFFFFFFFFFFFFFF02339B | ||
| 3 | :10002000C87581CE90FDE88583A012353CEC4D600B | ||
| 4 | :100030007378AB8003760018B89CFA787F800376DB | ||
| 5 | :100040000018B865FA78208003760018B820FA788E | ||
| 6 | :10005000208003760018B81FFA90FDDDAE83AF82D2 | ||
| 7 | :1000600090FBF81200AA6005E4F0A380F690FDE88A | ||
| 8 | :10007000A88290FDE8A982E8696005E4F20880F7AB | ||
| 9 | :100080009001081200B390010C1200B390011012FD | ||
| 10 | :1000900000B39001141200D190011A1200D1900106 | ||
| 11 | :1000A000201200D175D00012341A020126EF6582A9 | ||
| 12 | :1000B0007003EE658322E493F8740193F97402935C | ||
| 13 | :1000C000FE740393F5828E83E869700122E493F64F | ||
| 14 | :1000D000A30880F4E493FC740193FD740293FE740E | ||
| 15 | :1000E0000393FF740493F8740593F58288831200D8 | ||
| 16 | :1000F000AA700122E493A3A883A9828C838D82F045 | ||
| 17 | :10010000A3AC83AD828883898280E32121049B8014 | ||
| 18 | :1001100080049BACAE049BFDE8049D049DFBF304AE | ||
| 19 | :10012000A2049DFBF30502050280FED0F030F00929 | ||
| 20 | :1001300020F303F68010F7800D30F10920F303F26D | ||
| 21 | :100140008004F38001F020F404FCD0E0CC22CCC089 | ||
| 22 | :10015000E0120163020154BC0005D0F0ACF022C3F0 | ||
| 23 | :1001600013DCFC02012ABF0009ED258275F001F8BD | ||
| 24 | :10017000E622BF010FED2582F582EE3583F583750A | ||
| 25 | :10018000F004E022ED258275F002F8E222D083D05F | ||
| 26 | :1001900082F5F0C3E493A3C5F095F0C0E0C3D0F0BE | ||
| 27 | :1001A000E493A395F04012A3A3C3E5F033500205F6 | ||
| 28 | :1001B000832582F58250020583740193C0E0E493A5 | ||
| 29 | :1001C000C0E022D083D082F5F0E4937009740193EB | ||
| 30 | :1001D0007004A3A3800C74029365F06005A3A3A32D | ||
| 31 | :1001E00080E7740193C0E0E493C0E022120264024D | ||
| 32 | :1001F00001FB1202B80201FB1202DC0201FB30E03B | ||
| 33 | :100200000720E302E622E72230E10720E302E222B0 | ||
| 34 | :10021000E32230E202E022E493221202DC02022313 | ||
| 35 | :100220001202B8020223ABF012022DCBC5F0CB2292 | ||
| 36 | :1002300030E01020E306E6F5F008E622E7F5F009E5 | ||
| 37 | :10024000E7192230E11020E306E2F5F008E222E3AC | ||
| 38 | :10025000F5F009E3192230E206E0F5F0A3E022E42C | ||
| 39 | :1002600093F5F074019322BB0003740922BB0107CC | ||
| 40 | :1002700089828A83740422BB020789828A8374106C | ||
| 41 | :1002800022740A22020284BB0007E92582F8740165 | ||
| 42 | :1002900022BB010DE92582F582EA3583F5837404DA | ||
| 43 | :1002A00022BB020DE92582F582EA3583F5837410BD | ||
| 44 | :1002B00022E92582F87402220202B8BF0005EDF897 | ||
| 45 | :1002C000740122BF01078D828E83740422BF02074E | ||
| 46 | :1002D0008D828E83741022EDF87402220202DCBF3C | ||
| 47 | :1002E0000007ED2582F8740122BF010DED2582F58E | ||
| 48 | :1002F00082EE3583F583740422BF020DED2582F56D | ||
| 49 | :1003000082EE3583F583741022ED2582F874022283 | ||
| 50 | :10031000020310C0E0120264020328C0E01202B817 | ||
| 51 | :10032000020328C0E01202DC02032830E00B20E3C5 | ||
| 52 | :1003300004D0E0F622D0E0F72230E10B20E304D035 | ||
| 53 | :10034000E0F222D0E0F322D0E0F022C9CDC9CACE3B | ||
| 54 | :10035000CACBCFCB12035BEDF9EEFAEFFB22BB0069 | ||
| 55 | :100360002FBF000AFAEDF8E7F60809DAFA22BF0112 | ||
| 56 | :10037000128D828E83F802037809A3E7F0D8FA225F | ||
| 57 | :10038000020383FAEDF8E7F20809DAFA2202038D94 | ||
| 58 | :10039000BB014DBF001489828A83F9EDF802039FE7 | ||
| 59 | :1003A00008A3E0F6D9FA220203B0BF01228D828EA3 | ||
| 60 | :1003B00083FB08C9C582C9CAC583CAE0A3C9C5826F | ||
| 61 | :1003C000C9CAC583CAF0A3DBEAD8E8220203D38DE9 | ||
| 62 | :1003D000828E83F9EDF8E0F208A3D9FA220203DD58 | ||
| 63 | :1003E000BB024DBF001289828A83F9EDF80203EF48 | ||
| 64 | :1003F00008A3E493F6D9F922BF01238D828E83FBF3 | ||
| 65 | :1004000008C9C582C9CAC583CAE493A3C9C582C93C | ||
| 66 | :10041000CAC583CAF0A3DBE9D8E722020422898295 | ||
| 67 | :100420008A83F9EDF8E493F208A3D9F922020433A0 | ||
| 68 | :10043000BF000DFAEDF8E3F60809DAFA2202043DEE | ||
| 69 | :10044000BF01128D828E83F802044A09A3E3F0D81B | ||
| 70 | :10045000FA22020455FAEDF8E3F20809DAFA220268 | ||
| 71 | :10046000045FE6FB08E6FA08E6F904F618700106F0 | ||
| 72 | :1004700022E6FF08E6FE08E6FD22EFF0A3EEF0A379 | ||
| 73 | :10048000EDF022EBF0A3EAF0A3E9F022E0FFA3E015 | ||
| 74 | :10049000FEA3E0FD22E0FBA3E0FAA3E0F9220000C6 | ||
| 75 | :1004A00000000000000502006105710026059800AB | ||
| 76 | :1004B000330A0900610A750066154400610CF900F1 | ||
| 77 | :1004C0006109A9006109E000610DC000610BF10044 | ||
| 78 | :1004D000610A1C00610A510061173C0033174F008C | ||
| 79 | :1004E000341E1400431EBF0044202C0044201A0078 | ||
| 80 | :1004F000471EE600471F8B004D1FDC004F1F080002 | ||
| 81 | :100500005832A800617CCC7DFF121CC52290FFFCF4 | ||
| 82 | :10051000E020E72DC2AFAE59AF58755A20E55A1406 | ||
| 83 | :10052000C55A6019E4FE7F05EE4FCE24FFCECF34CE | ||
| 84 | :10053000FFCF6007E490FF92F080ED80E08E598F4E | ||
| 85 | :10054000582212050A7D077CB71232C47D0F7C6EDB | ||
| 86 | :100550001232DE789D7A06E4F608DAFC7A06120595 | ||
| 87 | :10056000CD7C03120E55122168E4FEFF7C0F12327F | ||
| 88 | :100570004DD2A822123138E490FC38F090FFF0E020 | ||
| 89 | :1005800030E408740190FC39F08005E490FC39F007 | ||
| 90 | :100590007D0A7C001225461231BB2212313890FCB4 | ||
| 91 | :1005A00039E014700E90FFF0E04410F07C0012254A | ||
| 92 | :1005B000DF801990FC39E0700E90FFF0E054EFF00E | ||
| 93 | :1005C0007C001225DF80057C171225DF1231BB224B | ||
| 94 | :1005D00090FFF0E054ABF090FFF0E04420F0228C6C | ||
| 95 | :1005E000378D367882EDF608ECF6EDFEECFD7F01F6 | ||
| 96 | :1005F0009000051201F57880F67882E6FD08E6FCA9 | ||
| 97 | :10060000EDFEECFD7F019000041201F5540FFC7D1E | ||
| 98 | :100610008012176D7880E6700DAD3AAE39AF38E4D0 | ||
| 99 | :100620001203187C082290FFF0E054FEF090FFF0D7 | ||
| 100 | :10063000E054FDF0801E7882E6FD08E6FCEDFEEC5D | ||
| 101 | :10064000FD7F0190000812021725E0440190FFF39E | ||
| 102 | :10065000F00206D97882E6FD08E6FCEDFEECFD7FAF | ||
| 103 | :100660000190000612021754FE90FFF3F0802B78E1 | ||
| 104 | :1006700082E6FD08E6FCEDFEECFD7F01900008122D | ||
| 105 | :100680000217FAEB90FFF1F01208C8400DAD3AAE38 | ||
| 106 | :1006900039AF38E41203187C18227882E6FD08E6A8 | ||
| 107 | :1006A000FCEDFEECFD7F0190000812021790FFF1B7 | ||
| 108 | :1006B000F01208C8400DAD3AAE39AF38E412031855 | ||
| 109 | :1006C0007C18227882E6FD08E6FCEDFEECFD7F0159 | ||
| 110 | :1006D000900006120217440190FFF3F07883E6249D | ||
| 111 | :1006E00003F618E63400F67880E624FE500990FF01 | ||
| 112 | :1006F000F0E054FDF0800790FFF0E04402F0E49059 | ||
| 113 | :10070000FFF1F0788176007880E624FFFCE434FF86 | ||
| 114 | :10071000FD7881E67F00FEECD39EEF6480CD64809F | ||
| 115 | :100720009D402F1208AD400F7881E6AD3AAE39AF4B | ||
| 116 | :10073000381203187C182290FFF2E0FC788286833E | ||
| 117 | :10074000088682ECF0788106A37882A68308A682C8 | ||
| 118 | :1007500080B51208AD400F7881E6AD3AAE39AF38BA | ||
| 119 | :100760001203187C182290FFF2E0FC78828683083E | ||
| 120 | :100770008682ECF07880E6AD3AAE39AF38120318D5 | ||
| 121 | :100780007C00228C378D367882EDF608ECF6EDFE93 | ||
| 122 | :10079000ECFD7F019000051201F57881F67882E684 | ||
| 123 | :1007A000FD08E6FCEDFEECFD7F019000041201F572 | ||
| 124 | :1007B000540FFC7D8112176D7881E670037C08224E | ||
| 125 | :1007C00090FFF0E054FEF090FFF0E054FDF0801B4D | ||
| 126 | :1007D0007882E6FD08E6FCEDFEECFD7F0190000866 | ||
| 127 | :1007E00012021725E090FFF3F0805B7882E6FD08A7 | ||
| 128 | :1007F000E6FCEDFEECFD7F0190000612021754FEB0 | ||
| 129 | :1008000090FFF3F080217882E6FD08E6FCEDFEEC37 | ||
| 130 | :10081000FD7F01900008120217FAEB90FFF1F01231 | ||
| 131 | :1008200008C840037C18227882E6FD08E6FCEDFE4D | ||
| 132 | :10083000ECFD7F0190000812021790FFF1F0120802 | ||
| 133 | :10084000C840037C18227883E6240AF618E63400B0 | ||
| 134 | :10085000F6788076007881E624FFFCE434FFFD78AA | ||
| 135 | :1008600080E67F00FEECD39EEF6480CD64809D40E7 | ||
| 136 | :100870002178828683088682E090FFF1F01208C812 | ||
| 137 | :1008800040037C1822788006788306E618700106FB | ||
| 138 | :1008900080C390FFF0E04401F0788286830886826E | ||
| 139 | :1008A000E090FFF1F01208C840037C18227C00227F | ||
| 140 | :1008B00090FFF0E020E71290FFF0E030E50990FFB4 | ||
| 141 | :1008C000F0E04420F0C32280E7D32290FFF0E02044 | ||
| 142 | :1008D000E31290FFF0E030E50990FFF0E04420F0F3 | ||
| 143 | :1008E000C32280E7D3228C428D417C00ED54F0FD81 | ||
| 144 | :1008F000EC7003ED64307005753E038003753E04B3 | ||
| 145 | :10090000AC3E120F72758300858340E541540FF5AC | ||
| 146 | :100910003FE5407004E53F64037035E53E24FD7516 | ||
| 147 | :10092000F00AA42402F582E434FCF583E030E60505 | ||
| 148 | :100930001210598019E53E249DF8E654FBF678A97B | ||
| 149 | :10094000E62405F58218E63400F583740FF080592B | ||
| 150 | :10095000E5407004E53F64047048E53E24FD75F011 | ||
| 151 | :100960000AA42402F582E434FCF583E030E507AC08 | ||
| 152 | :1009700042AD41121C5AE54230E21578ADE630E056 | ||
| 153 | :100980000F78ADE630E109E4FF04FE7C0412324D3D | ||
| 154 | :1009900078A9E62406F58218E63400F583740FF092 | ||
| 155 | :1009A0008007E4FC7DEE121C5AC203221231381279 | ||
| 156 | :1009B0000F7278A9E62406F58218E63400F583E084 | ||
| 157 | :1009C00090FC38F078A9E62405F58218E63400F5A5 | ||
| 158 | :1009D00083E090FC39F0C2037D027C0012254612B0 | ||
| 159 | :1009E00031BB221231387895ECF6EC249DF8E630D4 | ||
| 160 | :1009F000E1077C131225DF800F90FC39E0FD78952C | ||
| 161 | :100A0000E6FC1213EF1225DF1231BB2212313878C7 | ||
| 162 | :100A100095ECF67D00120F121225DF1231BB221267 | ||
| 163 | :100A200031387895ECF6EC249DF8E630E2077C133B | ||
| 164 | :100A30001225DF801B7895E6249DF8E620E1077CEF | ||
| 165 | :100A4000121225DF800A7895E6FC1214131225DFB6 | ||
| 166 | :100A50001231BB221231387895ECF6EC249DF8E681 | ||
| 167 | :100A600020E2077C111225DF800A7895E6FC12153A | ||
| 168 | :100A7000141225DF1231BB221231387895ECF612B0 | ||
| 169 | :100A80000F7278A9E62409F58218E63400F583E0B0 | ||
| 170 | :100A900090FC3FF078A9E6240AF58218E63400F5C8 | ||
| 171 | :100AA00083E090FC40F078A9E62403F58218E63450 | ||
| 172 | :100AB00000F583E0FC78A9E62404F58218E634000A | ||
| 173 | :100AC000F583E0F56278A9E62402F58218E63400A1 | ||
| 174 | :100AD000F583E0F5638C61E4EC333354017895F6EB | ||
| 175 | :100AE0006008E56230E1037895067895E690FC4170 | ||
| 176 | :100AF000F078A7E62402F58218E63400F583E0FDDD | ||
| 177 | :100B0000A3E0540CFCED54E68C65F564E56130E53A | ||
| 178 | :100B100003436501E56220E50EE561547F7008E559 | ||
| 179 | :100B20006120E703436502E56130E303436510E5B7 | ||
| 180 | :100B30006130E203436520E561540360034365408F | ||
| 181 | :100B4000E56130E103436580E56130E4034364011E | ||
| 182 | :100B5000E56130E603436408E56220E40EE5615494 | ||
| 183 | :100B60007F7008E56120E7034364105365FB53641D | ||
| 184 | :100B7000F9AD64E56590FC3ACDF0A3CDF0E56330C6 | ||
| 185 | :100B8000E30DE5635430C4540F90FC3DF08005E460 | ||
| 186 | :100B900090FC3DF0E563540390FC3CF0E5635404A5 | ||
| 187 | :100BA000C31390FC3EF090FC3CE0700E7D357EFC63 | ||
| 188 | :100BB0007F01740190000912014B78A9E62408F521 | ||
| 189 | :100BC0008218E63400F583E07C00FD78A9E624076E | ||
| 190 | :100BD000F58218E63400F583E07F004CFEEF4D907F | ||
| 191 | :100BE000FC38F0A3CEF0CEC2037D0A7C001225466D | ||
| 192 | :100BF0001231BB221231387895ECF6789A760108DA | ||
| 193 | :100C000076FC0876387897760C789A12046E120281 | ||
| 194 | :100C10001D7898CBF6CB08F67F00EF24EA401FE45E | ||
| 195 | :100C2000EF25E090357EFD93CD04937899667003AF | ||
| 196 | :100C3000ED186670067897760080030F80DC789652 | ||
| 197 | :100C4000EFF6789A12046E9000021202177898CB91 | ||
| 198 | :100C5000F6CB08F65404CB54064B60047897760B19 | ||
| 199 | :100C60007899E630E313789A12046E900005120129 | ||
| 200 | :100C7000F524FB50047897760D7899E654C07D00F2 | ||
| 201 | :100C800064C04D70047897760B789A12046E9000C9 | ||
| 202 | :100C9000041201F524FC50047897760F789A120418 | ||
| 203 | :100CA0006E9000061201F524FD50047897760E78B8 | ||
| 204 | :100CB0009A12046E9000091201F524FD50047897F1 | ||
| 205 | :100CC000760A7897E6702A7895E6FC120F72789A81 | ||
| 206 | :100CD00012046E78A7E6F978A6E6FA7B01740A7822 | ||
| 207 | :100CE00000120348C2037895E6FC1211157897ECC0 | ||
| 208 | :100CF000F67897E6FC1225DF1231BB2212313878E4 | ||
| 209 | :100D000095ECF6120F727895E624FD75F00AA4248E | ||
| 210 | :100D100014F582E434FCF583AC82AD8378A6868337 | ||
| 211 | :100D2000088682ECF9EDFA7B0A78011203B0C2035F | ||
| 212 | :100D30007895E6FC1211151231BB228D2B8C2AED11 | ||
| 213 | :100D400060407527017529487528FFE52A24FDFCB8 | ||
| 214 | :100D5000E434FFFDEC7C0325E0CD33CDDCF9FCE58C | ||
| 215 | :100D6000292CF529E5283DF528AD29AE28AF2774B3 | ||
| 216 | :100D7000809000061203207480900002120320125B | ||
| 217 | :100D80000FC5E52B14603B7527017529087528FFF1 | ||
| 218 | :100D9000E52A24FDFCE434FFFDEC7C0325E0CD33A3 | ||
| 219 | :100DA000CDDCF9FCE5292CF529E5283DF528AD2910 | ||
| 220 | :100DB000AE28AF27E4900006120320E49000021250 | ||
| 221 | :100DC0000320221231387895ECF6EC249DF8E630B9 | ||
| 222 | :100DD000E2097895E6FC121514D2007895E6FC122B | ||
| 223 | :100DE0000F727896760090FC39E030E704789676BA | ||
| 224 | :100DF000017896E6FD7895E6FC120D38C2033000C6 | ||
| 225 | :100E0000077895E6FC1214137C001225DF1231BB23 | ||
| 226 | :100E10002278A9E62404F58218E63400F583E0443C | ||
| 227 | :100E200001F078A9E62404F58218E63400F583E0A1 | ||
| 228 | :100E300030E00280ED78A9E6240BF58218E6340054 | ||
| 229 | :100E4000F583E054F8F078A9E62402F58218E63438 | ||
| 230 | :100E500000F583E04480F022C2038C58120F7278B0 | ||
| 231 | :100E6000A6868308868279AF7A357B0A78011203D9 | ||
| 232 | :100E7000FE120E0EAC587D02120D38C203AC581291 | ||
| 233 | :100E80001115228D538E528F518C50120F72754F47 | ||
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| 834 | :10341000D28DD002D001D000D0D0D0E0327581ADB5 | ||
| 835 | :10342000742A90FF93F0757F30757EF8757D607516 | ||
| 836 | :103430007CF012053F1234CE12175B90FF93E044EC | ||
| 837 | :1034400001F0B2B31234F81232A880DA22C0007C44 | ||
| 838 | :1034500001EC2408F8E660090CBC08F512329A80E9 | ||
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| 847 | :1034E000000809DAF8E478087480447FF67401442F | ||
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| 849 | :10350000D28CD2AFE57B6032FF90FD95E0548060B5 | ||
| 850 | :103510002478087908E0547FFA7B00E6547FB502EE | ||
| 851 | :10352000027BFF08D9F5EB700CEAF012344AAD04C7 | ||
| 852 | :10353000AC02123461A3A3A3DFD212329A80C57CFD | ||
| 853 | :10354000017D002204FE04F204F604EA04E604E22B | ||
| 854 | :1035500004EE04FA04A604AA04D604DA04A204A21F | ||
| 855 | :1035600004A204DE04BE04B604BA04B204CA04C64B | ||
| 856 | :1035700004C204CE04D204AE1901030022004802A2 | ||
| 857 | :1035800000480E301420C81AD0180A0C0506020391 | ||
| 858 | :1035900001020001CE0181010000C0008000600036 | ||
| 859 | :1035A0003000180010000800040002000100081894 | ||
| 860 | :1035B00028380C05100A0200000000000301100A60 | ||
| 861 | :1035C000020000000000FBE0FBF2090227000102FC | ||
| 862 | :1035D00000A0FA0904000003FF00000007058102B3 | ||
| 863 | :1035E00040000007050102400000070583030200B8 | ||
| 864 | :1035F00001220354005500530042003300340031CF | ||
| 865 | :1036000000300020002000200020002000200020AA | ||
| 866 | :073610000020000000000093 | ||
| 867 | :00000001FF | ||
diff --git a/firmware/mts_edge.fw.ihex b/firmware/mts_edge.fw.ihex new file mode 100644 index 000000000000..d14ebd647846 --- /dev/null +++ b/firmware/mts_edge.fw.ihex | |||
| @@ -0,0 +1,881 @@ | |||
| 1 | :10000000F0360002001E021AFBFFFFFFFFFF023363 | ||
| 2 | :10001000F9FFFFFFFFFFFFFFFFFFFFFFFFFF0234BE | ||
| 3 | :10002000A47581D490FDE88583A0123618EC4D604C | ||
| 4 | :100030007378AF8003760018B8A0FA787F800376D3 | ||
| 5 | :100040000018B865FA78208003760018B820FA788E | ||
| 6 | :10005000208003760018B81FFA90FDDDAE83AF82D2 | ||
| 7 | :1000600090FBF81200AA6005E4F0A380F690FDE88A | ||
| 8 | :10007000A88290FDE8A982E8696005E4F20880F7AB | ||
| 9 | :100080009001081200B390010C1200B390011012FD | ||
| 10 | :1000900000B39001141200D190011A1200D1900106 | ||
| 11 | :1000A000201200D175D0001234F6020126EF6582CD | ||
| 12 | :1000B0007003EE658322E493F8740193F97402935C | ||
| 13 | :1000C000FE740393F5828E83E869700122E493F64F | ||
| 14 | :1000D000A30880F4E493FC740193FD740293FE740E | ||
| 15 | :1000E0000393FF740493F8740593F58288831200D8 | ||
| 16 | :1000F000AA700122E493A3A883A9828C838D82F045 | ||
| 17 | :10010000A3AC83AD828883898280E32121049B8014 | ||
| 18 | :1001100080049BB0B4049BFDE8049F049FFBF304A0 | ||
| 19 | :10012000A4049FFBF30504050480FED0F030F00921 | ||
| 20 | :1001300020F303F68010F7800D30F10920F303F26D | ||
| 21 | :100140008004F38001F020F404FCD0E0CC22CCC089 | ||
| 22 | :10015000E0120163020154BC0005D0F0ACF022C3F0 | ||
| 23 | :1001600013DCFC02012ABF0009ED258275F001F8BD | ||
| 24 | :10017000E622BF010FED2582F582EE3583F583750A | ||
| 25 | :10018000F004E022ED258275F002F8E222D083D05F | ||
| 26 | :1001900082F5F0C3E493A3C5F095F0C0E0C3D0F0BE | ||
| 27 | :1001A000E493A395F04012A3A3C3E5F033500205F6 | ||
| 28 | :1001B000832582F58250020583740193C0E0E493A5 | ||
| 29 | :1001C000C0E022D083D082F5F0E4937009740193EB | ||
| 30 | :1001D0007004A3A3800C74029365F06005A3A3A32D | ||
| 31 | :1001E00080E7740193C0E0E493C0E022120264024D | ||
| 32 | :1001F00001FB1202B80201FB1202DC0201FB30E03B | ||
| 33 | :100200000720E302E622E72230E10720E302E222B0 | ||
| 34 | :10021000E32230E202E022E493221202DC02022313 | ||
| 35 | :100220001202B8020223ABF012022DCBC5F0CB2292 | ||
| 36 | :1002300030E01020E306E6F5F008E622E7F5F009E5 | ||
| 37 | :10024000E7192230E11020E306E2F5F008E222E3AC | ||
| 38 | :10025000F5F009E3192230E206E0F5F0A3E022E42C | ||
| 39 | :1002600093F5F074019322BB0003740922BB0107CC | ||
| 40 | :1002700089828A83740422BB020789828A8374106C | ||
| 41 | :1002800022740A22020284BB0007E92582F8740165 | ||
| 42 | :1002900022BB010DE92582F582EA3583F5837404DA | ||
| 43 | :1002A00022BB020DE92582F582EA3583F5837410BD | ||
| 44 | :1002B00022E92582F87402220202B8BF0005EDF897 | ||
| 45 | :1002C000740122BF01078D828E83740422BF02074E | ||
| 46 | :1002D0008D828E83741022EDF87402220202DCBF3C | ||
| 47 | :1002E0000007ED2582F8740122BF010DED2582F58E | ||
| 48 | :1002F00082EE3583F583740422BF020DED2582F56D | ||
| 49 | :1003000082EE3583F583741022ED2582F874022283 | ||
| 50 | :10031000020310C0E0120264020328C0E01202B817 | ||
| 51 | :10032000020328C0E01202DC02032830E00B20E3C5 | ||
| 52 | :1003300004D0E0F622D0E0F72230E10B20E304D035 | ||
| 53 | :10034000E0F222D0E0F322D0E0F022C9CDC9CACE3B | ||
| 54 | :10035000CACBCFCB12035BEDF9EEFAEFFB22BB0069 | ||
| 55 | :100360002FBF000AFAEDF8E7F60809DAFA22BF0112 | ||
| 56 | :10037000128D828E83F802037809A3E7F0D8FA225F | ||
| 57 | :10038000020383FAEDF8E7F20809DAFA2202038D94 | ||
| 58 | :10039000BB014DBF001489828A83F9EDF802039FE7 | ||
| 59 | :1003A00008A3E0F6D9FA220203B0BF01228D828EA3 | ||
| 60 | :1003B00083FB08C9C582C9CAC583CAE0A3C9C5826F | ||
| 61 | :1003C000C9CAC583CAF0A3DBEAD8E8220203D38DE9 | ||
| 62 | :1003D000828E83F9EDF8E0F208A3D9FA220203DD58 | ||
| 63 | :1003E000BB024DBF001289828A83F9EDF80203EF48 | ||
| 64 | :1003F00008A3E493F6D9F922BF01238D828E83FBF3 | ||
| 65 | :1004000008C9C582C9CAC583CAE493A3C9C582C93C | ||
| 66 | :10041000CAC583CAF0A3DBE9D8E722020422898295 | ||
| 67 | :100420008A83F9EDF8E493F208A3D9F922020433A0 | ||
| 68 | :10043000BF000DFAEDF8E3F60809DAFA2202043DEE | ||
| 69 | :10044000BF01128D828E83F802044A09A3E3F0D81B | ||
| 70 | :10045000FA22020455FAEDF8E3F20809DAFA220268 | ||
| 71 | :10046000045FE6FB08E6FA08E6F904F618700106F0 | ||
| 72 | :1004700022E6FF08E6FE08E6FD22EFF0A3EEF0A379 | ||
| 73 | :10048000EDF022EBF0A3EAF0A3E9F022E0FFA3E015 | ||
| 74 | :10049000FEA3E0FD22E0FBA3E0FAA3E0F9220000C6 | ||
| 75 | :1004A000000000000000000504006105730026053F | ||
| 76 | :1004B0009A00330A0B00610A770066154600610C4A | ||
| 77 | :1004C000FB006109AB006109E200610DC200610B34 | ||
| 78 | :1004D000F300610A1E00610A530061173E003317E2 | ||
| 79 | :1004E0005100341E1600431EBC0044202900442045 | ||
| 80 | :1004F0001700471EE300471F88004D1FD9004F1FFC | ||
| 81 | :10050000050058338400617CCC7DFF121CC722900B | ||
| 82 | :10051000FFFCE020E72DC2AFAE59AF58755A20E579 | ||
| 83 | :100520005A14C55A6019E4FE7F05EE4FCE24FFCE63 | ||
| 84 | :10053000CF34FFCF6007E490FF92F080ED80E08E33 | ||
| 85 | :10054000598F582212050C7D077CB71233A07D0FFE | ||
| 86 | :100550007C6E1233BA78A17A06E4F608DAFC7A06E1 | ||
| 87 | :100560001205CF7C03120E57122165E4FEFF7C0FAB | ||
| 88 | :10057000123329D2A822123214E490FC38F090FFF2 | ||
| 89 | :10058000F0E030E408740190FC39F08005E490FC60 | ||
| 90 | :1005900039F07D0A7C00122547123297221232145C | ||
| 91 | :1005A00090FC39E014700E90FFF0E04410F07C00F5 | ||
| 92 | :1005B0001225E0801990FC39E0700E90FFF0E054B5 | ||
| 93 | :1005C000EFF07C001225E080057C171225E0123246 | ||
| 94 | :1005D000972290FFF0E054ABF090FFF0E04420F061 | ||
| 95 | :1005E000228C378D367882EDF608ECF6EDFEECFDC8 | ||
| 96 | :1005F0007F019000051201F57880F67882E6FD080B | ||
| 97 | :10060000E6FCEDFEECFD7F019000041201F5540FB5 | ||
| 98 | :10061000FC7D8012176F7880E6700DAD3AAE39AF71 | ||
| 99 | :1006200038E41203187C082290FFF0E054FEF090AA | ||
| 100 | :10063000FFF0E054FDF0801E7882E6FD08E6FCED58 | ||
| 101 | :10064000FEECFD7F0190000812021725E0440190A6 | ||
| 102 | :10065000FFF3F00206DB7882E6FD08E6FCEDFEEC37 | ||
| 103 | :10066000FD7F0190000612021754FE90FFF3F08008 | ||
| 104 | :100670002B7882E6FD08E6FCEDFEECFD7F019000A4 | ||
| 105 | :1006800008120217FAEB90FFF1F01208CA400DAD04 | ||
| 106 | :100690003AAE39AF38E41203187C18227882E6FDAE | ||
| 107 | :1006A00008E6FCEDFEECFD7F0190000812021790B9 | ||
| 108 | :1006B000FFF1F01208CA400DAD3AAE39AF38E4127E | ||
| 109 | :1006C00003187C18227882E6FD08E6FCEDFEECFDBE | ||
| 110 | :1006D0007F01900006120217440190FFF3F0788327 | ||
| 111 | :1006E000E62403F618E63400F67880E624FE500986 | ||
| 112 | :1006F00090FFF0E054FDF0800790FFF0E04402F03E | ||
| 113 | :10070000E490FFF1F0788176007880E624FFFCE445 | ||
| 114 | :1007100034FFFD7881E67F00FEECD39EEF6480CD50 | ||
| 115 | :1007200064809D402F1208AF400F7881E6AD3AAE4D | ||
| 116 | :1007300039AF381203187C182290FFF2E0FC78825F | ||
| 117 | :100740008683088682ECF0788106A37882A68308E7 | ||
| 118 | :10075000A68280B51208AF400F7881E6AD3AAE3977 | ||
| 119 | :10076000AF381203187C182290FFF2E0FC788286E2 | ||
| 120 | :1007700083088682ECF07880E6AD3AAE39AF381265 | ||
| 121 | :1007800003187C00228C378D367882EDF608ECF663 | ||
| 122 | :10079000EDFEECFD7F019000051201F57881F67801 | ||
| 123 | :1007A00082E6FD08E6FCEDFEECFD7F019000041200 | ||
| 124 | :1007B00001F5540FFC7D8112176F7881E670037C80 | ||
| 125 | :1007C000082290FFF0E054FEF090FFF0E054FDF0BE | ||
| 126 | :1007D000801B7882E6FD08E6FCEDFEECFD7F0190D3 | ||
| 127 | :1007E000000812021725E090FFF3F0805B7882E6A4 | ||
| 128 | :1007F000FD08E6FCEDFEECFD7F01900006120217FD | ||
| 129 | :1008000054FE90FFF3F080217882E6FD08E6FCEDCF | ||
| 130 | :10081000FEECFD7F01900008120217FAEB90FFF149 | ||
| 131 | :10082000F01208CA40037C18227882E6FD08E6FC34 | ||
| 132 | :10083000EDFEECFD7F0190000812021790FFF1F031 | ||
| 133 | :100840001208CA40037C18227883E6240AF618E6C8 | ||
| 134 | :100850003400F6788076007881E624FFFCE434FFEB | ||
| 135 | :10086000FD7880E67F00FEECD39EEF6480CD64804F | ||
| 136 | :100870009D402178828683088682E090FFF1F01205 | ||
| 137 | :1008800008CA40037C1822788006788306E6187030 | ||
| 138 | :10089000010680C390FFF0E04401F078828683086F | ||
| 139 | :1008A0008682E090FFF1F01208CA40037C18227C97 | ||
| 140 | :1008B000002290FFF0E020E71290FFF0E030E50921 | ||
| 141 | :1008C00090FFF0E04420F0C32280E7D32290FFF0B5 | ||
| 142 | :1008D000E020E31290FFF0E030E50990FFF0E04403 | ||
| 143 | :1008E00020F0C32280E7D3228C428D417C00ED545E | ||
| 144 | :1008F000F0FDEC7003ED64307005753E0380037508 | ||
| 145 | :100900003E04AC3E120F74758300858340E541546C | ||
| 146 | :100910000FF53FE5407004E53F64037035E53E2484 | ||
| 147 | :10092000FD75F00AA42402F582E434FCF583E0307E | ||
| 148 | :10093000E60512105B8019E53E24A1F8E654FBF6AB | ||
| 149 | :1009400078ADE62405F58218E63400F583740FF0DF | ||
| 150 | :100950008059E5407004E53F64047048E53E24FD9D | ||
| 151 | :1009600075F00AA42402F582E434FCF583E030E556 | ||
| 152 | :1009700007AC42AD41121C5CE54230E21578B1E6AD | ||
| 153 | :1009800030E00F78B1E630E109E4FF04FE7C0412A8 | ||
| 154 | :10099000332978ADE62406F58218E63400F5837431 | ||
| 155 | :1009A0000FF08007E4FC7DEE121C5CC203221232C1 | ||
| 156 | :1009B00014120F7478ADE62406F58218E63400F5BB | ||
| 157 | :1009C00083E090FC38F078ADE62405F58218E63433 | ||
| 158 | :1009D00000F583E090FC39F0C2037D027C00122513 | ||
| 159 | :1009E00047123297221232147899ECF6EC24A1F8CF | ||
| 160 | :1009F000E630E1077C131225E0800F90FC39E0FD22 | ||
| 161 | :100A00007899E6FC1213F11225E012329722123285 | ||
| 162 | :100A1000147899ECF67D00120F141225E01232972B | ||
| 163 | :100A2000221232147899ECF6EC24A1F8E630E207B1 | ||
| 164 | :100A30007C131225E0801B7899E624A1F8E620E1DA | ||
| 165 | :100A4000077C121225E0800A7899E6FC1214151230 | ||
| 166 | :100A500025E0123297221232147899ECF6EC24A198 | ||
| 167 | :100A6000F8E620E2077C111225E0800A7899E6FC7E | ||
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| 765 | :102FC00000FE7C15123329227C071225E0221225EF | ||
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| 770 | :103010001225E022D3E5729448E5719400500BC369 | ||
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| 773 | :103040006D30E7087D007C05122547227C0512259E | ||
| 774 | :10305000E022B420028003D34000800012312D22F0 | ||
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| 785 | :103100007C141233292222B480004023B482005060 | ||
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| 793 | :103180006F94004015752108E5217D00FCC3E570B2 | ||
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| 801 | :10320000C32285727085716F90FF82E054F7F09051 | ||
| 802 | :10321000FF83E0547FF022C000C001C002C006C09E | ||
| 803 | :1032200007E5782408F8860653067F7CFF1232896A | ||
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| 811 | :1032A0000012337680FBC000C001C002C006C00718 | ||
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| 816 | :1032F000A3EAF0A3C083C082A3A3A380DA7808085E | ||
| 817 | :103300007918097C01E6547F6E700676007700809C | ||
| 818 | :103310000608090CBC08EE123322D007D006D002F2 | ||
| 819 | :10332000D001D00022757900857AA822C0F0C08231 | ||
| 820 | :10333000C083C3E57B24E8500512337680F4EC604B | ||
| 821 | :1033400031903651E493C39C4028C0047CFF123274 | ||
| 822 | :1033500089D004430480E57B75F003A42495F582AD | ||
| 823 | :10336000E434FDF583ECF0EFA3F0EEA3F0057B125F | ||
| 824 | :103370003322D083D082D0F022C0047C20D28CD2E1 | ||
| 825 | :103380008DD504FDD0042275A80075880075B8009D | ||
| 826 | :1033900075F00075D000E4F8900000F608B800FB66 | ||
| 827 | :1033A000020000C3ED940250047D037CE8ECF4FCC1 | ||
| 828 | :1033B000EDF4FD0CBC00010D8C7F8D7E22C3EC94DE | ||
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| 833 | :103400008C857D8AD28CC0E0C0D0C0F0C082C083E1 | ||
| 834 | :10341000C000C001C002C003C004C005C006C00790 | ||
| 835 | :10342000121AFAE5782408F8E66024E5782410F802 | ||
| 836 | :10343000A681E57875F021A4248DF582E434FCF5AD | ||
| 837 | :103440008378B4E58104C398F9E6F008A3D9FA7447 | ||
| 838 | :10345000082578F8057808E65480700CE578B407FC | ||
| 839 | :10346000F3780875780080EFE5782410F88681E518 | ||
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| 844 | :1034B00002C28E857E8D857F8BD28E781979097AAE | ||
| 845 | :1034C00007E77004A600800BE6600816E67004E7C4 | ||
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| 847 | :1034E000E5782408F87600123322D28CD28DD002EF | ||
| 848 | :1034F000D001D000D0D0D0E0327581B3742A90FFD3 | ||
| 849 | :1035000093F0757F30757EF8757D60757CF01205DF | ||
| 850 | :10351000411235AA12175D90FF93E04401F0B2B357 | ||
| 851 | :103520001235D412338480DA22C0007C01EC2408E6 | ||
| 852 | :10353000F8E660090CBC08F512337680EED0002264 | ||
| 853 | :10354000C0F0C082C083C000C006C007ED2410F8E0 | ||
| 854 | :1035500076C2ED75F021A4248DF582E434FCF58368 | ||
| 855 | :10356000C082C083A3A3E4780DF0A3D8FCEC547F01 | ||
| 856 | :1035700075F002A4241DF582E5F03436F583E4935A | ||
| 857 | :10358000FE740193F5828E83E493FE740193FFD061 | ||
| 858 | :1035900083D082EFF0A3EEF0ED2408F8EC4480F63F | ||
| 859 | :1035A000D007D006D000D083D082D0F0227578002A | ||
| 860 | :1035B000757B007A0879187808760077000809DAB0 | ||
| 861 | :1035C000F8E478087480447FF674014410F5897536 | ||
| 862 | :1035D000B808D2ABD2A9227581B3D28ED28CD2AF29 | ||
| 863 | :1035E000E57B6032FF90FD95E05480602478087997 | ||
| 864 | :1035F00008E0547FFA7B00E6547FB502027BFF08A7 | ||
| 865 | :10360000D9F5EB700CEAF0123526AD04AC02123598 | ||
| 866 | :103610003DA3A3A3DFD212337680C57C017D0022B7 | ||
| 867 | :10362000050004F404F804EC04E804E404F004FCE9 | ||
| 868 | :1036300004A804AC04D804DC04A404A404A404E096 | ||
| 869 | :1036400004C004B804BC04B404CC04C804C404D04A | ||
| 870 | :1036500004D404B0190103002200480200480E30CF | ||
| 871 | :103660001420C81AD0180A0C050602030102000132 | ||
| 872 | :10367000CE0181010000C000800060003000180011 | ||
| 873 | :1036800010000800040002000100081828380C058A | ||
| 874 | :10369000100A0200000000000301100A02000000EE | ||
| 875 | :1036A0000000FBE0FBF209022700010200A0FA097A | ||
| 876 | :1036B00004000003FF00000007058102400000072E | ||
| 877 | :1036C00005010240000007058303020001220354A4 | ||
| 878 | :1036D0000055005300420033003400310030002018 | ||
| 879 | :1036E00000200020002000200020002000200000FA | ||
| 880 | :0336F000000000D7 | ||
| 881 | :00000001FF | ||
diff --git a/firmware/mts_gsm.fw.ihex b/firmware/mts_gsm.fw.ihex new file mode 100644 index 000000000000..f6ad0cbd30cb --- /dev/null +++ b/firmware/mts_gsm.fw.ihex | |||
| @@ -0,0 +1,867 @@ | |||
| 1 | :1000000014360002001E021AF9FFFFFFFFFF023341 | ||
| 2 | :100010001DFFFFFFFFFFFFFFFFFFFFFFFFFF02339B | ||
| 3 | :10002000C87581CE90FDE88583A012353CEC4D600B | ||
| 4 | :100030007378AB8003760018B89CFA787F800376DB | ||
| 5 | :100040000018B865FA78208003760018B820FA788E | ||
| 6 | :10005000208003760018B81FFA90FDDDAE83AF82D2 | ||
| 7 | :1000600090FBF81200AA6005E4F0A380F690FDE88A | ||
| 8 | :10007000A88290FDE8A982E8696005E4F20880F7AB | ||
| 9 | :100080009001081200B390010C1200B390011012FD | ||
| 10 | :1000900000B39001141200D190011A1200D1900106 | ||
| 11 | :1000A000201200D175D00012341A020126EF6582A9 | ||
| 12 | :1000B0007003EE658322E493F8740193F97402935C | ||
| 13 | :1000C000FE740393F5828E83E869700122E493F64F | ||
| 14 | :1000D000A30880F4E493FC740193FD740293FE740E | ||
| 15 | :1000E0000393FF740493F8740593F58288831200D8 | ||
| 16 | :1000F000AA700122E493A3A883A9828C838D82F045 | ||
| 17 | :10010000A3AC83AD828883898280E32121049B8014 | ||
| 18 | :1001100080049BACAE049BFDE8049D049DFBF304AE | ||
| 19 | :10012000A2049DFBF30502050280FED0F030F00929 | ||
| 20 | :1001300020F303F68010F7800D30F10920F303F26D | ||
| 21 | :100140008004F38001F020F404FCD0E0CC22CCC089 | ||
| 22 | :10015000E0120163020154BC0005D0F0ACF022C3F0 | ||
| 23 | :1001600013DCFC02012ABF0009ED258275F001F8BD | ||
| 24 | :10017000E622BF010FED2582F582EE3583F583750A | ||
| 25 | :10018000F004E022ED258275F002F8E222D083D05F | ||
| 26 | :1001900082F5F0C3E493A3C5F095F0C0E0C3D0F0BE | ||
| 27 | :1001A000E493A395F04012A3A3C3E5F033500205F6 | ||
| 28 | :1001B000832582F58250020583740193C0E0E493A5 | ||
| 29 | :1001C000C0E022D083D082F5F0E4937009740193EB | ||
| 30 | :1001D0007004A3A3800C74029365F06005A3A3A32D | ||
| 31 | :1001E00080E7740193C0E0E493C0E022120264024D | ||
| 32 | :1001F00001FB1202B80201FB1202DC0201FB30E03B | ||
| 33 | :100200000720E302E622E72230E10720E302E222B0 | ||
| 34 | :10021000E32230E202E022E493221202DC02022313 | ||
| 35 | :100220001202B8020223ABF012022DCBC5F0CB2292 | ||
| 36 | :1002300030E01020E306E6F5F008E622E7F5F009E5 | ||
| 37 | :10024000E7192230E11020E306E2F5F008E222E3AC | ||
| 38 | :10025000F5F009E3192230E206E0F5F0A3E022E42C | ||
| 39 | :1002600093F5F074019322BB0003740922BB0107CC | ||
| 40 | :1002700089828A83740422BB020789828A8374106C | ||
| 41 | :1002800022740A22020284BB0007E92582F8740165 | ||
| 42 | :1002900022BB010DE92582F582EA3583F5837404DA | ||
| 43 | :1002A00022BB020DE92582F582EA3583F5837410BD | ||
| 44 | :1002B00022E92582F87402220202B8BF0005EDF897 | ||
| 45 | :1002C000740122BF01078D828E83740422BF02074E | ||
| 46 | :1002D0008D828E83741022EDF87402220202DCBF3C | ||
| 47 | :1002E0000007ED2582F8740122BF010DED2582F58E | ||
| 48 | :1002F00082EE3583F583740422BF020DED2582F56D | ||
| 49 | :1003000082EE3583F583741022ED2582F874022283 | ||
| 50 | :10031000020310C0E0120264020328C0E01202B817 | ||
| 51 | :10032000020328C0E01202DC02032830E00B20E3C5 | ||
| 52 | :1003300004D0E0F622D0E0F72230E10B20E304D035 | ||
| 53 | :10034000E0F222D0E0F322D0E0F022C9CDC9CACE3B | ||
| 54 | :10035000CACBCFCB12035BEDF9EEFAEFFB22BB0069 | ||
| 55 | :100360002FBF000AFAEDF8E7F60809DAFA22BF0112 | ||
| 56 | :10037000128D828E83F802037809A3E7F0D8FA225F | ||
| 57 | :10038000020383FAEDF8E7F20809DAFA2202038D94 | ||
| 58 | :10039000BB014DBF001489828A83F9EDF802039FE7 | ||
| 59 | :1003A00008A3E0F6D9FA220203B0BF01228D828EA3 | ||
| 60 | :1003B00083FB08C9C582C9CAC583CAE0A3C9C5826F | ||
| 61 | :1003C000C9CAC583CAF0A3DBEAD8E8220203D38DE9 | ||
| 62 | :1003D000828E83F9EDF8E0F208A3D9FA220203DD58 | ||
| 63 | :1003E000BB024DBF001289828A83F9EDF80203EF48 | ||
| 64 | :1003F00008A3E493F6D9F922BF01238D828E83FBF3 | ||
| 65 | :1004000008C9C582C9CAC583CAE493A3C9C582C93C | ||
| 66 | :10041000CAC583CAF0A3DBE9D8E722020422898295 | ||
| 67 | :100420008A83F9EDF8E493F208A3D9F922020433A0 | ||
| 68 | :10043000BF000DFAEDF8E3F60809DAFA2202043DEE | ||
| 69 | :10044000BF01128D828E83F802044A09A3E3F0D81B | ||
| 70 | :10045000FA22020455FAEDF8E3F20809DAFA220268 | ||
| 71 | :10046000045FE6FB08E6FA08E6F904F618700106F0 | ||
| 72 | :1004700022E6FF08E6FE08E6FD22EFF0A3EEF0A379 | ||
| 73 | :10048000EDF022EBF0A3EAF0A3E9F022E0FFA3E015 | ||
| 74 | :10049000FEA3E0FD22E0FBA3E0FAA3E0F9220000C6 | ||
| 75 | :1004A00000000000000502006105710026059800AB | ||
| 76 | :1004B000330A0900610A750066154400610CF900F1 | ||
| 77 | :1004C0006109A9006109E000610DC000610BF10044 | ||
| 78 | :1004D000610A1C00610A510061173C0033174F008C | ||
| 79 | :1004E000341E1400431EBF0044202C0044201A0078 | ||
| 80 | :1004F000471EE600471F8B004D1FDC004F1F080002 | ||
| 81 | :100500005832A800617CCC7DFF121CC52290FFFCF4 | ||
| 82 | :10051000E020E72DC2AFAE59AF58755A20E55A1406 | ||
| 83 | :10052000C55A6019E4FE7F05EE4FCE24FFCECF34CE | ||
| 84 | :10053000FFCF6007E490FF92F080ED80E08E598F4E | ||
| 85 | :10054000582212050A7D077CB71232C47D0F7C6EDB | ||
| 86 | :100550001232DE789D7A06E4F608DAFC7A06120595 | ||
| 87 | :10056000CD7C03120E55122168E4FEFF7C0F12327F | ||
| 88 | :100570004DD2A822123138E490FC38F090FFF0E020 | ||
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| 799 | :1031E00090FD95E0547F6E700BC083C082A3A3A3B3 | ||
| 800 | :1031F000157B8007A3A3A3DFEA8026DF06D082D059 | ||
| 801 | :103200008380D8E0F8A3E0F9A3E0FAD082D083E885 | ||
| 802 | :10321000F0A3E9F0A3EAF0A3C083C082A3A3A38034 | ||
| 803 | :10322000DA7808087918097C01E6547F6E70067612 | ||
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| 806 | :10325000C0F0C082C083C3E57B24E8500512329AD7 | ||
| 807 | :1032600080F4EC6031903575E493C39C4028C00431 | ||
| 808 | :103270007CFF1231ADD004430480E57B75F003A4DC | ||
| 809 | :103280002495F582E434FDF583ECF0EFA3F0EEA392 | ||
| 810 | :10329000F0057B123246D083D082D0F022C0047C6D | ||
| 811 | :1032A00020D28CD28DD504FDD0042275A80075885B | ||
| 812 | :1032B0000075B80075F00075D000E4F8900000F6D5 | ||
| 813 | :1032C00008B800FB020000C3ED940250047D037CAB | ||
| 814 | :1032D000E8ECF4FCEDF4FD0CBC00010D8C7F8D7E60 | ||
| 815 | :1032E00022C3EC94BCED940250047D077CD0ECF436 | ||
| 816 | :1032F000FCEDF4FD0CBC00010D8C7D8D7C22EC708E | ||
| 817 | :103300000122C000E5782418F8A604E5782408F81E | ||
| 818 | :10331000C6547FF6E630E703D0002212329A80F4DA | ||
| 819 | :10332000C28C857C8C857D8AD28CC0E0C0D0C0F0F8 | ||
| 820 | :10333000C082C083C000C001C002C003C004C00579 | ||
| 821 | :10334000C006C007121AF8E5782408F8E66024E5FC | ||
| 822 | :10335000782410F8A681E57875F021A4248DF582F3 | ||
| 823 | :10336000E434FCF58378AEE58104C398F9E6F0080F | ||
| 824 | :10337000A3D9FA74082578F8057808E65480700C0B | ||
| 825 | :10338000E578B407F3780875780080EFE5782410C5 | ||
| 826 | :10339000F88681E57875F021A4248DF582E434FC6B | ||
| 827 | :1033A000F58378AEE58104C398F9E0F608A3D9FA6D | ||
| 828 | :1033B000D007D006D005D004D003D002D001D00071 | ||
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| 830 | :1033D00000C001C002C28E857E8D857F8BD28E7823 | ||
| 831 | :1033E0001979097A07E77004A600800BE6600816D1 | ||
| 832 | :1033F000E67004E74480F70809DAEAE57960131417 | ||
| 833 | :10340000F579700EE5782408F87600123246D28CF1 | ||
| 834 | :10341000D28DD002D001D000D0D0D0E0327581ADB5 | ||
| 835 | :10342000742A90FF93F0757F30757EF8757D607516 | ||
| 836 | :103430007CF012053F1234CE12175B90FF93E044EC | ||
| 837 | :1034400001F0B2B31234F81232A880DA22C0007C44 | ||
| 838 | :1034500001EC2408F8E660090CBC08F512329A80E9 | ||
| 839 | :10346000EED00022C0F0C082C083C000C006C007FA | ||
| 840 | :10347000ED2410F876BCED75F021A4248DF582E4DE | ||
| 841 | :1034800034FCF583C082C083A3A3E4780DF0A3D8F5 | ||
| 842 | :10349000FCEC547F75F002A42441F582E5F034354C | ||
| 843 | :1034A000F583E493FE740193F5828E83E493FE74B6 | ||
| 844 | :1034B0000193FFD083D082EFF0A3EEF0ED2408F863 | ||
| 845 | :1034C000EC4480F6D007D006D000D083D082D0F074 | ||
| 846 | :1034D00022757800757B007A08791878087600776D | ||
| 847 | :1034E000000809DAF8E478087480447FF67401442F | ||
| 848 | :1034F00010F58975B808D2ABD2A9227581ADD28EEC | ||
| 849 | :10350000D28CD2AFE57B6032FF90FD95E0548060B5 | ||
| 850 | :103510002478087908E0547FFA7B00E6547FB502EE | ||
| 851 | :10352000027BFF08D9F5EB700CEAF012344AAD04C7 | ||
| 852 | :10353000AC02123461A3A3A3DFD212329A80C57CFD | ||
| 853 | :10354000017D002204FE04F204F604EA04E604E22B | ||
| 854 | :1035500004EE04FA04A604AA04D604DA04A204A21F | ||
| 855 | :1035600004A204DE04BE04B604BA04B204CA04C64B | ||
| 856 | :1035700004C204CE04D204AE1901030022004802A2 | ||
| 857 | :1035800000480E301420C81AD0180A0C0506020391 | ||
| 858 | :1035900001020001CE0181010000C0008000600036 | ||
| 859 | :1035A0003000180010000800040002000100081894 | ||
| 860 | :1035B00028380C05100A0200000000000301100A60 | ||
| 861 | :1035C000020000000000FBE0FBF2090227000102FC | ||
| 862 | :1035D00000A0FA0904000003FF00000007058102B3 | ||
| 863 | :1035E00040000007050102400000070583030200B8 | ||
| 864 | :1035F00001220354005500530042003300340031CF | ||
| 865 | :1036000000300020002000200020002000200020AA | ||
| 866 | :073610000020000000000093 | ||
| 867 | :00000001FF | ||
diff --git a/fs/dlm/debug_fs.c b/fs/dlm/debug_fs.c index 2f107d1a6a45..1d1d27442235 100644 --- a/fs/dlm/debug_fs.c +++ b/fs/dlm/debug_fs.c | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /****************************************************************************** | 1 | /****************************************************************************** |
| 2 | ******************************************************************************* | 2 | ******************************************************************************* |
| 3 | ** | 3 | ** |
| 4 | ** Copyright (C) 2005-2008 Red Hat, Inc. All rights reserved. | 4 | ** Copyright (C) 2005-2009 Red Hat, Inc. All rights reserved. |
| 5 | ** | 5 | ** |
| 6 | ** This copyrighted material is made available to anyone wishing to use, | 6 | ** This copyrighted material is made available to anyone wishing to use, |
| 7 | ** modify, copy, or redistribute it subject to the terms and conditions | 7 | ** modify, copy, or redistribute it subject to the terms and conditions |
| @@ -25,19 +25,6 @@ static struct mutex debug_buf_lock; | |||
| 25 | 25 | ||
| 26 | static struct dentry *dlm_root; | 26 | static struct dentry *dlm_root; |
| 27 | 27 | ||
| 28 | struct rsb_iter { | ||
| 29 | int entry; | ||
| 30 | int format; | ||
| 31 | int header; | ||
| 32 | struct dlm_ls *ls; | ||
| 33 | struct list_head *next; | ||
| 34 | struct dlm_rsb *rsb; | ||
| 35 | }; | ||
| 36 | |||
| 37 | /* | ||
| 38 | * dump all rsb's in the lockspace hash table | ||
| 39 | */ | ||
| 40 | |||
| 41 | static char *print_lockmode(int mode) | 28 | static char *print_lockmode(int mode) |
| 42 | { | 29 | { |
| 43 | switch (mode) { | 30 | switch (mode) { |
| @@ -60,13 +47,13 @@ static char *print_lockmode(int mode) | |||
| 60 | } | 47 | } |
| 61 | } | 48 | } |
| 62 | 49 | ||
| 63 | static void print_format1_lock(struct seq_file *s, struct dlm_lkb *lkb, | 50 | static int print_format1_lock(struct seq_file *s, struct dlm_lkb *lkb, |
| 64 | struct dlm_rsb *res) | 51 | struct dlm_rsb *res) |
| 65 | { | 52 | { |
| 66 | seq_printf(s, "%08x %s", lkb->lkb_id, print_lockmode(lkb->lkb_grmode)); | 53 | seq_printf(s, "%08x %s", lkb->lkb_id, print_lockmode(lkb->lkb_grmode)); |
| 67 | 54 | ||
| 68 | if (lkb->lkb_status == DLM_LKSTS_CONVERT | 55 | if (lkb->lkb_status == DLM_LKSTS_CONVERT || |
| 69 | || lkb->lkb_status == DLM_LKSTS_WAITING) | 56 | lkb->lkb_status == DLM_LKSTS_WAITING) |
| 70 | seq_printf(s, " (%s)", print_lockmode(lkb->lkb_rqmode)); | 57 | seq_printf(s, " (%s)", print_lockmode(lkb->lkb_rqmode)); |
| 71 | 58 | ||
| 72 | if (lkb->lkb_nodeid) { | 59 | if (lkb->lkb_nodeid) { |
| @@ -80,33 +67,42 @@ static void print_format1_lock(struct seq_file *s, struct dlm_lkb *lkb, | |||
| 80 | if (lkb->lkb_wait_type) | 67 | if (lkb->lkb_wait_type) |
| 81 | seq_printf(s, " wait_type: %d", lkb->lkb_wait_type); | 68 | seq_printf(s, " wait_type: %d", lkb->lkb_wait_type); |
| 82 | 69 | ||
| 83 | seq_printf(s, "\n"); | 70 | return seq_printf(s, "\n"); |
| 84 | } | 71 | } |
| 85 | 72 | ||
| 86 | static int print_format1(struct dlm_rsb *res, struct seq_file *s) | 73 | static int print_format1(struct dlm_rsb *res, struct seq_file *s) |
| 87 | { | 74 | { |
| 88 | struct dlm_lkb *lkb; | 75 | struct dlm_lkb *lkb; |
| 89 | int i, lvblen = res->res_ls->ls_lvblen, recover_list, root_list; | 76 | int i, lvblen = res->res_ls->ls_lvblen, recover_list, root_list; |
| 77 | int rv; | ||
| 90 | 78 | ||
| 91 | lock_rsb(res); | 79 | lock_rsb(res); |
| 92 | 80 | ||
| 93 | seq_printf(s, "\nResource %p Name (len=%d) \"", res, res->res_length); | 81 | rv = seq_printf(s, "\nResource %p Name (len=%d) \"", |
| 82 | res, res->res_length); | ||
| 83 | if (rv) | ||
| 84 | goto out; | ||
| 85 | |||
| 94 | for (i = 0; i < res->res_length; i++) { | 86 | for (i = 0; i < res->res_length; i++) { |
| 95 | if (isprint(res->res_name[i])) | 87 | if (isprint(res->res_name[i])) |
| 96 | seq_printf(s, "%c", res->res_name[i]); | 88 | seq_printf(s, "%c", res->res_name[i]); |
| 97 | else | 89 | else |
| 98 | seq_printf(s, "%c", '.'); | 90 | seq_printf(s, "%c", '.'); |
| 99 | } | 91 | } |
| 92 | |||
| 100 | if (res->res_nodeid > 0) | 93 | if (res->res_nodeid > 0) |
| 101 | seq_printf(s, "\" \nLocal Copy, Master is node %d\n", | 94 | rv = seq_printf(s, "\" \nLocal Copy, Master is node %d\n", |
| 102 | res->res_nodeid); | 95 | res->res_nodeid); |
| 103 | else if (res->res_nodeid == 0) | 96 | else if (res->res_nodeid == 0) |
| 104 | seq_printf(s, "\" \nMaster Copy\n"); | 97 | rv = seq_printf(s, "\" \nMaster Copy\n"); |
| 105 | else if (res->res_nodeid == -1) | 98 | else if (res->res_nodeid == -1) |
| 106 | seq_printf(s, "\" \nLooking up master (lkid %x)\n", | 99 | rv = seq_printf(s, "\" \nLooking up master (lkid %x)\n", |
| 107 | res->res_first_lkid); | 100 | res->res_first_lkid); |
| 108 | else | 101 | else |
| 109 | seq_printf(s, "\" \nInvalid master %d\n", res->res_nodeid); | 102 | rv = seq_printf(s, "\" \nInvalid master %d\n", |
| 103 | res->res_nodeid); | ||
| 104 | if (rv) | ||
| 105 | goto out; | ||
| 110 | 106 | ||
| 111 | /* Print the LVB: */ | 107 | /* Print the LVB: */ |
| 112 | if (res->res_lvbptr) { | 108 | if (res->res_lvbptr) { |
| @@ -119,52 +115,66 @@ static int print_format1(struct dlm_rsb *res, struct seq_file *s) | |||
| 119 | } | 115 | } |
| 120 | if (rsb_flag(res, RSB_VALNOTVALID)) | 116 | if (rsb_flag(res, RSB_VALNOTVALID)) |
| 121 | seq_printf(s, " (INVALID)"); | 117 | seq_printf(s, " (INVALID)"); |
| 122 | seq_printf(s, "\n"); | 118 | rv = seq_printf(s, "\n"); |
| 119 | if (rv) | ||
| 120 | goto out; | ||
| 123 | } | 121 | } |
| 124 | 122 | ||
| 125 | root_list = !list_empty(&res->res_root_list); | 123 | root_list = !list_empty(&res->res_root_list); |
| 126 | recover_list = !list_empty(&res->res_recover_list); | 124 | recover_list = !list_empty(&res->res_recover_list); |
| 127 | 125 | ||
| 128 | if (root_list || recover_list) { | 126 | if (root_list || recover_list) { |
| 129 | seq_printf(s, "Recovery: root %d recover %d flags %lx " | 127 | rv = seq_printf(s, "Recovery: root %d recover %d flags %lx " |
| 130 | "count %d\n", root_list, recover_list, | 128 | "count %d\n", root_list, recover_list, |
| 131 | res->res_flags, res->res_recover_locks_count); | 129 | res->res_flags, res->res_recover_locks_count); |
| 130 | if (rv) | ||
| 131 | goto out; | ||
| 132 | } | 132 | } |
| 133 | 133 | ||
| 134 | /* Print the locks attached to this resource */ | 134 | /* Print the locks attached to this resource */ |
| 135 | seq_printf(s, "Granted Queue\n"); | 135 | seq_printf(s, "Granted Queue\n"); |
| 136 | list_for_each_entry(lkb, &res->res_grantqueue, lkb_statequeue) | 136 | list_for_each_entry(lkb, &res->res_grantqueue, lkb_statequeue) { |
| 137 | print_format1_lock(s, lkb, res); | 137 | rv = print_format1_lock(s, lkb, res); |
| 138 | if (rv) | ||
| 139 | goto out; | ||
| 140 | } | ||
| 138 | 141 | ||
| 139 | seq_printf(s, "Conversion Queue\n"); | 142 | seq_printf(s, "Conversion Queue\n"); |
| 140 | list_for_each_entry(lkb, &res->res_convertqueue, lkb_statequeue) | 143 | list_for_each_entry(lkb, &res->res_convertqueue, lkb_statequeue) { |
| 141 | print_format1_lock(s, lkb, res); | 144 | rv = print_format1_lock(s, lkb, res); |
| 145 | if (rv) | ||
| 146 | goto out; | ||
| 147 | } | ||
| 142 | 148 | ||
| 143 | seq_printf(s, "Waiting Queue\n"); | 149 | seq_printf(s, "Waiting Queue\n"); |
| 144 | list_for_each_entry(lkb, &res->res_waitqueue, lkb_statequeue) | 150 | list_for_each_entry(lkb, &res->res_waitqueue, lkb_statequeue) { |
| 145 | print_format1_lock(s, lkb, res); | 151 | rv = print_format1_lock(s, lkb, res); |
| 152 | if (rv) | ||
| 153 | goto out; | ||
| 154 | } | ||
| 146 | 155 | ||
| 147 | if (list_empty(&res->res_lookup)) | 156 | if (list_empty(&res->res_lookup)) |
| 148 | goto out; | 157 | goto out; |
| 149 | 158 | ||
| 150 | seq_printf(s, "Lookup Queue\n"); | 159 | seq_printf(s, "Lookup Queue\n"); |
| 151 | list_for_each_entry(lkb, &res->res_lookup, lkb_rsb_lookup) { | 160 | list_for_each_entry(lkb, &res->res_lookup, lkb_rsb_lookup) { |
| 152 | seq_printf(s, "%08x %s", lkb->lkb_id, | 161 | rv = seq_printf(s, "%08x %s", lkb->lkb_id, |
| 153 | print_lockmode(lkb->lkb_rqmode)); | 162 | print_lockmode(lkb->lkb_rqmode)); |
| 154 | if (lkb->lkb_wait_type) | 163 | if (lkb->lkb_wait_type) |
| 155 | seq_printf(s, " wait_type: %d", lkb->lkb_wait_type); | 164 | seq_printf(s, " wait_type: %d", lkb->lkb_wait_type); |
| 156 | seq_printf(s, "\n"); | 165 | rv = seq_printf(s, "\n"); |
| 157 | } | 166 | } |
| 158 | out: | 167 | out: |
| 159 | unlock_rsb(res); | 168 | unlock_rsb(res); |
| 160 | return 0; | 169 | return rv; |
| 161 | } | 170 | } |
| 162 | 171 | ||
| 163 | static void print_format2_lock(struct seq_file *s, struct dlm_lkb *lkb, | 172 | static int print_format2_lock(struct seq_file *s, struct dlm_lkb *lkb, |
| 164 | struct dlm_rsb *r) | 173 | struct dlm_rsb *r) |
| 165 | { | 174 | { |
| 166 | u64 xid = 0; | 175 | u64 xid = 0; |
| 167 | u64 us; | 176 | u64 us; |
| 177 | int rv; | ||
| 168 | 178 | ||
| 169 | if (lkb->lkb_flags & DLM_IFL_USER) { | 179 | if (lkb->lkb_flags & DLM_IFL_USER) { |
| 170 | if (lkb->lkb_ua) | 180 | if (lkb->lkb_ua) |
| @@ -177,69 +187,82 @@ static void print_format2_lock(struct seq_file *s, struct dlm_lkb *lkb, | |||
| 177 | /* id nodeid remid pid xid exflags flags sts grmode rqmode time_us | 187 | /* id nodeid remid pid xid exflags flags sts grmode rqmode time_us |
| 178 | r_nodeid r_len r_name */ | 188 | r_nodeid r_len r_name */ |
| 179 | 189 | ||
| 180 | seq_printf(s, "%x %d %x %u %llu %x %x %d %d %d %llu %u %d \"%s\"\n", | 190 | rv = seq_printf(s, "%x %d %x %u %llu %x %x %d %d %d %llu %u %d \"%s\"\n", |
| 181 | lkb->lkb_id, | 191 | lkb->lkb_id, |
| 182 | lkb->lkb_nodeid, | 192 | lkb->lkb_nodeid, |
| 183 | lkb->lkb_remid, | 193 | lkb->lkb_remid, |
| 184 | lkb->lkb_ownpid, | 194 | lkb->lkb_ownpid, |
| 185 | (unsigned long long)xid, | 195 | (unsigned long long)xid, |
| 186 | lkb->lkb_exflags, | 196 | lkb->lkb_exflags, |
| 187 | lkb->lkb_flags, | 197 | lkb->lkb_flags, |
| 188 | lkb->lkb_status, | 198 | lkb->lkb_status, |
| 189 | lkb->lkb_grmode, | 199 | lkb->lkb_grmode, |
| 190 | lkb->lkb_rqmode, | 200 | lkb->lkb_rqmode, |
| 191 | (unsigned long long)us, | 201 | (unsigned long long)us, |
| 192 | r->res_nodeid, | 202 | r->res_nodeid, |
| 193 | r->res_length, | 203 | r->res_length, |
| 194 | r->res_name); | 204 | r->res_name); |
| 205 | return rv; | ||
| 195 | } | 206 | } |
| 196 | 207 | ||
| 197 | static int print_format2(struct dlm_rsb *r, struct seq_file *s) | 208 | static int print_format2(struct dlm_rsb *r, struct seq_file *s) |
| 198 | { | 209 | { |
| 199 | struct dlm_lkb *lkb; | 210 | struct dlm_lkb *lkb; |
| 211 | int rv = 0; | ||
| 200 | 212 | ||
| 201 | lock_rsb(r); | 213 | lock_rsb(r); |
| 202 | 214 | ||
| 203 | list_for_each_entry(lkb, &r->res_grantqueue, lkb_statequeue) | 215 | list_for_each_entry(lkb, &r->res_grantqueue, lkb_statequeue) { |
| 204 | print_format2_lock(s, lkb, r); | 216 | rv = print_format2_lock(s, lkb, r); |
| 205 | 217 | if (rv) | |
| 206 | list_for_each_entry(lkb, &r->res_convertqueue, lkb_statequeue) | 218 | goto out; |
| 207 | print_format2_lock(s, lkb, r); | 219 | } |
| 208 | 220 | ||
| 209 | list_for_each_entry(lkb, &r->res_waitqueue, lkb_statequeue) | 221 | list_for_each_entry(lkb, &r->res_convertqueue, lkb_statequeue) { |
| 210 | print_format2_lock(s, lkb, r); | 222 | rv = print_format2_lock(s, lkb, r); |
| 223 | if (rv) | ||
| 224 | goto out; | ||
| 225 | } | ||
| 211 | 226 | ||
| 227 | list_for_each_entry(lkb, &r->res_waitqueue, lkb_statequeue) { | ||
| 228 | rv = print_format2_lock(s, lkb, r); | ||
| 229 | if (rv) | ||
| 230 | goto out; | ||
| 231 | } | ||
| 232 | out: | ||
| 212 | unlock_rsb(r); | 233 | unlock_rsb(r); |
| 213 | return 0; | 234 | return rv; |
| 214 | } | 235 | } |
| 215 | 236 | ||
| 216 | static void print_format3_lock(struct seq_file *s, struct dlm_lkb *lkb, | 237 | static int print_format3_lock(struct seq_file *s, struct dlm_lkb *lkb, |
| 217 | int rsb_lookup) | 238 | int rsb_lookup) |
| 218 | { | 239 | { |
| 219 | u64 xid = 0; | 240 | u64 xid = 0; |
| 241 | int rv; | ||
| 220 | 242 | ||
| 221 | if (lkb->lkb_flags & DLM_IFL_USER) { | 243 | if (lkb->lkb_flags & DLM_IFL_USER) { |
| 222 | if (lkb->lkb_ua) | 244 | if (lkb->lkb_ua) |
| 223 | xid = lkb->lkb_ua->xid; | 245 | xid = lkb->lkb_ua->xid; |
| 224 | } | 246 | } |
| 225 | 247 | ||
| 226 | seq_printf(s, "lkb %x %d %x %u %llu %x %x %d %d %d %d %d %d %u %llu %llu\n", | 248 | rv = seq_printf(s, "lkb %x %d %x %u %llu %x %x %d %d %d %d %d %d %u %llu %llu\n", |
| 227 | lkb->lkb_id, | 249 | lkb->lkb_id, |
| 228 | lkb->lkb_nodeid, | 250 | lkb->lkb_nodeid, |
| 229 | lkb->lkb_remid, | 251 | lkb->lkb_remid, |
| 230 | lkb->lkb_ownpid, | 252 | lkb->lkb_ownpid, |
| 231 | (unsigned long long)xid, | 253 | (unsigned long long)xid, |
| 232 | lkb->lkb_exflags, | 254 | lkb->lkb_exflags, |
| 233 | lkb->lkb_flags, | 255 | lkb->lkb_flags, |
| 234 | lkb->lkb_status, | 256 | lkb->lkb_status, |
| 235 | lkb->lkb_grmode, | 257 | lkb->lkb_grmode, |
| 236 | lkb->lkb_rqmode, | 258 | lkb->lkb_rqmode, |
| 237 | lkb->lkb_highbast, | 259 | lkb->lkb_highbast, |
| 238 | rsb_lookup, | 260 | rsb_lookup, |
| 239 | lkb->lkb_wait_type, | 261 | lkb->lkb_wait_type, |
| 240 | lkb->lkb_lvbseq, | 262 | lkb->lkb_lvbseq, |
| 241 | (unsigned long long)ktime_to_ns(lkb->lkb_timestamp), | 263 | (unsigned long long)ktime_to_ns(lkb->lkb_timestamp), |
| 242 | (unsigned long long)ktime_to_ns(lkb->lkb_time_bast)); | 264 | (unsigned long long)ktime_to_ns(lkb->lkb_time_bast)); |
| 265 | return rv; | ||
| 243 | } | 266 | } |
| 244 | 267 | ||
| 245 | static int print_format3(struct dlm_rsb *r, struct seq_file *s) | 268 | static int print_format3(struct dlm_rsb *r, struct seq_file *s) |
| @@ -247,18 +270,21 @@ static int print_format3(struct dlm_rsb *r, struct seq_file *s) | |||
| 247 | struct dlm_lkb *lkb; | 270 | struct dlm_lkb *lkb; |
| 248 | int i, lvblen = r->res_ls->ls_lvblen; | 271 | int i, lvblen = r->res_ls->ls_lvblen; |
| 249 | int print_name = 1; | 272 | int print_name = 1; |
| 273 | int rv; | ||
| 250 | 274 | ||
| 251 | lock_rsb(r); | 275 | lock_rsb(r); |
| 252 | 276 | ||
| 253 | seq_printf(s, "rsb %p %d %x %lx %d %d %u %d ", | 277 | rv = seq_printf(s, "rsb %p %d %x %lx %d %d %u %d ", |
| 254 | r, | 278 | r, |
| 255 | r->res_nodeid, | 279 | r->res_nodeid, |
| 256 | r->res_first_lkid, | 280 | r->res_first_lkid, |
| 257 | r->res_flags, | 281 | r->res_flags, |
| 258 | !list_empty(&r->res_root_list), | 282 | !list_empty(&r->res_root_list), |
| 259 | !list_empty(&r->res_recover_list), | 283 | !list_empty(&r->res_recover_list), |
| 260 | r->res_recover_locks_count, | 284 | r->res_recover_locks_count, |
| 261 | r->res_length); | 285 | r->res_length); |
| 286 | if (rv) | ||
| 287 | goto out; | ||
| 262 | 288 | ||
| 263 | for (i = 0; i < r->res_length; i++) { | 289 | for (i = 0; i < r->res_length; i++) { |
| 264 | if (!isascii(r->res_name[i]) || !isprint(r->res_name[i])) | 290 | if (!isascii(r->res_name[i]) || !isprint(r->res_name[i])) |
| @@ -273,7 +299,9 @@ static int print_format3(struct dlm_rsb *r, struct seq_file *s) | |||
| 273 | else | 299 | else |
| 274 | seq_printf(s, " %02x", (unsigned char)r->res_name[i]); | 300 | seq_printf(s, " %02x", (unsigned char)r->res_name[i]); |
| 275 | } | 301 | } |
| 276 | seq_printf(s, "\n"); | 302 | rv = seq_printf(s, "\n"); |
| 303 | if (rv) | ||
| 304 | goto out; | ||
| 277 | 305 | ||
| 278 | if (!r->res_lvbptr) | 306 | if (!r->res_lvbptr) |
| 279 | goto do_locks; | 307 | goto do_locks; |
| @@ -282,344 +310,294 @@ static int print_format3(struct dlm_rsb *r, struct seq_file *s) | |||
| 282 | 310 | ||
| 283 | for (i = 0; i < lvblen; i++) | 311 | for (i = 0; i < lvblen; i++) |
| 284 | seq_printf(s, " %02x", (unsigned char)r->res_lvbptr[i]); | 312 | seq_printf(s, " %02x", (unsigned char)r->res_lvbptr[i]); |
| 285 | seq_printf(s, "\n"); | 313 | rv = seq_printf(s, "\n"); |
| 314 | if (rv) | ||
| 315 | goto out; | ||
| 286 | 316 | ||
| 287 | do_locks: | 317 | do_locks: |
| 288 | list_for_each_entry(lkb, &r->res_grantqueue, lkb_statequeue) | 318 | list_for_each_entry(lkb, &r->res_grantqueue, lkb_statequeue) { |
| 289 | print_format3_lock(s, lkb, 0); | 319 | rv = print_format3_lock(s, lkb, 0); |
| 290 | 320 | if (rv) | |
| 291 | list_for_each_entry(lkb, &r->res_convertqueue, lkb_statequeue) | 321 | goto out; |
| 292 | print_format3_lock(s, lkb, 0); | ||
| 293 | |||
| 294 | list_for_each_entry(lkb, &r->res_waitqueue, lkb_statequeue) | ||
| 295 | print_format3_lock(s, lkb, 0); | ||
| 296 | |||
| 297 | list_for_each_entry(lkb, &r->res_lookup, lkb_rsb_lookup) | ||
| 298 | print_format3_lock(s, lkb, 1); | ||
| 299 | |||
| 300 | unlock_rsb(r); | ||
| 301 | return 0; | ||
| 302 | } | ||
| 303 | |||
| 304 | static int rsb_iter_next(struct rsb_iter *ri) | ||
| 305 | { | ||
| 306 | struct dlm_ls *ls = ri->ls; | ||
| 307 | int i; | ||
| 308 | |||
| 309 | if (!ri->next) { | ||
| 310 | top: | ||
| 311 | /* Find the next non-empty hash bucket */ | ||
| 312 | for (i = ri->entry; i < ls->ls_rsbtbl_size; i++) { | ||
| 313 | read_lock(&ls->ls_rsbtbl[i].lock); | ||
| 314 | if (!list_empty(&ls->ls_rsbtbl[i].list)) { | ||
| 315 | ri->next = ls->ls_rsbtbl[i].list.next; | ||
| 316 | ri->rsb = list_entry(ri->next, struct dlm_rsb, | ||
| 317 | res_hashchain); | ||
| 318 | dlm_hold_rsb(ri->rsb); | ||
| 319 | read_unlock(&ls->ls_rsbtbl[i].lock); | ||
| 320 | break; | ||
| 321 | } | ||
| 322 | read_unlock(&ls->ls_rsbtbl[i].lock); | ||
| 323 | } | ||
| 324 | ri->entry = i; | ||
| 325 | |||
| 326 | if (ri->entry >= ls->ls_rsbtbl_size) | ||
| 327 | return 1; | ||
| 328 | } else { | ||
| 329 | struct dlm_rsb *old = ri->rsb; | ||
| 330 | i = ri->entry; | ||
| 331 | read_lock(&ls->ls_rsbtbl[i].lock); | ||
| 332 | ri->next = ri->next->next; | ||
| 333 | if (ri->next->next == ls->ls_rsbtbl[i].list.next) { | ||
| 334 | /* End of list - move to next bucket */ | ||
| 335 | ri->next = NULL; | ||
| 336 | ri->entry++; | ||
| 337 | read_unlock(&ls->ls_rsbtbl[i].lock); | ||
| 338 | dlm_put_rsb(old); | ||
| 339 | goto top; | ||
| 340 | } | ||
| 341 | ri->rsb = list_entry(ri->next, struct dlm_rsb, res_hashchain); | ||
| 342 | dlm_hold_rsb(ri->rsb); | ||
| 343 | read_unlock(&ls->ls_rsbtbl[i].lock); | ||
| 344 | dlm_put_rsb(old); | ||
| 345 | } | 322 | } |
| 346 | 323 | ||
| 347 | return 0; | 324 | list_for_each_entry(lkb, &r->res_convertqueue, lkb_statequeue) { |
| 348 | } | 325 | rv = print_format3_lock(s, lkb, 0); |
| 349 | 326 | if (rv) | |
| 350 | static void rsb_iter_free(struct rsb_iter *ri) | 327 | goto out; |
| 351 | { | ||
| 352 | kfree(ri); | ||
| 353 | } | ||
| 354 | |||
| 355 | static struct rsb_iter *rsb_iter_init(struct dlm_ls *ls) | ||
| 356 | { | ||
| 357 | struct rsb_iter *ri; | ||
| 358 | |||
| 359 | ri = kzalloc(sizeof *ri, GFP_KERNEL); | ||
| 360 | if (!ri) | ||
| 361 | return NULL; | ||
| 362 | |||
| 363 | ri->ls = ls; | ||
| 364 | ri->entry = 0; | ||
| 365 | ri->next = NULL; | ||
| 366 | ri->format = 1; | ||
| 367 | |||
| 368 | if (rsb_iter_next(ri)) { | ||
| 369 | rsb_iter_free(ri); | ||
| 370 | return NULL; | ||
| 371 | } | 328 | } |
| 372 | 329 | ||
| 373 | return ri; | 330 | list_for_each_entry(lkb, &r->res_waitqueue, lkb_statequeue) { |
| 374 | } | 331 | rv = print_format3_lock(s, lkb, 0); |
| 375 | 332 | if (rv) | |
| 376 | static void *rsb_seq_start(struct seq_file *file, loff_t *pos) | 333 | goto out; |
| 377 | { | ||
| 378 | struct rsb_iter *ri; | ||
| 379 | loff_t n = *pos; | ||
| 380 | |||
| 381 | ri = rsb_iter_init(file->private); | ||
| 382 | if (!ri) | ||
| 383 | return NULL; | ||
| 384 | |||
| 385 | while (n--) { | ||
| 386 | if (rsb_iter_next(ri)) { | ||
| 387 | rsb_iter_free(ri); | ||
| 388 | return NULL; | ||
| 389 | } | ||
| 390 | } | 334 | } |
| 391 | 335 | ||
| 392 | return ri; | 336 | list_for_each_entry(lkb, &r->res_lookup, lkb_rsb_lookup) { |
| 393 | } | 337 | rv = print_format3_lock(s, lkb, 1); |
| 394 | 338 | if (rv) | |
| 395 | static void *rsb_seq_next(struct seq_file *file, void *iter_ptr, loff_t *pos) | 339 | goto out; |
| 396 | { | ||
| 397 | struct rsb_iter *ri = iter_ptr; | ||
| 398 | |||
| 399 | (*pos)++; | ||
| 400 | |||
| 401 | if (rsb_iter_next(ri)) { | ||
| 402 | rsb_iter_free(ri); | ||
| 403 | return NULL; | ||
| 404 | } | 340 | } |
| 405 | 341 | out: | |
| 406 | return ri; | 342 | unlock_rsb(r); |
| 343 | return rv; | ||
| 407 | } | 344 | } |
| 408 | 345 | ||
| 409 | static void rsb_seq_stop(struct seq_file *file, void *iter_ptr) | 346 | struct rsbtbl_iter { |
| 410 | { | 347 | struct dlm_rsb *rsb; |
| 411 | /* nothing for now */ | 348 | unsigned bucket; |
| 412 | } | 349 | int format; |
| 350 | int header; | ||
| 351 | }; | ||
| 413 | 352 | ||
| 414 | static int rsb_seq_show(struct seq_file *file, void *iter_ptr) | 353 | /* seq_printf returns -1 if the buffer is full, and 0 otherwise. |
| 354 | If the buffer is full, seq_printf can be called again, but it | ||
| 355 | does nothing and just returns -1. So, the these printing routines | ||
| 356 | periodically check the return value to avoid wasting too much time | ||
| 357 | trying to print to a full buffer. */ | ||
| 358 | |||
| 359 | static int table_seq_show(struct seq_file *seq, void *iter_ptr) | ||
| 415 | { | 360 | { |
| 416 | struct rsb_iter *ri = iter_ptr; | 361 | struct rsbtbl_iter *ri = iter_ptr; |
| 362 | int rv = 0; | ||
| 417 | 363 | ||
| 418 | switch (ri->format) { | 364 | switch (ri->format) { |
| 419 | case 1: | 365 | case 1: |
| 420 | print_format1(ri->rsb, file); | 366 | rv = print_format1(ri->rsb, seq); |
| 421 | break; | 367 | break; |
| 422 | case 2: | 368 | case 2: |
| 423 | if (ri->header) { | 369 | if (ri->header) { |
| 424 | seq_printf(file, "id nodeid remid pid xid exflags " | 370 | seq_printf(seq, "id nodeid remid pid xid exflags " |
| 425 | "flags sts grmode rqmode time_ms " | 371 | "flags sts grmode rqmode time_ms " |
| 426 | "r_nodeid r_len r_name\n"); | 372 | "r_nodeid r_len r_name\n"); |
| 427 | ri->header = 0; | 373 | ri->header = 0; |
| 428 | } | 374 | } |
| 429 | print_format2(ri->rsb, file); | 375 | rv = print_format2(ri->rsb, seq); |
| 430 | break; | 376 | break; |
| 431 | case 3: | 377 | case 3: |
| 432 | if (ri->header) { | 378 | if (ri->header) { |
| 433 | seq_printf(file, "version rsb 1.1 lvb 1.1 lkb 1.1\n"); | 379 | seq_printf(seq, "version rsb 1.1 lvb 1.1 lkb 1.1\n"); |
| 434 | ri->header = 0; | 380 | ri->header = 0; |
| 435 | } | 381 | } |
| 436 | print_format3(ri->rsb, file); | 382 | rv = print_format3(ri->rsb, seq); |
| 437 | break; | 383 | break; |
| 438 | } | 384 | } |
| 439 | 385 | ||
| 440 | return 0; | 386 | return rv; |
| 441 | } | 387 | } |
| 442 | 388 | ||
| 443 | static struct seq_operations rsb_seq_ops = { | 389 | static struct seq_operations format1_seq_ops; |
| 444 | .start = rsb_seq_start, | 390 | static struct seq_operations format2_seq_ops; |
| 445 | .next = rsb_seq_next, | 391 | static struct seq_operations format3_seq_ops; |
| 446 | .stop = rsb_seq_stop, | ||
| 447 | .show = rsb_seq_show, | ||
| 448 | }; | ||
| 449 | 392 | ||
| 450 | static int rsb_open(struct inode *inode, struct file *file) | 393 | static void *table_seq_start(struct seq_file *seq, loff_t *pos) |
| 451 | { | 394 | { |
| 452 | struct seq_file *seq; | 395 | struct dlm_ls *ls = seq->private; |
| 453 | int ret; | 396 | struct rsbtbl_iter *ri; |
| 454 | 397 | struct dlm_rsb *r; | |
| 455 | ret = seq_open(file, &rsb_seq_ops); | 398 | loff_t n = *pos; |
| 456 | if (ret) | 399 | unsigned bucket, entry; |
| 457 | return ret; | ||
| 458 | |||
| 459 | seq = file->private_data; | ||
| 460 | seq->private = inode->i_private; | ||
| 461 | |||
| 462 | return 0; | ||
| 463 | } | ||
| 464 | |||
| 465 | static const struct file_operations rsb_fops = { | ||
| 466 | .owner = THIS_MODULE, | ||
| 467 | .open = rsb_open, | ||
| 468 | .read = seq_read, | ||
| 469 | .llseek = seq_lseek, | ||
| 470 | .release = seq_release | ||
| 471 | }; | ||
| 472 | 400 | ||
| 473 | /* | 401 | bucket = n >> 32; |
| 474 | * Dump state in compact per-lock listing | 402 | entry = n & ((1LL << 32) - 1); |
| 475 | */ | ||
| 476 | 403 | ||
| 477 | static struct rsb_iter *locks_iter_init(struct dlm_ls *ls, loff_t *pos) | 404 | if (bucket >= ls->ls_rsbtbl_size) |
| 478 | { | 405 | return NULL; |
| 479 | struct rsb_iter *ri; | ||
| 480 | 406 | ||
| 481 | ri = kzalloc(sizeof *ri, GFP_KERNEL); | 407 | ri = kzalloc(sizeof(struct rsbtbl_iter), GFP_KERNEL); |
| 482 | if (!ri) | 408 | if (!ri) |
| 483 | return NULL; | 409 | return NULL; |
| 484 | 410 | if (n == 0) | |
| 485 | ri->ls = ls; | ||
| 486 | ri->entry = 0; | ||
| 487 | ri->next = NULL; | ||
| 488 | ri->format = 2; | ||
| 489 | |||
| 490 | if (*pos == 0) | ||
| 491 | ri->header = 1; | 411 | ri->header = 1; |
| 492 | 412 | if (seq->op == &format1_seq_ops) | |
| 493 | if (rsb_iter_next(ri)) { | 413 | ri->format = 1; |
| 494 | rsb_iter_free(ri); | 414 | if (seq->op == &format2_seq_ops) |
| 495 | return NULL; | 415 | ri->format = 2; |
| 416 | if (seq->op == &format3_seq_ops) | ||
| 417 | ri->format = 3; | ||
| 418 | |||
| 419 | spin_lock(&ls->ls_rsbtbl[bucket].lock); | ||
| 420 | if (!list_empty(&ls->ls_rsbtbl[bucket].list)) { | ||
| 421 | list_for_each_entry(r, &ls->ls_rsbtbl[bucket].list, | ||
| 422 | res_hashchain) { | ||
| 423 | if (!entry--) { | ||
| 424 | dlm_hold_rsb(r); | ||
| 425 | ri->rsb = r; | ||
| 426 | ri->bucket = bucket; | ||
| 427 | spin_unlock(&ls->ls_rsbtbl[bucket].lock); | ||
| 428 | return ri; | ||
| 429 | } | ||
| 430 | } | ||
| 496 | } | 431 | } |
| 432 | spin_unlock(&ls->ls_rsbtbl[bucket].lock); | ||
| 497 | 433 | ||
| 498 | return ri; | 434 | /* |
| 499 | } | 435 | * move to the first rsb in the next non-empty bucket |
| 436 | */ | ||
| 500 | 437 | ||
| 501 | static void *locks_seq_start(struct seq_file *file, loff_t *pos) | 438 | /* zero the entry */ |
| 502 | { | 439 | n &= ~((1LL << 32) - 1); |
| 503 | struct rsb_iter *ri; | ||
| 504 | loff_t n = *pos; | ||
| 505 | 440 | ||
| 506 | ri = locks_iter_init(file->private, pos); | 441 | while (1) { |
| 507 | if (!ri) | 442 | bucket++; |
| 508 | return NULL; | 443 | n += 1LL << 32; |
| 509 | 444 | ||
| 510 | while (n--) { | 445 | if (bucket >= ls->ls_rsbtbl_size) { |
| 511 | if (rsb_iter_next(ri)) { | 446 | kfree(ri); |
| 512 | rsb_iter_free(ri); | ||
| 513 | return NULL; | 447 | return NULL; |
| 514 | } | 448 | } |
| 515 | } | ||
| 516 | 449 | ||
| 517 | return ri; | 450 | spin_lock(&ls->ls_rsbtbl[bucket].lock); |
| 451 | if (!list_empty(&ls->ls_rsbtbl[bucket].list)) { | ||
| 452 | r = list_first_entry(&ls->ls_rsbtbl[bucket].list, | ||
| 453 | struct dlm_rsb, res_hashchain); | ||
| 454 | dlm_hold_rsb(r); | ||
| 455 | ri->rsb = r; | ||
| 456 | ri->bucket = bucket; | ||
| 457 | spin_unlock(&ls->ls_rsbtbl[bucket].lock); | ||
| 458 | *pos = n; | ||
| 459 | return ri; | ||
| 460 | } | ||
| 461 | spin_unlock(&ls->ls_rsbtbl[bucket].lock); | ||
| 462 | } | ||
| 518 | } | 463 | } |
| 519 | 464 | ||
| 520 | static struct seq_operations locks_seq_ops = { | 465 | static void *table_seq_next(struct seq_file *seq, void *iter_ptr, loff_t *pos) |
| 521 | .start = locks_seq_start, | ||
| 522 | .next = rsb_seq_next, | ||
| 523 | .stop = rsb_seq_stop, | ||
| 524 | .show = rsb_seq_show, | ||
| 525 | }; | ||
| 526 | |||
| 527 | static int locks_open(struct inode *inode, struct file *file) | ||
| 528 | { | 466 | { |
| 529 | struct seq_file *seq; | 467 | struct dlm_ls *ls = seq->private; |
| 530 | int ret; | 468 | struct rsbtbl_iter *ri = iter_ptr; |
| 531 | 469 | struct list_head *next; | |
| 532 | ret = seq_open(file, &locks_seq_ops); | 470 | struct dlm_rsb *r, *rp; |
| 533 | if (ret) | 471 | loff_t n = *pos; |
| 534 | return ret; | 472 | unsigned bucket; |
| 535 | 473 | ||
| 536 | seq = file->private_data; | 474 | bucket = n >> 32; |
| 537 | seq->private = inode->i_private; | 475 | |
| 538 | 476 | /* | |
| 539 | return 0; | 477 | * move to the next rsb in the same bucket |
| 540 | } | 478 | */ |
| 541 | 479 | ||
| 542 | static const struct file_operations locks_fops = { | 480 | spin_lock(&ls->ls_rsbtbl[bucket].lock); |
| 543 | .owner = THIS_MODULE, | 481 | rp = ri->rsb; |
| 544 | .open = locks_open, | 482 | next = rp->res_hashchain.next; |
| 545 | .read = seq_read, | 483 | |
| 546 | .llseek = seq_lseek, | 484 | if (next != &ls->ls_rsbtbl[bucket].list) { |
| 547 | .release = seq_release | 485 | r = list_entry(next, struct dlm_rsb, res_hashchain); |
| 548 | }; | 486 | dlm_hold_rsb(r); |
| 549 | 487 | ri->rsb = r; | |
| 550 | /* | 488 | spin_unlock(&ls->ls_rsbtbl[bucket].lock); |
| 551 | * Dump all rsb/lvb/lkb state in compact listing, more complete than _locks | 489 | dlm_put_rsb(rp); |
| 552 | * This can replace both formats 1 and 2 eventually. | 490 | ++*pos; |
| 553 | */ | 491 | return ri; |
| 492 | } | ||
| 493 | spin_unlock(&ls->ls_rsbtbl[bucket].lock); | ||
| 494 | dlm_put_rsb(rp); | ||
| 554 | 495 | ||
| 555 | static struct rsb_iter *all_iter_init(struct dlm_ls *ls, loff_t *pos) | 496 | /* |
| 556 | { | 497 | * move to the first rsb in the next non-empty bucket |
| 557 | struct rsb_iter *ri; | 498 | */ |
| 558 | 499 | ||
| 559 | ri = kzalloc(sizeof *ri, GFP_KERNEL); | 500 | /* zero the entry */ |
| 560 | if (!ri) | 501 | n &= ~((1LL << 32) - 1); |
| 561 | return NULL; | ||
| 562 | 502 | ||
| 563 | ri->ls = ls; | 503 | while (1) { |
| 564 | ri->entry = 0; | 504 | bucket++; |
| 565 | ri->next = NULL; | 505 | n += 1LL << 32; |
| 566 | ri->format = 3; | ||
| 567 | 506 | ||
| 568 | if (*pos == 0) | 507 | if (bucket >= ls->ls_rsbtbl_size) { |
| 569 | ri->header = 1; | 508 | kfree(ri); |
| 509 | return NULL; | ||
| 510 | } | ||
| 570 | 511 | ||
| 571 | if (rsb_iter_next(ri)) { | 512 | spin_lock(&ls->ls_rsbtbl[bucket].lock); |
| 572 | rsb_iter_free(ri); | 513 | if (!list_empty(&ls->ls_rsbtbl[bucket].list)) { |
| 573 | return NULL; | 514 | r = list_first_entry(&ls->ls_rsbtbl[bucket].list, |
| 515 | struct dlm_rsb, res_hashchain); | ||
| 516 | dlm_hold_rsb(r); | ||
| 517 | ri->rsb = r; | ||
| 518 | ri->bucket = bucket; | ||
| 519 | spin_unlock(&ls->ls_rsbtbl[bucket].lock); | ||
| 520 | *pos = n; | ||
| 521 | return ri; | ||
| 522 | } | ||
| 523 | spin_unlock(&ls->ls_rsbtbl[bucket].lock); | ||
| 574 | } | 524 | } |
| 575 | |||
| 576 | return ri; | ||
| 577 | } | 525 | } |
| 578 | 526 | ||
| 579 | static void *all_seq_start(struct seq_file *file, loff_t *pos) | 527 | static void table_seq_stop(struct seq_file *seq, void *iter_ptr) |
| 580 | { | 528 | { |
| 581 | struct rsb_iter *ri; | 529 | struct rsbtbl_iter *ri = iter_ptr; |
| 582 | loff_t n = *pos; | ||
| 583 | |||
| 584 | ri = all_iter_init(file->private, pos); | ||
| 585 | if (!ri) | ||
| 586 | return NULL; | ||
| 587 | 530 | ||
| 588 | while (n--) { | 531 | if (ri) { |
| 589 | if (rsb_iter_next(ri)) { | 532 | dlm_put_rsb(ri->rsb); |
| 590 | rsb_iter_free(ri); | 533 | kfree(ri); |
| 591 | return NULL; | ||
| 592 | } | ||
| 593 | } | 534 | } |
| 594 | |||
| 595 | return ri; | ||
| 596 | } | 535 | } |
| 597 | 536 | ||
| 598 | static struct seq_operations all_seq_ops = { | 537 | static struct seq_operations format1_seq_ops = { |
| 599 | .start = all_seq_start, | 538 | .start = table_seq_start, |
| 600 | .next = rsb_seq_next, | 539 | .next = table_seq_next, |
| 601 | .stop = rsb_seq_stop, | 540 | .stop = table_seq_stop, |
| 602 | .show = rsb_seq_show, | 541 | .show = table_seq_show, |
| 603 | }; | 542 | }; |
| 604 | 543 | ||
| 605 | static int all_open(struct inode *inode, struct file *file) | 544 | static struct seq_operations format2_seq_ops = { |
| 545 | .start = table_seq_start, | ||
| 546 | .next = table_seq_next, | ||
| 547 | .stop = table_seq_stop, | ||
| 548 | .show = table_seq_show, | ||
| 549 | }; | ||
| 550 | |||
| 551 | static struct seq_operations format3_seq_ops = { | ||
| 552 | .start = table_seq_start, | ||
| 553 | .next = table_seq_next, | ||
| 554 | .stop = table_seq_stop, | ||
| 555 | .show = table_seq_show, | ||
| 556 | }; | ||
| 557 | |||
| 558 | static const struct file_operations format1_fops; | ||
| 559 | static const struct file_operations format2_fops; | ||
| 560 | static const struct file_operations format3_fops; | ||
| 561 | |||
| 562 | static int table_open(struct inode *inode, struct file *file) | ||
| 606 | { | 563 | { |
| 607 | struct seq_file *seq; | 564 | struct seq_file *seq; |
| 608 | int ret; | 565 | int ret = -1; |
| 566 | |||
| 567 | if (file->f_op == &format1_fops) | ||
| 568 | ret = seq_open(file, &format1_seq_ops); | ||
| 569 | else if (file->f_op == &format2_fops) | ||
| 570 | ret = seq_open(file, &format2_seq_ops); | ||
| 571 | else if (file->f_op == &format3_fops) | ||
| 572 | ret = seq_open(file, &format3_seq_ops); | ||
| 609 | 573 | ||
| 610 | ret = seq_open(file, &all_seq_ops); | ||
| 611 | if (ret) | 574 | if (ret) |
| 612 | return ret; | 575 | return ret; |
| 613 | 576 | ||
| 614 | seq = file->private_data; | 577 | seq = file->private_data; |
| 615 | seq->private = inode->i_private; | 578 | seq->private = inode->i_private; /* the dlm_ls */ |
| 616 | |||
| 617 | return 0; | 579 | return 0; |
| 618 | } | 580 | } |
| 619 | 581 | ||
| 620 | static const struct file_operations all_fops = { | 582 | static const struct file_operations format1_fops = { |
| 583 | .owner = THIS_MODULE, | ||
| 584 | .open = table_open, | ||
| 585 | .read = seq_read, | ||
| 586 | .llseek = seq_lseek, | ||
| 587 | .release = seq_release | ||
| 588 | }; | ||
| 589 | |||
| 590 | static const struct file_operations format2_fops = { | ||
| 591 | .owner = THIS_MODULE, | ||
| 592 | .open = table_open, | ||
| 593 | .read = seq_read, | ||
| 594 | .llseek = seq_lseek, | ||
| 595 | .release = seq_release | ||
| 596 | }; | ||
| 597 | |||
| 598 | static const struct file_operations format3_fops = { | ||
| 621 | .owner = THIS_MODULE, | 599 | .owner = THIS_MODULE, |
| 622 | .open = all_open, | 600 | .open = table_open, |
| 623 | .read = seq_read, | 601 | .read = seq_read, |
| 624 | .llseek = seq_lseek, | 602 | .llseek = seq_lseek, |
| 625 | .release = seq_release | 603 | .release = seq_release |
| @@ -689,7 +667,7 @@ int dlm_create_debug_file(struct dlm_ls *ls) | |||
| 689 | S_IFREG | S_IRUGO, | 667 | S_IFREG | S_IRUGO, |
| 690 | dlm_root, | 668 | dlm_root, |
| 691 | ls, | 669 | ls, |
| 692 | &rsb_fops); | 670 | &format1_fops); |
| 693 | if (!ls->ls_debug_rsb_dentry) | 671 | if (!ls->ls_debug_rsb_dentry) |
| 694 | goto fail; | 672 | goto fail; |
| 695 | 673 | ||
| @@ -702,7 +680,7 @@ int dlm_create_debug_file(struct dlm_ls *ls) | |||
| 702 | S_IFREG | S_IRUGO, | 680 | S_IFREG | S_IRUGO, |
| 703 | dlm_root, | 681 | dlm_root, |
| 704 | ls, | 682 | ls, |
| 705 | &locks_fops); | 683 | &format2_fops); |
| 706 | if (!ls->ls_debug_locks_dentry) | 684 | if (!ls->ls_debug_locks_dentry) |
| 707 | goto fail; | 685 | goto fail; |
| 708 | 686 | ||
| @@ -715,7 +693,7 @@ int dlm_create_debug_file(struct dlm_ls *ls) | |||
| 715 | S_IFREG | S_IRUGO, | 693 | S_IFREG | S_IRUGO, |
| 716 | dlm_root, | 694 | dlm_root, |
| 717 | ls, | 695 | ls, |
| 718 | &all_fops); | 696 | &format3_fops); |
| 719 | if (!ls->ls_debug_all_dentry) | 697 | if (!ls->ls_debug_all_dentry) |
| 720 | goto fail; | 698 | goto fail; |
| 721 | 699 | ||
diff --git a/fs/dlm/dlm_internal.h b/fs/dlm/dlm_internal.h index ef2f1e353966..076e86f38bc8 100644 --- a/fs/dlm/dlm_internal.h +++ b/fs/dlm/dlm_internal.h | |||
| @@ -105,7 +105,7 @@ struct dlm_dirtable { | |||
| 105 | struct dlm_rsbtable { | 105 | struct dlm_rsbtable { |
| 106 | struct list_head list; | 106 | struct list_head list; |
| 107 | struct list_head toss; | 107 | struct list_head toss; |
| 108 | rwlock_t lock; | 108 | spinlock_t lock; |
| 109 | }; | 109 | }; |
| 110 | 110 | ||
| 111 | struct dlm_lkbtable { | 111 | struct dlm_lkbtable { |
diff --git a/fs/dlm/lock.c b/fs/dlm/lock.c index 6cfe65bbf4a2..01e7d39c5fba 100644 --- a/fs/dlm/lock.c +++ b/fs/dlm/lock.c | |||
| @@ -412,9 +412,9 @@ static int search_rsb(struct dlm_ls *ls, char *name, int len, int b, | |||
| 412 | unsigned int flags, struct dlm_rsb **r_ret) | 412 | unsigned int flags, struct dlm_rsb **r_ret) |
| 413 | { | 413 | { |
| 414 | int error; | 414 | int error; |
| 415 | write_lock(&ls->ls_rsbtbl[b].lock); | 415 | spin_lock(&ls->ls_rsbtbl[b].lock); |
| 416 | error = _search_rsb(ls, name, len, b, flags, r_ret); | 416 | error = _search_rsb(ls, name, len, b, flags, r_ret); |
| 417 | write_unlock(&ls->ls_rsbtbl[b].lock); | 417 | spin_unlock(&ls->ls_rsbtbl[b].lock); |
| 418 | return error; | 418 | return error; |
| 419 | } | 419 | } |
| 420 | 420 | ||
| @@ -478,16 +478,16 @@ static int find_rsb(struct dlm_ls *ls, char *name, int namelen, | |||
| 478 | r->res_nodeid = nodeid; | 478 | r->res_nodeid = nodeid; |
| 479 | } | 479 | } |
| 480 | 480 | ||
| 481 | write_lock(&ls->ls_rsbtbl[bucket].lock); | 481 | spin_lock(&ls->ls_rsbtbl[bucket].lock); |
| 482 | error = _search_rsb(ls, name, namelen, bucket, 0, &tmp); | 482 | error = _search_rsb(ls, name, namelen, bucket, 0, &tmp); |
| 483 | if (!error) { | 483 | if (!error) { |
| 484 | write_unlock(&ls->ls_rsbtbl[bucket].lock); | 484 | spin_unlock(&ls->ls_rsbtbl[bucket].lock); |
| 485 | dlm_free_rsb(r); | 485 | dlm_free_rsb(r); |
| 486 | r = tmp; | 486 | r = tmp; |
| 487 | goto out; | 487 | goto out; |
| 488 | } | 488 | } |
| 489 | list_add(&r->res_hashchain, &ls->ls_rsbtbl[bucket].list); | 489 | list_add(&r->res_hashchain, &ls->ls_rsbtbl[bucket].list); |
| 490 | write_unlock(&ls->ls_rsbtbl[bucket].lock); | 490 | spin_unlock(&ls->ls_rsbtbl[bucket].lock); |
| 491 | error = 0; | 491 | error = 0; |
| 492 | out: | 492 | out: |
| 493 | *r_ret = r; | 493 | *r_ret = r; |
| @@ -530,9 +530,9 @@ static void put_rsb(struct dlm_rsb *r) | |||
| 530 | struct dlm_ls *ls = r->res_ls; | 530 | struct dlm_ls *ls = r->res_ls; |
| 531 | uint32_t bucket = r->res_bucket; | 531 | uint32_t bucket = r->res_bucket; |
| 532 | 532 | ||
| 533 | write_lock(&ls->ls_rsbtbl[bucket].lock); | 533 | spin_lock(&ls->ls_rsbtbl[bucket].lock); |
| 534 | kref_put(&r->res_ref, toss_rsb); | 534 | kref_put(&r->res_ref, toss_rsb); |
| 535 | write_unlock(&ls->ls_rsbtbl[bucket].lock); | 535 | spin_unlock(&ls->ls_rsbtbl[bucket].lock); |
| 536 | } | 536 | } |
| 537 | 537 | ||
| 538 | void dlm_put_rsb(struct dlm_rsb *r) | 538 | void dlm_put_rsb(struct dlm_rsb *r) |
| @@ -967,7 +967,7 @@ static int shrink_bucket(struct dlm_ls *ls, int b) | |||
| 967 | 967 | ||
| 968 | for (;;) { | 968 | for (;;) { |
| 969 | found = 0; | 969 | found = 0; |
| 970 | write_lock(&ls->ls_rsbtbl[b].lock); | 970 | spin_lock(&ls->ls_rsbtbl[b].lock); |
| 971 | list_for_each_entry_reverse(r, &ls->ls_rsbtbl[b].toss, | 971 | list_for_each_entry_reverse(r, &ls->ls_rsbtbl[b].toss, |
| 972 | res_hashchain) { | 972 | res_hashchain) { |
| 973 | if (!time_after_eq(jiffies, r->res_toss_time + | 973 | if (!time_after_eq(jiffies, r->res_toss_time + |
| @@ -978,20 +978,20 @@ static int shrink_bucket(struct dlm_ls *ls, int b) | |||
| 978 | } | 978 | } |
| 979 | 979 | ||
| 980 | if (!found) { | 980 | if (!found) { |
| 981 | write_unlock(&ls->ls_rsbtbl[b].lock); | 981 | spin_unlock(&ls->ls_rsbtbl[b].lock); |
| 982 | break; | 982 | break; |
| 983 | } | 983 | } |
| 984 | 984 | ||
| 985 | if (kref_put(&r->res_ref, kill_rsb)) { | 985 | if (kref_put(&r->res_ref, kill_rsb)) { |
| 986 | list_del(&r->res_hashchain); | 986 | list_del(&r->res_hashchain); |
| 987 | write_unlock(&ls->ls_rsbtbl[b].lock); | 987 | spin_unlock(&ls->ls_rsbtbl[b].lock); |
| 988 | 988 | ||
| 989 | if (is_master(r)) | 989 | if (is_master(r)) |
| 990 | dir_remove(r); | 990 | dir_remove(r); |
| 991 | dlm_free_rsb(r); | 991 | dlm_free_rsb(r); |
| 992 | count++; | 992 | count++; |
| 993 | } else { | 993 | } else { |
| 994 | write_unlock(&ls->ls_rsbtbl[b].lock); | 994 | spin_unlock(&ls->ls_rsbtbl[b].lock); |
| 995 | log_error(ls, "tossed rsb in use %s", r->res_name); | 995 | log_error(ls, "tossed rsb in use %s", r->res_name); |
| 996 | } | 996 | } |
| 997 | } | 997 | } |
| @@ -4224,7 +4224,7 @@ static struct dlm_rsb *find_purged_rsb(struct dlm_ls *ls, int bucket) | |||
| 4224 | { | 4224 | { |
| 4225 | struct dlm_rsb *r, *r_ret = NULL; | 4225 | struct dlm_rsb *r, *r_ret = NULL; |
| 4226 | 4226 | ||
| 4227 | read_lock(&ls->ls_rsbtbl[bucket].lock); | 4227 | spin_lock(&ls->ls_rsbtbl[bucket].lock); |
| 4228 | list_for_each_entry(r, &ls->ls_rsbtbl[bucket].list, res_hashchain) { | 4228 | list_for_each_entry(r, &ls->ls_rsbtbl[bucket].list, res_hashchain) { |
| 4229 | if (!rsb_flag(r, RSB_LOCKS_PURGED)) | 4229 | if (!rsb_flag(r, RSB_LOCKS_PURGED)) |
| 4230 | continue; | 4230 | continue; |
| @@ -4233,7 +4233,7 @@ static struct dlm_rsb *find_purged_rsb(struct dlm_ls *ls, int bucket) | |||
| 4233 | r_ret = r; | 4233 | r_ret = r; |
| 4234 | break; | 4234 | break; |
| 4235 | } | 4235 | } |
| 4236 | read_unlock(&ls->ls_rsbtbl[bucket].lock); | 4236 | spin_unlock(&ls->ls_rsbtbl[bucket].lock); |
| 4237 | return r_ret; | 4237 | return r_ret; |
| 4238 | } | 4238 | } |
| 4239 | 4239 | ||
diff --git a/fs/dlm/lockspace.c b/fs/dlm/lockspace.c index 8d86b7960f0d..aa32e5f02493 100644 --- a/fs/dlm/lockspace.c +++ b/fs/dlm/lockspace.c | |||
| @@ -464,7 +464,7 @@ static int new_lockspace(char *name, int namelen, void **lockspace, | |||
| 464 | for (i = 0; i < size; i++) { | 464 | for (i = 0; i < size; i++) { |
| 465 | INIT_LIST_HEAD(&ls->ls_rsbtbl[i].list); | 465 | INIT_LIST_HEAD(&ls->ls_rsbtbl[i].list); |
| 466 | INIT_LIST_HEAD(&ls->ls_rsbtbl[i].toss); | 466 | INIT_LIST_HEAD(&ls->ls_rsbtbl[i].toss); |
| 467 | rwlock_init(&ls->ls_rsbtbl[i].lock); | 467 | spin_lock_init(&ls->ls_rsbtbl[i].lock); |
| 468 | } | 468 | } |
| 469 | 469 | ||
| 470 | size = dlm_config.ci_lkbtbl_size; | 470 | size = dlm_config.ci_lkbtbl_size; |
diff --git a/fs/dlm/recover.c b/fs/dlm/recover.c index 80aba5bdd4a4..eda43f362616 100644 --- a/fs/dlm/recover.c +++ b/fs/dlm/recover.c | |||
| @@ -726,7 +726,7 @@ int dlm_create_root_list(struct dlm_ls *ls) | |||
| 726 | } | 726 | } |
| 727 | 727 | ||
| 728 | for (i = 0; i < ls->ls_rsbtbl_size; i++) { | 728 | for (i = 0; i < ls->ls_rsbtbl_size; i++) { |
| 729 | read_lock(&ls->ls_rsbtbl[i].lock); | 729 | spin_lock(&ls->ls_rsbtbl[i].lock); |
| 730 | list_for_each_entry(r, &ls->ls_rsbtbl[i].list, res_hashchain) { | 730 | list_for_each_entry(r, &ls->ls_rsbtbl[i].list, res_hashchain) { |
| 731 | list_add(&r->res_root_list, &ls->ls_root_list); | 731 | list_add(&r->res_root_list, &ls->ls_root_list); |
| 732 | dlm_hold_rsb(r); | 732 | dlm_hold_rsb(r); |
| @@ -737,7 +737,7 @@ int dlm_create_root_list(struct dlm_ls *ls) | |||
| 737 | but no other recovery steps should do anything with them. */ | 737 | but no other recovery steps should do anything with them. */ |
| 738 | 738 | ||
| 739 | if (dlm_no_directory(ls)) { | 739 | if (dlm_no_directory(ls)) { |
| 740 | read_unlock(&ls->ls_rsbtbl[i].lock); | 740 | spin_unlock(&ls->ls_rsbtbl[i].lock); |
| 741 | continue; | 741 | continue; |
| 742 | } | 742 | } |
| 743 | 743 | ||
| @@ -745,7 +745,7 @@ int dlm_create_root_list(struct dlm_ls *ls) | |||
| 745 | list_add(&r->res_root_list, &ls->ls_root_list); | 745 | list_add(&r->res_root_list, &ls->ls_root_list); |
| 746 | dlm_hold_rsb(r); | 746 | dlm_hold_rsb(r); |
| 747 | } | 747 | } |
| 748 | read_unlock(&ls->ls_rsbtbl[i].lock); | 748 | spin_unlock(&ls->ls_rsbtbl[i].lock); |
| 749 | } | 749 | } |
| 750 | out: | 750 | out: |
| 751 | up_write(&ls->ls_root_sem); | 751 | up_write(&ls->ls_root_sem); |
| @@ -775,7 +775,7 @@ void dlm_clear_toss_list(struct dlm_ls *ls) | |||
| 775 | int i; | 775 | int i; |
| 776 | 776 | ||
| 777 | for (i = 0; i < ls->ls_rsbtbl_size; i++) { | 777 | for (i = 0; i < ls->ls_rsbtbl_size; i++) { |
| 778 | write_lock(&ls->ls_rsbtbl[i].lock); | 778 | spin_lock(&ls->ls_rsbtbl[i].lock); |
| 779 | list_for_each_entry_safe(r, safe, &ls->ls_rsbtbl[i].toss, | 779 | list_for_each_entry_safe(r, safe, &ls->ls_rsbtbl[i].toss, |
| 780 | res_hashchain) { | 780 | res_hashchain) { |
| 781 | if (dlm_no_directory(ls) || !is_master(r)) { | 781 | if (dlm_no_directory(ls) || !is_master(r)) { |
| @@ -783,7 +783,7 @@ void dlm_clear_toss_list(struct dlm_ls *ls) | |||
| 783 | dlm_free_rsb(r); | 783 | dlm_free_rsb(r); |
| 784 | } | 784 | } |
| 785 | } | 785 | } |
| 786 | write_unlock(&ls->ls_rsbtbl[i].lock); | 786 | spin_unlock(&ls->ls_rsbtbl[i].lock); |
| 787 | } | 787 | } |
| 788 | } | 788 | } |
| 789 | 789 | ||
diff --git a/include/asm-m68k/unistd.h b/include/asm-m68k/unistd.h index 965abb8bc7ff..3c19027331fa 100644 --- a/include/asm-m68k/unistd.h +++ b/include/asm-m68k/unistd.h | |||
| @@ -5,6 +5,7 @@ | |||
| 5 | * This file contains the system call numbers. | 5 | * This file contains the system call numbers. |
| 6 | */ | 6 | */ |
| 7 | 7 | ||
| 8 | #define __NR_restart_syscall 0 | ||
| 8 | #define __NR_exit 1 | 9 | #define __NR_exit 1 |
| 9 | #define __NR_fork 2 | 10 | #define __NR_fork 2 |
| 10 | #define __NR_read 3 | 11 | #define __NR_read 3 |
| @@ -359,9 +360,6 @@ | |||
| 359 | #define __ARCH_WANT_SYS_SIGPROCMASK | 360 | #define __ARCH_WANT_SYS_SIGPROCMASK |
| 360 | #define __ARCH_WANT_SYS_RT_SIGACTION | 361 | #define __ARCH_WANT_SYS_RT_SIGACTION |
| 361 | 362 | ||
| 362 | /* whitelist for checksyscalls */ | ||
| 363 | #define __IGNORE_restart_syscall | ||
| 364 | |||
| 365 | /* | 363 | /* |
| 366 | * "Conditional" syscalls | 364 | * "Conditional" syscalls |
| 367 | * | 365 | * |
diff --git a/include/linux/dio.h b/include/linux/dio.h index 1e65ebc2a3db..b2dd31ca1710 100644 --- a/include/linux/dio.h +++ b/include/linux/dio.h | |||
| @@ -241,7 +241,7 @@ struct dio_driver { | |||
| 241 | 241 | ||
| 242 | extern int dio_find(int deviceid); | 242 | extern int dio_find(int deviceid); |
| 243 | extern unsigned long dio_scodetophysaddr(int scode); | 243 | extern unsigned long dio_scodetophysaddr(int scode); |
| 244 | extern void dio_create_sysfs_dev_files(struct dio_dev *); | 244 | extern int dio_create_sysfs_dev_files(struct dio_dev *); |
| 245 | 245 | ||
| 246 | /* New-style probing */ | 246 | /* New-style probing */ |
| 247 | extern int dio_register_driver(struct dio_driver *); | 247 | extern int dio_register_driver(struct dio_driver *); |
diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index 64dea2ab326c..c73f1e2b59b7 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h | |||
| @@ -270,8 +270,18 @@ struct dma_device { | |||
| 270 | 270 | ||
| 271 | /* --- public DMA engine API --- */ | 271 | /* --- public DMA engine API --- */ |
| 272 | 272 | ||
| 273 | #ifdef CONFIG_DMA_ENGINE | ||
| 273 | void dmaengine_get(void); | 274 | void dmaengine_get(void); |
| 274 | void dmaengine_put(void); | 275 | void dmaengine_put(void); |
| 276 | #else | ||
| 277 | static inline void dmaengine_get(void) | ||
| 278 | { | ||
| 279 | } | ||
| 280 | static inline void dmaengine_put(void) | ||
| 281 | { | ||
| 282 | } | ||
| 283 | #endif | ||
| 284 | |||
| 275 | dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan, | 285 | dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan, |
| 276 | void *dest, void *src, size_t len); | 286 | void *dest, void *src, size_t len); |
| 277 | dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan, | 287 | dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan, |
diff --git a/include/linux/mISDNif.h b/include/linux/mISDNif.h index 557477ac3d5b..5da3d95b27f1 100644 --- a/include/linux/mISDNif.h +++ b/include/linux/mISDNif.h | |||
| @@ -559,7 +559,10 @@ extern void mISDN_unregister_clock(struct mISDNclock *); | |||
| 559 | 559 | ||
| 560 | static inline struct mISDNdevice *dev_to_mISDN(struct device *dev) | 560 | static inline struct mISDNdevice *dev_to_mISDN(struct device *dev) |
| 561 | { | 561 | { |
| 562 | return dev_get_drvdata(dev); | 562 | if (dev) |
| 563 | return dev_get_drvdata(dev); | ||
| 564 | else | ||
| 565 | return NULL; | ||
| 563 | } | 566 | } |
| 564 | 567 | ||
| 565 | extern void set_channel_address(struct mISDNchannel *, u_int, u_int); | 568 | extern void set_channel_address(struct mISDNchannel *, u_int, u_int); |
diff --git a/include/linux/mfd/pcf50633/adc.h b/include/linux/mfd/pcf50633/adc.h new file mode 100644 index 000000000000..56669b4183ad --- /dev/null +++ b/include/linux/mfd/pcf50633/adc.h | |||
| @@ -0,0 +1,72 @@ | |||
| 1 | /* | ||
| 2 | * adc.h -- Driver for NXP PCF50633 ADC | ||
| 3 | * | ||
| 4 | * (C) 2006-2008 by Openmoko, Inc. | ||
| 5 | * All rights reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License as published by the | ||
| 9 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 10 | * option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __LINUX_MFD_PCF50633_ADC_H | ||
| 14 | #define __LINUX_MFD_PCF50633_ADC_H | ||
| 15 | |||
| 16 | #include <linux/mfd/pcf50633/core.h> | ||
| 17 | #include <linux/platform_device.h> | ||
| 18 | |||
| 19 | /* ADC Registers */ | ||
| 20 | #define PCF50633_REG_ADCC3 0x52 | ||
| 21 | #define PCF50633_REG_ADCC2 0x53 | ||
| 22 | #define PCF50633_REG_ADCC1 0x54 | ||
| 23 | #define PCF50633_REG_ADCS1 0x55 | ||
| 24 | #define PCF50633_REG_ADCS2 0x56 | ||
| 25 | #define PCF50633_REG_ADCS3 0x57 | ||
| 26 | |||
| 27 | #define PCF50633_ADCC1_ADCSTART 0x01 | ||
| 28 | #define PCF50633_ADCC1_RES_10BIT 0x02 | ||
| 29 | #define PCF50633_ADCC1_AVERAGE_NO 0x00 | ||
| 30 | #define PCF50633_ADCC1_AVERAGE_4 0x04 | ||
| 31 | #define PCF50633_ADCC1_AVERAGE_8 0x08 | ||
| 32 | #define PCF50633_ADCC1_AVERAGE_16 0x0c | ||
| 33 | #define PCF50633_ADCC1_MUX_BATSNS_RES 0x00 | ||
| 34 | #define PCF50633_ADCC1_MUX_BATSNS_SUBTR 0x10 | ||
| 35 | #define PCF50633_ADCC1_MUX_ADCIN2_RES 0x20 | ||
| 36 | #define PCF50633_ADCC1_MUX_ADCIN2_SUBTR 0x30 | ||
| 37 | #define PCF50633_ADCC1_MUX_BATTEMP 0x60 | ||
| 38 | #define PCF50633_ADCC1_MUX_ADCIN1 0x70 | ||
| 39 | #define PCF50633_ADCC1_AVERAGE_MASK 0x0c | ||
| 40 | #define PCF50633_ADCC1_ADCMUX_MASK 0xf0 | ||
| 41 | |||
| 42 | #define PCF50633_ADCC2_RATIO_NONE 0x00 | ||
| 43 | #define PCF50633_ADCC2_RATIO_BATTEMP 0x01 | ||
| 44 | #define PCF50633_ADCC2_RATIO_ADCIN1 0x02 | ||
| 45 | #define PCF50633_ADCC2_RATIO_BOTH 0x03 | ||
| 46 | #define PCF50633_ADCC2_RATIOSETTL_100US 0x04 | ||
| 47 | |||
| 48 | #define PCF50633_ADCC3_ACCSW_EN 0x01 | ||
| 49 | #define PCF50633_ADCC3_NTCSW_EN 0x04 | ||
| 50 | #define PCF50633_ADCC3_RES_DIV_TWO 0x10 | ||
| 51 | #define PCF50633_ADCC3_RES_DIV_THREE 0x00 | ||
| 52 | |||
| 53 | #define PCF50633_ADCS3_REF_NTCSW 0x00 | ||
| 54 | #define PCF50633_ADCS3_REF_ACCSW 0x10 | ||
| 55 | #define PCF50633_ADCS3_REF_2V0 0x20 | ||
| 56 | #define PCF50633_ADCS3_REF_VISA 0x30 | ||
| 57 | #define PCF50633_ADCS3_REF_2V0_2 0x70 | ||
| 58 | #define PCF50633_ADCS3_ADCRDY 0x80 | ||
| 59 | |||
| 60 | #define PCF50633_ADCS3_ADCDAT1L_MASK 0x03 | ||
| 61 | #define PCF50633_ADCS3_ADCDAT2L_MASK 0x0c | ||
| 62 | #define PCF50633_ADCS3_ADCDAT2L_SHIFT 2 | ||
| 63 | #define PCF50633_ASCS3_REF_MASK 0x70 | ||
| 64 | |||
| 65 | extern int | ||
| 66 | pcf50633_adc_async_read(struct pcf50633 *pcf, int mux, int avg, | ||
| 67 | void (*callback)(struct pcf50633 *, void *, int), | ||
| 68 | void *callback_param); | ||
| 69 | extern int | ||
| 70 | pcf50633_adc_sync_read(struct pcf50633 *pcf, int mux, int avg); | ||
| 71 | |||
| 72 | #endif /* __LINUX_PCF50633_ADC_H */ | ||
diff --git a/include/linux/mfd/pcf50633/core.h b/include/linux/mfd/pcf50633/core.h new file mode 100644 index 000000000000..4455b212d75a --- /dev/null +++ b/include/linux/mfd/pcf50633/core.h | |||
| @@ -0,0 +1,218 @@ | |||
| 1 | /* | ||
| 2 | * core.h -- Core driver for NXP PCF50633 | ||
| 3 | * | ||
| 4 | * (C) 2006-2008 by Openmoko, Inc. | ||
| 5 | * All rights reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License as published by the | ||
| 9 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 10 | * option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __LINUX_MFD_PCF50633_CORE_H | ||
| 14 | #define __LINUX_MFD_PCF50633_CORE_H | ||
| 15 | |||
| 16 | #include <linux/i2c.h> | ||
| 17 | #include <linux/workqueue.h> | ||
| 18 | #include <linux/regulator/driver.h> | ||
| 19 | #include <linux/regulator/machine.h> | ||
| 20 | #include <linux/power_supply.h> | ||
| 21 | |||
| 22 | struct pcf50633; | ||
| 23 | |||
| 24 | #define PCF50633_NUM_REGULATORS 11 | ||
| 25 | |||
| 26 | struct pcf50633_platform_data { | ||
| 27 | struct regulator_init_data reg_init_data[PCF50633_NUM_REGULATORS]; | ||
| 28 | |||
| 29 | char **batteries; | ||
| 30 | int num_batteries; | ||
| 31 | |||
| 32 | /* Callbacks */ | ||
| 33 | void (*probe_done)(struct pcf50633 *); | ||
| 34 | void (*mbc_event_callback)(struct pcf50633 *, int); | ||
| 35 | void (*regulator_registered)(struct pcf50633 *, int); | ||
| 36 | void (*force_shutdown)(struct pcf50633 *); | ||
| 37 | |||
| 38 | u8 resumers[5]; | ||
| 39 | }; | ||
| 40 | |||
| 41 | struct pcf50633_subdev_pdata { | ||
| 42 | struct pcf50633 *pcf; | ||
| 43 | }; | ||
| 44 | |||
| 45 | struct pcf50633_irq { | ||
| 46 | void (*handler) (int, void *); | ||
| 47 | void *data; | ||
| 48 | }; | ||
| 49 | |||
| 50 | int pcf50633_register_irq(struct pcf50633 *pcf, int irq, | ||
| 51 | void (*handler) (int, void *), void *data); | ||
| 52 | int pcf50633_free_irq(struct pcf50633 *pcf, int irq); | ||
| 53 | |||
| 54 | int pcf50633_irq_mask(struct pcf50633 *pcf, int irq); | ||
| 55 | int pcf50633_irq_unmask(struct pcf50633 *pcf, int irq); | ||
| 56 | int pcf50633_irq_mask_get(struct pcf50633 *pcf, int irq); | ||
| 57 | |||
| 58 | int pcf50633_read_block(struct pcf50633 *, u8 reg, | ||
| 59 | int nr_regs, u8 *data); | ||
| 60 | int pcf50633_write_block(struct pcf50633 *pcf, u8 reg, | ||
| 61 | int nr_regs, u8 *data); | ||
| 62 | u8 pcf50633_reg_read(struct pcf50633 *, u8 reg); | ||
| 63 | int pcf50633_reg_write(struct pcf50633 *pcf, u8 reg, u8 val); | ||
| 64 | |||
| 65 | int pcf50633_reg_set_bit_mask(struct pcf50633 *pcf, u8 reg, u8 mask, u8 val); | ||
| 66 | int pcf50633_reg_clear_bits(struct pcf50633 *pcf, u8 reg, u8 bits); | ||
| 67 | |||
| 68 | /* Interrupt registers */ | ||
| 69 | |||
| 70 | #define PCF50633_REG_INT1 0x02 | ||
| 71 | #define PCF50633_REG_INT2 0x03 | ||
| 72 | #define PCF50633_REG_INT3 0x04 | ||
| 73 | #define PCF50633_REG_INT4 0x05 | ||
| 74 | #define PCF50633_REG_INT5 0x06 | ||
| 75 | |||
| 76 | #define PCF50633_REG_INT1M 0x07 | ||
| 77 | #define PCF50633_REG_INT2M 0x08 | ||
| 78 | #define PCF50633_REG_INT3M 0x09 | ||
| 79 | #define PCF50633_REG_INT4M 0x0a | ||
| 80 | #define PCF50633_REG_INT5M 0x0b | ||
| 81 | |||
| 82 | enum { | ||
| 83 | /* Chip IRQs */ | ||
| 84 | PCF50633_IRQ_ADPINS, | ||
| 85 | PCF50633_IRQ_ADPREM, | ||
| 86 | PCF50633_IRQ_USBINS, | ||
| 87 | PCF50633_IRQ_USBREM, | ||
| 88 | PCF50633_IRQ_RESERVED1, | ||
| 89 | PCF50633_IRQ_RESERVED2, | ||
| 90 | PCF50633_IRQ_ALARM, | ||
| 91 | PCF50633_IRQ_SECOND, | ||
| 92 | PCF50633_IRQ_ONKEYR, | ||
| 93 | PCF50633_IRQ_ONKEYF, | ||
| 94 | PCF50633_IRQ_EXTON1R, | ||
| 95 | PCF50633_IRQ_EXTON1F, | ||
| 96 | PCF50633_IRQ_EXTON2R, | ||
| 97 | PCF50633_IRQ_EXTON2F, | ||
| 98 | PCF50633_IRQ_EXTON3R, | ||
| 99 | PCF50633_IRQ_EXTON3F, | ||
| 100 | PCF50633_IRQ_BATFULL, | ||
| 101 | PCF50633_IRQ_CHGHALT, | ||
| 102 | PCF50633_IRQ_THLIMON, | ||
| 103 | PCF50633_IRQ_THLIMOFF, | ||
| 104 | PCF50633_IRQ_USBLIMON, | ||
| 105 | PCF50633_IRQ_USBLIMOFF, | ||
| 106 | PCF50633_IRQ_ADCRDY, | ||
| 107 | PCF50633_IRQ_ONKEY1S, | ||
| 108 | PCF50633_IRQ_LOWSYS, | ||
| 109 | PCF50633_IRQ_LOWBAT, | ||
| 110 | PCF50633_IRQ_HIGHTMP, | ||
| 111 | PCF50633_IRQ_AUTOPWRFAIL, | ||
| 112 | PCF50633_IRQ_DWN1PWRFAIL, | ||
| 113 | PCF50633_IRQ_DWN2PWRFAIL, | ||
| 114 | PCF50633_IRQ_LEDPWRFAIL, | ||
| 115 | PCF50633_IRQ_LEDOVP, | ||
| 116 | PCF50633_IRQ_LDO1PWRFAIL, | ||
| 117 | PCF50633_IRQ_LDO2PWRFAIL, | ||
| 118 | PCF50633_IRQ_LDO3PWRFAIL, | ||
| 119 | PCF50633_IRQ_LDO4PWRFAIL, | ||
| 120 | PCF50633_IRQ_LDO5PWRFAIL, | ||
| 121 | PCF50633_IRQ_LDO6PWRFAIL, | ||
| 122 | PCF50633_IRQ_HCLDOPWRFAIL, | ||
| 123 | PCF50633_IRQ_HCLDOOVL, | ||
| 124 | |||
| 125 | /* Always last */ | ||
| 126 | PCF50633_NUM_IRQ, | ||
| 127 | }; | ||
| 128 | |||
| 129 | struct pcf50633 { | ||
| 130 | struct device *dev; | ||
| 131 | struct i2c_client *i2c_client; | ||
| 132 | |||
| 133 | struct pcf50633_platform_data *pdata; | ||
| 134 | int irq; | ||
| 135 | struct pcf50633_irq irq_handler[PCF50633_NUM_IRQ]; | ||
| 136 | struct work_struct irq_work; | ||
| 137 | struct mutex lock; | ||
| 138 | |||
| 139 | u8 mask_regs[5]; | ||
| 140 | |||
| 141 | u8 suspend_irq_masks[5]; | ||
| 142 | u8 resume_reason[5]; | ||
| 143 | int is_suspended; | ||
| 144 | |||
| 145 | int onkey1s_held; | ||
| 146 | |||
| 147 | struct platform_device *rtc_pdev; | ||
| 148 | struct platform_device *mbc_pdev; | ||
| 149 | struct platform_device *adc_pdev; | ||
| 150 | struct platform_device *input_pdev; | ||
| 151 | struct platform_device *regulator_pdev[PCF50633_NUM_REGULATORS]; | ||
| 152 | }; | ||
| 153 | |||
| 154 | enum pcf50633_reg_int1 { | ||
| 155 | PCF50633_INT1_ADPINS = 0x01, /* Adapter inserted */ | ||
| 156 | PCF50633_INT1_ADPREM = 0x02, /* Adapter removed */ | ||
| 157 | PCF50633_INT1_USBINS = 0x04, /* USB inserted */ | ||
| 158 | PCF50633_INT1_USBREM = 0x08, /* USB removed */ | ||
| 159 | /* reserved */ | ||
| 160 | PCF50633_INT1_ALARM = 0x40, /* RTC alarm time is reached */ | ||
| 161 | PCF50633_INT1_SECOND = 0x80, /* RTC periodic second interrupt */ | ||
| 162 | }; | ||
| 163 | |||
| 164 | enum pcf50633_reg_int2 { | ||
| 165 | PCF50633_INT2_ONKEYR = 0x01, /* ONKEY rising edge */ | ||
| 166 | PCF50633_INT2_ONKEYF = 0x02, /* ONKEY falling edge */ | ||
| 167 | PCF50633_INT2_EXTON1R = 0x04, /* EXTON1 rising edge */ | ||
| 168 | PCF50633_INT2_EXTON1F = 0x08, /* EXTON1 falling edge */ | ||
| 169 | PCF50633_INT2_EXTON2R = 0x10, /* EXTON2 rising edge */ | ||
| 170 | PCF50633_INT2_EXTON2F = 0x20, /* EXTON2 falling edge */ | ||
| 171 | PCF50633_INT2_EXTON3R = 0x40, /* EXTON3 rising edge */ | ||
| 172 | PCF50633_INT2_EXTON3F = 0x80, /* EXTON3 falling edge */ | ||
| 173 | }; | ||
| 174 | |||
| 175 | enum pcf50633_reg_int3 { | ||
| 176 | PCF50633_INT3_BATFULL = 0x01, /* Battery full */ | ||
| 177 | PCF50633_INT3_CHGHALT = 0x02, /* Charger halt */ | ||
| 178 | PCF50633_INT3_THLIMON = 0x04, | ||
| 179 | PCF50633_INT3_THLIMOFF = 0x08, | ||
| 180 | PCF50633_INT3_USBLIMON = 0x10, | ||
| 181 | PCF50633_INT3_USBLIMOFF = 0x20, | ||
| 182 | PCF50633_INT3_ADCRDY = 0x40, /* ADC result ready */ | ||
| 183 | PCF50633_INT3_ONKEY1S = 0x80, /* ONKEY pressed 1 second */ | ||
| 184 | }; | ||
| 185 | |||
| 186 | enum pcf50633_reg_int4 { | ||
| 187 | PCF50633_INT4_LOWSYS = 0x01, | ||
| 188 | PCF50633_INT4_LOWBAT = 0x02, | ||
| 189 | PCF50633_INT4_HIGHTMP = 0x04, | ||
| 190 | PCF50633_INT4_AUTOPWRFAIL = 0x08, | ||
| 191 | PCF50633_INT4_DWN1PWRFAIL = 0x10, | ||
| 192 | PCF50633_INT4_DWN2PWRFAIL = 0x20, | ||
| 193 | PCF50633_INT4_LEDPWRFAIL = 0x40, | ||
| 194 | PCF50633_INT4_LEDOVP = 0x80, | ||
| 195 | }; | ||
| 196 | |||
| 197 | enum pcf50633_reg_int5 { | ||
| 198 | PCF50633_INT5_LDO1PWRFAIL = 0x01, | ||
| 199 | PCF50633_INT5_LDO2PWRFAIL = 0x02, | ||
| 200 | PCF50633_INT5_LDO3PWRFAIL = 0x04, | ||
| 201 | PCF50633_INT5_LDO4PWRFAIL = 0x08, | ||
| 202 | PCF50633_INT5_LDO5PWRFAIL = 0x10, | ||
| 203 | PCF50633_INT5_LDO6PWRFAIL = 0x20, | ||
| 204 | PCF50633_INT5_HCLDOPWRFAIL = 0x40, | ||
| 205 | PCF50633_INT5_HCLDOOVL = 0x80, | ||
| 206 | }; | ||
| 207 | |||
| 208 | /* misc. registers */ | ||
| 209 | #define PCF50633_REG_OOCSHDWN 0x0c | ||
| 210 | |||
| 211 | /* LED registers */ | ||
| 212 | #define PCF50633_REG_LEDOUT 0x28 | ||
| 213 | #define PCF50633_REG_LEDENA 0x29 | ||
| 214 | #define PCF50633_REG_LEDCTL 0x2a | ||
| 215 | #define PCF50633_REG_LEDDIM 0x2b | ||
| 216 | |||
| 217 | #endif | ||
| 218 | |||
diff --git a/include/linux/mfd/pcf50633/gpio.h b/include/linux/mfd/pcf50633/gpio.h new file mode 100644 index 000000000000..a42b845efc54 --- /dev/null +++ b/include/linux/mfd/pcf50633/gpio.h | |||
| @@ -0,0 +1,52 @@ | |||
| 1 | /* | ||
| 2 | * gpio.h -- GPIO driver for NXP PCF50633 | ||
| 3 | * | ||
| 4 | * (C) 2006-2008 by Openmoko, Inc. | ||
| 5 | * All rights reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License as published by the | ||
| 9 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 10 | * option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __LINUX_MFD_PCF50633_GPIO_H | ||
| 14 | #define __LINUX_MFD_PCF50633_GPIO_H | ||
| 15 | |||
| 16 | #include <linux/mfd/pcf50633/core.h> | ||
| 17 | |||
| 18 | #define PCF50633_GPIO1 1 | ||
| 19 | #define PCF50633_GPIO2 2 | ||
| 20 | #define PCF50633_GPIO3 3 | ||
| 21 | #define PCF50633_GPO 4 | ||
| 22 | |||
| 23 | #define PCF50633_REG_GPIO1CFG 0x14 | ||
| 24 | #define PCF50633_REG_GPIO2CFG 0x15 | ||
| 25 | #define PCF50633_REG_GPIO3CFG 0x16 | ||
| 26 | #define PCF50633_REG_GPOCFG 0x17 | ||
| 27 | |||
| 28 | #define PCF50633_GPOCFG_GPOSEL_MASK 0x07 | ||
| 29 | |||
| 30 | enum pcf50633_reg_gpocfg { | ||
| 31 | PCF50633_GPOCFG_GPOSEL_0 = 0x00, | ||
| 32 | PCF50633_GPOCFG_GPOSEL_LED_NFET = 0x01, | ||
| 33 | PCF50633_GPOCFG_GPOSEL_SYSxOK = 0x02, | ||
| 34 | PCF50633_GPOCFG_GPOSEL_CLK32K = 0x03, | ||
| 35 | PCF50633_GPOCFG_GPOSEL_ADAPUSB = 0x04, | ||
| 36 | PCF50633_GPOCFG_GPOSEL_USBxOK = 0x05, | ||
| 37 | PCF50633_GPOCFG_GPOSEL_ACTPH4 = 0x06, | ||
| 38 | PCF50633_GPOCFG_GPOSEL_1 = 0x07, | ||
| 39 | PCF50633_GPOCFG_GPOSEL_INVERSE = 0x08, | ||
| 40 | }; | ||
| 41 | |||
| 42 | int pcf50633_gpio_set(struct pcf50633 *pcf, int gpio, u8 val); | ||
| 43 | u8 pcf50633_gpio_get(struct pcf50633 *pcf, int gpio); | ||
| 44 | |||
| 45 | int pcf50633_gpio_invert_set(struct pcf50633 *, int gpio, int invert); | ||
| 46 | int pcf50633_gpio_invert_get(struct pcf50633 *pcf, int gpio); | ||
| 47 | |||
| 48 | int pcf50633_gpio_power_supply_set(struct pcf50633 *, | ||
| 49 | int gpio, int regulator, int on); | ||
| 50 | #endif /* __LINUX_MFD_PCF50633_GPIO_H */ | ||
| 51 | |||
| 52 | |||
diff --git a/include/linux/mfd/pcf50633/mbc.h b/include/linux/mfd/pcf50633/mbc.h new file mode 100644 index 000000000000..6e17619b773a --- /dev/null +++ b/include/linux/mfd/pcf50633/mbc.h | |||
| @@ -0,0 +1,134 @@ | |||
| 1 | /* | ||
| 2 | * mbc.h -- Driver for NXP PCF50633 Main Battery Charger | ||
| 3 | * | ||
| 4 | * (C) 2006-2008 by Openmoko, Inc. | ||
| 5 | * All rights reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License as published by the | ||
| 9 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 10 | * option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __LINUX_MFD_PCF50633_MBC_H | ||
| 14 | #define __LINUX_MFD_PCF50633_MBC_H | ||
| 15 | |||
| 16 | #include <linux/mfd/pcf50633/core.h> | ||
| 17 | #include <linux/platform_device.h> | ||
| 18 | |||
| 19 | #define PCF50633_REG_MBCC1 0x43 | ||
| 20 | #define PCF50633_REG_MBCC2 0x44 | ||
| 21 | #define PCF50633_REG_MBCC3 0x45 | ||
| 22 | #define PCF50633_REG_MBCC4 0x46 | ||
| 23 | #define PCF50633_REG_MBCC5 0x47 | ||
| 24 | #define PCF50633_REG_MBCC6 0x48 | ||
| 25 | #define PCF50633_REG_MBCC7 0x49 | ||
| 26 | #define PCF50633_REG_MBCC8 0x4a | ||
| 27 | #define PCF50633_REG_MBCS1 0x4b | ||
| 28 | #define PCF50633_REG_MBCS2 0x4c | ||
| 29 | #define PCF50633_REG_MBCS3 0x4d | ||
| 30 | |||
| 31 | enum pcf50633_reg_mbcc1 { | ||
| 32 | PCF50633_MBCC1_CHGENA = 0x01, /* Charger enable */ | ||
| 33 | PCF50633_MBCC1_AUTOSTOP = 0x02, | ||
| 34 | PCF50633_MBCC1_AUTORES = 0x04, /* automatic resume */ | ||
| 35 | PCF50633_MBCC1_RESUME = 0x08, /* explicit resume cmd */ | ||
| 36 | PCF50633_MBCC1_RESTART = 0x10, /* restart charging */ | ||
| 37 | PCF50633_MBCC1_PREWDTIME_60M = 0x20, /* max. precharging time */ | ||
| 38 | PCF50633_MBCC1_WDTIME_1H = 0x00, | ||
| 39 | PCF50633_MBCC1_WDTIME_2H = 0x40, | ||
| 40 | PCF50633_MBCC1_WDTIME_4H = 0x80, | ||
| 41 | PCF50633_MBCC1_WDTIME_6H = 0xc0, | ||
| 42 | }; | ||
| 43 | #define PCF50633_MBCC1_WDTIME_MASK 0xc0 | ||
| 44 | |||
| 45 | enum pcf50633_reg_mbcc2 { | ||
| 46 | PCF50633_MBCC2_VBATCOND_2V7 = 0x00, | ||
| 47 | PCF50633_MBCC2_VBATCOND_2V85 = 0x01, | ||
| 48 | PCF50633_MBCC2_VBATCOND_3V0 = 0x02, | ||
| 49 | PCF50633_MBCC2_VBATCOND_3V15 = 0x03, | ||
| 50 | PCF50633_MBCC2_VMAX_4V = 0x00, | ||
| 51 | PCF50633_MBCC2_VMAX_4V20 = 0x28, | ||
| 52 | PCF50633_MBCC2_VRESDEBTIME_64S = 0x80, /* debounce time (32/64sec) */ | ||
| 53 | }; | ||
| 54 | |||
| 55 | enum pcf50633_reg_mbcc7 { | ||
| 56 | PCF50633_MBCC7_USB_100mA = 0x00, | ||
| 57 | PCF50633_MBCC7_USB_500mA = 0x01, | ||
| 58 | PCF50633_MBCC7_USB_1000mA = 0x02, | ||
| 59 | PCF50633_MBCC7_USB_SUSPEND = 0x03, | ||
| 60 | PCF50633_MBCC7_BATTEMP_EN = 0x04, | ||
| 61 | PCF50633_MBCC7_BATSYSIMAX_1A6 = 0x00, | ||
| 62 | PCF50633_MBCC7_BATSYSIMAX_1A8 = 0x40, | ||
| 63 | PCF50633_MBCC7_BATSYSIMAX_2A0 = 0x80, | ||
| 64 | PCF50633_MBCC7_BATSYSIMAX_2A2 = 0xc0, | ||
| 65 | }; | ||
| 66 | #define PCF50633_MBCC7_USB_MASK 0x03 | ||
| 67 | |||
| 68 | enum pcf50633_reg_mbcc8 { | ||
| 69 | PCF50633_MBCC8_USBENASUS = 0x10, | ||
| 70 | }; | ||
| 71 | |||
| 72 | enum pcf50633_reg_mbcs1 { | ||
| 73 | PCF50633_MBCS1_USBPRES = 0x01, | ||
| 74 | PCF50633_MBCS1_USBOK = 0x02, | ||
| 75 | PCF50633_MBCS1_ADAPTPRES = 0x04, | ||
| 76 | PCF50633_MBCS1_ADAPTOK = 0x08, | ||
| 77 | PCF50633_MBCS1_TBAT_OK = 0x00, | ||
| 78 | PCF50633_MBCS1_TBAT_ABOVE = 0x10, | ||
| 79 | PCF50633_MBCS1_TBAT_BELOW = 0x20, | ||
| 80 | PCF50633_MBCS1_TBAT_UNDEF = 0x30, | ||
| 81 | PCF50633_MBCS1_PREWDTEXP = 0x40, | ||
| 82 | PCF50633_MBCS1_WDTEXP = 0x80, | ||
| 83 | }; | ||
| 84 | |||
| 85 | enum pcf50633_reg_mbcs2_mbcmod { | ||
| 86 | PCF50633_MBCS2_MBC_PLAY = 0x00, | ||
| 87 | PCF50633_MBCS2_MBC_USB_PRE = 0x01, | ||
| 88 | PCF50633_MBCS2_MBC_USB_PRE_WAIT = 0x02, | ||
| 89 | PCF50633_MBCS2_MBC_USB_FAST = 0x03, | ||
| 90 | PCF50633_MBCS2_MBC_USB_FAST_WAIT = 0x04, | ||
| 91 | PCF50633_MBCS2_MBC_USB_SUSPEND = 0x05, | ||
| 92 | PCF50633_MBCS2_MBC_ADP_PRE = 0x06, | ||
| 93 | PCF50633_MBCS2_MBC_ADP_PRE_WAIT = 0x07, | ||
| 94 | PCF50633_MBCS2_MBC_ADP_FAST = 0x08, | ||
| 95 | PCF50633_MBCS2_MBC_ADP_FAST_WAIT = 0x09, | ||
| 96 | PCF50633_MBCS2_MBC_BAT_FULL = 0x0a, | ||
| 97 | PCF50633_MBCS2_MBC_HALT = 0x0b, | ||
| 98 | }; | ||
| 99 | #define PCF50633_MBCS2_MBC_MASK 0x0f | ||
| 100 | enum pcf50633_reg_mbcs2_chgstat { | ||
| 101 | PCF50633_MBCS2_CHGS_NONE = 0x00, | ||
| 102 | PCF50633_MBCS2_CHGS_ADAPTER = 0x10, | ||
| 103 | PCF50633_MBCS2_CHGS_USB = 0x20, | ||
| 104 | PCF50633_MBCS2_CHGS_BOTH = 0x30, | ||
| 105 | }; | ||
| 106 | #define PCF50633_MBCS2_RESSTAT_AUTO 0x40 | ||
| 107 | |||
| 108 | enum pcf50633_reg_mbcs3 { | ||
| 109 | PCF50633_MBCS3_USBLIM_PLAY = 0x01, | ||
| 110 | PCF50633_MBCS3_USBLIM_CGH = 0x02, | ||
| 111 | PCF50633_MBCS3_TLIM_PLAY = 0x04, | ||
| 112 | PCF50633_MBCS3_TLIM_CHG = 0x08, | ||
| 113 | PCF50633_MBCS3_ILIM = 0x10, /* 1: Ibat > Icutoff */ | ||
| 114 | PCF50633_MBCS3_VLIM = 0x20, /* 1: Vbat == Vmax */ | ||
| 115 | PCF50633_MBCS3_VBATSTAT = 0x40, /* 1: Vbat > Vbatcond */ | ||
| 116 | PCF50633_MBCS3_VRES = 0x80, /* 1: Vbat > Vth(RES) */ | ||
| 117 | }; | ||
| 118 | |||
| 119 | #define PCF50633_MBCC2_VBATCOND_MASK 0x03 | ||
| 120 | #define PCF50633_MBCC2_VMAX_MASK 0x3c | ||
| 121 | |||
| 122 | /* Charger status */ | ||
| 123 | #define PCF50633_MBC_USB_ONLINE 0x01 | ||
| 124 | #define PCF50633_MBC_USB_ACTIVE 0x02 | ||
| 125 | #define PCF50633_MBC_ADAPTER_ONLINE 0x04 | ||
| 126 | #define PCF50633_MBC_ADAPTER_ACTIVE 0x08 | ||
| 127 | |||
| 128 | int pcf50633_mbc_usb_curlim_set(struct pcf50633 *pcf, int ma); | ||
| 129 | |||
| 130 | int pcf50633_mbc_get_status(struct pcf50633 *); | ||
| 131 | void pcf50633_mbc_set_status(struct pcf50633 *, int what, int status); | ||
| 132 | |||
| 133 | #endif | ||
| 134 | |||
diff --git a/include/linux/mfd/pcf50633/pmic.h b/include/linux/mfd/pcf50633/pmic.h new file mode 100644 index 000000000000..2d3dbe53b235 --- /dev/null +++ b/include/linux/mfd/pcf50633/pmic.h | |||
| @@ -0,0 +1,67 @@ | |||
| 1 | #ifndef __LINUX_MFD_PCF50633_PMIC_H | ||
| 2 | #define __LINUX_MFD_PCF50633_PMIC_H | ||
| 3 | |||
| 4 | #include <linux/mfd/pcf50633/core.h> | ||
| 5 | #include <linux/platform_device.h> | ||
| 6 | |||
| 7 | #define PCF50633_REG_AUTOOUT 0x1a | ||
| 8 | #define PCF50633_REG_AUTOENA 0x1b | ||
| 9 | #define PCF50633_REG_AUTOCTL 0x1c | ||
| 10 | #define PCF50633_REG_AUTOMXC 0x1d | ||
| 11 | #define PCF50633_REG_DOWN1OUT 0x1e | ||
| 12 | #define PCF50633_REG_DOWN1ENA 0x1f | ||
| 13 | #define PCF50633_REG_DOWN1CTL 0x20 | ||
| 14 | #define PCF50633_REG_DOWN1MXC 0x21 | ||
| 15 | #define PCF50633_REG_DOWN2OUT 0x22 | ||
| 16 | #define PCF50633_REG_DOWN2ENA 0x23 | ||
| 17 | #define PCF50633_REG_DOWN2CTL 0x24 | ||
| 18 | #define PCF50633_REG_DOWN2MXC 0x25 | ||
| 19 | #define PCF50633_REG_MEMLDOOUT 0x26 | ||
| 20 | #define PCF50633_REG_MEMLDOENA 0x27 | ||
| 21 | #define PCF50633_REG_LDO1OUT 0x2d | ||
| 22 | #define PCF50633_REG_LDO1ENA 0x2e | ||
| 23 | #define PCF50633_REG_LDO2OUT 0x2f | ||
| 24 | #define PCF50633_REG_LDO2ENA 0x30 | ||
| 25 | #define PCF50633_REG_LDO3OUT 0x31 | ||
| 26 | #define PCF50633_REG_LDO3ENA 0x32 | ||
| 27 | #define PCF50633_REG_LDO4OUT 0x33 | ||
| 28 | #define PCF50633_REG_LDO4ENA 0x34 | ||
| 29 | #define PCF50633_REG_LDO5OUT 0x35 | ||
| 30 | #define PCF50633_REG_LDO5ENA 0x36 | ||
| 31 | #define PCF50633_REG_LDO6OUT 0x37 | ||
| 32 | #define PCF50633_REG_LDO6ENA 0x38 | ||
| 33 | #define PCF50633_REG_HCLDOOUT 0x39 | ||
| 34 | #define PCF50633_REG_HCLDOENA 0x3a | ||
| 35 | #define PCF50633_REG_HCLDOOVL 0x40 | ||
| 36 | |||
| 37 | enum pcf50633_regulator_enable { | ||
| 38 | PCF50633_REGULATOR_ON = 0x01, | ||
| 39 | PCF50633_REGULATOR_ON_GPIO1 = 0x02, | ||
| 40 | PCF50633_REGULATOR_ON_GPIO2 = 0x04, | ||
| 41 | PCF50633_REGULATOR_ON_GPIO3 = 0x08, | ||
| 42 | }; | ||
| 43 | #define PCF50633_REGULATOR_ON_MASK 0x0f | ||
| 44 | |||
| 45 | enum pcf50633_regulator_phase { | ||
| 46 | PCF50633_REGULATOR_ACTPH1 = 0x00, | ||
| 47 | PCF50633_REGULATOR_ACTPH2 = 0x10, | ||
| 48 | PCF50633_REGULATOR_ACTPH3 = 0x20, | ||
| 49 | PCF50633_REGULATOR_ACTPH4 = 0x30, | ||
| 50 | }; | ||
| 51 | #define PCF50633_REGULATOR_ACTPH_MASK 0x30 | ||
| 52 | |||
| 53 | enum pcf50633_regulator_id { | ||
| 54 | PCF50633_REGULATOR_AUTO, | ||
| 55 | PCF50633_REGULATOR_DOWN1, | ||
| 56 | PCF50633_REGULATOR_DOWN2, | ||
| 57 | PCF50633_REGULATOR_LDO1, | ||
| 58 | PCF50633_REGULATOR_LDO2, | ||
| 59 | PCF50633_REGULATOR_LDO3, | ||
| 60 | PCF50633_REGULATOR_LDO4, | ||
| 61 | PCF50633_REGULATOR_LDO5, | ||
| 62 | PCF50633_REGULATOR_LDO6, | ||
| 63 | PCF50633_REGULATOR_HCLDO, | ||
| 64 | PCF50633_REGULATOR_MEMLDO, | ||
| 65 | }; | ||
| 66 | #endif | ||
| 67 | |||
diff --git a/include/net/wimax.h b/include/net/wimax.h index 073809ce94f8..6b3824edb39e 100644 --- a/include/net/wimax.h +++ b/include/net/wimax.h | |||
| @@ -323,8 +323,8 @@ struct input_dev; | |||
| 323 | * | 323 | * |
| 324 | * @rf_hw: [private] State of the hardware radio switch (OFF/ON) | 324 | * @rf_hw: [private] State of the hardware radio switch (OFF/ON) |
| 325 | * | 325 | * |
| 326 | * @debufs_dentry: [private] Used to hook up a debugfs entry. This | 326 | * @debugfs_dentry: [private] Used to hook up a debugfs entry. This |
| 327 | * shows up in the debugfs root as wimax:DEVICENAME. | 327 | * shows up in the debugfs root as wimax\:DEVICENAME. |
| 328 | * | 328 | * |
| 329 | * Description: | 329 | * Description: |
| 330 | * This structure defines a common interface to access all WiMAX | 330 | * This structure defines a common interface to access all WiMAX |
diff --git a/include/sound/soc-dapm.h b/include/sound/soc-dapm.h index 4af1083e3287..93a4edb148b5 100644 --- a/include/sound/soc-dapm.h +++ b/include/sound/soc-dapm.h | |||
| @@ -178,7 +178,7 @@ | |||
| 178 | .private_value = (unsigned long)&xenum } | 178 | .private_value = (unsigned long)&xenum } |
| 179 | #define SOC_DAPM_VALUE_ENUM(xname, xenum) \ | 179 | #define SOC_DAPM_VALUE_ENUM(xname, xenum) \ |
| 180 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | 180 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ |
| 181 | .info = snd_soc_info_value_enum_double, \ | 181 | .info = snd_soc_info_enum_double, \ |
| 182 | .get = snd_soc_dapm_get_value_enum_double, \ | 182 | .get = snd_soc_dapm_get_value_enum_double, \ |
| 183 | .put = snd_soc_dapm_put_value_enum_double, \ | 183 | .put = snd_soc_dapm_put_value_enum_double, \ |
| 184 | .private_value = (unsigned long)&xenum } | 184 | .private_value = (unsigned long)&xenum } |
diff --git a/include/sound/soc.h b/include/sound/soc.h index 9b930d342116..24593ac3ea19 100644 --- a/include/sound/soc.h +++ b/include/sound/soc.h | |||
| @@ -106,7 +106,7 @@ | |||
| 106 | .private_value = (unsigned long)&xenum } | 106 | .private_value = (unsigned long)&xenum } |
| 107 | #define SOC_VALUE_ENUM(xname, xenum) \ | 107 | #define SOC_VALUE_ENUM(xname, xenum) \ |
| 108 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname,\ | 108 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname,\ |
| 109 | .info = snd_soc_info_value_enum_double, \ | 109 | .info = snd_soc_info_enum_double, \ |
| 110 | .get = snd_soc_get_value_enum_double, \ | 110 | .get = snd_soc_get_value_enum_double, \ |
| 111 | .put = snd_soc_put_value_enum_double, \ | 111 | .put = snd_soc_put_value_enum_double, \ |
| 112 | .private_value = (unsigned long)&xenum } | 112 | .private_value = (unsigned long)&xenum } |
| @@ -211,8 +211,6 @@ int snd_soc_get_enum_double(struct snd_kcontrol *kcontrol, | |||
| 211 | struct snd_ctl_elem_value *ucontrol); | 211 | struct snd_ctl_elem_value *ucontrol); |
| 212 | int snd_soc_put_enum_double(struct snd_kcontrol *kcontrol, | 212 | int snd_soc_put_enum_double(struct snd_kcontrol *kcontrol, |
| 213 | struct snd_ctl_elem_value *ucontrol); | 213 | struct snd_ctl_elem_value *ucontrol); |
| 214 | int snd_soc_info_value_enum_double(struct snd_kcontrol *kcontrol, | ||
| 215 | struct snd_ctl_elem_info *uinfo); | ||
| 216 | int snd_soc_get_value_enum_double(struct snd_kcontrol *kcontrol, | 214 | int snd_soc_get_value_enum_double(struct snd_kcontrol *kcontrol, |
| 217 | struct snd_ctl_elem_value *ucontrol); | 215 | struct snd_ctl_elem_value *ucontrol); |
| 218 | int snd_soc_put_value_enum_double(struct snd_kcontrol *kcontrol, | 216 | int snd_soc_put_value_enum_double(struct snd_kcontrol *kcontrol, |
| @@ -419,17 +417,6 @@ struct soc_enum { | |||
| 419 | unsigned char shift_l; | 417 | unsigned char shift_l; |
| 420 | unsigned char shift_r; | 418 | unsigned char shift_r; |
| 421 | unsigned int max; | 419 | unsigned int max; |
| 422 | const char **texts; | ||
| 423 | void *dapm; | ||
| 424 | }; | ||
| 425 | |||
| 426 | /* semi enumerated kcontrol */ | ||
| 427 | struct soc_value_enum { | ||
| 428 | unsigned short reg; | ||
| 429 | unsigned short reg2; | ||
| 430 | unsigned char shift_l; | ||
| 431 | unsigned char shift_r; | ||
| 432 | unsigned int max; | ||
| 433 | unsigned int mask; | 420 | unsigned int mask; |
| 434 | const char **texts; | 421 | const char **texts; |
| 435 | const unsigned int *values; | 422 | const unsigned int *values; |
diff --git a/kernel/async.c b/kernel/async.c index f286e9f2b736..608b32b42812 100644 --- a/kernel/async.c +++ b/kernel/async.c | |||
| @@ -90,12 +90,12 @@ extern int initcall_debug; | |||
| 90 | static async_cookie_t __lowest_in_progress(struct list_head *running) | 90 | static async_cookie_t __lowest_in_progress(struct list_head *running) |
| 91 | { | 91 | { |
| 92 | struct async_entry *entry; | 92 | struct async_entry *entry; |
| 93 | if (!list_empty(&async_pending)) { | 93 | if (!list_empty(running)) { |
| 94 | entry = list_first_entry(&async_pending, | 94 | entry = list_first_entry(running, |
| 95 | struct async_entry, list); | 95 | struct async_entry, list); |
| 96 | return entry->cookie; | 96 | return entry->cookie; |
| 97 | } else if (!list_empty(running)) { | 97 | } else if (!list_empty(&async_pending)) { |
| 98 | entry = list_first_entry(running, | 98 | entry = list_first_entry(&async_pending, |
| 99 | struct async_entry, list); | 99 | struct async_entry, list); |
| 100 | return entry->cookie; | 100 | return entry->cookie; |
| 101 | } else { | 101 | } else { |
| @@ -104,6 +104,17 @@ static async_cookie_t __lowest_in_progress(struct list_head *running) | |||
| 104 | } | 104 | } |
| 105 | 105 | ||
| 106 | } | 106 | } |
| 107 | |||
| 108 | static async_cookie_t lowest_in_progress(struct list_head *running) | ||
| 109 | { | ||
| 110 | unsigned long flags; | ||
| 111 | async_cookie_t ret; | ||
| 112 | |||
| 113 | spin_lock_irqsave(&async_lock, flags); | ||
| 114 | ret = __lowest_in_progress(running); | ||
| 115 | spin_unlock_irqrestore(&async_lock, flags); | ||
| 116 | return ret; | ||
| 117 | } | ||
| 107 | /* | 118 | /* |
| 108 | * pick the first pending entry and run it | 119 | * pick the first pending entry and run it |
| 109 | */ | 120 | */ |
| @@ -229,7 +240,7 @@ void async_synchronize_cookie_special(async_cookie_t cookie, struct list_head *r | |||
| 229 | starttime = ktime_get(); | 240 | starttime = ktime_get(); |
| 230 | } | 241 | } |
| 231 | 242 | ||
| 232 | wait_event(async_done, __lowest_in_progress(running) >= cookie); | 243 | wait_event(async_done, lowest_in_progress(running) >= cookie); |
| 233 | 244 | ||
| 234 | if (initcall_debug && system_state == SYSTEM_BOOTING) { | 245 | if (initcall_debug && system_state == SYSTEM_BOOTING) { |
| 235 | endtime = ktime_get(); | 246 | endtime = ktime_get(); |
diff --git a/kernel/sched.c b/kernel/sched.c index deb5ac8c12f3..8be2c13b50d0 100644 --- a/kernel/sched.c +++ b/kernel/sched.c | |||
| @@ -125,6 +125,9 @@ DEFINE_TRACE(sched_switch); | |||
| 125 | DEFINE_TRACE(sched_migrate_task); | 125 | DEFINE_TRACE(sched_migrate_task); |
| 126 | 126 | ||
| 127 | #ifdef CONFIG_SMP | 127 | #ifdef CONFIG_SMP |
| 128 | |||
| 129 | static void double_rq_lock(struct rq *rq1, struct rq *rq2); | ||
| 130 | |||
| 128 | /* | 131 | /* |
| 129 | * Divide a load by a sched group cpu_power : (load / sg->__cpu_power) | 132 | * Divide a load by a sched group cpu_power : (load / sg->__cpu_power) |
| 130 | * Since cpu_power is a 'constant', we can use a reciprocal divide. | 133 | * Since cpu_power is a 'constant', we can use a reciprocal divide. |
| @@ -7282,10 +7285,10 @@ cpu_to_phys_group(int cpu, const struct cpumask *cpu_map, | |||
| 7282 | * groups, so roll our own. Now each node has its own list of groups which | 7285 | * groups, so roll our own. Now each node has its own list of groups which |
| 7283 | * gets dynamically allocated. | 7286 | * gets dynamically allocated. |
| 7284 | */ | 7287 | */ |
| 7285 | static DEFINE_PER_CPU(struct sched_domain, node_domains); | 7288 | static DEFINE_PER_CPU(struct static_sched_domain, node_domains); |
| 7286 | static struct sched_group ***sched_group_nodes_bycpu; | 7289 | static struct sched_group ***sched_group_nodes_bycpu; |
| 7287 | 7290 | ||
| 7288 | static DEFINE_PER_CPU(struct sched_domain, allnodes_domains); | 7291 | static DEFINE_PER_CPU(struct static_sched_domain, allnodes_domains); |
| 7289 | static DEFINE_PER_CPU(struct static_sched_group, sched_group_allnodes); | 7292 | static DEFINE_PER_CPU(struct static_sched_group, sched_group_allnodes); |
| 7290 | 7293 | ||
| 7291 | static int cpu_to_allnodes_group(int cpu, const struct cpumask *cpu_map, | 7294 | static int cpu_to_allnodes_group(int cpu, const struct cpumask *cpu_map, |
| @@ -7560,7 +7563,7 @@ static int __build_sched_domains(const struct cpumask *cpu_map, | |||
| 7560 | #ifdef CONFIG_NUMA | 7563 | #ifdef CONFIG_NUMA |
| 7561 | if (cpumask_weight(cpu_map) > | 7564 | if (cpumask_weight(cpu_map) > |
| 7562 | SD_NODES_PER_DOMAIN*cpumask_weight(nodemask)) { | 7565 | SD_NODES_PER_DOMAIN*cpumask_weight(nodemask)) { |
| 7563 | sd = &per_cpu(allnodes_domains, i); | 7566 | sd = &per_cpu(allnodes_domains, i).sd; |
| 7564 | SD_INIT(sd, ALLNODES); | 7567 | SD_INIT(sd, ALLNODES); |
| 7565 | set_domain_attribute(sd, attr); | 7568 | set_domain_attribute(sd, attr); |
| 7566 | cpumask_copy(sched_domain_span(sd), cpu_map); | 7569 | cpumask_copy(sched_domain_span(sd), cpu_map); |
| @@ -7570,7 +7573,7 @@ static int __build_sched_domains(const struct cpumask *cpu_map, | |||
| 7570 | } else | 7573 | } else |
| 7571 | p = NULL; | 7574 | p = NULL; |
| 7572 | 7575 | ||
| 7573 | sd = &per_cpu(node_domains, i); | 7576 | sd = &per_cpu(node_domains, i).sd; |
| 7574 | SD_INIT(sd, NODE); | 7577 | SD_INIT(sd, NODE); |
| 7575 | set_domain_attribute(sd, attr); | 7578 | set_domain_attribute(sd, attr); |
| 7576 | sched_domain_node_span(cpu_to_node(i), sched_domain_span(sd)); | 7579 | sched_domain_node_span(cpu_to_node(i), sched_domain_span(sd)); |
| @@ -7688,7 +7691,7 @@ static int __build_sched_domains(const struct cpumask *cpu_map, | |||
| 7688 | for_each_cpu(j, nodemask) { | 7691 | for_each_cpu(j, nodemask) { |
| 7689 | struct sched_domain *sd; | 7692 | struct sched_domain *sd; |
| 7690 | 7693 | ||
| 7691 | sd = &per_cpu(node_domains, j); | 7694 | sd = &per_cpu(node_domains, j).sd; |
| 7692 | sd->groups = sg; | 7695 | sd->groups = sg; |
| 7693 | } | 7696 | } |
| 7694 | sg->__cpu_power = 0; | 7697 | sg->__cpu_power = 0; |
diff --git a/kernel/sched_debug.c b/kernel/sched_debug.c index 4293cfa9681d..16eeba4e4169 100644 --- a/kernel/sched_debug.c +++ b/kernel/sched_debug.c | |||
| @@ -145,6 +145,19 @@ static void print_rq(struct seq_file *m, struct rq *rq, int rq_cpu) | |||
| 145 | read_unlock_irqrestore(&tasklist_lock, flags); | 145 | read_unlock_irqrestore(&tasklist_lock, flags); |
| 146 | } | 146 | } |
| 147 | 147 | ||
| 148 | #if defined(CONFIG_CGROUP_SCHED) && \ | ||
| 149 | (defined(CONFIG_FAIR_GROUP_SCHED) || defined(CONFIG_RT_GROUP_SCHED)) | ||
| 150 | static void task_group_path(struct task_group *tg, char *buf, int buflen) | ||
| 151 | { | ||
| 152 | /* may be NULL if the underlying cgroup isn't fully-created yet */ | ||
| 153 | if (!tg->css.cgroup) { | ||
| 154 | buf[0] = '\0'; | ||
| 155 | return; | ||
| 156 | } | ||
| 157 | cgroup_path(tg->css.cgroup, buf, buflen); | ||
| 158 | } | ||
| 159 | #endif | ||
| 160 | |||
| 148 | void print_cfs_rq(struct seq_file *m, int cpu, struct cfs_rq *cfs_rq) | 161 | void print_cfs_rq(struct seq_file *m, int cpu, struct cfs_rq *cfs_rq) |
| 149 | { | 162 | { |
| 150 | s64 MIN_vruntime = -1, min_vruntime, max_vruntime = -1, | 163 | s64 MIN_vruntime = -1, min_vruntime, max_vruntime = -1, |
| @@ -154,10 +167,10 @@ void print_cfs_rq(struct seq_file *m, int cpu, struct cfs_rq *cfs_rq) | |||
| 154 | unsigned long flags; | 167 | unsigned long flags; |
| 155 | 168 | ||
| 156 | #if defined(CONFIG_CGROUP_SCHED) && defined(CONFIG_FAIR_GROUP_SCHED) | 169 | #if defined(CONFIG_CGROUP_SCHED) && defined(CONFIG_FAIR_GROUP_SCHED) |
| 157 | char path[128] = ""; | 170 | char path[128]; |
| 158 | struct task_group *tg = cfs_rq->tg; | 171 | struct task_group *tg = cfs_rq->tg; |
| 159 | 172 | ||
| 160 | cgroup_path(tg->css.cgroup, path, sizeof(path)); | 173 | task_group_path(tg, path, sizeof(path)); |
| 161 | 174 | ||
| 162 | SEQ_printf(m, "\ncfs_rq[%d]:%s\n", cpu, path); | 175 | SEQ_printf(m, "\ncfs_rq[%d]:%s\n", cpu, path); |
| 163 | #elif defined(CONFIG_USER_SCHED) && defined(CONFIG_FAIR_GROUP_SCHED) | 176 | #elif defined(CONFIG_USER_SCHED) && defined(CONFIG_FAIR_GROUP_SCHED) |
| @@ -208,10 +221,10 @@ void print_cfs_rq(struct seq_file *m, int cpu, struct cfs_rq *cfs_rq) | |||
| 208 | void print_rt_rq(struct seq_file *m, int cpu, struct rt_rq *rt_rq) | 221 | void print_rt_rq(struct seq_file *m, int cpu, struct rt_rq *rt_rq) |
| 209 | { | 222 | { |
| 210 | #if defined(CONFIG_CGROUP_SCHED) && defined(CONFIG_RT_GROUP_SCHED) | 223 | #if defined(CONFIG_CGROUP_SCHED) && defined(CONFIG_RT_GROUP_SCHED) |
| 211 | char path[128] = ""; | 224 | char path[128]; |
| 212 | struct task_group *tg = rt_rq->tg; | 225 | struct task_group *tg = rt_rq->tg; |
| 213 | 226 | ||
| 214 | cgroup_path(tg->css.cgroup, path, sizeof(path)); | 227 | task_group_path(tg, path, sizeof(path)); |
| 215 | 228 | ||
| 216 | SEQ_printf(m, "\nrt_rq[%d]:%s\n", cpu, path); | 229 | SEQ_printf(m, "\nrt_rq[%d]:%s\n", cpu, path); |
| 217 | #else | 230 | #else |
diff --git a/net/bridge/netfilter/ebtables.c b/net/bridge/netfilter/ebtables.c index fa108c46e851..8a8743d7d6e7 100644 --- a/net/bridge/netfilter/ebtables.c +++ b/net/bridge/netfilter/ebtables.c | |||
| @@ -85,12 +85,13 @@ static inline int ebt_do_match (struct ebt_entry_match *m, | |||
| 85 | static inline int ebt_dev_check(char *entry, const struct net_device *device) | 85 | static inline int ebt_dev_check(char *entry, const struct net_device *device) |
| 86 | { | 86 | { |
| 87 | int i = 0; | 87 | int i = 0; |
| 88 | const char *devname = device->name; | 88 | const char *devname; |
| 89 | 89 | ||
| 90 | if (*entry == '\0') | 90 | if (*entry == '\0') |
| 91 | return 0; | 91 | return 0; |
| 92 | if (!device) | 92 | if (!device) |
| 93 | return 1; | 93 | return 1; |
| 94 | devname = device->name; | ||
| 94 | /* 1 is the wildcard token */ | 95 | /* 1 is the wildcard token */ |
| 95 | while (entry[i] != '\0' && entry[i] != 1 && entry[i] == devname[i]) | 96 | while (entry[i] != '\0' && entry[i] != 1 && entry[i] == devname[i]) |
| 96 | i++; | 97 | i++; |
diff --git a/net/core/dev.c b/net/core/dev.c index 5f736f1ceeae..b715a55cccc4 100644 --- a/net/core/dev.c +++ b/net/core/dev.c | |||
| @@ -1088,6 +1088,11 @@ int dev_open(struct net_device *dev) | |||
| 1088 | dev->flags |= IFF_UP; | 1088 | dev->flags |= IFF_UP; |
| 1089 | 1089 | ||
| 1090 | /* | 1090 | /* |
| 1091 | * Enable NET_DMA | ||
| 1092 | */ | ||
| 1093 | dmaengine_get(); | ||
| 1094 | |||
| 1095 | /* | ||
| 1091 | * Initialize multicasting status | 1096 | * Initialize multicasting status |
| 1092 | */ | 1097 | */ |
| 1093 | dev_set_rx_mode(dev); | 1098 | dev_set_rx_mode(dev); |
| @@ -1164,6 +1169,11 @@ int dev_close(struct net_device *dev) | |||
| 1164 | */ | 1169 | */ |
| 1165 | call_netdevice_notifiers(NETDEV_DOWN, dev); | 1170 | call_netdevice_notifiers(NETDEV_DOWN, dev); |
| 1166 | 1171 | ||
| 1172 | /* | ||
| 1173 | * Shutdown NET_DMA | ||
| 1174 | */ | ||
| 1175 | dmaengine_put(); | ||
| 1176 | |||
| 1167 | return 0; | 1177 | return 0; |
| 1168 | } | 1178 | } |
| 1169 | 1179 | ||
| @@ -5151,9 +5161,6 @@ static int __init net_dev_init(void) | |||
| 5151 | hotcpu_notifier(dev_cpu_callback, 0); | 5161 | hotcpu_notifier(dev_cpu_callback, 0); |
| 5152 | dst_init(); | 5162 | dst_init(); |
| 5153 | dev_mcast_init(); | 5163 | dev_mcast_init(); |
| 5154 | #ifdef CONFIG_NET_DMA | ||
| 5155 | dmaengine_get(); | ||
| 5156 | #endif | ||
| 5157 | rc = 0; | 5164 | rc = 0; |
| 5158 | out: | 5165 | out: |
| 5159 | return rc; | 5166 | return rc; |
diff --git a/net/dccp/ccids/Kconfig b/net/dccp/ccids/Kconfig index b28bf962edc3..4b5db44970aa 100644 --- a/net/dccp/ccids/Kconfig +++ b/net/dccp/ccids/Kconfig | |||
| @@ -29,7 +29,7 @@ config IP_DCCP_CCID3 | |||
| 29 | http://www.ietf.org/rfc/rfc4342.txt | 29 | http://www.ietf.org/rfc/rfc4342.txt |
| 30 | 30 | ||
| 31 | The TFRC congestion control algorithms were initially described in | 31 | The TFRC congestion control algorithms were initially described in |
| 32 | RFC 5448. | 32 | RFC 5348. |
| 33 | 33 | ||
| 34 | This text was extracted from RFC 4340 (sec. 10.2), | 34 | This text was extracted from RFC 4340 (sec. 10.2), |
| 35 | http://www.ietf.org/rfc/rfc4340.txt | 35 | http://www.ietf.org/rfc/rfc4340.txt |
diff --git a/net/dccp/ccids/lib/tfrc.c b/net/dccp/ccids/lib/tfrc.c index 60c412ccfeef..4902029854d8 100644 --- a/net/dccp/ccids/lib/tfrc.c +++ b/net/dccp/ccids/lib/tfrc.c | |||
| @@ -36,7 +36,7 @@ out: | |||
| 36 | return rc; | 36 | return rc; |
| 37 | } | 37 | } |
| 38 | 38 | ||
| 39 | void __exit tfrc_lib_exit(void) | 39 | void tfrc_lib_exit(void) |
| 40 | { | 40 | { |
| 41 | tfrc_rx_packet_history_exit(); | 41 | tfrc_rx_packet_history_exit(); |
| 42 | tfrc_tx_packet_history_exit(); | 42 | tfrc_tx_packet_history_exit(); |
diff --git a/net/tipc/bcast.h b/net/tipc/bcast.h index 5aa024b99c55..2f2d731bc1c2 100644 --- a/net/tipc/bcast.h +++ b/net/tipc/bcast.h | |||
| @@ -124,7 +124,7 @@ static inline int tipc_nmap_equal(struct tipc_node_map *nm_a, struct tipc_node_m | |||
| 124 | static inline void tipc_nmap_diff(struct tipc_node_map *nm_a, struct tipc_node_map *nm_b, | 124 | static inline void tipc_nmap_diff(struct tipc_node_map *nm_a, struct tipc_node_map *nm_b, |
| 125 | struct tipc_node_map *nm_diff) | 125 | struct tipc_node_map *nm_diff) |
| 126 | { | 126 | { |
| 127 | int stop = sizeof(nm_a->map) / sizeof(u32); | 127 | int stop = ARRAY_SIZE(nm_a->map); |
| 128 | int w; | 128 | int w; |
| 129 | int b; | 129 | int b; |
| 130 | u32 map; | 130 | u32 map; |
diff --git a/net/xfrm/xfrm_ipcomp.c b/net/xfrm/xfrm_ipcomp.c index c609a4b98e15..42cd18391f46 100644 --- a/net/xfrm/xfrm_ipcomp.c +++ b/net/xfrm/xfrm_ipcomp.c | |||
| @@ -63,7 +63,6 @@ static int ipcomp_decompress(struct xfrm_state *x, struct sk_buff *skb) | |||
| 63 | if (len > skb_tailroom(skb)) | 63 | if (len > skb_tailroom(skb)) |
| 64 | len = skb_tailroom(skb); | 64 | len = skb_tailroom(skb); |
| 65 | 65 | ||
| 66 | skb->truesize += len; | ||
| 67 | __skb_put(skb, len); | 66 | __skb_put(skb, len); |
| 68 | 67 | ||
| 69 | len += plen; | 68 | len += plen; |
diff --git a/scripts/markup_oops.pl b/scripts/markup_oops.pl index 700a7a654a3f..d40449cafa84 100644 --- a/scripts/markup_oops.pl +++ b/scripts/markup_oops.pl | |||
| @@ -1,5 +1,7 @@ | |||
| 1 | #!/usr/bin/perl -w | 1 | #!/usr/bin/perl -w |
| 2 | 2 | ||
| 3 | use File::Basename; | ||
| 4 | |||
| 3 | # Copyright 2008, Intel Corporation | 5 | # Copyright 2008, Intel Corporation |
| 4 | # | 6 | # |
| 5 | # This file is part of the Linux kernel | 7 | # This file is part of the Linux kernel |
| @@ -13,23 +15,41 @@ | |||
| 13 | 15 | ||
| 14 | 16 | ||
| 15 | my $vmlinux_name = $ARGV[0]; | 17 | my $vmlinux_name = $ARGV[0]; |
| 16 | 18 | if (!defined($vmlinux_name)) { | |
| 19 | my $kerver = `uname -r`; | ||
| 20 | chomp($kerver); | ||
| 21 | $vmlinux_name = "/lib/modules/$kerver/build/vmlinux"; | ||
| 22 | print "No vmlinux specified, assuming $vmlinux_name\n"; | ||
| 23 | } | ||
| 24 | my $filename = $vmlinux_name; | ||
| 17 | # | 25 | # |
| 18 | # Step 1: Parse the oops to find the EIP value | 26 | # Step 1: Parse the oops to find the EIP value |
| 19 | # | 27 | # |
| 20 | 28 | ||
| 21 | my $target = "0"; | 29 | my $target = "0"; |
| 30 | my $function; | ||
| 31 | my $module = ""; | ||
| 32 | my $func_offset; | ||
| 33 | my $vmaoffset = 0; | ||
| 34 | |||
| 22 | while (<STDIN>) { | 35 | while (<STDIN>) { |
| 23 | if ($_ =~ /EIP: 0060:\[\<([a-z0-9]+)\>\]/) { | 36 | my $line = $_; |
| 37 | if ($line =~ /EIP: 0060:\[\<([a-z0-9]+)\>\]/) { | ||
| 24 | $target = $1; | 38 | $target = $1; |
| 25 | } | 39 | } |
| 26 | } | 40 | if ($line =~ /EIP is at ([a-zA-Z0-9\_]+)\+(0x[0-9a-f]+)\/0x[a-f0-9]/) { |
| 41 | $function = $1; | ||
| 42 | $func_offset = $2; | ||
| 43 | } | ||
| 27 | 44 | ||
| 28 | if ($target =~ /^f8/) { | 45 | # check if it's a module |
| 29 | print "This script does not work on modules ... \n"; | 46 | if ($line =~ /EIP is at ([a-zA-Z0-9\_]+)\+(0x[0-9a-f]+)\/0x[a-f0-9]+\W\[([a-zA-Z0-9\_\-]+)\]/) { |
| 30 | exit; | 47 | $module = $3; |
| 48 | } | ||
| 31 | } | 49 | } |
| 32 | 50 | ||
| 51 | my $decodestart = hex($target) - hex($func_offset); | ||
| 52 | my $decodestop = $decodestart + 8192; | ||
| 33 | if ($target eq "0") { | 53 | if ($target eq "0") { |
| 34 | print "No oops found!\n"; | 54 | print "No oops found!\n"; |
| 35 | print "Usage: \n"; | 55 | print "Usage: \n"; |
| @@ -37,6 +57,29 @@ if ($target eq "0") { | |||
| 37 | exit; | 57 | exit; |
| 38 | } | 58 | } |
| 39 | 59 | ||
| 60 | # if it's a module, we need to find the .ko file and calculate a load offset | ||
| 61 | if ($module ne "") { | ||
| 62 | my $dir = dirname($filename); | ||
| 63 | $dir = $dir . "/"; | ||
| 64 | my $mod = $module . ".ko"; | ||
| 65 | my $modulefile = `find $dir -name $mod | head -1`; | ||
| 66 | chomp($modulefile); | ||
| 67 | $filename = $modulefile; | ||
| 68 | if ($filename eq "") { | ||
| 69 | print "Module .ko file for $module not found. Aborting\n"; | ||
| 70 | exit; | ||
| 71 | } | ||
| 72 | # ok so we found the module, now we need to calculate the vma offset | ||
| 73 | open(FILE, "objdump -dS $filename |") || die "Cannot start objdump"; | ||
| 74 | while (<FILE>) { | ||
| 75 | if ($_ =~ /^([0-9a-f]+) \<$function\>\:/) { | ||
| 76 | my $fu = $1; | ||
| 77 | $vmaoffset = hex($target) - hex($fu) - hex($func_offset); | ||
| 78 | } | ||
| 79 | } | ||
| 80 | close(FILE); | ||
| 81 | } | ||
| 82 | |||
| 40 | my $counter = 0; | 83 | my $counter = 0; |
| 41 | my $state = 0; | 84 | my $state = 0; |
| 42 | my $center = 0; | 85 | my $center = 0; |
| @@ -59,9 +102,7 @@ sub InRange { | |||
| 59 | # first, parse the input into the lines array, but to keep size down, | 102 | # first, parse the input into the lines array, but to keep size down, |
| 60 | # we only do this for 4Kb around the sweet spot | 103 | # we only do this for 4Kb around the sweet spot |
| 61 | 104 | ||
| 62 | my $filename; | 105 | open(FILE, "objdump -dS --adjust-vma=$vmaoffset --start-address=$decodestart --stop-address=$decodestop $filename |") || die "Cannot start objdump"; |
| 63 | |||
| 64 | open(FILE, "objdump -dS $vmlinux_name |") || die "Cannot start objdump"; | ||
| 65 | 106 | ||
| 66 | while (<FILE>) { | 107 | while (<FILE>) { |
| 67 | my $line = $_; | 108 | my $line = $_; |
diff --git a/sound/oss/dmasound/dmasound_atari.c b/sound/oss/dmasound/dmasound_atari.c index 4d45bd63718b..57d9f154c88b 100644 --- a/sound/oss/dmasound/dmasound_atari.c +++ b/sound/oss/dmasound/dmasound_atari.c | |||
| @@ -851,8 +851,9 @@ static int __init AtaIrqInit(void) | |||
| 851 | mfp.tim_dt_a = 1; /* Cause interrupt after first event. */ | 851 | mfp.tim_dt_a = 1; /* Cause interrupt after first event. */ |
| 852 | mfp.tim_ct_a = 8; /* Turn on event counting. */ | 852 | mfp.tim_ct_a = 8; /* Turn on event counting. */ |
| 853 | /* Register interrupt handler. */ | 853 | /* Register interrupt handler. */ |
| 854 | request_irq(IRQ_MFP_TIMA, AtaInterrupt, IRQ_TYPE_SLOW, "DMA sound", | 854 | if (request_irq(IRQ_MFP_TIMA, AtaInterrupt, IRQ_TYPE_SLOW, "DMA sound", |
| 855 | AtaInterrupt); | 855 | AtaInterrupt)) |
| 856 | return 0; | ||
| 856 | mfp.int_en_a |= 0x20; /* Turn interrupt on. */ | 857 | mfp.int_en_a |= 0x20; /* Turn interrupt on. */ |
| 857 | mfp.int_mk_a |= 0x20; | 858 | mfp.int_mk_a |= 0x20; |
| 858 | return 1; | 859 | return 1; |
diff --git a/sound/oss/dmasound/dmasound_q40.c b/sound/oss/dmasound/dmasound_q40.c index 1855b14d90c3..99bcb21c2281 100644 --- a/sound/oss/dmasound/dmasound_q40.c +++ b/sound/oss/dmasound/dmasound_q40.c | |||
| @@ -371,8 +371,9 @@ static void Q40Free(void *ptr, unsigned int size) | |||
| 371 | static int __init Q40IrqInit(void) | 371 | static int __init Q40IrqInit(void) |
| 372 | { | 372 | { |
| 373 | /* Register interrupt handler. */ | 373 | /* Register interrupt handler. */ |
| 374 | request_irq(Q40_IRQ_SAMPLE, Q40StereoInterrupt, 0, | 374 | if (request_irq(Q40_IRQ_SAMPLE, Q40StereoInterrupt, 0, |
| 375 | "DMA sound", Q40Interrupt); | 375 | "DMA sound", Q40Interrupt)) |
| 376 | return 0; | ||
| 376 | 377 | ||
| 377 | return(1); | 378 | return(1); |
| 378 | } | 379 | } |
| @@ -401,6 +402,7 @@ static void Q40PlayNextFrame(int index) | |||
| 401 | u_char *start; | 402 | u_char *start; |
| 402 | u_long size; | 403 | u_long size; |
| 403 | u_char speed; | 404 | u_char speed; |
| 405 | int error; | ||
| 404 | 406 | ||
| 405 | /* used by Q40Play() if all doubts whether there really is something | 407 | /* used by Q40Play() if all doubts whether there really is something |
| 406 | * to be played are already wiped out. | 408 | * to be played are already wiped out. |
| @@ -419,11 +421,13 @@ static void Q40PlayNextFrame(int index) | |||
| 419 | master_outb( 0,SAMPLE_ENABLE_REG); | 421 | master_outb( 0,SAMPLE_ENABLE_REG); |
| 420 | free_irq(Q40_IRQ_SAMPLE, Q40Interrupt); | 422 | free_irq(Q40_IRQ_SAMPLE, Q40Interrupt); |
| 421 | if (dmasound.soft.stereo) | 423 | if (dmasound.soft.stereo) |
| 422 | request_irq(Q40_IRQ_SAMPLE, Q40StereoInterrupt, 0, | 424 | error = request_irq(Q40_IRQ_SAMPLE, Q40StereoInterrupt, 0, |
| 423 | "Q40 sound", Q40Interrupt); | 425 | "Q40 sound", Q40Interrupt); |
| 424 | else | 426 | else |
| 425 | request_irq(Q40_IRQ_SAMPLE, Q40MonoInterrupt, 0, | 427 | error = request_irq(Q40_IRQ_SAMPLE, Q40MonoInterrupt, 0, |
| 426 | "Q40 sound", Q40Interrupt); | 428 | "Q40 sound", Q40Interrupt); |
| 429 | if (error && printk_ratelimit()) | ||
| 430 | pr_err("Couldn't register sound interrupt\n"); | ||
| 427 | 431 | ||
| 428 | master_outb( speed, SAMPLE_RATE_REG); | 432 | master_outb( speed, SAMPLE_RATE_REG); |
| 429 | master_outb( 1,SAMPLE_CLEAR_REG); | 433 | master_outb( 1,SAMPLE_CLEAR_REG); |
diff --git a/sound/pci/hda/hda_beep.c b/sound/pci/hda/hda_beep.c index e00421c0d8ba..960fd7970384 100644 --- a/sound/pci/hda/hda_beep.c +++ b/sound/pci/hda/hda_beep.c | |||
| @@ -135,7 +135,6 @@ void snd_hda_detach_beep_device(struct hda_codec *codec) | |||
| 135 | struct hda_beep *beep = codec->beep; | 135 | struct hda_beep *beep = codec->beep; |
| 136 | if (beep) { | 136 | if (beep) { |
| 137 | cancel_work_sync(&beep->beep_work); | 137 | cancel_work_sync(&beep->beep_work); |
| 138 | flush_scheduled_work(); | ||
| 139 | 138 | ||
| 140 | input_unregister_device(beep->dev); | 139 | input_unregister_device(beep->dev); |
| 141 | kfree(beep); | 140 | kfree(beep); |
diff --git a/sound/pci/hda/hda_codec.c b/sound/pci/hda/hda_codec.c index e16cf63821ae..3c596da2b9b5 100644 --- a/sound/pci/hda/hda_codec.c +++ b/sound/pci/hda/hda_codec.c | |||
| @@ -373,7 +373,7 @@ int snd_hda_queue_unsol_event(struct hda_bus *bus, u32 res, u32 res_ex) | |||
| 373 | unsol->queue[wp] = res; | 373 | unsol->queue[wp] = res; |
| 374 | unsol->queue[wp + 1] = res_ex; | 374 | unsol->queue[wp + 1] = res_ex; |
| 375 | 375 | ||
| 376 | schedule_work(&unsol->work); | 376 | queue_work(bus->workq, &unsol->work); |
| 377 | 377 | ||
| 378 | return 0; | 378 | return 0; |
| 379 | } | 379 | } |
| @@ -437,15 +437,17 @@ static int snd_hda_bus_free(struct hda_bus *bus) | |||
| 437 | 437 | ||
| 438 | if (!bus) | 438 | if (!bus) |
| 439 | return 0; | 439 | return 0; |
| 440 | if (bus->unsol) { | 440 | if (bus->workq) |
| 441 | flush_scheduled_work(); | 441 | flush_workqueue(bus->workq); |
| 442 | if (bus->unsol) | ||
| 442 | kfree(bus->unsol); | 443 | kfree(bus->unsol); |
| 443 | } | ||
| 444 | list_for_each_entry_safe(codec, n, &bus->codec_list, list) { | 444 | list_for_each_entry_safe(codec, n, &bus->codec_list, list) { |
| 445 | snd_hda_codec_free(codec); | 445 | snd_hda_codec_free(codec); |
| 446 | } | 446 | } |
| 447 | if (bus->ops.private_free) | 447 | if (bus->ops.private_free) |
| 448 | bus->ops.private_free(bus); | 448 | bus->ops.private_free(bus); |
| 449 | if (bus->workq) | ||
| 450 | destroy_workqueue(bus->workq); | ||
| 449 | kfree(bus); | 451 | kfree(bus); |
| 450 | return 0; | 452 | return 0; |
| 451 | } | 453 | } |
| @@ -485,6 +487,7 @@ int /*__devinit*/ snd_hda_bus_new(struct snd_card *card, | |||
| 485 | { | 487 | { |
| 486 | struct hda_bus *bus; | 488 | struct hda_bus *bus; |
| 487 | int err; | 489 | int err; |
| 490 | char qname[8]; | ||
| 488 | static struct snd_device_ops dev_ops = { | 491 | static struct snd_device_ops dev_ops = { |
| 489 | .dev_register = snd_hda_bus_dev_register, | 492 | .dev_register = snd_hda_bus_dev_register, |
| 490 | .dev_free = snd_hda_bus_dev_free, | 493 | .dev_free = snd_hda_bus_dev_free, |
| @@ -514,6 +517,14 @@ int /*__devinit*/ snd_hda_bus_new(struct snd_card *card, | |||
| 514 | mutex_init(&bus->cmd_mutex); | 517 | mutex_init(&bus->cmd_mutex); |
| 515 | INIT_LIST_HEAD(&bus->codec_list); | 518 | INIT_LIST_HEAD(&bus->codec_list); |
| 516 | 519 | ||
| 520 | snprintf(qname, sizeof(qname), "hda%d", card->number); | ||
| 521 | bus->workq = create_workqueue(qname); | ||
| 522 | if (!bus->workq) { | ||
| 523 | snd_printk(KERN_ERR "cannot create workqueue %s\n", qname); | ||
| 524 | kfree(bus); | ||
| 525 | return -ENOMEM; | ||
| 526 | } | ||
| 527 | |||
| 517 | err = snd_device_new(card, SNDRV_DEV_BUS, bus, &dev_ops); | 528 | err = snd_device_new(card, SNDRV_DEV_BUS, bus, &dev_ops); |
| 518 | if (err < 0) { | 529 | if (err < 0) { |
| 519 | snd_hda_bus_free(bus); | 530 | snd_hda_bus_free(bus); |
| @@ -684,7 +695,7 @@ static void snd_hda_codec_free(struct hda_codec *codec) | |||
| 684 | return; | 695 | return; |
| 685 | #ifdef CONFIG_SND_HDA_POWER_SAVE | 696 | #ifdef CONFIG_SND_HDA_POWER_SAVE |
| 686 | cancel_delayed_work(&codec->power_work); | 697 | cancel_delayed_work(&codec->power_work); |
| 687 | flush_scheduled_work(); | 698 | flush_workqueue(codec->bus->workq); |
| 688 | #endif | 699 | #endif |
| 689 | list_del(&codec->list); | 700 | list_del(&codec->list); |
| 690 | snd_array_free(&codec->mixers); | 701 | snd_array_free(&codec->mixers); |
| @@ -735,6 +746,7 @@ int /*__devinit*/ snd_hda_codec_new(struct hda_bus *bus, unsigned int codec_addr | |||
| 735 | codec->bus = bus; | 746 | codec->bus = bus; |
| 736 | codec->addr = codec_addr; | 747 | codec->addr = codec_addr; |
| 737 | mutex_init(&codec->spdif_mutex); | 748 | mutex_init(&codec->spdif_mutex); |
| 749 | mutex_init(&codec->control_mutex); | ||
| 738 | init_hda_cache(&codec->amp_cache, sizeof(struct hda_amp_info)); | 750 | init_hda_cache(&codec->amp_cache, sizeof(struct hda_amp_info)); |
| 739 | init_hda_cache(&codec->cmd_cache, sizeof(struct hda_cache_head)); | 751 | init_hda_cache(&codec->cmd_cache, sizeof(struct hda_cache_head)); |
| 740 | snd_array_init(&codec->mixers, sizeof(struct snd_kcontrol *), 32); | 752 | snd_array_init(&codec->mixers, sizeof(struct snd_kcontrol *), 32); |
| @@ -1272,7 +1284,7 @@ void snd_hda_codec_reset(struct hda_codec *codec) | |||
| 1272 | 1284 | ||
| 1273 | #ifdef CONFIG_SND_HDA_POWER_SAVE | 1285 | #ifdef CONFIG_SND_HDA_POWER_SAVE |
| 1274 | cancel_delayed_work(&codec->power_work); | 1286 | cancel_delayed_work(&codec->power_work); |
| 1275 | flush_scheduled_work(); | 1287 | flush_workqueue(codec->bus->workq); |
| 1276 | #endif | 1288 | #endif |
| 1277 | snd_hda_ctls_clear(codec); | 1289 | snd_hda_ctls_clear(codec); |
| 1278 | /* relase PCMs */ | 1290 | /* relase PCMs */ |
| @@ -1418,12 +1430,12 @@ int snd_hda_mixer_bind_switch_get(struct snd_kcontrol *kcontrol, | |||
| 1418 | unsigned long pval; | 1430 | unsigned long pval; |
| 1419 | int err; | 1431 | int err; |
| 1420 | 1432 | ||
| 1421 | mutex_lock(&codec->spdif_mutex); /* reuse spdif_mutex */ | 1433 | mutex_lock(&codec->control_mutex); |
| 1422 | pval = kcontrol->private_value; | 1434 | pval = kcontrol->private_value; |
| 1423 | kcontrol->private_value = pval & ~AMP_VAL_IDX_MASK; /* index 0 */ | 1435 | kcontrol->private_value = pval & ~AMP_VAL_IDX_MASK; /* index 0 */ |
| 1424 | err = snd_hda_mixer_amp_switch_get(kcontrol, ucontrol); | 1436 | err = snd_hda_mixer_amp_switch_get(kcontrol, ucontrol); |
| 1425 | kcontrol->private_value = pval; | 1437 | kcontrol->private_value = pval; |
| 1426 | mutex_unlock(&codec->spdif_mutex); | 1438 | mutex_unlock(&codec->control_mutex); |
| 1427 | return err; | 1439 | return err; |
| 1428 | } | 1440 | } |
| 1429 | EXPORT_SYMBOL_HDA(snd_hda_mixer_bind_switch_get); | 1441 | EXPORT_SYMBOL_HDA(snd_hda_mixer_bind_switch_get); |
| @@ -1435,7 +1447,7 @@ int snd_hda_mixer_bind_switch_put(struct snd_kcontrol *kcontrol, | |||
| 1435 | unsigned long pval; | 1447 | unsigned long pval; |
| 1436 | int i, indices, err = 0, change = 0; | 1448 | int i, indices, err = 0, change = 0; |
| 1437 | 1449 | ||
| 1438 | mutex_lock(&codec->spdif_mutex); /* reuse spdif_mutex */ | 1450 | mutex_lock(&codec->control_mutex); |
| 1439 | pval = kcontrol->private_value; | 1451 | pval = kcontrol->private_value; |
| 1440 | indices = (pval & AMP_VAL_IDX_MASK) >> AMP_VAL_IDX_SHIFT; | 1452 | indices = (pval & AMP_VAL_IDX_MASK) >> AMP_VAL_IDX_SHIFT; |
| 1441 | for (i = 0; i < indices; i++) { | 1453 | for (i = 0; i < indices; i++) { |
| @@ -1447,7 +1459,7 @@ int snd_hda_mixer_bind_switch_put(struct snd_kcontrol *kcontrol, | |||
| 1447 | change |= err; | 1459 | change |= err; |
| 1448 | } | 1460 | } |
| 1449 | kcontrol->private_value = pval; | 1461 | kcontrol->private_value = pval; |
| 1450 | mutex_unlock(&codec->spdif_mutex); | 1462 | mutex_unlock(&codec->control_mutex); |
| 1451 | return err < 0 ? err : change; | 1463 | return err < 0 ? err : change; |
| 1452 | } | 1464 | } |
| 1453 | EXPORT_SYMBOL_HDA(snd_hda_mixer_bind_switch_put); | 1465 | EXPORT_SYMBOL_HDA(snd_hda_mixer_bind_switch_put); |
| @@ -1462,12 +1474,12 @@ int snd_hda_mixer_bind_ctls_info(struct snd_kcontrol *kcontrol, | |||
| 1462 | struct hda_bind_ctls *c; | 1474 | struct hda_bind_ctls *c; |
| 1463 | int err; | 1475 | int err; |
| 1464 | 1476 | ||
| 1465 | mutex_lock(&codec->spdif_mutex); /* reuse spdif_mutex */ | 1477 | mutex_lock(&codec->control_mutex); |
| 1466 | c = (struct hda_bind_ctls *)kcontrol->private_value; | 1478 | c = (struct hda_bind_ctls *)kcontrol->private_value; |
| 1467 | kcontrol->private_value = *c->values; | 1479 | kcontrol->private_value = *c->values; |
| 1468 | err = c->ops->info(kcontrol, uinfo); | 1480 | err = c->ops->info(kcontrol, uinfo); |
| 1469 | kcontrol->private_value = (long)c; | 1481 | kcontrol->private_value = (long)c; |
| 1470 | mutex_unlock(&codec->spdif_mutex); | 1482 | mutex_unlock(&codec->control_mutex); |
| 1471 | return err; | 1483 | return err; |
| 1472 | } | 1484 | } |
| 1473 | EXPORT_SYMBOL_HDA(snd_hda_mixer_bind_ctls_info); | 1485 | EXPORT_SYMBOL_HDA(snd_hda_mixer_bind_ctls_info); |
| @@ -1479,12 +1491,12 @@ int snd_hda_mixer_bind_ctls_get(struct snd_kcontrol *kcontrol, | |||
| 1479 | struct hda_bind_ctls *c; | 1491 | struct hda_bind_ctls *c; |
| 1480 | int err; | 1492 | int err; |
| 1481 | 1493 | ||
| 1482 | mutex_lock(&codec->spdif_mutex); /* reuse spdif_mutex */ | 1494 | mutex_lock(&codec->control_mutex); |
| 1483 | c = (struct hda_bind_ctls *)kcontrol->private_value; | 1495 | c = (struct hda_bind_ctls *)kcontrol->private_value; |
| 1484 | kcontrol->private_value = *c->values; | 1496 | kcontrol->private_value = *c->values; |
| 1485 | err = c->ops->get(kcontrol, ucontrol); | 1497 | err = c->ops->get(kcontrol, ucontrol); |
| 1486 | kcontrol->private_value = (long)c; | 1498 | kcontrol->private_value = (long)c; |
| 1487 | mutex_unlock(&codec->spdif_mutex); | 1499 | mutex_unlock(&codec->control_mutex); |
| 1488 | return err; | 1500 | return err; |
| 1489 | } | 1501 | } |
| 1490 | EXPORT_SYMBOL_HDA(snd_hda_mixer_bind_ctls_get); | 1502 | EXPORT_SYMBOL_HDA(snd_hda_mixer_bind_ctls_get); |
| @@ -1497,7 +1509,7 @@ int snd_hda_mixer_bind_ctls_put(struct snd_kcontrol *kcontrol, | |||
| 1497 | unsigned long *vals; | 1509 | unsigned long *vals; |
| 1498 | int err = 0, change = 0; | 1510 | int err = 0, change = 0; |
| 1499 | 1511 | ||
| 1500 | mutex_lock(&codec->spdif_mutex); /* reuse spdif_mutex */ | 1512 | mutex_lock(&codec->control_mutex); |
| 1501 | c = (struct hda_bind_ctls *)kcontrol->private_value; | 1513 | c = (struct hda_bind_ctls *)kcontrol->private_value; |
| 1502 | for (vals = c->values; *vals; vals++) { | 1514 | for (vals = c->values; *vals; vals++) { |
| 1503 | kcontrol->private_value = *vals; | 1515 | kcontrol->private_value = *vals; |
| @@ -1507,7 +1519,7 @@ int snd_hda_mixer_bind_ctls_put(struct snd_kcontrol *kcontrol, | |||
| 1507 | change |= err; | 1519 | change |= err; |
| 1508 | } | 1520 | } |
| 1509 | kcontrol->private_value = (long)c; | 1521 | kcontrol->private_value = (long)c; |
| 1510 | mutex_unlock(&codec->spdif_mutex); | 1522 | mutex_unlock(&codec->control_mutex); |
| 1511 | return err < 0 ? err : change; | 1523 | return err < 0 ? err : change; |
| 1512 | } | 1524 | } |
| 1513 | EXPORT_SYMBOL_HDA(snd_hda_mixer_bind_ctls_put); | 1525 | EXPORT_SYMBOL_HDA(snd_hda_mixer_bind_ctls_put); |
| @@ -1519,12 +1531,12 @@ int snd_hda_mixer_bind_tlv(struct snd_kcontrol *kcontrol, int op_flag, | |||
| 1519 | struct hda_bind_ctls *c; | 1531 | struct hda_bind_ctls *c; |
| 1520 | int err; | 1532 | int err; |
| 1521 | 1533 | ||
| 1522 | mutex_lock(&codec->spdif_mutex); /* reuse spdif_mutex */ | 1534 | mutex_lock(&codec->control_mutex); |
| 1523 | c = (struct hda_bind_ctls *)kcontrol->private_value; | 1535 | c = (struct hda_bind_ctls *)kcontrol->private_value; |
| 1524 | kcontrol->private_value = *c->values; | 1536 | kcontrol->private_value = *c->values; |
| 1525 | err = c->ops->tlv(kcontrol, op_flag, size, tlv); | 1537 | err = c->ops->tlv(kcontrol, op_flag, size, tlv); |
| 1526 | kcontrol->private_value = (long)c; | 1538 | kcontrol->private_value = (long)c; |
| 1527 | mutex_unlock(&codec->spdif_mutex); | 1539 | mutex_unlock(&codec->control_mutex); |
| 1528 | return err; | 1540 | return err; |
| 1529 | } | 1541 | } |
| 1530 | EXPORT_SYMBOL_HDA(snd_hda_mixer_bind_tlv); | 1542 | EXPORT_SYMBOL_HDA(snd_hda_mixer_bind_tlv); |
diff --git a/sound/pci/hda/hda_codec.h b/sound/pci/hda/hda_codec.h index 729fc7642d7f..5810ef588402 100644 --- a/sound/pci/hda/hda_codec.h +++ b/sound/pci/hda/hda_codec.h | |||
| @@ -614,6 +614,7 @@ struct hda_bus { | |||
| 614 | 614 | ||
| 615 | /* unsolicited event queue */ | 615 | /* unsolicited event queue */ |
| 616 | struct hda_bus_unsolicited *unsol; | 616 | struct hda_bus_unsolicited *unsol; |
| 617 | struct workqueue_struct *workq; /* common workqueue for codecs */ | ||
| 617 | 618 | ||
| 618 | /* assigned PCMs */ | 619 | /* assigned PCMs */ |
| 619 | DECLARE_BITMAP(pcm_dev_bits, SNDRV_PCM_DEVICES); | 620 | DECLARE_BITMAP(pcm_dev_bits, SNDRV_PCM_DEVICES); |
| @@ -771,6 +772,7 @@ struct hda_codec { | |||
| 771 | struct hda_cache_rec cmd_cache; /* cache for other commands */ | 772 | struct hda_cache_rec cmd_cache; /* cache for other commands */ |
| 772 | 773 | ||
| 773 | struct mutex spdif_mutex; | 774 | struct mutex spdif_mutex; |
| 775 | struct mutex control_mutex; | ||
| 774 | unsigned int spdif_status; /* IEC958 status bits */ | 776 | unsigned int spdif_status; /* IEC958 status bits */ |
| 775 | unsigned short spdif_ctls; /* SPDIF control bits */ | 777 | unsigned short spdif_ctls; /* SPDIF control bits */ |
| 776 | unsigned int spdif_in_enable; /* SPDIF input enable? */ | 778 | unsigned int spdif_in_enable; /* SPDIF input enable? */ |
diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c index f04de115ee11..11e791b965f6 100644 --- a/sound/pci/hda/hda_intel.c +++ b/sound/pci/hda/hda_intel.c | |||
| @@ -996,10 +996,11 @@ static irqreturn_t azx_interrupt(int irq, void *dev_id) | |||
| 996 | spin_unlock(&chip->reg_lock); | 996 | spin_unlock(&chip->reg_lock); |
| 997 | snd_pcm_period_elapsed(azx_dev->substream); | 997 | snd_pcm_period_elapsed(azx_dev->substream); |
| 998 | spin_lock(&chip->reg_lock); | 998 | spin_lock(&chip->reg_lock); |
| 999 | } else { | 999 | } else if (chip->bus && chip->bus->workq) { |
| 1000 | /* bogus IRQ, process it later */ | 1000 | /* bogus IRQ, process it later */ |
| 1001 | azx_dev->irq_pending = 1; | 1001 | azx_dev->irq_pending = 1; |
| 1002 | schedule_work(&chip->irq_pending_work); | 1002 | queue_work(chip->bus->workq, |
| 1003 | &chip->irq_pending_work); | ||
| 1003 | } | 1004 | } |
| 1004 | } | 1005 | } |
| 1005 | } | 1006 | } |
| @@ -1741,7 +1742,6 @@ static void azx_clear_irq_pending(struct azx *chip) | |||
| 1741 | for (i = 0; i < chip->num_streams; i++) | 1742 | for (i = 0; i < chip->num_streams; i++) |
| 1742 | chip->azx_dev[i].irq_pending = 0; | 1743 | chip->azx_dev[i].irq_pending = 0; |
| 1743 | spin_unlock_irq(&chip->reg_lock); | 1744 | spin_unlock_irq(&chip->reg_lock); |
| 1744 | flush_scheduled_work(); | ||
| 1745 | } | 1745 | } |
| 1746 | 1746 | ||
| 1747 | static struct snd_pcm_ops azx_pcm_ops = { | 1747 | static struct snd_pcm_ops azx_pcm_ops = { |
diff --git a/sound/pci/hda/patch_analog.c b/sound/pci/hda/patch_analog.c index 26247cfe749d..2e7371ec2e23 100644 --- a/sound/pci/hda/patch_analog.c +++ b/sound/pci/hda/patch_analog.c | |||
| @@ -3900,6 +3900,7 @@ static const char *ad1884a_models[AD1884A_MODELS] = { | |||
| 3900 | 3900 | ||
| 3901 | static struct snd_pci_quirk ad1884a_cfg_tbl[] = { | 3901 | static struct snd_pci_quirk ad1884a_cfg_tbl[] = { |
| 3902 | SND_PCI_QUIRK(0x103c, 0x3030, "HP", AD1884A_MOBILE), | 3902 | SND_PCI_QUIRK(0x103c, 0x3030, "HP", AD1884A_MOBILE), |
| 3903 | SND_PCI_QUIRK(0x103c, 0x3037, "HP 2230s", AD1884A_LAPTOP), | ||
| 3903 | SND_PCI_QUIRK(0x103c, 0x3056, "HP", AD1884A_MOBILE), | 3904 | SND_PCI_QUIRK(0x103c, 0x3056, "HP", AD1884A_MOBILE), |
| 3904 | SND_PCI_QUIRK(0x103c, 0x30e6, "HP 6730b", AD1884A_LAPTOP), | 3905 | SND_PCI_QUIRK(0x103c, 0x30e6, "HP 6730b", AD1884A_LAPTOP), |
| 3905 | SND_PCI_QUIRK(0x103c, 0x30e7, "HP EliteBook 8530p", AD1884A_LAPTOP), | 3906 | SND_PCI_QUIRK(0x103c, 0x30e7, "HP EliteBook 8530p", AD1884A_LAPTOP), |
| @@ -4262,13 +4263,13 @@ static int patch_ad1882(struct hda_codec *codec) | |||
| 4262 | spec->num_adc_nids = ARRAY_SIZE(ad1882_adc_nids); | 4263 | spec->num_adc_nids = ARRAY_SIZE(ad1882_adc_nids); |
| 4263 | spec->adc_nids = ad1882_adc_nids; | 4264 | spec->adc_nids = ad1882_adc_nids; |
| 4264 | spec->capsrc_nids = ad1882_capsrc_nids; | 4265 | spec->capsrc_nids = ad1882_capsrc_nids; |
| 4265 | if (codec->vendor_id == 0x11d1882) | 4266 | if (codec->vendor_id == 0x11d41882) |
| 4266 | spec->input_mux = &ad1882_capture_source; | 4267 | spec->input_mux = &ad1882_capture_source; |
| 4267 | else | 4268 | else |
| 4268 | spec->input_mux = &ad1882a_capture_source; | 4269 | spec->input_mux = &ad1882a_capture_source; |
| 4269 | spec->num_mixers = 2; | 4270 | spec->num_mixers = 2; |
| 4270 | spec->mixers[0] = ad1882_base_mixers; | 4271 | spec->mixers[0] = ad1882_base_mixers; |
| 4271 | if (codec->vendor_id == 0x11d1882) | 4272 | if (codec->vendor_id == 0x11d41882) |
| 4272 | spec->mixers[1] = ad1882_loopback_mixers; | 4273 | spec->mixers[1] = ad1882_loopback_mixers; |
| 4273 | else | 4274 | else |
| 4274 | spec->mixers[1] = ad1882a_loopback_mixers; | 4275 | spec->mixers[1] = ad1882a_loopback_mixers; |
diff --git a/sound/pci/hda/patch_nvhdmi.c b/sound/pci/hda/patch_nvhdmi.c index 0270fda0bda5..96952a37d884 100644 --- a/sound/pci/hda/patch_nvhdmi.c +++ b/sound/pci/hda/patch_nvhdmi.c | |||
| @@ -162,12 +162,14 @@ static struct hda_codec_preset snd_hda_preset_nvhdmi[] = { | |||
| 162 | { .id = 0x10de0002, .name = "MCP78 HDMI", .patch = patch_nvhdmi }, | 162 | { .id = 0x10de0002, .name = "MCP78 HDMI", .patch = patch_nvhdmi }, |
| 163 | { .id = 0x10de0007, .name = "MCP7A HDMI", .patch = patch_nvhdmi }, | 163 | { .id = 0x10de0007, .name = "MCP7A HDMI", .patch = patch_nvhdmi }, |
| 164 | { .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi }, | 164 | { .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi }, |
| 165 | { .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi }, | ||
| 165 | {} /* terminator */ | 166 | {} /* terminator */ |
| 166 | }; | 167 | }; |
| 167 | 168 | ||
| 168 | MODULE_ALIAS("snd-hda-codec-id:10de0002"); | 169 | MODULE_ALIAS("snd-hda-codec-id:10de0002"); |
| 169 | MODULE_ALIAS("snd-hda-codec-id:10de0007"); | 170 | MODULE_ALIAS("snd-hda-codec-id:10de0007"); |
| 170 | MODULE_ALIAS("snd-hda-codec-id:10de0067"); | 171 | MODULE_ALIAS("snd-hda-codec-id:10de0067"); |
| 172 | MODULE_ALIAS("snd-hda-codec-id:10de8001"); | ||
| 171 | 173 | ||
| 172 | MODULE_LICENSE("GPL"); | 174 | MODULE_LICENSE("GPL"); |
| 173 | MODULE_DESCRIPTION("Nvidia HDMI HD-audio codec"); | 175 | MODULE_DESCRIPTION("Nvidia HDMI HD-audio codec"); |
diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c index 9065ebf9c065..ea4c88fe05c4 100644 --- a/sound/pci/hda/patch_realtek.c +++ b/sound/pci/hda/patch_realtek.c | |||
| @@ -1502,11 +1502,11 @@ static int alc_cap_vol_info(struct snd_kcontrol *kcontrol, | |||
| 1502 | struct alc_spec *spec = codec->spec; | 1502 | struct alc_spec *spec = codec->spec; |
| 1503 | int err; | 1503 | int err; |
| 1504 | 1504 | ||
| 1505 | mutex_lock(&codec->spdif_mutex); /* reuse spdif_mutex */ | 1505 | mutex_lock(&codec->control_mutex); |
| 1506 | kcontrol->private_value = HDA_COMPOSE_AMP_VAL(spec->adc_nids[0], 3, 0, | 1506 | kcontrol->private_value = HDA_COMPOSE_AMP_VAL(spec->adc_nids[0], 3, 0, |
| 1507 | HDA_INPUT); | 1507 | HDA_INPUT); |
| 1508 | err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); | 1508 | err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); |
| 1509 | mutex_unlock(&codec->spdif_mutex); /* reuse spdif_mutex */ | 1509 | mutex_unlock(&codec->control_mutex); |
| 1510 | return err; | 1510 | return err; |
| 1511 | } | 1511 | } |
| 1512 | 1512 | ||
| @@ -1517,11 +1517,11 @@ static int alc_cap_vol_tlv(struct snd_kcontrol *kcontrol, int op_flag, | |||
| 1517 | struct alc_spec *spec = codec->spec; | 1517 | struct alc_spec *spec = codec->spec; |
| 1518 | int err; | 1518 | int err; |
| 1519 | 1519 | ||
| 1520 | mutex_lock(&codec->spdif_mutex); /* reuse spdif_mutex */ | 1520 | mutex_lock(&codec->control_mutex); |
| 1521 | kcontrol->private_value = HDA_COMPOSE_AMP_VAL(spec->adc_nids[0], 3, 0, | 1521 | kcontrol->private_value = HDA_COMPOSE_AMP_VAL(spec->adc_nids[0], 3, 0, |
| 1522 | HDA_INPUT); | 1522 | HDA_INPUT); |
| 1523 | err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); | 1523 | err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); |
| 1524 | mutex_unlock(&codec->spdif_mutex); /* reuse spdif_mutex */ | 1524 | mutex_unlock(&codec->control_mutex); |
| 1525 | return err; | 1525 | return err; |
| 1526 | } | 1526 | } |
| 1527 | 1527 | ||
| @@ -1537,11 +1537,11 @@ static int alc_cap_getput_caller(struct snd_kcontrol *kcontrol, | |||
| 1537 | unsigned int adc_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); | 1537 | unsigned int adc_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); |
| 1538 | int err; | 1538 | int err; |
| 1539 | 1539 | ||
| 1540 | mutex_lock(&codec->spdif_mutex); /* reuse spdif_mutex */ | 1540 | mutex_lock(&codec->control_mutex); |
| 1541 | kcontrol->private_value = HDA_COMPOSE_AMP_VAL(spec->adc_nids[adc_idx], | 1541 | kcontrol->private_value = HDA_COMPOSE_AMP_VAL(spec->adc_nids[adc_idx], |
| 1542 | 3, 0, HDA_INPUT); | 1542 | 3, 0, HDA_INPUT); |
| 1543 | err = func(kcontrol, ucontrol); | 1543 | err = func(kcontrol, ucontrol); |
| 1544 | mutex_unlock(&codec->spdif_mutex); /* reuse spdif_mutex */ | 1544 | mutex_unlock(&codec->control_mutex); |
| 1545 | return err; | 1545 | return err; |
| 1546 | } | 1546 | } |
| 1547 | 1547 | ||
| @@ -8461,6 +8461,10 @@ static struct snd_pci_quirk alc883_cfg_tbl[] = { | |||
| 8461 | SND_PCI_QUIRK(0x1025, 0x0121, "Acer Aspire 5920G", ALC883_ACER_ASPIRE), | 8461 | SND_PCI_QUIRK(0x1025, 0x0121, "Acer Aspire 5920G", ALC883_ACER_ASPIRE), |
| 8462 | SND_PCI_QUIRK(0x1025, 0x013e, "Acer Aspire 4930G", | 8462 | SND_PCI_QUIRK(0x1025, 0x013e, "Acer Aspire 4930G", |
| 8463 | ALC888_ACER_ASPIRE_4930G), | 8463 | ALC888_ACER_ASPIRE_4930G), |
| 8464 | SND_PCI_QUIRK(0x1025, 0x013f, "Acer Aspire 5930G", | ||
| 8465 | ALC888_ACER_ASPIRE_4930G), | ||
| 8466 | SND_PCI_QUIRK(0x1025, 0x015e, "Acer Aspire 6930G", | ||
| 8467 | ALC888_ACER_ASPIRE_4930G), | ||
| 8464 | SND_PCI_QUIRK(0x1025, 0, "Acer laptop", ALC883_ACER), /* default Acer */ | 8468 | SND_PCI_QUIRK(0x1025, 0, "Acer laptop", ALC883_ACER), /* default Acer */ |
| 8465 | SND_PCI_QUIRK(0x1028, 0x020d, "Dell Inspiron 530", ALC888_6ST_DELL), | 8469 | SND_PCI_QUIRK(0x1028, 0x020d, "Dell Inspiron 530", ALC888_6ST_DELL), |
| 8466 | SND_PCI_QUIRK(0x103c, 0x2a3d, "HP Pavillion", ALC883_6ST_DIG), | 8470 | SND_PCI_QUIRK(0x103c, 0x2a3d, "HP Pavillion", ALC883_6ST_DIG), |
| @@ -8522,6 +8526,7 @@ static struct snd_pci_quirk alc883_cfg_tbl[] = { | |||
| 8522 | SND_PCI_QUIRK(0x1991, 0x5625, "Haier W66", ALC883_HAIER_W66), | 8526 | SND_PCI_QUIRK(0x1991, 0x5625, "Haier W66", ALC883_HAIER_W66), |
| 8523 | SND_PCI_QUIRK(0x8086, 0x0001, "DG33BUC", ALC883_3ST_6ch_INTEL), | 8527 | SND_PCI_QUIRK(0x8086, 0x0001, "DG33BUC", ALC883_3ST_6ch_INTEL), |
| 8524 | SND_PCI_QUIRK(0x8086, 0x0002, "DG33FBC", ALC883_3ST_6ch_INTEL), | 8528 | SND_PCI_QUIRK(0x8086, 0x0002, "DG33FBC", ALC883_3ST_6ch_INTEL), |
| 8529 | SND_PCI_QUIRK(0x8086, 0x0022, "DX58SO", ALC883_3ST_6ch_INTEL), | ||
| 8525 | SND_PCI_QUIRK(0x8086, 0xd601, "D102GGC", ALC883_3ST_6ch), | 8530 | SND_PCI_QUIRK(0x8086, 0xd601, "D102GGC", ALC883_3ST_6ch), |
| 8526 | {} | 8531 | {} |
| 8527 | }; | 8532 | }; |
| @@ -11689,6 +11694,7 @@ static struct snd_pci_quirk alc268_cfg_tbl[] = { | |||
| 11689 | SND_PCI_QUIRK(0x1025, 0x015b, "Acer Aspire One", | 11694 | SND_PCI_QUIRK(0x1025, 0x015b, "Acer Aspire One", |
| 11690 | ALC268_ACER_ASPIRE_ONE), | 11695 | ALC268_ACER_ASPIRE_ONE), |
| 11691 | SND_PCI_QUIRK(0x1028, 0x0253, "Dell OEM", ALC268_DELL), | 11696 | SND_PCI_QUIRK(0x1028, 0x0253, "Dell OEM", ALC268_DELL), |
| 11697 | SND_PCI_QUIRK(0x1028, 0x02b0, "Dell Inspiron Mini9", ALC268_DELL), | ||
| 11692 | SND_PCI_QUIRK(0x103c, 0x30cc, "TOSHIBA", ALC268_TOSHIBA), | 11698 | SND_PCI_QUIRK(0x103c, 0x30cc, "TOSHIBA", ALC268_TOSHIBA), |
| 11693 | SND_PCI_QUIRK(0x1043, 0x1205, "ASUS W7J", ALC268_3ST), | 11699 | SND_PCI_QUIRK(0x1043, 0x1205, "ASUS W7J", ALC268_3ST), |
| 11694 | SND_PCI_QUIRK(0x1179, 0xff10, "TOSHIBA A205", ALC268_TOSHIBA), | 11700 | SND_PCI_QUIRK(0x1179, 0xff10, "TOSHIBA A205", ALC268_TOSHIBA), |
diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c index fd0f338374a7..ea370a4f86d5 100644 --- a/sound/soc/codecs/twl4030.c +++ b/sound/soc/codecs/twl4030.c | |||
| @@ -197,7 +197,7 @@ static const char *twl4030_earpiece_texts[] = | |||
| 197 | static const unsigned int twl4030_earpiece_values[] = | 197 | static const unsigned int twl4030_earpiece_values[] = |
| 198 | {0x0, 0x1, 0x2, 0x4}; | 198 | {0x0, 0x1, 0x2, 0x4}; |
| 199 | 199 | ||
| 200 | static const struct soc_value_enum twl4030_earpiece_enum = | 200 | static const struct soc_enum twl4030_earpiece_enum = |
| 201 | SOC_VALUE_ENUM_SINGLE(TWL4030_REG_EAR_CTL, 1, 0x7, | 201 | SOC_VALUE_ENUM_SINGLE(TWL4030_REG_EAR_CTL, 1, 0x7, |
| 202 | ARRAY_SIZE(twl4030_earpiece_texts), | 202 | ARRAY_SIZE(twl4030_earpiece_texts), |
| 203 | twl4030_earpiece_texts, | 203 | twl4030_earpiece_texts, |
| @@ -213,7 +213,7 @@ static const char *twl4030_predrivel_texts[] = | |||
| 213 | static const unsigned int twl4030_predrivel_values[] = | 213 | static const unsigned int twl4030_predrivel_values[] = |
| 214 | {0x0, 0x1, 0x2, 0x4}; | 214 | {0x0, 0x1, 0x2, 0x4}; |
| 215 | 215 | ||
| 216 | static const struct soc_value_enum twl4030_predrivel_enum = | 216 | static const struct soc_enum twl4030_predrivel_enum = |
| 217 | SOC_VALUE_ENUM_SINGLE(TWL4030_REG_PREDL_CTL, 1, 0x7, | 217 | SOC_VALUE_ENUM_SINGLE(TWL4030_REG_PREDL_CTL, 1, 0x7, |
| 218 | ARRAY_SIZE(twl4030_predrivel_texts), | 218 | ARRAY_SIZE(twl4030_predrivel_texts), |
| 219 | twl4030_predrivel_texts, | 219 | twl4030_predrivel_texts, |
| @@ -229,7 +229,7 @@ static const char *twl4030_predriver_texts[] = | |||
| 229 | static const unsigned int twl4030_predriver_values[] = | 229 | static const unsigned int twl4030_predriver_values[] = |
| 230 | {0x0, 0x1, 0x2, 0x4}; | 230 | {0x0, 0x1, 0x2, 0x4}; |
| 231 | 231 | ||
| 232 | static const struct soc_value_enum twl4030_predriver_enum = | 232 | static const struct soc_enum twl4030_predriver_enum = |
| 233 | SOC_VALUE_ENUM_SINGLE(TWL4030_REG_PREDR_CTL, 1, 0x7, | 233 | SOC_VALUE_ENUM_SINGLE(TWL4030_REG_PREDR_CTL, 1, 0x7, |
| 234 | ARRAY_SIZE(twl4030_predriver_texts), | 234 | ARRAY_SIZE(twl4030_predriver_texts), |
| 235 | twl4030_predriver_texts, | 235 | twl4030_predriver_texts, |
| @@ -317,7 +317,7 @@ static const char *twl4030_analoglmic_texts[] = | |||
| 317 | static const unsigned int twl4030_analoglmic_values[] = | 317 | static const unsigned int twl4030_analoglmic_values[] = |
| 318 | {0x0, 0x1, 0x2, 0x4, 0x8}; | 318 | {0x0, 0x1, 0x2, 0x4, 0x8}; |
| 319 | 319 | ||
| 320 | static const struct soc_value_enum twl4030_analoglmic_enum = | 320 | static const struct soc_enum twl4030_analoglmic_enum = |
| 321 | SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICL, 0, 0xf, | 321 | SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICL, 0, 0xf, |
| 322 | ARRAY_SIZE(twl4030_analoglmic_texts), | 322 | ARRAY_SIZE(twl4030_analoglmic_texts), |
| 323 | twl4030_analoglmic_texts, | 323 | twl4030_analoglmic_texts, |
| @@ -333,7 +333,7 @@ static const char *twl4030_analogrmic_texts[] = | |||
| 333 | static const unsigned int twl4030_analogrmic_values[] = | 333 | static const unsigned int twl4030_analogrmic_values[] = |
| 334 | {0x0, 0x1, 0x4}; | 334 | {0x0, 0x1, 0x4}; |
| 335 | 335 | ||
| 336 | static const struct soc_value_enum twl4030_analogrmic_enum = | 336 | static const struct soc_enum twl4030_analogrmic_enum = |
| 337 | SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICR, 0, 0x5, | 337 | SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICR, 0, 0x5, |
| 338 | ARRAY_SIZE(twl4030_analogrmic_texts), | 338 | ARRAY_SIZE(twl4030_analogrmic_texts), |
| 339 | twl4030_analogrmic_texts, | 339 | twl4030_analogrmic_texts, |
| @@ -1280,6 +1280,8 @@ static int twl4030_remove(struct platform_device *pdev) | |||
| 1280 | struct snd_soc_codec *codec = socdev->codec; | 1280 | struct snd_soc_codec *codec = socdev->codec; |
| 1281 | 1281 | ||
| 1282 | printk(KERN_INFO "TWL4030 Audio Codec remove\n"); | 1282 | printk(KERN_INFO "TWL4030 Audio Codec remove\n"); |
| 1283 | snd_soc_free_pcms(socdev); | ||
| 1284 | snd_soc_dapm_free(socdev); | ||
| 1283 | kfree(codec); | 1285 | kfree(codec); |
| 1284 | 1286 | ||
| 1285 | return 0; | 1287 | return 0; |
diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c index 6cbe7e82f238..55fdb4abb179 100644 --- a/sound/soc/soc-core.c +++ b/sound/soc/soc-core.c | |||
| @@ -1585,37 +1585,6 @@ int snd_soc_put_enum_double(struct snd_kcontrol *kcontrol, | |||
| 1585 | EXPORT_SYMBOL_GPL(snd_soc_put_enum_double); | 1585 | EXPORT_SYMBOL_GPL(snd_soc_put_enum_double); |
| 1586 | 1586 | ||
| 1587 | /** | 1587 | /** |
| 1588 | * snd_soc_info_value_enum_double - semi enumerated double mixer info callback | ||
| 1589 | * @kcontrol: mixer control | ||
| 1590 | * @uinfo: control element information | ||
| 1591 | * | ||
| 1592 | * Callback to provide information about a double semi enumerated | ||
| 1593 | * mixer control. | ||
| 1594 | * | ||
| 1595 | * Semi enumerated mixer: the enumerated items are referred as values. Can be | ||
| 1596 | * used for handling bitfield coded enumeration for example. | ||
| 1597 | * | ||
| 1598 | * Returns 0 for success. | ||
| 1599 | */ | ||
| 1600 | int snd_soc_info_value_enum_double(struct snd_kcontrol *kcontrol, | ||
| 1601 | struct snd_ctl_elem_info *uinfo) | ||
| 1602 | { | ||
| 1603 | struct soc_value_enum *e = (struct soc_value_enum *) | ||
| 1604 | kcontrol->private_value; | ||
| 1605 | |||
| 1606 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | ||
| 1607 | uinfo->count = e->shift_l == e->shift_r ? 1 : 2; | ||
| 1608 | uinfo->value.enumerated.items = e->max; | ||
| 1609 | |||
| 1610 | if (uinfo->value.enumerated.item > e->max - 1) | ||
| 1611 | uinfo->value.enumerated.item = e->max - 1; | ||
| 1612 | strcpy(uinfo->value.enumerated.name, | ||
| 1613 | e->texts[uinfo->value.enumerated.item]); | ||
| 1614 | return 0; | ||
| 1615 | } | ||
| 1616 | EXPORT_SYMBOL_GPL(snd_soc_info_value_enum_double); | ||
| 1617 | |||
| 1618 | /** | ||
| 1619 | * snd_soc_get_value_enum_double - semi enumerated double mixer get callback | 1588 | * snd_soc_get_value_enum_double - semi enumerated double mixer get callback |
| 1620 | * @kcontrol: mixer control | 1589 | * @kcontrol: mixer control |
| 1621 | * @ucontrol: control element information | 1590 | * @ucontrol: control element information |
| @@ -1631,8 +1600,7 @@ int snd_soc_get_value_enum_double(struct snd_kcontrol *kcontrol, | |||
| 1631 | struct snd_ctl_elem_value *ucontrol) | 1600 | struct snd_ctl_elem_value *ucontrol) |
| 1632 | { | 1601 | { |
| 1633 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | 1602 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); |
| 1634 | struct soc_value_enum *e = (struct soc_value_enum *) | 1603 | struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; |
| 1635 | kcontrol->private_value; | ||
| 1636 | unsigned short reg_val, val, mux; | 1604 | unsigned short reg_val, val, mux; |
| 1637 | 1605 | ||
| 1638 | reg_val = snd_soc_read(codec, e->reg); | 1606 | reg_val = snd_soc_read(codec, e->reg); |
| @@ -1671,8 +1639,7 @@ int snd_soc_put_value_enum_double(struct snd_kcontrol *kcontrol, | |||
| 1671 | struct snd_ctl_elem_value *ucontrol) | 1639 | struct snd_ctl_elem_value *ucontrol) |
| 1672 | { | 1640 | { |
| 1673 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | 1641 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); |
| 1674 | struct soc_value_enum *e = (struct soc_value_enum *) | 1642 | struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; |
| 1675 | kcontrol->private_value; | ||
| 1676 | unsigned short val; | 1643 | unsigned short val; |
| 1677 | unsigned short mask; | 1644 | unsigned short mask; |
| 1678 | 1645 | ||
diff --git a/sound/soc/soc-dapm.c b/sound/soc/soc-dapm.c index ad0d801677c1..493a4e8aa273 100644 --- a/sound/soc/soc-dapm.c +++ b/sound/soc/soc-dapm.c | |||
| @@ -137,7 +137,7 @@ static void dapm_set_path_status(struct snd_soc_dapm_widget *w, | |||
| 137 | } | 137 | } |
| 138 | break; | 138 | break; |
| 139 | case snd_soc_dapm_value_mux: { | 139 | case snd_soc_dapm_value_mux: { |
| 140 | struct soc_value_enum *e = (struct soc_value_enum *) | 140 | struct soc_enum *e = (struct soc_enum *) |
| 141 | w->kcontrols[i].private_value; | 141 | w->kcontrols[i].private_value; |
| 142 | int val, item; | 142 | int val, item; |
| 143 | 143 | ||
| @@ -200,30 +200,6 @@ static int dapm_connect_mux(struct snd_soc_codec *codec, | |||
| 200 | return -ENODEV; | 200 | return -ENODEV; |
| 201 | } | 201 | } |
| 202 | 202 | ||
| 203 | /* connect value_mux widget to it's interconnecting audio paths */ | ||
| 204 | static int dapm_connect_value_mux(struct snd_soc_codec *codec, | ||
| 205 | struct snd_soc_dapm_widget *src, struct snd_soc_dapm_widget *dest, | ||
| 206 | struct snd_soc_dapm_path *path, const char *control_name, | ||
| 207 | const struct snd_kcontrol_new *kcontrol) | ||
| 208 | { | ||
| 209 | struct soc_value_enum *e = (struct soc_value_enum *) | ||
| 210 | kcontrol->private_value; | ||
| 211 | int i; | ||
| 212 | |||
| 213 | for (i = 0; i < e->max; i++) { | ||
| 214 | if (!(strcmp(control_name, e->texts[i]))) { | ||
| 215 | list_add(&path->list, &codec->dapm_paths); | ||
| 216 | list_add(&path->list_sink, &dest->sources); | ||
| 217 | list_add(&path->list_source, &src->sinks); | ||
| 218 | path->name = (char *)e->texts[i]; | ||
| 219 | dapm_set_path_status(dest, path, 0); | ||
| 220 | return 0; | ||
| 221 | } | ||
| 222 | } | ||
| 223 | |||
| 224 | return -ENODEV; | ||
| 225 | } | ||
| 226 | |||
| 227 | /* connect mixer widget to it's interconnecting audio paths */ | 203 | /* connect mixer widget to it's interconnecting audio paths */ |
| 228 | static int dapm_connect_mixer(struct snd_soc_codec *codec, | 204 | static int dapm_connect_mixer(struct snd_soc_codec *codec, |
| 229 | struct snd_soc_dapm_widget *src, struct snd_soc_dapm_widget *dest, | 205 | struct snd_soc_dapm_widget *src, struct snd_soc_dapm_widget *dest, |
| @@ -774,45 +750,6 @@ static int dapm_mux_update_power(struct snd_soc_dapm_widget *widget, | |||
| 774 | return 0; | 750 | return 0; |
| 775 | } | 751 | } |
| 776 | 752 | ||
| 777 | /* test and update the power status of a value_mux widget */ | ||
| 778 | static int dapm_value_mux_update_power(struct snd_soc_dapm_widget *widget, | ||
| 779 | struct snd_kcontrol *kcontrol, int mask, | ||
| 780 | int mux, int val, struct soc_value_enum *e) | ||
| 781 | { | ||
| 782 | struct snd_soc_dapm_path *path; | ||
| 783 | int found = 0; | ||
| 784 | |||
| 785 | if (widget->id != snd_soc_dapm_value_mux) | ||
| 786 | return -ENODEV; | ||
| 787 | |||
| 788 | if (!snd_soc_test_bits(widget->codec, e->reg, mask, val)) | ||
| 789 | return 0; | ||
| 790 | |||
| 791 | /* find dapm widget path assoc with kcontrol */ | ||
| 792 | list_for_each_entry(path, &widget->codec->dapm_paths, list) { | ||
| 793 | if (path->kcontrol != kcontrol) | ||
| 794 | continue; | ||
| 795 | |||
| 796 | if (!path->name || !e->texts[mux]) | ||
| 797 | continue; | ||
| 798 | |||
| 799 | found = 1; | ||
| 800 | /* we now need to match the string in the enum to the path */ | ||
| 801 | if (!(strcmp(path->name, e->texts[mux]))) | ||
| 802 | path->connect = 1; /* new connection */ | ||
| 803 | else | ||
| 804 | path->connect = 0; /* old connection must be | ||
| 805 | powered down */ | ||
| 806 | } | ||
| 807 | |||
| 808 | if (found) { | ||
| 809 | dapm_power_widgets(widget->codec, SND_SOC_DAPM_STREAM_NOP); | ||
| 810 | dump_dapm(widget->codec, "mux power update"); | ||
| 811 | } | ||
| 812 | |||
| 813 | return 0; | ||
| 814 | } | ||
| 815 | |||
| 816 | /* test and update the power status of a mixer or switch widget */ | 753 | /* test and update the power status of a mixer or switch widget */ |
| 817 | static int dapm_mixer_update_power(struct snd_soc_dapm_widget *widget, | 754 | static int dapm_mixer_update_power(struct snd_soc_dapm_widget *widget, |
| 818 | struct snd_kcontrol *kcontrol, int reg, | 755 | struct snd_kcontrol *kcontrol, int reg, |
| @@ -1045,17 +982,12 @@ static int snd_soc_dapm_add_route(struct snd_soc_codec *codec, | |||
| 1045 | path->connect = 1; | 982 | path->connect = 1; |
| 1046 | return 0; | 983 | return 0; |
| 1047 | case snd_soc_dapm_mux: | 984 | case snd_soc_dapm_mux: |
| 985 | case snd_soc_dapm_value_mux: | ||
| 1048 | ret = dapm_connect_mux(codec, wsource, wsink, path, control, | 986 | ret = dapm_connect_mux(codec, wsource, wsink, path, control, |
| 1049 | &wsink->kcontrols[0]); | 987 | &wsink->kcontrols[0]); |
| 1050 | if (ret != 0) | 988 | if (ret != 0) |
| 1051 | goto err; | 989 | goto err; |
| 1052 | break; | 990 | break; |
| 1053 | case snd_soc_dapm_value_mux: | ||
| 1054 | ret = dapm_connect_value_mux(codec, wsource, wsink, path, | ||
| 1055 | control, &wsink->kcontrols[0]); | ||
| 1056 | if (ret != 0) | ||
| 1057 | goto err; | ||
| 1058 | break; | ||
| 1059 | case snd_soc_dapm_switch: | 991 | case snd_soc_dapm_switch: |
| 1060 | case snd_soc_dapm_mixer: | 992 | case snd_soc_dapm_mixer: |
| 1061 | ret = dapm_connect_mixer(codec, wsource, wsink, path, control); | 993 | ret = dapm_connect_mixer(codec, wsource, wsink, path, control); |
| @@ -1382,8 +1314,7 @@ int snd_soc_dapm_get_value_enum_double(struct snd_kcontrol *kcontrol, | |||
| 1382 | struct snd_ctl_elem_value *ucontrol) | 1314 | struct snd_ctl_elem_value *ucontrol) |
| 1383 | { | 1315 | { |
| 1384 | struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol); | 1316 | struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol); |
| 1385 | struct soc_value_enum *e = (struct soc_value_enum *) | 1317 | struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; |
| 1386 | kcontrol->private_value; | ||
| 1387 | unsigned short reg_val, val, mux; | 1318 | unsigned short reg_val, val, mux; |
| 1388 | 1319 | ||
| 1389 | reg_val = snd_soc_read(widget->codec, e->reg); | 1320 | reg_val = snd_soc_read(widget->codec, e->reg); |
| @@ -1423,8 +1354,7 @@ int snd_soc_dapm_put_value_enum_double(struct snd_kcontrol *kcontrol, | |||
| 1423 | struct snd_ctl_elem_value *ucontrol) | 1354 | struct snd_ctl_elem_value *ucontrol) |
| 1424 | { | 1355 | { |
| 1425 | struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol); | 1356 | struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol); |
| 1426 | struct soc_value_enum *e = (struct soc_value_enum *) | 1357 | struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; |
| 1427 | kcontrol->private_value; | ||
| 1428 | unsigned short val, mux; | 1358 | unsigned short val, mux; |
| 1429 | unsigned short mask; | 1359 | unsigned short mask; |
| 1430 | int ret = 0; | 1360 | int ret = 0; |
| @@ -1443,7 +1373,7 @@ int snd_soc_dapm_put_value_enum_double(struct snd_kcontrol *kcontrol, | |||
| 1443 | 1373 | ||
| 1444 | mutex_lock(&widget->codec->mutex); | 1374 | mutex_lock(&widget->codec->mutex); |
| 1445 | widget->value = val; | 1375 | widget->value = val; |
| 1446 | dapm_value_mux_update_power(widget, kcontrol, mask, mux, val, e); | 1376 | dapm_mux_update_power(widget, kcontrol, mask, mux, val, e); |
| 1447 | if (widget->event) { | 1377 | if (widget->event) { |
| 1448 | if (widget->event_flags & SND_SOC_DAPM_PRE_REG) { | 1378 | if (widget->event_flags & SND_SOC_DAPM_PRE_REG) { |
| 1449 | ret = widget->event(widget, | 1379 | ret = widget->event(widget, |
diff --git a/sound/usb/caiaq/caiaq-device.c b/sound/usb/caiaq/caiaq-device.c index a62500e387a6..41c36b055f6b 100644 --- a/sound/usb/caiaq/caiaq-device.c +++ b/sound/usb/caiaq/caiaq-device.c | |||
| @@ -42,7 +42,7 @@ | |||
| 42 | #endif | 42 | #endif |
| 43 | 43 | ||
| 44 | MODULE_AUTHOR("Daniel Mack <daniel@caiaq.de>"); | 44 | MODULE_AUTHOR("Daniel Mack <daniel@caiaq.de>"); |
| 45 | MODULE_DESCRIPTION("caiaq USB audio, version 1.3.9"); | 45 | MODULE_DESCRIPTION("caiaq USB audio, version 1.3.10"); |
| 46 | MODULE_LICENSE("GPL"); | 46 | MODULE_LICENSE("GPL"); |
| 47 | MODULE_SUPPORTED_DEVICE("{{Native Instruments, RigKontrol2}," | 47 | MODULE_SUPPORTED_DEVICE("{{Native Instruments, RigKontrol2}," |
| 48 | "{Native Instruments, RigKontrol3}," | 48 | "{Native Instruments, RigKontrol3}," |
diff --git a/sound/usb/caiaq/caiaq-device.h b/sound/usb/caiaq/caiaq-device.h index f9fbdbae269d..ab56e738c5fc 100644 --- a/sound/usb/caiaq/caiaq-device.h +++ b/sound/usb/caiaq/caiaq-device.h | |||
| @@ -75,6 +75,7 @@ struct snd_usb_caiaqdev { | |||
| 75 | wait_queue_head_t ep1_wait_queue; | 75 | wait_queue_head_t ep1_wait_queue; |
| 76 | wait_queue_head_t prepare_wait_queue; | 76 | wait_queue_head_t prepare_wait_queue; |
| 77 | int spec_received, audio_parm_answer; | 77 | int spec_received, audio_parm_answer; |
| 78 | int midi_out_active; | ||
| 78 | 79 | ||
| 79 | char vendor_name[CAIAQ_USB_STR_LEN]; | 80 | char vendor_name[CAIAQ_USB_STR_LEN]; |
| 80 | char product_name[CAIAQ_USB_STR_LEN]; | 81 | char product_name[CAIAQ_USB_STR_LEN]; |
diff --git a/sound/usb/caiaq/caiaq-midi.c b/sound/usb/caiaq/caiaq-midi.c index 30b57f97c6e4..f19fd360c936 100644 --- a/sound/usb/caiaq/caiaq-midi.c +++ b/sound/usb/caiaq/caiaq-midi.c | |||
| @@ -59,6 +59,11 @@ static int snd_usb_caiaq_midi_output_open(struct snd_rawmidi_substream *substrea | |||
| 59 | 59 | ||
| 60 | static int snd_usb_caiaq_midi_output_close(struct snd_rawmidi_substream *substream) | 60 | static int snd_usb_caiaq_midi_output_close(struct snd_rawmidi_substream *substream) |
| 61 | { | 61 | { |
| 62 | struct snd_usb_caiaqdev *dev = substream->rmidi->private_data; | ||
| 63 | if (dev->midi_out_active) { | ||
| 64 | usb_kill_urb(&dev->midi_out_urb); | ||
| 65 | dev->midi_out_active = 0; | ||
| 66 | } | ||
| 62 | return 0; | 67 | return 0; |
| 63 | } | 68 | } |
| 64 | 69 | ||
| @@ -69,7 +74,8 @@ static void snd_usb_caiaq_midi_send(struct snd_usb_caiaqdev *dev, | |||
| 69 | 74 | ||
| 70 | dev->midi_out_buf[0] = EP1_CMD_MIDI_WRITE; | 75 | dev->midi_out_buf[0] = EP1_CMD_MIDI_WRITE; |
| 71 | dev->midi_out_buf[1] = 0; /* port */ | 76 | dev->midi_out_buf[1] = 0; /* port */ |
| 72 | len = snd_rawmidi_transmit_peek(substream, dev->midi_out_buf+3, EP1_BUFSIZE-3); | 77 | len = snd_rawmidi_transmit(substream, dev->midi_out_buf + 3, |
| 78 | EP1_BUFSIZE - 3); | ||
| 73 | 79 | ||
| 74 | if (len <= 0) | 80 | if (len <= 0) |
| 75 | return; | 81 | return; |
| @@ -79,24 +85,24 @@ static void snd_usb_caiaq_midi_send(struct snd_usb_caiaqdev *dev, | |||
| 79 | 85 | ||
| 80 | ret = usb_submit_urb(&dev->midi_out_urb, GFP_ATOMIC); | 86 | ret = usb_submit_urb(&dev->midi_out_urb, GFP_ATOMIC); |
| 81 | if (ret < 0) | 87 | if (ret < 0) |
| 82 | log("snd_usb_caiaq_midi_send(%p): usb_submit_urb() failed, %d\n", | 88 | log("snd_usb_caiaq_midi_send(%p): usb_submit_urb() failed," |
| 83 | substream, ret); | 89 | "ret=%d, len=%d\n", |
| 90 | substream, ret, len); | ||
| 91 | else | ||
| 92 | dev->midi_out_active = 1; | ||
| 84 | } | 93 | } |
| 85 | 94 | ||
| 86 | static void snd_usb_caiaq_midi_output_trigger(struct snd_rawmidi_substream *substream, int up) | 95 | static void snd_usb_caiaq_midi_output_trigger(struct snd_rawmidi_substream *substream, int up) |
| 87 | { | 96 | { |
| 88 | struct snd_usb_caiaqdev *dev = substream->rmidi->private_data; | 97 | struct snd_usb_caiaqdev *dev = substream->rmidi->private_data; |
| 89 | 98 | ||
| 90 | if (dev->midi_out_substream != NULL) | 99 | if (up) { |
| 91 | return; | 100 | dev->midi_out_substream = substream; |
| 92 | 101 | if (!dev->midi_out_active) | |
| 93 | if (!up) { | 102 | snd_usb_caiaq_midi_send(dev, substream); |
| 103 | } else { | ||
| 94 | dev->midi_out_substream = NULL; | 104 | dev->midi_out_substream = NULL; |
| 95 | return; | ||
| 96 | } | 105 | } |
| 97 | |||
| 98 | dev->midi_out_substream = substream; | ||
| 99 | snd_usb_caiaq_midi_send(dev, substream); | ||
| 100 | } | 106 | } |
| 101 | 107 | ||
| 102 | 108 | ||
| @@ -161,16 +167,14 @@ int snd_usb_caiaq_midi_init(struct snd_usb_caiaqdev *device) | |||
| 161 | void snd_usb_caiaq_midi_output_done(struct urb* urb) | 167 | void snd_usb_caiaq_midi_output_done(struct urb* urb) |
| 162 | { | 168 | { |
| 163 | struct snd_usb_caiaqdev *dev = urb->context; | 169 | struct snd_usb_caiaqdev *dev = urb->context; |
| 164 | char *buf = urb->transfer_buffer; | ||
| 165 | 170 | ||
| 171 | dev->midi_out_active = 0; | ||
| 166 | if (urb->status != 0) | 172 | if (urb->status != 0) |
| 167 | return; | 173 | return; |
| 168 | 174 | ||
| 169 | if (!dev->midi_out_substream) | 175 | if (!dev->midi_out_substream) |
| 170 | return; | 176 | return; |
| 171 | 177 | ||
| 172 | snd_rawmidi_transmit_ack(dev->midi_out_substream, buf[2]); | ||
| 173 | dev->midi_out_substream = NULL; | ||
| 174 | snd_usb_caiaq_midi_send(dev, dev->midi_out_substream); | 178 | snd_usb_caiaq_midi_send(dev, dev->midi_out_substream); |
| 175 | } | 179 | } |
| 176 | 180 | ||