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-rw-r--r--drivers/net/bnx2x_link.c95
-rw-r--r--drivers/net/bnx2x_main.c17
2 files changed, 110 insertions, 2 deletions
diff --git a/drivers/net/bnx2x_link.c b/drivers/net/bnx2x_link.c
index 55f50c7093e0..bed11b9c2c2d 100644
--- a/drivers/net/bnx2x_link.c
+++ b/drivers/net/bnx2x_link.c
@@ -1755,7 +1755,9 @@ static u8 bnx2x_link_settings_status(struct link_params *params,
1755 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) == 1755 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
1756 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) || 1756 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) ||
1757 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) == 1757 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
1758 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726))) { 1758 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) ||
1759 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
1760 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481))) {
1759 vars->autoneg = AUTO_NEG_ENABLED; 1761 vars->autoneg = AUTO_NEG_ENABLED;
1760 1762
1761 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) { 1763 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) {
@@ -1997,6 +1999,23 @@ static void bnx2x_ext_phy_reset(struct link_params *params,
1997 1999
1998 break; 2000 break;
1999 2001
2002 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
2003
2004 /* Restore normal power mode*/
2005 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
2006 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
2007 params->port);
2008
2009 /* HW reset */
2010 bnx2x_hw_reset(bp, params->port);
2011
2012 bnx2x_cl45_write(bp, params->port,
2013 ext_phy_type,
2014 ext_phy_addr,
2015 MDIO_PMA_DEVAD,
2016 MDIO_PMA_REG_CTRL,
2017 1<<15);
2018 break;
2000 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: 2019 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
2001 DP(NETIF_MSG_LINK, "XGXS PHY Failure detected\n"); 2020 DP(NETIF_MSG_LINK, "XGXS PHY Failure detected\n");
2002 break; 2021 break;
@@ -3414,6 +3433,31 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
3414 ext_phy_addr, 3433 ext_phy_addr,
3415 MDIO_AN_DEVAD, 3434 MDIO_AN_DEVAD,
3416 MDIO_AN_REG_CTRL, val); 3435 MDIO_AN_REG_CTRL, val);
3436
3437 break;
3438 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
3439 DP(NETIF_MSG_LINK,
3440 "Setting the BCM8481 LASI control\n");
3441
3442 bnx2x_cl45_write(bp, params->port,
3443 ext_phy_type,
3444 ext_phy_addr,
3445 MDIO_PMA_DEVAD,
3446 MDIO_PMA_REG_LASI_CTRL, 0x1);
3447
3448 /* Restart autoneg */
3449 bnx2x_cl45_read(bp, params->port,
3450 ext_phy_type,
3451 ext_phy_addr,
3452 MDIO_AN_DEVAD,
3453 MDIO_AN_REG_CTRL, &val);
3454 val |= 0x200;
3455 bnx2x_cl45_write(bp, params->port,
3456 ext_phy_type,
3457 ext_phy_addr,
3458 MDIO_AN_DEVAD,
3459 MDIO_AN_REG_CTRL, val);
3460
3417 break; 3461 break;
3418 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: 3462 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
3419 DP(NETIF_MSG_LINK, 3463 DP(NETIF_MSG_LINK,
@@ -3830,7 +3874,53 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
3830 (val2 & (1<<14))); 3874 (val2 & (1<<14)));
3831 } 3875 }
3832 break; 3876 break;
3877 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
3878 /* Clear LASI interrupt */
3879 bnx2x_cl45_read(bp, params->port,
3880 ext_phy_type,
3881 ext_phy_addr,
3882 MDIO_PMA_DEVAD,
3883 MDIO_PMA_REG_LASI_STATUS, &val1);
3884 DP(NETIF_MSG_LINK, "8481 LASI status reg = 0x%x\n",
3885 val1);
3886
3887 /* Check 10G-BaseT link status */
3888 /* Check Global PMD signal ok */
3889 bnx2x_cl45_read(bp, params->port, ext_phy_type,
3890 ext_phy_addr,
3891 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD,
3892 &rx_sd);
3893 /* Check PCS block lock */
3894 bnx2x_cl45_read(bp, params->port, ext_phy_type,
3895 ext_phy_addr,
3896 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS,
3897 &pcs_status);
3898 DP(NETIF_MSG_LINK, "8481 1.a = 0x%x, 1.20 = 0x%x\n",
3899 rx_sd, pcs_status);
3900 if (rx_sd & pcs_status & 0x1) {
3901 vars->line_speed = SPEED_10000;
3902 ext_phy_link_up = 1;
3903 } else {
3904
3905 /* Check 1000-BaseT link status */
3906 bnx2x_cl45_read(bp, params->port, ext_phy_type,
3907 ext_phy_addr,
3908 MDIO_AN_DEVAD, 0xFFE1,
3909 &val1);
3833 3910
3911 bnx2x_cl45_read(bp, params->port, ext_phy_type,
3912 ext_phy_addr,
3913 MDIO_AN_DEVAD, 0xFFE1,
3914 &val2);
3915 DP(NETIF_MSG_LINK, "8481 7.FFE1 ="
3916 "0x%x-->0x%x\n", val1, val2);
3917 if (val2 & (1<<2)) {
3918 vars->line_speed = SPEED_1000;
3919 ext_phy_link_up = 1;
3920 }
3921 }
3922
3923 break;
3834 default: 3924 default:
3835 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n", 3925 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
3836 params->ext_phy_config); 3926 params->ext_phy_config);
@@ -4523,7 +4613,8 @@ static u8 bnx2x_link_initialize(struct link_params *params,
4523 4613
4524 if (non_ext_phy || 4614 if (non_ext_phy ||
4525 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) || 4615 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) ||
4526 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726)) { 4616 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) ||
4617 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481)) {
4527 if (params->req_line_speed == SPEED_AUTO_NEG) 4618 if (params->req_line_speed == SPEED_AUTO_NEG)
4528 bnx2x_set_parallel_detection(params, vars->phy_flags); 4619 bnx2x_set_parallel_detection(params, vars->phy_flags);
4529 bnx2x_init_internal_phy(params, vars); 4620 bnx2x_init_internal_phy(params, vars);
diff --git a/drivers/net/bnx2x_main.c b/drivers/net/bnx2x_main.c
index 2ee480b4b77c..0d2d5564f255 100644
--- a/drivers/net/bnx2x_main.c
+++ b/drivers/net/bnx2x_main.c
@@ -7730,6 +7730,22 @@ static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
7730 SUPPORTED_Asym_Pause); 7730 SUPPORTED_Asym_Pause);
7731 break; 7731 break;
7732 7732
7733 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
7734 BNX2X_DEV_INFO("ext_phy_type 0x%x (BCM8481)\n",
7735 ext_phy_type);
7736
7737 bp->port.supported |= (SUPPORTED_10baseT_Half |
7738 SUPPORTED_10baseT_Full |
7739 SUPPORTED_100baseT_Half |
7740 SUPPORTED_100baseT_Full |
7741 SUPPORTED_1000baseT_Full |
7742 SUPPORTED_10000baseT_Full |
7743 SUPPORTED_TP |
7744 SUPPORTED_Autoneg |
7745 SUPPORTED_Pause |
7746 SUPPORTED_Asym_Pause);
7747 break;
7748
7733 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: 7749 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
7734 BNX2X_ERR("XGXS PHY Failure detected 0x%x\n", 7750 BNX2X_ERR("XGXS PHY Failure detected 0x%x\n",
7735 bp->link_params.ext_phy_config); 7751 bp->link_params.ext_phy_config);
@@ -8189,6 +8205,7 @@ static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8189 break; 8205 break;
8190 8206
8191 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: 8207 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
8208 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
8192 cmd->port = PORT_TP; 8209 cmd->port = PORT_TP;
8193 break; 8210 break;
8194 8211
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 16:52:15 -0500