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-rw-r--r--drivers/dma/coh901318.c208
-rw-r--r--drivers/dma/coh901318.h212
-rw-r--r--drivers/dma/coh901318_lli.c1
3 files changed, 209 insertions, 212 deletions
diff --git a/drivers/dma/coh901318.c b/drivers/dma/coh901318.c
index 1be69b87a913..f7100dc6b8e2 100644
--- a/drivers/dma/coh901318.c
+++ b/drivers/dma/coh901318.c
@@ -27,6 +27,214 @@
27#include "coh901318_lli.h" 27#include "coh901318_lli.h"
28#include "dmaengine.h" 28#include "dmaengine.h"
29 29
30#define COH901318_MOD32_MASK (0x1F)
31#define COH901318_WORD_MASK (0xFFFFFFFF)
32/* INT_STATUS - Interrupt Status Registers 32bit (R/-) */
33#define COH901318_INT_STATUS1 (0x0000)
34#define COH901318_INT_STATUS2 (0x0004)
35/* TC_INT_STATUS - Terminal Count Interrupt Status Registers 32bit (R/-) */
36#define COH901318_TC_INT_STATUS1 (0x0008)
37#define COH901318_TC_INT_STATUS2 (0x000C)
38/* TC_INT_CLEAR - Terminal Count Interrupt Clear Registers 32bit (-/W) */
39#define COH901318_TC_INT_CLEAR1 (0x0010)
40#define COH901318_TC_INT_CLEAR2 (0x0014)
41/* RAW_TC_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
42#define COH901318_RAW_TC_INT_STATUS1 (0x0018)
43#define COH901318_RAW_TC_INT_STATUS2 (0x001C)
44/* BE_INT_STATUS - Bus Error Interrupt Status Registers 32bit (R/-) */
45#define COH901318_BE_INT_STATUS1 (0x0020)
46#define COH901318_BE_INT_STATUS2 (0x0024)
47/* BE_INT_CLEAR - Bus Error Interrupt Clear Registers 32bit (-/W) */
48#define COH901318_BE_INT_CLEAR1 (0x0028)
49#define COH901318_BE_INT_CLEAR2 (0x002C)
50/* RAW_BE_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
51#define COH901318_RAW_BE_INT_STATUS1 (0x0030)
52#define COH901318_RAW_BE_INT_STATUS2 (0x0034)
53
54/*
55 * CX_CFG - Channel Configuration Registers 32bit (R/W)
56 */
57#define COH901318_CX_CFG (0x0100)
58#define COH901318_CX_CFG_SPACING (0x04)
59/* Channel enable activates tha dma job */
60#define COH901318_CX_CFG_CH_ENABLE (0x00000001)
61#define COH901318_CX_CFG_CH_DISABLE (0x00000000)
62/* Request Mode */
63#define COH901318_CX_CFG_RM_MASK (0x00000006)
64#define COH901318_CX_CFG_RM_MEMORY_TO_MEMORY (0x0 << 1)
65#define COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY (0x1 << 1)
66#define COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY (0x1 << 1)
67#define COH901318_CX_CFG_RM_PRIMARY_TO_SECONDARY (0x3 << 1)
68#define COH901318_CX_CFG_RM_SECONDARY_TO_PRIMARY (0x3 << 1)
69/* Linked channel request field. RM must == 11 */
70#define COH901318_CX_CFG_LCRF_SHIFT 3
71#define COH901318_CX_CFG_LCRF_MASK (0x000001F8)
72#define COH901318_CX_CFG_LCR_DISABLE (0x00000000)
73/* Terminal Counter Interrupt Request Mask */
74#define COH901318_CX_CFG_TC_IRQ_ENABLE (0x00000200)
75#define COH901318_CX_CFG_TC_IRQ_DISABLE (0x00000000)
76/* Bus Error interrupt Mask */
77#define COH901318_CX_CFG_BE_IRQ_ENABLE (0x00000400)
78#define COH901318_CX_CFG_BE_IRQ_DISABLE (0x00000000)
79
80/*
81 * CX_STAT - Channel Status Registers 32bit (R/-)
82 */
83#define COH901318_CX_STAT (0x0200)
84#define COH901318_CX_STAT_SPACING (0x04)
85#define COH901318_CX_STAT_RBE_IRQ_IND (0x00000008)
86#define COH901318_CX_STAT_RTC_IRQ_IND (0x00000004)
87#define COH901318_CX_STAT_ACTIVE (0x00000002)
88#define COH901318_CX_STAT_ENABLED (0x00000001)
89
90/*
91 * CX_CTRL - Channel Control Registers 32bit (R/W)
92 */
93#define COH901318_CX_CTRL (0x0400)
94#define COH901318_CX_CTRL_SPACING (0x10)
95/* Transfer Count Enable */
96#define COH901318_CX_CTRL_TC_ENABLE (0x00001000)
97#define COH901318_CX_CTRL_TC_DISABLE (0x00000000)
98/* Transfer Count Value 0 - 4095 */
99#define COH901318_CX_CTRL_TC_VALUE_MASK (0x00000FFF)
100/* Burst count */
101#define COH901318_CX_CTRL_BURST_COUNT_MASK (0x0000E000)
102#define COH901318_CX_CTRL_BURST_COUNT_64_BYTES (0x7 << 13)
103#define COH901318_CX_CTRL_BURST_COUNT_48_BYTES (0x6 << 13)
104#define COH901318_CX_CTRL_BURST_COUNT_32_BYTES (0x5 << 13)
105#define COH901318_CX_CTRL_BURST_COUNT_16_BYTES (0x4 << 13)
106#define COH901318_CX_CTRL_BURST_COUNT_8_BYTES (0x3 << 13)
107#define COH901318_CX_CTRL_BURST_COUNT_4_BYTES (0x2 << 13)
108#define COH901318_CX_CTRL_BURST_COUNT_2_BYTES (0x1 << 13)
109#define COH901318_CX_CTRL_BURST_COUNT_1_BYTE (0x0 << 13)
110/* Source bus size */
111#define COH901318_CX_CTRL_SRC_BUS_SIZE_MASK (0x00030000)
112#define COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS (0x2 << 16)
113#define COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS (0x1 << 16)
114#define COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS (0x0 << 16)
115/* Source address increment */
116#define COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE (0x00040000)
117#define COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE (0x00000000)
118/* Destination Bus Size */
119#define COH901318_CX_CTRL_DST_BUS_SIZE_MASK (0x00180000)
120#define COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS (0x2 << 19)
121#define COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS (0x1 << 19)
122#define COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS (0x0 << 19)
123/* Destination address increment */
124#define COH901318_CX_CTRL_DST_ADDR_INC_ENABLE (0x00200000)
125#define COH901318_CX_CTRL_DST_ADDR_INC_DISABLE (0x00000000)
126/* Master Mode (Master2 is only connected to MSL) */
127#define COH901318_CX_CTRL_MASTER_MODE_MASK (0x00C00000)
128#define COH901318_CX_CTRL_MASTER_MODE_M2R_M1W (0x3 << 22)
129#define COH901318_CX_CTRL_MASTER_MODE_M1R_M2W (0x2 << 22)
130#define COH901318_CX_CTRL_MASTER_MODE_M2RW (0x1 << 22)
131#define COH901318_CX_CTRL_MASTER_MODE_M1RW (0x0 << 22)
132/* Terminal Count flag to PER enable */
133#define COH901318_CX_CTRL_TCP_ENABLE (0x01000000)
134#define COH901318_CX_CTRL_TCP_DISABLE (0x00000000)
135/* Terminal Count flags to CPU enable */
136#define COH901318_CX_CTRL_TC_IRQ_ENABLE (0x02000000)
137#define COH901318_CX_CTRL_TC_IRQ_DISABLE (0x00000000)
138/* Hand shake to peripheral */
139#define COH901318_CX_CTRL_HSP_ENABLE (0x04000000)
140#define COH901318_CX_CTRL_HSP_DISABLE (0x00000000)
141#define COH901318_CX_CTRL_HSS_ENABLE (0x08000000)
142#define COH901318_CX_CTRL_HSS_DISABLE (0x00000000)
143/* DMA mode */
144#define COH901318_CX_CTRL_DDMA_MASK (0x30000000)
145#define COH901318_CX_CTRL_DDMA_LEGACY (0x0 << 28)
146#define COH901318_CX_CTRL_DDMA_DEMAND_DMA1 (0x1 << 28)
147#define COH901318_CX_CTRL_DDMA_DEMAND_DMA2 (0x2 << 28)
148/* Primary Request Data Destination */
149#define COH901318_CX_CTRL_PRDD_MASK (0x40000000)
150#define COH901318_CX_CTRL_PRDD_DEST (0x1 << 30)
151#define COH901318_CX_CTRL_PRDD_SOURCE (0x0 << 30)
152
153/*
154 * CX_SRC_ADDR - Channel Source Address Registers 32bit (R/W)
155 */
156#define COH901318_CX_SRC_ADDR (0x0404)
157#define COH901318_CX_SRC_ADDR_SPACING (0x10)
158
159/*
160 * CX_DST_ADDR - Channel Destination Address Registers 32bit R/W
161 */
162#define COH901318_CX_DST_ADDR (0x0408)
163#define COH901318_CX_DST_ADDR_SPACING (0x10)
164
165/*
166 * CX_LNK_ADDR - Channel Link Address Registers 32bit (R/W)
167 */
168#define COH901318_CX_LNK_ADDR (0x040C)
169#define COH901318_CX_LNK_ADDR_SPACING (0x10)
170#define COH901318_CX_LNK_LINK_IMMEDIATE (0x00000001)
171
172/**
173 * struct coh901318_params - parameters for DMAC configuration
174 * @config: DMA config register
175 * @ctrl_lli_last: DMA control register for the last lli in the list
176 * @ctrl_lli: DMA control register for an lli
177 * @ctrl_lli_chained: DMA control register for a chained lli
178 */
179struct coh901318_params {
180 u32 config;
181 u32 ctrl_lli_last;
182 u32 ctrl_lli;
183 u32 ctrl_lli_chained;
184};
185
186/**
187 * struct coh_dma_channel - dma channel base
188 * @name: ascii name of dma channel
189 * @number: channel id number
190 * @desc_nbr_max: number of preallocated descriptors
191 * @priority_high: prio of channel, 0 low otherwise high.
192 * @param: configuration parameters
193 */
194struct coh_dma_channel {
195 const char name[32];
196 const int number;
197 const int desc_nbr_max;
198 const int priority_high;
199 const struct coh901318_params param;
200};
201
202/**
203 * dma_access_memory_state_t - register dma for memory access
204 *
205 * @dev: The dma device
206 * @active: 1 means dma intends to access memory
207 * 0 means dma wont access memory
208 */
209typedef void (*dma_access_memory_state_t)(struct device *dev,
210 bool active);
211
212/**
213 * struct powersave - DMA power save structure
214 * @lock: lock protecting data in this struct
215 * @started_channels: bit mask indicating active dma channels
216 */
217struct powersave {
218 spinlock_t lock;
219 u64 started_channels;
220};
221
222/**
223 * struct coh901318_platform - platform arch structure
224 * @chans_slave: specifying dma slave channels
225 * @chans_memcpy: specifying dma memcpy channels
226 * @access_memory_state: requesting DMA memory access (on / off)
227 * @chan_conf: dma channel configurations
228 * @max_channels: max number of dma chanenls
229 */
230struct coh901318_platform {
231 const int *chans_slave;
232 const int *chans_memcpy;
233 const dma_access_memory_state_t access_memory_state;
234 const struct coh_dma_channel *chan_conf;
235 const int max_channels;
236};
237
30/* points out all dma slave channels. 238/* points out all dma slave channels.
31 * Syntax is [A1, B1, A2, B2, .... ,-1,-1] 239 * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
32 * Select all channels from A to B, end of list is marked with -1,-1 240 * Select all channels from A to B, end of list is marked with -1,-1
diff --git a/drivers/dma/coh901318.h b/drivers/dma/coh901318.h
index 9353c40b152a..275a36e1afc3 100644
--- a/drivers/dma/coh901318.h
+++ b/drivers/dma/coh901318.h
@@ -8,9 +8,6 @@
8#ifndef COH901318_H 8#ifndef COH901318_H
9#define COH901318_H 9#define COH901318_H
10 10
11#include <linux/device.h>
12#include <linux/dmaengine.h>
13
14#define MAX_DMA_PACKET_SIZE_SHIFT 11 11#define MAX_DMA_PACKET_SIZE_SHIFT 11
15#define MAX_DMA_PACKET_SIZE (1 << MAX_DMA_PACKET_SIZE_SHIFT) 12#define MAX_DMA_PACKET_SIZE (1 << MAX_DMA_PACKET_SIZE_SHIFT)
16 13
@@ -32,214 +29,5 @@ struct coh901318_lli {
32 void *virt_link_addr; 29 void *virt_link_addr;
33 dma_addr_t phy_this; 30 dma_addr_t phy_this;
34}; 31};
35/**
36 * struct coh901318_params - parameters for DMAC configuration
37 * @config: DMA config register
38 * @ctrl_lli_last: DMA control register for the last lli in the list
39 * @ctrl_lli: DMA control register for an lli
40 * @ctrl_lli_chained: DMA control register for a chained lli
41 */
42struct coh901318_params {
43 u32 config;
44 u32 ctrl_lli_last;
45 u32 ctrl_lli;
46 u32 ctrl_lli_chained;
47};
48/**
49 * struct coh_dma_channel - dma channel base
50 * @name: ascii name of dma channel
51 * @number: channel id number
52 * @desc_nbr_max: number of preallocated descriptors
53 * @priority_high: prio of channel, 0 low otherwise high.
54 * @param: configuration parameters
55 */
56struct coh_dma_channel {
57 const char name[32];
58 const int number;
59 const int desc_nbr_max;
60 const int priority_high;
61 const struct coh901318_params param;
62};
63
64/**
65 * dma_access_memory_state_t - register dma for memory access
66 *
67 * @dev: The dma device
68 * @active: 1 means dma intends to access memory
69 * 0 means dma wont access memory
70 */
71typedef void (*dma_access_memory_state_t)(struct device *dev,
72 bool active);
73
74/**
75 * struct powersave - DMA power save structure
76 * @lock: lock protecting data in this struct
77 * @started_channels: bit mask indicating active dma channels
78 */
79struct powersave {
80 spinlock_t lock;
81 u64 started_channels;
82};
83/**
84 * struct coh901318_platform - platform arch structure
85 * @chans_slave: specifying dma slave channels
86 * @chans_memcpy: specifying dma memcpy channels
87 * @access_memory_state: requesting DMA memory access (on / off)
88 * @chan_conf: dma channel configurations
89 * @max_channels: max number of dma chanenls
90 */
91struct coh901318_platform {
92 const int *chans_slave;
93 const int *chans_memcpy;
94 const dma_access_memory_state_t access_memory_state;
95 const struct coh_dma_channel *chan_conf;
96 const int max_channels;
97};
98
99/*
100 * DMA Controller - this access the static mappings of the coh901318 dma.
101 *
102 */
103
104#define COH901318_MOD32_MASK (0x1F)
105#define COH901318_WORD_MASK (0xFFFFFFFF)
106/* INT_STATUS - Interrupt Status Registers 32bit (R/-) */
107#define COH901318_INT_STATUS1 (0x0000)
108#define COH901318_INT_STATUS2 (0x0004)
109/* TC_INT_STATUS - Terminal Count Interrupt Status Registers 32bit (R/-) */
110#define COH901318_TC_INT_STATUS1 (0x0008)
111#define COH901318_TC_INT_STATUS2 (0x000C)
112/* TC_INT_CLEAR - Terminal Count Interrupt Clear Registers 32bit (-/W) */
113#define COH901318_TC_INT_CLEAR1 (0x0010)
114#define COH901318_TC_INT_CLEAR2 (0x0014)
115/* RAW_TC_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
116#define COH901318_RAW_TC_INT_STATUS1 (0x0018)
117#define COH901318_RAW_TC_INT_STATUS2 (0x001C)
118/* BE_INT_STATUS - Bus Error Interrupt Status Registers 32bit (R/-) */
119#define COH901318_BE_INT_STATUS1 (0x0020)
120#define COH901318_BE_INT_STATUS2 (0x0024)
121/* BE_INT_CLEAR - Bus Error Interrupt Clear Registers 32bit (-/W) */
122#define COH901318_BE_INT_CLEAR1 (0x0028)
123#define COH901318_BE_INT_CLEAR2 (0x002C)
124/* RAW_BE_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
125#define COH901318_RAW_BE_INT_STATUS1 (0x0030)
126#define COH901318_RAW_BE_INT_STATUS2 (0x0034)
127
128/*
129 * CX_CFG - Channel Configuration Registers 32bit (R/W)
130 */
131#define COH901318_CX_CFG (0x0100)
132#define COH901318_CX_CFG_SPACING (0x04)
133/* Channel enable activates tha dma job */
134#define COH901318_CX_CFG_CH_ENABLE (0x00000001)
135#define COH901318_CX_CFG_CH_DISABLE (0x00000000)
136/* Request Mode */
137#define COH901318_CX_CFG_RM_MASK (0x00000006)
138#define COH901318_CX_CFG_RM_MEMORY_TO_MEMORY (0x0 << 1)
139#define COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY (0x1 << 1)
140#define COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY (0x1 << 1)
141#define COH901318_CX_CFG_RM_PRIMARY_TO_SECONDARY (0x3 << 1)
142#define COH901318_CX_CFG_RM_SECONDARY_TO_PRIMARY (0x3 << 1)
143/* Linked channel request field. RM must == 11 */
144#define COH901318_CX_CFG_LCRF_SHIFT 3
145#define COH901318_CX_CFG_LCRF_MASK (0x000001F8)
146#define COH901318_CX_CFG_LCR_DISABLE (0x00000000)
147/* Terminal Counter Interrupt Request Mask */
148#define COH901318_CX_CFG_TC_IRQ_ENABLE (0x00000200)
149#define COH901318_CX_CFG_TC_IRQ_DISABLE (0x00000000)
150/* Bus Error interrupt Mask */
151#define COH901318_CX_CFG_BE_IRQ_ENABLE (0x00000400)
152#define COH901318_CX_CFG_BE_IRQ_DISABLE (0x00000000)
153 32
154/*
155 * CX_STAT - Channel Status Registers 32bit (R/-)
156 */
157#define COH901318_CX_STAT (0x0200)
158#define COH901318_CX_STAT_SPACING (0x04)
159#define COH901318_CX_STAT_RBE_IRQ_IND (0x00000008)
160#define COH901318_CX_STAT_RTC_IRQ_IND (0x00000004)
161#define COH901318_CX_STAT_ACTIVE (0x00000002)
162#define COH901318_CX_STAT_ENABLED (0x00000001)
163
164/*
165 * CX_CTRL - Channel Control Registers 32bit (R/W)
166 */
167#define COH901318_CX_CTRL (0x0400)
168#define COH901318_CX_CTRL_SPACING (0x10)
169/* Transfer Count Enable */
170#define COH901318_CX_CTRL_TC_ENABLE (0x00001000)
171#define COH901318_CX_CTRL_TC_DISABLE (0x00000000)
172/* Transfer Count Value 0 - 4095 */
173#define COH901318_CX_CTRL_TC_VALUE_MASK (0x00000FFF)
174/* Burst count */
175#define COH901318_CX_CTRL_BURST_COUNT_MASK (0x0000E000)
176#define COH901318_CX_CTRL_BURST_COUNT_64_BYTES (0x7 << 13)
177#define COH901318_CX_CTRL_BURST_COUNT_48_BYTES (0x6 << 13)
178#define COH901318_CX_CTRL_BURST_COUNT_32_BYTES (0x5 << 13)
179#define COH901318_CX_CTRL_BURST_COUNT_16_BYTES (0x4 << 13)
180#define COH901318_CX_CTRL_BURST_COUNT_8_BYTES (0x3 << 13)
181#define COH901318_CX_CTRL_BURST_COUNT_4_BYTES (0x2 << 13)
182#define COH901318_CX_CTRL_BURST_COUNT_2_BYTES (0x1 << 13)
183#define COH901318_CX_CTRL_BURST_COUNT_1_BYTE (0x0 << 13)
184/* Source bus size */
185#define COH901318_CX_CTRL_SRC_BUS_SIZE_MASK (0x00030000)
186#define COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS (0x2 << 16)
187#define COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS (0x1 << 16)
188#define COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS (0x0 << 16)
189/* Source address increment */
190#define COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE (0x00040000)
191#define COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE (0x00000000)
192/* Destination Bus Size */
193#define COH901318_CX_CTRL_DST_BUS_SIZE_MASK (0x00180000)
194#define COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS (0x2 << 19)
195#define COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS (0x1 << 19)
196#define COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS (0x0 << 19)
197/* Destination address increment */
198#define COH901318_CX_CTRL_DST_ADDR_INC_ENABLE (0x00200000)
199#define COH901318_CX_CTRL_DST_ADDR_INC_DISABLE (0x00000000)
200/* Master Mode (Master2 is only connected to MSL) */
201#define COH901318_CX_CTRL_MASTER_MODE_MASK (0x00C00000)
202#define COH901318_CX_CTRL_MASTER_MODE_M2R_M1W (0x3 << 22)
203#define COH901318_CX_CTRL_MASTER_MODE_M1R_M2W (0x2 << 22)
204#define COH901318_CX_CTRL_MASTER_MODE_M2RW (0x1 << 22)
205#define COH901318_CX_CTRL_MASTER_MODE_M1RW (0x0 << 22)
206/* Terminal Count flag to PER enable */
207#define COH901318_CX_CTRL_TCP_ENABLE (0x01000000)
208#define COH901318_CX_CTRL_TCP_DISABLE (0x00000000)
209/* Terminal Count flags to CPU enable */
210#define COH901318_CX_CTRL_TC_IRQ_ENABLE (0x02000000)
211#define COH901318_CX_CTRL_TC_IRQ_DISABLE (0x00000000)
212/* Hand shake to peripheral */
213#define COH901318_CX_CTRL_HSP_ENABLE (0x04000000)
214#define COH901318_CX_CTRL_HSP_DISABLE (0x00000000)
215#define COH901318_CX_CTRL_HSS_ENABLE (0x08000000)
216#define COH901318_CX_CTRL_HSS_DISABLE (0x00000000)
217/* DMA mode */
218#define COH901318_CX_CTRL_DDMA_MASK (0x30000000)
219#define COH901318_CX_CTRL_DDMA_LEGACY (0x0 << 28)
220#define COH901318_CX_CTRL_DDMA_DEMAND_DMA1 (0x1 << 28)
221#define COH901318_CX_CTRL_DDMA_DEMAND_DMA2 (0x2 << 28)
222/* Primary Request Data Destination */
223#define COH901318_CX_CTRL_PRDD_MASK (0x40000000)
224#define COH901318_CX_CTRL_PRDD_DEST (0x1 << 30)
225#define COH901318_CX_CTRL_PRDD_SOURCE (0x0 << 30)
226
227/*
228 * CX_SRC_ADDR - Channel Source Address Registers 32bit (R/W)
229 */
230#define COH901318_CX_SRC_ADDR (0x0404)
231#define COH901318_CX_SRC_ADDR_SPACING (0x10)
232
233/*
234 * CX_DST_ADDR - Channel Destination Address Registers 32bit R/W
235 */
236#define COH901318_CX_DST_ADDR (0x0408)
237#define COH901318_CX_DST_ADDR_SPACING (0x10)
238
239/*
240 * CX_LNK_ADDR - Channel Link Address Registers 32bit (R/W)
241 */
242#define COH901318_CX_LNK_ADDR (0x040C)
243#define COH901318_CX_LNK_ADDR_SPACING (0x10)
244#define COH901318_CX_LNK_LINK_IMMEDIATE (0x00000001)
245#endif /* COH901318_H */ 33#endif /* COH901318_H */
diff --git a/drivers/dma/coh901318_lli.c b/drivers/dma/coh901318_lli.c
index e25cac0af3f6..b2e284f78c73 100644
--- a/drivers/dma/coh901318_lli.c
+++ b/drivers/dma/coh901318_lli.c
@@ -11,6 +11,7 @@
11#include <linux/memory.h> 11#include <linux/memory.h>
12#include <linux/gfp.h> 12#include <linux/gfp.h>
13#include <linux/dmapool.h> 13#include <linux/dmapool.h>
14#include <linux/dmaengine.h>
14 15
15#include "coh901318.h" 16#include "coh901318.h"
16#include "coh901318_lli.h" 17#include "coh901318_lli.h"
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-19 21:49:49 -0500