diff options
-rw-r--r-- | drivers/pinctrl/spear/pinctrl-spear1310.c | 93 |
1 files changed, 51 insertions, 42 deletions
diff --git a/drivers/pinctrl/spear/pinctrl-spear1310.c b/drivers/pinctrl/spear/pinctrl-spear1310.c index baf98ae0b1c7..a25ab73a1615 100644 --- a/drivers/pinctrl/spear/pinctrl-spear1310.c +++ b/drivers/pinctrl/spear/pinctrl-spear1310.c | |||
@@ -1763,29 +1763,52 @@ static struct spear_function can1_function = { | |||
1763 | .ngroups = ARRAY_SIZE(can1_grps), | 1763 | .ngroups = ARRAY_SIZE(can1_grps), |
1764 | }; | 1764 | }; |
1765 | 1765 | ||
1766 | /* Pad multiplexing for pci device */ | 1766 | /* Pad multiplexing for (ras-ip) pci device */ |
1767 | static const unsigned pci_sata_pins[] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 18, | 1767 | static const unsigned pci_pins[] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 18, |
1768 | 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, | 1768 | 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, |
1769 | 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, | 1769 | 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, |
1770 | 55, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99 }; | 1770 | 55, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99 }; |
1771 | #define PCI_SATA_MUXREG \ | ||
1772 | { \ | ||
1773 | .reg = PAD_FUNCTION_EN_0, \ | ||
1774 | .mask = PMX_MCI_DATA8_15_MASK, \ | ||
1775 | .val = 0, \ | ||
1776 | }, { \ | ||
1777 | .reg = PAD_FUNCTION_EN_1, \ | ||
1778 | .mask = PMX_PCI_REG1_MASK, \ | ||
1779 | .val = 0, \ | ||
1780 | }, { \ | ||
1781 | .reg = PAD_FUNCTION_EN_2, \ | ||
1782 | .mask = PMX_PCI_REG2_MASK, \ | ||
1783 | .val = 0, \ | ||
1784 | } | ||
1785 | 1771 | ||
1786 | /* pad multiplexing for pcie0 device */ | 1772 | static struct spear_muxreg pci_muxreg[] = { |
1773 | { | ||
1774 | .reg = PAD_FUNCTION_EN_0, | ||
1775 | .mask = PMX_MCI_DATA8_15_MASK, | ||
1776 | .val = 0, | ||
1777 | }, { | ||
1778 | .reg = PAD_FUNCTION_EN_1, | ||
1779 | .mask = PMX_PCI_REG1_MASK, | ||
1780 | .val = 0, | ||
1781 | }, { | ||
1782 | .reg = PAD_FUNCTION_EN_2, | ||
1783 | .mask = PMX_PCI_REG2_MASK, | ||
1784 | .val = 0, | ||
1785 | }, | ||
1786 | }; | ||
1787 | |||
1788 | static struct spear_modemux pci_modemux[] = { | ||
1789 | { | ||
1790 | .muxregs = pci_muxreg, | ||
1791 | .nmuxregs = ARRAY_SIZE(pci_muxreg), | ||
1792 | }, | ||
1793 | }; | ||
1794 | |||
1795 | static struct spear_pingroup pci_pingroup = { | ||
1796 | .name = "pci_grp", | ||
1797 | .pins = pci_pins, | ||
1798 | .npins = ARRAY_SIZE(pci_pins), | ||
1799 | .modemuxs = pci_modemux, | ||
1800 | .nmodemuxs = ARRAY_SIZE(pci_modemux), | ||
1801 | }; | ||
1802 | |||
1803 | static const char *const pci_grps[] = { "pci_grp" }; | ||
1804 | static struct spear_function pci_function = { | ||
1805 | .name = "pci", | ||
1806 | .groups = pci_grps, | ||
1807 | .ngroups = ARRAY_SIZE(pci_grps), | ||
1808 | }; | ||
1809 | |||
1810 | /* pad multiplexing for (fix-part) pcie0 device */ | ||
1787 | static struct spear_muxreg pcie0_muxreg[] = { | 1811 | static struct spear_muxreg pcie0_muxreg[] = { |
1788 | PCI_SATA_MUXREG, | ||
1789 | { | 1812 | { |
1790 | .reg = PCIE_SATA_CFG, | 1813 | .reg = PCIE_SATA_CFG, |
1791 | .mask = PCIE_CFG_VAL(0), | 1814 | .mask = PCIE_CFG_VAL(0), |
@@ -1802,15 +1825,12 @@ static struct spear_modemux pcie0_modemux[] = { | |||
1802 | 1825 | ||
1803 | static struct spear_pingroup pcie0_pingroup = { | 1826 | static struct spear_pingroup pcie0_pingroup = { |
1804 | .name = "pcie0_grp", | 1827 | .name = "pcie0_grp", |
1805 | .pins = pci_sata_pins, | ||
1806 | .npins = ARRAY_SIZE(pci_sata_pins), | ||
1807 | .modemuxs = pcie0_modemux, | 1828 | .modemuxs = pcie0_modemux, |
1808 | .nmodemuxs = ARRAY_SIZE(pcie0_modemux), | 1829 | .nmodemuxs = ARRAY_SIZE(pcie0_modemux), |
1809 | }; | 1830 | }; |
1810 | 1831 | ||
1811 | /* pad multiplexing for pcie1 device */ | 1832 | /* pad multiplexing for (fix-part) pcie1 device */ |
1812 | static struct spear_muxreg pcie1_muxreg[] = { | 1833 | static struct spear_muxreg pcie1_muxreg[] = { |
1813 | PCI_SATA_MUXREG, | ||
1814 | { | 1834 | { |
1815 | .reg = PCIE_SATA_CFG, | 1835 | .reg = PCIE_SATA_CFG, |
1816 | .mask = PCIE_CFG_VAL(1), | 1836 | .mask = PCIE_CFG_VAL(1), |
@@ -1827,15 +1847,12 @@ static struct spear_modemux pcie1_modemux[] = { | |||
1827 | 1847 | ||
1828 | static struct spear_pingroup pcie1_pingroup = { | 1848 | static struct spear_pingroup pcie1_pingroup = { |
1829 | .name = "pcie1_grp", | 1849 | .name = "pcie1_grp", |
1830 | .pins = pci_sata_pins, | ||
1831 | .npins = ARRAY_SIZE(pci_sata_pins), | ||
1832 | .modemuxs = pcie1_modemux, | 1850 | .modemuxs = pcie1_modemux, |
1833 | .nmodemuxs = ARRAY_SIZE(pcie1_modemux), | 1851 | .nmodemuxs = ARRAY_SIZE(pcie1_modemux), |
1834 | }; | 1852 | }; |
1835 | 1853 | ||
1836 | /* pad multiplexing for pcie2 device */ | 1854 | /* pad multiplexing for (fix-part) pcie2 device */ |
1837 | static struct spear_muxreg pcie2_muxreg[] = { | 1855 | static struct spear_muxreg pcie2_muxreg[] = { |
1838 | PCI_SATA_MUXREG, | ||
1839 | { | 1856 | { |
1840 | .reg = PCIE_SATA_CFG, | 1857 | .reg = PCIE_SATA_CFG, |
1841 | .mask = PCIE_CFG_VAL(2), | 1858 | .mask = PCIE_CFG_VAL(2), |
@@ -1852,22 +1869,20 @@ static struct spear_modemux pcie2_modemux[] = { | |||
1852 | 1869 | ||
1853 | static struct spear_pingroup pcie2_pingroup = { | 1870 | static struct spear_pingroup pcie2_pingroup = { |
1854 | .name = "pcie2_grp", | 1871 | .name = "pcie2_grp", |
1855 | .pins = pci_sata_pins, | ||
1856 | .npins = ARRAY_SIZE(pci_sata_pins), | ||
1857 | .modemuxs = pcie2_modemux, | 1872 | .modemuxs = pcie2_modemux, |
1858 | .nmodemuxs = ARRAY_SIZE(pcie2_modemux), | 1873 | .nmodemuxs = ARRAY_SIZE(pcie2_modemux), |
1859 | }; | 1874 | }; |
1860 | 1875 | ||
1861 | static const char *const pci_grps[] = { "pcie0_grp", "pcie1_grp", "pcie2_grp" }; | 1876 | static const char *const pcie_grps[] = { "pcie0_grp", "pcie1_grp", "pcie2_grp" |
1862 | static struct spear_function pci_function = { | 1877 | }; |
1863 | .name = "pci", | 1878 | static struct spear_function pcie_function = { |
1864 | .groups = pci_grps, | 1879 | .name = "pci_express", |
1865 | .ngroups = ARRAY_SIZE(pci_grps), | 1880 | .groups = pcie_grps, |
1881 | .ngroups = ARRAY_SIZE(pcie_grps), | ||
1866 | }; | 1882 | }; |
1867 | 1883 | ||
1868 | /* pad multiplexing for sata0 device */ | 1884 | /* pad multiplexing for sata0 device */ |
1869 | static struct spear_muxreg sata0_muxreg[] = { | 1885 | static struct spear_muxreg sata0_muxreg[] = { |
1870 | PCI_SATA_MUXREG, | ||
1871 | { | 1886 | { |
1872 | .reg = PCIE_SATA_CFG, | 1887 | .reg = PCIE_SATA_CFG, |
1873 | .mask = SATA_CFG_VAL(0), | 1888 | .mask = SATA_CFG_VAL(0), |
@@ -1884,15 +1899,12 @@ static struct spear_modemux sata0_modemux[] = { | |||
1884 | 1899 | ||
1885 | static struct spear_pingroup sata0_pingroup = { | 1900 | static struct spear_pingroup sata0_pingroup = { |
1886 | .name = "sata0_grp", | 1901 | .name = "sata0_grp", |
1887 | .pins = pci_sata_pins, | ||
1888 | .npins = ARRAY_SIZE(pci_sata_pins), | ||
1889 | .modemuxs = sata0_modemux, | 1902 | .modemuxs = sata0_modemux, |
1890 | .nmodemuxs = ARRAY_SIZE(sata0_modemux), | 1903 | .nmodemuxs = ARRAY_SIZE(sata0_modemux), |
1891 | }; | 1904 | }; |
1892 | 1905 | ||
1893 | /* pad multiplexing for sata1 device */ | 1906 | /* pad multiplexing for sata1 device */ |
1894 | static struct spear_muxreg sata1_muxreg[] = { | 1907 | static struct spear_muxreg sata1_muxreg[] = { |
1895 | PCI_SATA_MUXREG, | ||
1896 | { | 1908 | { |
1897 | .reg = PCIE_SATA_CFG, | 1909 | .reg = PCIE_SATA_CFG, |
1898 | .mask = SATA_CFG_VAL(1), | 1910 | .mask = SATA_CFG_VAL(1), |
@@ -1909,15 +1921,12 @@ static struct spear_modemux sata1_modemux[] = { | |||
1909 | 1921 | ||
1910 | static struct spear_pingroup sata1_pingroup = { | 1922 | static struct spear_pingroup sata1_pingroup = { |
1911 | .name = "sata1_grp", | 1923 | .name = "sata1_grp", |
1912 | .pins = pci_sata_pins, | ||
1913 | .npins = ARRAY_SIZE(pci_sata_pins), | ||
1914 | .modemuxs = sata1_modemux, | 1924 | .modemuxs = sata1_modemux, |
1915 | .nmodemuxs = ARRAY_SIZE(sata1_modemux), | 1925 | .nmodemuxs = ARRAY_SIZE(sata1_modemux), |
1916 | }; | 1926 | }; |
1917 | 1927 | ||
1918 | /* pad multiplexing for sata2 device */ | 1928 | /* pad multiplexing for sata2 device */ |
1919 | static struct spear_muxreg sata2_muxreg[] = { | 1929 | static struct spear_muxreg sata2_muxreg[] = { |
1920 | PCI_SATA_MUXREG, | ||
1921 | { | 1930 | { |
1922 | .reg = PCIE_SATA_CFG, | 1931 | .reg = PCIE_SATA_CFG, |
1923 | .mask = SATA_CFG_VAL(2), | 1932 | .mask = SATA_CFG_VAL(2), |
@@ -1934,8 +1943,6 @@ static struct spear_modemux sata2_modemux[] = { | |||
1934 | 1943 | ||
1935 | static struct spear_pingroup sata2_pingroup = { | 1944 | static struct spear_pingroup sata2_pingroup = { |
1936 | .name = "sata2_grp", | 1945 | .name = "sata2_grp", |
1937 | .pins = pci_sata_pins, | ||
1938 | .npins = ARRAY_SIZE(pci_sata_pins), | ||
1939 | .modemuxs = sata2_modemux, | 1946 | .modemuxs = sata2_modemux, |
1940 | .nmodemuxs = ARRAY_SIZE(sata2_modemux), | 1947 | .nmodemuxs = ARRAY_SIZE(sata2_modemux), |
1941 | }; | 1948 | }; |
@@ -2093,6 +2100,7 @@ static struct spear_pingroup *spear1310_pingroups[] = { | |||
2093 | &can0_dis_sd_pingroup, | 2100 | &can0_dis_sd_pingroup, |
2094 | &can1_dis_sd_pingroup, | 2101 | &can1_dis_sd_pingroup, |
2095 | &can1_dis_kbd_pingroup, | 2102 | &can1_dis_kbd_pingroup, |
2103 | &pci_pingroup, | ||
2096 | &pcie0_pingroup, | 2104 | &pcie0_pingroup, |
2097 | &pcie1_pingroup, | 2105 | &pcie1_pingroup, |
2098 | &pcie2_pingroup, | 2106 | &pcie2_pingroup, |
@@ -2138,6 +2146,7 @@ static struct spear_function *spear1310_functions[] = { | |||
2138 | &can0_function, | 2146 | &can0_function, |
2139 | &can1_function, | 2147 | &can1_function, |
2140 | &pci_function, | 2148 | &pci_function, |
2149 | &pcie_function, | ||
2141 | &sata_function, | 2150 | &sata_function, |
2142 | &ssp1_function, | 2151 | &ssp1_function, |
2143 | &gpt64_function, | 2152 | &gpt64_function, |