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-rw-r--r--drivers/regulator/Makefile1
-rw-r--r--drivers/regulator/wm831x-ldo.c852
-rw-r--r--include/linux/mfd/wm831x/regulator.h626
3 files changed, 1479 insertions, 0 deletions
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index b1d2b826f532..a0a635fdae87 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_REGULATOR_LP3971) += lp3971.o
13obj-$(CONFIG_REGULATOR_MAX1586) += max1586.o 13obj-$(CONFIG_REGULATOR_MAX1586) += max1586.o
14obj-$(CONFIG_REGULATOR_TWL4030) += twl4030-regulator.o 14obj-$(CONFIG_REGULATOR_TWL4030) += twl4030-regulator.o
15obj-$(CONFIG_REGULATOR_WM831X) += wm831x-dcdc.o 15obj-$(CONFIG_REGULATOR_WM831X) += wm831x-dcdc.o
16obj-$(CONFIG_REGULATOR_WM831X) += wm831x-ldo.o
16obj-$(CONFIG_REGULATOR_WM8350) += wm8350-regulator.o 17obj-$(CONFIG_REGULATOR_WM8350) += wm8350-regulator.o
17obj-$(CONFIG_REGULATOR_WM8400) += wm8400-regulator.o 18obj-$(CONFIG_REGULATOR_WM8400) += wm8400-regulator.o
18obj-$(CONFIG_REGULATOR_DA903X) += da903x.o 19obj-$(CONFIG_REGULATOR_DA903X) += da903x.o
diff --git a/drivers/regulator/wm831x-ldo.c b/drivers/regulator/wm831x-ldo.c
new file mode 100644
index 000000000000..bb61aede4801
--- /dev/null
+++ b/drivers/regulator/wm831x-ldo.c
@@ -0,0 +1,852 @@
1/*
2 * wm831x-ldo.c -- LDO driver for the WM831x series
3 *
4 * Copyright 2009 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/bitops.h>
18#include <linux/err.h>
19#include <linux/i2c.h>
20#include <linux/platform_device.h>
21#include <linux/regulator/driver.h>
22
23#include <linux/mfd/wm831x/core.h>
24#include <linux/mfd/wm831x/regulator.h>
25#include <linux/mfd/wm831x/pdata.h>
26
27#define WM831X_LDO_MAX_NAME 6
28
29#define WM831X_LDO_CONTROL 0
30#define WM831X_LDO_ON_CONTROL 1
31#define WM831X_LDO_SLEEP_CONTROL 2
32
33#define WM831X_ALIVE_LDO_ON_CONTROL 0
34#define WM831X_ALIVE_LDO_SLEEP_CONTROL 1
35
36struct wm831x_ldo {
37 char name[WM831X_LDO_MAX_NAME];
38 struct regulator_desc desc;
39 int base;
40 struct wm831x *wm831x;
41 struct regulator_dev *regulator;
42};
43
44/*
45 * Shared
46 */
47
48static int wm831x_ldo_is_enabled(struct regulator_dev *rdev)
49{
50 struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
51 struct wm831x *wm831x = ldo->wm831x;
52 int mask = 1 << rdev_get_id(rdev);
53 int reg;
54
55 reg = wm831x_reg_read(wm831x, WM831X_LDO_ENABLE);
56 if (reg < 0)
57 return reg;
58
59 if (reg & mask)
60 return 1;
61 else
62 return 0;
63}
64
65static int wm831x_ldo_enable(struct regulator_dev *rdev)
66{
67 struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
68 struct wm831x *wm831x = ldo->wm831x;
69 int mask = 1 << rdev_get_id(rdev);
70
71 return wm831x_set_bits(wm831x, WM831X_LDO_ENABLE, mask, mask);
72}
73
74static int wm831x_ldo_disable(struct regulator_dev *rdev)
75{
76 struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
77 struct wm831x *wm831x = ldo->wm831x;
78 int mask = 1 << rdev_get_id(rdev);
79
80 return wm831x_set_bits(wm831x, WM831X_LDO_ENABLE, mask, 0);
81}
82
83static irqreturn_t wm831x_ldo_uv_irq(int irq, void *data)
84{
85 struct wm831x_ldo *ldo = data;
86
87 regulator_notifier_call_chain(ldo->regulator,
88 REGULATOR_EVENT_UNDER_VOLTAGE,
89 NULL);
90
91 return IRQ_HANDLED;
92}
93
94/*
95 * General purpose LDOs
96 */
97
98#define WM831X_GP_LDO_SELECTOR_LOW 0xe
99#define WM831X_GP_LDO_MAX_SELECTOR 0x1f
100
101static int wm831x_gp_ldo_list_voltage(struct regulator_dev *rdev,
102 unsigned int selector)
103{
104 /* 0.9-1.6V in 50mV steps */
105 if (selector <= WM831X_GP_LDO_SELECTOR_LOW)
106 return 900000 + (selector * 50000);
107 /* 1.7-3.3V in 50mV steps */
108 if (selector <= WM831X_GP_LDO_MAX_SELECTOR)
109 return 1600000 + ((selector - WM831X_GP_LDO_SELECTOR_LOW)
110 * 100000);
111 return -EINVAL;
112}
113
114static int wm831x_gp_ldo_set_voltage_int(struct regulator_dev *rdev, int reg,
115 int min_uV, int max_uV)
116{
117 struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
118 struct wm831x *wm831x = ldo->wm831x;
119 int vsel, ret;
120
121 if (min_uV < 900000)
122 vsel = 0;
123 else if (min_uV < 1700000)
124 vsel = ((min_uV - 900000) / 50000);
125 else
126 vsel = ((min_uV - 1700000) / 100000)
127 + WM831X_GP_LDO_SELECTOR_LOW + 1;
128
129 ret = wm831x_gp_ldo_list_voltage(rdev, vsel);
130 if (ret < 0)
131 return ret;
132 if (ret < min_uV || ret > max_uV)
133 return -EINVAL;
134
135 return wm831x_set_bits(wm831x, reg, WM831X_LDO1_ON_VSEL_MASK, vsel);
136}
137
138static int wm831x_gp_ldo_set_voltage(struct regulator_dev *rdev,
139 int min_uV, int max_uV)
140{
141 struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
142 int reg = ldo->base + WM831X_LDO_ON_CONTROL;
143
144 return wm831x_gp_ldo_set_voltage_int(rdev, reg, min_uV, max_uV);
145}
146
147static int wm831x_gp_ldo_set_suspend_voltage(struct regulator_dev *rdev,
148 int uV)
149{
150 struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
151 int reg = ldo->base + WM831X_LDO_SLEEP_CONTROL;
152
153 return wm831x_gp_ldo_set_voltage_int(rdev, reg, uV, uV);
154}
155
156static int wm831x_gp_ldo_get_voltage(struct regulator_dev *rdev)
157{
158 struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
159 struct wm831x *wm831x = ldo->wm831x;
160 int reg = ldo->base + WM831X_LDO_ON_CONTROL;
161 int ret;
162
163 ret = wm831x_reg_read(wm831x, reg);
164 if (ret < 0)
165 return ret;
166
167 ret &= WM831X_LDO1_ON_VSEL_MASK;
168
169 return wm831x_gp_ldo_list_voltage(rdev, ret);
170}
171
172static unsigned int wm831x_gp_ldo_get_mode(struct regulator_dev *rdev)
173{
174 struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
175 struct wm831x *wm831x = ldo->wm831x;
176 int ctrl_reg = ldo->base + WM831X_LDO_CONTROL;
177 int on_reg = ldo->base + WM831X_LDO_ON_CONTROL;
178 unsigned int ret;
179
180 ret = wm831x_reg_read(wm831x, on_reg);
181 if (ret < 0)
182 return 0;
183
184 if (!(ret & WM831X_LDO1_ON_MODE))
185 return REGULATOR_MODE_NORMAL;
186
187 ret = wm831x_reg_read(wm831x, ctrl_reg);
188 if (ret < 0)
189 return 0;
190
191 if (ret & WM831X_LDO1_LP_MODE)
192 return REGULATOR_MODE_STANDBY;
193 else
194 return REGULATOR_MODE_IDLE;
195}
196
197static int wm831x_gp_ldo_set_mode(struct regulator_dev *rdev,
198 unsigned int mode)
199{
200 struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
201 struct wm831x *wm831x = ldo->wm831x;
202 int ctrl_reg = ldo->base + WM831X_LDO_CONTROL;
203 int on_reg = ldo->base + WM831X_LDO_ON_CONTROL;
204 int ret;
205
206
207 switch (mode) {
208 case REGULATOR_MODE_NORMAL:
209 ret = wm831x_set_bits(wm831x, on_reg,
210 WM831X_LDO1_ON_MODE, 0);
211 if (ret < 0)
212 return ret;
213 break;
214
215 case REGULATOR_MODE_IDLE:
216 ret = wm831x_set_bits(wm831x, ctrl_reg,
217 WM831X_LDO1_LP_MODE,
218 WM831X_LDO1_LP_MODE);
219 if (ret < 0)
220 return ret;
221
222 ret = wm831x_set_bits(wm831x, on_reg,
223 WM831X_LDO1_ON_MODE,
224 WM831X_LDO1_ON_MODE);
225 if (ret < 0)
226 return ret;
227
228 case REGULATOR_MODE_STANDBY:
229 ret = wm831x_set_bits(wm831x, ctrl_reg,
230 WM831X_LDO1_LP_MODE, 0);
231 if (ret < 0)
232 return ret;
233
234 ret = wm831x_set_bits(wm831x, on_reg,
235 WM831X_LDO1_ON_MODE,
236 WM831X_LDO1_ON_MODE);
237 if (ret < 0)
238 return ret;
239 break;
240
241 default:
242 return -EINVAL;
243 }
244
245 return 0;
246}
247
248static int wm831x_gp_ldo_get_status(struct regulator_dev *rdev)
249{
250 struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
251 struct wm831x *wm831x = ldo->wm831x;
252 int mask = 1 << rdev_get_id(rdev);
253 int ret;
254
255 /* Is the regulator on? */
256 ret = wm831x_reg_read(wm831x, WM831X_LDO_STATUS);
257 if (ret < 0)
258 return ret;
259 if (!(ret & mask))
260 return REGULATOR_STATUS_OFF;
261
262 /* Is it reporting under voltage? */
263 ret = wm831x_reg_read(wm831x, WM831X_LDO_UV_STATUS);
264 if (ret & mask)
265 return REGULATOR_STATUS_ERROR;
266
267 ret = wm831x_gp_ldo_get_mode(rdev);
268 if (ret < 0)
269 return ret;
270 else
271 return regulator_mode_to_status(ret);
272}
273
274static unsigned int wm831x_gp_ldo_get_optimum_mode(struct regulator_dev *rdev,
275 int input_uV,
276 int output_uV, int load_uA)
277{
278 if (load_uA < 20000)
279 return REGULATOR_MODE_STANDBY;
280 if (load_uA < 50000)
281 return REGULATOR_MODE_IDLE;
282 return REGULATOR_MODE_NORMAL;
283}
284
285
286static struct regulator_ops wm831x_gp_ldo_ops = {
287 .list_voltage = wm831x_gp_ldo_list_voltage,
288 .get_voltage = wm831x_gp_ldo_get_voltage,
289 .set_voltage = wm831x_gp_ldo_set_voltage,
290 .set_suspend_voltage = wm831x_gp_ldo_set_suspend_voltage,
291 .get_mode = wm831x_gp_ldo_get_mode,
292 .set_mode = wm831x_gp_ldo_set_mode,
293 .get_status = wm831x_gp_ldo_get_status,
294 .get_optimum_mode = wm831x_gp_ldo_get_optimum_mode,
295
296 .is_enabled = wm831x_ldo_is_enabled,
297 .enable = wm831x_ldo_enable,
298 .disable = wm831x_ldo_disable,
299};
300
301static __devinit int wm831x_gp_ldo_probe(struct platform_device *pdev)
302{
303 struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);
304 struct wm831x_pdata *pdata = wm831x->dev->platform_data;
305 int id = pdev->id % ARRAY_SIZE(pdata->ldo);
306 struct wm831x_ldo *ldo;
307 struct resource *res;
308 int ret, irq;
309
310 dev_dbg(&pdev->dev, "Probing LDO%d\n", id + 1);
311
312 if (pdata == NULL || pdata->ldo[id] == NULL)
313 return -ENODEV;
314
315 ldo = kzalloc(sizeof(struct wm831x_ldo), GFP_KERNEL);
316 if (ldo == NULL) {
317 dev_err(&pdev->dev, "Unable to allocate private data\n");
318 return -ENOMEM;
319 }
320
321 ldo->wm831x = wm831x;
322
323 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
324 if (res == NULL) {
325 dev_err(&pdev->dev, "No I/O resource\n");
326 ret = -EINVAL;
327 goto err;
328 }
329 ldo->base = res->start;
330
331 snprintf(ldo->name, sizeof(ldo->name), "LDO%d", id + 1);
332 ldo->desc.name = ldo->name;
333 ldo->desc.id = id;
334 ldo->desc.type = REGULATOR_VOLTAGE;
335 ldo->desc.n_voltages = WM831X_GP_LDO_MAX_SELECTOR + 1;
336 ldo->desc.ops = &wm831x_gp_ldo_ops;
337 ldo->desc.owner = THIS_MODULE;
338
339 ldo->regulator = regulator_register(&ldo->desc, &pdev->dev,
340 pdata->ldo[id], ldo);
341 if (IS_ERR(ldo->regulator)) {
342 ret = PTR_ERR(ldo->regulator);
343 dev_err(wm831x->dev, "Failed to register LDO%d: %d\n",
344 id + 1, ret);
345 goto err;
346 }
347
348 irq = platform_get_irq_byname(pdev, "UV");
349 ret = wm831x_request_irq(wm831x, irq, wm831x_ldo_uv_irq,
350 IRQF_TRIGGER_RISING, ldo->name,
351 ldo);
352 if (ret != 0) {
353 dev_err(&pdev->dev, "Failed to request UV IRQ %d: %d\n",
354 irq, ret);
355 goto err_regulator;
356 }
357
358 platform_set_drvdata(pdev, ldo);
359
360 return 0;
361
362err_regulator:
363 regulator_unregister(ldo->regulator);
364err:
365 kfree(ldo);
366 return ret;
367}
368
369static __devexit int wm831x_gp_ldo_remove(struct platform_device *pdev)
370{
371 struct wm831x_ldo *ldo = platform_get_drvdata(pdev);
372 struct wm831x *wm831x = ldo->wm831x;
373
374 wm831x_free_irq(wm831x, platform_get_irq_byname(pdev, "UV"), ldo);
375 regulator_unregister(ldo->regulator);
376 kfree(ldo);
377
378 return 0;
379}
380
381static struct platform_driver wm831x_gp_ldo_driver = {
382 .probe = wm831x_gp_ldo_probe,
383 .remove = __devexit_p(wm831x_gp_ldo_remove),
384 .driver = {
385 .name = "wm831x-ldo",
386 },
387};
388
389/*
390 * Analogue LDOs
391 */
392
393
394#define WM831X_ALDO_SELECTOR_LOW 0xc
395#define WM831X_ALDO_MAX_SELECTOR 0x1f
396
397static int wm831x_aldo_list_voltage(struct regulator_dev *rdev,
398 unsigned int selector)
399{
400 /* 1-1.6V in 50mV steps */
401 if (selector <= WM831X_ALDO_SELECTOR_LOW)
402 return 1000000 + (selector * 50000);
403 /* 1.7-3.5V in 50mV steps */
404 if (selector <= WM831X_ALDO_MAX_SELECTOR)
405 return 1600000 + ((selector - WM831X_ALDO_SELECTOR_LOW)
406 * 100000);
407 return -EINVAL;
408}
409
410static int wm831x_aldo_set_voltage_int(struct regulator_dev *rdev, int reg,
411 int min_uV, int max_uV)
412{
413 struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
414 struct wm831x *wm831x = ldo->wm831x;
415 int vsel, ret;
416
417 if (min_uV < 1000000)
418 vsel = 0;
419 else if (min_uV < 1700000)
420 vsel = ((min_uV - 1000000) / 50000);
421 else
422 vsel = ((min_uV - 1700000) / 100000)
423 + WM831X_ALDO_SELECTOR_LOW + 1;
424
425 ret = wm831x_aldo_list_voltage(rdev, vsel);
426 if (ret < 0)
427 return ret;
428 if (ret < min_uV || ret > max_uV)
429 return -EINVAL;
430
431 return wm831x_set_bits(wm831x, reg, WM831X_LDO7_ON_VSEL_MASK, vsel);
432}
433
434static int wm831x_aldo_set_voltage(struct regulator_dev *rdev,
435 int min_uV, int max_uV)
436{
437 struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
438 int reg = ldo->base + WM831X_LDO_ON_CONTROL;
439
440 return wm831x_aldo_set_voltage_int(rdev, reg, min_uV, max_uV);
441}
442
443static int wm831x_aldo_set_suspend_voltage(struct regulator_dev *rdev,
444 int uV)
445{
446 struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
447 int reg = ldo->base + WM831X_LDO_SLEEP_CONTROL;
448
449 return wm831x_aldo_set_voltage_int(rdev, reg, uV, uV);
450}
451
452static int wm831x_aldo_get_voltage(struct regulator_dev *rdev)
453{
454 struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
455 struct wm831x *wm831x = ldo->wm831x;
456 int reg = ldo->base + WM831X_LDO_ON_CONTROL;
457 int ret;
458
459 ret = wm831x_reg_read(wm831x, reg);
460 if (ret < 0)
461 return ret;
462
463 ret &= WM831X_LDO7_ON_VSEL_MASK;
464
465 return wm831x_aldo_list_voltage(rdev, ret);
466}
467
468static unsigned int wm831x_aldo_get_mode(struct regulator_dev *rdev)
469{
470 struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
471 struct wm831x *wm831x = ldo->wm831x;
472 int on_reg = ldo->base + WM831X_LDO_ON_CONTROL;
473 unsigned int ret;
474
475 ret = wm831x_reg_read(wm831x, on_reg);
476 if (ret < 0)
477 return 0;
478
479 if (ret & WM831X_LDO7_ON_MODE)
480 return REGULATOR_MODE_IDLE;
481 else
482 return REGULATOR_MODE_NORMAL;
483}
484
485static int wm831x_aldo_set_mode(struct regulator_dev *rdev,
486 unsigned int mode)
487{
488 struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
489 struct wm831x *wm831x = ldo->wm831x;
490 int ctrl_reg = ldo->base + WM831X_LDO_CONTROL;
491 int on_reg = ldo->base + WM831X_LDO_ON_CONTROL;
492 int ret;
493
494
495 switch (mode) {
496 case REGULATOR_MODE_NORMAL:
497 ret = wm831x_set_bits(wm831x, on_reg,
498 WM831X_LDO7_ON_MODE, 0);
499 if (ret < 0)
500 return ret;
501 break;
502
503 case REGULATOR_MODE_IDLE:
504 ret = wm831x_set_bits(wm831x, ctrl_reg,
505 WM831X_LDO7_ON_MODE,
506 WM831X_LDO7_ON_MODE);
507 if (ret < 0)
508 return ret;
509 break;
510
511 default:
512 return -EINVAL;
513 }
514
515 return 0;
516}
517
518static int wm831x_aldo_get_status(struct regulator_dev *rdev)
519{
520 struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
521 struct wm831x *wm831x = ldo->wm831x;
522 int mask = 1 << rdev_get_id(rdev);
523 int ret;
524
525 /* Is the regulator on? */
526 ret = wm831x_reg_read(wm831x, WM831X_LDO_STATUS);
527 if (ret < 0)
528 return ret;
529 if (!(ret & mask))
530 return REGULATOR_STATUS_OFF;
531
532 /* Is it reporting under voltage? */
533 ret = wm831x_reg_read(wm831x, WM831X_LDO_UV_STATUS);
534 if (ret & mask)
535 return REGULATOR_STATUS_ERROR;
536
537 ret = wm831x_aldo_get_mode(rdev);
538 if (ret < 0)
539 return ret;
540 else
541 return regulator_mode_to_status(ret);
542}
543
544static struct regulator_ops wm831x_aldo_ops = {
545 .list_voltage = wm831x_aldo_list_voltage,
546 .get_voltage = wm831x_aldo_get_voltage,
547 .set_voltage = wm831x_aldo_set_voltage,
548 .set_suspend_voltage = wm831x_aldo_set_suspend_voltage,
549 .get_mode = wm831x_aldo_get_mode,
550 .set_mode = wm831x_aldo_set_mode,
551 .get_status = wm831x_aldo_get_status,
552
553 .is_enabled = wm831x_ldo_is_enabled,
554 .enable = wm831x_ldo_enable,
555 .disable = wm831x_ldo_disable,
556};
557
558static __devinit int wm831x_aldo_probe(struct platform_device *pdev)
559{
560 struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);
561 struct wm831x_pdata *pdata = wm831x->dev->platform_data;
562 int id = pdev->id % ARRAY_SIZE(pdata->ldo);
563 struct wm831x_ldo *ldo;
564 struct resource *res;
565 int ret, irq;
566
567 dev_dbg(&pdev->dev, "Probing LDO%d\n", id + 1);
568
569 if (pdata == NULL || pdata->ldo[id] == NULL)
570 return -ENODEV;
571
572 ldo = kzalloc(sizeof(struct wm831x_ldo), GFP_KERNEL);
573 if (ldo == NULL) {
574 dev_err(&pdev->dev, "Unable to allocate private data\n");
575 return -ENOMEM;
576 }
577
578 ldo->wm831x = wm831x;
579
580 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
581 if (res == NULL) {
582 dev_err(&pdev->dev, "No I/O resource\n");
583 ret = -EINVAL;
584 goto err;
585 }
586 ldo->base = res->start;
587
588 snprintf(ldo->name, sizeof(ldo->name), "LDO%d", id + 1);
589 ldo->desc.name = ldo->name;
590 ldo->desc.id = id;
591 ldo->desc.type = REGULATOR_VOLTAGE;
592 ldo->desc.n_voltages = WM831X_ALDO_MAX_SELECTOR + 1;
593 ldo->desc.ops = &wm831x_aldo_ops;
594 ldo->desc.owner = THIS_MODULE;
595
596 ldo->regulator = regulator_register(&ldo->desc, &pdev->dev,
597 pdata->ldo[id], ldo);
598 if (IS_ERR(ldo->regulator)) {
599 ret = PTR_ERR(ldo->regulator);
600 dev_err(wm831x->dev, "Failed to register LDO%d: %d\n",
601 id + 1, ret);
602 goto err;
603 }
604
605 irq = platform_get_irq_byname(pdev, "UV");
606 ret = wm831x_request_irq(wm831x, irq, wm831x_ldo_uv_irq,
607 IRQF_TRIGGER_RISING, ldo->name,
608 ldo);
609 if (ret != 0) {
610 dev_err(&pdev->dev, "Failed to request UV IRQ %d: %d\n",
611 irq, ret);
612 goto err_regulator;
613 }
614
615 platform_set_drvdata(pdev, ldo);
616
617 return 0;
618
619err_regulator:
620 regulator_unregister(ldo->regulator);
621err:
622 kfree(ldo);
623 return ret;
624}
625
626static __devexit int wm831x_aldo_remove(struct platform_device *pdev)
627{
628 struct wm831x_ldo *ldo = platform_get_drvdata(pdev);
629 struct wm831x *wm831x = ldo->wm831x;
630
631 wm831x_free_irq(wm831x, platform_get_irq_byname(pdev, "UV"), ldo);
632 regulator_unregister(ldo->regulator);
633 kfree(ldo);
634
635 return 0;
636}
637
638static struct platform_driver wm831x_aldo_driver = {
639 .probe = wm831x_aldo_probe,
640 .remove = __devexit_p(wm831x_aldo_remove),
641 .driver = {
642 .name = "wm831x-aldo",
643 },
644};
645
646/*
647 * Alive LDO
648 */
649
650#define WM831X_ALIVE_LDO_MAX_SELECTOR 0xf
651
652static int wm831x_alive_ldo_list_voltage(struct regulator_dev *rdev,
653 unsigned int selector)
654{
655 /* 0.8-1.55V in 50mV steps */
656 if (selector <= WM831X_ALIVE_LDO_MAX_SELECTOR)
657 return 800000 + (selector * 50000);
658 return -EINVAL;
659}
660
661static int wm831x_alive_ldo_set_voltage_int(struct regulator_dev *rdev,
662 int reg,
663 int min_uV, int max_uV)
664{
665 struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
666 struct wm831x *wm831x = ldo->wm831x;
667 int vsel, ret;
668
669 vsel = (min_uV - 800000) / 50000;
670
671 ret = wm831x_alive_ldo_list_voltage(rdev, vsel);
672 if (ret < 0)
673 return ret;
674 if (ret < min_uV || ret > max_uV)
675 return -EINVAL;
676
677 return wm831x_set_bits(wm831x, reg, WM831X_LDO11_ON_VSEL_MASK, vsel);
678}
679
680static int wm831x_alive_ldo_set_voltage(struct regulator_dev *rdev,
681 int min_uV, int max_uV)
682{
683 struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
684 int reg = ldo->base + WM831X_ALIVE_LDO_ON_CONTROL;
685
686 return wm831x_alive_ldo_set_voltage_int(rdev, reg, min_uV, max_uV);
687}
688
689static int wm831x_alive_ldo_set_suspend_voltage(struct regulator_dev *rdev,
690 int uV)
691{
692 struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
693 int reg = ldo->base + WM831X_ALIVE_LDO_SLEEP_CONTROL;
694
695 return wm831x_alive_ldo_set_voltage_int(rdev, reg, uV, uV);
696}
697
698static int wm831x_alive_ldo_get_voltage(struct regulator_dev *rdev)
699{
700 struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
701 struct wm831x *wm831x = ldo->wm831x;
702 int reg = ldo->base + WM831X_ALIVE_LDO_ON_CONTROL;
703 int ret;
704
705 ret = wm831x_reg_read(wm831x, reg);
706 if (ret < 0)
707 return ret;
708
709 ret &= WM831X_LDO11_ON_VSEL_MASK;
710
711 return wm831x_alive_ldo_list_voltage(rdev, ret);
712}
713
714static int wm831x_alive_ldo_get_status(struct regulator_dev *rdev)
715{
716 struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
717 struct wm831x *wm831x = ldo->wm831x;
718 int mask = 1 << rdev_get_id(rdev);
719 int ret;
720
721 /* Is the regulator on? */
722 ret = wm831x_reg_read(wm831x, WM831X_LDO_STATUS);
723 if (ret < 0)
724 return ret;
725 if (ret & mask)
726 return REGULATOR_STATUS_ON;
727 else
728 return REGULATOR_STATUS_OFF;
729}
730
731static struct regulator_ops wm831x_alive_ldo_ops = {
732 .list_voltage = wm831x_alive_ldo_list_voltage,
733 .get_voltage = wm831x_alive_ldo_get_voltage,
734 .set_voltage = wm831x_alive_ldo_set_voltage,
735 .set_suspend_voltage = wm831x_alive_ldo_set_suspend_voltage,
736 .get_status = wm831x_alive_ldo_get_status,
737
738 .is_enabled = wm831x_ldo_is_enabled,
739 .enable = wm831x_ldo_enable,
740 .disable = wm831x_ldo_disable,
741};
742
743static __devinit int wm831x_alive_ldo_probe(struct platform_device *pdev)
744{
745 struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);
746 struct wm831x_pdata *pdata = wm831x->dev->platform_data;
747 int id = pdev->id % ARRAY_SIZE(pdata->ldo);
748 struct wm831x_ldo *ldo;
749 struct resource *res;
750 int ret;
751
752 dev_dbg(&pdev->dev, "Probing LDO%d\n", id + 1);
753
754 if (pdata == NULL || pdata->ldo[id] == NULL)
755 return -ENODEV;
756
757 ldo = kzalloc(sizeof(struct wm831x_ldo), GFP_KERNEL);
758 if (ldo == NULL) {
759 dev_err(&pdev->dev, "Unable to allocate private data\n");
760 return -ENOMEM;
761 }
762
763 ldo->wm831x = wm831x;
764
765 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
766 if (res == NULL) {
767 dev_err(&pdev->dev, "No I/O resource\n");
768 ret = -EINVAL;
769 goto err;
770 }
771 ldo->base = res->start;
772
773 snprintf(ldo->name, sizeof(ldo->name), "LDO%d", id + 1);
774 ldo->desc.name = ldo->name;
775 ldo->desc.id = id;
776 ldo->desc.type = REGULATOR_VOLTAGE;
777 ldo->desc.n_voltages = WM831X_ALIVE_LDO_MAX_SELECTOR + 1;
778 ldo->desc.ops = &wm831x_alive_ldo_ops;
779 ldo->desc.owner = THIS_MODULE;
780
781 ldo->regulator = regulator_register(&ldo->desc, &pdev->dev,
782 pdata->ldo[id], ldo);
783 if (IS_ERR(ldo->regulator)) {
784 ret = PTR_ERR(ldo->regulator);
785 dev_err(wm831x->dev, "Failed to register LDO%d: %d\n",
786 id + 1, ret);
787 goto err;
788 }
789
790 platform_set_drvdata(pdev, ldo);
791
792 return 0;
793
794err:
795 kfree(ldo);
796 return ret;
797}
798
799static __devexit int wm831x_alive_ldo_remove(struct platform_device *pdev)
800{
801 struct wm831x_ldo *ldo = platform_get_drvdata(pdev);
802
803 regulator_unregister(ldo->regulator);
804 kfree(ldo);
805
806 return 0;
807}
808
809static struct platform_driver wm831x_alive_ldo_driver = {
810 .probe = wm831x_alive_ldo_probe,
811 .remove = __devexit_p(wm831x_alive_ldo_remove),
812 .driver = {
813 .name = "wm831x-alive-ldo",
814 },
815};
816
817static int __init wm831x_ldo_init(void)
818{
819 int ret;
820
821 ret = platform_driver_register(&wm831x_gp_ldo_driver);
822 if (ret != 0)
823 pr_err("Failed to register WM831x GP LDO driver: %d\n", ret);
824
825 ret = platform_driver_register(&wm831x_aldo_driver);
826 if (ret != 0)
827 pr_err("Failed to register WM831x ALDO driver: %d\n", ret);
828
829 ret = platform_driver_register(&wm831x_alive_ldo_driver);
830 if (ret != 0)
831 pr_err("Failed to register WM831x alive LDO driver: %d\n",
832 ret);
833
834 return 0;
835}
836subsys_initcall(wm831x_ldo_init);
837
838static void __exit wm831x_ldo_exit(void)
839{
840 platform_driver_unregister(&wm831x_alive_ldo_driver);
841 platform_driver_unregister(&wm831x_aldo_driver);
842 platform_driver_unregister(&wm831x_gp_ldo_driver);
843}
844module_exit(wm831x_ldo_exit);
845
846/* Module information */
847MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
848MODULE_DESCRIPTION("WM831x LDO driver");
849MODULE_LICENSE("GPL");
850MODULE_ALIAS("platform:wm831x-ldo");
851MODULE_ALIAS("platform:wm831x-aldo");
852MODULE_ALIAS("platform:wm831x-aliveldo");
diff --git a/include/linux/mfd/wm831x/regulator.h b/include/linux/mfd/wm831x/regulator.h
index c74d6aafdca8..f95466343fb2 100644
--- a/include/linux/mfd/wm831x/regulator.h
+++ b/include/linux/mfd/wm831x/regulator.h
@@ -567,6 +567,588 @@
567#define WM831X_DC4_SLPENA_WIDTH 1 /* DC4_SLPENA */ 567#define WM831X_DC4_SLPENA_WIDTH 1 /* DC4_SLPENA */
568 568
569/* 569/*
570 * R16488 (0x4068) - LDO1 Control
571 */
572#define WM831X_LDO1_ERR_ACT_MASK 0xC000 /* LDO1_ERR_ACT - [15:14] */
573#define WM831X_LDO1_ERR_ACT_SHIFT 14 /* LDO1_ERR_ACT - [15:14] */
574#define WM831X_LDO1_ERR_ACT_WIDTH 2 /* LDO1_ERR_ACT - [15:14] */
575#define WM831X_LDO1_HWC_SRC_MASK 0x1800 /* LDO1_HWC_SRC - [12:11] */
576#define WM831X_LDO1_HWC_SRC_SHIFT 11 /* LDO1_HWC_SRC - [12:11] */
577#define WM831X_LDO1_HWC_SRC_WIDTH 2 /* LDO1_HWC_SRC - [12:11] */
578#define WM831X_LDO1_HWC_VSEL 0x0400 /* LDO1_HWC_VSEL */
579#define WM831X_LDO1_HWC_VSEL_MASK 0x0400 /* LDO1_HWC_VSEL */
580#define WM831X_LDO1_HWC_VSEL_SHIFT 10 /* LDO1_HWC_VSEL */
581#define WM831X_LDO1_HWC_VSEL_WIDTH 1 /* LDO1_HWC_VSEL */
582#define WM831X_LDO1_HWC_MODE_MASK 0x0300 /* LDO1_HWC_MODE - [9:8] */
583#define WM831X_LDO1_HWC_MODE_SHIFT 8 /* LDO1_HWC_MODE - [9:8] */
584#define WM831X_LDO1_HWC_MODE_WIDTH 2 /* LDO1_HWC_MODE - [9:8] */
585#define WM831X_LDO1_FLT 0x0080 /* LDO1_FLT */
586#define WM831X_LDO1_FLT_MASK 0x0080 /* LDO1_FLT */
587#define WM831X_LDO1_FLT_SHIFT 7 /* LDO1_FLT */
588#define WM831X_LDO1_FLT_WIDTH 1 /* LDO1_FLT */
589#define WM831X_LDO1_SWI 0x0040 /* LDO1_SWI */
590#define WM831X_LDO1_SWI_MASK 0x0040 /* LDO1_SWI */
591#define WM831X_LDO1_SWI_SHIFT 6 /* LDO1_SWI */
592#define WM831X_LDO1_SWI_WIDTH 1 /* LDO1_SWI */
593#define WM831X_LDO1_LP_MODE 0x0001 /* LDO1_LP_MODE */
594#define WM831X_LDO1_LP_MODE_MASK 0x0001 /* LDO1_LP_MODE */
595#define WM831X_LDO1_LP_MODE_SHIFT 0 /* LDO1_LP_MODE */
596#define WM831X_LDO1_LP_MODE_WIDTH 1 /* LDO1_LP_MODE */
597
598/*
599 * R16489 (0x4069) - LDO1 ON Control
600 */
601#define WM831X_LDO1_ON_SLOT_MASK 0xE000 /* LDO1_ON_SLOT - [15:13] */
602#define WM831X_LDO1_ON_SLOT_SHIFT 13 /* LDO1_ON_SLOT - [15:13] */
603#define WM831X_LDO1_ON_SLOT_WIDTH 3 /* LDO1_ON_SLOT - [15:13] */
604#define WM831X_LDO1_ON_MODE 0x0100 /* LDO1_ON_MODE */
605#define WM831X_LDO1_ON_MODE_MASK 0x0100 /* LDO1_ON_MODE */
606#define WM831X_LDO1_ON_MODE_SHIFT 8 /* LDO1_ON_MODE */
607#define WM831X_LDO1_ON_MODE_WIDTH 1 /* LDO1_ON_MODE */
608#define WM831X_LDO1_ON_VSEL_MASK 0x001F /* LDO1_ON_VSEL - [4:0] */
609#define WM831X_LDO1_ON_VSEL_SHIFT 0 /* LDO1_ON_VSEL - [4:0] */
610#define WM831X_LDO1_ON_VSEL_WIDTH 5 /* LDO1_ON_VSEL - [4:0] */
611
612/*
613 * R16490 (0x406A) - LDO1 SLEEP Control
614 */
615#define WM831X_LDO1_SLP_SLOT_MASK 0xE000 /* LDO1_SLP_SLOT - [15:13] */
616#define WM831X_LDO1_SLP_SLOT_SHIFT 13 /* LDO1_SLP_SLOT - [15:13] */
617#define WM831X_LDO1_SLP_SLOT_WIDTH 3 /* LDO1_SLP_SLOT - [15:13] */
618#define WM831X_LDO1_SLP_MODE 0x0100 /* LDO1_SLP_MODE */
619#define WM831X_LDO1_SLP_MODE_MASK 0x0100 /* LDO1_SLP_MODE */
620#define WM831X_LDO1_SLP_MODE_SHIFT 8 /* LDO1_SLP_MODE */
621#define WM831X_LDO1_SLP_MODE_WIDTH 1 /* LDO1_SLP_MODE */
622#define WM831X_LDO1_SLP_VSEL_MASK 0x001F /* LDO1_SLP_VSEL - [4:0] */
623#define WM831X_LDO1_SLP_VSEL_SHIFT 0 /* LDO1_SLP_VSEL - [4:0] */
624#define WM831X_LDO1_SLP_VSEL_WIDTH 5 /* LDO1_SLP_VSEL - [4:0] */
625
626/*
627 * R16491 (0x406B) - LDO2 Control
628 */
629#define WM831X_LDO2_ERR_ACT_MASK 0xC000 /* LDO2_ERR_ACT - [15:14] */
630#define WM831X_LDO2_ERR_ACT_SHIFT 14 /* LDO2_ERR_ACT - [15:14] */
631#define WM831X_LDO2_ERR_ACT_WIDTH 2 /* LDO2_ERR_ACT - [15:14] */
632#define WM831X_LDO2_HWC_SRC_MASK 0x1800 /* LDO2_HWC_SRC - [12:11] */
633#define WM831X_LDO2_HWC_SRC_SHIFT 11 /* LDO2_HWC_SRC - [12:11] */
634#define WM831X_LDO2_HWC_SRC_WIDTH 2 /* LDO2_HWC_SRC - [12:11] */
635#define WM831X_LDO2_HWC_VSEL 0x0400 /* LDO2_HWC_VSEL */
636#define WM831X_LDO2_HWC_VSEL_MASK 0x0400 /* LDO2_HWC_VSEL */
637#define WM831X_LDO2_HWC_VSEL_SHIFT 10 /* LDO2_HWC_VSEL */
638#define WM831X_LDO2_HWC_VSEL_WIDTH 1 /* LDO2_HWC_VSEL */
639#define WM831X_LDO2_HWC_MODE_MASK 0x0300 /* LDO2_HWC_MODE - [9:8] */
640#define WM831X_LDO2_HWC_MODE_SHIFT 8 /* LDO2_HWC_MODE - [9:8] */
641#define WM831X_LDO2_HWC_MODE_WIDTH 2 /* LDO2_HWC_MODE - [9:8] */
642#define WM831X_LDO2_FLT 0x0080 /* LDO2_FLT */
643#define WM831X_LDO2_FLT_MASK 0x0080 /* LDO2_FLT */
644#define WM831X_LDO2_FLT_SHIFT 7 /* LDO2_FLT */
645#define WM831X_LDO2_FLT_WIDTH 1 /* LDO2_FLT */
646#define WM831X_LDO2_SWI 0x0040 /* LDO2_SWI */
647#define WM831X_LDO2_SWI_MASK 0x0040 /* LDO2_SWI */
648#define WM831X_LDO2_SWI_SHIFT 6 /* LDO2_SWI */
649#define WM831X_LDO2_SWI_WIDTH 1 /* LDO2_SWI */
650#define WM831X_LDO2_LP_MODE 0x0001 /* LDO2_LP_MODE */
651#define WM831X_LDO2_LP_MODE_MASK 0x0001 /* LDO2_LP_MODE */
652#define WM831X_LDO2_LP_MODE_SHIFT 0 /* LDO2_LP_MODE */
653#define WM831X_LDO2_LP_MODE_WIDTH 1 /* LDO2_LP_MODE */
654
655/*
656 * R16492 (0x406C) - LDO2 ON Control
657 */
658#define WM831X_LDO2_ON_SLOT_MASK 0xE000 /* LDO2_ON_SLOT - [15:13] */
659#define WM831X_LDO2_ON_SLOT_SHIFT 13 /* LDO2_ON_SLOT - [15:13] */
660#define WM831X_LDO2_ON_SLOT_WIDTH 3 /* LDO2_ON_SLOT - [15:13] */
661#define WM831X_LDO2_ON_MODE 0x0100 /* LDO2_ON_MODE */
662#define WM831X_LDO2_ON_MODE_MASK 0x0100 /* LDO2_ON_MODE */
663#define WM831X_LDO2_ON_MODE_SHIFT 8 /* LDO2_ON_MODE */
664#define WM831X_LDO2_ON_MODE_WIDTH 1 /* LDO2_ON_MODE */
665#define WM831X_LDO2_ON_VSEL_MASK 0x001F /* LDO2_ON_VSEL - [4:0] */
666#define WM831X_LDO2_ON_VSEL_SHIFT 0 /* LDO2_ON_VSEL - [4:0] */
667#define WM831X_LDO2_ON_VSEL_WIDTH 5 /* LDO2_ON_VSEL - [4:0] */
668
669/*
670 * R16493 (0x406D) - LDO2 SLEEP Control
671 */
672#define WM831X_LDO2_SLP_SLOT_MASK 0xE000 /* LDO2_SLP_SLOT - [15:13] */
673#define WM831X_LDO2_SLP_SLOT_SHIFT 13 /* LDO2_SLP_SLOT - [15:13] */
674#define WM831X_LDO2_SLP_SLOT_WIDTH 3 /* LDO2_SLP_SLOT - [15:13] */
675#define WM831X_LDO2_SLP_MODE 0x0100 /* LDO2_SLP_MODE */
676#define WM831X_LDO2_SLP_MODE_MASK 0x0100 /* LDO2_SLP_MODE */
677#define WM831X_LDO2_SLP_MODE_SHIFT 8 /* LDO2_SLP_MODE */
678#define WM831X_LDO2_SLP_MODE_WIDTH 1 /* LDO2_SLP_MODE */
679#define WM831X_LDO2_SLP_VSEL_MASK 0x001F /* LDO2_SLP_VSEL - [4:0] */
680#define WM831X_LDO2_SLP_VSEL_SHIFT 0 /* LDO2_SLP_VSEL - [4:0] */
681#define WM831X_LDO2_SLP_VSEL_WIDTH 5 /* LDO2_SLP_VSEL - [4:0] */
682
683/*
684 * R16494 (0x406E) - LDO3 Control
685 */
686#define WM831X_LDO3_ERR_ACT_MASK 0xC000 /* LDO3_ERR_ACT - [15:14] */
687#define WM831X_LDO3_ERR_ACT_SHIFT 14 /* LDO3_ERR_ACT - [15:14] */
688#define WM831X_LDO3_ERR_ACT_WIDTH 2 /* LDO3_ERR_ACT - [15:14] */
689#define WM831X_LDO3_HWC_SRC_MASK 0x1800 /* LDO3_HWC_SRC - [12:11] */
690#define WM831X_LDO3_HWC_SRC_SHIFT 11 /* LDO3_HWC_SRC - [12:11] */
691#define WM831X_LDO3_HWC_SRC_WIDTH 2 /* LDO3_HWC_SRC - [12:11] */
692#define WM831X_LDO3_HWC_VSEL 0x0400 /* LDO3_HWC_VSEL */
693#define WM831X_LDO3_HWC_VSEL_MASK 0x0400 /* LDO3_HWC_VSEL */
694#define WM831X_LDO3_HWC_VSEL_SHIFT 10 /* LDO3_HWC_VSEL */
695#define WM831X_LDO3_HWC_VSEL_WIDTH 1 /* LDO3_HWC_VSEL */
696#define WM831X_LDO3_HWC_MODE_MASK 0x0300 /* LDO3_HWC_MODE - [9:8] */
697#define WM831X_LDO3_HWC_MODE_SHIFT 8 /* LDO3_HWC_MODE - [9:8] */
698#define WM831X_LDO3_HWC_MODE_WIDTH 2 /* LDO3_HWC_MODE - [9:8] */
699#define WM831X_LDO3_FLT 0x0080 /* LDO3_FLT */
700#define WM831X_LDO3_FLT_MASK 0x0080 /* LDO3_FLT */
701#define WM831X_LDO3_FLT_SHIFT 7 /* LDO3_FLT */
702#define WM831X_LDO3_FLT_WIDTH 1 /* LDO3_FLT */
703#define WM831X_LDO3_SWI 0x0040 /* LDO3_SWI */
704#define WM831X_LDO3_SWI_MASK 0x0040 /* LDO3_SWI */
705#define WM831X_LDO3_SWI_SHIFT 6 /* LDO3_SWI */
706#define WM831X_LDO3_SWI_WIDTH 1 /* LDO3_SWI */
707#define WM831X_LDO3_LP_MODE 0x0001 /* LDO3_LP_MODE */
708#define WM831X_LDO3_LP_MODE_MASK 0x0001 /* LDO3_LP_MODE */
709#define WM831X_LDO3_LP_MODE_SHIFT 0 /* LDO3_LP_MODE */
710#define WM831X_LDO3_LP_MODE_WIDTH 1 /* LDO3_LP_MODE */
711
712/*
713 * R16495 (0x406F) - LDO3 ON Control
714 */
715#define WM831X_LDO3_ON_SLOT_MASK 0xE000 /* LDO3_ON_SLOT - [15:13] */
716#define WM831X_LDO3_ON_SLOT_SHIFT 13 /* LDO3_ON_SLOT - [15:13] */
717#define WM831X_LDO3_ON_SLOT_WIDTH 3 /* LDO3_ON_SLOT - [15:13] */
718#define WM831X_LDO3_ON_MODE 0x0100 /* LDO3_ON_MODE */
719#define WM831X_LDO3_ON_MODE_MASK 0x0100 /* LDO3_ON_MODE */
720#define WM831X_LDO3_ON_MODE_SHIFT 8 /* LDO3_ON_MODE */
721#define WM831X_LDO3_ON_MODE_WIDTH 1 /* LDO3_ON_MODE */
722#define WM831X_LDO3_ON_VSEL_MASK 0x001F /* LDO3_ON_VSEL - [4:0] */
723#define WM831X_LDO3_ON_VSEL_SHIFT 0 /* LDO3_ON_VSEL - [4:0] */
724#define WM831X_LDO3_ON_VSEL_WIDTH 5 /* LDO3_ON_VSEL - [4:0] */
725
726/*
727 * R16496 (0x4070) - LDO3 SLEEP Control
728 */
729#define WM831X_LDO3_SLP_SLOT_MASK 0xE000 /* LDO3_SLP_SLOT - [15:13] */
730#define WM831X_LDO3_SLP_SLOT_SHIFT 13 /* LDO3_SLP_SLOT - [15:13] */
731#define WM831X_LDO3_SLP_SLOT_WIDTH 3 /* LDO3_SLP_SLOT - [15:13] */
732#define WM831X_LDO3_SLP_MODE 0x0100 /* LDO3_SLP_MODE */
733#define WM831X_LDO3_SLP_MODE_MASK 0x0100 /* LDO3_SLP_MODE */
734#define WM831X_LDO3_SLP_MODE_SHIFT 8 /* LDO3_SLP_MODE */
735#define WM831X_LDO3_SLP_MODE_WIDTH 1 /* LDO3_SLP_MODE */
736#define WM831X_LDO3_SLP_VSEL_MASK 0x001F /* LDO3_SLP_VSEL - [4:0] */
737#define WM831X_LDO3_SLP_VSEL_SHIFT 0 /* LDO3_SLP_VSEL - [4:0] */
738#define WM831X_LDO3_SLP_VSEL_WIDTH 5 /* LDO3_SLP_VSEL - [4:0] */
739
740/*
741 * R16497 (0x4071) - LDO4 Control
742 */
743#define WM831X_LDO4_ERR_ACT_MASK 0xC000 /* LDO4_ERR_ACT - [15:14] */
744#define WM831X_LDO4_ERR_ACT_SHIFT 14 /* LDO4_ERR_ACT - [15:14] */
745#define WM831X_LDO4_ERR_ACT_WIDTH 2 /* LDO4_ERR_ACT - [15:14] */
746#define WM831X_LDO4_HWC_SRC_MASK 0x1800 /* LDO4_HWC_SRC - [12:11] */
747#define WM831X_LDO4_HWC_SRC_SHIFT 11 /* LDO4_HWC_SRC - [12:11] */
748#define WM831X_LDO4_HWC_SRC_WIDTH 2 /* LDO4_HWC_SRC - [12:11] */
749#define WM831X_LDO4_HWC_VSEL 0x0400 /* LDO4_HWC_VSEL */
750#define WM831X_LDO4_HWC_VSEL_MASK 0x0400 /* LDO4_HWC_VSEL */
751#define WM831X_LDO4_HWC_VSEL_SHIFT 10 /* LDO4_HWC_VSEL */
752#define WM831X_LDO4_HWC_VSEL_WIDTH 1 /* LDO4_HWC_VSEL */
753#define WM831X_LDO4_HWC_MODE_MASK 0x0300 /* LDO4_HWC_MODE - [9:8] */
754#define WM831X_LDO4_HWC_MODE_SHIFT 8 /* LDO4_HWC_MODE - [9:8] */
755#define WM831X_LDO4_HWC_MODE_WIDTH 2 /* LDO4_HWC_MODE - [9:8] */
756#define WM831X_LDO4_FLT 0x0080 /* LDO4_FLT */
757#define WM831X_LDO4_FLT_MASK 0x0080 /* LDO4_FLT */
758#define WM831X_LDO4_FLT_SHIFT 7 /* LDO4_FLT */
759#define WM831X_LDO4_FLT_WIDTH 1 /* LDO4_FLT */
760#define WM831X_LDO4_SWI 0x0040 /* LDO4_SWI */
761#define WM831X_LDO4_SWI_MASK 0x0040 /* LDO4_SWI */
762#define WM831X_LDO4_SWI_SHIFT 6 /* LDO4_SWI */
763#define WM831X_LDO4_SWI_WIDTH 1 /* LDO4_SWI */
764#define WM831X_LDO4_LP_MODE 0x0001 /* LDO4_LP_MODE */
765#define WM831X_LDO4_LP_MODE_MASK 0x0001 /* LDO4_LP_MODE */
766#define WM831X_LDO4_LP_MODE_SHIFT 0 /* LDO4_LP_MODE */
767#define WM831X_LDO4_LP_MODE_WIDTH 1 /* LDO4_LP_MODE */
768
769/*
770 * R16498 (0x4072) - LDO4 ON Control
771 */
772#define WM831X_LDO4_ON_SLOT_MASK 0xE000 /* LDO4_ON_SLOT - [15:13] */
773#define WM831X_LDO4_ON_SLOT_SHIFT 13 /* LDO4_ON_SLOT - [15:13] */
774#define WM831X_LDO4_ON_SLOT_WIDTH 3 /* LDO4_ON_SLOT - [15:13] */
775#define WM831X_LDO4_ON_MODE 0x0100 /* LDO4_ON_MODE */
776#define WM831X_LDO4_ON_MODE_MASK 0x0100 /* LDO4_ON_MODE */
777#define WM831X_LDO4_ON_MODE_SHIFT 8 /* LDO4_ON_MODE */
778#define WM831X_LDO4_ON_MODE_WIDTH 1 /* LDO4_ON_MODE */
779#define WM831X_LDO4_ON_VSEL_MASK 0x001F /* LDO4_ON_VSEL - [4:0] */
780#define WM831X_LDO4_ON_VSEL_SHIFT 0 /* LDO4_ON_VSEL - [4:0] */
781#define WM831X_LDO4_ON_VSEL_WIDTH 5 /* LDO4_ON_VSEL - [4:0] */
782
783/*
784 * R16499 (0x4073) - LDO4 SLEEP Control
785 */
786#define WM831X_LDO4_SLP_SLOT_MASK 0xE000 /* LDO4_SLP_SLOT - [15:13] */
787#define WM831X_LDO4_SLP_SLOT_SHIFT 13 /* LDO4_SLP_SLOT - [15:13] */
788#define WM831X_LDO4_SLP_SLOT_WIDTH 3 /* LDO4_SLP_SLOT - [15:13] */
789#define WM831X_LDO4_SLP_MODE 0x0100 /* LDO4_SLP_MODE */
790#define WM831X_LDO4_SLP_MODE_MASK 0x0100 /* LDO4_SLP_MODE */
791#define WM831X_LDO4_SLP_MODE_SHIFT 8 /* LDO4_SLP_MODE */
792#define WM831X_LDO4_SLP_MODE_WIDTH 1 /* LDO4_SLP_MODE */
793#define WM831X_LDO4_SLP_VSEL_MASK 0x001F /* LDO4_SLP_VSEL - [4:0] */
794#define WM831X_LDO4_SLP_VSEL_SHIFT 0 /* LDO4_SLP_VSEL - [4:0] */
795#define WM831X_LDO4_SLP_VSEL_WIDTH 5 /* LDO4_SLP_VSEL - [4:0] */
796
797/*
798 * R16500 (0x4074) - LDO5 Control
799 */
800#define WM831X_LDO5_ERR_ACT_MASK 0xC000 /* LDO5_ERR_ACT - [15:14] */
801#define WM831X_LDO5_ERR_ACT_SHIFT 14 /* LDO5_ERR_ACT - [15:14] */
802#define WM831X_LDO5_ERR_ACT_WIDTH 2 /* LDO5_ERR_ACT - [15:14] */
803#define WM831X_LDO5_HWC_SRC_MASK 0x1800 /* LDO5_HWC_SRC - [12:11] */
804#define WM831X_LDO5_HWC_SRC_SHIFT 11 /* LDO5_HWC_SRC - [12:11] */
805#define WM831X_LDO5_HWC_SRC_WIDTH 2 /* LDO5_HWC_SRC - [12:11] */
806#define WM831X_LDO5_HWC_VSEL 0x0400 /* LDO5_HWC_VSEL */
807#define WM831X_LDO5_HWC_VSEL_MASK 0x0400 /* LDO5_HWC_VSEL */
808#define WM831X_LDO5_HWC_VSEL_SHIFT 10 /* LDO5_HWC_VSEL */
809#define WM831X_LDO5_HWC_VSEL_WIDTH 1 /* LDO5_HWC_VSEL */
810#define WM831X_LDO5_HWC_MODE_MASK 0x0300 /* LDO5_HWC_MODE - [9:8] */
811#define WM831X_LDO5_HWC_MODE_SHIFT 8 /* LDO5_HWC_MODE - [9:8] */
812#define WM831X_LDO5_HWC_MODE_WIDTH 2 /* LDO5_HWC_MODE - [9:8] */
813#define WM831X_LDO5_FLT 0x0080 /* LDO5_FLT */
814#define WM831X_LDO5_FLT_MASK 0x0080 /* LDO5_FLT */
815#define WM831X_LDO5_FLT_SHIFT 7 /* LDO5_FLT */
816#define WM831X_LDO5_FLT_WIDTH 1 /* LDO5_FLT */
817#define WM831X_LDO5_SWI 0x0040 /* LDO5_SWI */
818#define WM831X_LDO5_SWI_MASK 0x0040 /* LDO5_SWI */
819#define WM831X_LDO5_SWI_SHIFT 6 /* LDO5_SWI */
820#define WM831X_LDO5_SWI_WIDTH 1 /* LDO5_SWI */
821#define WM831X_LDO5_LP_MODE 0x0001 /* LDO5_LP_MODE */
822#define WM831X_LDO5_LP_MODE_MASK 0x0001 /* LDO5_LP_MODE */
823#define WM831X_LDO5_LP_MODE_SHIFT 0 /* LDO5_LP_MODE */
824#define WM831X_LDO5_LP_MODE_WIDTH 1 /* LDO5_LP_MODE */
825
826/*
827 * R16501 (0x4075) - LDO5 ON Control
828 */
829#define WM831X_LDO5_ON_SLOT_MASK 0xE000 /* LDO5_ON_SLOT - [15:13] */
830#define WM831X_LDO5_ON_SLOT_SHIFT 13 /* LDO5_ON_SLOT - [15:13] */
831#define WM831X_LDO5_ON_SLOT_WIDTH 3 /* LDO5_ON_SLOT - [15:13] */
832#define WM831X_LDO5_ON_MODE 0x0100 /* LDO5_ON_MODE */
833#define WM831X_LDO5_ON_MODE_MASK 0x0100 /* LDO5_ON_MODE */
834#define WM831X_LDO5_ON_MODE_SHIFT 8 /* LDO5_ON_MODE */
835#define WM831X_LDO5_ON_MODE_WIDTH 1 /* LDO5_ON_MODE */
836#define WM831X_LDO5_ON_VSEL_MASK 0x001F /* LDO5_ON_VSEL - [4:0] */
837#define WM831X_LDO5_ON_VSEL_SHIFT 0 /* LDO5_ON_VSEL - [4:0] */
838#define WM831X_LDO5_ON_VSEL_WIDTH 5 /* LDO5_ON_VSEL - [4:0] */
839
840/*
841 * R16502 (0x4076) - LDO5 SLEEP Control
842 */
843#define WM831X_LDO5_SLP_SLOT_MASK 0xE000 /* LDO5_SLP_SLOT - [15:13] */
844#define WM831X_LDO5_SLP_SLOT_SHIFT 13 /* LDO5_SLP_SLOT - [15:13] */
845#define WM831X_LDO5_SLP_SLOT_WIDTH 3 /* LDO5_SLP_SLOT - [15:13] */
846#define WM831X_LDO5_SLP_MODE 0x0100 /* LDO5_SLP_MODE */
847#define WM831X_LDO5_SLP_MODE_MASK 0x0100 /* LDO5_SLP_MODE */
848#define WM831X_LDO5_SLP_MODE_SHIFT 8 /* LDO5_SLP_MODE */
849#define WM831X_LDO5_SLP_MODE_WIDTH 1 /* LDO5_SLP_MODE */
850#define WM831X_LDO5_SLP_VSEL_MASK 0x001F /* LDO5_SLP_VSEL - [4:0] */
851#define WM831X_LDO5_SLP_VSEL_SHIFT 0 /* LDO5_SLP_VSEL - [4:0] */
852#define WM831X_LDO5_SLP_VSEL_WIDTH 5 /* LDO5_SLP_VSEL - [4:0] */
853
854/*
855 * R16503 (0x4077) - LDO6 Control
856 */
857#define WM831X_LDO6_ERR_ACT_MASK 0xC000 /* LDO6_ERR_ACT - [15:14] */
858#define WM831X_LDO6_ERR_ACT_SHIFT 14 /* LDO6_ERR_ACT - [15:14] */
859#define WM831X_LDO6_ERR_ACT_WIDTH 2 /* LDO6_ERR_ACT - [15:14] */
860#define WM831X_LDO6_HWC_SRC_MASK 0x1800 /* LDO6_HWC_SRC - [12:11] */
861#define WM831X_LDO6_HWC_SRC_SHIFT 11 /* LDO6_HWC_SRC - [12:11] */
862#define WM831X_LDO6_HWC_SRC_WIDTH 2 /* LDO6_HWC_SRC - [12:11] */
863#define WM831X_LDO6_HWC_VSEL 0x0400 /* LDO6_HWC_VSEL */
864#define WM831X_LDO6_HWC_VSEL_MASK 0x0400 /* LDO6_HWC_VSEL */
865#define WM831X_LDO6_HWC_VSEL_SHIFT 10 /* LDO6_HWC_VSEL */
866#define WM831X_LDO6_HWC_VSEL_WIDTH 1 /* LDO6_HWC_VSEL */
867#define WM831X_LDO6_HWC_MODE_MASK 0x0300 /* LDO6_HWC_MODE - [9:8] */
868#define WM831X_LDO6_HWC_MODE_SHIFT 8 /* LDO6_HWC_MODE - [9:8] */
869#define WM831X_LDO6_HWC_MODE_WIDTH 2 /* LDO6_HWC_MODE - [9:8] */
870#define WM831X_LDO6_FLT 0x0080 /* LDO6_FLT */
871#define WM831X_LDO6_FLT_MASK 0x0080 /* LDO6_FLT */
872#define WM831X_LDO6_FLT_SHIFT 7 /* LDO6_FLT */
873#define WM831X_LDO6_FLT_WIDTH 1 /* LDO6_FLT */
874#define WM831X_LDO6_SWI 0x0040 /* LDO6_SWI */
875#define WM831X_LDO6_SWI_MASK 0x0040 /* LDO6_SWI */
876#define WM831X_LDO6_SWI_SHIFT 6 /* LDO6_SWI */
877#define WM831X_LDO6_SWI_WIDTH 1 /* LDO6_SWI */
878#define WM831X_LDO6_LP_MODE 0x0001 /* LDO6_LP_MODE */
879#define WM831X_LDO6_LP_MODE_MASK 0x0001 /* LDO6_LP_MODE */
880#define WM831X_LDO6_LP_MODE_SHIFT 0 /* LDO6_LP_MODE */
881#define WM831X_LDO6_LP_MODE_WIDTH 1 /* LDO6_LP_MODE */
882
883/*
884 * R16504 (0x4078) - LDO6 ON Control
885 */
886#define WM831X_LDO6_ON_SLOT_MASK 0xE000 /* LDO6_ON_SLOT - [15:13] */
887#define WM831X_LDO6_ON_SLOT_SHIFT 13 /* LDO6_ON_SLOT - [15:13] */
888#define WM831X_LDO6_ON_SLOT_WIDTH 3 /* LDO6_ON_SLOT - [15:13] */
889#define WM831X_LDO6_ON_MODE 0x0100 /* LDO6_ON_MODE */
890#define WM831X_LDO6_ON_MODE_MASK 0x0100 /* LDO6_ON_MODE */
891#define WM831X_LDO6_ON_MODE_SHIFT 8 /* LDO6_ON_MODE */
892#define WM831X_LDO6_ON_MODE_WIDTH 1 /* LDO6_ON_MODE */
893#define WM831X_LDO6_ON_VSEL_MASK 0x001F /* LDO6_ON_VSEL - [4:0] */
894#define WM831X_LDO6_ON_VSEL_SHIFT 0 /* LDO6_ON_VSEL - [4:0] */
895#define WM831X_LDO6_ON_VSEL_WIDTH 5 /* LDO6_ON_VSEL - [4:0] */
896
897/*
898 * R16505 (0x4079) - LDO6 SLEEP Control
899 */
900#define WM831X_LDO6_SLP_SLOT_MASK 0xE000 /* LDO6_SLP_SLOT - [15:13] */
901#define WM831X_LDO6_SLP_SLOT_SHIFT 13 /* LDO6_SLP_SLOT - [15:13] */
902#define WM831X_LDO6_SLP_SLOT_WIDTH 3 /* LDO6_SLP_SLOT - [15:13] */
903#define WM831X_LDO6_SLP_MODE 0x0100 /* LDO6_SLP_MODE */
904#define WM831X_LDO6_SLP_MODE_MASK 0x0100 /* LDO6_SLP_MODE */
905#define WM831X_LDO6_SLP_MODE_SHIFT 8 /* LDO6_SLP_MODE */
906#define WM831X_LDO6_SLP_MODE_WIDTH 1 /* LDO6_SLP_MODE */
907#define WM831X_LDO6_SLP_VSEL_MASK 0x001F /* LDO6_SLP_VSEL - [4:0] */
908#define WM831X_LDO6_SLP_VSEL_SHIFT 0 /* LDO6_SLP_VSEL - [4:0] */
909#define WM831X_LDO6_SLP_VSEL_WIDTH 5 /* LDO6_SLP_VSEL - [4:0] */
910
911/*
912 * R16506 (0x407A) - LDO7 Control
913 */
914#define WM831X_LDO7_ERR_ACT_MASK 0xC000 /* LDO7_ERR_ACT - [15:14] */
915#define WM831X_LDO7_ERR_ACT_SHIFT 14 /* LDO7_ERR_ACT - [15:14] */
916#define WM831X_LDO7_ERR_ACT_WIDTH 2 /* LDO7_ERR_ACT - [15:14] */
917#define WM831X_LDO7_HWC_SRC_MASK 0x1800 /* LDO7_HWC_SRC - [12:11] */
918#define WM831X_LDO7_HWC_SRC_SHIFT 11 /* LDO7_HWC_SRC - [12:11] */
919#define WM831X_LDO7_HWC_SRC_WIDTH 2 /* LDO7_HWC_SRC - [12:11] */
920#define WM831X_LDO7_HWC_VSEL 0x0400 /* LDO7_HWC_VSEL */
921#define WM831X_LDO7_HWC_VSEL_MASK 0x0400 /* LDO7_HWC_VSEL */
922#define WM831X_LDO7_HWC_VSEL_SHIFT 10 /* LDO7_HWC_VSEL */
923#define WM831X_LDO7_HWC_VSEL_WIDTH 1 /* LDO7_HWC_VSEL */
924#define WM831X_LDO7_HWC_MODE_MASK 0x0300 /* LDO7_HWC_MODE - [9:8] */
925#define WM831X_LDO7_HWC_MODE_SHIFT 8 /* LDO7_HWC_MODE - [9:8] */
926#define WM831X_LDO7_HWC_MODE_WIDTH 2 /* LDO7_HWC_MODE - [9:8] */
927#define WM831X_LDO7_FLT 0x0080 /* LDO7_FLT */
928#define WM831X_LDO7_FLT_MASK 0x0080 /* LDO7_FLT */
929#define WM831X_LDO7_FLT_SHIFT 7 /* LDO7_FLT */
930#define WM831X_LDO7_FLT_WIDTH 1 /* LDO7_FLT */
931#define WM831X_LDO7_SWI 0x0040 /* LDO7_SWI */
932#define WM831X_LDO7_SWI_MASK 0x0040 /* LDO7_SWI */
933#define WM831X_LDO7_SWI_SHIFT 6 /* LDO7_SWI */
934#define WM831X_LDO7_SWI_WIDTH 1 /* LDO7_SWI */
935
936/*
937 * R16507 (0x407B) - LDO7 ON Control
938 */
939#define WM831X_LDO7_ON_SLOT_MASK 0xE000 /* LDO7_ON_SLOT - [15:13] */
940#define WM831X_LDO7_ON_SLOT_SHIFT 13 /* LDO7_ON_SLOT - [15:13] */
941#define WM831X_LDO7_ON_SLOT_WIDTH 3 /* LDO7_ON_SLOT - [15:13] */
942#define WM831X_LDO7_ON_MODE 0x0100 /* LDO7_ON_MODE */
943#define WM831X_LDO7_ON_MODE_MASK 0x0100 /* LDO7_ON_MODE */
944#define WM831X_LDO7_ON_MODE_SHIFT 8 /* LDO7_ON_MODE */
945#define WM831X_LDO7_ON_MODE_WIDTH 1 /* LDO7_ON_MODE */
946#define WM831X_LDO7_ON_VSEL_MASK 0x001F /* LDO7_ON_VSEL - [4:0] */
947#define WM831X_LDO7_ON_VSEL_SHIFT 0 /* LDO7_ON_VSEL - [4:0] */
948#define WM831X_LDO7_ON_VSEL_WIDTH 5 /* LDO7_ON_VSEL - [4:0] */
949
950/*
951 * R16508 (0x407C) - LDO7 SLEEP Control
952 */
953#define WM831X_LDO7_SLP_SLOT_MASK 0xE000 /* LDO7_SLP_SLOT - [15:13] */
954#define WM831X_LDO7_SLP_SLOT_SHIFT 13 /* LDO7_SLP_SLOT - [15:13] */
955#define WM831X_LDO7_SLP_SLOT_WIDTH 3 /* LDO7_SLP_SLOT - [15:13] */
956#define WM831X_LDO7_SLP_MODE 0x0100 /* LDO7_SLP_MODE */
957#define WM831X_LDO7_SLP_MODE_MASK 0x0100 /* LDO7_SLP_MODE */
958#define WM831X_LDO7_SLP_MODE_SHIFT 8 /* LDO7_SLP_MODE */
959#define WM831X_LDO7_SLP_MODE_WIDTH 1 /* LDO7_SLP_MODE */
960#define WM831X_LDO7_SLP_VSEL_MASK 0x001F /* LDO7_SLP_VSEL - [4:0] */
961#define WM831X_LDO7_SLP_VSEL_SHIFT 0 /* LDO7_SLP_VSEL - [4:0] */
962#define WM831X_LDO7_SLP_VSEL_WIDTH 5 /* LDO7_SLP_VSEL - [4:0] */
963
964/*
965 * R16509 (0x407D) - LDO8 Control
966 */
967#define WM831X_LDO8_ERR_ACT_MASK 0xC000 /* LDO8_ERR_ACT - [15:14] */
968#define WM831X_LDO8_ERR_ACT_SHIFT 14 /* LDO8_ERR_ACT - [15:14] */
969#define WM831X_LDO8_ERR_ACT_WIDTH 2 /* LDO8_ERR_ACT - [15:14] */
970#define WM831X_LDO8_HWC_SRC_MASK 0x1800 /* LDO8_HWC_SRC - [12:11] */
971#define WM831X_LDO8_HWC_SRC_SHIFT 11 /* LDO8_HWC_SRC - [12:11] */
972#define WM831X_LDO8_HWC_SRC_WIDTH 2 /* LDO8_HWC_SRC - [12:11] */
973#define WM831X_LDO8_HWC_VSEL 0x0400 /* LDO8_HWC_VSEL */
974#define WM831X_LDO8_HWC_VSEL_MASK 0x0400 /* LDO8_HWC_VSEL */
975#define WM831X_LDO8_HWC_VSEL_SHIFT 10 /* LDO8_HWC_VSEL */
976#define WM831X_LDO8_HWC_VSEL_WIDTH 1 /* LDO8_HWC_VSEL */
977#define WM831X_LDO8_HWC_MODE_MASK 0x0300 /* LDO8_HWC_MODE - [9:8] */
978#define WM831X_LDO8_HWC_MODE_SHIFT 8 /* LDO8_HWC_MODE - [9:8] */
979#define WM831X_LDO8_HWC_MODE_WIDTH 2 /* LDO8_HWC_MODE - [9:8] */
980#define WM831X_LDO8_FLT 0x0080 /* LDO8_FLT */
981#define WM831X_LDO8_FLT_MASK 0x0080 /* LDO8_FLT */
982#define WM831X_LDO8_FLT_SHIFT 7 /* LDO8_FLT */
983#define WM831X_LDO8_FLT_WIDTH 1 /* LDO8_FLT */
984#define WM831X_LDO8_SWI 0x0040 /* LDO8_SWI */
985#define WM831X_LDO8_SWI_MASK 0x0040 /* LDO8_SWI */
986#define WM831X_LDO8_SWI_SHIFT 6 /* LDO8_SWI */
987#define WM831X_LDO8_SWI_WIDTH 1 /* LDO8_SWI */
988
989/*
990 * R16510 (0x407E) - LDO8 ON Control
991 */
992#define WM831X_LDO8_ON_SLOT_MASK 0xE000 /* LDO8_ON_SLOT - [15:13] */
993#define WM831X_LDO8_ON_SLOT_SHIFT 13 /* LDO8_ON_SLOT - [15:13] */
994#define WM831X_LDO8_ON_SLOT_WIDTH 3 /* LDO8_ON_SLOT - [15:13] */
995#define WM831X_LDO8_ON_MODE 0x0100 /* LDO8_ON_MODE */
996#define WM831X_LDO8_ON_MODE_MASK 0x0100 /* LDO8_ON_MODE */
997#define WM831X_LDO8_ON_MODE_SHIFT 8 /* LDO8_ON_MODE */
998#define WM831X_LDO8_ON_MODE_WIDTH 1 /* LDO8_ON_MODE */
999#define WM831X_LDO8_ON_VSEL_MASK 0x001F /* LDO8_ON_VSEL - [4:0] */
1000#define WM831X_LDO8_ON_VSEL_SHIFT 0 /* LDO8_ON_VSEL - [4:0] */
1001#define WM831X_LDO8_ON_VSEL_WIDTH 5 /* LDO8_ON_VSEL - [4:0] */
1002
1003/*
1004 * R16511 (0x407F) - LDO8 SLEEP Control
1005 */
1006#define WM831X_LDO8_SLP_SLOT_MASK 0xE000 /* LDO8_SLP_SLOT - [15:13] */
1007#define WM831X_LDO8_SLP_SLOT_SHIFT 13 /* LDO8_SLP_SLOT - [15:13] */
1008#define WM831X_LDO8_SLP_SLOT_WIDTH 3 /* LDO8_SLP_SLOT - [15:13] */
1009#define WM831X_LDO8_SLP_MODE 0x0100 /* LDO8_SLP_MODE */
1010#define WM831X_LDO8_SLP_MODE_MASK 0x0100 /* LDO8_SLP_MODE */
1011#define WM831X_LDO8_SLP_MODE_SHIFT 8 /* LDO8_SLP_MODE */
1012#define WM831X_LDO8_SLP_MODE_WIDTH 1 /* LDO8_SLP_MODE */
1013#define WM831X_LDO8_SLP_VSEL_MASK 0x001F /* LDO8_SLP_VSEL - [4:0] */
1014#define WM831X_LDO8_SLP_VSEL_SHIFT 0 /* LDO8_SLP_VSEL - [4:0] */
1015#define WM831X_LDO8_SLP_VSEL_WIDTH 5 /* LDO8_SLP_VSEL - [4:0] */
1016
1017/*
1018 * R16512 (0x4080) - LDO9 Control
1019 */
1020#define WM831X_LDO9_ERR_ACT_MASK 0xC000 /* LDO9_ERR_ACT - [15:14] */
1021#define WM831X_LDO9_ERR_ACT_SHIFT 14 /* LDO9_ERR_ACT - [15:14] */
1022#define WM831X_LDO9_ERR_ACT_WIDTH 2 /* LDO9_ERR_ACT - [15:14] */
1023#define WM831X_LDO9_HWC_SRC_MASK 0x1800 /* LDO9_HWC_SRC - [12:11] */
1024#define WM831X_LDO9_HWC_SRC_SHIFT 11 /* LDO9_HWC_SRC - [12:11] */
1025#define WM831X_LDO9_HWC_SRC_WIDTH 2 /* LDO9_HWC_SRC - [12:11] */
1026#define WM831X_LDO9_HWC_VSEL 0x0400 /* LDO9_HWC_VSEL */
1027#define WM831X_LDO9_HWC_VSEL_MASK 0x0400 /* LDO9_HWC_VSEL */
1028#define WM831X_LDO9_HWC_VSEL_SHIFT 10 /* LDO9_HWC_VSEL */
1029#define WM831X_LDO9_HWC_VSEL_WIDTH 1 /* LDO9_HWC_VSEL */
1030#define WM831X_LDO9_HWC_MODE_MASK 0x0300 /* LDO9_HWC_MODE - [9:8] */
1031#define WM831X_LDO9_HWC_MODE_SHIFT 8 /* LDO9_HWC_MODE - [9:8] */
1032#define WM831X_LDO9_HWC_MODE_WIDTH 2 /* LDO9_HWC_MODE - [9:8] */
1033#define WM831X_LDO9_FLT 0x0080 /* LDO9_FLT */
1034#define WM831X_LDO9_FLT_MASK 0x0080 /* LDO9_FLT */
1035#define WM831X_LDO9_FLT_SHIFT 7 /* LDO9_FLT */
1036#define WM831X_LDO9_FLT_WIDTH 1 /* LDO9_FLT */
1037#define WM831X_LDO9_SWI 0x0040 /* LDO9_SWI */
1038#define WM831X_LDO9_SWI_MASK 0x0040 /* LDO9_SWI */
1039#define WM831X_LDO9_SWI_SHIFT 6 /* LDO9_SWI */
1040#define WM831X_LDO9_SWI_WIDTH 1 /* LDO9_SWI */
1041
1042/*
1043 * R16513 (0x4081) - LDO9 ON Control
1044 */
1045#define WM831X_LDO9_ON_SLOT_MASK 0xE000 /* LDO9_ON_SLOT - [15:13] */
1046#define WM831X_LDO9_ON_SLOT_SHIFT 13 /* LDO9_ON_SLOT - [15:13] */
1047#define WM831X_LDO9_ON_SLOT_WIDTH 3 /* LDO9_ON_SLOT - [15:13] */
1048#define WM831X_LDO9_ON_MODE 0x0100 /* LDO9_ON_MODE */
1049#define WM831X_LDO9_ON_MODE_MASK 0x0100 /* LDO9_ON_MODE */
1050#define WM831X_LDO9_ON_MODE_SHIFT 8 /* LDO9_ON_MODE */
1051#define WM831X_LDO9_ON_MODE_WIDTH 1 /* LDO9_ON_MODE */
1052#define WM831X_LDO9_ON_VSEL_MASK 0x001F /* LDO9_ON_VSEL - [4:0] */
1053#define WM831X_LDO9_ON_VSEL_SHIFT 0 /* LDO9_ON_VSEL - [4:0] */
1054#define WM831X_LDO9_ON_VSEL_WIDTH 5 /* LDO9_ON_VSEL - [4:0] */
1055
1056/*
1057 * R16514 (0x4082) - LDO9 SLEEP Control
1058 */
1059#define WM831X_LDO9_SLP_SLOT_MASK 0xE000 /* LDO9_SLP_SLOT - [15:13] */
1060#define WM831X_LDO9_SLP_SLOT_SHIFT 13 /* LDO9_SLP_SLOT - [15:13] */
1061#define WM831X_LDO9_SLP_SLOT_WIDTH 3 /* LDO9_SLP_SLOT - [15:13] */
1062#define WM831X_LDO9_SLP_MODE 0x0100 /* LDO9_SLP_MODE */
1063#define WM831X_LDO9_SLP_MODE_MASK 0x0100 /* LDO9_SLP_MODE */
1064#define WM831X_LDO9_SLP_MODE_SHIFT 8 /* LDO9_SLP_MODE */
1065#define WM831X_LDO9_SLP_MODE_WIDTH 1 /* LDO9_SLP_MODE */
1066#define WM831X_LDO9_SLP_VSEL_MASK 0x001F /* LDO9_SLP_VSEL - [4:0] */
1067#define WM831X_LDO9_SLP_VSEL_SHIFT 0 /* LDO9_SLP_VSEL - [4:0] */
1068#define WM831X_LDO9_SLP_VSEL_WIDTH 5 /* LDO9_SLP_VSEL - [4:0] */
1069
1070/*
1071 * R16515 (0x4083) - LDO10 Control
1072 */
1073#define WM831X_LDO10_ERR_ACT_MASK 0xC000 /* LDO10_ERR_ACT - [15:14] */
1074#define WM831X_LDO10_ERR_ACT_SHIFT 14 /* LDO10_ERR_ACT - [15:14] */
1075#define WM831X_LDO10_ERR_ACT_WIDTH 2 /* LDO10_ERR_ACT - [15:14] */
1076#define WM831X_LDO10_HWC_SRC_MASK 0x1800 /* LDO10_HWC_SRC - [12:11] */
1077#define WM831X_LDO10_HWC_SRC_SHIFT 11 /* LDO10_HWC_SRC - [12:11] */
1078#define WM831X_LDO10_HWC_SRC_WIDTH 2 /* LDO10_HWC_SRC - [12:11] */
1079#define WM831X_LDO10_HWC_VSEL 0x0400 /* LDO10_HWC_VSEL */
1080#define WM831X_LDO10_HWC_VSEL_MASK 0x0400 /* LDO10_HWC_VSEL */
1081#define WM831X_LDO10_HWC_VSEL_SHIFT 10 /* LDO10_HWC_VSEL */
1082#define WM831X_LDO10_HWC_VSEL_WIDTH 1 /* LDO10_HWC_VSEL */
1083#define WM831X_LDO10_HWC_MODE_MASK 0x0300 /* LDO10_HWC_MODE - [9:8] */
1084#define WM831X_LDO10_HWC_MODE_SHIFT 8 /* LDO10_HWC_MODE - [9:8] */
1085#define WM831X_LDO10_HWC_MODE_WIDTH 2 /* LDO10_HWC_MODE - [9:8] */
1086#define WM831X_LDO10_FLT 0x0080 /* LDO10_FLT */
1087#define WM831X_LDO10_FLT_MASK 0x0080 /* LDO10_FLT */
1088#define WM831X_LDO10_FLT_SHIFT 7 /* LDO10_FLT */
1089#define WM831X_LDO10_FLT_WIDTH 1 /* LDO10_FLT */
1090#define WM831X_LDO10_SWI 0x0040 /* LDO10_SWI */
1091#define WM831X_LDO10_SWI_MASK 0x0040 /* LDO10_SWI */
1092#define WM831X_LDO10_SWI_SHIFT 6 /* LDO10_SWI */
1093#define WM831X_LDO10_SWI_WIDTH 1 /* LDO10_SWI */
1094
1095/*
1096 * R16516 (0x4084) - LDO10 ON Control
1097 */
1098#define WM831X_LDO10_ON_SLOT_MASK 0xE000 /* LDO10_ON_SLOT - [15:13] */
1099#define WM831X_LDO10_ON_SLOT_SHIFT 13 /* LDO10_ON_SLOT - [15:13] */
1100#define WM831X_LDO10_ON_SLOT_WIDTH 3 /* LDO10_ON_SLOT - [15:13] */
1101#define WM831X_LDO10_ON_MODE 0x0100 /* LDO10_ON_MODE */
1102#define WM831X_LDO10_ON_MODE_MASK 0x0100 /* LDO10_ON_MODE */
1103#define WM831X_LDO10_ON_MODE_SHIFT 8 /* LDO10_ON_MODE */
1104#define WM831X_LDO10_ON_MODE_WIDTH 1 /* LDO10_ON_MODE */
1105#define WM831X_LDO10_ON_VSEL_MASK 0x001F /* LDO10_ON_VSEL - [4:0] */
1106#define WM831X_LDO10_ON_VSEL_SHIFT 0 /* LDO10_ON_VSEL - [4:0] */
1107#define WM831X_LDO10_ON_VSEL_WIDTH 5 /* LDO10_ON_VSEL - [4:0] */
1108
1109/*
1110 * R16517 (0x4085) - LDO10 SLEEP Control
1111 */
1112#define WM831X_LDO10_SLP_SLOT_MASK 0xE000 /* LDO10_SLP_SLOT - [15:13] */
1113#define WM831X_LDO10_SLP_SLOT_SHIFT 13 /* LDO10_SLP_SLOT - [15:13] */
1114#define WM831X_LDO10_SLP_SLOT_WIDTH 3 /* LDO10_SLP_SLOT - [15:13] */
1115#define WM831X_LDO10_SLP_MODE 0x0100 /* LDO10_SLP_MODE */
1116#define WM831X_LDO10_SLP_MODE_MASK 0x0100 /* LDO10_SLP_MODE */
1117#define WM831X_LDO10_SLP_MODE_SHIFT 8 /* LDO10_SLP_MODE */
1118#define WM831X_LDO10_SLP_MODE_WIDTH 1 /* LDO10_SLP_MODE */
1119#define WM831X_LDO10_SLP_VSEL_MASK 0x001F /* LDO10_SLP_VSEL - [4:0] */
1120#define WM831X_LDO10_SLP_VSEL_SHIFT 0 /* LDO10_SLP_VSEL - [4:0] */
1121#define WM831X_LDO10_SLP_VSEL_WIDTH 5 /* LDO10_SLP_VSEL - [4:0] */
1122
1123/*
1124 * R16519 (0x4087) - LDO11 ON Control
1125 */
1126#define WM831X_LDO11_ON_SLOT_MASK 0xE000 /* LDO11_ON_SLOT - [15:13] */
1127#define WM831X_LDO11_ON_SLOT_SHIFT 13 /* LDO11_ON_SLOT - [15:13] */
1128#define WM831X_LDO11_ON_SLOT_WIDTH 3 /* LDO11_ON_SLOT - [15:13] */
1129#define WM831X_LDO11_OFFENA 0x1000 /* LDO11_OFFENA */
1130#define WM831X_LDO11_OFFENA_MASK 0x1000 /* LDO11_OFFENA */
1131#define WM831X_LDO11_OFFENA_SHIFT 12 /* LDO11_OFFENA */
1132#define WM831X_LDO11_OFFENA_WIDTH 1 /* LDO11_OFFENA */
1133#define WM831X_LDO11_VSEL_SRC 0x0080 /* LDO11_VSEL_SRC */
1134#define WM831X_LDO11_VSEL_SRC_MASK 0x0080 /* LDO11_VSEL_SRC */
1135#define WM831X_LDO11_VSEL_SRC_SHIFT 7 /* LDO11_VSEL_SRC */
1136#define WM831X_LDO11_VSEL_SRC_WIDTH 1 /* LDO11_VSEL_SRC */
1137#define WM831X_LDO11_ON_VSEL_MASK 0x000F /* LDO11_ON_VSEL - [3:0] */
1138#define WM831X_LDO11_ON_VSEL_SHIFT 0 /* LDO11_ON_VSEL - [3:0] */
1139#define WM831X_LDO11_ON_VSEL_WIDTH 4 /* LDO11_ON_VSEL - [3:0] */
1140
1141/*
1142 * R16520 (0x4088) - LDO11 SLEEP Control
1143 */
1144#define WM831X_LDO11_SLP_SLOT_MASK 0xE000 /* LDO11_SLP_SLOT - [15:13] */
1145#define WM831X_LDO11_SLP_SLOT_SHIFT 13 /* LDO11_SLP_SLOT - [15:13] */
1146#define WM831X_LDO11_SLP_SLOT_WIDTH 3 /* LDO11_SLP_SLOT - [15:13] */
1147#define WM831X_LDO11_SLP_VSEL_MASK 0x000F /* LDO11_SLP_VSEL - [3:0] */
1148#define WM831X_LDO11_SLP_VSEL_SHIFT 0 /* LDO11_SLP_VSEL - [3:0] */
1149#define WM831X_LDO11_SLP_VSEL_WIDTH 4 /* LDO11_SLP_VSEL - [3:0] */
1150
1151/*
570 * R16526 (0x408E) - Power Good Source 1 1152 * R16526 (0x408E) - Power Good Source 1
571 */ 1153 */
572#define WM831X_DC4_OK 0x0008 /* DC4_OK */ 1154#define WM831X_DC4_OK 0x0008 /* DC4_OK */
@@ -586,6 +1168,50 @@
586#define WM831X_DC1_OK_SHIFT 0 /* DC1_OK */ 1168#define WM831X_DC1_OK_SHIFT 0 /* DC1_OK */
587#define WM831X_DC1_OK_WIDTH 1 /* DC1_OK */ 1169#define WM831X_DC1_OK_WIDTH 1 /* DC1_OK */
588 1170
1171/*
1172 * R16527 (0x408F) - Power Good Source 2
1173 */
1174#define WM831X_LDO10_OK 0x0200 /* LDO10_OK */
1175#define WM831X_LDO10_OK_MASK 0x0200 /* LDO10_OK */
1176#define WM831X_LDO10_OK_SHIFT 9 /* LDO10_OK */
1177#define WM831X_LDO10_OK_WIDTH 1 /* LDO10_OK */
1178#define WM831X_LDO9_OK 0x0100 /* LDO9_OK */
1179#define WM831X_LDO9_OK_MASK 0x0100 /* LDO9_OK */
1180#define WM831X_LDO9_OK_SHIFT 8 /* LDO9_OK */
1181#define WM831X_LDO9_OK_WIDTH 1 /* LDO9_OK */
1182#define WM831X_LDO8_OK 0x0080 /* LDO8_OK */
1183#define WM831X_LDO8_OK_MASK 0x0080 /* LDO8_OK */
1184#define WM831X_LDO8_OK_SHIFT 7 /* LDO8_OK */
1185#define WM831X_LDO8_OK_WIDTH 1 /* LDO8_OK */
1186#define WM831X_LDO7_OK 0x0040 /* LDO7_OK */
1187#define WM831X_LDO7_OK_MASK 0x0040 /* LDO7_OK */
1188#define WM831X_LDO7_OK_SHIFT 6 /* LDO7_OK */
1189#define WM831X_LDO7_OK_WIDTH 1 /* LDO7_OK */
1190#define WM831X_LDO6_OK 0x0020 /* LDO6_OK */
1191#define WM831X_LDO6_OK_MASK 0x0020 /* LDO6_OK */
1192#define WM831X_LDO6_OK_SHIFT 5 /* LDO6_OK */
1193#define WM831X_LDO6_OK_WIDTH 1 /* LDO6_OK */
1194#define WM831X_LDO5_OK 0x0010 /* LDO5_OK */
1195#define WM831X_LDO5_OK_MASK 0x0010 /* LDO5_OK */
1196#define WM831X_LDO5_OK_SHIFT 4 /* LDO5_OK */
1197#define WM831X_LDO5_OK_WIDTH 1 /* LDO5_OK */
1198#define WM831X_LDO4_OK 0x0008 /* LDO4_OK */
1199#define WM831X_LDO4_OK_MASK 0x0008 /* LDO4_OK */
1200#define WM831X_LDO4_OK_SHIFT 3 /* LDO4_OK */
1201#define WM831X_LDO4_OK_WIDTH 1 /* LDO4_OK */
1202#define WM831X_LDO3_OK 0x0004 /* LDO3_OK */
1203#define WM831X_LDO3_OK_MASK 0x0004 /* LDO3_OK */
1204#define WM831X_LDO3_OK_SHIFT 2 /* LDO3_OK */
1205#define WM831X_LDO3_OK_WIDTH 1 /* LDO3_OK */
1206#define WM831X_LDO2_OK 0x0002 /* LDO2_OK */
1207#define WM831X_LDO2_OK_MASK 0x0002 /* LDO2_OK */
1208#define WM831X_LDO2_OK_SHIFT 1 /* LDO2_OK */
1209#define WM831X_LDO2_OK_WIDTH 1 /* LDO2_OK */
1210#define WM831X_LDO1_OK 0x0001 /* LDO1_OK */
1211#define WM831X_LDO1_OK_MASK 0x0001 /* LDO1_OK */
1212#define WM831X_LDO1_OK_SHIFT 0 /* LDO1_OK */
1213#define WM831X_LDO1_OK_WIDTH 1 /* LDO1_OK */
1214
589#define WM831X_ISINK_MAX_ISEL 56 1215#define WM831X_ISINK_MAX_ISEL 56
590extern int wm831x_isinkv_values[WM831X_ISINK_MAX_ISEL]; 1216extern int wm831x_isinkv_values[WM831X_ISINK_MAX_ISEL];
591 1217
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-23 00:24:37 -0500