7 files changed, 55 insertions, 55 deletions

diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index 2ba9ab953731..04f1d29cba2c 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -214,8 +214,8 @@ int omap1_select_table_rate(struct clk *clk, unsigned long rate)
         struct mpu_rate * ptr;
         unsigned long dpll1_rate, ref_rate;
 
-        dpll1_rate = clk_get_rate(ck_dpll1_p);
-        ref_rate = clk_get_rate(ck_ref_p);
+        dpll1_rate = ck_dpll1_p->rate;
+        ref_rate = ck_ref_p->rate;
 
         for (ptr = omap1_rate_table; ptr->rate; ptr++) {
                 if (ptr->xtal != ref_rate)
@@ -306,7 +306,7 @@ long omap1_round_to_table_rate(struct clk *clk, unsigned long rate)
         long highest_rate;
         unsigned long ref_rate;
 
-        ref_rate = clk_get_rate(ck_ref_p);
+        ref_rate = ck_ref_p->rate;
 
         highest_rate = -EINVAL;
 
diff --git a/arch/arm/mach-omap2/clock34xx_data.c b/arch/arm/mach-omap2/clock34xx_data.c
index c6031d74d6f6..74930e3158e3 100644
--- a/arch/arm/mach-omap2/clock34xx_data.c
+++ b/arch/arm/mach-omap2/clock34xx_data.c
@@ -671,7 +671,6 @@ static struct clk dpll4_m3x2_ck = {
         .name           = "dpll4_m3x2_ck",
         .ops            = &clkops_omap2_dflt_wait,
         .parent         = &dpll4_m3_ck,
-        .init           = &omap2_init_clksel_parent,
         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
         .flags          = INVERT_ENABLE,
@@ -811,7 +810,6 @@ static struct clk dpll4_m6x2_ck = {
         .name           = "dpll4_m6x2_ck",
         .ops            = &clkops_omap2_dflt_wait,
         .parent         = &dpll4_m6_ck,
-        .init           = &omap2_init_clksel_parent,
         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
         .flags          = INVERT_ENABLE,
@@ -1047,7 +1045,6 @@ static struct clk iva2_ck = {
         .name           = "iva2_ck",
         .ops            = &clkops_omap2_dflt_wait,
         .parent         = &dpll2_m2_ck,
-        .init           = &omap2_init_clksel_parent,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
         .clkdm_name     = "iva2_clkdm",
@@ -1121,7 +1118,6 @@ static struct clk gfx_l3_ck = {
         .name           = "gfx_l3_ck",
         .ops            = &clkops_omap2_dflt_wait,
         .parent         = &l3_ick,
-        .init           = &omap2_init_clksel_parent,
         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
         .enable_bit     = OMAP_EN_GFX_SHIFT,
         .recalc         = &followparent_recalc,
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 2210e227d78a..9d882bcb56e3 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -346,37 +346,37 @@ static struct clk aess_fclk = {
 };
 
 static const struct clksel_rate div31_1to31_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_4430 },
-        { .div = 2, .val = 1, .flags = RATE_IN_4430 },
-        { .div = 3, .val = 2, .flags = RATE_IN_4430 },
-        { .div = 4, .val = 3, .flags = RATE_IN_4430 },
-        { .div = 5, .val = 4, .flags = RATE_IN_4430 },
-        { .div = 6, .val = 5, .flags = RATE_IN_4430 },
-        { .div = 7, .val = 6, .flags = RATE_IN_4430 },
-        { .div = 8, .val = 7, .flags = RATE_IN_4430 },
-        { .div = 9, .val = 8, .flags = RATE_IN_4430 },
-        { .div = 10, .val = 9, .flags = RATE_IN_4430 },
-        { .div = 11, .val = 10, .flags = RATE_IN_4430 },
-        { .div = 12, .val = 11, .flags = RATE_IN_4430 },
-        { .div = 13, .val = 12, .flags = RATE_IN_4430 },
-        { .div = 14, .val = 13, .flags = RATE_IN_4430 },
-        { .div = 15, .val = 14, .flags = RATE_IN_4430 },
-        { .div = 16, .val = 15, .flags = RATE_IN_4430 },
-        { .div = 17, .val = 16, .flags = RATE_IN_4430 },
-        { .div = 18, .val = 17, .flags = RATE_IN_4430 },
-        { .div = 19, .val = 18, .flags = RATE_IN_4430 },
-        { .div = 20, .val = 19, .flags = RATE_IN_4430 },
-        { .div = 21, .val = 20, .flags = RATE_IN_4430 },
-        { .div = 22, .val = 21, .flags = RATE_IN_4430 },
-        { .div = 23, .val = 22, .flags = RATE_IN_4430 },
-        { .div = 24, .val = 23, .flags = RATE_IN_4430 },
-        { .div = 25, .val = 24, .flags = RATE_IN_4430 },
-        { .div = 26, .val = 25, .flags = RATE_IN_4430 },
-        { .div = 27, .val = 26, .flags = RATE_IN_4430 },
-        { .div = 28, .val = 27, .flags = RATE_IN_4430 },
-        { .div = 29, .val = 28, .flags = RATE_IN_4430 },
-        { .div = 30, .val = 29, .flags = RATE_IN_4430 },
-        { .div = 31, .val = 30, .flags = RATE_IN_4430 },
+        { .div = 1, .val = 1, .flags = RATE_IN_4430 },
+        { .div = 2, .val = 2, .flags = RATE_IN_4430 },
+        { .div = 3, .val = 3, .flags = RATE_IN_4430 },
+        { .div = 4, .val = 4, .flags = RATE_IN_4430 },
+        { .div = 5, .val = 5, .flags = RATE_IN_4430 },
+        { .div = 6, .val = 6, .flags = RATE_IN_4430 },
+        { .div = 7, .val = 7, .flags = RATE_IN_4430 },
+        { .div = 8, .val = 8, .flags = RATE_IN_4430 },
+        { .div = 9, .val = 9, .flags = RATE_IN_4430 },
+        { .div = 10, .val = 10, .flags = RATE_IN_4430 },
+        { .div = 11, .val = 11, .flags = RATE_IN_4430 },
+        { .div = 12, .val = 12, .flags = RATE_IN_4430 },
+        { .div = 13, .val = 13, .flags = RATE_IN_4430 },
+        { .div = 14, .val = 14, .flags = RATE_IN_4430 },
+        { .div = 15, .val = 15, .flags = RATE_IN_4430 },
+        { .div = 16, .val = 16, .flags = RATE_IN_4430 },
+        { .div = 17, .val = 17, .flags = RATE_IN_4430 },
+        { .div = 18, .val = 18, .flags = RATE_IN_4430 },
+        { .div = 19, .val = 19, .flags = RATE_IN_4430 },
+        { .div = 20, .val = 20, .flags = RATE_IN_4430 },
+        { .div = 21, .val = 21, .flags = RATE_IN_4430 },
+        { .div = 22, .val = 22, .flags = RATE_IN_4430 },
+        { .div = 23, .val = 23, .flags = RATE_IN_4430 },
+        { .div = 24, .val = 24, .flags = RATE_IN_4430 },
+        { .div = 25, .val = 25, .flags = RATE_IN_4430 },
+        { .div = 26, .val = 26, .flags = RATE_IN_4430 },
+        { .div = 27, .val = 27, .flags = RATE_IN_4430 },
+        { .div = 28, .val = 28, .flags = RATE_IN_4430 },
+        { .div = 29, .val = 29, .flags = RATE_IN_4430 },
+        { .div = 30, .val = 30, .flags = RATE_IN_4430 },
+        { .div = 31, .val = 31, .flags = RATE_IN_4430 },
         { .div = 0 },
 };
 
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index d8c8545875b1..478ae585ca39 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -94,7 +94,8 @@ static int _update_sysc_cache(struct omap_hwmod *oh)
 
         oh->_sysc_cache = omap_hwmod_readl(oh, oh->sysconfig->sysc_offs);
 
-        oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED;
+        if (!(oh->sysconfig->sysc_flags & SYSC_NO_CACHE))
+                oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED;
 
         return 0;
 }
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index ea050ce188a7..40f006285163 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -24,6 +24,8 @@
                 OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
 #define OMAP44XX_PRM_REGADDR(module, reg)                               \
                 OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (module) + (reg))
+#define OMAP44XX_CHIRONSS_REGADDR(module, reg)                          \
+                OMAP2_L4_IO_ADDRESS(OMAP4430_CHIRONSS_BASE + (module) + (reg))
 
 #include "prm44xx.h"
 
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index 89be97f0589d..adb2558bb121 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -386,26 +386,26 @@
 
 
 /* CHIRON_PRCM.CHIRONSS_OCP_SOCKET_PRCM register offsets */
-#define OMAP4430_REVISION_PRCM                          OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_OCP_SOCKET_PRCM_MOD, 0x0000)
+#define OMAP4430_REVISION_PRCM                          OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_OCP_SOCKET_PRCM_MOD, 0x0000)
 
 /* CHIRON_PRCM.CHIRONSS_DEVICE_PRM register offsets */
-#define OMAP4430_CHIRON_PRCM_PRM_RSTST                  OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_DEVICE_PRM_MOD, 0x0000)
+#define OMAP4430_CHIRON_PRCM_PRM_RSTST                  OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_DEVICE_PRM_MOD, 0x0000)
 
 /* CHIRON_PRCM.CHIRONSS_CPU0 register offsets */
-#define OMAP4430_PM_PDA_CPU0_PWRSTCTRL                  OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0000)
-#define OMAP4430_PM_PDA_CPU0_PWRSTST                    OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0004)
-#define OMAP4430_RM_PDA_CPU0_CPU0_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0008)
-#define OMAP4430_RM_PDA_CPU0_CPU0_RSTCTRL               OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x000c)
-#define OMAP4430_RM_PDA_CPU0_CPU0_RSTST                 OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0010)
-#define OMAP4430_CM_PDA_CPU0_CPU0_CLKCTRL               OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0014)
-#define OMAP4430_CM_PDA_CPU0_CLKSTCTRL                  OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0018)
+#define OMAP4430_PM_PDA_CPU0_PWRSTCTRL                  OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0000)
+#define OMAP4430_PM_PDA_CPU0_PWRSTST                    OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0004)
+#define OMAP4430_RM_PDA_CPU0_CPU0_CONTEXT               OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0008)
+#define OMAP4430_RM_PDA_CPU0_CPU0_RSTCTRL               OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x000c)
+#define OMAP4430_RM_PDA_CPU0_CPU0_RSTST                 OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0010)
+#define OMAP4430_CM_PDA_CPU0_CPU0_CLKCTRL               OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0014)
+#define OMAP4430_CM_PDA_CPU0_CLKSTCTRL                  OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0018)
 
 /* CHIRON_PRCM.CHIRONSS_CPU1 register offsets */
-#define OMAP4430_PM_PDA_CPU1_PWRSTCTRL                  OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0000)
-#define OMAP4430_PM_PDA_CPU1_PWRSTST                    OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0004)
-#define OMAP4430_RM_PDA_CPU1_CPU1_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0008)
-#define OMAP4430_RM_PDA_CPU1_CPU1_RSTCTRL               OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x000c)
-#define OMAP4430_RM_PDA_CPU1_CPU1_RSTST                 OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0010)
-#define OMAP4430_CM_PDA_CPU1_CPU1_CLKCTRL               OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0014)
-#define OMAP4430_CM_PDA_CPU1_CLKSTCTRL                  OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0018)
+#define OMAP4430_PM_PDA_CPU1_PWRSTCTRL                  OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0000)
+#define OMAP4430_PM_PDA_CPU1_PWRSTST                    OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0004)
+#define OMAP4430_RM_PDA_CPU1_CPU1_CONTEXT               OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0008)
+#define OMAP4430_RM_PDA_CPU1_CPU1_RSTCTRL               OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x000c)
+#define OMAP4430_RM_PDA_CPU1_CPU1_RSTST                 OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0010)
+#define OMAP4430_CM_PDA_CPU1_CPU1_CLKCTRL               OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0014)
+#define OMAP4430_CM_PDA_CPU1_CLKSTCTRL                  OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0018)
 #endif
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 007935a921ea..33933256a226 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -227,6 +227,7 @@ struct omap_hwmod_ocp_if {
 #define SYSC_HAS_SIDLEMODE      (1 << 5)
 #define SYSC_HAS_MIDLEMODE      (1 << 6)
 #define SYSS_MISSING            (1 << 7)
+#define SYSC_NO_CACHE           (1 << 8)  /* XXX SW flag, belongs elsewhere */
 
 /* omap_hwmod_sysconfig.clockact flags */
 #define CLOCKACT_TEST_BOTH      0x0