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-rw-r--r--drivers/media/dvb/dvb-usb/dib0700_devices.c4
-rw-r--r--drivers/media/video/cx23885/cx23885-dvb.c4
2 files changed, 4 insertions, 4 deletions
diff --git a/drivers/media/dvb/dvb-usb/dib0700_devices.c b/drivers/media/dvb/dvb-usb/dib0700_devices.c
index 6477fc66cc23..346223856f59 100644
--- a/drivers/media/dvb/dvb-usb/dib0700_devices.c
+++ b/drivers/media/dvb/dvb-usb/dib0700_devices.c
@@ -299,7 +299,7 @@ static int stk7700d_tuner_attach(struct dvb_usb_adapter *adap)
299} 299}
300 300
301/* STK7700-PH: Digital/Analog Hybrid Tuner, e.h. Cinergy HT USB HE */ 301/* STK7700-PH: Digital/Analog Hybrid Tuner, e.h. Cinergy HT USB HE */
302struct dibx000_agc_config xc3028_agc_config = { 302static struct dibx000_agc_config xc3028_agc_config = {
303 BAND_VHF | BAND_UHF, /* band_caps */ 303 BAND_VHF | BAND_UHF, /* band_caps */
304 304
305 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0, 305 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0,
@@ -342,7 +342,7 @@ struct dibx000_agc_config xc3028_agc_config = {
342}; 342};
343 343
344/* PLL Configuration for COFDM BW_MHz = 8.00 with external clock = 30.00 */ 344/* PLL Configuration for COFDM BW_MHz = 8.00 with external clock = 30.00 */
345struct dibx000_bandwidth_config xc3028_bw_config = { 345static struct dibx000_bandwidth_config xc3028_bw_config = {
346 60000, 30000, /* internal, sampling */ 346 60000, 30000, /* internal, sampling */
347 1, 8, 3, 1, 0, /* pll_cfg: prediv, ratio, range, reset, bypass */ 347 1, 8, 3, 1, 0, /* pll_cfg: prediv, ratio, range, reset, bypass */
348 0, 0, 1, 1, 0, /* misc: refdiv, bypclk_div, IO_CLK_en_core, ADClkSrc, 348 0, 0, 1, 1, 0, /* misc: refdiv, bypclk_div, IO_CLK_en_core, ADClkSrc,
diff --git a/drivers/media/video/cx23885/cx23885-dvb.c b/drivers/media/video/cx23885/cx23885-dvb.c
index 870d6e197d65..f05649727b60 100644
--- a/drivers/media/video/cx23885/cx23885-dvb.c
+++ b/drivers/media/video/cx23885/cx23885-dvb.c
@@ -191,7 +191,7 @@ static struct tda18271_config hauppauge_hvr1200_tuner_config = {
191 .gate = TDA18271_GATE_ANALOG, 191 .gate = TDA18271_GATE_ANALOG,
192}; 192};
193 193
194struct dibx000_agc_config xc3028_agc_config = { 194static struct dibx000_agc_config xc3028_agc_config = {
195 BAND_VHF | BAND_UHF, /* band_caps */ 195 BAND_VHF | BAND_UHF, /* band_caps */
196 196
197 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0, 197 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0,
@@ -237,7 +237,7 @@ struct dibx000_agc_config xc3028_agc_config = {
237 237
238/* PLL Configuration for COFDM BW_MHz = 8.000000 238/* PLL Configuration for COFDM BW_MHz = 8.000000
239 * With external clock = 30.000000 */ 239 * With external clock = 30.000000 */
240struct dibx000_bandwidth_config xc3028_bw_config = { 240static struct dibx000_bandwidth_config xc3028_bw_config = {
241 60000, /* internal */ 241 60000, /* internal */
242 30000, /* sampling */ 242 30000, /* sampling */
243 1, /* pll_cfg: prediv */ 243 1, /* pll_cfg: prediv */