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-rw-r--r--arch/sparc64/kernel/pci_fire.c136
-rw-r--r--arch/sparc64/kernel/pci_psycho.c69
-rw-r--r--arch/sparc64/kernel/pci_sabre.c61
-rw-r--r--arch/sparc64/kernel/pci_schizo.c167
4 files changed, 177 insertions, 256 deletions
diff --git a/arch/sparc64/kernel/pci_fire.c b/arch/sparc64/kernel/pci_fire.c
index 7e1a9b6717b5..9462b68f4894 100644
--- a/arch/sparc64/kernel/pci_fire.c
+++ b/arch/sparc64/kernel/pci_fire.c
@@ -12,27 +12,13 @@
12 12
13#include <asm/prom.h> 13#include <asm/prom.h>
14#include <asm/irq.h> 14#include <asm/irq.h>
15#include <asm/upa.h>
15 16
16#include "pci_impl.h" 17#include "pci_impl.h"
17 18
18#define DRIVER_NAME "fire" 19#define DRIVER_NAME "fire"
19#define PFX DRIVER_NAME ": " 20#define PFX DRIVER_NAME ": "
20 21
21#define fire_read(__reg) \
22({ u64 __ret; \
23 __asm__ __volatile__("ldxa [%1] %2, %0" \
24 : "=r" (__ret) \
25 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
26 : "memory"); \
27 __ret; \
28})
29#define fire_write(__reg, __val) \
30 __asm__ __volatile__("stxa %0, [%1] %2" \
31 : /* no outputs */ \
32 : "r" (__val), "r" (__reg), \
33 "i" (ASI_PHYS_BYPASS_EC_E) \
34 : "memory")
35
36#define FIRE_IOMMU_CONTROL 0x40000UL 22#define FIRE_IOMMU_CONTROL 0x40000UL
37#define FIRE_IOMMU_TSBBASE 0x40008UL 23#define FIRE_IOMMU_TSBBASE 0x40008UL
38#define FIRE_IOMMU_FLUSH 0x40100UL 24#define FIRE_IOMMU_FLUSH 0x40100UL
@@ -65,21 +51,21 @@ static int pci_fire_pbm_iommu_init(struct pci_pbm_info *pbm)
65 /* 51 /*
66 * Invalidate TLB Entries. 52 * Invalidate TLB Entries.
67 */ 53 */
68 fire_write(iommu->iommu_flushinv, ~(u64)0); 54 upa_writeq(~(u64)0, iommu->iommu_flushinv);
69 55
70 err = iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask, 56 err = iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask,
71 pbm->numa_node); 57 pbm->numa_node);
72 if (err) 58 if (err)
73 return err; 59 return err;
74 60
75 fire_write(iommu->iommu_tsbbase, __pa(iommu->page_table) | 0x7UL); 61 upa_writeq(__pa(iommu->page_table) | 0x7UL, iommu->iommu_tsbbase);
76 62
77 control = fire_read(iommu->iommu_control); 63 control = upa_readq(iommu->iommu_control);
78 control |= (0x00000400 /* TSB cache snoop enable */ | 64 control |= (0x00000400 /* TSB cache snoop enable */ |
79 0x00000300 /* Cache mode */ | 65 0x00000300 /* Cache mode */ |
80 0x00000002 /* Bypass enable */ | 66 0x00000002 /* Bypass enable */ |
81 0x00000001 /* Translation enable */); 67 0x00000001 /* Translation enable */);
82 fire_write(iommu->iommu_control, control); 68 upa_writeq(control, iommu->iommu_control);
83 69
84 return 0; 70 return 0;
85} 71}
@@ -161,7 +147,7 @@ struct pci_msiq_entry {
161static int pci_fire_get_head(struct pci_pbm_info *pbm, unsigned long msiqid, 147static int pci_fire_get_head(struct pci_pbm_info *pbm, unsigned long msiqid,
162 unsigned long *head) 148 unsigned long *head)
163{ 149{
164 *head = fire_read(pbm->pbm_regs + EVENT_QUEUE_HEAD(msiqid)); 150 *head = upa_readq(pbm->pbm_regs + EVENT_QUEUE_HEAD(msiqid));
165 return 0; 151 return 0;
166} 152}
167 153
@@ -187,8 +173,7 @@ static int pci_fire_dequeue_msi(struct pci_pbm_info *pbm, unsigned long msiqid,
187 *msi = msi_num = ((ep->word0 & MSIQ_WORD0_DATA0) >> 173 *msi = msi_num = ((ep->word0 & MSIQ_WORD0_DATA0) >>
188 MSIQ_WORD0_DATA0_SHIFT); 174 MSIQ_WORD0_DATA0_SHIFT);
189 175
190 fire_write(pbm->pbm_regs + MSI_CLEAR(msi_num), 176 upa_writeq(MSI_CLEAR_EQWR_N, pbm->pbm_regs + MSI_CLEAR(msi_num));
191 MSI_CLEAR_EQWR_N);
192 177
193 /* Clear the entry. */ 178 /* Clear the entry. */
194 ep->word0 &= ~MSIQ_WORD0_FMT_TYPE; 179 ep->word0 &= ~MSIQ_WORD0_FMT_TYPE;
@@ -204,7 +189,7 @@ static int pci_fire_dequeue_msi(struct pci_pbm_info *pbm, unsigned long msiqid,
204static int pci_fire_set_head(struct pci_pbm_info *pbm, unsigned long msiqid, 189static int pci_fire_set_head(struct pci_pbm_info *pbm, unsigned long msiqid,
205 unsigned long head) 190 unsigned long head)
206{ 191{
207 fire_write(pbm->pbm_regs + EVENT_QUEUE_HEAD(msiqid), head); 192 upa_writeq(head, pbm->pbm_regs + EVENT_QUEUE_HEAD(msiqid));
208 return 0; 193 return 0;
209} 194}
210 195
@@ -213,17 +198,16 @@ static int pci_fire_msi_setup(struct pci_pbm_info *pbm, unsigned long msiqid,
213{ 198{
214 u64 val; 199 u64 val;
215 200
216 val = fire_read(pbm->pbm_regs + MSI_MAP(msi)); 201 val = upa_readq(pbm->pbm_regs + MSI_MAP(msi));
217 val &= ~(MSI_MAP_EQNUM); 202 val &= ~(MSI_MAP_EQNUM);
218 val |= msiqid; 203 val |= msiqid;
219 fire_write(pbm->pbm_regs + MSI_MAP(msi), val); 204 upa_writeq(val, pbm->pbm_regs + MSI_MAP(msi));
220 205
221 fire_write(pbm->pbm_regs + MSI_CLEAR(msi), 206 upa_writeq(MSI_CLEAR_EQWR_N, pbm->pbm_regs + MSI_CLEAR(msi));
222 MSI_CLEAR_EQWR_N);
223 207
224 val = fire_read(pbm->pbm_regs + MSI_MAP(msi)); 208 val = upa_readq(pbm->pbm_regs + MSI_MAP(msi));
225 val |= MSI_MAP_VALID; 209 val |= MSI_MAP_VALID;
226 fire_write(pbm->pbm_regs + MSI_MAP(msi), val); 210 upa_writeq(val, pbm->pbm_regs + MSI_MAP(msi));
227 211
228 return 0; 212 return 0;
229} 213}
@@ -233,12 +217,12 @@ static int pci_fire_msi_teardown(struct pci_pbm_info *pbm, unsigned long msi)
233 unsigned long msiqid; 217 unsigned long msiqid;
234 u64 val; 218 u64 val;
235 219
236 val = fire_read(pbm->pbm_regs + MSI_MAP(msi)); 220 val = upa_readq(pbm->pbm_regs + MSI_MAP(msi));
237 msiqid = (val & MSI_MAP_EQNUM); 221 msiqid = (val & MSI_MAP_EQNUM);
238 222
239 val &= ~MSI_MAP_VALID; 223 val &= ~MSI_MAP_VALID;
240 224
241 fire_write(pbm->pbm_regs + MSI_MAP(msi), val); 225 upa_writeq(val, pbm->pbm_regs + MSI_MAP(msi));
242 226
243 return 0; 227 return 0;
244} 228}
@@ -257,22 +241,19 @@ static int pci_fire_msiq_alloc(struct pci_pbm_info *pbm)
257 memset((char *)pages, 0, PAGE_SIZE << order); 241 memset((char *)pages, 0, PAGE_SIZE << order);
258 pbm->msi_queues = (void *) pages; 242 pbm->msi_queues = (void *) pages;
259 243
260 fire_write(pbm->pbm_regs + EVENT_QUEUE_BASE_ADDR_REG, 244 upa_writeq((EVENT_QUEUE_BASE_ADDR_ALL_ONES |
261 (EVENT_QUEUE_BASE_ADDR_ALL_ONES | 245 __pa(pbm->msi_queues)),
262 __pa(pbm->msi_queues))); 246 pbm->pbm_regs + EVENT_QUEUE_BASE_ADDR_REG);
263 247
264 fire_write(pbm->pbm_regs + IMONDO_DATA0, 248 upa_writeq(pbm->portid << 6, pbm->pbm_regs + IMONDO_DATA0);
265 pbm->portid << 6); 249 upa_writeq(0, pbm->pbm_regs + IMONDO_DATA1);
266 fire_write(pbm->pbm_regs + IMONDO_DATA1, 0);
267 250
268 fire_write(pbm->pbm_regs + MSI_32BIT_ADDR, 251 upa_writeq(pbm->msi32_start, pbm->pbm_regs + MSI_32BIT_ADDR);
269 pbm->msi32_start); 252 upa_writeq(pbm->msi64_start, pbm->pbm_regs + MSI_64BIT_ADDR);
270 fire_write(pbm->pbm_regs + MSI_64BIT_ADDR,
271 pbm->msi64_start);
272 253
273 for (i = 0; i < pbm->msiq_num; i++) { 254 for (i = 0; i < pbm->msiq_num; i++) {
274 fire_write(pbm->pbm_regs + EVENT_QUEUE_HEAD(i), 0); 255 upa_writeq(0, pbm->pbm_regs + EVENT_QUEUE_HEAD(i));
275 fire_write(pbm->pbm_regs + EVENT_QUEUE_TAIL(i), 0); 256 upa_writeq(0, pbm->pbm_regs + EVENT_QUEUE_TAIL(i));
276 } 257 }
277 258
278 return 0; 259 return 0;
@@ -306,9 +287,9 @@ static int pci_fire_msiq_build_irq(struct pci_pbm_info *pbm,
306 /* XXX iterate amongst the 4 IRQ controllers XXX */ 287 /* XXX iterate amongst the 4 IRQ controllers XXX */
307 int_ctrlr = (1UL << 6); 288 int_ctrlr = (1UL << 6);
308 289
309 val = fire_read(imap_reg); 290 val = upa_readq(imap_reg);
310 val |= (1UL << 63) | int_ctrlr; 291 val |= (1UL << 63) | int_ctrlr;
311 fire_write(imap_reg, val); 292 upa_writeq(val, imap_reg);
312 293
313 fixup = ((pbm->portid << 6) | devino) - int_ctrlr; 294 fixup = ((pbm->portid << 6) | devino) - int_ctrlr;
314 295
@@ -316,9 +297,8 @@ static int pci_fire_msiq_build_irq(struct pci_pbm_info *pbm,
316 if (!virt_irq) 297 if (!virt_irq)
317 return -ENOMEM; 298 return -ENOMEM;
318 299
319 fire_write(pbm->pbm_regs + 300 upa_writeq(EVENT_QUEUE_CONTROL_SET_EN,
320 EVENT_QUEUE_CONTROL_SET(msiqid), 301 pbm->pbm_regs + EVENT_QUEUE_CONTROL_SET(msiqid));
321 EVENT_QUEUE_CONTROL_SET_EN);
322 302
323 return virt_irq; 303 return virt_irq;
324} 304}
@@ -386,49 +366,47 @@ static void pci_fire_hw_init(struct pci_pbm_info *pbm)
386{ 366{
387 u64 val; 367 u64 val;
388 368
389 fire_write(pbm->controller_regs + FIRE_PARITY_CONTROL, 369 upa_writeq(FIRE_PARITY_ENAB,
390 FIRE_PARITY_ENAB); 370 pbm->controller_regs + FIRE_PARITY_CONTROL);
391 371
392 fire_write(pbm->controller_regs + FIRE_FATAL_RESET_CTL, 372 upa_writeq((FIRE_FATAL_RESET_SPARE |
393 (FIRE_FATAL_RESET_SPARE |
394 FIRE_FATAL_RESET_MB | 373 FIRE_FATAL_RESET_MB |
395 FIRE_FATAL_RESET_CPE | 374 FIRE_FATAL_RESET_CPE |
396 FIRE_FATAL_RESET_APE | 375 FIRE_FATAL_RESET_APE |
397 FIRE_FATAL_RESET_PIO | 376 FIRE_FATAL_RESET_PIO |
398 FIRE_FATAL_RESET_JW | 377 FIRE_FATAL_RESET_JW |
399 FIRE_FATAL_RESET_JI | 378 FIRE_FATAL_RESET_JI |
400 FIRE_FATAL_RESET_JR)); 379 FIRE_FATAL_RESET_JR),
380 pbm->controller_regs + FIRE_FATAL_RESET_CTL);
401 381
402 fire_write(pbm->controller_regs + FIRE_CORE_INTR_ENABLE, ~(u64)0); 382 upa_writeq(~(u64)0, pbm->controller_regs + FIRE_CORE_INTR_ENABLE);
403 383
404 val = fire_read(pbm->pbm_regs + FIRE_TLU_CTRL); 384 val = upa_readq(pbm->pbm_regs + FIRE_TLU_CTRL);
405 val |= (FIRE_TLU_CTRL_TIM | 385 val |= (FIRE_TLU_CTRL_TIM |
406 FIRE_TLU_CTRL_QDET | 386 FIRE_TLU_CTRL_QDET |
407 FIRE_TLU_CTRL_CFG); 387 FIRE_TLU_CTRL_CFG);
408 fire_write(pbm->pbm_regs + FIRE_TLU_CTRL, val); 388 upa_writeq(val, pbm->pbm_regs + FIRE_TLU_CTRL);
409 fire_write(pbm->pbm_regs + FIRE_TLU_DEV_CTRL, 0); 389 upa_writeq(0, pbm->pbm_regs + FIRE_TLU_DEV_CTRL);
410 fire_write(pbm->pbm_regs + FIRE_TLU_LINK_CTRL, 390 upa_writeq(FIRE_TLU_LINK_CTRL_CLK,
411 FIRE_TLU_LINK_CTRL_CLK); 391 pbm->pbm_regs + FIRE_TLU_LINK_CTRL);
412 392
413 fire_write(pbm->pbm_regs + FIRE_LPU_RESET, 0); 393 upa_writeq(0, pbm->pbm_regs + FIRE_LPU_RESET);
414 fire_write(pbm->pbm_regs + FIRE_LPU_LLCFG, 394 upa_writeq(FIRE_LPU_LLCFG_VC0, pbm->pbm_regs + FIRE_LPU_LLCFG);
415 FIRE_LPU_LLCFG_VC0); 395 upa_writeq((FIRE_LPU_FCTRL_UCTRL_N | FIRE_LPU_FCTRL_UCTRL_P),
416 fire_write(pbm->pbm_regs + FIRE_LPU_FCTRL_UCTRL, 396 pbm->pbm_regs + FIRE_LPU_FCTRL_UCTRL);
417 (FIRE_LPU_FCTRL_UCTRL_N | 397 upa_writeq(((0xffff << 16) | (0x0000 << 0)),
418 FIRE_LPU_FCTRL_UCTRL_P)); 398 pbm->pbm_regs + FIRE_LPU_TXL_FIFOP);
419 fire_write(pbm->pbm_regs + FIRE_LPU_TXL_FIFOP, 399 upa_writeq(3000000, pbm->pbm_regs + FIRE_LPU_LTSSM_CFG2);
420 ((0xffff << 16) | (0x0000 << 0))); 400 upa_writeq(500000, pbm->pbm_regs + FIRE_LPU_LTSSM_CFG3);
421 fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG2, 3000000); 401 upa_writeq((2 << 16) | (140 << 8),
422 fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG3, 500000); 402 pbm->pbm_regs + FIRE_LPU_LTSSM_CFG4);
423 fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG4, 403 upa_writeq(0, pbm->pbm_regs + FIRE_LPU_LTSSM_CFG5);
424 (2 << 16) | (140 << 8)); 404
425 fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG5, 0); 405 upa_writeq(~(u64)0, pbm->pbm_regs + FIRE_DMC_IENAB);
426 406 upa_writeq(0, pbm->pbm_regs + FIRE_DMC_DBG_SEL_A);
427 fire_write(pbm->pbm_regs + FIRE_DMC_IENAB, ~(u64)0); 407 upa_writeq(0, pbm->pbm_regs + FIRE_DMC_DBG_SEL_B);
428 fire_write(pbm->pbm_regs + FIRE_DMC_DBG_SEL_A, 0); 408
429 fire_write(pbm->pbm_regs + FIRE_DMC_DBG_SEL_B, 0); 409 upa_writeq(~(u64)0, pbm->pbm_regs + FIRE_PEC_IENAB);
430
431 fire_write(pbm->pbm_regs + FIRE_PEC_IENAB, ~(u64)0);
432} 410}
433 411
434static int __init pci_fire_pbm_init(struct pci_pbm_info *pbm, 412static int __init pci_fire_pbm_init(struct pci_pbm_info *pbm,
diff --git a/arch/sparc64/kernel/pci_psycho.c b/arch/sparc64/kernel/pci_psycho.c
index bac9c1ba40e0..897334680657 100644
--- a/arch/sparc64/kernel/pci_psycho.c
+++ b/arch/sparc64/kernel/pci_psycho.c
@@ -17,6 +17,7 @@
17#include <asm/irq.h> 17#include <asm/irq.h>
18#include <asm/starfire.h> 18#include <asm/starfire.h>
19#include <asm/prom.h> 19#include <asm/prom.h>
20#include <asm/upa.h>
20 21
21#include "pci_impl.h" 22#include "pci_impl.h"
22#include "iommu_common.h" 23#include "iommu_common.h"
@@ -25,25 +26,6 @@
25#define DRIVER_NAME "psycho" 26#define DRIVER_NAME "psycho"
26#define PFX DRIVER_NAME ": " 27#define PFX DRIVER_NAME ": "
27 28
28/* All PSYCHO registers are 64-bits. The following accessor
29 * routines are how they are accessed. The REG parameter
30 * is a physical address.
31 */
32#define psycho_read(__reg) \
33({ u64 __ret; \
34 __asm__ __volatile__("ldxa [%1] %2, %0" \
35 : "=r" (__ret) \
36 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
37 : "memory"); \
38 __ret; \
39})
40#define psycho_write(__reg, __val) \
41 __asm__ __volatile__("stxa %0, [%1] %2" \
42 : /* no outputs */ \
43 : "r" (__val), "r" (__reg), \
44 "i" (ASI_PHYS_BYPASS_EC_E) \
45 : "memory")
46
47/* Misc. PSYCHO PCI controller register offsets and definitions. */ 29/* Misc. PSYCHO PCI controller register offsets and definitions. */
48#define PSYCHO_CONTROL 0x0010UL 30#define PSYCHO_CONTROL 0x0010UL
49#define PSYCHO_CONTROL_IMPL 0xf000000000000000UL /* Implementation of this PSYCHO*/ 31#define PSYCHO_CONTROL_IMPL 0xf000000000000000UL /* Implementation of this PSYCHO*/
@@ -182,8 +164,8 @@ static irqreturn_t psycho_ue_intr(int irq, void *dev_id)
182 int reported; 164 int reported;
183 165
184 /* Latch uncorrectable error status. */ 166 /* Latch uncorrectable error status. */
185 afar = psycho_read(afar_reg); 167 afar = upa_readq(afar_reg);
186 afsr = psycho_read(afsr_reg); 168 afsr = upa_readq(afsr_reg);
187 169
188 /* Clear the primary/secondary error status bits. */ 170 /* Clear the primary/secondary error status bits. */
189 error_bits = afsr & 171 error_bits = afsr &
@@ -191,7 +173,7 @@ static irqreturn_t psycho_ue_intr(int irq, void *dev_id)
191 PSYCHO_UEAFSR_SPIO | PSYCHO_UEAFSR_SDRD | PSYCHO_UEAFSR_SDWR); 173 PSYCHO_UEAFSR_SPIO | PSYCHO_UEAFSR_SDRD | PSYCHO_UEAFSR_SDWR);
192 if (!error_bits) 174 if (!error_bits)
193 return IRQ_NONE; 175 return IRQ_NONE;
194 psycho_write(afsr_reg, error_bits); 176 upa_writeq(error_bits, afsr_reg);
195 177
196 /* Log the error. */ 178 /* Log the error. */
197 printk("%s: Uncorrectable Error, primary error type[%s]\n", 179 printk("%s: Uncorrectable Error, primary error type[%s]\n",
@@ -261,8 +243,8 @@ static irqreturn_t psycho_ce_intr(int irq, void *dev_id)
261 int reported; 243 int reported;
262 244
263 /* Latch error status. */ 245 /* Latch error status. */
264 afar = psycho_read(afar_reg); 246 afar = upa_readq(afar_reg);
265 afsr = psycho_read(afsr_reg); 247 afsr = upa_readq(afsr_reg);
266 248
267 /* Clear primary/secondary error status bits. */ 249 /* Clear primary/secondary error status bits. */
268 error_bits = afsr & 250 error_bits = afsr &
@@ -270,7 +252,7 @@ static irqreturn_t psycho_ce_intr(int irq, void *dev_id)
270 PSYCHO_CEAFSR_SPIO | PSYCHO_CEAFSR_SDRD | PSYCHO_CEAFSR_SDWR); 252 PSYCHO_CEAFSR_SPIO | PSYCHO_CEAFSR_SDRD | PSYCHO_CEAFSR_SDWR);
271 if (!error_bits) 253 if (!error_bits)
272 return IRQ_NONE; 254 return IRQ_NONE;
273 psycho_write(afsr_reg, error_bits); 255 upa_writeq(error_bits, afsr_reg);
274 256
275 /* Log the error. */ 257 /* Log the error. */
276 printk("%s: Correctable Error, primary error type[%s]\n", 258 printk("%s: Correctable Error, primary error type[%s]\n",
@@ -373,27 +355,26 @@ static void psycho_register_error_handlers(struct pci_pbm_info *pbm)
373 "err=%d\n", pbm->name, err); 355 "err=%d\n", pbm->name, err);
374 356
375 /* Enable UE and CE interrupts for controller. */ 357 /* Enable UE and CE interrupts for controller. */
376 psycho_write(base + PSYCHO_ECC_CTRL, 358 upa_writeq((PSYCHO_ECCCTRL_EE |
377 (PSYCHO_ECCCTRL_EE | 359 PSYCHO_ECCCTRL_UE |
378 PSYCHO_ECCCTRL_UE | 360 PSYCHO_ECCCTRL_CE), base + PSYCHO_ECC_CTRL);
379 PSYCHO_ECCCTRL_CE));
380 361
381 /* Enable PCI Error interrupts and clear error 362 /* Enable PCI Error interrupts and clear error
382 * bits for each PBM. 363 * bits for each PBM.
383 */ 364 */
384 tmp = psycho_read(base + PSYCHO_PCIA_CTRL); 365 tmp = upa_readq(base + PSYCHO_PCIA_CTRL);
385 tmp |= (PSYCHO_PCICTRL_SERR | 366 tmp |= (PSYCHO_PCICTRL_SERR |
386 PSYCHO_PCICTRL_SBH_ERR | 367 PSYCHO_PCICTRL_SBH_ERR |
387 PSYCHO_PCICTRL_EEN); 368 PSYCHO_PCICTRL_EEN);
388 tmp &= ~(PSYCHO_PCICTRL_SBH_INT); 369 tmp &= ~(PSYCHO_PCICTRL_SBH_INT);
389 psycho_write(base + PSYCHO_PCIA_CTRL, tmp); 370 upa_writeq(tmp, base + PSYCHO_PCIA_CTRL);
390 371
391 tmp = psycho_read(base + PSYCHO_PCIB_CTRL); 372 tmp = upa_readq(base + PSYCHO_PCIB_CTRL);
392 tmp |= (PSYCHO_PCICTRL_SERR | 373 tmp |= (PSYCHO_PCICTRL_SERR |
393 PSYCHO_PCICTRL_SBH_ERR | 374 PSYCHO_PCICTRL_SBH_ERR |
394 PSYCHO_PCICTRL_EEN); 375 PSYCHO_PCICTRL_EEN);
395 tmp &= ~(PSYCHO_PCICTRL_SBH_INT); 376 tmp &= ~(PSYCHO_PCICTRL_SBH_INT);
396 psycho_write(base + PSYCHO_PCIB_CTRL, tmp); 377 upa_writeq(tmp, base + PSYCHO_PCIB_CTRL);
397} 378}
398 379
399/* PSYCHO boot time probing and initialization. */ 380/* PSYCHO boot time probing and initialization. */
@@ -443,28 +424,28 @@ static void psycho_controller_hwinit(struct pci_pbm_info *pbm)
443{ 424{
444 u64 tmp; 425 u64 tmp;
445 426
446 psycho_write(pbm->controller_regs + PSYCHO_IRQ_RETRY, 5); 427 upa_writeq(5, pbm->controller_regs + PSYCHO_IRQ_RETRY);
447 428
448 /* Enable arbiter for all PCI slots. */ 429 /* Enable arbiter for all PCI slots. */
449 tmp = psycho_read(pbm->controller_regs + PSYCHO_PCIA_CTRL); 430 tmp = upa_readq(pbm->controller_regs + PSYCHO_PCIA_CTRL);
450 tmp |= PSYCHO_PCICTRL_AEN; 431 tmp |= PSYCHO_PCICTRL_AEN;
451 psycho_write(pbm->controller_regs + PSYCHO_PCIA_CTRL, tmp); 432 upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIA_CTRL);
452 433
453 tmp = psycho_read(pbm->controller_regs + PSYCHO_PCIB_CTRL); 434 tmp = upa_readq(pbm->controller_regs + PSYCHO_PCIB_CTRL);
454 tmp |= PSYCHO_PCICTRL_AEN; 435 tmp |= PSYCHO_PCICTRL_AEN;
455 psycho_write(pbm->controller_regs + PSYCHO_PCIB_CTRL, tmp); 436 upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIB_CTRL);
456 437
457 /* Disable DMA write / PIO read synchronization on 438 /* Disable DMA write / PIO read synchronization on
458 * both PCI bus segments. 439 * both PCI bus segments.
459 * [ U2P Erratum 1243770, STP2223BGA data sheet ] 440 * [ U2P Erratum 1243770, STP2223BGA data sheet ]
460 */ 441 */
461 tmp = psycho_read(pbm->controller_regs + PSYCHO_PCIA_DIAG); 442 tmp = upa_readq(pbm->controller_regs + PSYCHO_PCIA_DIAG);
462 tmp |= PSYCHO_PCIDIAG_DDWSYNC; 443 tmp |= PSYCHO_PCIDIAG_DDWSYNC;
463 psycho_write(pbm->controller_regs + PSYCHO_PCIA_DIAG, tmp); 444 upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIA_DIAG);
464 445
465 tmp = psycho_read(pbm->controller_regs + PSYCHO_PCIB_DIAG); 446 tmp = upa_readq(pbm->controller_regs + PSYCHO_PCIB_DIAG);
466 tmp |= PSYCHO_PCIDIAG_DDWSYNC; 447 tmp |= PSYCHO_PCIDIAG_DDWSYNC;
467 psycho_write(pbm->controller_regs + PSYCHO_PCIB_DIAG, tmp); 448 upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIB_DIAG);
468} 449}
469 450
470static void psycho_pbm_strbuf_init(struct pci_pbm_info *pbm, 451static void psycho_pbm_strbuf_init(struct pci_pbm_info *pbm,
@@ -509,7 +490,7 @@ static void psycho_pbm_strbuf_init(struct pci_pbm_info *pbm,
509 */ 490 */
510#undef PSYCHO_STRBUF_RERUN_ENABLE 491#undef PSYCHO_STRBUF_RERUN_ENABLE
511#undef PSYCHO_STRBUF_RERUN_DISABLE 492#undef PSYCHO_STRBUF_RERUN_DISABLE
512 control = psycho_read(pbm->stc.strbuf_control); 493 control = upa_readq(pbm->stc.strbuf_control);
513 control |= PSYCHO_STRBUF_CTRL_ENAB; 494 control |= PSYCHO_STRBUF_CTRL_ENAB;
514 control &= ~(PSYCHO_STRBUF_CTRL_LENAB | PSYCHO_STRBUF_CTRL_LPTR); 495 control &= ~(PSYCHO_STRBUF_CTRL_LENAB | PSYCHO_STRBUF_CTRL_LPTR);
515#ifdef PSYCHO_STRBUF_RERUN_ENABLE 496#ifdef PSYCHO_STRBUF_RERUN_ENABLE
@@ -519,7 +500,7 @@ static void psycho_pbm_strbuf_init(struct pci_pbm_info *pbm,
519 control |= PSYCHO_STRBUF_CTRL_RRDIS; 500 control |= PSYCHO_STRBUF_CTRL_RRDIS;
520#endif 501#endif
521#endif 502#endif
522 psycho_write(pbm->stc.strbuf_control, control); 503 upa_writeq(control, pbm->stc.strbuf_control);
523 504
524 pbm->stc.strbuf_enabled = 1; 505 pbm->stc.strbuf_enabled = 1;
525} 506}
diff --git a/arch/sparc64/kernel/pci_sabre.c b/arch/sparc64/kernel/pci_sabre.c
index f8089aa84f64..713257b6963c 100644
--- a/arch/sparc64/kernel/pci_sabre.c
+++ b/arch/sparc64/kernel/pci_sabre.c
@@ -17,6 +17,7 @@
17#include <asm/iommu.h> 17#include <asm/iommu.h>
18#include <asm/irq.h> 18#include <asm/irq.h>
19#include <asm/prom.h> 19#include <asm/prom.h>
20#include <asm/upa.h>
20 21
21#include "pci_impl.h" 22#include "pci_impl.h"
22#include "iommu_common.h" 23#include "iommu_common.h"
@@ -25,25 +26,6 @@
25#define DRIVER_NAME "sabre" 26#define DRIVER_NAME "sabre"
26#define PFX DRIVER_NAME ": " 27#define PFX DRIVER_NAME ": "
27 28
28/* All SABRE registers are 64-bits. The following accessor
29 * routines are how they are accessed. The REG parameter
30 * is a physical address.
31 */
32#define sabre_read(__reg) \
33({ u64 __ret; \
34 __asm__ __volatile__("ldxa [%1] %2, %0" \
35 : "=r" (__ret) \
36 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
37 : "memory"); \
38 __ret; \
39})
40#define sabre_write(__reg, __val) \
41 __asm__ __volatile__("stxa %0, [%1] %2" \
42 : /* no outputs */ \
43 : "r" (__val), "r" (__reg), \
44 "i" (ASI_PHYS_BYPASS_EC_E) \
45 : "memory")
46
47/* SABRE PCI controller register offsets and definitions. */ 29/* SABRE PCI controller register offsets and definitions. */
48#define SABRE_UE_AFSR 0x0030UL 30#define SABRE_UE_AFSR 0x0030UL
49#define SABRE_UEAFSR_PDRD 0x4000000000000000UL /* Primary PCI DMA Read */ 31#define SABRE_UEAFSR_PDRD 0x4000000000000000UL /* Primary PCI DMA Read */
@@ -219,8 +201,8 @@ static irqreturn_t sabre_ue_intr(int irq, void *dev_id)
219 int reported; 201 int reported;
220 202
221 /* Latch uncorrectable error status. */ 203 /* Latch uncorrectable error status. */
222 afar = sabre_read(afar_reg); 204 afar = upa_readq(afar_reg);
223 afsr = sabre_read(afsr_reg); 205 afsr = upa_readq(afsr_reg);
224 206
225 /* Clear the primary/secondary error status bits. */ 207 /* Clear the primary/secondary error status bits. */
226 error_bits = afsr & 208 error_bits = afsr &
@@ -229,7 +211,7 @@ static irqreturn_t sabre_ue_intr(int irq, void *dev_id)
229 SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE); 211 SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE);
230 if (!error_bits) 212 if (!error_bits)
231 return IRQ_NONE; 213 return IRQ_NONE;
232 sabre_write(afsr_reg, error_bits); 214 upa_writeq(error_bits, afsr_reg);
233 215
234 /* Log the error. */ 216 /* Log the error. */
235 printk("%s: Uncorrectable Error, primary error type[%s%s]\n", 217 printk("%s: Uncorrectable Error, primary error type[%s%s]\n",
@@ -279,8 +261,8 @@ static irqreturn_t sabre_ce_intr(int irq, void *dev_id)
279 int reported; 261 int reported;
280 262
281 /* Latch error status. */ 263 /* Latch error status. */
282 afar = sabre_read(afar_reg); 264 afar = upa_readq(afar_reg);
283 afsr = sabre_read(afsr_reg); 265 afsr = upa_readq(afsr_reg);
284 266
285 /* Clear primary/secondary error status bits. */ 267 /* Clear primary/secondary error status bits. */
286 error_bits = afsr & 268 error_bits = afsr &
@@ -288,7 +270,7 @@ static irqreturn_t sabre_ce_intr(int irq, void *dev_id)
288 SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR); 270 SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR);
289 if (!error_bits) 271 if (!error_bits)
290 return IRQ_NONE; 272 return IRQ_NONE;
291 sabre_write(afsr_reg, error_bits); 273 upa_writeq(error_bits, afsr_reg);
292 274
293 /* Log the error. */ 275 /* Log the error. */
294 printk("%s: Correctable Error, primary error type[%s]\n", 276 printk("%s: Correctable Error, primary error type[%s]\n",
@@ -354,19 +336,20 @@ static void sabre_register_error_handlers(struct pci_pbm_info *pbm)
354 * registering the handler so that we don't get spurious 336 * registering the handler so that we don't get spurious
355 * interrupts. 337 * interrupts.
356 */ 338 */
357 sabre_write(base + SABRE_UE_AFSR, 339 upa_writeq((SABRE_UEAFSR_PDRD | SABRE_UEAFSR_PDWR |
358 (SABRE_UEAFSR_PDRD | SABRE_UEAFSR_PDWR | 340 SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR |
359 SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR | 341 SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE),
360 SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE)); 342 base + SABRE_UE_AFSR);
361 343
362 err = request_irq(op->irqs[1], sabre_ue_intr, 0, "SABRE_UE", pbm); 344 err = request_irq(op->irqs[1], sabre_ue_intr, 0, "SABRE_UE", pbm);
363 if (err) 345 if (err)
364 printk(KERN_WARNING "%s: Couldn't register UE, err=%d.\n", 346 printk(KERN_WARNING "%s: Couldn't register UE, err=%d.\n",
365 pbm->name, err); 347 pbm->name, err);
366 348
367 sabre_write(base + SABRE_CE_AFSR, 349 upa_writeq((SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR |
368 (SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR | 350 SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR),
369 SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR)); 351 base + SABRE_CE_AFSR);
352
370 353
371 err = request_irq(op->irqs[2], sabre_ce_intr, 0, "SABRE_CE", pbm); 354 err = request_irq(op->irqs[2], sabre_ce_intr, 0, "SABRE_CE", pbm);
372 if (err) 355 if (err)
@@ -378,9 +361,9 @@ static void sabre_register_error_handlers(struct pci_pbm_info *pbm)
378 printk(KERN_WARNING "%s: Couldn't register PCIERR, err=%d.\n", 361 printk(KERN_WARNING "%s: Couldn't register PCIERR, err=%d.\n",
379 pbm->name, err); 362 pbm->name, err);
380 363
381 tmp = sabre_read(base + SABRE_PCICTRL); 364 tmp = upa_readq(base + SABRE_PCICTRL);
382 tmp |= SABRE_PCICTRL_ERREN; 365 tmp |= SABRE_PCICTRL_ERREN;
383 sabre_write(base + SABRE_PCICTRL, tmp); 366 upa_writeq(tmp, base + SABRE_PCICTRL);
384} 367}
385 368
386static void apb_init(struct pci_bus *sabre_bus) 369static void apb_init(struct pci_bus *sabre_bus)
@@ -533,16 +516,16 @@ static int __devinit sabre_probe(struct of_device *op,
533 516
534 /* PCI first */ 517 /* PCI first */
535 for (clear_irq = SABRE_ICLR_A_SLOT0; clear_irq < SABRE_ICLR_B_SLOT0 + 0x80; clear_irq += 8) 518 for (clear_irq = SABRE_ICLR_A_SLOT0; clear_irq < SABRE_ICLR_B_SLOT0 + 0x80; clear_irq += 8)
536 sabre_write(pbm->controller_regs + clear_irq, 0x0UL); 519 upa_writeq(0x0UL, pbm->controller_regs + clear_irq);
537 520
538 /* Then OBIO */ 521 /* Then OBIO */
539 for (clear_irq = SABRE_ICLR_SCSI; clear_irq < SABRE_ICLR_SCSI + 0x80; clear_irq += 8) 522 for (clear_irq = SABRE_ICLR_SCSI; clear_irq < SABRE_ICLR_SCSI + 0x80; clear_irq += 8)
540 sabre_write(pbm->controller_regs + clear_irq, 0x0UL); 523 upa_writeq(0x0UL, pbm->controller_regs + clear_irq);
541 524
542 /* Error interrupts are enabled later after the bus scan. */ 525 /* Error interrupts are enabled later after the bus scan. */
543 sabre_write(pbm->controller_regs + SABRE_PCICTRL, 526 upa_writeq((SABRE_PCICTRL_MRLEN | SABRE_PCICTRL_SERR |
544 (SABRE_PCICTRL_MRLEN | SABRE_PCICTRL_SERR | 527 SABRE_PCICTRL_ARBPARK | SABRE_PCICTRL_AEN),
545 SABRE_PCICTRL_ARBPARK | SABRE_PCICTRL_AEN)); 528 pbm->controller_regs + SABRE_PCICTRL);
546 529
547 /* Now map in PCI config space for entire SABRE. */ 530 /* Now map in PCI config space for entire SABRE. */
548 pbm->config_space = pbm->controller_regs + SABRE_CONFIGSPACE; 531 pbm->config_space = pbm->controller_regs + SABRE_CONFIGSPACE;
diff --git a/arch/sparc64/kernel/pci_schizo.c b/arch/sparc64/kernel/pci_schizo.c
index c30856541bb4..45d9dba1ba11 100644
--- a/arch/sparc64/kernel/pci_schizo.c
+++ b/arch/sparc64/kernel/pci_schizo.c
@@ -15,6 +15,7 @@
15#include <asm/irq.h> 15#include <asm/irq.h>
16#include <asm/pstate.h> 16#include <asm/pstate.h>
17#include <asm/prom.h> 17#include <asm/prom.h>
18#include <asm/upa.h>
18 19
19#include "pci_impl.h" 20#include "pci_impl.h"
20#include "iommu_common.h" 21#include "iommu_common.h"
@@ -22,25 +23,6 @@
22#define DRIVER_NAME "schizo" 23#define DRIVER_NAME "schizo"
23#define PFX DRIVER_NAME ": " 24#define PFX DRIVER_NAME ": "
24 25
25/* All SCHIZO registers are 64-bits. The following accessor
26 * routines are how they are accessed. The REG parameter
27 * is a physical address.
28 */
29#define schizo_read(__reg) \
30({ u64 __ret; \
31 __asm__ __volatile__("ldxa [%1] %2, %0" \
32 : "=r" (__ret) \
33 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
34 : "memory"); \
35 __ret; \
36})
37#define schizo_write(__reg, __val) \
38 __asm__ __volatile__("stxa %0, [%1] %2" \
39 : /* no outputs */ \
40 : "r" (__val), "r" (__reg), \
41 "i" (ASI_PHYS_BYPASS_EC_E) \
42 : "memory")
43
44/* This is a convention that at least Excalibur and Merlin 26/* This is a convention that at least Excalibur and Merlin
45 * follow. I suppose the SCHIZO used in Starcat and friends 27 * follow. I suppose the SCHIZO used in Starcat and friends
46 * will do similar. 28 * will do similar.
@@ -164,25 +146,25 @@ static void __schizo_check_stc_error_pbm(struct pci_pbm_info *pbm,
164 * invalidating it before it has a chance to reach 146 * invalidating it before it has a chance to reach
165 * main memory. 147 * main memory.
166 */ 148 */
167 control = schizo_read(strbuf->strbuf_control); 149 control = upa_readq(strbuf->strbuf_control);
168 schizo_write(strbuf->strbuf_control, 150 upa_writeq((control | SCHIZO_STRBUF_CTRL_DENAB),
169 (control | SCHIZO_STRBUF_CTRL_DENAB)); 151 strbuf->strbuf_control);
170 for (i = 0; i < 128; i++) { 152 for (i = 0; i < 128; i++) {
171 unsigned long val; 153 unsigned long val;
172 154
173 val = schizo_read(err_base + (i * 8UL)); 155 val = upa_readq(err_base + (i * 8UL));
174 schizo_write(err_base + (i * 8UL), 0UL); 156 upa_writeq(0UL, err_base + (i * 8UL));
175 stc_error_buf[i] = val; 157 stc_error_buf[i] = val;
176 } 158 }
177 for (i = 0; i < 16; i++) { 159 for (i = 0; i < 16; i++) {
178 stc_tag_buf[i] = schizo_read(tag_base + (i * 8UL)); 160 stc_tag_buf[i] = upa_readq(tag_base + (i * 8UL));
179 stc_line_buf[i] = schizo_read(line_base + (i * 8UL)); 161 stc_line_buf[i] = upa_readq(line_base + (i * 8UL));
180 schizo_write(tag_base + (i * 8UL), 0UL); 162 upa_writeq(0UL, tag_base + (i * 8UL));
181 schizo_write(line_base + (i * 8UL), 0UL); 163 upa_writeq(0UL, line_base + (i * 8UL));
182 } 164 }
183 165
184 /* OK, state is logged, exit diagnostic mode. */ 166 /* OK, state is logged, exit diagnostic mode. */
185 schizo_write(strbuf->strbuf_control, control); 167 upa_writeq(control, strbuf->strbuf_control);
186 168
187 for (i = 0; i < 16; i++) { 169 for (i = 0; i < 16; i++) {
188 int j, saw_error, first, last; 170 int j, saw_error, first, last;
@@ -259,14 +241,14 @@ static void schizo_check_iommu_error_pbm(struct pci_pbm_info *pbm,
259 int i; 241 int i;
260 242
261 spin_lock_irqsave(&iommu->lock, flags); 243 spin_lock_irqsave(&iommu->lock, flags);
262 control = schizo_read(iommu->iommu_control); 244 control = upa_readq(iommu->iommu_control);
263 if (control & SCHIZO_IOMMU_CTRL_XLTEERR) { 245 if (control & SCHIZO_IOMMU_CTRL_XLTEERR) {
264 unsigned long base; 246 unsigned long base;
265 char *type_string; 247 char *type_string;
266 248
267 /* Clear the error encountered bit. */ 249 /* Clear the error encountered bit. */
268 control &= ~SCHIZO_IOMMU_CTRL_XLTEERR; 250 control &= ~SCHIZO_IOMMU_CTRL_XLTEERR;
269 schizo_write(iommu->iommu_control, control); 251 upa_writeq(control, iommu->iommu_control);
270 252
271 switch((control & SCHIZO_IOMMU_CTRL_XLTESTAT) >> 25UL) { 253 switch((control & SCHIZO_IOMMU_CTRL_XLTESTAT) >> 25UL) {
272 case 0: 254 case 0:
@@ -296,24 +278,24 @@ static void schizo_check_iommu_error_pbm(struct pci_pbm_info *pbm,
296 * get as much diagnostic information to the 278 * get as much diagnostic information to the
297 * console as we can. 279 * console as we can.
298 */ 280 */
299 schizo_write(iommu->iommu_control, 281 upa_writeq(control | SCHIZO_IOMMU_CTRL_DENAB,
300 control | SCHIZO_IOMMU_CTRL_DENAB); 282 iommu->iommu_control);
301 283
302 base = pbm->pbm_regs; 284 base = pbm->pbm_regs;
303 285
304 for (i = 0; i < 16; i++) { 286 for (i = 0; i < 16; i++) {
305 iommu_tag[i] = 287 iommu_tag[i] =
306 schizo_read(base + SCHIZO_IOMMU_TAG + (i * 8UL)); 288 upa_readq(base + SCHIZO_IOMMU_TAG + (i * 8UL));
307 iommu_data[i] = 289 iommu_data[i] =
308 schizo_read(base + SCHIZO_IOMMU_DATA + (i * 8UL)); 290 upa_readq(base + SCHIZO_IOMMU_DATA + (i * 8UL));
309 291
310 /* Now clear out the entry. */ 292 /* Now clear out the entry. */
311 schizo_write(base + SCHIZO_IOMMU_TAG + (i * 8UL), 0); 293 upa_writeq(0, base + SCHIZO_IOMMU_TAG + (i * 8UL));
312 schizo_write(base + SCHIZO_IOMMU_DATA + (i * 8UL), 0); 294 upa_writeq(0, base + SCHIZO_IOMMU_DATA + (i * 8UL));
313 } 295 }
314 296
315 /* Leave diagnostic mode. */ 297 /* Leave diagnostic mode. */
316 schizo_write(iommu->iommu_control, control); 298 upa_writeq(control, iommu->iommu_control);
317 299
318 for (i = 0; i < 16; i++) { 300 for (i = 0; i < 16; i++) {
319 unsigned long tag, data; 301 unsigned long tag, data;
@@ -394,7 +376,7 @@ static irqreturn_t schizo_ue_intr(int irq, void *dev_id)
394 int reported, limit; 376 int reported, limit;
395 377
396 /* Latch uncorrectable error status. */ 378 /* Latch uncorrectable error status. */
397 afar = schizo_read(afar_reg); 379 afar = upa_readq(afar_reg);
398 380
399 /* If either of the error pending bits are set in the 381 /* If either of the error pending bits are set in the
400 * AFSR, the error status is being actively updated by 382 * AFSR, the error status is being actively updated by
@@ -402,7 +384,7 @@ static irqreturn_t schizo_ue_intr(int irq, void *dev_id)
402 */ 384 */
403 limit = 1000; 385 limit = 1000;
404 do { 386 do {
405 afsr = schizo_read(afsr_reg); 387 afsr = upa_readq(afsr_reg);
406 } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit); 388 } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit);
407 389
408 /* Clear the primary/secondary error status bits. */ 390 /* Clear the primary/secondary error status bits. */
@@ -411,7 +393,7 @@ static irqreturn_t schizo_ue_intr(int irq, void *dev_id)
411 SCHIZO_UEAFSR_SPIO | SCHIZO_UEAFSR_SDMA); 393 SCHIZO_UEAFSR_SPIO | SCHIZO_UEAFSR_SDMA);
412 if (!error_bits) 394 if (!error_bits)
413 return IRQ_NONE; 395 return IRQ_NONE;
414 schizo_write(afsr_reg, error_bits); 396 upa_writeq(error_bits, afsr_reg);
415 397
416 /* Log the error. */ 398 /* Log the error. */
417 printk("%s: Uncorrectable Error, primary error type[%s]\n", 399 printk("%s: Uncorrectable Error, primary error type[%s]\n",
@@ -482,7 +464,7 @@ static irqreturn_t schizo_ce_intr(int irq, void *dev_id)
482 int reported, limit; 464 int reported, limit;
483 465
484 /* Latch error status. */ 466 /* Latch error status. */
485 afar = schizo_read(afar_reg); 467 afar = upa_readq(afar_reg);
486 468
487 /* If either of the error pending bits are set in the 469 /* If either of the error pending bits are set in the
488 * AFSR, the error status is being actively updated by 470 * AFSR, the error status is being actively updated by
@@ -490,7 +472,7 @@ static irqreturn_t schizo_ce_intr(int irq, void *dev_id)
490 */ 472 */
491 limit = 1000; 473 limit = 1000;
492 do { 474 do {
493 afsr = schizo_read(afsr_reg); 475 afsr = upa_readq(afsr_reg);
494 } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit); 476 } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit);
495 477
496 /* Clear primary/secondary error status bits. */ 478 /* Clear primary/secondary error status bits. */
@@ -499,7 +481,7 @@ static irqreturn_t schizo_ce_intr(int irq, void *dev_id)
499 SCHIZO_CEAFSR_SPIO | SCHIZO_CEAFSR_SDMA); 481 SCHIZO_CEAFSR_SPIO | SCHIZO_CEAFSR_SDMA);
500 if (!error_bits) 482 if (!error_bits)
501 return IRQ_NONE; 483 return IRQ_NONE;
502 schizo_write(afsr_reg, error_bits); 484 upa_writeq(error_bits, afsr_reg);
503 485
504 /* Log the error. */ 486 /* Log the error. */
505 printk("%s: Correctable Error, primary error type[%s]\n", 487 printk("%s: Correctable Error, primary error type[%s]\n",
@@ -601,7 +583,7 @@ static irqreturn_t schizo_pcierr_intr_other(struct pci_pbm_info *pbm)
601 u16 stat; 583 u16 stat;
602 584
603 csr_reg = pbm->pbm_regs + SCHIZO_PCI_CTRL; 585 csr_reg = pbm->pbm_regs + SCHIZO_PCI_CTRL;
604 csr = schizo_read(csr_reg); 586 csr = upa_readq(csr_reg);
605 csr_error_bits = 587 csr_error_bits =
606 csr & (SCHIZO_PCICTRL_BUS_UNUS | 588 csr & (SCHIZO_PCICTRL_BUS_UNUS |
607 SCHIZO_PCICTRL_TTO_ERR | 589 SCHIZO_PCICTRL_TTO_ERR |
@@ -611,7 +593,7 @@ static irqreturn_t schizo_pcierr_intr_other(struct pci_pbm_info *pbm)
611 SCHIZO_PCICTRL_SERR); 593 SCHIZO_PCICTRL_SERR);
612 if (csr_error_bits) { 594 if (csr_error_bits) {
613 /* Clear the errors. */ 595 /* Clear the errors. */
614 schizo_write(csr_reg, csr); 596 upa_writeq(csr, csr_reg);
615 597
616 /* Log 'em. */ 598 /* Log 'em. */
617 if (csr_error_bits & SCHIZO_PCICTRL_BUS_UNUS) 599 if (csr_error_bits & SCHIZO_PCICTRL_BUS_UNUS)
@@ -661,8 +643,8 @@ static irqreturn_t schizo_pcierr_intr(int irq, void *dev_id)
661 afar_reg = base + SCHIZO_PCI_AFAR; 643 afar_reg = base + SCHIZO_PCI_AFAR;
662 644
663 /* Latch error status. */ 645 /* Latch error status. */
664 afar = schizo_read(afar_reg); 646 afar = upa_readq(afar_reg);
665 afsr = schizo_read(afsr_reg); 647 afsr = upa_readq(afsr_reg);
666 648
667 /* Clear primary/secondary error status bits. */ 649 /* Clear primary/secondary error status bits. */
668 error_bits = afsr & 650 error_bits = afsr &
@@ -674,7 +656,7 @@ static irqreturn_t schizo_pcierr_intr(int irq, void *dev_id)
674 SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS); 656 SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS);
675 if (!error_bits) 657 if (!error_bits)
676 return schizo_pcierr_intr_other(pbm); 658 return schizo_pcierr_intr_other(pbm);
677 schizo_write(afsr_reg, error_bits); 659 upa_writeq(error_bits, afsr_reg);
678 660
679 /* Log the error. */ 661 /* Log the error. */
680 printk("%s: PCI Error, primary error type[%s]\n", 662 printk("%s: PCI Error, primary error type[%s]\n",
@@ -807,9 +789,9 @@ static irqreturn_t schizo_safarierr_intr(int irq, void *dev_id)
807 struct pci_pbm_info *pbm = dev_id; 789 struct pci_pbm_info *pbm = dev_id;
808 u64 errlog; 790 u64 errlog;
809 791
810 errlog = schizo_read(pbm->controller_regs + SCHIZO_SAFARI_ERRLOG); 792 errlog = upa_readq(pbm->controller_regs + SCHIZO_SAFARI_ERRLOG);
811 schizo_write(pbm->controller_regs + SCHIZO_SAFARI_ERRLOG, 793 upa_writeq(errlog & ~(SAFARI_ERRLOG_ERROUT),
812 errlog & ~(SAFARI_ERRLOG_ERROUT)); 794 pbm->controller_regs + SCHIZO_SAFARI_ERRLOG);
813 795
814 if (!(errlog & BUS_ERROR_UNMAP)) { 796 if (!(errlog & BUS_ERROR_UNMAP)) {
815 printk("%s: Unexpected Safari/JBUS error interrupt, errlog[%016lx]\n", 797 printk("%s: Unexpected Safari/JBUS error interrupt, errlog[%016lx]\n",
@@ -909,10 +891,9 @@ static void tomatillo_register_error_handlers(struct pci_pbm_info *pbm)
909 } 891 }
910 892
911 /* Enable UE and CE interrupts for controller. */ 893 /* Enable UE and CE interrupts for controller. */
912 schizo_write(pbm->controller_regs + SCHIZO_ECC_CTRL, 894 upa_writeq((SCHIZO_ECCCTRL_EE |
913 (SCHIZO_ECCCTRL_EE | 895 SCHIZO_ECCCTRL_UE |
914 SCHIZO_ECCCTRL_UE | 896 SCHIZO_ECCCTRL_CE), pbm->controller_regs + SCHIZO_ECC_CTRL);
915 SCHIZO_ECCCTRL_CE));
916 897
917 /* Enable PCI Error interrupts and clear error 898 /* Enable PCI Error interrupts and clear error
918 * bits. 899 * bits.
@@ -925,10 +906,10 @@ static void tomatillo_register_error_handlers(struct pci_pbm_info *pbm)
925 906
926 err_no_mask = SCHIZO_PCICTRL_DTO_ERR; 907 err_no_mask = SCHIZO_PCICTRL_DTO_ERR;
927 908
928 tmp = schizo_read(pbm->pbm_regs + SCHIZO_PCI_CTRL); 909 tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_CTRL);
929 tmp |= err_mask; 910 tmp |= err_mask;
930 tmp &= ~err_no_mask; 911 tmp &= ~err_no_mask;
931 schizo_write(pbm->pbm_regs + SCHIZO_PCI_CTRL, tmp); 912 upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_CTRL);
932 913
933 err_mask = (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA | 914 err_mask = (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
934 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR | 915 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
@@ -937,7 +918,7 @@ static void tomatillo_register_error_handlers(struct pci_pbm_info *pbm)
937 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR | 918 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
938 SCHIZO_PCIAFSR_STTO); 919 SCHIZO_PCIAFSR_STTO);
939 920
940 schizo_write(pbm->pbm_regs + SCHIZO_PCI_AFSR, err_mask); 921 upa_writeq(err_mask, pbm->pbm_regs + SCHIZO_PCI_AFSR);
941 922
942 err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SNOOP_GR | 923 err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SNOOP_GR |
943 BUS_ERROR_SNOOP_PCI | BUS_ERROR_SNOOP_RD | 924 BUS_ERROR_SNOOP_PCI | BUS_ERROR_SNOOP_RD |
@@ -949,11 +930,11 @@ static void tomatillo_register_error_handlers(struct pci_pbm_info *pbm)
949 BUS_ERROR_APERR | BUS_ERROR_UNMAP | 930 BUS_ERROR_APERR | BUS_ERROR_UNMAP |
950 BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT); 931 BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT);
951 932
952 schizo_write(pbm->controller_regs + SCHIZO_SAFARI_ERRCTRL, 933 upa_writeq((SCHIZO_SAFERRCTRL_EN | err_mask),
953 (SCHIZO_SAFERRCTRL_EN | err_mask)); 934 pbm->controller_regs + SCHIZO_SAFARI_ERRCTRL);
954 935
955 schizo_write(pbm->controller_regs + SCHIZO_SAFARI_IRQCTRL, 936 upa_writeq((SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP)),
956 (SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP))); 937 pbm->controller_regs + SCHIZO_SAFARI_IRQCTRL);
957} 938}
958 939
959static void schizo_register_error_handlers(struct pci_pbm_info *pbm) 940static void schizo_register_error_handlers(struct pci_pbm_info *pbm)
@@ -1005,10 +986,9 @@ static void schizo_register_error_handlers(struct pci_pbm_info *pbm)
1005 } 986 }
1006 987
1007 /* Enable UE and CE interrupts for controller. */ 988 /* Enable UE and CE interrupts for controller. */
1008 schizo_write(pbm->controller_regs + SCHIZO_ECC_CTRL, 989 upa_writeq((SCHIZO_ECCCTRL_EE |
1009 (SCHIZO_ECCCTRL_EE | 990 SCHIZO_ECCCTRL_UE |
1010 SCHIZO_ECCCTRL_UE | 991 SCHIZO_ECCCTRL_CE), pbm->controller_regs + SCHIZO_ECC_CTRL);
1011 SCHIZO_ECCCTRL_CE));
1012 992
1013 err_mask = (SCHIZO_PCICTRL_BUS_UNUS | 993 err_mask = (SCHIZO_PCICTRL_BUS_UNUS |
1014 SCHIZO_PCICTRL_ESLCK | 994 SCHIZO_PCICTRL_ESLCK |
@@ -1024,18 +1004,18 @@ static void schizo_register_error_handlers(struct pci_pbm_info *pbm)
1024 /* Enable PCI Error interrupts and clear error 1004 /* Enable PCI Error interrupts and clear error
1025 * bits for each PBM. 1005 * bits for each PBM.
1026 */ 1006 */
1027 tmp = schizo_read(pbm->pbm_regs + SCHIZO_PCI_CTRL); 1007 tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_CTRL);
1028 tmp |= err_mask; 1008 tmp |= err_mask;
1029 tmp &= ~err_no_mask; 1009 tmp &= ~err_no_mask;
1030 schizo_write(pbm->pbm_regs + SCHIZO_PCI_CTRL, tmp); 1010 upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_CTRL);
1031 1011
1032 schizo_write(pbm->pbm_regs + SCHIZO_PCI_AFSR, 1012 upa_writeq((SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
1033 (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA | 1013 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
1034 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR | 1014 SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS |
1035 SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS | 1015 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
1036 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA | 1016 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
1037 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR | 1017 SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS),
1038 SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS)); 1018 pbm->pbm_regs + SCHIZO_PCI_AFSR);
1039 1019
1040 /* Make all Safari error conditions fatal except unmapped 1020 /* Make all Safari error conditions fatal except unmapped
1041 * errors which we make generate interrupts. 1021 * errors which we make generate interrupts.
@@ -1062,8 +1042,8 @@ static void schizo_register_error_handlers(struct pci_pbm_info *pbm)
1062 BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB); 1042 BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB);
1063#endif 1043#endif
1064 1044
1065 schizo_write(pbm->controller_regs + SCHIZO_SAFARI_ERRCTRL, 1045 upa_writeq((SCHIZO_SAFERRCTRL_EN | err_mask),
1066 (SCHIZO_SAFERRCTRL_EN | err_mask)); 1046 pbm->controller_regs + SCHIZO_SAFARI_ERRCTRL);
1067} 1047}
1068 1048
1069static void pbm_config_busmastering(struct pci_pbm_info *pbm) 1049static void pbm_config_busmastering(struct pci_pbm_info *pbm)
@@ -1133,12 +1113,12 @@ static void schizo_pbm_strbuf_init(struct pci_pbm_info *pbm)
1133 * streaming buffer and leave the rerun-disable 1113 * streaming buffer and leave the rerun-disable
1134 * setting however OBP set it. 1114 * setting however OBP set it.
1135 */ 1115 */
1136 control = schizo_read(pbm->stc.strbuf_control); 1116 control = upa_readq(pbm->stc.strbuf_control);
1137 control &= ~(SCHIZO_STRBUF_CTRL_LPTR | 1117 control &= ~(SCHIZO_STRBUF_CTRL_LPTR |
1138 SCHIZO_STRBUF_CTRL_LENAB | 1118 SCHIZO_STRBUF_CTRL_LENAB |
1139 SCHIZO_STRBUF_CTRL_DENAB); 1119 SCHIZO_STRBUF_CTRL_DENAB);
1140 control |= SCHIZO_STRBUF_CTRL_ENAB; 1120 control |= SCHIZO_STRBUF_CTRL_ENAB;
1141 schizo_write(pbm->stc.strbuf_control, control); 1121 upa_writeq(control, pbm->stc.strbuf_control);
1142 1122
1143 pbm->stc.strbuf_enabled = 1; 1123 pbm->stc.strbuf_enabled = 1;
1144} 1124}
@@ -1199,15 +1179,15 @@ static int schizo_pbm_iommu_init(struct pci_pbm_info *pbm)
1199 /* 1179 /*
1200 * Invalidate TLB Entries. 1180 * Invalidate TLB Entries.
1201 */ 1181 */
1202 control = schizo_read(iommu->iommu_control); 1182 control = upa_readq(iommu->iommu_control);
1203 control |= SCHIZO_IOMMU_CTRL_DENAB; 1183 control |= SCHIZO_IOMMU_CTRL_DENAB;
1204 schizo_write(iommu->iommu_control, control); 1184 upa_writeq(control, iommu->iommu_control);
1205 1185
1206 tagbase = SCHIZO_IOMMU_TAG, database = SCHIZO_IOMMU_DATA; 1186 tagbase = SCHIZO_IOMMU_TAG, database = SCHIZO_IOMMU_DATA;
1207 1187
1208 for (i = 0; i < 16; i++) { 1188 for (i = 0; i < 16; i++) {
1209 schizo_write(pbm->pbm_regs + tagbase + (i * 8UL), 0); 1189 upa_writeq(0, pbm->pbm_regs + tagbase + (i * 8UL));
1210 schizo_write(pbm->pbm_regs + database + (i * 8UL), 0); 1190 upa_writeq(0, pbm->pbm_regs + database + (i * 8UL));
1211 } 1191 }
1212 1192
1213 /* Leave diag mode enabled for full-flushing done 1193 /* Leave diag mode enabled for full-flushing done
@@ -1220,9 +1200,9 @@ static int schizo_pbm_iommu_init(struct pci_pbm_info *pbm)
1220 return err; 1200 return err;
1221 } 1201 }
1222 1202
1223 schizo_write(iommu->iommu_tsbbase, __pa(iommu->page_table)); 1203 upa_writeq(__pa(iommu->page_table), iommu->iommu_tsbbase);
1224 1204
1225 control = schizo_read(iommu->iommu_control); 1205 control = upa_readq(iommu->iommu_control);
1226 control &= ~(SCHIZO_IOMMU_CTRL_TSBSZ | SCHIZO_IOMMU_CTRL_TBWSZ); 1206 control &= ~(SCHIZO_IOMMU_CTRL_TSBSZ | SCHIZO_IOMMU_CTRL_TBWSZ);
1227 switch (tsbsize) { 1207 switch (tsbsize) {
1228 case 64: 1208 case 64:
@@ -1234,7 +1214,7 @@ static int schizo_pbm_iommu_init(struct pci_pbm_info *pbm)
1234 } 1214 }
1235 1215
1236 control |= SCHIZO_IOMMU_CTRL_ENAB; 1216 control |= SCHIZO_IOMMU_CTRL_ENAB;
1237 schizo_write(iommu->iommu_control, control); 1217 upa_writeq(control, iommu->iommu_control);
1238 1218
1239 return 0; 1219 return 0;
1240} 1220}
@@ -1277,9 +1257,9 @@ static void schizo_pbm_hw_init(struct pci_pbm_info *pbm)
1277{ 1257{
1278 u64 tmp; 1258 u64 tmp;
1279 1259
1280 schizo_write(pbm->pbm_regs + SCHIZO_PCI_IRQ_RETRY, 5); 1260 upa_writeq(5, pbm->pbm_regs + SCHIZO_PCI_IRQ_RETRY);
1281 1261
1282 tmp = schizo_read(pbm->pbm_regs + SCHIZO_PCI_CTRL); 1262 tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_CTRL);
1283 1263
1284 /* Enable arbiter for all PCI slots. */ 1264 /* Enable arbiter for all PCI slots. */
1285 tmp |= 0xff; 1265 tmp |= 0xff;
@@ -1304,13 +1284,13 @@ static void schizo_pbm_hw_init(struct pci_pbm_info *pbm)
1304 SCHIZO_PCICTRL_RDO_PREF | 1284 SCHIZO_PCICTRL_RDO_PREF |
1305 SCHIZO_PCICTRL_RDL_PREF); 1285 SCHIZO_PCICTRL_RDL_PREF);
1306 1286
1307 schizo_write(pbm->pbm_regs + SCHIZO_PCI_CTRL, tmp); 1287 upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_CTRL);
1308 1288
1309 tmp = schizo_read(pbm->pbm_regs + SCHIZO_PCI_DIAG); 1289 tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_DIAG);
1310 tmp &= ~(SCHIZO_PCIDIAG_D_RTRYARB | 1290 tmp &= ~(SCHIZO_PCIDIAG_D_RTRYARB |
1311 SCHIZO_PCIDIAG_D_RETRY | 1291 SCHIZO_PCIDIAG_D_RETRY |
1312 SCHIZO_PCIDIAG_D_INTSYNC); 1292 SCHIZO_PCIDIAG_D_INTSYNC);
1313 schizo_write(pbm->pbm_regs + SCHIZO_PCI_DIAG, tmp); 1293 upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_DIAG);
1314 1294
1315 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) { 1295 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) {
1316 /* Clear prefetch lengths to workaround a bug in 1296 /* Clear prefetch lengths to workaround a bug in
@@ -1322,8 +1302,7 @@ static void schizo_pbm_hw_init(struct pci_pbm_info *pbm)
1322 TOMATILLO_IOC_RDONE_CPENAB | 1302 TOMATILLO_IOC_RDONE_CPENAB |
1323 TOMATILLO_IOC_RDLINE_CPENAB); 1303 TOMATILLO_IOC_RDLINE_CPENAB);
1324 1304
1325 schizo_write(pbm->pbm_regs + TOMATILLO_PCI_IOC_CSR, 1305 upa_writeq(tmp, pbm->pbm_regs + TOMATILLO_PCI_IOC_CSR);
1326 tmp);
1327 } 1306 }
1328} 1307}
1329 1308
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-22 08:38:03 -0500