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-rw-r--r--arch/mips/Kconfig82
-rw-r--r--arch/mips/Makefile1
-rw-r--r--arch/mips/alchemy/Kconfig60
-rw-r--r--arch/mips/alchemy/Makefile3
-rw-r--r--arch/mips/alchemy/Platform58
-rw-r--r--arch/mips/alchemy/board-gpr.c (renamed from arch/mips/alchemy/gpr/platform.c)81
-rw-r--r--arch/mips/alchemy/board-mtx1.c (renamed from arch/mips/alchemy/mtx-1/platform.c)93
-rw-r--r--arch/mips/alchemy/board-xxs1500.c154
-rw-r--r--arch/mips/alchemy/common/Makefile4
-rw-r--r--arch/mips/alchemy/common/dbdma.c49
-rw-r--r--arch/mips/alchemy/common/gpiolib.c42
-rw-r--r--arch/mips/alchemy/common/irq.c875
-rw-r--r--arch/mips/alchemy/common/platform.c31
-rw-r--r--arch/mips/alchemy/common/power.c3
-rw-r--r--arch/mips/alchemy/common/sleeper.S73
-rw-r--r--arch/mips/alchemy/common/time.c3
-rw-r--r--arch/mips/alchemy/common/vss.c84
-rw-r--r--arch/mips/alchemy/devboards/Makefile19
-rw-r--r--arch/mips/alchemy/devboards/bcsr.c11
-rw-r--r--arch/mips/alchemy/devboards/db1000.c565
-rw-r--r--arch/mips/alchemy/devboards/db1200.c (renamed from arch/mips/alchemy/devboards/db1200/platform.c)401
-rw-r--r--arch/mips/alchemy/devboards/db1200/Makefile1
-rw-r--r--arch/mips/alchemy/devboards/db1200/setup.c81
-rw-r--r--arch/mips/alchemy/devboards/db1300.c785
-rw-r--r--arch/mips/alchemy/devboards/db1550.c498
-rw-r--r--arch/mips/alchemy/devboards/db1x00/Makefile8
-rw-r--r--arch/mips/alchemy/devboards/db1x00/board_setup.c229
-rw-r--r--arch/mips/alchemy/devboards/db1x00/platform.c316
-rw-r--r--arch/mips/alchemy/devboards/pb1000/Makefile8
-rw-r--r--arch/mips/alchemy/devboards/pb1000/board_setup.c209
-rw-r--r--arch/mips/alchemy/devboards/pb1100.c (renamed from arch/mips/alchemy/devboards/pb1100/board_setup.c)92
-rw-r--r--arch/mips/alchemy/devboards/pb1100/Makefile8
-rw-r--r--arch/mips/alchemy/devboards/pb1100/platform.c77
-rw-r--r--arch/mips/alchemy/devboards/pb1200/Makefile5
-rw-r--r--arch/mips/alchemy/devboards/pb1200/board_setup.c174
-rw-r--r--arch/mips/alchemy/devboards/pb1200/platform.c339
-rw-r--r--arch/mips/alchemy/devboards/pb1500.c (renamed from arch/mips/alchemy/devboards/pb1500/board_setup.c)113
-rw-r--r--arch/mips/alchemy/devboards/pb1500/Makefile8
-rw-r--r--arch/mips/alchemy/devboards/pb1500/platform.c94
-rw-r--r--arch/mips/alchemy/devboards/pb1550.c (renamed from arch/mips/alchemy/devboards/pb1550/platform.c)112
-rw-r--r--arch/mips/alchemy/devboards/pb1550/Makefile8
-rw-r--r--arch/mips/alchemy/devboards/pb1550/board_setup.c80
-rw-r--r--arch/mips/alchemy/devboards/platform.c13
-rw-r--r--arch/mips/alchemy/devboards/prom.c11
-rw-r--r--arch/mips/alchemy/gpr/Makefile8
-rw-r--r--arch/mips/alchemy/gpr/board_setup.c75
-rw-r--r--arch/mips/alchemy/gpr/init.c63
-rw-r--r--arch/mips/alchemy/mtx-1/Makefile9
-rw-r--r--arch/mips/alchemy/mtx-1/board_setup.c94
-rw-r--r--arch/mips/alchemy/mtx-1/init.c66
-rw-r--r--arch/mips/alchemy/xxs1500/Makefile8
-rw-r--r--arch/mips/alchemy/xxs1500/board_setup.c93
-rw-r--r--arch/mips/alchemy/xxs1500/init.c63
-rw-r--r--arch/mips/alchemy/xxs1500/platform.c63
-rw-r--r--arch/mips/ar7/gpio.c2
-rw-r--r--arch/mips/ar7/platform.c39
-rw-r--r--arch/mips/ar7/prom.c4
-rw-r--r--arch/mips/ar7/setup.c2
-rw-r--r--arch/mips/ath79/Kconfig38
-rw-r--r--arch/mips/ath79/Makefile5
-rw-r--r--arch/mips/ath79/clock.c55
-rw-r--r--arch/mips/ath79/common.c5
-rw-r--r--arch/mips/ath79/dev-ar913x-wmac.c60
-rw-r--r--arch/mips/ath79/dev-common.c38
-rw-r--r--arch/mips/ath79/dev-usb.c197
-rw-r--r--arch/mips/ath79/dev-usb.h (renamed from arch/mips/ath79/dev-ar913x-wmac.h)10
-rw-r--r--arch/mips/ath79/dev-wmac.c109
-rw-r--r--arch/mips/ath79/dev-wmac.h17
-rw-r--r--arch/mips/ath79/early_printk.c76
-rw-r--r--arch/mips/ath79/gpio.c2
-rw-r--r--arch/mips/ath79/irq.c17
-rw-r--r--arch/mips/ath79/mach-ap121.c92
-rw-r--r--arch/mips/ath79/mach-ap81.c6
-rw-r--r--arch/mips/ath79/mach-pb44.c2
-rw-r--r--arch/mips/ath79/mach-ubnt-xm.c119
-rw-r--r--arch/mips/ath79/machtypes.h2
-rw-r--r--arch/mips/ath79/setup.c22
-rw-r--r--arch/mips/bcm47xx/setup.c4
-rw-r--r--arch/mips/bcm63xx/Kconfig4
-rw-r--r--arch/mips/bcm63xx/boards/board_bcm963xx.c46
-rw-r--r--arch/mips/bcm63xx/clk.c70
-rw-r--r--arch/mips/bcm63xx/cpu.c261
-rw-r--r--arch/mips/bcm63xx/dev-uart.c2
-rw-r--r--arch/mips/bcm63xx/gpio.c41
-rw-r--r--arch/mips/bcm63xx/irq.c403
-rw-r--r--arch/mips/bcm63xx/prom.c7
-rw-r--r--arch/mips/bcm63xx/setup.c32
-rw-r--r--arch/mips/boot/compressed/uart-alchemy.c5
-rw-r--r--arch/mips/cavium-octeon/setup.c14
-rw-r--r--arch/mips/cavium-octeon/smp.c2
-rw-r--r--arch/mips/configs/db1000_defconfig369
-rw-r--r--arch/mips/configs/db1100_defconfig122
-rw-r--r--arch/mips/configs/db1300_defconfig391
-rw-r--r--arch/mips/configs/db1500_defconfig128
-rw-r--r--arch/mips/configs/db1550_defconfig288
-rw-r--r--arch/mips/configs/nlm_xlp_defconfig570
-rw-r--r--arch/mips/configs/nlm_xlr_defconfig16
-rw-r--r--arch/mips/configs/pb1200_defconfig170
-rw-r--r--arch/mips/dec/setup.c1
-rw-r--r--arch/mips/include/asm/bmips.h110
-rw-r--r--arch/mips/include/asm/bootinfo.h1
-rw-r--r--arch/mips/include/asm/branch.h5
-rw-r--r--arch/mips/include/asm/cpu.h6
-rw-r--r--arch/mips/include/asm/gio_device.h56
-rw-r--r--arch/mips/include/asm/hazards.h7
-rw-r--r--arch/mips/include/asm/hugetlb.h2
-rw-r--r--arch/mips/include/asm/kprobes.h5
-rw-r--r--arch/mips/include/asm/mach-ath79/ar71xx_regs.h81
-rw-r--r--arch/mips/include/asm/mach-ath79/ar933x_uart.h67
-rw-r--r--arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h18
-rw-r--r--arch/mips/include/asm/mach-ath79/ath79.h11
-rw-r--r--arch/mips/include/asm/mach-ath79/irq.h8
-rw-r--r--arch/mips/include/asm/mach-ath79/pci-ath724x.h21
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1000.h273
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1100_mmc.h2
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1200fb.h14
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1550nd.h16
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h31
-rw-r--r--arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h3
-rw-r--r--arch/mips/include/asm/mach-au1x00/gpio-au1300.h241
-rw-r--r--arch/mips/include/asm/mach-au1x00/gpio.h3
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h597
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h2
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h2
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h12
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h231
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/ioremap.h42
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/irq.h7
-rw-r--r--arch/mips/include/asm/mach-db1x00/bcsr.h36
-rw-r--r--arch/mips/include/asm/mach-db1x00/db1200.h11
-rw-r--r--arch/mips/include/asm/mach-db1x00/db1300.h40
-rw-r--r--arch/mips/include/asm/mach-db1x00/db1x00.h79
-rw-r--r--arch/mips/include/asm/mach-db1x00/irq.h23
-rw-r--r--arch/mips/include/asm/mach-generic/floppy.h2
-rw-r--r--arch/mips/include/asm/mach-jazz/floppy.h2
-rw-r--r--arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h23
-rw-r--r--arch/mips/include/asm/mach-pb1x00/mc146818rtc.h34
-rw-r--r--arch/mips/include/asm/mach-pb1x00/pb1000.h87
-rw-r--r--arch/mips/include/asm/mach-pb1x00/pb1200.h139
-rw-r--r--arch/mips/include/asm/mach-pb1x00/pb1550.h73
-rw-r--r--arch/mips/include/asm/mipsregs.h9
-rw-r--r--arch/mips/include/asm/module.h6
-rw-r--r--arch/mips/include/asm/netlogic/common.h76
-rw-r--r--arch/mips/include/asm/netlogic/haldefs.h163
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/bridge.h187
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h83
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/iomap.h153
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/pic.h411
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/sys.h129
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/uart.h191
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/xlp.h (renamed from arch/mips/netlogic/xlr/xlr_console.c)25
-rw-r--r--arch/mips/include/asm/netlogic/xlr/iomap.h22
-rw-r--r--arch/mips/include/asm/netlogic/xlr/msidef.h84
-rw-r--r--arch/mips/include/asm/netlogic/xlr/pic.h69
-rw-r--r--arch/mips/include/asm/netlogic/xlr/xlr.h13
-rw-r--r--arch/mips/include/asm/page.h8
-rw-r--r--arch/mips/include/asm/pgtable-32.h18
-rw-r--r--arch/mips/include/asm/tlbmisc.h10
-rw-r--r--arch/mips/include/asm/traps.h13
-rw-r--r--arch/mips/jazz/irq.c3
-rw-r--r--arch/mips/jazz/setup.c1
-rw-r--r--arch/mips/jz4740/board-qi_lb60.c2
-rw-r--r--arch/mips/kernel/Makefile2
-rw-r--r--arch/mips/kernel/bmips_vec.S255
-rw-r--r--arch/mips/kernel/branch.c128
-rw-r--r--arch/mips/kernel/cevt-bcm1480.c2
-rw-r--r--arch/mips/kernel/cevt-ds1287.c2
-rw-r--r--arch/mips/kernel/cevt-gt641xx.c2
-rw-r--r--arch/mips/kernel/cevt-r4k.c2
-rw-r--r--arch/mips/kernel/cevt-sb1250.c2
-rw-r--r--arch/mips/kernel/cevt-txx9.c2
-rw-r--r--arch/mips/kernel/cpu-probe.c28
-rw-r--r--arch/mips/kernel/i8253.c2
-rw-r--r--arch/mips/kernel/kprobes.c177
-rw-r--r--arch/mips/kernel/perf_event_mipsxx.c72
-rw-r--r--arch/mips/kernel/rtlx.c1
-rw-r--r--arch/mips/kernel/setup.c43
-rw-r--r--arch/mips/kernel/smp-bmips.c458
-rw-r--r--arch/mips/kernel/smtc.c6
-rw-r--r--arch/mips/kernel/traps.c16
-rw-r--r--arch/mips/lantiq/clk.c4
-rw-r--r--arch/mips/lantiq/irq.c13
-rw-r--r--arch/mips/lantiq/xway/dma.c6
-rw-r--r--arch/mips/lantiq/xway/ebu.c6
-rw-r--r--arch/mips/lantiq/xway/pmu.c8
-rw-r--r--arch/mips/lantiq/xway/reset.c6
-rw-r--r--arch/mips/lib/Makefile1
-rw-r--r--arch/mips/loongson/common/cs5536/cs5536_mfgpt.c2
-rw-r--r--arch/mips/math-emu/cp1emu.c2
-rw-r--r--arch/mips/mm/Makefile5
-rw-r--r--arch/mips/mm/c-octeon.c2
-rw-r--r--arch/mips/mm/c-r4k.c3
-rw-r--r--arch/mips/mm/gup.c315
-rw-r--r--arch/mips/mm/init.c9
-rw-r--r--arch/mips/mm/tlb-r3k.c1
-rw-r--r--arch/mips/mm/tlb-r4k.c68
-rw-r--r--arch/mips/mti-malta/malta-int.c4
-rw-r--r--arch/mips/netlogic/Kconfig3
-rw-r--r--arch/mips/netlogic/Makefile3
-rw-r--r--arch/mips/netlogic/Platform13
-rw-r--r--arch/mips/netlogic/common/Makefile3
-rw-r--r--arch/mips/netlogic/common/earlycons.c60
-rw-r--r--arch/mips/netlogic/common/irq.c238
-rw-r--r--arch/mips/netlogic/common/smp.c (renamed from arch/mips/netlogic/xlr/smp.c)152
-rw-r--r--arch/mips/netlogic/common/smpboot.S272
-rw-r--r--arch/mips/netlogic/common/time.c (renamed from arch/mips/netlogic/xlr/time.c)6
-rw-r--r--arch/mips/netlogic/xlp/Makefile2
-rw-r--r--arch/mips/netlogic/xlp/nlm_hal.c111
-rw-r--r--arch/mips/netlogic/xlp/platform.c108
-rw-r--r--arch/mips/netlogic/xlp/setup.c105
-rw-r--r--arch/mips/netlogic/xlp/wakeup.c102
-rw-r--r--arch/mips/netlogic/xlr/Makefile7
-rw-r--r--arch/mips/netlogic/xlr/irq.c300
-rw-r--r--arch/mips/netlogic/xlr/platform.c31
-rw-r--r--arch/mips/netlogic/xlr/setup.c31
-rw-r--r--arch/mips/netlogic/xlr/wakeup.c (renamed from arch/mips/netlogic/xlr/smpboot.S)80
-rw-r--r--arch/mips/pci/Makefile3
-rw-r--r--arch/mips/pci/msi-octeon.c2
-rw-r--r--arch/mips/pci/ops-pmcmsp.c2
-rw-r--r--arch/mips/pci/ops-tx3927.c2
-rw-r--r--arch/mips/pci/pci-alchemy.c138
-rw-r--r--arch/mips/pci/pci-ath724x.c174
-rw-r--r--arch/mips/pci/pci-bcm63xx.c4
-rw-r--r--arch/mips/pci/pci-tx4927.c2
-rw-r--r--arch/mips/pci/pci-tx4938.c2
-rw-r--r--arch/mips/pci/pci-tx4939.c2
-rw-r--r--arch/mips/pci/pci-xlr.c128
-rw-r--r--arch/mips/pci/pci.c29
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c2
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_setup.c2
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_smp.c4
-rw-r--r--arch/mips/pnx8550/common/int.c4
-rw-r--r--arch/mips/pnx8550/common/time.c4
-rw-r--r--arch/mips/sgi-ip22/Makefile2
-rw-r--r--arch/mips/sgi-ip22/ip22-gio.c428
-rw-r--r--arch/mips/sgi-ip22/ip22-int.c10
-rw-r--r--arch/mips/sgi-ip22/ip22-mc.c10
-rw-r--r--arch/mips/sgi-ip22/ip22-setup.c21
-rw-r--r--arch/mips/sgi-ip27/ip27-irq.c6
-rw-r--r--arch/mips/sgi-ip27/ip27-timer.c2
-rw-r--r--arch/mips/sgi-ip32/ip32-irq.c2
-rw-r--r--arch/mips/sni/irq.c2
-rw-r--r--arch/mips/sni/time.c2
-rw-r--r--arch/mips/txx9/generic/pci.c2
-rw-r--r--drivers/i2c/busses/Kconfig4
-rw-r--r--drivers/mmc/host/au1xmmc.c45
-rw-r--r--drivers/mtd/nand/au1550nd.c298
-rw-r--r--drivers/net/irda/Kconfig6
-rw-r--r--drivers/net/irda/au1000_ircc.h125
-rw-r--r--drivers/net/irda/au1k_ir.c1229
-rw-r--r--drivers/pcmcia/Kconfig8
-rw-r--r--drivers/pcmcia/Makefile4
-rw-r--r--drivers/pcmcia/au1000_generic.c545
-rw-r--r--drivers/pcmcia/au1000_generic.h135
-rw-r--r--drivers/pcmcia/au1000_pb1x00.c294
-rw-r--r--drivers/pcmcia/db1xxx_ss.c26
-rw-r--r--drivers/spi/Kconfig4
-rw-r--r--drivers/tty/serial/Kconfig23
-rw-r--r--drivers/tty/serial/Makefile1
-rw-r--r--drivers/tty/serial/ar933x_uart.c688
-rw-r--r--drivers/usb/host/Kconfig2
-rw-r--r--drivers/usb/host/alchemy-common.c277
-rw-r--r--drivers/usb/host/ehci-ath79.c4
-rw-r--r--drivers/usb/host/ohci-au1xxx.c13
-rw-r--r--drivers/video/Kconfig8
-rw-r--r--drivers/video/au1100fb.c12
-rw-r--r--drivers/video/au1200fb.c273
-rw-r--r--drivers/video/console/newport_con.c63
-rw-r--r--include/linux/serial_core.h4
-rw-r--r--sound/soc/au1x/Kconfig14
-rw-r--r--sound/soc/au1x/db1200.c73
271 files changed, 15569 insertions, 7349 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 387a7c5bb899..0c55582a49c3 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -759,7 +759,6 @@ config NLM_XLR_BOARD
759 depends on EXPERIMENTAL 759 depends on EXPERIMENTAL
760 select BOOT_ELF32 760 select BOOT_ELF32
761 select NLM_COMMON 761 select NLM_COMMON
762 select NLM_XLR
763 select SYS_HAS_CPU_XLR 762 select SYS_HAS_CPU_XLR
764 select SYS_SUPPORTS_SMP 763 select SYS_SUPPORTS_SMP
765 select HW_HAS_PCI 764 select HW_HAS_PCI
@@ -774,6 +773,7 @@ config NLM_XLR_BOARD
774 select CEVT_R4K 773 select CEVT_R4K
775 select CSRC_R4K 774 select CSRC_R4K
776 select IRQ_CPU 775 select IRQ_CPU
776 select ARCH_SUPPORTS_MSI
777 select ZONE_DMA if 64BIT 777 select ZONE_DMA if 64BIT
778 select SYNC_R4K 778 select SYNC_R4K
779 select SYS_HAS_EARLY_PRINTK 779 select SYS_HAS_EARLY_PRINTK
@@ -781,6 +781,33 @@ config NLM_XLR_BOARD
781 Support for systems based on Netlogic XLR and XLS processors. 781 Support for systems based on Netlogic XLR and XLS processors.
782 Say Y here if you have a XLR or XLS based board. 782 Say Y here if you have a XLR or XLS based board.
783 783
784config NLM_XLP_BOARD
785 bool "Netlogic XLP based systems"
786 depends on EXPERIMENTAL
787 select BOOT_ELF32
788 select NLM_COMMON
789 select SYS_HAS_CPU_XLP
790 select SYS_SUPPORTS_SMP
791 select HW_HAS_PCI
792 select SWAP_IO_SPACE
793 select SYS_SUPPORTS_32BIT_KERNEL
794 select SYS_SUPPORTS_64BIT_KERNEL
795 select 64BIT_PHYS_ADDR
796 select SYS_SUPPORTS_BIG_ENDIAN
797 select SYS_SUPPORTS_LITTLE_ENDIAN
798 select SYS_SUPPORTS_HIGHMEM
799 select DMA_COHERENT
800 select NR_CPUS_DEFAULT_32
801 select CEVT_R4K
802 select CSRC_R4K
803 select IRQ_CPU
804 select ZONE_DMA if 64BIT
805 select SYNC_R4K
806 select SYS_HAS_EARLY_PRINTK
807 help
808 This board is based on Netlogic XLP Processor.
809 Say Y here if you have a XLP based board.
810
784endchoice 811endchoice
785 812
786source "arch/mips/alchemy/Kconfig" 813source "arch/mips/alchemy/Kconfig"
@@ -1411,51 +1438,36 @@ config CPU_CAVIUM_OCTEON
1411config CPU_BMIPS3300 1438config CPU_BMIPS3300
1412 bool "BMIPS3300" 1439 bool "BMIPS3300"
1413 depends on SYS_HAS_CPU_BMIPS3300 1440 depends on SYS_HAS_CPU_BMIPS3300
1414 select DMA_NONCOHERENT 1441 select CPU_BMIPS
1415 select IRQ_CPU
1416 select SWAP_IO_SPACE
1417 select SYS_SUPPORTS_32BIT_KERNEL
1418 select WEAK_ORDERING
1419 help 1442 help
1420 Broadcom BMIPS3300 processors. 1443 Broadcom BMIPS3300 processors.
1421 1444
1422config CPU_BMIPS4350 1445config CPU_BMIPS4350
1423 bool "BMIPS4350" 1446 bool "BMIPS4350"
1424 depends on SYS_HAS_CPU_BMIPS4350 1447 depends on SYS_HAS_CPU_BMIPS4350
1425 select CPU_SUPPORTS_32BIT_KERNEL 1448 select CPU_BMIPS
1426 select DMA_NONCOHERENT
1427 select IRQ_CPU
1428 select SWAP_IO_SPACE
1429 select SYS_SUPPORTS_SMP 1449 select SYS_SUPPORTS_SMP
1430 select SYS_SUPPORTS_HOTPLUG_CPU 1450 select SYS_SUPPORTS_HOTPLUG_CPU
1431 select WEAK_ORDERING
1432 help 1451 help
1433 Broadcom BMIPS4350 ("VIPER") processors. 1452 Broadcom BMIPS4350 ("VIPER") processors.
1434 1453
1435config CPU_BMIPS4380 1454config CPU_BMIPS4380
1436 bool "BMIPS4380" 1455 bool "BMIPS4380"
1437 depends on SYS_HAS_CPU_BMIPS4380 1456 depends on SYS_HAS_CPU_BMIPS4380
1438 select CPU_SUPPORTS_32BIT_KERNEL 1457 select CPU_BMIPS
1439 select DMA_NONCOHERENT
1440 select IRQ_CPU
1441 select SWAP_IO_SPACE
1442 select SYS_SUPPORTS_SMP 1458 select SYS_SUPPORTS_SMP
1443 select SYS_SUPPORTS_HOTPLUG_CPU 1459 select SYS_SUPPORTS_HOTPLUG_CPU
1444 select WEAK_ORDERING
1445 help 1460 help
1446 Broadcom BMIPS4380 processors. 1461 Broadcom BMIPS4380 processors.
1447 1462
1448config CPU_BMIPS5000 1463config CPU_BMIPS5000
1449 bool "BMIPS5000" 1464 bool "BMIPS5000"
1450 depends on SYS_HAS_CPU_BMIPS5000 1465 depends on SYS_HAS_CPU_BMIPS5000
1451 select CPU_SUPPORTS_32BIT_KERNEL 1466 select CPU_BMIPS
1452 select CPU_SUPPORTS_HIGHMEM 1467 select CPU_SUPPORTS_HIGHMEM
1453 select DMA_NONCOHERENT 1468 select MIPS_CPU_SCACHE
1454 select IRQ_CPU
1455 select SWAP_IO_SPACE
1456 select SYS_SUPPORTS_SMP 1469 select SYS_SUPPORTS_SMP
1457 select SYS_SUPPORTS_HOTPLUG_CPU 1470 select SYS_SUPPORTS_HOTPLUG_CPU
1458 select WEAK_ORDERING
1459 help 1471 help
1460 Broadcom BMIPS5000 processors. 1472 Broadcom BMIPS5000 processors.
1461 1473
@@ -1470,6 +1482,19 @@ config CPU_XLR
1470 select CPU_SUPPORTS_HUGEPAGES 1482 select CPU_SUPPORTS_HUGEPAGES
1471 help 1483 help
1472 Netlogic Microsystems XLR/XLS processors. 1484 Netlogic Microsystems XLR/XLS processors.
1485
1486config CPU_XLP
1487 bool "Netlogic XLP SoC"
1488 depends on SYS_HAS_CPU_XLP
1489 select CPU_SUPPORTS_32BIT_KERNEL
1490 select CPU_SUPPORTS_64BIT_KERNEL
1491 select CPU_SUPPORTS_HIGHMEM
1492 select CPU_HAS_LLSC
1493 select WEAK_ORDERING
1494 select WEAK_REORDERING_BEYOND_LLSC
1495 select CPU_HAS_PREFETCH
1496 help
1497 Netlogic Microsystems XLP processors.
1473endchoice 1498endchoice
1474 1499
1475if CPU_LOONGSON2F 1500if CPU_LOONGSON2F
@@ -1516,6 +1541,15 @@ config CPU_LOONGSON2
1516 select CPU_SUPPORTS_64BIT_KERNEL 1541 select CPU_SUPPORTS_64BIT_KERNEL
1517 select CPU_SUPPORTS_HIGHMEM 1542 select CPU_SUPPORTS_HIGHMEM
1518 1543
1544config CPU_BMIPS
1545 bool
1546 select CPU_MIPS32
1547 select CPU_SUPPORTS_32BIT_KERNEL
1548 select DMA_NONCOHERENT
1549 select IRQ_CPU
1550 select SWAP_IO_SPACE
1551 select WEAK_ORDERING
1552
1519config SYS_HAS_CPU_LOONGSON2E 1553config SYS_HAS_CPU_LOONGSON2E
1520 bool 1554 bool
1521 1555
@@ -1603,6 +1637,9 @@ config SYS_HAS_CPU_BMIPS5000
1603config SYS_HAS_CPU_XLR 1637config SYS_HAS_CPU_XLR
1604 bool 1638 bool
1605 1639
1640config SYS_HAS_CPU_XLP
1641 bool
1642
1606# 1643#
1607# CPU may reorder R->R, R->W, W->R, W->W 1644# CPU may reorder R->R, R->W, W->R, W->W
1608# Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC 1645# Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
@@ -1990,6 +2027,9 @@ config CPU_HAS_SMARTMIPS
1990config CPU_HAS_WB 2027config CPU_HAS_WB
1991 bool 2028 bool
1992 2029
2030config XKS01
2031 bool
2032
1993# 2033#
1994# Vectored interrupt mode is an R2 feature 2034# Vectored interrupt mode is an R2 feature
1995# 2035#
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 0be318609fc6..4fedf5a51d96 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -157,6 +157,7 @@ ifeq (,$(findstring march=octeon, $(cflags-$(CONFIG_CPU_CAVIUM_OCTEON))))
157cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -Wa,-march=octeon 157cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -Wa,-march=octeon
158endif 158endif
159cflags-$(CONFIG_CAVIUM_CN63XXP1) += -Wa,-mfix-cn63xxp1 159cflags-$(CONFIG_CAVIUM_CN63XXP1) += -Wa,-mfix-cn63xxp1
160cflags-$(CONFIG_CPU_BMIPS) += -march=mips32 -Wa,-mips32 -Wa,--trap
160 161
161cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,) 162cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,)
162cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += $(call cc-option,-mfix-r4400,) 163cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += $(call cc-option,-mfix-r4400,)
diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig
index 2a68be6a1b97..0faaab24376e 100644
--- a/arch/mips/alchemy/Kconfig
+++ b/arch/mips/alchemy/Kconfig
@@ -2,6 +2,10 @@
2config ALCHEMY_GPIOINT_AU1000 2config ALCHEMY_GPIOINT_AU1000
3 bool 3 bool
4 4
5# au1300-style GPIO/INT controller
6config ALCHEMY_GPIOINT_AU1300
7 bool
8
5# select this in your board config if you don't want to use the gpio 9# select this in your board config if you don't want to use the gpio
6# namespace as documented in the manuals. In this case however you need 10# namespace as documented in the manuals. In this case however you need
7# to create the necessary gpio_* functions in your board code/headers! 11# to create the necessary gpio_* functions in your board code/headers!
@@ -22,43 +26,29 @@ config MIPS_MTX1
22 select SYS_SUPPORTS_LITTLE_ENDIAN 26 select SYS_SUPPORTS_LITTLE_ENDIAN
23 select SYS_HAS_EARLY_PRINTK 27 select SYS_HAS_EARLY_PRINTK
24 28
25config MIPS_BOSPORUS
26 bool "Alchemy Bosporus board"
27 select ALCHEMY_GPIOINT_AU1000
28 select DMA_NONCOHERENT
29 select SYS_SUPPORTS_LITTLE_ENDIAN
30 select SYS_HAS_EARLY_PRINTK
31
32config MIPS_DB1000 29config MIPS_DB1000
33 bool "Alchemy DB1000 board" 30 bool "Alchemy DB1000/DB1500/DB1100 boards"
34 select ALCHEMY_GPIOINT_AU1000 31 select ALCHEMY_GPIOINT_AU1000
35 select DMA_NONCOHERENT 32 select DMA_NONCOHERENT
36 select HW_HAS_PCI 33 select HW_HAS_PCI
37 select SYS_SUPPORTS_LITTLE_ENDIAN 34 select MIPS_DISABLE_OBSOLETE_IDE
38 select SYS_HAS_EARLY_PRINTK 35 select SYS_SUPPORTS_BIG_ENDIAN
39
40config MIPS_DB1100
41 bool "Alchemy DB1100 board"
42 select ALCHEMY_GPIOINT_AU1000
43 select DMA_NONCOHERENT
44 select SYS_SUPPORTS_LITTLE_ENDIAN 36 select SYS_SUPPORTS_LITTLE_ENDIAN
45 select SYS_HAS_EARLY_PRINTK 37 select SYS_HAS_EARLY_PRINTK
46 38
47config MIPS_DB1200 39config MIPS_DB1200
48 bool "Alchemy DB1200 board" 40 bool "Alchemy DB1200/PB1200 board"
49 select ALCHEMY_GPIOINT_AU1000 41 select ALCHEMY_GPIOINT_AU1000
50 select DMA_COHERENT 42 select DMA_COHERENT
51 select MIPS_DISABLE_OBSOLETE_IDE 43 select MIPS_DISABLE_OBSOLETE_IDE
52 select SYS_SUPPORTS_LITTLE_ENDIAN 44 select SYS_SUPPORTS_LITTLE_ENDIAN
53 select SYS_HAS_EARLY_PRINTK 45 select SYS_HAS_EARLY_PRINTK
54 46
55config MIPS_DB1500 47config MIPS_DB1300
56 bool "Alchemy DB1500 board" 48 bool "NetLogic DB1300 board"
57 select ALCHEMY_GPIOINT_AU1000 49 select ALCHEMY_GPIOINT_AU1300
58 select DMA_NONCOHERENT 50 select DMA_COHERENT
59 select HW_HAS_PCI
60 select MIPS_DISABLE_OBSOLETE_IDE 51 select MIPS_DISABLE_OBSOLETE_IDE
61 select SYS_SUPPORTS_BIG_ENDIAN
62 select SYS_SUPPORTS_LITTLE_ENDIAN 52 select SYS_SUPPORTS_LITTLE_ENDIAN
63 select SYS_HAS_EARLY_PRINTK 53 select SYS_HAS_EARLY_PRINTK
64 54
@@ -66,27 +56,11 @@ config MIPS_DB1550
66 bool "Alchemy DB1550 board" 56 bool "Alchemy DB1550 board"
67 select ALCHEMY_GPIOINT_AU1000 57 select ALCHEMY_GPIOINT_AU1000
68 select HW_HAS_PCI 58 select HW_HAS_PCI
69 select DMA_NONCOHERENT 59 select DMA_COHERENT
70 select MIPS_DISABLE_OBSOLETE_IDE 60 select MIPS_DISABLE_OBSOLETE_IDE
71 select SYS_SUPPORTS_LITTLE_ENDIAN 61 select SYS_SUPPORTS_LITTLE_ENDIAN
72 select SYS_HAS_EARLY_PRINTK 62 select SYS_HAS_EARLY_PRINTK
73 63
74config MIPS_MIRAGE
75 bool "Alchemy Mirage board"
76 select DMA_NONCOHERENT
77 select ALCHEMY_GPIOINT_AU1000
78 select SYS_SUPPORTS_LITTLE_ENDIAN
79 select SYS_HAS_EARLY_PRINTK
80
81config MIPS_PB1000
82 bool "Alchemy PB1000 board"
83 select ALCHEMY_GPIOINT_AU1000
84 select DMA_NONCOHERENT
85 select HW_HAS_PCI
86 select SWAP_IO_SPACE
87 select SYS_SUPPORTS_LITTLE_ENDIAN
88 select SYS_HAS_EARLY_PRINTK
89
90config MIPS_PB1100 64config MIPS_PB1100
91 bool "Alchemy PB1100 board" 65 bool "Alchemy PB1100 board"
92 select ALCHEMY_GPIOINT_AU1000 66 select ALCHEMY_GPIOINT_AU1000
@@ -96,14 +70,6 @@ config MIPS_PB1100
96 select SYS_SUPPORTS_LITTLE_ENDIAN 70 select SYS_SUPPORTS_LITTLE_ENDIAN
97 select SYS_HAS_EARLY_PRINTK 71 select SYS_HAS_EARLY_PRINTK
98 72
99config MIPS_PB1200
100 bool "Alchemy PB1200 board"
101 select ALCHEMY_GPIOINT_AU1000
102 select DMA_NONCOHERENT
103 select MIPS_DISABLE_OBSOLETE_IDE
104 select SYS_SUPPORTS_LITTLE_ENDIAN
105 select SYS_HAS_EARLY_PRINTK
106
107config MIPS_PB1500 73config MIPS_PB1500
108 bool "Alchemy PB1500 board" 74 bool "Alchemy PB1500 board"
109 select ALCHEMY_GPIOINT_AU1000 75 select ALCHEMY_GPIOINT_AU1000
diff --git a/arch/mips/alchemy/Makefile b/arch/mips/alchemy/Makefile
new file mode 100644
index 000000000000..aac3b179bbc0
--- /dev/null
+++ b/arch/mips/alchemy/Makefile
@@ -0,0 +1,3 @@
1obj-$(CONFIG_MIPS_GPR) += board-gpr.o
2obj-$(CONFIG_MIPS_MTX1) += board-mtx1.o
3obj-$(CONFIG_MIPS_XXS1500) += board-xxs1500.o
diff --git a/arch/mips/alchemy/Platform b/arch/mips/alchemy/Platform
index 96e9e41f1b2a..7956274de15f 100644
--- a/arch/mips/alchemy/Platform
+++ b/arch/mips/alchemy/Platform
@@ -5,62 +5,31 @@ platform-$(CONFIG_MIPS_ALCHEMY) += alchemy/common/
5 5
6 6
7# 7#
8# AMD Alchemy Pb1000 eval board
9#
10platform-$(CONFIG_MIPS_PB1000) += alchemy/devboards/
11cflags-$(CONFIG_MIPS_PB1000) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
12load-$(CONFIG_MIPS_PB1000) += 0xffffffff80100000
13
14#
15# AMD Alchemy Pb1100 eval board 8# AMD Alchemy Pb1100 eval board
16# 9#
17platform-$(CONFIG_MIPS_PB1100) += alchemy/devboards/ 10platform-$(CONFIG_MIPS_PB1100) += alchemy/devboards/
18cflags-$(CONFIG_MIPS_PB1100) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
19load-$(CONFIG_MIPS_PB1100) += 0xffffffff80100000 11load-$(CONFIG_MIPS_PB1100) += 0xffffffff80100000
20 12
21# 13#
22# AMD Alchemy Pb1500 eval board 14# AMD Alchemy Pb1500 eval board
23# 15#
24platform-$(CONFIG_MIPS_PB1500) += alchemy/devboards/ 16platform-$(CONFIG_MIPS_PB1500) += alchemy/devboards/
25cflags-$(CONFIG_MIPS_PB1500) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
26load-$(CONFIG_MIPS_PB1500) += 0xffffffff80100000 17load-$(CONFIG_MIPS_PB1500) += 0xffffffff80100000
27 18
28# 19#
29# AMD Alchemy Pb1550 eval board 20# AMD Alchemy Pb1550 eval board
30# 21#
31platform-$(CONFIG_MIPS_PB1550) += alchemy/devboards/ 22platform-$(CONFIG_MIPS_PB1550) += alchemy/devboards/
32cflags-$(CONFIG_MIPS_PB1550) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
33load-$(CONFIG_MIPS_PB1550) += 0xffffffff80100000 23load-$(CONFIG_MIPS_PB1550) += 0xffffffff80100000
34 24
35# 25#
36# AMD Alchemy Pb1200 eval board 26# AMD Alchemy Db1000/Db1500/Db1100 eval boards
37#
38platform-$(CONFIG_MIPS_PB1200) += alchemy/devboards/
39cflags-$(CONFIG_MIPS_PB1200) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
40load-$(CONFIG_MIPS_PB1200) += 0xffffffff80100000
41
42#
43# AMD Alchemy Db1000 eval board
44# 27#
45platform-$(CONFIG_MIPS_DB1000) += alchemy/devboards/ 28platform-$(CONFIG_MIPS_DB1000) += alchemy/devboards/
46cflags-$(CONFIG_MIPS_DB1000) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 29cflags-$(CONFIG_MIPS_DB1000) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
47load-$(CONFIG_MIPS_DB1000) += 0xffffffff80100000 30load-$(CONFIG_MIPS_DB1000) += 0xffffffff80100000
48 31
49# 32#
50# AMD Alchemy Db1100 eval board
51#
52platform-$(CONFIG_MIPS_DB1100) += alchemy/devboards/
53cflags-$(CONFIG_MIPS_DB1100) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
54load-$(CONFIG_MIPS_DB1100) += 0xffffffff80100000
55
56#
57# AMD Alchemy Db1500 eval board
58#
59platform-$(CONFIG_MIPS_DB1500) += alchemy/devboards/
60cflags-$(CONFIG_MIPS_DB1500) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
61load-$(CONFIG_MIPS_DB1500) += 0xffffffff80100000
62
63#
64# AMD Alchemy Db1550 eval board 33# AMD Alchemy Db1550 eval board
65# 34#
66platform-$(CONFIG_MIPS_DB1550) += alchemy/devboards/ 35platform-$(CONFIG_MIPS_DB1550) += alchemy/devboards/
@@ -68,42 +37,35 @@ cflags-$(CONFIG_MIPS_DB1550) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
68load-$(CONFIG_MIPS_DB1550) += 0xffffffff80100000 37load-$(CONFIG_MIPS_DB1550) += 0xffffffff80100000
69 38
70# 39#
71# AMD Alchemy Db1200 eval board 40# AMD Alchemy Db1200/Pb1200 eval boards
72# 41#
73platform-$(CONFIG_MIPS_DB1200) += alchemy/devboards/ 42platform-$(CONFIG_MIPS_DB1200) += alchemy/devboards/
74cflags-$(CONFIG_MIPS_DB1200) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 43cflags-$(CONFIG_MIPS_DB1200) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
75load-$(CONFIG_MIPS_DB1200) += 0xffffffff80100000 44load-$(CONFIG_MIPS_DB1200) += 0xffffffff80100000
76 45
77# 46#
78# AMD Alchemy Bosporus eval board 47# NetLogic DBAu1300 development platform
79#
80platform-$(CONFIG_MIPS_BOSPORUS) += alchemy/devboards/
81cflags-$(CONFIG_MIPS_BOSPORUS) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
82load-$(CONFIG_MIPS_BOSPORUS) += 0xffffffff80100000
83
84#
85# AMD Alchemy Mirage eval board
86# 48#
87platform-$(CONFIG_MIPS_MIRAGE) += alchemy/devboards/ 49platform-$(CONFIG_MIPS_DB1300) += alchemy/devboards/
88cflags-$(CONFIG_MIPS_MIRAGE) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 50cflags-$(CONFIG_MIPS_DB1300) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
89load-$(CONFIG_MIPS_MIRAGE) += 0xffffffff80100000 51load-$(CONFIG_MIPS_DB1300) += 0xffffffff80100000
90 52
91# 53#
92# 4G-Systems eval board 54# 4G-Systems MTX-1 "MeshCube" wireless router
93# 55#
94platform-$(CONFIG_MIPS_MTX1) += alchemy/mtx-1/ 56platform-$(CONFIG_MIPS_MTX1) += alchemy/
95load-$(CONFIG_MIPS_MTX1) += 0xffffffff80100000 57load-$(CONFIG_MIPS_MTX1) += 0xffffffff80100000
96 58
97# 59#
98# MyCable eval board 60# MyCable eval board
99# 61#
100platform-$(CONFIG_MIPS_XXS1500) += alchemy/xxs1500/ 62platform-$(CONFIG_MIPS_XXS1500) += alchemy/
101load-$(CONFIG_MIPS_XXS1500) += 0xffffffff80100000 63load-$(CONFIG_MIPS_XXS1500) += 0xffffffff80100000
102 64
103# 65#
104# Trapeze ITS GRP board 66# Trapeze ITS GRP board
105# 67#
106platform-$(CONFIG_MIPS_GPR) += alchemy/gpr/ 68platform-$(CONFIG_MIPS_GPR) += alchemy/
107load-$(CONFIG_MIPS_GPR) += 0xffffffff80100000 69load-$(CONFIG_MIPS_GPR) += 0xffffffff80100000
108 70
109# boards can specify their own <gpio.h> in one of their include dirs. 71# boards can specify their own <gpio.h> in one of their include dirs.
diff --git a/arch/mips/alchemy/gpr/platform.c b/arch/mips/alchemy/board-gpr.c
index 982ce85db60d..ba3259086b9d 100644
--- a/arch/mips/alchemy/gpr/platform.c
+++ b/arch/mips/alchemy/board-gpr.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * GPR board platform device registration 2 * GPR board platform device registration (Au1550)
3 * 3 *
4 * Copyright (C) 2010 Wolfgang Grandegger <wg@denx.de> 4 * Copyright (C) 2010 Wolfgang Grandegger <wg@denx.de>
5 * 5 *
@@ -18,16 +18,89 @@
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */ 19 */
20 20
21#include <linux/delay.h>
21#include <linux/init.h> 22#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/kernel.h>
22#include <linux/platform_device.h> 25#include <linux/platform_device.h>
26#include <linux/pm.h>
23#include <linux/mtd/partitions.h> 27#include <linux/mtd/partitions.h>
24#include <linux/mtd/physmap.h> 28#include <linux/mtd/physmap.h>
25#include <linux/leds.h> 29#include <linux/leds.h>
26#include <linux/gpio.h> 30#include <linux/gpio.h>
27#include <linux/i2c.h> 31#include <linux/i2c.h>
28#include <linux/i2c-gpio.h> 32#include <linux/i2c-gpio.h>
29 33#include <asm/bootinfo.h>
34#include <asm/reboot.h>
30#include <asm/mach-au1x00/au1000.h> 35#include <asm/mach-au1x00/au1000.h>
36#include <prom.h>
37
38const char *get_system_type(void)
39{
40 return "GPR";
41}
42
43void __init prom_init(void)
44{
45 unsigned char *memsize_str;
46 unsigned long memsize;
47
48 prom_argc = fw_arg0;
49 prom_argv = (char **)fw_arg1;
50 prom_envp = (char **)fw_arg2;
51
52 prom_init_cmdline();
53
54 memsize_str = prom_getenv("memsize");
55 if (!memsize_str)
56 memsize = 0x04000000;
57 else
58 strict_strtoul(memsize_str, 0, &memsize);
59 add_memory_region(0, memsize, BOOT_MEM_RAM);
60}
61
62void prom_putchar(unsigned char c)
63{
64 alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
65}
66
67static void gpr_reset(char *c)
68{
69 /* switch System-LED to orange (red# and green# on) */
70 alchemy_gpio_direction_output(4, 0);
71 alchemy_gpio_direction_output(5, 0);
72
73 /* trigger watchdog to reset board in 200ms */
74 printk(KERN_EMERG "Triggering watchdog soft reset...\n");
75 raw_local_irq_disable();
76 alchemy_gpio_direction_output(1, 0);
77 udelay(1);
78 alchemy_gpio_set_value(1, 1);
79 while (1)
80 cpu_wait();
81}
82
83static void gpr_power_off(void)
84{
85 while (1)
86 cpu_wait();
87}
88
89void __init board_setup(void)
90{
91 printk(KERN_INFO "Trapeze ITS GPR board\n");
92
93 pm_power_off = gpr_power_off;
94 _machine_halt = gpr_power_off;
95 _machine_restart = gpr_reset;
96
97 /* Enable UART1/3 */
98 alchemy_uart_enable(AU1000_UART3_PHYS_ADDR);
99 alchemy_uart_enable(AU1000_UART1_PHYS_ADDR);
100
101 /* Take away Reset of UMTS-card */
102 alchemy_gpio_direction_output(215, 1);
103}
31 104
32/* 105/*
33 * Watchdog 106 * Watchdog
@@ -152,7 +225,7 @@ static struct i2c_gpio_platform_data gpr_i2c_data = {
152 .scl_is_open_drain = 1, 225 .scl_is_open_drain = 1,
153 .udelay = 2, /* ~100 kHz */ 226 .udelay = 2, /* ~100 kHz */
154 .timeout = HZ, 227 .timeout = HZ,
155 }; 228};
156 229
157static struct platform_device gpr_i2c_device = { 230static struct platform_device gpr_i2c_device = {
158 .name = "i2c-gpio", 231 .name = "i2c-gpio",
@@ -184,7 +257,7 @@ static int gpr_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
184 else if ((slot == 0) && (pin == 2)) 257 else if ((slot == 0) && (pin == 2))
185 return AU1550_PCI_INTB; 258 return AU1550_PCI_INTB;
186 259
187 return -1; 260 return 0xff;
188} 261}
189 262
190static struct alchemy_pci_platdata gpr_pci_pd = { 263static struct alchemy_pci_platdata gpr_pci_pd = {
diff --git a/arch/mips/alchemy/mtx-1/platform.c b/arch/mips/alchemy/board-mtx1.c
index cc47b6868ca3..295f1a95f745 100644
--- a/arch/mips/alchemy/mtx-1/platform.c
+++ b/arch/mips/alchemy/board-mtx1.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * MTX-1 platform devices registration 2 * MTX-1 platform devices registration (Au1500)
3 * 3 *
4 * Copyright (C) 2007-2009, Florian Fainelli <florian@openwrt.org> 4 * Copyright (C) 2007-2009, Florian Fainelli <florian@openwrt.org>
5 * 5 *
@@ -19,6 +19,8 @@
19 */ 19 */
20 20
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/kernel.h>
22#include <linux/platform_device.h> 24#include <linux/platform_device.h>
23#include <linux/leds.h> 25#include <linux/leds.h>
24#include <linux/gpio.h> 26#include <linux/gpio.h>
@@ -27,8 +29,85 @@
27#include <linux/mtd/partitions.h> 29#include <linux/mtd/partitions.h>
28#include <linux/mtd/physmap.h> 30#include <linux/mtd/physmap.h>
29#include <mtd/mtd-abi.h> 31#include <mtd/mtd-abi.h>
30 32#include <asm/bootinfo.h>
33#include <asm/reboot.h>
34#include <asm/mach-au1x00/au1000.h>
31#include <asm/mach-au1x00/au1xxx_eth.h> 35#include <asm/mach-au1x00/au1xxx_eth.h>
36#include <prom.h>
37
38const char *get_system_type(void)
39{
40 return "MTX-1";
41}
42
43void __init prom_init(void)
44{
45 unsigned char *memsize_str;
46 unsigned long memsize;
47
48 prom_argc = fw_arg0;
49 prom_argv = (char **)fw_arg1;
50 prom_envp = (char **)fw_arg2;
51
52 prom_init_cmdline();
53
54 memsize_str = prom_getenv("memsize");
55 if (!memsize_str)
56 memsize = 0x04000000;
57 else
58 strict_strtoul(memsize_str, 0, &memsize);
59 add_memory_region(0, memsize, BOOT_MEM_RAM);
60}
61
62void prom_putchar(unsigned char c)
63{
64 alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
65}
66
67static void mtx1_reset(char *c)
68{
69 /* Jump to the reset vector */
70 __asm__ __volatile__("jr\t%0" : : "r"(0xbfc00000));
71}
72
73static void mtx1_power_off(void)
74{
75 while (1)
76 asm volatile (
77 " .set mips32 \n"
78 " wait \n"
79 " .set mips0 \n");
80}
81
82void __init board_setup(void)
83{
84#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
85 /* Enable USB power switch */
86 alchemy_gpio_direction_output(204, 0);
87#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
88
89 /* Initialize sys_pinfunc */
90 au_writel(SYS_PF_NI2, SYS_PINFUNC);
91
92 /* Initialize GPIO */
93 au_writel(~0, KSEG1ADDR(AU1000_SYS_PHYS_ADDR) + SYS_TRIOUTCLR);
94 alchemy_gpio_direction_output(0, 0); /* Disable M66EN (PCI 66MHz) */
95 alchemy_gpio_direction_output(3, 1); /* Disable PCI CLKRUN# */
96 alchemy_gpio_direction_output(1, 1); /* Enable EXT_IO3 */
97 alchemy_gpio_direction_output(5, 0); /* Disable eth PHY TX_ER */
98
99 /* Enable LED and set it to green */
100 alchemy_gpio_direction_output(211, 1); /* green on */
101 alchemy_gpio_direction_output(212, 0); /* red off */
102
103 pm_power_off = mtx1_power_off;
104 _machine_halt = mtx1_power_off;
105 _machine_restart = mtx1_reset;
106
107 printk(KERN_INFO "4G Systems MTX-1 Board\n");
108}
109
110/******************************************************************************/
32 111
33static struct gpio_keys_button mtx1_gpio_button[] = { 112static struct gpio_keys_button mtx1_gpio_button[] = {
34 { 113 {
@@ -195,7 +274,6 @@ static struct platform_device mtx1_pci_host = {
195 .resource = alchemy_pci_host_res, 274 .resource = alchemy_pci_host_res,
196}; 275};
197 276
198
199static struct __initdata platform_device * mtx1_devs[] = { 277static struct __initdata platform_device * mtx1_devs[] = {
200 &mtx1_pci_host, 278 &mtx1_pci_host,
201 &mtx1_gpio_leds, 279 &mtx1_gpio_leds,
@@ -206,13 +284,19 @@ static struct __initdata platform_device * mtx1_devs[] = {
206 284
207static struct au1000_eth_platform_data mtx1_au1000_eth0_pdata = { 285static struct au1000_eth_platform_data mtx1_au1000_eth0_pdata = {
208 .phy_search_highest_addr = 1, 286 .phy_search_highest_addr = 1,
209 .phy1_search_mac0 = 1, 287 .phy1_search_mac0 = 1,
210}; 288};
211 289
212static int __init mtx1_register_devices(void) 290static int __init mtx1_register_devices(void)
213{ 291{
214 int rc; 292 int rc;
215 293
294 irq_set_irq_type(AU1500_GPIO204_INT, IRQ_TYPE_LEVEL_HIGH);
295 irq_set_irq_type(AU1500_GPIO201_INT, IRQ_TYPE_LEVEL_LOW);
296 irq_set_irq_type(AU1500_GPIO202_INT, IRQ_TYPE_LEVEL_LOW);
297 irq_set_irq_type(AU1500_GPIO203_INT, IRQ_TYPE_LEVEL_LOW);
298 irq_set_irq_type(AU1500_GPIO205_INT, IRQ_TYPE_LEVEL_LOW);
299
216 au1xxx_override_eth_cfg(0, &mtx1_au1000_eth0_pdata); 300 au1xxx_override_eth_cfg(0, &mtx1_au1000_eth0_pdata);
217 301
218 rc = gpio_request(mtx1_gpio_button[0].gpio, 302 rc = gpio_request(mtx1_gpio_button[0].gpio,
@@ -226,5 +310,4 @@ static int __init mtx1_register_devices(void)
226out: 310out:
227 return platform_add_devices(mtx1_devs, ARRAY_SIZE(mtx1_devs)); 311 return platform_add_devices(mtx1_devs, ARRAY_SIZE(mtx1_devs));
228} 312}
229
230arch_initcall(mtx1_register_devices); 313arch_initcall(mtx1_register_devices);
diff --git a/arch/mips/alchemy/board-xxs1500.c b/arch/mips/alchemy/board-xxs1500.c
new file mode 100644
index 000000000000..bd5513650293
--- /dev/null
+++ b/arch/mips/alchemy/board-xxs1500.c
@@ -0,0 +1,154 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * MyCable XXS1500 board support
4 *
5 * Copyright 2003, 2008 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc. <source@mvista.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 */
22
23#include <linux/kernel.h>
24#include <linux/init.h>
25#include <linux/interrupt.h>
26#include <linux/platform_device.h>
27#include <linux/gpio.h>
28#include <linux/delay.h>
29#include <linux/pm.h>
30#include <asm/bootinfo.h>
31#include <asm/reboot.h>
32#include <asm/mach-au1x00/au1000.h>
33#include <prom.h>
34
35const char *get_system_type(void)
36{
37 return "XXS1500";
38}
39
40void __init prom_init(void)
41{
42 unsigned char *memsize_str;
43 unsigned long memsize;
44
45 prom_argc = fw_arg0;
46 prom_argv = (char **)fw_arg1;
47 prom_envp = (char **)fw_arg2;
48
49 prom_init_cmdline();
50
51 memsize_str = prom_getenv("memsize");
52 if (!memsize_str || strict_strtoul(memsize_str, 0, &memsize))
53 memsize = 0x04000000;
54
55 add_memory_region(0, memsize, BOOT_MEM_RAM);
56}
57
58void prom_putchar(unsigned char c)
59{
60 alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
61}
62
63static void xxs1500_reset(char *c)
64{
65 /* Jump to the reset vector */
66 __asm__ __volatile__("jr\t%0" : : "r"(0xbfc00000));
67}
68
69static void xxs1500_power_off(void)
70{
71 while (1)
72 asm volatile (
73 " .set mips32 \n"
74 " wait \n"
75 " .set mips0 \n");
76}
77
78void __init board_setup(void)
79{
80 u32 pin_func;
81
82 pm_power_off = xxs1500_power_off;
83 _machine_halt = xxs1500_power_off;
84 _machine_restart = xxs1500_reset;
85
86 alchemy_gpio1_input_enable();
87 alchemy_gpio2_enable();
88
89 /* Set multiple use pins (UART3/GPIO) to UART (it's used as UART too) */
90 pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_UR3;
91 pin_func |= SYS_PF_UR3;
92 au_writel(pin_func, SYS_PINFUNC);
93
94 /* Enable UART */
95 alchemy_uart_enable(AU1000_UART3_PHYS_ADDR);
96 /* Enable DTR (MCR bit 0) = USB power up */
97 __raw_writel(1, (void __iomem *)KSEG1ADDR(AU1000_UART3_PHYS_ADDR + 0x18));
98 wmb();
99}
100
101/******************************************************************************/
102
103static struct resource xxs1500_pcmcia_res[] = {
104 {
105 .name = "pcmcia-io",
106 .flags = IORESOURCE_MEM,
107 .start = AU1000_PCMCIA_IO_PHYS_ADDR,
108 .end = AU1000_PCMCIA_IO_PHYS_ADDR + 0x000400000 - 1,
109 },
110 {
111 .name = "pcmcia-attr",
112 .flags = IORESOURCE_MEM,
113 .start = AU1000_PCMCIA_ATTR_PHYS_ADDR,
114 .end = AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
115 },
116 {
117 .name = "pcmcia-mem",
118 .flags = IORESOURCE_MEM,
119 .start = AU1000_PCMCIA_MEM_PHYS_ADDR,
120 .end = AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
121 },
122};
123
124static struct platform_device xxs1500_pcmcia_dev = {
125 .name = "xxs1500_pcmcia",
126 .id = -1,
127 .num_resources = ARRAY_SIZE(xxs1500_pcmcia_res),
128 .resource = xxs1500_pcmcia_res,
129};
130
131static struct platform_device *xxs1500_devs[] __initdata = {
132 &xxs1500_pcmcia_dev,
133};
134
135static int __init xxs1500_dev_init(void)
136{
137 irq_set_irq_type(AU1500_GPIO204_INT, IRQ_TYPE_LEVEL_HIGH);
138 irq_set_irq_type(AU1500_GPIO201_INT, IRQ_TYPE_LEVEL_LOW);
139 irq_set_irq_type(AU1500_GPIO202_INT, IRQ_TYPE_LEVEL_LOW);
140 irq_set_irq_type(AU1500_GPIO203_INT, IRQ_TYPE_LEVEL_LOW);
141 irq_set_irq_type(AU1500_GPIO205_INT, IRQ_TYPE_LEVEL_LOW);
142 irq_set_irq_type(AU1500_GPIO207_INT, IRQ_TYPE_LEVEL_LOW);
143
144 irq_set_irq_type(AU1500_GPIO0_INT, IRQ_TYPE_LEVEL_LOW);
145 irq_set_irq_type(AU1500_GPIO1_INT, IRQ_TYPE_LEVEL_LOW);
146 irq_set_irq_type(AU1500_GPIO2_INT, IRQ_TYPE_LEVEL_LOW);
147 irq_set_irq_type(AU1500_GPIO3_INT, IRQ_TYPE_LEVEL_LOW);
148 irq_set_irq_type(AU1500_GPIO4_INT, IRQ_TYPE_LEVEL_LOW); /* CF irq */
149 irq_set_irq_type(AU1500_GPIO5_INT, IRQ_TYPE_LEVEL_LOW);
150
151 return platform_add_devices(xxs1500_devs,
152 ARRAY_SIZE(xxs1500_devs));
153}
154device_initcall(xxs1500_dev_init);
diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile
index 811ece7b22e3..407ebc00e661 100644
--- a/arch/mips/alchemy/common/Makefile
+++ b/arch/mips/alchemy/common/Makefile
@@ -6,9 +6,7 @@
6# 6#
7 7
8obj-y += prom.o time.o clocks.o platform.o power.o setup.o \ 8obj-y += prom.o time.o clocks.o platform.o power.o setup.o \
9 sleeper.o dma.o dbdma.o 9 sleeper.o dma.o dbdma.o vss.o irq.o
10
11obj-$(CONFIG_ALCHEMY_GPIOINT_AU1000) += irq.o
12 10
13# optional gpiolib support 11# optional gpiolib support
14ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),) 12ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),)
diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c
index 0e63ee487d6d..cf02d7dc2df0 100644
--- a/arch/mips/alchemy/common/dbdma.c
+++ b/arch/mips/alchemy/common/dbdma.c
@@ -148,6 +148,50 @@ static dbdev_tab_t au1200_dbdev_tab[] __initdata = {
148 { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, 148 { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
149}; 149};
150 150
151static dbdev_tab_t au1300_dbdev_tab[] __initdata = {
152 { AU1300_DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x10100004, 0, 0 },
153 { AU1300_DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x10100000, 0, 0 },
154 { AU1300_DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x10101004, 0, 0 },
155 { AU1300_DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x10101000, 0, 0 },
156 { AU1300_DSCR_CMD0_UART2_TX, DEV_FLAGS_OUT, 0, 8, 0x10102004, 0, 0 },
157 { AU1300_DSCR_CMD0_UART2_RX, DEV_FLAGS_IN, 0, 8, 0x10102000, 0, 0 },
158 { AU1300_DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x10103004, 0, 0 },
159 { AU1300_DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x10103000, 0, 0 },
160
161 { AU1300_DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 },
162 { AU1300_DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 },
163 { AU1300_DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 8, 8, 0x10601000, 0, 0 },
164 { AU1300_DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 8, 8, 0x10601004, 0, 0 },
165
166 { AU1300_DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 },
167 { AU1300_DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 },
168
169 { AU1300_DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0001c, 0, 0 },
170 { AU1300_DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x10a0001c, 0, 0 },
171 { AU1300_DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0101c, 0, 0 },
172 { AU1300_DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x10a0101c, 0, 0 },
173 { AU1300_DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0201c, 0, 0 },
174 { AU1300_DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 16, 0x10a0201c, 0, 0 },
175 { AU1300_DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0301c, 0, 0 },
176 { AU1300_DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 16, 0x10a0301c, 0, 0 },
177
178 { AU1300_DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
179 { AU1300_DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
180
181 { AU1300_DSCR_CMD0_SDMS_TX2, DEV_FLAGS_OUT, 4, 8, 0x10602000, 0, 0 },
182 { AU1300_DSCR_CMD0_SDMS_RX2, DEV_FLAGS_IN, 4, 8, 0x10602004, 0, 0 },
183
184 { AU1300_DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
185
186 { AU1300_DSCR_CMD0_UDMA, DEV_FLAGS_ANYUSE, 0, 32, 0x14001810, 0, 0 },
187
188 { AU1300_DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
189 { AU1300_DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
190
191 { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
192 { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
193};
194
151/* 32 predefined plus 32 custom */ 195/* 32 predefined plus 32 custom */
152#define DBDEV_TAB_SIZE 64 196#define DBDEV_TAB_SIZE 64
153 197
@@ -1019,8 +1063,7 @@ static int __init dbdma_setup(unsigned int irq, dbdev_tab_t *idtable)
1019 dbdma_gptr->ddma_inten = 0xffff; 1063 dbdma_gptr->ddma_inten = 0xffff;
1020 au_sync(); 1064 au_sync();
1021 1065
1022 ret = request_irq(irq, dbdma_interrupt, IRQF_DISABLED, "dbdma", 1066 ret = request_irq(irq, dbdma_interrupt, 0, "dbdma", (void *)dbdma_gptr);
1023 (void *)dbdma_gptr);
1024 if (ret) 1067 if (ret)
1025 printk(KERN_ERR "Cannot grab DBDMA interrupt!\n"); 1068 printk(KERN_ERR "Cannot grab DBDMA interrupt!\n");
1026 else { 1069 else {
@@ -1038,6 +1081,8 @@ static int __init alchemy_dbdma_init(void)
1038 return dbdma_setup(AU1550_DDMA_INT, au1550_dbdev_tab); 1081 return dbdma_setup(AU1550_DDMA_INT, au1550_dbdev_tab);
1039 case ALCHEMY_CPU_AU1200: 1082 case ALCHEMY_CPU_AU1200:
1040 return dbdma_setup(AU1200_DDMA_INT, au1200_dbdev_tab); 1083 return dbdma_setup(AU1200_DDMA_INT, au1200_dbdev_tab);
1084 case ALCHEMY_CPU_AU1300:
1085 return dbdma_setup(AU1300_DDMA_INT, au1300_dbdev_tab);
1041 } 1086 }
1042 return 0; 1087 return 0;
1043} 1088}
diff --git a/arch/mips/alchemy/common/gpiolib.c b/arch/mips/alchemy/common/gpiolib.c
index 91fb4d9e30fd..f1b50f0c01db 100644
--- a/arch/mips/alchemy/common/gpiolib.c
+++ b/arch/mips/alchemy/common/gpiolib.c
@@ -27,6 +27,7 @@
27 * CONFIG_ALCHEMY_GPIO_INDIRECT=n, otherwise compilation will fail! 27 * CONFIG_ALCHEMY_GPIO_INDIRECT=n, otherwise compilation will fail!
28 * au1000 SoC have only one GPIO block : GPIO1 28 * au1000 SoC have only one GPIO block : GPIO1
29 * Au1100, Au15x0, Au12x0 have a second one : GPIO2 29 * Au1100, Au15x0, Au12x0 have a second one : GPIO2
30 * Au1300 is totally different: 1 block with up to 128 GPIOs
30 */ 31 */
31 32
32#include <linux/init.h> 33#include <linux/init.h>
@@ -35,6 +36,7 @@
35#include <linux/types.h> 36#include <linux/types.h>
36#include <linux/gpio.h> 37#include <linux/gpio.h>
37#include <asm/mach-au1x00/gpio-au1000.h> 38#include <asm/mach-au1x00/gpio-au1000.h>
39#include <asm/mach-au1x00/gpio-au1300.h>
38 40
39static int gpio2_get(struct gpio_chip *chip, unsigned offset) 41static int gpio2_get(struct gpio_chip *chip, unsigned offset)
40{ 42{
@@ -115,6 +117,43 @@ struct gpio_chip alchemy_gpio_chip[] = {
115 }, 117 },
116}; 118};
117 119
120static int alchemy_gpic_get(struct gpio_chip *chip, unsigned int off)
121{
122 return au1300_gpio_get_value(off + AU1300_GPIO_BASE);
123}
124
125static void alchemy_gpic_set(struct gpio_chip *chip, unsigned int off, int v)
126{
127 au1300_gpio_set_value(off + AU1300_GPIO_BASE, v);
128}
129
130static int alchemy_gpic_dir_input(struct gpio_chip *chip, unsigned int off)
131{
132 return au1300_gpio_direction_input(off + AU1300_GPIO_BASE);
133}
134
135static int alchemy_gpic_dir_output(struct gpio_chip *chip, unsigned int off,
136 int v)
137{
138 return au1300_gpio_direction_output(off + AU1300_GPIO_BASE, v);
139}
140
141static int alchemy_gpic_gpio_to_irq(struct gpio_chip *chip, unsigned int off)
142{
143 return au1300_gpio_to_irq(off + AU1300_GPIO_BASE);
144}
145
146static struct gpio_chip au1300_gpiochip = {
147 .label = "alchemy-gpic",
148 .direction_input = alchemy_gpic_dir_input,
149 .direction_output = alchemy_gpic_dir_output,
150 .get = alchemy_gpic_get,
151 .set = alchemy_gpic_set,
152 .to_irq = alchemy_gpic_gpio_to_irq,
153 .base = AU1300_GPIO_BASE,
154 .ngpio = AU1300_GPIO_NUM,
155};
156
118static int __init alchemy_gpiochip_init(void) 157static int __init alchemy_gpiochip_init(void)
119{ 158{
120 int ret = 0; 159 int ret = 0;
@@ -127,6 +166,9 @@ static int __init alchemy_gpiochip_init(void)
127 ret = gpiochip_add(&alchemy_gpio_chip[0]); 166 ret = gpiochip_add(&alchemy_gpio_chip[0]);
128 ret |= gpiochip_add(&alchemy_gpio_chip[1]); 167 ret |= gpiochip_add(&alchemy_gpio_chip[1]);
129 break; 168 break;
169 case ALCHEMY_CPU_AU1300:
170 ret = gpiochip_add(&au1300_gpiochip);
171 break;
130 } 172 }
131 return ret; 173 return ret;
132} 174}
diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c
index 8b60ba0675e2..94fbcd19eb9c 100644
--- a/arch/mips/alchemy/common/irq.c
+++ b/arch/mips/alchemy/common/irq.c
@@ -25,19 +25,15 @@
25 * 675 Mass Ave, Cambridge, MA 02139, USA. 25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */ 26 */
27 27
28#include <linux/bitops.h> 28#include <linux/export.h>
29#include <linux/init.h> 29#include <linux/init.h>
30#include <linux/interrupt.h> 30#include <linux/interrupt.h>
31#include <linux/irq.h>
32#include <linux/slab.h> 31#include <linux/slab.h>
33#include <linux/syscore_ops.h> 32#include <linux/syscore_ops.h>
34 33
35#include <asm/irq_cpu.h> 34#include <asm/irq_cpu.h>
36#include <asm/mipsregs.h>
37#include <asm/mach-au1x00/au1000.h> 35#include <asm/mach-au1x00/au1000.h>
38#ifdef CONFIG_MIPS_PB1000 36#include <asm/mach-au1x00/gpio-au1300.h>
39#include <asm/mach-pb1x00/pb1000.h>
40#endif
41 37
42/* Interrupt Controller register offsets */ 38/* Interrupt Controller register offsets */
43#define IC_CFG0RD 0x40 39#define IC_CFG0RD 0x40
@@ -69,7 +65,17 @@
69#define IC_FALLINGCLR 0x7C 65#define IC_FALLINGCLR 0x7C
70#define IC_TESTBIT 0x80 66#define IC_TESTBIT 0x80
71 67
72static int au1x_ic_settype(struct irq_data *d, unsigned int flow_type); 68/* per-processor fixed function irqs */
69struct alchemy_irqmap {
70 int irq; /* linux IRQ number */
71 int type; /* IRQ_TYPE_ */
72 int prio; /* irq priority, 0 highest, 3 lowest */
73 int internal; /* GPIC: internal source (no ext. pin)? */
74};
75
76static int au1x_ic_settype(struct irq_data *d, unsigned int type);
77static int au1300_gpic_settype(struct irq_data *d, unsigned int type);
78
73 79
74/* NOTE on interrupt priorities: The original writers of this code said: 80/* NOTE on interrupt priorities: The original writers of this code said:
75 * 81 *
@@ -77,176 +83,207 @@ static int au1x_ic_settype(struct irq_data *d, unsigned int flow_type);
77 * the USB devices-side packet complete interrupt (USB_DEV_REQ_INT) 83 * the USB devices-side packet complete interrupt (USB_DEV_REQ_INT)
78 * needs the highest priority. 84 * needs the highest priority.
79 */ 85 */
80 86struct alchemy_irqmap au1000_irqmap[] __initdata = {
81/* per-processor fixed function irqs */ 87 { AU1000_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
82struct au1xxx_irqmap { 88 { AU1000_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
83 int im_irq; 89 { AU1000_UART2_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
84 int im_type; 90 { AU1000_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
85 int im_request; /* set 1 to get higher priority */ 91 { AU1000_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
92 { AU1000_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
93 { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
94 { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
95 { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
96 { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
97 { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
98 { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
99 { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
100 { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
101 { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
102 { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
103 { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
104 { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
105 { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
106 { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
107 { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
108 { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0, 0 },
109 { AU1000_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
110 { AU1000_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
111 { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0, 0 },
112 { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
113 { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 1, 0 },
114 { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
115 { AU1000_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
116 { AU1000_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
117 { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
118 { -1, },
86}; 119};
87 120
88struct au1xxx_irqmap au1000_irqmap[] __initdata = { 121struct alchemy_irqmap au1500_irqmap[] __initdata = {
89 { AU1000_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 122 { AU1500_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
90 { AU1000_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 123 { AU1500_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 1, 0 },
91 { AU1000_UART2_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 124 { AU1500_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 1, 0 },
92 { AU1000_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 125 { AU1500_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
93 { AU1000_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 126 { AU1500_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 1, 0 },
94 { AU1000_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 127 { AU1500_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 1, 0 },
95 { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 }, 128 { AU1500_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
96 { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 }, 129 { AU1500_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
97 { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 }, 130 { AU1500_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
98 { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 }, 131 { AU1500_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
99 { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 }, 132 { AU1500_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
100 { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 }, 133 { AU1500_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
101 { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 }, 134 { AU1500_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
102 { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 }, 135 { AU1500_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
103 { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, 136 { AU1500_TOY_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
104 { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 137 { AU1500_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
105 { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 138 { AU1500_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
106 { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, 139 { AU1500_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
107 { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, 140 { AU1500_RTC_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
108 { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 141 { AU1500_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
109 { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 142 { AU1500_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
110 { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, 143 { AU1500_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0, 0 },
111 { AU1000_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 144 { AU1500_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0, 0 },
112 { AU1000_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 145 { AU1500_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
113 { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, 146 { AU1500_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 1, 0 },
114 { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 }, 147 { AU1500_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
115 { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, 148 { AU1500_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
116 { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 }, 149 { AU1500_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
117 { AU1000_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 150 { AU1500_AC97C_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
118 { AU1000_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
119 { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 },
120 { -1, }, 151 { -1, },
121}; 152};
122 153
123struct au1xxx_irqmap au1500_irqmap[] __initdata = { 154struct alchemy_irqmap au1100_irqmap[] __initdata = {
124 { AU1500_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 155 { AU1100_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
125 { AU1500_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 0 }, 156 { AU1100_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
126 { AU1500_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 0 }, 157 { AU1100_SD_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
127 { AU1500_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 158 { AU1100_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
128 { AU1500_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 0 }, 159 { AU1100_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
129 { AU1500_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 0 }, 160 { AU1100_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
130 { AU1500_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 }, 161 { AU1100_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
131 { AU1500_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 }, 162 { AU1100_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
132 { AU1500_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 }, 163 { AU1100_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
133 { AU1500_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 }, 164 { AU1100_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
134 { AU1500_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 }, 165 { AU1100_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
135 { AU1500_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 }, 166 { AU1100_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
136 { AU1500_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 }, 167 { AU1100_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
137 { AU1500_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 }, 168 { AU1100_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
138 { AU1500_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, 169 { AU1100_TOY_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
139 { AU1500_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 170 { AU1100_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
140 { AU1500_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 171 { AU1100_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
141 { AU1500_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, 172 { AU1100_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
142 { AU1500_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, 173 { AU1100_RTC_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
143 { AU1500_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 174 { AU1100_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
144 { AU1500_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 175 { AU1100_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
145 { AU1500_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, 176 { AU1100_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0, 0 },
146 { AU1500_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, 177 { AU1100_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
147 { AU1500_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 }, 178 { AU1100_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
148 { AU1500_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, 179 { AU1100_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0, 0 },
149 { AU1500_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 }, 180 { AU1100_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
150 { AU1500_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 181 { AU1100_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 1, 0 },
151 { AU1500_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 182 { AU1100_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
152 { AU1500_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 }, 183 { AU1100_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
184 { AU1100_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
185 { AU1100_AC97C_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
153 { -1, }, 186 { -1, },
154}; 187};
155 188
156struct au1xxx_irqmap au1100_irqmap[] __initdata = { 189struct alchemy_irqmap au1550_irqmap[] __initdata = {
157 { AU1100_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 190 { AU1550_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
158 { AU1100_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 191 { AU1550_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 1, 0 },
159 { AU1100_SD_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 192 { AU1550_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 1, 0 },
160 { AU1100_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 193 { AU1550_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
161 { AU1100_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 194 { AU1550_CRYPTO_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
162 { AU1100_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 195 { AU1550_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 1, 0 },
163 { AU1100_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 }, 196 { AU1550_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 1, 0 },
164 { AU1100_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 }, 197 { AU1550_PCI_RST_INT, IRQ_TYPE_LEVEL_LOW, 1, 0 },
165 { AU1100_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 }, 198 { AU1550_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
166 { AU1100_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 }, 199 { AU1550_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
167 { AU1100_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 }, 200 { AU1550_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
168 { AU1100_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 }, 201 { AU1550_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
169 { AU1100_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 }, 202 { AU1550_PSC2_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
170 { AU1100_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 }, 203 { AU1550_PSC3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
171 { AU1100_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, 204 { AU1550_TOY_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
172 { AU1100_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 205 { AU1550_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
173 { AU1100_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 206 { AU1550_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
174 { AU1100_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, 207 { AU1550_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
175 { AU1100_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, 208 { AU1550_RTC_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
176 { AU1100_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 209 { AU1550_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
177 { AU1100_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 210 { AU1550_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
178 { AU1100_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, 211 { AU1550_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0, 0 },
179 { AU1100_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 212 { AU1550_NAND_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
180 { AU1100_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 213 { AU1550_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0, 0 },
181 { AU1100_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, 214 { AU1550_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
182 { AU1100_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 }, 215 { AU1550_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 1, 0 },
183 { AU1100_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, 216 { AU1550_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
184 { AU1100_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 }, 217 { AU1550_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
185 { AU1100_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
186 { AU1100_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
187 { AU1100_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 },
188 { -1, }, 218 { -1, },
189}; 219};
190 220
191struct au1xxx_irqmap au1550_irqmap[] __initdata = { 221struct alchemy_irqmap au1200_irqmap[] __initdata = {
192 { AU1550_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 222 { AU1200_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
193 { AU1550_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 0 }, 223 { AU1200_SWT_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
194 { AU1550_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 0 }, 224 { AU1200_SD_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
195 { AU1550_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 225 { AU1200_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
196 { AU1550_CRYPTO_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 226 { AU1200_MAE_BE_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
197 { AU1550_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 0 }, 227 { AU1200_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
198 { AU1550_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 0 }, 228 { AU1200_MAE_FE_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
199 { AU1550_PCI_RST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, 229 { AU1200_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
200 { AU1550_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 230 { AU1200_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
201 { AU1550_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 231 { AU1200_AES_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
202 { AU1550_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 232 { AU1200_CAMERA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
203 { AU1550_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 233 { AU1200_TOY_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
204 { AU1550_PSC2_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 234 { AU1200_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
205 { AU1550_PSC3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 235 { AU1200_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
206 { AU1550_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, 236 { AU1200_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
207 { AU1550_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 237 { AU1200_RTC_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
208 { AU1550_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 238 { AU1200_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
209 { AU1550_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, 239 { AU1200_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
210 { AU1550_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, 240 { AU1200_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0, 0 },
211 { AU1550_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 241 { AU1200_NAND_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
212 { AU1550_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 242 { AU1200_USB_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
213 { AU1550_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, 243 { AU1200_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
214 { AU1550_NAND_INT, IRQ_TYPE_EDGE_RISING, 0 }, 244 { AU1200_MAE_BOTH_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
215 { AU1550_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 1 },
216 { AU1550_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
217 { AU1550_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
218 { AU1550_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
219 { AU1550_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
220 { -1, }, 245 { -1, },
221}; 246};
222 247
223struct au1xxx_irqmap au1200_irqmap[] __initdata = { 248static struct alchemy_irqmap au1300_irqmap[] __initdata = {
224 { AU1200_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 249 /* multifunction: gpio pin or device */
225 { AU1200_SWT_INT, IRQ_TYPE_EDGE_RISING, 0 }, 250 { AU1300_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, },
226 { AU1200_SD_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 251 { AU1300_UART2_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, },
227 { AU1200_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 252 { AU1300_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, },
228 { AU1200_MAE_BE_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 253 { AU1300_SD1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, },
229 { AU1200_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 254 { AU1300_SD2_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, },
230 { AU1200_MAE_FE_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 255 { AU1300_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, },
231 { AU1200_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 256 { AU1300_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, },
232 { AU1200_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 257 { AU1300_PSC2_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, },
233 { AU1200_AES_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 258 { AU1300_PSC3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, },
234 { AU1200_CAMERA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 259 { AU1300_NAND_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, },
235 { AU1200_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, 260 /* au1300 internal */
236 { AU1200_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 261 { AU1300_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, },
237 { AU1200_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 262 { AU1300_MMU_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, },
238 { AU1200_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, 263 { AU1300_MPU_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, },
239 { AU1200_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, 264 { AU1300_GPU_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, },
240 { AU1200_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 265 { AU1300_UDMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, },
241 { AU1200_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 266 { AU1300_TOY_INT, IRQ_TYPE_EDGE_RISING, 1, 1, },
242 { AU1200_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, 267 { AU1300_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 1, },
243 { AU1200_NAND_INT, IRQ_TYPE_EDGE_RISING, 0 }, 268 { AU1300_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 1, },
244 { AU1200_USB_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 269 { AU1300_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1, 1, },
245 { AU1200_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 270 { AU1300_RTC_INT, IRQ_TYPE_EDGE_RISING, 1, 1, },
246 { AU1200_MAE_BOTH_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 271 { AU1300_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 1, },
247 { -1, }, 272 { AU1300_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 1, },
273 { AU1300_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0, 1, },
274 { AU1300_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, },
275 { AU1300_SD0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, },
276 { AU1300_USB_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, },
277 { AU1300_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, },
278 { AU1300_BSA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, },
279 { AU1300_MPE_INT, IRQ_TYPE_EDGE_RISING, 1, 1, },
280 { AU1300_ITE_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, },
281 { AU1300_AES_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, },
282 { AU1300_CIM_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, },
283 { -1, }, /* terminator */
248}; 284};
249 285
286/******************************************************************************/
250 287
251static void au1x_ic0_unmask(struct irq_data *d) 288static void au1x_ic0_unmask(struct irq_data *d)
252{ 289{
@@ -265,14 +302,6 @@ static void au1x_ic1_unmask(struct irq_data *d)
265 302
266 __raw_writel(1 << bit, base + IC_MASKSET); 303 __raw_writel(1 << bit, base + IC_MASKSET);
267 __raw_writel(1 << bit, base + IC_WAKESET); 304 __raw_writel(1 << bit, base + IC_WAKESET);
268
269/* very hacky. does the pb1000 cpld auto-disable this int?
270 * nowhere in the current kernel sources is it disabled. --mlau
271 */
272#if defined(CONFIG_MIPS_PB1000)
273 if (d->irq == AU1000_GPIO15_INT)
274 __raw_writel(0x4000, (void __iomem *)PB1000_MDR); /* enable int */
275#endif
276 wmb(); 305 wmb();
277} 306}
278 307
@@ -470,40 +499,219 @@ static int au1x_ic_settype(struct irq_data *d, unsigned int flow_type)
470 return ret; 499 return ret;
471} 500}
472 501
473asmlinkage void plat_irq_dispatch(void) 502/******************************************************************************/
503
504/*
505 * au1300_gpic_chgcfg - change PIN configuration.
506 * @gpio: pin to change (0-based GPIO number from datasheet).
507 * @clr: clear all bits set in 'clr'.
508 * @set: set these bits.
509 *
510 * modifies a pins' configuration register, bits set in @clr will
511 * be cleared in the register, bits in @set will be set.
512 */
513static inline void au1300_gpic_chgcfg(unsigned int gpio,
514 unsigned long clr,
515 unsigned long set)
516{
517 void __iomem *r = AU1300_GPIC_ADDR;
518 unsigned long l;
519
520 r += gpio * 4; /* offset into pin config array */
521 l = __raw_readl(r + AU1300_GPIC_PINCFG);
522 l &= ~clr;
523 l |= set;
524 __raw_writel(l, r + AU1300_GPIC_PINCFG);
525 wmb();
526}
527
528/*
529 * au1300_pinfunc_to_gpio - assign a pin as GPIO input (GPIO ctrl).
530 * @pin: pin (0-based GPIO number from datasheet).
531 *
532 * Assigns a GPIO pin to the GPIO controller, so its level can either
533 * be read or set through the generic GPIO functions.
534 * If you need a GPOUT, use au1300_gpio_set_value(pin, 0/1).
535 * REVISIT: is this function really necessary?
536 */
537void au1300_pinfunc_to_gpio(enum au1300_multifunc_pins gpio)
538{
539 au1300_gpio_direction_input(gpio + AU1300_GPIO_BASE);
540}
541EXPORT_SYMBOL_GPL(au1300_pinfunc_to_gpio);
542
543/*
544 * au1300_pinfunc_to_dev - assign a pin to the device function.
545 * @pin: pin (0-based GPIO number from datasheet).
546 *
547 * Assigns a GPIO pin to its associated device function; the pin will be
548 * driven by the device and not through GPIO functions.
549 */
550void au1300_pinfunc_to_dev(enum au1300_multifunc_pins gpio)
551{
552 void __iomem *r = AU1300_GPIC_ADDR;
553 unsigned long bit;
554
555 r += GPIC_GPIO_BANKOFF(gpio);
556 bit = GPIC_GPIO_TO_BIT(gpio);
557 __raw_writel(bit, r + AU1300_GPIC_DEVSEL);
558 wmb();
559}
560EXPORT_SYMBOL_GPL(au1300_pinfunc_to_dev);
561
562/*
563 * au1300_set_irq_priority - set internal priority of IRQ.
564 * @irq: irq to set priority (linux irq number).
565 * @p: priority (0 = highest, 3 = lowest).
566 */
567void au1300_set_irq_priority(unsigned int irq, int p)
474{ 568{
475 unsigned int pending = read_c0_status() & read_c0_cause(); 569 irq -= ALCHEMY_GPIC_INT_BASE;
476 unsigned long s, off; 570 au1300_gpic_chgcfg(irq, GPIC_CFG_IL_MASK, GPIC_CFG_IL_SET(p));
477 571}
478 if (pending & CAUSEF_IP7) { 572EXPORT_SYMBOL_GPL(au1300_set_irq_priority);
479 off = MIPS_CPU_IRQ_BASE + 7; 573
480 goto handle; 574/*
481 } else if (pending & CAUSEF_IP2) { 575 * au1300_set_dbdma_gpio - assign a gpio to one of the DBDMA triggers.
482 s = KSEG1ADDR(AU1000_IC0_PHYS_ADDR) + IC_REQ0INT; 576 * @dchan: dbdma trigger select (0, 1).
483 off = AU1000_INTC0_INT_BASE; 577 * @gpio: pin to assign as trigger.
484 } else if (pending & CAUSEF_IP3) { 578 *
485 s = KSEG1ADDR(AU1000_IC0_PHYS_ADDR) + IC_REQ1INT; 579 * DBDMA controller has 2 external trigger sources; this function
486 off = AU1000_INTC0_INT_BASE; 580 * assigns a GPIO to the selected trigger.
487 } else if (pending & CAUSEF_IP4) { 581 */
488 s = KSEG1ADDR(AU1000_IC1_PHYS_ADDR) + IC_REQ0INT; 582void au1300_set_dbdma_gpio(int dchan, unsigned int gpio)
489 off = AU1000_INTC1_INT_BASE; 583{
490 } else if (pending & CAUSEF_IP5) { 584 unsigned long r;
491 s = KSEG1ADDR(AU1000_IC1_PHYS_ADDR) + IC_REQ1INT; 585
492 off = AU1000_INTC1_INT_BASE; 586 if ((dchan >= 0) && (dchan <= 1)) {
493 } else 587 r = __raw_readl(AU1300_GPIC_ADDR + AU1300_GPIC_DMASEL);
494 goto spurious; 588 r &= ~(0xff << (8 * dchan));
495 589 r |= (gpio & 0x7f) << (8 * dchan);
496 s = __raw_readl((void __iomem *)s); 590 __raw_writel(r, AU1300_GPIC_ADDR + AU1300_GPIC_DMASEL);
497 if (unlikely(!s)) { 591 wmb();
498spurious:
499 spurious_interrupt();
500 return;
501 } 592 }
502 off += __ffs(s);
503handle:
504 do_IRQ(off);
505} 593}
506 594
595static inline void gpic_pin_set_idlewake(unsigned int gpio, int allow)
596{
597 au1300_gpic_chgcfg(gpio, GPIC_CFG_IDLEWAKE,
598 allow ? GPIC_CFG_IDLEWAKE : 0);
599}
600
601static void au1300_gpic_mask(struct irq_data *d)
602{
603 void __iomem *r = AU1300_GPIC_ADDR;
604 unsigned long bit, irq = d->irq;
605
606 irq -= ALCHEMY_GPIC_INT_BASE;
607 r += GPIC_GPIO_BANKOFF(irq);
608 bit = GPIC_GPIO_TO_BIT(irq);
609 __raw_writel(bit, r + AU1300_GPIC_IDIS);
610 wmb();
611
612 gpic_pin_set_idlewake(irq, 0);
613}
614
615static void au1300_gpic_unmask(struct irq_data *d)
616{
617 void __iomem *r = AU1300_GPIC_ADDR;
618 unsigned long bit, irq = d->irq;
619
620 irq -= ALCHEMY_GPIC_INT_BASE;
621
622 gpic_pin_set_idlewake(irq, 1);
623
624 r += GPIC_GPIO_BANKOFF(irq);
625 bit = GPIC_GPIO_TO_BIT(irq);
626 __raw_writel(bit, r + AU1300_GPIC_IEN);
627 wmb();
628}
629
630static void au1300_gpic_maskack(struct irq_data *d)
631{
632 void __iomem *r = AU1300_GPIC_ADDR;
633 unsigned long bit, irq = d->irq;
634
635 irq -= ALCHEMY_GPIC_INT_BASE;
636 r += GPIC_GPIO_BANKOFF(irq);
637 bit = GPIC_GPIO_TO_BIT(irq);
638 __raw_writel(bit, r + AU1300_GPIC_IPEND); /* ack */
639 __raw_writel(bit, r + AU1300_GPIC_IDIS); /* mask */
640 wmb();
641
642 gpic_pin_set_idlewake(irq, 0);
643}
644
645static void au1300_gpic_ack(struct irq_data *d)
646{
647 void __iomem *r = AU1300_GPIC_ADDR;
648 unsigned long bit, irq = d->irq;
649
650 irq -= ALCHEMY_GPIC_INT_BASE;
651 r += GPIC_GPIO_BANKOFF(irq);
652 bit = GPIC_GPIO_TO_BIT(irq);
653 __raw_writel(bit, r + AU1300_GPIC_IPEND); /* ack */
654 wmb();
655}
656
657static struct irq_chip au1300_gpic = {
658 .name = "GPIOINT",
659 .irq_ack = au1300_gpic_ack,
660 .irq_mask = au1300_gpic_mask,
661 .irq_mask_ack = au1300_gpic_maskack,
662 .irq_unmask = au1300_gpic_unmask,
663 .irq_set_type = au1300_gpic_settype,
664};
665
666static int au1300_gpic_settype(struct irq_data *d, unsigned int type)
667{
668 unsigned long s;
669 unsigned char *name = NULL;
670 irq_flow_handler_t hdl = NULL;
671
672 switch (type) {
673 case IRQ_TYPE_LEVEL_HIGH:
674 s = GPIC_CFG_IC_LEVEL_HIGH;
675 name = "high";
676 hdl = handle_level_irq;
677 break;
678 case IRQ_TYPE_LEVEL_LOW:
679 s = GPIC_CFG_IC_LEVEL_LOW;
680 name = "low";
681 hdl = handle_level_irq;
682 break;
683 case IRQ_TYPE_EDGE_RISING:
684 s = GPIC_CFG_IC_EDGE_RISE;
685 name = "posedge";
686 hdl = handle_edge_irq;
687 break;
688 case IRQ_TYPE_EDGE_FALLING:
689 s = GPIC_CFG_IC_EDGE_FALL;
690 name = "negedge";
691 hdl = handle_edge_irq;
692 break;
693 case IRQ_TYPE_EDGE_BOTH:
694 s = GPIC_CFG_IC_EDGE_BOTH;
695 name = "bothedge";
696 hdl = handle_edge_irq;
697 break;
698 case IRQ_TYPE_NONE:
699 s = GPIC_CFG_IC_OFF;
700 name = "disabled";
701 hdl = handle_level_irq;
702 break;
703 default:
704 return -EINVAL;
705 }
706
707 __irq_set_chip_handler_name_locked(d->irq, &au1300_gpic, hdl, name);
708
709 au1300_gpic_chgcfg(d->irq - ALCHEMY_GPIC_INT_BASE, GPIC_CFG_IC_MASK, s);
710
711 return 0;
712}
713
714/******************************************************************************/
507 715
508static inline void ic_init(void __iomem *base) 716static inline void ic_init(void __iomem *base)
509{ 717{
@@ -521,13 +729,159 @@ static inline void ic_init(void __iomem *base)
521 wmb(); 729 wmb();
522} 730}
523 731
524static void __init au1000_init_irq(struct au1xxx_irqmap *map) 732static unsigned long alchemy_gpic_pmdata[ALCHEMY_GPIC_INT_NUM + 6];
733
734static inline void alchemy_ic_suspend_one(void __iomem *base, unsigned long *d)
735{
736 d[0] = __raw_readl(base + IC_CFG0RD);
737 d[1] = __raw_readl(base + IC_CFG1RD);
738 d[2] = __raw_readl(base + IC_CFG2RD);
739 d[3] = __raw_readl(base + IC_SRCRD);
740 d[4] = __raw_readl(base + IC_ASSIGNRD);
741 d[5] = __raw_readl(base + IC_WAKERD);
742 d[6] = __raw_readl(base + IC_MASKRD);
743 ic_init(base); /* shut it up too while at it */
744}
745
746static inline void alchemy_ic_resume_one(void __iomem *base, unsigned long *d)
747{
748 ic_init(base);
749
750 __raw_writel(d[0], base + IC_CFG0SET);
751 __raw_writel(d[1], base + IC_CFG1SET);
752 __raw_writel(d[2], base + IC_CFG2SET);
753 __raw_writel(d[3], base + IC_SRCSET);
754 __raw_writel(d[4], base + IC_ASSIGNSET);
755 __raw_writel(d[5], base + IC_WAKESET);
756 wmb();
757
758 __raw_writel(d[6], base + IC_MASKSET);
759 wmb();
760}
761
762static int alchemy_ic_suspend(void)
763{
764 alchemy_ic_suspend_one((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR),
765 alchemy_gpic_pmdata);
766 alchemy_ic_suspend_one((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR),
767 &alchemy_gpic_pmdata[7]);
768 return 0;
769}
770
771static void alchemy_ic_resume(void)
772{
773 alchemy_ic_resume_one((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR),
774 &alchemy_gpic_pmdata[7]);
775 alchemy_ic_resume_one((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR),
776 alchemy_gpic_pmdata);
777}
778
779static int alchemy_gpic_suspend(void)
780{
781 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR);
782 int i;
783
784 /* save 4 interrupt mask status registers */
785 alchemy_gpic_pmdata[0] = __raw_readl(base + AU1300_GPIC_IEN + 0x0);
786 alchemy_gpic_pmdata[1] = __raw_readl(base + AU1300_GPIC_IEN + 0x4);
787 alchemy_gpic_pmdata[2] = __raw_readl(base + AU1300_GPIC_IEN + 0x8);
788 alchemy_gpic_pmdata[3] = __raw_readl(base + AU1300_GPIC_IEN + 0xc);
789
790 /* save misc register(s) */
791 alchemy_gpic_pmdata[4] = __raw_readl(base + AU1300_GPIC_DMASEL);
792
793 /* molto silenzioso */
794 __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x0);
795 __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x4);
796 __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x8);
797 __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0xc);
798 wmb();
799
800 /* save pin/int-type configuration */
801 base += AU1300_GPIC_PINCFG;
802 for (i = 0; i < ALCHEMY_GPIC_INT_NUM; i++)
803 alchemy_gpic_pmdata[i + 5] = __raw_readl(base + (i << 2));
804
805 wmb();
806
807 return 0;
808}
809
810static void alchemy_gpic_resume(void)
811{
812 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR);
813 int i;
814
815 /* disable all first */
816 __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x0);
817 __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x4);
818 __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x8);
819 __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0xc);
820 wmb();
821
822 /* restore pin/int-type configurations */
823 base += AU1300_GPIC_PINCFG;
824 for (i = 0; i < ALCHEMY_GPIC_INT_NUM; i++)
825 __raw_writel(alchemy_gpic_pmdata[i + 5], base + (i << 2));
826 wmb();
827
828 /* restore misc register(s) */
829 base = (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR);
830 __raw_writel(alchemy_gpic_pmdata[4], base + AU1300_GPIC_DMASEL);
831 wmb();
832
833 /* finally restore masks */
834 __raw_writel(alchemy_gpic_pmdata[0], base + AU1300_GPIC_IEN + 0x0);
835 __raw_writel(alchemy_gpic_pmdata[1], base + AU1300_GPIC_IEN + 0x4);
836 __raw_writel(alchemy_gpic_pmdata[2], base + AU1300_GPIC_IEN + 0x8);
837 __raw_writel(alchemy_gpic_pmdata[3], base + AU1300_GPIC_IEN + 0xc);
838 wmb();
839}
840
841static struct syscore_ops alchemy_ic_pmops = {
842 .suspend = alchemy_ic_suspend,
843 .resume = alchemy_ic_resume,
844};
845
846static struct syscore_ops alchemy_gpic_pmops = {
847 .suspend = alchemy_gpic_suspend,
848 .resume = alchemy_gpic_resume,
849};
850
851/******************************************************************************/
852
853/* create chained handlers for the 4 IC requests to the MIPS IRQ ctrl */
854#define DISP(name, base, addr) \
855static void au1000_##name##_dispatch(unsigned int irq, struct irq_desc *d) \
856{ \
857 unsigned long r = __raw_readl((void __iomem *)KSEG1ADDR(addr)); \
858 if (likely(r)) \
859 generic_handle_irq(base + __ffs(r)); \
860 else \
861 spurious_interrupt(); \
862}
863
864DISP(ic0r0, AU1000_INTC0_INT_BASE, AU1000_IC0_PHYS_ADDR + IC_REQ0INT)
865DISP(ic0r1, AU1000_INTC0_INT_BASE, AU1000_IC0_PHYS_ADDR + IC_REQ1INT)
866DISP(ic1r0, AU1000_INTC1_INT_BASE, AU1000_IC1_PHYS_ADDR + IC_REQ0INT)
867DISP(ic1r1, AU1000_INTC1_INT_BASE, AU1000_IC1_PHYS_ADDR + IC_REQ1INT)
868
869static void alchemy_gpic_dispatch(unsigned int irq, struct irq_desc *d)
870{
871 int i = __raw_readl(AU1300_GPIC_ADDR + AU1300_GPIC_PRIENC);
872 generic_handle_irq(ALCHEMY_GPIC_INT_BASE + i);
873}
874
875/******************************************************************************/
876
877static void __init au1000_init_irq(struct alchemy_irqmap *map)
525{ 878{
526 unsigned int bit, irq_nr; 879 unsigned int bit, irq_nr;
527 void __iomem *base; 880 void __iomem *base;
528 881
529 ic_init((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR)); 882 ic_init((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR));
530 ic_init((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR)); 883 ic_init((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR));
884 register_syscore_ops(&alchemy_ic_pmops);
531 mips_cpu_irq_init(); 885 mips_cpu_irq_init();
532 886
533 /* register all 64 possible IC0+IC1 irq sources as type "none". 887 /* register all 64 possible IC0+IC1 irq sources as type "none".
@@ -544,8 +898,8 @@ static void __init au1000_init_irq(struct au1xxx_irqmap *map)
544 /* 898 /*
545 * Initialize IC0, which is fixed per processor. 899 * Initialize IC0, which is fixed per processor.
546 */ 900 */
547 while (map->im_irq != -1) { 901 while (map->irq != -1) {
548 irq_nr = map->im_irq; 902 irq_nr = map->irq;
549 903
550 if (irq_nr >= AU1000_INTC1_INT_BASE) { 904 if (irq_nr >= AU1000_INTC1_INT_BASE) {
551 bit = irq_nr - AU1000_INTC1_INT_BASE; 905 bit = irq_nr - AU1000_INTC1_INT_BASE;
@@ -554,16 +908,61 @@ static void __init au1000_init_irq(struct au1xxx_irqmap *map)
554 bit = irq_nr - AU1000_INTC0_INT_BASE; 908 bit = irq_nr - AU1000_INTC0_INT_BASE;
555 base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); 909 base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR);
556 } 910 }
557 if (map->im_request) 911 if (map->prio == 0)
558 __raw_writel(1 << bit, base + IC_ASSIGNSET); 912 __raw_writel(1 << bit, base + IC_ASSIGNSET);
559 913
560 au1x_ic_settype(irq_get_irq_data(irq_nr), map->im_type); 914 au1x_ic_settype(irq_get_irq_data(irq_nr), map->type);
561 ++map; 915 ++map;
562 } 916 }
563 917
564 set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3); 918 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 2, au1000_ic0r0_dispatch);
919 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 3, au1000_ic0r1_dispatch);
920 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 4, au1000_ic1r0_dispatch);
921 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 5, au1000_ic1r1_dispatch);
922}
923
924static void __init alchemy_gpic_init_irq(const struct alchemy_irqmap *dints)
925{
926 int i;
927 void __iomem *bank_base;
928
929 register_syscore_ops(&alchemy_gpic_pmops);
930 mips_cpu_irq_init();
931
932 /* disable & ack all possible interrupt sources */
933 for (i = 0; i < 4; i++) {
934 bank_base = AU1300_GPIC_ADDR + (i * 4);
935 __raw_writel(~0UL, bank_base + AU1300_GPIC_IDIS);
936 wmb();
937 __raw_writel(~0UL, bank_base + AU1300_GPIC_IPEND);
938 wmb();
939 }
940
941 /* register an irq_chip for them, with 2nd highest priority */
942 for (i = ALCHEMY_GPIC_INT_BASE; i <= ALCHEMY_GPIC_INT_LAST; i++) {
943 au1300_set_irq_priority(i, 1);
944 au1300_gpic_settype(irq_get_irq_data(i), IRQ_TYPE_NONE);
945 }
946
947 /* setup known on-chip sources */
948 while ((i = dints->irq) != -1) {
949 au1300_gpic_settype(irq_get_irq_data(i), dints->type);
950 au1300_set_irq_priority(i, dints->prio);
951
952 if (dints->internal)
953 au1300_pinfunc_to_dev(i - ALCHEMY_GPIC_INT_BASE);
954
955 dints++;
956 }
957
958 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 2, alchemy_gpic_dispatch);
959 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 3, alchemy_gpic_dispatch);
960 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 4, alchemy_gpic_dispatch);
961 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 5, alchemy_gpic_dispatch);
565} 962}
566 963
964/******************************************************************************/
965
567void __init arch_init_irq(void) 966void __init arch_init_irq(void)
568{ 967{
569 switch (alchemy_get_cputype()) { 968 switch (alchemy_get_cputype()) {
@@ -582,65 +981,17 @@ void __init arch_init_irq(void)
582 case ALCHEMY_CPU_AU1200: 981 case ALCHEMY_CPU_AU1200:
583 au1000_init_irq(au1200_irqmap); 982 au1000_init_irq(au1200_irqmap);
584 break; 983 break;
984 case ALCHEMY_CPU_AU1300:
985 alchemy_gpic_init_irq(au1300_irqmap);
986 break;
987 default:
988 pr_err("unknown Alchemy IRQ core\n");
989 break;
585 } 990 }
586} 991}
587 992
588 993asmlinkage void plat_irq_dispatch(void)
589static unsigned long alchemy_ic_pmdata[7 * 2];
590
591static inline void alchemy_ic_suspend_one(void __iomem *base, unsigned long *d)
592{
593 d[0] = __raw_readl(base + IC_CFG0RD);
594 d[1] = __raw_readl(base + IC_CFG1RD);
595 d[2] = __raw_readl(base + IC_CFG2RD);
596 d[3] = __raw_readl(base + IC_SRCRD);
597 d[4] = __raw_readl(base + IC_ASSIGNRD);
598 d[5] = __raw_readl(base + IC_WAKERD);
599 d[6] = __raw_readl(base + IC_MASKRD);
600 ic_init(base); /* shut it up too while at it */
601}
602
603static inline void alchemy_ic_resume_one(void __iomem *base, unsigned long *d)
604{
605 ic_init(base);
606
607 __raw_writel(d[0], base + IC_CFG0SET);
608 __raw_writel(d[1], base + IC_CFG1SET);
609 __raw_writel(d[2], base + IC_CFG2SET);
610 __raw_writel(d[3], base + IC_SRCSET);
611 __raw_writel(d[4], base + IC_ASSIGNSET);
612 __raw_writel(d[5], base + IC_WAKESET);
613 wmb();
614
615 __raw_writel(d[6], base + IC_MASKSET);
616 wmb();
617}
618
619static int alchemy_ic_suspend(void)
620{
621 alchemy_ic_suspend_one((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR),
622 alchemy_ic_pmdata);
623 alchemy_ic_suspend_one((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR),
624 &alchemy_ic_pmdata[7]);
625 return 0;
626}
627
628static void alchemy_ic_resume(void)
629{
630 alchemy_ic_resume_one((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR),
631 &alchemy_ic_pmdata[7]);
632 alchemy_ic_resume_one((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR),
633 alchemy_ic_pmdata);
634}
635
636static struct syscore_ops alchemy_ic_syscore_ops = {
637 .suspend = alchemy_ic_suspend,
638 .resume = alchemy_ic_resume,
639};
640
641static int __init alchemy_ic_pm_init(void)
642{ 994{
643 register_syscore_ops(&alchemy_ic_syscore_ops); 995 unsigned long r = (read_c0_status() & read_c0_cause()) >> 8;
644 return 0; 996 do_IRQ(MIPS_CPU_IRQ_BASE + __ffs(r & 0xff));
645} 997}
646device_initcall(alchemy_ic_pm_init);
diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c
index c8e5d72a5826..95cb9113b12c 100644
--- a/arch/mips/alchemy/common/platform.c
+++ b/arch/mips/alchemy/common/platform.c
@@ -82,6 +82,12 @@ static struct plat_serial8250_port au1x00_uart_data[][4] __initdata = {
82 PORT(AU1000_UART0_PHYS_ADDR, AU1200_UART0_INT), 82 PORT(AU1000_UART0_PHYS_ADDR, AU1200_UART0_INT),
83 PORT(AU1000_UART1_PHYS_ADDR, AU1200_UART1_INT), 83 PORT(AU1000_UART1_PHYS_ADDR, AU1200_UART1_INT),
84 }, 84 },
85 [ALCHEMY_CPU_AU1300] = {
86 PORT(AU1300_UART0_PHYS_ADDR, AU1300_UART0_INT),
87 PORT(AU1300_UART1_PHYS_ADDR, AU1300_UART1_INT),
88 PORT(AU1300_UART2_PHYS_ADDR, AU1300_UART2_INT),
89 PORT(AU1300_UART3_PHYS_ADDR, AU1300_UART3_INT),
90 },
85}; 91};
86 92
87static struct platform_device au1xx0_uart_device = { 93static struct platform_device au1xx0_uart_device = {
@@ -122,10 +128,12 @@ static unsigned long alchemy_ohci_data[][2] __initdata = {
122 [ALCHEMY_CPU_AU1100] = { AU1000_USB_OHCI_PHYS_ADDR, AU1100_USB_HOST_INT }, 128 [ALCHEMY_CPU_AU1100] = { AU1000_USB_OHCI_PHYS_ADDR, AU1100_USB_HOST_INT },
123 [ALCHEMY_CPU_AU1550] = { AU1550_USB_OHCI_PHYS_ADDR, AU1550_USB_HOST_INT }, 129 [ALCHEMY_CPU_AU1550] = { AU1550_USB_OHCI_PHYS_ADDR, AU1550_USB_HOST_INT },
124 [ALCHEMY_CPU_AU1200] = { AU1200_USB_OHCI_PHYS_ADDR, AU1200_USB_INT }, 130 [ALCHEMY_CPU_AU1200] = { AU1200_USB_OHCI_PHYS_ADDR, AU1200_USB_INT },
131 [ALCHEMY_CPU_AU1300] = { AU1300_USB_OHCI0_PHYS_ADDR, AU1300_USB_INT },
125}; 132};
126 133
127static unsigned long alchemy_ehci_data[][2] __initdata = { 134static unsigned long alchemy_ehci_data[][2] __initdata = {
128 [ALCHEMY_CPU_AU1200] = { AU1200_USB_EHCI_PHYS_ADDR, AU1200_USB_INT }, 135 [ALCHEMY_CPU_AU1200] = { AU1200_USB_EHCI_PHYS_ADDR, AU1200_USB_INT },
136 [ALCHEMY_CPU_AU1300] = { AU1300_USB_EHCI_PHYS_ADDR, AU1300_USB_INT },
129}; 137};
130 138
131static int __init _new_usbres(struct resource **r, struct platform_device **d) 139static int __init _new_usbres(struct resource **r, struct platform_device **d)
@@ -169,8 +177,8 @@ static void __init alchemy_setup_usb(int ctype)
169 printk(KERN_INFO "Alchemy USB: cannot add OHCI0\n"); 177 printk(KERN_INFO "Alchemy USB: cannot add OHCI0\n");
170 178
171 179
172 /* setup EHCI0: Au1200 */ 180 /* setup EHCI0: Au1200/Au1300 */
173 if (ctype == ALCHEMY_CPU_AU1200) { 181 if ((ctype == ALCHEMY_CPU_AU1200) || (ctype == ALCHEMY_CPU_AU1300)) {
174 if (_new_usbres(&res, &pdev)) 182 if (_new_usbres(&res, &pdev))
175 return; 183 return;
176 184
@@ -187,6 +195,25 @@ static void __init alchemy_setup_usb(int ctype)
187 if (platform_device_register(pdev)) 195 if (platform_device_register(pdev))
188 printk(KERN_INFO "Alchemy USB: cannot add EHCI0\n"); 196 printk(KERN_INFO "Alchemy USB: cannot add EHCI0\n");
189 } 197 }
198
199 /* Au1300: OHCI1 */
200 if (ctype == ALCHEMY_CPU_AU1300) {
201 if (_new_usbres(&res, &pdev))
202 return;
203
204 res[0].start = AU1300_USB_OHCI1_PHYS_ADDR;
205 res[0].end = res[0].start + 0x100 - 1;
206 res[0].flags = IORESOURCE_MEM;
207 res[1].start = AU1300_USB_INT;
208 res[1].end = res[1].start;
209 res[1].flags = IORESOURCE_IRQ;
210 pdev->name = "au1xxx-ohci";
211 pdev->id = 1;
212 pdev->dev.dma_mask = &alchemy_ohci_dmamask;
213
214 if (platform_device_register(pdev))
215 printk(KERN_INFO "Alchemy USB: cannot add OHCI1\n");
216 }
190} 217}
191 218
192/* Macro to help defining the Ethernet MAC resources */ 219/* Macro to help defining the Ethernet MAC resources */
diff --git a/arch/mips/alchemy/common/power.c b/arch/mips/alchemy/common/power.c
index bdd6651e9a4f..0c7fce2a3c12 100644
--- a/arch/mips/alchemy/common/power.c
+++ b/arch/mips/alchemy/common/power.c
@@ -126,6 +126,9 @@ void au_sleep(void)
126 case ALCHEMY_CPU_AU1200: 126 case ALCHEMY_CPU_AU1200:
127 alchemy_sleep_au1550(); 127 alchemy_sleep_au1550();
128 break; 128 break;
129 case ALCHEMY_CPU_AU1300:
130 alchemy_sleep_au1300();
131 break;
129 } 132 }
130 133
131 restore_core_regs(); 134 restore_core_regs();
diff --git a/arch/mips/alchemy/common/sleeper.S b/arch/mips/alchemy/common/sleeper.S
index 77f3c743b716..c7bcc7e5c822 100644
--- a/arch/mips/alchemy/common/sleeper.S
+++ b/arch/mips/alchemy/common/sleeper.S
@@ -153,6 +153,79 @@ LEAF(alchemy_sleep_au1550)
153 153
154END(alchemy_sleep_au1550) 154END(alchemy_sleep_au1550)
155 155
156/* sleepcode for Au1300 memory controller type */
157LEAF(alchemy_sleep_au1300)
158
159 SETUP_SLEEP
160
161 /* cache following instructions, as memory gets put to sleep */
162 la t0, 2f
163 la t1, 4f
164 subu t2, t1, t0
165
166 .set mips3
167
1681: cache 0x14, 0(t0)
169 subu t2, t2, 32
170 bgez t2, 1b
171 addu t0, t0, 32
172
173 .set mips0
174
1752: lui a0, 0xb400 /* mem_xxx */
176
177 /* disable all ports in mem_sdportcfga */
178 sw zero, 0x868(a0) /* mem_sdportcfga */
179 sync
180
181 /* disable ODT */
182 li t0, 0x03010000
183 sw t0, 0x08d8(a0) /* mem_sdcmd0 */
184 sw t0, 0x08dc(a0) /* mem_sdcmd1 */
185 sync
186
187 /* precharge */
188 li t0, 0x23000400
189 sw t0, 0x08dc(a0) /* mem_sdcmd1 */
190 sw t0, 0x08d8(a0) /* mem_sdcmd0 */
191 sync
192
193 /* auto refresh */
194 sw zero, 0x08c8(a0) /* mem_sdautoref */
195 sync
196
197 /* block access to the DDR */
198 lw t0, 0x0848(a0) /* mem_sdconfigb */
199 li t1, (1 << 7 | 0x3F)
200 or t0, t0, t1
201 sw t0, 0x0848(a0) /* mem_sdconfigb */
202 sync
203
204 /* issue the Self Refresh command */
205 li t0, 0x10000000
206 sw t0, 0x08dc(a0) /* mem_sdcmd1 */
207 sw t0, 0x08d8(a0) /* mem_sdcmd0 */
208 sync
209
210 /* wait for sdram to enter self-refresh mode */
211 lui t0, 0x0300
2123: lw t1, 0x0850(a0) /* mem_sdstat */
213 and t2, t1, t0
214 bne t2, t0, 3b
215 nop
216
217 /* disable SDRAM clocks */
218 li t0, ~(3<<28)
219 lw t1, 0x0840(a0) /* mem_sdconfiga */
220 and t1, t1, t0 /* clear CE[1:0] */
221 sw t1, 0x0840(a0) /* mem_sdconfiga */
222 sync
223
224 DO_SLEEP
2254:
226
227END(alchemy_sleep_au1300)
228
156 229
157 /* This is where we return upon wakeup. 230 /* This is where we return upon wakeup.
158 * Reload all of the registers and return. 231 * Reload all of the registers and return.
diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c
index d5da6adbf634..7da4d0081487 100644
--- a/arch/mips/alchemy/common/time.c
+++ b/arch/mips/alchemy/common/time.c
@@ -92,7 +92,7 @@ static struct clock_event_device au1x_rtcmatch2_clockdev = {
92 92
93static struct irqaction au1x_rtcmatch2_irqaction = { 93static struct irqaction au1x_rtcmatch2_irqaction = {
94 .handler = au1x_rtcmatch2_irq, 94 .handler = au1x_rtcmatch2_irq,
95 .flags = IRQF_DISABLED | IRQF_TIMER, 95 .flags = IRQF_TIMER,
96 .name = "timer", 96 .name = "timer",
97 .dev_id = &au1x_rtcmatch2_clockdev, 97 .dev_id = &au1x_rtcmatch2_clockdev,
98}; 98};
@@ -178,6 +178,7 @@ static int alchemy_m2inttab[] __initdata = {
178 AU1100_RTC_MATCH2_INT, 178 AU1100_RTC_MATCH2_INT,
179 AU1550_RTC_MATCH2_INT, 179 AU1550_RTC_MATCH2_INT,
180 AU1200_RTC_MATCH2_INT, 180 AU1200_RTC_MATCH2_INT,
181 AU1300_RTC_MATCH2_INT,
181}; 182};
182 183
183void __init plat_time_init(void) 184void __init plat_time_init(void)
diff --git a/arch/mips/alchemy/common/vss.c b/arch/mips/alchemy/common/vss.c
new file mode 100644
index 000000000000..d23b1444d365
--- /dev/null
+++ b/arch/mips/alchemy/common/vss.c
@@ -0,0 +1,84 @@
1/*
2 * Au1300 media block power gating (VSS)
3 *
4 * This is a stop-gap solution until I have the clock framework integration
5 * ready. This stuff here really must be handled transparently when clocks
6 * for various media blocks are enabled/disabled.
7 */
8
9#include <linux/module.h>
10#include <linux/spinlock.h>
11#include <asm/mach-au1x00/au1000.h>
12
13#define VSS_GATE 0x00 /* gate wait timers */
14#define VSS_CLKRST 0x04 /* clock/block control */
15#define VSS_FTR 0x08 /* footers */
16
17#define VSS_ADDR(blk) (KSEG1ADDR(AU1300_VSS_PHYS_ADDR) + (blk * 0x0c))
18
19static DEFINE_SPINLOCK(au1300_vss_lock);
20
21/* enable a block as outlined in the databook */
22static inline void __enable_block(int block)
23{
24 void __iomem *base = (void __iomem *)VSS_ADDR(block);
25
26 __raw_writel(3, base + VSS_CLKRST); /* enable clock, assert reset */
27 wmb();
28
29 __raw_writel(0x01fffffe, base + VSS_GATE); /* maximum setup time */
30 wmb();
31
32 /* enable footers in sequence */
33 __raw_writel(0x01, base + VSS_FTR);
34 wmb();
35 __raw_writel(0x03, base + VSS_FTR);
36 wmb();
37 __raw_writel(0x07, base + VSS_FTR);
38 wmb();
39 __raw_writel(0x0f, base + VSS_FTR);
40 wmb();
41
42 __raw_writel(0x01ffffff, base + VSS_GATE); /* start FSM too */
43 wmb();
44
45 __raw_writel(2, base + VSS_CLKRST); /* deassert reset */
46 wmb();
47
48 __raw_writel(0x1f, base + VSS_FTR); /* enable isolation cells */
49 wmb();
50}
51
52/* disable a block as outlined in the databook */
53static inline void __disable_block(int block)
54{
55 void __iomem *base = (void __iomem *)VSS_ADDR(block);
56
57 __raw_writel(0x0f, base + VSS_FTR); /* disable isolation cells */
58 wmb();
59 __raw_writel(0, base + VSS_GATE); /* disable FSM */
60 wmb();
61 __raw_writel(3, base + VSS_CLKRST); /* assert reset */
62 wmb();
63 __raw_writel(1, base + VSS_CLKRST); /* disable clock */
64 wmb();
65 __raw_writel(0, base + VSS_FTR); /* disable all footers */
66 wmb();
67}
68
69void au1300_vss_block_control(int block, int enable)
70{
71 unsigned long flags;
72
73 if (alchemy_get_cputype() != ALCHEMY_CPU_AU1300)
74 return;
75
76 /* only one block at a time */
77 spin_lock_irqsave(&au1300_vss_lock, flags);
78 if (enable)
79 __enable_block(block);
80 else
81 __disable_block(block);
82 spin_unlock_irqrestore(&au1300_vss_lock, flags);
83}
84EXPORT_SYMBOL_GPL(au1300_vss_block_control);
diff --git a/arch/mips/alchemy/devboards/Makefile b/arch/mips/alchemy/devboards/Makefile
index 826449c817c3..3c37fb303364 100644
--- a/arch/mips/alchemy/devboards/Makefile
+++ b/arch/mips/alchemy/devboards/Makefile
@@ -4,15 +4,10 @@
4 4
5obj-y += prom.o bcsr.o platform.o 5obj-y += prom.o bcsr.o platform.o
6obj-$(CONFIG_PM) += pm.o 6obj-$(CONFIG_PM) += pm.o
7obj-$(CONFIG_MIPS_PB1000) += pb1000/ 7obj-$(CONFIG_MIPS_PB1100) += pb1100.o
8obj-$(CONFIG_MIPS_PB1100) += pb1100/ 8obj-$(CONFIG_MIPS_PB1500) += pb1500.o
9obj-$(CONFIG_MIPS_PB1200) += pb1200/ 9obj-$(CONFIG_MIPS_PB1550) += pb1550.o
10obj-$(CONFIG_MIPS_PB1500) += pb1500/ 10obj-$(CONFIG_MIPS_DB1000) += db1000.o
11obj-$(CONFIG_MIPS_PB1550) += pb1550/ 11obj-$(CONFIG_MIPS_DB1200) += db1200.o
12obj-$(CONFIG_MIPS_DB1000) += db1x00/ 12obj-$(CONFIG_MIPS_DB1300) += db1300.o
13obj-$(CONFIG_MIPS_DB1100) += db1x00/ 13obj-$(CONFIG_MIPS_DB1550) += db1550.o
14obj-$(CONFIG_MIPS_DB1200) += db1200/
15obj-$(CONFIG_MIPS_DB1500) += db1x00/
16obj-$(CONFIG_MIPS_DB1550) += db1x00/
17obj-$(CONFIG_MIPS_BOSPORUS) += db1x00/
18obj-$(CONFIG_MIPS_MIRAGE) += db1x00/
diff --git a/arch/mips/alchemy/devboards/bcsr.c b/arch/mips/alchemy/devboards/bcsr.c
index 463d2c4d9441..1e83ce2e1147 100644
--- a/arch/mips/alchemy/devboards/bcsr.c
+++ b/arch/mips/alchemy/devboards/bcsr.c
@@ -97,14 +97,9 @@ static void bcsr_csc_handler(unsigned int irq, struct irq_desc *d)
97 enable_irq(irq); 97 enable_irq(irq);
98} 98}
99 99
100/* NOTE: both the enable and mask bits must be cleared, otherwise the
101 * CPLD generates tons of spurious interrupts (at least on my DB1200).
102 * -- mlau
103 */
104static void bcsr_irq_mask(struct irq_data *d) 100static void bcsr_irq_mask(struct irq_data *d)
105{ 101{
106 unsigned short v = 1 << (d->irq - bcsr_csc_base); 102 unsigned short v = 1 << (d->irq - bcsr_csc_base);
107 __raw_writew(v, bcsr_virt + BCSR_REG_INTCLR);
108 __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR); 103 __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR);
109 wmb(); 104 wmb();
110} 105}
@@ -112,7 +107,6 @@ static void bcsr_irq_mask(struct irq_data *d)
112static void bcsr_irq_maskack(struct irq_data *d) 107static void bcsr_irq_maskack(struct irq_data *d)
113{ 108{
114 unsigned short v = 1 << (d->irq - bcsr_csc_base); 109 unsigned short v = 1 << (d->irq - bcsr_csc_base);
115 __raw_writew(v, bcsr_virt + BCSR_REG_INTCLR);
116 __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR); 110 __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR);
117 __raw_writew(v, bcsr_virt + BCSR_REG_INTSTAT); /* ack */ 111 __raw_writew(v, bcsr_virt + BCSR_REG_INTSTAT); /* ack */
118 wmb(); 112 wmb();
@@ -121,7 +115,6 @@ static void bcsr_irq_maskack(struct irq_data *d)
121static void bcsr_irq_unmask(struct irq_data *d) 115static void bcsr_irq_unmask(struct irq_data *d)
122{ 116{
123 unsigned short v = 1 << (d->irq - bcsr_csc_base); 117 unsigned short v = 1 << (d->irq - bcsr_csc_base);
124 __raw_writew(v, bcsr_virt + BCSR_REG_INTSET);
125 __raw_writew(v, bcsr_virt + BCSR_REG_MASKSET); 118 __raw_writew(v, bcsr_virt + BCSR_REG_MASKSET);
126 wmb(); 119 wmb();
127} 120}
@@ -137,9 +130,9 @@ void __init bcsr_init_irq(int csc_start, int csc_end, int hook_irq)
137{ 130{
138 unsigned int irq; 131 unsigned int irq;
139 132
140 /* mask & disable & ack all */ 133 /* mask & enable & ack all */
141 __raw_writew(0xffff, bcsr_virt + BCSR_REG_INTCLR);
142 __raw_writew(0xffff, bcsr_virt + BCSR_REG_MASKCLR); 134 __raw_writew(0xffff, bcsr_virt + BCSR_REG_MASKCLR);
135 __raw_writew(0xffff, bcsr_virt + BCSR_REG_INTSET);
143 __raw_writew(0xffff, bcsr_virt + BCSR_REG_INTSTAT); 136 __raw_writew(0xffff, bcsr_virt + BCSR_REG_INTSTAT);
144 wmb(); 137 wmb();
145 138
diff --git a/arch/mips/alchemy/devboards/db1000.c b/arch/mips/alchemy/devboards/db1000.c
new file mode 100644
index 000000000000..1b81dbf6b804
--- /dev/null
+++ b/arch/mips/alchemy/devboards/db1000.c
@@ -0,0 +1,565 @@
1/*
2 * DBAu1000/1500/1100 board support
3 *
4 * Copyright 2000, 2008 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc. <source@mvista.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21
22#include <linux/dma-mapping.h>
23#include <linux/gpio.h>
24#include <linux/init.h>
25#include <linux/interrupt.h>
26#include <linux/leds.h>
27#include <linux/mmc/host.h>
28#include <linux/module.h>
29#include <linux/platform_device.h>
30#include <linux/pm.h>
31#include <linux/spi/spi.h>
32#include <linux/spi/spi_gpio.h>
33#include <linux/spi/ads7846.h>
34#include <asm/mach-au1x00/au1000.h>
35#include <asm/mach-au1x00/au1000_dma.h>
36#include <asm/mach-au1x00/au1100_mmc.h>
37#include <asm/mach-db1x00/bcsr.h>
38#include <asm/reboot.h>
39#include <prom.h>
40#include "platform.h"
41
42#define F_SWAPPED (bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT)
43
44struct pci_dev;
45
46static const char *board_type_str(void)
47{
48 switch (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) {
49 case BCSR_WHOAMI_DB1000:
50 return "DB1000";
51 case BCSR_WHOAMI_DB1500:
52 return "DB1500";
53 case BCSR_WHOAMI_DB1100:
54 return "DB1100";
55 default:
56 return "(unknown)";
57 }
58}
59
60const char *get_system_type(void)
61{
62 return board_type_str();
63}
64
65void __init board_setup(void)
66{
67 /* initialize board register space */
68 bcsr_init(DB1000_BCSR_PHYS_ADDR,
69 DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS);
70
71 printk(KERN_INFO "AMD Alchemy %s Board\n", board_type_str());
72}
73
74
75static int db1500_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
76{
77 if ((slot < 12) || (slot > 13) || pin == 0)
78 return -1;
79 if (slot == 12)
80 return (pin == 1) ? AU1500_PCI_INTA : 0xff;
81 if (slot == 13) {
82 switch (pin) {
83 case 1: return AU1500_PCI_INTA;
84 case 2: return AU1500_PCI_INTB;
85 case 3: return AU1500_PCI_INTC;
86 case 4: return AU1500_PCI_INTD;
87 }
88 }
89 return -1;
90}
91
92static struct resource alchemy_pci_host_res[] = {
93 [0] = {
94 .start = AU1500_PCI_PHYS_ADDR,
95 .end = AU1500_PCI_PHYS_ADDR + 0xfff,
96 .flags = IORESOURCE_MEM,
97 },
98};
99
100static struct alchemy_pci_platdata db1500_pci_pd = {
101 .board_map_irq = db1500_map_pci_irq,
102};
103
104static struct platform_device db1500_pci_host_dev = {
105 .dev.platform_data = &db1500_pci_pd,
106 .name = "alchemy-pci",
107 .id = 0,
108 .num_resources = ARRAY_SIZE(alchemy_pci_host_res),
109 .resource = alchemy_pci_host_res,
110};
111
112static int __init db1500_pci_init(void)
113{
114 if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1500)
115 return platform_device_register(&db1500_pci_host_dev);
116 return 0;
117}
118/* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */
119arch_initcall(db1500_pci_init);
120
121
122static struct resource au1100_lcd_resources[] = {
123 [0] = {
124 .start = AU1100_LCD_PHYS_ADDR,
125 .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1,
126 .flags = IORESOURCE_MEM,
127 },
128 [1] = {
129 .start = AU1100_LCD_INT,
130 .end = AU1100_LCD_INT,
131 .flags = IORESOURCE_IRQ,
132 }
133};
134
135static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32);
136
137static struct platform_device au1100_lcd_device = {
138 .name = "au1100-lcd",
139 .id = 0,
140 .dev = {
141 .dma_mask = &au1100_lcd_dmamask,
142 .coherent_dma_mask = DMA_BIT_MASK(32),
143 },
144 .num_resources = ARRAY_SIZE(au1100_lcd_resources),
145 .resource = au1100_lcd_resources,
146};
147
148static struct resource alchemy_ac97c_res[] = {
149 [0] = {
150 .start = AU1000_AC97_PHYS_ADDR,
151 .end = AU1000_AC97_PHYS_ADDR + 0xfff,
152 .flags = IORESOURCE_MEM,
153 },
154 [1] = {
155 .start = DMA_ID_AC97C_TX,
156 .end = DMA_ID_AC97C_TX,
157 .flags = IORESOURCE_DMA,
158 },
159 [2] = {
160 .start = DMA_ID_AC97C_RX,
161 .end = DMA_ID_AC97C_RX,
162 .flags = IORESOURCE_DMA,
163 },
164};
165
166static struct platform_device alchemy_ac97c_dev = {
167 .name = "alchemy-ac97c",
168 .id = -1,
169 .resource = alchemy_ac97c_res,
170 .num_resources = ARRAY_SIZE(alchemy_ac97c_res),
171};
172
173static struct platform_device alchemy_ac97c_dma_dev = {
174 .name = "alchemy-pcm-dma",
175 .id = 0,
176};
177
178static struct platform_device db1x00_codec_dev = {
179 .name = "ac97-codec",
180 .id = -1,
181};
182
183static struct platform_device db1x00_audio_dev = {
184 .name = "db1000-audio",
185};
186
187/******************************************************************************/
188
189static irqreturn_t db1100_mmc_cd(int irq, void *ptr)
190{
191 void (*mmc_cd)(struct mmc_host *, unsigned long);
192 /* link against CONFIG_MMC=m */
193 mmc_cd = symbol_get(mmc_detect_change);
194 mmc_cd(ptr, msecs_to_jiffies(500));
195 symbol_put(mmc_detect_change);
196
197 return IRQ_HANDLED;
198}
199
200static int db1100_mmc_cd_setup(void *mmc_host, int en)
201{
202 int ret = 0;
203
204 if (en) {
205 irq_set_irq_type(AU1100_GPIO19_INT, IRQ_TYPE_EDGE_BOTH);
206 ret = request_irq(AU1100_GPIO19_INT, db1100_mmc_cd, 0,
207 "sd0_cd", mmc_host);
208 } else
209 free_irq(AU1100_GPIO19_INT, mmc_host);
210 return ret;
211}
212
213static int db1100_mmc1_cd_setup(void *mmc_host, int en)
214{
215 int ret = 0;
216
217 if (en) {
218 irq_set_irq_type(AU1100_GPIO20_INT, IRQ_TYPE_EDGE_BOTH);
219 ret = request_irq(AU1100_GPIO20_INT, db1100_mmc_cd, 0,
220 "sd1_cd", mmc_host);
221 } else
222 free_irq(AU1100_GPIO20_INT, mmc_host);
223 return ret;
224}
225
226static int db1100_mmc_card_readonly(void *mmc_host)
227{
228 /* testing suggests that this bit is inverted */
229 return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 0 : 1;
230}
231
232static int db1100_mmc_card_inserted(void *mmc_host)
233{
234 return !alchemy_gpio_get_value(19);
235}
236
237static void db1100_mmc_set_power(void *mmc_host, int state)
238{
239 if (state) {
240 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD0PWR);
241 msleep(400); /* stabilization time */
242 } else
243 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD0PWR, 0);
244}
245
246static void db1100_mmcled_set(struct led_classdev *led, enum led_brightness b)
247{
248 if (b != LED_OFF)
249 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0);
250 else
251 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0);
252}
253
254static struct led_classdev db1100_mmc_led = {
255 .brightness_set = db1100_mmcled_set,
256};
257
258static int db1100_mmc1_card_readonly(void *mmc_host)
259{
260 return (bcsr_read(BCSR_BOARD) & BCSR_BOARD_SD1WP) ? 1 : 0;
261}
262
263static int db1100_mmc1_card_inserted(void *mmc_host)
264{
265 return !alchemy_gpio_get_value(20);
266}
267
268static void db1100_mmc1_set_power(void *mmc_host, int state)
269{
270 if (state) {
271 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD1PWR);
272 msleep(400); /* stabilization time */
273 } else
274 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD1PWR, 0);
275}
276
277static void db1100_mmc1led_set(struct led_classdev *led, enum led_brightness b)
278{
279 if (b != LED_OFF)
280 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0);
281 else
282 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1);
283}
284
285static struct led_classdev db1100_mmc1_led = {
286 .brightness_set = db1100_mmc1led_set,
287};
288
289static struct au1xmmc_platform_data db1100_mmc_platdata[2] = {
290 [0] = {
291 .cd_setup = db1100_mmc_cd_setup,
292 .set_power = db1100_mmc_set_power,
293 .card_inserted = db1100_mmc_card_inserted,
294 .card_readonly = db1100_mmc_card_readonly,
295 .led = &db1100_mmc_led,
296 },
297 [1] = {
298 .cd_setup = db1100_mmc1_cd_setup,
299 .set_power = db1100_mmc1_set_power,
300 .card_inserted = db1100_mmc1_card_inserted,
301 .card_readonly = db1100_mmc1_card_readonly,
302 .led = &db1100_mmc1_led,
303 },
304};
305
306static struct resource au1100_mmc0_resources[] = {
307 [0] = {
308 .start = AU1100_SD0_PHYS_ADDR,
309 .end = AU1100_SD0_PHYS_ADDR + 0xfff,
310 .flags = IORESOURCE_MEM,
311 },
312 [1] = {
313 .start = AU1100_SD_INT,
314 .end = AU1100_SD_INT,
315 .flags = IORESOURCE_IRQ,
316 },
317 [2] = {
318 .start = DMA_ID_SD0_TX,
319 .end = DMA_ID_SD0_TX,
320 .flags = IORESOURCE_DMA,
321 },
322 [3] = {
323 .start = DMA_ID_SD0_RX,
324 .end = DMA_ID_SD0_RX,
325 .flags = IORESOURCE_DMA,
326 }
327};
328
329static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32);
330
331static struct platform_device db1100_mmc0_dev = {
332 .name = "au1xxx-mmc",
333 .id = 0,
334 .dev = {
335 .dma_mask = &au1xxx_mmc_dmamask,
336 .coherent_dma_mask = DMA_BIT_MASK(32),
337 .platform_data = &db1100_mmc_platdata[0],
338 },
339 .num_resources = ARRAY_SIZE(au1100_mmc0_resources),
340 .resource = au1100_mmc0_resources,
341};
342
343static struct resource au1100_mmc1_res[] = {
344 [0] = {
345 .start = AU1100_SD1_PHYS_ADDR,
346 .end = AU1100_SD1_PHYS_ADDR + 0xfff,
347 .flags = IORESOURCE_MEM,
348 },
349 [1] = {
350 .start = AU1100_SD_INT,
351 .end = AU1100_SD_INT,
352 .flags = IORESOURCE_IRQ,
353 },
354 [2] = {
355 .start = DMA_ID_SD1_TX,
356 .end = DMA_ID_SD1_TX,
357 .flags = IORESOURCE_DMA,
358 },
359 [3] = {
360 .start = DMA_ID_SD1_RX,
361 .end = DMA_ID_SD1_RX,
362 .flags = IORESOURCE_DMA,
363 }
364};
365
366static struct platform_device db1100_mmc1_dev = {
367 .name = "au1xxx-mmc",
368 .id = 1,
369 .dev = {
370 .dma_mask = &au1xxx_mmc_dmamask,
371 .coherent_dma_mask = DMA_BIT_MASK(32),
372 .platform_data = &db1100_mmc_platdata[1],
373 },
374 .num_resources = ARRAY_SIZE(au1100_mmc1_res),
375 .resource = au1100_mmc1_res,
376};
377
378/******************************************************************************/
379
380static void db1000_irda_set_phy_mode(int mode)
381{
382 unsigned short mask = BCSR_RESETS_IRDA_MODE_MASK | BCSR_RESETS_FIR_SEL;
383
384 switch (mode) {
385 case AU1000_IRDA_PHY_MODE_OFF:
386 bcsr_mod(BCSR_RESETS, mask, BCSR_RESETS_IRDA_MODE_OFF);
387 break;
388 case AU1000_IRDA_PHY_MODE_SIR:
389 bcsr_mod(BCSR_RESETS, mask, BCSR_RESETS_IRDA_MODE_FULL);
390 break;
391 case AU1000_IRDA_PHY_MODE_FIR:
392 bcsr_mod(BCSR_RESETS, mask, BCSR_RESETS_IRDA_MODE_FULL |
393 BCSR_RESETS_FIR_SEL);
394 break;
395 }
396}
397
398static struct au1k_irda_platform_data db1000_irda_platdata = {
399 .set_phy_mode = db1000_irda_set_phy_mode,
400};
401
402static struct resource au1000_irda_res[] = {
403 [0] = {
404 .start = AU1000_IRDA_PHYS_ADDR,
405 .end = AU1000_IRDA_PHYS_ADDR + 0x0fff,
406 .flags = IORESOURCE_MEM,
407 },
408 [1] = {
409 .start = AU1000_IRDA_TX_INT,
410 .end = AU1000_IRDA_TX_INT,
411 .flags = IORESOURCE_IRQ,
412 },
413 [2] = {
414 .start = AU1000_IRDA_RX_INT,
415 .end = AU1000_IRDA_RX_INT,
416 .flags = IORESOURCE_IRQ,
417 },
418};
419
420static struct platform_device db1000_irda_dev = {
421 .name = "au1000-irda",
422 .id = -1,
423 .dev = {
424 .platform_data = &db1000_irda_platdata,
425 },
426 .resource = au1000_irda_res,
427 .num_resources = ARRAY_SIZE(au1000_irda_res),
428};
429
430/******************************************************************************/
431
432static struct ads7846_platform_data db1100_touch_pd = {
433 .model = 7846,
434 .vref_mv = 3300,
435 .gpio_pendown = 21,
436};
437
438static struct spi_gpio_platform_data db1100_spictl_pd = {
439 .sck = 209,
440 .mosi = 208,
441 .miso = 207,
442 .num_chipselect = 1,
443};
444
445static struct spi_board_info db1100_spi_info[] __initdata = {
446 [0] = {
447 .modalias = "ads7846",
448 .max_speed_hz = 3250000,
449 .bus_num = 0,
450 .chip_select = 0,
451 .mode = 0,
452 .irq = AU1100_GPIO21_INT,
453 .platform_data = &db1100_touch_pd,
454 .controller_data = (void *)210, /* for spi_gpio: CS# GPIO210 */
455 },
456};
457
458static struct platform_device db1100_spi_dev = {
459 .name = "spi_gpio",
460 .id = 0,
461 .dev = {
462 .platform_data = &db1100_spictl_pd,
463 },
464};
465
466
467static struct platform_device *db1x00_devs[] = {
468 &db1x00_codec_dev,
469 &alchemy_ac97c_dma_dev,
470 &alchemy_ac97c_dev,
471 &db1x00_audio_dev,
472};
473
474static struct platform_device *db1000_devs[] = {
475 &db1000_irda_dev,
476};
477
478static struct platform_device *db1100_devs[] = {
479 &au1100_lcd_device,
480 &db1100_mmc0_dev,
481 &db1100_mmc1_dev,
482 &db1000_irda_dev,
483 &db1100_spi_dev,
484};
485
486static int __init db1000_dev_init(void)
487{
488 int board = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
489 int c0, c1, d0, d1, s0, s1;
490 unsigned long pfc;
491
492 if (board == BCSR_WHOAMI_DB1500) {
493 c0 = AU1500_GPIO2_INT;
494 c1 = AU1500_GPIO5_INT;
495 d0 = AU1500_GPIO0_INT;
496 d1 = AU1500_GPIO3_INT;
497 s0 = AU1500_GPIO1_INT;
498 s1 = AU1500_GPIO4_INT;
499 } else if (board == BCSR_WHOAMI_DB1100) {
500 c0 = AU1100_GPIO2_INT;
501 c1 = AU1100_GPIO5_INT;
502 d0 = AU1100_GPIO0_INT;
503 d1 = AU1100_GPIO3_INT;
504 s0 = AU1100_GPIO1_INT;
505 s1 = AU1100_GPIO4_INT;
506
507 gpio_direction_input(19); /* sd0 cd# */
508 gpio_direction_input(20); /* sd1 cd# */
509 gpio_direction_input(21); /* touch pendown# */
510 gpio_direction_input(207); /* SPI MISO */
511 gpio_direction_output(208, 0); /* SPI MOSI */
512 gpio_direction_output(209, 1); /* SPI SCK */
513 gpio_direction_output(210, 1); /* SPI CS# */
514
515 /* spi_gpio on SSI0 pins */
516 pfc = __raw_readl((void __iomem *)SYS_PINFUNC);
517 pfc |= (1 << 0); /* SSI0 pins as GPIOs */
518 __raw_writel(pfc, (void __iomem *)SYS_PINFUNC);
519 wmb();
520
521 spi_register_board_info(db1100_spi_info,
522 ARRAY_SIZE(db1100_spi_info));
523
524 platform_add_devices(db1100_devs, ARRAY_SIZE(db1100_devs));
525 } else if (board == BCSR_WHOAMI_DB1000) {
526 c0 = AU1000_GPIO2_INT;
527 c1 = AU1000_GPIO5_INT;
528 d0 = AU1000_GPIO0_INT;
529 d1 = AU1000_GPIO3_INT;
530 s0 = AU1000_GPIO1_INT;
531 s1 = AU1000_GPIO4_INT;
532 platform_add_devices(db1000_devs, ARRAY_SIZE(db1000_devs));
533 } else
534 return 0; /* unknown board, no further dev setup to do */
535
536 irq_set_irq_type(d0, IRQ_TYPE_EDGE_BOTH);
537 irq_set_irq_type(d1, IRQ_TYPE_EDGE_BOTH);
538 irq_set_irq_type(c0, IRQ_TYPE_LEVEL_LOW);
539 irq_set_irq_type(c1, IRQ_TYPE_LEVEL_LOW);
540 irq_set_irq_type(s0, IRQ_TYPE_LEVEL_LOW);
541 irq_set_irq_type(s1, IRQ_TYPE_LEVEL_LOW);
542
543 db1x_register_pcmcia_socket(
544 AU1000_PCMCIA_ATTR_PHYS_ADDR,
545 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
546 AU1000_PCMCIA_MEM_PHYS_ADDR,
547 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
548 AU1000_PCMCIA_IO_PHYS_ADDR,
549 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
550 c0, d0, /*s0*/0, 0, 0);
551
552 db1x_register_pcmcia_socket(
553 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
554 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
555 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000,
556 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
557 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000,
558 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
559 c1, d1, /*s1*/0, 0, 1);
560
561 platform_add_devices(db1x00_devs, ARRAY_SIZE(db1x00_devs));
562 db1x_register_norflash(32 << 20, 4 /* 32bit */, F_SWAPPED);
563 return 0;
564}
565device_initcall(db1000_dev_init);
diff --git a/arch/mips/alchemy/devboards/db1200/platform.c b/arch/mips/alchemy/devboards/db1200.c
index c61867c93c4a..a83302b96c01 100644
--- a/arch/mips/alchemy/devboards/db1200/platform.c
+++ b/arch/mips/alchemy/devboards/db1200.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * DBAu1200 board platform device registration 2 * DBAu1200/PBAu1200 board platform device registration
3 * 3 *
4 * Copyright (C) 2008-2009 Manuel Lauss 4 * Copyright (C) 2008-2011 Manuel Lauss
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by 7 * it under the terms of the GNU General Public License as published by
@@ -22,6 +22,7 @@
22#include <linux/gpio.h> 22#include <linux/gpio.h>
23#include <linux/i2c.h> 23#include <linux/i2c.h>
24#include <linux/init.h> 24#include <linux/init.h>
25#include <linux/interrupt.h>
25#include <linux/io.h> 26#include <linux/io.h>
26#include <linux/leds.h> 27#include <linux/leds.h>
27#include <linux/mmc/host.h> 28#include <linux/mmc/host.h>
@@ -33,18 +34,116 @@
33#include <linux/spi/spi.h> 34#include <linux/spi/spi.h>
34#include <linux/spi/flash.h> 35#include <linux/spi/flash.h>
35#include <linux/smc91x.h> 36#include <linux/smc91x.h>
36 37#include <asm/mach-au1x00/au1000.h>
37#include <asm/mach-au1x00/au1100_mmc.h> 38#include <asm/mach-au1x00/au1100_mmc.h>
38#include <asm/mach-au1x00/au1xxx_dbdma.h> 39#include <asm/mach-au1x00/au1xxx_dbdma.h>
40#include <asm/mach-au1x00/au1200fb.h>
39#include <asm/mach-au1x00/au1550_spi.h> 41#include <asm/mach-au1x00/au1550_spi.h>
40#include <asm/mach-db1x00/bcsr.h> 42#include <asm/mach-db1x00/bcsr.h>
41#include <asm/mach-db1x00/db1200.h> 43#include <asm/mach-db1x00/db1200.h>
42 44
43#include "../platform.h" 45#include "platform.h"
46
47static const char *board_type_str(void)
48{
49 switch (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) {
50 case BCSR_WHOAMI_PB1200_DDR1:
51 case BCSR_WHOAMI_PB1200_DDR2:
52 return "PB1200";
53 case BCSR_WHOAMI_DB1200:
54 return "DB1200";
55 default:
56 return "(unknown)";
57 }
58}
59
60const char *get_system_type(void)
61{
62 return board_type_str();
63}
64
65static int __init detect_board(void)
66{
67 int bid;
68
69 /* try the DB1200 first */
70 bcsr_init(DB1200_BCSR_PHYS_ADDR,
71 DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);
72 if (BCSR_WHOAMI_DB1200 == BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) {
73 unsigned short t = bcsr_read(BCSR_HEXLEDS);
74 bcsr_write(BCSR_HEXLEDS, ~t);
75 if (bcsr_read(BCSR_HEXLEDS) != t) {
76 bcsr_write(BCSR_HEXLEDS, t);
77 return 0;
78 }
79 }
80
81 /* okay, try the PB1200 then */
82 bcsr_init(PB1200_BCSR_PHYS_ADDR,
83 PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS);
84 bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
85 if ((bid == BCSR_WHOAMI_PB1200_DDR1) ||
86 (bid == BCSR_WHOAMI_PB1200_DDR2)) {
87 unsigned short t = bcsr_read(BCSR_HEXLEDS);
88 bcsr_write(BCSR_HEXLEDS, ~t);
89 if (bcsr_read(BCSR_HEXLEDS) != t) {
90 bcsr_write(BCSR_HEXLEDS, t);
91 return 0;
92 }
93 }
94
95 return 1; /* it's neither */
96}
97
98void __init board_setup(void)
99{
100 unsigned long freq0, clksrc, div, pfc;
101 unsigned short whoami;
102
103 if (detect_board()) {
104 printk(KERN_ERR "NOT running on a DB1200/PB1200 board!\n");
105 return;
106 }
107
108 whoami = bcsr_read(BCSR_WHOAMI);
109 printk(KERN_INFO "Alchemy/AMD/RMI %s Board, CPLD Rev %d"
110 " Board-ID %d Daughtercard ID %d\n", board_type_str(),
111 (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
112
113 /* SMBus/SPI on PSC0, Audio on PSC1 */
114 pfc = __raw_readl((void __iomem *)SYS_PINFUNC);
115 pfc &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B);
116 pfc &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B | SYS_PINFUNC_FS3);
117 pfc |= SYS_PINFUNC_P1C; /* SPI is configured later */
118 __raw_writel(pfc, (void __iomem *)SYS_PINFUNC);
119 wmb();
120
121 /* Clock configurations: PSC0: ~50MHz via Clkgen0, derived from
122 * CPU clock; all other clock generators off/unused.
123 */
124 div = (get_au1x00_speed() + 25000000) / 50000000;
125 if (div & 1)
126 div++;
127 div = ((div >> 1) - 1) & 0xff;
128
129 freq0 = div << SYS_FC_FRDIV0_BIT;
130 __raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0);
131 wmb();
132 freq0 |= SYS_FC_FE0; /* enable F0 */
133 __raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0);
134 wmb();
135
136 /* psc0_intclk comes 1:1 from F0 */
137 clksrc = SYS_CS_MUX_FQ0 << SYS_CS_ME0_BIT;
138 __raw_writel(clksrc, (void __iomem *)SYS_CLKSRC);
139 wmb();
140}
141
142/******************************************************************************/
44 143
45static struct mtd_partition db1200_spiflash_parts[] = { 144static struct mtd_partition db1200_spiflash_parts[] = {
46 { 145 {
47 .name = "DB1200 SPI flash", 146 .name = "spi_flash",
48 .offset = 0, 147 .offset = 0,
49 .size = MTDPART_SIZ_FULL, 148 .size = MTDPART_SIZ_FULL,
50 }, 149 },
@@ -78,18 +177,9 @@ static struct spi_board_info db1200_spi_devs[] __initdata = {
78}; 177};
79 178
80static struct i2c_board_info db1200_i2c_devs[] __initdata = { 179static struct i2c_board_info db1200_i2c_devs[] __initdata = {
81 { 180 { I2C_BOARD_INFO("24c04", 0x52), }, /* AT24C04-10 I2C eeprom */
82 /* AT24C04-10 I2C eeprom */ 181 { I2C_BOARD_INFO("ne1619", 0x2d), }, /* adm1025-compat hwmon */
83 I2C_BOARD_INFO("24c04", 0x52), 182 { I2C_BOARD_INFO("wm8731", 0x1b), }, /* I2S audio codec WM8731 */
84 },
85 {
86 /* Philips NE1619 temp/voltage sensor (adm1025 drv) */
87 I2C_BOARD_INFO("ne1619", 0x2d),
88 },
89 {
90 /* I2S audio codec WM8731 */
91 I2C_BOARD_INFO("wm8731", 0x1b),
92 },
93}; 183};
94 184
95/**********************************************************************/ 185/**********************************************************************/
@@ -206,7 +296,7 @@ static struct platform_device db1200_eth_dev = {
206static struct resource db1200_ide_res[] = { 296static struct resource db1200_ide_res[] = {
207 [0] = { 297 [0] = {
208 .start = DB1200_IDE_PHYS_ADDR, 298 .start = DB1200_IDE_PHYS_ADDR,
209 .end = DB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1, 299 .end = DB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1,
210 .flags = IORESOURCE_MEM, 300 .flags = IORESOURCE_MEM,
211 }, 301 },
212 [1] = { 302 [1] = {
@@ -221,13 +311,13 @@ static struct resource db1200_ide_res[] = {
221 }, 311 },
222}; 312};
223 313
224static u64 ide_dmamask = DMA_BIT_MASK(32); 314static u64 au1200_ide_dmamask = DMA_BIT_MASK(32);
225 315
226static struct platform_device db1200_ide_dev = { 316static struct platform_device db1200_ide_dev = {
227 .name = "au1200-ide", 317 .name = "au1200-ide",
228 .id = 0, 318 .id = 0,
229 .dev = { 319 .dev = {
230 .dma_mask = &ide_dmamask, 320 .dma_mask = &au1200_ide_dmamask,
231 .coherent_dma_mask = DMA_BIT_MASK(32), 321 .coherent_dma_mask = DMA_BIT_MASK(32),
232 }, 322 },
233 .num_resources = ARRAY_SIZE(db1200_ide_res), 323 .num_resources = ARRAY_SIZE(db1200_ide_res),
@@ -236,13 +326,6 @@ static struct platform_device db1200_ide_dev = {
236 326
237/**********************************************************************/ 327/**********************************************************************/
238 328
239static struct platform_device db1200_rtc_dev = {
240 .name = "rtc-au1xxx",
241 .id = -1,
242};
243
244/**********************************************************************/
245
246/* SD carddetects: they're supposed to be edge-triggered, but ack 329/* SD carddetects: they're supposed to be edge-triggered, but ack
247 * doesn't seem to work (CPLD Rev 2). Instead, the screaming one 330 * doesn't seem to work (CPLD Rev 2). Instead, the screaming one
248 * is disabled and its counterpart enabled. The 500ms timeout is 331 * is disabled and its counterpart enabled. The 500ms timeout is
@@ -276,12 +359,12 @@ static int db1200_mmc_cd_setup(void *mmc_host, int en)
276 359
277 if (en) { 360 if (en) {
278 ret = request_irq(DB1200_SD0_INSERT_INT, db1200_mmc_cd, 361 ret = request_irq(DB1200_SD0_INSERT_INT, db1200_mmc_cd,
279 IRQF_DISABLED, "sd_insert", mmc_host); 362 0, "sd_insert", mmc_host);
280 if (ret) 363 if (ret)
281 goto out; 364 goto out;
282 365
283 ret = request_irq(DB1200_SD0_EJECT_INT, db1200_mmc_cd, 366 ret = request_irq(DB1200_SD0_EJECT_INT, db1200_mmc_cd,
284 IRQF_DISABLED, "sd_eject", mmc_host); 367 0, "sd_eject", mmc_host);
285 if (ret) { 368 if (ret) {
286 free_irq(DB1200_SD0_INSERT_INT, mmc_host); 369 free_irq(DB1200_SD0_INSERT_INT, mmc_host);
287 goto out; 370 goto out;
@@ -333,12 +416,109 @@ static struct led_classdev db1200_mmc_led = {
333 .brightness_set = db1200_mmcled_set, 416 .brightness_set = db1200_mmcled_set,
334}; 417};
335 418
336static struct au1xmmc_platform_data db1200mmc_platdata = { 419/* -- */
337 .cd_setup = db1200_mmc_cd_setup, 420
338 .set_power = db1200_mmc_set_power, 421static irqreturn_t pb1200_mmc1_cd(int irq, void *ptr)
339 .card_inserted = db1200_mmc_card_inserted, 422{
340 .card_readonly = db1200_mmc_card_readonly, 423 void(*mmc_cd)(struct mmc_host *, unsigned long);
341 .led = &db1200_mmc_led, 424
425 if (irq == PB1200_SD1_INSERT_INT) {
426 disable_irq_nosync(PB1200_SD1_INSERT_INT);
427 enable_irq(PB1200_SD1_EJECT_INT);
428 } else {
429 disable_irq_nosync(PB1200_SD1_EJECT_INT);
430 enable_irq(PB1200_SD1_INSERT_INT);
431 }
432
433 /* link against CONFIG_MMC=m */
434 mmc_cd = symbol_get(mmc_detect_change);
435 if (mmc_cd) {
436 mmc_cd(ptr, msecs_to_jiffies(500));
437 symbol_put(mmc_detect_change);
438 }
439
440 return IRQ_HANDLED;
441}
442
443static int pb1200_mmc1_cd_setup(void *mmc_host, int en)
444{
445 int ret;
446
447 if (en) {
448 ret = request_irq(PB1200_SD1_INSERT_INT, pb1200_mmc1_cd, 0,
449 "sd1_insert", mmc_host);
450 if (ret)
451 goto out;
452
453 ret = request_irq(PB1200_SD1_EJECT_INT, pb1200_mmc1_cd, 0,
454 "sd1_eject", mmc_host);
455 if (ret) {
456 free_irq(PB1200_SD1_INSERT_INT, mmc_host);
457 goto out;
458 }
459
460 if (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT)
461 enable_irq(PB1200_SD1_EJECT_INT);
462 else
463 enable_irq(PB1200_SD1_INSERT_INT);
464
465 } else {
466 free_irq(PB1200_SD1_INSERT_INT, mmc_host);
467 free_irq(PB1200_SD1_EJECT_INT, mmc_host);
468 }
469 ret = 0;
470out:
471 return ret;
472}
473
474static void pb1200_mmc1led_set(struct led_classdev *led,
475 enum led_brightness brightness)
476{
477 if (brightness != LED_OFF)
478 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0);
479 else
480 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1);
481}
482
483static struct led_classdev pb1200_mmc1_led = {
484 .brightness_set = pb1200_mmc1led_set,
485};
486
487static void pb1200_mmc1_set_power(void *mmc_host, int state)
488{
489 if (state) {
490 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD1PWR);
491 msleep(400); /* stabilization time */
492 } else
493 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD1PWR, 0);
494}
495
496static int pb1200_mmc1_card_readonly(void *mmc_host)
497{
498 return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD1WP) ? 1 : 0;
499}
500
501static int pb1200_mmc1_card_inserted(void *mmc_host)
502{
503 return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0;
504}
505
506
507static struct au1xmmc_platform_data db1200_mmc_platdata[2] = {
508 [0] = {
509 .cd_setup = db1200_mmc_cd_setup,
510 .set_power = db1200_mmc_set_power,
511 .card_inserted = db1200_mmc_card_inserted,
512 .card_readonly = db1200_mmc_card_readonly,
513 .led = &db1200_mmc_led,
514 },
515 [1] = {
516 .cd_setup = pb1200_mmc1_cd_setup,
517 .set_power = pb1200_mmc1_set_power,
518 .card_inserted = pb1200_mmc1_card_inserted,
519 .card_readonly = pb1200_mmc1_card_readonly,
520 .led = &pb1200_mmc1_led,
521 },
342}; 522};
343 523
344static struct resource au1200_mmc0_resources[] = { 524static struct resource au1200_mmc0_resources[] = {
@@ -372,14 +552,76 @@ static struct platform_device db1200_mmc0_dev = {
372 .dev = { 552 .dev = {
373 .dma_mask = &au1xxx_mmc_dmamask, 553 .dma_mask = &au1xxx_mmc_dmamask,
374 .coherent_dma_mask = DMA_BIT_MASK(32), 554 .coherent_dma_mask = DMA_BIT_MASK(32),
375 .platform_data = &db1200mmc_platdata, 555 .platform_data = &db1200_mmc_platdata[0],
376 }, 556 },
377 .num_resources = ARRAY_SIZE(au1200_mmc0_resources), 557 .num_resources = ARRAY_SIZE(au1200_mmc0_resources),
378 .resource = au1200_mmc0_resources, 558 .resource = au1200_mmc0_resources,
379}; 559};
380 560
561static struct resource au1200_mmc1_res[] = {
562 [0] = {
563 .start = AU1100_SD1_PHYS_ADDR,
564 .end = AU1100_SD1_PHYS_ADDR + 0xfff,
565 .flags = IORESOURCE_MEM,
566 },
567 [1] = {
568 .start = AU1200_SD_INT,
569 .end = AU1200_SD_INT,
570 .flags = IORESOURCE_IRQ,
571 },
572 [2] = {
573 .start = AU1200_DSCR_CMD0_SDMS_TX1,
574 .end = AU1200_DSCR_CMD0_SDMS_TX1,
575 .flags = IORESOURCE_DMA,
576 },
577 [3] = {
578 .start = AU1200_DSCR_CMD0_SDMS_RX1,
579 .end = AU1200_DSCR_CMD0_SDMS_RX1,
580 .flags = IORESOURCE_DMA,
581 }
582};
583
584static struct platform_device pb1200_mmc1_dev = {
585 .name = "au1xxx-mmc",
586 .id = 1,
587 .dev = {
588 .dma_mask = &au1xxx_mmc_dmamask,
589 .coherent_dma_mask = DMA_BIT_MASK(32),
590 .platform_data = &db1200_mmc_platdata[1],
591 },
592 .num_resources = ARRAY_SIZE(au1200_mmc1_res),
593 .resource = au1200_mmc1_res,
594};
595
381/**********************************************************************/ 596/**********************************************************************/
382 597
598static int db1200fb_panel_index(void)
599{
600 return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f;
601}
602
603static int db1200fb_panel_init(void)
604{
605 /* Apply power */
606 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
607 BCSR_BOARD_LCDBL);
608 return 0;
609}
610
611static int db1200fb_panel_shutdown(void)
612{
613 /* Remove power */
614 bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
615 BCSR_BOARD_LCDBL, 0);
616 return 0;
617}
618
619static struct au1200fb_platdata db1200fb_pd = {
620 .panel_index = db1200fb_panel_index,
621 .panel_init = db1200fb_panel_init,
622 .panel_shutdown = db1200fb_panel_shutdown,
623};
624
383static struct resource au1200_lcd_res[] = { 625static struct resource au1200_lcd_res[] = {
384 [0] = { 626 [0] = {
385 .start = AU1200_LCD_PHYS_ADDR, 627 .start = AU1200_LCD_PHYS_ADDR,
@@ -401,6 +643,7 @@ static struct platform_device au1200_lcd_dev = {
401 .dev = { 643 .dev = {
402 .dma_mask = &au1200_lcd_dmamask, 644 .dma_mask = &au1200_lcd_dmamask,
403 .coherent_dma_mask = DMA_BIT_MASK(32), 645 .coherent_dma_mask = DMA_BIT_MASK(32),
646 .platform_data = &db1200fb_pd,
404 }, 647 },
405 .num_resources = ARRAY_SIZE(au1200_lcd_res), 648 .num_resources = ARRAY_SIZE(au1200_lcd_res),
406 .resource = au1200_lcd_res, 649 .resource = au1200_lcd_res,
@@ -519,7 +762,6 @@ static struct platform_device *db1200_devs[] __initdata = {
519 &db1200_mmc0_dev, 762 &db1200_mmc0_dev,
520 &au1200_lcd_dev, 763 &au1200_lcd_dev,
521 &db1200_eth_dev, 764 &db1200_eth_dev,
522 &db1200_rtc_dev,
523 &db1200_nand_dev, 765 &db1200_nand_dev,
524 &db1200_audiodma_dev, 766 &db1200_audiodma_dev,
525 &db1200_audio_dev, 767 &db1200_audio_dev,
@@ -527,11 +769,62 @@ static struct platform_device *db1200_devs[] __initdata = {
527 &db1200_sound_dev, 769 &db1200_sound_dev,
528}; 770};
529 771
772static struct platform_device *pb1200_devs[] __initdata = {
773 &pb1200_mmc1_dev,
774};
775
776/* Some peripheral base addresses differ on the PB1200 */
777static int __init pb1200_res_fixup(void)
778{
779 /* CPLD Revs earlier than 4 cause problems */
780 if (BCSR_WHOAMI_CPLD(bcsr_read(BCSR_WHOAMI)) <= 3) {
781 printk(KERN_ERR "WARNING!!!\n");
782 printk(KERN_ERR "WARNING!!!\n");
783 printk(KERN_ERR "PB1200 must be at CPLD rev 4. Please have\n");
784 printk(KERN_ERR "the board updated to latest revisions.\n");
785 printk(KERN_ERR "This software will not work reliably\n");
786 printk(KERN_ERR "on anything older than CPLD rev 4.!\n");
787 printk(KERN_ERR "WARNING!!!\n");
788 printk(KERN_ERR "WARNING!!!\n");
789 return 1;
790 }
791
792 db1200_nand_res[0].start = PB1200_NAND_PHYS_ADDR;
793 db1200_nand_res[0].end = PB1200_NAND_PHYS_ADDR + 0xff;
794 db1200_ide_res[0].start = PB1200_IDE_PHYS_ADDR;
795 db1200_ide_res[0].end = PB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1;
796 db1200_eth_res[0].start = PB1200_ETH_PHYS_ADDR;
797 db1200_eth_res[0].end = PB1200_ETH_PHYS_ADDR + 0xff;
798 return 0;
799}
800
530static int __init db1200_dev_init(void) 801static int __init db1200_dev_init(void)
531{ 802{
532 unsigned long pfc; 803 unsigned long pfc;
533 unsigned short sw; 804 unsigned short sw;
534 int swapped; 805 int swapped, bid;
806
807 bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
808 if ((bid == BCSR_WHOAMI_PB1200_DDR1) ||
809 (bid == BCSR_WHOAMI_PB1200_DDR2)) {
810 if (pb1200_res_fixup())
811 return -ENODEV;
812 }
813
814 /* GPIO7 is low-level triggered CPLD cascade */
815 irq_set_irq_type(AU1200_GPIO7_INT, IRQ_TYPE_LEVEL_LOW);
816 bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT);
817
818 /* insert/eject pairs: one of both is always screaming. To avoid
819 * issues they must not be automatically enabled when initially
820 * requested.
821 */
822 irq_set_status_flags(DB1200_SD0_INSERT_INT, IRQ_NOAUTOEN);
823 irq_set_status_flags(DB1200_SD0_EJECT_INT, IRQ_NOAUTOEN);
824 irq_set_status_flags(DB1200_PC0_INSERT_INT, IRQ_NOAUTOEN);
825 irq_set_status_flags(DB1200_PC0_EJECT_INT, IRQ_NOAUTOEN);
826 irq_set_status_flags(DB1200_PC1_INSERT_INT, IRQ_NOAUTOEN);
827 irq_set_status_flags(DB1200_PC1_EJECT_INT, IRQ_NOAUTOEN);
535 828
536 i2c_register_board_info(0, db1200_i2c_devs, 829 i2c_register_board_info(0, db1200_i2c_devs,
537 ARRAY_SIZE(db1200_i2c_devs)); 830 ARRAY_SIZE(db1200_i2c_devs));
@@ -540,6 +833,7 @@ static int __init db1200_dev_init(void)
540 833
541 /* SWITCHES: S6.8 I2C/SPI selector (OFF=I2C ON=SPI) 834 /* SWITCHES: S6.8 I2C/SPI selector (OFF=I2C ON=SPI)
542 * S6.7 AC97/I2S selector (OFF=AC97 ON=I2S) 835 * S6.7 AC97/I2S selector (OFF=AC97 ON=I2S)
836 * or S12 on the PB1200.
543 */ 837 */
544 838
545 /* NOTE: GPIO215 controls OTG VBUS supply. In SPI mode however 839 /* NOTE: GPIO215 controls OTG VBUS supply. In SPI mode however
@@ -554,7 +848,7 @@ static int __init db1200_dev_init(void)
554 gpio_request(215, "otg-vbus"); 848 gpio_request(215, "otg-vbus");
555 gpio_direction_output(215, 1); 849 gpio_direction_output(215, 1);
556 850
557 printk(KERN_INFO "DB1200 device configuration:\n"); 851 printk(KERN_INFO "%s device configuration:\n", board_type_str());
558 852
559 sw = bcsr_read(BCSR_SWITCHES); 853 sw = bcsr_read(BCSR_SWITCHES);
560 if (sw & BCSR_SWITCHES_DIP_8) { 854 if (sw & BCSR_SWITCHES_DIP_8) {
@@ -595,7 +889,7 @@ static int __init db1200_dev_init(void)
595 889
596 /* Audio PSC clock is supplied externally. (FIXME: platdata!!) */ 890 /* Audio PSC clock is supplied externally. (FIXME: platdata!!) */
597 __raw_writel(PSC_SEL_CLK_SERCLK, 891 __raw_writel(PSC_SEL_CLK_SERCLK,
598 (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET); 892 (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
599 wmb(); 893 wmb();
600 894
601 db1x_register_pcmcia_socket( 895 db1x_register_pcmcia_socket(
@@ -621,28 +915,13 @@ static int __init db1200_dev_init(void)
621 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT; 915 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT;
622 db1x_register_norflash(64 << 20, 2, swapped); 916 db1x_register_norflash(64 << 20, 2, swapped);
623 917
624 return platform_add_devices(db1200_devs, ARRAY_SIZE(db1200_devs)); 918 platform_add_devices(db1200_devs, ARRAY_SIZE(db1200_devs));
625}
626device_initcall(db1200_dev_init);
627
628/* au1200fb calls these: STERBT EINEN TRAGISCHEN TOD!!! */
629int board_au1200fb_panel(void)
630{
631 return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f;
632}
633 919
634int board_au1200fb_panel_init(void) 920 /* PB1200 is a DB1200 with a 2nd MMC and Camera connector */
635{ 921 if ((bid == BCSR_WHOAMI_PB1200_DDR1) ||
636 /* Apply power */ 922 (bid == BCSR_WHOAMI_PB1200_DDR2))
637 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | 923 platform_add_devices(pb1200_devs, ARRAY_SIZE(pb1200_devs));
638 BCSR_BOARD_LCDBL);
639 return 0;
640}
641 924
642int board_au1200fb_panel_shutdown(void)
643{
644 /* Remove power */
645 bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
646 BCSR_BOARD_LCDBL, 0);
647 return 0; 925 return 0;
648} 926}
927device_initcall(db1200_dev_init);
diff --git a/arch/mips/alchemy/devboards/db1200/Makefile b/arch/mips/alchemy/devboards/db1200/Makefile
deleted file mode 100644
index 17840a5e2738..000000000000
--- a/arch/mips/alchemy/devboards/db1200/Makefile
+++ /dev/null
@@ -1 +0,0 @@
1obj-y += setup.o platform.o
diff --git a/arch/mips/alchemy/devboards/db1200/setup.c b/arch/mips/alchemy/devboards/db1200/setup.c
deleted file mode 100644
index 4a8980027ecf..000000000000
--- a/arch/mips/alchemy/devboards/db1200/setup.c
+++ /dev/null
@@ -1,81 +0,0 @@
1/*
2 * Alchemy/AMD/RMI DB1200 board setup.
3 *
4 * Licensed under the terms outlined in the file COPYING in the root of
5 * this source archive.
6 */
7
8#include <linux/init.h>
9#include <linux/interrupt.h>
10#include <linux/io.h>
11#include <linux/kernel.h>
12#include <asm/mach-au1x00/au1000.h>
13#include <asm/mach-db1x00/bcsr.h>
14#include <asm/mach-db1x00/db1200.h>
15
16const char *get_system_type(void)
17{
18 return "Alchemy Db1200";
19}
20
21void __init board_setup(void)
22{
23 unsigned long freq0, clksrc, div, pfc;
24 unsigned short whoami;
25
26 bcsr_init(DB1200_BCSR_PHYS_ADDR,
27 DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);
28
29 whoami = bcsr_read(BCSR_WHOAMI);
30 printk(KERN_INFO "Alchemy/AMD/RMI DB1200 Board, CPLD Rev %d"
31 " Board-ID %d Daughtercard ID %d\n",
32 (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
33
34 /* SMBus/SPI on PSC0, Audio on PSC1 */
35 pfc = __raw_readl((void __iomem *)SYS_PINFUNC);
36 pfc &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B);
37 pfc &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B | SYS_PINFUNC_FS3);
38 pfc |= SYS_PINFUNC_P1C; /* SPI is configured later */
39 __raw_writel(pfc, (void __iomem *)SYS_PINFUNC);
40 wmb();
41
42 /* Clock configurations: PSC0: ~50MHz via Clkgen0, derived from
43 * CPU clock; all other clock generators off/unused.
44 */
45 div = (get_au1x00_speed() + 25000000) / 50000000;
46 if (div & 1)
47 div++;
48 div = ((div >> 1) - 1) & 0xff;
49
50 freq0 = div << SYS_FC_FRDIV0_BIT;
51 __raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0);
52 wmb();
53 freq0 |= SYS_FC_FE0; /* enable F0 */
54 __raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0);
55 wmb();
56
57 /* psc0_intclk comes 1:1 from F0 */
58 clksrc = SYS_CS_MUX_FQ0 << SYS_CS_ME0_BIT;
59 __raw_writel(clksrc, (void __iomem *)SYS_CLKSRC);
60 wmb();
61}
62
63static int __init db1200_arch_init(void)
64{
65 /* GPIO7 is low-level triggered CPLD cascade */
66 irq_set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW);
67 bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT);
68
69 /* insert/eject pairs: one of both is always screaming. To avoid
70 * issues they must not be automatically enabled when initially
71 * requested.
72 */
73 irq_set_status_flags(DB1200_SD0_INSERT_INT, IRQ_NOAUTOEN);
74 irq_set_status_flags(DB1200_SD0_EJECT_INT, IRQ_NOAUTOEN);
75 irq_set_status_flags(DB1200_PC0_INSERT_INT, IRQ_NOAUTOEN);
76 irq_set_status_flags(DB1200_PC0_EJECT_INT, IRQ_NOAUTOEN);
77 irq_set_status_flags(DB1200_PC1_INSERT_INT, IRQ_NOAUTOEN);
78 irq_set_status_flags(DB1200_PC1_EJECT_INT, IRQ_NOAUTOEN);
79 return 0;
80}
81arch_initcall(db1200_arch_init);
diff --git a/arch/mips/alchemy/devboards/db1300.c b/arch/mips/alchemy/devboards/db1300.c
new file mode 100644
index 000000000000..0893f2af0d01
--- /dev/null
+++ b/arch/mips/alchemy/devboards/db1300.c
@@ -0,0 +1,785 @@
1/*
2 * DBAu1300 init and platform device setup.
3 *
4 * (c) 2009 Manuel Lauss <manuel.lauss@googlemail.com>
5 */
6
7#include <linux/dma-mapping.h>
8#include <linux/gpio.h>
9#include <linux/gpio_keys.h>
10#include <linux/init.h>
11#include <linux/input.h> /* KEY_* codes */
12#include <linux/i2c.h>
13#include <linux/io.h>
14#include <linux/leds.h>
15#include <linux/ata_platform.h>
16#include <linux/mmc/host.h>
17#include <linux/module.h>
18#include <linux/mtd/mtd.h>
19#include <linux/mtd/nand.h>
20#include <linux/mtd/partitions.h>
21#include <linux/platform_device.h>
22#include <linux/smsc911x.h>
23
24#include <asm/mach-au1x00/au1000.h>
25#include <asm/mach-au1x00/au1100_mmc.h>
26#include <asm/mach-au1x00/au1200fb.h>
27#include <asm/mach-au1x00/au1xxx_dbdma.h>
28#include <asm/mach-au1x00/au1xxx_psc.h>
29#include <asm/mach-db1x00/db1300.h>
30#include <asm/mach-db1x00/bcsr.h>
31#include <asm/mach-au1x00/prom.h>
32
33#include "platform.h"
34
35static struct i2c_board_info db1300_i2c_devs[] __initdata = {
36 { I2C_BOARD_INFO("wm8731", 0x1b), }, /* I2S audio codec */
37 { I2C_BOARD_INFO("ne1619", 0x2d), }, /* adm1025-compat hwmon */
38};
39
40/* multifunction pins to assign to GPIO controller */
41static int db1300_gpio_pins[] __initdata = {
42 AU1300_PIN_LCDPWM0, AU1300_PIN_PSC2SYNC1, AU1300_PIN_WAKE1,
43 AU1300_PIN_WAKE2, AU1300_PIN_WAKE3, AU1300_PIN_FG3AUX,
44 AU1300_PIN_EXTCLK1,
45 -1, /* terminator */
46};
47
48/* multifunction pins to assign to device functions */
49static int db1300_dev_pins[] __initdata = {
50 /* wake-from-str pins 0-3 */
51 AU1300_PIN_WAKE0,
52 /* external clock sources for PSC0 */
53 AU1300_PIN_EXTCLK0,
54 /* 8bit MMC interface on SD0: 6-9 */
55 AU1300_PIN_SD0DAT4, AU1300_PIN_SD0DAT5, AU1300_PIN_SD0DAT6,
56 AU1300_PIN_SD0DAT7,
57 /* UART1 pins: 11-18 */
58 AU1300_PIN_U1RI, AU1300_PIN_U1DCD, AU1300_PIN_U1DSR,
59 AU1300_PIN_U1CTS, AU1300_PIN_U1RTS, AU1300_PIN_U1DTR,
60 AU1300_PIN_U1RX, AU1300_PIN_U1TX,
61 /* UART0 pins: 19-24 */
62 AU1300_PIN_U0RI, AU1300_PIN_U0DCD, AU1300_PIN_U0DSR,
63 AU1300_PIN_U0CTS, AU1300_PIN_U0RTS, AU1300_PIN_U0DTR,
64 /* UART2: 25-26 */
65 AU1300_PIN_U2RX, AU1300_PIN_U2TX,
66 /* UART3: 27-28 */
67 AU1300_PIN_U3RX, AU1300_PIN_U3TX,
68 /* LCD controller PWMs, ext pixclock: 30-31 */
69 AU1300_PIN_LCDPWM1, AU1300_PIN_LCDCLKIN,
70 /* SD1 interface: 32-37 */
71 AU1300_PIN_SD1DAT0, AU1300_PIN_SD1DAT1, AU1300_PIN_SD1DAT2,
72 AU1300_PIN_SD1DAT3, AU1300_PIN_SD1CMD, AU1300_PIN_SD1CLK,
73 /* SD2 interface: 38-43 */
74 AU1300_PIN_SD2DAT0, AU1300_PIN_SD2DAT1, AU1300_PIN_SD2DAT2,
75 AU1300_PIN_SD2DAT3, AU1300_PIN_SD2CMD, AU1300_PIN_SD2CLK,
76 /* PSC0/1 clocks: 44-45 */
77 AU1300_PIN_PSC0CLK, AU1300_PIN_PSC1CLK,
78 /* PSCs: 46-49/50-53/54-57/58-61 */
79 AU1300_PIN_PSC0SYNC0, AU1300_PIN_PSC0SYNC1, AU1300_PIN_PSC0D0,
80 AU1300_PIN_PSC0D1,
81 AU1300_PIN_PSC1SYNC0, AU1300_PIN_PSC1SYNC1, AU1300_PIN_PSC1D0,
82 AU1300_PIN_PSC1D1,
83 AU1300_PIN_PSC2SYNC0, AU1300_PIN_PSC2D0,
84 AU1300_PIN_PSC2D1,
85 AU1300_PIN_PSC3SYNC0, AU1300_PIN_PSC3SYNC1, AU1300_PIN_PSC3D0,
86 AU1300_PIN_PSC3D1,
87 /* PCMCIA interface: 62-70 */
88 AU1300_PIN_PCE2, AU1300_PIN_PCE1, AU1300_PIN_PIOS16,
89 AU1300_PIN_PIOR, AU1300_PIN_PWE, AU1300_PIN_PWAIT,
90 AU1300_PIN_PREG, AU1300_PIN_POE, AU1300_PIN_PIOW,
91 /* camera interface H/V sync inputs: 71-72 */
92 AU1300_PIN_CIMLS, AU1300_PIN_CIMFS,
93 /* PSC2/3 clocks: 73-74 */
94 AU1300_PIN_PSC2CLK, AU1300_PIN_PSC3CLK,
95 -1, /* terminator */
96};
97
98static void __init db1300_gpio_config(void)
99{
100 int *i;
101
102 i = &db1300_dev_pins[0];
103 while (*i != -1)
104 au1300_pinfunc_to_dev(*i++);
105
106 i = &db1300_gpio_pins[0];
107 while (*i != -1)
108 au1300_gpio_direction_input(*i++);/* implies pin_to_gpio */
109
110 au1300_set_dbdma_gpio(1, AU1300_PIN_FG3AUX);
111}
112
113char *get_system_type(void)
114{
115 return "DB1300";
116}
117
118/**********************************************************************/
119
120static void au1300_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
121 unsigned int ctrl)
122{
123 struct nand_chip *this = mtd->priv;
124 unsigned long ioaddr = (unsigned long)this->IO_ADDR_W;
125
126 ioaddr &= 0xffffff00;
127
128 if (ctrl & NAND_CLE) {
129 ioaddr += MEM_STNAND_CMD;
130 } else if (ctrl & NAND_ALE) {
131 ioaddr += MEM_STNAND_ADDR;
132 } else {
133 /* assume we want to r/w real data by default */
134 ioaddr += MEM_STNAND_DATA;
135 }
136 this->IO_ADDR_R = this->IO_ADDR_W = (void __iomem *)ioaddr;
137 if (cmd != NAND_CMD_NONE) {
138 __raw_writeb(cmd, this->IO_ADDR_W);
139 wmb();
140 }
141}
142
143static int au1300_nand_device_ready(struct mtd_info *mtd)
144{
145 return __raw_readl((void __iomem *)MEM_STSTAT) & 1;
146}
147
148static const char *db1300_part_probes[] = { "cmdlinepart", NULL };
149
150static struct mtd_partition db1300_nand_parts[] = {
151 {
152 .name = "NAND FS 0",
153 .offset = 0,
154 .size = 8 * 1024 * 1024,
155 },
156 {
157 .name = "NAND FS 1",
158 .offset = MTDPART_OFS_APPEND,
159 .size = MTDPART_SIZ_FULL
160 },
161};
162
163struct platform_nand_data db1300_nand_platdata = {
164 .chip = {
165 .nr_chips = 1,
166 .chip_offset = 0,
167 .nr_partitions = ARRAY_SIZE(db1300_nand_parts),
168 .partitions = db1300_nand_parts,
169 .chip_delay = 20,
170 .part_probe_types = db1300_part_probes,
171 },
172 .ctrl = {
173 .dev_ready = au1300_nand_device_ready,
174 .cmd_ctrl = au1300_nand_cmd_ctrl,
175 },
176};
177
178static struct resource db1300_nand_res[] = {
179 [0] = {
180 .start = DB1300_NAND_PHYS_ADDR,
181 .end = DB1300_NAND_PHYS_ADDR + 0xff,
182 .flags = IORESOURCE_MEM,
183 },
184};
185
186static struct platform_device db1300_nand_dev = {
187 .name = "gen_nand",
188 .num_resources = ARRAY_SIZE(db1300_nand_res),
189 .resource = db1300_nand_res,
190 .id = -1,
191 .dev = {
192 .platform_data = &db1300_nand_platdata,
193 }
194};
195
196/**********************************************************************/
197
198static struct resource db1300_eth_res[] = {
199 [0] = {
200 .start = DB1300_ETH_PHYS_ADDR,
201 .end = DB1300_ETH_PHYS_END,
202 .flags = IORESOURCE_MEM,
203 },
204 [1] = {
205 .start = DB1300_ETH_INT,
206 .end = DB1300_ETH_INT,
207 .flags = IORESOURCE_IRQ,
208 },
209};
210
211static struct smsc911x_platform_config db1300_eth_config = {
212 .phy_interface = PHY_INTERFACE_MODE_MII,
213 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
214 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
215 .flags = SMSC911X_USE_32BIT,
216};
217
218static struct platform_device db1300_eth_dev = {
219 .name = "smsc911x",
220 .id = -1,
221 .num_resources = ARRAY_SIZE(db1300_eth_res),
222 .resource = db1300_eth_res,
223 .dev = {
224 .platform_data = &db1300_eth_config,
225 },
226};
227
228/**********************************************************************/
229
230static struct resource au1300_psc1_res[] = {
231 [0] = {
232 .start = AU1300_PSC1_PHYS_ADDR,
233 .end = AU1300_PSC1_PHYS_ADDR + 0x0fff,
234 .flags = IORESOURCE_MEM,
235 },
236 [1] = {
237 .start = AU1300_PSC1_INT,
238 .end = AU1300_PSC1_INT,
239 .flags = IORESOURCE_IRQ,
240 },
241 [2] = {
242 .start = AU1300_DSCR_CMD0_PSC1_TX,
243 .end = AU1300_DSCR_CMD0_PSC1_TX,
244 .flags = IORESOURCE_DMA,
245 },
246 [3] = {
247 .start = AU1300_DSCR_CMD0_PSC1_RX,
248 .end = AU1300_DSCR_CMD0_PSC1_RX,
249 .flags = IORESOURCE_DMA,
250 },
251};
252
253static struct platform_device db1300_ac97_dev = {
254 .name = "au1xpsc_ac97",
255 .id = 1, /* PSC ID. match with AC97 codec ID! */
256 .num_resources = ARRAY_SIZE(au1300_psc1_res),
257 .resource = au1300_psc1_res,
258};
259
260/**********************************************************************/
261
262static struct resource au1300_psc2_res[] = {
263 [0] = {
264 .start = AU1300_PSC2_PHYS_ADDR,
265 .end = AU1300_PSC2_PHYS_ADDR + 0x0fff,
266 .flags = IORESOURCE_MEM,
267 },
268 [1] = {
269 .start = AU1300_PSC2_INT,
270 .end = AU1300_PSC2_INT,
271 .flags = IORESOURCE_IRQ,
272 },
273 [2] = {
274 .start = AU1300_DSCR_CMD0_PSC2_TX,
275 .end = AU1300_DSCR_CMD0_PSC2_TX,
276 .flags = IORESOURCE_DMA,
277 },
278 [3] = {
279 .start = AU1300_DSCR_CMD0_PSC2_RX,
280 .end = AU1300_DSCR_CMD0_PSC2_RX,
281 .flags = IORESOURCE_DMA,
282 },
283};
284
285static struct platform_device db1300_i2s_dev = {
286 .name = "au1xpsc_i2s",
287 .id = 2, /* PSC ID */
288 .num_resources = ARRAY_SIZE(au1300_psc2_res),
289 .resource = au1300_psc2_res,
290};
291
292/**********************************************************************/
293
294static struct resource au1300_psc3_res[] = {
295 [0] = {
296 .start = AU1300_PSC3_PHYS_ADDR,
297 .end = AU1300_PSC3_PHYS_ADDR + 0x0fff,
298 .flags = IORESOURCE_MEM,
299 },
300 [1] = {
301 .start = AU1300_PSC3_INT,
302 .end = AU1300_PSC3_INT,
303 .flags = IORESOURCE_IRQ,
304 },
305 [2] = {
306 .start = AU1300_DSCR_CMD0_PSC3_TX,
307 .end = AU1300_DSCR_CMD0_PSC3_TX,
308 .flags = IORESOURCE_DMA,
309 },
310 [3] = {
311 .start = AU1300_DSCR_CMD0_PSC3_RX,
312 .end = AU1300_DSCR_CMD0_PSC3_RX,
313 .flags = IORESOURCE_DMA,
314 },
315};
316
317static struct platform_device db1300_i2c_dev = {
318 .name = "au1xpsc_smbus",
319 .id = 0, /* bus number */
320 .num_resources = ARRAY_SIZE(au1300_psc3_res),
321 .resource = au1300_psc3_res,
322};
323
324/**********************************************************************/
325
326/* proper key assignments when facing the LCD panel. For key assignments
327 * according to the schematics swap up with down and left with right.
328 * I chose to use it to emulate the arrow keys of a keyboard.
329 */
330static struct gpio_keys_button db1300_5waysw_arrowkeys[] = {
331 {
332 .code = KEY_DOWN,
333 .gpio = AU1300_PIN_LCDPWM0,
334 .type = EV_KEY,
335 .debounce_interval = 1,
336 .active_low = 1,
337 .desc = "5waysw-down",
338 },
339 {
340 .code = KEY_UP,
341 .gpio = AU1300_PIN_PSC2SYNC1,
342 .type = EV_KEY,
343 .debounce_interval = 1,
344 .active_low = 1,
345 .desc = "5waysw-up",
346 },
347 {
348 .code = KEY_RIGHT,
349 .gpio = AU1300_PIN_WAKE3,
350 .type = EV_KEY,
351 .debounce_interval = 1,
352 .active_low = 1,
353 .desc = "5waysw-right",
354 },
355 {
356 .code = KEY_LEFT,
357 .gpio = AU1300_PIN_WAKE2,
358 .type = EV_KEY,
359 .debounce_interval = 1,
360 .active_low = 1,
361 .desc = "5waysw-left",
362 },
363 {
364 .code = KEY_ENTER,
365 .gpio = AU1300_PIN_WAKE1,
366 .type = EV_KEY,
367 .debounce_interval = 1,
368 .active_low = 1,
369 .desc = "5waysw-push",
370 },
371};
372
373static struct gpio_keys_platform_data db1300_5waysw_data = {
374 .buttons = db1300_5waysw_arrowkeys,
375 .nbuttons = ARRAY_SIZE(db1300_5waysw_arrowkeys),
376 .rep = 1,
377 .name = "db1300-5wayswitch",
378};
379
380static struct platform_device db1300_5waysw_dev = {
381 .name = "gpio-keys",
382 .dev = {
383 .platform_data = &db1300_5waysw_data,
384 },
385};
386
387/**********************************************************************/
388
389static struct pata_platform_info db1300_ide_info = {
390 .ioport_shift = DB1300_IDE_REG_SHIFT,
391};
392
393#define IDE_ALT_START (14 << DB1300_IDE_REG_SHIFT)
394static struct resource db1300_ide_res[] = {
395 [0] = {
396 .start = DB1300_IDE_PHYS_ADDR,
397 .end = DB1300_IDE_PHYS_ADDR + IDE_ALT_START - 1,
398 .flags = IORESOURCE_MEM,
399 },
400 [1] = {
401 .start = DB1300_IDE_PHYS_ADDR + IDE_ALT_START,
402 .end = DB1300_IDE_PHYS_ADDR + DB1300_IDE_PHYS_LEN - 1,
403 .flags = IORESOURCE_MEM,
404 },
405 [2] = {
406 .start = DB1300_IDE_INT,
407 .end = DB1300_IDE_INT,
408 .flags = IORESOURCE_IRQ,
409 },
410};
411
412static struct platform_device db1300_ide_dev = {
413 .dev = {
414 .platform_data = &db1300_ide_info,
415 },
416 .name = "pata_platform",
417 .resource = db1300_ide_res,
418 .num_resources = ARRAY_SIZE(db1300_ide_res),
419};
420
421/**********************************************************************/
422
423static irqreturn_t db1300_mmc_cd(int irq, void *ptr)
424{
425 void(*mmc_cd)(struct mmc_host *, unsigned long);
426
427 /* disable the one currently screaming. No other way to shut it up */
428 if (irq == DB1300_SD1_INSERT_INT) {
429 disable_irq_nosync(DB1300_SD1_INSERT_INT);
430 enable_irq(DB1300_SD1_EJECT_INT);
431 } else {
432 disable_irq_nosync(DB1300_SD1_EJECT_INT);
433 enable_irq(DB1300_SD1_INSERT_INT);
434 }
435
436 /* link against CONFIG_MMC=m. We can only be called once MMC core has
437 * initialized the controller, so symbol_get() should always succeed.
438 */
439 mmc_cd = symbol_get(mmc_detect_change);
440 mmc_cd(ptr, msecs_to_jiffies(500));
441 symbol_put(mmc_detect_change);
442
443 return IRQ_HANDLED;
444}
445
446static int db1300_mmc_card_readonly(void *mmc_host)
447{
448 /* it uses SD1 interface, but the DB1200's SD0 bit in the CPLD */
449 return bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP;
450}
451
452static int db1300_mmc_card_inserted(void *mmc_host)
453{
454 return bcsr_read(BCSR_SIGSTAT) & (1 << 12); /* insertion irq signal */
455}
456
457static int db1300_mmc_cd_setup(void *mmc_host, int en)
458{
459 int ret;
460
461 if (en) {
462 ret = request_irq(DB1300_SD1_INSERT_INT, db1300_mmc_cd, 0,
463 "sd_insert", mmc_host);
464 if (ret)
465 goto out;
466
467 ret = request_irq(DB1300_SD1_EJECT_INT, db1300_mmc_cd, 0,
468 "sd_eject", mmc_host);
469 if (ret) {
470 free_irq(DB1300_SD1_INSERT_INT, mmc_host);
471 goto out;
472 }
473
474 if (db1300_mmc_card_inserted(mmc_host))
475 enable_irq(DB1300_SD1_EJECT_INT);
476 else
477 enable_irq(DB1300_SD1_INSERT_INT);
478
479 } else {
480 free_irq(DB1300_SD1_INSERT_INT, mmc_host);
481 free_irq(DB1300_SD1_EJECT_INT, mmc_host);
482 }
483 ret = 0;
484out:
485 return ret;
486}
487
488static void db1300_mmcled_set(struct led_classdev *led,
489 enum led_brightness brightness)
490{
491 if (brightness != LED_OFF)
492 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0);
493 else
494 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0);
495}
496
497static struct led_classdev db1300_mmc_led = {
498 .brightness_set = db1300_mmcled_set,
499};
500
501struct au1xmmc_platform_data db1300_sd1_platdata = {
502 .cd_setup = db1300_mmc_cd_setup,
503 .card_inserted = db1300_mmc_card_inserted,
504 .card_readonly = db1300_mmc_card_readonly,
505 .led = &db1300_mmc_led,
506};
507
508static struct resource au1300_sd1_res[] = {
509 [0] = {
510 .start = AU1300_SD1_PHYS_ADDR,
511 .end = AU1300_SD1_PHYS_ADDR,
512 .flags = IORESOURCE_MEM,
513 },
514 [1] = {
515 .start = AU1300_SD1_INT,
516 .end = AU1300_SD1_INT,
517 .flags = IORESOURCE_IRQ,
518 },
519 [2] = {
520 .start = AU1300_DSCR_CMD0_SDMS_TX1,
521 .end = AU1300_DSCR_CMD0_SDMS_TX1,
522 .flags = IORESOURCE_DMA,
523 },
524 [3] = {
525 .start = AU1300_DSCR_CMD0_SDMS_RX1,
526 .end = AU1300_DSCR_CMD0_SDMS_RX1,
527 .flags = IORESOURCE_DMA,
528 },
529};
530
531static struct platform_device db1300_sd1_dev = {
532 .dev = {
533 .platform_data = &db1300_sd1_platdata,
534 },
535 .name = "au1xxx-mmc",
536 .id = 1,
537 .resource = au1300_sd1_res,
538 .num_resources = ARRAY_SIZE(au1300_sd1_res),
539};
540
541/**********************************************************************/
542
543static int db1300_movinand_inserted(void *mmc_host)
544{
545 return 0; /* disable for now, it doesn't work yet */
546}
547
548static int db1300_movinand_readonly(void *mmc_host)
549{
550 return 0;
551}
552
553static void db1300_movinand_led_set(struct led_classdev *led,
554 enum led_brightness brightness)
555{
556 if (brightness != LED_OFF)
557 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0);
558 else
559 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1);
560}
561
562static struct led_classdev db1300_movinand_led = {
563 .brightness_set = db1300_movinand_led_set,
564};
565
566struct au1xmmc_platform_data db1300_sd0_platdata = {
567 .card_inserted = db1300_movinand_inserted,
568 .card_readonly = db1300_movinand_readonly,
569 .led = &db1300_movinand_led,
570 .mask_host_caps = MMC_CAP_NEEDS_POLL,
571};
572
573static struct resource au1300_sd0_res[] = {
574 [0] = {
575 .start = AU1100_SD0_PHYS_ADDR,
576 .end = AU1100_SD0_PHYS_ADDR,
577 .flags = IORESOURCE_MEM,
578 },
579 [1] = {
580 .start = AU1300_SD0_INT,
581 .end = AU1300_SD0_INT,
582 .flags = IORESOURCE_IRQ,
583 },
584 [2] = {
585 .start = AU1300_DSCR_CMD0_SDMS_TX0,
586 .end = AU1300_DSCR_CMD0_SDMS_TX0,
587 .flags = IORESOURCE_DMA,
588 },
589 [3] = {
590 .start = AU1300_DSCR_CMD0_SDMS_RX0,
591 .end = AU1300_DSCR_CMD0_SDMS_RX0,
592 .flags = IORESOURCE_DMA,
593 },
594};
595
596static struct platform_device db1300_sd0_dev = {
597 .dev = {
598 .platform_data = &db1300_sd0_platdata,
599 },
600 .name = "au1xxx-mmc",
601 .id = 0,
602 .resource = au1300_sd0_res,
603 .num_resources = ARRAY_SIZE(au1300_sd0_res),
604};
605
606/**********************************************************************/
607
608static struct platform_device db1300_wm9715_dev = {
609 .name = "wm9712-codec",
610 .id = 1, /* ID of PSC for AC97 audio, see asoc glue! */
611};
612
613static struct platform_device db1300_ac97dma_dev = {
614 .name = "au1xpsc-pcm",
615 .id = 1, /* PSC ID */
616};
617
618static struct platform_device db1300_i2sdma_dev = {
619 .name = "au1xpsc-pcm",
620 .id = 2, /* PSC ID */
621};
622
623static struct platform_device db1300_sndac97_dev = {
624 .name = "db1300-ac97",
625};
626
627static struct platform_device db1300_sndi2s_dev = {
628 .name = "db1300-i2s",
629};
630
631/**********************************************************************/
632
633static int db1300fb_panel_index(void)
634{
635 return 9; /* DB1300_800x480 */
636}
637
638static int db1300fb_panel_init(void)
639{
640 /* Apply power (Vee/Vdd logic is inverted on Panel DB1300_800x480) */
641 bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD,
642 BCSR_BOARD_LCDBL);
643 return 0;
644}
645
646static int db1300fb_panel_shutdown(void)
647{
648 /* Remove power (Vee/Vdd logic is inverted on Panel DB1300_800x480) */
649 bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDBL,
650 BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD);
651 return 0;
652}
653
654static struct au1200fb_platdata db1300fb_pd = {
655 .panel_index = db1300fb_panel_index,
656 .panel_init = db1300fb_panel_init,
657 .panel_shutdown = db1300fb_panel_shutdown,
658};
659
660static struct resource au1300_lcd_res[] = {
661 [0] = {
662 .start = AU1200_LCD_PHYS_ADDR,
663 .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1,
664 .flags = IORESOURCE_MEM,
665 },
666 [1] = {
667 .start = AU1300_LCD_INT,
668 .end = AU1300_LCD_INT,
669 .flags = IORESOURCE_IRQ,
670 }
671};
672
673static u64 au1300_lcd_dmamask = DMA_BIT_MASK(32);
674
675static struct platform_device db1300_lcd_dev = {
676 .name = "au1200-lcd",
677 .id = 0,
678 .dev = {
679 .dma_mask = &au1300_lcd_dmamask,
680 .coherent_dma_mask = DMA_BIT_MASK(32),
681 .platform_data = &db1300fb_pd,
682 },
683 .num_resources = ARRAY_SIZE(au1300_lcd_res),
684 .resource = au1300_lcd_res,
685};
686
687/**********************************************************************/
688
689static struct platform_device *db1300_dev[] __initdata = {
690 &db1300_eth_dev,
691 &db1300_i2c_dev,
692 &db1300_5waysw_dev,
693 &db1300_nand_dev,
694 &db1300_ide_dev,
695 &db1300_sd0_dev,
696 &db1300_sd1_dev,
697 &db1300_lcd_dev,
698 &db1300_ac97_dev,
699 &db1300_i2s_dev,
700 &db1300_wm9715_dev,
701 &db1300_ac97dma_dev,
702 &db1300_i2sdma_dev,
703 &db1300_sndac97_dev,
704 &db1300_sndi2s_dev,
705};
706
707static int __init db1300_device_init(void)
708{
709 int swapped, cpldirq;
710
711 /* setup CPLD IRQ muxer */
712 cpldirq = au1300_gpio_to_irq(AU1300_PIN_EXTCLK1);
713 irq_set_irq_type(cpldirq, IRQ_TYPE_LEVEL_HIGH);
714 bcsr_init_irq(DB1300_FIRST_INT, DB1300_LAST_INT, cpldirq);
715
716 /* insert/eject IRQs: one always triggers so don't enable them
717 * when doing request_irq() on them. DB1200 has this bug too.
718 */
719 irq_set_status_flags(DB1300_SD1_INSERT_INT, IRQ_NOAUTOEN);
720 irq_set_status_flags(DB1300_SD1_EJECT_INT, IRQ_NOAUTOEN);
721 irq_set_status_flags(DB1300_CF_INSERT_INT, IRQ_NOAUTOEN);
722 irq_set_status_flags(DB1300_CF_EJECT_INT, IRQ_NOAUTOEN);
723
724 /*
725 * setup board
726 */
727 prom_get_ethernet_addr(&db1300_eth_config.mac[0]);
728
729 i2c_register_board_info(0, db1300_i2c_devs,
730 ARRAY_SIZE(db1300_i2c_devs));
731
732 /* Audio PSC clock is supplied by codecs (PSC1, 2) */
733 __raw_writel(PSC_SEL_CLK_SERCLK,
734 (void __iomem *)KSEG1ADDR(AU1300_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
735 wmb();
736 __raw_writel(PSC_SEL_CLK_SERCLK,
737 (void __iomem *)KSEG1ADDR(AU1300_PSC2_PHYS_ADDR) + PSC_SEL_OFFSET);
738 wmb();
739 /* I2C uses internal 48MHz EXTCLK1 */
740 __raw_writel(PSC_SEL_CLK_INTCLK,
741 (void __iomem *)KSEG1ADDR(AU1300_PSC3_PHYS_ADDR) + PSC_SEL_OFFSET);
742 wmb();
743
744 /* enable power to USB ports */
745 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_USBHPWR | BCSR_RESETS_OTGPWR);
746
747 /* although it is socket #0, it uses the CPLD bits which previous boards
748 * have used for socket #1.
749 */
750 db1x_register_pcmcia_socket(
751 AU1000_PCMCIA_ATTR_PHYS_ADDR,
752 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x00400000 - 1,
753 AU1000_PCMCIA_MEM_PHYS_ADDR,
754 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x00400000 - 1,
755 AU1000_PCMCIA_IO_PHYS_ADDR,
756 AU1000_PCMCIA_IO_PHYS_ADDR + 0x00010000 - 1,
757 DB1300_CF_INT, DB1300_CF_INSERT_INT, 0, DB1300_CF_EJECT_INT, 1);
758
759 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT;
760 db1x_register_norflash(64 << 20, 2, swapped);
761
762 return platform_add_devices(db1300_dev, ARRAY_SIZE(db1300_dev));
763}
764device_initcall(db1300_device_init);
765
766
767void __init board_setup(void)
768{
769 unsigned short whoami;
770
771 db1300_gpio_config();
772 bcsr_init(DB1300_BCSR_PHYS_ADDR,
773 DB1300_BCSR_PHYS_ADDR + DB1300_BCSR_HEXLED_OFS);
774
775 whoami = bcsr_read(BCSR_WHOAMI);
776 printk(KERN_INFO "NetLogic DBAu1300 Development Platform.\n\t"
777 "BoardID %d CPLD Rev %d DaughtercardID %d\n",
778 BCSR_WHOAMI_BOARD(whoami), BCSR_WHOAMI_CPLD(whoami),
779 BCSR_WHOAMI_DCID(whoami));
780
781 /* enable UARTs, YAMON only enables #2 */
782 alchemy_uart_enable(AU1300_UART0_PHYS_ADDR);
783 alchemy_uart_enable(AU1300_UART1_PHYS_ADDR);
784 alchemy_uart_enable(AU1300_UART3_PHYS_ADDR);
785}
diff --git a/arch/mips/alchemy/devboards/db1550.c b/arch/mips/alchemy/devboards/db1550.c
new file mode 100644
index 000000000000..6815d0783cd8
--- /dev/null
+++ b/arch/mips/alchemy/devboards/db1550.c
@@ -0,0 +1,498 @@
1/*
2 * Alchemy Db1550 board support
3 *
4 * (c) 2011 Manuel Lauss <manuel.lauss@googlemail.com>
5 */
6
7#include <linux/dma-mapping.h>
8#include <linux/gpio.h>
9#include <linux/i2c.h>
10#include <linux/init.h>
11#include <linux/io.h>
12#include <linux/interrupt.h>
13#include <linux/mtd/mtd.h>
14#include <linux/mtd/nand.h>
15#include <linux/mtd/partitions.h>
16#include <linux/platform_device.h>
17#include <linux/pm.h>
18#include <linux/spi/spi.h>
19#include <linux/spi/flash.h>
20#include <asm/mach-au1x00/au1000.h>
21#include <asm/mach-au1x00/au1xxx_eth.h>
22#include <asm/mach-au1x00/au1xxx_dbdma.h>
23#include <asm/mach-au1x00/au1xxx_psc.h>
24#include <asm/mach-au1x00/au1550_spi.h>
25#include <asm/mach-db1x00/bcsr.h>
26#include <prom.h>
27#include "platform.h"
28
29
30const char *get_system_type(void)
31{
32 return "DB1550";
33}
34
35static void __init db1550_hw_setup(void)
36{
37 void __iomem *base;
38
39 alchemy_gpio_direction_output(203, 0); /* red led on */
40
41 /* complete SPI setup: link psc0_intclk to a 48MHz source,
42 * and assign GPIO16 to PSC0_SYNC1 (SPI cs# line)
43 */
44 base = (void __iomem *)SYS_CLKSRC;
45 __raw_writel(__raw_readl(base) | 0x000001e0, base);
46 base = (void __iomem *)SYS_PINFUNC;
47 __raw_writel(__raw_readl(base) | 1, base);
48 wmb();
49
50 /* reset the AC97 codec now, the reset time in the psc-ac97 driver
51 * is apparently too short although it's ridiculous as it is.
52 */
53 base = (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR);
54 __raw_writel(PSC_SEL_CLK_SERCLK | PSC_SEL_PS_AC97MODE,
55 base + PSC_SEL_OFFSET);
56 __raw_writel(PSC_CTRL_DISABLE, base + PSC_CTRL_OFFSET);
57 wmb();
58 __raw_writel(PSC_AC97RST_RST, base + PSC_AC97RST_OFFSET);
59 wmb();
60
61 alchemy_gpio_direction_output(202, 0); /* green led on */
62}
63
64void __init board_setup(void)
65{
66 unsigned short whoami;
67
68 bcsr_init(DB1550_BCSR_PHYS_ADDR,
69 DB1550_BCSR_PHYS_ADDR + DB1550_BCSR_HEXLED_OFS);
70
71 whoami = bcsr_read(BCSR_WHOAMI);
72 printk(KERN_INFO "Alchemy/AMD DB1550 Board, CPLD Rev %d"
73 " Board-ID %d Daughtercard ID %d\n",
74 (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
75
76 db1550_hw_setup();
77}
78
79/*****************************************************************************/
80
81static struct mtd_partition db1550_spiflash_parts[] = {
82 {
83 .name = "spi_flash",
84 .offset = 0,
85 .size = MTDPART_SIZ_FULL,
86 },
87};
88
89static struct flash_platform_data db1550_spiflash_data = {
90 .name = "s25fl010",
91 .parts = db1550_spiflash_parts,
92 .nr_parts = ARRAY_SIZE(db1550_spiflash_parts),
93 .type = "m25p10",
94};
95
96static struct spi_board_info db1550_spi_devs[] __initdata = {
97 {
98 /* TI TMP121AIDBVR temp sensor */
99 .modalias = "tmp121",
100 .max_speed_hz = 2400000,
101 .bus_num = 0,
102 .chip_select = 0,
103 .mode = SPI_MODE_0,
104 },
105 {
106 /* Spansion S25FL001D0FMA SPI flash */
107 .modalias = "m25p80",
108 .max_speed_hz = 2400000,
109 .bus_num = 0,
110 .chip_select = 1,
111 .mode = SPI_MODE_0,
112 .platform_data = &db1550_spiflash_data,
113 },
114};
115
116static struct i2c_board_info db1550_i2c_devs[] __initdata = {
117 { I2C_BOARD_INFO("24c04", 0x52),}, /* AT24C04-10 I2C eeprom */
118 { I2C_BOARD_INFO("ne1619", 0x2d),}, /* adm1025-compat hwmon */
119 { I2C_BOARD_INFO("wm8731", 0x1b),}, /* I2S audio codec WM8731 */
120};
121
122/**********************************************************************/
123
124static void au1550_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
125 unsigned int ctrl)
126{
127 struct nand_chip *this = mtd->priv;
128 unsigned long ioaddr = (unsigned long)this->IO_ADDR_W;
129
130 ioaddr &= 0xffffff00;
131
132 if (ctrl & NAND_CLE) {
133 ioaddr += MEM_STNAND_CMD;
134 } else if (ctrl & NAND_ALE) {
135 ioaddr += MEM_STNAND_ADDR;
136 } else {
137 /* assume we want to r/w real data by default */
138 ioaddr += MEM_STNAND_DATA;
139 }
140 this->IO_ADDR_R = this->IO_ADDR_W = (void __iomem *)ioaddr;
141 if (cmd != NAND_CMD_NONE) {
142 __raw_writeb(cmd, this->IO_ADDR_W);
143 wmb();
144 }
145}
146
147static int au1550_nand_device_ready(struct mtd_info *mtd)
148{
149 return __raw_readl((void __iomem *)MEM_STSTAT) & 1;
150}
151
152static const char *db1550_part_probes[] = { "cmdlinepart", NULL };
153
154static struct mtd_partition db1550_nand_parts[] = {
155 {
156 .name = "NAND FS 0",
157 .offset = 0,
158 .size = 8 * 1024 * 1024,
159 },
160 {
161 .name = "NAND FS 1",
162 .offset = MTDPART_OFS_APPEND,
163 .size = MTDPART_SIZ_FULL
164 },
165};
166
167struct platform_nand_data db1550_nand_platdata = {
168 .chip = {
169 .nr_chips = 1,
170 .chip_offset = 0,
171 .nr_partitions = ARRAY_SIZE(db1550_nand_parts),
172 .partitions = db1550_nand_parts,
173 .chip_delay = 20,
174 .part_probe_types = db1550_part_probes,
175 },
176 .ctrl = {
177 .dev_ready = au1550_nand_device_ready,
178 .cmd_ctrl = au1550_nand_cmd_ctrl,
179 },
180};
181
182static struct resource db1550_nand_res[] = {
183 [0] = {
184 .start = 0x20000000,
185 .end = 0x200000ff,
186 .flags = IORESOURCE_MEM,
187 },
188};
189
190static struct platform_device db1550_nand_dev = {
191 .name = "gen_nand",
192 .num_resources = ARRAY_SIZE(db1550_nand_res),
193 .resource = db1550_nand_res,
194 .id = -1,
195 .dev = {
196 .platform_data = &db1550_nand_platdata,
197 }
198};
199
200/**********************************************************************/
201
202static struct resource au1550_psc0_res[] = {
203 [0] = {
204 .start = AU1550_PSC0_PHYS_ADDR,
205 .end = AU1550_PSC0_PHYS_ADDR + 0xfff,
206 .flags = IORESOURCE_MEM,
207 },
208 [1] = {
209 .start = AU1550_PSC0_INT,
210 .end = AU1550_PSC0_INT,
211 .flags = IORESOURCE_IRQ,
212 },
213 [2] = {
214 .start = AU1550_DSCR_CMD0_PSC0_TX,
215 .end = AU1550_DSCR_CMD0_PSC0_TX,
216 .flags = IORESOURCE_DMA,
217 },
218 [3] = {
219 .start = AU1550_DSCR_CMD0_PSC0_RX,
220 .end = AU1550_DSCR_CMD0_PSC0_RX,
221 .flags = IORESOURCE_DMA,
222 },
223};
224
225static void db1550_spi_cs_en(struct au1550_spi_info *spi, int cs, int pol)
226{
227 if (cs)
228 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SPISEL);
229 else
230 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SPISEL, 0);
231}
232
233static struct au1550_spi_info db1550_spi_platdata = {
234 .mainclk_hz = 48000000, /* PSC0 clock: max. 2.4MHz SPI clk */
235 .num_chipselect = 2,
236 .activate_cs = db1550_spi_cs_en,
237};
238
239static u64 spi_dmamask = DMA_BIT_MASK(32);
240
241static struct platform_device db1550_spi_dev = {
242 .dev = {
243 .dma_mask = &spi_dmamask,
244 .coherent_dma_mask = DMA_BIT_MASK(32),
245 .platform_data = &db1550_spi_platdata,
246 },
247 .name = "au1550-spi",
248 .id = 0, /* bus number */
249 .num_resources = ARRAY_SIZE(au1550_psc0_res),
250 .resource = au1550_psc0_res,
251};
252
253/**********************************************************************/
254
255static struct resource au1550_psc1_res[] = {
256 [0] = {
257 .start = AU1550_PSC1_PHYS_ADDR,
258 .end = AU1550_PSC1_PHYS_ADDR + 0xfff,
259 .flags = IORESOURCE_MEM,
260 },
261 [1] = {
262 .start = AU1550_PSC1_INT,
263 .end = AU1550_PSC1_INT,
264 .flags = IORESOURCE_IRQ,
265 },
266 [2] = {
267 .start = AU1550_DSCR_CMD0_PSC1_TX,
268 .end = AU1550_DSCR_CMD0_PSC1_TX,
269 .flags = IORESOURCE_DMA,
270 },
271 [3] = {
272 .start = AU1550_DSCR_CMD0_PSC1_RX,
273 .end = AU1550_DSCR_CMD0_PSC1_RX,
274 .flags = IORESOURCE_DMA,
275 },
276};
277
278static struct platform_device db1550_ac97_dev = {
279 .name = "au1xpsc_ac97",
280 .id = 1, /* PSC ID */
281 .num_resources = ARRAY_SIZE(au1550_psc1_res),
282 .resource = au1550_psc1_res,
283};
284
285
286static struct resource au1550_psc2_res[] = {
287 [0] = {
288 .start = AU1550_PSC2_PHYS_ADDR,
289 .end = AU1550_PSC2_PHYS_ADDR + 0xfff,
290 .flags = IORESOURCE_MEM,
291 },
292 [1] = {
293 .start = AU1550_PSC2_INT,
294 .end = AU1550_PSC2_INT,
295 .flags = IORESOURCE_IRQ,
296 },
297 [2] = {
298 .start = AU1550_DSCR_CMD0_PSC2_TX,
299 .end = AU1550_DSCR_CMD0_PSC2_TX,
300 .flags = IORESOURCE_DMA,
301 },
302 [3] = {
303 .start = AU1550_DSCR_CMD0_PSC2_RX,
304 .end = AU1550_DSCR_CMD0_PSC2_RX,
305 .flags = IORESOURCE_DMA,
306 },
307};
308
309static struct platform_device db1550_i2c_dev = {
310 .name = "au1xpsc_smbus",
311 .id = 0, /* bus number */
312 .num_resources = ARRAY_SIZE(au1550_psc2_res),
313 .resource = au1550_psc2_res,
314};
315
316/**********************************************************************/
317
318static struct resource au1550_psc3_res[] = {
319 [0] = {
320 .start = AU1550_PSC3_PHYS_ADDR,
321 .end = AU1550_PSC3_PHYS_ADDR + 0xfff,
322 .flags = IORESOURCE_MEM,
323 },
324 [1] = {
325 .start = AU1550_PSC3_INT,
326 .end = AU1550_PSC3_INT,
327 .flags = IORESOURCE_IRQ,
328 },
329 [2] = {
330 .start = AU1550_DSCR_CMD0_PSC3_TX,
331 .end = AU1550_DSCR_CMD0_PSC3_TX,
332 .flags = IORESOURCE_DMA,
333 },
334 [3] = {
335 .start = AU1550_DSCR_CMD0_PSC3_RX,
336 .end = AU1550_DSCR_CMD0_PSC3_RX,
337 .flags = IORESOURCE_DMA,
338 },
339};
340
341static struct platform_device db1550_i2s_dev = {
342 .name = "au1xpsc_i2s",
343 .id = 3, /* PSC ID */
344 .num_resources = ARRAY_SIZE(au1550_psc3_res),
345 .resource = au1550_psc3_res,
346};
347
348/**********************************************************************/
349
350static struct platform_device db1550_stac_dev = {
351 .name = "ac97-codec",
352 .id = 1, /* on PSC1 */
353};
354
355static struct platform_device db1550_ac97dma_dev = {
356 .name = "au1xpsc-pcm",
357 .id = 1, /* on PSC3 */
358};
359
360static struct platform_device db1550_i2sdma_dev = {
361 .name = "au1xpsc-pcm",
362 .id = 3, /* on PSC3 */
363};
364
365static struct platform_device db1550_sndac97_dev = {
366 .name = "db1550-ac97",
367};
368
369static struct platform_device db1550_sndi2s_dev = {
370 .name = "db1550-i2s",
371};
372
373/**********************************************************************/
374
375static int db1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
376{
377 if ((slot < 11) || (slot > 13) || pin == 0)
378 return -1;
379 if (slot == 11)
380 return (pin == 1) ? AU1550_PCI_INTC : 0xff;
381 if (slot == 12) {
382 switch (pin) {
383 case 1: return AU1550_PCI_INTB;
384 case 2: return AU1550_PCI_INTC;
385 case 3: return AU1550_PCI_INTD;
386 case 4: return AU1550_PCI_INTA;
387 }
388 }
389 if (slot == 13) {
390 switch (pin) {
391 case 1: return AU1550_PCI_INTA;
392 case 2: return AU1550_PCI_INTB;
393 case 3: return AU1550_PCI_INTC;
394 case 4: return AU1550_PCI_INTD;
395 }
396 }
397 return -1;
398}
399
400static struct resource alchemy_pci_host_res[] = {
401 [0] = {
402 .start = AU1500_PCI_PHYS_ADDR,
403 .end = AU1500_PCI_PHYS_ADDR + 0xfff,
404 .flags = IORESOURCE_MEM,
405 },
406};
407
408static struct alchemy_pci_platdata db1550_pci_pd = {
409 .board_map_irq = db1550_map_pci_irq,
410};
411
412static struct platform_device db1550_pci_host_dev = {
413 .dev.platform_data = &db1550_pci_pd,
414 .name = "alchemy-pci",
415 .id = 0,
416 .num_resources = ARRAY_SIZE(alchemy_pci_host_res),
417 .resource = alchemy_pci_host_res,
418};
419
420/**********************************************************************/
421
422static struct platform_device *db1550_devs[] __initdata = {
423 &db1550_nand_dev,
424 &db1550_i2c_dev,
425 &db1550_ac97_dev,
426 &db1550_spi_dev,
427 &db1550_i2s_dev,
428 &db1550_stac_dev,
429 &db1550_ac97dma_dev,
430 &db1550_i2sdma_dev,
431 &db1550_sndac97_dev,
432 &db1550_sndi2s_dev,
433};
434
435/* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */
436static int __init db1550_pci_init(void)
437{
438 return platform_device_register(&db1550_pci_host_dev);
439}
440arch_initcall(db1550_pci_init);
441
442static int __init db1550_dev_init(void)
443{
444 int swapped;
445
446 irq_set_irq_type(AU1550_GPIO0_INT, IRQ_TYPE_EDGE_BOTH); /* CD0# */
447 irq_set_irq_type(AU1550_GPIO1_INT, IRQ_TYPE_EDGE_BOTH); /* CD1# */
448 irq_set_irq_type(AU1550_GPIO3_INT, IRQ_TYPE_LEVEL_LOW); /* CARD0# */
449 irq_set_irq_type(AU1550_GPIO5_INT, IRQ_TYPE_LEVEL_LOW); /* CARD1# */
450 irq_set_irq_type(AU1550_GPIO21_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG0# */
451 irq_set_irq_type(AU1550_GPIO22_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG1# */
452
453 i2c_register_board_info(0, db1550_i2c_devs,
454 ARRAY_SIZE(db1550_i2c_devs));
455 spi_register_board_info(db1550_spi_devs,
456 ARRAY_SIZE(db1550_i2c_devs));
457
458 /* Audio PSC clock is supplied by codecs (PSC1, 3) FIXME: platdata!! */
459 __raw_writel(PSC_SEL_CLK_SERCLK,
460 (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
461 wmb();
462 __raw_writel(PSC_SEL_CLK_SERCLK,
463 (void __iomem *)KSEG1ADDR(AU1550_PSC3_PHYS_ADDR) + PSC_SEL_OFFSET);
464 wmb();
465 /* SPI/I2C use internally supplied 50MHz source */
466 __raw_writel(PSC_SEL_CLK_INTCLK,
467 (void __iomem *)KSEG1ADDR(AU1550_PSC0_PHYS_ADDR) + PSC_SEL_OFFSET);
468 wmb();
469 __raw_writel(PSC_SEL_CLK_INTCLK,
470 (void __iomem *)KSEG1ADDR(AU1550_PSC2_PHYS_ADDR) + PSC_SEL_OFFSET);
471 wmb();
472
473 db1x_register_pcmcia_socket(
474 AU1000_PCMCIA_ATTR_PHYS_ADDR,
475 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
476 AU1000_PCMCIA_MEM_PHYS_ADDR,
477 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
478 AU1000_PCMCIA_IO_PHYS_ADDR,
479 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
480 AU1550_GPIO3_INT, AU1550_GPIO0_INT,
481 /*AU1550_GPIO21_INT*/0, 0, 0);
482
483 db1x_register_pcmcia_socket(
484 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
485 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
486 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000,
487 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
488 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000,
489 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
490 AU1550_GPIO5_INT, AU1550_GPIO1_INT,
491 /*AU1550_GPIO22_INT*/0, 0, 1);
492
493 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT;
494 db1x_register_norflash(128 << 20, 4, swapped);
495
496 return platform_add_devices(db1550_devs, ARRAY_SIZE(db1550_devs));
497}
498device_initcall(db1550_dev_init);
diff --git a/arch/mips/alchemy/devboards/db1x00/Makefile b/arch/mips/alchemy/devboards/db1x00/Makefile
deleted file mode 100644
index 613c0c0c8be9..000000000000
--- a/arch/mips/alchemy/devboards/db1x00/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
1#
2# Copyright 2000, 2008 MontaVista Software Inc.
3# Author: MontaVista Software, Inc. <source@mvista.com>
4#
5# Makefile for the Alchemy Semiconductor DBAu1xx0 boards.
6#
7
8obj-y := board_setup.o platform.o
diff --git a/arch/mips/alchemy/devboards/db1x00/board_setup.c b/arch/mips/alchemy/devboards/db1x00/board_setup.c
deleted file mode 100644
index 7cd36e631f6c..000000000000
--- a/arch/mips/alchemy/devboards/db1x00/board_setup.c
+++ /dev/null
@@ -1,229 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Alchemy Db1x00 board setup.
5 *
6 * Copyright 2000, 2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. <source@mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29
30#include <linux/gpio.h>
31#include <linux/init.h>
32#include <linux/interrupt.h>
33#include <linux/pm.h>
34
35#include <asm/mach-au1x00/au1000.h>
36#include <asm/mach-au1x00/au1xxx_eth.h>
37#include <asm/mach-db1x00/db1x00.h>
38#include <asm/mach-db1x00/bcsr.h>
39#include <asm/reboot.h>
40
41#include <prom.h>
42
43#ifdef CONFIG_MIPS_BOSPORUS
44char irq_tab_alchemy[][5] __initdata = {
45 [11] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 11 - miniPCI */
46 [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - SN1741 */
47 [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */
48};
49
50/*
51 * Micrel/Kendin 5 port switch attached to MAC0,
52 * MAC0 is associated with PHY address 5 (== WAN port)
53 * MAC1 is not associated with any PHY, since it's connected directly
54 * to the switch.
55 * no interrupts are used
56 */
57static struct au1000_eth_platform_data eth0_pdata = {
58 .phy_static_config = 1,
59 .phy_addr = 5,
60};
61
62static void bosporus_power_off(void)
63{
64 while (1)
65 asm volatile (".set mips3 ; wait ; .set mips0");
66}
67
68const char *get_system_type(void)
69{
70 return "Alchemy Bosporus Gateway Reference";
71}
72#endif
73
74
75#ifdef CONFIG_MIPS_MIRAGE
76static void mirage_power_off(void)
77{
78 alchemy_gpio_direction_output(210, 1);
79}
80
81const char *get_system_type(void)
82{
83 return "Alchemy Mirage";
84}
85#endif
86
87
88#if defined(CONFIG_MIPS_BOSPORUS) || defined(CONFIG_MIPS_MIRAGE)
89static void mips_softreset(void)
90{
91 asm volatile ("jr\t%0" : : "r"(0xbfc00000));
92}
93
94#else
95
96const char *get_system_type(void)
97{
98 return "Alchemy Db1x00";
99}
100#endif
101
102
103void __init board_setup(void)
104{
105 unsigned long bcsr1, bcsr2;
106
107 bcsr1 = DB1000_BCSR_PHYS_ADDR;
108 bcsr2 = DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS;
109
110#ifdef CONFIG_MIPS_DB1000
111 printk(KERN_INFO "AMD Alchemy Au1000/Db1000 Board\n");
112#endif
113#ifdef CONFIG_MIPS_DB1500
114 printk(KERN_INFO "AMD Alchemy Au1500/Db1500 Board\n");
115#endif
116#ifdef CONFIG_MIPS_DB1100
117 printk(KERN_INFO "AMD Alchemy Au1100/Db1100 Board\n");
118#endif
119#ifdef CONFIG_MIPS_BOSPORUS
120 au1xxx_override_eth_cfg(0, &eth0_pdata);
121
122 printk(KERN_INFO "AMD Alchemy Bosporus Board\n");
123#endif
124#ifdef CONFIG_MIPS_MIRAGE
125 printk(KERN_INFO "AMD Alchemy Mirage Board\n");
126#endif
127#ifdef CONFIG_MIPS_DB1550
128 printk(KERN_INFO "AMD Alchemy Au1550/Db1550 Board\n");
129
130 bcsr1 = DB1550_BCSR_PHYS_ADDR;
131 bcsr2 = DB1550_BCSR_PHYS_ADDR + DB1550_BCSR_HEXLED_OFS;
132#endif
133
134 /* initialize board register space */
135 bcsr_init(bcsr1, bcsr2);
136
137#if defined(CONFIG_IRDA) && defined(CONFIG_AU1000_FIR)
138 {
139 u32 pin_func;
140
141 /* Set IRFIRSEL instead of GPIO15 */
142 pin_func = au_readl(SYS_PINFUNC) | SYS_PF_IRF;
143 au_writel(pin_func, SYS_PINFUNC);
144 /* Power off until the driver is in use */
145 bcsr_mod(BCSR_RESETS, BCSR_RESETS_IRDA_MODE_MASK,
146 BCSR_RESETS_IRDA_MODE_OFF);
147 }
148#endif
149 bcsr_write(BCSR_PCMCIA, 0); /* turn off PCMCIA power */
150
151 /* Enable GPIO[31:0] inputs */
152 alchemy_gpio1_input_enable();
153
154#ifdef CONFIG_MIPS_MIRAGE
155 {
156 u32 pin_func;
157
158 /* GPIO[20] is output */
159 alchemy_gpio_direction_output(20, 0);
160
161 /* Set GPIO[210:208] instead of SSI_0 */
162 pin_func = au_readl(SYS_PINFUNC) | SYS_PF_S0;
163
164 /* Set GPIO[215:211] for LEDs */
165 pin_func |= 5 << 2;
166
167 /* Set GPIO[214:213] for more LEDs */
168 pin_func |= 5 << 12;
169
170 /* Set GPIO[207:200] instead of PCMCIA/LCD */
171 pin_func |= SYS_PF_LCD | SYS_PF_PC;
172 au_writel(pin_func, SYS_PINFUNC);
173
174 /*
175 * Enable speaker amplifier. This should
176 * be part of the audio driver.
177 */
178 alchemy_gpio_direction_output(209, 1);
179
180 pm_power_off = mirage_power_off;
181 _machine_halt = mirage_power_off;
182 _machine_restart = (void(*)(char *))mips_softreset;
183 }
184#endif
185
186#ifdef CONFIG_MIPS_BOSPORUS
187 pm_power_off = bosporus_power_off;
188 _machine_halt = bosporus_power_off;
189 _machine_restart = (void(*)(char *))mips_softreset;
190#endif
191 au_sync();
192}
193
194static int __init db1x00_init_irq(void)
195{
196#if defined(CONFIG_MIPS_MIRAGE)
197 irq_set_irq_type(AU1500_GPIO7_INT, IRQF_TRIGGER_RISING); /* TS pendown */
198#elif defined(CONFIG_MIPS_DB1550)
199 irq_set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
200 irq_set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW); /* CD1# */
201 irq_set_irq_type(AU1550_GPIO3_INT, IRQF_TRIGGER_LOW); /* CARD0# */
202 irq_set_irq_type(AU1550_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
203 irq_set_irq_type(AU1550_GPIO21_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
204 irq_set_irq_type(AU1550_GPIO22_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
205#elif defined(CONFIG_MIPS_DB1500)
206 irq_set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
207 irq_set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
208 irq_set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
209 irq_set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
210 irq_set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
211 irq_set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
212#elif defined(CONFIG_MIPS_DB1100)
213 irq_set_irq_type(AU1100_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
214 irq_set_irq_type(AU1100_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
215 irq_set_irq_type(AU1100_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
216 irq_set_irq_type(AU1100_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
217 irq_set_irq_type(AU1100_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
218 irq_set_irq_type(AU1100_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
219#elif defined(CONFIG_MIPS_DB1000)
220 irq_set_irq_type(AU1000_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
221 irq_set_irq_type(AU1000_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
222 irq_set_irq_type(AU1000_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
223 irq_set_irq_type(AU1000_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
224 irq_set_irq_type(AU1000_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
225 irq_set_irq_type(AU1000_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
226#endif
227 return 0;
228}
229arch_initcall(db1x00_init_irq);
diff --git a/arch/mips/alchemy/devboards/db1x00/platform.c b/arch/mips/alchemy/devboards/db1x00/platform.c
deleted file mode 100644
index 9e6b3d442acd..000000000000
--- a/arch/mips/alchemy/devboards/db1x00/platform.c
+++ /dev/null
@@ -1,316 +0,0 @@
1/*
2 * DBAu1xxx board platform device registration
3 *
4 * Copyright (C) 2009 Manuel Lauss
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/dma-mapping.h>
24#include <linux/platform_device.h>
25
26#include <asm/mach-au1x00/au1000.h>
27#include <asm/mach-au1x00/au1000_dma.h>
28#include <asm/mach-db1x00/bcsr.h>
29#include "../platform.h"
30
31struct pci_dev;
32
33/* DB1xxx PCMCIA interrupt sources:
34 * CD0/1 GPIO0/3
35 * STSCHG0/1 GPIO1/4
36 * CARD0/1 GPIO2/5
37 * Db1550: 0/1, 21/22, 3/5
38 */
39
40#define DB1XXX_HAS_PCMCIA
41#define F_SWAPPED (bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT)
42
43#if defined(CONFIG_MIPS_DB1000)
44#define DB1XXX_PCMCIA_CD0 AU1000_GPIO0_INT
45#define DB1XXX_PCMCIA_STSCHG0 AU1000_GPIO1_INT
46#define DB1XXX_PCMCIA_CARD0 AU1000_GPIO2_INT
47#define DB1XXX_PCMCIA_CD1 AU1000_GPIO3_INT
48#define DB1XXX_PCMCIA_STSCHG1 AU1000_GPIO4_INT
49#define DB1XXX_PCMCIA_CARD1 AU1000_GPIO5_INT
50#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */
51#define BOARD_FLASH_WIDTH 4 /* 32-bits */
52#elif defined(CONFIG_MIPS_DB1100)
53#define DB1XXX_PCMCIA_CD0 AU1100_GPIO0_INT
54#define DB1XXX_PCMCIA_STSCHG0 AU1100_GPIO1_INT
55#define DB1XXX_PCMCIA_CARD0 AU1100_GPIO2_INT
56#define DB1XXX_PCMCIA_CD1 AU1100_GPIO3_INT
57#define DB1XXX_PCMCIA_STSCHG1 AU1100_GPIO4_INT
58#define DB1XXX_PCMCIA_CARD1 AU1100_GPIO5_INT
59#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */
60#define BOARD_FLASH_WIDTH 4 /* 32-bits */
61#elif defined(CONFIG_MIPS_DB1500)
62#define DB1XXX_PCMCIA_CD0 AU1500_GPIO0_INT
63#define DB1XXX_PCMCIA_STSCHG0 AU1500_GPIO1_INT
64#define DB1XXX_PCMCIA_CARD0 AU1500_GPIO2_INT
65#define DB1XXX_PCMCIA_CD1 AU1500_GPIO3_INT
66#define DB1XXX_PCMCIA_STSCHG1 AU1500_GPIO4_INT
67#define DB1XXX_PCMCIA_CARD1 AU1500_GPIO5_INT
68#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */
69#define BOARD_FLASH_WIDTH 4 /* 32-bits */
70#elif defined(CONFIG_MIPS_DB1550)
71#define DB1XXX_PCMCIA_CD0 AU1550_GPIO0_INT
72#define DB1XXX_PCMCIA_STSCHG0 AU1550_GPIO21_INT
73#define DB1XXX_PCMCIA_CARD0 AU1550_GPIO3_INT
74#define DB1XXX_PCMCIA_CD1 AU1550_GPIO1_INT
75#define DB1XXX_PCMCIA_STSCHG1 AU1550_GPIO22_INT
76#define DB1XXX_PCMCIA_CARD1 AU1550_GPIO5_INT
77#define BOARD_FLASH_SIZE 0x08000000 /* 128MB */
78#define BOARD_FLASH_WIDTH 4 /* 32-bits */
79#else
80/* other board: no PCMCIA */
81#undef DB1XXX_HAS_PCMCIA
82#undef F_SWAPPED
83#define F_SWAPPED 0
84#if defined(CONFIG_MIPS_BOSPORUS)
85#define BOARD_FLASH_SIZE 0x01000000 /* 16MB */
86#define BOARD_FLASH_WIDTH 2 /* 16-bits */
87#elif defined(CONFIG_MIPS_MIRAGE)
88#define BOARD_FLASH_SIZE 0x04000000 /* 64MB */
89#define BOARD_FLASH_WIDTH 4 /* 32-bits */
90#endif
91#endif
92
93#ifdef CONFIG_PCI
94#ifdef CONFIG_MIPS_DB1500
95static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
96{
97 if ((slot < 12) || (slot > 13) || pin == 0)
98 return -1;
99 if (slot == 12)
100 return (pin == 1) ? AU1500_PCI_INTA : 0xff;
101 if (slot == 13) {
102 switch (pin) {
103 case 1: return AU1500_PCI_INTA;
104 case 2: return AU1500_PCI_INTB;
105 case 3: return AU1500_PCI_INTC;
106 case 4: return AU1500_PCI_INTD;
107 }
108 }
109 return -1;
110}
111#endif
112
113#ifdef CONFIG_MIPS_DB1550
114static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
115{
116 if ((slot < 11) || (slot > 13) || pin == 0)
117 return -1;
118 if (slot == 11)
119 return (pin == 1) ? AU1550_PCI_INTC : 0xff;
120 if (slot == 12) {
121 switch (pin) {
122 case 1: return AU1550_PCI_INTB;
123 case 2: return AU1550_PCI_INTC;
124 case 3: return AU1550_PCI_INTD;
125 case 4: return AU1550_PCI_INTA;
126 }
127 }
128 if (slot == 13) {
129 switch (pin) {
130 case 1: return AU1550_PCI_INTA;
131 case 2: return AU1550_PCI_INTB;
132 case 3: return AU1550_PCI_INTC;
133 case 4: return AU1550_PCI_INTD;
134 }
135 }
136 return -1;
137}
138#endif
139
140#ifdef CONFIG_MIPS_BOSPORUS
141static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
142{
143 if ((slot < 11) || (slot > 13) || pin == 0)
144 return -1;
145 if (slot == 12)
146 return (pin == 1) ? AU1500_PCI_INTA : 0xff;
147 if (slot == 11) {
148 switch (pin) {
149 case 1: return AU1500_PCI_INTA;
150 case 2: return AU1500_PCI_INTB;
151 default: return 0xff;
152 }
153 }
154 if (slot == 13) {
155 switch (pin) {
156 case 1: return AU1500_PCI_INTA;
157 case 2: return AU1500_PCI_INTB;
158 case 3: return AU1500_PCI_INTC;
159 case 4: return AU1500_PCI_INTD;
160 }
161 }
162 return -1;
163}
164#endif
165
166#ifdef CONFIG_MIPS_MIRAGE
167static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
168{
169 if ((slot < 11) || (slot > 13) || pin == 0)
170 return -1;
171 if (slot == 11)
172 return (pin == 1) ? AU1500_PCI_INTD : 0xff;
173 if (slot == 12)
174 return (pin == 3) ? AU1500_PCI_INTC : 0xff;
175 if (slot == 13) {
176 switch (pin) {
177 case 1: return AU1500_PCI_INTA;
178 case 2: return AU1500_PCI_INTB;
179 default: return 0xff;
180 }
181 }
182 return -1;
183}
184#endif
185
186static struct resource alchemy_pci_host_res[] = {
187 [0] = {
188 .start = AU1500_PCI_PHYS_ADDR,
189 .end = AU1500_PCI_PHYS_ADDR + 0xfff,
190 .flags = IORESOURCE_MEM,
191 },
192};
193
194static struct alchemy_pci_platdata db1xxx_pci_pd = {
195 .board_map_irq = db1xxx_map_pci_irq,
196};
197
198static struct platform_device db1xxx_pci_host_dev = {
199 .dev.platform_data = &db1xxx_pci_pd,
200 .name = "alchemy-pci",
201 .id = 0,
202 .num_resources = ARRAY_SIZE(alchemy_pci_host_res),
203 .resource = alchemy_pci_host_res,
204};
205
206static int __init db15x0_pci_init(void)
207{
208 return platform_device_register(&db1xxx_pci_host_dev);
209}
210/* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */
211arch_initcall(db15x0_pci_init);
212#endif
213
214#ifdef CONFIG_MIPS_DB1100
215static struct resource au1100_lcd_resources[] = {
216 [0] = {
217 .start = AU1100_LCD_PHYS_ADDR,
218 .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1,
219 .flags = IORESOURCE_MEM,
220 },
221 [1] = {
222 .start = AU1100_LCD_INT,
223 .end = AU1100_LCD_INT,
224 .flags = IORESOURCE_IRQ,
225 }
226};
227
228static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32);
229
230static struct platform_device au1100_lcd_device = {
231 .name = "au1100-lcd",
232 .id = 0,
233 .dev = {
234 .dma_mask = &au1100_lcd_dmamask,
235 .coherent_dma_mask = DMA_BIT_MASK(32),
236 },
237 .num_resources = ARRAY_SIZE(au1100_lcd_resources),
238 .resource = au1100_lcd_resources,
239};
240#endif
241
242static struct resource alchemy_ac97c_res[] = {
243 [0] = {
244 .start = AU1000_AC97_PHYS_ADDR,
245 .end = AU1000_AC97_PHYS_ADDR + 0xfff,
246 .flags = IORESOURCE_MEM,
247 },
248 [1] = {
249 .start = DMA_ID_AC97C_TX,
250 .end = DMA_ID_AC97C_TX,
251 .flags = IORESOURCE_DMA,
252 },
253 [2] = {
254 .start = DMA_ID_AC97C_RX,
255 .end = DMA_ID_AC97C_RX,
256 .flags = IORESOURCE_DMA,
257 },
258};
259
260static struct platform_device alchemy_ac97c_dev = {
261 .name = "alchemy-ac97c",
262 .id = -1,
263 .resource = alchemy_ac97c_res,
264 .num_resources = ARRAY_SIZE(alchemy_ac97c_res),
265};
266
267static struct platform_device alchemy_ac97c_dma_dev = {
268 .name = "alchemy-pcm-dma",
269 .id = 0,
270};
271
272static struct platform_device db1x00_codec_dev = {
273 .name = "ac97-codec",
274 .id = -1,
275};
276
277static struct platform_device db1x00_audio_dev = {
278 .name = "db1000-audio",
279};
280
281static int __init db1xxx_dev_init(void)
282{
283#ifdef DB1XXX_HAS_PCMCIA
284 db1x_register_pcmcia_socket(
285 AU1000_PCMCIA_ATTR_PHYS_ADDR,
286 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
287 AU1000_PCMCIA_MEM_PHYS_ADDR,
288 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
289 AU1000_PCMCIA_IO_PHYS_ADDR,
290 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
291 DB1XXX_PCMCIA_CARD0, DB1XXX_PCMCIA_CD0,
292 /*DB1XXX_PCMCIA_STSCHG0*/0, 0, 0);
293
294 db1x_register_pcmcia_socket(
295 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
296 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
297 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000,
298 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
299 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000,
300 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
301 DB1XXX_PCMCIA_CARD1, DB1XXX_PCMCIA_CD1,
302 /*DB1XXX_PCMCIA_STSCHG1*/0, 0, 1);
303#endif
304#ifdef CONFIG_MIPS_DB1100
305 platform_device_register(&au1100_lcd_device);
306#endif
307 db1x_register_norflash(BOARD_FLASH_SIZE, BOARD_FLASH_WIDTH, F_SWAPPED);
308
309 platform_device_register(&db1x00_codec_dev);
310 platform_device_register(&alchemy_ac97c_dma_dev);
311 platform_device_register(&alchemy_ac97c_dev);
312 platform_device_register(&db1x00_audio_dev);
313
314 return 0;
315}
316device_initcall(db1xxx_dev_init);
diff --git a/arch/mips/alchemy/devboards/pb1000/Makefile b/arch/mips/alchemy/devboards/pb1000/Makefile
deleted file mode 100644
index 97c6615ba2bb..000000000000
--- a/arch/mips/alchemy/devboards/pb1000/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
1#
2# Copyright 2000, 2008 MontaVista Software Inc.
3# Author: MontaVista Software, Inc. <source@mvista.com>
4#
5# Makefile for the Alchemy Semiconductor Pb1000 board.
6#
7
8obj-y := board_setup.o
diff --git a/arch/mips/alchemy/devboards/pb1000/board_setup.c b/arch/mips/alchemy/devboards/pb1000/board_setup.c
deleted file mode 100644
index e64fdcbf75d0..000000000000
--- a/arch/mips/alchemy/devboards/pb1000/board_setup.c
+++ /dev/null
@@ -1,209 +0,0 @@
1/*
2 * Copyright 2000, 2008 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc. <source@mvista.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26#include <linux/delay.h>
27#include <linux/gpio.h>
28#include <linux/init.h>
29#include <linux/interrupt.h>
30#include <linux/pm.h>
31#include <asm/mach-au1x00/au1000.h>
32#include <asm/mach-pb1x00/pb1000.h>
33#include <asm/reboot.h>
34#include <prom.h>
35
36#include "../platform.h"
37
38const char *get_system_type(void)
39{
40 return "Alchemy Pb1000";
41}
42
43static void board_reset(char *c)
44{
45 asm volatile ("jr %0" : : "r" (0xbfc00000));
46}
47
48static void board_power_off(void)
49{
50 while (1)
51 asm volatile (
52 " .set mips32 \n"
53 " wait \n"
54 " .set mips0 \n");
55}
56
57void __init board_setup(void)
58{
59 u32 pin_func, static_cfg0;
60 u32 sys_freqctrl, sys_clksrc;
61 u32 prid = read_c0_prid();
62
63 sys_freqctrl = 0;
64 sys_clksrc = 0;
65
66 /* Set AUX clock to 12 MHz * 8 = 96 MHz */
67 au_writel(8, SYS_AUXPLL);
68 alchemy_gpio1_input_enable();
69 udelay(100);
70
71#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
72 /* Zero and disable FREQ2 */
73 sys_freqctrl = au_readl(SYS_FREQCTRL0);
74 sys_freqctrl &= ~0xFFF00000;
75 au_writel(sys_freqctrl, SYS_FREQCTRL0);
76
77 /* Zero and disable USBH/USBD clocks */
78 sys_clksrc = au_readl(SYS_CLKSRC);
79 sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
80 SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
81 au_writel(sys_clksrc, SYS_CLKSRC);
82
83 sys_freqctrl = au_readl(SYS_FREQCTRL0);
84 sys_freqctrl &= ~0xFFF00000;
85
86 sys_clksrc = au_readl(SYS_CLKSRC);
87 sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
88 SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
89
90 switch (prid & 0x000000FF) {
91 case 0x00: /* DA */
92 case 0x01: /* HA */
93 case 0x02: /* HB */
94 /* CPU core freq to 48 MHz to slow it way down... */
95 au_writel(4, SYS_CPUPLL);
96
97 /*
98 * Setup 48 MHz FREQ2 from CPUPLL for USB Host
99 * FRDIV2 = 3 -> div by 8 of 384 MHz -> 48 MHz
100 */
101 sys_freqctrl |= (3 << SYS_FC_FRDIV2_BIT) | SYS_FC_FE2;
102 au_writel(sys_freqctrl, SYS_FREQCTRL0);
103
104 /* CPU core freq to 384 MHz */
105 au_writel(0x20, SYS_CPUPLL);
106
107 printk(KERN_INFO "Au1000: 48 MHz OHCI workaround enabled\n");
108 break;
109
110 default: /* HC and newer */
111 /* FREQ2 = aux / 2 = 48 MHz */
112 sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) |
113 SYS_FC_FE2 | SYS_FC_FS2;
114 au_writel(sys_freqctrl, SYS_FREQCTRL0);
115 break;
116 }
117
118 /*
119 * Route 48 MHz FREQ2 into USB Host and/or Device
120 */
121 sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MUH_BIT;
122 au_writel(sys_clksrc, SYS_CLKSRC);
123
124 /* Configure pins GPIO[14:9] as GPIO */
125 pin_func = au_readl(SYS_PINFUNC) & ~(SYS_PF_UR3 | SYS_PF_USB);
126
127 /* 2nd USB port is USB host */
128 pin_func |= SYS_PF_USB;
129
130 au_writel(pin_func, SYS_PINFUNC);
131
132 alchemy_gpio_direction_input(11);
133 alchemy_gpio_direction_input(13);
134 alchemy_gpio_direction_output(4, 0);
135 alchemy_gpio_direction_output(5, 0);
136#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
137
138 /* Make GPIO 15 an input (for interrupt line) */
139 pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_IRF;
140 /* We don't need I2S, so make it available for GPIO[31:29] */
141 pin_func |= SYS_PF_I2S;
142 au_writel(pin_func, SYS_PINFUNC);
143
144 alchemy_gpio_direction_input(15);
145
146 static_cfg0 = au_readl(MEM_STCFG0) & ~0xc00;
147 au_writel(static_cfg0, MEM_STCFG0);
148
149 /* configure RCE2* for LCD */
150 au_writel(0x00000004, MEM_STCFG2);
151
152 /* MEM_STTIME2 */
153 au_writel(0x09000000, MEM_STTIME2);
154
155 /* Set 32-bit base address decoding for RCE2* */
156 au_writel(0x10003ff0, MEM_STADDR2);
157
158 /*
159 * PCI CPLD setup
160 * Expand CE0 to cover PCI
161 */
162 au_writel(0x11803e40, MEM_STADDR1);
163
164 /* Burst visibility on */
165 au_writel(au_readl(MEM_STCFG0) | 0x1000, MEM_STCFG0);
166
167 au_writel(0x83, MEM_STCFG1); /* ewait enabled, flash timing */
168 au_writel(0x33030a10, MEM_STTIME1); /* slower timing for FPGA */
169
170 /* Setup the static bus controller */
171 au_writel(0x00000002, MEM_STCFG3); /* type = PCMCIA */
172 au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */
173 au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */
174
175 /*
176 * Enable Au1000 BCLK switching - note: sed1356 must not use
177 * its BCLK (Au1000 LCLK) for any timings
178 */
179 switch (prid & 0x000000FF) {
180 case 0x00: /* DA */
181 case 0x01: /* HA */
182 case 0x02: /* HB */
183 break;
184 default: /* HC and newer */
185 /*
186 * Enable sys bus clock divider when IDLE state or no bus
187 * activity.
188 */
189 au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
190 break;
191 }
192
193 pm_power_off = board_power_off;
194 _machine_halt = board_power_off;
195 _machine_restart = board_reset;
196}
197
198static int __init pb1000_init_irq(void)
199{
200 irq_set_irq_type(AU1000_GPIO15_INT, IRQF_TRIGGER_LOW);
201 return 0;
202}
203arch_initcall(pb1000_init_irq);
204
205static int __init pb1000_device_init(void)
206{
207 return db1x_register_norflash(8 * 1024 * 1024, 4, 0);
208}
209device_initcall(pb1000_device_init);
diff --git a/arch/mips/alchemy/devboards/pb1100/board_setup.c b/arch/mips/alchemy/devboards/pb1100.c
index d108fd573aaf..cff50d05ddd4 100644
--- a/arch/mips/alchemy/devboards/pb1100/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1100.c
@@ -1,42 +1,37 @@
1/* 1/*
2 * Copyright 2002, 2008 MontaVista Software Inc. 2 * Pb1100 board platform device registration
3 * Author: MontaVista Software, Inc. <source@mvista.com>
4 * 3 *
5 * This program is free software; you can redistribute it and/or modify it 4 * Copyright (C) 2009 Manuel Lauss
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 * 5 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 6 * This program is free software; you can redistribute it and/or modify
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 7 * it under the terms of the GNU General Public License as published by
12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 8 * the Free Software Foundation; either version 2 of the License, or
13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 9 * (at your option) any later version.
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
20 * 10 *
21 * You should have received a copy of the GNU General Public License along 11 * This program is distributed in the hope that it will be useful,
22 * with this program; if not, write to the Free Software Foundation, Inc., 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * 675 Mass Ave, Cambridge, MA 02139, USA. 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 */ 19 */
25 20
21#include <linux/delay.h>
26#include <linux/gpio.h> 22#include <linux/gpio.h>
27#include <linux/init.h> 23#include <linux/init.h>
28#include <linux/delay.h>
29#include <linux/interrupt.h> 24#include <linux/interrupt.h>
30 25#include <linux/dma-mapping.h>
26#include <linux/platform_device.h>
31#include <asm/mach-au1x00/au1000.h> 27#include <asm/mach-au1x00/au1000.h>
32#include <asm/mach-db1x00/bcsr.h> 28#include <asm/mach-db1x00/bcsr.h>
33
34#include <prom.h> 29#include <prom.h>
35 30#include "platform.h"
36 31
37const char *get_system_type(void) 32const char *get_system_type(void)
38{ 33{
39 return "Alchemy Pb1100"; 34 return "PB1100";
40} 35}
41 36
42void __init board_setup(void) 37void __init board_setup(void)
@@ -115,13 +110,58 @@ void __init board_setup(void)
115 } 110 }
116} 111}
117 112
118static int __init pb1100_init_irq(void) 113/******************************************************************************/
114
115static struct resource au1100_lcd_resources[] = {
116 [0] = {
117 .start = AU1100_LCD_PHYS_ADDR,
118 .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1,
119 .flags = IORESOURCE_MEM,
120 },
121 [1] = {
122 .start = AU1100_LCD_INT,
123 .end = AU1100_LCD_INT,
124 .flags = IORESOURCE_IRQ,
125 }
126};
127
128static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32);
129
130static struct platform_device au1100_lcd_device = {
131 .name = "au1100-lcd",
132 .id = 0,
133 .dev = {
134 .dma_mask = &au1100_lcd_dmamask,
135 .coherent_dma_mask = DMA_BIT_MASK(32),
136 },
137 .num_resources = ARRAY_SIZE(au1100_lcd_resources),
138 .resource = au1100_lcd_resources,
139};
140
141static int __init pb1100_dev_init(void)
119{ 142{
143 int swapped;
144
120 irq_set_irq_type(AU1100_GPIO9_INT, IRQF_TRIGGER_LOW); /* PCCD# */ 145 irq_set_irq_type(AU1100_GPIO9_INT, IRQF_TRIGGER_LOW); /* PCCD# */
121 irq_set_irq_type(AU1100_GPIO10_INT, IRQF_TRIGGER_LOW); /* PCSTSCHG# */ 146 irq_set_irq_type(AU1100_GPIO10_INT, IRQF_TRIGGER_LOW); /* PCSTSCHG# */
122 irq_set_irq_type(AU1100_GPIO11_INT, IRQF_TRIGGER_LOW); /* PCCard# */ 147 irq_set_irq_type(AU1100_GPIO11_INT, IRQF_TRIGGER_LOW); /* PCCard# */
123 irq_set_irq_type(AU1100_GPIO13_INT, IRQF_TRIGGER_LOW); /* DC_IRQ# */ 148 irq_set_irq_type(AU1100_GPIO13_INT, IRQF_TRIGGER_LOW); /* DC_IRQ# */
124 149
150 /* PCMCIA. single socket, identical to Pb1500 */
151 db1x_register_pcmcia_socket(
152 AU1000_PCMCIA_ATTR_PHYS_ADDR,
153 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
154 AU1000_PCMCIA_MEM_PHYS_ADDR,
155 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
156 AU1000_PCMCIA_IO_PHYS_ADDR,
157 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
158 AU1100_GPIO11_INT, AU1100_GPIO9_INT, /* card / insert */
159 /*AU1100_GPIO10_INT*/0, 0, 0); /* stschg / eject / id */
160
161 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT;
162 db1x_register_norflash(64 * 1024 * 1024, 4, swapped);
163 platform_device_register(&au1100_lcd_device);
164
125 return 0; 165 return 0;
126} 166}
127arch_initcall(pb1100_init_irq); 167device_initcall(pb1100_dev_init);
diff --git a/arch/mips/alchemy/devboards/pb1100/Makefile b/arch/mips/alchemy/devboards/pb1100/Makefile
deleted file mode 100644
index 7e3756c83fe5..000000000000
--- a/arch/mips/alchemy/devboards/pb1100/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
1#
2# Copyright 2000, 2001, 2008 MontaVista Software Inc.
3# Author: MontaVista Software, Inc. <source@mvista.com>
4#
5# Makefile for the Alchemy Semiconductor Pb1100 board.
6#
7
8obj-y := board_setup.o platform.o
diff --git a/arch/mips/alchemy/devboards/pb1100/platform.c b/arch/mips/alchemy/devboards/pb1100/platform.c
deleted file mode 100644
index 9c57c01a68c4..000000000000
--- a/arch/mips/alchemy/devboards/pb1100/platform.c
+++ /dev/null
@@ -1,77 +0,0 @@
1/*
2 * Pb1100 board platform device registration
3 *
4 * Copyright (C) 2009 Manuel Lauss
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/init.h>
22#include <linux/dma-mapping.h>
23#include <linux/platform_device.h>
24
25#include <asm/mach-au1x00/au1000.h>
26#include <asm/mach-db1x00/bcsr.h>
27
28#include "../platform.h"
29
30static struct resource au1100_lcd_resources[] = {
31 [0] = {
32 .start = AU1100_LCD_PHYS_ADDR,
33 .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1,
34 .flags = IORESOURCE_MEM,
35 },
36 [1] = {
37 .start = AU1100_LCD_INT,
38 .end = AU1100_LCD_INT,
39 .flags = IORESOURCE_IRQ,
40 }
41};
42
43static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32);
44
45static struct platform_device au1100_lcd_device = {
46 .name = "au1100-lcd",
47 .id = 0,
48 .dev = {
49 .dma_mask = &au1100_lcd_dmamask,
50 .coherent_dma_mask = DMA_BIT_MASK(32),
51 },
52 .num_resources = ARRAY_SIZE(au1100_lcd_resources),
53 .resource = au1100_lcd_resources,
54};
55
56static int __init pb1100_dev_init(void)
57{
58 int swapped;
59
60 /* PCMCIA. single socket, identical to Pb1500 */
61 db1x_register_pcmcia_socket(
62 AU1000_PCMCIA_ATTR_PHYS_ADDR,
63 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
64 AU1000_PCMCIA_MEM_PHYS_ADDR,
65 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
66 AU1000_PCMCIA_IO_PHYS_ADDR,
67 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
68 AU1100_GPIO11_INT, AU1100_GPIO9_INT, /* card / insert */
69 /*AU1100_GPIO10_INT*/0, 0, 0); /* stschg / eject / id */
70
71 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT;
72 db1x_register_norflash(64 * 1024 * 1024, 4, swapped);
73 platform_device_register(&au1100_lcd_device);
74
75 return 0;
76}
77device_initcall(pb1100_dev_init);
diff --git a/arch/mips/alchemy/devboards/pb1200/Makefile b/arch/mips/alchemy/devboards/pb1200/Makefile
deleted file mode 100644
index 18c1bd53e4c0..000000000000
--- a/arch/mips/alchemy/devboards/pb1200/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
1#
2# Makefile for the Alchemy Semiconductor Pb1200/DBAu1200 boards.
3#
4
5obj-y := board_setup.o platform.o
diff --git a/arch/mips/alchemy/devboards/pb1200/board_setup.c b/arch/mips/alchemy/devboards/pb1200/board_setup.c
deleted file mode 100644
index 6d06b07c2381..000000000000
--- a/arch/mips/alchemy/devboards/pb1200/board_setup.c
+++ /dev/null
@@ -1,174 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Alchemy Pb1200/Db1200 board setup.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27#include <linux/init.h>
28#include <linux/interrupt.h>
29#include <linux/sched.h>
30
31#include <asm/mach-au1x00/au1000.h>
32#include <asm/mach-db1x00/bcsr.h>
33
34#ifdef CONFIG_MIPS_PB1200
35#include <asm/mach-pb1x00/pb1200.h>
36#endif
37
38#ifdef CONFIG_MIPS_DB1200
39#include <asm/mach-db1x00/db1200.h>
40#define PB1200_INT_BEGIN DB1200_INT_BEGIN
41#define PB1200_INT_END DB1200_INT_END
42#endif
43
44#include <prom.h>
45
46const char *get_system_type(void)
47{
48 return "Alchemy Pb1200";
49}
50
51void __init board_setup(void)
52{
53 printk(KERN_INFO "AMD Alchemy Pb1200 Board\n");
54 bcsr_init(PB1200_BCSR_PHYS_ADDR,
55 PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS);
56
57#if 0
58 {
59 u32 pin_func;
60
61 /*
62 * Enable PSC1 SYNC for AC97. Normaly done in audio driver,
63 * but it is board specific code, so put it here.
64 */
65 pin_func = au_readl(SYS_PINFUNC);
66 au_sync();
67 pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1;
68 au_writel(pin_func, SYS_PINFUNC);
69
70 au_writel(0, (u32)bcsr | 0x10); /* turn off PCMCIA power */
71 au_sync();
72 }
73#endif
74
75#if defined(CONFIG_I2C_AU1550)
76 {
77 u32 freq0, clksrc;
78 u32 pin_func;
79
80 /* Select SMBus in CPLD */
81 bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0);
82
83 pin_func = au_readl(SYS_PINFUNC);
84 au_sync();
85 pin_func &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B);
86 /* Set GPIOs correctly */
87 pin_func |= 2 << 17;
88 au_writel(pin_func, SYS_PINFUNC);
89 au_sync();
90
91 /* The I2C driver depends on 50 MHz clock */
92 freq0 = au_readl(SYS_FREQCTRL0);
93 au_sync();
94 freq0 &= ~(SYS_FC_FRDIV1_MASK | SYS_FC_FS1 | SYS_FC_FE1);
95 freq0 |= 3 << SYS_FC_FRDIV1_BIT;
96 /* 396 MHz / (3 + 1) * 2 == 49.5 MHz */
97 au_writel(freq0, SYS_FREQCTRL0);
98 au_sync();
99 freq0 |= SYS_FC_FE1;
100 au_writel(freq0, SYS_FREQCTRL0);
101 au_sync();
102
103 clksrc = au_readl(SYS_CLKSRC);
104 au_sync();
105 clksrc &= ~(SYS_CS_CE0 | SYS_CS_DE0 | SYS_CS_ME0_MASK);
106 /* Bit 22 is EXTCLK0 for PSC0 */
107 clksrc |= SYS_CS_MUX_FQ1 << SYS_CS_ME0_BIT;
108 au_writel(clksrc, SYS_CLKSRC);
109 au_sync();
110 }
111#endif
112
113 /*
114 * The Pb1200 development board uses external MUX for PSC0 to
115 * support SMB/SPI. bcsr_resets bit 12: 0=SMB 1=SPI
116 */
117#ifdef CONFIG_I2C_AU1550
118 bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0);
119#endif
120 au_sync();
121}
122
123static int __init pb1200_init_irq(void)
124{
125 /* We have a problem with CPLD rev 3. */
126 if (BCSR_WHOAMI_CPLD(bcsr_read(BCSR_WHOAMI)) <= 3) {
127 printk(KERN_ERR "WARNING!!!\n");
128 printk(KERN_ERR "WARNING!!!\n");
129 printk(KERN_ERR "WARNING!!!\n");
130 printk(KERN_ERR "WARNING!!!\n");
131 printk(KERN_ERR "WARNING!!!\n");
132 printk(KERN_ERR "WARNING!!!\n");
133 printk(KERN_ERR "Pb1200 must be at CPLD rev 4. Please have Pb1200\n");
134 printk(KERN_ERR "updated to latest revision. This software will\n");
135 printk(KERN_ERR "not work on anything less than CPLD rev 4.\n");
136 printk(KERN_ERR "WARNING!!!\n");
137 printk(KERN_ERR "WARNING!!!\n");
138 printk(KERN_ERR "WARNING!!!\n");
139 printk(KERN_ERR "WARNING!!!\n");
140 printk(KERN_ERR "WARNING!!!\n");
141 printk(KERN_ERR "WARNING!!!\n");
142 panic("Game over. Your score is 0.");
143 }
144
145 irq_set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW);
146 bcsr_init_irq(PB1200_INT_BEGIN, PB1200_INT_END, AU1200_GPIO7_INT);
147
148 return 0;
149}
150arch_initcall(pb1200_init_irq);
151
152
153int board_au1200fb_panel(void)
154{
155 return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f;
156}
157
158int board_au1200fb_panel_init(void)
159{
160 /* Apply power */
161 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
162 BCSR_BOARD_LCDBL);
163 /* printk(KERN_DEBUG "board_au1200fb_panel_init()\n"); */
164 return 0;
165}
166
167int board_au1200fb_panel_shutdown(void)
168{
169 /* Remove power */
170 bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
171 BCSR_BOARD_LCDBL, 0);
172 /* printk(KERN_DEBUG "board_au1200fb_panel_shutdown()\n"); */
173 return 0;
174}
diff --git a/arch/mips/alchemy/devboards/pb1200/platform.c b/arch/mips/alchemy/devboards/pb1200/platform.c
deleted file mode 100644
index 54f7f7b0676e..000000000000
--- a/arch/mips/alchemy/devboards/pb1200/platform.c
+++ /dev/null
@@ -1,339 +0,0 @@
1/*
2 * Pb1200/DBAu1200 board platform device registration
3 *
4 * Copyright (C) 2008 MontaVista Software Inc. <source@mvista.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/dma-mapping.h>
22#include <linux/init.h>
23#include <linux/leds.h>
24#include <linux/platform_device.h>
25#include <linux/smc91x.h>
26
27#include <asm/mach-au1x00/au1000.h>
28#include <asm/mach-au1x00/au1100_mmc.h>
29#include <asm/mach-au1x00/au1xxx_dbdma.h>
30#include <asm/mach-db1x00/bcsr.h>
31#include <asm/mach-pb1x00/pb1200.h>
32
33#include "../platform.h"
34
35static int mmc_activity;
36
37static void pb1200mmc0_set_power(void *mmc_host, int state)
38{
39 if (state)
40 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD0PWR);
41 else
42 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD0PWR, 0);
43
44 msleep(1);
45}
46
47static int pb1200mmc0_card_readonly(void *mmc_host)
48{
49 return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 1 : 0;
50}
51
52static int pb1200mmc0_card_inserted(void *mmc_host)
53{
54 return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT) ? 1 : 0;
55}
56
57static void pb1200_mmcled_set(struct led_classdev *led,
58 enum led_brightness brightness)
59{
60 if (brightness != LED_OFF) {
61 if (++mmc_activity == 1)
62 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0);
63 } else {
64 if (--mmc_activity == 0)
65 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0);
66 }
67}
68
69static struct led_classdev pb1200mmc_led = {
70 .brightness_set = pb1200_mmcled_set,
71};
72
73static void pb1200mmc1_set_power(void *mmc_host, int state)
74{
75 if (state)
76 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD1PWR);
77 else
78 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD1PWR, 0);
79
80 msleep(1);
81}
82
83static int pb1200mmc1_card_readonly(void *mmc_host)
84{
85 return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD1WP) ? 1 : 0;
86}
87
88static int pb1200mmc1_card_inserted(void *mmc_host)
89{
90 return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0;
91}
92
93static struct au1xmmc_platform_data pb1200mmc_platdata[2] = {
94 [0] = {
95 .set_power = pb1200mmc0_set_power,
96 .card_inserted = pb1200mmc0_card_inserted,
97 .card_readonly = pb1200mmc0_card_readonly,
98 .cd_setup = NULL, /* use poll-timer in driver */
99 .led = &pb1200mmc_led,
100 },
101 [1] = {
102 .set_power = pb1200mmc1_set_power,
103 .card_inserted = pb1200mmc1_card_inserted,
104 .card_readonly = pb1200mmc1_card_readonly,
105 .cd_setup = NULL, /* use poll-timer in driver */
106 .led = &pb1200mmc_led,
107 },
108};
109
110static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32);
111
112static struct resource au1200_mmc0_res[] = {
113 [0] = {
114 .start = AU1100_SD0_PHYS_ADDR,
115 .end = AU1100_SD0_PHYS_ADDR + 0xfff,
116 .flags = IORESOURCE_MEM,
117 },
118 [1] = {
119 .start = AU1200_SD_INT,
120 .end = AU1200_SD_INT,
121 .flags = IORESOURCE_IRQ,
122 },
123 [2] = {
124 .start = AU1200_DSCR_CMD0_SDMS_TX0,
125 .end = AU1200_DSCR_CMD0_SDMS_TX0,
126 .flags = IORESOURCE_DMA,
127 },
128 [3] = {
129 .start = AU1200_DSCR_CMD0_SDMS_RX0,
130 .end = AU1200_DSCR_CMD0_SDMS_RX0,
131 .flags = IORESOURCE_DMA,
132 }
133};
134
135static struct platform_device pb1200_mmc0_dev = {
136 .name = "au1xxx-mmc",
137 .id = 0,
138 .dev = {
139 .dma_mask = &au1xxx_mmc_dmamask,
140 .coherent_dma_mask = DMA_BIT_MASK(32),
141 .platform_data = &pb1200mmc_platdata[0],
142 },
143 .num_resources = ARRAY_SIZE(au1200_mmc0_res),
144 .resource = au1200_mmc0_res,
145};
146
147static struct resource au1200_mmc1_res[] = {
148 [0] = {
149 .start = AU1100_SD1_PHYS_ADDR,
150 .end = AU1100_SD1_PHYS_ADDR + 0xfff,
151 .flags = IORESOURCE_MEM,
152 },
153 [1] = {
154 .start = AU1200_SD_INT,
155 .end = AU1200_SD_INT,
156 .flags = IORESOURCE_IRQ,
157 },
158 [2] = {
159 .start = AU1200_DSCR_CMD0_SDMS_TX1,
160 .end = AU1200_DSCR_CMD0_SDMS_TX1,
161 .flags = IORESOURCE_DMA,
162 },
163 [3] = {
164 .start = AU1200_DSCR_CMD0_SDMS_RX1,
165 .end = AU1200_DSCR_CMD0_SDMS_RX1,
166 .flags = IORESOURCE_DMA,
167 }
168};
169
170static struct platform_device pb1200_mmc1_dev = {
171 .name = "au1xxx-mmc",
172 .id = 1,
173 .dev = {
174 .dma_mask = &au1xxx_mmc_dmamask,
175 .coherent_dma_mask = DMA_BIT_MASK(32),
176 .platform_data = &pb1200mmc_platdata[1],
177 },
178 .num_resources = ARRAY_SIZE(au1200_mmc1_res),
179 .resource = au1200_mmc1_res,
180};
181
182
183static struct resource ide_resources[] = {
184 [0] = {
185 .start = IDE_PHYS_ADDR,
186 .end = IDE_PHYS_ADDR + IDE_PHYS_LEN - 1,
187 .flags = IORESOURCE_MEM
188 },
189 [1] = {
190 .start = IDE_INT,
191 .end = IDE_INT,
192 .flags = IORESOURCE_IRQ
193 },
194 [2] = {
195 .start = AU1200_DSCR_CMD0_DMA_REQ1,
196 .end = AU1200_DSCR_CMD0_DMA_REQ1,
197 .flags = IORESOURCE_DMA,
198 },
199};
200
201static u64 ide_dmamask = DMA_BIT_MASK(32);
202
203static struct platform_device ide_device = {
204 .name = "au1200-ide",
205 .id = 0,
206 .dev = {
207 .dma_mask = &ide_dmamask,
208 .coherent_dma_mask = DMA_BIT_MASK(32),
209 },
210 .num_resources = ARRAY_SIZE(ide_resources),
211 .resource = ide_resources
212};
213
214static struct smc91x_platdata smc_data = {
215 .flags = SMC91X_NOWAIT | SMC91X_USE_16BIT,
216 .leda = RPC_LED_100_10,
217 .ledb = RPC_LED_TX_RX,
218};
219
220static struct resource smc91c111_resources[] = {
221 [0] = {
222 .name = "smc91x-regs",
223 .start = SMC91C111_PHYS_ADDR,
224 .end = SMC91C111_PHYS_ADDR + 0xf,
225 .flags = IORESOURCE_MEM
226 },
227 [1] = {
228 .start = SMC91C111_INT,
229 .end = SMC91C111_INT,
230 .flags = IORESOURCE_IRQ
231 },
232};
233
234static struct platform_device smc91c111_device = {
235 .dev = {
236 .platform_data = &smc_data,
237 },
238 .name = "smc91x",
239 .id = -1,
240 .num_resources = ARRAY_SIZE(smc91c111_resources),
241 .resource = smc91c111_resources
242};
243
244static struct resource au1200_psc0_res[] = {
245 [0] = {
246 .start = AU1550_PSC0_PHYS_ADDR,
247 .end = AU1550_PSC0_PHYS_ADDR + 0xfff,
248 .flags = IORESOURCE_MEM,
249 },
250 [1] = {
251 .start = AU1200_PSC0_INT,
252 .end = AU1200_PSC0_INT,
253 .flags = IORESOURCE_IRQ,
254 },
255 [2] = {
256 .start = AU1200_DSCR_CMD0_PSC0_TX,
257 .end = AU1200_DSCR_CMD0_PSC0_TX,
258 .flags = IORESOURCE_DMA,
259 },
260 [3] = {
261 .start = AU1200_DSCR_CMD0_PSC0_RX,
262 .end = AU1200_DSCR_CMD0_PSC0_RX,
263 .flags = IORESOURCE_DMA,
264 },
265};
266
267static struct platform_device pb1200_i2c_dev = {
268 .name = "au1xpsc_smbus",
269 .id = 0, /* bus number */
270 .num_resources = ARRAY_SIZE(au1200_psc0_res),
271 .resource = au1200_psc0_res,
272};
273
274static struct resource au1200_lcd_res[] = {
275 [0] = {
276 .start = AU1200_LCD_PHYS_ADDR,
277 .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1,
278 .flags = IORESOURCE_MEM,
279 },
280 [1] = {
281 .start = AU1200_LCD_INT,
282 .end = AU1200_LCD_INT,
283 .flags = IORESOURCE_IRQ,
284 }
285};
286
287static u64 au1200_lcd_dmamask = DMA_BIT_MASK(32);
288
289static struct platform_device au1200_lcd_dev = {
290 .name = "au1200-lcd",
291 .id = 0,
292 .dev = {
293 .dma_mask = &au1200_lcd_dmamask,
294 .coherent_dma_mask = DMA_BIT_MASK(32),
295 },
296 .num_resources = ARRAY_SIZE(au1200_lcd_res),
297 .resource = au1200_lcd_res,
298};
299
300static struct platform_device *board_platform_devices[] __initdata = {
301 &ide_device,
302 &smc91c111_device,
303 &pb1200_i2c_dev,
304 &pb1200_mmc0_dev,
305 &pb1200_mmc1_dev,
306 &au1200_lcd_dev,
307};
308
309static int __init board_register_devices(void)
310{
311 int swapped;
312
313 db1x_register_pcmcia_socket(
314 AU1000_PCMCIA_ATTR_PHYS_ADDR,
315 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
316 AU1000_PCMCIA_MEM_PHYS_ADDR,
317 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
318 AU1000_PCMCIA_IO_PHYS_ADDR,
319 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
320 PB1200_PC0_INT, PB1200_PC0_INSERT_INT,
321 /*PB1200_PC0_STSCHG_INT*/0, PB1200_PC0_EJECT_INT, 0);
322
323 db1x_register_pcmcia_socket(
324 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008000000,
325 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1,
326 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008000000,
327 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008400000 - 1,
328 AU1000_PCMCIA_IO_PHYS_ADDR + 0x008000000,
329 AU1000_PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1,
330 PB1200_PC1_INT, PB1200_PC1_INSERT_INT,
331 /*PB1200_PC1_STSCHG_INT*/0, PB1200_PC1_EJECT_INT, 1);
332
333 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT;
334 db1x_register_norflash(128 * 1024 * 1024, 2, swapped);
335
336 return platform_add_devices(board_platform_devices,
337 ARRAY_SIZE(board_platform_devices));
338}
339device_initcall(board_register_devices);
diff --git a/arch/mips/alchemy/devboards/pb1500/board_setup.c b/arch/mips/alchemy/devboards/pb1500.c
index 37c1883b5ea9..e7b807b3ec51 100644
--- a/arch/mips/alchemy/devboards/pb1500/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1500.c
@@ -1,41 +1,37 @@
1/* 1/*
2 * Copyright 2000, 2008 MontaVista Software Inc. 2 * Pb1500 board support.
3 * Author: MontaVista Software, Inc. <source@mvista.com>
4 * 3 *
5 * This program is free software; you can redistribute it and/or modify it 4 * Copyright (C) 2009 Manuel Lauss
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 * 5 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 6 * This program is free software; you can redistribute it and/or modify
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 7 * it under the terms of the GNU General Public License as published by
12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 8 * the Free Software Foundation; either version 2 of the License, or
13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 9 * (at your option) any later version.
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
20 * 10 *
21 * You should have received a copy of the GNU General Public License along 11 * This program is distributed in the hope that it will be useful,
22 * with this program; if not, write to the Free Software Foundation, Inc., 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * 675 Mass Ave, Cambridge, MA 02139, USA. 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 */ 19 */
25 20
26#include <linux/delay.h> 21#include <linux/delay.h>
22#include <linux/dma-mapping.h>
27#include <linux/gpio.h> 23#include <linux/gpio.h>
28#include <linux/init.h> 24#include <linux/init.h>
29#include <linux/interrupt.h> 25#include <linux/interrupt.h>
30 26#include <linux/platform_device.h>
31#include <asm/mach-au1x00/au1000.h> 27#include <asm/mach-au1x00/au1000.h>
32#include <asm/mach-db1x00/bcsr.h> 28#include <asm/mach-db1x00/bcsr.h>
33
34#include <prom.h> 29#include <prom.h>
30#include "platform.h"
35 31
36const char *get_system_type(void) 32const char *get_system_type(void)
37{ 33{
38 return "Alchemy Pb1500"; 34 return "PB1500";
39} 35}
40 36
41void __init board_setup(void) 37void __init board_setup(void)
@@ -123,17 +119,80 @@ void __init board_setup(void)
123 } 119 }
124} 120}
125 121
126static int __init pb1500_init_irq(void) 122/******************************************************************************/
123
124static int pb1500_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
127{ 125{
128 irq_set_irq_type(AU1500_GPIO9_INT, IRQF_TRIGGER_LOW); /* CD0# */ 126 if ((slot < 12) || (slot > 13) || pin == 0)
129 irq_set_irq_type(AU1500_GPIO10_INT, IRQF_TRIGGER_LOW); /* CARD0 */ 127 return -1;
130 irq_set_irq_type(AU1500_GPIO11_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ 128 if (slot == 12)
129 return (pin == 1) ? AU1500_PCI_INTA : 0xff;
130 if (slot == 13) {
131 switch (pin) {
132 case 1: return AU1500_PCI_INTA;
133 case 2: return AU1500_PCI_INTB;
134 case 3: return AU1500_PCI_INTC;
135 case 4: return AU1500_PCI_INTD;
136 }
137 }
138 return -1;
139}
140
141static struct resource alchemy_pci_host_res[] = {
142 [0] = {
143 .start = AU1500_PCI_PHYS_ADDR,
144 .end = AU1500_PCI_PHYS_ADDR + 0xfff,
145 .flags = IORESOURCE_MEM,
146 },
147};
148
149static struct alchemy_pci_platdata pb1500_pci_pd = {
150 .board_map_irq = pb1500_map_pci_irq,
151 .pci_cfg_set = PCI_CONFIG_AEN | PCI_CONFIG_R2H | PCI_CONFIG_R1H |
152 PCI_CONFIG_CH |
153#if defined(__MIPSEB__)
154 PCI_CONFIG_SIC_HWA_DAT | PCI_CONFIG_SM,
155#else
156 0,
157#endif
158};
159
160static struct platform_device pb1500_pci_host = {
161 .dev.platform_data = &pb1500_pci_pd,
162 .name = "alchemy-pci",
163 .id = 0,
164 .num_resources = ARRAY_SIZE(alchemy_pci_host_res),
165 .resource = alchemy_pci_host_res,
166};
167
168static int __init pb1500_dev_init(void)
169{
170 int swapped;
171
172 irq_set_irq_type(AU1500_GPIO9_INT, IRQF_TRIGGER_LOW); /* CD0# */
173 irq_set_irq_type(AU1500_GPIO10_INT, IRQF_TRIGGER_LOW); /* CARD0 */
174 irq_set_irq_type(AU1500_GPIO11_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
131 irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH); 175 irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
132 irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW); 176 irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
133 irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW); 177 irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
134 irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW); 178 irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
135 irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW); 179 irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
136 180
181 /* PCMCIA. single socket, identical to Pb1100 */
182 db1x_register_pcmcia_socket(
183 AU1000_PCMCIA_ATTR_PHYS_ADDR,
184 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
185 AU1000_PCMCIA_MEM_PHYS_ADDR,
186 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
187 AU1000_PCMCIA_IO_PHYS_ADDR,
188 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
189 AU1500_GPIO11_INT, AU1500_GPIO9_INT, /* card / insert */
190 /*AU1500_GPIO10_INT*/0, 0, 0); /* stschg / eject / id */
191
192 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT;
193 db1x_register_norflash(64 * 1024 * 1024, 4, swapped);
194 platform_device_register(&pb1500_pci_host);
195
137 return 0; 196 return 0;
138} 197}
139arch_initcall(pb1500_init_irq); 198arch_initcall(pb1500_dev_init);
diff --git a/arch/mips/alchemy/devboards/pb1500/Makefile b/arch/mips/alchemy/devboards/pb1500/Makefile
deleted file mode 100644
index e83b151b5b63..000000000000
--- a/arch/mips/alchemy/devboards/pb1500/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
1#
2# Copyright 2000, 2001, 2008 MontaVista Software Inc.
3# Author: MontaVista Software, Inc. <source@mvista.com>
4#
5# Makefile for the Alchemy Semiconductor Pb1500 board.
6#
7
8obj-y := board_setup.o platform.o
diff --git a/arch/mips/alchemy/devboards/pb1500/platform.c b/arch/mips/alchemy/devboards/pb1500/platform.c
deleted file mode 100644
index 1e52a01bac00..000000000000
--- a/arch/mips/alchemy/devboards/pb1500/platform.c
+++ /dev/null
@@ -1,94 +0,0 @@
1/*
2 * Pb1500 board platform device registration
3 *
4 * Copyright (C) 2009 Manuel Lauss
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/dma-mapping.h>
22#include <linux/init.h>
23#include <linux/platform_device.h>
24#include <asm/mach-au1x00/au1000.h>
25#include <asm/mach-db1x00/bcsr.h>
26
27#include "../platform.h"
28
29static int pb1500_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
30{
31 if ((slot < 12) || (slot > 13) || pin == 0)
32 return -1;
33 if (slot == 12)
34 return (pin == 1) ? AU1500_PCI_INTA : 0xff;
35 if (slot == 13) {
36 switch (pin) {
37 case 1: return AU1500_PCI_INTA;
38 case 2: return AU1500_PCI_INTB;
39 case 3: return AU1500_PCI_INTC;
40 case 4: return AU1500_PCI_INTD;
41 }
42 }
43 return -1;
44}
45
46static struct resource alchemy_pci_host_res[] = {
47 [0] = {
48 .start = AU1500_PCI_PHYS_ADDR,
49 .end = AU1500_PCI_PHYS_ADDR + 0xfff,
50 .flags = IORESOURCE_MEM,
51 },
52};
53
54static struct alchemy_pci_platdata pb1500_pci_pd = {
55 .board_map_irq = pb1500_map_pci_irq,
56 .pci_cfg_set = PCI_CONFIG_AEN | PCI_CONFIG_R2H | PCI_CONFIG_R1H |
57 PCI_CONFIG_CH |
58#if defined(__MIPSEB__)
59 PCI_CONFIG_SIC_HWA_DAT | PCI_CONFIG_SM,
60#else
61 0,
62#endif
63};
64
65static struct platform_device pb1500_pci_host = {
66 .dev.platform_data = &pb1500_pci_pd,
67 .name = "alchemy-pci",
68 .id = 0,
69 .num_resources = ARRAY_SIZE(alchemy_pci_host_res),
70 .resource = alchemy_pci_host_res,
71};
72
73static int __init pb1500_dev_init(void)
74{
75 int swapped;
76
77 /* PCMCIA. single socket, identical to Pb1100 */
78 db1x_register_pcmcia_socket(
79 AU1000_PCMCIA_ATTR_PHYS_ADDR,
80 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
81 AU1000_PCMCIA_MEM_PHYS_ADDR,
82 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
83 AU1000_PCMCIA_IO_PHYS_ADDR,
84 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
85 AU1500_GPIO11_INT, AU1500_GPIO9_INT, /* card / insert */
86 /*AU1500_GPIO10_INT*/0, 0, 0); /* stschg / eject / id */
87
88 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT;
89 db1x_register_norflash(64 * 1024 * 1024, 4, swapped);
90 platform_device_register(&pb1500_pci_host);
91
92 return 0;
93}
94arch_initcall(pb1500_dev_init);
diff --git a/arch/mips/alchemy/devboards/pb1550/platform.c b/arch/mips/alchemy/devboards/pb1550.c
index a4604b8a349e..b37e7de8d920 100644
--- a/arch/mips/alchemy/devboards/pb1550/platform.c
+++ b/arch/mips/alchemy/devboards/pb1550.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Pb1550 board platform device registration 2 * Pb1550 board support.
3 * 3 *
4 * Copyright (C) 2009 Manuel Lauss 4 * Copyright (C) 2009-2011 Manuel Lauss
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by 7 * it under the terms of the GNU General Public License as published by
@@ -20,13 +20,44 @@
20 20
21#include <linux/dma-mapping.h> 21#include <linux/dma-mapping.h>
22#include <linux/init.h> 22#include <linux/init.h>
23#include <linux/interrupt.h>
23#include <linux/platform_device.h> 24#include <linux/platform_device.h>
24#include <asm/mach-au1x00/au1000.h> 25#include <asm/mach-au1x00/au1000.h>
25#include <asm/mach-au1x00/au1xxx_dbdma.h> 26#include <asm/mach-au1x00/au1xxx_dbdma.h>
26#include <asm/mach-pb1x00/pb1550.h> 27#include <asm/mach-au1x00/au1550nd.h>
28#include <asm/mach-au1x00/gpio.h>
27#include <asm/mach-db1x00/bcsr.h> 29#include <asm/mach-db1x00/bcsr.h>
30#include "platform.h"
28 31
29#include "../platform.h" 32const char *get_system_type(void)
33{
34 return "PB1550";
35}
36
37void __init board_setup(void)
38{
39 u32 pin_func;
40
41 bcsr_init(PB1550_BCSR_PHYS_ADDR,
42 PB1550_BCSR_PHYS_ADDR + PB1550_BCSR_HEXLED_OFS);
43
44 alchemy_gpio2_enable();
45
46 /*
47 * Enable PSC1 SYNC for AC'97. Normaly done in audio driver,
48 * but it is board specific code, so put it here.
49 */
50 pin_func = au_readl(SYS_PINFUNC);
51 au_sync();
52 pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1;
53 au_writel(pin_func, SYS_PINFUNC);
54
55 bcsr_write(BCSR_PCMCIA, 0); /* turn off PCMCIA power */
56
57 printk(KERN_INFO "AMD Alchemy Pb1550 Board\n");
58}
59
60/******************************************************************************/
30 61
31static int pb1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) 62static int pb1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
32{ 63{
@@ -101,10 +132,79 @@ static struct platform_device pb1550_i2c_dev = {
101 .resource = au1550_psc2_res, 132 .resource = au1550_psc2_res,
102}; 133};
103 134
135static struct mtd_partition pb1550_nand_parts[] = {
136 [0] = {
137 .name = "NAND FS 0",
138 .offset = 0,
139 .size = 8 * 1024 * 1024,
140 },
141 [1] = {
142 .name = "NAND FS 1",
143 .offset = MTDPART_OFS_APPEND,
144 .size = MTDPART_SIZ_FULL,
145 },
146};
147
148static struct au1550nd_platdata pb1550_nand_pd = {
149 .parts = pb1550_nand_parts,
150 .num_parts = ARRAY_SIZE(pb1550_nand_parts),
151 .devwidth = 0, /* x8 NAND default, needs fixing up */
152};
153
154static struct resource pb1550_nand_res[] = {
155 [0] = {
156 .start = 0x20000000,
157 .end = 0x20000fff,
158 .flags = IORESOURCE_MEM,
159 },
160};
161
162static struct platform_device pb1550_nand_dev = {
163 .name = "au1550-nand",
164 .id = -1,
165 .resource = pb1550_nand_res,
166 .num_resources = ARRAY_SIZE(pb1550_nand_res),
167 .dev = {
168 .platform_data = &pb1550_nand_pd,
169 },
170};
171
172static void __init pb1550_nand_setup(void)
173{
174 int boot_swapboot = (au_readl(MEM_STSTAT) & (0x7 << 1)) |
175 ((bcsr_read(BCSR_STATUS) >> 6) & 0x1);
176
177 switch (boot_swapboot) {
178 case 0:
179 case 2:
180 case 8:
181 case 0xC:
182 case 0xD:
183 /* x16 NAND Flash */
184 pb1550_nand_pd.devwidth = 1;
185 /* fallthrough */
186 case 1:
187 case 9:
188 case 3:
189 case 0xE:
190 case 0xF:
191 /* x8 NAND, already set up */
192 platform_device_register(&pb1550_nand_dev);
193 }
194}
195
104static int __init pb1550_dev_init(void) 196static int __init pb1550_dev_init(void)
105{ 197{
106 int swapped; 198 int swapped;
107 199
200 irq_set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW);
201 irq_set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW);
202 irq_set_irq_type(AU1550_GPIO201_205_INT, IRQF_TRIGGER_HIGH);
203
204 /* enable both PCMCIA card irqs in the shared line */
205 alchemy_gpio2_enable_int(201);
206 alchemy_gpio2_enable_int(202);
207
108 /* Pb1550, like all others, also has statuschange irqs; however they're 208 /* Pb1550, like all others, also has statuschange irqs; however they're
109 * wired up on one of the Au1550's shared GPIO201_205 line, which also 209 * wired up on one of the Au1550's shared GPIO201_205 line, which also
110 * services the PCMCIA card interrupts. So we ignore statuschange and 210 * services the PCMCIA card interrupts. So we ignore statuschange and
@@ -130,6 +230,10 @@ static int __init pb1550_dev_init(void)
130 AU1000_PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1, 230 AU1000_PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1,
131 AU1550_GPIO201_205_INT, AU1550_GPIO1_INT, 0, 0, 1); 231 AU1550_GPIO201_205_INT, AU1550_GPIO1_INT, 0, 0, 1);
132 232
233 /* NAND setup */
234 gpio_direction_input(206); /* GPIO206 high */
235 pb1550_nand_setup();
236
133 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_PB1550_SWAPBOOT; 237 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_PB1550_SWAPBOOT;
134 db1x_register_norflash(128 * 1024 * 1024, 4, swapped); 238 db1x_register_norflash(128 * 1024 * 1024, 4, swapped);
135 platform_device_register(&pb1550_pci_host); 239 platform_device_register(&pb1550_pci_host);
diff --git a/arch/mips/alchemy/devboards/pb1550/Makefile b/arch/mips/alchemy/devboards/pb1550/Makefile
deleted file mode 100644
index 9661b6ec5dd3..000000000000
--- a/arch/mips/alchemy/devboards/pb1550/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
1#
2# Copyright 2000, 2008 MontaVista Software Inc.
3# Author: MontaVista Software, Inc. <source@mvista.com>
4#
5# Makefile for the Alchemy Semiconductor Pb1550 board.
6#
7
8obj-y := board_setup.o platform.o
diff --git a/arch/mips/alchemy/devboards/pb1550/board_setup.c b/arch/mips/alchemy/devboards/pb1550/board_setup.c
deleted file mode 100644
index 0f62d1e3df24..000000000000
--- a/arch/mips/alchemy/devboards/pb1550/board_setup.c
+++ /dev/null
@@ -1,80 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Alchemy Pb1550 board setup.
5 *
6 * Copyright 2000, 2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. <source@mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29
30#include <linux/init.h>
31#include <linux/interrupt.h>
32
33#include <asm/mach-au1x00/au1000.h>
34#include <asm/mach-pb1x00/pb1550.h>
35#include <asm/mach-db1x00/bcsr.h>
36#include <asm/mach-au1x00/gpio.h>
37
38#include <prom.h>
39
40const char *get_system_type(void)
41{
42 return "Alchemy Pb1550";
43}
44
45void __init board_setup(void)
46{
47 u32 pin_func;
48
49 bcsr_init(PB1550_BCSR_PHYS_ADDR,
50 PB1550_BCSR_PHYS_ADDR + PB1550_BCSR_HEXLED_OFS);
51
52 alchemy_gpio2_enable();
53
54 /*
55 * Enable PSC1 SYNC for AC'97. Normaly done in audio driver,
56 * but it is board specific code, so put it here.
57 */
58 pin_func = au_readl(SYS_PINFUNC);
59 au_sync();
60 pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1;
61 au_writel(pin_func, SYS_PINFUNC);
62
63 bcsr_write(BCSR_PCMCIA, 0); /* turn off PCMCIA power */
64
65 printk(KERN_INFO "AMD Alchemy Pb1550 Board\n");
66}
67
68static int __init pb1550_init_irq(void)
69{
70 irq_set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW);
71 irq_set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW);
72 irq_set_irq_type(AU1550_GPIO201_205_INT, IRQF_TRIGGER_HIGH);
73
74 /* enable both PCMCIA card irqs in the shared line */
75 alchemy_gpio2_enable_int(201);
76 alchemy_gpio2_enable_int(202);
77
78 return 0;
79}
80arch_initcall(pb1550_init_irq);
diff --git a/arch/mips/alchemy/devboards/platform.c b/arch/mips/alchemy/devboards/platform.c
index 49a4b3244d8e..621f70afb63a 100644
--- a/arch/mips/alchemy/devboards/platform.c
+++ b/arch/mips/alchemy/devboards/platform.c
@@ -13,6 +13,13 @@
13#include <asm/reboot.h> 13#include <asm/reboot.h>
14#include <asm/mach-db1x00/bcsr.h> 14#include <asm/mach-db1x00/bcsr.h>
15 15
16
17static struct platform_device db1x00_rtc_dev = {
18 .name = "rtc-au1xxx",
19 .id = -1,
20};
21
22
16static void db1x_power_off(void) 23static void db1x_power_off(void)
17{ 24{
18 bcsr_write(BCSR_RESETS, 0); 25 bcsr_write(BCSR_RESETS, 0);
@@ -25,7 +32,7 @@ static void db1x_reset(char *c)
25 bcsr_write(BCSR_SYSTEM, 0); 32 bcsr_write(BCSR_SYSTEM, 0);
26} 33}
27 34
28static int __init db1x_poweroff_setup(void) 35static int __init db1x_late_setup(void)
29{ 36{
30 if (!pm_power_off) 37 if (!pm_power_off)
31 pm_power_off = db1x_power_off; 38 pm_power_off = db1x_power_off;
@@ -34,9 +41,11 @@ static int __init db1x_poweroff_setup(void)
34 if (!_machine_restart) 41 if (!_machine_restart)
35 _machine_restart = db1x_reset; 42 _machine_restart = db1x_reset;
36 43
44 platform_device_register(&db1x00_rtc_dev);
45
37 return 0; 46 return 0;
38} 47}
39late_initcall(db1x_poweroff_setup); 48device_initcall(db1x_late_setup);
40 49
41/* register a pcmcia socket */ 50/* register a pcmcia socket */
42int __init db1x_register_pcmcia_socket(phys_addr_t pcmcia_attr_start, 51int __init db1x_register_pcmcia_socket(phys_addr_t pcmcia_attr_start,
diff --git a/arch/mips/alchemy/devboards/prom.c b/arch/mips/alchemy/devboards/prom.c
index e5306b56da6d..93a22107cc41 100644
--- a/arch/mips/alchemy/devboards/prom.c
+++ b/arch/mips/alchemy/devboards/prom.c
@@ -33,10 +33,9 @@
33#include <asm/mach-au1x00/au1000.h> 33#include <asm/mach-au1x00/au1000.h>
34#include <prom.h> 34#include <prom.h>
35 35
36#if defined(CONFIG_MIPS_PB1000) || defined(CONFIG_MIPS_DB1000) || \ 36#if defined(CONFIG_MIPS_DB1000) || \
37 defined(CONFIG_MIPS_PB1100) || defined(CONFIG_MIPS_DB1100) || \ 37 defined(CONFIG_MIPS_PB1100) || \
38 defined(CONFIG_MIPS_PB1500) || defined(CONFIG_MIPS_DB1500) || \ 38 defined(CONFIG_MIPS_PB1500)
39 defined(CONFIG_MIPS_BOSPORUS) || defined(CONFIG_MIPS_MIRAGE)
40#define ALCHEMY_BOARD_DEFAULT_MEMSIZE 0x04000000 39#define ALCHEMY_BOARD_DEFAULT_MEMSIZE 0x04000000
41 40
42#else /* Au1550/Au1200-based develboards */ 41#else /* Au1550/Au1200-based develboards */
@@ -62,5 +61,9 @@ void __init prom_init(void)
62 61
63void prom_putchar(unsigned char c) 62void prom_putchar(unsigned char c)
64{ 63{
64#ifdef CONFIG_MIPS_DB1300
65 alchemy_uart_putchar(AU1300_UART2_PHYS_ADDR, c);
66#else
65 alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c); 67 alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
68#endif
66} 69}
diff --git a/arch/mips/alchemy/gpr/Makefile b/arch/mips/alchemy/gpr/Makefile
deleted file mode 100644
index cb73fe256dce..000000000000
--- a/arch/mips/alchemy/gpr/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
1#
2# Copyright 2003 MontaVista Software Inc.
3# Author: MontaVista Software, Inc. <source@mvista.com>
4#
5# Makefile for Trapeze ITS GPR board.
6#
7
8obj-y += board_setup.o init.o platform.o
diff --git a/arch/mips/alchemy/gpr/board_setup.c b/arch/mips/alchemy/gpr/board_setup.c
deleted file mode 100644
index dea45c78fdcd..000000000000
--- a/arch/mips/alchemy/gpr/board_setup.c
+++ /dev/null
@@ -1,75 +0,0 @@
1/*
2 * Copyright 2010 Wolfgang Grandegger <wg@denx.de>
3 *
4 * Copyright 2000-2003, 2008 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc. <source@mvista.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#include <linux/gpio.h>
29#include <linux/init.h>
30#include <linux/interrupt.h>
31#include <linux/delay.h>
32#include <linux/pm.h>
33
34#include <asm/reboot.h>
35#include <asm/mach-au1x00/au1000.h>
36
37#include <prom.h>
38
39static void gpr_reset(char *c)
40{
41 /* switch System-LED to orange (red# and green# on) */
42 alchemy_gpio_direction_output(4, 0);
43 alchemy_gpio_direction_output(5, 0);
44
45 /* trigger watchdog to reset board in 200ms */
46 printk(KERN_EMERG "Triggering watchdog soft reset...\n");
47 raw_local_irq_disable();
48 alchemy_gpio_direction_output(1, 0);
49 udelay(1);
50 alchemy_gpio_set_value(1, 1);
51 while (1)
52 cpu_wait();
53}
54
55static void gpr_power_off(void)
56{
57 while (1)
58 cpu_wait();
59}
60
61void __init board_setup(void)
62{
63 printk(KERN_INFO "Trapeze ITS GPR board\n");
64
65 pm_power_off = gpr_power_off;
66 _machine_halt = gpr_power_off;
67 _machine_restart = gpr_reset;
68
69 /* Enable UART1/3 */
70 alchemy_uart_enable(AU1000_UART3_PHYS_ADDR);
71 alchemy_uart_enable(AU1000_UART1_PHYS_ADDR);
72
73 /* Take away Reset of UMTS-card */
74 alchemy_gpio_direction_output(215, 1);
75}
diff --git a/arch/mips/alchemy/gpr/init.c b/arch/mips/alchemy/gpr/init.c
deleted file mode 100644
index 229aafae680c..000000000000
--- a/arch/mips/alchemy/gpr/init.c
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * Copyright 2010 Wolfgang Grandegger <wg@denx.de>
3 *
4 * Copyright 2003, 2008 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc. <source@mvista.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#include <linux/init.h>
29#include <linux/kernel.h>
30
31#include <asm/bootinfo.h>
32#include <asm/mach-au1x00/au1000.h>
33
34#include <prom.h>
35
36const char *get_system_type(void)
37{
38 return "GPR";
39}
40
41void __init prom_init(void)
42{
43 unsigned char *memsize_str;
44 unsigned long memsize;
45
46 prom_argc = fw_arg0;
47 prom_argv = (char **)fw_arg1;
48 prom_envp = (char **)fw_arg2;
49
50 prom_init_cmdline();
51
52 memsize_str = prom_getenv("memsize");
53 if (!memsize_str)
54 memsize = 0x04000000;
55 else
56 strict_strtoul(memsize_str, 0, &memsize);
57 add_memory_region(0, memsize, BOOT_MEM_RAM);
58}
59
60void prom_putchar(unsigned char c)
61{
62 alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
63}
diff --git a/arch/mips/alchemy/mtx-1/Makefile b/arch/mips/alchemy/mtx-1/Makefile
deleted file mode 100644
index 81b540ceaf88..000000000000
--- a/arch/mips/alchemy/mtx-1/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
1#
2# Copyright 2003 MontaVista Software Inc.
3# Author: MontaVista Software, Inc. <source@mvista.com>
4# Bruno Randolf <bruno.randolf@4g-systems.biz>
5#
6# Makefile for 4G Systems MTX-1 board.
7#
8
9obj-y += init.o board_setup.o platform.o
diff --git a/arch/mips/alchemy/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c
deleted file mode 100644
index 851a5ab4c8f2..000000000000
--- a/arch/mips/alchemy/mtx-1/board_setup.c
+++ /dev/null
@@ -1,94 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * 4G Systems MTX-1 board setup.
5 *
6 * Copyright 2003, 2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. <source@mvista.com>
8 * Bruno Randolf <bruno.randolf@4g-systems.biz>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31#include <linux/gpio.h>
32#include <linux/init.h>
33#include <linux/interrupt.h>
34#include <linux/pm.h>
35
36#include <asm/reboot.h>
37#include <asm/mach-au1x00/au1000.h>
38
39#include <prom.h>
40
41static void mtx1_reset(char *c)
42{
43 /* Jump to the reset vector */
44 __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
45}
46
47static void mtx1_power_off(void)
48{
49 while (1)
50 asm volatile (
51 " .set mips32 \n"
52 " wait \n"
53 " .set mips0 \n");
54}
55
56void __init board_setup(void)
57{
58#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
59 /* Enable USB power switch */
60 alchemy_gpio_direction_output(204, 0);
61#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
62
63 /* Initialize sys_pinfunc */
64 au_writel(SYS_PF_NI2, SYS_PINFUNC);
65
66 /* Initialize GPIO */
67 au_writel(~0, KSEG1ADDR(AU1000_SYS_PHYS_ADDR) + SYS_TRIOUTCLR);
68 alchemy_gpio_direction_output(0, 0); /* Disable M66EN (PCI 66MHz) */
69 alchemy_gpio_direction_output(3, 1); /* Disable PCI CLKRUN# */
70 alchemy_gpio_direction_output(1, 1); /* Enable EXT_IO3 */
71 alchemy_gpio_direction_output(5, 0); /* Disable eth PHY TX_ER */
72
73 /* Enable LED and set it to green */
74 alchemy_gpio_direction_output(211, 1); /* green on */
75 alchemy_gpio_direction_output(212, 0); /* red off */
76
77 pm_power_off = mtx1_power_off;
78 _machine_halt = mtx1_power_off;
79 _machine_restart = mtx1_reset;
80
81 printk(KERN_INFO "4G Systems MTX-1 Board\n");
82}
83
84static int __init mtx1_init_irq(void)
85{
86 irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
87 irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
88 irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
89 irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
90 irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
91
92 return 0;
93}
94arch_initcall(mtx1_init_irq);
diff --git a/arch/mips/alchemy/mtx-1/init.c b/arch/mips/alchemy/mtx-1/init.c
deleted file mode 100644
index 2e81cc7f3422..000000000000
--- a/arch/mips/alchemy/mtx-1/init.c
+++ /dev/null
@@ -1,66 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * 4G Systems MTX-1 board setup
5 *
6 * Copyright 2003, 2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. <source@mvista.com>
8 * Bruno Randolf <bruno.randolf@4g-systems.biz>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31#include <linux/kernel.h>
32#include <linux/init.h>
33
34#include <asm/bootinfo.h>
35#include <asm/mach-au1x00/au1000.h>
36
37#include <prom.h>
38
39const char *get_system_type(void)
40{
41 return "MTX-1";
42}
43
44void __init prom_init(void)
45{
46 unsigned char *memsize_str;
47 unsigned long memsize;
48
49 prom_argc = fw_arg0;
50 prom_argv = (char **)fw_arg1;
51 prom_envp = (char **)fw_arg2;
52
53 prom_init_cmdline();
54
55 memsize_str = prom_getenv("memsize");
56 if (!memsize_str)
57 memsize = 0x04000000;
58 else
59 strict_strtoul(memsize_str, 0, &memsize);
60 add_memory_region(0, memsize, BOOT_MEM_RAM);
61}
62
63void prom_putchar(unsigned char c)
64{
65 alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
66}
diff --git a/arch/mips/alchemy/xxs1500/Makefile b/arch/mips/alchemy/xxs1500/Makefile
deleted file mode 100644
index 91defcf4f335..000000000000
--- a/arch/mips/alchemy/xxs1500/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
1#
2# Copyright 2003 MontaVista Software Inc.
3# Author: MontaVista Software, Inc. <source@mvista.com>
4#
5# Makefile for MyCable XXS1500 board.
6#
7
8obj-y += init.o board_setup.o platform.o
diff --git a/arch/mips/alchemy/xxs1500/board_setup.c b/arch/mips/alchemy/xxs1500/board_setup.c
deleted file mode 100644
index 3fa83f72e014..000000000000
--- a/arch/mips/alchemy/xxs1500/board_setup.c
+++ /dev/null
@@ -1,93 +0,0 @@
1/*
2 * Copyright 2000-2003, 2008 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc. <source@mvista.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26#include <linux/gpio.h>
27#include <linux/init.h>
28#include <linux/interrupt.h>
29#include <linux/delay.h>
30#include <linux/pm.h>
31
32#include <asm/reboot.h>
33#include <asm/mach-au1x00/au1000.h>
34
35#include <prom.h>
36
37static void xxs1500_reset(char *c)
38{
39 /* Jump to the reset vector */
40 __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
41}
42
43static void xxs1500_power_off(void)
44{
45 while (1)
46 asm volatile (
47 " .set mips32 \n"
48 " wait \n"
49 " .set mips0 \n");
50}
51
52void __init board_setup(void)
53{
54 u32 pin_func;
55
56 pm_power_off = xxs1500_power_off;
57 _machine_halt = xxs1500_power_off;
58 _machine_restart = xxs1500_reset;
59
60 alchemy_gpio1_input_enable();
61 alchemy_gpio2_enable();
62
63 /* Set multiple use pins (UART3/GPIO) to UART (it's used as UART too) */
64 pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_UR3;
65 pin_func |= SYS_PF_UR3;
66 au_writel(pin_func, SYS_PINFUNC);
67
68 /* Enable UART */
69 alchemy_uart_enable(AU1000_UART3_PHYS_ADDR);
70 /* Enable DTR (MCR bit 0) = USB power up */
71 __raw_writel(1, (void __iomem *)KSEG1ADDR(AU1000_UART3_PHYS_ADDR + 0x18));
72 wmb();
73}
74
75static int __init xxs1500_init_irq(void)
76{
77 irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
78 irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
79 irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
80 irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
81 irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
82 irq_set_irq_type(AU1500_GPIO207_INT, IRQF_TRIGGER_LOW);
83
84 irq_set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW);
85 irq_set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW);
86 irq_set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW);
87 irq_set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW);
88 irq_set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* CF irq */
89 irq_set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW);
90
91 return 0;
92}
93arch_initcall(xxs1500_init_irq);
diff --git a/arch/mips/alchemy/xxs1500/init.c b/arch/mips/alchemy/xxs1500/init.c
deleted file mode 100644
index 0ee02cfa989d..000000000000
--- a/arch/mips/alchemy/xxs1500/init.c
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * XXS1500 board setup
4 *
5 * Copyright 2003, 2008 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc. <source@mvista.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#include <linux/init.h>
30#include <linux/kernel.h>
31
32#include <asm/bootinfo.h>
33#include <asm/mach-au1x00/au1000.h>
34
35#include <prom.h>
36
37const char *get_system_type(void)
38{
39 return "XXS1500";
40}
41
42void __init prom_init(void)
43{
44 unsigned char *memsize_str;
45 unsigned long memsize;
46
47 prom_argc = fw_arg0;
48 prom_argv = (char **)fw_arg1;
49 prom_envp = (char **)fw_arg2;
50
51 prom_init_cmdline();
52
53 memsize_str = prom_getenv("memsize");
54 if (!memsize_str || strict_strtoul(memsize_str, 0, &memsize))
55 memsize = 0x04000000;
56
57 add_memory_region(0, memsize, BOOT_MEM_RAM);
58}
59
60void prom_putchar(unsigned char c)
61{
62 alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
63}
diff --git a/arch/mips/alchemy/xxs1500/platform.c b/arch/mips/alchemy/xxs1500/platform.c
deleted file mode 100644
index 06a3a459b8aa..000000000000
--- a/arch/mips/alchemy/xxs1500/platform.c
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * XXS1500 board platform device registration
3 *
4 * Copyright (C) 2009 Manuel Lauss
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/init.h>
22#include <linux/platform_device.h>
23
24#include <asm/mach-au1x00/au1000.h>
25
26static struct resource xxs1500_pcmcia_res[] = {
27 {
28 .name = "pcmcia-io",
29 .flags = IORESOURCE_MEM,
30 .start = AU1000_PCMCIA_IO_PHYS_ADDR,
31 .end = AU1000_PCMCIA_IO_PHYS_ADDR + 0x000400000 - 1,
32 },
33 {
34 .name = "pcmcia-attr",
35 .flags = IORESOURCE_MEM,
36 .start = AU1000_PCMCIA_ATTR_PHYS_ADDR,
37 .end = AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
38 },
39 {
40 .name = "pcmcia-mem",
41 .flags = IORESOURCE_MEM,
42 .start = AU1000_PCMCIA_MEM_PHYS_ADDR,
43 .end = AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
44 },
45};
46
47static struct platform_device xxs1500_pcmcia_dev = {
48 .name = "xxs1500_pcmcia",
49 .id = -1,
50 .num_resources = ARRAY_SIZE(xxs1500_pcmcia_res),
51 .resource = xxs1500_pcmcia_res,
52};
53
54static struct platform_device *xxs1500_devs[] __initdata = {
55 &xxs1500_pcmcia_dev,
56};
57
58static int __init xxs1500_dev_init(void)
59{
60 return platform_add_devices(xxs1500_devs,
61 ARRAY_SIZE(xxs1500_devs));
62}
63device_initcall(xxs1500_dev_init);
diff --git a/arch/mips/ar7/gpio.c b/arch/mips/ar7/gpio.c
index bb571bcdb8f2..d8dbd8f0c1d2 100644
--- a/arch/mips/ar7/gpio.c
+++ b/arch/mips/ar7/gpio.c
@@ -217,7 +217,7 @@ struct titan_gpio_cfg {
217 u32 func; 217 u32 func;
218}; 218};
219 219
220static struct titan_gpio_cfg titan_gpio_table[] = { 220static const struct titan_gpio_cfg titan_gpio_table[] = {
221 /* reg, start bit, mux value */ 221 /* reg, start bit, mux value */
222 {4, 24, 1}, 222 {4, 24, 1},
223 {4, 26, 1}, 223 {4, 26, 1},
diff --git a/arch/mips/ar7/platform.c b/arch/mips/ar7/platform.c
index 33ffecf6a6d6..1a24d317e7a3 100644
--- a/arch/mips/ar7/platform.c
+++ b/arch/mips/ar7/platform.c
@@ -462,6 +462,40 @@ static struct gpio_led fb_fon_leds[] = {
462 }, 462 },
463}; 463};
464 464
465static struct gpio_led gt701_leds[] = {
466 {
467 .name = "inet:green",
468 .gpio = 13,
469 .active_low = 1,
470 },
471 {
472 .name = "usb",
473 .gpio = 12,
474 .active_low = 1,
475 },
476 {
477 .name = "inet:red",
478 .gpio = 9,
479 .active_low = 1,
480 },
481 {
482 .name = "power:red",
483 .gpio = 7,
484 .active_low = 1,
485 },
486 {
487 .name = "power:green",
488 .gpio = 8,
489 .active_low = 1,
490 .default_trigger = "default-on",
491 },
492 {
493 .name = "ethernet",
494 .gpio = 10,
495 .active_low = 1,
496 },
497};
498
465static struct gpio_led_platform_data ar7_led_data; 499static struct gpio_led_platform_data ar7_led_data;
466 500
467static struct platform_device ar7_gpio_leds = { 501static struct platform_device ar7_gpio_leds = {
@@ -503,6 +537,9 @@ static void __init detect_leds(void)
503 } else if (strstr(prid, "CYWM") || strstr(prid, "CYWL")) { 537 } else if (strstr(prid, "CYWM") || strstr(prid, "CYWL")) {
504 ar7_led_data.num_leds = ARRAY_SIZE(titan_leds); 538 ar7_led_data.num_leds = ARRAY_SIZE(titan_leds);
505 ar7_led_data.leds = titan_leds; 539 ar7_led_data.leds = titan_leds;
540 } else if (strstr(prid, "GT701")) {
541 ar7_led_data.num_leds = ARRAY_SIZE(gt701_leds);
542 ar7_led_data.leds = gt701_leds;
506 } 543 }
507} 544}
508 545
@@ -536,7 +573,7 @@ static int __init ar7_register_uarts(void)
536 573
537 bus_clk = clk_get(NULL, "bus"); 574 bus_clk = clk_get(NULL, "bus");
538 if (IS_ERR(bus_clk)) 575 if (IS_ERR(bus_clk))
539 panic("unable to get bus clk\n"); 576 panic("unable to get bus clk");
540 577
541 uart_port.type = PORT_AR7; 578 uart_port.type = PORT_AR7;
542 uart_port.uartclk = clk_get_rate(bus_clk) / 2; 579 uart_port.uartclk = clk_get_rate(bus_clk) / 2;
diff --git a/arch/mips/ar7/prom.c b/arch/mips/ar7/prom.c
index 8088c6fdb83e..a23adc49d50f 100644
--- a/arch/mips/ar7/prom.c
+++ b/arch/mips/ar7/prom.c
@@ -69,7 +69,7 @@ struct psbl_rec {
69 u32 ffs_size; 69 u32 ffs_size;
70}; 70};
71 71
72static __initdata char psp_env_version[] = "TIENV0.8"; 72static const char psp_env_version[] __initconst = "TIENV0.8";
73 73
74struct psp_env_chunk { 74struct psp_env_chunk {
75 u8 num; 75 u8 num;
@@ -84,7 +84,7 @@ struct psp_var_map_entry {
84 char *value; 84 char *value;
85}; 85};
86 86
87static struct psp_var_map_entry psp_var_map[] = { 87static const struct psp_var_map_entry psp_var_map[] = {
88 { 1, "cpufrequency" }, 88 { 1, "cpufrequency" },
89 { 2, "memsize" }, 89 { 2, "memsize" },
90 { 3, "flashsize" }, 90 { 3, "flashsize" },
diff --git a/arch/mips/ar7/setup.c b/arch/mips/ar7/setup.c
index f20b53e597c4..9a357fffcfbe 100644
--- a/arch/mips/ar7/setup.c
+++ b/arch/mips/ar7/setup.c
@@ -96,7 +96,7 @@ void __init plat_mem_setup(void)
96 96
97 io_base = (unsigned long)ioremap(AR7_REGS_BASE, 0x10000); 97 io_base = (unsigned long)ioremap(AR7_REGS_BASE, 0x10000);
98 if (!io_base) 98 if (!io_base)
99 panic("Can't remap IO base!\n"); 99 panic("Can't remap IO base!");
100 set_io_port_base(io_base); 100 set_io_port_base(io_base);
101 101
102 prom_meminit(); 102 prom_meminit();
diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig
index 47707410582c..e0fae8f4442b 100644
--- a/arch/mips/ath79/Kconfig
+++ b/arch/mips/ath79/Kconfig
@@ -2,13 +2,26 @@ if ATH79
2 2
3menu "Atheros AR71XX/AR724X/AR913X machine selection" 3menu "Atheros AR71XX/AR724X/AR913X machine selection"
4 4
5config ATH79_MACH_AP121
6 bool "Atheros AP121 reference board"
7 select SOC_AR933X
8 select ATH79_DEV_GPIO_BUTTONS
9 select ATH79_DEV_LEDS_GPIO
10 select ATH79_DEV_SPI
11 select ATH79_DEV_USB
12 select ATH79_DEV_WMAC
13 help
14 Say 'Y' here if you want your kernel to support the
15 Atheros AP121 reference board.
16
5config ATH79_MACH_AP81 17config ATH79_MACH_AP81
6 bool "Atheros AP81 reference board" 18 bool "Atheros AP81 reference board"
7 select SOC_AR913X 19 select SOC_AR913X
8 select ATH79_DEV_AR913X_WMAC
9 select ATH79_DEV_GPIO_BUTTONS 20 select ATH79_DEV_GPIO_BUTTONS
10 select ATH79_DEV_LEDS_GPIO 21 select ATH79_DEV_LEDS_GPIO
11 select ATH79_DEV_SPI 22 select ATH79_DEV_SPI
23 select ATH79_DEV_USB
24 select ATH79_DEV_WMAC
12 help 25 help
13 Say 'Y' here if you want your kernel to support the 26 Say 'Y' here if you want your kernel to support the
14 Atheros AP81 reference board. 27 Atheros AP81 reference board.
@@ -19,10 +32,21 @@ config ATH79_MACH_PB44
19 select ATH79_DEV_GPIO_BUTTONS 32 select ATH79_DEV_GPIO_BUTTONS
20 select ATH79_DEV_LEDS_GPIO 33 select ATH79_DEV_LEDS_GPIO
21 select ATH79_DEV_SPI 34 select ATH79_DEV_SPI
35 select ATH79_DEV_USB
22 help 36 help
23 Say 'Y' here if you want your kernel to support the 37 Say 'Y' here if you want your kernel to support the
24 Atheros PB44 reference board. 38 Atheros PB44 reference board.
25 39
40config ATH79_MACH_UBNT_XM
41 bool "Ubiquiti Networks XM (rev 1.0) board"
42 select SOC_AR724X
43 select ATH79_DEV_GPIO_BUTTONS
44 select ATH79_DEV_LEDS_GPIO
45 select ATH79_DEV_SPI
46 help
47 Say 'Y' here if you want your kernel to support the
48 Ubiquiti Networks XM (rev 1.0) board.
49
26endmenu 50endmenu
27 51
28config SOC_AR71XX 52config SOC_AR71XX
@@ -33,14 +57,15 @@ config SOC_AR71XX
33config SOC_AR724X 57config SOC_AR724X
34 select USB_ARCH_HAS_EHCI 58 select USB_ARCH_HAS_EHCI
35 select USB_ARCH_HAS_OHCI 59 select USB_ARCH_HAS_OHCI
60 select HW_HAS_PCI
36 def_bool n 61 def_bool n
37 62
38config SOC_AR913X 63config SOC_AR913X
39 select USB_ARCH_HAS_EHCI 64 select USB_ARCH_HAS_EHCI
40 def_bool n 65 def_bool n
41 66
42config ATH79_DEV_AR913X_WMAC 67config SOC_AR933X
43 depends on SOC_AR913X 68 select USB_ARCH_HAS_EHCI
44 def_bool n 69 def_bool n
45 70
46config ATH79_DEV_GPIO_BUTTONS 71config ATH79_DEV_GPIO_BUTTONS
@@ -52,4 +77,11 @@ config ATH79_DEV_LEDS_GPIO
52config ATH79_DEV_SPI 77config ATH79_DEV_SPI
53 def_bool n 78 def_bool n
54 79
80config ATH79_DEV_USB
81 def_bool n
82
83config ATH79_DEV_WMAC
84 depends on (SOC_AR913X || SOC_AR933X)
85 def_bool n
86
55endif 87endif
diff --git a/arch/mips/ath79/Makefile b/arch/mips/ath79/Makefile
index c33d4653007c..3b911e09dbec 100644
--- a/arch/mips/ath79/Makefile
+++ b/arch/mips/ath79/Makefile
@@ -16,13 +16,16 @@ obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
16# Devices 16# Devices
17# 17#
18obj-y += dev-common.o 18obj-y += dev-common.o
19obj-$(CONFIG_ATH79_DEV_AR913X_WMAC) += dev-ar913x-wmac.o
20obj-$(CONFIG_ATH79_DEV_GPIO_BUTTONS) += dev-gpio-buttons.o 19obj-$(CONFIG_ATH79_DEV_GPIO_BUTTONS) += dev-gpio-buttons.o
21obj-$(CONFIG_ATH79_DEV_LEDS_GPIO) += dev-leds-gpio.o 20obj-$(CONFIG_ATH79_DEV_LEDS_GPIO) += dev-leds-gpio.o
22obj-$(CONFIG_ATH79_DEV_SPI) += dev-spi.o 21obj-$(CONFIG_ATH79_DEV_SPI) += dev-spi.o
22obj-$(CONFIG_ATH79_DEV_USB) += dev-usb.o
23obj-$(CONFIG_ATH79_DEV_WMAC) += dev-wmac.o
23 24
24# 25#
25# Machines 26# Machines
26# 27#
28obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o
27obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o 29obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o
28obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o 30obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o
31obj-$(CONFIG_ATH79_MACH_UBNT_XM) += mach-ubnt-xm.o
diff --git a/arch/mips/ath79/clock.c b/arch/mips/ath79/clock.c
index 680bde99a26c..54d0eb4db987 100644
--- a/arch/mips/ath79/clock.c
+++ b/arch/mips/ath79/clock.c
@@ -110,6 +110,59 @@ static void __init ar913x_clocks_init(void)
110 ath79_uart_clk.rate = ath79_ahb_clk.rate; 110 ath79_uart_clk.rate = ath79_ahb_clk.rate;
111} 111}
112 112
113static void __init ar933x_clocks_init(void)
114{
115 u32 clock_ctrl;
116 u32 cpu_config;
117 u32 freq;
118 u32 t;
119
120 t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
121 if (t & AR933X_BOOTSTRAP_REF_CLK_40)
122 ath79_ref_clk.rate = (40 * 1000 * 1000);
123 else
124 ath79_ref_clk.rate = (25 * 1000 * 1000);
125
126 clock_ctrl = ath79_pll_rr(AR933X_PLL_CLOCK_CTRL_REG);
127 if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
128 ath79_cpu_clk.rate = ath79_ref_clk.rate;
129 ath79_ahb_clk.rate = ath79_ref_clk.rate;
130 ath79_ddr_clk.rate = ath79_ref_clk.rate;
131 } else {
132 cpu_config = ath79_pll_rr(AR933X_PLL_CPU_CONFIG_REG);
133
134 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
135 AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
136 freq = ath79_ref_clk.rate / t;
137
138 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
139 AR933X_PLL_CPU_CONFIG_NINT_MASK;
140 freq *= t;
141
142 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
143 AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
144 if (t == 0)
145 t = 1;
146
147 freq >>= t;
148
149 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
150 AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
151 ath79_cpu_clk.rate = freq / t;
152
153 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
154 AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
155 ath79_ddr_clk.rate = freq / t;
156
157 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
158 AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
159 ath79_ahb_clk.rate = freq / t;
160 }
161
162 ath79_wdt_clk.rate = ath79_ref_clk.rate;
163 ath79_uart_clk.rate = ath79_ref_clk.rate;
164}
165
113void __init ath79_clocks_init(void) 166void __init ath79_clocks_init(void)
114{ 167{
115 if (soc_is_ar71xx()) 168 if (soc_is_ar71xx())
@@ -118,6 +171,8 @@ void __init ath79_clocks_init(void)
118 ar724x_clocks_init(); 171 ar724x_clocks_init();
119 else if (soc_is_ar913x()) 172 else if (soc_is_ar913x())
120 ar913x_clocks_init(); 173 ar913x_clocks_init();
174 else if (soc_is_ar933x())
175 ar933x_clocks_init();
121 else 176 else
122 BUG(); 177 BUG();
123 178
diff --git a/arch/mips/ath79/common.c b/arch/mips/ath79/common.c
index 58f60e722a03..f0fda982b965 100644
--- a/arch/mips/ath79/common.c
+++ b/arch/mips/ath79/common.c
@@ -30,6 +30,7 @@ u32 ath79_ddr_freq;
30EXPORT_SYMBOL_GPL(ath79_ddr_freq); 30EXPORT_SYMBOL_GPL(ath79_ddr_freq);
31 31
32enum ath79_soc_type ath79_soc; 32enum ath79_soc_type ath79_soc;
33unsigned int ath79_soc_rev;
33 34
34void __iomem *ath79_pll_base; 35void __iomem *ath79_pll_base;
35void __iomem *ath79_reset_base; 36void __iomem *ath79_reset_base;
@@ -64,6 +65,8 @@ void ath79_device_reset_set(u32 mask)
64 reg = AR724X_RESET_REG_RESET_MODULE; 65 reg = AR724X_RESET_REG_RESET_MODULE;
65 else if (soc_is_ar913x()) 66 else if (soc_is_ar913x())
66 reg = AR913X_RESET_REG_RESET_MODULE; 67 reg = AR913X_RESET_REG_RESET_MODULE;
68 else if (soc_is_ar933x())
69 reg = AR933X_RESET_REG_RESET_MODULE;
67 else 70 else
68 BUG(); 71 BUG();
69 72
@@ -86,6 +89,8 @@ void ath79_device_reset_clear(u32 mask)
86 reg = AR724X_RESET_REG_RESET_MODULE; 89 reg = AR724X_RESET_REG_RESET_MODULE;
87 else if (soc_is_ar913x()) 90 else if (soc_is_ar913x())
88 reg = AR913X_RESET_REG_RESET_MODULE; 91 reg = AR913X_RESET_REG_RESET_MODULE;
92 else if (soc_is_ar933x())
93 reg = AR933X_RESET_REG_RESET_MODULE;
89 else 94 else
90 BUG(); 95 BUG();
91 96
diff --git a/arch/mips/ath79/dev-ar913x-wmac.c b/arch/mips/ath79/dev-ar913x-wmac.c
deleted file mode 100644
index 48f425a5ba28..000000000000
--- a/arch/mips/ath79/dev-ar913x-wmac.c
+++ /dev/null
@@ -1,60 +0,0 @@
1/*
2 * Atheros AR913X SoC built-in WMAC device support
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12#include <linux/init.h>
13#include <linux/delay.h>
14#include <linux/irq.h>
15#include <linux/platform_device.h>
16#include <linux/ath9k_platform.h>
17
18#include <asm/mach-ath79/ath79.h>
19#include <asm/mach-ath79/ar71xx_regs.h>
20#include "dev-ar913x-wmac.h"
21
22static struct ath9k_platform_data ar913x_wmac_data;
23
24static struct resource ar913x_wmac_resources[] = {
25 {
26 .start = AR913X_WMAC_BASE,
27 .end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1,
28 .flags = IORESOURCE_MEM,
29 }, {
30 .start = ATH79_CPU_IRQ_IP2,
31 .end = ATH79_CPU_IRQ_IP2,
32 .flags = IORESOURCE_IRQ,
33 },
34};
35
36static struct platform_device ar913x_wmac_device = {
37 .name = "ath9k",
38 .id = -1,
39 .resource = ar913x_wmac_resources,
40 .num_resources = ARRAY_SIZE(ar913x_wmac_resources),
41 .dev = {
42 .platform_data = &ar913x_wmac_data,
43 },
44};
45
46void __init ath79_register_ar913x_wmac(u8 *cal_data)
47{
48 if (cal_data)
49 memcpy(ar913x_wmac_data.eeprom_data, cal_data,
50 sizeof(ar913x_wmac_data.eeprom_data));
51
52 /* reset the WMAC */
53 ath79_device_reset_set(AR913X_RESET_AMBA2WMAC);
54 mdelay(10);
55
56 ath79_device_reset_clear(AR913X_RESET_AMBA2WMAC);
57 mdelay(10);
58
59 platform_device_register(&ar913x_wmac_device);
60}
diff --git a/arch/mips/ath79/dev-common.c b/arch/mips/ath79/dev-common.c
index 3b82e325bebf..f4956f809072 100644
--- a/arch/mips/ath79/dev-common.c
+++ b/arch/mips/ath79/dev-common.c
@@ -20,6 +20,7 @@
20 20
21#include <asm/mach-ath79/ath79.h> 21#include <asm/mach-ath79/ath79.h>
22#include <asm/mach-ath79/ar71xx_regs.h> 22#include <asm/mach-ath79/ar71xx_regs.h>
23#include <asm/mach-ath79/ar933x_uart_platform.h>
23#include "common.h" 24#include "common.h"
24#include "dev-common.h" 25#include "dev-common.h"
25 26
@@ -54,6 +55,30 @@ static struct platform_device ath79_uart_device = {
54 }, 55 },
55}; 56};
56 57
58static struct resource ar933x_uart_resources[] = {
59 {
60 .start = AR933X_UART_BASE,
61 .end = AR933X_UART_BASE + AR71XX_UART_SIZE - 1,
62 .flags = IORESOURCE_MEM,
63 },
64 {
65 .start = ATH79_MISC_IRQ_UART,
66 .end = ATH79_MISC_IRQ_UART,
67 .flags = IORESOURCE_IRQ,
68 },
69};
70
71static struct ar933x_uart_platform_data ar933x_uart_data;
72static struct platform_device ar933x_uart_device = {
73 .name = "ar933x-uart",
74 .id = -1,
75 .resource = ar933x_uart_resources,
76 .num_resources = ARRAY_SIZE(ar933x_uart_resources),
77 .dev = {
78 .platform_data = &ar933x_uart_data,
79 },
80};
81
57void __init ath79_register_uart(void) 82void __init ath79_register_uart(void)
58{ 83{
59 struct clk *clk; 84 struct clk *clk;
@@ -62,8 +87,17 @@ void __init ath79_register_uart(void)
62 if (IS_ERR(clk)) 87 if (IS_ERR(clk))
63 panic("unable to get UART clock, err=%ld", PTR_ERR(clk)); 88 panic("unable to get UART clock, err=%ld", PTR_ERR(clk));
64 89
65 ath79_uart_data[0].uartclk = clk_get_rate(clk); 90 if (soc_is_ar71xx() ||
66 platform_device_register(&ath79_uart_device); 91 soc_is_ar724x() ||
92 soc_is_ar913x()) {
93 ath79_uart_data[0].uartclk = clk_get_rate(clk);
94 platform_device_register(&ath79_uart_device);
95 } else if (soc_is_ar933x()) {
96 ar933x_uart_data.uartclk = clk_get_rate(clk);
97 platform_device_register(&ar933x_uart_device);
98 } else {
99 BUG();
100 }
67} 101}
68 102
69static struct platform_device ath79_wdt_device = { 103static struct platform_device ath79_wdt_device = {
diff --git a/arch/mips/ath79/dev-usb.c b/arch/mips/ath79/dev-usb.c
new file mode 100644
index 000000000000..002d6d2afe04
--- /dev/null
+++ b/arch/mips/ath79/dev-usb.c
@@ -0,0 +1,197 @@
1/*
2 * Atheros AR7XXX/AR9XXX USB Host Controller device
3 *
4 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Parts of this file are based on Atheros' 2.6.15 BSP
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/irq.h>
18#include <linux/dma-mapping.h>
19#include <linux/platform_device.h>
20
21#include <asm/mach-ath79/ath79.h>
22#include <asm/mach-ath79/ar71xx_regs.h>
23#include "common.h"
24#include "dev-usb.h"
25
26static struct resource ath79_ohci_resources[] = {
27 [0] = {
28 /* .start and .end fields are filled dynamically */
29 .flags = IORESOURCE_MEM,
30 },
31 [1] = {
32 .start = ATH79_MISC_IRQ_OHCI,
33 .end = ATH79_MISC_IRQ_OHCI,
34 .flags = IORESOURCE_IRQ,
35 },
36};
37
38static u64 ath79_ohci_dmamask = DMA_BIT_MASK(32);
39static struct platform_device ath79_ohci_device = {
40 .name = "ath79-ohci",
41 .id = -1,
42 .resource = ath79_ohci_resources,
43 .num_resources = ARRAY_SIZE(ath79_ohci_resources),
44 .dev = {
45 .dma_mask = &ath79_ohci_dmamask,
46 .coherent_dma_mask = DMA_BIT_MASK(32),
47 },
48};
49
50static struct resource ath79_ehci_resources[] = {
51 [0] = {
52 /* .start and .end fields are filled dynamically */
53 .flags = IORESOURCE_MEM,
54 },
55 [1] = {
56 .start = ATH79_CPU_IRQ_USB,
57 .end = ATH79_CPU_IRQ_USB,
58 .flags = IORESOURCE_IRQ,
59 },
60};
61
62static u64 ath79_ehci_dmamask = DMA_BIT_MASK(32);
63static struct platform_device ath79_ehci_device = {
64 .name = "ath79-ehci",
65 .id = -1,
66 .resource = ath79_ehci_resources,
67 .num_resources = ARRAY_SIZE(ath79_ehci_resources),
68 .dev = {
69 .dma_mask = &ath79_ehci_dmamask,
70 .coherent_dma_mask = DMA_BIT_MASK(32),
71 },
72};
73
74#define AR71XX_USB_RESET_MASK (AR71XX_RESET_USB_HOST | \
75 AR71XX_RESET_USB_PHY | \
76 AR71XX_RESET_USB_OHCI_DLL)
77
78static void __init ath79_usb_setup(void)
79{
80 void __iomem *usb_ctrl_base;
81
82 ath79_device_reset_set(AR71XX_USB_RESET_MASK);
83 mdelay(1000);
84 ath79_device_reset_clear(AR71XX_USB_RESET_MASK);
85
86 usb_ctrl_base = ioremap(AR71XX_USB_CTRL_BASE, AR71XX_USB_CTRL_SIZE);
87
88 /* Turning on the Buff and Desc swap bits */
89 __raw_writel(0xf0000, usb_ctrl_base + AR71XX_USB_CTRL_REG_CONFIG);
90
91 /* WAR for HW bug. Here it adjusts the duration between two SOFS */
92 __raw_writel(0x20c00, usb_ctrl_base + AR71XX_USB_CTRL_REG_FLADJ);
93
94 iounmap(usb_ctrl_base);
95
96 mdelay(900);
97
98 ath79_ohci_resources[0].start = AR71XX_OHCI_BASE;
99 ath79_ohci_resources[0].end = AR71XX_OHCI_BASE + AR71XX_OHCI_SIZE - 1;
100 platform_device_register(&ath79_ohci_device);
101
102 ath79_ehci_resources[0].start = AR71XX_EHCI_BASE;
103 ath79_ehci_resources[0].end = AR71XX_EHCI_BASE + AR71XX_EHCI_SIZE - 1;
104 ath79_ehci_device.name = "ar71xx-ehci";
105 platform_device_register(&ath79_ehci_device);
106}
107
108static void __init ar7240_usb_setup(void)
109{
110 void __iomem *usb_ctrl_base;
111
112 ath79_device_reset_clear(AR7240_RESET_OHCI_DLL);
113 ath79_device_reset_set(AR7240_RESET_USB_HOST);
114
115 mdelay(1000);
116
117 ath79_device_reset_set(AR7240_RESET_OHCI_DLL);
118 ath79_device_reset_clear(AR7240_RESET_USB_HOST);
119
120 usb_ctrl_base = ioremap(AR7240_USB_CTRL_BASE, AR7240_USB_CTRL_SIZE);
121
122 /* WAR for HW bug. Here it adjusts the duration between two SOFS */
123 __raw_writel(0x3, usb_ctrl_base + AR71XX_USB_CTRL_REG_FLADJ);
124
125 iounmap(usb_ctrl_base);
126
127 ath79_ohci_resources[0].start = AR7240_OHCI_BASE;
128 ath79_ohci_resources[0].end = AR7240_OHCI_BASE + AR7240_OHCI_SIZE - 1;
129 platform_device_register(&ath79_ohci_device);
130}
131
132static void __init ar724x_usb_setup(void)
133{
134 ath79_device_reset_set(AR724X_RESET_USBSUS_OVERRIDE);
135 mdelay(10);
136
137 ath79_device_reset_clear(AR724X_RESET_USB_HOST);
138 mdelay(10);
139
140 ath79_device_reset_clear(AR724X_RESET_USB_PHY);
141 mdelay(10);
142
143 ath79_ehci_resources[0].start = AR724X_EHCI_BASE;
144 ath79_ehci_resources[0].end = AR724X_EHCI_BASE + AR724X_EHCI_SIZE - 1;
145 ath79_ehci_device.name = "ar724x-ehci";
146 platform_device_register(&ath79_ehci_device);
147}
148
149static void __init ar913x_usb_setup(void)
150{
151 ath79_device_reset_set(AR913X_RESET_USBSUS_OVERRIDE);
152 mdelay(10);
153
154 ath79_device_reset_clear(AR913X_RESET_USB_HOST);
155 mdelay(10);
156
157 ath79_device_reset_clear(AR913X_RESET_USB_PHY);
158 mdelay(10);
159
160 ath79_ehci_resources[0].start = AR913X_EHCI_BASE;
161 ath79_ehci_resources[0].end = AR913X_EHCI_BASE + AR913X_EHCI_SIZE - 1;
162 ath79_ehci_device.name = "ar913x-ehci";
163 platform_device_register(&ath79_ehci_device);
164}
165
166static void __init ar933x_usb_setup(void)
167{
168 ath79_device_reset_set(AR933X_RESET_USBSUS_OVERRIDE);
169 mdelay(10);
170
171 ath79_device_reset_clear(AR933X_RESET_USB_HOST);
172 mdelay(10);
173
174 ath79_device_reset_clear(AR933X_RESET_USB_PHY);
175 mdelay(10);
176
177 ath79_ehci_resources[0].start = AR933X_EHCI_BASE;
178 ath79_ehci_resources[0].end = AR933X_EHCI_BASE + AR933X_EHCI_SIZE - 1;
179 ath79_ehci_device.name = "ar933x-ehci";
180 platform_device_register(&ath79_ehci_device);
181}
182
183void __init ath79_register_usb(void)
184{
185 if (soc_is_ar71xx())
186 ath79_usb_setup();
187 else if (soc_is_ar7240())
188 ar7240_usb_setup();
189 else if (soc_is_ar7241() || soc_is_ar7242())
190 ar724x_usb_setup();
191 else if (soc_is_ar913x())
192 ar913x_usb_setup();
193 else if (soc_is_ar933x())
194 ar933x_usb_setup();
195 else
196 BUG();
197}
diff --git a/arch/mips/ath79/dev-ar913x-wmac.h b/arch/mips/ath79/dev-usb.h
index 579d562bbda8..4b86a69ca080 100644
--- a/arch/mips/ath79/dev-ar913x-wmac.h
+++ b/arch/mips/ath79/dev-usb.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Atheros AR913X SoC built-in WMAC device support 2 * Atheros AR71XX/AR724X/AR913X USB Host Controller support
3 * 3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> 4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
@@ -9,9 +9,9 @@
9 * by the Free Software Foundation. 9 * by the Free Software Foundation.
10 */ 10 */
11 11
12#ifndef _ATH79_DEV_AR913X_WMAC_H 12#ifndef _ATH79_DEV_USB_H
13#define _ATH79_DEV_AR913X_WMAC_H 13#define _ATH79_DEV_USB_H
14 14
15void ath79_register_ar913x_wmac(u8 *cal_data); 15void ath79_register_usb(void);
16 16
17#endif /* _ATH79_DEV_AR913X_WMAC_H */ 17#endif /* _ATH79_DEV_USB_H */
diff --git a/arch/mips/ath79/dev-wmac.c b/arch/mips/ath79/dev-wmac.c
new file mode 100644
index 000000000000..24f546985b69
--- /dev/null
+++ b/arch/mips/ath79/dev-wmac.c
@@ -0,0 +1,109 @@
1/*
2 * Atheros AR913X/AR933X SoC built-in WMAC device support
3 *
4 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12#include <linux/init.h>
13#include <linux/delay.h>
14#include <linux/irq.h>
15#include <linux/platform_device.h>
16#include <linux/ath9k_platform.h>
17
18#include <asm/mach-ath79/ath79.h>
19#include <asm/mach-ath79/ar71xx_regs.h>
20#include "dev-wmac.h"
21
22static struct ath9k_platform_data ath79_wmac_data;
23
24static struct resource ath79_wmac_resources[] = {
25 {
26 /* .start and .end fields are filled dynamically */
27 .flags = IORESOURCE_MEM,
28 }, {
29 .start = ATH79_CPU_IRQ_IP2,
30 .end = ATH79_CPU_IRQ_IP2,
31 .flags = IORESOURCE_IRQ,
32 },
33};
34
35static struct platform_device ath79_wmac_device = {
36 .name = "ath9k",
37 .id = -1,
38 .resource = ath79_wmac_resources,
39 .num_resources = ARRAY_SIZE(ath79_wmac_resources),
40 .dev = {
41 .platform_data = &ath79_wmac_data,
42 },
43};
44
45static void __init ar913x_wmac_setup(void)
46{
47 /* reset the WMAC */
48 ath79_device_reset_set(AR913X_RESET_AMBA2WMAC);
49 mdelay(10);
50
51 ath79_device_reset_clear(AR913X_RESET_AMBA2WMAC);
52 mdelay(10);
53
54 ath79_wmac_resources[0].start = AR913X_WMAC_BASE;
55 ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1;
56}
57
58
59static int ar933x_wmac_reset(void)
60{
61 ath79_device_reset_clear(AR933X_RESET_WMAC);
62 ath79_device_reset_set(AR933X_RESET_WMAC);
63
64 return 0;
65}
66
67static int ar933x_r1_get_wmac_revision(void)
68{
69 return ath79_soc_rev;
70}
71
72static void __init ar933x_wmac_setup(void)
73{
74 u32 t;
75
76 ar933x_wmac_reset();
77
78 ath79_wmac_device.name = "ar933x_wmac";
79
80 ath79_wmac_resources[0].start = AR933X_WMAC_BASE;
81 ath79_wmac_resources[0].end = AR933X_WMAC_BASE + AR933X_WMAC_SIZE - 1;
82
83 t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
84 if (t & AR933X_BOOTSTRAP_REF_CLK_40)
85 ath79_wmac_data.is_clk_25mhz = false;
86 else
87 ath79_wmac_data.is_clk_25mhz = true;
88
89 if (ath79_soc_rev == 1)
90 ath79_wmac_data.get_mac_revision = ar933x_r1_get_wmac_revision;
91
92 ath79_wmac_data.external_reset = ar933x_wmac_reset;
93}
94
95void __init ath79_register_wmac(u8 *cal_data)
96{
97 if (soc_is_ar913x())
98 ar913x_wmac_setup();
99 if (soc_is_ar933x())
100 ar933x_wmac_setup();
101 else
102 BUG();
103
104 if (cal_data)
105 memcpy(ath79_wmac_data.eeprom_data, cal_data,
106 sizeof(ath79_wmac_data.eeprom_data));
107
108 platform_device_register(&ath79_wmac_device);
109}
diff --git a/arch/mips/ath79/dev-wmac.h b/arch/mips/ath79/dev-wmac.h
new file mode 100644
index 000000000000..c9cd8709f090
--- /dev/null
+++ b/arch/mips/ath79/dev-wmac.h
@@ -0,0 +1,17 @@
1/*
2 * Atheros AR913X/AR933X SoC built-in WMAC device support
3 *
4 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12#ifndef _ATH79_DEV_WMAC_H
13#define _ATH79_DEV_WMAC_H
14
15void ath79_register_wmac(u8 *cal_data);
16
17#endif /* _ATH79_DEV_WMAC_H */
diff --git a/arch/mips/ath79/early_printk.c b/arch/mips/ath79/early_printk.c
index 7499b0e9df26..6a51ced7a293 100644
--- a/arch/mips/ath79/early_printk.c
+++ b/arch/mips/ath79/early_printk.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Atheros AR71XX/AR724X/AR913X SoC early printk support 2 * Atheros AR7XXX/AR9XXX SoC early printk support
3 * 3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> 4 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify it 7 * This program is free software; you can redistribute it and/or modify it
@@ -10,27 +10,85 @@
10 */ 10 */
11 11
12#include <linux/io.h> 12#include <linux/io.h>
13#include <linux/errno.h>
13#include <linux/serial_reg.h> 14#include <linux/serial_reg.h>
14#include <asm/addrspace.h> 15#include <asm/addrspace.h>
15 16
17#include <asm/mach-ath79/ath79.h>
16#include <asm/mach-ath79/ar71xx_regs.h> 18#include <asm/mach-ath79/ar71xx_regs.h>
19#include <asm/mach-ath79/ar933x_uart.h>
17 20
18static inline void prom_wait_thre(void __iomem *base) 21static void (*_prom_putchar) (unsigned char);
22
23static inline void prom_putchar_wait(void __iomem *reg, u32 mask, u32 val)
19{ 24{
20 u32 lsr; 25 u32 t;
21 26
22 do { 27 do {
23 lsr = __raw_readl(base + UART_LSR * 4); 28 t = __raw_readl(reg);
24 if (lsr & UART_LSR_THRE) 29 if ((t & mask) == val)
25 break; 30 break;
26 } while (1); 31 } while (1);
27} 32}
28 33
29void prom_putchar(unsigned char ch) 34static void prom_putchar_ar71xx(unsigned char ch)
30{ 35{
31 void __iomem *base = (void __iomem *)(KSEG1ADDR(AR71XX_UART_BASE)); 36 void __iomem *base = (void __iomem *)(KSEG1ADDR(AR71XX_UART_BASE));
32 37
33 prom_wait_thre(base); 38 prom_putchar_wait(base + UART_LSR * 4, UART_LSR_THRE, UART_LSR_THRE);
34 __raw_writel(ch, base + UART_TX * 4); 39 __raw_writel(ch, base + UART_TX * 4);
35 prom_wait_thre(base); 40 prom_putchar_wait(base + UART_LSR * 4, UART_LSR_THRE, UART_LSR_THRE);
41}
42
43static void prom_putchar_ar933x(unsigned char ch)
44{
45 void __iomem *base = (void __iomem *)(KSEG1ADDR(AR933X_UART_BASE));
46
47 prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR,
48 AR933X_UART_DATA_TX_CSR);
49 __raw_writel(AR933X_UART_DATA_TX_CSR | ch, base + AR933X_UART_DATA_REG);
50 prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR,
51 AR933X_UART_DATA_TX_CSR);
52}
53
54static void prom_putchar_dummy(unsigned char ch)
55{
56 /* nothing to do */
57}
58
59static void prom_putchar_init(void)
60{
61 void __iomem *base;
62 u32 id;
63
64 base = (void __iomem *)(KSEG1ADDR(AR71XX_RESET_BASE));
65 id = __raw_readl(base + AR71XX_RESET_REG_REV_ID);
66 id &= REV_ID_MAJOR_MASK;
67
68 switch (id) {
69 case REV_ID_MAJOR_AR71XX:
70 case REV_ID_MAJOR_AR7240:
71 case REV_ID_MAJOR_AR7241:
72 case REV_ID_MAJOR_AR7242:
73 case REV_ID_MAJOR_AR913X:
74 _prom_putchar = prom_putchar_ar71xx;
75 break;
76
77 case REV_ID_MAJOR_AR9330:
78 case REV_ID_MAJOR_AR9331:
79 _prom_putchar = prom_putchar_ar933x;
80 break;
81
82 default:
83 _prom_putchar = prom_putchar_dummy;
84 break;
85 }
86}
87
88void prom_putchar(unsigned char ch)
89{
90 if (!_prom_putchar)
91 prom_putchar_init();
92
93 _prom_putchar(ch);
36} 94}
diff --git a/arch/mips/ath79/gpio.c b/arch/mips/ath79/gpio.c
index a0c426b82123..a2f8ca630ed6 100644
--- a/arch/mips/ath79/gpio.c
+++ b/arch/mips/ath79/gpio.c
@@ -153,6 +153,8 @@ void __init ath79_gpio_init(void)
153 ath79_gpio_count = AR724X_GPIO_COUNT; 153 ath79_gpio_count = AR724X_GPIO_COUNT;
154 else if (soc_is_ar913x()) 154 else if (soc_is_ar913x())
155 ath79_gpio_count = AR913X_GPIO_COUNT; 155 ath79_gpio_count = AR913X_GPIO_COUNT;
156 else if (soc_is_ar933x())
157 ath79_gpio_count = AR933X_GPIO_COUNT;
156 else 158 else
157 BUG(); 159 BUG();
158 160
diff --git a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c
index ac610d5fe3ba..1b073de44680 100644
--- a/arch/mips/ath79/irq.c
+++ b/arch/mips/ath79/irq.c
@@ -46,6 +46,15 @@ static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc)
46 else if (pending & MISC_INT_TIMER) 46 else if (pending & MISC_INT_TIMER)
47 generic_handle_irq(ATH79_MISC_IRQ_TIMER); 47 generic_handle_irq(ATH79_MISC_IRQ_TIMER);
48 48
49 else if (pending & MISC_INT_TIMER2)
50 generic_handle_irq(ATH79_MISC_IRQ_TIMER2);
51
52 else if (pending & MISC_INT_TIMER3)
53 generic_handle_irq(ATH79_MISC_IRQ_TIMER3);
54
55 else if (pending & MISC_INT_TIMER4)
56 generic_handle_irq(ATH79_MISC_IRQ_TIMER4);
57
49 else if (pending & MISC_INT_OHCI) 58 else if (pending & MISC_INT_OHCI)
50 generic_handle_irq(ATH79_MISC_IRQ_OHCI); 59 generic_handle_irq(ATH79_MISC_IRQ_OHCI);
51 60
@@ -58,6 +67,9 @@ static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc)
58 else if (pending & MISC_INT_WDOG) 67 else if (pending & MISC_INT_WDOG)
59 generic_handle_irq(ATH79_MISC_IRQ_WDOG); 68 generic_handle_irq(ATH79_MISC_IRQ_WDOG);
60 69
70 else if (pending & MISC_INT_ETHSW)
71 generic_handle_irq(ATH79_MISC_IRQ_ETHSW);
72
61 else 73 else
62 spurious_interrupt(); 74 spurious_interrupt();
63} 75}
@@ -117,7 +129,7 @@ static void __init ath79_misc_irq_init(void)
117 129
118 if (soc_is_ar71xx() || soc_is_ar913x()) 130 if (soc_is_ar71xx() || soc_is_ar913x())
119 ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask; 131 ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
120 else if (soc_is_ar724x()) 132 else if (soc_is_ar724x() || soc_is_ar933x())
121 ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack; 133 ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
122 else 134 else
123 BUG(); 135 BUG();
@@ -174,6 +186,9 @@ void __init arch_init_irq(void)
174 } else if (soc_is_ar913x()) { 186 } else if (soc_is_ar913x()) {
175 ath79_ip2_flush_reg = AR913X_DDR_REG_FLUSH_WMAC; 187 ath79_ip2_flush_reg = AR913X_DDR_REG_FLUSH_WMAC;
176 ath79_ip3_flush_reg = AR913X_DDR_REG_FLUSH_USB; 188 ath79_ip3_flush_reg = AR913X_DDR_REG_FLUSH_USB;
189 } else if (soc_is_ar933x()) {
190 ath79_ip2_flush_reg = AR933X_DDR_REG_FLUSH_WMAC;
191 ath79_ip3_flush_reg = AR933X_DDR_REG_FLUSH_USB;
177 } else 192 } else
178 BUG(); 193 BUG();
179 194
diff --git a/arch/mips/ath79/mach-ap121.c b/arch/mips/ath79/mach-ap121.c
new file mode 100644
index 000000000000..4c20200d7c72
--- /dev/null
+++ b/arch/mips/ath79/mach-ap121.c
@@ -0,0 +1,92 @@
1/*
2 * Atheros AP121 board support
3 *
4 * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 */
10
11#include "machtypes.h"
12#include "dev-gpio-buttons.h"
13#include "dev-leds-gpio.h"
14#include "dev-spi.h"
15#include "dev-usb.h"
16#include "dev-wmac.h"
17
18#define AP121_GPIO_LED_WLAN 0
19#define AP121_GPIO_LED_USB 1
20
21#define AP121_GPIO_BTN_JUMPSTART 11
22#define AP121_GPIO_BTN_RESET 12
23
24#define AP121_KEYS_POLL_INTERVAL 20 /* msecs */
25#define AP121_KEYS_DEBOUNCE_INTERVAL (3 * AP121_KEYS_POLL_INTERVAL)
26
27#define AP121_CAL_DATA_ADDR 0x1fff1000
28
29static struct gpio_led ap121_leds_gpio[] __initdata = {
30 {
31 .name = "ap121:green:usb",
32 .gpio = AP121_GPIO_LED_USB,
33 .active_low = 0,
34 },
35 {
36 .name = "ap121:green:wlan",
37 .gpio = AP121_GPIO_LED_WLAN,
38 .active_low = 0,
39 },
40};
41
42static struct gpio_keys_button ap121_gpio_keys[] __initdata = {
43 {
44 .desc = "jumpstart button",
45 .type = EV_KEY,
46 .code = KEY_WPS_BUTTON,
47 .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL,
48 .gpio = AP121_GPIO_BTN_JUMPSTART,
49 .active_low = 1,
50 },
51 {
52 .desc = "reset button",
53 .type = EV_KEY,
54 .code = KEY_RESTART,
55 .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL,
56 .gpio = AP121_GPIO_BTN_RESET,
57 .active_low = 1,
58 }
59};
60
61static struct spi_board_info ap121_spi_info[] = {
62 {
63 .bus_num = 0,
64 .chip_select = 0,
65 .max_speed_hz = 25000000,
66 .modalias = "mx25l1606e",
67 }
68};
69
70static struct ath79_spi_platform_data ap121_spi_data = {
71 .bus_num = 0,
72 .num_chipselect = 1,
73};
74
75static void __init ap121_setup(void)
76{
77 u8 *cal_data = (u8 *) KSEG1ADDR(AP121_CAL_DATA_ADDR);
78
79 ath79_register_leds_gpio(-1, ARRAY_SIZE(ap121_leds_gpio),
80 ap121_leds_gpio);
81 ath79_register_gpio_keys_polled(-1, AP121_KEYS_POLL_INTERVAL,
82 ARRAY_SIZE(ap121_gpio_keys),
83 ap121_gpio_keys);
84
85 ath79_register_spi(&ap121_spi_data, ap121_spi_info,
86 ARRAY_SIZE(ap121_spi_info));
87 ath79_register_usb();
88 ath79_register_wmac(cal_data);
89}
90
91MIPS_MACHINE(ATH79_MACH_AP121, "AP121", "Atheros AP121 reference board",
92 ap121_setup);
diff --git a/arch/mips/ath79/mach-ap81.c b/arch/mips/ath79/mach-ap81.c
index eee4c121deb4..abe19836331c 100644
--- a/arch/mips/ath79/mach-ap81.c
+++ b/arch/mips/ath79/mach-ap81.c
@@ -10,10 +10,11 @@
10 */ 10 */
11 11
12#include "machtypes.h" 12#include "machtypes.h"
13#include "dev-ar913x-wmac.h" 13#include "dev-wmac.h"
14#include "dev-gpio-buttons.h" 14#include "dev-gpio-buttons.h"
15#include "dev-leds-gpio.h" 15#include "dev-leds-gpio.h"
16#include "dev-spi.h" 16#include "dev-spi.h"
17#include "dev-usb.h"
17 18
18#define AP81_GPIO_LED_STATUS 1 19#define AP81_GPIO_LED_STATUS 1
19#define AP81_GPIO_LED_AOSS 3 20#define AP81_GPIO_LED_AOSS 3
@@ -91,7 +92,8 @@ static void __init ap81_setup(void)
91 ap81_gpio_keys); 92 ap81_gpio_keys);
92 ath79_register_spi(&ap81_spi_data, ap81_spi_info, 93 ath79_register_spi(&ap81_spi_data, ap81_spi_info,
93 ARRAY_SIZE(ap81_spi_info)); 94 ARRAY_SIZE(ap81_spi_info));
94 ath79_register_ar913x_wmac(cal_data); 95 ath79_register_wmac(cal_data);
96 ath79_register_usb();
95} 97}
96 98
97MIPS_MACHINE(ATH79_MACH_AP81, "AP81", "Atheros AP81 reference board", 99MIPS_MACHINE(ATH79_MACH_AP81, "AP81", "Atheros AP81 reference board",
diff --git a/arch/mips/ath79/mach-pb44.c b/arch/mips/ath79/mach-pb44.c
index ec7b7a135d53..fe9701a32291 100644
--- a/arch/mips/ath79/mach-pb44.c
+++ b/arch/mips/ath79/mach-pb44.c
@@ -18,6 +18,7 @@
18#include "dev-gpio-buttons.h" 18#include "dev-gpio-buttons.h"
19#include "dev-leds-gpio.h" 19#include "dev-leds-gpio.h"
20#include "dev-spi.h" 20#include "dev-spi.h"
21#include "dev-usb.h"
21 22
22#define PB44_GPIO_I2C_SCL 0 23#define PB44_GPIO_I2C_SCL 0
23#define PB44_GPIO_I2C_SDA 1 24#define PB44_GPIO_I2C_SDA 1
@@ -112,6 +113,7 @@ static void __init pb44_init(void)
112 pb44_gpio_keys); 113 pb44_gpio_keys);
113 ath79_register_spi(&pb44_spi_data, pb44_spi_info, 114 ath79_register_spi(&pb44_spi_data, pb44_spi_info,
114 ARRAY_SIZE(pb44_spi_info)); 115 ARRAY_SIZE(pb44_spi_info));
116 ath79_register_usb();
115} 117}
116 118
117MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board", 119MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board",
diff --git a/arch/mips/ath79/mach-ubnt-xm.c b/arch/mips/ath79/mach-ubnt-xm.c
new file mode 100644
index 000000000000..3c311a539347
--- /dev/null
+++ b/arch/mips/ath79/mach-ubnt-xm.c
@@ -0,0 +1,119 @@
1/*
2 * Ubiquiti Networks XM (rev 1.0) board support
3 *
4 * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
5 *
6 * Derived from: mach-pb44.c
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published
10 * by the Free Software Foundation.
11 */
12
13#include <linux/init.h>
14#include <linux/pci.h>
15
16#ifdef CONFIG_PCI
17#include <linux/ath9k_platform.h>
18#include <asm/mach-ath79/pci-ath724x.h>
19#endif /* CONFIG_PCI */
20
21#include "machtypes.h"
22#include "dev-gpio-buttons.h"
23#include "dev-leds-gpio.h"
24#include "dev-spi.h"
25
26#define UBNT_XM_GPIO_LED_L1 0
27#define UBNT_XM_GPIO_LED_L2 1
28#define UBNT_XM_GPIO_LED_L3 11
29#define UBNT_XM_GPIO_LED_L4 7
30
31#define UBNT_XM_GPIO_BTN_RESET 12
32
33#define UBNT_XM_KEYS_POLL_INTERVAL 20
34#define UBNT_XM_KEYS_DEBOUNCE_INTERVAL (3 * UBNT_XM_KEYS_POLL_INTERVAL)
35
36#define UBNT_XM_PCI_IRQ 48
37#define UBNT_XM_EEPROM_ADDR (u8 *) KSEG1ADDR(0x1fff1000)
38
39static struct gpio_led ubnt_xm_leds_gpio[] __initdata = {
40 {
41 .name = "ubnt-xm:red:link1",
42 .gpio = UBNT_XM_GPIO_LED_L1,
43 .active_low = 0,
44 }, {
45 .name = "ubnt-xm:orange:link2",
46 .gpio = UBNT_XM_GPIO_LED_L2,
47 .active_low = 0,
48 }, {
49 .name = "ubnt-xm:green:link3",
50 .gpio = UBNT_XM_GPIO_LED_L3,
51 .active_low = 0,
52 }, {
53 .name = "ubnt-xm:green:link4",
54 .gpio = UBNT_XM_GPIO_LED_L4,
55 .active_low = 0,
56 },
57};
58
59static struct gpio_keys_button ubnt_xm_gpio_keys[] __initdata = {
60 {
61 .desc = "reset",
62 .type = EV_KEY,
63 .code = KEY_RESTART,
64 .debounce_interval = UBNT_XM_KEYS_DEBOUNCE_INTERVAL,
65 .gpio = UBNT_XM_GPIO_BTN_RESET,
66 .active_low = 1,
67 }
68};
69
70static struct spi_board_info ubnt_xm_spi_info[] = {
71 {
72 .bus_num = 0,
73 .chip_select = 0,
74 .max_speed_hz = 25000000,
75 .modalias = "mx25l6405d",
76 }
77};
78
79static struct ath79_spi_platform_data ubnt_xm_spi_data = {
80 .bus_num = 0,
81 .num_chipselect = 1,
82};
83
84#ifdef CONFIG_PCI
85static struct ath9k_platform_data ubnt_xm_eeprom_data;
86
87static struct ath724x_pci_data ubnt_xm_pci_data[] = {
88 {
89 .irq = UBNT_XM_PCI_IRQ,
90 .pdata = &ubnt_xm_eeprom_data,
91 },
92};
93#endif /* CONFIG_PCI */
94
95static void __init ubnt_xm_init(void)
96{
97 ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_xm_leds_gpio),
98 ubnt_xm_leds_gpio);
99
100 ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL,
101 ARRAY_SIZE(ubnt_xm_gpio_keys),
102 ubnt_xm_gpio_keys);
103
104 ath79_register_spi(&ubnt_xm_spi_data, ubnt_xm_spi_info,
105 ARRAY_SIZE(ubnt_xm_spi_info));
106
107#ifdef CONFIG_PCI
108 memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR,
109 sizeof(ubnt_xm_eeprom_data.eeprom_data));
110
111 ath724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data));
112#endif /* CONFIG_PCI */
113
114}
115
116MIPS_MACHINE(ATH79_MACH_UBNT_XM,
117 "UBNT-XM",
118 "Ubiquiti Networks XM (rev 1.0) board",
119 ubnt_xm_init);
diff --git a/arch/mips/ath79/machtypes.h b/arch/mips/ath79/machtypes.h
index 3940fe470b2d..9a1f3826626e 100644
--- a/arch/mips/ath79/machtypes.h
+++ b/arch/mips/ath79/machtypes.h
@@ -16,8 +16,10 @@
16 16
17enum ath79_mach_type { 17enum ath79_mach_type {
18 ATH79_MACH_GENERIC = 0, 18 ATH79_MACH_GENERIC = 0,
19 ATH79_MACH_AP121, /* Atheros AP121 reference board */
19 ATH79_MACH_AP81, /* Atheros AP81 reference board */ 20 ATH79_MACH_AP81, /* Atheros AP81 reference board */
20 ATH79_MACH_PB44, /* Atheros PB44 reference board */ 21 ATH79_MACH_PB44, /* Atheros PB44 reference board */
22 ATH79_MACH_UBNT_XM, /* Ubiquiti Networks XM board rev 1.0 */
21}; 23};
22 24
23#endif /* _ATH79_MACHTYPE_H */ 25#endif /* _ATH79_MACHTYPE_H */
diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c
index 159b42f106b0..80a7d4023d7f 100644
--- a/arch/mips/ath79/setup.c
+++ b/arch/mips/ath79/setup.c
@@ -101,19 +101,31 @@ static void __init ath79_detect_sys_type(void)
101 case REV_ID_MAJOR_AR7240: 101 case REV_ID_MAJOR_AR7240:
102 ath79_soc = ATH79_SOC_AR7240; 102 ath79_soc = ATH79_SOC_AR7240;
103 chip = "7240"; 103 chip = "7240";
104 rev = (id & AR724X_REV_ID_REVISION_MASK); 104 rev = id & AR724X_REV_ID_REVISION_MASK;
105 break; 105 break;
106 106
107 case REV_ID_MAJOR_AR7241: 107 case REV_ID_MAJOR_AR7241:
108 ath79_soc = ATH79_SOC_AR7241; 108 ath79_soc = ATH79_SOC_AR7241;
109 chip = "7241"; 109 chip = "7241";
110 rev = (id & AR724X_REV_ID_REVISION_MASK); 110 rev = id & AR724X_REV_ID_REVISION_MASK;
111 break; 111 break;
112 112
113 case REV_ID_MAJOR_AR7242: 113 case REV_ID_MAJOR_AR7242:
114 ath79_soc = ATH79_SOC_AR7242; 114 ath79_soc = ATH79_SOC_AR7242;
115 chip = "7242"; 115 chip = "7242";
116 rev = (id & AR724X_REV_ID_REVISION_MASK); 116 rev = id & AR724X_REV_ID_REVISION_MASK;
117 break;
118
119 case REV_ID_MAJOR_AR9330:
120 ath79_soc = ATH79_SOC_AR9330;
121 chip = "9330";
122 rev = id & AR933X_REV_ID_REVISION_MASK;
123 break;
124
125 case REV_ID_MAJOR_AR9331:
126 ath79_soc = ATH79_SOC_AR9331;
127 chip = "9331";
128 rev = id & AR933X_REV_ID_REVISION_MASK;
117 break; 129 break;
118 130
119 case REV_ID_MAJOR_AR913X: 131 case REV_ID_MAJOR_AR913X:
@@ -134,9 +146,11 @@ static void __init ath79_detect_sys_type(void)
134 break; 146 break;
135 147
136 default: 148 default:
137 panic("ath79: unknown SoC, id:0x%08x\n", id); 149 panic("ath79: unknown SoC, id:0x%08x", id);
138 } 150 }
139 151
152 ath79_soc_rev = rev;
153
140 sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev); 154 sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
141 pr_info("SoC: %s\n", ath79_sys_type); 155 pr_info("SoC: %s\n", ath79_sys_type);
142} 156}
diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c
index 1cfdda03546a..aab6b0c40a75 100644
--- a/arch/mips/bcm47xx/setup.c
+++ b/arch/mips/bcm47xx/setup.c
@@ -289,7 +289,7 @@ static void __init bcm47xx_register_ssb(void)
289 err = ssb_bus_ssbbus_register(&(bcm47xx_bus.ssb), SSB_ENUM_BASE, 289 err = ssb_bus_ssbbus_register(&(bcm47xx_bus.ssb), SSB_ENUM_BASE,
290 bcm47xx_get_invariants); 290 bcm47xx_get_invariants);
291 if (err) 291 if (err)
292 panic("Failed to initialize SSB bus (err %d)\n", err); 292 panic("Failed to initialize SSB bus (err %d)", err);
293 293
294 mcore = &bcm47xx_bus.ssb.mipscore; 294 mcore = &bcm47xx_bus.ssb.mipscore;
295 if (nvram_getenv("kernel_args", buf, sizeof(buf)) >= 0) { 295 if (nvram_getenv("kernel_args", buf, sizeof(buf)) >= 0) {
@@ -314,7 +314,7 @@ static void __init bcm47xx_register_bcma(void)
314 314
315 err = bcma_host_soc_register(&bcm47xx_bus.bcma); 315 err = bcma_host_soc_register(&bcm47xx_bus.bcma);
316 if (err) 316 if (err)
317 panic("Failed to initialize BCMA bus (err %d)\n", err); 317 panic("Failed to initialize BCMA bus (err %d)", err);
318} 318}
319#endif 319#endif
320 320
diff --git a/arch/mips/bcm63xx/Kconfig b/arch/mips/bcm63xx/Kconfig
index fb177d6df066..6b1b9ad8d857 100644
--- a/arch/mips/bcm63xx/Kconfig
+++ b/arch/mips/bcm63xx/Kconfig
@@ -20,6 +20,10 @@ config BCM63XX_CPU_6348
20config BCM63XX_CPU_6358 20config BCM63XX_CPU_6358
21 bool "support 6358 CPU" 21 bool "support 6358 CPU"
22 select HW_HAS_PCI 22 select HW_HAS_PCI
23
24config BCM63XX_CPU_6368
25 bool "support 6368 CPU"
26 select HW_HAS_PCI
23endmenu 27endmenu
24 28
25source "arch/mips/bcm63xx/boards/Kconfig" 29source "arch/mips/bcm63xx/boards/Kconfig"
diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c
index 40b223b603be..e62461f817d7 100644
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
@@ -709,15 +709,9 @@ void __init board_prom_init(void)
709 char cfe_version[32]; 709 char cfe_version[32];
710 u32 val; 710 u32 val;
711 711
712 /* read base address of boot chip select (0) 712 /* read base address of boot chip select (0) */
713 * 6345 does not have MPI but boots from standard 713 val = bcm_mpi_readl(MPI_CSBASE_REG(0));
714 * MIPS Flash address */ 714 val &= MPI_CSBASE_BASE_MASK;
715 if (BCMCPU_IS_6345())
716 val = 0x1fc00000;
717 else {
718 val = bcm_mpi_readl(MPI_CSBASE_REG(0));
719 val &= MPI_CSBASE_BASE_MASK;
720 }
721 boot_addr = (u8 *)KSEG1ADDR(val); 715 boot_addr = (u8 *)KSEG1ADDR(val);
722 716
723 /* dump cfe version */ 717 /* dump cfe version */
@@ -797,18 +791,6 @@ void __init board_prom_init(void)
797 } 791 }
798 792
799 bcm_gpio_writel(val, GPIO_MODE_REG); 793 bcm_gpio_writel(val, GPIO_MODE_REG);
800
801 /* Generate MAC address for WLAN and
802 * register our SPROM */
803#ifdef CONFIG_SSB_PCIHOST
804 if (!board_get_mac_address(bcm63xx_sprom.il0mac)) {
805 memcpy(bcm63xx_sprom.et0mac, bcm63xx_sprom.il0mac, ETH_ALEN);
806 memcpy(bcm63xx_sprom.et1mac, bcm63xx_sprom.il0mac, ETH_ALEN);
807 if (ssb_arch_register_fallback_sprom(
808 &bcm63xx_get_fallback_sprom) < 0)
809 printk(KERN_ERR PFX "failed to register fallback SPROM\n");
810 }
811#endif
812} 794}
813 795
814/* 796/*
@@ -892,13 +874,23 @@ int __init board_register_devices(void)
892 if (board.has_dsp) 874 if (board.has_dsp)
893 bcm63xx_dsp_register(&board.dsp); 875 bcm63xx_dsp_register(&board.dsp);
894 876
895 /* read base address of boot chip select (0) */ 877 /* Generate MAC address for WLAN and register our SPROM,
896 if (BCMCPU_IS_6345()) 878 * do this after registering enet devices
897 val = 0x1fc00000; 879 */
898 else { 880#ifdef CONFIG_SSB_PCIHOST
899 val = bcm_mpi_readl(MPI_CSBASE_REG(0)); 881 if (!board_get_mac_address(bcm63xx_sprom.il0mac)) {
900 val &= MPI_CSBASE_BASE_MASK; 882 memcpy(bcm63xx_sprom.et0mac, bcm63xx_sprom.il0mac, ETH_ALEN);
883 memcpy(bcm63xx_sprom.et1mac, bcm63xx_sprom.il0mac, ETH_ALEN);
884 if (ssb_arch_register_fallback_sprom(
885 &bcm63xx_get_fallback_sprom) < 0)
886 pr_err(PFX "failed to register fallback SPROM\n");
901 } 887 }
888#endif
889
890 /* read base address of boot chip select (0) */
891 val = bcm_mpi_readl(MPI_CSBASE_REG(0));
892 val &= MPI_CSBASE_BASE_MASK;
893
902 mtd_resources[0].start = val; 894 mtd_resources[0].start = val;
903 mtd_resources[0].end = 0x1FFFFFFF; 895 mtd_resources[0].end = 0x1FFFFFFF;
904 896
diff --git a/arch/mips/bcm63xx/clk.c b/arch/mips/bcm63xx/clk.c
index 2c68ee9ccee2..9d57c71b7b58 100644
--- a/arch/mips/bcm63xx/clk.c
+++ b/arch/mips/bcm63xx/clk.c
@@ -10,6 +10,7 @@
10#include <linux/mutex.h> 10#include <linux/mutex.h>
11#include <linux/err.h> 11#include <linux/err.h>
12#include <linux/clk.h> 12#include <linux/clk.h>
13#include <linux/delay.h>
13#include <bcm63xx_cpu.h> 14#include <bcm63xx_cpu.h>
14#include <bcm63xx_io.h> 15#include <bcm63xx_io.h>
15#include <bcm63xx_regs.h> 16#include <bcm63xx_regs.h>
@@ -113,6 +114,34 @@ static struct clk clk_ephy = {
113}; 114};
114 115
115/* 116/*
117 * Ethernet switch clock
118 */
119static void enetsw_set(struct clk *clk, int enable)
120{
121 if (!BCMCPU_IS_6368())
122 return;
123 bcm_hwclock_set(CKCTL_6368_ROBOSW_CLK_EN |
124 CKCTL_6368_SWPKT_USB_EN |
125 CKCTL_6368_SWPKT_SAR_EN, enable);
126 if (enable) {
127 u32 val;
128
129 /* reset switch core afer clock change */
130 val = bcm_perf_readl(PERF_SOFTRESET_6368_REG);
131 val &= ~SOFTRESET_6368_ENETSW_MASK;
132 bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
133 msleep(10);
134 val |= SOFTRESET_6368_ENETSW_MASK;
135 bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
136 msleep(10);
137 }
138}
139
140static struct clk clk_enetsw = {
141 .set = enetsw_set,
142};
143
144/*
116 * PCM clock 145 * PCM clock
117 */ 146 */
118static void pcm_set(struct clk *clk, int enable) 147static void pcm_set(struct clk *clk, int enable)
@@ -131,9 +160,10 @@ static struct clk clk_pcm = {
131 */ 160 */
132static void usbh_set(struct clk *clk, int enable) 161static void usbh_set(struct clk *clk, int enable)
133{ 162{
134 if (!BCMCPU_IS_6348()) 163 if (BCMCPU_IS_6348())
135 return; 164 bcm_hwclock_set(CKCTL_6348_USBH_EN, enable);
136 bcm_hwclock_set(CKCTL_6348_USBH_EN, enable); 165 else if (BCMCPU_IS_6368())
166 bcm_hwclock_set(CKCTL_6368_USBH_CLK_EN, enable);
137} 167}
138 168
139static struct clk clk_usbh = { 169static struct clk clk_usbh = {
@@ -162,6 +192,36 @@ static struct clk clk_spi = {
162}; 192};
163 193
164/* 194/*
195 * XTM clock
196 */
197static void xtm_set(struct clk *clk, int enable)
198{
199 if (!BCMCPU_IS_6368())
200 return;
201
202 bcm_hwclock_set(CKCTL_6368_SAR_CLK_EN |
203 CKCTL_6368_SWPKT_SAR_EN, enable);
204
205 if (enable) {
206 u32 val;
207
208 /* reset sar core afer clock change */
209 val = bcm_perf_readl(PERF_SOFTRESET_6368_REG);
210 val &= ~SOFTRESET_6368_SAR_MASK;
211 bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
212 mdelay(1);
213 val |= SOFTRESET_6368_SAR_MASK;
214 bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
215 mdelay(1);
216 }
217}
218
219
220static struct clk clk_xtm = {
221 .set = xtm_set,
222};
223
224/*
165 * Internal peripheral clock 225 * Internal peripheral clock
166 */ 226 */
167static struct clk clk_periph = { 227static struct clk clk_periph = {
@@ -204,12 +264,16 @@ struct clk *clk_get(struct device *dev, const char *id)
204 return &clk_enet0; 264 return &clk_enet0;
205 if (!strcmp(id, "enet1")) 265 if (!strcmp(id, "enet1"))
206 return &clk_enet1; 266 return &clk_enet1;
267 if (!strcmp(id, "enetsw"))
268 return &clk_enetsw;
207 if (!strcmp(id, "ephy")) 269 if (!strcmp(id, "ephy"))
208 return &clk_ephy; 270 return &clk_ephy;
209 if (!strcmp(id, "usbh")) 271 if (!strcmp(id, "usbh"))
210 return &clk_usbh; 272 return &clk_usbh;
211 if (!strcmp(id, "spi")) 273 if (!strcmp(id, "spi"))
212 return &clk_spi; 274 return &clk_spi;
275 if (!strcmp(id, "xtm"))
276 return &clk_xtm;
213 if (!strcmp(id, "periph")) 277 if (!strcmp(id, "periph"))
214 return &clk_periph; 278 return &clk_periph;
215 if (BCMCPU_IS_6358() && !strcmp(id, "pcm")) 279 if (BCMCPU_IS_6358() && !strcmp(id, "pcm"))
diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c
index 7c7e4d4486ce..8f0d6c7725ea 100644
--- a/arch/mips/bcm63xx/cpu.c
+++ b/arch/mips/bcm63xx/cpu.c
@@ -29,166 +29,47 @@ static u16 bcm63xx_cpu_rev;
29static unsigned int bcm63xx_cpu_freq; 29static unsigned int bcm63xx_cpu_freq;
30static unsigned int bcm63xx_memory_size; 30static unsigned int bcm63xx_memory_size;
31 31
32/* 32static const unsigned long bcm6338_regs_base[] = {
33 * 6338 register sets and irqs 33 __GEN_CPU_REGS_TABLE(6338)
34 */
35static const unsigned long bcm96338_regs_base[] = {
36 [RSET_DSL_LMEM] = BCM_6338_DSL_LMEM_BASE,
37 [RSET_PERF] = BCM_6338_PERF_BASE,
38 [RSET_TIMER] = BCM_6338_TIMER_BASE,
39 [RSET_WDT] = BCM_6338_WDT_BASE,
40 [RSET_UART0] = BCM_6338_UART0_BASE,
41 [RSET_UART1] = BCM_6338_UART1_BASE,
42 [RSET_GPIO] = BCM_6338_GPIO_BASE,
43 [RSET_SPI] = BCM_6338_SPI_BASE,
44 [RSET_OHCI0] = BCM_6338_OHCI0_BASE,
45 [RSET_OHCI_PRIV] = BCM_6338_OHCI_PRIV_BASE,
46 [RSET_USBH_PRIV] = BCM_6338_USBH_PRIV_BASE,
47 [RSET_UDC0] = BCM_6338_UDC0_BASE,
48 [RSET_MPI] = BCM_6338_MPI_BASE,
49 [RSET_PCMCIA] = BCM_6338_PCMCIA_BASE,
50 [RSET_SDRAM] = BCM_6338_SDRAM_BASE,
51 [RSET_DSL] = BCM_6338_DSL_BASE,
52 [RSET_ENET0] = BCM_6338_ENET0_BASE,
53 [RSET_ENET1] = BCM_6338_ENET1_BASE,
54 [RSET_ENETDMA] = BCM_6338_ENETDMA_BASE,
55 [RSET_MEMC] = BCM_6338_MEMC_BASE,
56 [RSET_DDR] = BCM_6338_DDR_BASE,
57}; 34};
58 35
59static const int bcm96338_irqs[] = { 36static const int bcm6338_irqs[] = {
60 [IRQ_TIMER] = BCM_6338_TIMER_IRQ, 37 __GEN_CPU_IRQ_TABLE(6338)
61 [IRQ_UART0] = BCM_6338_UART0_IRQ,
62 [IRQ_DSL] = BCM_6338_DSL_IRQ,
63 [IRQ_ENET0] = BCM_6338_ENET0_IRQ,
64 [IRQ_ENET_PHY] = BCM_6338_ENET_PHY_IRQ,
65 [IRQ_ENET0_RXDMA] = BCM_6338_ENET0_RXDMA_IRQ,
66 [IRQ_ENET0_TXDMA] = BCM_6338_ENET0_TXDMA_IRQ,
67}; 38};
68 39
69/* 40static const unsigned long bcm6345_regs_base[] = {
70 * 6345 register sets and irqs 41 __GEN_CPU_REGS_TABLE(6345)
71 */
72static const unsigned long bcm96345_regs_base[] = {
73 [RSET_DSL_LMEM] = BCM_6345_DSL_LMEM_BASE,
74 [RSET_PERF] = BCM_6345_PERF_BASE,
75 [RSET_TIMER] = BCM_6345_TIMER_BASE,
76 [RSET_WDT] = BCM_6345_WDT_BASE,
77 [RSET_UART0] = BCM_6345_UART0_BASE,
78 [RSET_UART1] = BCM_6345_UART1_BASE,
79 [RSET_GPIO] = BCM_6345_GPIO_BASE,
80 [RSET_SPI] = BCM_6345_SPI_BASE,
81 [RSET_UDC0] = BCM_6345_UDC0_BASE,
82 [RSET_OHCI0] = BCM_6345_OHCI0_BASE,
83 [RSET_OHCI_PRIV] = BCM_6345_OHCI_PRIV_BASE,
84 [RSET_USBH_PRIV] = BCM_6345_USBH_PRIV_BASE,
85 [RSET_MPI] = BCM_6345_MPI_BASE,
86 [RSET_PCMCIA] = BCM_6345_PCMCIA_BASE,
87 [RSET_DSL] = BCM_6345_DSL_BASE,
88 [RSET_ENET0] = BCM_6345_ENET0_BASE,
89 [RSET_ENET1] = BCM_6345_ENET1_BASE,
90 [RSET_ENETDMA] = BCM_6345_ENETDMA_BASE,
91 [RSET_EHCI0] = BCM_6345_EHCI0_BASE,
92 [RSET_SDRAM] = BCM_6345_SDRAM_BASE,
93 [RSET_MEMC] = BCM_6345_MEMC_BASE,
94 [RSET_DDR] = BCM_6345_DDR_BASE,
95}; 42};
96 43
97static const int bcm96345_irqs[] = { 44static const int bcm6345_irqs[] = {
98 [IRQ_TIMER] = BCM_6345_TIMER_IRQ, 45 __GEN_CPU_IRQ_TABLE(6345)
99 [IRQ_UART0] = BCM_6345_UART0_IRQ,
100 [IRQ_DSL] = BCM_6345_DSL_IRQ,
101 [IRQ_ENET0] = BCM_6345_ENET0_IRQ,
102 [IRQ_ENET_PHY] = BCM_6345_ENET_PHY_IRQ,
103 [IRQ_ENET0_RXDMA] = BCM_6345_ENET0_RXDMA_IRQ,
104 [IRQ_ENET0_TXDMA] = BCM_6345_ENET0_TXDMA_IRQ,
105}; 46};
106 47
107/* 48static const unsigned long bcm6348_regs_base[] = {
108 * 6348 register sets and irqs 49 __GEN_CPU_REGS_TABLE(6348)
109 */
110static const unsigned long bcm96348_regs_base[] = {
111 [RSET_DSL_LMEM] = BCM_6348_DSL_LMEM_BASE,
112 [RSET_PERF] = BCM_6348_PERF_BASE,
113 [RSET_TIMER] = BCM_6348_TIMER_BASE,
114 [RSET_WDT] = BCM_6348_WDT_BASE,
115 [RSET_UART0] = BCM_6348_UART0_BASE,
116 [RSET_UART1] = BCM_6348_UART1_BASE,
117 [RSET_GPIO] = BCM_6348_GPIO_BASE,
118 [RSET_SPI] = BCM_6348_SPI_BASE,
119 [RSET_OHCI0] = BCM_6348_OHCI0_BASE,
120 [RSET_OHCI_PRIV] = BCM_6348_OHCI_PRIV_BASE,
121 [RSET_USBH_PRIV] = BCM_6348_USBH_PRIV_BASE,
122 [RSET_MPI] = BCM_6348_MPI_BASE,
123 [RSET_PCMCIA] = BCM_6348_PCMCIA_BASE,
124 [RSET_SDRAM] = BCM_6348_SDRAM_BASE,
125 [RSET_DSL] = BCM_6348_DSL_BASE,
126 [RSET_ENET0] = BCM_6348_ENET0_BASE,
127 [RSET_ENET1] = BCM_6348_ENET1_BASE,
128 [RSET_ENETDMA] = BCM_6348_ENETDMA_BASE,
129 [RSET_MEMC] = BCM_6348_MEMC_BASE,
130 [RSET_DDR] = BCM_6348_DDR_BASE,
131}; 50};
132 51
133static const int bcm96348_irqs[] = { 52static const int bcm6348_irqs[] = {
134 [IRQ_TIMER] = BCM_6348_TIMER_IRQ, 53 __GEN_CPU_IRQ_TABLE(6348)
135 [IRQ_UART0] = BCM_6348_UART0_IRQ, 54
136 [IRQ_DSL] = BCM_6348_DSL_IRQ,
137 [IRQ_ENET0] = BCM_6348_ENET0_IRQ,
138 [IRQ_ENET1] = BCM_6348_ENET1_IRQ,
139 [IRQ_ENET_PHY] = BCM_6348_ENET_PHY_IRQ,
140 [IRQ_OHCI0] = BCM_6348_OHCI0_IRQ,
141 [IRQ_PCMCIA] = BCM_6348_PCMCIA_IRQ,
142 [IRQ_ENET0_RXDMA] = BCM_6348_ENET0_RXDMA_IRQ,
143 [IRQ_ENET0_TXDMA] = BCM_6348_ENET0_TXDMA_IRQ,
144 [IRQ_ENET1_RXDMA] = BCM_6348_ENET1_RXDMA_IRQ,
145 [IRQ_ENET1_TXDMA] = BCM_6348_ENET1_TXDMA_IRQ,
146 [IRQ_PCI] = BCM_6348_PCI_IRQ,
147}; 55};
148 56
149/* 57static const unsigned long bcm6358_regs_base[] = {
150 * 6358 register sets and irqs 58 __GEN_CPU_REGS_TABLE(6358)
151 */ 59};
152static const unsigned long bcm96358_regs_base[] = { 60
153 [RSET_DSL_LMEM] = BCM_6358_DSL_LMEM_BASE, 61static const int bcm6358_irqs[] = {
154 [RSET_PERF] = BCM_6358_PERF_BASE, 62 __GEN_CPU_IRQ_TABLE(6358)
155 [RSET_TIMER] = BCM_6358_TIMER_BASE, 63
156 [RSET_WDT] = BCM_6358_WDT_BASE,
157 [RSET_UART0] = BCM_6358_UART0_BASE,
158 [RSET_UART1] = BCM_6358_UART1_BASE,
159 [RSET_GPIO] = BCM_6358_GPIO_BASE,
160 [RSET_SPI] = BCM_6358_SPI_BASE,
161 [RSET_OHCI0] = BCM_6358_OHCI0_BASE,
162 [RSET_EHCI0] = BCM_6358_EHCI0_BASE,
163 [RSET_OHCI_PRIV] = BCM_6358_OHCI_PRIV_BASE,
164 [RSET_USBH_PRIV] = BCM_6358_USBH_PRIV_BASE,
165 [RSET_MPI] = BCM_6358_MPI_BASE,
166 [RSET_PCMCIA] = BCM_6358_PCMCIA_BASE,
167 [RSET_SDRAM] = BCM_6358_SDRAM_BASE,
168 [RSET_DSL] = BCM_6358_DSL_BASE,
169 [RSET_ENET0] = BCM_6358_ENET0_BASE,
170 [RSET_ENET1] = BCM_6358_ENET1_BASE,
171 [RSET_ENETDMA] = BCM_6358_ENETDMA_BASE,
172 [RSET_MEMC] = BCM_6358_MEMC_BASE,
173 [RSET_DDR] = BCM_6358_DDR_BASE,
174}; 64};
175 65
176static const int bcm96358_irqs[] = { 66static const unsigned long bcm6368_regs_base[] = {
177 [IRQ_TIMER] = BCM_6358_TIMER_IRQ, 67 __GEN_CPU_REGS_TABLE(6368)
178 [IRQ_UART0] = BCM_6358_UART0_IRQ, 68};
179 [IRQ_UART1] = BCM_6358_UART1_IRQ, 69
180 [IRQ_DSL] = BCM_6358_DSL_IRQ, 70static const int bcm6368_irqs[] = {
181 [IRQ_ENET0] = BCM_6358_ENET0_IRQ, 71 __GEN_CPU_IRQ_TABLE(6368)
182 [IRQ_ENET1] = BCM_6358_ENET1_IRQ, 72
183 [IRQ_ENET_PHY] = BCM_6358_ENET_PHY_IRQ,
184 [IRQ_OHCI0] = BCM_6358_OHCI0_IRQ,
185 [IRQ_EHCI0] = BCM_6358_EHCI0_IRQ,
186 [IRQ_PCMCIA] = BCM_6358_PCMCIA_IRQ,
187 [IRQ_ENET0_RXDMA] = BCM_6358_ENET0_RXDMA_IRQ,
188 [IRQ_ENET0_TXDMA] = BCM_6358_ENET0_TXDMA_IRQ,
189 [IRQ_ENET1_RXDMA] = BCM_6358_ENET1_RXDMA_IRQ,
190 [IRQ_ENET1_TXDMA] = BCM_6358_ENET1_TXDMA_IRQ,
191 [IRQ_PCI] = BCM_6358_PCI_IRQ,
192}; 73};
193 74
194u16 __bcm63xx_get_cpu_id(void) 75u16 __bcm63xx_get_cpu_id(void)
@@ -217,20 +98,19 @@ unsigned int bcm63xx_get_memory_size(void)
217 98
218static unsigned int detect_cpu_clock(void) 99static unsigned int detect_cpu_clock(void)
219{ 100{
220 unsigned int tmp, n1 = 0, n2 = 0, m1 = 0; 101 switch (bcm63xx_get_cpu_id()) {
221 102 case BCM6338_CPU_ID:
222 /* BCM6338 has a fixed 240 Mhz frequency */ 103 /* BCM6338 has a fixed 240 Mhz frequency */
223 if (BCMCPU_IS_6338())
224 return 240000000; 104 return 240000000;
225 105
226 /* BCM6345 has a fixed 140Mhz frequency */ 106 case BCM6345_CPU_ID:
227 if (BCMCPU_IS_6345()) 107 /* BCM6345 has a fixed 140Mhz frequency */
228 return 140000000; 108 return 140000000;
229 109
230 /* 110 case BCM6348_CPU_ID:
231 * frequency depends on PLL configuration: 111 {
232 */ 112 unsigned int tmp, n1, n2, m1;
233 if (BCMCPU_IS_6348()) { 113
234 /* 16MHz * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) */ 114 /* 16MHz * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) */
235 tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG); 115 tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG);
236 n1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT; 116 n1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT;
@@ -239,17 +119,47 @@ static unsigned int detect_cpu_clock(void)
239 n1 += 1; 119 n1 += 1;
240 n2 += 2; 120 n2 += 2;
241 m1 += 1; 121 m1 += 1;
122 return (16 * 1000000 * n1 * n2) / m1;
242 } 123 }
243 124
244 if (BCMCPU_IS_6358()) { 125 case BCM6358_CPU_ID:
126 {
127 unsigned int tmp, n1, n2, m1;
128
245 /* 16MHz * N1 * N2 / M1_CPU */ 129 /* 16MHz * N1 * N2 / M1_CPU */
246 tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG); 130 tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG);
247 n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT; 131 n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT;
248 n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT; 132 n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT;
249 m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT; 133 m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT;
134 return (16 * 1000000 * n1 * n2) / m1;
250 } 135 }
251 136
252 return (16 * 1000000 * n1 * n2) / m1; 137 case BCM6368_CPU_ID:
138 {
139 unsigned int tmp, p1, p2, ndiv, m1;
140
141 /* (64MHz / P1) * P2 * NDIV / M1_CPU */
142 tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_6368_REG);
143
144 p1 = (tmp & DMIPSPLLCFG_6368_P1_MASK) >>
145 DMIPSPLLCFG_6368_P1_SHIFT;
146
147 p2 = (tmp & DMIPSPLLCFG_6368_P2_MASK) >>
148 DMIPSPLLCFG_6368_P2_SHIFT;
149
150 ndiv = (tmp & DMIPSPLLCFG_6368_NDIV_MASK) >>
151 DMIPSPLLCFG_6368_NDIV_SHIFT;
152
153 tmp = bcm_ddr_readl(DDR_DMIPSPLLDIV_6368_REG);
154 m1 = (tmp & DMIPSPLLDIV_6368_MDIV_MASK) >>
155 DMIPSPLLDIV_6368_MDIV_SHIFT;
156
157 return (((64 * 1000000) / p1) * p2 * ndiv) / m1;
158 }
159
160 default:
161 BUG();
162 }
253} 163}
254 164
255/* 165/*
@@ -260,8 +170,10 @@ static unsigned int detect_memory_size(void)
260 unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0; 170 unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
261 u32 val; 171 u32 val;
262 172
263 if (BCMCPU_IS_6345()) 173 if (BCMCPU_IS_6345()) {
264 return (8 * 1024 * 1024); 174 val = bcm_sdram_readl(SDRAM_MBASE_REG);
175 return (val * 8 * 1024 * 1024);
176 }
265 177
266 if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) { 178 if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
267 val = bcm_sdram_readl(SDRAM_CFG_REG); 179 val = bcm_sdram_readl(SDRAM_CFG_REG);
@@ -271,7 +183,7 @@ static unsigned int detect_memory_size(void)
271 banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1; 183 banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
272 } 184 }
273 185
274 if (BCMCPU_IS_6358()) { 186 if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
275 val = bcm_memc_readl(MEMC_CFG_REG); 187 val = bcm_memc_readl(MEMC_CFG_REG);
276 rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT; 188 rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
277 cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT; 189 cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
@@ -301,24 +213,33 @@ void __init bcm63xx_cpu_init(void)
301 case CPU_BMIPS3300: 213 case CPU_BMIPS3300:
302 if ((read_c0_prid() & 0xff00) == PRID_IMP_BMIPS3300_ALT) { 214 if ((read_c0_prid() & 0xff00) == PRID_IMP_BMIPS3300_ALT) {
303 expected_cpu_id = BCM6348_CPU_ID; 215 expected_cpu_id = BCM6348_CPU_ID;
304 bcm63xx_regs_base = bcm96348_regs_base; 216 bcm63xx_regs_base = bcm6348_regs_base;
305 bcm63xx_irqs = bcm96348_irqs; 217 bcm63xx_irqs = bcm6348_irqs;
306 } else { 218 } else {
307 __cpu_name[cpu] = "Broadcom BCM6338"; 219 __cpu_name[cpu] = "Broadcom BCM6338";
308 expected_cpu_id = BCM6338_CPU_ID; 220 expected_cpu_id = BCM6338_CPU_ID;
309 bcm63xx_regs_base = bcm96338_regs_base; 221 bcm63xx_regs_base = bcm6338_regs_base;
310 bcm63xx_irqs = bcm96338_irqs; 222 bcm63xx_irqs = bcm6338_irqs;
311 } 223 }
312 break; 224 break;
313 case CPU_BMIPS32: 225 case CPU_BMIPS32:
314 expected_cpu_id = BCM6345_CPU_ID; 226 expected_cpu_id = BCM6345_CPU_ID;
315 bcm63xx_regs_base = bcm96345_regs_base; 227 bcm63xx_regs_base = bcm6345_regs_base;
316 bcm63xx_irqs = bcm96345_irqs; 228 bcm63xx_irqs = bcm6345_irqs;
317 break; 229 break;
318 case CPU_BMIPS4350: 230 case CPU_BMIPS4350:
319 expected_cpu_id = BCM6358_CPU_ID; 231 switch (read_c0_prid() & 0xf0) {
320 bcm63xx_regs_base = bcm96358_regs_base; 232 case 0x10:
321 bcm63xx_irqs = bcm96358_irqs; 233 expected_cpu_id = BCM6358_CPU_ID;
234 bcm63xx_regs_base = bcm6358_regs_base;
235 bcm63xx_irqs = bcm6358_irqs;
236 break;
237 case 0x30:
238 expected_cpu_id = BCM6368_CPU_ID;
239 bcm63xx_regs_base = bcm6368_regs_base;
240 bcm63xx_irqs = bcm6368_irqs;
241 break;
242 }
322 break; 243 break;
323 } 244 }
324 245
diff --git a/arch/mips/bcm63xx/dev-uart.c b/arch/mips/bcm63xx/dev-uart.c
index c2963da0253e..d6e42c608325 100644
--- a/arch/mips/bcm63xx/dev-uart.c
+++ b/arch/mips/bcm63xx/dev-uart.c
@@ -54,7 +54,7 @@ int __init bcm63xx_uart_register(unsigned int id)
54 if (id >= ARRAY_SIZE(bcm63xx_uart_devices)) 54 if (id >= ARRAY_SIZE(bcm63xx_uart_devices))
55 return -ENODEV; 55 return -ENODEV;
56 56
57 if (id == 1 && !BCMCPU_IS_6358()) 57 if (id == 1 && (!BCMCPU_IS_6358() && !BCMCPU_IS_6368()))
58 return -ENODEV; 58 return -ENODEV;
59 59
60 if (id == 0) { 60 if (id == 0) {
diff --git a/arch/mips/bcm63xx/gpio.c b/arch/mips/bcm63xx/gpio.c
index f560fe7d38dd..a6c2135dbf38 100644
--- a/arch/mips/bcm63xx/gpio.c
+++ b/arch/mips/bcm63xx/gpio.c
@@ -4,7 +4,7 @@
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> 6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org> 7 * Copyright (C) 2008-2011 Florian Fainelli <florian@openwrt.org>
8 */ 8 */
9 9
10#include <linux/kernel.h> 10#include <linux/kernel.h>
@@ -18,6 +18,34 @@
18#include <bcm63xx_io.h> 18#include <bcm63xx_io.h>
19#include <bcm63xx_regs.h> 19#include <bcm63xx_regs.h>
20 20
21#ifndef BCMCPU_RUNTIME_DETECT
22#define gpio_out_low_reg GPIO_DATA_LO_REG
23#ifdef CONFIG_BCM63XX_CPU_6345
24#ifdef gpio_out_low_reg
25#undef gpio_out_low_reg
26#define gpio_out_low_reg GPIO_DATA_LO_REG_6345
27#endif /* gpio_out_low_reg */
28#endif /* CONFIG_BCM63XX_CPU_6345 */
29
30static inline void bcm63xx_gpio_out_low_reg_init(void)
31{
32}
33#else /* ! BCMCPU_RUNTIME_DETECT */
34static u32 gpio_out_low_reg;
35
36static void bcm63xx_gpio_out_low_reg_init(void)
37{
38 switch (bcm63xx_get_cpu_id()) {
39 case BCM6345_CPU_ID:
40 gpio_out_low_reg = GPIO_DATA_LO_REG_6345;
41 break;
42 default:
43 gpio_out_low_reg = GPIO_DATA_LO_REG;
44 break;
45 }
46}
47#endif /* ! BCMCPU_RUNTIME_DETECT */
48
21static DEFINE_SPINLOCK(bcm63xx_gpio_lock); 49static DEFINE_SPINLOCK(bcm63xx_gpio_lock);
22static u32 gpio_out_low, gpio_out_high; 50static u32 gpio_out_low, gpio_out_high;
23 51
@@ -33,7 +61,7 @@ static void bcm63xx_gpio_set(struct gpio_chip *chip,
33 BUG(); 61 BUG();
34 62
35 if (gpio < 32) { 63 if (gpio < 32) {
36 reg = GPIO_DATA_LO_REG; 64 reg = gpio_out_low_reg;
37 mask = 1 << gpio; 65 mask = 1 << gpio;
38 v = &gpio_out_low; 66 v = &gpio_out_low;
39 } else { 67 } else {
@@ -60,7 +88,7 @@ static int bcm63xx_gpio_get(struct gpio_chip *chip, unsigned gpio)
60 BUG(); 88 BUG();
61 89
62 if (gpio < 32) { 90 if (gpio < 32) {
63 reg = GPIO_DATA_LO_REG; 91 reg = gpio_out_low_reg;
64 mask = 1 << gpio; 92 mask = 1 << gpio;
65 } else { 93 } else {
66 reg = GPIO_DATA_HI_REG; 94 reg = GPIO_DATA_HI_REG;
@@ -125,8 +153,11 @@ static struct gpio_chip bcm63xx_gpio_chip = {
125 153
126int __init bcm63xx_gpio_init(void) 154int __init bcm63xx_gpio_init(void)
127{ 155{
128 gpio_out_low = bcm_gpio_readl(GPIO_DATA_LO_REG); 156 bcm63xx_gpio_out_low_reg_init();
129 gpio_out_high = bcm_gpio_readl(GPIO_DATA_HI_REG); 157
158 gpio_out_low = bcm_gpio_readl(gpio_out_low_reg);
159 if (!BCMCPU_IS_6345())
160 gpio_out_high = bcm_gpio_readl(GPIO_DATA_HI_REG);
130 bcm63xx_gpio_chip.ngpio = bcm63xx_gpio_count(); 161 bcm63xx_gpio_chip.ngpio = bcm63xx_gpio_count();
131 pr_info("registering %d GPIOs\n", bcm63xx_gpio_chip.ngpio); 162 pr_info("registering %d GPIOs\n", bcm63xx_gpio_chip.ngpio);
132 163
diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c
index 162e11b4ed75..9a216a451d92 100644
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
@@ -19,19 +19,187 @@
19#include <bcm63xx_io.h> 19#include <bcm63xx_io.h>
20#include <bcm63xx_irq.h> 20#include <bcm63xx_irq.h>
21 21
22static void __dispatch_internal(void) __maybe_unused;
23static void __dispatch_internal_64(void) __maybe_unused;
24static void __internal_irq_mask_32(unsigned int irq) __maybe_unused;
25static void __internal_irq_mask_64(unsigned int irq) __maybe_unused;
26static void __internal_irq_unmask_32(unsigned int irq) __maybe_unused;
27static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
28
29#ifndef BCMCPU_RUNTIME_DETECT
30#ifdef CONFIG_BCM63XX_CPU_6338
31#define irq_stat_reg PERF_IRQSTAT_6338_REG
32#define irq_mask_reg PERF_IRQMASK_6338_REG
33#define irq_bits 32
34#define is_ext_irq_cascaded 0
35#define ext_irq_start 0
36#define ext_irq_end 0
37#define ext_irq_count 4
38#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6338
39#define ext_irq_cfg_reg2 0
40#endif
41#ifdef CONFIG_BCM63XX_CPU_6345
42#define irq_stat_reg PERF_IRQSTAT_6345_REG
43#define irq_mask_reg PERF_IRQMASK_6345_REG
44#define irq_bits 32
45#define is_ext_irq_cascaded 0
46#define ext_irq_start 0
47#define ext_irq_end 0
48#define ext_irq_count 0
49#define ext_irq_cfg_reg1 0
50#define ext_irq_cfg_reg2 0
51#endif
52#ifdef CONFIG_BCM63XX_CPU_6348
53#define irq_stat_reg PERF_IRQSTAT_6348_REG
54#define irq_mask_reg PERF_IRQMASK_6348_REG
55#define irq_bits 32
56#define is_ext_irq_cascaded 0
57#define ext_irq_start 0
58#define ext_irq_end 0
59#define ext_irq_count 4
60#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6348
61#define ext_irq_cfg_reg2 0
62#endif
63#ifdef CONFIG_BCM63XX_CPU_6358
64#define irq_stat_reg PERF_IRQSTAT_6358_REG
65#define irq_mask_reg PERF_IRQMASK_6358_REG
66#define irq_bits 32
67#define is_ext_irq_cascaded 1
68#define ext_irq_start (BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE)
69#define ext_irq_end (BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE)
70#define ext_irq_count 4
71#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6358
72#define ext_irq_cfg_reg2 0
73#endif
74#ifdef CONFIG_BCM63XX_CPU_6368
75#define irq_stat_reg PERF_IRQSTAT_6368_REG
76#define irq_mask_reg PERF_IRQMASK_6368_REG
77#define irq_bits 64
78#define is_ext_irq_cascaded 1
79#define ext_irq_start (BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE)
80#define ext_irq_end (BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE)
81#define ext_irq_count 6
82#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6368
83#define ext_irq_cfg_reg2 PERF_EXTIRQ_CFG_REG2_6368
84#endif
85
86#if irq_bits == 32
87#define dispatch_internal __dispatch_internal
88#define internal_irq_mask __internal_irq_mask_32
89#define internal_irq_unmask __internal_irq_unmask_32
90#else
91#define dispatch_internal __dispatch_internal_64
92#define internal_irq_mask __internal_irq_mask_64
93#define internal_irq_unmask __internal_irq_unmask_64
94#endif
95
96#define irq_stat_addr (bcm63xx_regset_address(RSET_PERF) + irq_stat_reg)
97#define irq_mask_addr (bcm63xx_regset_address(RSET_PERF) + irq_mask_reg)
98
99static inline void bcm63xx_init_irq(void)
100{
101}
102#else /* ! BCMCPU_RUNTIME_DETECT */
103
104static u32 irq_stat_addr, irq_mask_addr;
105static void (*dispatch_internal)(void);
106static int is_ext_irq_cascaded;
107static unsigned int ext_irq_count;
108static unsigned int ext_irq_start, ext_irq_end;
109static unsigned int ext_irq_cfg_reg1, ext_irq_cfg_reg2;
110static void (*internal_irq_mask)(unsigned int irq);
111static void (*internal_irq_unmask)(unsigned int irq);
112
113static void bcm63xx_init_irq(void)
114{
115 int irq_bits;
116
117 irq_stat_addr = bcm63xx_regset_address(RSET_PERF);
118 irq_mask_addr = bcm63xx_regset_address(RSET_PERF);
119
120 switch (bcm63xx_get_cpu_id()) {
121 case BCM6338_CPU_ID:
122 irq_stat_addr += PERF_IRQSTAT_6338_REG;
123 irq_mask_addr += PERF_IRQMASK_6338_REG;
124 irq_bits = 32;
125 break;
126 case BCM6345_CPU_ID:
127 irq_stat_addr += PERF_IRQSTAT_6345_REG;
128 irq_mask_addr += PERF_IRQMASK_6345_REG;
129 irq_bits = 32;
130 break;
131 case BCM6348_CPU_ID:
132 irq_stat_addr += PERF_IRQSTAT_6348_REG;
133 irq_mask_addr += PERF_IRQMASK_6348_REG;
134 irq_bits = 32;
135 ext_irq_count = 4;
136 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348;
137 break;
138 case BCM6358_CPU_ID:
139 irq_stat_addr += PERF_IRQSTAT_6358_REG;
140 irq_mask_addr += PERF_IRQMASK_6358_REG;
141 irq_bits = 32;
142 ext_irq_count = 4;
143 is_ext_irq_cascaded = 1;
144 ext_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE;
145 ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;
146 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
147 break;
148 case BCM6368_CPU_ID:
149 irq_stat_addr += PERF_IRQSTAT_6368_REG;
150 irq_mask_addr += PERF_IRQMASK_6368_REG;
151 irq_bits = 64;
152 ext_irq_count = 6;
153 is_ext_irq_cascaded = 1;
154 ext_irq_start = BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE;
155 ext_irq_end = BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE;
156 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6368;
157 ext_irq_cfg_reg2 = PERF_EXTIRQ_CFG_REG2_6368;
158 break;
159 default:
160 BUG();
161 }
162
163 if (irq_bits == 32) {
164 dispatch_internal = __dispatch_internal;
165 internal_irq_mask = __internal_irq_mask_32;
166 internal_irq_unmask = __internal_irq_unmask_32;
167 } else {
168 dispatch_internal = __dispatch_internal_64;
169 internal_irq_mask = __internal_irq_mask_64;
170 internal_irq_unmask = __internal_irq_unmask_64;
171 }
172}
173#endif /* ! BCMCPU_RUNTIME_DETECT */
174
175static inline u32 get_ext_irq_perf_reg(int irq)
176{
177 if (irq < 4)
178 return ext_irq_cfg_reg1;
179 return ext_irq_cfg_reg2;
180}
181
182static inline void handle_internal(int intbit)
183{
184 if (is_ext_irq_cascaded &&
185 intbit >= ext_irq_start && intbit <= ext_irq_end)
186 do_IRQ(intbit - ext_irq_start + IRQ_EXTERNAL_BASE);
187 else
188 do_IRQ(intbit + IRQ_INTERNAL_BASE);
189}
190
22/* 191/*
23 * dispatch internal devices IRQ (uart, enet, watchdog, ...). do not 192 * dispatch internal devices IRQ (uart, enet, watchdog, ...). do not
24 * prioritize any interrupt relatively to another. the static counter 193 * prioritize any interrupt relatively to another. the static counter
25 * will resume the loop where it ended the last time we left this 194 * will resume the loop where it ended the last time we left this
26 * function. 195 * function.
27 */ 196 */
28static void bcm63xx_irq_dispatch_internal(void) 197static void __dispatch_internal(void)
29{ 198{
30 u32 pending; 199 u32 pending;
31 static int i; 200 static int i;
32 201
33 pending = bcm_perf_readl(PERF_IRQMASK_REG) & 202 pending = bcm_readl(irq_stat_addr) & bcm_readl(irq_mask_addr);
34 bcm_perf_readl(PERF_IRQSTAT_REG);
35 203
36 if (!pending) 204 if (!pending)
37 return ; 205 return ;
@@ -41,7 +209,28 @@ static void bcm63xx_irq_dispatch_internal(void)
41 209
42 i = (i + 1) & 0x1f; 210 i = (i + 1) & 0x1f;
43 if (pending & (1 << to_call)) { 211 if (pending & (1 << to_call)) {
44 do_IRQ(to_call + IRQ_INTERNAL_BASE); 212 handle_internal(to_call);
213 break;
214 }
215 }
216}
217
218static void __dispatch_internal_64(void)
219{
220 u64 pending;
221 static int i;
222
223 pending = bcm_readq(irq_stat_addr) & bcm_readq(irq_mask_addr);
224
225 if (!pending)
226 return ;
227
228 while (1) {
229 int to_call = i;
230
231 i = (i + 1) & 0x3f;
232 if (pending & (1ull << to_call)) {
233 handle_internal(to_call);
45 break; 234 break;
46 } 235 }
47 } 236 }
@@ -60,15 +249,17 @@ asmlinkage void plat_irq_dispatch(void)
60 if (cause & CAUSEF_IP7) 249 if (cause & CAUSEF_IP7)
61 do_IRQ(7); 250 do_IRQ(7);
62 if (cause & CAUSEF_IP2) 251 if (cause & CAUSEF_IP2)
63 bcm63xx_irq_dispatch_internal(); 252 dispatch_internal();
64 if (cause & CAUSEF_IP3) 253 if (!is_ext_irq_cascaded) {
65 do_IRQ(IRQ_EXT_0); 254 if (cause & CAUSEF_IP3)
66 if (cause & CAUSEF_IP4) 255 do_IRQ(IRQ_EXT_0);
67 do_IRQ(IRQ_EXT_1); 256 if (cause & CAUSEF_IP4)
68 if (cause & CAUSEF_IP5) 257 do_IRQ(IRQ_EXT_1);
69 do_IRQ(IRQ_EXT_2); 258 if (cause & CAUSEF_IP5)
70 if (cause & CAUSEF_IP6) 259 do_IRQ(IRQ_EXT_2);
71 do_IRQ(IRQ_EXT_3); 260 if (cause & CAUSEF_IP6)
261 do_IRQ(IRQ_EXT_3);
262 }
72 } while (1); 263 } while (1);
73} 264}
74 265
@@ -76,24 +267,50 @@ asmlinkage void plat_irq_dispatch(void)
76 * internal IRQs operations: only mask/unmask on PERF irq mask 267 * internal IRQs operations: only mask/unmask on PERF irq mask
77 * register. 268 * register.
78 */ 269 */
79static inline void bcm63xx_internal_irq_mask(struct irq_data *d) 270static void __internal_irq_mask_32(unsigned int irq)
80{ 271{
81 unsigned int irq = d->irq - IRQ_INTERNAL_BASE;
82 u32 mask; 272 u32 mask;
83 273
84 mask = bcm_perf_readl(PERF_IRQMASK_REG); 274 mask = bcm_readl(irq_mask_addr);
85 mask &= ~(1 << irq); 275 mask &= ~(1 << irq);
86 bcm_perf_writel(mask, PERF_IRQMASK_REG); 276 bcm_writel(mask, irq_mask_addr);
87} 277}
88 278
89static void bcm63xx_internal_irq_unmask(struct irq_data *d) 279static void __internal_irq_mask_64(unsigned int irq)
280{
281 u64 mask;
282
283 mask = bcm_readq(irq_mask_addr);
284 mask &= ~(1ull << irq);
285 bcm_writeq(mask, irq_mask_addr);
286}
287
288static void __internal_irq_unmask_32(unsigned int irq)
90{ 289{
91 unsigned int irq = d->irq - IRQ_INTERNAL_BASE;
92 u32 mask; 290 u32 mask;
93 291
94 mask = bcm_perf_readl(PERF_IRQMASK_REG); 292 mask = bcm_readl(irq_mask_addr);
95 mask |= (1 << irq); 293 mask |= (1 << irq);
96 bcm_perf_writel(mask, PERF_IRQMASK_REG); 294 bcm_writel(mask, irq_mask_addr);
295}
296
297static void __internal_irq_unmask_64(unsigned int irq)
298{
299 u64 mask;
300
301 mask = bcm_readq(irq_mask_addr);
302 mask |= (1ull << irq);
303 bcm_writeq(mask, irq_mask_addr);
304}
305
306static void bcm63xx_internal_irq_mask(struct irq_data *d)
307{
308 internal_irq_mask(d->irq - IRQ_INTERNAL_BASE);
309}
310
311static void bcm63xx_internal_irq_unmask(struct irq_data *d)
312{
313 internal_irq_unmask(d->irq - IRQ_INTERNAL_BASE);
97} 314}
98 315
99/* 316/*
@@ -102,94 +319,131 @@ static void bcm63xx_internal_irq_unmask(struct irq_data *d)
102 */ 319 */
103static void bcm63xx_external_irq_mask(struct irq_data *d) 320static void bcm63xx_external_irq_mask(struct irq_data *d)
104{ 321{
105 unsigned int irq = d->irq - IRQ_EXT_BASE; 322 unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
106 u32 reg; 323 u32 reg, regaddr;
107 324
108 reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG); 325 regaddr = get_ext_irq_perf_reg(irq);
109 reg &= ~EXTIRQ_CFG_MASK(irq); 326 reg = bcm_perf_readl(regaddr);
110 bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG); 327
328 if (BCMCPU_IS_6348())
329 reg &= ~EXTIRQ_CFG_MASK_6348(irq % 4);
330 else
331 reg &= ~EXTIRQ_CFG_MASK(irq % 4);
332
333 bcm_perf_writel(reg, regaddr);
334 if (is_ext_irq_cascaded)
335 internal_irq_mask(irq + ext_irq_start);
111} 336}
112 337
113static void bcm63xx_external_irq_unmask(struct irq_data *d) 338static void bcm63xx_external_irq_unmask(struct irq_data *d)
114{ 339{
115 unsigned int irq = d->irq - IRQ_EXT_BASE; 340 unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
116 u32 reg; 341 u32 reg, regaddr;
117 342
118 reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG); 343 regaddr = get_ext_irq_perf_reg(irq);
119 reg |= EXTIRQ_CFG_MASK(irq); 344 reg = bcm_perf_readl(regaddr);
120 bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG); 345
346 if (BCMCPU_IS_6348())
347 reg |= EXTIRQ_CFG_MASK_6348(irq % 4);
348 else
349 reg |= EXTIRQ_CFG_MASK(irq % 4);
350
351 bcm_perf_writel(reg, regaddr);
352
353 if (is_ext_irq_cascaded)
354 internal_irq_unmask(irq + ext_irq_start);
121} 355}
122 356
123static void bcm63xx_external_irq_clear(struct irq_data *d) 357static void bcm63xx_external_irq_clear(struct irq_data *d)
124{ 358{
125 unsigned int irq = d->irq - IRQ_EXT_BASE; 359 unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
126 u32 reg; 360 u32 reg, regaddr;
127 361
128 reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG); 362 regaddr = get_ext_irq_perf_reg(irq);
129 reg |= EXTIRQ_CFG_CLEAR(irq); 363 reg = bcm_perf_readl(regaddr);
130 bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
131}
132 364
133static unsigned int bcm63xx_external_irq_startup(struct irq_data *d) 365 if (BCMCPU_IS_6348())
134{ 366 reg |= EXTIRQ_CFG_CLEAR_6348(irq % 4);
135 set_c0_status(0x100 << (d->irq - IRQ_MIPS_BASE)); 367 else
136 irq_enable_hazard(); 368 reg |= EXTIRQ_CFG_CLEAR(irq % 4);
137 bcm63xx_external_irq_unmask(d);
138 return 0;
139}
140 369
141static void bcm63xx_external_irq_shutdown(struct irq_data *d) 370 bcm_perf_writel(reg, regaddr);
142{
143 bcm63xx_external_irq_mask(d);
144 clear_c0_status(0x100 << (d->irq - IRQ_MIPS_BASE));
145 irq_disable_hazard();
146} 371}
147 372
148static int bcm63xx_external_irq_set_type(struct irq_data *d, 373static int bcm63xx_external_irq_set_type(struct irq_data *d,
149 unsigned int flow_type) 374 unsigned int flow_type)
150{ 375{
151 unsigned int irq = d->irq - IRQ_EXT_BASE; 376 unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
152 u32 reg; 377 u32 reg, regaddr;
378 int levelsense, sense, bothedge;
153 379
154 flow_type &= IRQ_TYPE_SENSE_MASK; 380 flow_type &= IRQ_TYPE_SENSE_MASK;
155 381
156 if (flow_type == IRQ_TYPE_NONE) 382 if (flow_type == IRQ_TYPE_NONE)
157 flow_type = IRQ_TYPE_LEVEL_LOW; 383 flow_type = IRQ_TYPE_LEVEL_LOW;
158 384
159 reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG); 385 levelsense = sense = bothedge = 0;
160 switch (flow_type) { 386 switch (flow_type) {
161 case IRQ_TYPE_EDGE_BOTH: 387 case IRQ_TYPE_EDGE_BOTH:
162 reg &= ~EXTIRQ_CFG_LEVELSENSE(irq); 388 bothedge = 1;
163 reg |= EXTIRQ_CFG_BOTHEDGE(irq);
164 break; 389 break;
165 390
166 case IRQ_TYPE_EDGE_RISING: 391 case IRQ_TYPE_EDGE_RISING:
167 reg &= ~EXTIRQ_CFG_LEVELSENSE(irq); 392 sense = 1;
168 reg |= EXTIRQ_CFG_SENSE(irq);
169 reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
170 break; 393 break;
171 394
172 case IRQ_TYPE_EDGE_FALLING: 395 case IRQ_TYPE_EDGE_FALLING:
173 reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
174 reg &= ~EXTIRQ_CFG_SENSE(irq);
175 reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
176 break; 396 break;
177 397
178 case IRQ_TYPE_LEVEL_HIGH: 398 case IRQ_TYPE_LEVEL_HIGH:
179 reg |= EXTIRQ_CFG_LEVELSENSE(irq); 399 levelsense = 1;
180 reg |= EXTIRQ_CFG_SENSE(irq); 400 sense = 1;
181 break; 401 break;
182 402
183 case IRQ_TYPE_LEVEL_LOW: 403 case IRQ_TYPE_LEVEL_LOW:
184 reg |= EXTIRQ_CFG_LEVELSENSE(irq); 404 levelsense = 1;
185 reg &= ~EXTIRQ_CFG_SENSE(irq);
186 break; 405 break;
187 406
188 default: 407 default:
189 printk(KERN_ERR "bogus flow type combination given !\n"); 408 printk(KERN_ERR "bogus flow type combination given !\n");
190 return -EINVAL; 409 return -EINVAL;
191 } 410 }
192 bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG); 411
412 regaddr = get_ext_irq_perf_reg(irq);
413 reg = bcm_perf_readl(regaddr);
414 irq %= 4;
415
416 if (BCMCPU_IS_6348()) {
417 if (levelsense)
418 reg |= EXTIRQ_CFG_LEVELSENSE_6348(irq);
419 else
420 reg &= ~EXTIRQ_CFG_LEVELSENSE_6348(irq);
421 if (sense)
422 reg |= EXTIRQ_CFG_SENSE_6348(irq);
423 else
424 reg &= ~EXTIRQ_CFG_SENSE_6348(irq);
425 if (bothedge)
426 reg |= EXTIRQ_CFG_BOTHEDGE_6348(irq);
427 else
428 reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq);
429 }
430
431 if (BCMCPU_IS_6338() || BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
432 if (levelsense)
433 reg |= EXTIRQ_CFG_LEVELSENSE(irq);
434 else
435 reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
436 if (sense)
437 reg |= EXTIRQ_CFG_SENSE(irq);
438 else
439 reg &= ~EXTIRQ_CFG_SENSE(irq);
440 if (bothedge)
441 reg |= EXTIRQ_CFG_BOTHEDGE(irq);
442 else
443 reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
444 }
445
446 bcm_perf_writel(reg, regaddr);
193 447
194 irqd_set_trigger_type(d, flow_type); 448 irqd_set_trigger_type(d, flow_type);
195 if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) 449 if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
@@ -208,9 +462,6 @@ static struct irq_chip bcm63xx_internal_irq_chip = {
208 462
209static struct irq_chip bcm63xx_external_irq_chip = { 463static struct irq_chip bcm63xx_external_irq_chip = {
210 .name = "bcm63xx_epic", 464 .name = "bcm63xx_epic",
211 .irq_startup = bcm63xx_external_irq_startup,
212 .irq_shutdown = bcm63xx_external_irq_shutdown,
213
214 .irq_ack = bcm63xx_external_irq_clear, 465 .irq_ack = bcm63xx_external_irq_clear,
215 466
216 .irq_mask = bcm63xx_external_irq_mask, 467 .irq_mask = bcm63xx_external_irq_mask,
@@ -225,18 +476,30 @@ static struct irqaction cpu_ip2_cascade_action = {
225 .flags = IRQF_NO_THREAD, 476 .flags = IRQF_NO_THREAD,
226}; 477};
227 478
479static struct irqaction cpu_ext_cascade_action = {
480 .handler = no_action,
481 .name = "cascade_extirq",
482 .flags = IRQF_NO_THREAD,
483};
484
228void __init arch_init_irq(void) 485void __init arch_init_irq(void)
229{ 486{
230 int i; 487 int i;
231 488
489 bcm63xx_init_irq();
232 mips_cpu_irq_init(); 490 mips_cpu_irq_init();
233 for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i) 491 for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i)
234 irq_set_chip_and_handler(i, &bcm63xx_internal_irq_chip, 492 irq_set_chip_and_handler(i, &bcm63xx_internal_irq_chip,
235 handle_level_irq); 493 handle_level_irq);
236 494
237 for (i = IRQ_EXT_BASE; i < IRQ_EXT_BASE + 4; ++i) 495 for (i = IRQ_EXTERNAL_BASE; i < IRQ_EXTERNAL_BASE + ext_irq_count; ++i)
238 irq_set_chip_and_handler(i, &bcm63xx_external_irq_chip, 496 irq_set_chip_and_handler(i, &bcm63xx_external_irq_chip,
239 handle_edge_irq); 497 handle_edge_irq);
240 498
241 setup_irq(IRQ_MIPS_BASE + 2, &cpu_ip2_cascade_action); 499 if (!is_ext_irq_cascaded) {
500 for (i = 3; i < 3 + ext_irq_count; ++i)
501 setup_irq(MIPS_CPU_IRQ_BASE + i, &cpu_ext_cascade_action);
502 }
503
504 setup_irq(MIPS_CPU_IRQ_BASE + 2, &cpu_ip2_cascade_action);
242} 505}
diff --git a/arch/mips/bcm63xx/prom.c b/arch/mips/bcm63xx/prom.c
index be252efa0757..99d7f405cbeb 100644
--- a/arch/mips/bcm63xx/prom.c
+++ b/arch/mips/bcm63xx/prom.c
@@ -32,9 +32,12 @@ void __init prom_init(void)
32 mask = CKCTL_6345_ALL_SAFE_EN; 32 mask = CKCTL_6345_ALL_SAFE_EN;
33 else if (BCMCPU_IS_6348()) 33 else if (BCMCPU_IS_6348())
34 mask = CKCTL_6348_ALL_SAFE_EN; 34 mask = CKCTL_6348_ALL_SAFE_EN;
35 else 35 else if (BCMCPU_IS_6358())
36 /* BCMCPU_IS_6358() */
37 mask = CKCTL_6358_ALL_SAFE_EN; 36 mask = CKCTL_6358_ALL_SAFE_EN;
37 else if (BCMCPU_IS_6368())
38 mask = CKCTL_6368_ALL_SAFE_EN;
39 else
40 mask = 0;
38 41
39 reg = bcm_perf_readl(PERF_CKCTL_REG); 42 reg = bcm_perf_readl(PERF_CKCTL_REG);
40 reg &= ~mask; 43 reg &= ~mask;
diff --git a/arch/mips/bcm63xx/setup.c b/arch/mips/bcm63xx/setup.c
index d0056598fbfc..d209f85d87bb 100644
--- a/arch/mips/bcm63xx/setup.c
+++ b/arch/mips/bcm63xx/setup.c
@@ -63,13 +63,33 @@ static void bcm6348_a1_reboot(void)
63 63
64void bcm63xx_machine_reboot(void) 64void bcm63xx_machine_reboot(void)
65{ 65{
66 u32 reg; 66 u32 reg, perf_regs[2] = { 0, 0 };
67 unsigned int i;
67 68
68 /* mask and clear all external irq */ 69 /* mask and clear all external irq */
69 reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG); 70 switch (bcm63xx_get_cpu_id()) {
70 reg &= ~EXTIRQ_CFG_MASK_ALL; 71 case BCM6338_CPU_ID:
71 reg |= EXTIRQ_CFG_CLEAR_ALL; 72 perf_regs[0] = PERF_EXTIRQ_CFG_REG_6338;
72 bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG); 73 break;
74 case BCM6348_CPU_ID:
75 perf_regs[0] = PERF_EXTIRQ_CFG_REG_6348;
76 break;
77 case BCM6358_CPU_ID:
78 perf_regs[0] = PERF_EXTIRQ_CFG_REG_6358;
79 break;
80 }
81
82 for (i = 0; i < 2; i++) {
83 reg = bcm_perf_readl(perf_regs[i]);
84 if (BCMCPU_IS_6348()) {
85 reg &= ~EXTIRQ_CFG_MASK_ALL_6348;
86 reg |= EXTIRQ_CFG_CLEAR_ALL_6348;
87 } else {
88 reg &= ~EXTIRQ_CFG_MASK_ALL;
89 reg |= EXTIRQ_CFG_CLEAR_ALL;
90 }
91 bcm_perf_writel(reg, perf_regs[i]);
92 }
73 93
74 if (BCMCPU_IS_6348() && (bcm63xx_get_cpu_rev() == 0xa1)) 94 if (BCMCPU_IS_6348() && (bcm63xx_get_cpu_rev() == 0xa1))
75 bcm6348_a1_reboot(); 95 bcm6348_a1_reboot();
@@ -124,4 +144,4 @@ int __init bcm63xx_register_devices(void)
124 return board_register_devices(); 144 return board_register_devices();
125} 145}
126 146
127arch_initcall(bcm63xx_register_devices); 147device_initcall(bcm63xx_register_devices);
diff --git a/arch/mips/boot/compressed/uart-alchemy.c b/arch/mips/boot/compressed/uart-alchemy.c
index eb063e6dead9..3112df8f90db 100644
--- a/arch/mips/boot/compressed/uart-alchemy.c
+++ b/arch/mips/boot/compressed/uart-alchemy.c
@@ -2,6 +2,9 @@
2 2
3void putc(char c) 3void putc(char c)
4{ 4{
5 /* all current (Jan. 2010) in-kernel boards */ 5#ifdef CONFIG_MIPS_DB1300
6 alchemy_uart_putchar(AU1300_UART2_PHYS_ADDR, c);
7#else
6 alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c); 8 alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
9#endif
7} 10}
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index 2d9028f1474c..260b27367347 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -642,14 +642,6 @@ void __init plat_mem_setup(void)
642 642
643 total = 0; 643 total = 0;
644 644
645 /* First add the init memory we will be returning. */
646 memory = __pa_symbol(&__init_begin) & PAGE_MASK;
647 mem_alloc_size = (__pa_symbol(&__init_end) & PAGE_MASK) - memory;
648 if (mem_alloc_size > 0) {
649 add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM);
650 total += mem_alloc_size;
651 }
652
653 /* 645 /*
654 * The Mips memory init uses the first memory location for 646 * The Mips memory init uses the first memory location for
655 * some memory vectors. When SPARSEMEM is in use, it doesn't 647 * some memory vectors. When SPARSEMEM is in use, it doesn't
@@ -767,11 +759,11 @@ void prom_free_prom_memory(void)
767 : "=r" (insn) : : "$31", "memory"); 759 : "=r" (insn) : : "$31", "memory");
768 760
769 if ((insn >> 26) != 0x33) 761 if ((insn >> 26) != 0x33)
770 panic("No PREF instruction at Core-14449 probe point.\n"); 762 panic("No PREF instruction at Core-14449 probe point.");
771 763
772 if (((insn >> 16) & 0x1f) != 28) 764 if (((insn >> 16) & 0x1f) != 28)
773 panic("Core-14449 WAR not in place (%04x).\n" 765 panic("Core-14449 WAR not in place (%04x).\n"
774 "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).\n", insn); 766 "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).", insn);
775 } 767 }
776#ifdef CONFIG_CAVIUM_DECODE_RSL 768#ifdef CONFIG_CAVIUM_DECODE_RSL
777 cvmx_interrupt_rsl_enable(); 769 cvmx_interrupt_rsl_enable();
@@ -779,7 +771,7 @@ void prom_free_prom_memory(void)
779 /* Add an interrupt handler for general failures. */ 771 /* Add an interrupt handler for general failures. */
780 if (request_irq(OCTEON_IRQ_RML, octeon_rlm_interrupt, IRQF_SHARED, 772 if (request_irq(OCTEON_IRQ_RML, octeon_rlm_interrupt, IRQF_SHARED,
781 "RML/RSL", octeon_rlm_interrupt)) { 773 "RML/RSL", octeon_rlm_interrupt)) {
782 panic("Unable to request_irq(OCTEON_IRQ_RML)\n"); 774 panic("Unable to request_irq(OCTEON_IRQ_RML)");
783 } 775 }
784#endif 776#endif
785} 777}
diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c
index efcfff4d4627..b1535fe409d4 100644
--- a/arch/mips/cavium-octeon/smp.c
+++ b/arch/mips/cavium-octeon/smp.c
@@ -210,7 +210,7 @@ void octeon_prepare_cpus(unsigned int max_cpus)
210 if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, 210 if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt,
211 IRQF_PERCPU | IRQF_NO_THREAD, "SMP-IPI", 211 IRQF_PERCPU | IRQF_NO_THREAD, "SMP-IPI",
212 mailbox_interrupt)) { 212 mailbox_interrupt)) {
213 panic("Cannot request_irq(OCTEON_IRQ_MBOX0)\n"); 213 panic("Cannot request_irq(OCTEON_IRQ_MBOX0)");
214 } 214 }
215} 215}
216 216
diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig
index 4044c9e0fb73..17a36c125172 100644
--- a/arch/mips/configs/db1000_defconfig
+++ b/arch/mips/configs/db1000_defconfig
@@ -1,118 +1,359 @@
1CONFIG_MIPS=y
1CONFIG_MIPS_ALCHEMY=y 2CONFIG_MIPS_ALCHEMY=y
3CONFIG_MIPS_DB1000=y
4CONFIG_SCHED_OMIT_FRAME_POINTER=y
5CONFIG_TICK_ONESHOT=y
2CONFIG_NO_HZ=y 6CONFIG_NO_HZ=y
3CONFIG_HIGH_RES_TIMERS=y 7CONFIG_HIGH_RES_TIMERS=y
4CONFIG_HZ_100=y 8CONFIG_HZ_100=y
5# CONFIG_SECCOMP is not set 9CONFIG_HZ=100
10CONFIG_PREEMPT_NONE=y
6CONFIG_EXPERIMENTAL=y 11CONFIG_EXPERIMENTAL=y
7CONFIG_LOCALVERSION="-db1000" 12CONFIG_BROKEN_ON_SMP=y
13CONFIG_INIT_ENV_ARG_LIMIT=32
14CONFIG_CROSS_COMPILE=""
15CONFIG_LOCALVERSION="-db1x00"
16CONFIG_LOCALVERSION_AUTO=y
8CONFIG_KERNEL_LZMA=y 17CONFIG_KERNEL_LZMA=y
18CONFIG_DEFAULT_HOSTNAME="db1x00"
19CONFIG_SWAP=y
9CONFIG_SYSVIPC=y 20CONFIG_SYSVIPC=y
10CONFIG_POSIX_MQUEUE=y 21CONFIG_SYSVIPC_SYSCTL=y
22CONFIG_FHANDLE=y
23CONFIG_AUDIT=y
11CONFIG_TINY_RCU=y 24CONFIG_TINY_RCU=y
12CONFIG_LOG_BUF_SHIFT=14 25CONFIG_LOG_BUF_SHIFT=18
13# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 26CONFIG_NAMESPACES=y
27CONFIG_UTS_NS=y
28CONFIG_IPC_NS=y
29CONFIG_USER_NS=y
30CONFIG_PID_NS=y
31CONFIG_NET_NS=y
32CONFIG_SYSCTL=y
14CONFIG_EXPERT=y 33CONFIG_EXPERT=y
15# CONFIG_KALLSYMS is not set 34CONFIG_KALLSYMS=y
16# CONFIG_PCSPKR_PLATFORM is not set 35CONFIG_KALLSYMS_ALL=y
17# CONFIG_VM_EVENT_COUNTERS is not set 36CONFIG_HOTPLUG=y
18# CONFIG_COMPAT_BRK is not set 37CONFIG_PRINTK=y
38CONFIG_BUG=y
39CONFIG_ELF_CORE=y
40CONFIG_BASE_FULL=y
41CONFIG_FUTEX=y
42CONFIG_EPOLL=y
43CONFIG_SIGNALFD=y
44CONFIG_TIMERFD=y
45CONFIG_EVENTFD=y
46CONFIG_SHMEM=y
47CONFIG_AIO=y
48CONFIG_EMBEDDED=y
49CONFIG_HAVE_PERF_EVENTS=y
50CONFIG_PERF_USE_VMALLOC=y
51CONFIG_PCI_QUIRKS=y
19CONFIG_SLAB=y 52CONFIG_SLAB=y
20CONFIG_MODULES=y 53CONFIG_SLABINFO=y
21CONFIG_MODULE_UNLOAD=y 54CONFIG_BLOCK=y
22# CONFIG_LBDAF is not set 55CONFIG_LBDAF=y
23# CONFIG_BLK_DEV_BSG is not set 56CONFIG_BLK_DEV_BSG=y
24# CONFIG_IOSCHED_DEADLINE is not set 57CONFIG_BLK_DEV_BSGLIB=y
25# CONFIG_IOSCHED_CFQ is not set 58CONFIG_IOSCHED_NOOP=y
59CONFIG_DEFAULT_NOOP=y
60CONFIG_DEFAULT_IOSCHED="noop"
61CONFIG_FREEZER=y
62CONFIG_PCI=y
63CONFIG_PCI_DOMAINS=y
26CONFIG_PCCARD=y 64CONFIG_PCCARD=y
65CONFIG_PCMCIA=y
66CONFIG_PCMCIA_LOAD_CIS=y
27CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y 67CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y
28CONFIG_PM=y 68CONFIG_BINFMT_ELF=y
69CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
70CONFIG_SUSPEND=y
71CONFIG_SUSPEND_FREEZER=y
72CONFIG_PM_SLEEP=y
29CONFIG_PM_RUNTIME=y 73CONFIG_PM_RUNTIME=y
74CONFIG_PM=y
30CONFIG_NET=y 75CONFIG_NET=y
31CONFIG_PACKET=y 76CONFIG_PACKET=y
32CONFIG_UNIX=y 77CONFIG_UNIX=y
78CONFIG_XFRM=y
33CONFIG_INET=y 79CONFIG_INET=y
34CONFIG_IP_MULTICAST=y 80CONFIG_IP_MULTICAST=y
35CONFIG_IP_PNP=y 81CONFIG_IP_PNP=y
36CONFIG_IP_PNP_DHCP=y 82CONFIG_IP_PNP_DHCP=y
37CONFIG_IP_PNP_BOOTP=y 83CONFIG_IP_PNP_BOOTP=y
38CONFIG_IP_PNP_RARP=y 84CONFIG_IP_PNP_RARP=y
39# CONFIG_INET_XFRM_MODE_TRANSPORT is not set 85CONFIG_NET_IPIP=y
40# CONFIG_INET_XFRM_MODE_TUNNEL is not set 86CONFIG_INET_TUNNEL=y
41# CONFIG_INET_XFRM_MODE_BEET is not set 87CONFIG_INET_LRO=y
42# CONFIG_INET_DIAG is not set 88CONFIG_TCP_CONG_CUBIC=y
43# CONFIG_IPV6 is not set 89CONFIG_DEFAULT_TCP_CONG="cubic"
44# CONFIG_WIRELESS is not set 90CONFIG_IPV6=y
45CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 91CONFIG_INET6_XFRM_MODE_TRANSPORT=y
92CONFIG_INET6_XFRM_MODE_TUNNEL=y
93CONFIG_INET6_XFRM_MODE_BEET=y
94CONFIG_IPV6_SIT=y
95CONFIG_IPV6_NDISC_NODETYPE=y
96CONFIG_STP=y
97CONFIG_GARP=y
98CONFIG_BRIDGE=y
99CONFIG_BRIDGE_IGMP_SNOOPING=y
100CONFIG_VLAN_8021Q=y
101CONFIG_VLAN_8021Q_GVRP=y
102CONFIG_LLC=y
103CONFIG_LLC2=y
104CONFIG_DNS_RESOLVER=y
105CONFIG_BT=y
106CONFIG_BT_L2CAP=y
107CONFIG_BT_SCO=y
108CONFIG_BT_RFCOMM=y
109CONFIG_BT_RFCOMM_TTY=y
110CONFIG_BT_BNEP=y
111CONFIG_BT_BNEP_MC_FILTER=y
112CONFIG_BT_BNEP_PROTO_FILTER=y
113CONFIG_BT_HIDP=y
114CONFIG_BT_HCIBTUSB=y
115CONFIG_UEVENT_HELPER_PATH=""
116CONFIG_STANDALONE=y
117CONFIG_PREVENT_FIRMWARE_BUILD=y
118CONFIG_FW_LOADER=y
46CONFIG_MTD=y 119CONFIG_MTD=y
47CONFIG_MTD_PARTITIONS=y
48CONFIG_MTD_CMDLINE_PARTS=y 120CONFIG_MTD_CMDLINE_PARTS=y
49CONFIG_MTD_CHAR=y 121CONFIG_MTD_CHAR=y
122CONFIG_MTD_BLKDEVS=y
50CONFIG_MTD_BLOCK=y 123CONFIG_MTD_BLOCK=y
51CONFIG_MTD_CFI=y 124CONFIG_MTD_CFI=y
125CONFIG_MTD_GEN_PROBE=y
126CONFIG_MTD_CFI_ADV_OPTIONS=y
127CONFIG_MTD_CFI_NOSWAP=y
128CONFIG_MTD_CFI_GEOMETRY=y
129CONFIG_MTD_MAP_BANK_WIDTH_1=y
130CONFIG_MTD_MAP_BANK_WIDTH_2=y
131CONFIG_MTD_MAP_BANK_WIDTH_4=y
132CONFIG_MTD_CFI_I1=y
133CONFIG_MTD_CFI_I2=y
134CONFIG_MTD_CFI_I4=y
135CONFIG_MTD_CFI_I8=y
136CONFIG_MTD_CFI_INTELEXT=y
52CONFIG_MTD_CFI_AMDSTD=y 137CONFIG_MTD_CFI_AMDSTD=y
138CONFIG_MTD_CFI_UTIL=y
53CONFIG_MTD_PHYSMAP=y 139CONFIG_MTD_PHYSMAP=y
54# CONFIG_MISC_DEVICES is not set 140CONFIG_SCSI_MOD=y
141CONFIG_SCSI=y
142CONFIG_SCSI_DMA=y
143CONFIG_SCSI_PROC_FS=y
144CONFIG_BLK_DEV_SD=y
145CONFIG_CHR_DEV_SG=y
146CONFIG_SCSI_MULTI_LUN=y
147CONFIG_SCSI_CONSTANTS=y
148CONFIG_ATA=y
149CONFIG_ATA_VERBOSE_ERROR=y
150CONFIG_ATA_SFF=y
151CONFIG_ATA_BMDMA=y
152CONFIG_PATA_HPT37X=y
153CONFIG_PATA_PCMCIA=y
154CONFIG_MD=y
155CONFIG_BLK_DEV_DM=y
156CONFIG_FIREWIRE=y
157CONFIG_FIREWIRE_OHCI=y
158CONFIG_FIREWIRE_OHCI_DEBUG=y
159CONFIG_FIREWIRE_NET=y
55CONFIG_NETDEVICES=y 160CONFIG_NETDEVICES=y
56CONFIG_MARVELL_PHY=y
57CONFIG_DAVICOM_PHY=y
58CONFIG_QSEMI_PHY=y
59CONFIG_LXT_PHY=y
60CONFIG_CICADA_PHY=y
61CONFIG_VITESSE_PHY=y
62CONFIG_SMSC_PHY=y
63CONFIG_BROADCOM_PHY=y
64CONFIG_ICPLUS_PHY=y
65CONFIG_REALTEK_PHY=y
66CONFIG_NATIONAL_PHY=y
67CONFIG_STE10XP=y
68CONFIG_LSI_ET1011C_PHY=y
69CONFIG_NET_ETHERNET=y
70CONFIG_MII=y 161CONFIG_MII=y
162CONFIG_PHYLIB=y
163CONFIG_NET_ETHERNET=y
71CONFIG_MIPS_AU1X00_ENET=y 164CONFIG_MIPS_AU1X00_ENET=y
72# CONFIG_NETDEV_1000 is not set 165CONFIG_NET_PCMCIA=y
73# CONFIG_NETDEV_10000 is not set 166CONFIG_PCMCIA_3C589=y
74# CONFIG_WLAN is not set 167CONFIG_PCMCIA_PCNET=y
75# CONFIG_INPUT_MOUSEDEV is not set 168CONFIG_PPP=y
169CONFIG_PPP_MULTILINK=y
170CONFIG_PPP_FILTER=y
171CONFIG_PPP_ASYNC=y
172CONFIG_PPP_SYNC_TTY=y
173CONFIG_PPP_DEFLATE=y
174CONFIG_PPP_BSDCOMP=y
175CONFIG_PPP_MPPE=y
176CONFIG_PPPOE=y
177CONFIG_INPUT=y
76CONFIG_INPUT_EVDEV=y 178CONFIG_INPUT_EVDEV=y
77# CONFIG_INPUT_KEYBOARD is not set 179CONFIG_INPUT_MISC=y
78# CONFIG_INPUT_MOUSE is not set 180CONFIG_INPUT_UINPUT=y
79# CONFIG_SERIO is not set 181CONFIG_VT=y
182CONFIG_CONSOLE_TRANSLATIONS=y
183CONFIG_VT_CONSOLE=y
184CONFIG_HW_CONSOLE=y
185CONFIG_UNIX98_PTYS=y
186CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
187CONFIG_DEVKMEM=y
80CONFIG_SERIAL_8250=y 188CONFIG_SERIAL_8250=y
81CONFIG_SERIAL_8250_CONSOLE=y 189CONFIG_SERIAL_8250_CONSOLE=y
82# CONFIG_LEGACY_PTYS is not set 190CONFIG_SERIAL_8250_NR_UARTS=4
83# CONFIG_HW_RANDOM is not set 191CONFIG_SERIAL_8250_RUNTIME_UARTS=4
84# CONFIG_HWMON is not set 192CONFIG_SERIAL_CORE=y
85# CONFIG_VGA_CONSOLE is not set 193CONFIG_SERIAL_CORE_CONSOLE=y
194CONFIG_TTY_PRINTK=y
195CONFIG_DEVPORT=y
196CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
197CONFIG_FB=y
198CONFIG_FB_CFB_FILLRECT=y
199CONFIG_FB_CFB_COPYAREA=y
200CONFIG_FB_CFB_IMAGEBLIT=y
201CONFIG_FB_AU1100=y
202CONFIG_DUMMY_CONSOLE=y
203CONFIG_FRAMEBUFFER_CONSOLE=y
204CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
205CONFIG_FONTS=y
206CONFIG_FONT_8x16=y
207CONFIG_SOUND=y
208CONFIG_SND=y
209CONFIG_SND_TIMER=y
210CONFIG_SND_PCM=y
211CONFIG_SND_JACK=y
212CONFIG_SND_SEQUENCER=y
213CONFIG_SND_HRTIMER=y
214CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
215CONFIG_SND_DYNAMIC_MINORS=y
216CONFIG_SND_VMASTER=y
217CONFIG_SND_AC97_CODEC=y
218CONFIG_SND_SOC=y
219CONFIG_SND_SOC_AC97_BUS=y
220CONFIG_SND_SOC_AU1XAUDIO=y
221CONFIG_SND_SOC_AU1XAC97C=y
222CONFIG_SND_SOC_DB1000=y
223CONFIG_SND_SOC_AC97_CODEC=y
224CONFIG_AC97_BUS=y
225CONFIG_HID_SUPPORT=y
226CONFIG_HID=y
227CONFIG_HIDRAW=y
228CONFIG_USB_HID=y
229CONFIG_USB_SUPPORT=y
86CONFIG_USB=y 230CONFIG_USB=y
87# CONFIG_USB_DEVICE_CLASS is not set
88CONFIG_USB_DYNAMIC_MINORS=y
89CONFIG_USB_SUSPEND=y 231CONFIG_USB_SUSPEND=y
232CONFIG_USB_EHCI_HCD=y
233CONFIG_USB_EHCI_ROOT_HUB_TT=y
234CONFIG_USB_EHCI_TT_NEWSCHED=y
90CONFIG_USB_OHCI_HCD=y 235CONFIG_USB_OHCI_HCD=y
236CONFIG_USB_UHCI_HCD=y
237CONFIG_USB_STORAGE=y
238CONFIG_NEW_LEDS=y
239CONFIG_LEDS_CLASS=y
240CONFIG_LEDS_TRIGGERS=y
241CONFIG_RTC_LIB=y
91CONFIG_RTC_CLASS=y 242CONFIG_RTC_CLASS=y
243CONFIG_RTC_HCTOSYS=y
244CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
245CONFIG_RTC_INTF_SYSFS=y
246CONFIG_RTC_INTF_PROC=y
247CONFIG_RTC_INTF_DEV=y
92CONFIG_RTC_DRV_AU1XXX=y 248CONFIG_RTC_DRV_AU1XXX=y
93CONFIG_EXT2_FS=y 249CONFIG_EXT4_FS=y
94CONFIG_EXT3_FS=y 250CONFIG_EXT4_USE_FOR_EXT23=y
95# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set 251CONFIG_EXT4_FS_XATTR=y
96# CONFIG_EXT3_FS_XATTR is not set 252CONFIG_EXT4_FS_POSIX_ACL=y
97# CONFIG_PROC_PAGE_MONITOR is not set 253CONFIG_EXT4_FS_SECURITY=y
254CONFIG_JBD2=y
255CONFIG_FS_MBCACHE=y
256CONFIG_FS_POSIX_ACL=y
257CONFIG_EXPORTFS=y
258CONFIG_FILE_LOCKING=y
259CONFIG_FSNOTIFY=y
260CONFIG_DNOTIFY=y
261CONFIG_INOTIFY_USER=y
262CONFIG_GENERIC_ACL=y
263CONFIG_PROC_FS=y
264CONFIG_PROC_KCORE=y
265CONFIG_PROC_SYSCTL=y
266CONFIG_SYSFS=y
98CONFIG_TMPFS=y 267CONFIG_TMPFS=y
99CONFIG_CRAMFS=y 268CONFIG_TMPFS_POSIX_ACL=y
269CONFIG_TMPFS_XATTR=y
270CONFIG_MISC_FILESYSTEMS=y
271CONFIG_JFFS2_FS=y
272CONFIG_JFFS2_FS_DEBUG=0
273CONFIG_JFFS2_FS_WRITEBUFFER=y
274CONFIG_JFFS2_SUMMARY=y
275CONFIG_JFFS2_FS_XATTR=y
276CONFIG_JFFS2_FS_POSIX_ACL=y
277CONFIG_JFFS2_FS_SECURITY=y
278CONFIG_JFFS2_COMPRESSION_OPTIONS=y
279CONFIG_JFFS2_ZLIB=y
280CONFIG_JFFS2_LZO=y
281CONFIG_JFFS2_RTIME=y
282CONFIG_JFFS2_RUBIN=y
283CONFIG_JFFS2_CMODE_PRIORITY=y
100CONFIG_SQUASHFS=y 284CONFIG_SQUASHFS=y
285CONFIG_SQUASHFS_ZLIB=y
286CONFIG_SQUASHFS_LZO=y
287CONFIG_SQUASHFS_XZ=y
288CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
289CONFIG_NETWORK_FILESYSTEMS=y
101CONFIG_NFS_FS=y 290CONFIG_NFS_FS=y
102CONFIG_NFS_V3=y 291CONFIG_NFS_V3=y
292CONFIG_NFS_V4=y
293CONFIG_NFS_V4_1=y
294CONFIG_PNFS_FILE_LAYOUT=y
295CONFIG_PNFS_BLOCK=y
103CONFIG_ROOT_NFS=y 296CONFIG_ROOT_NFS=y
297CONFIG_NFS_USE_KERNEL_DNS=y
298CONFIG_NFS_USE_NEW_IDMAPPER=y
299CONFIG_NFSD=y
300CONFIG_NFSD_V2_ACL=y
301CONFIG_NFSD_V3=y
302CONFIG_NFSD_V3_ACL=y
303CONFIG_NFSD_V4=y
304CONFIG_LOCKD=y
305CONFIG_LOCKD_V4=y
306CONFIG_NFS_ACL_SUPPORT=y
307CONFIG_NFS_COMMON=y
308CONFIG_SUNRPC=y
309CONFIG_SUNRPC_GSS=y
310CONFIG_SUNRPC_BACKCHANNEL=y
311CONFIG_MSDOS_PARTITION=y
312CONFIG_NLS=y
313CONFIG_NLS_DEFAULT="iso8859-1"
104CONFIG_NLS_CODEPAGE_437=y 314CONFIG_NLS_CODEPAGE_437=y
105CONFIG_NLS_CODEPAGE_850=y 315CONFIG_NLS_CODEPAGE_850=y
106CONFIG_NLS_CODEPAGE_1250=y 316CONFIG_NLS_CODEPAGE_1250=y
317CONFIG_NLS_ASCII=y
107CONFIG_NLS_ISO8859_1=y 318CONFIG_NLS_ISO8859_1=y
108CONFIG_NLS_ISO8859_15=y 319CONFIG_NLS_ISO8859_15=y
109CONFIG_NLS_UTF8=y 320CONFIG_NLS_UTF8=y
110# CONFIG_ENABLE_WARN_DEPRECATED is not set 321CONFIG_HAVE_ARCH_KGDB=y
111# CONFIG_ENABLE_MUST_CHECK is not set 322CONFIG_EARLY_PRINTK=y
112CONFIG_STRIP_ASM_SYMS=y 323CONFIG_CMDLINE_BOOL=y
113CONFIG_DEBUG_KERNEL=y 324CONFIG_CMDLINE="noirqdebug rootwait root=/dev/sda1 rootfstype=ext4 console=ttyS0,115200 video=au1100fb:panel:CRT_800x600_16"
114# CONFIG_SCHED_DEBUG is not set
115# CONFIG_FTRACE is not set
116CONFIG_DEBUG_ZBOOT=y 325CONFIG_DEBUG_ZBOOT=y
117CONFIG_KEYS=y 326CONFIG_KEYS=y
118CONFIG_KEYS_DEBUG_PROC_KEYS=y 327CONFIG_KEYS_DEBUG_PROC_KEYS=y
328CONFIG_SECURITYFS=y
329CONFIG_DEFAULT_SECURITY_DAC=y
330CONFIG_DEFAULT_SECURITY=""
331CONFIG_CRYPTO=y
332CONFIG_CRYPTO_ALGAPI=y
333CONFIG_CRYPTO_ALGAPI2=y
334CONFIG_CRYPTO_AEAD2=y
335CONFIG_CRYPTO_BLKCIPHER=y
336CONFIG_CRYPTO_BLKCIPHER2=y
337CONFIG_CRYPTO_HASH=y
338CONFIG_CRYPTO_HASH2=y
339CONFIG_CRYPTO_RNG=y
340CONFIG_CRYPTO_RNG2=y
341CONFIG_CRYPTO_PCOMP2=y
342CONFIG_CRYPTO_MANAGER=y
343CONFIG_CRYPTO_MANAGER2=y
344CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
345CONFIG_CRYPTO_WORKQUEUE=y
346CONFIG_CRYPTO_ECB=y
347CONFIG_CRYPTO_SHA1=y
348CONFIG_CRYPTO_AES=y
349CONFIG_CRYPTO_ANSI_CPRNG=y
350CONFIG_BITREVERSE=y
351CONFIG_CRC_CCITT=y
352CONFIG_CRC16=y
353CONFIG_CRC_ITU_T=y
354CONFIG_CRC32=y
355CONFIG_ZLIB_INFLATE=y
356CONFIG_ZLIB_DEFLATE=y
357CONFIG_LZO_COMPRESS=y
358CONFIG_LZO_DECOMPRESS=y
359CONFIG_XZ_DEC=y
diff --git a/arch/mips/configs/db1100_defconfig b/arch/mips/configs/db1100_defconfig
deleted file mode 100644
index c6b49938ee84..000000000000
--- a/arch/mips/configs/db1100_defconfig
+++ /dev/null
@@ -1,122 +0,0 @@
1CONFIG_MIPS_ALCHEMY=y
2CONFIG_MIPS_DB1100=y
3CONFIG_NO_HZ=y
4CONFIG_HIGH_RES_TIMERS=y
5CONFIG_HZ_100=y
6# CONFIG_SECCOMP is not set
7CONFIG_EXPERIMENTAL=y
8CONFIG_LOCALVERSION="-db1100"
9CONFIG_KERNEL_LZMA=y
10CONFIG_SYSVIPC=y
11CONFIG_POSIX_MQUEUE=y
12CONFIG_TINY_RCU=y
13CONFIG_LOG_BUF_SHIFT=14
14CONFIG_EXPERT=y
15# CONFIG_SYSCTL_SYSCALL is not set
16# CONFIG_KALLSYMS is not set
17# CONFIG_PCSPKR_PLATFORM is not set
18# CONFIG_COMPAT_BRK is not set
19CONFIG_SLAB=y
20CONFIG_MODULES=y
21CONFIG_MODULE_UNLOAD=y
22# CONFIG_LBDAF is not set
23# CONFIG_BLK_DEV_BSG is not set
24# CONFIG_IOSCHED_DEADLINE is not set
25# CONFIG_IOSCHED_CFQ is not set
26CONFIG_PCCARD=y
27CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y
28CONFIG_PM=y
29CONFIG_PM_RUNTIME=y
30CONFIG_NET=y
31CONFIG_PACKET=y
32CONFIG_UNIX=y
33CONFIG_INET=y
34CONFIG_IP_MULTICAST=y
35CONFIG_IP_PNP=y
36CONFIG_IP_PNP_DHCP=y
37CONFIG_IP_PNP_BOOTP=y
38CONFIG_IP_PNP_RARP=y
39# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
40# CONFIG_INET_XFRM_MODE_TUNNEL is not set
41# CONFIG_INET_XFRM_MODE_BEET is not set
42# CONFIG_INET_DIAG is not set
43# CONFIG_IPV6 is not set
44# CONFIG_WIRELESS is not set
45CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
46CONFIG_MTD=y
47CONFIG_MTD_PARTITIONS=y
48CONFIG_MTD_CHAR=y
49CONFIG_MTD_BLOCK=y
50CONFIG_MTD_CFI=y
51CONFIG_MTD_CFI_AMDSTD=y
52CONFIG_MTD_PHYSMAP=y
53# CONFIG_BLK_DEV is not set
54# CONFIG_MISC_DEVICES is not set
55CONFIG_IDE=y
56CONFIG_IDE_TASK_IOCTL=y
57CONFIG_NETDEVICES=y
58CONFIG_MARVELL_PHY=y
59CONFIG_DAVICOM_PHY=y
60CONFIG_QSEMI_PHY=y
61CONFIG_LXT_PHY=y
62CONFIG_CICADA_PHY=y
63CONFIG_VITESSE_PHY=y
64CONFIG_SMSC_PHY=y
65CONFIG_BROADCOM_PHY=y
66CONFIG_ICPLUS_PHY=y
67CONFIG_REALTEK_PHY=y
68CONFIG_NATIONAL_PHY=y
69CONFIG_STE10XP=y
70CONFIG_LSI_ET1011C_PHY=y
71CONFIG_NET_ETHERNET=y
72CONFIG_MII=y
73CONFIG_MIPS_AU1X00_ENET=y
74# CONFIG_NETDEV_1000 is not set
75# CONFIG_NETDEV_10000 is not set
76# CONFIG_WLAN is not set
77# CONFIG_INPUT_MOUSEDEV is not set
78CONFIG_INPUT_EVDEV=y
79# CONFIG_INPUT_KEYBOARD is not set
80# CONFIG_INPUT_MOUSE is not set
81# CONFIG_SERIO is not set
82CONFIG_VT_HW_CONSOLE_BINDING=y
83CONFIG_SERIAL_8250=y
84CONFIG_SERIAL_8250_CONSOLE=y
85# CONFIG_LEGACY_PTYS is not set
86# CONFIG_HW_RANDOM is not set
87# CONFIG_HWMON is not set
88CONFIG_FB=y
89CONFIG_FB_AU1100=y
90# CONFIG_VGA_CONSOLE is not set
91CONFIG_FRAMEBUFFER_CONSOLE=y
92CONFIG_FONTS=y
93CONFIG_FONT_8x16=y
94# CONFIG_HID_SUPPORT is not set
95CONFIG_USB=y
96# CONFIG_USB_DEVICE_CLASS is not set
97CONFIG_USB_DYNAMIC_MINORS=y
98CONFIG_USB_SUSPEND=y
99CONFIG_USB_OHCI_HCD=y
100CONFIG_RTC_CLASS=y
101CONFIG_RTC_DRV_AU1XXX=y
102CONFIG_EXT2_FS=y
103# CONFIG_PROC_PAGE_MONITOR is not set
104CONFIG_TMPFS=y
105CONFIG_JFFS2_FS=y
106CONFIG_JFFS2_SUMMARY=y
107CONFIG_JFFS2_FS_XATTR=y
108CONFIG_JFFS2_COMPRESSION_OPTIONS=y
109CONFIG_JFFS2_LZO=y
110CONFIG_JFFS2_RUBIN=y
111CONFIG_SQUASHFS=y
112CONFIG_NFS_FS=y
113CONFIG_NFS_V3=y
114CONFIG_ROOT_NFS=y
115CONFIG_STRIP_ASM_SYMS=y
116CONFIG_DEBUG_KERNEL=y
117# CONFIG_SCHED_DEBUG is not set
118# CONFIG_FTRACE is not set
119CONFIG_DEBUG_ZBOOT=y
120CONFIG_KEYS=y
121CONFIG_KEYS_DEBUG_PROC_KEYS=y
122CONFIG_SECURITYFS=y
diff --git a/arch/mips/configs/db1300_defconfig b/arch/mips/configs/db1300_defconfig
new file mode 100644
index 000000000000..c38b190151c4
--- /dev/null
+++ b/arch/mips/configs/db1300_defconfig
@@ -0,0 +1,391 @@
1CONFIG_MIPS=y
2CONFIG_MIPS_ALCHEMY=y
3CONFIG_ALCHEMY_GPIOINT_AU1300=y
4CONFIG_MIPS_DB1300=y
5CONFIG_SOC_AU1300=y
6CONFIG_RWSEM_GENERIC_SPINLOCK=y
7CONFIG_ARCH_SUPPORTS_OPROFILE=y
8CONFIG_GENERIC_HWEIGHT=y
9CONFIG_GENERIC_CALIBRATE_DELAY=y
10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_GENERIC_CMOS_UPDATE=y
12CONFIG_SCHED_OMIT_FRAME_POINTER=y
13CONFIG_CEVT_R4K_LIB=y
14CONFIG_CSRC_R4K_LIB=y
15CONFIG_DMA_COHERENT=y
16CONFIG_SYS_HAS_EARLY_PRINTK=y
17CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y
18CONFIG_GENERIC_GPIO=y
19CONFIG_CPU_LITTLE_ENDIAN=y
20CONFIG_SYS_SUPPORTS_APM_EMULATION=y
21CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
22CONFIG_IRQ_CPU=y
23CONFIG_MIPS_L1_CACHE_SHIFT=5
24CONFIG_CPU_MIPS32_R1=y
25CONFIG_SYS_SUPPORTS_ZBOOT=y
26CONFIG_SYS_HAS_CPU_MIPS32_R1=y
27CONFIG_CPU_MIPS32=y
28CONFIG_CPU_MIPSR1=y
29CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
30CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
31CONFIG_HARDWARE_WATCHPOINTS=y
32CONFIG_32BIT=y
33CONFIG_PAGE_SIZE_4KB=y
34CONFIG_FORCE_MAX_ZONEORDER=11
35CONFIG_CPU_HAS_PREFETCH=y
36CONFIG_MIPS_MT_DISABLED=y
37CONFIG_64BIT_PHYS_ADDR=y
38CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
39CONFIG_CPU_HAS_SYNC=y
40CONFIG_CPU_SUPPORTS_HIGHMEM=y
41CONFIG_ARCH_FLATMEM_ENABLE=y
42CONFIG_ARCH_POPULATES_NODE_MAP=y
43CONFIG_SELECT_MEMORY_MODEL=y
44CONFIG_FLATMEM_MANUAL=y
45CONFIG_FLATMEM=y
46CONFIG_FLAT_NODE_MEM_MAP=y
47CONFIG_PAGEFLAGS_EXTENDED=y
48CONFIG_SPLIT_PTLOCK_CPUS=4
49CONFIG_COMPACTION=y
50CONFIG_MIGRATION=y
51CONFIG_PHYS_ADDR_T_64BIT=y
52CONFIG_ZONE_DMA_FLAG=0
53CONFIG_VIRT_TO_BUS=y
54CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
55CONFIG_NEED_PER_CPU_KM=y
56CONFIG_TICK_ONESHOT=y
57CONFIG_NO_HZ=y
58CONFIG_HIGH_RES_TIMERS=y
59CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
60CONFIG_HZ_100=y
61CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
62CONFIG_HZ=100
63CONFIG_PREEMPT_NONE=y
64CONFIG_LOCKDEP_SUPPORT=y
65CONFIG_STACKTRACE_SUPPORT=y
66CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
67CONFIG_CONSTRUCTORS=y
68CONFIG_HAVE_IRQ_WORK=y
69CONFIG_EXPERIMENTAL=y
70CONFIG_BROKEN_ON_SMP=y
71CONFIG_INIT_ENV_ARG_LIMIT=32
72CONFIG_CROSS_COMPILE=""
73CONFIG_LOCALVERSION="-db1300"
74CONFIG_LOCALVERSION_AUTO=y
75CONFIG_HAVE_KERNEL_GZIP=y
76CONFIG_HAVE_KERNEL_BZIP2=y
77CONFIG_HAVE_KERNEL_LZMA=y
78CONFIG_HAVE_KERNEL_LZO=y
79CONFIG_KERNEL_LZMA=y
80CONFIG_SWAP=y
81CONFIG_SYSVIPC=y
82CONFIG_SYSVIPC_SYSCTL=y
83CONFIG_POSIX_MQUEUE=y
84CONFIG_POSIX_MQUEUE_SYSCTL=y
85CONFIG_FHANDLE=y
86CONFIG_HAVE_GENERIC_HARDIRQS=y
87CONFIG_GENERIC_HARDIRQS=y
88CONFIG_GENERIC_IRQ_PROBE=y
89CONFIG_GENERIC_IRQ_SHOW=y
90CONFIG_TINY_RCU=y
91CONFIG_LOG_BUF_SHIFT=19
92CONFIG_NAMESPACES=y
93CONFIG_UTS_NS=y
94CONFIG_IPC_NS=y
95CONFIG_USER_NS=y
96CONFIG_PID_NS=y
97CONFIG_NET_NS=y
98CONFIG_SYSCTL=y
99CONFIG_ANON_INODES=y
100CONFIG_EXPERT=y
101CONFIG_SYSCTL_SYSCALL=y
102CONFIG_KALLSYMS=y
103CONFIG_KALLSYMS_ALL=y
104CONFIG_HOTPLUG=y
105CONFIG_PRINTK=y
106CONFIG_BUG=y
107CONFIG_ELF_CORE=y
108CONFIG_BASE_FULL=y
109CONFIG_FUTEX=y
110CONFIG_EPOLL=y
111CONFIG_SIGNALFD=y
112CONFIG_TIMERFD=y
113CONFIG_EVENTFD=y
114CONFIG_SHMEM=y
115CONFIG_AIO=y
116CONFIG_EMBEDDED=y
117CONFIG_HAVE_PERF_EVENTS=y
118CONFIG_PERF_USE_VMALLOC=y
119CONFIG_SLAB=y
120CONFIG_HAVE_OPROFILE=y
121CONFIG_HAVE_KPROBES=y
122CONFIG_HAVE_KRETPROBES=y
123CONFIG_HAVE_DMA_ATTRS=y
124CONFIG_HAVE_DMA_API_DEBUG=y
125CONFIG_HAVE_ARCH_JUMP_LABEL=y
126CONFIG_HAVE_GENERIC_DMA_COHERENT=y
127CONFIG_SLABINFO=y
128CONFIG_RT_MUTEXES=y
129CONFIG_BASE_SMALL=0
130CONFIG_BLOCK=y
131CONFIG_LBDAF=y
132CONFIG_BLK_DEV_BSG=y
133CONFIG_IOSCHED_NOOP=y
134CONFIG_DEFAULT_NOOP=y
135CONFIG_DEFAULT_IOSCHED="noop"
136CONFIG_INLINE_SPIN_UNLOCK=y
137CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
138CONFIG_INLINE_READ_UNLOCK=y
139CONFIG_INLINE_READ_UNLOCK_IRQ=y
140CONFIG_INLINE_WRITE_UNLOCK=y
141CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
142CONFIG_MMU=y
143CONFIG_PCCARD=y
144CONFIG_PCMCIA=y
145CONFIG_PCMCIA_LOAD_CIS=y
146CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y
147CONFIG_BINFMT_ELF=y
148CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
149CONFIG_TRAD_SIGNALS=y
150CONFIG_ARCH_HIBERNATION_POSSIBLE=y
151CONFIG_ARCH_SUSPEND_POSSIBLE=y
152CONFIG_NET=y
153CONFIG_PACKET=y
154CONFIG_UNIX=y
155CONFIG_XFRM=y
156CONFIG_INET=y
157CONFIG_IP_MULTICAST=y
158CONFIG_IP_PNP=y
159CONFIG_IP_PNP_DHCP=y
160CONFIG_IP_PNP_BOOTP=y
161CONFIG_IP_PNP_RARP=y
162CONFIG_INET_TUNNEL=y
163CONFIG_TCP_CONG_CUBIC=y
164CONFIG_DEFAULT_TCP_CONG="cubic"
165CONFIG_IPV6=y
166CONFIG_INET6_XFRM_MODE_TRANSPORT=y
167CONFIG_INET6_XFRM_MODE_TUNNEL=y
168CONFIG_INET6_XFRM_MODE_BEET=y
169CONFIG_IPV6_SIT=y
170CONFIG_IPV6_NDISC_NODETYPE=y
171CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
172CONFIG_STANDALONE=y
173CONFIG_PREVENT_FIRMWARE_BUILD=y
174CONFIG_FW_LOADER=y
175CONFIG_FIRMWARE_IN_KERNEL=y
176CONFIG_EXTRA_FIRMWARE=""
177CONFIG_MTD=y
178CONFIG_MTD_CMDLINE_PARTS=y
179CONFIG_MTD_CHAR=y
180CONFIG_MTD_BLKDEVS=y
181CONFIG_MTD_BLOCK=y
182CONFIG_MTD_CFI=y
183CONFIG_MTD_GEN_PROBE=y
184CONFIG_MTD_MAP_BANK_WIDTH_1=y
185CONFIG_MTD_MAP_BANK_WIDTH_2=y
186CONFIG_MTD_MAP_BANK_WIDTH_4=y
187CONFIG_MTD_CFI_I1=y
188CONFIG_MTD_CFI_I2=y
189CONFIG_MTD_CFI_AMDSTD=y
190CONFIG_MTD_CFI_UTIL=y
191CONFIG_MTD_PHYSMAP=y
192CONFIG_MTD_NAND_ECC=y
193CONFIG_MTD_NAND=y
194CONFIG_MTD_NAND_IDS=y
195CONFIG_MTD_NAND_PLATFORM=y
196CONFIG_BLK_DEV=y
197CONFIG_BLK_DEV_LOOP=y
198CONFIG_BLK_DEV_UB=y
199CONFIG_HAVE_IDE=y
200CONFIG_IDE=y
201CONFIG_IDE_GD=y
202CONFIG_IDE_GD_ATA=y
203CONFIG_BLK_DEV_IDECS=y
204CONFIG_IDE_TASK_IOCTL=y
205CONFIG_IDE_PROC_FS=y
206CONFIG_BLK_DEV_PLATFORM=y
207CONFIG_SCSI_MOD=y
208CONFIG_NETDEVICES=y
209CONFIG_MII=y
210CONFIG_PHYLIB=y
211CONFIG_SMSC_PHY=y
212CONFIG_NET_ETHERNET=y
213CONFIG_SMSC911X=y
214CONFIG_INPUT=y
215CONFIG_INPUT_EVDEV=y
216CONFIG_INPUT_KEYBOARD=y
217CONFIG_KEYBOARD_GPIO=y
218CONFIG_INPUT_TOUCHSCREEN=y
219CONFIG_TOUCHSCREEN_WM97XX=y
220CONFIG_TOUCHSCREEN_WM9712=y
221CONFIG_TOUCHSCREEN_WM9713=y
222CONFIG_INPUT_MISC=y
223CONFIG_INPUT_UINPUT=y
224CONFIG_VT=y
225CONFIG_CONSOLE_TRANSLATIONS=y
226CONFIG_VT_CONSOLE=y
227CONFIG_HW_CONSOLE=y
228CONFIG_VT_HW_CONSOLE_BINDING=y
229CONFIG_UNIX98_PTYS=y
230CONFIG_SERIAL_8250=y
231CONFIG_SERIAL_8250_CONSOLE=y
232CONFIG_SERIAL_8250_NR_UARTS=4
233CONFIG_SERIAL_8250_RUNTIME_UARTS=4
234CONFIG_SERIAL_CORE=y
235CONFIG_SERIAL_CORE_CONSOLE=y
236CONFIG_I2C=y
237CONFIG_I2C_BOARDINFO=y
238CONFIG_I2C_CHARDEV=y
239CONFIG_I2C_SMBUS=y
240CONFIG_I2C_AU1550=y
241CONFIG_SPI=y
242CONFIG_SPI_MASTER=y
243CONFIG_SPI_AU1550=y
244CONFIG_SPI_BITBANG=y
245CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
246CONFIG_HWMON=y
247CONFIG_HWMON_VID=y
248CONFIG_SENSORS_ADM1025=y
249CONFIG_FB=y
250CONFIG_FB_AU1200=y
251CONFIG_DUMMY_CONSOLE=y
252CONFIG_FRAMEBUFFER_CONSOLE=y
253CONFIG_FONTS=y
254CONFIG_FONT_ACORN_8x8=y
255CONFIG_LOGO=y
256CONFIG_LOGO_LINUX_CLUT224=y
257CONFIG_SOUND=y
258CONFIG_SND=y
259CONFIG_SND_TIMER=y
260CONFIG_SND_PCM=y
261CONFIG_SND_JACK=y
262CONFIG_SND_HRTIMER=y
263CONFIG_SND_DYNAMIC_MINORS=y
264CONFIG_SND_VERBOSE_PROCFS=y
265CONFIG_SND_VERBOSE_PRINTK=y
266CONFIG_SND_VMASTER=y
267CONFIG_SND_AC97_CODEC=y
268CONFIG_SND_SOC=y
269CONFIG_SND_SOC_CACHE_LZO=y
270CONFIG_SND_SOC_AC97_BUS=y
271CONFIG_SND_SOC_AU1XPSC=y
272CONFIG_SND_SOC_AU1XPSC_I2S=y
273CONFIG_SND_SOC_AU1XPSC_AC97=y
274CONFIG_SND_SOC_DB1300=y
275CONFIG_SND_SOC_I2C_AND_SPI=y
276CONFIG_SND_SOC_WM8731=y
277CONFIG_SND_SOC_WM9712=y
278CONFIG_AC97_BUS=y
279CONFIG_HID_SUPPORT=y
280CONFIG_HID=y
281CONFIG_HIDRAW=y
282CONFIG_USB_HID=y
283CONFIG_USB_HIDDEV=y
284CONFIG_USB_SUPPORT=y
285CONFIG_USB_ARCH_HAS_HCD=y
286CONFIG_USB_ARCH_HAS_OHCI=y
287CONFIG_USB_ARCH_HAS_EHCI=y
288CONFIG_USB=y
289CONFIG_USB_DYNAMIC_MINORS=y
290CONFIG_USB_EHCI_HCD=y
291CONFIG_USB_EHCI_ROOT_HUB_TT=y
292CONFIG_USB_EHCI_TT_NEWSCHED=y
293CONFIG_USB_OHCI_HCD=y
294CONFIG_USB_OHCI_LITTLE_ENDIAN=y
295CONFIG_RTC_LIB=y
296CONFIG_RTC_CLASS=y
297CONFIG_RTC_HCTOSYS=y
298CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
299CONFIG_RTC_INTF_SYSFS=y
300CONFIG_RTC_INTF_PROC=y
301CONFIG_RTC_INTF_DEV=y
302CONFIG_RTC_INTF_DEV_UIE_EMUL=y
303CONFIG_RTC_DRV_AU1XXX=y
304CONFIG_EXT2_FS=y
305CONFIG_FS_POSIX_ACL=y
306CONFIG_EXPORTFS=y
307CONFIG_FILE_LOCKING=y
308CONFIG_FSNOTIFY=y
309CONFIG_DNOTIFY=y
310CONFIG_INOTIFY_USER=y
311CONFIG_GENERIC_ACL=y
312CONFIG_FAT_FS=y
313CONFIG_VFAT_FS=y
314CONFIG_FAT_DEFAULT_CODEPAGE=437
315CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
316CONFIG_PROC_FS=y
317CONFIG_PROC_SYSCTL=y
318CONFIG_PROC_PAGE_MONITOR=y
319CONFIG_SYSFS=y
320CONFIG_TMPFS=y
321CONFIG_TMPFS_POSIX_ACL=y
322CONFIG_TMPFS_XATTR=y
323CONFIG_MISC_FILESYSTEMS=y
324CONFIG_JFFS2_FS=y
325CONFIG_JFFS2_FS_DEBUG=0
326CONFIG_JFFS2_FS_WRITEBUFFER=y
327CONFIG_JFFS2_SUMMARY=y
328CONFIG_JFFS2_FS_XATTR=y
329CONFIG_JFFS2_FS_POSIX_ACL=y
330CONFIG_JFFS2_FS_SECURITY=y
331CONFIG_JFFS2_COMPRESSION_OPTIONS=y
332CONFIG_JFFS2_ZLIB=y
333CONFIG_JFFS2_LZO=y
334CONFIG_JFFS2_RTIME=y
335CONFIG_JFFS2_RUBIN=y
336CONFIG_JFFS2_CMODE_PRIORITY=y
337CONFIG_SQUASHFS=y
338CONFIG_SQUASHFS_XZ=y
339CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
340CONFIG_NETWORK_FILESYSTEMS=y
341CONFIG_NFS_FS=y
342CONFIG_NFS_V3=y
343CONFIG_ROOT_NFS=y
344CONFIG_LOCKD=y
345CONFIG_LOCKD_V4=y
346CONFIG_NFS_COMMON=y
347CONFIG_SUNRPC=y
348CONFIG_MSDOS_PARTITION=y
349CONFIG_NLS=y
350CONFIG_NLS_DEFAULT="iso8859-1"
351CONFIG_NLS_CODEPAGE_437=y
352CONFIG_NLS_CODEPAGE_850=y
353CONFIG_NLS_ASCII=y
354CONFIG_NLS_ISO8859_1=y
355CONFIG_NLS_ISO8859_15=y
356CONFIG_NLS_UTF8=y
357CONFIG_TRACE_IRQFLAGS_SUPPORT=y
358CONFIG_PRINTK_TIME=y
359CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
360CONFIG_ENABLE_WARN_DEPRECATED=y
361CONFIG_ENABLE_MUST_CHECK=y
362CONFIG_FRAME_WARN=1024
363CONFIG_MAGIC_SYSRQ=y
364CONFIG_STRIP_ASM_SYMS=y
365CONFIG_HAVE_FUNCTION_TRACER=y
366CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
367CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
368CONFIG_HAVE_DYNAMIC_FTRACE=y
369CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
370CONFIG_HAVE_C_RECORDMCOUNT=y
371CONFIG_TRACING_SUPPORT=y
372CONFIG_HAVE_ARCH_KGDB=y
373CONFIG_EARLY_PRINTK=y
374CONFIG_CMDLINE_BOOL=y
375CONFIG_CMDLINE="video=au1200fb:panel:bs console=tty console=ttyS2,115200"
376CONFIG_DEBUG_ZBOOT=y
377CONFIG_DEFAULT_SECURITY_DAC=y
378CONFIG_DEFAULT_SECURITY=""
379CONFIG_CRYPTO=y
380CONFIG_BITREVERSE=y
381CONFIG_CRC32=y
382CONFIG_ZLIB_INFLATE=y
383CONFIG_ZLIB_DEFLATE=y
384CONFIG_LZO_COMPRESS=y
385CONFIG_LZO_DECOMPRESS=y
386CONFIG_XZ_DEC=y
387CONFIG_HAS_IOMEM=y
388CONFIG_HAS_IOPORT=y
389CONFIG_HAS_DMA=y
390CONFIG_NLATTR=y
391CONFIG_GENERIC_ATOMIC64=y
diff --git a/arch/mips/configs/db1500_defconfig b/arch/mips/configs/db1500_defconfig
deleted file mode 100644
index b6e21c7cb6bd..000000000000
--- a/arch/mips/configs/db1500_defconfig
+++ /dev/null
@@ -1,128 +0,0 @@
1CONFIG_MIPS_ALCHEMY=y
2CONFIG_MIPS_DB1500=y
3CONFIG_CPU_LITTLE_ENDIAN=y
4CONFIG_NO_HZ=y
5CONFIG_HIGH_RES_TIMERS=y
6CONFIG_HZ_100=y
7# CONFIG_SECCOMP is not set
8CONFIG_EXPERIMENTAL=y
9CONFIG_LOCALVERSION="-db1500"
10CONFIG_KERNEL_LZMA=y
11CONFIG_SYSVIPC=y
12CONFIG_LOG_BUF_SHIFT=14
13CONFIG_EXPERT=y
14# CONFIG_KALLSYMS is not set
15# CONFIG_PCSPKR_PLATFORM is not set
16# CONFIG_VM_EVENT_COUNTERS is not set
17# CONFIG_COMPAT_BRK is not set
18CONFIG_SLAB=y
19CONFIG_MODULES=y
20CONFIG_MODULE_UNLOAD=y
21# CONFIG_IOSCHED_DEADLINE is not set
22# CONFIG_IOSCHED_CFQ is not set
23CONFIG_PCI=y
24CONFIG_PCCARD=y
25# CONFIG_CARDBUS is not set
26CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y
27CONFIG_PM=y
28CONFIG_PM_RUNTIME=y
29CONFIG_NET=y
30CONFIG_PACKET=y
31CONFIG_UNIX=y
32CONFIG_INET=y
33CONFIG_IP_MULTICAST=y
34CONFIG_IP_PNP=y
35CONFIG_IP_PNP_DHCP=y
36CONFIG_IP_PNP_BOOTP=y
37CONFIG_IP_PNP_RARP=y
38# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
39# CONFIG_INET_XFRM_MODE_TUNNEL is not set
40# CONFIG_INET_XFRM_MODE_BEET is not set
41# CONFIG_INET_DIAG is not set
42# CONFIG_IPV6 is not set
43# CONFIG_WIRELESS is not set
44CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
45CONFIG_MTD=y
46CONFIG_MTD_PARTITIONS=y
47CONFIG_MTD_CMDLINE_PARTS=y
48CONFIG_MTD_CHAR=y
49CONFIG_MTD_BLOCK=y
50CONFIG_MTD_CFI=y
51CONFIG_MTD_CFI_INTELEXT=y
52CONFIG_MTD_CFI_AMDSTD=y
53CONFIG_MTD_PHYSMAP=y
54# CONFIG_MISC_DEVICES is not set
55CONFIG_IDE=y
56CONFIG_BLK_DEV_IDECS=y
57# CONFIG_IDEPCI_PCIBUS_ORDER is not set
58CONFIG_BLK_DEV_HPT366=y
59CONFIG_NETDEVICES=y
60CONFIG_MARVELL_PHY=y
61CONFIG_DAVICOM_PHY=y
62CONFIG_QSEMI_PHY=y
63CONFIG_LXT_PHY=y
64CONFIG_CICADA_PHY=y
65CONFIG_VITESSE_PHY=y
66CONFIG_SMSC_PHY=y
67CONFIG_BROADCOM_PHY=y
68CONFIG_ICPLUS_PHY=y
69CONFIG_REALTEK_PHY=y
70CONFIG_NATIONAL_PHY=y
71CONFIG_STE10XP=y
72CONFIG_LSI_ET1011C_PHY=y
73CONFIG_NET_ETHERNET=y
74CONFIG_MII=y
75CONFIG_MIPS_AU1X00_ENET=y
76# CONFIG_NETDEV_1000 is not set
77# CONFIG_NETDEV_10000 is not set
78# CONFIG_WLAN is not set
79# CONFIG_INPUT_MOUSEDEV is not set
80CONFIG_INPUT_EVDEV=y
81# CONFIG_INPUT_KEYBOARD is not set
82# CONFIG_INPUT_MOUSE is not set
83# CONFIG_SERIO is not set
84CONFIG_SERIAL_8250=y
85CONFIG_SERIAL_8250_CONSOLE=y
86# CONFIG_SERIAL_8250_PCI is not set
87# CONFIG_LEGACY_PTYS is not set
88# CONFIG_HW_RANDOM is not set
89# CONFIG_HWMON is not set
90# CONFIG_VGA_ARB is not set
91# CONFIG_VGA_CONSOLE is not set
92# CONFIG_HID_SUPPORT is not set
93CONFIG_USB=y
94# CONFIG_USB_DEVICE_CLASS is not set
95CONFIG_USB_DYNAMIC_MINORS=y
96CONFIG_USB_SUSPEND=y
97CONFIG_USB_OHCI_HCD=y
98CONFIG_RTC_CLASS=y
99CONFIG_RTC_DRV_AU1XXX=y
100CONFIG_EXT2_FS=y
101# CONFIG_PROC_PAGE_MONITOR is not set
102CONFIG_TMPFS=y
103CONFIG_JFFS2_FS=y
104CONFIG_JFFS2_SUMMARY=y
105CONFIG_JFFS2_FS_XATTR=y
106CONFIG_JFFS2_COMPRESSION_OPTIONS=y
107CONFIG_JFFS2_LZO=y
108CONFIG_JFFS2_RUBIN=y
109CONFIG_SQUASHFS=y
110CONFIG_NFS_FS=y
111CONFIG_NFS_V3=y
112CONFIG_ROOT_NFS=y
113CONFIG_NLS_CODEPAGE_437=y
114CONFIG_NLS_CODEPAGE_850=y
115CONFIG_NLS_CODEPAGE_1250=y
116CONFIG_NLS_ASCII=y
117CONFIG_NLS_ISO8859_1=y
118CONFIG_NLS_ISO8859_15=y
119CONFIG_NLS_UTF8=y
120CONFIG_STRIP_ASM_SYMS=y
121CONFIG_DEBUG_KERNEL=y
122# CONFIG_SCHED_DEBUG is not set
123# CONFIG_RCU_CPU_STALL_DETECTOR is not set
124# CONFIG_FTRACE is not set
125CONFIG_DEBUG_ZBOOT=y
126CONFIG_KEYS=y
127CONFIG_KEYS_DEBUG_PROC_KEYS=y
128CONFIG_SECURITYFS=y
diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig
index 798a553c9e80..36cda27725e7 100644
--- a/arch/mips/configs/db1550_defconfig
+++ b/arch/mips/configs/db1550_defconfig
@@ -1,145 +1,262 @@
1CONFIG_MIPS=y
1CONFIG_MIPS_ALCHEMY=y 2CONFIG_MIPS_ALCHEMY=y
2CONFIG_MIPS_DB1550=y 3CONFIG_MIPS_DB1550=y
4CONFIG_SCHED_OMIT_FRAME_POINTER=y
5CONFIG_GENERIC_GPIO=y
6CONFIG_TICK_ONESHOT=y
3CONFIG_NO_HZ=y 7CONFIG_NO_HZ=y
4CONFIG_HIGH_RES_TIMERS=y 8CONFIG_HIGH_RES_TIMERS=y
5CONFIG_HZ_100=y 9CONFIG_HZ_100=y
6# CONFIG_SECCOMP is not set 10CONFIG_HZ=100
7CONFIG_EXPERIMENTAL=y 11CONFIG_EXPERIMENTAL=y
12CONFIG_BROKEN_ON_SMP=y
13CONFIG_INIT_ENV_ARG_LIMIT=32
8CONFIG_LOCALVERSION="-db1550" 14CONFIG_LOCALVERSION="-db1550"
15CONFIG_LOCALVERSION_AUTO=y
9CONFIG_KERNEL_LZMA=y 16CONFIG_KERNEL_LZMA=y
17CONFIG_DEFAULT_HOSTNAME="db1550"
18CONFIG_SWAP=y
10CONFIG_SYSVIPC=y 19CONFIG_SYSVIPC=y
20CONFIG_SYSVIPC_SYSCTL=y
11CONFIG_POSIX_MQUEUE=y 21CONFIG_POSIX_MQUEUE=y
22CONFIG_POSIX_MQUEUE_SYSCTL=y
23CONFIG_FHANDLE=y
24CONFIG_AUDIT=y
12CONFIG_TINY_RCU=y 25CONFIG_TINY_RCU=y
13CONFIG_LOG_BUF_SHIFT=14 26CONFIG_LOG_BUF_SHIFT=18
27CONFIG_NAMESPACES=y
28CONFIG_UTS_NS=y
29CONFIG_IPC_NS=y
30CONFIG_USER_NS=y
31CONFIG_PID_NS=y
32CONFIG_NET_NS=y
14CONFIG_EXPERT=y 33CONFIG_EXPERT=y
15# CONFIG_SYSCTL_SYSCALL is not set 34CONFIG_HOTPLUG=y
16# CONFIG_KALLSYMS is not set 35CONFIG_PRINTK=y
17# CONFIG_PCSPKR_PLATFORM is not set 36CONFIG_BUG=y
18# CONFIG_VM_EVENT_COUNTERS is not set 37CONFIG_ELF_CORE=y
19# CONFIG_COMPAT_BRK is not set 38CONFIG_BASE_FULL=y
39CONFIG_FUTEX=y
40CONFIG_EPOLL=y
41CONFIG_SIGNALFD=y
42CONFIG_TIMERFD=y
43CONFIG_EVENTFD=y
44CONFIG_SHMEM=y
45CONFIG_AIO=y
46CONFIG_EMBEDDED=y
47CONFIG_PCI_QUIRKS=y
20CONFIG_SLAB=y 48CONFIG_SLAB=y
21CONFIG_MODULES=y 49CONFIG_BLOCK=y
22CONFIG_MODULE_UNLOAD=y 50CONFIG_LBDAF=y
23# CONFIG_IOSCHED_DEADLINE is not set 51CONFIG_BLK_DEV_BSG=y
24# CONFIG_IOSCHED_CFQ is not set 52CONFIG_BLK_DEV_BSGLIB=y
53CONFIG_IOSCHED_NOOP=y
54CONFIG_DEFAULT_NOOP=y
55CONFIG_DEFAULT_IOSCHED="noop"
25CONFIG_PCI=y 56CONFIG_PCI=y
26CONFIG_PCCARD=y 57CONFIG_PCCARD=y
27# CONFIG_CARDBUS is not set 58CONFIG_PCMCIA=y
59CONFIG_PCMCIA_LOAD_CIS=y
28CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y 60CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y
29CONFIG_PM=y 61CONFIG_BINFMT_ELF=y
62CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
63CONFIG_BINFMT_MISC=y
64CONFIG_SUSPEND=y
65CONFIG_SUSPEND_FREEZER=y
66CONFIG_PM_SLEEP=y
30CONFIG_PM_RUNTIME=y 67CONFIG_PM_RUNTIME=y
68CONFIG_PM=y
31CONFIG_NET=y 69CONFIG_NET=y
32CONFIG_PACKET=y 70CONFIG_PACKET=y
33CONFIG_UNIX=y 71CONFIG_UNIX=y
72CONFIG_XFRM=y
34CONFIG_INET=y 73CONFIG_INET=y
35CONFIG_IP_MULTICAST=y 74CONFIG_IP_MULTICAST=y
36CONFIG_IP_PNP=y 75CONFIG_IP_PNP=y
37CONFIG_IP_PNP_DHCP=y 76CONFIG_IP_PNP_DHCP=y
38CONFIG_IP_PNP_BOOTP=y 77CONFIG_IP_PNP_BOOTP=y
39CONFIG_IP_PNP_RARP=y 78CONFIG_IP_PNP_RARP=y
40# CONFIG_INET_XFRM_MODE_TRANSPORT is not set 79CONFIG_INET_TUNNEL=y
41# CONFIG_INET_XFRM_MODE_TUNNEL is not set 80CONFIG_INET_LRO=y
42# CONFIG_INET_XFRM_MODE_BEET is not set 81CONFIG_TCP_CONG_CUBIC=y
43# CONFIG_INET_DIAG is not set 82CONFIG_DEFAULT_TCP_CONG="cubic"
44# CONFIG_IPV6 is not set 83CONFIG_IPV6=y
45# CONFIG_WIRELESS is not set 84CONFIG_INET6_XFRM_MODE_TRANSPORT=y
46CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 85CONFIG_INET6_XFRM_MODE_TUNNEL=y
86CONFIG_INET6_XFRM_MODE_BEET=y
87CONFIG_IPV6_SIT=y
88CONFIG_IPV6_NDISC_NODETYPE=y
89CONFIG_DNS_RESOLVER=y
90CONFIG_UEVENT_HELPER_PATH=""
91CONFIG_STANDALONE=y
92CONFIG_PREVENT_FIRMWARE_BUILD=y
93CONFIG_FW_LOADER=y
94CONFIG_FIRMWARE_IN_KERNEL=y
47CONFIG_MTD=y 95CONFIG_MTD=y
48CONFIG_MTD_PARTITIONS=y
49CONFIG_MTD_CHAR=y 96CONFIG_MTD_CHAR=y
97CONFIG_MTD_BLKDEVS=y
50CONFIG_MTD_BLOCK=y 98CONFIG_MTD_BLOCK=y
51CONFIG_MTD_CFI=y 99CONFIG_MTD_CFI=y
100CONFIG_MTD_GEN_PROBE=y
101CONFIG_MTD_MAP_BANK_WIDTH_1=y
102CONFIG_MTD_MAP_BANK_WIDTH_2=y
103CONFIG_MTD_MAP_BANK_WIDTH_4=y
104CONFIG_MTD_CFI_I1=y
105CONFIG_MTD_CFI_I2=y
52CONFIG_MTD_CFI_AMDSTD=y 106CONFIG_MTD_CFI_AMDSTD=y
107CONFIG_MTD_CFI_UTIL=y
53CONFIG_MTD_PHYSMAP=y 108CONFIG_MTD_PHYSMAP=y
109CONFIG_MTD_M25P80=y
110CONFIG_MTD_NAND_ECC=y
54CONFIG_MTD_NAND=y 111CONFIG_MTD_NAND=y
55CONFIG_MTD_NAND_AU1550=y 112CONFIG_MTD_NAND_IDS=y
56CONFIG_BLK_DEV_UB=y 113CONFIG_MTD_NAND_PLATFORM=y
57# CONFIG_MISC_DEVICES is not set 114CONFIG_MISC_DEVICES=y
58CONFIG_IDE=y 115CONFIG_EEPROM_AT24=y
59CONFIG_BLK_DEV_IDECS=y 116CONFIG_SCSI_MOD=y
60CONFIG_BLK_DEV_IDECD=y 117CONFIG_SCSI=y
61# CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS is not set 118CONFIG_SCSI_DMA=y
62CONFIG_IDE_TASK_IOCTL=y 119CONFIG_BLK_DEV_SD=y
63# CONFIG_IDEPCI_PCIBUS_ORDER is not set 120CONFIG_CHR_DEV_SG=y
64CONFIG_BLK_DEV_HPT366=y 121CONFIG_SCSI_MULTI_LUN=y
122CONFIG_SCSI_SCAN_ASYNC=y
123CONFIG_ATA=y
124CONFIG_ATA_SFF=y
125CONFIG_ATA_BMDMA=y
126CONFIG_PATA_HPT37X=y
127CONFIG_PATA_PCMCIA=y
128CONFIG_MD=y
129CONFIG_BLK_DEV_DM=y
65CONFIG_NETDEVICES=y 130CONFIG_NETDEVICES=y
66CONFIG_MARVELL_PHY=y
67CONFIG_DAVICOM_PHY=y
68CONFIG_QSEMI_PHY=y
69CONFIG_LXT_PHY=y
70CONFIG_CICADA_PHY=y
71CONFIG_VITESSE_PHY=y
72CONFIG_SMSC_PHY=y
73CONFIG_BROADCOM_PHY=y
74CONFIG_ICPLUS_PHY=y
75CONFIG_REALTEK_PHY=y
76CONFIG_NATIONAL_PHY=y
77CONFIG_STE10XP=y
78CONFIG_LSI_ET1011C_PHY=y
79CONFIG_NET_ETHERNET=y
80CONFIG_MII=y 131CONFIG_MII=y
132CONFIG_PHYLIB=y
133CONFIG_NET_ETHERNET=y
81CONFIG_MIPS_AU1X00_ENET=y 134CONFIG_MIPS_AU1X00_ENET=y
82# CONFIG_NETDEV_1000 is not set 135CONFIG_NET_PCMCIA=y
83# CONFIG_NETDEV_10000 is not set 136CONFIG_PCMCIA_3C589=y
84# CONFIG_WLAN is not set 137CONFIG_PCMCIA_PCNET=y
85# CONFIG_INPUT_MOUSEDEV is not set 138CONFIG_INPUT=y
86CONFIG_INPUT_EVDEV=y 139CONFIG_INPUT_EVDEV=y
87# CONFIG_INPUT_KEYBOARD is not set 140CONFIG_VT=y
88# CONFIG_INPUT_MOUSE is not set 141CONFIG_CONSOLE_TRANSLATIONS=y
89# CONFIG_SERIO is not set 142CONFIG_VT_CONSOLE=y
143CONFIG_HW_CONSOLE=y
144CONFIG_UNIX98_PTYS=y
145CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
146CONFIG_DEVKMEM=y
90CONFIG_SERIAL_8250=y 147CONFIG_SERIAL_8250=y
91CONFIG_SERIAL_8250_CONSOLE=y 148CONFIG_SERIAL_8250_CONSOLE=y
92# CONFIG_LEGACY_PTYS is not set 149CONFIG_SERIAL_8250_NR_UARTS=4
93# CONFIG_HW_RANDOM is not set 150CONFIG_SERIAL_8250_RUNTIME_UARTS=4
151CONFIG_SERIAL_CORE=y
152CONFIG_SERIAL_CORE_CONSOLE=y
153CONFIG_DEVPORT=y
94CONFIG_I2C=y 154CONFIG_I2C=y
95# CONFIG_I2C_COMPAT is not set 155CONFIG_I2C_BOARDINFO=y
96CONFIG_I2C_CHARDEV=y 156CONFIG_I2C_CHARDEV=y
97# CONFIG_I2C_HELPER_AUTO is not set
98CONFIG_I2C_AU1550=y 157CONFIG_I2C_AU1550=y
99CONFIG_SPI=y 158CONFIG_SPI=y
159CONFIG_SPI_MASTER=y
100CONFIG_SPI_AU1550=y 160CONFIG_SPI_AU1550=y
101# CONFIG_HWMON is not set 161CONFIG_SPI_BITBANG=y
102# CONFIG_VGA_ARB is not set 162CONFIG_HWMON=y
103# CONFIG_VGA_CONSOLE is not set 163CONFIG_SENSORS_ADM1025=y
164CONFIG_SENSORS_LM70=y
165CONFIG_DUMMY_CONSOLE=y
104CONFIG_SOUND=y 166CONFIG_SOUND=y
105CONFIG_SND=y 167CONFIG_SND=y
106CONFIG_SND_HRTIMER=y 168CONFIG_SND_TIMER=y
107CONFIG_SND_DYNAMIC_MINORS=y 169CONFIG_SND_PCM=y
108# CONFIG_SND_SUPPORT_OLD_API is not set 170CONFIG_SND_JACK=y
109# CONFIG_SND_VERBOSE_PROCFS is not set 171CONFIG_SND_VMASTER=y
110# CONFIG_SND_DRIVERS is not set 172CONFIG_SND_AC97_CODEC=y
111# CONFIG_SND_PCI is not set
112# CONFIG_SND_SPI is not set
113# CONFIG_SND_MIPS is not set
114# CONFIG_SND_PCMCIA is not set
115CONFIG_SND_SOC=y 173CONFIG_SND_SOC=y
174CONFIG_SND_SOC_AC97_BUS=y
116CONFIG_SND_SOC_AU1XPSC=y 175CONFIG_SND_SOC_AU1XPSC=y
117# CONFIG_HID_SUPPORT is not set 176CONFIG_SND_SOC_AU1XPSC_I2S=y
177CONFIG_SND_SOC_AU1XPSC_AC97=y
178CONFIG_SND_SOC_DB1200=y
179CONFIG_SND_SOC_I2C_AND_SPI=y
180CONFIG_SND_SOC_AC97_CODEC=y
181CONFIG_SND_SOC_WM8731=y
182CONFIG_SND_SOC_WM9712=y
183CONFIG_AC97_BUS=y
118CONFIG_USB=y 184CONFIG_USB=y
119# CONFIG_USB_DEVICE_CLASS is not set
120CONFIG_USB_DYNAMIC_MINORS=y 185CONFIG_USB_DYNAMIC_MINORS=y
121CONFIG_USB_SUSPEND=y
122CONFIG_USB_EHCI_HCD=y 186CONFIG_USB_EHCI_HCD=y
123CONFIG_USB_EHCI_ROOT_HUB_TT=y 187CONFIG_USB_EHCI_ROOT_HUB_TT=y
188CONFIG_USB_EHCI_TT_NEWSCHED=y
124CONFIG_USB_OHCI_HCD=y 189CONFIG_USB_OHCI_HCD=y
190CONFIG_USB_OHCI_LITTLE_ENDIAN=y
191CONFIG_USB_UHCI_HCD=y
192CONFIG_USB_STORAGE=y
193CONFIG_RTC_LIB=y
125CONFIG_RTC_CLASS=y 194CONFIG_RTC_CLASS=y
195CONFIG_RTC_HCTOSYS=y
196CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
197CONFIG_RTC_INTF_SYSFS=y
198CONFIG_RTC_INTF_PROC=y
199CONFIG_RTC_INTF_DEV=y
126CONFIG_RTC_DRV_AU1XXX=y 200CONFIG_RTC_DRV_AU1XXX=y
127CONFIG_EXT2_FS=y 201CONFIG_EXT4_FS=y
128# CONFIG_PROC_PAGE_MONITOR is not set 202CONFIG_EXT4_USE_FOR_EXT23=y
203CONFIG_EXT4_FS_XATTR=y
204CONFIG_EXT4_FS_POSIX_ACL=y
205CONFIG_EXT4_FS_SECURITY=y
206CONFIG_JBD2=y
207CONFIG_FS_MBCACHE=y
208CONFIG_FS_POSIX_ACL=y
209CONFIG_EXPORTFS=y
210CONFIG_FILE_LOCKING=y
211CONFIG_FSNOTIFY=y
212CONFIG_DNOTIFY=y
213CONFIG_INOTIFY_USER=y
214CONFIG_PROC_FS=y
215CONFIG_PROC_SYSCTL=y
216CONFIG_SYSFS=y
129CONFIG_TMPFS=y 217CONFIG_TMPFS=y
130CONFIG_CONFIGFS_FS=y 218CONFIG_CONFIGFS_FS=y
219CONFIG_MISC_FILESYSTEMS=y
131CONFIG_JFFS2_FS=y 220CONFIG_JFFS2_FS=y
221CONFIG_JFFS2_FS_DEBUG=0
222CONFIG_JFFS2_FS_WRITEBUFFER=y
132CONFIG_JFFS2_SUMMARY=y 223CONFIG_JFFS2_SUMMARY=y
133CONFIG_JFFS2_FS_XATTR=y 224CONFIG_JFFS2_FS_XATTR=y
134# CONFIG_JFFS2_FS_POSIX_ACL is not set
135# CONFIG_JFFS2_FS_SECURITY is not set
136CONFIG_JFFS2_COMPRESSION_OPTIONS=y 225CONFIG_JFFS2_COMPRESSION_OPTIONS=y
226CONFIG_JFFS2_ZLIB=y
137CONFIG_JFFS2_LZO=y 227CONFIG_JFFS2_LZO=y
228CONFIG_JFFS2_RTIME=y
138CONFIG_JFFS2_RUBIN=y 229CONFIG_JFFS2_RUBIN=y
230CONFIG_JFFS2_CMODE_PRIORITY=y
139CONFIG_SQUASHFS=y 231CONFIG_SQUASHFS=y
232CONFIG_SQUASHFS_ZLIB=y
233CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
234CONFIG_NETWORK_FILESYSTEMS=y
140CONFIG_NFS_FS=y 235CONFIG_NFS_FS=y
141CONFIG_NFS_V3=y 236CONFIG_NFS_V3=y
237CONFIG_NFS_V3_ACL=y
238CONFIG_NFS_V4=y
239CONFIG_NFS_V4_1=y
240CONFIG_PNFS_FILE_LAYOUT=y
241CONFIG_PNFS_BLOCK=y
142CONFIG_ROOT_NFS=y 242CONFIG_ROOT_NFS=y
243CONFIG_NFS_USE_KERNEL_DNS=y
244CONFIG_NFS_USE_NEW_IDMAPPER=y
245CONFIG_NFSD=y
246CONFIG_NFSD_V2_ACL=y
247CONFIG_NFSD_V3=y
248CONFIG_NFSD_V3_ACL=y
249CONFIG_NFSD_V4=y
250CONFIG_LOCKD=y
251CONFIG_LOCKD_V4=y
252CONFIG_NFS_ACL_SUPPORT=y
253CONFIG_NFS_COMMON=y
254CONFIG_SUNRPC=y
255CONFIG_SUNRPC_GSS=y
256CONFIG_SUNRPC_BACKCHANNEL=y
257CONFIG_MSDOS_PARTITION=y
258CONFIG_NLS=y
259CONFIG_NLS_DEFAULT="iso8859-1"
143CONFIG_NLS_CODEPAGE_437=y 260CONFIG_NLS_CODEPAGE_437=y
144CONFIG_NLS_CODEPAGE_850=y 261CONFIG_NLS_CODEPAGE_850=y
145CONFIG_NLS_CODEPAGE_852=y 262CONFIG_NLS_CODEPAGE_852=y
@@ -148,10 +265,21 @@ CONFIG_NLS_ASCII=y
148CONFIG_NLS_ISO8859_1=y 265CONFIG_NLS_ISO8859_1=y
149CONFIG_NLS_ISO8859_15=y 266CONFIG_NLS_ISO8859_15=y
150CONFIG_NLS_UTF8=y 267CONFIG_NLS_UTF8=y
151CONFIG_DEBUG_KERNEL=y 268CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
152# CONFIG_SCHED_DEBUG is not set 269CONFIG_FRAME_WARN=1024
153# CONFIG_FTRACE is not set 270CONFIG_CMDLINE_BOOL=y
154CONFIG_DEBUG_ZBOOT=y 271CONFIG_CMDLINE="noirqdebug console=ttyS0,115200 root=/dev/sda1 rootfstype=ext4"
155CONFIG_KEYS=y 272CONFIG_KEYS=y
156CONFIG_KEYS_DEBUG_PROC_KEYS=y
157CONFIG_SECURITYFS=y 273CONFIG_SECURITYFS=y
274CONFIG_DEFAULT_SECURITY_DAC=y
275CONFIG_BITREVERSE=y
276CONFIG_CRC16=y
277CONFIG_CRC_ITU_T=y
278CONFIG_CRC32=y
279CONFIG_AUDIT_GENERIC=y
280CONFIG_ZLIB_INFLATE=y
281CONFIG_ZLIB_DEFLATE=y
282CONFIG_LZO_COMPRESS=y
283CONFIG_LZO_DECOMPRESS=y
284CONFIG_BCH=y
285CONFIG_NLATTR=y
diff --git a/arch/mips/configs/nlm_xlp_defconfig b/arch/mips/configs/nlm_xlp_defconfig
new file mode 100644
index 000000000000..4479fd669ac1
--- /dev/null
+++ b/arch/mips/configs/nlm_xlp_defconfig
@@ -0,0 +1,570 @@
1CONFIG_NLM_XLP_BOARD=y
2CONFIG_64BIT=y
3CONFIG_KSM=y
4CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
5CONFIG_SMP=y
6CONFIG_NO_HZ=y
7CONFIG_HIGH_RES_TIMERS=y
8# CONFIG_SECCOMP is not set
9CONFIG_USE_OF=y
10CONFIG_EXPERIMENTAL=y
11CONFIG_CROSS_COMPILE="mips-linux-gnu-"
12# CONFIG_LOCALVERSION_AUTO is not set
13CONFIG_SYSVIPC=y
14CONFIG_POSIX_MQUEUE=y
15CONFIG_BSD_PROCESS_ACCT=y
16CONFIG_BSD_PROCESS_ACCT_V3=y
17CONFIG_TASKSTATS=y
18CONFIG_TASK_DELAY_ACCT=y
19CONFIG_TASK_XACCT=y
20CONFIG_TASK_IO_ACCOUNTING=y
21CONFIG_AUDIT=y
22CONFIG_CGROUPS=y
23CONFIG_NAMESPACES=y
24CONFIG_BLK_DEV_INITRD=y
25CONFIG_INITRAMFS_SOURCE="usr/dev_file_list usr/rootfs.xlp"
26CONFIG_RD_BZIP2=y
27CONFIG_RD_LZMA=y
28CONFIG_INITRAMFS_COMPRESSION_LZMA=y
29CONFIG_KALLSYMS_ALL=y
30CONFIG_EMBEDDED=y
31# CONFIG_COMPAT_BRK is not set
32CONFIG_PROFILING=y
33CONFIG_MODULES=y
34CONFIG_MODULE_UNLOAD=y
35CONFIG_MODVERSIONS=y
36CONFIG_MODULE_SRCVERSION_ALL=y
37CONFIG_BLK_DEV_INTEGRITY=y
38# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
39CONFIG_BINFMT_MISC=y
40CONFIG_MIPS32_COMPAT=y
41CONFIG_MIPS32_O32=y
42CONFIG_MIPS32_N32=y
43CONFIG_PM_RUNTIME=y
44CONFIG_PM_DEBUG=y
45CONFIG_PACKET=y
46CONFIG_UNIX=y
47CONFIG_XFRM_USER=m
48CONFIG_NET_KEY=m
49CONFIG_INET=y
50CONFIG_IP_MULTICAST=y
51CONFIG_IP_ADVANCED_ROUTER=y
52CONFIG_IP_MULTIPLE_TABLES=y
53CONFIG_IP_ROUTE_MULTIPATH=y
54CONFIG_IP_ROUTE_VERBOSE=y
55CONFIG_NET_IPIP=m
56CONFIG_IP_MROUTE=y
57CONFIG_IP_PIMSM_V1=y
58CONFIG_IP_PIMSM_V2=y
59CONFIG_SYN_COOKIES=y
60CONFIG_INET_AH=m
61CONFIG_INET_ESP=m
62CONFIG_INET_IPCOMP=m
63CONFIG_INET_XFRM_MODE_TRANSPORT=m
64CONFIG_INET_XFRM_MODE_TUNNEL=m
65CONFIG_INET_XFRM_MODE_BEET=m
66CONFIG_TCP_CONG_ADVANCED=y
67CONFIG_TCP_CONG_HSTCP=m
68CONFIG_TCP_CONG_HYBLA=m
69CONFIG_TCP_CONG_SCALABLE=m
70CONFIG_TCP_CONG_LP=m
71CONFIG_TCP_CONG_VENO=m
72CONFIG_TCP_CONG_YEAH=m
73CONFIG_TCP_CONG_ILLINOIS=m
74CONFIG_TCP_MD5SIG=y
75CONFIG_IPV6=y
76CONFIG_IPV6_PRIVACY=y
77CONFIG_INET6_AH=m
78CONFIG_INET6_ESP=m
79CONFIG_INET6_IPCOMP=m
80CONFIG_INET6_XFRM_MODE_TRANSPORT=m
81CONFIG_INET6_XFRM_MODE_TUNNEL=m
82CONFIG_INET6_XFRM_MODE_BEET=m
83CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
84CONFIG_IPV6_SIT=m
85CONFIG_IPV6_TUNNEL=m
86CONFIG_IPV6_MULTIPLE_TABLES=y
87CONFIG_NETLABEL=y
88CONFIG_NETFILTER=y
89CONFIG_NF_CONNTRACK=m
90CONFIG_NF_CONNTRACK_SECMARK=y
91CONFIG_NF_CONNTRACK_EVENTS=y
92CONFIG_NF_CT_PROTO_UDPLITE=m
93CONFIG_NF_CONNTRACK_AMANDA=m
94CONFIG_NF_CONNTRACK_FTP=m
95CONFIG_NF_CONNTRACK_H323=m
96CONFIG_NF_CONNTRACK_IRC=m
97CONFIG_NF_CONNTRACK_NETBIOS_NS=m
98CONFIG_NF_CONNTRACK_PPTP=m
99CONFIG_NF_CONNTRACK_SANE=m
100CONFIG_NF_CONNTRACK_SIP=m
101CONFIG_NF_CONNTRACK_TFTP=m
102CONFIG_NF_CT_NETLINK=m
103CONFIG_NETFILTER_TPROXY=m
104CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
105CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
106CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
107CONFIG_NETFILTER_XT_TARGET_DSCP=m
108CONFIG_NETFILTER_XT_TARGET_MARK=m
109CONFIG_NETFILTER_XT_TARGET_NFLOG=m
110CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
111CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
112CONFIG_NETFILTER_XT_TARGET_TPROXY=m
113CONFIG_NETFILTER_XT_TARGET_TRACE=m
114CONFIG_NETFILTER_XT_TARGET_SECMARK=m
115CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
116CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
117CONFIG_NETFILTER_XT_MATCH_COMMENT=m
118CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
119CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
120CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
121CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
122CONFIG_NETFILTER_XT_MATCH_DSCP=m
123CONFIG_NETFILTER_XT_MATCH_ESP=m
124CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
125CONFIG_NETFILTER_XT_MATCH_HELPER=m
126CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
127CONFIG_NETFILTER_XT_MATCH_LENGTH=m
128CONFIG_NETFILTER_XT_MATCH_LIMIT=m
129CONFIG_NETFILTER_XT_MATCH_MAC=m
130CONFIG_NETFILTER_XT_MATCH_MARK=m
131CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
132CONFIG_NETFILTER_XT_MATCH_OSF=m
133CONFIG_NETFILTER_XT_MATCH_OWNER=m
134CONFIG_NETFILTER_XT_MATCH_POLICY=m
135CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
136CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
137CONFIG_NETFILTER_XT_MATCH_QUOTA=m
138CONFIG_NETFILTER_XT_MATCH_RATEEST=m
139CONFIG_NETFILTER_XT_MATCH_REALM=m
140CONFIG_NETFILTER_XT_MATCH_RECENT=m
141CONFIG_NETFILTER_XT_MATCH_SOCKET=m
142CONFIG_NETFILTER_XT_MATCH_STATE=m
143CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
144CONFIG_NETFILTER_XT_MATCH_STRING=m
145CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
146CONFIG_NETFILTER_XT_MATCH_TIME=m
147CONFIG_NETFILTER_XT_MATCH_U32=m
148CONFIG_IP_VS=m
149CONFIG_IP_VS_IPV6=y
150CONFIG_IP_VS_PROTO_TCP=y
151CONFIG_IP_VS_PROTO_UDP=y
152CONFIG_IP_VS_PROTO_ESP=y
153CONFIG_IP_VS_PROTO_AH=y
154CONFIG_IP_VS_RR=m
155CONFIG_IP_VS_WRR=m
156CONFIG_IP_VS_LC=m
157CONFIG_IP_VS_WLC=m
158CONFIG_IP_VS_LBLC=m
159CONFIG_IP_VS_LBLCR=m
160CONFIG_IP_VS_DH=m
161CONFIG_IP_VS_SH=m
162CONFIG_IP_VS_SED=m
163CONFIG_IP_VS_NQ=m
164CONFIG_IP_VS_FTP=m
165CONFIG_NF_CONNTRACK_IPV4=m
166CONFIG_IP_NF_QUEUE=m
167CONFIG_IP_NF_IPTABLES=m
168CONFIG_IP_NF_MATCH_AH=m
169CONFIG_IP_NF_MATCH_ECN=m
170CONFIG_IP_NF_MATCH_TTL=m
171CONFIG_IP_NF_FILTER=m
172CONFIG_IP_NF_TARGET_REJECT=m
173CONFIG_IP_NF_TARGET_LOG=m
174CONFIG_IP_NF_TARGET_ULOG=m
175CONFIG_NF_NAT=m
176CONFIG_IP_NF_TARGET_MASQUERADE=m
177CONFIG_IP_NF_TARGET_NETMAP=m
178CONFIG_IP_NF_TARGET_REDIRECT=m
179CONFIG_IP_NF_MANGLE=m
180CONFIG_IP_NF_TARGET_CLUSTERIP=m
181CONFIG_IP_NF_TARGET_ECN=m
182CONFIG_IP_NF_TARGET_TTL=m
183CONFIG_IP_NF_RAW=m
184CONFIG_IP_NF_SECURITY=m
185CONFIG_IP_NF_ARPTABLES=m
186CONFIG_IP_NF_ARPFILTER=m
187CONFIG_IP_NF_ARP_MANGLE=m
188CONFIG_NF_CONNTRACK_IPV6=m
189CONFIG_IP6_NF_QUEUE=m
190CONFIG_IP6_NF_IPTABLES=m
191CONFIG_IP6_NF_MATCH_AH=m
192CONFIG_IP6_NF_MATCH_EUI64=m
193CONFIG_IP6_NF_MATCH_FRAG=m
194CONFIG_IP6_NF_MATCH_OPTS=m
195CONFIG_IP6_NF_MATCH_HL=m
196CONFIG_IP6_NF_MATCH_IPV6HEADER=m
197CONFIG_IP6_NF_MATCH_MH=m
198CONFIG_IP6_NF_MATCH_RT=m
199CONFIG_IP6_NF_TARGET_HL=m
200CONFIG_IP6_NF_TARGET_LOG=m
201CONFIG_IP6_NF_FILTER=m
202CONFIG_IP6_NF_TARGET_REJECT=m
203CONFIG_IP6_NF_MANGLE=m
204CONFIG_IP6_NF_RAW=m
205CONFIG_IP6_NF_SECURITY=m
206CONFIG_DECNET_NF_GRABULATOR=m
207CONFIG_BRIDGE_NF_EBTABLES=m
208CONFIG_BRIDGE_EBT_BROUTE=m
209CONFIG_BRIDGE_EBT_T_FILTER=m
210CONFIG_BRIDGE_EBT_T_NAT=m
211CONFIG_BRIDGE_EBT_802_3=m
212CONFIG_BRIDGE_EBT_AMONG=m
213CONFIG_BRIDGE_EBT_ARP=m
214CONFIG_BRIDGE_EBT_IP=m
215CONFIG_BRIDGE_EBT_IP6=m
216CONFIG_BRIDGE_EBT_LIMIT=m
217CONFIG_BRIDGE_EBT_MARK=m
218CONFIG_BRIDGE_EBT_PKTTYPE=m
219CONFIG_BRIDGE_EBT_STP=m
220CONFIG_BRIDGE_EBT_VLAN=m
221CONFIG_BRIDGE_EBT_ARPREPLY=m
222CONFIG_BRIDGE_EBT_DNAT=m
223CONFIG_BRIDGE_EBT_MARK_T=m
224CONFIG_BRIDGE_EBT_REDIRECT=m
225CONFIG_BRIDGE_EBT_SNAT=m
226CONFIG_BRIDGE_EBT_LOG=m
227CONFIG_BRIDGE_EBT_ULOG=m
228CONFIG_BRIDGE_EBT_NFLOG=m
229CONFIG_IP_DCCP=m
230CONFIG_RDS=m
231CONFIG_RDS_TCP=m
232CONFIG_TIPC=m
233CONFIG_ATM=m
234CONFIG_ATM_CLIP=m
235CONFIG_ATM_LANE=m
236CONFIG_ATM_MPOA=m
237CONFIG_ATM_BR2684=m
238CONFIG_BRIDGE=m
239CONFIG_VLAN_8021Q=m
240CONFIG_VLAN_8021Q_GVRP=y
241CONFIG_DECNET=m
242CONFIG_LLC2=m
243CONFIG_IPX=m
244CONFIG_ATALK=m
245CONFIG_DEV_APPLETALK=m
246CONFIG_IPDDP=m
247CONFIG_IPDDP_ENCAP=y
248CONFIG_IPDDP_DECAP=y
249CONFIG_X25=m
250CONFIG_LAPB=m
251CONFIG_ECONET=m
252CONFIG_ECONET_AUNUDP=y
253CONFIG_ECONET_NATIVE=y
254CONFIG_WAN_ROUTER=m
255CONFIG_PHONET=m
256CONFIG_IEEE802154=m
257CONFIG_NET_SCHED=y
258CONFIG_NET_SCH_CBQ=m
259CONFIG_NET_SCH_HTB=m
260CONFIG_NET_SCH_HFSC=m
261CONFIG_NET_SCH_ATM=m
262CONFIG_NET_SCH_PRIO=m
263CONFIG_NET_SCH_MULTIQ=m
264CONFIG_NET_SCH_RED=m
265CONFIG_NET_SCH_SFQ=m
266CONFIG_NET_SCH_TEQL=m
267CONFIG_NET_SCH_TBF=m
268CONFIG_NET_SCH_GRED=m
269CONFIG_NET_SCH_DSMARK=m
270CONFIG_NET_SCH_NETEM=m
271CONFIG_NET_SCH_DRR=m
272CONFIG_NET_SCH_INGRESS=m
273CONFIG_NET_CLS_BASIC=m
274CONFIG_NET_CLS_TCINDEX=m
275CONFIG_NET_CLS_ROUTE4=m
276CONFIG_NET_CLS_FW=m
277CONFIG_NET_CLS_U32=m
278CONFIG_CLS_U32_MARK=y
279CONFIG_NET_CLS_RSVP=m
280CONFIG_NET_CLS_RSVP6=m
281CONFIG_NET_CLS_FLOW=m
282CONFIG_NET_EMATCH=y
283CONFIG_NET_EMATCH_CMP=m
284CONFIG_NET_EMATCH_NBYTE=m
285CONFIG_NET_EMATCH_U32=m
286CONFIG_NET_EMATCH_META=m
287CONFIG_NET_EMATCH_TEXT=m
288CONFIG_NET_CLS_ACT=y
289CONFIG_NET_ACT_POLICE=m
290CONFIG_NET_ACT_GACT=m
291CONFIG_GACT_PROB=y
292CONFIG_NET_ACT_MIRRED=m
293CONFIG_NET_ACT_IPT=m
294CONFIG_NET_ACT_NAT=m
295CONFIG_NET_ACT_PEDIT=m
296CONFIG_NET_ACT_SIMP=m
297CONFIG_NET_ACT_SKBEDIT=m
298CONFIG_DCB=y
299CONFIG_NET_PKTGEN=m
300# CONFIG_WIRELESS is not set
301CONFIG_DEVTMPFS=y
302CONFIG_DEVTMPFS_MOUNT=y
303# CONFIG_STANDALONE is not set
304CONFIG_CONNECTOR=y
305CONFIG_BLK_DEV_LOOP=y
306CONFIG_BLK_DEV_CRYPTOLOOP=m
307CONFIG_BLK_DEV_NBD=m
308CONFIG_BLK_DEV_OSD=m
309CONFIG_BLK_DEV_RAM=y
310CONFIG_BLK_DEV_RAM_SIZE=65536
311CONFIG_CDROM_PKTCDVD=y
312CONFIG_RAID_ATTRS=m
313CONFIG_SCSI=y
314CONFIG_SCSI_TGT=m
315CONFIG_BLK_DEV_SD=y
316CONFIG_CHR_DEV_ST=m
317CONFIG_CHR_DEV_OSST=m
318CONFIG_BLK_DEV_SR=y
319CONFIG_CHR_DEV_SG=y
320CONFIG_CHR_DEV_SCH=m
321CONFIG_SCSI_MULTI_LUN=y
322CONFIG_SCSI_CONSTANTS=y
323CONFIG_SCSI_LOGGING=y
324CONFIG_SCSI_SCAN_ASYNC=y
325CONFIG_SCSI_SPI_ATTRS=m
326CONFIG_SCSI_FC_TGT_ATTRS=y
327CONFIG_SCSI_SAS_LIBSAS=m
328CONFIG_SCSI_SRP_ATTRS=m
329CONFIG_SCSI_SRP_TGT_ATTRS=y
330CONFIG_ISCSI_TCP=m
331CONFIG_LIBFCOE=m
332CONFIG_SCSI_DEBUG=m
333CONFIG_SCSI_DH=y
334CONFIG_SCSI_DH_RDAC=m
335CONFIG_SCSI_DH_HP_SW=m
336CONFIG_SCSI_DH_EMC=m
337CONFIG_SCSI_DH_ALUA=m
338CONFIG_SCSI_OSD_INITIATOR=m
339CONFIG_SCSI_OSD_ULD=m
340# CONFIG_INPUT_MOUSEDEV is not set
341CONFIG_INPUT_EVDEV=y
342CONFIG_INPUT_EVBUG=m
343# CONFIG_INPUT_KEYBOARD is not set
344# CONFIG_INPUT_MOUSE is not set
345# CONFIG_SERIO_I8042 is not set
346CONFIG_SERIO_SERPORT=m
347CONFIG_SERIO_LIBPS2=y
348CONFIG_SERIO_RAW=m
349CONFIG_VT_HW_CONSOLE_BINDING=y
350CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
351CONFIG_LEGACY_PTY_COUNT=0
352CONFIG_SERIAL_NONSTANDARD=y
353CONFIG_N_HDLC=m
354# CONFIG_DEVKMEM is not set
355CONFIG_STALDRV=y
356CONFIG_SERIAL_8250=y
357CONFIG_SERIAL_8250_CONSOLE=y
358CONFIG_SERIAL_8250_NR_UARTS=48
359CONFIG_SERIAL_8250_EXTENDED=y
360CONFIG_SERIAL_8250_MANY_PORTS=y
361CONFIG_SERIAL_8250_SHARE_IRQ=y
362CONFIG_SERIAL_8250_RSA=y
363CONFIG_HW_RANDOM=y
364CONFIG_HW_RANDOM_TIMERIOMEM=m
365CONFIG_RAW_DRIVER=m
366# CONFIG_HWMON is not set
367# CONFIG_VGA_CONSOLE is not set
368# CONFIG_HID_SUPPORT is not set
369# CONFIG_USB_SUPPORT is not set
370CONFIG_UIO=y
371CONFIG_UIO_PDRV=m
372CONFIG_UIO_PDRV_GENIRQ=m
373CONFIG_EXT2_FS=y
374CONFIG_EXT2_FS_XATTR=y
375CONFIG_EXT2_FS_POSIX_ACL=y
376CONFIG_EXT2_FS_SECURITY=y
377CONFIG_EXT3_FS=y
378CONFIG_EXT3_FS_POSIX_ACL=y
379CONFIG_EXT3_FS_SECURITY=y
380CONFIG_EXT4_FS=y
381CONFIG_EXT4_FS_POSIX_ACL=y
382CONFIG_EXT4_FS_SECURITY=y
383CONFIG_GFS2_FS=m
384CONFIG_GFS2_FS_LOCKING_DLM=y
385CONFIG_OCFS2_FS=m
386CONFIG_BTRFS_FS=m
387CONFIG_BTRFS_FS_POSIX_ACL=y
388CONFIG_NILFS2_FS=m
389CONFIG_QUOTA_NETLINK_INTERFACE=y
390# CONFIG_PRINT_QUOTA_WARNING is not set
391CONFIG_QFMT_V1=m
392CONFIG_QFMT_V2=m
393CONFIG_AUTOFS4_FS=m
394CONFIG_FUSE_FS=y
395CONFIG_CUSE=m
396CONFIG_FSCACHE=m
397CONFIG_FSCACHE_STATS=y
398CONFIG_FSCACHE_HISTOGRAM=y
399CONFIG_CACHEFILES=m
400CONFIG_ISO9660_FS=m
401CONFIG_JOLIET=y
402CONFIG_ZISOFS=y
403CONFIG_UDF_FS=m
404CONFIG_MSDOS_FS=m
405CONFIG_VFAT_FS=m
406CONFIG_NTFS_FS=m
407CONFIG_PROC_KCORE=y
408CONFIG_TMPFS=y
409CONFIG_TMPFS_POSIX_ACL=y
410CONFIG_ADFS_FS=m
411CONFIG_AFFS_FS=m
412CONFIG_ECRYPT_FS=y
413CONFIG_HFS_FS=m
414CONFIG_HFSPLUS_FS=m
415CONFIG_BEFS_FS=m
416CONFIG_BFS_FS=m
417CONFIG_EFS_FS=m
418CONFIG_CRAMFS=m
419CONFIG_SQUASHFS=m
420CONFIG_VXFS_FS=m
421CONFIG_MINIX_FS=m
422CONFIG_OMFS_FS=m
423CONFIG_HPFS_FS=m
424CONFIG_QNX4FS_FS=m
425CONFIG_ROMFS_FS=m
426CONFIG_SYSV_FS=m
427CONFIG_UFS_FS=m
428CONFIG_EXOFS_FS=m
429CONFIG_NFS_FS=m
430CONFIG_NFS_V3=y
431CONFIG_NFS_V3_ACL=y
432CONFIG_NFS_V4=y
433CONFIG_NFS_FSCACHE=y
434CONFIG_NFSD=m
435CONFIG_NFSD_V3_ACL=y
436CONFIG_NFSD_V4=y
437CONFIG_CIFS=m
438CONFIG_CIFS_WEAK_PW_HASH=y
439CONFIG_CIFS_UPCALL=y
440CONFIG_CIFS_XATTR=y
441CONFIG_CIFS_POSIX=y
442CONFIG_CIFS_DFS_UPCALL=y
443CONFIG_NCP_FS=m
444CONFIG_NCPFS_PACKET_SIGNING=y
445CONFIG_NCPFS_IOCTL_LOCKING=y
446CONFIG_NCPFS_STRONG=y
447CONFIG_NCPFS_NFS_NS=y
448CONFIG_NCPFS_OS2_NS=y
449CONFIG_NCPFS_NLS=y
450CONFIG_NCPFS_EXTRAS=y
451CONFIG_CODA_FS=m
452CONFIG_AFS_FS=m
453CONFIG_PARTITION_ADVANCED=y
454CONFIG_ACORN_PARTITION=y
455CONFIG_ACORN_PARTITION_ICS=y
456CONFIG_ACORN_PARTITION_RISCIX=y
457CONFIG_OSF_PARTITION=y
458CONFIG_AMIGA_PARTITION=y
459CONFIG_ATARI_PARTITION=y
460CONFIG_MAC_PARTITION=y
461CONFIG_BSD_DISKLABEL=y
462CONFIG_MINIX_SUBPARTITION=y
463CONFIG_SOLARIS_X86_PARTITION=y
464CONFIG_UNIXWARE_DISKLABEL=y
465CONFIG_LDM_PARTITION=y
466CONFIG_SGI_PARTITION=y
467CONFIG_ULTRIX_PARTITION=y
468CONFIG_SUN_PARTITION=y
469CONFIG_KARMA_PARTITION=y
470CONFIG_EFI_PARTITION=y
471CONFIG_SYSV68_PARTITION=y
472CONFIG_NLS=y
473CONFIG_NLS_DEFAULT="cp437"
474CONFIG_NLS_CODEPAGE_437=m
475CONFIG_NLS_CODEPAGE_737=m
476CONFIG_NLS_CODEPAGE_775=m
477CONFIG_NLS_CODEPAGE_850=m
478CONFIG_NLS_CODEPAGE_852=m
479CONFIG_NLS_CODEPAGE_855=m
480CONFIG_NLS_CODEPAGE_857=m
481CONFIG_NLS_CODEPAGE_860=m
482CONFIG_NLS_CODEPAGE_861=m
483CONFIG_NLS_CODEPAGE_862=m
484CONFIG_NLS_CODEPAGE_863=m
485CONFIG_NLS_CODEPAGE_864=m
486CONFIG_NLS_CODEPAGE_865=m
487CONFIG_NLS_CODEPAGE_866=m
488CONFIG_NLS_CODEPAGE_869=m
489CONFIG_NLS_CODEPAGE_936=m
490CONFIG_NLS_CODEPAGE_950=m
491CONFIG_NLS_CODEPAGE_932=m
492CONFIG_NLS_CODEPAGE_949=m
493CONFIG_NLS_CODEPAGE_874=m
494CONFIG_NLS_ISO8859_8=m
495CONFIG_NLS_CODEPAGE_1250=m
496CONFIG_NLS_CODEPAGE_1251=m
497CONFIG_NLS_ASCII=m
498CONFIG_NLS_ISO8859_1=m
499CONFIG_NLS_ISO8859_2=m
500CONFIG_NLS_ISO8859_3=m
501CONFIG_NLS_ISO8859_4=m
502CONFIG_NLS_ISO8859_5=m
503CONFIG_NLS_ISO8859_6=m
504CONFIG_NLS_ISO8859_7=m
505CONFIG_NLS_ISO8859_9=m
506CONFIG_NLS_ISO8859_13=m
507CONFIG_NLS_ISO8859_14=m
508CONFIG_NLS_ISO8859_15=m
509CONFIG_NLS_KOI8_R=m
510CONFIG_NLS_KOI8_U=m
511CONFIG_PRINTK_TIME=y
512# CONFIG_ENABLE_WARN_DEPRECATED is not set
513# CONFIG_ENABLE_MUST_CHECK is not set
514CONFIG_FRAME_WARN=1024
515CONFIG_UNUSED_SYMBOLS=y
516CONFIG_DETECT_HUNG_TASK=y
517CONFIG_SCHEDSTATS=y
518CONFIG_TIMER_STATS=y
519CONFIG_DEBUG_INFO=y
520CONFIG_DEBUG_MEMORY_INIT=y
521CONFIG_SYSCTL_SYSCALL_CHECK=y
522CONFIG_SCHED_TRACER=y
523CONFIG_BLK_DEV_IO_TRACE=y
524CONFIG_KGDB=y
525CONFIG_SECURITY=y
526CONFIG_SECURITY_NETWORK=y
527CONFIG_LSM_MMAP_MIN_ADDR=0
528CONFIG_SECURITY_SELINUX=y
529CONFIG_SECURITY_SELINUX_BOOTPARAM=y
530CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=0
531CONFIG_SECURITY_SELINUX_DISABLE=y
532CONFIG_SECURITY_SMACK=y
533CONFIG_SECURITY_TOMOYO=y
534CONFIG_CRYPTO_NULL=m
535CONFIG_CRYPTO_CRYPTD=m
536CONFIG_CRYPTO_TEST=m
537CONFIG_CRYPTO_CCM=m
538CONFIG_CRYPTO_GCM=m
539CONFIG_CRYPTO_CTS=m
540CONFIG_CRYPTO_LRW=m
541CONFIG_CRYPTO_PCBC=m
542CONFIG_CRYPTO_XTS=m
543CONFIG_CRYPTO_HMAC=y
544CONFIG_CRYPTO_XCBC=m
545CONFIG_CRYPTO_VMAC=m
546CONFIG_CRYPTO_MICHAEL_MIC=m
547CONFIG_CRYPTO_RMD128=m
548CONFIG_CRYPTO_RMD160=m
549CONFIG_CRYPTO_RMD256=m
550CONFIG_CRYPTO_RMD320=m
551CONFIG_CRYPTO_SHA256=m
552CONFIG_CRYPTO_SHA512=m
553CONFIG_CRYPTO_TGR192=m
554CONFIG_CRYPTO_WP512=m
555CONFIG_CRYPTO_ANUBIS=m
556CONFIG_CRYPTO_BLOWFISH=m
557CONFIG_CRYPTO_CAMELLIA=m
558CONFIG_CRYPTO_CAST5=m
559CONFIG_CRYPTO_CAST6=m
560CONFIG_CRYPTO_FCRYPT=m
561CONFIG_CRYPTO_KHAZAD=m
562CONFIG_CRYPTO_SALSA20=m
563CONFIG_CRYPTO_SEED=m
564CONFIG_CRYPTO_SERPENT=m
565CONFIG_CRYPTO_TEA=m
566CONFIG_CRYPTO_TWOFISH=m
567CONFIG_CRYPTO_ZLIB=m
568CONFIG_CRYPTO_LZO=m
569CONFIG_CRC_CCITT=m
570CONFIG_CRC7=m
diff --git a/arch/mips/configs/nlm_xlr_defconfig b/arch/mips/configs/nlm_xlr_defconfig
index e4b399fdaa61..7c68666fdd64 100644
--- a/arch/mips/configs/nlm_xlr_defconfig
+++ b/arch/mips/configs/nlm_xlr_defconfig
@@ -8,7 +8,7 @@ CONFIG_HIGH_RES_TIMERS=y
8CONFIG_PREEMPT_VOLUNTARY=y 8CONFIG_PREEMPT_VOLUNTARY=y
9CONFIG_KEXEC=y 9CONFIG_KEXEC=y
10CONFIG_EXPERIMENTAL=y 10CONFIG_EXPERIMENTAL=y
11CONFIG_CROSS_COMPILE="mips64-unknown-linux-gnu-" 11CONFIG_CROSS_COMPILE="mips-linux-gnu-"
12# CONFIG_LOCALVERSION_AUTO is not set 12# CONFIG_LOCALVERSION_AUTO is not set
13CONFIG_SYSVIPC=y 13CONFIG_SYSVIPC=y
14CONFIG_POSIX_MQUEUE=y 14CONFIG_POSIX_MQUEUE=y
@@ -22,15 +22,13 @@ CONFIG_AUDIT=y
22CONFIG_NAMESPACES=y 22CONFIG_NAMESPACES=y
23CONFIG_SCHED_AUTOGROUP=y 23CONFIG_SCHED_AUTOGROUP=y
24CONFIG_BLK_DEV_INITRD=y 24CONFIG_BLK_DEV_INITRD=y
25CONFIG_INITRAMFS_SOURCE="usr/dev_file_list usr/rootfs" 25CONFIG_INITRAMFS_SOURCE="usr/dev_file_list usr/rootfs.xlr"
26CONFIG_RD_BZIP2=y 26CONFIG_RD_BZIP2=y
27CONFIG_RD_LZMA=y 27CONFIG_RD_LZMA=y
28CONFIG_INITRAMFS_COMPRESSION_GZIP=y 28CONFIG_INITRAMFS_COMPRESSION_GZIP=y
29# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
30CONFIG_EXPERT=y 29CONFIG_EXPERT=y
31CONFIG_KALLSYMS_ALL=y 30CONFIG_KALLSYMS_ALL=y
32# CONFIG_ELF_CORE is not set 31# CONFIG_ELF_CORE is not set
33# CONFIG_PCSPKR_PLATFORM is not set
34# CONFIG_PERF_EVENTS is not set 32# CONFIG_PERF_EVENTS is not set
35# CONFIG_COMPAT_BRK is not set 33# CONFIG_COMPAT_BRK is not set
36CONFIG_PROFILING=y 34CONFIG_PROFILING=y
@@ -39,6 +37,9 @@ CONFIG_MODULE_UNLOAD=y
39CONFIG_MODVERSIONS=y 37CONFIG_MODVERSIONS=y
40CONFIG_MODULE_SRCVERSION_ALL=y 38CONFIG_MODULE_SRCVERSION_ALL=y
41CONFIG_BLK_DEV_INTEGRITY=y 39CONFIG_BLK_DEV_INTEGRITY=y
40CONFIG_PCI=y
41CONFIG_PCI_MSI=y
42CONFIG_PCI_DEBUG=y
42CONFIG_BINFMT_MISC=m 43CONFIG_BINFMT_MISC=m
43CONFIG_PM_RUNTIME=y 44CONFIG_PM_RUNTIME=y
44CONFIG_PM_DEBUG=y 45CONFIG_PM_DEBUG=y
@@ -297,12 +298,10 @@ CONFIG_NET_ACT_SIMP=m
297CONFIG_NET_ACT_SKBEDIT=m 298CONFIG_NET_ACT_SKBEDIT=m
298CONFIG_DCB=y 299CONFIG_DCB=y
299CONFIG_NET_PKTGEN=m 300CONFIG_NET_PKTGEN=m
300# CONFIG_WIRELESS is not set
301CONFIG_DEVTMPFS=y 301CONFIG_DEVTMPFS=y
302CONFIG_DEVTMPFS_MOUNT=y 302CONFIG_DEVTMPFS_MOUNT=y
303# CONFIG_STANDALONE is not set 303# CONFIG_STANDALONE is not set
304CONFIG_CONNECTOR=y 304CONFIG_CONNECTOR=y
305CONFIG_MTD=m
306CONFIG_BLK_DEV_LOOP=y 305CONFIG_BLK_DEV_LOOP=y
307CONFIG_BLK_DEV_CRYPTOLOOP=m 306CONFIG_BLK_DEV_CRYPTOLOOP=m
308CONFIG_BLK_DEV_NBD=m 307CONFIG_BLK_DEV_NBD=m
@@ -339,6 +338,9 @@ CONFIG_SCSI_DH_EMC=m
339CONFIG_SCSI_DH_ALUA=m 338CONFIG_SCSI_DH_ALUA=m
340CONFIG_SCSI_OSD_INITIATOR=m 339CONFIG_SCSI_OSD_INITIATOR=m
341CONFIG_SCSI_OSD_ULD=m 340CONFIG_SCSI_OSD_ULD=m
341CONFIG_NETDEVICES=y
342CONFIG_E1000E=y
343CONFIG_SKY2=y
342# CONFIG_INPUT_MOUSEDEV is not set 344# CONFIG_INPUT_MOUSEDEV is not set
343CONFIG_INPUT_EVDEV=y 345CONFIG_INPUT_EVDEV=y
344CONFIG_INPUT_EVBUG=m 346CONFIG_INPUT_EVBUG=m
@@ -443,7 +445,6 @@ CONFIG_CIFS_UPCALL=y
443CONFIG_CIFS_XATTR=y 445CONFIG_CIFS_XATTR=y
444CONFIG_CIFS_POSIX=y 446CONFIG_CIFS_POSIX=y
445CONFIG_CIFS_DFS_UPCALL=y 447CONFIG_CIFS_DFS_UPCALL=y
446CONFIG_CIFS_EXPERIMENTAL=y
447CONFIG_NCP_FS=m 448CONFIG_NCP_FS=m
448CONFIG_NCPFS_PACKET_SIGNING=y 449CONFIG_NCPFS_PACKET_SIGNING=y
449CONFIG_NCPFS_IOCTL_LOCKING=y 450CONFIG_NCPFS_IOCTL_LOCKING=y
@@ -516,7 +517,6 @@ CONFIG_PRINTK_TIME=y
516# CONFIG_ENABLE_WARN_DEPRECATED is not set 517# CONFIG_ENABLE_WARN_DEPRECATED is not set
517# CONFIG_ENABLE_MUST_CHECK is not set 518# CONFIG_ENABLE_MUST_CHECK is not set
518CONFIG_UNUSED_SYMBOLS=y 519CONFIG_UNUSED_SYMBOLS=y
519CONFIG_DEBUG_KERNEL=y
520CONFIG_DETECT_HUNG_TASK=y 520CONFIG_DETECT_HUNG_TASK=y
521CONFIG_SCHEDSTATS=y 521CONFIG_SCHEDSTATS=y
522CONFIG_TIMER_STATS=y 522CONFIG_TIMER_STATS=y
diff --git a/arch/mips/configs/pb1200_defconfig b/arch/mips/configs/pb1200_defconfig
deleted file mode 100644
index dcbe2704e5ed..000000000000
--- a/arch/mips/configs/pb1200_defconfig
+++ /dev/null
@@ -1,170 +0,0 @@
1CONFIG_MIPS_ALCHEMY=y
2CONFIG_MIPS_PB1200=y
3CONFIG_KSM=y
4CONFIG_NO_HZ=y
5CONFIG_HIGH_RES_TIMERS=y
6CONFIG_HZ_100=y
7# CONFIG_SECCOMP is not set
8CONFIG_EXPERIMENTAL=y
9CONFIG_LOCALVERSION="-pb1200"
10CONFIG_KERNEL_LZMA=y
11CONFIG_SYSVIPC=y
12CONFIG_POSIX_MQUEUE=y
13CONFIG_TINY_RCU=y
14CONFIG_LOG_BUF_SHIFT=14
15CONFIG_EXPERT=y
16# CONFIG_SYSCTL_SYSCALL is not set
17# CONFIG_KALLSYMS is not set
18# CONFIG_PCSPKR_PLATFORM is not set
19# CONFIG_VM_EVENT_COUNTERS is not set
20# CONFIG_COMPAT_BRK is not set
21CONFIG_SLAB=y
22CONFIG_MODULES=y
23CONFIG_MODULE_UNLOAD=y
24# CONFIG_LBDAF is not set
25# CONFIG_BLK_DEV_BSG is not set
26# CONFIG_IOSCHED_DEADLINE is not set
27# CONFIG_IOSCHED_CFQ is not set
28CONFIG_PCCARD=y
29CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y
30CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
31CONFIG_BINFMT_MISC=y
32CONFIG_NET=y
33CONFIG_PACKET=y
34CONFIG_UNIX=y
35CONFIG_INET=y
36CONFIG_IP_MULTICAST=y
37CONFIG_IP_PNP=y
38# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
39# CONFIG_INET_XFRM_MODE_TUNNEL is not set
40# CONFIG_INET_XFRM_MODE_BEET is not set
41# CONFIG_INET_DIAG is not set
42# CONFIG_IPV6 is not set
43# CONFIG_WIRELESS is not set
44CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
45CONFIG_MTD=y
46CONFIG_MTD_PARTITIONS=y
47CONFIG_MTD_CMDLINE_PARTS=y
48CONFIG_MTD_CHAR=y
49CONFIG_MTD_BLOCK=y
50CONFIG_MTD_CFI=y
51CONFIG_MTD_CFI_AMDSTD=y
52CONFIG_MTD_PHYSMAP=y
53CONFIG_MTD_NAND=y
54CONFIG_MTD_NAND_PLATFORM=y
55CONFIG_BLK_DEV_LOOP=y
56CONFIG_BLK_DEV_UB=y
57# CONFIG_MISC_DEVICES is not set
58CONFIG_IDE=y
59CONFIG_BLK_DEV_IDECS=y
60CONFIG_BLK_DEV_IDECD=y
61CONFIG_IDE_TASK_IOCTL=y
62# CONFIG_IDE_PROC_FS is not set
63CONFIG_BLK_DEV_IDE_AU1XXX=y
64CONFIG_NETDEVICES=y
65CONFIG_NET_ETHERNET=y
66CONFIG_SMC91X=y
67# CONFIG_NETDEV_1000 is not set
68# CONFIG_NETDEV_10000 is not set
69# CONFIG_WLAN is not set
70# CONFIG_INPUT_MOUSEDEV is not set
71CONFIG_INPUT_EVDEV=y
72# CONFIG_INPUT_KEYBOARD is not set
73# CONFIG_INPUT_MOUSE is not set
74# CONFIG_SERIO is not set
75CONFIG_VT_HW_CONSOLE_BINDING=y
76CONFIG_SERIAL_8250=y
77CONFIG_SERIAL_8250_CONSOLE=y
78CONFIG_SERIAL_8250_NR_UARTS=2
79CONFIG_SERIAL_8250_RUNTIME_UARTS=2
80# CONFIG_LEGACY_PTYS is not set
81# CONFIG_HW_RANDOM is not set
82CONFIG_I2C=y
83# CONFIG_I2C_COMPAT is not set
84CONFIG_I2C_CHARDEV=y
85# CONFIG_I2C_HELPER_AUTO is not set
86CONFIG_I2C_AU1550=y
87CONFIG_SPI=y
88CONFIG_SPI_AU1550=y
89CONFIG_GPIOLIB=y
90CONFIG_GPIO_SYSFS=y
91CONFIG_SENSORS_ADM1025=y
92CONFIG_SENSORS_LM70=y
93CONFIG_FB=y
94CONFIG_FB_AU1200=y
95# CONFIG_VGA_CONSOLE is not set
96CONFIG_FRAMEBUFFER_CONSOLE=y
97CONFIG_FONTS=y
98CONFIG_FONT_8x16=y
99CONFIG_SOUND=y
100CONFIG_SND=y
101CONFIG_SND_DYNAMIC_MINORS=y
102# CONFIG_SND_SUPPORT_OLD_API is not set
103# CONFIG_SND_VERBOSE_PROCFS is not set
104# CONFIG_SND_DRIVERS is not set
105# CONFIG_SND_SPI is not set
106# CONFIG_SND_MIPS is not set
107# CONFIG_SND_USB is not set
108# CONFIG_SND_PCMCIA is not set
109CONFIG_SND_SOC=y
110CONFIG_SND_SOC_AU1XPSC=y
111CONFIG_SND_SOC_DB1200=y
112CONFIG_HIDRAW=y
113CONFIG_USB_HIDDEV=y
114CONFIG_USB=y
115CONFIG_USB_DEBUG=y
116CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
117# CONFIG_USB_DEVICE_CLASS is not set
118CONFIG_USB_DYNAMIC_MINORS=y
119CONFIG_USB_EHCI_HCD=y
120CONFIG_USB_EHCI_ROOT_HUB_TT=y
121CONFIG_USB_OHCI_HCD=y
122CONFIG_MMC=y
123# CONFIG_MMC_BLOCK_BOUNCE is not set
124CONFIG_MMC_AU1X=y
125CONFIG_NEW_LEDS=y
126CONFIG_LEDS_CLASS=y
127CONFIG_LEDS_TRIGGERS=y
128CONFIG_RTC_CLASS=y
129CONFIG_RTC_DRV_AU1XXX=y
130CONFIG_EXT2_FS=y
131CONFIG_ISO9660_FS=y
132CONFIG_JOLIET=y
133CONFIG_ZISOFS=y
134CONFIG_UDF_FS=y
135CONFIG_VFAT_FS=y
136# CONFIG_PROC_PAGE_MONITOR is not set
137CONFIG_TMPFS=y
138CONFIG_JFFS2_FS=y
139CONFIG_JFFS2_SUMMARY=y
140CONFIG_JFFS2_COMPRESSION_OPTIONS=y
141CONFIG_JFFS2_LZO=y
142CONFIG_JFFS2_RUBIN=y
143CONFIG_SQUASHFS=y
144CONFIG_NFS_FS=y
145CONFIG_NFS_V3=y
146CONFIG_ROOT_NFS=y
147CONFIG_PARTITION_ADVANCED=y
148CONFIG_EFI_PARTITION=y
149CONFIG_NLS_CODEPAGE_437=y
150CONFIG_NLS_CODEPAGE_850=y
151CONFIG_NLS_CODEPAGE_852=y
152CONFIG_NLS_CODEPAGE_1250=y
153CONFIG_NLS_ASCII=y
154CONFIG_NLS_ISO8859_1=y
155CONFIG_NLS_ISO8859_2=y
156CONFIG_NLS_ISO8859_15=y
157CONFIG_NLS_UTF8=y
158# CONFIG_ENABLE_WARN_DEPRECATED is not set
159# CONFIG_ENABLE_MUST_CHECK is not set
160CONFIG_MAGIC_SYSRQ=y
161CONFIG_STRIP_ASM_SYMS=y
162CONFIG_DEBUG_KERNEL=y
163# CONFIG_SCHED_DEBUG is not set
164# CONFIG_FTRACE is not set
165CONFIG_CMDLINE_BOOL=y
166CONFIG_CMDLINE="console=ttyS0,115200"
167CONFIG_DEBUG_ZBOOT=y
168CONFIG_KEYS=y
169CONFIG_KEYS_DEBUG_PROC_KEYS=y
170CONFIG_SECURITYFS=y
diff --git a/arch/mips/dec/setup.c b/arch/mips/dec/setup.c
index f7b7ba6d5c45..b874accd878a 100644
--- a/arch/mips/dec/setup.c
+++ b/arch/mips/dec/setup.c
@@ -110,7 +110,6 @@ static struct irqaction fpuirq = {
110}; 110};
111 111
112static struct irqaction busirq = { 112static struct irqaction busirq = {
113 .flags = IRQF_DISABLED,
114 .name = "bus error", 113 .name = "bus error",
115 .flags = IRQF_NO_THREAD, 114 .flags = IRQF_NO_THREAD,
116}; 115};
diff --git a/arch/mips/include/asm/bmips.h b/arch/mips/include/asm/bmips.h
new file mode 100644
index 000000000000..552a65a0cf2b
--- /dev/null
+++ b/arch/mips/include/asm/bmips.h
@@ -0,0 +1,110 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
7 *
8 * Definitions for BMIPS processors
9 */
10#ifndef _ASM_BMIPS_H
11#define _ASM_BMIPS_H
12
13#include <linux/compiler.h>
14#include <linux/linkage.h>
15#include <asm/addrspace.h>
16#include <asm/mipsregs.h>
17#include <asm/hazards.h>
18
19/* NOTE: the CBR register returns a PA, and it can be above 0xff00_0000 */
20#define BMIPS_GET_CBR() ((void __iomem *)(CKSEG1 | \
21 (unsigned long) \
22 ((read_c0_brcm_cbr() >> 18) << 18)))
23
24#define BMIPS_RAC_CONFIG 0x00000000
25#define BMIPS_RAC_ADDRESS_RANGE 0x00000004
26#define BMIPS_RAC_CONFIG_1 0x00000008
27#define BMIPS_L2_CONFIG 0x0000000c
28#define BMIPS_LMB_CONTROL 0x0000001c
29#define BMIPS_SYSTEM_BASE 0x00000020
30#define BMIPS_PERF_GLOBAL_CONTROL 0x00020000
31#define BMIPS_PERF_CONTROL_0 0x00020004
32#define BMIPS_PERF_CONTROL_1 0x00020008
33#define BMIPS_PERF_COUNTER_0 0x00020010
34#define BMIPS_PERF_COUNTER_1 0x00020014
35#define BMIPS_PERF_COUNTER_2 0x00020018
36#define BMIPS_PERF_COUNTER_3 0x0002001c
37#define BMIPS_RELO_VECTOR_CONTROL_0 0x00030000
38#define BMIPS_RELO_VECTOR_CONTROL_1 0x00038000
39
40#define BMIPS_NMI_RESET_VEC 0x80000000
41#define BMIPS_WARM_RESTART_VEC 0x80000380
42
43#define ZSCM_REG_BASE 0x97000000
44
45#if !defined(__ASSEMBLY__)
46
47#include <linux/cpumask.h>
48#include <asm/r4kcache.h>
49
50extern struct plat_smp_ops bmips_smp_ops;
51extern char bmips_reset_nmi_vec;
52extern char bmips_reset_nmi_vec_end;
53extern char bmips_smp_movevec;
54extern char bmips_smp_int_vec;
55extern char bmips_smp_int_vec_end;
56
57extern int bmips_smp_enabled;
58extern int bmips_cpu_offset;
59extern cpumask_t bmips_booted_mask;
60
61extern void bmips_ebase_setup(void);
62extern asmlinkage void plat_wired_tlb_setup(void);
63
64static inline unsigned long bmips_read_zscm_reg(unsigned int offset)
65{
66 unsigned long ret;
67
68 __asm__ __volatile__(
69 ".set push\n"
70 ".set noreorder\n"
71 "cache %1, 0(%2)\n"
72 "sync\n"
73 "_ssnop\n"
74 "_ssnop\n"
75 "_ssnop\n"
76 "_ssnop\n"
77 "_ssnop\n"
78 "_ssnop\n"
79 "_ssnop\n"
80 "mfc0 %0, $28, 3\n"
81 "_ssnop\n"
82 ".set pop\n"
83 : "=&r" (ret)
84 : "i" (Index_Load_Tag_S), "r" (ZSCM_REG_BASE + offset)
85 : "memory");
86 return ret;
87}
88
89static inline void bmips_write_zscm_reg(unsigned int offset, unsigned long data)
90{
91 __asm__ __volatile__(
92 ".set push\n"
93 ".set noreorder\n"
94 "mtc0 %0, $28, 3\n"
95 "_ssnop\n"
96 "_ssnop\n"
97 "_ssnop\n"
98 "cache %1, 0(%2)\n"
99 "_ssnop\n"
100 "_ssnop\n"
101 "_ssnop\n"
102 : /* no outputs */
103 : "r" (data),
104 "i" (Index_Store_Tag_S), "r" (ZSCM_REG_BASE + offset)
105 : "memory");
106}
107
108#endif /* !defined(__ASSEMBLY__) */
109
110#endif /* _ASM_BMIPS_H */
diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h
index 35cd1bab69c3..7a51d879e6ca 100644
--- a/arch/mips/include/asm/bootinfo.h
+++ b/arch/mips/include/asm/bootinfo.h
@@ -86,6 +86,7 @@ extern unsigned long mips_machtype;
86#define BOOT_MEM_RAM 1 86#define BOOT_MEM_RAM 1
87#define BOOT_MEM_ROM_DATA 2 87#define BOOT_MEM_ROM_DATA 2
88#define BOOT_MEM_RESERVED 3 88#define BOOT_MEM_RESERVED 3
89#define BOOT_MEM_INIT_RAM 4
89 90
90/* 91/*
91 * A memory map that's built upon what was determined 92 * A memory map that's built upon what was determined
diff --git a/arch/mips/include/asm/branch.h b/arch/mips/include/asm/branch.h
index 37c6857c8d4a..888766ae1f85 100644
--- a/arch/mips/include/asm/branch.h
+++ b/arch/mips/include/asm/branch.h
@@ -9,6 +9,7 @@
9#define _ASM_BRANCH_H 9#define _ASM_BRANCH_H
10 10
11#include <asm/ptrace.h> 11#include <asm/ptrace.h>
12#include <asm/inst.h>
12 13
13static inline int delay_slot(struct pt_regs *regs) 14static inline int delay_slot(struct pt_regs *regs)
14{ 15{
@@ -23,7 +24,11 @@ static inline unsigned long exception_epc(struct pt_regs *regs)
23 return regs->cp0_epc + 4; 24 return regs->cp0_epc + 4;
24} 25}
25 26
27#define BRANCH_LIKELY_TAKEN 0x0001
28
26extern int __compute_return_epc(struct pt_regs *regs); 29extern int __compute_return_epc(struct pt_regs *regs);
30extern int __compute_return_epc_for_insn(struct pt_regs *regs,
31 union mips_instruction insn);
27 32
28static inline int compute_return_epc(struct pt_regs *regs) 33static inline int compute_return_epc(struct pt_regs *regs)
29{ 34{
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 2f7f41873f24..f9fa2a479dd0 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -169,6 +169,10 @@
169#define PRID_IMP_NETLOGIC_XLS412B 0x4c00 169#define PRID_IMP_NETLOGIC_XLS412B 0x4c00
170#define PRID_IMP_NETLOGIC_XLS408B 0x4e00 170#define PRID_IMP_NETLOGIC_XLS408B 0x4e00
171#define PRID_IMP_NETLOGIC_XLS404B 0x4f00 171#define PRID_IMP_NETLOGIC_XLS404B 0x4f00
172#define PRID_IMP_NETLOGIC_AU13XX 0x8000
173
174#define PRID_IMP_NETLOGIC_XLP8XX 0x1000
175#define PRID_IMP_NETLOGIC_XLP3XX 0x1100
172 176
173/* 177/*
174 * Definitions for 7:0 on legacy processors 178 * Definitions for 7:0 on legacy processors
@@ -263,7 +267,7 @@ enum cpu_type_enum {
263 */ 267 */
264 CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, 268 CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
265 CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2, 269 CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2,
266 CPU_XLR, 270 CPU_XLR, CPU_XLP,
267 271
268 CPU_LAST 272 CPU_LAST
269}; 273};
diff --git a/arch/mips/include/asm/gio_device.h b/arch/mips/include/asm/gio_device.h
new file mode 100644
index 000000000000..5437c84664bf
--- /dev/null
+++ b/arch/mips/include/asm/gio_device.h
@@ -0,0 +1,56 @@
1#include <linux/device.h>
2#include <linux/mod_devicetable.h>
3
4struct gio_device_id {
5 __u8 id;
6};
7
8struct gio_device {
9 struct device dev;
10 struct resource resource;
11 unsigned int irq;
12 unsigned int slotno;
13
14 const char *name;
15 struct gio_device_id id;
16 unsigned id32:1;
17 unsigned gio64:1;
18};
19#define to_gio_device(d) container_of(d, struct gio_device, dev)
20
21struct gio_driver {
22 const char *name;
23 struct module *owner;
24 const struct gio_device_id *id_table;
25
26 int (*probe)(struct gio_device *, const struct gio_device_id *);
27 void (*remove)(struct gio_device *);
28 int (*suspend)(struct gio_device *, pm_message_t);
29 int (*resume)(struct gio_device *);
30 void (*shutdown)(struct gio_device *);
31
32 struct device_driver driver;
33};
34#define to_gio_driver(drv) container_of(drv, struct gio_driver, driver)
35
36extern const struct gio_device_id *gio_match_device(const struct gio_device_id *,
37 const struct gio_device *);
38extern struct gio_device *gio_dev_get(struct gio_device *);
39extern void gio_dev_put(struct gio_device *);
40
41extern int gio_device_register(struct gio_device *);
42extern void gio_device_unregister(struct gio_device *);
43extern void gio_release_dev(struct device *);
44
45static inline void gio_device_free(struct gio_device *dev)
46{
47 gio_release_dev(&dev->dev);
48}
49
50extern int gio_register_driver(struct gio_driver *);
51extern void gio_unregister_driver(struct gio_driver *);
52
53#define gio_get_drvdata(_dev) drv_get_drvdata(&(_dev)->dev)
54#define gio_set_drvdata(_dev, data) drv_set_drvdata(&(_dev)->dev, (data))
55
56extern void gio_set_master(struct gio_device *);
diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h
index 4e332165d7b7..b4c20e4f87cd 100644
--- a/arch/mips/include/asm/hazards.h
+++ b/arch/mips/include/asm/hazards.h
@@ -87,7 +87,8 @@ do { \
87 : "=r" (tmp)); \ 87 : "=r" (tmp)); \
88} while (0) 88} while (0)
89 89
90#elif defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MIPS_ALCHEMY) 90#elif (defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MIPS_ALCHEMY)) || \
91 defined(CONFIG_CPU_BMIPS)
91 92
92/* 93/*
93 * These are slightly complicated by the fact that we guarantee R1 kernels to 94 * These are slightly complicated by the fact that we guarantee R1 kernels to
@@ -139,8 +140,8 @@ do { \
139} while (0) 140} while (0)
140 141
141#elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \ 142#elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
142 defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \ 143 defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \
143 defined(CONFIG_CPU_R5500) 144 defined(CONFIG_CPU_R5500)
144 145
145/* 146/*
146 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. 147 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
diff --git a/arch/mips/include/asm/hugetlb.h b/arch/mips/include/asm/hugetlb.h
index c565b7c3f0b5..58d36889f09b 100644
--- a/arch/mips/include/asm/hugetlb.h
+++ b/arch/mips/include/asm/hugetlb.h
@@ -70,7 +70,7 @@ static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
70static inline void huge_ptep_clear_flush(struct vm_area_struct *vma, 70static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
71 unsigned long addr, pte_t *ptep) 71 unsigned long addr, pte_t *ptep)
72{ 72{
73 flush_tlb_mm(vma->vm_mm); 73 flush_tlb_page(vma, addr & huge_page_mask(hstate_vma(vma)));
74} 74}
75 75
76static inline int huge_pte_none(pte_t pte) 76static inline int huge_pte_none(pte_t pte)
diff --git a/arch/mips/include/asm/kprobes.h b/arch/mips/include/asm/kprobes.h
index e6ea4d4d7205..1fbbca01e681 100644
--- a/arch/mips/include/asm/kprobes.h
+++ b/arch/mips/include/asm/kprobes.h
@@ -74,6 +74,8 @@ struct prev_kprobe {
74 : MAX_JPROBES_STACK_SIZE) 74 : MAX_JPROBES_STACK_SIZE)
75 75
76 76
77#define SKIP_DELAYSLOT 0x0001
78
77/* per-cpu kprobe control block */ 79/* per-cpu kprobe control block */
78struct kprobe_ctlblk { 80struct kprobe_ctlblk {
79 unsigned long kprobe_status; 81 unsigned long kprobe_status;
@@ -82,6 +84,9 @@ struct kprobe_ctlblk {
82 unsigned long kprobe_saved_epc; 84 unsigned long kprobe_saved_epc;
83 unsigned long jprobe_saved_sp; 85 unsigned long jprobe_saved_sp;
84 struct pt_regs jprobe_saved_regs; 86 struct pt_regs jprobe_saved_regs;
87 /* Per-thread fields, used while emulating branches */
88 unsigned long flags;
89 unsigned long target_epc;
85 u8 jprobes_stack[MAX_JPROBES_STACK_SIZE]; 90 u8 jprobes_stack[MAX_JPROBES_STACK_SIZE];
86 struct prev_kprobe prev_kprobe; 91 struct prev_kprobe prev_kprobe;
87}; 92};
diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
index cda1c8070b27..2f0becb4ec8f 100644
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -20,6 +20,10 @@
20#include <linux/bitops.h> 20#include <linux/bitops.h>
21 21
22#define AR71XX_APB_BASE 0x18000000 22#define AR71XX_APB_BASE 0x18000000
23#define AR71XX_EHCI_BASE 0x1b000000
24#define AR71XX_EHCI_SIZE 0x1000
25#define AR71XX_OHCI_BASE 0x1c000000
26#define AR71XX_OHCI_SIZE 0x1000
23#define AR71XX_SPI_BASE 0x1f000000 27#define AR71XX_SPI_BASE 0x1f000000
24#define AR71XX_SPI_SIZE 0x01000000 28#define AR71XX_SPI_SIZE 0x01000000
25 29
@@ -27,6 +31,8 @@
27#define AR71XX_DDR_CTRL_SIZE 0x100 31#define AR71XX_DDR_CTRL_SIZE 0x100
28#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000) 32#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000)
29#define AR71XX_UART_SIZE 0x100 33#define AR71XX_UART_SIZE 0x100
34#define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
35#define AR71XX_USB_CTRL_SIZE 0x100
30#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000) 36#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000)
31#define AR71XX_GPIO_SIZE 0x100 37#define AR71XX_GPIO_SIZE 0x100
32#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000) 38#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
@@ -34,9 +40,26 @@
34#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) 40#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
35#define AR71XX_RESET_SIZE 0x100 41#define AR71XX_RESET_SIZE 0x100
36 42
43#define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
44#define AR7240_USB_CTRL_SIZE 0x100
45#define AR7240_OHCI_BASE 0x1b000000
46#define AR7240_OHCI_SIZE 0x1000
47
48#define AR724X_EHCI_BASE 0x1b000000
49#define AR724X_EHCI_SIZE 0x1000
50
51#define AR913X_EHCI_BASE 0x1b000000
52#define AR913X_EHCI_SIZE 0x1000
37#define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000) 53#define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)
38#define AR913X_WMAC_SIZE 0x30000 54#define AR913X_WMAC_SIZE 0x30000
39 55
56#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
57#define AR933X_UART_SIZE 0x14
58#define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
59#define AR933X_WMAC_SIZE 0x20000
60#define AR933X_EHCI_BASE 0x1b000000
61#define AR933X_EHCI_SIZE 0x1000
62
40/* 63/*
41 * DDR_CTRL block 64 * DDR_CTRL block
42 */ 65 */
@@ -63,6 +86,11 @@
63#define AR913X_DDR_REG_FLUSH_USB 0x84 86#define AR913X_DDR_REG_FLUSH_USB 0x84
64#define AR913X_DDR_REG_FLUSH_WMAC 0x88 87#define AR913X_DDR_REG_FLUSH_WMAC 0x88
65 88
89#define AR933X_DDR_REG_FLUSH_GE0 0x7c
90#define AR933X_DDR_REG_FLUSH_GE1 0x80
91#define AR933X_DDR_REG_FLUSH_USB 0x84
92#define AR933X_DDR_REG_FLUSH_WMAC 0x88
93
66/* 94/*
67 * PLL block 95 * PLL block
68 */ 96 */
@@ -104,6 +132,30 @@
104#define AR913X_AHB_DIV_SHIFT 19 132#define AR913X_AHB_DIV_SHIFT 19
105#define AR913X_AHB_DIV_MASK 0x1 133#define AR913X_AHB_DIV_MASK 0x1
106 134
135#define AR933X_PLL_CPU_CONFIG_REG 0x00
136#define AR933X_PLL_CLOCK_CTRL_REG 0x08
137
138#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10
139#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f
140#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16
141#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
142#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23
143#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
144
145#define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2)
146#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5
147#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3
148#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10
149#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3
150#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15
151#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7
152
153/*
154 * USB_CONFIG block
155 */
156#define AR71XX_USB_CTRL_REG_FLADJ 0x00
157#define AR71XX_USB_CTRL_REG_CONFIG 0x04
158
107/* 159/*
108 * RESET block 160 * RESET block
109 */ 161 */
@@ -130,6 +182,13 @@
130 182
131#define AR724X_RESET_REG_RESET_MODULE 0x1c 183#define AR724X_RESET_REG_RESET_MODULE 0x1c
132 184
185#define AR933X_RESET_REG_RESET_MODULE 0x1c
186#define AR933X_RESET_REG_BOOTSTRAP 0xac
187
188#define MISC_INT_ETHSW BIT(12)
189#define MISC_INT_TIMER4 BIT(10)
190#define MISC_INT_TIMER3 BIT(9)
191#define MISC_INT_TIMER2 BIT(8)
133#define MISC_INT_DMA BIT(7) 192#define MISC_INT_DMA BIT(7)
134#define MISC_INT_OHCI BIT(6) 193#define MISC_INT_OHCI BIT(6)
135#define MISC_INT_PERFC BIT(5) 194#define MISC_INT_PERFC BIT(5)
@@ -158,14 +217,29 @@
158#define AR71XX_RESET_PCI_BUS BIT(1) 217#define AR71XX_RESET_PCI_BUS BIT(1)
159#define AR71XX_RESET_PCI_CORE BIT(0) 218#define AR71XX_RESET_PCI_CORE BIT(0)
160 219
220#define AR7240_RESET_USB_HOST BIT(5)
221#define AR7240_RESET_OHCI_DLL BIT(3)
222
161#define AR724X_RESET_GE1_MDIO BIT(23) 223#define AR724X_RESET_GE1_MDIO BIT(23)
162#define AR724X_RESET_GE0_MDIO BIT(22) 224#define AR724X_RESET_GE0_MDIO BIT(22)
163#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10) 225#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10)
164#define AR724X_RESET_PCIE_PHY BIT(7) 226#define AR724X_RESET_PCIE_PHY BIT(7)
165#define AR724X_RESET_PCIE BIT(6) 227#define AR724X_RESET_PCIE BIT(6)
166#define AR724X_RESET_OHCI_DLL BIT(3) 228#define AR724X_RESET_USB_HOST BIT(5)
229#define AR724X_RESET_USB_PHY BIT(4)
230#define AR724X_RESET_USBSUS_OVERRIDE BIT(3)
167 231
168#define AR913X_RESET_AMBA2WMAC BIT(22) 232#define AR913X_RESET_AMBA2WMAC BIT(22)
233#define AR913X_RESET_USBSUS_OVERRIDE BIT(10)
234#define AR913X_RESET_USB_HOST BIT(5)
235#define AR913X_RESET_USB_PHY BIT(4)
236
237#define AR933X_RESET_WMAC BIT(11)
238#define AR933X_RESET_USB_HOST BIT(5)
239#define AR933X_RESET_USB_PHY BIT(4)
240#define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
241
242#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
169 243
170#define REV_ID_MAJOR_MASK 0xfff0 244#define REV_ID_MAJOR_MASK 0xfff0
171#define REV_ID_MAJOR_AR71XX 0x00a0 245#define REV_ID_MAJOR_AR71XX 0x00a0
@@ -173,6 +247,8 @@
173#define REV_ID_MAJOR_AR7240 0x00c0 247#define REV_ID_MAJOR_AR7240 0x00c0
174#define REV_ID_MAJOR_AR7241 0x0100 248#define REV_ID_MAJOR_AR7241 0x0100
175#define REV_ID_MAJOR_AR7242 0x1100 249#define REV_ID_MAJOR_AR7242 0x1100
250#define REV_ID_MAJOR_AR9330 0x0110
251#define REV_ID_MAJOR_AR9331 0x1110
176 252
177#define AR71XX_REV_ID_MINOR_MASK 0x3 253#define AR71XX_REV_ID_MINOR_MASK 0x3
178#define AR71XX_REV_ID_MINOR_AR7130 0x0 254#define AR71XX_REV_ID_MINOR_AR7130 0x0
@@ -187,6 +263,8 @@
187#define AR913X_REV_ID_REVISION_MASK 0x3 263#define AR913X_REV_ID_REVISION_MASK 0x3
188#define AR913X_REV_ID_REVISION_SHIFT 2 264#define AR913X_REV_ID_REVISION_SHIFT 2
189 265
266#define AR933X_REV_ID_REVISION_MASK 0x3
267
190#define AR724X_REV_ID_REVISION_MASK 0x3 268#define AR724X_REV_ID_REVISION_MASK 0x3
191 269
192/* 270/*
@@ -229,5 +307,6 @@
229#define AR71XX_GPIO_COUNT 16 307#define AR71XX_GPIO_COUNT 16
230#define AR724X_GPIO_COUNT 18 308#define AR724X_GPIO_COUNT 18
231#define AR913X_GPIO_COUNT 22 309#define AR913X_GPIO_COUNT 22
310#define AR933X_GPIO_COUNT 30
232 311
233#endif /* __ASM_MACH_AR71XX_REGS_H */ 312#endif /* __ASM_MACH_AR71XX_REGS_H */
diff --git a/arch/mips/include/asm/mach-ath79/ar933x_uart.h b/arch/mips/include/asm/mach-ath79/ar933x_uart.h
new file mode 100644
index 000000000000..52730555937f
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath79/ar933x_uart.h
@@ -0,0 +1,67 @@
1/*
2 * Atheros AR933X UART defines
3 *
4 * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 */
10
11#ifndef __AR933X_UART_H
12#define __AR933X_UART_H
13
14#define AR933X_UART_REGS_SIZE 20
15#define AR933X_UART_FIFO_SIZE 16
16
17#define AR933X_UART_DATA_REG 0x00
18#define AR933X_UART_CS_REG 0x04
19#define AR933X_UART_CLOCK_REG 0x08
20#define AR933X_UART_INT_REG 0x0c
21#define AR933X_UART_INT_EN_REG 0x10
22
23#define AR933X_UART_DATA_TX_RX_MASK 0xff
24#define AR933X_UART_DATA_RX_CSR BIT(8)
25#define AR933X_UART_DATA_TX_CSR BIT(9)
26
27#define AR933X_UART_CS_PARITY_S 0
28#define AR933X_UART_CS_PARITY_M 0x3
29#define AR933X_UART_CS_PARITY_NONE 0
30#define AR933X_UART_CS_PARITY_ODD 1
31#define AR933X_UART_CS_PARITY_EVEN 2
32#define AR933X_UART_CS_IF_MODE_S 2
33#define AR933X_UART_CS_IF_MODE_M 0x3
34#define AR933X_UART_CS_IF_MODE_NONE 0
35#define AR933X_UART_CS_IF_MODE_DTE 1
36#define AR933X_UART_CS_IF_MODE_DCE 2
37#define AR933X_UART_CS_FLOW_CTRL_S 4
38#define AR933X_UART_CS_FLOW_CTRL_M 0x3
39#define AR933X_UART_CS_DMA_EN BIT(6)
40#define AR933X_UART_CS_TX_READY_ORIDE BIT(7)
41#define AR933X_UART_CS_RX_READY_ORIDE BIT(8)
42#define AR933X_UART_CS_TX_READY BIT(9)
43#define AR933X_UART_CS_RX_BREAK BIT(10)
44#define AR933X_UART_CS_TX_BREAK BIT(11)
45#define AR933X_UART_CS_HOST_INT BIT(12)
46#define AR933X_UART_CS_HOST_INT_EN BIT(13)
47#define AR933X_UART_CS_TX_BUSY BIT(14)
48#define AR933X_UART_CS_RX_BUSY BIT(15)
49
50#define AR933X_UART_CLOCK_STEP_M 0xffff
51#define AR933X_UART_CLOCK_SCALE_M 0xfff
52#define AR933X_UART_CLOCK_SCALE_S 16
53#define AR933X_UART_CLOCK_STEP_M 0xffff
54
55#define AR933X_UART_INT_RX_VALID BIT(0)
56#define AR933X_UART_INT_TX_READY BIT(1)
57#define AR933X_UART_INT_RX_FRAMING_ERR BIT(2)
58#define AR933X_UART_INT_RX_OFLOW_ERR BIT(3)
59#define AR933X_UART_INT_TX_OFLOW_ERR BIT(4)
60#define AR933X_UART_INT_RX_PARITY_ERR BIT(5)
61#define AR933X_UART_INT_RX_BREAK_ON BIT(6)
62#define AR933X_UART_INT_RX_BREAK_OFF BIT(7)
63#define AR933X_UART_INT_RX_FULL BIT(8)
64#define AR933X_UART_INT_TX_EMPTY BIT(9)
65#define AR933X_UART_INT_ALLINTS 0x3ff
66
67#endif /* __AR933X_UART_H */
diff --git a/arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h b/arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h
new file mode 100644
index 000000000000..6cb30f2b7198
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h
@@ -0,0 +1,18 @@
1/*
2 * Platform data definition for Atheros AR933X UART
3 *
4 * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 */
10
11#ifndef _AR933X_UART_PLATFORM_H
12#define _AR933X_UART_PLATFORM_H
13
14struct ar933x_uart_platform_data {
15 unsigned uartclk;
16};
17
18#endif /* _AR933X_UART_PLATFORM_H */
diff --git a/arch/mips/include/asm/mach-ath79/ath79.h b/arch/mips/include/asm/mach-ath79/ath79.h
index 6a9f168506fe..6d0c6c9d5622 100644
--- a/arch/mips/include/asm/mach-ath79/ath79.h
+++ b/arch/mips/include/asm/mach-ath79/ath79.h
@@ -26,10 +26,13 @@ enum ath79_soc_type {
26 ATH79_SOC_AR7241, 26 ATH79_SOC_AR7241,
27 ATH79_SOC_AR7242, 27 ATH79_SOC_AR7242,
28 ATH79_SOC_AR9130, 28 ATH79_SOC_AR9130,
29 ATH79_SOC_AR9132 29 ATH79_SOC_AR9132,
30 ATH79_SOC_AR9330,
31 ATH79_SOC_AR9331,
30}; 32};
31 33
32extern enum ath79_soc_type ath79_soc; 34extern enum ath79_soc_type ath79_soc;
35extern unsigned int ath79_soc_rev;
33 36
34static inline int soc_is_ar71xx(void) 37static inline int soc_is_ar71xx(void)
35{ 38{
@@ -66,6 +69,12 @@ static inline int soc_is_ar913x(void)
66 ath79_soc == ATH79_SOC_AR9132); 69 ath79_soc == ATH79_SOC_AR9132);
67} 70}
68 71
72static inline int soc_is_ar933x(void)
73{
74 return (ath79_soc == ATH79_SOC_AR9330 ||
75 ath79_soc == ATH79_SOC_AR9331);
76}
77
69extern void __iomem *ath79_ddr_base; 78extern void __iomem *ath79_ddr_base;
70extern void __iomem *ath79_pll_base; 79extern void __iomem *ath79_pll_base;
71extern void __iomem *ath79_reset_base; 80extern void __iomem *ath79_reset_base;
diff --git a/arch/mips/include/asm/mach-ath79/irq.h b/arch/mips/include/asm/mach-ath79/irq.h
index 189bc6eb9c10..519958fe4e3c 100644
--- a/arch/mips/include/asm/mach-ath79/irq.h
+++ b/arch/mips/include/asm/mach-ath79/irq.h
@@ -10,10 +10,10 @@
10#define __ASM_MACH_ATH79_IRQ_H 10#define __ASM_MACH_ATH79_IRQ_H
11 11
12#define MIPS_CPU_IRQ_BASE 0 12#define MIPS_CPU_IRQ_BASE 0
13#define NR_IRQS 16 13#define NR_IRQS 40
14 14
15#define ATH79_MISC_IRQ_BASE 8 15#define ATH79_MISC_IRQ_BASE 8
16#define ATH79_MISC_IRQ_COUNT 8 16#define ATH79_MISC_IRQ_COUNT 32
17 17
18#define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2) 18#define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2)
19#define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3) 19#define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3)
@@ -30,6 +30,10 @@
30#define ATH79_MISC_IRQ_PERFC (ATH79_MISC_IRQ_BASE + 5) 30#define ATH79_MISC_IRQ_PERFC (ATH79_MISC_IRQ_BASE + 5)
31#define ATH79_MISC_IRQ_OHCI (ATH79_MISC_IRQ_BASE + 6) 31#define ATH79_MISC_IRQ_OHCI (ATH79_MISC_IRQ_BASE + 6)
32#define ATH79_MISC_IRQ_DMA (ATH79_MISC_IRQ_BASE + 7) 32#define ATH79_MISC_IRQ_DMA (ATH79_MISC_IRQ_BASE + 7)
33#define ATH79_MISC_IRQ_TIMER2 (ATH79_MISC_IRQ_BASE + 8)
34#define ATH79_MISC_IRQ_TIMER3 (ATH79_MISC_IRQ_BASE + 9)
35#define ATH79_MISC_IRQ_TIMER4 (ATH79_MISC_IRQ_BASE + 10)
36#define ATH79_MISC_IRQ_ETHSW (ATH79_MISC_IRQ_BASE + 12)
33 37
34#include_next <irq.h> 38#include_next <irq.h>
35 39
diff --git a/arch/mips/include/asm/mach-ath79/pci-ath724x.h b/arch/mips/include/asm/mach-ath79/pci-ath724x.h
new file mode 100644
index 000000000000..454885fa30c3
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath79/pci-ath724x.h
@@ -0,0 +1,21 @@
1/*
2 * Atheros 724x PCI support
3 *
4 * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 */
10
11#ifndef __ASM_MACH_ATH79_PCI_ATH724X_H
12#define __ASM_MACH_ATH79_PCI_ATH724X_H
13
14struct ath724x_pci_data {
15 int irq;
16 void *pdata;
17};
18
19void ath724x_pci_add_data(struct ath724x_pci_data *data, int size);
20
21#endif /* __ASM_MACH_ATH79_PCI_ATH724X_H */
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
index de24ec57dd2f..569828d3ccab 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -136,6 +136,7 @@ static inline int au1xxx_cpu_needs_config_od(void)
136#define ALCHEMY_CPU_AU1100 2 136#define ALCHEMY_CPU_AU1100 2
137#define ALCHEMY_CPU_AU1550 3 137#define ALCHEMY_CPU_AU1550 3
138#define ALCHEMY_CPU_AU1200 4 138#define ALCHEMY_CPU_AU1200 4
139#define ALCHEMY_CPU_AU1300 5
139 140
140static inline int alchemy_get_cputype(void) 141static inline int alchemy_get_cputype(void)
141{ 142{
@@ -156,6 +157,9 @@ static inline int alchemy_get_cputype(void)
156 case 0x05030000: 157 case 0x05030000:
157 return ALCHEMY_CPU_AU1200; 158 return ALCHEMY_CPU_AU1200;
158 break; 159 break;
160 case 0x800c0000:
161 return ALCHEMY_CPU_AU1300;
162 break;
159 } 163 }
160 164
161 return ALCHEMY_CPU_UNKNOWN; 165 return ALCHEMY_CPU_UNKNOWN;
@@ -166,6 +170,7 @@ static inline int alchemy_get_uarts(int type)
166{ 170{
167 switch (type) { 171 switch (type) {
168 case ALCHEMY_CPU_AU1000: 172 case ALCHEMY_CPU_AU1000:
173 case ALCHEMY_CPU_AU1300:
169 return 4; 174 return 4;
170 case ALCHEMY_CPU_AU1500: 175 case ALCHEMY_CPU_AU1500:
171 case ALCHEMY_CPU_AU1200: 176 case ALCHEMY_CPU_AU1200:
@@ -243,6 +248,7 @@ extern unsigned long au1xxx_calc_clock(void);
243/* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */ 248/* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */
244void alchemy_sleep_au1000(void); 249void alchemy_sleep_au1000(void);
245void alchemy_sleep_au1550(void); 250void alchemy_sleep_au1550(void);
251void alchemy_sleep_au1300(void);
246void au_sleep(void); 252void au_sleep(void);
247 253
248/* USB: drivers/usb/host/alchemy-common.c */ 254/* USB: drivers/usb/host/alchemy-common.c */
@@ -251,6 +257,7 @@ enum alchemy_usb_block {
251 ALCHEMY_USB_UDC0, 257 ALCHEMY_USB_UDC0,
252 ALCHEMY_USB_EHCI0, 258 ALCHEMY_USB_EHCI0,
253 ALCHEMY_USB_OTG0, 259 ALCHEMY_USB_OTG0,
260 ALCHEMY_USB_OHCI1,
254}; 261};
255int alchemy_usb_control(int block, int enable); 262int alchemy_usb_control(int block, int enable);
256 263
@@ -263,14 +270,92 @@ struct alchemy_pci_platdata {
263 unsigned long pci_cfg_clr; 270 unsigned long pci_cfg_clr;
264}; 271};
265 272
266/* SOC Interrupt numbers */ 273/* Multifunction pins: Each of these pins can either be assigned to the
274 * GPIO controller or a on-chip peripheral.
275 * Call "au1300_pinfunc_to_dev()" or "au1300_pinfunc_to_gpio()" to
276 * assign one of these to either the GPIO controller or the device.
277 */
278enum au1300_multifunc_pins {
279 /* wake-from-str pins 0-3 */
280 AU1300_PIN_WAKE0 = 0, AU1300_PIN_WAKE1, AU1300_PIN_WAKE2,
281 AU1300_PIN_WAKE3,
282 /* external clock sources for PSCs: 4-5 */
283 AU1300_PIN_EXTCLK0, AU1300_PIN_EXTCLK1,
284 /* 8bit MMC interface on SD0: 6-9 */
285 AU1300_PIN_SD0DAT4, AU1300_PIN_SD0DAT5, AU1300_PIN_SD0DAT6,
286 AU1300_PIN_SD0DAT7,
287 /* aux clk input for freqgen 3: 10 */
288 AU1300_PIN_FG3AUX,
289 /* UART1 pins: 11-18 */
290 AU1300_PIN_U1RI, AU1300_PIN_U1DCD, AU1300_PIN_U1DSR,
291 AU1300_PIN_U1CTS, AU1300_PIN_U1RTS, AU1300_PIN_U1DTR,
292 AU1300_PIN_U1RX, AU1300_PIN_U1TX,
293 /* UART0 pins: 19-24 */
294 AU1300_PIN_U0RI, AU1300_PIN_U0DCD, AU1300_PIN_U0DSR,
295 AU1300_PIN_U0CTS, AU1300_PIN_U0RTS, AU1300_PIN_U0DTR,
296 /* UART2: 25-26 */
297 AU1300_PIN_U2RX, AU1300_PIN_U2TX,
298 /* UART3: 27-28 */
299 AU1300_PIN_U3RX, AU1300_PIN_U3TX,
300 /* LCD controller PWMs, ext pixclock: 29-31 */
301 AU1300_PIN_LCDPWM0, AU1300_PIN_LCDPWM1, AU1300_PIN_LCDCLKIN,
302 /* SD1 interface: 32-37 */
303 AU1300_PIN_SD1DAT0, AU1300_PIN_SD1DAT1, AU1300_PIN_SD1DAT2,
304 AU1300_PIN_SD1DAT3, AU1300_PIN_SD1CMD, AU1300_PIN_SD1CLK,
305 /* SD2 interface: 38-43 */
306 AU1300_PIN_SD2DAT0, AU1300_PIN_SD2DAT1, AU1300_PIN_SD2DAT2,
307 AU1300_PIN_SD2DAT3, AU1300_PIN_SD2CMD, AU1300_PIN_SD2CLK,
308 /* PSC0/1 clocks: 44-45 */
309 AU1300_PIN_PSC0CLK, AU1300_PIN_PSC1CLK,
310 /* PSCs: 46-49/50-53/54-57/58-61 */
311 AU1300_PIN_PSC0SYNC0, AU1300_PIN_PSC0SYNC1, AU1300_PIN_PSC0D0,
312 AU1300_PIN_PSC0D1,
313 AU1300_PIN_PSC1SYNC0, AU1300_PIN_PSC1SYNC1, AU1300_PIN_PSC1D0,
314 AU1300_PIN_PSC1D1,
315 AU1300_PIN_PSC2SYNC0, AU1300_PIN_PSC2SYNC1, AU1300_PIN_PSC2D0,
316 AU1300_PIN_PSC2D1,
317 AU1300_PIN_PSC3SYNC0, AU1300_PIN_PSC3SYNC1, AU1300_PIN_PSC3D0,
318 AU1300_PIN_PSC3D1,
319 /* PCMCIA interface: 62-70 */
320 AU1300_PIN_PCE2, AU1300_PIN_PCE1, AU1300_PIN_PIOS16,
321 AU1300_PIN_PIOR, AU1300_PIN_PWE, AU1300_PIN_PWAIT,
322 AU1300_PIN_PREG, AU1300_PIN_POE, AU1300_PIN_PIOW,
323 /* camera interface H/V sync inputs: 71-72 */
324 AU1300_PIN_CIMLS, AU1300_PIN_CIMFS,
325 /* PSC2/3 clocks: 73-74 */
326 AU1300_PIN_PSC2CLK, AU1300_PIN_PSC3CLK,
327};
328
329/* GPIC (Au1300) pin management: arch/mips/alchemy/common/gpioint.c */
330extern void au1300_pinfunc_to_gpio(enum au1300_multifunc_pins gpio);
331extern void au1300_pinfunc_to_dev(enum au1300_multifunc_pins gpio);
332extern void au1300_set_irq_priority(unsigned int irq, int p);
333extern void au1300_set_dbdma_gpio(int dchan, unsigned int gpio);
334
335/* Au1300 allows to disconnect certain blocks from internal power supply */
336enum au1300_vss_block {
337 AU1300_VSS_MPE = 0,
338 AU1300_VSS_BSA,
339 AU1300_VSS_GPE,
340 AU1300_VSS_MGP,
341};
267 342
343extern void au1300_vss_block_control(int block, int enable);
344
345
346/* SOC Interrupt numbers */
347/* Au1000-style (IC0/1): 2 controllers with 32 sources each */
268#define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8) 348#define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
269#define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31) 349#define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31)
270#define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_LAST + 1) 350#define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_LAST + 1)
271#define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31) 351#define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31)
272#define AU1000_MAX_INTR AU1000_INTC1_INT_LAST 352#define AU1000_MAX_INTR AU1000_INTC1_INT_LAST
273 353
354/* Au1300-style (GPIC): 1 controller with up to 128 sources */
355#define ALCHEMY_GPIC_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
356#define ALCHEMY_GPIC_INT_NUM 128
357#define ALCHEMY_GPIC_INT_LAST (ALCHEMY_GPIC_INT_BASE + ALCHEMY_GPIC_INT_NUM - 1)
358
274enum soc_au1000_ints { 359enum soc_au1000_ints {
275 AU1000_FIRST_INT = AU1000_INTC0_INT_BASE, 360 AU1000_FIRST_INT = AU1000_INTC0_INT_BASE,
276 AU1000_UART0_INT = AU1000_FIRST_INT, 361 AU1000_UART0_INT = AU1000_FIRST_INT,
@@ -591,24 +676,77 @@ enum soc_au1200_ints {
591 676
592#endif /* !defined (_LANGUAGE_ASSEMBLY) */ 677#endif /* !defined (_LANGUAGE_ASSEMBLY) */
593 678
679/* Au1300 peripheral interrupt numbers */
680#define AU1300_FIRST_INT (ALCHEMY_GPIC_INT_BASE)
681#define AU1300_UART1_INT (AU1300_FIRST_INT + 17)
682#define AU1300_UART2_INT (AU1300_FIRST_INT + 25)
683#define AU1300_UART3_INT (AU1300_FIRST_INT + 27)
684#define AU1300_SD1_INT (AU1300_FIRST_INT + 32)
685#define AU1300_SD2_INT (AU1300_FIRST_INT + 38)
686#define AU1300_PSC0_INT (AU1300_FIRST_INT + 48)
687#define AU1300_PSC1_INT (AU1300_FIRST_INT + 52)
688#define AU1300_PSC2_INT (AU1300_FIRST_INT + 56)
689#define AU1300_PSC3_INT (AU1300_FIRST_INT + 60)
690#define AU1300_NAND_INT (AU1300_FIRST_INT + 62)
691#define AU1300_DDMA_INT (AU1300_FIRST_INT + 75)
692#define AU1300_MMU_INT (AU1300_FIRST_INT + 76)
693#define AU1300_MPU_INT (AU1300_FIRST_INT + 77)
694#define AU1300_GPU_INT (AU1300_FIRST_INT + 78)
695#define AU1300_UDMA_INT (AU1300_FIRST_INT + 79)
696#define AU1300_TOY_INT (AU1300_FIRST_INT + 80)
697#define AU1300_TOY_MATCH0_INT (AU1300_FIRST_INT + 81)
698#define AU1300_TOY_MATCH1_INT (AU1300_FIRST_INT + 82)
699#define AU1300_TOY_MATCH2_INT (AU1300_FIRST_INT + 83)
700#define AU1300_RTC_INT (AU1300_FIRST_INT + 84)
701#define AU1300_RTC_MATCH0_INT (AU1300_FIRST_INT + 85)
702#define AU1300_RTC_MATCH1_INT (AU1300_FIRST_INT + 86)
703#define AU1300_RTC_MATCH2_INT (AU1300_FIRST_INT + 87)
704#define AU1300_UART0_INT (AU1300_FIRST_INT + 88)
705#define AU1300_SD0_INT (AU1300_FIRST_INT + 89)
706#define AU1300_USB_INT (AU1300_FIRST_INT + 90)
707#define AU1300_LCD_INT (AU1300_FIRST_INT + 91)
708#define AU1300_BSA_INT (AU1300_FIRST_INT + 92)
709#define AU1300_MPE_INT (AU1300_FIRST_INT + 93)
710#define AU1300_ITE_INT (AU1300_FIRST_INT + 94)
711#define AU1300_AES_INT (AU1300_FIRST_INT + 95)
712#define AU1300_CIM_INT (AU1300_FIRST_INT + 96)
713
714/**********************************************************************/
715
594/* 716/*
595 * Physical base addresses for integrated peripherals 717 * Physical base addresses for integrated peripherals
596 * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 718 * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 5..au1300
597 */ 719 */
598 720
599#define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */ 721#define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */
722#define AU1300_ROM_PHYS_ADDR 0x10000000 /* 5 */
723#define AU1300_OTP_PHYS_ADDR 0x10002000 /* 5 */
724#define AU1300_VSS_PHYS_ADDR 0x10003000 /* 5 */
725#define AU1300_UART0_PHYS_ADDR 0x10100000 /* 5 */
726#define AU1300_UART1_PHYS_ADDR 0x10101000 /* 5 */
727#define AU1300_UART2_PHYS_ADDR 0x10102000 /* 5 */
728#define AU1300_UART3_PHYS_ADDR 0x10103000 /* 5 */
600#define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */ 729#define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */
601#define AU1000_USB_UDC_PHYS_ADDR 0x10200000 /* 0123 */ 730#define AU1000_USB_UDC_PHYS_ADDR 0x10200000 /* 0123 */
731#define AU1300_GPIC_PHYS_ADDR 0x10200000 /* 5 */
602#define AU1000_IRDA_PHYS_ADDR 0x10300000 /* 02 */ 732#define AU1000_IRDA_PHYS_ADDR 0x10300000 /* 02 */
603#define AU1200_AES_PHYS_ADDR 0x10300000 /* 4 */ 733#define AU1200_AES_PHYS_ADDR 0x10300000 /* 45 */
604#define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */ 734#define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */
735#define AU1300_GPU_PHYS_ADDR 0x10500000 /* 5 */
605#define AU1000_MAC0_PHYS_ADDR 0x10500000 /* 023 */ 736#define AU1000_MAC0_PHYS_ADDR 0x10500000 /* 023 */
606#define AU1000_MAC1_PHYS_ADDR 0x10510000 /* 023 */ 737#define AU1000_MAC1_PHYS_ADDR 0x10510000 /* 023 */
607#define AU1000_MACEN_PHYS_ADDR 0x10520000 /* 023 */ 738#define AU1000_MACEN_PHYS_ADDR 0x10520000 /* 023 */
608#define AU1100_SD0_PHYS_ADDR 0x10600000 /* 24 */ 739#define AU1100_SD0_PHYS_ADDR 0x10600000 /* 245 */
740#define AU1300_SD1_PHYS_ADDR 0x10601000 /* 5 */
741#define AU1300_SD2_PHYS_ADDR 0x10602000 /* 5 */
609#define AU1100_SD1_PHYS_ADDR 0x10680000 /* 24 */ 742#define AU1100_SD1_PHYS_ADDR 0x10680000 /* 24 */
743#define AU1300_SYS_PHYS_ADDR 0x10900000 /* 5 */
610#define AU1550_PSC2_PHYS_ADDR 0x10A00000 /* 3 */ 744#define AU1550_PSC2_PHYS_ADDR 0x10A00000 /* 3 */
611#define AU1550_PSC3_PHYS_ADDR 0x10B00000 /* 3 */ 745#define AU1550_PSC3_PHYS_ADDR 0x10B00000 /* 3 */
746#define AU1300_PSC0_PHYS_ADDR 0x10A00000 /* 5 */
747#define AU1300_PSC1_PHYS_ADDR 0x10A01000 /* 5 */
748#define AU1300_PSC2_PHYS_ADDR 0x10A02000 /* 5 */
749#define AU1300_PSC3_PHYS_ADDR 0x10A03000 /* 5 */
612#define AU1000_I2S_PHYS_ADDR 0x11000000 /* 02 */ 750#define AU1000_I2S_PHYS_ADDR 0x11000000 /* 02 */
613#define AU1500_MAC0_PHYS_ADDR 0x11500000 /* 1 */ 751#define AU1500_MAC0_PHYS_ADDR 0x11500000 /* 1 */
614#define AU1500_MAC1_PHYS_ADDR 0x11510000 /* 1 */ 752#define AU1500_MAC1_PHYS_ADDR 0x11510000 /* 1 */
@@ -622,37 +760,96 @@ enum soc_au1200_ints {
622#define AU1000_SSI1_PHYS_ADDR 0x11680000 /* 02 */ 760#define AU1000_SSI1_PHYS_ADDR 0x11680000 /* 02 */
623#define AU1500_GPIO2_PHYS_ADDR 0x11700000 /* 1234 */ 761#define AU1500_GPIO2_PHYS_ADDR 0x11700000 /* 1234 */
624#define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */ 762#define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */
625#define AU1000_SYS_PHYS_ADDR 0x11900000 /* 01234 */ 763#define AU1000_SYS_PHYS_ADDR 0x11900000 /* 012345 */
626#define AU1550_PSC0_PHYS_ADDR 0x11A00000 /* 34 */ 764#define AU1550_PSC0_PHYS_ADDR 0x11A00000 /* 34 */
627#define AU1550_PSC1_PHYS_ADDR 0x11B00000 /* 34 */ 765#define AU1550_PSC1_PHYS_ADDR 0x11B00000 /* 34 */
628#define AU1000_MEM_PHYS_ADDR 0x14000000 /* 01234 */ 766#define AU1000_MEM_PHYS_ADDR 0x14000000 /* 01234 */
629#define AU1000_STATIC_MEM_PHYS_ADDR 0x14001000 /* 01234 */ 767#define AU1000_STATIC_MEM_PHYS_ADDR 0x14001000 /* 01234 */
768#define AU1300_UDMA_PHYS_ADDR 0x14001800 /* 5 */
630#define AU1000_DMA_PHYS_ADDR 0x14002000 /* 012 */ 769#define AU1000_DMA_PHYS_ADDR 0x14002000 /* 012 */
631#define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 34 */ 770#define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 345 */
632#define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 34 */ 771#define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 345 */
633#define AU1000_MACDMA0_PHYS_ADDR 0x14004000 /* 0123 */ 772#define AU1000_MACDMA0_PHYS_ADDR 0x14004000 /* 0123 */
634#define AU1000_MACDMA1_PHYS_ADDR 0x14004200 /* 0123 */ 773#define AU1000_MACDMA1_PHYS_ADDR 0x14004200 /* 0123 */
635#define AU1200_CIM_PHYS_ADDR 0x14004000 /* 4 */ 774#define AU1200_CIM_PHYS_ADDR 0x14004000 /* 45 */
636#define AU1500_PCI_PHYS_ADDR 0x14005000 /* 13 */ 775#define AU1500_PCI_PHYS_ADDR 0x14005000 /* 13 */
637#define AU1550_PE_PHYS_ADDR 0x14008000 /* 3 */ 776#define AU1550_PE_PHYS_ADDR 0x14008000 /* 3 */
638#define AU1200_MAEBE_PHYS_ADDR 0x14010000 /* 4 */ 777#define AU1200_MAEBE_PHYS_ADDR 0x14010000 /* 4 */
639#define AU1200_MAEFE_PHYS_ADDR 0x14012000 /* 4 */ 778#define AU1200_MAEFE_PHYS_ADDR 0x14012000 /* 4 */
779#define AU1300_MAEITE_PHYS_ADDR 0x14010000 /* 5 */
780#define AU1300_MAEMPE_PHYS_ADDR 0x14014000 /* 5 */
640#define AU1550_USB_OHCI_PHYS_ADDR 0x14020000 /* 3 */ 781#define AU1550_USB_OHCI_PHYS_ADDR 0x14020000 /* 3 */
641#define AU1200_USB_CTL_PHYS_ADDR 0x14020000 /* 4 */ 782#define AU1200_USB_CTL_PHYS_ADDR 0x14020000 /* 4 */
642#define AU1200_USB_OTG_PHYS_ADDR 0x14020020 /* 4 */ 783#define AU1200_USB_OTG_PHYS_ADDR 0x14020020 /* 4 */
643#define AU1200_USB_OHCI_PHYS_ADDR 0x14020100 /* 4 */ 784#define AU1200_USB_OHCI_PHYS_ADDR 0x14020100 /* 4 */
644#define AU1200_USB_EHCI_PHYS_ADDR 0x14020200 /* 4 */ 785#define AU1200_USB_EHCI_PHYS_ADDR 0x14020200 /* 4 */
645#define AU1200_USB_UDC_PHYS_ADDR 0x14022000 /* 4 */ 786#define AU1200_USB_UDC_PHYS_ADDR 0x14022000 /* 4 */
787#define AU1300_USB_EHCI_PHYS_ADDR 0x14020000 /* 5 */
788#define AU1300_USB_OHCI0_PHYS_ADDR 0x14020400 /* 5 */
789#define AU1300_USB_OHCI1_PHYS_ADDR 0x14020800 /* 5 */
790#define AU1300_USB_CTL_PHYS_ADDR 0x14021000 /* 5 */
791#define AU1300_USB_OTG_PHYS_ADDR 0x14022000 /* 5 */
792#define AU1300_MAEBSA_PHYS_ADDR 0x14030000 /* 5 */
646#define AU1100_LCD_PHYS_ADDR 0x15000000 /* 2 */ 793#define AU1100_LCD_PHYS_ADDR 0x15000000 /* 2 */
647#define AU1200_LCD_PHYS_ADDR 0x15000000 /* 4 */ 794#define AU1200_LCD_PHYS_ADDR 0x15000000 /* 45 */
648#define AU1500_PCI_MEM_PHYS_ADDR 0x400000000ULL /* 13 */ 795#define AU1500_PCI_MEM_PHYS_ADDR 0x400000000ULL /* 13 */
649#define AU1500_PCI_IO_PHYS_ADDR 0x500000000ULL /* 13 */ 796#define AU1500_PCI_IO_PHYS_ADDR 0x500000000ULL /* 13 */
650#define AU1500_PCI_CONFIG0_PHYS_ADDR 0x600000000ULL /* 13 */ 797#define AU1500_PCI_CONFIG0_PHYS_ADDR 0x600000000ULL /* 13 */
651#define AU1500_PCI_CONFIG1_PHYS_ADDR 0x680000000ULL /* 13 */ 798#define AU1500_PCI_CONFIG1_PHYS_ADDR 0x680000000ULL /* 13 */
652#define AU1000_PCMCIA_IO_PHYS_ADDR 0xF00000000ULL /* 01234 */ 799#define AU1000_PCMCIA_IO_PHYS_ADDR 0xF00000000ULL /* 012345 */
653#define AU1000_PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL /* 01234 */ 800#define AU1000_PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL /* 012345 */
654#define AU1000_PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL /* 01234 */ 801#define AU1000_PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL /* 012345 */
655 802
803/**********************************************************************/
804
805
806/*
807 * Au1300 GPIO+INT controller (GPIC) register offsets and bits
808 * Registers are 128bits (0x10 bytes), divided into 4 "banks".
809 */
810#define AU1300_GPIC_PINVAL 0x0000
811#define AU1300_GPIC_PINVALCLR 0x0010
812#define AU1300_GPIC_IPEND 0x0020
813#define AU1300_GPIC_PRIENC 0x0030
814#define AU1300_GPIC_IEN 0x0040 /* int_mask in manual */
815#define AU1300_GPIC_IDIS 0x0050 /* int_maskclr in manual */
816#define AU1300_GPIC_DMASEL 0x0060
817#define AU1300_GPIC_DEVSEL 0x0080
818#define AU1300_GPIC_DEVCLR 0x0090
819#define AU1300_GPIC_RSTVAL 0x00a0
820/* pin configuration space. one 32bit register for up to 128 IRQs */
821#define AU1300_GPIC_PINCFG 0x1000
822
823#define GPIC_GPIO_TO_BIT(gpio) \
824 (1 << ((gpio) & 0x1f))
825
826#define GPIC_GPIO_BANKOFF(gpio) \
827 (((gpio) >> 5) * 4)
828
829/* Pin Control bits: who owns the pin, what does it do */
830#define GPIC_CFG_PC_GPIN 0
831#define GPIC_CFG_PC_DEV 1
832#define GPIC_CFG_PC_GPOLOW 2
833#define GPIC_CFG_PC_GPOHIGH 3
834#define GPIC_CFG_PC_MASK 3
835
836/* assign pin to MIPS IRQ line */
837#define GPIC_CFG_IL_SET(x) (((x) & 3) << 2)
838#define GPIC_CFG_IL_MASK (3 << 2)
839
840/* pin interrupt type setup */
841#define GPIC_CFG_IC_OFF (0 << 4)
842#define GPIC_CFG_IC_LEVEL_LOW (1 << 4)
843#define GPIC_CFG_IC_LEVEL_HIGH (2 << 4)
844#define GPIC_CFG_IC_EDGE_FALL (5 << 4)
845#define GPIC_CFG_IC_EDGE_RISE (6 << 4)
846#define GPIC_CFG_IC_EDGE_BOTH (7 << 4)
847#define GPIC_CFG_IC_MASK (7 << 4)
848
849/* allow interrupt to wake cpu from 'wait' */
850#define GPIC_CFG_IDLEWAKE (1 << 7)
851
852/***********************************************************************/
656 853
657/* Au1000 SDRAM memory controller register offsets */ 854/* Au1000 SDRAM memory controller register offsets */
658#define AU1000_MEM_SDMODE0 0x0000 855#define AU1000_MEM_SDMODE0 0x0000
@@ -1068,44 +1265,20 @@ enum soc_au1200_ints {
1068#define SSI_ENABLE_CD (1 << 1) 1265#define SSI_ENABLE_CD (1 << 1)
1069#define SSI_ENABLE_E (1 << 0) 1266#define SSI_ENABLE_E (1 << 0)
1070 1267
1071/* IrDA Controller */ 1268
1072#define IRDA_BASE 0xB0300000 1269/*
1073#define IR_RING_PTR_STATUS (IRDA_BASE + 0x00) 1270 * The IrDA peripheral has an IRFIRSEL pin, but on the DB/PB boards it's not
1074#define IR_RING_BASE_ADDR_H (IRDA_BASE + 0x04) 1271 * used to select FIR/SIR mode on the transceiver but as a GPIO. Instead a
1075#define IR_RING_BASE_ADDR_L (IRDA_BASE + 0x08) 1272 * CPLD has to be told about the mode.
1076#define IR_RING_SIZE (IRDA_BASE + 0x0C) 1273 */
1077#define IR_RING_PROMPT (IRDA_BASE + 0x10) 1274#define AU1000_IRDA_PHY_MODE_OFF 0
1078#define IR_RING_ADDR_CMPR (IRDA_BASE + 0x14) 1275#define AU1000_IRDA_PHY_MODE_SIR 1
1079#define IR_INT_CLEAR (IRDA_BASE + 0x18) 1276#define AU1000_IRDA_PHY_MODE_FIR 2
1080#define IR_CONFIG_1 (IRDA_BASE + 0x20) 1277
1081# define IR_RX_INVERT_LED (1 << 0) 1278struct au1k_irda_platform_data {
1082# define IR_TX_INVERT_LED (1 << 1) 1279 void(*set_phy_mode)(int mode);
1083# define IR_ST (1 << 2) 1280};
1084# define IR_SF (1 << 3) 1281
1085# define IR_SIR (1 << 4)
1086# define IR_MIR (1 << 5)
1087# define IR_FIR (1 << 6)
1088# define IR_16CRC (1 << 7)
1089# define IR_TD (1 << 8)
1090# define IR_RX_ALL (1 << 9)
1091# define IR_DMA_ENABLE (1 << 10)
1092# define IR_RX_ENABLE (1 << 11)
1093# define IR_TX_ENABLE (1 << 12)
1094# define IR_LOOPBACK (1 << 14)
1095# define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \
1096 IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
1097#define IR_SIR_FLAGS (IRDA_BASE + 0x24)
1098#define IR_ENABLE (IRDA_BASE + 0x28)
1099# define IR_RX_STATUS (1 << 9)
1100# define IR_TX_STATUS (1 << 10)
1101#define IR_READ_PHY_CONFIG (IRDA_BASE + 0x2C)
1102#define IR_WRITE_PHY_CONFIG (IRDA_BASE + 0x30)
1103#define IR_MAX_PKT_LEN (IRDA_BASE + 0x34)
1104#define IR_RX_BYTE_CNT (IRDA_BASE + 0x38)
1105#define IR_CONFIG_2 (IRDA_BASE + 0x3C)
1106# define IR_MODE_INV (1 << 0)
1107# define IR_ONE_PIN (1 << 1)
1108#define IR_INTERFACE_CONFIG (IRDA_BASE + 0x40)
1109 1282
1110/* GPIO */ 1283/* GPIO */
1111#define SYS_PINFUNC 0xB190002C 1284#define SYS_PINFUNC 0xB190002C
diff --git a/arch/mips/include/asm/mach-au1x00/au1100_mmc.h b/arch/mips/include/asm/mach-au1x00/au1100_mmc.h
index 94000a3b6f0b..e221659f1bca 100644
--- a/arch/mips/include/asm/mach-au1x00/au1100_mmc.h
+++ b/arch/mips/include/asm/mach-au1x00/au1100_mmc.h
@@ -130,8 +130,10 @@ struct au1xmmc_platform_data {
130#define SD_CONFIG2_DF (0x00000008) 130#define SD_CONFIG2_DF (0x00000008)
131#define SD_CONFIG2_DC (0x00000010) 131#define SD_CONFIG2_DC (0x00000010)
132#define SD_CONFIG2_xx2 (0x000000e0) 132#define SD_CONFIG2_xx2 (0x000000e0)
133#define SD_CONFIG2_BB (0x00000080)
133#define SD_CONFIG2_WB (0x00000100) 134#define SD_CONFIG2_WB (0x00000100)
134#define SD_CONFIG2_RW (0x00000200) 135#define SD_CONFIG2_RW (0x00000200)
136#define SD_CONFIG2_DP (0x00000400)
135 137
136 138
137/* 139/*
diff --git a/arch/mips/include/asm/mach-au1x00/au1200fb.h b/arch/mips/include/asm/mach-au1x00/au1200fb.h
new file mode 100644
index 000000000000..b3c87cc64bb9
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/au1200fb.h
@@ -0,0 +1,14 @@
1/*
2 * platform data for au1200fb driver.
3 */
4
5#ifndef _AU1200FB_PLAT_H_
6#define _AU1200FB_PLAT_H_
7
8struct au1200fb_platdata {
9 int (*panel_index)(void);
10 int (*panel_init)(void);
11 int (*panel_shutdown)(void);
12};
13
14#endif
diff --git a/arch/mips/include/asm/mach-au1x00/au1550nd.h b/arch/mips/include/asm/mach-au1x00/au1550nd.h
new file mode 100644
index 000000000000..ad4c0a03afef
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/au1550nd.h
@@ -0,0 +1,16 @@
1/*
2 * platform data for the Au1550 NAND driver
3 */
4
5#ifndef _AU1550ND_H_
6#define _AU1550ND_H_
7
8#include <linux/mtd/partitions.h>
9
10struct au1550nd_platdata {
11 struct mtd_partition *parts;
12 int num_parts;
13 int devwidth; /* 0 = 8bit device, 1 = 16bit device */
14};
15
16#endif
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
index 323ce2d145f2..217810e18361 100644
--- a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
@@ -183,6 +183,37 @@ typedef volatile struct au1xxx_ddma_desc {
183#define AU1200_DSCR_CMD0_PSC1_SYNC 25 183#define AU1200_DSCR_CMD0_PSC1_SYNC 25
184#define AU1200_DSCR_CMD0_CIM_SYNC 26 184#define AU1200_DSCR_CMD0_CIM_SYNC 26
185 185
186#define AU1300_DSCR_CMD0_UART0_TX 0
187#define AU1300_DSCR_CMD0_UART0_RX 1
188#define AU1300_DSCR_CMD0_UART1_TX 2
189#define AU1300_DSCR_CMD0_UART1_RX 3
190#define AU1300_DSCR_CMD0_UART2_TX 4
191#define AU1300_DSCR_CMD0_UART2_RX 5
192#define AU1300_DSCR_CMD0_UART3_TX 6
193#define AU1300_DSCR_CMD0_UART3_RX 7
194#define AU1300_DSCR_CMD0_SDMS_TX0 8
195#define AU1300_DSCR_CMD0_SDMS_RX0 9
196#define AU1300_DSCR_CMD0_SDMS_TX1 10
197#define AU1300_DSCR_CMD0_SDMS_RX1 11
198#define AU1300_DSCR_CMD0_AES_TX 12
199#define AU1300_DSCR_CMD0_AES_RX 13
200#define AU1300_DSCR_CMD0_PSC0_TX 14
201#define AU1300_DSCR_CMD0_PSC0_RX 15
202#define AU1300_DSCR_CMD0_PSC1_TX 16
203#define AU1300_DSCR_CMD0_PSC1_RX 17
204#define AU1300_DSCR_CMD0_PSC2_TX 18
205#define AU1300_DSCR_CMD0_PSC2_RX 19
206#define AU1300_DSCR_CMD0_PSC3_TX 20
207#define AU1300_DSCR_CMD0_PSC3_RX 21
208#define AU1300_DSCR_CMD0_LCD 22
209#define AU1300_DSCR_CMD0_NAND_FLASH 23
210#define AU1300_DSCR_CMD0_SDMS_TX2 24
211#define AU1300_DSCR_CMD0_SDMS_RX2 25
212#define AU1300_DSCR_CMD0_CIM_SYNC 26
213#define AU1300_DSCR_CMD0_UDMA 27
214#define AU1300_DSCR_CMD0_DMA_REQ0 28
215#define AU1300_DSCR_CMD0_DMA_REQ1 29
216
186#define DSCR_CMD0_THROTTLE 30 217#define DSCR_CMD0_THROTTLE 30
187#define DSCR_CMD0_ALWAYS 31 218#define DSCR_CMD0_ALWAYS 31
188#define DSCR_NDEV_IDS 32 219#define DSCR_NDEV_IDS 32
diff --git a/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h b/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
index d5df0cab9b87..3f741af37d47 100644
--- a/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
@@ -13,12 +13,14 @@
13#define cpu_has_4k_cache 1 13#define cpu_has_4k_cache 1
14#define cpu_has_tx39_cache 0 14#define cpu_has_tx39_cache 0
15#define cpu_has_fpu 0 15#define cpu_has_fpu 0
16#define cpu_has_32fpr 0
16#define cpu_has_counter 1 17#define cpu_has_counter 1
17#define cpu_has_watch 1 18#define cpu_has_watch 1
18#define cpu_has_divec 1 19#define cpu_has_divec 1
19#define cpu_has_vce 0 20#define cpu_has_vce 0
20#define cpu_has_cache_cdex_p 0 21#define cpu_has_cache_cdex_p 0
21#define cpu_has_cache_cdex_s 0 22#define cpu_has_cache_cdex_s 0
23#define cpu_has_prefetch 1
22#define cpu_has_mcheck 1 24#define cpu_has_mcheck 1
23#define cpu_has_ejtag 1 25#define cpu_has_ejtag 1
24#define cpu_has_llsc 1 26#define cpu_has_llsc 1
@@ -29,6 +31,7 @@
29#define cpu_has_vtag_icache 0 31#define cpu_has_vtag_icache 0
30#define cpu_has_dc_aliases 0 32#define cpu_has_dc_aliases 0
31#define cpu_has_ic_fills_f_dc 1 33#define cpu_has_ic_fills_f_dc 1
34#define cpu_has_pindexed_dcache 0
32#define cpu_has_mips32r1 1 35#define cpu_has_mips32r1 1
33#define cpu_has_mips32r2 0 36#define cpu_has_mips32r2 0
34#define cpu_has_mips64r1 0 37#define cpu_has_mips64r1 0
diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1300.h b/arch/mips/include/asm/mach-au1x00/gpio-au1300.h
new file mode 100644
index 000000000000..556e1be20bf6
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/gpio-au1300.h
@@ -0,0 +1,241 @@
1/*
2 * gpio-au1300.h -- GPIO control for Au1300 GPIC and compatibles.
3 *
4 * Copyright (c) 2009-2011 Manuel Lauss <manuel.lauss@googlemail.com>
5 */
6
7#ifndef _GPIO_AU1300_H_
8#define _GPIO_AU1300_H_
9
10#include <asm/addrspace.h>
11#include <asm/io.h>
12#include <asm/mach-au1x00/au1000.h>
13
14/* with the current GPIC design, up to 128 GPIOs are possible.
15 * The only implementation so far is in the Au1300, which has 75 externally
16 * available GPIOs.
17 */
18#define AU1300_GPIO_BASE 0
19#define AU1300_GPIO_NUM 75
20#define AU1300_GPIO_MAX (AU1300_GPIO_BASE + AU1300_GPIO_NUM - 1)
21
22#define AU1300_GPIC_ADDR \
23 (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR)
24
25static inline int au1300_gpio_get_value(unsigned int gpio)
26{
27 void __iomem *roff = AU1300_GPIC_ADDR;
28 int bit;
29
30 gpio -= AU1300_GPIO_BASE;
31 roff += GPIC_GPIO_BANKOFF(gpio);
32 bit = GPIC_GPIO_TO_BIT(gpio);
33 return __raw_readl(roff + AU1300_GPIC_PINVAL) & bit;
34}
35
36static inline int au1300_gpio_direction_input(unsigned int gpio)
37{
38 void __iomem *roff = AU1300_GPIC_ADDR;
39 unsigned long bit;
40
41 gpio -= AU1300_GPIO_BASE;
42
43 roff += GPIC_GPIO_BANKOFF(gpio);
44 bit = GPIC_GPIO_TO_BIT(gpio);
45 __raw_writel(bit, roff + AU1300_GPIC_DEVCLR);
46 wmb();
47
48 return 0;
49}
50
51static inline int au1300_gpio_set_value(unsigned int gpio, int v)
52{
53 void __iomem *roff = AU1300_GPIC_ADDR;
54 unsigned long bit;
55
56 gpio -= AU1300_GPIO_BASE;
57
58 roff += GPIC_GPIO_BANKOFF(gpio);
59 bit = GPIC_GPIO_TO_BIT(gpio);
60 __raw_writel(bit, roff + (v ? AU1300_GPIC_PINVAL
61 : AU1300_GPIC_PINVALCLR));
62 wmb();
63
64 return 0;
65}
66
67static inline int au1300_gpio_direction_output(unsigned int gpio, int v)
68{
69 /* hw switches to output automatically */
70 return au1300_gpio_set_value(gpio, v);
71}
72
73static inline int au1300_gpio_to_irq(unsigned int gpio)
74{
75 return AU1300_FIRST_INT + (gpio - AU1300_GPIO_BASE);
76}
77
78static inline int au1300_irq_to_gpio(unsigned int irq)
79{
80 return (irq - AU1300_FIRST_INT) + AU1300_GPIO_BASE;
81}
82
83static inline int au1300_gpio_is_valid(unsigned int gpio)
84{
85 int ret;
86
87 switch (alchemy_get_cputype()) {
88 case ALCHEMY_CPU_AU1300:
89 ret = ((gpio >= AU1300_GPIO_BASE) && (gpio <= AU1300_GPIO_MAX));
90 break;
91 default:
92 ret = 0;
93 }
94 return ret;
95}
96
97static inline int au1300_gpio_cansleep(unsigned int gpio)
98{
99 return 0;
100}
101
102/* hardware remembers gpio 0-63 levels on powerup */
103static inline int au1300_gpio_getinitlvl(unsigned int gpio)
104{
105 void __iomem *roff = AU1300_GPIC_ADDR;
106 unsigned long v;
107
108 if (unlikely(gpio > 63))
109 return 0;
110 else if (gpio > 31) {
111 gpio -= 32;
112 roff += 4;
113 }
114
115 v = __raw_readl(roff + AU1300_GPIC_RSTVAL);
116 return (v >> gpio) & 1;
117}
118
119/**********************************************************************/
120
121/* Linux gpio framework integration.
122*
123* 4 use cases of Alchemy GPIOS:
124*(1) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=y:
125* Board must register gpiochips.
126*(2) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=n:
127* A gpiochip for the 75 GPIOs is registered.
128*
129*(3) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=y:
130* the boards' gpio.h must provide the linux gpio wrapper functions,
131*
132*(4) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=n:
133* inlinable gpio functions are provided which enable access to the
134* Au1300 gpios only by using the numbers straight out of the data-
135* sheets.
136
137* Cases 1 and 3 are intended for boards which want to provide their own
138* GPIO namespace and -operations (i.e. for example you have 8 GPIOs
139* which are in part provided by spare Au1300 GPIO pins and in part by
140* an external FPGA but you still want them to be accssible in linux
141* as gpio0-7. The board can of course use the alchemy_gpioX_* functions
142* as required).
143*/
144
145#ifndef CONFIG_GPIOLIB
146
147#ifdef CONFIG_ALCHEMY_GPIOINT_AU1300
148
149#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (4) */
150
151static inline int gpio_direction_input(unsigned int gpio)
152{
153 return au1300_gpio_direction_input(gpio);
154}
155
156static inline int gpio_direction_output(unsigned int gpio, int v)
157{
158 return au1300_gpio_direction_output(gpio, v);
159}
160
161static inline int gpio_get_value(unsigned int gpio)
162{
163 return au1300_gpio_get_value(gpio);
164}
165
166static inline void gpio_set_value(unsigned int gpio, int v)
167{
168 au1300_gpio_set_value(gpio, v);
169}
170
171static inline int gpio_get_value_cansleep(unsigned gpio)
172{
173 return gpio_get_value(gpio);
174}
175
176static inline void gpio_set_value_cansleep(unsigned gpio, int value)
177{
178 gpio_set_value(gpio, value);
179}
180
181static inline int gpio_is_valid(unsigned int gpio)
182{
183 return au1300_gpio_is_valid(gpio);
184}
185
186static inline int gpio_cansleep(unsigned int gpio)
187{
188 return au1300_gpio_cansleep(gpio);
189}
190
191static inline int gpio_to_irq(unsigned int gpio)
192{
193 return au1300_gpio_to_irq(gpio);
194}
195
196static inline int irq_to_gpio(unsigned int irq)
197{
198 return au1300_irq_to_gpio(irq);
199}
200
201static inline int gpio_request(unsigned int gpio, const char *label)
202{
203 return 0;
204}
205
206static inline void gpio_free(unsigned int gpio)
207{
208}
209
210static inline int gpio_set_debounce(unsigned gpio, unsigned debounce)
211{
212 return -ENOSYS;
213}
214
215static inline void gpio_unexport(unsigned gpio)
216{
217}
218
219static inline int gpio_export(unsigned gpio, bool direction_may_change)
220{
221 return -ENOSYS;
222}
223
224static inline int gpio_sysfs_set_active_low(unsigned gpio, int value)
225{
226 return -ENOSYS;
227}
228
229static inline int gpio_export_link(struct device *dev, const char *name,
230 unsigned gpio)
231{
232 return -ENOSYS;
233}
234
235#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
236
237#endif /* CONFIG_ALCHEMY_GPIOINT_AU1300 */
238
239#endif /* CONFIG GPIOLIB */
240
241#endif /* _GPIO_AU1300_H_ */
diff --git a/arch/mips/include/asm/mach-au1x00/gpio.h b/arch/mips/include/asm/mach-au1x00/gpio.h
index fcdc8c4809db..22e7ff17fc48 100644
--- a/arch/mips/include/asm/mach-au1x00/gpio.h
+++ b/arch/mips/include/asm/mach-au1x00/gpio.h
@@ -12,6 +12,7 @@
12 12
13#include <asm/mach-au1x00/au1000.h> 13#include <asm/mach-au1x00/au1000.h>
14#include <asm/mach-au1x00/gpio-au1000.h> 14#include <asm/mach-au1x00/gpio-au1000.h>
15#include <asm/mach-au1x00/gpio-au1300.h>
15 16
16/* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before 17/* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before
17 * SYS_PININPUTEN is written to at least once. On Au1550/Au1200/Au1300 this 18 * SYS_PININPUTEN is written to at least once. On Au1550/Au1200/Au1300 this
@@ -58,6 +59,8 @@ static inline int __au_irq_to_gpio(unsigned int irq)
58 switch (alchemy_get_cputype()) { 59 switch (alchemy_get_cputype()) {
59 case ALCHEMY_CPU_AU1000...ALCHEMY_CPU_AU1200: 60 case ALCHEMY_CPU_AU1000...ALCHEMY_CPU_AU1200:
60 return alchemy_irq_to_gpio(irq); 61 return alchemy_irq_to_gpio(irq);
62 case ALCHEMY_CPU_AU1300:
63 return au1300_irq_to_gpio(irq);
61 } 64 }
62 return -EINVAL; 65 return -EINVAL;
63} 66}
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
index 96a2391ad85b..5b8d15bb5fe8 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -13,6 +13,7 @@
13#define BCM6345_CPU_ID 0x6345 13#define BCM6345_CPU_ID 0x6345
14#define BCM6348_CPU_ID 0x6348 14#define BCM6348_CPU_ID 0x6348
15#define BCM6358_CPU_ID 0x6358 15#define BCM6358_CPU_ID 0x6358
16#define BCM6368_CPU_ID 0x6368
16 17
17void __init bcm63xx_cpu_init(void); 18void __init bcm63xx_cpu_init(void);
18u16 __bcm63xx_get_cpu_id(void); 19u16 __bcm63xx_get_cpu_id(void);
@@ -71,6 +72,19 @@ unsigned int bcm63xx_get_cpu_freq(void);
71# define BCMCPU_IS_6358() (0) 72# define BCMCPU_IS_6358() (0)
72#endif 73#endif
73 74
75#ifdef CONFIG_BCM63XX_CPU_6368
76# ifdef bcm63xx_get_cpu_id
77# undef bcm63xx_get_cpu_id
78# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
79# define BCMCPU_RUNTIME_DETECT
80# else
81# define bcm63xx_get_cpu_id() BCM6368_CPU_ID
82# endif
83# define BCMCPU_IS_6368() (bcm63xx_get_cpu_id() == BCM6368_CPU_ID)
84#else
85# define BCMCPU_IS_6368() (0)
86#endif
87
74#ifndef bcm63xx_get_cpu_id 88#ifndef bcm63xx_get_cpu_id
75#error "No CPU support configured" 89#error "No CPU support configured"
76#endif 90#endif
@@ -88,6 +102,7 @@ enum bcm63xx_regs_set {
88 RSET_UART1, 102 RSET_UART1,
89 RSET_GPIO, 103 RSET_GPIO,
90 RSET_SPI, 104 RSET_SPI,
105 RSET_SPI2,
91 RSET_UDC0, 106 RSET_UDC0,
92 RSET_OHCI0, 107 RSET_OHCI0,
93 RSET_OHCI_PRIV, 108 RSET_OHCI_PRIV,
@@ -98,10 +113,23 @@ enum bcm63xx_regs_set {
98 RSET_ENET0, 113 RSET_ENET0,
99 RSET_ENET1, 114 RSET_ENET1,
100 RSET_ENETDMA, 115 RSET_ENETDMA,
116 RSET_ENETDMAC,
117 RSET_ENETDMAS,
118 RSET_ENETSW,
101 RSET_EHCI0, 119 RSET_EHCI0,
102 RSET_SDRAM, 120 RSET_SDRAM,
103 RSET_MEMC, 121 RSET_MEMC,
104 RSET_DDR, 122 RSET_DDR,
123 RSET_M2M,
124 RSET_ATM,
125 RSET_XTM,
126 RSET_XTMDMA,
127 RSET_XTMDMAC,
128 RSET_XTMDMAS,
129 RSET_PCM,
130 RSET_PCMDMA,
131 RSET_PCMDMAC,
132 RSET_PCMDMAS,
105}; 133};
106 134
107#define RSET_DSL_LMEM_SIZE (64 * 1024 * 4) 135#define RSET_DSL_LMEM_SIZE (64 * 1024 * 4)
@@ -109,11 +137,18 @@ enum bcm63xx_regs_set {
109#define RSET_WDT_SIZE 12 137#define RSET_WDT_SIZE 12
110#define RSET_ENET_SIZE 2048 138#define RSET_ENET_SIZE 2048
111#define RSET_ENETDMA_SIZE 2048 139#define RSET_ENETDMA_SIZE 2048
140#define RSET_ENETSW_SIZE 65536
112#define RSET_UART_SIZE 24 141#define RSET_UART_SIZE 24
113#define RSET_UDC_SIZE 256 142#define RSET_UDC_SIZE 256
114#define RSET_OHCI_SIZE 256 143#define RSET_OHCI_SIZE 256
115#define RSET_EHCI_SIZE 256 144#define RSET_EHCI_SIZE 256
116#define RSET_PCMCIA_SIZE 12 145#define RSET_PCMCIA_SIZE 12
146#define RSET_M2M_SIZE 256
147#define RSET_ATM_SIZE 4096
148#define RSET_XTM_SIZE 10240
149#define RSET_XTMDMA_SIZE 256
150#define RSET_XTMDMAC_SIZE(chans) (16 * (chans))
151#define RSET_XTMDMAS_SIZE(chans) (16 * (chans))
117 152
118/* 153/*
119 * 6338 register sets base address 154 * 6338 register sets base address
@@ -127,6 +162,7 @@ enum bcm63xx_regs_set {
127#define BCM_6338_UART1_BASE (0xdeadbeef) 162#define BCM_6338_UART1_BASE (0xdeadbeef)
128#define BCM_6338_GPIO_BASE (0xfffe0400) 163#define BCM_6338_GPIO_BASE (0xfffe0400)
129#define BCM_6338_SPI_BASE (0xfffe0c00) 164#define BCM_6338_SPI_BASE (0xfffe0c00)
165#define BCM_6338_SPI2_BASE (0xdeadbeef)
130#define BCM_6338_UDC0_BASE (0xdeadbeef) 166#define BCM_6338_UDC0_BASE (0xdeadbeef)
131#define BCM_6338_USBDMA_BASE (0xfffe2400) 167#define BCM_6338_USBDMA_BASE (0xfffe2400)
132#define BCM_6338_OHCI0_BASE (0xdeadbeef) 168#define BCM_6338_OHCI0_BASE (0xdeadbeef)
@@ -136,15 +172,27 @@ enum bcm63xx_regs_set {
136#define BCM_6338_PCMCIA_BASE (0xdeadbeef) 172#define BCM_6338_PCMCIA_BASE (0xdeadbeef)
137#define BCM_6338_SDRAM_REGS_BASE (0xfffe3100) 173#define BCM_6338_SDRAM_REGS_BASE (0xfffe3100)
138#define BCM_6338_DSL_BASE (0xfffe1000) 174#define BCM_6338_DSL_BASE (0xfffe1000)
139#define BCM_6338_SAR_BASE (0xfffe2000)
140#define BCM_6338_UBUS_BASE (0xdeadbeef) 175#define BCM_6338_UBUS_BASE (0xdeadbeef)
141#define BCM_6338_ENET0_BASE (0xfffe2800) 176#define BCM_6338_ENET0_BASE (0xfffe2800)
142#define BCM_6338_ENET1_BASE (0xdeadbeef) 177#define BCM_6338_ENET1_BASE (0xdeadbeef)
143#define BCM_6338_ENETDMA_BASE (0xfffe2400) 178#define BCM_6338_ENETDMA_BASE (0xfffe2400)
179#define BCM_6338_ENETDMAC_BASE (0xfffe2500)
180#define BCM_6338_ENETDMAS_BASE (0xfffe2600)
181#define BCM_6338_ENETSW_BASE (0xdeadbeef)
144#define BCM_6338_EHCI0_BASE (0xdeadbeef) 182#define BCM_6338_EHCI0_BASE (0xdeadbeef)
145#define BCM_6338_SDRAM_BASE (0xfffe3100) 183#define BCM_6338_SDRAM_BASE (0xfffe3100)
146#define BCM_6338_MEMC_BASE (0xdeadbeef) 184#define BCM_6338_MEMC_BASE (0xdeadbeef)
147#define BCM_6338_DDR_BASE (0xdeadbeef) 185#define BCM_6338_DDR_BASE (0xdeadbeef)
186#define BCM_6338_M2M_BASE (0xdeadbeef)
187#define BCM_6338_ATM_BASE (0xfffe2000)
188#define BCM_6338_XTM_BASE (0xdeadbeef)
189#define BCM_6338_XTMDMA_BASE (0xdeadbeef)
190#define BCM_6338_XTMDMAC_BASE (0xdeadbeef)
191#define BCM_6338_XTMDMAS_BASE (0xdeadbeef)
192#define BCM_6338_PCM_BASE (0xdeadbeef)
193#define BCM_6338_PCMDMA_BASE (0xdeadbeef)
194#define BCM_6338_PCMDMAC_BASE (0xdeadbeef)
195#define BCM_6338_PCMDMAS_BASE (0xdeadbeef)
148 196
149/* 197/*
150 * 6345 register sets base address 198 * 6345 register sets base address
@@ -158,24 +206,37 @@ enum bcm63xx_regs_set {
158#define BCM_6345_UART1_BASE (0xdeadbeef) 206#define BCM_6345_UART1_BASE (0xdeadbeef)
159#define BCM_6345_GPIO_BASE (0xfffe0400) 207#define BCM_6345_GPIO_BASE (0xfffe0400)
160#define BCM_6345_SPI_BASE (0xdeadbeef) 208#define BCM_6345_SPI_BASE (0xdeadbeef)
209#define BCM_6345_SPI2_BASE (0xdeadbeef)
161#define BCM_6345_UDC0_BASE (0xdeadbeef) 210#define BCM_6345_UDC0_BASE (0xdeadbeef)
162#define BCM_6345_USBDMA_BASE (0xfffe2800) 211#define BCM_6345_USBDMA_BASE (0xfffe2800)
163#define BCM_6345_ENET0_BASE (0xfffe1800) 212#define BCM_6345_ENET0_BASE (0xfffe1800)
164#define BCM_6345_ENETDMA_BASE (0xfffe2800) 213#define BCM_6345_ENETDMA_BASE (0xfffe2800)
214#define BCM_6345_ENETDMAC_BASE (0xfffe2900)
215#define BCM_6345_ENETDMAS_BASE (0xfffe2a00)
216#define BCM_6345_ENETSW_BASE (0xdeadbeef)
165#define BCM_6345_PCMCIA_BASE (0xfffe2028) 217#define BCM_6345_PCMCIA_BASE (0xfffe2028)
166#define BCM_6345_MPI_BASE (0xdeadbeef) 218#define BCM_6345_MPI_BASE (0xfffe2000)
167#define BCM_6345_OHCI0_BASE (0xfffe2100) 219#define BCM_6345_OHCI0_BASE (0xfffe2100)
168#define BCM_6345_OHCI_PRIV_BASE (0xfffe2200) 220#define BCM_6345_OHCI_PRIV_BASE (0xfffe2200)
169#define BCM_6345_USBH_PRIV_BASE (0xdeadbeef) 221#define BCM_6345_USBH_PRIV_BASE (0xdeadbeef)
170#define BCM_6345_SDRAM_REGS_BASE (0xfffe2300) 222#define BCM_6345_SDRAM_REGS_BASE (0xfffe2300)
171#define BCM_6345_DSL_BASE (0xdeadbeef) 223#define BCM_6345_DSL_BASE (0xdeadbeef)
172#define BCM_6345_SAR_BASE (0xdeadbeef)
173#define BCM_6345_UBUS_BASE (0xdeadbeef) 224#define BCM_6345_UBUS_BASE (0xdeadbeef)
174#define BCM_6345_ENET1_BASE (0xdeadbeef) 225#define BCM_6345_ENET1_BASE (0xdeadbeef)
175#define BCM_6345_EHCI0_BASE (0xdeadbeef) 226#define BCM_6345_EHCI0_BASE (0xdeadbeef)
176#define BCM_6345_SDRAM_BASE (0xfffe2300) 227#define BCM_6345_SDRAM_BASE (0xfffe2300)
177#define BCM_6345_MEMC_BASE (0xdeadbeef) 228#define BCM_6345_MEMC_BASE (0xdeadbeef)
178#define BCM_6345_DDR_BASE (0xdeadbeef) 229#define BCM_6345_DDR_BASE (0xdeadbeef)
230#define BCM_6345_M2M_BASE (0xdeadbeef)
231#define BCM_6345_ATM_BASE (0xfffe4000)
232#define BCM_6345_XTM_BASE (0xdeadbeef)
233#define BCM_6345_XTMDMA_BASE (0xdeadbeef)
234#define BCM_6345_XTMDMAC_BASE (0xdeadbeef)
235#define BCM_6345_XTMDMAS_BASE (0xdeadbeef)
236#define BCM_6345_PCM_BASE (0xdeadbeef)
237#define BCM_6345_PCMDMA_BASE (0xdeadbeef)
238#define BCM_6345_PCMDMAC_BASE (0xdeadbeef)
239#define BCM_6345_PCMDMAS_BASE (0xdeadbeef)
179 240
180/* 241/*
181 * 6348 register sets base address 242 * 6348 register sets base address
@@ -188,6 +249,7 @@ enum bcm63xx_regs_set {
188#define BCM_6348_UART1_BASE (0xdeadbeef) 249#define BCM_6348_UART1_BASE (0xdeadbeef)
189#define BCM_6348_GPIO_BASE (0xfffe0400) 250#define BCM_6348_GPIO_BASE (0xfffe0400)
190#define BCM_6348_SPI_BASE (0xfffe0c00) 251#define BCM_6348_SPI_BASE (0xfffe0c00)
252#define BCM_6348_SPI2_BASE (0xdeadbeef)
191#define BCM_6348_UDC0_BASE (0xfffe1000) 253#define BCM_6348_UDC0_BASE (0xfffe1000)
192#define BCM_6348_OHCI0_BASE (0xfffe1b00) 254#define BCM_6348_OHCI0_BASE (0xfffe1b00)
193#define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00) 255#define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00)
@@ -195,14 +257,27 @@ enum bcm63xx_regs_set {
195#define BCM_6348_MPI_BASE (0xfffe2000) 257#define BCM_6348_MPI_BASE (0xfffe2000)
196#define BCM_6348_PCMCIA_BASE (0xfffe2054) 258#define BCM_6348_PCMCIA_BASE (0xfffe2054)
197#define BCM_6348_SDRAM_REGS_BASE (0xfffe2300) 259#define BCM_6348_SDRAM_REGS_BASE (0xfffe2300)
260#define BCM_6348_M2M_BASE (0xfffe2800)
198#define BCM_6348_DSL_BASE (0xfffe3000) 261#define BCM_6348_DSL_BASE (0xfffe3000)
199#define BCM_6348_ENET0_BASE (0xfffe6000) 262#define BCM_6348_ENET0_BASE (0xfffe6000)
200#define BCM_6348_ENET1_BASE (0xfffe6800) 263#define BCM_6348_ENET1_BASE (0xfffe6800)
201#define BCM_6348_ENETDMA_BASE (0xfffe7000) 264#define BCM_6348_ENETDMA_BASE (0xfffe7000)
265#define BCM_6348_ENETDMAC_BASE (0xfffe7100)
266#define BCM_6348_ENETDMAS_BASE (0xfffe7200)
267#define BCM_6348_ENETSW_BASE (0xdeadbeef)
202#define BCM_6348_EHCI0_BASE (0xdeadbeef) 268#define BCM_6348_EHCI0_BASE (0xdeadbeef)
203#define BCM_6348_SDRAM_BASE (0xfffe2300) 269#define BCM_6348_SDRAM_BASE (0xfffe2300)
204#define BCM_6348_MEMC_BASE (0xdeadbeef) 270#define BCM_6348_MEMC_BASE (0xdeadbeef)
205#define BCM_6348_DDR_BASE (0xdeadbeef) 271#define BCM_6348_DDR_BASE (0xdeadbeef)
272#define BCM_6348_ATM_BASE (0xfffe4000)
273#define BCM_6348_XTM_BASE (0xdeadbeef)
274#define BCM_6348_XTMDMA_BASE (0xdeadbeef)
275#define BCM_6348_XTMDMAC_BASE (0xdeadbeef)
276#define BCM_6348_XTMDMAS_BASE (0xdeadbeef)
277#define BCM_6348_PCM_BASE (0xdeadbeef)
278#define BCM_6348_PCMDMA_BASE (0xdeadbeef)
279#define BCM_6348_PCMDMAC_BASE (0xdeadbeef)
280#define BCM_6348_PCMDMAS_BASE (0xdeadbeef)
206 281
207/* 282/*
208 * 6358 register sets base address 283 * 6358 register sets base address
@@ -215,6 +290,7 @@ enum bcm63xx_regs_set {
215#define BCM_6358_UART1_BASE (0xfffe0120) 290#define BCM_6358_UART1_BASE (0xfffe0120)
216#define BCM_6358_GPIO_BASE (0xfffe0080) 291#define BCM_6358_GPIO_BASE (0xfffe0080)
217#define BCM_6358_SPI_BASE (0xdeadbeef) 292#define BCM_6358_SPI_BASE (0xdeadbeef)
293#define BCM_6358_SPI2_BASE (0xfffe0800)
218#define BCM_6358_UDC0_BASE (0xfffe0800) 294#define BCM_6358_UDC0_BASE (0xfffe0800)
219#define BCM_6358_OHCI0_BASE (0xfffe1400) 295#define BCM_6358_OHCI0_BASE (0xfffe1400)
220#define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef) 296#define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef)
@@ -222,214 +298,175 @@ enum bcm63xx_regs_set {
222#define BCM_6358_MPI_BASE (0xfffe1000) 298#define BCM_6358_MPI_BASE (0xfffe1000)
223#define BCM_6358_PCMCIA_BASE (0xfffe1054) 299#define BCM_6358_PCMCIA_BASE (0xfffe1054)
224#define BCM_6358_SDRAM_REGS_BASE (0xfffe2300) 300#define BCM_6358_SDRAM_REGS_BASE (0xfffe2300)
301#define BCM_6358_M2M_BASE (0xdeadbeef)
225#define BCM_6358_DSL_BASE (0xfffe3000) 302#define BCM_6358_DSL_BASE (0xfffe3000)
226#define BCM_6358_ENET0_BASE (0xfffe4000) 303#define BCM_6358_ENET0_BASE (0xfffe4000)
227#define BCM_6358_ENET1_BASE (0xfffe4800) 304#define BCM_6358_ENET1_BASE (0xfffe4800)
228#define BCM_6358_ENETDMA_BASE (0xfffe5000) 305#define BCM_6358_ENETDMA_BASE (0xfffe5000)
306#define BCM_6358_ENETDMAC_BASE (0xfffe5100)
307#define BCM_6358_ENETDMAS_BASE (0xfffe5200)
308#define BCM_6358_ENETSW_BASE (0xdeadbeef)
229#define BCM_6358_EHCI0_BASE (0xfffe1300) 309#define BCM_6358_EHCI0_BASE (0xfffe1300)
230#define BCM_6358_SDRAM_BASE (0xdeadbeef) 310#define BCM_6358_SDRAM_BASE (0xdeadbeef)
231#define BCM_6358_MEMC_BASE (0xfffe1200) 311#define BCM_6358_MEMC_BASE (0xfffe1200)
232#define BCM_6358_DDR_BASE (0xfffe12a0) 312#define BCM_6358_DDR_BASE (0xfffe12a0)
313#define BCM_6358_ATM_BASE (0xfffe2000)
314#define BCM_6358_XTM_BASE (0xdeadbeef)
315#define BCM_6358_XTMDMA_BASE (0xdeadbeef)
316#define BCM_6358_XTMDMAC_BASE (0xdeadbeef)
317#define BCM_6358_XTMDMAS_BASE (0xdeadbeef)
318#define BCM_6358_PCM_BASE (0xfffe1600)
319#define BCM_6358_PCMDMA_BASE (0xfffe1800)
320#define BCM_6358_PCMDMAC_BASE (0xfffe1900)
321#define BCM_6358_PCMDMAS_BASE (0xfffe1a00)
322
323
324/*
325 * 6368 register sets base address
326 */
327#define BCM_6368_DSL_LMEM_BASE (0xdeadbeef)
328#define BCM_6368_PERF_BASE (0xb0000000)
329#define BCM_6368_TIMER_BASE (0xb0000040)
330#define BCM_6368_WDT_BASE (0xb000005c)
331#define BCM_6368_UART0_BASE (0xb0000100)
332#define BCM_6368_UART1_BASE (0xb0000120)
333#define BCM_6368_GPIO_BASE (0xb0000080)
334#define BCM_6368_SPI_BASE (0xdeadbeef)
335#define BCM_6368_SPI2_BASE (0xb0000800)
336#define BCM_6368_UDC0_BASE (0xdeadbeef)
337#define BCM_6368_OHCI0_BASE (0xb0001600)
338#define BCM_6368_OHCI_PRIV_BASE (0xdeadbeef)
339#define BCM_6368_USBH_PRIV_BASE (0xb0001700)
340#define BCM_6368_MPI_BASE (0xb0001000)
341#define BCM_6368_PCMCIA_BASE (0xb0001054)
342#define BCM_6368_SDRAM_REGS_BASE (0xdeadbeef)
343#define BCM_6368_M2M_BASE (0xdeadbeef)
344#define BCM_6368_DSL_BASE (0xdeadbeef)
345#define BCM_6368_ENET0_BASE (0xdeadbeef)
346#define BCM_6368_ENET1_BASE (0xdeadbeef)
347#define BCM_6368_ENETDMA_BASE (0xb0006800)
348#define BCM_6368_ENETDMAC_BASE (0xb0006a00)
349#define BCM_6368_ENETDMAS_BASE (0xb0006c00)
350#define BCM_6368_ENETSW_BASE (0xb0f00000)
351#define BCM_6368_EHCI0_BASE (0xb0001500)
352#define BCM_6368_SDRAM_BASE (0xdeadbeef)
353#define BCM_6368_MEMC_BASE (0xb0001200)
354#define BCM_6368_DDR_BASE (0xb0001280)
355#define BCM_6368_ATM_BASE (0xdeadbeef)
356#define BCM_6368_XTM_BASE (0xb0001800)
357#define BCM_6368_XTMDMA_BASE (0xb0005000)
358#define BCM_6368_XTMDMAC_BASE (0xb0005200)
359#define BCM_6368_XTMDMAS_BASE (0xb0005400)
360#define BCM_6368_PCM_BASE (0xb0004000)
361#define BCM_6368_PCMDMA_BASE (0xb0005800)
362#define BCM_6368_PCMDMAC_BASE (0xb0005a00)
363#define BCM_6368_PCMDMAS_BASE (0xb0005c00)
233 364
234 365
235extern const unsigned long *bcm63xx_regs_base; 366extern const unsigned long *bcm63xx_regs_base;
236 367
368#define __GEN_RSET_BASE(__cpu, __rset) \
369 case RSET_## __rset : \
370 return BCM_## __cpu ##_## __rset ##_BASE;
371
372#define __GEN_RSET(__cpu) \
373 switch (set) { \
374 __GEN_RSET_BASE(__cpu, DSL_LMEM) \
375 __GEN_RSET_BASE(__cpu, PERF) \
376 __GEN_RSET_BASE(__cpu, TIMER) \
377 __GEN_RSET_BASE(__cpu, WDT) \
378 __GEN_RSET_BASE(__cpu, UART0) \
379 __GEN_RSET_BASE(__cpu, UART1) \
380 __GEN_RSET_BASE(__cpu, GPIO) \
381 __GEN_RSET_BASE(__cpu, SPI) \
382 __GEN_RSET_BASE(__cpu, SPI2) \
383 __GEN_RSET_BASE(__cpu, UDC0) \
384 __GEN_RSET_BASE(__cpu, OHCI0) \
385 __GEN_RSET_BASE(__cpu, OHCI_PRIV) \
386 __GEN_RSET_BASE(__cpu, USBH_PRIV) \
387 __GEN_RSET_BASE(__cpu, MPI) \
388 __GEN_RSET_BASE(__cpu, PCMCIA) \
389 __GEN_RSET_BASE(__cpu, DSL) \
390 __GEN_RSET_BASE(__cpu, ENET0) \
391 __GEN_RSET_BASE(__cpu, ENET1) \
392 __GEN_RSET_BASE(__cpu, ENETDMA) \
393 __GEN_RSET_BASE(__cpu, ENETDMAC) \
394 __GEN_RSET_BASE(__cpu, ENETDMAS) \
395 __GEN_RSET_BASE(__cpu, ENETSW) \
396 __GEN_RSET_BASE(__cpu, EHCI0) \
397 __GEN_RSET_BASE(__cpu, SDRAM) \
398 __GEN_RSET_BASE(__cpu, MEMC) \
399 __GEN_RSET_BASE(__cpu, DDR) \
400 __GEN_RSET_BASE(__cpu, M2M) \
401 __GEN_RSET_BASE(__cpu, ATM) \
402 __GEN_RSET_BASE(__cpu, XTM) \
403 __GEN_RSET_BASE(__cpu, XTMDMA) \
404 __GEN_RSET_BASE(__cpu, XTMDMAC) \
405 __GEN_RSET_BASE(__cpu, XTMDMAS) \
406 __GEN_RSET_BASE(__cpu, PCM) \
407 __GEN_RSET_BASE(__cpu, PCMDMA) \
408 __GEN_RSET_BASE(__cpu, PCMDMAC) \
409 __GEN_RSET_BASE(__cpu, PCMDMAS) \
410 }
411
412#define __GEN_CPU_REGS_TABLE(__cpu) \
413 [RSET_DSL_LMEM] = BCM_## __cpu ##_DSL_LMEM_BASE, \
414 [RSET_PERF] = BCM_## __cpu ##_PERF_BASE, \
415 [RSET_TIMER] = BCM_## __cpu ##_TIMER_BASE, \
416 [RSET_WDT] = BCM_## __cpu ##_WDT_BASE, \
417 [RSET_UART0] = BCM_## __cpu ##_UART0_BASE, \
418 [RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \
419 [RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \
420 [RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \
421 [RSET_SPI2] = BCM_## __cpu ##_SPI2_BASE, \
422 [RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \
423 [RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \
424 [RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \
425 [RSET_USBH_PRIV] = BCM_## __cpu ##_USBH_PRIV_BASE, \
426 [RSET_MPI] = BCM_## __cpu ##_MPI_BASE, \
427 [RSET_PCMCIA] = BCM_## __cpu ##_PCMCIA_BASE, \
428 [RSET_DSL] = BCM_## __cpu ##_DSL_BASE, \
429 [RSET_ENET0] = BCM_## __cpu ##_ENET0_BASE, \
430 [RSET_ENET1] = BCM_## __cpu ##_ENET1_BASE, \
431 [RSET_ENETDMA] = BCM_## __cpu ##_ENETDMA_BASE, \
432 [RSET_ENETDMAC] = BCM_## __cpu ##_ENETDMAC_BASE, \
433 [RSET_ENETDMAS] = BCM_## __cpu ##_ENETDMAS_BASE, \
434 [RSET_ENETSW] = BCM_## __cpu ##_ENETSW_BASE, \
435 [RSET_EHCI0] = BCM_## __cpu ##_EHCI0_BASE, \
436 [RSET_SDRAM] = BCM_## __cpu ##_SDRAM_BASE, \
437 [RSET_MEMC] = BCM_## __cpu ##_MEMC_BASE, \
438 [RSET_DDR] = BCM_## __cpu ##_DDR_BASE, \
439 [RSET_M2M] = BCM_## __cpu ##_M2M_BASE, \
440 [RSET_ATM] = BCM_## __cpu ##_ATM_BASE, \
441 [RSET_XTM] = BCM_## __cpu ##_XTM_BASE, \
442 [RSET_XTMDMA] = BCM_## __cpu ##_XTMDMA_BASE, \
443 [RSET_XTMDMAC] = BCM_## __cpu ##_XTMDMAC_BASE, \
444 [RSET_XTMDMAS] = BCM_## __cpu ##_XTMDMAS_BASE, \
445 [RSET_PCM] = BCM_## __cpu ##_PCM_BASE, \
446 [RSET_PCMDMA] = BCM_## __cpu ##_PCMDMA_BASE, \
447 [RSET_PCMDMAC] = BCM_## __cpu ##_PCMDMAC_BASE, \
448 [RSET_PCMDMAS] = BCM_## __cpu ##_PCMDMAS_BASE, \
449
450
237static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set) 451static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
238{ 452{
239#ifdef BCMCPU_RUNTIME_DETECT 453#ifdef BCMCPU_RUNTIME_DETECT
240 return bcm63xx_regs_base[set]; 454 return bcm63xx_regs_base[set];
241#else 455#else
242#ifdef CONFIG_BCM63XX_CPU_6338 456#ifdef CONFIG_BCM63XX_CPU_6338
243 switch (set) { 457 __GEN_RSET(6338)
244 case RSET_DSL_LMEM:
245 return BCM_6338_DSL_LMEM_BASE;
246 case RSET_PERF:
247 return BCM_6338_PERF_BASE;
248 case RSET_TIMER:
249 return BCM_6338_TIMER_BASE;
250 case RSET_WDT:
251 return BCM_6338_WDT_BASE;
252 case RSET_UART0:
253 return BCM_6338_UART0_BASE;
254 case RSET_UART1:
255 return BCM_6338_UART1_BASE;
256 case RSET_GPIO:
257 return BCM_6338_GPIO_BASE;
258 case RSET_SPI:
259 return BCM_6338_SPI_BASE;
260 case RSET_UDC0:
261 return BCM_6338_UDC0_BASE;
262 case RSET_OHCI0:
263 return BCM_6338_OHCI0_BASE;
264 case RSET_OHCI_PRIV:
265 return BCM_6338_OHCI_PRIV_BASE;
266 case RSET_USBH_PRIV:
267 return BCM_6338_USBH_PRIV_BASE;
268 case RSET_MPI:
269 return BCM_6338_MPI_BASE;
270 case RSET_PCMCIA:
271 return BCM_6338_PCMCIA_BASE;
272 case RSET_DSL:
273 return BCM_6338_DSL_BASE;
274 case RSET_ENET0:
275 return BCM_6338_ENET0_BASE;
276 case RSET_ENET1:
277 return BCM_6338_ENET1_BASE;
278 case RSET_ENETDMA:
279 return BCM_6338_ENETDMA_BASE;
280 case RSET_EHCI0:
281 return BCM_6338_EHCI0_BASE;
282 case RSET_SDRAM:
283 return BCM_6338_SDRAM_BASE;
284 case RSET_MEMC:
285 return BCM_6338_MEMC_BASE;
286 case RSET_DDR:
287 return BCM_6338_DDR_BASE;
288 }
289#endif 458#endif
290#ifdef CONFIG_BCM63XX_CPU_6345 459#ifdef CONFIG_BCM63XX_CPU_6345
291 switch (set) { 460 __GEN_RSET(6345)
292 case RSET_DSL_LMEM:
293 return BCM_6345_DSL_LMEM_BASE;
294 case RSET_PERF:
295 return BCM_6345_PERF_BASE;
296 case RSET_TIMER:
297 return BCM_6345_TIMER_BASE;
298 case RSET_WDT:
299 return BCM_6345_WDT_BASE;
300 case RSET_UART0:
301 return BCM_6345_UART0_BASE;
302 case RSET_UART1:
303 return BCM_6345_UART1_BASE;
304 case RSET_GPIO:
305 return BCM_6345_GPIO_BASE;
306 case RSET_SPI:
307 return BCM_6345_SPI_BASE;
308 case RSET_UDC0:
309 return BCM_6345_UDC0_BASE;
310 case RSET_OHCI0:
311 return BCM_6345_OHCI0_BASE;
312 case RSET_OHCI_PRIV:
313 return BCM_6345_OHCI_PRIV_BASE;
314 case RSET_USBH_PRIV:
315 return BCM_6345_USBH_PRIV_BASE;
316 case RSET_MPI:
317 return BCM_6345_MPI_BASE;
318 case RSET_PCMCIA:
319 return BCM_6345_PCMCIA_BASE;
320 case RSET_DSL:
321 return BCM_6345_DSL_BASE;
322 case RSET_ENET0:
323 return BCM_6345_ENET0_BASE;
324 case RSET_ENET1:
325 return BCM_6345_ENET1_BASE;
326 case RSET_ENETDMA:
327 return BCM_6345_ENETDMA_BASE;
328 case RSET_EHCI0:
329 return BCM_6345_EHCI0_BASE;
330 case RSET_SDRAM:
331 return BCM_6345_SDRAM_BASE;
332 case RSET_MEMC:
333 return BCM_6345_MEMC_BASE;
334 case RSET_DDR:
335 return BCM_6345_DDR_BASE;
336 }
337#endif 461#endif
338#ifdef CONFIG_BCM63XX_CPU_6348 462#ifdef CONFIG_BCM63XX_CPU_6348
339 switch (set) { 463 __GEN_RSET(6348)
340 case RSET_DSL_LMEM:
341 return BCM_6348_DSL_LMEM_BASE;
342 case RSET_PERF:
343 return BCM_6348_PERF_BASE;
344 case RSET_TIMER:
345 return BCM_6348_TIMER_BASE;
346 case RSET_WDT:
347 return BCM_6348_WDT_BASE;
348 case RSET_UART0:
349 return BCM_6348_UART0_BASE;
350 case RSET_UART1:
351 return BCM_6348_UART1_BASE;
352 case RSET_GPIO:
353 return BCM_6348_GPIO_BASE;
354 case RSET_SPI:
355 return BCM_6348_SPI_BASE;
356 case RSET_UDC0:
357 return BCM_6348_UDC0_BASE;
358 case RSET_OHCI0:
359 return BCM_6348_OHCI0_BASE;
360 case RSET_OHCI_PRIV:
361 return BCM_6348_OHCI_PRIV_BASE;
362 case RSET_USBH_PRIV:
363 return BCM_6348_USBH_PRIV_BASE;
364 case RSET_MPI:
365 return BCM_6348_MPI_BASE;
366 case RSET_PCMCIA:
367 return BCM_6348_PCMCIA_BASE;
368 case RSET_DSL:
369 return BCM_6348_DSL_BASE;
370 case RSET_ENET0:
371 return BCM_6348_ENET0_BASE;
372 case RSET_ENET1:
373 return BCM_6348_ENET1_BASE;
374 case RSET_ENETDMA:
375 return BCM_6348_ENETDMA_BASE;
376 case RSET_EHCI0:
377 return BCM_6348_EHCI0_BASE;
378 case RSET_SDRAM:
379 return BCM_6348_SDRAM_BASE;
380 case RSET_MEMC:
381 return BCM_6348_MEMC_BASE;
382 case RSET_DDR:
383 return BCM_6348_DDR_BASE;
384 }
385#endif 464#endif
386#ifdef CONFIG_BCM63XX_CPU_6358 465#ifdef CONFIG_BCM63XX_CPU_6358
387 switch (set) { 466 __GEN_RSET(6358)
388 case RSET_DSL_LMEM: 467#endif
389 return BCM_6358_DSL_LMEM_BASE; 468#ifdef CONFIG_BCM63XX_CPU_6368
390 case RSET_PERF: 469 __GEN_RSET(6368)
391 return BCM_6358_PERF_BASE;
392 case RSET_TIMER:
393 return BCM_6358_TIMER_BASE;
394 case RSET_WDT:
395 return BCM_6358_WDT_BASE;
396 case RSET_UART0:
397 return BCM_6358_UART0_BASE;
398 case RSET_UART1:
399 return BCM_6358_UART1_BASE;
400 case RSET_GPIO:
401 return BCM_6358_GPIO_BASE;
402 case RSET_SPI:
403 return BCM_6358_SPI_BASE;
404 case RSET_UDC0:
405 return BCM_6358_UDC0_BASE;
406 case RSET_OHCI0:
407 return BCM_6358_OHCI0_BASE;
408 case RSET_OHCI_PRIV:
409 return BCM_6358_OHCI_PRIV_BASE;
410 case RSET_USBH_PRIV:
411 return BCM_6358_USBH_PRIV_BASE;
412 case RSET_MPI:
413 return BCM_6358_MPI_BASE;
414 case RSET_PCMCIA:
415 return BCM_6358_PCMCIA_BASE;
416 case RSET_ENET0:
417 return BCM_6358_ENET0_BASE;
418 case RSET_ENET1:
419 return BCM_6358_ENET1_BASE;
420 case RSET_ENETDMA:
421 return BCM_6358_ENETDMA_BASE;
422 case RSET_DSL:
423 return BCM_6358_DSL_BASE;
424 case RSET_EHCI0:
425 return BCM_6358_EHCI0_BASE;
426 case RSET_SDRAM:
427 return BCM_6358_SDRAM_BASE;
428 case RSET_MEMC:
429 return BCM_6358_MEMC_BASE;
430 case RSET_DDR:
431 return BCM_6358_DDR_BASE;
432 }
433#endif 470#endif
434#endif 471#endif
435 /* unreached */ 472 /* unreached */
@@ -449,75 +486,114 @@ enum bcm63xx_irq {
449 IRQ_ENET_PHY, 486 IRQ_ENET_PHY,
450 IRQ_OHCI0, 487 IRQ_OHCI0,
451 IRQ_EHCI0, 488 IRQ_EHCI0,
452 IRQ_PCMCIA0,
453 IRQ_ENET0_RXDMA, 489 IRQ_ENET0_RXDMA,
454 IRQ_ENET0_TXDMA, 490 IRQ_ENET0_TXDMA,
455 IRQ_ENET1_RXDMA, 491 IRQ_ENET1_RXDMA,
456 IRQ_ENET1_TXDMA, 492 IRQ_ENET1_TXDMA,
457 IRQ_PCI, 493 IRQ_PCI,
458 IRQ_PCMCIA, 494 IRQ_PCMCIA,
495 IRQ_ATM,
496 IRQ_ENETSW_RXDMA0,
497 IRQ_ENETSW_RXDMA1,
498 IRQ_ENETSW_RXDMA2,
499 IRQ_ENETSW_RXDMA3,
500 IRQ_ENETSW_TXDMA0,
501 IRQ_ENETSW_TXDMA1,
502 IRQ_ENETSW_TXDMA2,
503 IRQ_ENETSW_TXDMA3,
504 IRQ_XTM,
505 IRQ_XTM_DMA0,
459}; 506};
460 507
461/* 508/*
462 * 6338 irqs 509 * 6338 irqs
463 */ 510 */
464#define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 511#define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
465#define BCM_6338_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
466#define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 512#define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
467#define BCM_6338_DG_IRQ (IRQ_INTERNAL_BASE + 4) 513#define BCM_6338_UART1_IRQ 0
468#define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5) 514#define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5)
469#define BCM_6338_ATM_IRQ (IRQ_INTERNAL_BASE + 6)
470#define BCM_6338_UDC0_IRQ (IRQ_INTERNAL_BASE + 7)
471#define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 515#define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
516#define BCM_6338_ENET1_IRQ 0
472#define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 517#define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
473#define BCM_6338_SDRAM_IRQ (IRQ_INTERNAL_BASE + 10) 518#define BCM_6338_OHCI0_IRQ 0
474#define BCM_6338_USB_CNTL_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 11) 519#define BCM_6338_EHCI0_IRQ 0
475#define BCM_6338_USB_CNTL_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 12)
476#define BCM_6338_USB_BULK_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13)
477#define BCM_6338_USB_BULK_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 14)
478#define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) 520#define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
479#define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) 521#define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
480#define BCM_6338_SDIO_IRQ (IRQ_INTERNAL_BASE + 17) 522#define BCM_6338_ENET1_RXDMA_IRQ 0
523#define BCM_6338_ENET1_TXDMA_IRQ 0
524#define BCM_6338_PCI_IRQ 0
525#define BCM_6338_PCMCIA_IRQ 0
526#define BCM_6338_ATM_IRQ 0
527#define BCM_6338_ENETSW_RXDMA0_IRQ 0
528#define BCM_6338_ENETSW_RXDMA1_IRQ 0
529#define BCM_6338_ENETSW_RXDMA2_IRQ 0
530#define BCM_6338_ENETSW_RXDMA3_IRQ 0
531#define BCM_6338_ENETSW_TXDMA0_IRQ 0
532#define BCM_6338_ENETSW_TXDMA1_IRQ 0
533#define BCM_6338_ENETSW_TXDMA2_IRQ 0
534#define BCM_6338_ENETSW_TXDMA3_IRQ 0
535#define BCM_6338_XTM_IRQ 0
536#define BCM_6338_XTM_DMA0_IRQ 0
481 537
482/* 538/*
483 * 6345 irqs 539 * 6345 irqs
484 */ 540 */
485#define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 541#define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
486#define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 542#define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
543#define BCM_6345_UART1_IRQ 0
487#define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3) 544#define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3)
488#define BCM_6345_ATM_IRQ (IRQ_INTERNAL_BASE + 4)
489#define BCM_6345_USB_IRQ (IRQ_INTERNAL_BASE + 5)
490#define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 545#define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
546#define BCM_6345_ENET1_IRQ 0
491#define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) 547#define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
548#define BCM_6345_OHCI0_IRQ 0
549#define BCM_6345_EHCI0_IRQ 0
492#define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1) 550#define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1)
493#define BCM_6345_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 2) 551#define BCM_6345_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 2)
494#define BCM_6345_EBI_RX_IRQ (IRQ_INTERNAL_BASE + 13 + 5) 552#define BCM_6345_ENET1_RXDMA_IRQ 0
495#define BCM_6345_EBI_TX_IRQ (IRQ_INTERNAL_BASE + 13 + 6) 553#define BCM_6345_ENET1_TXDMA_IRQ 0
496#define BCM_6345_RESERVED_RX_IRQ (IRQ_INTERNAL_BASE + 13 + 9) 554#define BCM_6345_PCI_IRQ 0
497#define BCM_6345_RESERVED_TX_IRQ (IRQ_INTERNAL_BASE + 13 + 10) 555#define BCM_6345_PCMCIA_IRQ 0
498#define BCM_6345_USB_BULK_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 13) 556#define BCM_6345_ATM_IRQ 0
499#define BCM_6345_USB_BULK_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 14) 557#define BCM_6345_ENETSW_RXDMA0_IRQ 0
500#define BCM_6345_USB_CNTL_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 15) 558#define BCM_6345_ENETSW_RXDMA1_IRQ 0
501#define BCM_6345_USB_CNTL_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 16) 559#define BCM_6345_ENETSW_RXDMA2_IRQ 0
502#define BCM_6345_USB_ISO_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 17) 560#define BCM_6345_ENETSW_RXDMA3_IRQ 0
503#define BCM_6345_USB_ISO_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 18) 561#define BCM_6345_ENETSW_TXDMA0_IRQ 0
562#define BCM_6345_ENETSW_TXDMA1_IRQ 0
563#define BCM_6345_ENETSW_TXDMA2_IRQ 0
564#define BCM_6345_ENETSW_TXDMA3_IRQ 0
565#define BCM_6345_XTM_IRQ 0
566#define BCM_6345_XTM_DMA0_IRQ 0
504 567
505/* 568/*
506 * 6348 irqs 569 * 6348 irqs
507 */ 570 */
508#define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 571#define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
509#define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 572#define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
573#define BCM_6348_UART1_IRQ 0
510#define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4) 574#define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
511#define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7)
512#define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 575#define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
576#define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7)
513#define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 577#define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
514#define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12) 578#define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12)
579#define BCM_6348_EHCI0_IRQ 0
515#define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20) 580#define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20)
516#define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21) 581#define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21)
517#define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22) 582#define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22)
518#define BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23) 583#define BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23)
519#define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
520#define BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24) 584#define BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24)
585#define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
586#define BCM_6348_ATM_IRQ (IRQ_INTERNAL_BASE + 5)
587#define BCM_6348_ENETSW_RXDMA0_IRQ 0
588#define BCM_6348_ENETSW_RXDMA1_IRQ 0
589#define BCM_6348_ENETSW_RXDMA2_IRQ 0
590#define BCM_6348_ENETSW_RXDMA3_IRQ 0
591#define BCM_6348_ENETSW_TXDMA0_IRQ 0
592#define BCM_6348_ENETSW_TXDMA1_IRQ 0
593#define BCM_6348_ENETSW_TXDMA2_IRQ 0
594#define BCM_6348_ENETSW_TXDMA3_IRQ 0
595#define BCM_6348_XTM_IRQ 0
596#define BCM_6348_XTM_DMA0_IRQ 0
521 597
522/* 598/*
523 * 6358 irqs 599 * 6358 irqs
@@ -525,21 +601,108 @@ enum bcm63xx_irq {
525#define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 601#define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
526#define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 602#define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
527#define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3) 603#define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
528#define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) 604#define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29)
529#define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
530#define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 605#define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
606#define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
531#define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 607#define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
608#define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
532#define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10) 609#define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
533#define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) 610#define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
534#define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) 611#define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
535#define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17) 612#define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17)
536#define BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18) 613#define BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18)
537#define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29)
538#define BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31) 614#define BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31)
539#define BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24) 615#define BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
616#define BCM_6358_ATM_IRQ (IRQ_INTERNAL_BASE + 19)
617#define BCM_6358_ENETSW_RXDMA0_IRQ 0
618#define BCM_6358_ENETSW_RXDMA1_IRQ 0
619#define BCM_6358_ENETSW_RXDMA2_IRQ 0
620#define BCM_6358_ENETSW_RXDMA3_IRQ 0
621#define BCM_6358_ENETSW_TXDMA0_IRQ 0
622#define BCM_6358_ENETSW_TXDMA1_IRQ 0
623#define BCM_6358_ENETSW_TXDMA2_IRQ 0
624#define BCM_6358_ENETSW_TXDMA3_IRQ 0
625#define BCM_6358_XTM_IRQ 0
626#define BCM_6358_XTM_DMA0_IRQ 0
627
628#define BCM_6358_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 23)
629#define BCM_6358_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 24)
630#define BCM_6358_EXT_IRQ0 (IRQ_INTERNAL_BASE + 25)
631#define BCM_6358_EXT_IRQ1 (IRQ_INTERNAL_BASE + 26)
632#define BCM_6358_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27)
633#define BCM_6358_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28)
634
635/*
636 * 6368 irqs
637 */
638#define BCM_6368_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
639
640#define BCM_6368_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
641#define BCM_6368_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
642#define BCM_6368_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
643#define BCM_6368_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
644#define BCM_6368_ENET0_IRQ 0
645#define BCM_6368_ENET1_IRQ 0
646#define BCM_6368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 15)
647#define BCM_6368_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
648#define BCM_6368_EHCI0_IRQ (IRQ_INTERNAL_BASE + 7)
649#define BCM_6368_PCMCIA_IRQ 0
650#define BCM_6368_ENET0_RXDMA_IRQ 0
651#define BCM_6368_ENET0_TXDMA_IRQ 0
652#define BCM_6368_ENET1_RXDMA_IRQ 0
653#define BCM_6368_ENET1_TXDMA_IRQ 0
654#define BCM_6368_PCI_IRQ (IRQ_INTERNAL_BASE + 13)
655#define BCM_6368_ATM_IRQ 0
656#define BCM_6368_ENETSW_RXDMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 0)
657#define BCM_6368_ENETSW_RXDMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 1)
658#define BCM_6368_ENETSW_RXDMA2_IRQ (BCM_6368_HIGH_IRQ_BASE + 2)
659#define BCM_6368_ENETSW_RXDMA3_IRQ (BCM_6368_HIGH_IRQ_BASE + 3)
660#define BCM_6368_ENETSW_TXDMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 4)
661#define BCM_6368_ENETSW_TXDMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 5)
662#define BCM_6368_ENETSW_TXDMA2_IRQ (BCM_6368_HIGH_IRQ_BASE + 6)
663#define BCM_6368_ENETSW_TXDMA3_IRQ (BCM_6368_HIGH_IRQ_BASE + 7)
664#define BCM_6368_XTM_IRQ (IRQ_INTERNAL_BASE + 11)
665#define BCM_6368_XTM_DMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 8)
666
667#define BCM_6368_PCM_DMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 30)
668#define BCM_6368_PCM_DMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 31)
669#define BCM_6368_EXT_IRQ0 (IRQ_INTERNAL_BASE + 20)
670#define BCM_6368_EXT_IRQ1 (IRQ_INTERNAL_BASE + 21)
671#define BCM_6368_EXT_IRQ2 (IRQ_INTERNAL_BASE + 22)
672#define BCM_6368_EXT_IRQ3 (IRQ_INTERNAL_BASE + 23)
673#define BCM_6368_EXT_IRQ4 (IRQ_INTERNAL_BASE + 24)
674#define BCM_6368_EXT_IRQ5 (IRQ_INTERNAL_BASE + 25)
540 675
541extern const int *bcm63xx_irqs; 676extern const int *bcm63xx_irqs;
542 677
678#define __GEN_CPU_IRQ_TABLE(__cpu) \
679 [IRQ_TIMER] = BCM_## __cpu ##_TIMER_IRQ, \
680 [IRQ_UART0] = BCM_## __cpu ##_UART0_IRQ, \
681 [IRQ_UART1] = BCM_## __cpu ##_UART1_IRQ, \
682 [IRQ_DSL] = BCM_## __cpu ##_DSL_IRQ, \
683 [IRQ_ENET0] = BCM_## __cpu ##_ENET0_IRQ, \
684 [IRQ_ENET1] = BCM_## __cpu ##_ENET1_IRQ, \
685 [IRQ_ENET_PHY] = BCM_## __cpu ##_ENET_PHY_IRQ, \
686 [IRQ_OHCI0] = BCM_## __cpu ##_OHCI0_IRQ, \
687 [IRQ_EHCI0] = BCM_## __cpu ##_EHCI0_IRQ, \
688 [IRQ_ENET0_RXDMA] = BCM_## __cpu ##_ENET0_RXDMA_IRQ, \
689 [IRQ_ENET0_TXDMA] = BCM_## __cpu ##_ENET0_TXDMA_IRQ, \
690 [IRQ_ENET1_RXDMA] = BCM_## __cpu ##_ENET1_RXDMA_IRQ, \
691 [IRQ_ENET1_TXDMA] = BCM_## __cpu ##_ENET1_TXDMA_IRQ, \
692 [IRQ_PCI] = BCM_## __cpu ##_PCI_IRQ, \
693 [IRQ_PCMCIA] = BCM_## __cpu ##_PCMCIA_IRQ, \
694 [IRQ_ATM] = BCM_## __cpu ##_ATM_IRQ, \
695 [IRQ_ENETSW_RXDMA0] = BCM_## __cpu ##_ENETSW_RXDMA0_IRQ, \
696 [IRQ_ENETSW_RXDMA1] = BCM_## __cpu ##_ENETSW_RXDMA1_IRQ, \
697 [IRQ_ENETSW_RXDMA2] = BCM_## __cpu ##_ENETSW_RXDMA2_IRQ, \
698 [IRQ_ENETSW_RXDMA3] = BCM_## __cpu ##_ENETSW_RXDMA3_IRQ, \
699 [IRQ_ENETSW_TXDMA0] = BCM_## __cpu ##_ENETSW_TXDMA0_IRQ, \
700 [IRQ_ENETSW_TXDMA1] = BCM_## __cpu ##_ENETSW_TXDMA1_IRQ, \
701 [IRQ_ENETSW_TXDMA2] = BCM_## __cpu ##_ENETSW_TXDMA2_IRQ, \
702 [IRQ_ENETSW_TXDMA3] = BCM_## __cpu ##_ENETSW_TXDMA3_IRQ, \
703 [IRQ_XTM] = BCM_## __cpu ##_XTM_IRQ, \
704 [IRQ_XTM_DMA0] = BCM_## __cpu ##_XTM_DMA0_IRQ, \
705
543static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq) 706static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
544{ 707{
545 return bcm63xx_irqs[irq]; 708 return bcm63xx_irqs[irq];
@@ -550,4 +713,8 @@ static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
550 */ 713 */
551unsigned int bcm63xx_get_memory_size(void); 714unsigned int bcm63xx_get_memory_size(void);
552 715
716void bcm63xx_machine_halt(void);
717
718void bcm63xx_machine_reboot(void);
719
553#endif /* !BCM63XX_CPU_H_ */ 720#endif /* !BCM63XX_CPU_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
index 3999ec0aa7f5..3d5de96d4036 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
@@ -14,6 +14,8 @@ static inline unsigned long bcm63xx_gpio_count(void)
14 return 8; 14 return 8;
15 case BCM6345_CPU_ID: 15 case BCM6345_CPU_ID:
16 return 16; 16 return 16;
17 case BCM6368_CPU_ID:
18 return 38;
17 case BCM6348_CPU_ID: 19 case BCM6348_CPU_ID:
18 default: 20 default:
19 return 37; 21 return 37;
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
index 91180fac6ed9..72477a6441dd 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
@@ -49,9 +49,11 @@
49#define bcm_readb(a) (*(volatile unsigned char *) BCM_REGS_VA(a)) 49#define bcm_readb(a) (*(volatile unsigned char *) BCM_REGS_VA(a))
50#define bcm_readw(a) (*(volatile unsigned short *) BCM_REGS_VA(a)) 50#define bcm_readw(a) (*(volatile unsigned short *) BCM_REGS_VA(a))
51#define bcm_readl(a) (*(volatile unsigned int *) BCM_REGS_VA(a)) 51#define bcm_readl(a) (*(volatile unsigned int *) BCM_REGS_VA(a))
52#define bcm_readq(a) (*(volatile u64 *) BCM_REGS_VA(a))
52#define bcm_writeb(v, a) (*(volatile unsigned char *) BCM_REGS_VA((a)) = (v)) 53#define bcm_writeb(v, a) (*(volatile unsigned char *) BCM_REGS_VA((a)) = (v))
53#define bcm_writew(v, a) (*(volatile unsigned short *) BCM_REGS_VA((a)) = (v)) 54#define bcm_writew(v, a) (*(volatile unsigned short *) BCM_REGS_VA((a)) = (v))
54#define bcm_writel(v, a) (*(volatile unsigned int *) BCM_REGS_VA((a)) = (v)) 55#define bcm_writel(v, a) (*(volatile unsigned int *) BCM_REGS_VA((a)) = (v))
56#define bcm_writeq(v, a) (*(volatile u64 *) BCM_REGS_VA((a)) = (v))
55 57
56/* 58/*
57 * IO helpers to access register set for current CPU 59 * IO helpers to access register set for current CPU
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h
index 5f95577c8213..0c3074b871b8 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h
@@ -3,13 +3,11 @@
3 3
4#include <bcm63xx_cpu.h> 4#include <bcm63xx_cpu.h>
5 5
6#define IRQ_MIPS_BASE 0
7#define IRQ_INTERNAL_BASE 8 6#define IRQ_INTERNAL_BASE 8
8 7#define IRQ_EXTERNAL_BASE 100
9#define IRQ_EXT_BASE (IRQ_MIPS_BASE + 3) 8#define IRQ_EXT_0 (IRQ_EXTERNAL_BASE + 0)
10#define IRQ_EXT_0 (IRQ_EXT_BASE + 0) 9#define IRQ_EXT_1 (IRQ_EXTERNAL_BASE + 1)
11#define IRQ_EXT_1 (IRQ_EXT_BASE + 1) 10#define IRQ_EXT_2 (IRQ_EXTERNAL_BASE + 2)
12#define IRQ_EXT_2 (IRQ_EXT_BASE + 2) 11#define IRQ_EXT_3 (IRQ_EXTERNAL_BASE + 3)
13#define IRQ_EXT_3 (IRQ_EXT_BASE + 3)
14 12
15#endif /* ! BCM63XX_IRQ_H_ */ 13#endif /* ! BCM63XX_IRQ_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index 0ed5230243c9..94d4faad29a1 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -83,30 +83,86 @@
83 CKCTL_6358_USBSU_EN | \ 83 CKCTL_6358_USBSU_EN | \
84 CKCTL_6358_EPHY_EN) 84 CKCTL_6358_EPHY_EN)
85 85
86#define CKCTL_6368_VDSL_QPROC_EN (1 << 2)
87#define CKCTL_6368_VDSL_AFE_EN (1 << 3)
88#define CKCTL_6368_VDSL_BONDING_EN (1 << 4)
89#define CKCTL_6368_VDSL_EN (1 << 5)
90#define CKCTL_6368_PHYMIPS_EN (1 << 6)
91#define CKCTL_6368_SWPKT_USB_EN (1 << 7)
92#define CKCTL_6368_SWPKT_SAR_EN (1 << 8)
93#define CKCTL_6368_SPI_CLK_EN (1 << 9)
94#define CKCTL_6368_USBD_CLK_EN (1 << 10)
95#define CKCTL_6368_SAR_CLK_EN (1 << 11)
96#define CKCTL_6368_ROBOSW_CLK_EN (1 << 12)
97#define CKCTL_6368_UTOPIA_CLK_EN (1 << 13)
98#define CKCTL_6368_PCM_CLK_EN (1 << 14)
99#define CKCTL_6368_USBH_CLK_EN (1 << 15)
100#define CKCTL_6368_DISABLE_GLESS_EN (1 << 16)
101#define CKCTL_6368_NAND_CLK_EN (1 << 17)
102#define CKCTL_6368_IPSEC_CLK_EN (1 << 17)
103
104#define CKCTL_6368_ALL_SAFE_EN (CKCTL_6368_SWPKT_USB_EN | \
105 CKCTL_6368_SWPKT_SAR_EN | \
106 CKCTL_6368_SPI_CLK_EN | \
107 CKCTL_6368_USBD_CLK_EN | \
108 CKCTL_6368_SAR_CLK_EN | \
109 CKCTL_6368_ROBOSW_CLK_EN | \
110 CKCTL_6368_UTOPIA_CLK_EN | \
111 CKCTL_6368_PCM_CLK_EN | \
112 CKCTL_6368_USBH_CLK_EN | \
113 CKCTL_6368_DISABLE_GLESS_EN | \
114 CKCTL_6368_NAND_CLK_EN | \
115 CKCTL_6368_IPSEC_CLK_EN)
116
86/* System PLL Control register */ 117/* System PLL Control register */
87#define PERF_SYS_PLL_CTL_REG 0x8 118#define PERF_SYS_PLL_CTL_REG 0x8
88#define SYS_PLL_SOFT_RESET 0x1 119#define SYS_PLL_SOFT_RESET 0x1
89 120
90/* Interrupt Mask register */ 121/* Interrupt Mask register */
91#define PERF_IRQMASK_REG 0xc 122#define PERF_IRQMASK_6338_REG 0xc
123#define PERF_IRQMASK_6345_REG 0xc
124#define PERF_IRQMASK_6348_REG 0xc
125#define PERF_IRQMASK_6358_REG 0xc
126#define PERF_IRQMASK_6368_REG 0x20
92 127
93/* Interrupt Status register */ 128/* Interrupt Status register */
94#define PERF_IRQSTAT_REG 0x10 129#define PERF_IRQSTAT_6338_REG 0x10
130#define PERF_IRQSTAT_6345_REG 0x10
131#define PERF_IRQSTAT_6348_REG 0x10
132#define PERF_IRQSTAT_6358_REG 0x10
133#define PERF_IRQSTAT_6368_REG 0x28
95 134
96/* External Interrupt Configuration register */ 135/* External Interrupt Configuration register */
97#define PERF_EXTIRQ_CFG_REG 0x14 136#define PERF_EXTIRQ_CFG_REG_6338 0x14
137#define PERF_EXTIRQ_CFG_REG_6348 0x14
138#define PERF_EXTIRQ_CFG_REG_6358 0x14
139#define PERF_EXTIRQ_CFG_REG_6368 0x18
140
141#define PERF_EXTIRQ_CFG_REG2_6368 0x1c
142
143/* for 6348 only */
144#define EXTIRQ_CFG_SENSE_6348(x) (1 << (x))
145#define EXTIRQ_CFG_STAT_6348(x) (1 << (x + 5))
146#define EXTIRQ_CFG_CLEAR_6348(x) (1 << (x + 10))
147#define EXTIRQ_CFG_MASK_6348(x) (1 << (x + 15))
148#define EXTIRQ_CFG_BOTHEDGE_6348(x) (1 << (x + 20))
149#define EXTIRQ_CFG_LEVELSENSE_6348(x) (1 << (x + 25))
150#define EXTIRQ_CFG_CLEAR_ALL_6348 (0xf << 10)
151#define EXTIRQ_CFG_MASK_ALL_6348 (0xf << 15)
152
153/* for all others */
98#define EXTIRQ_CFG_SENSE(x) (1 << (x)) 154#define EXTIRQ_CFG_SENSE(x) (1 << (x))
99#define EXTIRQ_CFG_STAT(x) (1 << (x + 5)) 155#define EXTIRQ_CFG_STAT(x) (1 << (x + 4))
100#define EXTIRQ_CFG_CLEAR(x) (1 << (x + 10)) 156#define EXTIRQ_CFG_CLEAR(x) (1 << (x + 8))
101#define EXTIRQ_CFG_MASK(x) (1 << (x + 15)) 157#define EXTIRQ_CFG_MASK(x) (1 << (x + 12))
102#define EXTIRQ_CFG_BOTHEDGE(x) (1 << (x + 20)) 158#define EXTIRQ_CFG_BOTHEDGE(x) (1 << (x + 16))
103#define EXTIRQ_CFG_LEVELSENSE(x) (1 << (x + 25)) 159#define EXTIRQ_CFG_LEVELSENSE(x) (1 << (x + 20))
104 160#define EXTIRQ_CFG_CLEAR_ALL (0xf << 8)
105#define EXTIRQ_CFG_CLEAR_ALL (0xf << 10) 161#define EXTIRQ_CFG_MASK_ALL (0xf << 12)
106#define EXTIRQ_CFG_MASK_ALL (0xf << 15)
107 162
108/* Soft Reset register */ 163/* Soft Reset register */
109#define PERF_SOFTRESET_REG 0x28 164#define PERF_SOFTRESET_REG 0x28
165#define PERF_SOFTRESET_6368_REG 0x10
110 166
111#define SOFTRESET_6338_SPI_MASK (1 << 0) 167#define SOFTRESET_6338_SPI_MASK (1 << 0)
112#define SOFTRESET_6338_ENET_MASK (1 << 2) 168#define SOFTRESET_6338_ENET_MASK (1 << 2)
@@ -147,6 +203,15 @@
147 SOFTRESET_6348_ACLC_MASK | \ 203 SOFTRESET_6348_ACLC_MASK | \
148 SOFTRESET_6348_ADSLMIPSPLL_MASK) 204 SOFTRESET_6348_ADSLMIPSPLL_MASK)
149 205
206#define SOFTRESET_6368_SPI_MASK (1 << 0)
207#define SOFTRESET_6368_MPI_MASK (1 << 3)
208#define SOFTRESET_6368_EPHY_MASK (1 << 6)
209#define SOFTRESET_6368_SAR_MASK (1 << 7)
210#define SOFTRESET_6368_ENETSW_MASK (1 << 10)
211#define SOFTRESET_6368_USBS_MASK (1 << 11)
212#define SOFTRESET_6368_USBH_MASK (1 << 12)
213#define SOFTRESET_6368_PCM_MASK (1 << 13)
214
150/* MIPS PLL control register */ 215/* MIPS PLL control register */
151#define PERF_MIPSPLLCTL_REG 0x34 216#define PERF_MIPSPLLCTL_REG 0x34
152#define MIPSPLLCTL_N1_SHIFT 20 217#define MIPSPLLCTL_N1_SHIFT 20
@@ -372,6 +437,7 @@
372#define GPIO_CTL_LO_REG 0x4 437#define GPIO_CTL_LO_REG 0x4
373#define GPIO_DATA_HI_REG 0x8 438#define GPIO_DATA_HI_REG 0x8
374#define GPIO_DATA_LO_REG 0xC 439#define GPIO_DATA_LO_REG 0xC
440#define GPIO_DATA_LO_REG_6345 0x8
375 441
376/* GPIO mux registers and constants */ 442/* GPIO mux registers and constants */
377#define GPIO_MODE_REG 0x18 443#define GPIO_MODE_REG 0x18
@@ -402,6 +468,44 @@
402#define GPIO_MODE_6358_SERIAL_LED (1 << 10) 468#define GPIO_MODE_6358_SERIAL_LED (1 << 10)
403#define GPIO_MODE_6358_UTOPIA (1 << 12) 469#define GPIO_MODE_6358_UTOPIA (1 << 12)
404 470
471#define GPIO_MODE_6368_ANALOG_AFE_0 (1 << 0)
472#define GPIO_MODE_6368_ANALOG_AFE_1 (1 << 1)
473#define GPIO_MODE_6368_SYS_IRQ (1 << 2)
474#define GPIO_MODE_6368_SERIAL_LED_DATA (1 << 3)
475#define GPIO_MODE_6368_SERIAL_LED_CLK (1 << 4)
476#define GPIO_MODE_6368_INET_LED (1 << 5)
477#define GPIO_MODE_6368_EPHY0_LED (1 << 6)
478#define GPIO_MODE_6368_EPHY1_LED (1 << 7)
479#define GPIO_MODE_6368_EPHY2_LED (1 << 8)
480#define GPIO_MODE_6368_EPHY3_LED (1 << 9)
481#define GPIO_MODE_6368_ROBOSW_LED_DAT (1 << 10)
482#define GPIO_MODE_6368_ROBOSW_LED_CLK (1 << 11)
483#define GPIO_MODE_6368_ROBOSW_LED0 (1 << 12)
484#define GPIO_MODE_6368_ROBOSW_LED1 (1 << 13)
485#define GPIO_MODE_6368_USBD_LED (1 << 14)
486#define GPIO_MODE_6368_NTR_PULSE (1 << 15)
487#define GPIO_MODE_6368_PCI_REQ1 (1 << 16)
488#define GPIO_MODE_6368_PCI_GNT1 (1 << 17)
489#define GPIO_MODE_6368_PCI_INTB (1 << 18)
490#define GPIO_MODE_6368_PCI_REQ0 (1 << 19)
491#define GPIO_MODE_6368_PCI_GNT0 (1 << 20)
492#define GPIO_MODE_6368_PCMCIA_CD1 (1 << 22)
493#define GPIO_MODE_6368_PCMCIA_CD2 (1 << 23)
494#define GPIO_MODE_6368_PCMCIA_VS1 (1 << 24)
495#define GPIO_MODE_6368_PCMCIA_VS2 (1 << 25)
496#define GPIO_MODE_6368_EBI_CS2 (1 << 26)
497#define GPIO_MODE_6368_EBI_CS3 (1 << 27)
498#define GPIO_MODE_6368_SPI_SSN2 (1 << 28)
499#define GPIO_MODE_6368_SPI_SSN3 (1 << 29)
500#define GPIO_MODE_6368_SPI_SSN4 (1 << 30)
501#define GPIO_MODE_6368_SPI_SSN5 (1 << 31)
502
503
504#define GPIO_BASEMODE_6368_REG 0x38
505#define GPIO_BASEMODE_6368_UART2 0x1
506#define GPIO_BASEMODE_6368_GPIO 0x0
507#define GPIO_BASEMODE_6368_MASK 0x7
508/* those bits must be kept as read in gpio basemode register*/
405 509
406/************************************************************************* 510/*************************************************************************
407 * _REG relative to RSET_ENET 511 * _REG relative to RSET_ENET
@@ -548,6 +652,56 @@
548 652
549 653
550/************************************************************************* 654/*************************************************************************
655 * _REG relative to RSET_ENETDMAC
656 *************************************************************************/
657
658/* Channel Configuration register */
659#define ENETDMAC_CHANCFG_REG(x) ((x) * 0x10)
660#define ENETDMAC_CHANCFG_EN_SHIFT 0
661#define ENETDMAC_CHANCFG_EN_MASK (1 << ENETDMA_CHANCFG_EN_SHIFT)
662#define ENETDMAC_CHANCFG_PKTHALT_SHIFT 1
663#define ENETDMAC_CHANCFG_PKTHALT_MASK (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT)
664
665/* Interrupt Control/Status register */
666#define ENETDMAC_IR_REG(x) (0x4 + (x) * 0x10)
667#define ENETDMAC_IR_BUFDONE_MASK (1 << 0)
668#define ENETDMAC_IR_PKTDONE_MASK (1 << 1)
669#define ENETDMAC_IR_NOTOWNER_MASK (1 << 2)
670
671/* Interrupt Mask register */
672#define ENETDMAC_IRMASK_REG(x) (0x8 + (x) * 0x10)
673
674/* Maximum Burst Length */
675#define ENETDMAC_MAXBURST_REG(x) (0xc + (x) * 0x10)
676
677
678/*************************************************************************
679 * _REG relative to RSET_ENETDMAS
680 *************************************************************************/
681
682/* Ring Start Address register */
683#define ENETDMAS_RSTART_REG(x) ((x) * 0x10)
684
685/* State Ram Word 2 */
686#define ENETDMAS_SRAM2_REG(x) (0x4 + (x) * 0x10)
687
688/* State Ram Word 3 */
689#define ENETDMAS_SRAM3_REG(x) (0x8 + (x) * 0x10)
690
691/* State Ram Word 4 */
692#define ENETDMAS_SRAM4_REG(x) (0xc + (x) * 0x10)
693
694
695/*************************************************************************
696 * _REG relative to RSET_ENETSW
697 *************************************************************************/
698
699/* MIB register */
700#define ENETSW_MIB_REG(x) (0x2800 + (x) * 4)
701#define ENETSW_MIB_REG_COUNT 47
702
703
704/*************************************************************************
551 * _REG relative to RSET_OHCI_PRIV 705 * _REG relative to RSET_OHCI_PRIV
552 *************************************************************************/ 706 *************************************************************************/
553 707
@@ -562,7 +716,9 @@
562 * _REG relative to RSET_USBH_PRIV 716 * _REG relative to RSET_USBH_PRIV
563 *************************************************************************/ 717 *************************************************************************/
564 718
565#define USBH_PRIV_SWAP_REG 0x0 719#define USBH_PRIV_SWAP_6358_REG 0x0
720#define USBH_PRIV_SWAP_6368_REG 0x1c
721
566#define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT 4 722#define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT 4
567#define USBH_PRIV_SWAP_EHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT) 723#define USBH_PRIV_SWAP_EHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT)
568#define USBH_PRIV_SWAP_EHCI_DATA_SHIFT 3 724#define USBH_PRIV_SWAP_EHCI_DATA_SHIFT 3
@@ -572,7 +728,13 @@
572#define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0 728#define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0
573#define USBH_PRIV_SWAP_OHCI_DATA_MASK (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT) 729#define USBH_PRIV_SWAP_OHCI_DATA_MASK (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT)
574 730
575#define USBH_PRIV_TEST_REG 0x24 731#define USBH_PRIV_TEST_6358_REG 0x24
732#define USBH_PRIV_TEST_6368_REG 0x14
733
734#define USBH_PRIV_SETUP_6368_REG 0x28
735#define USBH_PRIV_SETUP_IOC_SHIFT 4
736#define USBH_PRIV_SETUP_IOC_MASK (1 << USBH_PRIV_SETUP_IOC_SHIFT)
737
576 738
577 739
578/************************************************************************* 740/*************************************************************************
@@ -734,6 +896,8 @@
734#define SDRAM_CFG_BANK_SHIFT 13 896#define SDRAM_CFG_BANK_SHIFT 13
735#define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT) 897#define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT)
736 898
899#define SDRAM_MBASE_REG 0xc
900
737#define SDRAM_PRIO_REG 0x2C 901#define SDRAM_PRIO_REG 0x2C
738#define SDRAM_PRIO_MIPS_SHIFT 29 902#define SDRAM_PRIO_MIPS_SHIFT 29
739#define SDRAM_PRIO_MIPS_MASK (1 << SDRAM_PRIO_MIPS_SHIFT) 903#define SDRAM_PRIO_MIPS_MASK (1 << SDRAM_PRIO_MIPS_SHIFT)
@@ -768,4 +932,45 @@
768#define DMIPSPLLCFG_N2_SHIFT 29 932#define DMIPSPLLCFG_N2_SHIFT 29
769#define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT) 933#define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT)
770 934
935#define DDR_DMIPSPLLCFG_6368_REG 0x20
936#define DMIPSPLLCFG_6368_P1_SHIFT 0
937#define DMIPSPLLCFG_6368_P1_MASK (0xf << DMIPSPLLCFG_6368_P1_SHIFT)
938#define DMIPSPLLCFG_6368_P2_SHIFT 4
939#define DMIPSPLLCFG_6368_P2_MASK (0xf << DMIPSPLLCFG_6368_P2_SHIFT)
940#define DMIPSPLLCFG_6368_NDIV_SHIFT 16
941#define DMIPSPLLCFG_6368_NDIV_MASK (0x1ff << DMIPSPLLCFG_6368_NDIV_SHIFT)
942
943#define DDR_DMIPSPLLDIV_6368_REG 0x24
944#define DMIPSPLLDIV_6368_MDIV_SHIFT 0
945#define DMIPSPLLDIV_6368_MDIV_MASK (0xff << DMIPSPLLDIV_6368_MDIV_SHIFT)
946
947
948/*************************************************************************
949 * _REG relative to RSET_M2M
950 *************************************************************************/
951
952#define M2M_RX 0
953#define M2M_TX 1
954
955#define M2M_SRC_REG(x) ((x) * 0x40 + 0x00)
956#define M2M_DST_REG(x) ((x) * 0x40 + 0x04)
957#define M2M_SIZE_REG(x) ((x) * 0x40 + 0x08)
958
959#define M2M_CTRL_REG(x) ((x) * 0x40 + 0x0c)
960#define M2M_CTRL_ENABLE_MASK (1 << 0)
961#define M2M_CTRL_IRQEN_MASK (1 << 1)
962#define M2M_CTRL_ERROR_CLR_MASK (1 << 6)
963#define M2M_CTRL_DONE_CLR_MASK (1 << 7)
964#define M2M_CTRL_NOINC_MASK (1 << 8)
965#define M2M_CTRL_PCMCIASWAP_MASK (1 << 9)
966#define M2M_CTRL_SWAPBYTE_MASK (1 << 10)
967#define M2M_CTRL_ENDIAN_MASK (1 << 11)
968
969#define M2M_STAT_REG(x) ((x) * 0x40 + 0x10)
970#define M2M_STAT_DONE (1 << 0)
971#define M2M_STAT_ERROR (1 << 1)
972
973#define M2M_SRCID_REG(x) ((x) * 0x40 + 0x14)
974#define M2M_DSTID_REG(x) ((x) * 0x40 + 0x18)
975
771#endif /* BCM63XX_REGS_H_ */ 976#endif /* BCM63XX_REGS_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/ioremap.h b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
new file mode 100644
index 000000000000..ef94ba73646e
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
@@ -0,0 +1,42 @@
1#ifndef BCM63XX_IOREMAP_H_
2#define BCM63XX_IOREMAP_H_
3
4#include <bcm63xx_cpu.h>
5
6static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
7{
8 return phys_addr;
9}
10
11static inline int is_bcm63xx_internal_registers(phys_t offset)
12{
13 switch (bcm63xx_get_cpu_id()) {
14 case BCM6338_CPU_ID:
15 case BCM6345_CPU_ID:
16 case BCM6348_CPU_ID:
17 case BCM6358_CPU_ID:
18 if (offset >= 0xfff00000)
19 return 1;
20 break;
21 case BCM6368_CPU_ID:
22 if (offset >= 0xb0000000 && offset < 0xb1000000)
23 return 1;
24 break;
25 }
26 return 0;
27}
28
29static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
30 unsigned long flags)
31{
32 if (is_bcm63xx_internal_registers(offset))
33 return (void __iomem *)offset;
34 return NULL;
35}
36
37static inline int plat_iounmap(const volatile void __iomem *addr)
38{
39 return is_bcm63xx_internal_registers((unsigned long)addr);
40}
41
42#endif /* BCM63XX_IOREMAP_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/irq.h b/arch/mips/include/asm/mach-bcm63xx/irq.h
new file mode 100644
index 000000000000..9332e788a5c9
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/irq.h
@@ -0,0 +1,7 @@
1#ifndef __ASM_MACH_BCM63XX_IRQ_H
2#define __ASM_MACH_BCM63XX_IRQ_H
3
4#define NR_IRQS 128
5#define MIPS_CPU_IRQ_BASE 0
6
7#endif
diff --git a/arch/mips/include/asm/mach-db1x00/bcsr.h b/arch/mips/include/asm/mach-db1x00/bcsr.h
index 618d2de02ed3..bb9fc23d853a 100644
--- a/arch/mips/include/asm/mach-db1x00/bcsr.h
+++ b/arch/mips/include/asm/mach-db1x00/bcsr.h
@@ -34,6 +34,8 @@
34#define PB1200_BCSR_PHYS_ADDR 0x0D800000 34#define PB1200_BCSR_PHYS_ADDR 0x0D800000
35#define PB1200_BCSR_HEXLED_OFS 0x00400000 35#define PB1200_BCSR_HEXLED_OFS 0x00400000
36 36
37#define DB1300_BCSR_PHYS_ADDR 0x19800000
38#define DB1300_BCSR_HEXLED_OFS 0x00400000
37 39
38enum bcsr_id { 40enum bcsr_id {
39 /* BCSR base 1 */ 41 /* BCSR base 1 */
@@ -105,6 +107,7 @@ enum bcsr_whoami_boards {
105 BCSR_WHOAMI_PB1200 = BCSR_WHOAMI_PB1200_DDR1, 107 BCSR_WHOAMI_PB1200 = BCSR_WHOAMI_PB1200_DDR1,
106 BCSR_WHOAMI_PB1200_DDR2, 108 BCSR_WHOAMI_PB1200_DDR2,
107 BCSR_WHOAMI_DB1200, 109 BCSR_WHOAMI_DB1200,
110 BCSR_WHOAMI_DB1300,
108}; 111};
109 112
110/* STATUS reg. Unless otherwise noted, they're valid on all boards. 113/* STATUS reg. Unless otherwise noted, they're valid on all boards.
@@ -118,12 +121,12 @@ enum bcsr_whoami_boards {
118#define BCSR_STATUS_SRAMWIDTH 0x0080 121#define BCSR_STATUS_SRAMWIDTH 0x0080
119#define BCSR_STATUS_FLASHBUSY 0x0100 122#define BCSR_STATUS_FLASHBUSY 0x0100
120#define BCSR_STATUS_ROMBUSY 0x0400 123#define BCSR_STATUS_ROMBUSY 0x0400
121#define BCSR_STATUS_SD0WP 0x0400 /* DB1200 */ 124#define BCSR_STATUS_SD0WP 0x0400 /* DB1200/DB1300:SD1 */
122#define BCSR_STATUS_SD1WP 0x0800 125#define BCSR_STATUS_SD1WP 0x0800
123#define BCSR_STATUS_USBOTGID 0x0800 /* PB/DB1550 */ 126#define BCSR_STATUS_USBOTGID 0x0800 /* PB/DB1550 */
124#define BCSR_STATUS_DB1000_SWAPBOOT 0x2000 127#define BCSR_STATUS_DB1000_SWAPBOOT 0x2000
125#define BCSR_STATUS_DB1200_SWAPBOOT 0x0040 /* DB1200 */ 128#define BCSR_STATUS_DB1200_SWAPBOOT 0x0040 /* DB1200/1300 */
126#define BCSR_STATUS_IDECBLID 0x0200 /* DB1200 */ 129#define BCSR_STATUS_IDECBLID 0x0200 /* DB1200/1300 */
127#define BCSR_STATUS_DB1200_U0RXD 0x1000 /* DB1200 */ 130#define BCSR_STATUS_DB1200_U0RXD 0x1000 /* DB1200 */
128#define BCSR_STATUS_DB1200_U1RXD 0x2000 /* DB1200 */ 131#define BCSR_STATUS_DB1200_U1RXD 0x2000 /* DB1200 */
129#define BCSR_STATUS_FLASHDEN 0xC000 132#define BCSR_STATUS_FLASHDEN 0xC000
@@ -133,6 +136,11 @@ enum bcsr_whoami_boards {
133#define BCSR_STATUS_PB1550_U1RXD 0x2000 /* PB1550 */ 136#define BCSR_STATUS_PB1550_U1RXD 0x2000 /* PB1550 */
134#define BCSR_STATUS_PB1550_U3RXD 0x8000 /* PB1550 */ 137#define BCSR_STATUS_PB1550_U3RXD 0x8000 /* PB1550 */
135 138
139#define BCSR_STATUS_CFWP 0x4000 /* DB1300 */
140#define BCSR_STATUS_USBOCn 0x2000 /* DB1300 */
141#define BCSR_STATUS_OTGOCn 0x1000 /* DB1300 */
142#define BCSR_STATUS_DCDMARQ 0x0010 /* DB1300 */
143#define BCSR_STATUS_IDEDMARQ 0x0020 /* DB1300 */
136 144
137/* DB/PB1000,1100,1500,1550 */ 145/* DB/PB1000,1100,1500,1550 */
138#define BCSR_RESETS_PHY0 0x0001 146#define BCSR_RESETS_PHY0 0x0001
@@ -155,17 +163,17 @@ enum bcsr_whoami_boards {
155#define BCSR_BOARD_GPIO200RST 0x0400 163#define BCSR_BOARD_GPIO200RST 0x0400
156#define BCSR_BOARD_PCICLKOUT 0x0800 164#define BCSR_BOARD_PCICLKOUT 0x0800
157#define BCSR_BOARD_PCICFG 0x1000 165#define BCSR_BOARD_PCICFG 0x1000
158#define BCSR_BOARD_SPISEL 0x4000 /* PB/DB1550 */ 166#define BCSR_BOARD_SPISEL 0x2000 /* PB/DB1550 */
159#define BCSR_BOARD_SD0WP 0x4000 /* DB1100 */ 167#define BCSR_BOARD_SD0WP 0x4000 /* DB1100 */
160#define BCSR_BOARD_SD1WP 0x8000 /* DB1100 */ 168#define BCSR_BOARD_SD1WP 0x8000 /* DB1100 */
161 169
162 170
163/* DB/PB1200 */ 171/* DB/PB1200/1300 */
164#define BCSR_RESETS_ETH 0x0001 172#define BCSR_RESETS_ETH 0x0001
165#define BCSR_RESETS_CAMERA 0x0002 173#define BCSR_RESETS_CAMERA 0x0002
166#define BCSR_RESETS_DC 0x0004 174#define BCSR_RESETS_DC 0x0004
167#define BCSR_RESETS_IDE 0x0008 175#define BCSR_RESETS_IDE 0x0008
168#define BCSR_RESETS_TV 0x0010 /* DB1200 */ 176#define BCSR_RESETS_TV 0x0010 /* DB1200/1300 */
169/* Not resets but in the same register */ 177/* Not resets but in the same register */
170#define BCSR_RESETS_PWMR1MUX 0x0800 /* DB1200 */ 178#define BCSR_RESETS_PWMR1MUX 0x0800 /* DB1200 */
171#define BCSR_RESETS_PB1200_WSCFSM 0x0800 /* PB1200 */ 179#define BCSR_RESETS_PB1200_WSCFSM 0x0800 /* PB1200 */
@@ -174,13 +182,22 @@ enum bcsr_whoami_boards {
174#define BCSR_RESETS_SPISEL 0x4000 182#define BCSR_RESETS_SPISEL 0x4000
175#define BCSR_RESETS_SD1MUX 0x8000 /* PB1200 */ 183#define BCSR_RESETS_SD1MUX 0x8000 /* PB1200 */
176 184
185#define BCSR_RESETS_VDDQSHDN 0x0200 /* DB1300 */
186#define BCSR_RESETS_OTPPGM 0x0400 /* DB1300 */
187#define BCSR_RESETS_OTPSCLK 0x0800 /* DB1300 */
188#define BCSR_RESETS_OTPWRPROT 0x1000 /* DB1300 */
189#define BCSR_RESETS_OTPCSB 0x2000 /* DB1300 */
190#define BCSR_RESETS_OTGPWR 0x4000 /* DB1300 */
191#define BCSR_RESETS_USBHPWR 0x8000 /* DB1300 */
192
177#define BCSR_BOARD_LCDVEE 0x0001 193#define BCSR_BOARD_LCDVEE 0x0001
178#define BCSR_BOARD_LCDVDD 0x0002 194#define BCSR_BOARD_LCDVDD 0x0002
179#define BCSR_BOARD_LCDBL 0x0004 195#define BCSR_BOARD_LCDBL 0x0004
180#define BCSR_BOARD_CAMSNAP 0x0010 196#define BCSR_BOARD_CAMSNAP 0x0010
181#define BCSR_BOARD_CAMPWR 0x0020 197#define BCSR_BOARD_CAMPWR 0x0020
182#define BCSR_BOARD_SD0PWR 0x0040 198#define BCSR_BOARD_SD0PWR 0x0040
183 199#define BCSR_BOARD_CAMCS 0x0010 /* DB1300 */
200#define BCSR_BOARD_HDMI_DE 0x0040 /* DB1300 */
184 201
185#define BCSR_SWITCHES_DIP 0x00FF 202#define BCSR_SWITCHES_DIP 0x00FF
186#define BCSR_SWITCHES_DIP_1 0x0080 203#define BCSR_SWITCHES_DIP_1 0x0080
@@ -214,7 +231,10 @@ enum bcsr_whoami_boards {
214#define BCSR_SYSTEM_RESET 0x8000 /* clear to reset */ 231#define BCSR_SYSTEM_RESET 0x8000 /* clear to reset */
215#define BCSR_SYSTEM_PWROFF 0x4000 /* set to power off */ 232#define BCSR_SYSTEM_PWROFF 0x4000 /* set to power off */
216#define BCSR_SYSTEM_VDDI 0x001F /* PB1xxx boards */ 233#define BCSR_SYSTEM_VDDI 0x001F /* PB1xxx boards */
217 234#define BCSR_SYSTEM_DEBUGCSMASK 0x003F /* DB1300 */
235#define BCSR_SYSTEM_UDMAMODE 0x0100 /* DB1300 */
236#define BCSR_SYSTEM_WAKEONIRQ 0x0200 /* DB1300 */
237#define BCSR_SYSTEM_VDDI1300 0x3C00 /* DB1300 */
218 238
219 239
220 240
diff --git a/arch/mips/include/asm/mach-db1x00/db1200.h b/arch/mips/include/asm/mach-db1x00/db1200.h
index 7a39657108c4..b2a8319521e5 100644
--- a/arch/mips/include/asm/mach-db1x00/db1200.h
+++ b/arch/mips/include/asm/mach-db1x00/db1200.h
@@ -43,15 +43,20 @@
43#define BCSR_INT_PC1EJECT 0x0800 43#define BCSR_INT_PC1EJECT 0x0800
44#define BCSR_INT_SD0INSERT 0x1000 44#define BCSR_INT_SD0INSERT 0x1000
45#define BCSR_INT_SD0EJECT 0x2000 45#define BCSR_INT_SD0EJECT 0x2000
46#define BCSR_INT_SD1INSERT 0x4000
47#define BCSR_INT_SD1EJECT 0x8000
46 48
47#define IDE_PHYS_ADDR 0x18800000
48#define IDE_REG_SHIFT 5 49#define IDE_REG_SHIFT 5
49 50
50#define DB1200_IDE_PHYS_ADDR IDE_PHYS_ADDR 51#define DB1200_IDE_PHYS_ADDR 0x18800000
51#define DB1200_IDE_PHYS_LEN (16 << IDE_REG_SHIFT) 52#define DB1200_IDE_PHYS_LEN (16 << IDE_REG_SHIFT)
52#define DB1200_ETH_PHYS_ADDR 0x19000300 53#define DB1200_ETH_PHYS_ADDR 0x19000300
53#define DB1200_NAND_PHYS_ADDR 0x20000000 54#define DB1200_NAND_PHYS_ADDR 0x20000000
54 55
56#define PB1200_IDE_PHYS_ADDR 0x0C800000
57#define PB1200_ETH_PHYS_ADDR 0x0D000300
58#define PB1200_NAND_PHYS_ADDR 0x1C000000
59
55/* 60/*
56 * External Interrupts for DBAu1200 as of 8/6/2004. 61 * External Interrupts for DBAu1200 as of 8/6/2004.
57 * Bit positions in the CPLD registers can be calculated by taking 62 * Bit positions in the CPLD registers can be calculated by taking
@@ -77,6 +82,8 @@ enum external_db1200_ints {
77 DB1200_PC1_EJECT_INT, 82 DB1200_PC1_EJECT_INT,
78 DB1200_SD0_INSERT_INT, 83 DB1200_SD0_INSERT_INT,
79 DB1200_SD0_EJECT_INT, 84 DB1200_SD0_EJECT_INT,
85 PB1200_SD1_INSERT_INT,
86 PB1200_SD1_EJECT_INT,
80 87
81 DB1200_INT_END = DB1200_INT_BEGIN + 15, 88 DB1200_INT_END = DB1200_INT_BEGIN + 15,
82}; 89};
diff --git a/arch/mips/include/asm/mach-db1x00/db1300.h b/arch/mips/include/asm/mach-db1x00/db1300.h
new file mode 100644
index 000000000000..7fe5fb3ba877
--- /dev/null
+++ b/arch/mips/include/asm/mach-db1x00/db1300.h
@@ -0,0 +1,40 @@
1/*
2 * NetLogic DB1300 board constants
3 */
4
5#ifndef _DB1300_H_
6#define _DB1300_H_
7
8/* FPGA (external mux) interrupt sources */
9#define DB1300_FIRST_INT (ALCHEMY_GPIC_INT_LAST + 1)
10#define DB1300_IDE_INT (DB1300_FIRST_INT + 0)
11#define DB1300_ETH_INT (DB1300_FIRST_INT + 1)
12#define DB1300_CF_INT (DB1300_FIRST_INT + 2)
13#define DB1300_VIDEO_INT (DB1300_FIRST_INT + 4)
14#define DB1300_HDMI_INT (DB1300_FIRST_INT + 5)
15#define DB1300_DC_INT (DB1300_FIRST_INT + 6)
16#define DB1300_FLASH_INT (DB1300_FIRST_INT + 7)
17#define DB1300_CF_INSERT_INT (DB1300_FIRST_INT + 8)
18#define DB1300_CF_EJECT_INT (DB1300_FIRST_INT + 9)
19#define DB1300_AC97_INT (DB1300_FIRST_INT + 10)
20#define DB1300_AC97_PEN_INT (DB1300_FIRST_INT + 11)
21#define DB1300_SD1_INSERT_INT (DB1300_FIRST_INT + 12)
22#define DB1300_SD1_EJECT_INT (DB1300_FIRST_INT + 13)
23#define DB1300_OTG_VBUS_OC_INT (DB1300_FIRST_INT + 14)
24#define DB1300_HOST_VBUS_OC_INT (DB1300_FIRST_INT + 15)
25#define DB1300_LAST_INT (DB1300_FIRST_INT + 15)
26
27/* SMSC9210 CS */
28#define DB1300_ETH_PHYS_ADDR 0x19000000
29#define DB1300_ETH_PHYS_END 0x197fffff
30
31/* ATA CS */
32#define DB1300_IDE_PHYS_ADDR 0x18800000
33#define DB1300_IDE_REG_SHIFT 5
34#define DB1300_IDE_PHYS_LEN (16 << DB1300_IDE_REG_SHIFT)
35
36/* NAND CS */
37#define DB1300_NAND_PHYS_ADDR 0x20000000
38#define DB1300_NAND_PHYS_END 0x20000fff
39
40#endif /* _DB1300_H_ */
diff --git a/arch/mips/include/asm/mach-db1x00/db1x00.h b/arch/mips/include/asm/mach-db1x00/db1x00.h
deleted file mode 100644
index a5affb0568ef..000000000000
--- a/arch/mips/include/asm/mach-db1x00/db1x00.h
+++ /dev/null
@@ -1,79 +0,0 @@
1/*
2 * AMD Alchemy DBAu1x00 Reference Boards
3 *
4 * Copyright 2001, 2008 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc. <source@mvista.com>
6 * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
7 *
8 * ########################################################################
9 *
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
22 *
23 * ########################################################################
24 *
25 *
26 */
27#ifndef __ASM_DB1X00_H
28#define __ASM_DB1X00_H
29
30#include <asm/mach-au1x00/au1xxx_psc.h>
31
32#ifdef CONFIG_MIPS_DB1550
33
34#define DBDMA_AC97_TX_CHAN AU1550_DSCR_CMD0_PSC1_TX
35#define DBDMA_AC97_RX_CHAN AU1550_DSCR_CMD0_PSC1_RX
36#define DBDMA_I2S_TX_CHAN AU1550_DSCR_CMD0_PSC3_TX
37#define DBDMA_I2S_RX_CHAN AU1550_DSCR_CMD0_PSC3_RX
38
39#define SPI_PSC_BASE AU1550_PSC0_PHYS_ADDR
40#define AC97_PSC_BASE AU1550_PSC1_PHYS_ADDR
41#define SMBUS_PSC_BASE AU1550_PSC2_PHYS_ADDR
42#define I2S_PSC_BASE AU1550_PSC3_PHYS_ADDR
43
44#define NAND_PHYS_ADDR 0x20000000
45
46#endif
47
48/*
49 * NAND defines
50 *
51 * Timing values as described in databook, * ns value stripped of the
52 * lower 2 bits.
53 * These defines are here rather than an Au1550 generic file because
54 * the parts chosen on another board may be different and may require
55 * different timings.
56 */
57#define NAND_T_H (18 >> 2)
58#define NAND_T_PUL (30 >> 2)
59#define NAND_T_SU (30 >> 2)
60#define NAND_T_WH (30 >> 2)
61
62/* Bitfield shift amounts */
63#define NAND_T_H_SHIFT 0
64#define NAND_T_PUL_SHIFT 4
65#define NAND_T_SU_SHIFT 8
66#define NAND_T_WH_SHIFT 12
67
68#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
69 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
70 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
71 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
72#define NAND_CS 1
73
74/* Should be done by YAMON */
75#define NAND_STCFG 0x00400005 /* 8-bit NAND */
76#define NAND_STTIME 0x00007774 /* valid for 396 MHz SD=2 only */
77#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */
78
79#endif /* __ASM_DB1X00_H */
diff --git a/arch/mips/include/asm/mach-db1x00/irq.h b/arch/mips/include/asm/mach-db1x00/irq.h
new file mode 100644
index 000000000000..15b26693238f
--- /dev/null
+++ b/arch/mips/include/asm/mach-db1x00/irq.h
@@ -0,0 +1,23 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003 by Ralf Baechle
7 */
8#ifndef __ASM_MACH_GENERIC_IRQ_H
9#define __ASM_MACH_GENERIC_IRQ_H
10
11
12#ifdef NR_IRQS
13#undef NR_IRQS
14#endif
15
16#ifndef MIPS_CPU_IRQ_BASE
17#define MIPS_CPU_IRQ_BASE 0
18#endif
19
20/* 8 (MIPS) + 128 (au1300) + 16 (cpld) */
21#define NR_IRQS 152
22
23#endif /* __ASM_MACH_GENERIC_IRQ_H */
diff --git a/arch/mips/include/asm/mach-generic/floppy.h b/arch/mips/include/asm/mach-generic/floppy.h
index 001a8ce17c17..a38f4d43e5e5 100644
--- a/arch/mips/include/asm/mach-generic/floppy.h
+++ b/arch/mips/include/asm/mach-generic/floppy.h
@@ -98,7 +98,7 @@ static inline void fd_disable_irq(void)
98static inline int fd_request_irq(void) 98static inline int fd_request_irq(void)
99{ 99{
100 return request_irq(FLOPPY_IRQ, floppy_interrupt, 100 return request_irq(FLOPPY_IRQ, floppy_interrupt,
101 IRQF_DISABLED, "floppy", NULL); 101 0, "floppy", NULL);
102} 102}
103 103
104static inline void fd_free_irq(void) 104static inline void fd_free_irq(void)
diff --git a/arch/mips/include/asm/mach-jazz/floppy.h b/arch/mips/include/asm/mach-jazz/floppy.h
index 56e9ca6ae426..88b5acb75145 100644
--- a/arch/mips/include/asm/mach-jazz/floppy.h
+++ b/arch/mips/include/asm/mach-jazz/floppy.h
@@ -90,7 +90,7 @@ static inline void fd_disable_irq(void)
90static inline int fd_request_irq(void) 90static inline int fd_request_irq(void)
91{ 91{
92 return request_irq(FLOPPY_IRQ, floppy_interrupt, 92 return request_irq(FLOPPY_IRQ, floppy_interrupt,
93 IRQF_DISABLED, "floppy", NULL); 93 0, "floppy", NULL);
94} 94}
95 95
96static inline void fd_free_irq(void) 96static inline void fd_free_irq(void)
diff --git a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
index 3b728275b9b0..d193fb68cf27 100644
--- a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
@@ -24,24 +24,33 @@
24 24
25#define cpu_has_llsc 1 25#define cpu_has_llsc 1
26#define cpu_has_vtag_icache 0 26#define cpu_has_vtag_icache 0
27#define cpu_has_dc_aliases 0 27#define cpu_has_ic_fills_f_dc 1
28#define cpu_has_ic_fills_f_dc 0
29#define cpu_has_dsp 0 28#define cpu_has_dsp 0
30#define cpu_has_mipsmt 0 29#define cpu_has_mipsmt 0
31#define cpu_has_userlocal 0 30#define cpu_icache_snoops_remote_store 1
32#define cpu_icache_snoops_remote_store 0
33 31
34#define cpu_has_nofpuex 0
35#define cpu_has_64bits 1 32#define cpu_has_64bits 1
36 33
37#define cpu_has_mips32r1 1 34#define cpu_has_mips32r1 1
38#define cpu_has_mips32r2 0
39#define cpu_has_mips64r1 1 35#define cpu_has_mips64r1 1
40#define cpu_has_mips64r2 0
41 36
42#define cpu_has_inclusive_pcaches 0 37#define cpu_has_inclusive_pcaches 0
43 38
44#define cpu_dcache_line_size() 32 39#define cpu_dcache_line_size() 32
45#define cpu_icache_line_size() 32 40#define cpu_icache_line_size() 32
46 41
42#if defined(CONFIG_CPU_XLR)
43#define cpu_has_userlocal 0
44#define cpu_has_dc_aliases 0
45#define cpu_has_mips32r2 0
46#define cpu_has_mips64r2 0
47#elif defined(CONFIG_CPU_XLP)
48#define cpu_has_userlocal 1
49#define cpu_has_mips32r2 1
50#define cpu_has_mips64r2 1
51#define cpu_has_dc_aliases 1
52#else
53#error "Unknown Netlogic CPU"
54#endif
55
47#endif /* __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H */ 56#endif /* __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/mc146818rtc.h b/arch/mips/include/asm/mach-pb1x00/mc146818rtc.h
deleted file mode 100644
index 622c58710e5b..000000000000
--- a/arch/mips/include/asm/mach-pb1x00/mc146818rtc.h
+++ /dev/null
@@ -1,34 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1998, 2001, 03 by Ralf Baechle
7 *
8 * RTC routines for PC style attached Dallas chip.
9 */
10#ifndef __ASM_MACH_AU1XX_MC146818RTC_H
11#define __ASM_MACH_AU1XX_MC146818RTC_H
12
13#include <asm/io.h>
14#include <asm/mach-au1x00/au1000.h>
15
16#define RTC_PORT(x) (0x0c000000 + (x))
17#define RTC_IRQ 8
18#define PB1500_RTC_ADDR 0x0c000000
19
20static inline unsigned char CMOS_READ(unsigned long offset)
21{
22 offset <<= 2;
23 return (u8)(au_readl(offset + PB1500_RTC_ADDR) & 0xff);
24}
25
26static inline void CMOS_WRITE(unsigned char data, unsigned long offset)
27{
28 offset <<= 2;
29 au_writel(data, offset + PB1500_RTC_ADDR);
30}
31
32#define RTC_ALWAYS_BCD 1
33
34#endif /* __ASM_MACH_AU1XX_MC146818RTC_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1000.h b/arch/mips/include/asm/mach-pb1x00/pb1000.h
deleted file mode 100644
index 65059255dc1e..000000000000
--- a/arch/mips/include/asm/mach-pb1x00/pb1000.h
+++ /dev/null
@@ -1,87 +0,0 @@
1/*
2 * Alchemy Semi Pb1000 Reference Board
3 *
4 * Copyright 2001, 2008 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc. <source@mvista.com>
6 *
7 * ########################################################################
8 *
9 * This program is free software; you can distribute it and/or modify it
10 * under the terms of the GNU General Public License (Version 2) as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
21 *
22 * ########################################################################
23 *
24 *
25 */
26#ifndef __ASM_PB1000_H
27#define __ASM_PB1000_H
28
29/* PCMCIA PB1000 specific defines */
30#define PCMCIA_MAX_SOCK 1
31#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
32
33#define PB1000_PCR 0xBE000000
34# define PCR_SLOT_0_VPP0 (1 << 0)
35# define PCR_SLOT_0_VPP1 (1 << 1)
36# define PCR_SLOT_0_VCC0 (1 << 2)
37# define PCR_SLOT_0_VCC1 (1 << 3)
38# define PCR_SLOT_0_RST (1 << 4)
39# define PCR_SLOT_1_VPP0 (1 << 8)
40# define PCR_SLOT_1_VPP1 (1 << 9)
41# define PCR_SLOT_1_VCC0 (1 << 10)
42# define PCR_SLOT_1_VCC1 (1 << 11)
43# define PCR_SLOT_1_RST (1 << 12)
44
45#define PB1000_MDR 0xBE000004
46# define MDR_PI (1 << 5) /* PCMCIA int latch */
47# define MDR_EPI (1 << 14) /* enable PCMCIA int */
48# define MDR_CPI (1 << 15) /* clear PCMCIA int */
49
50#define PB1000_ACR1 0xBE000008
51# define ACR1_SLOT_0_CD1 (1 << 0) /* card detect 1 */
52# define ACR1_SLOT_0_CD2 (1 << 1) /* card detect 2 */
53# define ACR1_SLOT_0_READY (1 << 2) /* ready */
54# define ACR1_SLOT_0_STATUS (1 << 3) /* status change */
55# define ACR1_SLOT_0_VS1 (1 << 4) /* voltage sense 1 */
56# define ACR1_SLOT_0_VS2 (1 << 5) /* voltage sense 2 */
57# define ACR1_SLOT_0_INPACK (1 << 6) /* inpack pin status */
58# define ACR1_SLOT_1_CD1 (1 << 8) /* card detect 1 */
59# define ACR1_SLOT_1_CD2 (1 << 9) /* card detect 2 */
60# define ACR1_SLOT_1_READY (1 << 10) /* ready */
61# define ACR1_SLOT_1_STATUS (1 << 11) /* status change */
62# define ACR1_SLOT_1_VS1 (1 << 12) /* voltage sense 1 */
63# define ACR1_SLOT_1_VS2 (1 << 13) /* voltage sense 2 */
64# define ACR1_SLOT_1_INPACK (1 << 14) /* inpack pin status */
65
66#define CPLD_AUX0 0xBE00000C
67#define CPLD_AUX1 0xBE000010
68#define CPLD_AUX2 0xBE000014
69
70/* Voltage levels */
71
72/* VPPEN1 - VPPEN0 */
73#define VPP_GND ((0 << 1) | (0 << 0))
74#define VPP_5V ((1 << 1) | (0 << 0))
75#define VPP_3V ((0 << 1) | (1 << 0))
76#define VPP_12V ((0 << 1) | (1 << 0))
77#define VPP_HIZ ((1 << 1) | (1 << 0))
78
79/* VCCEN1 - VCCEN0 */
80#define VCC_3V ((0 << 1) | (1 << 0))
81#define VCC_5V ((1 << 1) | (0 << 0))
82#define VCC_HIZ ((0 << 1) | (0 << 0))
83
84/* VPP/VCC */
85#define SET_VCC_VPP(VCC, VPP, SLOT) \
86 ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
87#endif /* __ASM_PB1000_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1200.h b/arch/mips/include/asm/mach-pb1x00/pb1200.h
deleted file mode 100644
index 374416adb65b..000000000000
--- a/arch/mips/include/asm/mach-pb1x00/pb1200.h
+++ /dev/null
@@ -1,139 +0,0 @@
1/*
2 * AMD Alchemy Pb1200 Reference Board
3 * Board Registers defines.
4 *
5 * ########################################################################
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 *
20 * ########################################################################
21 *
22 *
23 */
24#ifndef __ASM_PB1200_H
25#define __ASM_PB1200_H
26
27#include <linux/types.h>
28#include <asm/mach-au1x00/au1000.h>
29#include <asm/mach-au1x00/au1xxx_psc.h>
30
31#define DBDMA_AC97_TX_CHAN AU1200_DSCR_CMD0_PSC1_TX
32#define DBDMA_AC97_RX_CHAN AU1200_DSCR_CMD0_PSC1_RX
33#define DBDMA_I2S_TX_CHAN AU1200_DSCR_CMD0_PSC1_TX
34#define DBDMA_I2S_RX_CHAN AU1200_DSCR_CMD0_PSC1_RX
35
36/*
37 * SPI and SMB are muxed on the Pb1200 board.
38 * Refer to board documentation.
39 */
40#define SPI_PSC_BASE AU1550_PSC0_PHYS_ADDR
41#define SMBUS_PSC_BASE AU1550_PSC0_PHYS_ADDR
42/*
43 * AC97 and I2S are muxed on the Pb1200 board.
44 * Refer to board documentation.
45 */
46#define AC97_PSC_BASE AU1550_PSC1_PHYS_ADDR
47#define I2S_PSC_BASE AU1550_PSC1_PHYS_ADDR
48
49
50#define BCSR_SYSTEM_VDDI 0x001F
51#define BCSR_SYSTEM_POWEROFF 0x4000
52#define BCSR_SYSTEM_RESET 0x8000
53
54/* Bit positions for the different interrupt sources */
55#define BCSR_INT_IDE 0x0001
56#define BCSR_INT_ETH 0x0002
57#define BCSR_INT_PC0 0x0004
58#define BCSR_INT_PC0STSCHG 0x0008
59#define BCSR_INT_PC1 0x0010
60#define BCSR_INT_PC1STSCHG 0x0020
61#define BCSR_INT_DC 0x0040
62#define BCSR_INT_FLASHBUSY 0x0080
63#define BCSR_INT_PC0INSERT 0x0100
64#define BCSR_INT_PC0EJECT 0x0200
65#define BCSR_INT_PC1INSERT 0x0400
66#define BCSR_INT_PC1EJECT 0x0800
67#define BCSR_INT_SD0INSERT 0x1000
68#define BCSR_INT_SD0EJECT 0x2000
69#define BCSR_INT_SD1INSERT 0x4000
70#define BCSR_INT_SD1EJECT 0x8000
71
72#define SMC91C111_PHYS_ADDR 0x0D000300
73#define SMC91C111_INT PB1200_ETH_INT
74
75#define IDE_PHYS_ADDR 0x0C800000
76#define IDE_REG_SHIFT 5
77#define IDE_PHYS_LEN (16 << IDE_REG_SHIFT)
78#define IDE_INT PB1200_IDE_INT
79
80#define NAND_PHYS_ADDR 0x1C000000
81
82/*
83 * Timing values as described in databook, * ns value stripped of
84 * lower 2 bits.
85 * These defines are here rather than an Au1200 generic file because
86 * the parts chosen on another board may be different and may require
87 * different timings.
88 */
89#define NAND_T_H (18 >> 2)
90#define NAND_T_PUL (30 >> 2)
91#define NAND_T_SU (30 >> 2)
92#define NAND_T_WH (30 >> 2)
93
94/* Bitfield shift amounts */
95#define NAND_T_H_SHIFT 0
96#define NAND_T_PUL_SHIFT 4
97#define NAND_T_SU_SHIFT 8
98#define NAND_T_WH_SHIFT 12
99
100#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
101 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
102 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
103 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
104
105/*
106 * External Interrupts for Pb1200 as of 8/6/2004.
107 * Bit positions in the CPLD registers can be calculated by taking
108 * the interrupt define and subtracting the PB1200_INT_BEGIN value.
109 *
110 * Example: IDE bis pos is = 64 - 64
111 * ETH bit pos is = 65 - 64
112 */
113enum external_pb1200_ints {
114 PB1200_INT_BEGIN = AU1000_MAX_INTR + 1,
115
116 PB1200_IDE_INT = PB1200_INT_BEGIN,
117 PB1200_ETH_INT,
118 PB1200_PC0_INT,
119 PB1200_PC0_STSCHG_INT,
120 PB1200_PC1_INT,
121 PB1200_PC1_STSCHG_INT,
122 PB1200_DC_INT,
123 PB1200_FLASHBUSY_INT,
124 PB1200_PC0_INSERT_INT,
125 PB1200_PC0_EJECT_INT,
126 PB1200_PC1_INSERT_INT,
127 PB1200_PC1_EJECT_INT,
128 PB1200_SD0_INSERT_INT,
129 PB1200_SD0_EJECT_INT,
130 PB1200_SD1_INSERT_INT,
131 PB1200_SD1_EJECT_INT,
132
133 PB1200_INT_END = PB1200_INT_BEGIN + 15
134};
135
136/* NAND chip select */
137#define NAND_CS 1
138
139#endif /* __ASM_PB1200_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1550.h b/arch/mips/include/asm/mach-pb1x00/pb1550.h
deleted file mode 100644
index 443b88adebf1..000000000000
--- a/arch/mips/include/asm/mach-pb1x00/pb1550.h
+++ /dev/null
@@ -1,73 +0,0 @@
1/*
2 * AMD Alchemy Semi PB1550 Reference Board
3 * Board Registers defines.
4 *
5 * Copyright 2004 Embedded Edge LLC.
6 * Copyright 2005 Ralf Baechle (ralf@linux-mips.org)
7 *
8 * ########################################################################
9 *
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
22 *
23 * ########################################################################
24 *
25 *
26 */
27#ifndef __ASM_PB1550_H
28#define __ASM_PB1550_H
29
30#include <linux/types.h>
31#include <asm/mach-au1x00/au1xxx_psc.h>
32
33#define DBDMA_AC97_TX_CHAN AU1550_DSCR_CMD0_PSC1_TX
34#define DBDMA_AC97_RX_CHAN AU1550_DSCR_CMD0_PSC1_RX
35#define DBDMA_I2S_TX_CHAN AU1550_DSCR_CMD0_PSC3_TX
36#define DBDMA_I2S_RX_CHAN AU1550_DSCR_CMD0_PSC3_RX
37
38#define SPI_PSC_BASE AU1550_PSC0_PHYS_ADDR
39#define AC97_PSC_BASE AU1550_PSC1_PHYS_ADDR
40#define SMBUS_PSC_BASE AU1550_PSC2_PHYS_ADDR
41#define I2S_PSC_BASE AU1550_PSC3_PHYS_ADDR
42
43/*
44 * Timing values as described in databook, * ns value stripped of
45 * lower 2 bits.
46 * These defines are here rather than an SOC1550 generic file because
47 * the parts chosen on another board may be different and may require
48 * different timings.
49 */
50#define NAND_T_H (18 >> 2)
51#define NAND_T_PUL (30 >> 2)
52#define NAND_T_SU (30 >> 2)
53#define NAND_T_WH (30 >> 2)
54
55/* Bitfield shift amounts */
56#define NAND_T_H_SHIFT 0
57#define NAND_T_PUL_SHIFT 4
58#define NAND_T_SU_SHIFT 8
59#define NAND_T_WH_SHIFT 12
60
61#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
62 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
63 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
64 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
65
66#define NAND_CS 1
67
68/* Should be done by YAMON */
69#define NAND_STCFG 0x00400005 /* 8-bit NAND */
70#define NAND_STTIME 0x00007774 /* valid for 396 MHz SD=2 only */
71#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */
72
73#endif /* __ASM_PB1550_H */
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 2ea7b817feb8..7f87d824eeb0 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -1106,7 +1106,7 @@ do { \
1106#define read_c0_brcm_reset() __read_32bit_c0_register($22, 5) 1106#define read_c0_brcm_reset() __read_32bit_c0_register($22, 5)
1107#define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val) 1107#define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val)
1108 1108
1109/* BMIPS4380 */ 1109/* BMIPS43xx */
1110#define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1) 1110#define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1)
1111#define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val) 1111#define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val)
1112 1112
@@ -1667,6 +1667,13 @@ __BUILD_SET_C0(config)
1667__BUILD_SET_C0(intcontrol) 1667__BUILD_SET_C0(intcontrol)
1668__BUILD_SET_C0(intctl) 1668__BUILD_SET_C0(intctl)
1669__BUILD_SET_C0(srsmap) 1669__BUILD_SET_C0(srsmap)
1670__BUILD_SET_C0(brcm_config_0)
1671__BUILD_SET_C0(brcm_bus_pll)
1672__BUILD_SET_C0(brcm_reset)
1673__BUILD_SET_C0(brcm_cmt_intr)
1674__BUILD_SET_C0(brcm_cmt_ctrl)
1675__BUILD_SET_C0(brcm_config)
1676__BUILD_SET_C0(brcm_mode)
1670 1677
1671#endif /* !__ASSEMBLY__ */ 1678#endif /* !__ASSEMBLY__ */
1672 1679
diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h
index bc01a02cacd8..7467d1d933d5 100644
--- a/arch/mips/include/asm/module.h
+++ b/arch/mips/include/asm/module.h
@@ -74,7 +74,9 @@ search_module_dbetables(unsigned long addr)
74} 74}
75#endif 75#endif
76 76
77#ifdef CONFIG_CPU_MIPS32_R1 77#ifdef CONFIG_CPU_BMIPS
78#define MODULE_PROC_FAMILY "BMIPS "
79#elif defined CONFIG_CPU_MIPS32_R1
78#define MODULE_PROC_FAMILY "MIPS32_R1 " 80#define MODULE_PROC_FAMILY "MIPS32_R1 "
79#elif defined CONFIG_CPU_MIPS32_R2 81#elif defined CONFIG_CPU_MIPS32_R2
80#define MODULE_PROC_FAMILY "MIPS32_R2 " 82#define MODULE_PROC_FAMILY "MIPS32_R2 "
@@ -120,6 +122,8 @@ search_module_dbetables(unsigned long addr)
120#define MODULE_PROC_FAMILY "OCTEON " 122#define MODULE_PROC_FAMILY "OCTEON "
121#elif defined CONFIG_CPU_XLR 123#elif defined CONFIG_CPU_XLR
122#define MODULE_PROC_FAMILY "XLR " 124#define MODULE_PROC_FAMILY "XLR "
125#elif defined CONFIG_CPU_XLP
126#define MODULE_PROC_FAMILY "XLP "
123#else 127#else
124#error MODULE_PROC_FAMILY undefined for your processor configuration 128#error MODULE_PROC_FAMILY undefined for your processor configuration
125#endif 129#endif
diff --git a/arch/mips/include/asm/netlogic/common.h b/arch/mips/include/asm/netlogic/common.h
new file mode 100644
index 000000000000..fdd2f44c7b59
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/common.h
@@ -0,0 +1,76 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef _NETLOGIC_COMMON_H_
36#define _NETLOGIC_COMMON_H_
37
38/*
39 * Common SMP definitions
40 */
41#define RESET_VEC_PHYS 0x1fc00000
42#define RESET_DATA_PHYS (RESET_VEC_PHYS + (1<<10))
43#define BOOT_THREAD_MODE 0
44#define BOOT_NMI_LOCK 4
45#define BOOT_NMI_HANDLER 8
46
47#ifndef __ASSEMBLY__
48struct irq_desc;
49extern struct plat_smp_ops nlm_smp_ops;
50extern char nlm_reset_entry[], nlm_reset_entry_end[];
51void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc);
52void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc);
53void nlm_smp_irq_init(void);
54void nlm_boot_secondary_cpus(void);
55int nlm_wakeup_secondary_cpus(u32 wakeup_mask);
56void nlm_rmiboot_preboot(void);
57
58static inline void
59nlm_set_nmi_handler(void *handler)
60{
61 char *reset_data;
62
63 reset_data = (char *)CKSEG1ADDR(RESET_DATA_PHYS);
64 *(int64_t *)(reset_data + BOOT_NMI_HANDLER) = (long)handler;
65}
66
67/*
68 * Misc.
69 */
70unsigned int nlm_get_cpu_frequency(void);
71
72extern unsigned long nlm_common_ebase;
73extern int nlm_threads_per_core;
74extern uint32_t nlm_cpumask, nlm_coremask;
75#endif
76#endif /* _NETLOGIC_COMMON_H_ */
diff --git a/arch/mips/include/asm/netlogic/haldefs.h b/arch/mips/include/asm/netlogic/haldefs.h
new file mode 100644
index 000000000000..72a0c788b472
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/haldefs.h
@@ -0,0 +1,163 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef __NLM_HAL_HALDEFS_H__
36#define __NLM_HAL_HALDEFS_H__
37
38/*
39 * This file contains platform specific memory mapped IO implementation
40 * and will provide a way to read 32/64 bit memory mapped registers in
41 * all ABIs
42 */
43#if !defined(CONFIG_64BIT) && defined(CONFIG_CPU_XLP)
44#error "o32 compile not supported on XLP yet"
45#endif
46/*
47 * For o32 compilation, we have to disable interrupts and enable KX bit to
48 * access 64 bit addresses or data.
49 *
50 * We need to disable interrupts because we save just the lower 32 bits of
51 * registers in interrupt handling. So if we get hit by an interrupt while
52 * using the upper 32 bits of a register, we lose.
53 */
54static inline uint32_t nlm_save_flags_kx(void)
55{
56 return change_c0_status(ST0_KX | ST0_IE, ST0_KX);
57}
58
59static inline uint32_t nlm_save_flags_cop2(void)
60{
61 return change_c0_status(ST0_CU2 | ST0_IE, ST0_CU2);
62}
63
64static inline void nlm_restore_flags(uint32_t sr)
65{
66 write_c0_status(sr);
67}
68
69/*
70 * The n64 implementations are simple, the o32 implementations when they
71 * are added, will have to disable interrupts and enable KX before doing
72 * 64 bit ops.
73 */
74static inline uint32_t
75nlm_read_reg(uint64_t base, uint32_t reg)
76{
77 volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg;
78
79 return *addr;
80}
81
82static inline void
83nlm_write_reg(uint64_t base, uint32_t reg, uint32_t val)
84{
85 volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg;
86
87 *addr = val;
88}
89
90static inline uint64_t
91nlm_read_reg64(uint64_t base, uint32_t reg)
92{
93 uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
94 volatile uint64_t *ptr = (volatile uint64_t *)(long)addr;
95
96 return *ptr;
97}
98
99static inline void
100nlm_write_reg64(uint64_t base, uint32_t reg, uint64_t val)
101{
102 uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
103 volatile uint64_t *ptr = (volatile uint64_t *)(long)addr;
104
105 *ptr = val;
106}
107
108/*
109 * Routines to store 32/64 bit values to 64 bit addresses,
110 * used when going thru XKPHYS to access registers
111 */
112static inline uint32_t
113nlm_read_reg_xkphys(uint64_t base, uint32_t reg)
114{
115 return nlm_read_reg(base, reg);
116}
117
118static inline void
119nlm_write_reg_xkphys(uint64_t base, uint32_t reg, uint32_t val)
120{
121 nlm_write_reg(base, reg, val);
122}
123
124static inline uint64_t
125nlm_read_reg64_xkphys(uint64_t base, uint32_t reg)
126{
127 return nlm_read_reg64(base, reg);
128}
129
130static inline void
131nlm_write_reg64_xkphys(uint64_t base, uint32_t reg, uint64_t val)
132{
133 nlm_write_reg64(base, reg, val);
134}
135
136/* Location where IO base is mapped */
137extern uint64_t nlm_io_base;
138
139#if defined(CONFIG_CPU_XLP)
140static inline uint64_t
141nlm_pcicfg_base(uint32_t devoffset)
142{
143 return nlm_io_base + devoffset;
144}
145
146static inline uint64_t
147nlm_xkphys_map_pcibar0(uint64_t pcibase)
148{
149 uint64_t paddr;
150
151 paddr = nlm_read_reg(pcibase, 0x4) & ~0xfu;
152 return (uint64_t)0x9000000000000000 | paddr;
153}
154#elif defined(CONFIG_CPU_XLR)
155
156static inline uint64_t
157nlm_mmio_base(uint32_t devoffset)
158{
159 return nlm_io_base + devoffset;
160}
161#endif
162
163#endif
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/bridge.h b/arch/mips/include/asm/netlogic/xlp-hal/bridge.h
new file mode 100644
index 000000000000..ca95133f1ad1
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/bridge.h
@@ -0,0 +1,187 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef __NLM_HAL_BRIDGE_H__
36#define __NLM_HAL_BRIDGE_H__
37
38/**
39* @file_name mio.h
40* @author Netlogic Microsystems
41* @brief Basic definitions of XLP memory and io subsystem
42*/
43
44/*
45 * BRIDGE specific registers
46 *
47 * These registers start after the PCIe header, which has 0x40
48 * standard entries
49 */
50#define BRIDGE_MODE 0x00
51#define BRIDGE_PCI_CFG_BASE 0x01
52#define BRIDGE_PCI_CFG_LIMIT 0x02
53#define BRIDGE_PCIE_CFG_BASE 0x03
54#define BRIDGE_PCIE_CFG_LIMIT 0x04
55#define BRIDGE_BUSNUM_BAR0 0x05
56#define BRIDGE_BUSNUM_BAR1 0x06
57#define BRIDGE_BUSNUM_BAR2 0x07
58#define BRIDGE_BUSNUM_BAR3 0x08
59#define BRIDGE_BUSNUM_BAR4 0x09
60#define BRIDGE_BUSNUM_BAR5 0x0a
61#define BRIDGE_BUSNUM_BAR6 0x0b
62#define BRIDGE_FLASH_BAR0 0x0c
63#define BRIDGE_FLASH_BAR1 0x0d
64#define BRIDGE_FLASH_BAR2 0x0e
65#define BRIDGE_FLASH_BAR3 0x0f
66#define BRIDGE_FLASH_LIMIT0 0x10
67#define BRIDGE_FLASH_LIMIT1 0x11
68#define BRIDGE_FLASH_LIMIT2 0x12
69#define BRIDGE_FLASH_LIMIT3 0x13
70
71#define BRIDGE_DRAM_BAR(i) (0x14 + (i))
72#define BRIDGE_DRAM_BAR0 0x14
73#define BRIDGE_DRAM_BAR1 0x15
74#define BRIDGE_DRAM_BAR2 0x16
75#define BRIDGE_DRAM_BAR3 0x17
76#define BRIDGE_DRAM_BAR4 0x18
77#define BRIDGE_DRAM_BAR5 0x19
78#define BRIDGE_DRAM_BAR6 0x1a
79#define BRIDGE_DRAM_BAR7 0x1b
80
81#define BRIDGE_DRAM_LIMIT(i) (0x1c + (i))
82#define BRIDGE_DRAM_LIMIT0 0x1c
83#define BRIDGE_DRAM_LIMIT1 0x1d
84#define BRIDGE_DRAM_LIMIT2 0x1e
85#define BRIDGE_DRAM_LIMIT3 0x1f
86#define BRIDGE_DRAM_LIMIT4 0x20
87#define BRIDGE_DRAM_LIMIT5 0x21
88#define BRIDGE_DRAM_LIMIT6 0x22
89#define BRIDGE_DRAM_LIMIT7 0x23
90
91#define BRIDGE_DRAM_NODE_TRANSLN0 0x24
92#define BRIDGE_DRAM_NODE_TRANSLN1 0x25
93#define BRIDGE_DRAM_NODE_TRANSLN2 0x26
94#define BRIDGE_DRAM_NODE_TRANSLN3 0x27
95#define BRIDGE_DRAM_NODE_TRANSLN4 0x28
96#define BRIDGE_DRAM_NODE_TRANSLN5 0x29
97#define BRIDGE_DRAM_NODE_TRANSLN6 0x2a
98#define BRIDGE_DRAM_NODE_TRANSLN7 0x2b
99#define BRIDGE_DRAM_CHNL_TRANSLN0 0x2c
100#define BRIDGE_DRAM_CHNL_TRANSLN1 0x2d
101#define BRIDGE_DRAM_CHNL_TRANSLN2 0x2e
102#define BRIDGE_DRAM_CHNL_TRANSLN3 0x2f
103#define BRIDGE_DRAM_CHNL_TRANSLN4 0x30
104#define BRIDGE_DRAM_CHNL_TRANSLN5 0x31
105#define BRIDGE_DRAM_CHNL_TRANSLN6 0x32
106#define BRIDGE_DRAM_CHNL_TRANSLN7 0x33
107#define BRIDGE_PCIEMEM_BASE0 0x34
108#define BRIDGE_PCIEMEM_BASE1 0x35
109#define BRIDGE_PCIEMEM_BASE2 0x36
110#define BRIDGE_PCIEMEM_BASE3 0x37
111#define BRIDGE_PCIEMEM_LIMIT0 0x38
112#define BRIDGE_PCIEMEM_LIMIT1 0x39
113#define BRIDGE_PCIEMEM_LIMIT2 0x3a
114#define BRIDGE_PCIEMEM_LIMIT3 0x3b
115#define BRIDGE_PCIEIO_BASE0 0x3c
116#define BRIDGE_PCIEIO_BASE1 0x3d
117#define BRIDGE_PCIEIO_BASE2 0x3e
118#define BRIDGE_PCIEIO_BASE3 0x3f
119#define BRIDGE_PCIEIO_LIMIT0 0x40
120#define BRIDGE_PCIEIO_LIMIT1 0x41
121#define BRIDGE_PCIEIO_LIMIT2 0x42
122#define BRIDGE_PCIEIO_LIMIT3 0x43
123#define BRIDGE_PCIEMEM_BASE4 0x44
124#define BRIDGE_PCIEMEM_BASE5 0x45
125#define BRIDGE_PCIEMEM_BASE6 0x46
126#define BRIDGE_PCIEMEM_LIMIT4 0x47
127#define BRIDGE_PCIEMEM_LIMIT5 0x48
128#define BRIDGE_PCIEMEM_LIMIT6 0x49
129#define BRIDGE_PCIEIO_BASE4 0x4a
130#define BRIDGE_PCIEIO_BASE5 0x4b
131#define BRIDGE_PCIEIO_BASE6 0x4c
132#define BRIDGE_PCIEIO_LIMIT4 0x4d
133#define BRIDGE_PCIEIO_LIMIT5 0x4e
134#define BRIDGE_PCIEIO_LIMIT6 0x4f
135#define BRIDGE_NBU_EVENT_CNT_CTL 0x50
136#define BRIDGE_EVNTCTR1_LOW 0x51
137#define BRIDGE_EVNTCTR1_HI 0x52
138#define BRIDGE_EVNT_CNT_CTL2 0x53
139#define BRIDGE_EVNTCTR2_LOW 0x54
140#define BRIDGE_EVNTCTR2_HI 0x55
141#define BRIDGE_TRACEBUF_MATCH0 0x56
142#define BRIDGE_TRACEBUF_MATCH1 0x57
143#define BRIDGE_TRACEBUF_MATCH_LOW 0x58
144#define BRIDGE_TRACEBUF_MATCH_HI 0x59
145#define BRIDGE_TRACEBUF_CTRL 0x5a
146#define BRIDGE_TRACEBUF_INIT 0x5b
147#define BRIDGE_TRACEBUF_ACCESS 0x5c
148#define BRIDGE_TRACEBUF_READ_DATA0 0x5d
149#define BRIDGE_TRACEBUF_READ_DATA1 0x5d
150#define BRIDGE_TRACEBUF_READ_DATA2 0x5f
151#define BRIDGE_TRACEBUF_READ_DATA3 0x60
152#define BRIDGE_TRACEBUF_STATUS 0x61
153#define BRIDGE_ADDRESS_ERROR0 0x62
154#define BRIDGE_ADDRESS_ERROR1 0x63
155#define BRIDGE_ADDRESS_ERROR2 0x64
156#define BRIDGE_TAG_ECC_ADDR_ERROR0 0x65
157#define BRIDGE_TAG_ECC_ADDR_ERROR1 0x66
158#define BRIDGE_TAG_ECC_ADDR_ERROR2 0x67
159#define BRIDGE_LINE_FLUSH0 0x68
160#define BRIDGE_LINE_FLUSH1 0x69
161#define BRIDGE_NODE_ID 0x6a
162#define BRIDGE_ERROR_INTERRUPT_EN 0x6b
163#define BRIDGE_PCIE0_WEIGHT 0x2c0
164#define BRIDGE_PCIE1_WEIGHT 0x2c1
165#define BRIDGE_PCIE2_WEIGHT 0x2c2
166#define BRIDGE_PCIE3_WEIGHT 0x2c3
167#define BRIDGE_USB_WEIGHT 0x2c4
168#define BRIDGE_NET_WEIGHT 0x2c5
169#define BRIDGE_POE_WEIGHT 0x2c6
170#define BRIDGE_CMS_WEIGHT 0x2c7
171#define BRIDGE_DMAENG_WEIGHT 0x2c8
172#define BRIDGE_SEC_WEIGHT 0x2c9
173#define BRIDGE_COMP_WEIGHT 0x2ca
174#define BRIDGE_GIO_WEIGHT 0x2cb
175#define BRIDGE_FLASH_WEIGHT 0x2cc
176
177#ifndef __ASSEMBLY__
178
179#define nlm_read_bridge_reg(b, r) nlm_read_reg(b, r)
180#define nlm_write_bridge_reg(b, r, v) nlm_write_reg(b, r, v)
181#define nlm_get_bridge_pcibase(node) \
182 nlm_pcicfg_base(XLP_IO_BRIDGE_OFFSET(node))
183#define nlm_get_bridge_regbase(node) \
184 (nlm_get_bridge_pcibase(node) + XLP_IO_PCI_HDRSZ)
185
186#endif /* __ASSEMBLY__ */
187#endif /* __NLM_HAL_BRIDGE_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
new file mode 100644
index 000000000000..bf7d41deb9be
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
@@ -0,0 +1,83 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef __NLM_HAL_CPUCONTROL_H__
36#define __NLM_HAL_CPUCONTROL_H__
37
38#define CPU_BLOCKID_IFU 0
39#define CPU_BLOCKID_ICU 1
40#define CPU_BLOCKID_IEU 2
41#define CPU_BLOCKID_LSU 3
42#define CPU_BLOCKID_MMU 4
43#define CPU_BLOCKID_PRF 5
44#define CPU_BLOCKID_SCH 7
45#define CPU_BLOCKID_SCU 8
46#define CPU_BLOCKID_FPU 9
47#define CPU_BLOCKID_MAP 10
48
49#define LSU_DEFEATURE 0x304
50#define LSU_CERRLOG_REGID 0x09
51#define SCHED_DEFEATURE 0x700
52
53/* Offsets of interest from the 'MAP' Block */
54#define MAP_THREADMODE 0x00
55#define MAP_EXT_EBASE_ENABLE 0x04
56#define MAP_CCDI_CONFIG 0x08
57#define MAP_THRD0_CCDI_STATUS 0x0c
58#define MAP_THRD1_CCDI_STATUS 0x10
59#define MAP_THRD2_CCDI_STATUS 0x14
60#define MAP_THRD3_CCDI_STATUS 0x18
61#define MAP_THRD0_DEBUG_MODE 0x1c
62#define MAP_THRD1_DEBUG_MODE 0x20
63#define MAP_THRD2_DEBUG_MODE 0x24
64#define MAP_THRD3_DEBUG_MODE 0x28
65#define MAP_MISC_STATE 0x60
66#define MAP_DEBUG_READ_CTL 0x64
67#define MAP_DEBUG_READ_REG0 0x68
68#define MAP_DEBUG_READ_REG1 0x6c
69
70#define MMU_SETUP 0x400
71#define MMU_LFSRSEED 0x401
72#define MMU_HPW_NUM_PAGE_LVL 0x410
73#define MMU_PGWKR_PGDBASE 0x411
74#define MMU_PGWKR_PGDSHFT 0x412
75#define MMU_PGWKR_PGDMASK 0x413
76#define MMU_PGWKR_PUDSHFT 0x414
77#define MMU_PGWKR_PUDMASK 0x415
78#define MMU_PGWKR_PMDSHFT 0x416
79#define MMU_PGWKR_PMDMASK 0x417
80#define MMU_PGWKR_PTESHFT 0x418
81#define MMU_PGWKR_PTEMASK 0x419
82
83#endif /* __NLM_CPUCONTROL_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
new file mode 100644
index 000000000000..86cc3391e50c
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
@@ -0,0 +1,153 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef __NLM_HAL_IOMAP_H__
36#define __NLM_HAL_IOMAP_H__
37
38#define XLP_DEFAULT_IO_BASE 0x18000000
39#define NMI_BASE 0xbfc00000
40#define XLP_IO_CLK 133333333
41
42#define XLP_PCIE_CFG_SIZE 0x1000 /* 4K */
43#define XLP_PCIE_DEV_BLK_SIZE (8 * XLP_PCIE_CFG_SIZE)
44#define XLP_PCIE_BUS_BLK_SIZE (256 * XLP_PCIE_DEV_BLK_SIZE)
45#define XLP_IO_SIZE (64 << 20) /* ECFG space size */
46#define XLP_IO_PCI_HDRSZ 0x100
47#define XLP_IO_DEV(node, dev) ((dev) + (node) * 8)
48#define XLP_HDR_OFFSET(node, bus, dev, fn) (((bus) << 20) | \
49 ((XLP_IO_DEV(node, dev)) << 15) | ((fn) << 12))
50
51#define XLP_IO_BRIDGE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 0)
52/* coherent inter chip */
53#define XLP_IO_CIC0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 1)
54#define XLP_IO_CIC1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 2)
55#define XLP_IO_CIC2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 3)
56#define XLP_IO_PIC_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 4)
57
58#define XLP_IO_PCIE_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 1, i)
59#define XLP_IO_PCIE0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 0)
60#define XLP_IO_PCIE1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 1)
61#define XLP_IO_PCIE2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 2)
62#define XLP_IO_PCIE3_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 3)
63
64#define XLP_IO_USB_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 2, i)
65#define XLP_IO_USB_EHCI0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 0)
66#define XLP_IO_USB_OHCI0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 1)
67#define XLP_IO_USB_OHCI1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 2)
68#define XLP_IO_USB_EHCI1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 3)
69#define XLP_IO_USB_OHCI2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 4)
70#define XLP_IO_USB_OHCI3_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 5)
71
72#define XLP_IO_NAE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 0)
73#define XLP_IO_POE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 1)
74
75#define XLP_IO_CMS_OFFSET(node) XLP_HDR_OFFSET(node, 0, 4, 0)
76
77#define XLP_IO_DMA_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 1)
78#define XLP_IO_SEC_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 2)
79#define XLP_IO_CMP_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 3)
80
81#define XLP_IO_UART_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 6, i)
82#define XLP_IO_UART0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 0)
83#define XLP_IO_UART1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 1)
84#define XLP_IO_I2C_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 6, 2 + i)
85#define XLP_IO_I2C0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 2)
86#define XLP_IO_I2C1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 3)
87#define XLP_IO_GPIO_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 4)
88/* system management */
89#define XLP_IO_SYS_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 5)
90#define XLP_IO_JTAG_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 6)
91
92#define XLP_IO_NOR_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 0)
93#define XLP_IO_NAND_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 1)
94#define XLP_IO_SPI_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 2)
95/* SD flash */
96#define XLP_IO_SD_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 3)
97#define XLP_IO_MMC_OFFSET(node, slot) \
98 ((XLP_IO_SD_OFFSET(node))+(slot*0x100)+XLP_IO_PCI_HDRSZ)
99
100/* PCI config header register id's */
101#define XLP_PCI_CFGREG0 0x00
102#define XLP_PCI_CFGREG1 0x01
103#define XLP_PCI_CFGREG2 0x02
104#define XLP_PCI_CFGREG3 0x03
105#define XLP_PCI_CFGREG4 0x04
106#define XLP_PCI_CFGREG5 0x05
107#define XLP_PCI_DEVINFO_REG0 0x30
108#define XLP_PCI_DEVINFO_REG1 0x31
109#define XLP_PCI_DEVINFO_REG2 0x32
110#define XLP_PCI_DEVINFO_REG3 0x33
111#define XLP_PCI_DEVINFO_REG4 0x34
112#define XLP_PCI_DEVINFO_REG5 0x35
113#define XLP_PCI_DEVINFO_REG6 0x36
114#define XLP_PCI_DEVINFO_REG7 0x37
115#define XLP_PCI_DEVSCRATCH_REG0 0x38
116#define XLP_PCI_DEVSCRATCH_REG1 0x39
117#define XLP_PCI_DEVSCRATCH_REG2 0x3a
118#define XLP_PCI_DEVSCRATCH_REG3 0x3b
119#define XLP_PCI_MSGSTN_REG 0x3c
120#define XLP_PCI_IRTINFO_REG 0x3d
121#define XLP_PCI_UCODEINFO_REG 0x3e
122#define XLP_PCI_SBB_WT_REG 0x3f
123
124/* PCI IDs for SoC device */
125#define PCI_VENDOR_NETLOGIC 0x184e
126
127#define PCI_DEVICE_ID_NLM_ROOT 0x1001
128#define PCI_DEVICE_ID_NLM_ICI 0x1002
129#define PCI_DEVICE_ID_NLM_PIC 0x1003
130#define PCI_DEVICE_ID_NLM_PCIE 0x1004
131#define PCI_DEVICE_ID_NLM_EHCI 0x1007
132#define PCI_DEVICE_ID_NLM_ILK 0x1008
133#define PCI_DEVICE_ID_NLM_NAE 0x1009
134#define PCI_DEVICE_ID_NLM_POE 0x100A
135#define PCI_DEVICE_ID_NLM_FMN 0x100B
136#define PCI_DEVICE_ID_NLM_RAID 0x100D
137#define PCI_DEVICE_ID_NLM_SAE 0x100D
138#define PCI_DEVICE_ID_NLM_RSA 0x100E
139#define PCI_DEVICE_ID_NLM_CMP 0x100F
140#define PCI_DEVICE_ID_NLM_UART 0x1010
141#define PCI_DEVICE_ID_NLM_I2C 0x1011
142#define PCI_DEVICE_ID_NLM_NOR 0x1015
143#define PCI_DEVICE_ID_NLM_NAND 0x1016
144#define PCI_DEVICE_ID_NLM_MMC 0x1018
145
146#ifndef __ASSEMBLY__
147
148#define nlm_read_pci_reg(b, r) nlm_read_reg(b, r)
149#define nlm_write_pci_reg(b, r, v) nlm_write_reg(b, r, v)
150
151#endif /* !__ASSEMBLY */
152
153#endif /* __NLM_HAL_IOMAP_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pic.h b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
new file mode 100644
index 000000000000..b6628f7ccf74
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
@@ -0,0 +1,411 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef _NLM_HAL_PIC_H
36#define _NLM_HAL_PIC_H
37
38/* PIC Specific registers */
39#define PIC_CTRL 0x00
40
41/* PIC control register defines */
42#define PIC_CTRL_ITV 32 /* interrupt timeout value */
43#define PIC_CTRL_ICI 19 /* ICI interrupt timeout enable */
44#define PIC_CTRL_ITE 18 /* interrupt timeout enable */
45#define PIC_CTRL_STE 10 /* system timer interrupt enable */
46#define PIC_CTRL_WWR1 8 /* watchdog 1 wraparound count for reset */
47#define PIC_CTRL_WWR0 6 /* watchdog 0 wraparound count for reset */
48#define PIC_CTRL_WWN1 4 /* watchdog 1 wraparound count for NMI */
49#define PIC_CTRL_WWN0 2 /* watchdog 0 wraparound count for NMI */
50#define PIC_CTRL_WTE 0 /* watchdog timer enable */
51
52/* PIC Status register defines */
53#define PIC_ICI_STATUS 33 /* ICI interrupt timeout status */
54#define PIC_ITE_STATUS 32 /* interrupt timeout status */
55#define PIC_STS_STATUS 4 /* System timer interrupt status */
56#define PIC_WNS_STATUS 2 /* NMI status for watchdog timers */
57#define PIC_WIS_STATUS 0 /* Interrupt status for watchdog timers */
58
59/* PIC IPI control register offsets */
60#define PIC_IPICTRL_NMI 32
61#define PIC_IPICTRL_RIV 20 /* received interrupt vector */
62#define PIC_IPICTRL_IDB 16 /* interrupt destination base */
63#define PIC_IPICTRL_DTE 0 /* interrupt destination thread enables */
64
65/* PIC IRT register offsets */
66#define PIC_IRT_ENABLE 31
67#define PIC_IRT_NMI 29
68#define PIC_IRT_SCH 28 /* Scheduling scheme */
69#define PIC_IRT_RVEC 20 /* Interrupt receive vectors */
70#define PIC_IRT_DT 19 /* Destination type */
71#define PIC_IRT_DB 16 /* Destination base */
72#define PIC_IRT_DTE 0 /* Destination thread enables */
73
74#define PIC_BYTESWAP 0x02
75#define PIC_STATUS 0x04
76#define PIC_INTR_TIMEOUT 0x06
77#define PIC_ICI0_INTR_TIMEOUT 0x08
78#define PIC_ICI1_INTR_TIMEOUT 0x0a
79#define PIC_ICI2_INTR_TIMEOUT 0x0c
80#define PIC_IPI_CTL 0x0e
81#define PIC_INT_ACK 0x10
82#define PIC_INT_PENDING0 0x12
83#define PIC_INT_PENDING1 0x14
84#define PIC_INT_PENDING2 0x16
85
86#define PIC_WDOG0_MAXVAL 0x18
87#define PIC_WDOG0_COUNT 0x1a
88#define PIC_WDOG0_ENABLE0 0x1c
89#define PIC_WDOG0_ENABLE1 0x1e
90#define PIC_WDOG0_BEATCMD 0x20
91#define PIC_WDOG0_BEAT0 0x22
92#define PIC_WDOG0_BEAT1 0x24
93
94#define PIC_WDOG1_MAXVAL 0x26
95#define PIC_WDOG1_COUNT 0x28
96#define PIC_WDOG1_ENABLE0 0x2a
97#define PIC_WDOG1_ENABLE1 0x2c
98#define PIC_WDOG1_BEATCMD 0x2e
99#define PIC_WDOG1_BEAT0 0x30
100#define PIC_WDOG1_BEAT1 0x32
101
102#define PIC_WDOG_MAXVAL(i) (PIC_WDOG0_MAXVAL + ((i) ? 7 : 0))
103#define PIC_WDOG_COUNT(i) (PIC_WDOG0_COUNT + ((i) ? 7 : 0))
104#define PIC_WDOG_ENABLE0(i) (PIC_WDOG0_ENABLE0 + ((i) ? 7 : 0))
105#define PIC_WDOG_ENABLE1(i) (PIC_WDOG0_ENABLE1 + ((i) ? 7 : 0))
106#define PIC_WDOG_BEATCMD(i) (PIC_WDOG0_BEATCMD + ((i) ? 7 : 0))
107#define PIC_WDOG_BEAT0(i) (PIC_WDOG0_BEAT0 + ((i) ? 7 : 0))
108#define PIC_WDOG_BEAT1(i) (PIC_WDOG0_BEAT1 + ((i) ? 7 : 0))
109
110#define PIC_TIMER0_MAXVAL 0x34
111#define PIC_TIMER1_MAXVAL 0x36
112#define PIC_TIMER2_MAXVAL 0x38
113#define PIC_TIMER3_MAXVAL 0x3a
114#define PIC_TIMER4_MAXVAL 0x3c
115#define PIC_TIMER5_MAXVAL 0x3e
116#define PIC_TIMER6_MAXVAL 0x40
117#define PIC_TIMER7_MAXVAL 0x42
118#define PIC_TIMER_MAXVAL(i) (PIC_TIMER0_MAXVAL + ((i) * 2))
119
120#define PIC_TIMER0_COUNT 0x44
121#define PIC_TIMER1_COUNT 0x46
122#define PIC_TIMER2_COUNT 0x48
123#define PIC_TIMER3_COUNT 0x4a
124#define PIC_TIMER4_COUNT 0x4c
125#define PIC_TIMER5_COUNT 0x4e
126#define PIC_TIMER6_COUNT 0x50
127#define PIC_TIMER7_COUNT 0x52
128#define PIC_TIMER_COUNT(i) (PIC_TIMER0_COUNT + ((i) * 2))
129
130#define PIC_ITE0_N0_N1 0x54
131#define PIC_ITE1_N0_N1 0x58
132#define PIC_ITE2_N0_N1 0x5c
133#define PIC_ITE3_N0_N1 0x60
134#define PIC_ITE4_N0_N1 0x64
135#define PIC_ITE5_N0_N1 0x68
136#define PIC_ITE6_N0_N1 0x6c
137#define PIC_ITE7_N0_N1 0x70
138#define PIC_ITE_N0_N1(i) (PIC_ITE0_N0_N1 + ((i) * 4))
139
140#define PIC_ITE0_N2_N3 0x56
141#define PIC_ITE1_N2_N3 0x5a
142#define PIC_ITE2_N2_N3 0x5e
143#define PIC_ITE3_N2_N3 0x62
144#define PIC_ITE4_N2_N3 0x66
145#define PIC_ITE5_N2_N3 0x6a
146#define PIC_ITE6_N2_N3 0x6e
147#define PIC_ITE7_N2_N3 0x72
148#define PIC_ITE_N2_N3(i) (PIC_ITE0_N2_N3 + ((i) * 4))
149
150#define PIC_IRT0 0x74
151#define PIC_IRT(i) (PIC_IRT0 + ((i) * 2))
152
153#define TIMER_CYCLES_MAXVAL 0xffffffffffffffffULL
154
155/*
156 * IRT Map
157 */
158#define PIC_NUM_IRTS 160
159
160#define PIC_IRT_WD_0_INDEX 0
161#define PIC_IRT_WD_1_INDEX 1
162#define PIC_IRT_WD_NMI_0_INDEX 2
163#define PIC_IRT_WD_NMI_1_INDEX 3
164#define PIC_IRT_TIMER_0_INDEX 4
165#define PIC_IRT_TIMER_1_INDEX 5
166#define PIC_IRT_TIMER_2_INDEX 6
167#define PIC_IRT_TIMER_3_INDEX 7
168#define PIC_IRT_TIMER_4_INDEX 8
169#define PIC_IRT_TIMER_5_INDEX 9
170#define PIC_IRT_TIMER_6_INDEX 10
171#define PIC_IRT_TIMER_7_INDEX 11
172#define PIC_IRT_CLOCK_INDEX PIC_IRT_TIMER_7_INDEX
173#define PIC_IRT_TIMER_INDEX(num) ((num) + PIC_IRT_TIMER_0_INDEX)
174
175
176/* 11 and 12 */
177#define PIC_NUM_MSG_Q_IRTS 32
178#define PIC_IRT_MSG_Q0_INDEX 12
179#define PIC_IRT_MSG_Q_INDEX(qid) ((qid) + PIC_IRT_MSG_Q0_INDEX)
180/* 12 to 43 */
181#define PIC_IRT_MSG_0_INDEX 44
182#define PIC_IRT_MSG_1_INDEX 45
183/* 44 and 45 */
184#define PIC_NUM_PCIE_MSIX_IRTS 32
185#define PIC_IRT_PCIE_MSIX_0_INDEX 46
186#define PIC_IRT_PCIE_MSIX_INDEX(num) ((num) + PIC_IRT_PCIE_MSIX_0_INDEX)
187/* 46 to 77 */
188#define PIC_NUM_PCIE_LINK_IRTS 4
189#define PIC_IRT_PCIE_LINK_0_INDEX 78
190#define PIC_IRT_PCIE_LINK_1_INDEX 79
191#define PIC_IRT_PCIE_LINK_2_INDEX 80
192#define PIC_IRT_PCIE_LINK_3_INDEX 81
193#define PIC_IRT_PCIE_LINK_INDEX(num) ((num) + PIC_IRT_PCIE_LINK_0_INDEX)
194/* 78 to 81 */
195#define PIC_NUM_NA_IRTS 32
196/* 82 to 113 */
197#define PIC_IRT_NA_0_INDEX 82
198#define PIC_IRT_NA_INDEX(num) ((num) + PIC_IRT_NA_0_INDEX)
199#define PIC_IRT_POE_INDEX 114
200
201#define PIC_NUM_USB_IRTS 6
202#define PIC_IRT_USB_0_INDEX 115
203#define PIC_IRT_EHCI_0_INDEX 115
204#define PIC_IRT_EHCI_1_INDEX 118
205#define PIC_IRT_USB_INDEX(num) ((num) + PIC_IRT_USB_0_INDEX)
206/* 115 to 120 */
207#define PIC_IRT_GDX_INDEX 121
208#define PIC_IRT_SEC_INDEX 122
209#define PIC_IRT_RSA_INDEX 123
210
211#define PIC_NUM_COMP_IRTS 4
212#define PIC_IRT_COMP_0_INDEX 124
213#define PIC_IRT_COMP_INDEX(num) ((num) + PIC_IRT_COMP_0_INDEX)
214/* 124 to 127 */
215#define PIC_IRT_GBU_INDEX 128
216#define PIC_IRT_ICC_0_INDEX 129 /* ICC - Inter Chip Coherency */
217#define PIC_IRT_ICC_1_INDEX 130
218#define PIC_IRT_ICC_2_INDEX 131
219#define PIC_IRT_CAM_INDEX 132
220#define PIC_IRT_UART_0_INDEX 133
221#define PIC_IRT_UART_1_INDEX 134
222#define PIC_IRT_I2C_0_INDEX 135
223#define PIC_IRT_I2C_1_INDEX 136
224#define PIC_IRT_SYS_0_INDEX 137
225#define PIC_IRT_SYS_1_INDEX 138
226#define PIC_IRT_JTAG_INDEX 139
227#define PIC_IRT_PIC_INDEX 140
228#define PIC_IRT_NBU_INDEX 141
229#define PIC_IRT_TCU_INDEX 142
230#define PIC_IRT_GCU_INDEX 143 /* GBC - Global Coherency */
231#define PIC_IRT_DMC_0_INDEX 144
232#define PIC_IRT_DMC_1_INDEX 145
233
234#define PIC_NUM_GPIO_IRTS 4
235#define PIC_IRT_GPIO_0_INDEX 146
236#define PIC_IRT_GPIO_INDEX(num) ((num) + PIC_IRT_GPIO_0_INDEX)
237
238/* 146 to 149 */
239#define PIC_IRT_NOR_INDEX 150
240#define PIC_IRT_NAND_INDEX 151
241#define PIC_IRT_SPI_INDEX 152
242#define PIC_IRT_MMC_INDEX 153
243
244#define PIC_CLOCK_TIMER 7
245#define PIC_IRQ_BASE 8
246
247#if !defined(LOCORE) && !defined(__ASSEMBLY__)
248
249#define PIC_IRT_FIRST_IRQ (PIC_IRQ_BASE)
250#define PIC_IRT_LAST_IRQ 63
251#define PIC_IRQ_IS_IRT(irq) ((irq) >= PIC_IRT_FIRST_IRQ)
252
253/*
254 * Misc
255 */
256#define PIC_IRT_VALID 1
257#define PIC_LOCAL_SCHEDULING 1
258#define PIC_GLOBAL_SCHEDULING 0
259
260#define nlm_read_pic_reg(b, r) nlm_read_reg64(b, r)
261#define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v)
262#define nlm_get_pic_pcibase(node) nlm_pcicfg_base(XLP_IO_PIC_OFFSET(node))
263#define nlm_get_pic_regbase(node) (nlm_get_pic_pcibase(node) + XLP_IO_PCI_HDRSZ)
264
265/* IRT and h/w interrupt routines */
266static inline int
267nlm_pic_read_irt(uint64_t base, int irt_index)
268{
269 return nlm_read_pic_reg(base, PIC_IRT(irt_index));
270}
271
272static inline uint64_t
273nlm_pic_read_control(uint64_t base)
274{
275 return nlm_read_pic_reg(base, PIC_CTRL);
276}
277
278static inline void
279nlm_pic_write_control(uint64_t base, uint64_t control)
280{
281 nlm_write_pic_reg(base, PIC_CTRL, control);
282}
283
284static inline void
285nlm_pic_update_control(uint64_t base, uint64_t control)
286{
287 uint64_t val;
288
289 val = nlm_read_pic_reg(base, PIC_CTRL);
290 nlm_write_pic_reg(base, PIC_CTRL, control | val);
291}
292
293static inline void
294nlm_set_irt_to_cpu(uint64_t base, int irt, int cpu)
295{
296 uint64_t val;
297
298 val = nlm_read_pic_reg(base, PIC_IRT(irt));
299 val |= cpu & 0xf;
300 if (cpu > 15)
301 val |= 1 << 16;
302 nlm_write_pic_reg(base, PIC_IRT(irt), val);
303}
304
305static inline void
306nlm_pic_write_irt(uint64_t base, int irt_num, int en, int nmi,
307 int sch, int vec, int dt, int db, int dte)
308{
309 uint64_t val;
310
311 val = (((uint64_t)en & 0x1) << 31) | ((nmi & 0x1) << 29) |
312 ((sch & 0x1) << 28) | ((vec & 0x3f) << 20) |
313 ((dt & 0x1) << 19) | ((db & 0x7) << 16) |
314 (dte & 0xffff);
315
316 nlm_write_pic_reg(base, PIC_IRT(irt_num), val);
317}
318
319static inline void
320nlm_pic_write_irt_direct(uint64_t base, int irt_num, int en, int nmi,
321 int sch, int vec, int cpu)
322{
323 nlm_pic_write_irt(base, irt_num, en, nmi, sch, vec, 1,
324 (cpu >> 4), /* thread group */
325 1 << (cpu & 0xf)); /* thread mask */
326}
327
328static inline uint64_t
329nlm_pic_read_timer(uint64_t base, int timer)
330{
331 return nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer));
332}
333
334static inline void
335nlm_pic_write_timer(uint64_t base, int timer, uint64_t value)
336{
337 nlm_write_pic_reg(base, PIC_TIMER_COUNT(timer), value);
338}
339
340static inline void
341nlm_pic_set_timer(uint64_t base, int timer, uint64_t value, int irq, int cpu)
342{
343 uint64_t pic_ctrl = nlm_read_pic_reg(base, PIC_CTRL);
344 int en;
345
346 en = (irq > 0);
347 nlm_write_pic_reg(base, PIC_TIMER_MAXVAL(timer), value);
348 nlm_pic_write_irt_direct(base, PIC_IRT_TIMER_INDEX(timer),
349 en, 0, 0, irq, cpu);
350
351 /* enable the timer */
352 pic_ctrl |= (1 << (PIC_CTRL_STE + timer));
353 nlm_write_pic_reg(base, PIC_CTRL, pic_ctrl);
354}
355
356static inline void
357nlm_pic_enable_irt(uint64_t base, int irt)
358{
359 uint64_t reg;
360
361 reg = nlm_read_pic_reg(base, PIC_IRT(irt));
362 nlm_write_pic_reg(base, PIC_IRT(irt), reg | (1u << 31));
363}
364
365static inline void
366nlm_pic_disable_irt(uint64_t base, int irt)
367{
368 uint32_t reg;
369
370 reg = nlm_read_pic_reg(base, PIC_IRT(irt));
371 nlm_write_pic_reg(base, PIC_IRT(irt), reg & ~((uint64_t)1 << 31));
372}
373
374static inline void
375nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi)
376{
377 uint64_t ipi;
378 int node, ncpu;
379
380 node = hwt / 32;
381 ncpu = hwt & 0x1f;
382 ipi = ((uint64_t)nmi << 31) | (irq << 20) | (node << 17) |
383 (1 << (ncpu & 0xf));
384 if (ncpu > 15)
385 ipi |= 0x10000; /* Setting bit 16 to select cpus 16-31 */
386
387 nlm_write_pic_reg(base, PIC_IPI_CTL, ipi);
388}
389
390static inline void
391nlm_pic_ack(uint64_t base, int irt_num)
392{
393 nlm_write_pic_reg(base, PIC_INT_ACK, irt_num);
394
395 /* Ack the Status register for Watchdog & System timers */
396 if (irt_num < 12)
397 nlm_write_pic_reg(base, PIC_STATUS, (1 << irt_num));
398}
399
400static inline void
401nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt)
402{
403 nlm_pic_write_irt_direct(base, irt, 0, 0, 0, irq, 0);
404}
405
406extern uint64_t nlm_pic_base;
407int nlm_irq_to_irt(int irq);
408int nlm_irt_to_irq(int irt);
409
410#endif /* __ASSEMBLY__ */
411#endif /* _NLM_HAL_PIC_H */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/sys.h b/arch/mips/include/asm/netlogic/xlp-hal/sys.h
new file mode 100644
index 000000000000..21432f7d89b9
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/sys.h
@@ -0,0 +1,129 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef __NLM_HAL_SYS_H__
36#define __NLM_HAL_SYS_H__
37
38/**
39* @file_name sys.h
40* @author Netlogic Microsystems
41* @brief HAL for System configuration registers
42*/
43#define SYS_CHIP_RESET 0x00
44#define SYS_POWER_ON_RESET_CFG 0x01
45#define SYS_EFUSE_DEVICE_CFG_STATUS0 0x02
46#define SYS_EFUSE_DEVICE_CFG_STATUS1 0x03
47#define SYS_EFUSE_DEVICE_CFG_STATUS2 0x04
48#define SYS_EFUSE_DEVICE_CFG3 0x05
49#define SYS_EFUSE_DEVICE_CFG4 0x06
50#define SYS_EFUSE_DEVICE_CFG5 0x07
51#define SYS_EFUSE_DEVICE_CFG6 0x08
52#define SYS_EFUSE_DEVICE_CFG7 0x09
53#define SYS_PLL_CTRL 0x0a
54#define SYS_CPU_RESET 0x0b
55#define SYS_CPU_NONCOHERENT_MODE 0x0d
56#define SYS_CORE_DFS_DIS_CTRL 0x0e
57#define SYS_CORE_DFS_RST_CTRL 0x0f
58#define SYS_CORE_DFS_BYP_CTRL 0x10
59#define SYS_CORE_DFS_PHA_CTRL 0x11
60#define SYS_CORE_DFS_DIV_INC_CTRL 0x12
61#define SYS_CORE_DFS_DIV_DEC_CTRL 0x13
62#define SYS_CORE_DFS_DIV_VALUE 0x14
63#define SYS_RESET 0x15
64#define SYS_DFS_DIS_CTRL 0x16
65#define SYS_DFS_RST_CTRL 0x17
66#define SYS_DFS_BYP_CTRL 0x18
67#define SYS_DFS_DIV_INC_CTRL 0x19
68#define SYS_DFS_DIV_DEC_CTRL 0x1a
69#define SYS_DFS_DIV_VALUE0 0x1b
70#define SYS_DFS_DIV_VALUE1 0x1c
71#define SYS_SENSE_AMP_DLY 0x1d
72#define SYS_SOC_SENSE_AMP_DLY 0x1e
73#define SYS_CTRL0 0x1f
74#define SYS_CTRL1 0x20
75#define SYS_TIMEOUT_BS1 0x21
76#define SYS_BYTE_SWAP 0x22
77#define SYS_VRM_VID 0x23
78#define SYS_PWR_RAM_CMD 0x24
79#define SYS_PWR_RAM_ADDR 0x25
80#define SYS_PWR_RAM_DATA0 0x26
81#define SYS_PWR_RAM_DATA1 0x27
82#define SYS_PWR_RAM_DATA2 0x28
83#define SYS_PWR_UCODE 0x29
84#define SYS_CPU0_PWR_STATUS 0x2a
85#define SYS_CPU1_PWR_STATUS 0x2b
86#define SYS_CPU2_PWR_STATUS 0x2c
87#define SYS_CPU3_PWR_STATUS 0x2d
88#define SYS_CPU4_PWR_STATUS 0x2e
89#define SYS_CPU5_PWR_STATUS 0x2f
90#define SYS_CPU6_PWR_STATUS 0x30
91#define SYS_CPU7_PWR_STATUS 0x31
92#define SYS_STATUS 0x32
93#define SYS_INT_POL 0x33
94#define SYS_INT_TYPE 0x34
95#define SYS_INT_STATUS 0x35
96#define SYS_INT_MASK0 0x36
97#define SYS_INT_MASK1 0x37
98#define SYS_UCO_S_ECC 0x38
99#define SYS_UCO_M_ECC 0x39
100#define SYS_UCO_ADDR 0x3a
101#define SYS_UCO_INSTR 0x3b
102#define SYS_MEM_BIST0 0x3c
103#define SYS_MEM_BIST1 0x3d
104#define SYS_MEM_BIST2 0x3e
105#define SYS_MEM_BIST3 0x3f
106#define SYS_MEM_BIST4 0x40
107#define SYS_MEM_BIST5 0x41
108#define SYS_MEM_BIST6 0x42
109#define SYS_MEM_BIST7 0x43
110#define SYS_MEM_BIST8 0x44
111#define SYS_MEM_BIST9 0x45
112#define SYS_MEM_BIST10 0x46
113#define SYS_MEM_BIST11 0x47
114#define SYS_MEM_BIST12 0x48
115#define SYS_SCRTCH0 0x49
116#define SYS_SCRTCH1 0x4a
117#define SYS_SCRTCH2 0x4b
118#define SYS_SCRTCH3 0x4c
119
120#ifndef __ASSEMBLY__
121
122#define nlm_read_sys_reg(b, r) nlm_read_reg(b, r)
123#define nlm_write_sys_reg(b, r, v) nlm_write_reg(b, r, v)
124#define nlm_get_sys_pcibase(node) nlm_pcicfg_base(XLP_IO_SYS_OFFSET(node))
125#define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ)
126
127extern uint64_t nlm_sys_base;
128#endif
129#endif
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/uart.h b/arch/mips/include/asm/netlogic/xlp-hal/uart.h
new file mode 100644
index 000000000000..6a7046ca094d
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/uart.h
@@ -0,0 +1,191 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef __XLP_HAL_UART_H__
36#define __XLP_HAL_UART_H__
37
38/* UART Specific registers */
39#define UART_RX_DATA 0x00
40#define UART_TX_DATA 0x00
41
42#define UART_INT_EN 0x01
43#define UART_INT_ID 0x02
44#define UART_FIFO_CTL 0x02
45#define UART_LINE_CTL 0x03
46#define UART_MODEM_CTL 0x04
47#define UART_LINE_STS 0x05
48#define UART_MODEM_STS 0x06
49
50#define UART_DIVISOR0 0x00
51#define UART_DIVISOR1 0x01
52
53#define BASE_BAUD (XLP_IO_CLK/16)
54#define BAUD_DIVISOR(baud) (BASE_BAUD / baud)
55
56/* LCR mask values */
57#define LCR_5BITS 0x00
58#define LCR_6BITS 0x01
59#define LCR_7BITS 0x02
60#define LCR_8BITS 0x03
61#define LCR_STOPB 0x04
62#define LCR_PENAB 0x08
63#define LCR_PODD 0x00
64#define LCR_PEVEN 0x10
65#define LCR_PONE 0x20
66#define LCR_PZERO 0x30
67#define LCR_SBREAK 0x40
68#define LCR_EFR_ENABLE 0xbf
69#define LCR_DLAB 0x80
70
71/* MCR mask values */
72#define MCR_DTR 0x01
73#define MCR_RTS 0x02
74#define MCR_DRS 0x04
75#define MCR_IE 0x08
76#define MCR_LOOPBACK 0x10
77
78/* FCR mask values */
79#define FCR_RCV_RST 0x02
80#define FCR_XMT_RST 0x04
81#define FCR_RX_LOW 0x00
82#define FCR_RX_MEDL 0x40
83#define FCR_RX_MEDH 0x80
84#define FCR_RX_HIGH 0xc0
85
86/* IER mask values */
87#define IER_ERXRDY 0x1
88#define IER_ETXRDY 0x2
89#define IER_ERLS 0x4
90#define IER_EMSC 0x8
91
92#if !defined(LOCORE) && !defined(__ASSEMBLY__)
93
94#define nlm_read_uart_reg(b, r) nlm_read_reg(b, r)
95#define nlm_write_uart_reg(b, r, v) nlm_write_reg(b, r, v)
96#define nlm_get_uart_pcibase(node, inst) \
97 nlm_pcicfg_base(XLP_IO_UART_OFFSET(node, inst))
98#define nlm_get_uart_regbase(node, inst) \
99 (nlm_get_uart_pcibase(node, inst) + XLP_IO_PCI_HDRSZ)
100
101static inline void
102nlm_uart_set_baudrate(uint64_t base, int baud)
103{
104 uint32_t lcr;
105
106 lcr = nlm_read_uart_reg(base, UART_LINE_CTL);
107
108 /* enable divisor register, and write baud values */
109 nlm_write_uart_reg(base, UART_LINE_CTL, lcr | (1 << 7));
110 nlm_write_uart_reg(base, UART_DIVISOR0,
111 (BAUD_DIVISOR(baud) & 0xff));
112 nlm_write_uart_reg(base, UART_DIVISOR1,
113 ((BAUD_DIVISOR(baud) >> 8) & 0xff));
114
115 /* restore default lcr */
116 nlm_write_uart_reg(base, UART_LINE_CTL, lcr);
117}
118
119static inline void
120nlm_uart_outbyte(uint64_t base, char c)
121{
122 uint32_t lsr;
123
124 for (;;) {
125 lsr = nlm_read_uart_reg(base, UART_LINE_STS);
126 if (lsr & 0x20)
127 break;
128 }
129
130 nlm_write_uart_reg(base, UART_TX_DATA, (int)c);
131}
132
133static inline char
134nlm_uart_inbyte(uint64_t base)
135{
136 int data, lsr;
137
138 for (;;) {
139 lsr = nlm_read_uart_reg(base, UART_LINE_STS);
140 if (lsr & 0x80) { /* parity/frame/break-error - push a zero */
141 data = 0;
142 break;
143 }
144 if (lsr & 0x01) { /* Rx data */
145 data = nlm_read_uart_reg(base, UART_RX_DATA);
146 break;
147 }
148 }
149
150 return (char)data;
151}
152
153static inline int
154nlm_uart_init(uint64_t base, int baud, int databits, int stopbits,
155 int parity, int int_en, int loopback)
156{
157 uint32_t lcr;
158
159 lcr = 0;
160 if (databits >= 8)
161 lcr |= LCR_8BITS;
162 else if (databits == 7)
163 lcr |= LCR_7BITS;
164 else if (databits == 6)
165 lcr |= LCR_6BITS;
166 else
167 lcr |= LCR_5BITS;
168
169 if (stopbits > 1)
170 lcr |= LCR_STOPB;
171
172 lcr |= parity << 3;
173
174 /* setup default lcr */
175 nlm_write_uart_reg(base, UART_LINE_CTL, lcr);
176
177 /* Reset the FIFOs */
178 nlm_write_uart_reg(base, UART_LINE_CTL, FCR_RCV_RST | FCR_XMT_RST);
179
180 nlm_uart_set_baudrate(base, baud);
181
182 if (loopback)
183 nlm_write_uart_reg(base, UART_MODEM_CTL, 0x1f);
184
185 if (int_en)
186 nlm_write_uart_reg(base, UART_INT_EN, IER_ERXRDY | IER_ETXRDY);
187
188 return 0;
189}
190#endif /* !LOCORE && !__ASSEMBLY__ */
191#endif /* __XLP_HAL_UART_H__ */
diff --git a/arch/mips/netlogic/xlr/xlr_console.c b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
index 759df0692201..1540588e396d 100644
--- a/arch/mips/netlogic/xlr/xlr_console.c
+++ b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
@@ -32,15 +32,20 @@
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */ 33 */
34 34
35#include <linux/types.h> 35#ifndef _NLM_HAL_XLP_H
36#include <asm/netlogic/xlr/iomap.h> 36#define _NLM_HAL_XLP_H
37 37
38void prom_putchar(char c) 38#define PIC_UART_0_IRQ 17
39{ 39#define PIC_UART_1_IRQ 18
40 nlm_reg_t *mmio;
41 40
42 mmio = netlogic_io_mmio(NETLOGIC_IO_UART_0_OFFSET); 41#ifndef __ASSEMBLY__
43 while (netlogic_read_reg(mmio, 0x5) == 0) 42
44 ; 43/* SMP support functions */
45 netlogic_write_reg(mmio, 0x0, c); 44void xlp_boot_core0_siblings(void);
46} 45void xlp_wakeup_secondary_cpus(void);
46
47void xlp_mmu_init(void);
48void nlm_hal_init(void);
49
50#endif /* !__ASSEMBLY__ */
51#endif /* _ASM_NLM_XLP_H */
diff --git a/arch/mips/include/asm/netlogic/xlr/iomap.h b/arch/mips/include/asm/netlogic/xlr/iomap.h
index 2e3a4dd53045..2e768f032e83 100644
--- a/arch/mips/include/asm/netlogic/xlr/iomap.h
+++ b/arch/mips/include/asm/netlogic/xlr/iomap.h
@@ -106,26 +106,4 @@
106#define DEFAULT_HT_TYPE0_CFG_BASE 0x16000000 106#define DEFAULT_HT_TYPE0_CFG_BASE 0x16000000
107#define DEFAULT_HT_TYPE1_CFG_BASE 0x17000000 107#define DEFAULT_HT_TYPE1_CFG_BASE 0x17000000
108 108
109#ifndef __ASSEMBLY__
110#include <linux/types.h>
111#include <asm/byteorder.h>
112
113typedef volatile __u32 nlm_reg_t;
114extern unsigned long netlogic_io_base;
115
116/* FIXME read once in write_reg */
117#ifdef CONFIG_CPU_LITTLE_ENDIAN
118#define netlogic_read_reg(base, offset) ((base)[(offset)])
119#define netlogic_write_reg(base, offset, value) ((base)[(offset)] = (value))
120#else
121#define netlogic_read_reg(base, offset) (be32_to_cpu((base)[(offset)]))
122#define netlogic_write_reg(base, offset, value) \
123 ((base)[(offset)] = cpu_to_be32((value)))
124#endif
125
126#define netlogic_read_reg_le32(base, offset) (le32_to_cpu((base)[(offset)]))
127#define netlogic_write_reg_le32(base, offset, value) \
128 ((base)[(offset)] = cpu_to_le32((value)))
129#define netlogic_io_mmio(offset) ((nlm_reg_t *)(netlogic_io_base+(offset)))
130#endif /* __ASSEMBLY__ */
131#endif 109#endif
diff --git a/arch/mips/include/asm/netlogic/xlr/msidef.h b/arch/mips/include/asm/netlogic/xlr/msidef.h
new file mode 100644
index 000000000000..7e39d40be4f5
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlr/msidef.h
@@ -0,0 +1,84 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef ASM_RMI_MSIDEF_H
36#define ASM_RMI_MSIDEF_H
37
38/*
39 * Constants for Intel APIC based MSI messages.
40 * Adapted for the RMI XLR using identical defines
41 */
42
43/*
44 * Shifts for MSI data
45 */
46
47#define MSI_DATA_VECTOR_SHIFT 0
48#define MSI_DATA_VECTOR_MASK 0x000000ff
49#define MSI_DATA_VECTOR(v) (((v) << MSI_DATA_VECTOR_SHIFT) & \
50 MSI_DATA_VECTOR_MASK)
51
52#define MSI_DATA_DELIVERY_MODE_SHIFT 8
53#define MSI_DATA_DELIVERY_FIXED (0 << MSI_DATA_DELIVERY_MODE_SHIFT)
54#define MSI_DATA_DELIVERY_LOWPRI (1 << MSI_DATA_DELIVERY_MODE_SHIFT)
55
56#define MSI_DATA_LEVEL_SHIFT 14
57#define MSI_DATA_LEVEL_DEASSERT (0 << MSI_DATA_LEVEL_SHIFT)
58#define MSI_DATA_LEVEL_ASSERT (1 << MSI_DATA_LEVEL_SHIFT)
59
60#define MSI_DATA_TRIGGER_SHIFT 15
61#define MSI_DATA_TRIGGER_EDGE (0 << MSI_DATA_TRIGGER_SHIFT)
62#define MSI_DATA_TRIGGER_LEVEL (1 << MSI_DATA_TRIGGER_SHIFT)
63
64/*
65 * Shift/mask fields for msi address
66 */
67
68#define MSI_ADDR_BASE_HI 0
69#define MSI_ADDR_BASE_LO 0xfee00000
70
71#define MSI_ADDR_DEST_MODE_SHIFT 2
72#define MSI_ADDR_DEST_MODE_PHYSICAL (0 << MSI_ADDR_DEST_MODE_SHIFT)
73#define MSI_ADDR_DEST_MODE_LOGICAL (1 << MSI_ADDR_DEST_MODE_SHIFT)
74
75#define MSI_ADDR_REDIRECTION_SHIFT 3
76#define MSI_ADDR_REDIRECTION_CPU (0 << MSI_ADDR_REDIRECTION_SHIFT)
77#define MSI_ADDR_REDIRECTION_LOWPRI (1 << MSI_ADDR_REDIRECTION_SHIFT)
78
79#define MSI_ADDR_DEST_ID_SHIFT 12
80#define MSI_ADDR_DEST_ID_MASK 0x00ffff0
81#define MSI_ADDR_DEST_ID(dest) (((dest) << MSI_ADDR_DEST_ID_SHIFT) & \
82 MSI_ADDR_DEST_ID_MASK)
83
84#endif /* ASM_RMI_MSIDEF_H */
diff --git a/arch/mips/include/asm/netlogic/xlr/pic.h b/arch/mips/include/asm/netlogic/xlr/pic.h
index 5cceb746f080..868013e62f32 100644
--- a/arch/mips/include/asm/netlogic/xlr/pic.h
+++ b/arch/mips/include/asm/netlogic/xlr/pic.h
@@ -193,39 +193,72 @@
193/* end XLS */ 193/* end XLS */
194 194
195#ifndef __ASSEMBLY__ 195#ifndef __ASSEMBLY__
196static inline void pic_send_ipi(u32 ipi) 196
197#define PIC_IRQ_IS_EDGE_TRIGGERED(irq) (((irq) >= PIC_TIMER_0_IRQ) && \
198 ((irq) <= PIC_TIMER_7_IRQ))
199#define PIC_IRQ_IS_IRT(irq) (((irq) >= PIC_IRT_FIRST_IRQ) && \
200 ((irq) <= PIC_IRT_LAST_IRQ))
201
202static inline int
203nlm_irq_to_irt(int irq)
197{ 204{
198 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); 205 if (PIC_IRQ_IS_IRT(irq) == 0)
206 return -1;
199 207
200 netlogic_write_reg(mmio, PIC_IPI, ipi); 208 return PIC_IRQ_TO_INTR(irq);
201} 209}
202 210
203static inline u32 pic_read_control(void) 211static inline int
212nlm_irt_to_irq(int irt)
204{ 213{
205 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
206 214
207 return netlogic_read_reg(mmio, PIC_CTRL); 215 return PIC_INTR_TO_IRQ(irt);
208} 216}
209 217
210static inline void pic_write_control(u32 control) 218static inline void
219nlm_pic_enable_irt(uint64_t base, int irt)
211{ 220{
212 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); 221 uint32_t reg;
213 222
214 netlogic_write_reg(mmio, PIC_CTRL, control); 223 reg = nlm_read_reg(base, PIC_IRT_1(irt));
224 nlm_write_reg(base, PIC_IRT_1(irt), reg | (1u << 31));
215} 225}
216 226
217static inline void pic_update_control(u32 control) 227static inline void
228nlm_pic_disable_irt(uint64_t base, int irt)
218{ 229{
219 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); 230 uint32_t reg;
220 231
221 netlogic_write_reg(mmio, PIC_CTRL, 232 reg = nlm_read_reg(base, PIC_IRT_1(irt));
222 (control | netlogic_read_reg(mmio, PIC_CTRL))); 233 nlm_write_reg(base, PIC_IRT_1(irt), reg & ~(1u << 31));
223} 234}
224 235
225#define PIC_IRQ_IS_EDGE_TRIGGERED(irq) (((irq) >= PIC_TIMER_0_IRQ) && \ 236static inline void
226 ((irq) <= PIC_TIMER_7_IRQ)) 237nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi)
227#define PIC_IRQ_IS_IRT(irq) (((irq) >= PIC_IRT_FIRST_IRQ) && \ 238{
228 ((irq) <= PIC_IRT_LAST_IRQ)) 239 unsigned int tid, pid;
229#endif 240
241 tid = hwt & 0x3;
242 pid = (hwt >> 2) & 0x07;
243 nlm_write_reg(base, PIC_IPI,
244 (pid << 20) | (tid << 16) | (nmi << 8) | irq);
245}
246
247static inline void
248nlm_pic_ack(uint64_t base, int irt)
249{
250 nlm_write_reg(base, PIC_INT_ACK, 1u << irt);
251}
230 252
253static inline void
254nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt)
255{
256 nlm_write_reg(base, PIC_IRT_0(irt), (1u << hwt));
257 /* local scheduling, invalid, level by default */
258 nlm_write_reg(base, PIC_IRT_1(irt),
259 (1 << 30) | (1 << 6) | irq);
260}
261
262extern uint64_t nlm_pic_base;
263#endif
231#endif /* _ASM_NLM_XLR_PIC_H */ 264#endif /* _ASM_NLM_XLR_PIC_H */
diff --git a/arch/mips/include/asm/netlogic/xlr/xlr.h b/arch/mips/include/asm/netlogic/xlr/xlr.h
index 3e6372692a04..ff4a17b0bf78 100644
--- a/arch/mips/include/asm/netlogic/xlr/xlr.h
+++ b/arch/mips/include/asm/netlogic/xlr/xlr.h
@@ -40,17 +40,8 @@ struct uart_port;
40unsigned int nlm_xlr_uart_in(struct uart_port *, int); 40unsigned int nlm_xlr_uart_in(struct uart_port *, int);
41void nlm_xlr_uart_out(struct uart_port *, int, int); 41void nlm_xlr_uart_out(struct uart_port *, int, int);
42 42
43/* SMP support functions */ 43/* SMP helpers */
44struct irq_desc; 44void xlr_wakeup_secondary_cpus(void);
45void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc);
46void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc);
47int nlm_wakeup_secondary_cpus(u32 wakeup_mask);
48void nlm_smp_irq_init(void);
49void nlm_boot_smp_nmi(void);
50void prom_pre_boot_secondary_cpus(void);
51
52extern struct plat_smp_ops nlm_smp_ops;
53extern unsigned long nlm_common_ebase;
54 45
55/* XLS B silicon "Rook" */ 46/* XLS B silicon "Rook" */
56static inline unsigned int nlm_chip_is_xls_b(void) 47static inline unsigned int nlm_chip_is_xls_b(void)
diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
index e59cd1ac09c2..d41790928c64 100644
--- a/arch/mips/include/asm/page.h
+++ b/arch/mips/include/asm/page.h
@@ -38,6 +38,14 @@
38#define HPAGE_SIZE (_AC(1,UL) << HPAGE_SHIFT) 38#define HPAGE_SIZE (_AC(1,UL) << HPAGE_SHIFT)
39#define HPAGE_MASK (~(HPAGE_SIZE - 1)) 39#define HPAGE_MASK (~(HPAGE_SIZE - 1))
40#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 40#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
41#else /* !CONFIG_HUGETLB_PAGE */
42# ifndef BUILD_BUG
43# define BUILD_BUG() do { extern void __build_bug(void); __build_bug(); } while (0)
44# endif
45#define HPAGE_SHIFT ({BUILD_BUG(); 0; })
46#define HPAGE_SIZE ({BUILD_BUG(); 0; })
47#define HPAGE_MASK ({BUILD_BUG(); 0; })
48#define HUGETLB_PAGE_ORDER ({BUILD_BUG(); 0; })
41#endif /* CONFIG_HUGETLB_PAGE */ 49#endif /* CONFIG_HUGETLB_PAGE */
42 50
43#ifndef __ASSEMBLY__ 51#ifndef __ASSEMBLY__
diff --git a/arch/mips/include/asm/pgtable-32.h b/arch/mips/include/asm/pgtable-32.h
index 8a153d2fa62a..5d56bb230345 100644
--- a/arch/mips/include/asm/pgtable-32.h
+++ b/arch/mips/include/asm/pgtable-32.h
@@ -19,23 +19,7 @@
19#include <asm-generic/pgtable-nopmd.h> 19#include <asm-generic/pgtable-nopmd.h>
20 20
21/* 21/*
22 * - add_wired_entry() add a fixed TLB entry, and move wired register 22 * Basically we have the same two-level (which is the logical three level
23 */
24extern void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
25 unsigned long entryhi, unsigned long pagemask);
26
27/*
28 * - add_temporary_entry() add a temporary TLB entry. We use TLB entries
29 * starting at the top and working down. This is for populating the
30 * TLB before trap_init() puts the TLB miss handler in place. It
31 * should be used only for entries matching the actual page tables,
32 * to prevent inconsistencies.
33 */
34extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
35 unsigned long entryhi, unsigned long pagemask);
36
37
38/* Basically we have the same two-level (which is the logical three level
39 * Linux page table layout folded) page tables as the i386. Some day 23 * Linux page table layout folded) page tables as the i386. Some day
40 * when we have proper page coloring support we can have a 1% quicker 24 * when we have proper page coloring support we can have a 1% quicker
41 * tlb refill handling mechanism, but for now it is a bit slower but 25 * tlb refill handling mechanism, but for now it is a bit slower but
diff --git a/arch/mips/include/asm/tlbmisc.h b/arch/mips/include/asm/tlbmisc.h
new file mode 100644
index 000000000000..3a452282cba0
--- /dev/null
+++ b/arch/mips/include/asm/tlbmisc.h
@@ -0,0 +1,10 @@
1#ifndef __ASM_TLBMISC_H
2#define __ASM_TLBMISC_H
3
4/*
5 * - add_wired_entry() add a fixed TLB entry, and move wired register
6 */
7extern void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
8 unsigned long entryhi, unsigned long pagemask);
9
10#endif /* __ASM_TLBMISC_H */
diff --git a/arch/mips/include/asm/traps.h b/arch/mips/include/asm/traps.h
index 90ff2f497c50..ff74aec3561a 100644
--- a/arch/mips/include/asm/traps.h
+++ b/arch/mips/include/asm/traps.h
@@ -24,5 +24,18 @@ extern int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
24extern void (*board_nmi_handler_setup)(void); 24extern void (*board_nmi_handler_setup)(void);
25extern void (*board_ejtag_handler_setup)(void); 25extern void (*board_ejtag_handler_setup)(void);
26extern void (*board_bind_eic_interrupt)(int irq, int regset); 26extern void (*board_bind_eic_interrupt)(int irq, int regset);
27extern void (*board_ebase_setup)(void);
28
29extern int register_nmi_notifier(struct notifier_block *nb);
30
31#define nmi_notifier(fn, pri) \
32({ \
33 static struct notifier_block fn##_nb = { \
34 .notifier_call = fn, \
35 .priority = pri \
36 }; \
37 \
38 register_nmi_notifier(&fn##_nb); \
39})
27 40
28#endif /* _ASM_TRAPS_H */ 41#endif /* _ASM_TRAPS_H */
diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c
index ca9bd2069142..f21868b28b24 100644
--- a/arch/mips/jazz/irq.c
+++ b/arch/mips/jazz/irq.c
@@ -20,6 +20,7 @@
20#include <asm/io.h> 20#include <asm/io.h>
21#include <asm/jazz.h> 21#include <asm/jazz.h>
22#include <asm/pgtable.h> 22#include <asm/pgtable.h>
23#include <asm/tlbmisc.h>
23 24
24static DEFINE_RAW_SPINLOCK(r4030_lock); 25static DEFINE_RAW_SPINLOCK(r4030_lock);
25 26
@@ -133,7 +134,7 @@ static irqreturn_t r4030_timer_interrupt(int irq, void *dev_id)
133 134
134static struct irqaction r4030_timer_irqaction = { 135static struct irqaction r4030_timer_irqaction = {
135 .handler = r4030_timer_interrupt, 136 .handler = r4030_timer_interrupt,
136 .flags = IRQF_DISABLED | IRQF_TIMER, 137 .flags = IRQF_TIMER,
137 .name = "R4030 timer", 138 .name = "R4030 timer",
138}; 139};
139 140
diff --git a/arch/mips/jazz/setup.c b/arch/mips/jazz/setup.c
index 0d0f054a02f4..820e926dacbc 100644
--- a/arch/mips/jazz/setup.c
+++ b/arch/mips/jazz/setup.c
@@ -21,6 +21,7 @@
21#include <asm/jazzdma.h> 21#include <asm/jazzdma.h>
22#include <asm/reboot.h> 22#include <asm/reboot.h>
23#include <asm/pgtable.h> 23#include <asm/pgtable.h>
24#include <asm/tlbmisc.h>
24 25
25extern asmlinkage void jazz_handle_int(void); 26extern asmlinkage void jazz_handle_int(void);
26 27
diff --git a/arch/mips/jz4740/board-qi_lb60.c b/arch/mips/jz4740/board-qi_lb60.c
index c3b04be3fb2b..639e3ce6c264 100644
--- a/arch/mips/jz4740/board-qi_lb60.c
+++ b/arch/mips/jz4740/board-qi_lb60.c
@@ -488,7 +488,7 @@ static int __init qi_lb60_board_setup(void)
488 board_gpio_setup(); 488 board_gpio_setup();
489 489
490 if (qi_lb60_init_platform_devices()) 490 if (qi_lb60_init_platform_devices())
491 panic("Failed to initialize platform devices\n"); 491 panic("Failed to initialize platform devices");
492 492
493 return 0; 493 return 0;
494} 494}
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 1a966183e353..0c6877ea9004 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -55,9 +55,11 @@ obj-$(CONFIG_CPU_TX49XX) += r4k_fpu.o r4k_switch.o
55obj-$(CONFIG_CPU_VR41XX) += r4k_fpu.o r4k_switch.o 55obj-$(CONFIG_CPU_VR41XX) += r4k_fpu.o r4k_switch.o
56obj-$(CONFIG_CPU_CAVIUM_OCTEON) += octeon_switch.o 56obj-$(CONFIG_CPU_CAVIUM_OCTEON) += octeon_switch.o
57obj-$(CONFIG_CPU_XLR) += r4k_fpu.o r4k_switch.o 57obj-$(CONFIG_CPU_XLR) += r4k_fpu.o r4k_switch.o
58obj-$(CONFIG_CPU_XLP) += r4k_fpu.o r4k_switch.o
58 59
59obj-$(CONFIG_SMP) += smp.o 60obj-$(CONFIG_SMP) += smp.o
60obj-$(CONFIG_SMP_UP) += smp-up.o 61obj-$(CONFIG_SMP_UP) += smp-up.o
62obj-$(CONFIG_CPU_BMIPS) += smp-bmips.o bmips_vec.o
61 63
62obj-$(CONFIG_MIPS_MT) += mips-mt.o 64obj-$(CONFIG_MIPS_MT) += mips-mt.o
63obj-$(CONFIG_MIPS_MT_FPAFF) += mips-mt-fpaff.o 65obj-$(CONFIG_MIPS_MT_FPAFF) += mips-mt-fpaff.o
diff --git a/arch/mips/kernel/bmips_vec.S b/arch/mips/kernel/bmips_vec.S
new file mode 100644
index 000000000000..e908e81330b1
--- /dev/null
+++ b/arch/mips/kernel/bmips_vec.S
@@ -0,0 +1,255 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
7 *
8 * Reset/NMI/re-entry vectors for BMIPS processors
9 */
10
11#include <linux/init.h>
12
13#include <asm/asm.h>
14#include <asm/asmmacro.h>
15#include <asm/cacheops.h>
16#include <asm/regdef.h>
17#include <asm/mipsregs.h>
18#include <asm/stackframe.h>
19#include <asm/addrspace.h>
20#include <asm/hazards.h>
21#include <asm/bmips.h>
22
23 .macro BARRIER
24 .set mips32
25 _ssnop
26 _ssnop
27 _ssnop
28 .set mips0
29 .endm
30
31 __CPUINIT
32
33/***********************************************************************
34 * Alternate CPU1 startup vector for BMIPS4350
35 *
36 * On some systems the bootloader has already started CPU1 and configured
37 * it to resume execution at 0x8000_0200 (!BEV IV vector) when it is
38 * triggered by the SW1 interrupt. If that is the case we try to move
39 * it to a more convenient place: BMIPS_WARM_RESTART_VEC @ 0x8000_0380.
40 ***********************************************************************/
41
42LEAF(bmips_smp_movevec)
43 la k0, 1f
44 li k1, CKSEG1
45 or k0, k1
46 jr k0
47
481:
49 /* clear IV, pending IPIs */
50 mtc0 zero, CP0_CAUSE
51
52 /* re-enable IRQs to wait for SW1 */
53 li k0, ST0_IE | ST0_BEV | STATUSF_IP1
54 mtc0 k0, CP0_STATUS
55
56 /* set up CPU1 CBR; move BASE to 0xa000_0000 */
57 li k0, 0xff400000
58 mtc0 k0, $22, 6
59 li k1, CKSEG1 | BMIPS_RELO_VECTOR_CONTROL_1
60 or k0, k1
61 li k1, 0xa0080000
62 sw k1, 0(k0)
63
64 /* wait here for SW1 interrupt from bmips_boot_secondary() */
65 wait
66
67 la k0, bmips_reset_nmi_vec
68 li k1, CKSEG1
69 or k0, k1
70 jr k0
71END(bmips_smp_movevec)
72
73/***********************************************************************
74 * Reset/NMI vector
75 * For BMIPS processors that can relocate their exception vectors, this
76 * entire function gets copied to 0x8000_0000.
77 ***********************************************************************/
78
79NESTED(bmips_reset_nmi_vec, PT_SIZE, sp)
80 .set push
81 .set noat
82 .align 4
83
84#ifdef CONFIG_SMP
85 /* if the NMI bit is clear, assume this is a CPU1 reset instead */
86 li k1, (1 << 19)
87 mfc0 k0, CP0_STATUS
88 and k0, k1
89 beqz k0, bmips_smp_entry
90
91#if defined(CONFIG_CPU_BMIPS5000)
92 /* if we're not on core 0, this must be the SMP boot signal */
93 li k1, (3 << 25)
94 mfc0 k0, $22
95 and k0, k1
96 bnez k0, bmips_smp_entry
97#endif
98#endif /* CONFIG_SMP */
99
100 /* nope, it's just a regular NMI */
101 SAVE_ALL
102 move a0, sp
103
104 /* clear EXL, ERL, BEV so that TLB refills still work */
105 mfc0 k0, CP0_STATUS
106 li k1, ST0_ERL | ST0_EXL | ST0_BEV | ST0_IE
107 or k0, k1
108 xor k0, k1
109 mtc0 k0, CP0_STATUS
110 BARRIER
111
112 /* jump to the NMI handler function */
113 la k0, nmi_handler
114 jr k0
115
116 RESTORE_ALL
117 .set mips3
118 eret
119
120/***********************************************************************
121 * CPU1 reset vector (used for the initial boot only)
122 * This is still part of bmips_reset_nmi_vec().
123 ***********************************************************************/
124
125#ifdef CONFIG_SMP
126
127bmips_smp_entry:
128
129 /* set up CP0 STATUS; enable FPU */
130 li k0, 0x30000000
131 mtc0 k0, CP0_STATUS
132 BARRIER
133
134 /* set local CP0 CONFIG to make kseg0 cacheable, write-back */
135 mfc0 k0, CP0_CONFIG
136 ori k0, 0x07
137 xori k0, 0x04
138 mtc0 k0, CP0_CONFIG
139
140#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
141 /* initialize CPU1's local I-cache */
142 li k0, 0x80000000
143 li k1, 0x80010000
144 mtc0 zero, $28
145 mtc0 zero, $28, 1
146 BARRIER
147
1481: cache Index_Store_Tag_I, 0(k0)
149 addiu k0, 16
150 bne k0, k1, 1b
151#elif defined(CONFIG_CPU_BMIPS5000)
152 /* set exception vector base */
153 la k0, ebase
154 lw k0, 0(k0)
155 mtc0 k0, $15, 1
156 BARRIER
157#endif
158
159 /* jump back to kseg0 in case we need to remap the kseg1 area */
160 la k0, 1f
161 jr k0
1621:
163 la k0, bmips_enable_xks01
164 jalr k0
165
166 /* use temporary stack to set up upper memory TLB */
167 li sp, BMIPS_WARM_RESTART_VEC
168 la k0, plat_wired_tlb_setup
169 jalr k0
170
171 /* switch to permanent stack and continue booting */
172
173 .global bmips_secondary_reentry
174bmips_secondary_reentry:
175 la k0, bmips_smp_boot_sp
176 lw sp, 0(k0)
177 la k0, bmips_smp_boot_gp
178 lw gp, 0(k0)
179 la k0, start_secondary
180 jr k0
181
182#endif /* CONFIG_SMP */
183
184 .align 4
185 .global bmips_reset_nmi_vec_end
186bmips_reset_nmi_vec_end:
187
188END(bmips_reset_nmi_vec)
189
190 .set pop
191 .previous
192
193/***********************************************************************
194 * CPU1 warm restart vector (used for second and subsequent boots).
195 * Also used for S2 standby recovery (PM).
196 * This entire function gets copied to (BMIPS_WARM_RESTART_VEC)
197 ***********************************************************************/
198
199LEAF(bmips_smp_int_vec)
200
201 .align 4
202 mfc0 k0, CP0_STATUS
203 ori k0, 0x01
204 xori k0, 0x01
205 mtc0 k0, CP0_STATUS
206 eret
207
208 .align 4
209 .global bmips_smp_int_vec_end
210bmips_smp_int_vec_end:
211
212END(bmips_smp_int_vec)
213
214/***********************************************************************
215 * XKS01 support
216 * Certain CPUs support extending kseg0 to 1024MB.
217 ***********************************************************************/
218
219 __CPUINIT
220
221LEAF(bmips_enable_xks01)
222
223#if defined(CONFIG_XKS01)
224
225#if defined(CONFIG_CPU_BMIPS4380)
226 mfc0 t0, $22, 3
227 li t1, 0x1ff0
228 li t2, (1 << 12) | (1 << 9)
229 or t0, t1
230 xor t0, t1
231 or t0, t2
232 mtc0 t0, $22, 3
233 BARRIER
234#elif defined(CONFIG_CPU_BMIPS5000)
235 mfc0 t0, $22, 5
236 li t1, 0x01ff
237 li t2, (1 << 8) | (1 << 5)
238 or t0, t1
239 xor t0, t1
240 or t0, t2
241 mtc0 t0, $22, 5
242 BARRIER
243#else
244
245#error Missing XKS01 setup
246
247#endif
248
249#endif /* defined(CONFIG_XKS01) */
250
251 jr ra
252
253END(bmips_enable_xks01)
254
255 .previous
diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c
index 32103cc2a257..4d735d0e58f5 100644
--- a/arch/mips/kernel/branch.c
+++ b/arch/mips/kernel/branch.c
@@ -9,6 +9,7 @@
9#include <linux/kernel.h> 9#include <linux/kernel.h>
10#include <linux/sched.h> 10#include <linux/sched.h>
11#include <linux/signal.h> 11#include <linux/signal.h>
12#include <linux/module.h>
12#include <asm/branch.h> 13#include <asm/branch.h>
13#include <asm/cpu.h> 14#include <asm/cpu.h>
14#include <asm/cpu-features.h> 15#include <asm/cpu-features.h>
@@ -17,28 +18,22 @@
17#include <asm/ptrace.h> 18#include <asm/ptrace.h>
18#include <asm/uaccess.h> 19#include <asm/uaccess.h>
19 20
20/* 21/**
21 * Compute the return address and do emulate branch simulation, if required. 22 * __compute_return_epc_for_insn - Computes the return address and do emulate
23 * branch simulation, if required.
24 *
25 * @regs: Pointer to pt_regs
26 * @insn: branch instruction to decode
27 * @returns: -EFAULT on error and forces SIGBUS, and on success
28 * returns 0 or BRANCH_LIKELY_TAKEN as appropriate after
29 * evaluating the branch.
22 */ 30 */
23int __compute_return_epc(struct pt_regs *regs) 31int __compute_return_epc_for_insn(struct pt_regs *regs,
32 union mips_instruction insn)
24{ 33{
25 unsigned int __user *addr;
26 unsigned int bit, fcr31, dspcontrol; 34 unsigned int bit, fcr31, dspcontrol;
27 long epc; 35 long epc = regs->cp0_epc;
28 union mips_instruction insn; 36 int ret = 0;
29
30 epc = regs->cp0_epc;
31 if (epc & 3)
32 goto unaligned;
33
34 /*
35 * Read the instruction
36 */
37 addr = (unsigned int __user *) epc;
38 if (__get_user(insn.word, addr)) {
39 force_sig(SIGSEGV, current);
40 return -EFAULT;
41 }
42 37
43 switch (insn.i_format.opcode) { 38 switch (insn.i_format.opcode) {
44 /* 39 /*
@@ -64,18 +59,22 @@ int __compute_return_epc(struct pt_regs *regs)
64 switch (insn.i_format.rt) { 59 switch (insn.i_format.rt) {
65 case bltz_op: 60 case bltz_op:
66 case bltzl_op: 61 case bltzl_op:
67 if ((long)regs->regs[insn.i_format.rs] < 0) 62 if ((long)regs->regs[insn.i_format.rs] < 0) {
68 epc = epc + 4 + (insn.i_format.simmediate << 2); 63 epc = epc + 4 + (insn.i_format.simmediate << 2);
69 else 64 if (insn.i_format.rt == bltzl_op)
65 ret = BRANCH_LIKELY_TAKEN;
66 } else
70 epc += 8; 67 epc += 8;
71 regs->cp0_epc = epc; 68 regs->cp0_epc = epc;
72 break; 69 break;
73 70
74 case bgez_op: 71 case bgez_op:
75 case bgezl_op: 72 case bgezl_op:
76 if ((long)regs->regs[insn.i_format.rs] >= 0) 73 if ((long)regs->regs[insn.i_format.rs] >= 0) {
77 epc = epc + 4 + (insn.i_format.simmediate << 2); 74 epc = epc + 4 + (insn.i_format.simmediate << 2);
78 else 75 if (insn.i_format.rt == bgezl_op)
76 ret = BRANCH_LIKELY_TAKEN;
77 } else
79 epc += 8; 78 epc += 8;
80 regs->cp0_epc = epc; 79 regs->cp0_epc = epc;
81 break; 80 break;
@@ -83,9 +82,11 @@ int __compute_return_epc(struct pt_regs *regs)
83 case bltzal_op: 82 case bltzal_op:
84 case bltzall_op: 83 case bltzall_op:
85 regs->regs[31] = epc + 8; 84 regs->regs[31] = epc + 8;
86 if ((long)regs->regs[insn.i_format.rs] < 0) 85 if ((long)regs->regs[insn.i_format.rs] < 0) {
87 epc = epc + 4 + (insn.i_format.simmediate << 2); 86 epc = epc + 4 + (insn.i_format.simmediate << 2);
88 else 87 if (insn.i_format.rt == bltzall_op)
88 ret = BRANCH_LIKELY_TAKEN;
89 } else
89 epc += 8; 90 epc += 8;
90 regs->cp0_epc = epc; 91 regs->cp0_epc = epc;
91 break; 92 break;
@@ -93,12 +94,15 @@ int __compute_return_epc(struct pt_regs *regs)
93 case bgezal_op: 94 case bgezal_op:
94 case bgezall_op: 95 case bgezall_op:
95 regs->regs[31] = epc + 8; 96 regs->regs[31] = epc + 8;
96 if ((long)regs->regs[insn.i_format.rs] >= 0) 97 if ((long)regs->regs[insn.i_format.rs] >= 0) {
97 epc = epc + 4 + (insn.i_format.simmediate << 2); 98 epc = epc + 4 + (insn.i_format.simmediate << 2);
98 else 99 if (insn.i_format.rt == bgezall_op)
100 ret = BRANCH_LIKELY_TAKEN;
101 } else
99 epc += 8; 102 epc += 8;
100 regs->cp0_epc = epc; 103 regs->cp0_epc = epc;
101 break; 104 break;
105
102 case bposge32_op: 106 case bposge32_op:
103 if (!cpu_has_dsp) 107 if (!cpu_has_dsp)
104 goto sigill; 108 goto sigill;
@@ -133,9 +137,11 @@ int __compute_return_epc(struct pt_regs *regs)
133 case beq_op: 137 case beq_op:
134 case beql_op: 138 case beql_op:
135 if (regs->regs[insn.i_format.rs] == 139 if (regs->regs[insn.i_format.rs] ==
136 regs->regs[insn.i_format.rt]) 140 regs->regs[insn.i_format.rt]) {
137 epc = epc + 4 + (insn.i_format.simmediate << 2); 141 epc = epc + 4 + (insn.i_format.simmediate << 2);
138 else 142 if (insn.i_format.rt == beql_op)
143 ret = BRANCH_LIKELY_TAKEN;
144 } else
139 epc += 8; 145 epc += 8;
140 regs->cp0_epc = epc; 146 regs->cp0_epc = epc;
141 break; 147 break;
@@ -143,9 +149,11 @@ int __compute_return_epc(struct pt_regs *regs)
143 case bne_op: 149 case bne_op:
144 case bnel_op: 150 case bnel_op:
145 if (regs->regs[insn.i_format.rs] != 151 if (regs->regs[insn.i_format.rs] !=
146 regs->regs[insn.i_format.rt]) 152 regs->regs[insn.i_format.rt]) {
147 epc = epc + 4 + (insn.i_format.simmediate << 2); 153 epc = epc + 4 + (insn.i_format.simmediate << 2);
148 else 154 if (insn.i_format.rt == bnel_op)
155 ret = BRANCH_LIKELY_TAKEN;
156 } else
149 epc += 8; 157 epc += 8;
150 regs->cp0_epc = epc; 158 regs->cp0_epc = epc;
151 break; 159 break;
@@ -153,9 +161,11 @@ int __compute_return_epc(struct pt_regs *regs)
153 case blez_op: /* not really i_format */ 161 case blez_op: /* not really i_format */
154 case blezl_op: 162 case blezl_op:
155 /* rt field assumed to be zero */ 163 /* rt field assumed to be zero */
156 if ((long)regs->regs[insn.i_format.rs] <= 0) 164 if ((long)regs->regs[insn.i_format.rs] <= 0) {
157 epc = epc + 4 + (insn.i_format.simmediate << 2); 165 epc = epc + 4 + (insn.i_format.simmediate << 2);
158 else 166 if (insn.i_format.rt == bnel_op)
167 ret = BRANCH_LIKELY_TAKEN;
168 } else
159 epc += 8; 169 epc += 8;
160 regs->cp0_epc = epc; 170 regs->cp0_epc = epc;
161 break; 171 break;
@@ -163,9 +173,11 @@ int __compute_return_epc(struct pt_regs *regs)
163 case bgtz_op: 173 case bgtz_op:
164 case bgtzl_op: 174 case bgtzl_op:
165 /* rt field assumed to be zero */ 175 /* rt field assumed to be zero */
166 if ((long)regs->regs[insn.i_format.rs] > 0) 176 if ((long)regs->regs[insn.i_format.rs] > 0) {
167 epc = epc + 4 + (insn.i_format.simmediate << 2); 177 epc = epc + 4 + (insn.i_format.simmediate << 2);
168 else 178 if (insn.i_format.rt == bnel_op)
179 ret = BRANCH_LIKELY_TAKEN;
180 } else
169 epc += 8; 181 epc += 8;
170 regs->cp0_epc = epc; 182 regs->cp0_epc = epc;
171 break; 183 break;
@@ -187,18 +199,22 @@ int __compute_return_epc(struct pt_regs *regs)
187 switch (insn.i_format.rt & 3) { 199 switch (insn.i_format.rt & 3) {
188 case 0: /* bc1f */ 200 case 0: /* bc1f */
189 case 2: /* bc1fl */ 201 case 2: /* bc1fl */
190 if (~fcr31 & (1 << bit)) 202 if (~fcr31 & (1 << bit)) {
191 epc = epc + 4 + (insn.i_format.simmediate << 2); 203 epc = epc + 4 + (insn.i_format.simmediate << 2);
192 else 204 if (insn.i_format.rt == 2)
205 ret = BRANCH_LIKELY_TAKEN;
206 } else
193 epc += 8; 207 epc += 8;
194 regs->cp0_epc = epc; 208 regs->cp0_epc = epc;
195 break; 209 break;
196 210
197 case 1: /* bc1t */ 211 case 1: /* bc1t */
198 case 3: /* bc1tl */ 212 case 3: /* bc1tl */
199 if (fcr31 & (1 << bit)) 213 if (fcr31 & (1 << bit)) {
200 epc = epc + 4 + (insn.i_format.simmediate << 2); 214 epc = epc + 4 + (insn.i_format.simmediate << 2);
201 else 215 if (insn.i_format.rt == 3)
216 ret = BRANCH_LIKELY_TAKEN;
217 } else
202 epc += 8; 218 epc += 8;
203 regs->cp0_epc = epc; 219 regs->cp0_epc = epc;
204 break; 220 break;
@@ -239,15 +255,39 @@ int __compute_return_epc(struct pt_regs *regs)
239#endif 255#endif
240 } 256 }
241 257
242 return 0; 258 return ret;
243 259
244unaligned: 260sigill:
245 printk("%s: unaligned epc - sending SIGBUS.\n", current->comm); 261 printk("%s: DSP branch but not DSP ASE - sending SIGBUS.\n", current->comm);
246 force_sig(SIGBUS, current); 262 force_sig(SIGBUS, current);
247 return -EFAULT; 263 return -EFAULT;
264}
265EXPORT_SYMBOL_GPL(__compute_return_epc_for_insn);
248 266
249sigill: 267int __compute_return_epc(struct pt_regs *regs)
250 printk("%s: DSP branch but not DSP ASE - sending SIGBUS.\n", current->comm); 268{
269 unsigned int __user *addr;
270 long epc;
271 union mips_instruction insn;
272
273 epc = regs->cp0_epc;
274 if (epc & 3)
275 goto unaligned;
276
277 /*
278 * Read the instruction
279 */
280 addr = (unsigned int __user *) epc;
281 if (__get_user(insn.word, addr)) {
282 force_sig(SIGSEGV, current);
283 return -EFAULT;
284 }
285
286 return __compute_return_epc_for_insn(regs, insn);
287
288unaligned:
289 printk("%s: unaligned epc - sending SIGBUS.\n", current->comm);
251 force_sig(SIGBUS, current); 290 force_sig(SIGBUS, current);
252 return -EFAULT; 291 return -EFAULT;
292
253} 293}
diff --git a/arch/mips/kernel/cevt-bcm1480.c b/arch/mips/kernel/cevt-bcm1480.c
index 36c3898b76db..69bbfae183bc 100644
--- a/arch/mips/kernel/cevt-bcm1480.c
+++ b/arch/mips/kernel/cevt-bcm1480.c
@@ -145,7 +145,7 @@ void __cpuinit sb1480_clockevent_init(void)
145 bcm1480_unmask_irq(cpu, irq); 145 bcm1480_unmask_irq(cpu, irq);
146 146
147 action->handler = sibyte_counter_handler; 147 action->handler = sibyte_counter_handler;
148 action->flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER; 148 action->flags = IRQF_PERCPU | IRQF_TIMER;
149 action->name = name; 149 action->name = name;
150 action->dev_id = cd; 150 action->dev_id = cd;
151 151
diff --git a/arch/mips/kernel/cevt-ds1287.c b/arch/mips/kernel/cevt-ds1287.c
index 939157e397b9..ed648cb5a69f 100644
--- a/arch/mips/kernel/cevt-ds1287.c
+++ b/arch/mips/kernel/cevt-ds1287.c
@@ -108,7 +108,7 @@ static irqreturn_t ds1287_interrupt(int irq, void *dev_id)
108 108
109static struct irqaction ds1287_irqaction = { 109static struct irqaction ds1287_irqaction = {
110 .handler = ds1287_interrupt, 110 .handler = ds1287_interrupt,
111 .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER, 111 .flags = IRQF_PERCPU | IRQF_TIMER,
112 .name = "ds1287", 112 .name = "ds1287",
113}; 113};
114 114
diff --git a/arch/mips/kernel/cevt-gt641xx.c b/arch/mips/kernel/cevt-gt641xx.c
index 339f3639b90e..831b47585b7c 100644
--- a/arch/mips/kernel/cevt-gt641xx.c
+++ b/arch/mips/kernel/cevt-gt641xx.c
@@ -114,7 +114,7 @@ static irqreturn_t gt641xx_timer0_interrupt(int irq, void *dev_id)
114 114
115static struct irqaction gt641xx_timer0_irqaction = { 115static struct irqaction gt641xx_timer0_irqaction = {
116 .handler = gt641xx_timer0_interrupt, 116 .handler = gt641xx_timer0_interrupt,
117 .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER, 117 .flags = IRQF_PERCPU | IRQF_TIMER,
118 .name = "gt641xx_timer0", 118 .name = "gt641xx_timer0",
119}; 119};
120 120
diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index e2d8e199be32..51095dd9599d 100644
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -84,7 +84,7 @@ out:
84 84
85struct irqaction c0_compare_irqaction = { 85struct irqaction c0_compare_irqaction = {
86 .handler = c0_compare_interrupt, 86 .handler = c0_compare_interrupt,
87 .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER, 87 .flags = IRQF_PERCPU | IRQF_TIMER,
88 .name = "timer", 88 .name = "timer",
89}; 89};
90 90
diff --git a/arch/mips/kernel/cevt-sb1250.c b/arch/mips/kernel/cevt-sb1250.c
index 590c54f28a81..e73439fd6850 100644
--- a/arch/mips/kernel/cevt-sb1250.c
+++ b/arch/mips/kernel/cevt-sb1250.c
@@ -144,7 +144,7 @@ void __cpuinit sb1250_clockevent_init(void)
144 sb1250_unmask_irq(cpu, irq); 144 sb1250_unmask_irq(cpu, irq);
145 145
146 action->handler = sibyte_counter_handler; 146 action->handler = sibyte_counter_handler;
147 action->flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER; 147 action->flags = IRQF_PERCPU | IRQF_TIMER;
148 action->name = name; 148 action->name = name;
149 action->dev_id = cd; 149 action->dev_id = cd;
150 150
diff --git a/arch/mips/kernel/cevt-txx9.c b/arch/mips/kernel/cevt-txx9.c
index f0ab92a1b057..e5c30b1d0860 100644
--- a/arch/mips/kernel/cevt-txx9.c
+++ b/arch/mips/kernel/cevt-txx9.c
@@ -146,7 +146,7 @@ static irqreturn_t txx9tmr_interrupt(int irq, void *dev_id)
146 146
147static struct irqaction txx9tmr_irq = { 147static struct irqaction txx9tmr_irq = {
148 .handler = txx9tmr_interrupt, 148 .handler = txx9tmr_interrupt,
149 .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER, 149 .flags = IRQF_PERCPU | IRQF_TIMER,
150 .name = "txx9tmr", 150 .name = "txx9tmr",
151 .dev_id = &txx9_clock_event_device, 151 .dev_id = &txx9_clock_event_device,
152}; 152};
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index c7d3cf1ce46e..0bab464b8e33 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -191,6 +191,8 @@ void __init check_wait(void)
191 case CPU_CAVIUM_OCTEON_PLUS: 191 case CPU_CAVIUM_OCTEON_PLUS:
192 case CPU_CAVIUM_OCTEON2: 192 case CPU_CAVIUM_OCTEON2:
193 case CPU_JZRISC: 193 case CPU_JZRISC:
194 case CPU_XLR:
195 case CPU_XLP:
194 cpu_wait = r4k_wait; 196 cpu_wait = r4k_wait;
195 break; 197 break;
196 198
@@ -1014,6 +1016,13 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1014{ 1016{
1015 decode_configs(c); 1017 decode_configs(c);
1016 1018
1019 if ((c->processor_id & 0xff00) == PRID_IMP_NETLOGIC_AU13XX) {
1020 c->cputype = CPU_ALCHEMY;
1021 __cpu_name[cpu] = "Au1300";
1022 /* following stuff is not for Alchemy */
1023 return;
1024 }
1025
1017 c->options = (MIPS_CPU_TLB | 1026 c->options = (MIPS_CPU_TLB |
1018 MIPS_CPU_4KEX | 1027 MIPS_CPU_4KEX |
1019 MIPS_CPU_COUNTER | 1028 MIPS_CPU_COUNTER |
@@ -1023,6 +1032,12 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1023 MIPS_CPU_LLSC); 1032 MIPS_CPU_LLSC);
1024 1033
1025 switch (c->processor_id & 0xff00) { 1034 switch (c->processor_id & 0xff00) {
1035 case PRID_IMP_NETLOGIC_XLP8XX:
1036 case PRID_IMP_NETLOGIC_XLP3XX:
1037 c->cputype = CPU_XLP;
1038 __cpu_name[cpu] = "Netlogic XLP";
1039 break;
1040
1026 case PRID_IMP_NETLOGIC_XLR732: 1041 case PRID_IMP_NETLOGIC_XLR732:
1027 case PRID_IMP_NETLOGIC_XLR716: 1042 case PRID_IMP_NETLOGIC_XLR716:
1028 case PRID_IMP_NETLOGIC_XLR532: 1043 case PRID_IMP_NETLOGIC_XLR532:
@@ -1053,14 +1068,21 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1053 break; 1068 break;
1054 1069
1055 default: 1070 default:
1056 printk(KERN_INFO "Unknown Netlogic chip id [%02x]!\n", 1071 pr_info("Unknown Netlogic chip id [%02x]!\n",
1057 c->processor_id); 1072 c->processor_id);
1058 c->cputype = CPU_XLR; 1073 c->cputype = CPU_XLR;
1059 break; 1074 break;
1060 } 1075 }
1061 1076
1062 c->isa_level = MIPS_CPU_ISA_M64R1; 1077 if (c->cputype == CPU_XLP) {
1063 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1; 1078 c->isa_level = MIPS_CPU_ISA_M64R2;
1079 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1080 /* This will be updated again after all threads are woken up */
1081 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1082 } else {
1083 c->isa_level = MIPS_CPU_ISA_M64R1;
1084 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1085 }
1064} 1086}
1065 1087
1066#ifdef CONFIG_64BIT 1088#ifdef CONFIG_64BIT
diff --git a/arch/mips/kernel/i8253.c b/arch/mips/kernel/i8253.c
index 7047bff35ea5..c5bc344fc745 100644
--- a/arch/mips/kernel/i8253.c
+++ b/arch/mips/kernel/i8253.c
@@ -19,7 +19,7 @@ static irqreturn_t timer_interrupt(int irq, void *dev_id)
19 19
20static struct irqaction irq0 = { 20static struct irqaction irq0 = {
21 .handler = timer_interrupt, 21 .handler = timer_interrupt,
22 .flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_TIMER, 22 .flags = IRQF_NOBALANCING | IRQF_TIMER,
23 .name = "timer" 23 .name = "timer"
24}; 24};
25 25
diff --git a/arch/mips/kernel/kprobes.c b/arch/mips/kernel/kprobes.c
index ee28683fc2ac..158467da9bc1 100644
--- a/arch/mips/kernel/kprobes.c
+++ b/arch/mips/kernel/kprobes.c
@@ -25,10 +25,12 @@
25 25
26#include <linux/kprobes.h> 26#include <linux/kprobes.h>
27#include <linux/preempt.h> 27#include <linux/preempt.h>
28#include <linux/uaccess.h>
28#include <linux/kdebug.h> 29#include <linux/kdebug.h>
29#include <linux/slab.h> 30#include <linux/slab.h>
30 31
31#include <asm/ptrace.h> 32#include <asm/ptrace.h>
33#include <asm/branch.h>
32#include <asm/break.h> 34#include <asm/break.h>
33#include <asm/inst.h> 35#include <asm/inst.h>
34 36
@@ -112,17 +114,49 @@ insn_ok:
112 return 0; 114 return 0;
113} 115}
114 116
117/*
118 * insn_has_ll_or_sc function checks whether instruction is ll or sc
119 * one; putting breakpoint on top of atomic ll/sc pair is bad idea;
120 * so we need to prevent it and refuse kprobes insertion for such
121 * instructions; cannot do much about breakpoint in the middle of
122 * ll/sc pair; it is upto user to avoid those places
123 */
124static int __kprobes insn_has_ll_or_sc(union mips_instruction insn)
125{
126 int ret = 0;
127
128 switch (insn.i_format.opcode) {
129 case ll_op:
130 case lld_op:
131 case sc_op:
132 case scd_op:
133 ret = 1;
134 break;
135 default:
136 break;
137 }
138 return ret;
139}
140
115int __kprobes arch_prepare_kprobe(struct kprobe *p) 141int __kprobes arch_prepare_kprobe(struct kprobe *p)
116{ 142{
117 union mips_instruction insn; 143 union mips_instruction insn;
118 union mips_instruction prev_insn; 144 union mips_instruction prev_insn;
119 int ret = 0; 145 int ret = 0;
120 146
121 prev_insn = p->addr[-1];
122 insn = p->addr[0]; 147 insn = p->addr[0];
123 148
124 if (insn_has_delayslot(insn) || insn_has_delayslot(prev_insn)) { 149 if (insn_has_ll_or_sc(insn)) {
125 pr_notice("Kprobes for branch and jump instructions are not supported\n"); 150 pr_notice("Kprobes for ll and sc instructions are not"
151 "supported\n");
152 ret = -EINVAL;
153 goto out;
154 }
155
156 if ((probe_kernel_read(&prev_insn, p->addr - 1,
157 sizeof(mips_instruction)) == 0) &&
158 insn_has_delayslot(prev_insn)) {
159 pr_notice("Kprobes for branch delayslot are not supported\n");
126 ret = -EINVAL; 160 ret = -EINVAL;
127 goto out; 161 goto out;
128 } 162 }
@@ -138,9 +172,20 @@ int __kprobes arch_prepare_kprobe(struct kprobe *p)
138 * In the kprobe->ainsn.insn[] array we store the original 172 * In the kprobe->ainsn.insn[] array we store the original
139 * instruction at index zero and a break trap instruction at 173 * instruction at index zero and a break trap instruction at
140 * index one. 174 * index one.
175 *
176 * On MIPS arch if the instruction at probed address is a
177 * branch instruction, we need to execute the instruction at
178 * Branch Delayslot (BD) at the time of probe hit. As MIPS also
179 * doesn't have single stepping support, the BD instruction can
180 * not be executed in-line and it would be executed on SSOL slot
181 * using a normal breakpoint instruction in the next slot.
182 * So, read the instruction and save it for later execution.
141 */ 183 */
184 if (insn_has_delayslot(insn))
185 memcpy(&p->ainsn.insn[0], p->addr + 1, sizeof(kprobe_opcode_t));
186 else
187 memcpy(&p->ainsn.insn[0], p->addr, sizeof(kprobe_opcode_t));
142 188
143 memcpy(&p->ainsn.insn[0], p->addr, sizeof(kprobe_opcode_t));
144 p->ainsn.insn[1] = breakpoint2_insn; 189 p->ainsn.insn[1] = breakpoint2_insn;
145 p->opcode = *p->addr; 190 p->opcode = *p->addr;
146 191
@@ -191,16 +236,96 @@ static void set_current_kprobe(struct kprobe *p, struct pt_regs *regs,
191 kcb->kprobe_saved_epc = regs->cp0_epc; 236 kcb->kprobe_saved_epc = regs->cp0_epc;
192} 237}
193 238
194static void prepare_singlestep(struct kprobe *p, struct pt_regs *regs) 239/**
240 * evaluate_branch_instrucion -
241 *
242 * Evaluate the branch instruction at probed address during probe hit. The
243 * result of evaluation would be the updated epc. The insturction in delayslot
244 * would actually be single stepped using a normal breakpoint) on SSOL slot.
245 *
246 * The result is also saved in the kprobe control block for later use,
247 * in case we need to execute the delayslot instruction. The latter will be
248 * false for NOP instruction in dealyslot and the branch-likely instructions
249 * when the branch is taken. And for those cases we set a flag as
250 * SKIP_DELAYSLOT in the kprobe control block
251 */
252static int evaluate_branch_instruction(struct kprobe *p, struct pt_regs *regs,
253 struct kprobe_ctlblk *kcb)
195{ 254{
255 union mips_instruction insn = p->opcode;
256 long epc;
257 int ret = 0;
258
259 epc = regs->cp0_epc;
260 if (epc & 3)
261 goto unaligned;
262
263 if (p->ainsn.insn->word == 0)
264 kcb->flags |= SKIP_DELAYSLOT;
265 else
266 kcb->flags &= ~SKIP_DELAYSLOT;
267
268 ret = __compute_return_epc_for_insn(regs, insn);
269 if (ret < 0)
270 return ret;
271
272 if (ret == BRANCH_LIKELY_TAKEN)
273 kcb->flags |= SKIP_DELAYSLOT;
274
275 kcb->target_epc = regs->cp0_epc;
276
277 return 0;
278
279unaligned:
280 pr_notice("%s: unaligned epc - sending SIGBUS.\n", current->comm);
281 force_sig(SIGBUS, current);
282 return -EFAULT;
283
284}
285
286static void prepare_singlestep(struct kprobe *p, struct pt_regs *regs,
287 struct kprobe_ctlblk *kcb)
288{
289 int ret = 0;
290
196 regs->cp0_status &= ~ST0_IE; 291 regs->cp0_status &= ~ST0_IE;
197 292
198 /* single step inline if the instruction is a break */ 293 /* single step inline if the instruction is a break */
199 if (p->opcode.word == breakpoint_insn.word || 294 if (p->opcode.word == breakpoint_insn.word ||
200 p->opcode.word == breakpoint2_insn.word) 295 p->opcode.word == breakpoint2_insn.word)
201 regs->cp0_epc = (unsigned long)p->addr; 296 regs->cp0_epc = (unsigned long)p->addr;
202 else 297 else if (insn_has_delayslot(p->opcode)) {
203 regs->cp0_epc = (unsigned long)&p->ainsn.insn[0]; 298 ret = evaluate_branch_instruction(p, regs, kcb);
299 if (ret < 0) {
300 pr_notice("Kprobes: Error in evaluating branch\n");
301 return;
302 }
303 }
304 regs->cp0_epc = (unsigned long)&p->ainsn.insn[0];
305}
306
307/*
308 * Called after single-stepping. p->addr is the address of the
309 * instruction whose first byte has been replaced by the "break 0"
310 * instruction. To avoid the SMP problems that can occur when we
311 * temporarily put back the original opcode to single-step, we
312 * single-stepped a copy of the instruction. The address of this
313 * copy is p->ainsn.insn.
314 *
315 * This function prepares to return from the post-single-step
316 * breakpoint trap. In case of branch instructions, the target
317 * epc to be restored.
318 */
319static void __kprobes resume_execution(struct kprobe *p,
320 struct pt_regs *regs,
321 struct kprobe_ctlblk *kcb)
322{
323 if (insn_has_delayslot(p->opcode))
324 regs->cp0_epc = kcb->target_epc;
325 else {
326 unsigned long orig_epc = kcb->kprobe_saved_epc;
327 regs->cp0_epc = orig_epc + 4;
328 }
204} 329}
205 330
206static int __kprobes kprobe_handler(struct pt_regs *regs) 331static int __kprobes kprobe_handler(struct pt_regs *regs)
@@ -239,8 +364,13 @@ static int __kprobes kprobe_handler(struct pt_regs *regs)
239 save_previous_kprobe(kcb); 364 save_previous_kprobe(kcb);
240 set_current_kprobe(p, regs, kcb); 365 set_current_kprobe(p, regs, kcb);
241 kprobes_inc_nmissed_count(p); 366 kprobes_inc_nmissed_count(p);
242 prepare_singlestep(p, regs); 367 prepare_singlestep(p, regs, kcb);
243 kcb->kprobe_status = KPROBE_REENTER; 368 kcb->kprobe_status = KPROBE_REENTER;
369 if (kcb->flags & SKIP_DELAYSLOT) {
370 resume_execution(p, regs, kcb);
371 restore_previous_kprobe(kcb);
372 preempt_enable_no_resched();
373 }
244 return 1; 374 return 1;
245 } else { 375 } else {
246 if (addr->word != breakpoint_insn.word) { 376 if (addr->word != breakpoint_insn.word) {
@@ -284,8 +414,16 @@ static int __kprobes kprobe_handler(struct pt_regs *regs)
284 } 414 }
285 415
286ss_probe: 416ss_probe:
287 prepare_singlestep(p, regs); 417 prepare_singlestep(p, regs, kcb);
288 kcb->kprobe_status = KPROBE_HIT_SS; 418 if (kcb->flags & SKIP_DELAYSLOT) {
419 kcb->kprobe_status = KPROBE_HIT_SSDONE;
420 if (p->post_handler)
421 p->post_handler(p, regs, 0);
422 resume_execution(p, regs, kcb);
423 preempt_enable_no_resched();
424 } else
425 kcb->kprobe_status = KPROBE_HIT_SS;
426
289 return 1; 427 return 1;
290 428
291no_kprobe: 429no_kprobe:
@@ -294,25 +432,6 @@ no_kprobe:
294 432
295} 433}
296 434
297/*
298 * Called after single-stepping. p->addr is the address of the
299 * instruction whose first byte has been replaced by the "break 0"
300 * instruction. To avoid the SMP problems that can occur when we
301 * temporarily put back the original opcode to single-step, we
302 * single-stepped a copy of the instruction. The address of this
303 * copy is p->ainsn.insn.
304 *
305 * This function prepares to return from the post-single-step
306 * breakpoint trap.
307 */
308static void __kprobes resume_execution(struct kprobe *p,
309 struct pt_regs *regs,
310 struct kprobe_ctlblk *kcb)
311{
312 unsigned long orig_epc = kcb->kprobe_saved_epc;
313 regs->cp0_epc = orig_epc + 4;
314}
315
316static inline int post_kprobe_handler(struct pt_regs *regs) 435static inline int post_kprobe_handler(struct pt_regs *regs)
317{ 436{
318 struct kprobe *cur = kprobe_running(); 437 struct kprobe *cur = kprobe_running();
diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index 4f2971bcf8e5..bda4bc9e6988 100644
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -621,11 +621,6 @@ static int mipspmu_event_init(struct perf_event *event)
621 return -ENODEV; 621 return -ENODEV;
622 622
623 if (!atomic_inc_not_zero(&active_events)) { 623 if (!atomic_inc_not_zero(&active_events)) {
624 if (atomic_read(&active_events) > MIPS_MAX_HWEVENTS) {
625 atomic_dec(&active_events);
626 return -ENOSPC;
627 }
628
629 mutex_lock(&pmu_reserve_mutex); 624 mutex_lock(&pmu_reserve_mutex);
630 if (atomic_read(&active_events) == 0) 625 if (atomic_read(&active_events) == 0)
631 err = mipspmu_get_irq(); 626 err = mipspmu_get_irq();
@@ -638,11 +633,7 @@ static int mipspmu_event_init(struct perf_event *event)
638 if (err) 633 if (err)
639 return err; 634 return err;
640 635
641 err = __hw_perf_event_init(event); 636 return __hw_perf_event_init(event);
642 if (err)
643 hw_perf_event_destroy(event);
644
645 return err;
646} 637}
647 638
648static struct pmu pmu = { 639static struct pmu pmu = {
@@ -712,18 +703,6 @@ static const struct mips_perf_event *mipspmu_map_cache_event(u64 config)
712 703
713} 704}
714 705
715static int validate_event(struct cpu_hw_events *cpuc,
716 struct perf_event *event)
717{
718 struct hw_perf_event fake_hwc = event->hw;
719
720 /* Allow mixed event group. So return 1 to pass validation. */
721 if (event->pmu != &pmu || event->state <= PERF_EVENT_STATE_OFF)
722 return 1;
723
724 return mipsxx_pmu_alloc_counter(cpuc, &fake_hwc) >= 0;
725}
726
727static int validate_group(struct perf_event *event) 706static int validate_group(struct perf_event *event)
728{ 707{
729 struct perf_event *sibling, *leader = event->group_leader; 708 struct perf_event *sibling, *leader = event->group_leader;
@@ -731,15 +710,15 @@ static int validate_group(struct perf_event *event)
731 710
732 memset(&fake_cpuc, 0, sizeof(fake_cpuc)); 711 memset(&fake_cpuc, 0, sizeof(fake_cpuc));
733 712
734 if (!validate_event(&fake_cpuc, leader)) 713 if (mipsxx_pmu_alloc_counter(&fake_cpuc, &leader->hw) < 0)
735 return -ENOSPC; 714 return -ENOSPC;
736 715
737 list_for_each_entry(sibling, &leader->sibling_list, group_entry) { 716 list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
738 if (!validate_event(&fake_cpuc, sibling)) 717 if (mipsxx_pmu_alloc_counter(&fake_cpuc, &sibling->hw) < 0)
739 return -ENOSPC; 718 return -ENOSPC;
740 } 719 }
741 720
742 if (!validate_event(&fake_cpuc, event)) 721 if (mipsxx_pmu_alloc_counter(&fake_cpuc, &event->hw) < 0)
743 return -ENOSPC; 722 return -ENOSPC;
744 723
745 return 0; 724 return 0;
@@ -1279,13 +1258,14 @@ static int __hw_perf_event_init(struct perf_event *event)
1279 } 1258 }
1280 1259
1281 err = 0; 1260 err = 0;
1282 if (event->group_leader != event) { 1261 if (event->group_leader != event)
1283 err = validate_group(event); 1262 err = validate_group(event);
1284 if (err)
1285 return -EINVAL;
1286 }
1287 1263
1288 event->destroy = hw_perf_event_destroy; 1264 event->destroy = hw_perf_event_destroy;
1265
1266 if (err)
1267 event->destroy(event);
1268
1289 return err; 1269 return err;
1290} 1270}
1291 1271
@@ -1380,20 +1360,10 @@ static irqreturn_t mipsxx_pmu_handle_irq(int irq, void *dev)
1380} 1360}
1381 1361
1382/* 24K */ 1362/* 24K */
1383#define IS_UNSUPPORTED_24K_EVENT(r, b) \
1384 ((b) == 12 || (r) == 151 || (r) == 152 || (b) == 26 || \
1385 (b) == 27 || (r) == 28 || (r) == 158 || (b) == 31 || \
1386 (b) == 32 || (b) == 34 || (b) == 36 || (r) == 168 || \
1387 (r) == 172 || (b) == 47 || ((b) >= 56 && (b) <= 63) || \
1388 ((b) >= 68 && (b) <= 127))
1389#define IS_BOTH_COUNTERS_24K_EVENT(b) \ 1363#define IS_BOTH_COUNTERS_24K_EVENT(b) \
1390 ((b) == 0 || (b) == 1 || (b) == 11) 1364 ((b) == 0 || (b) == 1 || (b) == 11)
1391 1365
1392/* 34K */ 1366/* 34K */
1393#define IS_UNSUPPORTED_34K_EVENT(r, b) \
1394 ((b) == 12 || (r) == 27 || (r) == 158 || (b) == 36 || \
1395 (b) == 38 || (r) == 175 || ((b) >= 56 && (b) <= 63) || \
1396 ((b) >= 68 && (b) <= 127))
1397#define IS_BOTH_COUNTERS_34K_EVENT(b) \ 1367#define IS_BOTH_COUNTERS_34K_EVENT(b) \
1398 ((b) == 0 || (b) == 1 || (b) == 11) 1368 ((b) == 0 || (b) == 1 || (b) == 11)
1399#ifdef CONFIG_MIPS_MT_SMP 1369#ifdef CONFIG_MIPS_MT_SMP
@@ -1406,20 +1376,10 @@ static irqreturn_t mipsxx_pmu_handle_irq(int irq, void *dev)
1406#endif 1376#endif
1407 1377
1408/* 74K */ 1378/* 74K */
1409#define IS_UNSUPPORTED_74K_EVENT(r, b) \
1410 ((r) == 5 || ((r) >= 135 && (r) <= 137) || \
1411 ((b) >= 10 && (b) <= 12) || (b) == 22 || (b) == 27 || \
1412 (b) == 33 || (b) == 34 || ((b) >= 47 && (b) <= 49) || \
1413 (r) == 178 || (b) == 55 || (b) == 57 || (b) == 60 || \
1414 (b) == 61 || (r) == 62 || (r) == 191 || \
1415 ((b) >= 64 && (b) <= 127))
1416#define IS_BOTH_COUNTERS_74K_EVENT(b) \ 1379#define IS_BOTH_COUNTERS_74K_EVENT(b) \
1417 ((b) == 0 || (b) == 1) 1380 ((b) == 0 || (b) == 1)
1418 1381
1419/* 1004K */ 1382/* 1004K */
1420#define IS_UNSUPPORTED_1004K_EVENT(r, b) \
1421 ((b) == 12 || (r) == 27 || (r) == 158 || (b) == 38 || \
1422 (r) == 175 || (b) == 63 || ((b) >= 68 && (b) <= 127))
1423#define IS_BOTH_COUNTERS_1004K_EVENT(b) \ 1383#define IS_BOTH_COUNTERS_1004K_EVENT(b) \
1424 ((b) == 0 || (b) == 1 || (b) == 11) 1384 ((b) == 0 || (b) == 1 || (b) == 11)
1425#ifdef CONFIG_MIPS_MT_SMP 1385#ifdef CONFIG_MIPS_MT_SMP
@@ -1445,11 +1405,10 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
1445 unsigned int raw_id = config & 0xff; 1405 unsigned int raw_id = config & 0xff;
1446 unsigned int base_id = raw_id & 0x7f; 1406 unsigned int base_id = raw_id & 0x7f;
1447 1407
1408 raw_event.event_id = base_id;
1409
1448 switch (current_cpu_type()) { 1410 switch (current_cpu_type()) {
1449 case CPU_24K: 1411 case CPU_24K:
1450 if (IS_UNSUPPORTED_24K_EVENT(raw_id, base_id))
1451 return ERR_PTR(-EOPNOTSUPP);
1452 raw_event.event_id = base_id;
1453 if (IS_BOTH_COUNTERS_24K_EVENT(base_id)) 1412 if (IS_BOTH_COUNTERS_24K_EVENT(base_id))
1454 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; 1413 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1455 else 1414 else
@@ -1464,9 +1423,6 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
1464#endif 1423#endif
1465 break; 1424 break;
1466 case CPU_34K: 1425 case CPU_34K:
1467 if (IS_UNSUPPORTED_34K_EVENT(raw_id, base_id))
1468 return ERR_PTR(-EOPNOTSUPP);
1469 raw_event.event_id = base_id;
1470 if (IS_BOTH_COUNTERS_34K_EVENT(base_id)) 1426 if (IS_BOTH_COUNTERS_34K_EVENT(base_id))
1471 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; 1427 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1472 else 1428 else
@@ -1482,9 +1438,6 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
1482#endif 1438#endif
1483 break; 1439 break;
1484 case CPU_74K: 1440 case CPU_74K:
1485 if (IS_UNSUPPORTED_74K_EVENT(raw_id, base_id))
1486 return ERR_PTR(-EOPNOTSUPP);
1487 raw_event.event_id = base_id;
1488 if (IS_BOTH_COUNTERS_74K_EVENT(base_id)) 1441 if (IS_BOTH_COUNTERS_74K_EVENT(base_id))
1489 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; 1442 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1490 else 1443 else
@@ -1495,9 +1448,6 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
1495#endif 1448#endif
1496 break; 1449 break;
1497 case CPU_1004K: 1450 case CPU_1004K:
1498 if (IS_UNSUPPORTED_1004K_EVENT(raw_id, base_id))
1499 return ERR_PTR(-EOPNOTSUPP);
1500 raw_event.event_id = base_id;
1501 if (IS_BOTH_COUNTERS_1004K_EVENT(base_id)) 1451 if (IS_BOTH_COUNTERS_1004K_EVENT(base_id))
1502 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; 1452 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1503 else 1453 else
diff --git a/arch/mips/kernel/rtlx.c b/arch/mips/kernel/rtlx.c
index 933166f44a6d..a9d801dec6b0 100644
--- a/arch/mips/kernel/rtlx.c
+++ b/arch/mips/kernel/rtlx.c
@@ -473,7 +473,6 @@ static const struct file_operations rtlx_fops = {
473 473
474static struct irqaction rtlx_irq = { 474static struct irqaction rtlx_irq = {
475 .handler = rtlx_interrupt, 475 .handler = rtlx_interrupt,
476 .flags = IRQF_DISABLED,
477 .name = "RTLX", 476 .name = "RTLX",
478}; 477};
479 478
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 84af26ab2212..e86c2cf554aa 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -121,6 +121,9 @@ static void __init print_memory_map(void)
121 case BOOT_MEM_RAM: 121 case BOOT_MEM_RAM:
122 printk(KERN_CONT "(usable)\n"); 122 printk(KERN_CONT "(usable)\n");
123 break; 123 break;
124 case BOOT_MEM_INIT_RAM:
125 printk(KERN_CONT "(usable after init)\n");
126 break;
124 case BOOT_MEM_ROM_DATA: 127 case BOOT_MEM_ROM_DATA:
125 printk(KERN_CONT "(ROM data)\n"); 128 printk(KERN_CONT "(ROM data)\n");
126 break; 129 break;
@@ -361,15 +364,24 @@ static void __init bootmem_init(void)
361 for (i = 0; i < boot_mem_map.nr_map; i++) { 364 for (i = 0; i < boot_mem_map.nr_map; i++) {
362 unsigned long start, end, size; 365 unsigned long start, end, size;
363 366
367 start = PFN_UP(boot_mem_map.map[i].addr);
368 end = PFN_DOWN(boot_mem_map.map[i].addr
369 + boot_mem_map.map[i].size);
370
364 /* 371 /*
365 * Reserve usable memory. 372 * Reserve usable memory.
366 */ 373 */
367 if (boot_mem_map.map[i].type != BOOT_MEM_RAM) 374 switch (boot_mem_map.map[i].type) {
375 case BOOT_MEM_RAM:
376 break;
377 case BOOT_MEM_INIT_RAM:
378 memory_present(0, start, end);
368 continue; 379 continue;
380 default:
381 /* Not usable memory */
382 continue;
383 }
369 384
370 start = PFN_UP(boot_mem_map.map[i].addr);
371 end = PFN_DOWN(boot_mem_map.map[i].addr
372 + boot_mem_map.map[i].size);
373 /* 385 /*
374 * We are rounding up the start address of usable memory 386 * We are rounding up the start address of usable memory
375 * and at the end of the usable range downwards. 387 * and at the end of the usable range downwards.
@@ -455,11 +467,33 @@ early_param("mem", early_parse_mem);
455 467
456static void __init arch_mem_init(char **cmdline_p) 468static void __init arch_mem_init(char **cmdline_p)
457{ 469{
470 phys_t init_mem, init_end, init_size;
471
458 extern void plat_mem_setup(void); 472 extern void plat_mem_setup(void);
459 473
460 /* call board setup routine */ 474 /* call board setup routine */
461 plat_mem_setup(); 475 plat_mem_setup();
462 476
477 init_mem = PFN_UP(__pa_symbol(&__init_begin)) << PAGE_SHIFT;
478 init_end = PFN_DOWN(__pa_symbol(&__init_end)) << PAGE_SHIFT;
479 init_size = init_end - init_mem;
480 if (init_size) {
481 /* Make sure it is in the boot_mem_map */
482 int i, found;
483 found = 0;
484 for (i = 0; i < boot_mem_map.nr_map; i++) {
485 if (init_mem >= boot_mem_map.map[i].addr &&
486 init_mem < (boot_mem_map.map[i].addr +
487 boot_mem_map.map[i].size)) {
488 found = 1;
489 break;
490 }
491 }
492 if (!found)
493 add_memory_region(init_mem, init_size,
494 BOOT_MEM_INIT_RAM);
495 }
496
463 pr_info("Determined physical RAM map:\n"); 497 pr_info("Determined physical RAM map:\n");
464 print_memory_map(); 498 print_memory_map();
465 499
@@ -523,6 +557,7 @@ static void __init resource_init(void)
523 res = alloc_bootmem(sizeof(struct resource)); 557 res = alloc_bootmem(sizeof(struct resource));
524 switch (boot_mem_map.map[i].type) { 558 switch (boot_mem_map.map[i].type) {
525 case BOOT_MEM_RAM: 559 case BOOT_MEM_RAM:
560 case BOOT_MEM_INIT_RAM:
526 case BOOT_MEM_ROM_DATA: 561 case BOOT_MEM_ROM_DATA:
527 res->name = "System RAM"; 562 res->name = "System RAM";
528 break; 563 break;
diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c
new file mode 100644
index 000000000000..58fe71afd879
--- /dev/null
+++ b/arch/mips/kernel/smp-bmips.c
@@ -0,0 +1,458 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
7 *
8 * SMP support for BMIPS
9 */
10
11#include <linux/version.h>
12#include <linux/init.h>
13#include <linux/sched.h>
14#include <linux/mm.h>
15#include <linux/delay.h>
16#include <linux/smp.h>
17#include <linux/interrupt.h>
18#include <linux/spinlock.h>
19#include <linux/init.h>
20#include <linux/cpu.h>
21#include <linux/cpumask.h>
22#include <linux/reboot.h>
23#include <linux/io.h>
24#include <linux/compiler.h>
25#include <linux/linkage.h>
26#include <linux/bug.h>
27#include <linux/kernel.h>
28
29#include <asm/time.h>
30#include <asm/pgtable.h>
31#include <asm/processor.h>
32#include <asm/system.h>
33#include <asm/bootinfo.h>
34#include <asm/pmon.h>
35#include <asm/cacheflush.h>
36#include <asm/tlbflush.h>
37#include <asm/mipsregs.h>
38#include <asm/bmips.h>
39#include <asm/traps.h>
40#include <asm/barrier.h>
41
42static int __maybe_unused max_cpus = 1;
43
44/* these may be configured by the platform code */
45int bmips_smp_enabled = 1;
46int bmips_cpu_offset;
47cpumask_t bmips_booted_mask;
48
49#ifdef CONFIG_SMP
50
51/* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */
52unsigned long bmips_smp_boot_sp;
53unsigned long bmips_smp_boot_gp;
54
55static void bmips_send_ipi_single(int cpu, unsigned int action);
56static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id);
57
58/* SW interrupts 0,1 are used for interprocessor signaling */
59#define IPI0_IRQ (MIPS_CPU_IRQ_BASE + 0)
60#define IPI1_IRQ (MIPS_CPU_IRQ_BASE + 1)
61
62#define CPUNUM(cpu, shift) (((cpu) + bmips_cpu_offset) << (shift))
63#define ACTION_CLR_IPI(cpu, ipi) (0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8))
64#define ACTION_SET_IPI(cpu, ipi) (0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8))
65#define ACTION_BOOT_THREAD(cpu) (0x08 | CPUNUM(cpu, 0))
66
67static void __init bmips_smp_setup(void)
68{
69 int i;
70
71#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
72 /* arbitration priority */
73 clear_c0_brcm_cmt_ctrl(0x30);
74
75 /* NBK and weak order flags */
76 set_c0_brcm_config_0(0x30000);
77
78 /*
79 * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other thread
80 * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
81 * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
82 */
83 change_c0_brcm_cmt_intr(0xf8018000,
84 (0x02 << 27) | (0x03 << 15));
85
86 /* single core, 2 threads (2 pipelines) */
87 max_cpus = 2;
88#elif defined(CONFIG_CPU_BMIPS5000)
89 /* enable raceless SW interrupts */
90 set_c0_brcm_config(0x03 << 22);
91
92 /* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */
93 change_c0_brcm_mode(0x1f << 27, 0x02 << 27);
94
95 /* N cores, 2 threads per core */
96 max_cpus = (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1;
97
98 /* clear any pending SW interrupts */
99 for (i = 0; i < max_cpus; i++) {
100 write_c0_brcm_action(ACTION_CLR_IPI(i, 0));
101 write_c0_brcm_action(ACTION_CLR_IPI(i, 1));
102 }
103#endif
104
105 if (!bmips_smp_enabled)
106 max_cpus = 1;
107
108 /* this can be overridden by the BSP */
109 if (!board_ebase_setup)
110 board_ebase_setup = &bmips_ebase_setup;
111
112 for (i = 0; i < max_cpus; i++) {
113 __cpu_number_map[i] = 1;
114 __cpu_logical_map[i] = 1;
115 set_cpu_possible(i, 1);
116 set_cpu_present(i, 1);
117 }
118}
119
120/*
121 * IPI IRQ setup - runs on CPU0
122 */
123static void bmips_prepare_cpus(unsigned int max_cpus)
124{
125 if (request_irq(IPI0_IRQ, bmips_ipi_interrupt, IRQF_PERCPU,
126 "smp_ipi0", NULL))
127 panic("Can't request IPI0 interrupt\n");
128 if (request_irq(IPI1_IRQ, bmips_ipi_interrupt, IRQF_PERCPU,
129 "smp_ipi1", NULL))
130 panic("Can't request IPI1 interrupt\n");
131}
132
133/*
134 * Tell the hardware to boot CPUx - runs on CPU0
135 */
136static void bmips_boot_secondary(int cpu, struct task_struct *idle)
137{
138 bmips_smp_boot_sp = __KSTK_TOS(idle);
139 bmips_smp_boot_gp = (unsigned long)task_thread_info(idle);
140 mb();
141
142 /*
143 * Initial boot sequence for secondary CPU:
144 * bmips_reset_nmi_vec @ a000_0000 ->
145 * bmips_smp_entry ->
146 * plat_wired_tlb_setup (cached function call; optional) ->
147 * start_secondary (cached jump)
148 *
149 * Warm restart sequence:
150 * play_dead WAIT loop ->
151 * bmips_smp_int_vec @ BMIPS_WARM_RESTART_VEC ->
152 * eret to play_dead ->
153 * bmips_secondary_reentry ->
154 * start_secondary
155 */
156
157 pr_info("SMP: Booting CPU%d...\n", cpu);
158
159 if (cpumask_test_cpu(cpu, &bmips_booted_mask))
160 bmips_send_ipi_single(cpu, 0);
161 else {
162#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
163 set_c0_brcm_cmt_ctrl(0x01);
164#elif defined(CONFIG_CPU_BMIPS5000)
165 if (cpu & 0x01)
166 write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));
167 else {
168 /*
169 * core N thread 0 was already booted; just
170 * pulse the NMI line
171 */
172 bmips_write_zscm_reg(0x210, 0xc0000000);
173 udelay(10);
174 bmips_write_zscm_reg(0x210, 0x00);
175 }
176#endif
177 cpumask_set_cpu(cpu, &bmips_booted_mask);
178 }
179}
180
181/*
182 * Early setup - runs on secondary CPU after cache probe
183 */
184static void bmips_init_secondary(void)
185{
186 /* move NMI vector to kseg0, in case XKS01 is enabled */
187
188#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
189 void __iomem *cbr = BMIPS_GET_CBR();
190 unsigned long old_vec;
191
192 old_vec = __raw_readl(cbr + BMIPS_RELO_VECTOR_CONTROL_1);
193 __raw_writel(old_vec & ~0x20000000, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
194
195 clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0);
196#elif defined(CONFIG_CPU_BMIPS5000)
197 write_c0_brcm_bootvec(read_c0_brcm_bootvec() &
198 (smp_processor_id() & 0x01 ? ~0x20000000 : ~0x2000));
199
200 write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0));
201#endif
202
203 /* make sure there won't be a timer interrupt for a little while */
204 write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
205
206 irq_enable_hazard();
207 set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ1 | IE_IRQ5 | ST0_IE);
208 irq_enable_hazard();
209}
210
211/*
212 * Late setup - runs on secondary CPU before entering the idle loop
213 */
214static void bmips_smp_finish(void)
215{
216 pr_info("SMP: CPU%d is running\n", smp_processor_id());
217}
218
219/*
220 * Runs on CPU0 after all CPUs have been booted
221 */
222static void bmips_cpus_done(void)
223{
224}
225
226#if defined(CONFIG_CPU_BMIPS5000)
227
228/*
229 * BMIPS5000 raceless IPIs
230 *
231 * Each CPU has two inbound SW IRQs which are independent of all other CPUs.
232 * IPI0 is used for SMP_RESCHEDULE_YOURSELF
233 * IPI1 is used for SMP_CALL_FUNCTION
234 */
235
236static void bmips_send_ipi_single(int cpu, unsigned int action)
237{
238 write_c0_brcm_action(ACTION_SET_IPI(cpu, action == SMP_CALL_FUNCTION));
239}
240
241static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id)
242{
243 int action = irq - IPI0_IRQ;
244
245 write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), action));
246
247 if (action == 0)
248 scheduler_ipi();
249 else
250 smp_call_function_interrupt();
251
252 return IRQ_HANDLED;
253}
254
255#else
256
257/*
258 * BMIPS43xx racey IPIs
259 *
260 * We use one inbound SW IRQ for each CPU.
261 *
262 * A spinlock must be held in order to keep CPUx from accidentally clearing
263 * an incoming IPI when it writes CP0 CAUSE to raise an IPI on CPUy. The
264 * same spinlock is used to protect the action masks.
265 */
266
267static DEFINE_SPINLOCK(ipi_lock);
268static DEFINE_PER_CPU(int, ipi_action_mask);
269
270static void bmips_send_ipi_single(int cpu, unsigned int action)
271{
272 unsigned long flags;
273
274 spin_lock_irqsave(&ipi_lock, flags);
275 set_c0_cause(cpu ? C_SW1 : C_SW0);
276 per_cpu(ipi_action_mask, cpu) |= action;
277 irq_enable_hazard();
278 spin_unlock_irqrestore(&ipi_lock, flags);
279}
280
281static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id)
282{
283 unsigned long flags;
284 int action, cpu = irq - IPI0_IRQ;
285
286 spin_lock_irqsave(&ipi_lock, flags);
287 action = __get_cpu_var(ipi_action_mask);
288 per_cpu(ipi_action_mask, cpu) = 0;
289 clear_c0_cause(cpu ? C_SW1 : C_SW0);
290 spin_unlock_irqrestore(&ipi_lock, flags);
291
292 if (action & SMP_RESCHEDULE_YOURSELF)
293 scheduler_ipi();
294 if (action & SMP_CALL_FUNCTION)
295 smp_call_function_interrupt();
296
297 return IRQ_HANDLED;
298}
299
300#endif /* BMIPS type */
301
302static void bmips_send_ipi_mask(const struct cpumask *mask,
303 unsigned int action)
304{
305 unsigned int i;
306
307 for_each_cpu(i, mask)
308 bmips_send_ipi_single(i, action);
309}
310
311#ifdef CONFIG_HOTPLUG_CPU
312
313static int bmips_cpu_disable(void)
314{
315 unsigned int cpu = smp_processor_id();
316
317 if (cpu == 0)
318 return -EBUSY;
319
320 pr_info("SMP: CPU%d is offline\n", cpu);
321
322 cpu_clear(cpu, cpu_online_map);
323 cpu_clear(cpu, cpu_callin_map);
324
325 local_flush_tlb_all();
326 local_flush_icache_range(0, ~0);
327
328 return 0;
329}
330
331static void bmips_cpu_die(unsigned int cpu)
332{
333}
334
335void __ref play_dead(void)
336{
337 idle_task_exit();
338
339 /* flush data cache */
340 _dma_cache_wback_inv(0, ~0);
341
342 /*
343 * Wakeup is on SW0 or SW1; disable everything else
344 * Use BEV !IV (BMIPS_WARM_RESTART_VEC) to avoid the regular Linux
345 * IRQ handlers; this clears ST0_IE and returns immediately.
346 */
347 clear_c0_cause(CAUSEF_IV | C_SW0 | C_SW1);
348 change_c0_status(IE_IRQ5 | IE_IRQ1 | IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV,
349 IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV);
350 irq_disable_hazard();
351
352 /*
353 * wait for SW interrupt from bmips_boot_secondary(), then jump
354 * back to start_secondary()
355 */
356 __asm__ __volatile__(
357 " wait\n"
358 " j bmips_secondary_reentry\n"
359 : : : "memory");
360}
361
362#endif /* CONFIG_HOTPLUG_CPU */
363
364struct plat_smp_ops bmips_smp_ops = {
365 .smp_setup = bmips_smp_setup,
366 .prepare_cpus = bmips_prepare_cpus,
367 .boot_secondary = bmips_boot_secondary,
368 .smp_finish = bmips_smp_finish,
369 .init_secondary = bmips_init_secondary,
370 .cpus_done = bmips_cpus_done,
371 .send_ipi_single = bmips_send_ipi_single,
372 .send_ipi_mask = bmips_send_ipi_mask,
373#ifdef CONFIG_HOTPLUG_CPU
374 .cpu_disable = bmips_cpu_disable,
375 .cpu_die = bmips_cpu_die,
376#endif
377};
378
379#endif /* CONFIG_SMP */
380
381/***********************************************************************
382 * BMIPS vector relocation
383 * This is primarily used for SMP boot, but it is applicable to some
384 * UP BMIPS systems as well.
385 ***********************************************************************/
386
387static void __cpuinit bmips_wr_vec(unsigned long dst, char *start, char *end)
388{
389 memcpy((void *)dst, start, end - start);
390 dma_cache_wback((unsigned long)start, end - start);
391 local_flush_icache_range(dst, dst + (end - start));
392 instruction_hazard();
393}
394
395static inline void __cpuinit bmips_nmi_handler_setup(void)
396{
397 bmips_wr_vec(BMIPS_NMI_RESET_VEC, &bmips_reset_nmi_vec,
398 &bmips_reset_nmi_vec_end);
399 bmips_wr_vec(BMIPS_WARM_RESTART_VEC, &bmips_smp_int_vec,
400 &bmips_smp_int_vec_end);
401}
402
403void __cpuinit bmips_ebase_setup(void)
404{
405 unsigned long new_ebase = ebase;
406 void __iomem __maybe_unused *cbr;
407
408 BUG_ON(ebase != CKSEG0);
409
410#if defined(CONFIG_CPU_BMIPS4350)
411 /*
412 * BMIPS4350 cannot relocate the normal vectors, but it
413 * can relocate the BEV=1 vectors. So CPU1 starts up at
414 * the relocated BEV=1, IV=0 general exception vector @
415 * 0xa000_0380.
416 *
417 * set_uncached_handler() is used here because:
418 * - CPU1 will run this from uncached space
419 * - None of the cacheflush functions are set up yet
420 */
421 set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0,
422 &bmips_smp_int_vec, 0x80);
423 __sync();
424 return;
425#elif defined(CONFIG_CPU_BMIPS4380)
426 /*
427 * 0x8000_0000: reset/NMI (initially in kseg1)
428 * 0x8000_0400: normal vectors
429 */
430 new_ebase = 0x80000400;
431 cbr = BMIPS_GET_CBR();
432 __raw_writel(0x80080800, cbr + BMIPS_RELO_VECTOR_CONTROL_0);
433 __raw_writel(0xa0080800, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
434#elif defined(CONFIG_CPU_BMIPS5000)
435 /*
436 * 0x8000_0000: reset/NMI (initially in kseg1)
437 * 0x8000_1000: normal vectors
438 */
439 new_ebase = 0x80001000;
440 write_c0_brcm_bootvec(0xa0088008);
441 write_c0_ebase(new_ebase);
442 if (max_cpus > 2)
443 bmips_write_zscm_reg(0xa0, 0xa008a008);
444#else
445 return;
446#endif
447 board_nmi_handler_setup = &bmips_nmi_handler_setup;
448 ebase = new_ebase;
449}
450
451asmlinkage void __weak plat_wired_tlb_setup(void)
452{
453 /*
454 * Called when starting/restarting a secondary CPU.
455 * Kernel stacks and other important data might only be accessible
456 * once the wired entries are present.
457 */
458}
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index f0895e70e283..0a42ff3ff6a1 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -559,7 +559,7 @@ void smtc_prepare_cpus(int cpus)
559 559
560 pipi = kmalloc(nipi *sizeof(struct smtc_ipi), GFP_KERNEL); 560 pipi = kmalloc(nipi *sizeof(struct smtc_ipi), GFP_KERNEL);
561 if (pipi == NULL) 561 if (pipi == NULL)
562 panic("kmalloc of IPI message buffers failed\n"); 562 panic("kmalloc of IPI message buffers failed");
563 else 563 else
564 printk("IPI buffer pool of %d buffers\n", nipi); 564 printk("IPI buffer pool of %d buffers\n", nipi);
565 for (i = 0; i < nipi; i++) { 565 for (i = 0; i < nipi; i++) {
@@ -813,7 +813,7 @@ void smtc_send_ipi(int cpu, int type, unsigned int action)
813 if (pipi == NULL) { 813 if (pipi == NULL) {
814 bust_spinlocks(1); 814 bust_spinlocks(1);
815 mips_mt_regdump(dvpe()); 815 mips_mt_regdump(dvpe());
816 panic("IPI Msg. Buffers Depleted\n"); 816 panic("IPI Msg. Buffers Depleted");
817 } 817 }
818 pipi->type = type; 818 pipi->type = type;
819 pipi->arg = (void *)action; 819 pipi->arg = (void *)action;
@@ -1130,7 +1130,7 @@ static void ipi_irq_dispatch(void)
1130 1130
1131static struct irqaction irq_ipi = { 1131static struct irqaction irq_ipi = {
1132 .handler = ipi_interrupt, 1132 .handler = ipi_interrupt,
1133 .flags = IRQF_DISABLED | IRQF_PERCPU, 1133 .flags = IRQF_PERCPU,
1134 .name = "SMTC_IPI" 1134 .name = "SMTC_IPI"
1135}; 1135};
1136 1136
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 5c8a49d55054..48240fd8c297 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -91,6 +91,7 @@ int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
91void (*board_nmi_handler_setup)(void); 91void (*board_nmi_handler_setup)(void);
92void (*board_ejtag_handler_setup)(void); 92void (*board_ejtag_handler_setup)(void);
93void (*board_bind_eic_interrupt)(int irq, int regset); 93void (*board_bind_eic_interrupt)(int irq, int regset);
94void (*board_ebase_setup)(void);
94 95
95 96
96static void show_raw_backtrace(unsigned long reg29) 97static void show_raw_backtrace(unsigned long reg29)
@@ -400,7 +401,7 @@ void __noreturn die(const char *str, struct pt_regs *regs)
400 panic("Fatal exception in interrupt"); 401 panic("Fatal exception in interrupt");
401 402
402 if (panic_on_oops) { 403 if (panic_on_oops) {
403 printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n"); 404 printk(KERN_EMERG "Fatal exception: panic in 5 seconds");
404 ssleep(5); 405 ssleep(5);
405 panic("Fatal exception"); 406 panic("Fatal exception");
406 } 407 }
@@ -1150,7 +1151,7 @@ asmlinkage void do_mt(struct pt_regs *regs)
1150asmlinkage void do_dsp(struct pt_regs *regs) 1151asmlinkage void do_dsp(struct pt_regs *regs)
1151{ 1152{
1152 if (cpu_has_dsp) 1153 if (cpu_has_dsp)
1153 panic("Unexpected DSP exception\n"); 1154 panic("Unexpected DSP exception");
1154 1155
1155 force_sig(SIGILL, current); 1156 force_sig(SIGILL, current);
1156} 1157}
@@ -1339,9 +1340,18 @@ void ejtag_exception_handler(struct pt_regs *regs)
1339 1340
1340/* 1341/*
1341 * NMI exception handler. 1342 * NMI exception handler.
1343 * No lock; only written during early bootup by CPU 0.
1342 */ 1344 */
1345static RAW_NOTIFIER_HEAD(nmi_chain);
1346
1347int register_nmi_notifier(struct notifier_block *nb)
1348{
1349 return raw_notifier_chain_register(&nmi_chain, nb);
1350}
1351
1343NORET_TYPE void ATTRIB_NORET nmi_exception_handler(struct pt_regs *regs) 1352NORET_TYPE void ATTRIB_NORET nmi_exception_handler(struct pt_regs *regs)
1344{ 1353{
1354 raw_notifier_call_chain(&nmi_chain, 0, regs);
1345 bust_spinlocks(1); 1355 bust_spinlocks(1);
1346 printk("NMI taken!!!!\n"); 1356 printk("NMI taken!!!!\n");
1347 die("NMI", regs); 1357 die("NMI", regs);
@@ -1682,6 +1692,8 @@ void __init trap_init(void)
1682 ebase += (read_c0_ebase() & 0x3ffff000); 1692 ebase += (read_c0_ebase() & 0x3ffff000);
1683 } 1693 }
1684 1694
1695 if (board_ebase_setup)
1696 board_ebase_setup();
1685 per_cpu_trap_init(); 1697 per_cpu_trap_init();
1686 1698
1687 /* 1699 /*
diff --git a/arch/mips/lantiq/clk.c b/arch/mips/lantiq/clk.c
index 77ed70fc2fe5..412814fdd3ee 100644
--- a/arch/mips/lantiq/clk.c
+++ b/arch/mips/lantiq/clk.c
@@ -134,11 +134,11 @@ void __init plat_time_init(void)
134 struct clk *clk; 134 struct clk *clk;
135 135
136 if (insert_resource(&iomem_resource, &ltq_cgu_resource) < 0) 136 if (insert_resource(&iomem_resource, &ltq_cgu_resource) < 0)
137 panic("Failed to insert cgu memory\n"); 137 panic("Failed to insert cgu memory");
138 138
139 if (request_mem_region(ltq_cgu_resource.start, 139 if (request_mem_region(ltq_cgu_resource.start,
140 resource_size(&ltq_cgu_resource), "cgu") < 0) 140 resource_size(&ltq_cgu_resource), "cgu") < 0)
141 panic("Failed to request cgu memory\n"); 141 panic("Failed to request cgu memory");
142 142
143 ltq_cgu_membase = ioremap_nocache(ltq_cgu_resource.start, 143 ltq_cgu_membase = ioremap_nocache(ltq_cgu_resource.start,
144 resource_size(&ltq_cgu_resource)); 144 resource_size(&ltq_cgu_resource));
diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
index f9737bb3c5ab..d673731c538a 100644
--- a/arch/mips/lantiq/irq.c
+++ b/arch/mips/lantiq/irq.c
@@ -240,7 +240,6 @@ out:
240 240
241static struct irqaction cascade = { 241static struct irqaction cascade = {
242 .handler = no_action, 242 .handler = no_action,
243 .flags = IRQF_DISABLED,
244 .name = "cascade", 243 .name = "cascade",
245}; 244};
246 245
@@ -249,28 +248,28 @@ void __init arch_init_irq(void)
249 int i; 248 int i;
250 249
251 if (insert_resource(&iomem_resource, &ltq_icu_resource) < 0) 250 if (insert_resource(&iomem_resource, &ltq_icu_resource) < 0)
252 panic("Failed to insert icu memory\n"); 251 panic("Failed to insert icu memory");
253 252
254 if (request_mem_region(ltq_icu_resource.start, 253 if (request_mem_region(ltq_icu_resource.start,
255 resource_size(&ltq_icu_resource), "icu") < 0) 254 resource_size(&ltq_icu_resource), "icu") < 0)
256 panic("Failed to request icu memory\n"); 255 panic("Failed to request icu memory");
257 256
258 ltq_icu_membase = ioremap_nocache(ltq_icu_resource.start, 257 ltq_icu_membase = ioremap_nocache(ltq_icu_resource.start,
259 resource_size(&ltq_icu_resource)); 258 resource_size(&ltq_icu_resource));
260 if (!ltq_icu_membase) 259 if (!ltq_icu_membase)
261 panic("Failed to remap icu memory\n"); 260 panic("Failed to remap icu memory");
262 261
263 if (insert_resource(&iomem_resource, &ltq_eiu_resource) < 0) 262 if (insert_resource(&iomem_resource, &ltq_eiu_resource) < 0)
264 panic("Failed to insert eiu memory\n"); 263 panic("Failed to insert eiu memory");
265 264
266 if (request_mem_region(ltq_eiu_resource.start, 265 if (request_mem_region(ltq_eiu_resource.start,
267 resource_size(&ltq_eiu_resource), "eiu") < 0) 266 resource_size(&ltq_eiu_resource), "eiu") < 0)
268 panic("Failed to request eiu memory\n"); 267 panic("Failed to request eiu memory");
269 268
270 ltq_eiu_membase = ioremap_nocache(ltq_eiu_resource.start, 269 ltq_eiu_membase = ioremap_nocache(ltq_eiu_resource.start,
271 resource_size(&ltq_eiu_resource)); 270 resource_size(&ltq_eiu_resource));
272 if (!ltq_eiu_membase) 271 if (!ltq_eiu_membase)
273 panic("Failed to remap eiu memory\n"); 272 panic("Failed to remap eiu memory");
274 273
275 /* make sure all irqs are turned off by default */ 274 /* make sure all irqs are turned off by default */
276 for (i = 0; i < 5; i++) 275 for (i = 0; i < 5; i++)
diff --git a/arch/mips/lantiq/xway/dma.c b/arch/mips/lantiq/xway/dma.c
index cbb6ae5747b9..b210e936c7c3 100644
--- a/arch/mips/lantiq/xway/dma.c
+++ b/arch/mips/lantiq/xway/dma.c
@@ -222,17 +222,17 @@ ltq_dma_init(void)
222 222
223 /* insert and request the memory region */ 223 /* insert and request the memory region */
224 if (insert_resource(&iomem_resource, &ltq_dma_resource) < 0) 224 if (insert_resource(&iomem_resource, &ltq_dma_resource) < 0)
225 panic("Failed to insert dma memory\n"); 225 panic("Failed to insert dma memory");
226 226
227 if (request_mem_region(ltq_dma_resource.start, 227 if (request_mem_region(ltq_dma_resource.start,
228 resource_size(&ltq_dma_resource), "dma") < 0) 228 resource_size(&ltq_dma_resource), "dma") < 0)
229 panic("Failed to request dma memory\n"); 229 panic("Failed to request dma memory");
230 230
231 /* remap dma register range */ 231 /* remap dma register range */
232 ltq_dma_membase = ioremap_nocache(ltq_dma_resource.start, 232 ltq_dma_membase = ioremap_nocache(ltq_dma_resource.start,
233 resource_size(&ltq_dma_resource)); 233 resource_size(&ltq_dma_resource));
234 if (!ltq_dma_membase) 234 if (!ltq_dma_membase)
235 panic("Failed to remap dma memory\n"); 235 panic("Failed to remap dma memory");
236 236
237 /* power up and reset the dma engine */ 237 /* power up and reset the dma engine */
238 ltq_pmu_enable(PMU_DMA); 238 ltq_pmu_enable(PMU_DMA);
diff --git a/arch/mips/lantiq/xway/ebu.c b/arch/mips/lantiq/xway/ebu.c
index 033b3184c7a7..862e3e830680 100644
--- a/arch/mips/lantiq/xway/ebu.c
+++ b/arch/mips/lantiq/xway/ebu.c
@@ -32,17 +32,17 @@ static int __init lantiq_ebu_init(void)
32{ 32{
33 /* insert and request the memory region */ 33 /* insert and request the memory region */
34 if (insert_resource(&iomem_resource, &ltq_ebu_resource) < 0) 34 if (insert_resource(&iomem_resource, &ltq_ebu_resource) < 0)
35 panic("Failed to insert ebu memory\n"); 35 panic("Failed to insert ebu memory");
36 36
37 if (request_mem_region(ltq_ebu_resource.start, 37 if (request_mem_region(ltq_ebu_resource.start,
38 resource_size(&ltq_ebu_resource), "ebu") < 0) 38 resource_size(&ltq_ebu_resource), "ebu") < 0)
39 panic("Failed to request ebu memory\n"); 39 panic("Failed to request ebu memory");
40 40
41 /* remap ebu register range */ 41 /* remap ebu register range */
42 ltq_ebu_membase = ioremap_nocache(ltq_ebu_resource.start, 42 ltq_ebu_membase = ioremap_nocache(ltq_ebu_resource.start,
43 resource_size(&ltq_ebu_resource)); 43 resource_size(&ltq_ebu_resource));
44 if (!ltq_ebu_membase) 44 if (!ltq_ebu_membase)
45 panic("Failed to remap ebu memory\n"); 45 panic("Failed to remap ebu memory");
46 46
47 /* make sure to unprotect the memory region where flash is located */ 47 /* make sure to unprotect the memory region where flash is located */
48 ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0); 48 ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
diff --git a/arch/mips/lantiq/xway/pmu.c b/arch/mips/lantiq/xway/pmu.c
index 39f0d2641cbf..fe85361e032e 100644
--- a/arch/mips/lantiq/xway/pmu.c
+++ b/arch/mips/lantiq/xway/pmu.c
@@ -40,7 +40,7 @@ void ltq_pmu_enable(unsigned int module)
40 do {} while (--err && (ltq_pmu_r32(LTQ_PMU_PWDSR) & module)); 40 do {} while (--err && (ltq_pmu_r32(LTQ_PMU_PWDSR) & module));
41 41
42 if (!err) 42 if (!err)
43 panic("activating PMU module failed!\n"); 43 panic("activating PMU module failed!");
44} 44}
45EXPORT_SYMBOL(ltq_pmu_enable); 45EXPORT_SYMBOL(ltq_pmu_enable);
46 46
@@ -53,16 +53,16 @@ EXPORT_SYMBOL(ltq_pmu_disable);
53int __init ltq_pmu_init(void) 53int __init ltq_pmu_init(void)
54{ 54{
55 if (insert_resource(&iomem_resource, &ltq_pmu_resource) < 0) 55 if (insert_resource(&iomem_resource, &ltq_pmu_resource) < 0)
56 panic("Failed to insert pmu memory\n"); 56 panic("Failed to insert pmu memory");
57 57
58 if (request_mem_region(ltq_pmu_resource.start, 58 if (request_mem_region(ltq_pmu_resource.start,
59 resource_size(&ltq_pmu_resource), "pmu") < 0) 59 resource_size(&ltq_pmu_resource), "pmu") < 0)
60 panic("Failed to request pmu memory\n"); 60 panic("Failed to request pmu memory");
61 61
62 ltq_pmu_membase = ioremap_nocache(ltq_pmu_resource.start, 62 ltq_pmu_membase = ioremap_nocache(ltq_pmu_resource.start,
63 resource_size(&ltq_pmu_resource)); 63 resource_size(&ltq_pmu_resource));
64 if (!ltq_pmu_membase) 64 if (!ltq_pmu_membase)
65 panic("Failed to remap pmu memory\n"); 65 panic("Failed to remap pmu memory");
66 return 0; 66 return 0;
67} 67}
68 68
diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
index 3d41f0bb5bf7..8b66bd87f0c1 100644
--- a/arch/mips/lantiq/xway/reset.c
+++ b/arch/mips/lantiq/xway/reset.c
@@ -69,17 +69,17 @@ static int __init mips_reboot_setup(void)
69{ 69{
70 /* insert and request the memory region */ 70 /* insert and request the memory region */
71 if (insert_resource(&iomem_resource, &ltq_rcu_resource) < 0) 71 if (insert_resource(&iomem_resource, &ltq_rcu_resource) < 0)
72 panic("Failed to insert rcu memory\n"); 72 panic("Failed to insert rcu memory");
73 73
74 if (request_mem_region(ltq_rcu_resource.start, 74 if (request_mem_region(ltq_rcu_resource.start,
75 resource_size(&ltq_rcu_resource), "rcu") < 0) 75 resource_size(&ltq_rcu_resource), "rcu") < 0)
76 panic("Failed to request rcu memory\n"); 76 panic("Failed to request rcu memory");
77 77
78 /* remap rcu register range */ 78 /* remap rcu register range */
79 ltq_rcu_membase = ioremap_nocache(ltq_rcu_resource.start, 79 ltq_rcu_membase = ioremap_nocache(ltq_rcu_resource.start,
80 resource_size(&ltq_rcu_resource)); 80 resource_size(&ltq_rcu_resource));
81 if (!ltq_rcu_membase) 81 if (!ltq_rcu_membase)
82 panic("Failed to remap rcu memory\n"); 82 panic("Failed to remap rcu memory");
83 83
84 _machine_restart = ltq_machine_restart; 84 _machine_restart = ltq_machine_restart;
85 _machine_halt = ltq_machine_halt; 85 _machine_halt = ltq_machine_halt;
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index b2cad4fd5fc4..2a7c74fc15fc 100644
--- a/arch/mips/lib/Makefile
+++ b/arch/mips/lib/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_CPU_TX49XX) += dump_tlb.o
29obj-$(CONFIG_CPU_VR41XX) += dump_tlb.o 29obj-$(CONFIG_CPU_VR41XX) += dump_tlb.o
30obj-$(CONFIG_CPU_CAVIUM_OCTEON) += dump_tlb.o 30obj-$(CONFIG_CPU_CAVIUM_OCTEON) += dump_tlb.o
31obj-$(CONFIG_CPU_XLR) += dump_tlb.o 31obj-$(CONFIG_CPU_XLR) += dump_tlb.o
32obj-$(CONFIG_CPU_XLP) += dump_tlb.o
32 33
33# libgcc-style stuff needed in the kernel 34# libgcc-style stuff needed in the kernel
34obj-y += ashldi3.o ashrdi3.o cmpdi2.o lshrdi3.o ucmpdi2.o 35obj-y += ashldi3.o ashrdi3.o cmpdi2.o lshrdi3.o ucmpdi2.o
diff --git a/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c b/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c
index 0cb1b9760e34..5d1f48fa1a52 100644
--- a/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c
+++ b/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c
@@ -111,7 +111,7 @@ static irqreturn_t timer_interrupt(int irq, void *dev_id)
111 111
112static struct irqaction irq5 = { 112static struct irqaction irq5 = {
113 .handler = timer_interrupt, 113 .handler = timer_interrupt,
114 .flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_TIMER, 114 .flags = IRQF_NOBALANCING | IRQF_TIMER,
115 .name = "timer" 115 .name = "timer"
116}; 116};
117 117
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index dbf2f93a5091..a03bf00a1a9c 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -245,7 +245,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
245 */ 245 */
246 emulpc = xcp->cp0_epc + 4; /* Snapshot emulation target */ 246 emulpc = xcp->cp0_epc + 4; /* Snapshot emulation target */
247 247
248 if (__compute_return_epc(xcp)) { 248 if (__compute_return_epc(xcp) < 0) {
249#ifdef CP1DBG 249#ifdef CP1DBG
250 printk("failed to emulate branch at %p\n", 250 printk("failed to emulate branch at %p\n",
251 (void *) (xcp->cp0_epc)); 251 (void *) (xcp->cp0_epc));
diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile
index 4d8c1623eee2..4aa20280613e 100644
--- a/arch/mips/mm/Makefile
+++ b/arch/mips/mm/Makefile
@@ -3,8 +3,8 @@
3# 3#
4 4
5obj-y += cache.o dma-default.o extable.o fault.o \ 5obj-y += cache.o dma-default.o extable.o fault.o \
6 init.o mmap.o tlbex.o tlbex-fault.o uasm.o \ 6 gup.o init.o mmap.o page.o tlbex.o \
7 page.o 7 tlbex-fault.o uasm.o
8 8
9obj-$(CONFIG_32BIT) += ioremap.o pgtable-32.o 9obj-$(CONFIG_32BIT) += ioremap.o pgtable-32.o
10obj-$(CONFIG_64BIT) += pgtable-64.o 10obj-$(CONFIG_64BIT) += pgtable-64.o
@@ -31,6 +31,7 @@ obj-$(CONFIG_CPU_TX49XX) += c-r4k.o cex-gen.o tlb-r4k.o
31obj-$(CONFIG_CPU_VR41XX) += c-r4k.o cex-gen.o tlb-r4k.o 31obj-$(CONFIG_CPU_VR41XX) += c-r4k.o cex-gen.o tlb-r4k.o
32obj-$(CONFIG_CPU_CAVIUM_OCTEON) += c-octeon.o cex-oct.o tlb-r4k.o 32obj-$(CONFIG_CPU_CAVIUM_OCTEON) += c-octeon.o cex-oct.o tlb-r4k.o
33obj-$(CONFIG_CPU_XLR) += c-r4k.o tlb-r4k.o cex-gen.o 33obj-$(CONFIG_CPU_XLR) += c-r4k.o tlb-r4k.o cex-gen.o
34obj-$(CONFIG_CPU_XLP) += c-r4k.o tlb-r4k.o cex-gen.o
34 35
35obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o 36obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o
36obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o 37obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o
diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c
index daa81f7284ac..cf7895db0739 100644
--- a/arch/mips/mm/c-octeon.c
+++ b/arch/mips/mm/c-octeon.c
@@ -223,7 +223,7 @@ static void __cpuinit probe_octeon(void)
223 break; 223 break;
224 224
225 default: 225 default:
226 panic("Unsupported Cavium Networks CPU type\n"); 226 panic("Unsupported Cavium Networks CPU type");
227 break; 227 break;
228 } 228 }
229 229
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index a79fe9aa7721..4f9eb0b23036 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1235,6 +1235,9 @@ static void __cpuinit setup_scache(void)
1235 loongson2_sc_init(); 1235 loongson2_sc_init();
1236 return; 1236 return;
1237#endif 1237#endif
1238 case CPU_XLP:
1239 /* don't need to worry about L2, fully coherent */
1240 return;
1238 1241
1239 default: 1242 default:
1240 if (c->isa_level == MIPS_CPU_ISA_M32R1 || 1243 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
diff --git a/arch/mips/mm/gup.c b/arch/mips/mm/gup.c
new file mode 100644
index 000000000000..33aadbcf170b
--- /dev/null
+++ b/arch/mips/mm/gup.c
@@ -0,0 +1,315 @@
1/*
2 * Lockless get_user_pages_fast for MIPS
3 *
4 * Copyright (C) 2008 Nick Piggin
5 * Copyright (C) 2008 Novell Inc.
6 * Copyright (C) 2011 Ralf Baechle
7 */
8#include <linux/sched.h>
9#include <linux/mm.h>
10#include <linux/vmstat.h>
11#include <linux/highmem.h>
12#include <linux/swap.h>
13#include <linux/hugetlb.h>
14
15#include <asm/pgtable.h>
16
17static inline pte_t gup_get_pte(pte_t *ptep)
18{
19#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
20 pte_t pte;
21
22retry:
23 pte.pte_low = ptep->pte_low;
24 smp_rmb();
25 pte.pte_high = ptep->pte_high;
26 smp_rmb();
27 if (unlikely(pte.pte_low != ptep->pte_low))
28 goto retry;
29
30 return pte;
31#else
32 return ACCESS_ONCE(*ptep);
33#endif
34}
35
36static int gup_pte_range(pmd_t pmd, unsigned long addr, unsigned long end,
37 int write, struct page **pages, int *nr)
38{
39 pte_t *ptep = pte_offset_map(&pmd, addr);
40 do {
41 pte_t pte = gup_get_pte(ptep);
42 struct page *page;
43
44 if (!pte_present(pte) ||
45 pte_special(pte) || (write && !pte_write(pte))) {
46 pte_unmap(ptep);
47 return 0;
48 }
49 VM_BUG_ON(!pfn_valid(pte_pfn(pte)));
50 page = pte_page(pte);
51 get_page(page);
52 SetPageReferenced(page);
53 pages[*nr] = page;
54 (*nr)++;
55
56 } while (ptep++, addr += PAGE_SIZE, addr != end);
57
58 pte_unmap(ptep - 1);
59 return 1;
60}
61
62static inline void get_head_page_multiple(struct page *page, int nr)
63{
64 VM_BUG_ON(page != compound_head(page));
65 VM_BUG_ON(page_count(page) == 0);
66 atomic_add(nr, &page->_count);
67 SetPageReferenced(page);
68}
69
70static int gup_huge_pmd(pmd_t pmd, unsigned long addr, unsigned long end,
71 int write, struct page **pages, int *nr)
72{
73 pte_t pte = *(pte_t *)&pmd;
74 struct page *head, *page;
75 int refs;
76
77 if (write && !pte_write(pte))
78 return 0;
79 /* hugepages are never "special" */
80 VM_BUG_ON(pte_special(pte));
81 VM_BUG_ON(!pfn_valid(pte_pfn(pte)));
82
83 refs = 0;
84 head = pte_page(pte);
85 page = head + ((addr & ~PMD_MASK) >> PAGE_SHIFT);
86 do {
87 VM_BUG_ON(compound_head(page) != head);
88 pages[*nr] = page;
89 if (PageTail(page))
90 get_huge_page_tail(page);
91 (*nr)++;
92 page++;
93 refs++;
94 } while (addr += PAGE_SIZE, addr != end);
95
96 get_head_page_multiple(head, refs);
97 return 1;
98}
99
100static int gup_pmd_range(pud_t pud, unsigned long addr, unsigned long end,
101 int write, struct page **pages, int *nr)
102{
103 unsigned long next;
104 pmd_t *pmdp;
105
106 pmdp = pmd_offset(&pud, addr);
107 do {
108 pmd_t pmd = *pmdp;
109
110 next = pmd_addr_end(addr, end);
111 /*
112 * The pmd_trans_splitting() check below explains why
113 * pmdp_splitting_flush has to flush the tlb, to stop
114 * this gup-fast code from running while we set the
115 * splitting bit in the pmd. Returning zero will take
116 * the slow path that will call wait_split_huge_page()
117 * if the pmd is still in splitting state. gup-fast
118 * can't because it has irq disabled and
119 * wait_split_huge_page() would never return as the
120 * tlb flush IPI wouldn't run.
121 */
122 if (pmd_none(pmd) || pmd_trans_splitting(pmd))
123 return 0;
124 if (unlikely(pmd_huge(pmd))) {
125 if (!gup_huge_pmd(pmd, addr, next, write, pages,nr))
126 return 0;
127 } else {
128 if (!gup_pte_range(pmd, addr, next, write, pages,nr))
129 return 0;
130 }
131 } while (pmdp++, addr = next, addr != end);
132
133 return 1;
134}
135
136static int gup_huge_pud(pud_t pud, unsigned long addr, unsigned long end,
137 int write, struct page **pages, int *nr)
138{
139 pte_t pte = *(pte_t *)&pud;
140 struct page *head, *page;
141 int refs;
142
143 if (write && !pte_write(pte))
144 return 0;
145 /* hugepages are never "special" */
146 VM_BUG_ON(pte_special(pte));
147 VM_BUG_ON(!pfn_valid(pte_pfn(pte)));
148
149 refs = 0;
150 head = pte_page(pte);
151 page = head + ((addr & ~PUD_MASK) >> PAGE_SHIFT);
152 do {
153 VM_BUG_ON(compound_head(page) != head);
154 pages[*nr] = page;
155 (*nr)++;
156 page++;
157 refs++;
158 } while (addr += PAGE_SIZE, addr != end);
159
160 get_head_page_multiple(head, refs);
161 return 1;
162}
163
164static int gup_pud_range(pgd_t pgd, unsigned long addr, unsigned long end,
165 int write, struct page **pages, int *nr)
166{
167 unsigned long next;
168 pud_t *pudp;
169
170 pudp = pud_offset(&pgd, addr);
171 do {
172 pud_t pud = *pudp;
173
174 next = pud_addr_end(addr, end);
175 if (pud_none(pud))
176 return 0;
177 if (unlikely(pud_huge(pud))) {
178 if (!gup_huge_pud(pud, addr, next, write, pages,nr))
179 return 0;
180 } else {
181 if (!gup_pmd_range(pud, addr, next, write, pages,nr))
182 return 0;
183 }
184 } while (pudp++, addr = next, addr != end);
185
186 return 1;
187}
188
189/*
190 * Like get_user_pages_fast() except its IRQ-safe in that it won't fall
191 * back to the regular GUP.
192 */
193int __get_user_pages_fast(unsigned long start, int nr_pages, int write,
194 struct page **pages)
195{
196 struct mm_struct *mm = current->mm;
197 unsigned long addr, len, end;
198 unsigned long next;
199 unsigned long flags;
200 pgd_t *pgdp;
201 int nr = 0;
202
203 start &= PAGE_MASK;
204 addr = start;
205 len = (unsigned long) nr_pages << PAGE_SHIFT;
206 end = start + len;
207 if (unlikely(!access_ok(write ? VERIFY_WRITE : VERIFY_READ,
208 (void __user *)start, len)))
209 return 0;
210
211 /*
212 * XXX: batch / limit 'nr', to avoid large irq off latency
213 * needs some instrumenting to determine the common sizes used by
214 * important workloads (eg. DB2), and whether limiting the batch
215 * size will decrease performance.
216 *
217 * It seems like we're in the clear for the moment. Direct-IO is
218 * the main guy that batches up lots of get_user_pages, and even
219 * they are limited to 64-at-a-time which is not so many.
220 */
221 /*
222 * This doesn't prevent pagetable teardown, but does prevent
223 * the pagetables and pages from being freed.
224 *
225 * So long as we atomically load page table pointers versus teardown,
226 * we can follow the address down to the page and take a ref on it.
227 */
228 local_irq_save(flags);
229 pgdp = pgd_offset(mm, addr);
230 do {
231 pgd_t pgd = *pgdp;
232
233 next = pgd_addr_end(addr, end);
234 if (pgd_none(pgd))
235 break;
236 if (!gup_pud_range(pgd, addr, next, write, pages, &nr))
237 break;
238 } while (pgdp++, addr = next, addr != end);
239 local_irq_restore(flags);
240
241 return nr;
242}
243
244/**
245 * get_user_pages_fast() - pin user pages in memory
246 * @start: starting user address
247 * @nr_pages: number of pages from start to pin
248 * @write: whether pages will be written to
249 * @pages: array that receives pointers to the pages pinned.
250 * Should be at least nr_pages long.
251 *
252 * Attempt to pin user pages in memory without taking mm->mmap_sem.
253 * If not successful, it will fall back to taking the lock and
254 * calling get_user_pages().
255 *
256 * Returns number of pages pinned. This may be fewer than the number
257 * requested. If nr_pages is 0 or negative, returns 0. If no pages
258 * were pinned, returns -errno.
259 */
260int get_user_pages_fast(unsigned long start, int nr_pages, int write,
261 struct page **pages)
262{
263 struct mm_struct *mm = current->mm;
264 unsigned long addr, len, end;
265 unsigned long next;
266 pgd_t *pgdp;
267 int ret, nr = 0;
268
269 start &= PAGE_MASK;
270 addr = start;
271 len = (unsigned long) nr_pages << PAGE_SHIFT;
272
273 end = start + len;
274 if (end < start)
275 goto slow_irqon;
276
277 /* XXX: batch / limit 'nr' */
278 local_irq_disable();
279 pgdp = pgd_offset(mm, addr);
280 do {
281 pgd_t pgd = *pgdp;
282
283 next = pgd_addr_end(addr, end);
284 if (pgd_none(pgd))
285 goto slow;
286 if (!gup_pud_range(pgd, addr, next, write, pages, &nr))
287 goto slow;
288 } while (pgdp++, addr = next, addr != end);
289 local_irq_enable();
290
291 VM_BUG_ON(nr != (end - start) >> PAGE_SHIFT);
292 return nr;
293slow:
294 local_irq_enable();
295
296slow_irqon:
297 /* Try to get the remaining pages with get_user_pages */
298 start += nr << PAGE_SHIFT;
299 pages += nr;
300
301 down_read(&mm->mmap_sem);
302 ret = get_user_pages(current, mm, start,
303 (end - start) >> PAGE_SHIFT,
304 write, 0, pages, NULL);
305 up_read(&mm->mmap_sem);
306
307 /* Have to be a bit careful with return values */
308 if (nr > 0) {
309 if (ret < 0)
310 ret = nr;
311 else
312 ret += nr;
313 }
314 return ret;
315}
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index b7ebc4fa89bc..3b3ffd439cd7 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -304,9 +304,14 @@ int page_is_ram(unsigned long pagenr)
304 for (i = 0; i < boot_mem_map.nr_map; i++) { 304 for (i = 0; i < boot_mem_map.nr_map; i++) {
305 unsigned long addr, end; 305 unsigned long addr, end;
306 306
307 if (boot_mem_map.map[i].type != BOOT_MEM_RAM) 307 switch (boot_mem_map.map[i].type) {
308 case BOOT_MEM_RAM:
309 case BOOT_MEM_INIT_RAM:
310 break;
311 default:
308 /* not usable memory */ 312 /* not usable memory */
309 continue; 313 continue;
314 }
310 315
311 addr = PFN_UP(boot_mem_map.map[i].addr); 316 addr = PFN_UP(boot_mem_map.map[i].addr);
312 end = PFN_DOWN(boot_mem_map.map[i].addr + 317 end = PFN_DOWN(boot_mem_map.map[i].addr +
@@ -379,7 +384,7 @@ void __init mem_init(void)
379 384
380 reservedpages = ram = 0; 385 reservedpages = ram = 0;
381 for (tmp = 0; tmp < max_low_pfn; tmp++) 386 for (tmp = 0; tmp < max_low_pfn; tmp++)
382 if (page_is_ram(tmp)) { 387 if (page_is_ram(tmp) && pfn_valid(tmp)) {
383 ram++; 388 ram++;
384 if (PageReserved(pfn_to_page(tmp))) 389 if (PageReserved(pfn_to_page(tmp)))
385 reservedpages++; 390 reservedpages++;
diff --git a/arch/mips/mm/tlb-r3k.c b/arch/mips/mm/tlb-r3k.c
index 87bb85d8d537..ed1fa460f84e 100644
--- a/arch/mips/mm/tlb-r3k.c
+++ b/arch/mips/mm/tlb-r3k.c
@@ -20,6 +20,7 @@
20#include <asm/pgtable.h> 20#include <asm/pgtable.h>
21#include <asm/mmu_context.h> 21#include <asm/mmu_context.h>
22#include <asm/system.h> 22#include <asm/system.h>
23#include <asm/tlbmisc.h>
23#include <asm/isadep.h> 24#include <asm/isadep.h>
24#include <asm/io.h> 25#include <asm/io.h>
25#include <asm/bootinfo.h> 26#include <asm/bootinfo.h>
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index 0d394e0e8837..2dc625346c40 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -19,6 +19,7 @@
19#include <asm/mmu_context.h> 19#include <asm/mmu_context.h>
20#include <asm/pgtable.h> 20#include <asm/pgtable.h>
21#include <asm/system.h> 21#include <asm/system.h>
22#include <asm/tlbmisc.h>
22 23
23extern void build_tlb_refill_handler(void); 24extern void build_tlb_refill_handler(void);
24 25
@@ -120,22 +121,30 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
120 121
121 if (cpu_context(cpu, mm) != 0) { 122 if (cpu_context(cpu, mm) != 0) {
122 unsigned long size, flags; 123 unsigned long size, flags;
124 int huge = is_vm_hugetlb_page(vma);
123 125
124 ENTER_CRITICAL(flags); 126 ENTER_CRITICAL(flags);
125 size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; 127 if (huge) {
126 size = (size + 1) >> 1; 128 start = round_down(start, HPAGE_SIZE);
129 end = round_up(end, HPAGE_SIZE);
130 size = (end - start) >> HPAGE_SHIFT;
131 } else {
132 start = round_down(start, PAGE_SIZE << 1);
133 end = round_up(end, PAGE_SIZE << 1);
134 size = (end - start) >> (PAGE_SHIFT + 1);
135 }
127 if (size <= current_cpu_data.tlbsize/2) { 136 if (size <= current_cpu_data.tlbsize/2) {
128 int oldpid = read_c0_entryhi(); 137 int oldpid = read_c0_entryhi();
129 int newpid = cpu_asid(cpu, mm); 138 int newpid = cpu_asid(cpu, mm);
130 139
131 start &= (PAGE_MASK << 1);
132 end += ((PAGE_SIZE << 1) - 1);
133 end &= (PAGE_MASK << 1);
134 while (start < end) { 140 while (start < end) {
135 int idx; 141 int idx;
136 142
137 write_c0_entryhi(start | newpid); 143 write_c0_entryhi(start | newpid);
138 start += (PAGE_SIZE << 1); 144 if (huge)
145 start += HPAGE_SIZE;
146 else
147 start += (PAGE_SIZE << 1);
139 mtc0_tlbw_hazard(); 148 mtc0_tlbw_hazard();
140 tlb_probe(); 149 tlb_probe();
141 tlb_probe_hazard(); 150 tlb_probe_hazard();
@@ -368,51 +377,6 @@ void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
368 EXIT_CRITICAL(flags); 377 EXIT_CRITICAL(flags);
369} 378}
370 379
371/*
372 * Used for loading TLB entries before trap_init() has started, when we
373 * don't actually want to add a wired entry which remains throughout the
374 * lifetime of the system
375 */
376
377static int temp_tlb_entry __cpuinitdata;
378
379__init int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
380 unsigned long entryhi, unsigned long pagemask)
381{
382 int ret = 0;
383 unsigned long flags;
384 unsigned long wired;
385 unsigned long old_pagemask;
386 unsigned long old_ctx;
387
388 ENTER_CRITICAL(flags);
389 /* Save old context and create impossible VPN2 value */
390 old_ctx = read_c0_entryhi();
391 old_pagemask = read_c0_pagemask();
392 wired = read_c0_wired();
393 if (--temp_tlb_entry < wired) {
394 printk(KERN_WARNING
395 "No TLB space left for add_temporary_entry\n");
396 ret = -ENOSPC;
397 goto out;
398 }
399
400 write_c0_index(temp_tlb_entry);
401 write_c0_pagemask(pagemask);
402 write_c0_entryhi(entryhi);
403 write_c0_entrylo0(entrylo0);
404 write_c0_entrylo1(entrylo1);
405 mtc0_tlbw_hazard();
406 tlb_write_indexed();
407 tlbw_use_hazard();
408
409 write_c0_entryhi(old_ctx);
410 write_c0_pagemask(old_pagemask);
411out:
412 EXIT_CRITICAL(flags);
413 return ret;
414}
415
416static int __cpuinitdata ntlb; 380static int __cpuinitdata ntlb;
417static int __init set_ntlb(char *str) 381static int __init set_ntlb(char *str)
418{ 382{
@@ -450,8 +414,6 @@ void __cpuinit tlb_init(void)
450 write_c0_pagegrain(pg); 414 write_c0_pagegrain(pg);
451 } 415 }
452 416
453 temp_tlb_entry = current_cpu_data.tlbsize - 1;
454
455 /* From this point on the ARC firmware is dead. */ 417 /* From this point on the ARC firmware is dead. */
456 local_flush_tlb_all(); 418 local_flush_tlb_all();
457 419
diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c
index d53ff91b277c..a588b5cef8d2 100644
--- a/arch/mips/mti-malta/malta-int.c
+++ b/arch/mips/mti-malta/malta-int.c
@@ -322,13 +322,13 @@ static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
322 322
323static struct irqaction irq_resched = { 323static struct irqaction irq_resched = {
324 .handler = ipi_resched_interrupt, 324 .handler = ipi_resched_interrupt,
325 .flags = IRQF_DISABLED|IRQF_PERCPU, 325 .flags = IRQF_PERCPU,
326 .name = "IPI_resched" 326 .name = "IPI_resched"
327}; 327};
328 328
329static struct irqaction irq_call = { 329static struct irqaction irq_call = {
330 .handler = ipi_call_interrupt, 330 .handler = ipi_call_interrupt,
331 .flags = IRQF_DISABLED|IRQF_PERCPU, 331 .flags = IRQF_PERCPU,
332 .name = "IPI_call" 332 .name = "IPI_call"
333}; 333};
334#endif /* CONFIG_MIPS_MT_SMP */ 334#endif /* CONFIG_MIPS_MT_SMP */
diff --git a/arch/mips/netlogic/Kconfig b/arch/mips/netlogic/Kconfig
index a5ca743613f2..75bec44b5856 100644
--- a/arch/mips/netlogic/Kconfig
+++ b/arch/mips/netlogic/Kconfig
@@ -1,5 +1,2 @@
1config NLM_COMMON 1config NLM_COMMON
2 bool 2 bool
3
4config NLM_XLR
5 bool
diff --git a/arch/mips/netlogic/Makefile b/arch/mips/netlogic/Makefile
new file mode 100644
index 000000000000..36d169b2ca6d
--- /dev/null
+++ b/arch/mips/netlogic/Makefile
@@ -0,0 +1,3 @@
1obj-$(CONFIG_NLM_COMMON) += common/
2obj-$(CONFIG_CPU_XLR) += xlr/
3obj-$(CONFIG_CPU_XLP) += xlp/
diff --git a/arch/mips/netlogic/Platform b/arch/mips/netlogic/Platform
index b648b487fd66..cdfc9abbbb7b 100644
--- a/arch/mips/netlogic/Platform
+++ b/arch/mips/netlogic/Platform
@@ -1,16 +1,17 @@
1# 1#
2# NETLOGIC includes 2# NETLOGIC includes
3# 3#
4cflags-$(CONFIG_NLM_COMMON) += -I$(srctree)/arch/mips/include/asm/mach-netlogic 4cflags-$(CONFIG_NLM_COMMON) += -I$(srctree)/arch/mips/include/asm/mach-netlogic
5cflags-$(CONFIG_NLM_COMMON) += -I$(srctree)/arch/mips/include/asm/netlogic 5cflags-$(CONFIG_NLM_COMMON) += -I$(srctree)/arch/mips/include/asm/netlogic
6 6
7# 7#
8# use mips64 if xlr is not available 8# use mips64 if xlr is not available
9# 9#
10cflags-$(CONFIG_NLM_XLR) += $(call cc-option,-march=xlr,-march=mips64) 10cflags-$(CONFIG_CPU_XLR) += $(call cc-option,-march=xlr,-march=mips64)
11cflags-$(CONFIG_CPU_XLP) += $(call cc-option,-march=xlp,-march=mips64r2)
11 12
12# 13#
13# NETLOGIC XLR/XLS SoC, Simulator and boards 14# NETLOGIC processor support
14# 15#
15core-$(CONFIG_NLM_XLR) += arch/mips/netlogic/xlr/ 16platform-$(CONFIG_NLM_COMMON) += netlogic/
16load-$(CONFIG_NLM_XLR_BOARD) += 0xffffffff84000000 17load-$(CONFIG_NLM_COMMON) += 0xffffffff80100000
diff --git a/arch/mips/netlogic/common/Makefile b/arch/mips/netlogic/common/Makefile
new file mode 100644
index 000000000000..291372a086f5
--- /dev/null
+++ b/arch/mips/netlogic/common/Makefile
@@ -0,0 +1,3 @@
1obj-y += irq.o time.o
2obj-$(CONFIG_SMP) += smp.o smpboot.o
3obj-$(CONFIG_EARLY_PRINTK) += earlycons.o
diff --git a/arch/mips/netlogic/common/earlycons.c b/arch/mips/netlogic/common/earlycons.c
new file mode 100644
index 000000000000..f193f7b3bd81
--- /dev/null
+++ b/arch/mips/netlogic/common/earlycons.c
@@ -0,0 +1,60 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/types.h>
36#include <linux/serial_reg.h>
37
38#include <asm/mipsregs.h>
39#include <asm/netlogic/haldefs.h>
40
41#if defined(CONFIG_CPU_XLP)
42#include <asm/netlogic/xlp-hal/iomap.h>
43#include <asm/netlogic/xlp-hal/uart.h>
44#elif defined(CONFIG_CPU_XLR)
45#include <asm/netlogic/xlr/iomap.h>
46#endif
47
48void prom_putchar(char c)
49{
50 uint64_t uartbase;
51
52#if defined(CONFIG_CPU_XLP)
53 uartbase = nlm_get_uart_regbase(0, 0);
54#elif defined(CONFIG_CPU_XLR)
55 uartbase = nlm_mmio_base(NETLOGIC_IO_UART_0_OFFSET);
56#endif
57 while (nlm_read_reg(uartbase, UART_LSR) == 0)
58 ;
59 nlm_write_reg(uartbase, UART_TX, c);
60}
diff --git a/arch/mips/netlogic/common/irq.c b/arch/mips/netlogic/common/irq.c
new file mode 100644
index 000000000000..49a4f6cf71e5
--- /dev/null
+++ b/arch/mips/netlogic/common/irq.c
@@ -0,0 +1,238 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/kernel.h>
36#include <linux/init.h>
37#include <linux/linkage.h>
38#include <linux/interrupt.h>
39#include <linux/spinlock.h>
40#include <linux/mm.h>
41#include <linux/slab.h>
42#include <linux/irq.h>
43
44#include <asm/errno.h>
45#include <asm/signal.h>
46#include <asm/system.h>
47#include <asm/ptrace.h>
48#include <asm/mipsregs.h>
49#include <asm/thread_info.h>
50
51#include <asm/netlogic/mips-extns.h>
52#include <asm/netlogic/interrupt.h>
53#include <asm/netlogic/haldefs.h>
54#include <asm/netlogic/common.h>
55
56#if defined(CONFIG_CPU_XLP)
57#include <asm/netlogic/xlp-hal/iomap.h>
58#include <asm/netlogic/xlp-hal/xlp.h>
59#include <asm/netlogic/xlp-hal/pic.h>
60#elif defined(CONFIG_CPU_XLR)
61#include <asm/netlogic/xlr/iomap.h>
62#include <asm/netlogic/xlr/pic.h>
63#else
64#error "Unknown CPU"
65#endif
66/*
67 * These are the routines that handle all the low level interrupt stuff.
68 * Actions handled here are: initialization of the interrupt map, requesting of
69 * interrupt lines by handlers, dispatching if interrupts to handlers, probing
70 * for interrupt lines
71 */
72
73/* Globals */
74static uint64_t nlm_irq_mask;
75static DEFINE_SPINLOCK(nlm_pic_lock);
76
77static void xlp_pic_enable(struct irq_data *d)
78{
79 unsigned long flags;
80 int irt;
81
82 irt = nlm_irq_to_irt(d->irq);
83 if (irt == -1)
84 return;
85 spin_lock_irqsave(&nlm_pic_lock, flags);
86 nlm_pic_enable_irt(nlm_pic_base, irt);
87 spin_unlock_irqrestore(&nlm_pic_lock, flags);
88}
89
90static void xlp_pic_disable(struct irq_data *d)
91{
92 unsigned long flags;
93 int irt;
94
95 irt = nlm_irq_to_irt(d->irq);
96 if (irt == -1)
97 return;
98 spin_lock_irqsave(&nlm_pic_lock, flags);
99 nlm_pic_disable_irt(nlm_pic_base, irt);
100 spin_unlock_irqrestore(&nlm_pic_lock, flags);
101}
102
103static void xlp_pic_mask_ack(struct irq_data *d)
104{
105 uint64_t mask = 1ull << d->irq;
106
107 write_c0_eirr(mask); /* ack by writing EIRR */
108}
109
110static void xlp_pic_unmask(struct irq_data *d)
111{
112 void *hd = irq_data_get_irq_handler_data(d);
113 int irt;
114
115 irt = nlm_irq_to_irt(d->irq);
116 if (irt == -1)
117 return;
118
119 if (hd) {
120 void (*extra_ack)(void *) = hd;
121 extra_ack(d);
122 }
123 /* Ack is a single write, no need to lock */
124 nlm_pic_ack(nlm_pic_base, irt);
125}
126
127static struct irq_chip xlp_pic = {
128 .name = "XLP-PIC",
129 .irq_enable = xlp_pic_enable,
130 .irq_disable = xlp_pic_disable,
131 .irq_mask_ack = xlp_pic_mask_ack,
132 .irq_unmask = xlp_pic_unmask,
133};
134
135static void cpuintr_disable(struct irq_data *d)
136{
137 uint64_t eimr;
138 uint64_t mask = 1ull << d->irq;
139
140 eimr = read_c0_eimr();
141 write_c0_eimr(eimr & ~mask);
142}
143
144static void cpuintr_enable(struct irq_data *d)
145{
146 uint64_t eimr;
147 uint64_t mask = 1ull << d->irq;
148
149 eimr = read_c0_eimr();
150 write_c0_eimr(eimr | mask);
151}
152
153static void cpuintr_ack(struct irq_data *d)
154{
155 uint64_t mask = 1ull << d->irq;
156
157 write_c0_eirr(mask);
158}
159
160static void cpuintr_nop(struct irq_data *d)
161{
162 WARN(d->irq >= PIC_IRQ_BASE, "Bad irq %d", d->irq);
163}
164
165/*
166 * Chip definition for CPU originated interrupts(timer, msg) and
167 * IPIs
168 */
169struct irq_chip nlm_cpu_intr = {
170 .name = "XLP-CPU-INTR",
171 .irq_enable = cpuintr_enable,
172 .irq_disable = cpuintr_disable,
173 .irq_mask = cpuintr_nop,
174 .irq_ack = cpuintr_nop,
175 .irq_eoi = cpuintr_ack,
176};
177
178void __init init_nlm_common_irqs(void)
179{
180 int i, irq, irt;
181
182 for (i = 0; i < PIC_IRT_FIRST_IRQ; i++)
183 irq_set_chip_and_handler(i, &nlm_cpu_intr, handle_percpu_irq);
184
185 for (i = PIC_IRT_FIRST_IRQ; i <= PIC_IRT_LAST_IRQ ; i++)
186 irq_set_chip_and_handler(i, &xlp_pic, handle_level_irq);
187
188#ifdef CONFIG_SMP
189 irq_set_chip_and_handler(IRQ_IPI_SMP_FUNCTION, &nlm_cpu_intr,
190 nlm_smp_function_ipi_handler);
191 irq_set_chip_and_handler(IRQ_IPI_SMP_RESCHEDULE, &nlm_cpu_intr,
192 nlm_smp_resched_ipi_handler);
193 nlm_irq_mask |=
194 ((1ULL << IRQ_IPI_SMP_FUNCTION) | (1ULL << IRQ_IPI_SMP_RESCHEDULE));
195#endif
196
197 for (irq = PIC_IRT_FIRST_IRQ; irq <= PIC_IRT_LAST_IRQ; irq++) {
198 irt = nlm_irq_to_irt(irq);
199 if (irt == -1)
200 continue;
201 nlm_irq_mask |= (1ULL << irq);
202 nlm_pic_init_irt(nlm_pic_base, irt, irq, 0);
203 }
204
205 nlm_irq_mask |= (1ULL << IRQ_TIMER);
206}
207
208void __init arch_init_irq(void)
209{
210 /* Initialize the irq descriptors */
211 init_nlm_common_irqs();
212
213 write_c0_eimr(nlm_irq_mask);
214}
215
216void __cpuinit nlm_smp_irq_init(void)
217{
218 /* set interrupt mask for non-zero cpus */
219 write_c0_eimr(nlm_irq_mask);
220}
221
222asmlinkage void plat_irq_dispatch(void)
223{
224 uint64_t eirr;
225 int i;
226
227 eirr = read_c0_eirr() & read_c0_eimr();
228 if (eirr & (1 << IRQ_TIMER)) {
229 do_IRQ(IRQ_TIMER);
230 return;
231 }
232
233 i = __ilog2_u64(eirr);
234 if (i == -1)
235 return;
236
237 do_IRQ(i);
238}
diff --git a/arch/mips/netlogic/xlr/smp.c b/arch/mips/netlogic/common/smp.c
index 080284ded508..db17f49886c2 100644
--- a/arch/mips/netlogic/xlr/smp.c
+++ b/arch/mips/netlogic/common/smp.c
@@ -42,31 +42,29 @@
42 42
43#include <asm/netlogic/interrupt.h> 43#include <asm/netlogic/interrupt.h>
44#include <asm/netlogic/mips-extns.h> 44#include <asm/netlogic/mips-extns.h>
45 45#include <asm/netlogic/haldefs.h>
46#include <asm/netlogic/common.h>
47
48#if defined(CONFIG_CPU_XLP)
49#include <asm/netlogic/xlp-hal/iomap.h>
50#include <asm/netlogic/xlp-hal/xlp.h>
51#include <asm/netlogic/xlp-hal/pic.h>
52#elif defined(CONFIG_CPU_XLR)
46#include <asm/netlogic/xlr/iomap.h> 53#include <asm/netlogic/xlr/iomap.h>
47#include <asm/netlogic/xlr/pic.h> 54#include <asm/netlogic/xlr/pic.h>
48#include <asm/netlogic/xlr/xlr.h> 55#include <asm/netlogic/xlr/xlr.h>
56#else
57#error "Unknown CPU"
58#endif
49 59
50void core_send_ipi(int logical_cpu, unsigned int action) 60void nlm_send_ipi_single(int logical_cpu, unsigned int action)
51{ 61{
52 int cpu = cpu_logical_map(logical_cpu); 62 int cpu = cpu_logical_map(logical_cpu);
53 u32 tid = cpu & 0x3;
54 u32 pid = (cpu >> 2) & 0x07;
55 u32 ipi = (tid << 16) | (pid << 20);
56 63
57 if (action & SMP_CALL_FUNCTION) 64 if (action & SMP_CALL_FUNCTION)
58 ipi |= IRQ_IPI_SMP_FUNCTION; 65 nlm_pic_send_ipi(nlm_pic_base, cpu, IRQ_IPI_SMP_FUNCTION, 0);
59 else if (action & SMP_RESCHEDULE_YOURSELF) 66 if (action & SMP_RESCHEDULE_YOURSELF)
60 ipi |= IRQ_IPI_SMP_RESCHEDULE; 67 nlm_pic_send_ipi(nlm_pic_base, cpu, IRQ_IPI_SMP_RESCHEDULE, 0);
61 else
62 return;
63
64 pic_send_ipi(ipi);
65}
66
67void nlm_send_ipi_single(int cpu, unsigned int action)
68{
69 core_send_ipi(cpu, action);
70} 68}
71 69
72void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action) 70void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action)
@@ -74,29 +72,35 @@ void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action)
74 int cpu; 72 int cpu;
75 73
76 for_each_cpu(cpu, mask) { 74 for_each_cpu(cpu, mask) {
77 core_send_ipi(cpu, action); 75 nlm_send_ipi_single(cpu, action);
78 } 76 }
79} 77}
80 78
81/* IRQ_IPI_SMP_FUNCTION Handler */ 79/* IRQ_IPI_SMP_FUNCTION Handler */
82void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc) 80void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc)
83{ 81{
82 write_c0_eirr(1ull << irq);
84 smp_call_function_interrupt(); 83 smp_call_function_interrupt();
85} 84}
86 85
87/* IRQ_IPI_SMP_RESCHEDULE handler */ 86/* IRQ_IPI_SMP_RESCHEDULE handler */
88void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc) 87void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc)
89{ 88{
89 write_c0_eirr(1ull << irq);
90 scheduler_ipi(); 90 scheduler_ipi();
91} 91}
92 92
93/* 93/*
94 * Called before going into mips code, early cpu init 94 * Called before going into mips code, early cpu init
95 */ 95 */
96void nlm_early_init_secondary(void) 96void nlm_early_init_secondary(int cpu)
97{ 97{
98 change_c0_config(CONF_CM_CMASK, 0x3);
98 write_c0_ebase((uint32_t)nlm_common_ebase); 99 write_c0_ebase((uint32_t)nlm_common_ebase);
99 /* TLB partition here later */ 100#ifdef CONFIG_CPU_XLP
101 if (hard_smp_processor_id() % 4 == 0)
102 xlp_mmu_init();
103#endif
100} 104}
101 105
102/* 106/*
@@ -104,9 +108,16 @@ void nlm_early_init_secondary(void)
104 */ 108 */
105static void __cpuinit nlm_init_secondary(void) 109static void __cpuinit nlm_init_secondary(void)
106{ 110{
111 current_cpu_data.core = hard_smp_processor_id() / 4;
107 nlm_smp_irq_init(); 112 nlm_smp_irq_init();
108} 113}
109 114
115void nlm_prepare_cpus(unsigned int max_cpus)
116{
117 /* declare we are SMT capable */
118 smp_num_siblings = nlm_threads_per_core;
119}
120
110void nlm_smp_finish(void) 121void nlm_smp_finish(void)
111{ 122{
112#ifdef notyet 123#ifdef notyet
@@ -123,10 +134,10 @@ void nlm_cpus_done(void)
123 * Boot all other cpus in the system, initialize them, and bring them into 134 * Boot all other cpus in the system, initialize them, and bring them into
124 * the boot function 135 * the boot function
125 */ 136 */
126int nlm_cpu_unblock[NR_CPUS];
127int nlm_cpu_ready[NR_CPUS]; 137int nlm_cpu_ready[NR_CPUS];
128unsigned long nlm_next_gp; 138unsigned long nlm_next_gp;
129unsigned long nlm_next_sp; 139unsigned long nlm_next_sp;
140
130cpumask_t phys_cpu_present_map; 141cpumask_t phys_cpu_present_map;
131 142
132void nlm_boot_secondary(int logical_cpu, struct task_struct *idle) 143void nlm_boot_secondary(int logical_cpu, struct task_struct *idle)
@@ -140,7 +151,7 @@ void nlm_boot_secondary(int logical_cpu, struct task_struct *idle)
140 151
141 /* barrier */ 152 /* barrier */
142 __sync(); 153 __sync();
143 nlm_cpu_unblock[cpu] = 1; 154 nlm_pic_send_ipi(nlm_pic_base, cpu, 1, 1);
144} 155}
145 156
146void __init nlm_smp_setup(void) 157void __init nlm_smp_setup(void)
@@ -159,8 +170,8 @@ void __init nlm_smp_setup(void)
159 num_cpus = 1; 170 num_cpus = 1;
160 for (i = 0; i < NR_CPUS; i++) { 171 for (i = 0; i < NR_CPUS; i++) {
161 /* 172 /*
162 * BSP is not set in nlm_cpu_ready array, it is only for 173 * nlm_cpu_ready array is not set for the boot_cpu,
163 * ASPs (goto see smpboot.S) 174 * it is only set for ASPs (see smpboot.S)
164 */ 175 */
165 if (nlm_cpu_ready[i]) { 176 if (nlm_cpu_ready[i]) {
166 cpu_set(i, phys_cpu_present_map); 177 cpu_set(i, phys_cpu_present_map);
@@ -176,10 +187,75 @@ void __init nlm_smp_setup(void)
176 (unsigned long)cpu_possible_map.bits[0]); 187 (unsigned long)cpu_possible_map.bits[0]);
177 188
178 pr_info("Detected %i Slave CPU(s)\n", num_cpus); 189 pr_info("Detected %i Slave CPU(s)\n", num_cpus);
190 nlm_set_nmi_handler(nlm_boot_secondary_cpus);
179} 191}
180 192
181void nlm_prepare_cpus(unsigned int max_cpus) 193static int nlm_parse_cpumask(u32 cpu_mask)
194{
195 uint32_t core0_thr_mask, core_thr_mask;
196 int threadmode, i;
197
198 core0_thr_mask = cpu_mask & 0xf;
199 switch (core0_thr_mask) {
200 case 1:
201 nlm_threads_per_core = 1;
202 threadmode = 0;
203 break;
204 case 3:
205 nlm_threads_per_core = 2;
206 threadmode = 2;
207 break;
208 case 0xf:
209 nlm_threads_per_core = 4;
210 threadmode = 3;
211 break;
212 default:
213 goto unsupp;
214 }
215
216 /* Verify other cores CPU masks */
217 nlm_coremask = 1;
218 nlm_cpumask = core0_thr_mask;
219 for (i = 1; i < 8; i++) {
220 core_thr_mask = (cpu_mask >> (i * 4)) & 0xf;
221 if (core_thr_mask) {
222 if (core_thr_mask != core0_thr_mask)
223 goto unsupp;
224 nlm_coremask |= 1 << i;
225 nlm_cpumask |= core0_thr_mask << (4 * i);
226 }
227 }
228 return threadmode;
229
230unsupp:
231 panic("Unsupported CPU mask %x\n", cpu_mask);
232 return 0;
233}
234
235int __cpuinit nlm_wakeup_secondary_cpus(u32 wakeup_mask)
182{ 236{
237 unsigned long reset_vec;
238 char *reset_data;
239 int threadmode;
240
241 /* Update reset entry point with CPU init code */
242 reset_vec = CKSEG1ADDR(RESET_VEC_PHYS);
243 memcpy((void *)reset_vec, (void *)nlm_reset_entry,
244 (nlm_reset_entry_end - nlm_reset_entry));
245
246 /* verify the mask and setup core config variables */
247 threadmode = nlm_parse_cpumask(wakeup_mask);
248
249 /* Setup CPU init parameters */
250 reset_data = (char *)CKSEG1ADDR(RESET_DATA_PHYS);
251 *(int *)(reset_data + BOOT_THREAD_MODE) = threadmode;
252
253#ifdef CONFIG_CPU_XLP
254 xlp_wakeup_secondary_cpus();
255#else
256 xlr_wakeup_secondary_cpus();
257#endif
258 return 0;
183} 259}
184 260
185struct plat_smp_ops nlm_smp_ops = { 261struct plat_smp_ops nlm_smp_ops = {
@@ -192,29 +268,3 @@ struct plat_smp_ops nlm_smp_ops = {
192 .smp_setup = nlm_smp_setup, 268 .smp_setup = nlm_smp_setup,
193 .prepare_cpus = nlm_prepare_cpus, 269 .prepare_cpus = nlm_prepare_cpus,
194}; 270};
195
196unsigned long secondary_entry_point;
197
198int __cpuinit nlm_wakeup_secondary_cpus(u32 wakeup_mask)
199{
200 unsigned int tid, pid, ipi, i, boot_cpu;
201 void *reset_vec;
202
203 secondary_entry_point = (unsigned long)prom_pre_boot_secondary_cpus;
204 reset_vec = (void *)CKSEG1ADDR(0x1fc00000);
205 memcpy(reset_vec, nlm_boot_smp_nmi, 0x80);
206 boot_cpu = hard_smp_processor_id();
207
208 for (i = 0; i < NR_CPUS; i++) {
209 if (i == boot_cpu)
210 continue;
211 if (wakeup_mask & (1u << i)) {
212 tid = i & 0x3;
213 pid = (i >> 2) & 0x7;
214 ipi = (tid << 16) | (pid << 20) | (1 << 8);
215 pic_send_ipi(ipi);
216 }
217 }
218
219 return 0;
220}
diff --git a/arch/mips/netlogic/common/smpboot.S b/arch/mips/netlogic/common/smpboot.S
new file mode 100644
index 000000000000..c138b1a6dec3
--- /dev/null
+++ b/arch/mips/netlogic/common/smpboot.S
@@ -0,0 +1,272 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/init.h>
36
37#include <asm/asm.h>
38#include <asm/asm-offsets.h>
39#include <asm/regdef.h>
40#include <asm/mipsregs.h>
41#include <asm/stackframe.h>
42#include <asm/asmmacro.h>
43#include <asm/addrspace.h>
44
45#include <asm/netlogic/common.h>
46
47#include <asm/netlogic/xlp-hal/iomap.h>
48#include <asm/netlogic/xlp-hal/xlp.h>
49#include <asm/netlogic/xlp-hal/sys.h>
50#include <asm/netlogic/xlp-hal/cpucontrol.h>
51
52#define CP0_EBASE $15
53#define SYS_CPU_COHERENT_BASE(node) CKSEG1ADDR(XLP_DEFAULT_IO_BASE) + \
54 XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + \
55 SYS_CPU_NONCOHERENT_MODE * 4
56
57.macro __config_lsu
58 li t0, LSU_DEFEATURE
59 mfcr t1, t0
60
61 lui t2, 0x4080 /* Enable Unaligned Access, L2HPE */
62 or t1, t1, t2
63 li t2, ~0xe /* S1RCM */
64 and t1, t1, t2
65 mtcr t1, t0
66
67 li t0, SCHED_DEFEATURE
68 lui t1, 0x0100 /* Experimental: Disable BRU accepting ALU ops */
69 mtcr t1, t0
70.endm
71
72/*
73 * The cores can come start when they are woken up. This is also the NMI
74 * entry, so check that first.
75 *
76 * The data corresponding to reset is stored at RESET_DATA_PHYS location,
77 * this will have the thread mask (used when core is woken up) and the
78 * current NMI handler in case we reached here for an NMI.
79 *
80 * When a core or thread is newly woken up, it loops in a 'wait'. When
81 * the CPU really needs waking up, we send an NMI to it, with the NMI
82 * handler set to prom_boot_secondary_cpus
83 */
84
85 .set noreorder
86 .set noat
87 .set arch=xlr /* for mfcr/mtcr, XLR is sufficient */
88
89FEXPORT(nlm_reset_entry)
90 dmtc0 k0, $22, 6
91 dmtc0 k1, $22, 7
92 mfc0 k0, CP0_STATUS
93 li k1, 0x80000
94 and k1, k0, k1
95 beqz k1, 1f /* go to real reset entry */
96 nop
97 li k1, CKSEG1ADDR(RESET_DATA_PHYS) /* NMI */
98 ld k0, BOOT_NMI_HANDLER(k1)
99 jr k0
100 nop
101
1021: /* Entry point on core wakeup */
103 mfc0 t0, CP0_EBASE, 1
104 mfc0 t1, CP0_EBASE, 1
105 srl t1, 5
106 andi t1, 0x3 /* t1 <- node */
107 li t2, 0x40000
108 mul t3, t2, t1 /* t3 = node * 0x40000 */
109 srl t0, t0, 2
110 and t0, t0, 0x7 /* t0 <- core */
111 li t1, 0x1
112 sll t0, t1, t0
113 nor t0, t0, zero /* t0 <- ~(1 << core) */
114 li t2, SYS_CPU_COHERENT_BASE(0)
115 add t2, t2, t3 /* t2 <- SYS offset for node */
116 lw t1, 0(t2)
117 and t1, t1, t0
118 sw t1, 0(t2)
119
120 /* read back to ensure complete */
121 lw t1, 0(t2)
122 sync
123
124 /* Configure LSU on Non-0 Cores. */
125 __config_lsu
126
127/*
128 * Wake up sibling threads from the initial thread in
129 * a core.
130 */
131EXPORT(nlm_boot_siblings)
132 li t0, CKSEG1ADDR(RESET_DATA_PHYS)
133 lw t1, BOOT_THREAD_MODE(t0) /* t1 <- thread mode */
134 li t0, ((CPU_BLOCKID_MAP << 8) | MAP_THREADMODE)
135 mfcr t2, t0
136 or t2, t2, t1
137 mtcr t2, t0
138
139 /*
140 * The new hardware thread starts at the next instruction
141 * For all the cases other than core 0 thread 0, we will
142 * jump to the secondary wait function.
143 */
144 mfc0 v0, CP0_EBASE, 1
145 andi v0, 0x7f /* v0 <- node/core */
146
147#if 1
148 /* A0 errata - Write MMU_SETUP after changing thread mode register. */
149 andi v1, v0, 0x3 /* v1 <- thread id */
150 bnez v1, 2f
151 nop
152
153 li t0, MMU_SETUP
154 li t1, 0
155 mtcr t1, t0
156 ehb
157#endif
158
1592: beqz v0, 4f
160 nop
161
162 /* setup status reg */
163 mfc0 t1, CP0_STATUS
164 li t0, ST0_BEV
165 or t1, t0
166 xor t1, t0
167#ifdef CONFIG_64BIT
168 ori t1, ST0_KX
169#endif
170 mtc0 t1, CP0_STATUS
171 /* mark CPU ready */
172 PTR_LA t1, nlm_cpu_ready
173 sll v1, v0, 2
174 PTR_ADDU t1, v1
175 li t2, 1
176 sw t2, 0(t1)
177 /* Wait until NMI hits */
1783: wait
179 j 3b
180 nop
181
182 /*
183 * For the boot CPU, we have to restore registers and
184 * return
185 */
1864: dmfc0 t0, $4, 2 /* restore SP from UserLocal */
187 li t1, 0xfadebeef
188 dmtc0 t1, $4, 2 /* restore SP from UserLocal */
189 PTR_SUBU sp, t0, PT_SIZE
190 RESTORE_ALL
191 jr ra
192 nop
193EXPORT(nlm_reset_entry_end)
194
195FEXPORT(xlp_boot_core0_siblings) /* "Master" cpu starts from here */
196 __config_lsu
197 dmtc0 sp, $4, 2 /* SP saved in UserLocal */
198 SAVE_ALL
199 sync
200 /* find the location to which nlm_boot_siblings was relocated */
201 li t0, CKSEG1ADDR(RESET_VEC_PHYS)
202 dla t1, nlm_reset_entry
203 dla t2, nlm_boot_siblings
204 dsubu t2, t1
205 daddu t2, t0
206 /* call it */
207 jr t2
208 nop
209 /* not reached */
210
211 __CPUINIT
212NESTED(nlm_boot_secondary_cpus, 16, sp)
213 PTR_LA t1, nlm_next_sp
214 PTR_L sp, 0(t1)
215 PTR_LA t1, nlm_next_gp
216 PTR_L gp, 0(t1)
217
218 /* a0 has the processor id */
219 PTR_LA t0, nlm_early_init_secondary
220 jalr t0
221 nop
222
223 PTR_LA t0, smp_bootstrap
224 jr t0
225 nop
226END(nlm_boot_secondary_cpus)
227 __FINIT
228
229/*
230 * In case of RMIboot bootloader which is used on XLR boards, the CPUs
231 * be already woken up and waiting in bootloader code.
232 * This will get them out of the bootloader code and into linux. Needed
233 * because the bootloader area will be taken and initialized by linux.
234 */
235 __CPUINIT
236NESTED(nlm_rmiboot_preboot, 16, sp)
237 mfc0 t0, $15, 1 # read ebase
238 andi t0, 0x1f # t0 has the processor_id()
239 andi t2, t0, 0x3 # thread no
240 sll t0, 2 # offset in cpu array
241
242 PTR_LA t1, nlm_cpu_ready # mark CPU ready
243 PTR_ADDU t1, t0
244 li t3, 1
245 sw t3, 0(t1)
246
247 bnez t2, 1f # skip thread programming
248 nop # for non zero hw threads
249
250 /*
251 * MMU setup only for first thread in core
252 */
253 li t0, 0x400
254 mfcr t1, t0
255 li t2, 6 # XLR thread mode mask
256 nor t3, t2, zero
257 and t2, t1, t2 # t2 - current thread mode
258 li v0, CKSEG1ADDR(RESET_DATA_PHYS)
259 lw v1, BOOT_THREAD_MODE(v0) # v1 - new thread mode
260 sll v1, 1
261 beq v1, t2, 1f # same as request value
262 nop # nothing to do */
263
264 and t2, t1, t3 # mask out old thread mode
265 or t1, t2, v1 # put in new value
266 mtcr t1, t0 # update core control
267
2681: wait
269 j 1b
270 nop
271END(nlm_rmiboot_preboot)
272 __FINIT
diff --git a/arch/mips/netlogic/xlr/time.c b/arch/mips/netlogic/common/time.c
index 0d81b262593c..bd3e498157ff 100644
--- a/arch/mips/netlogic/xlr/time.c
+++ b/arch/mips/netlogic/common/time.c
@@ -36,7 +36,7 @@
36 36
37#include <asm/time.h> 37#include <asm/time.h>
38#include <asm/netlogic/interrupt.h> 38#include <asm/netlogic/interrupt.h>
39#include <asm/netlogic/psb-bootinfo.h> 39#include <asm/netlogic/common.h>
40 40
41unsigned int __cpuinit get_c0_compare_int(void) 41unsigned int __cpuinit get_c0_compare_int(void)
42{ 42{
@@ -45,7 +45,7 @@ unsigned int __cpuinit get_c0_compare_int(void)
45 45
46void __init plat_time_init(void) 46void __init plat_time_init(void)
47{ 47{
48 mips_hpt_frequency = nlm_prom_info.cpu_frequency; 48 mips_hpt_frequency = nlm_get_cpu_frequency();
49 pr_info("MIPS counter frequency [%ld]\n", 49 pr_info("MIPS counter frequency [%ld]\n",
50 (unsigned long)mips_hpt_frequency); 50 (unsigned long)mips_hpt_frequency);
51} 51}
diff --git a/arch/mips/netlogic/xlp/Makefile b/arch/mips/netlogic/xlp/Makefile
new file mode 100644
index 000000000000..b93ed83474ec
--- /dev/null
+++ b/arch/mips/netlogic/xlp/Makefile
@@ -0,0 +1,2 @@
1obj-y += setup.o platform.o nlm_hal.o
2obj-$(CONFIG_SMP) += wakeup.o
diff --git a/arch/mips/netlogic/xlp/nlm_hal.c b/arch/mips/netlogic/xlp/nlm_hal.c
new file mode 100644
index 000000000000..9428e7125fed
--- /dev/null
+++ b/arch/mips/netlogic/xlp/nlm_hal.c
@@ -0,0 +1,111 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/types.h>
36#include <linux/kernel.h>
37#include <linux/mm.h>
38#include <linux/delay.h>
39
40#include <asm/mipsregs.h>
41#include <asm/time.h>
42
43#include <asm/netlogic/haldefs.h>
44#include <asm/netlogic/xlp-hal/iomap.h>
45#include <asm/netlogic/xlp-hal/xlp.h>
46#include <asm/netlogic/xlp-hal/pic.h>
47#include <asm/netlogic/xlp-hal/sys.h>
48
49/* These addresses are computed by the nlm_hal_init() */
50uint64_t nlm_io_base;
51uint64_t nlm_sys_base;
52uint64_t nlm_pic_base;
53
54/* Main initialization */
55void nlm_hal_init(void)
56{
57 nlm_io_base = CKSEG1ADDR(XLP_DEFAULT_IO_BASE);
58 nlm_sys_base = nlm_get_sys_regbase(0); /* node 0 */
59 nlm_pic_base = nlm_get_pic_regbase(0); /* node 0 */
60}
61
62int nlm_irq_to_irt(int irq)
63{
64 if (!PIC_IRQ_IS_IRT(irq))
65 return -1;
66
67 switch (irq) {
68 case PIC_UART_0_IRQ:
69 return PIC_IRT_UART_0_INDEX;
70 case PIC_UART_1_IRQ:
71 return PIC_IRT_UART_1_INDEX;
72 default:
73 return -1;
74 }
75}
76
77int nlm_irt_to_irq(int irt)
78{
79 switch (irt) {
80 case PIC_IRT_UART_0_INDEX:
81 return PIC_UART_0_IRQ;
82 case PIC_IRT_UART_1_INDEX:
83 return PIC_UART_1_IRQ;
84 default:
85 return -1;
86 }
87}
88
89unsigned int nlm_get_core_frequency(int core)
90{
91 unsigned int pll_divf, pll_divr, dfs_div, ext_div;
92 unsigned int rstval, dfsval, denom;
93 uint64_t num;
94
95 rstval = nlm_read_sys_reg(nlm_sys_base, SYS_POWER_ON_RESET_CFG);
96 dfsval = nlm_read_sys_reg(nlm_sys_base, SYS_CORE_DFS_DIV_VALUE);
97 pll_divf = ((rstval >> 10) & 0x7f) + 1;
98 pll_divr = ((rstval >> 8) & 0x3) + 1;
99 ext_div = ((rstval >> 30) & 0x3) + 1;
100 dfs_div = ((dfsval >> (core * 4)) & 0xf) + 1;
101
102 num = 800000000ULL * pll_divf;
103 denom = 3 * pll_divr * ext_div * dfs_div;
104 do_div(num, denom);
105 return (unsigned int)num;
106}
107
108unsigned int nlm_get_cpu_frequency(void)
109{
110 return nlm_get_core_frequency(0);
111}
diff --git a/arch/mips/netlogic/xlp/platform.c b/arch/mips/netlogic/xlp/platform.c
new file mode 100644
index 000000000000..1f5e4cba891d
--- /dev/null
+++ b/arch/mips/netlogic/xlp/platform.c
@@ -0,0 +1,108 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/dma-mapping.h>
36#include <linux/kernel.h>
37#include <linux/delay.h>
38#include <linux/init.h>
39#include <linux/platform_device.h>
40#include <linux/serial.h>
41#include <linux/serial_8250.h>
42#include <linux/pci.h>
43#include <linux/serial_reg.h>
44#include <linux/spinlock.h>
45
46#include <asm/time.h>
47#include <asm/addrspace.h>
48#include <asm/netlogic/haldefs.h>
49#include <asm/netlogic/xlp-hal/iomap.h>
50#include <asm/netlogic/xlp-hal/xlp.h>
51#include <asm/netlogic/xlp-hal/pic.h>
52#include <asm/netlogic/xlp-hal/uart.h>
53
54static unsigned int nlm_xlp_uart_in(struct uart_port *p, int offset)
55{
56 return nlm_read_reg(p->iobase, offset);
57}
58
59static void nlm_xlp_uart_out(struct uart_port *p, int offset, int value)
60{
61 nlm_write_reg(p->iobase, offset, value);
62}
63
64#define PORT(_irq) \
65 { \
66 .irq = _irq, \
67 .regshift = 2, \
68 .iotype = UPIO_MEM32, \
69 .flags = (UPF_SKIP_TEST|UPF_FIXED_TYPE|\
70 UPF_BOOT_AUTOCONF), \
71 .uartclk = XLP_IO_CLK, \
72 .type = PORT_16550A, \
73 .serial_in = nlm_xlp_uart_in, \
74 .serial_out = nlm_xlp_uart_out, \
75 }
76
77static struct plat_serial8250_port xlp_uart_data[] = {
78 PORT(PIC_UART_0_IRQ),
79 PORT(PIC_UART_1_IRQ),
80 {},
81};
82
83static struct platform_device uart_device = {
84 .name = "serial8250",
85 .id = PLAT8250_DEV_PLATFORM,
86 .dev = {
87 .platform_data = xlp_uart_data,
88 },
89};
90
91static int __init nlm_platform_uart_init(void)
92{
93 unsigned long mmio;
94
95 mmio = (unsigned long)nlm_get_uart_regbase(0, 0);
96 xlp_uart_data[0].iobase = mmio;
97 xlp_uart_data[0].membase = (void __iomem *)mmio;
98 xlp_uart_data[0].mapbase = mmio;
99
100 mmio = (unsigned long)nlm_get_uart_regbase(0, 1);
101 xlp_uart_data[1].iobase = mmio;
102 xlp_uart_data[1].membase = (void __iomem *)mmio;
103 xlp_uart_data[1].mapbase = mmio;
104
105 return platform_device_register(&uart_device);
106}
107
108arch_initcall(nlm_platform_uart_init);
diff --git a/arch/mips/netlogic/xlp/setup.c b/arch/mips/netlogic/xlp/setup.c
new file mode 100644
index 000000000000..acb677a1227c
--- /dev/null
+++ b/arch/mips/netlogic/xlp/setup.c
@@ -0,0 +1,105 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/kernel.h>
36#include <linux/serial_8250.h>
37#include <linux/pm.h>
38
39#include <asm/reboot.h>
40#include <asm/time.h>
41#include <asm/bootinfo.h>
42
43#include <linux/of_fdt.h>
44
45#include <asm/netlogic/haldefs.h>
46#include <asm/netlogic/common.h>
47
48#include <asm/netlogic/xlp-hal/iomap.h>
49#include <asm/netlogic/xlp-hal/xlp.h>
50#include <asm/netlogic/xlp-hal/sys.h>
51
52unsigned long nlm_common_ebase = 0x0;
53
54/* default to uniprocessor */
55uint32_t nlm_coremask = 1, nlm_cpumask = 1;
56int nlm_threads_per_core = 1;
57
58static void nlm_linux_exit(void)
59{
60 nlm_write_sys_reg(nlm_sys_base, SYS_CHIP_RESET, 1);
61 for ( ; ; )
62 cpu_wait();
63}
64
65void __init plat_mem_setup(void)
66{
67 panic_timeout = 5;
68 _machine_restart = (void (*)(char *))nlm_linux_exit;
69 _machine_halt = nlm_linux_exit;
70 pm_power_off = nlm_linux_exit;
71}
72
73const char *get_system_type(void)
74{
75 return "Netlogic XLP Series";
76}
77
78void __init prom_free_prom_memory(void)
79{
80 /* Nothing yet */
81}
82
83void xlp_mmu_init(void)
84{
85 write_c0_config6(read_c0_config6() | 0x24);
86 current_cpu_data.tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
87 write_c0_config7(PM_DEFAULT_MASK >>
88 (13 + (ffz(PM_DEFAULT_MASK >> 13) / 2)));
89}
90
91void __init prom_init(void)
92{
93 void *fdtp;
94
95 fdtp = (void *)(long)fw_arg0;
96 xlp_mmu_init();
97 nlm_hal_init();
98 early_init_devtree(fdtp);
99
100 nlm_common_ebase = read_c0_ebase() & (~((1 << 12) - 1));
101#ifdef CONFIG_SMP
102 nlm_wakeup_secondary_cpus(0xffffffff);
103 register_smp_ops(&nlm_smp_ops);
104#endif
105}
diff --git a/arch/mips/netlogic/xlp/wakeup.c b/arch/mips/netlogic/xlp/wakeup.c
new file mode 100644
index 000000000000..44d923ff3846
--- /dev/null
+++ b/arch/mips/netlogic/xlp/wakeup.c
@@ -0,0 +1,102 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/init.h>
36#include <linux/kernel.h>
37#include <linux/threads.h>
38
39#include <asm/asm.h>
40#include <asm/asm-offsets.h>
41#include <asm/mipsregs.h>
42#include <asm/addrspace.h>
43#include <asm/string.h>
44
45#include <asm/netlogic/haldefs.h>
46#include <asm/netlogic/common.h>
47#include <asm/netlogic/mips-extns.h>
48
49#include <asm/netlogic/xlp-hal/iomap.h>
50#include <asm/netlogic/xlp-hal/pic.h>
51#include <asm/netlogic/xlp-hal/xlp.h>
52#include <asm/netlogic/xlp-hal/sys.h>
53
54static void xlp_enable_secondary_cores(void)
55{
56 uint32_t core, value, coremask, syscoremask;
57 int count;
58
59 /* read cores in reset from SYS block */
60 syscoremask = nlm_read_sys_reg(nlm_sys_base, SYS_CPU_RESET);
61
62 /* update user specified */
63 nlm_coremask = nlm_coremask & (syscoremask | 1);
64
65 for (core = 1; core < 8; core++) {
66 coremask = 1 << core;
67 if ((nlm_coremask & coremask) == 0)
68 continue;
69
70 /* Enable CPU clock */
71 value = nlm_read_sys_reg(nlm_sys_base, SYS_CORE_DFS_DIS_CTRL);
72 value &= ~coremask;
73 nlm_write_sys_reg(nlm_sys_base, SYS_CORE_DFS_DIS_CTRL, value);
74
75 /* Remove CPU Reset */
76 value = nlm_read_sys_reg(nlm_sys_base, SYS_CPU_RESET);
77 value &= ~coremask;
78 nlm_write_sys_reg(nlm_sys_base, SYS_CPU_RESET, value);
79
80 /* Poll for CPU to mark itself coherent */
81 count = 100000;
82 do {
83 value = nlm_read_sys_reg(nlm_sys_base,
84 SYS_CPU_NONCOHERENT_MODE);
85 } while ((value & coremask) != 0 && count-- > 0);
86
87 if (count == 0)
88 pr_err("Failed to enable core %d\n", core);
89 }
90}
91
92void xlp_wakeup_secondary_cpus(void)
93{
94 /*
95 * In case of u-boot, the secondaries are in reset
96 * first wakeup core 0 threads
97 */
98 xlp_boot_core0_siblings();
99
100 /* now get other cores out of reset */
101 xlp_enable_secondary_cores();
102}
diff --git a/arch/mips/netlogic/xlr/Makefile b/arch/mips/netlogic/xlr/Makefile
index 2dca585dd2f7..f01e4d7a0600 100644
--- a/arch/mips/netlogic/xlr/Makefile
+++ b/arch/mips/netlogic/xlr/Makefile
@@ -1,5 +1,2 @@
1obj-y += setup.o platform.o irq.o setup.o time.o 1obj-y += setup.o platform.o
2obj-$(CONFIG_SMP) += smp.o smpboot.o 2obj-$(CONFIG_SMP) += wakeup.o
3obj-$(CONFIG_EARLY_PRINTK) += xlr_console.o
4
5ccflags-y += -Werror
diff --git a/arch/mips/netlogic/xlr/irq.c b/arch/mips/netlogic/xlr/irq.c
deleted file mode 100644
index 521bb7377eb0..000000000000
--- a/arch/mips/netlogic/xlr/irq.c
+++ /dev/null
@@ -1,300 +0,0 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/kernel.h>
36#include <linux/init.h>
37#include <linux/linkage.h>
38#include <linux/interrupt.h>
39#include <linux/spinlock.h>
40#include <linux/mm.h>
41
42#include <asm/mipsregs.h>
43
44#include <asm/netlogic/xlr/iomap.h>
45#include <asm/netlogic/xlr/pic.h>
46#include <asm/netlogic/xlr/xlr.h>
47
48#include <asm/netlogic/interrupt.h>
49#include <asm/netlogic/mips-extns.h>
50
51static u64 nlm_irq_mask;
52static DEFINE_SPINLOCK(nlm_pic_lock);
53
54static void xlr_pic_enable(struct irq_data *d)
55{
56 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
57 unsigned long flags;
58 nlm_reg_t reg;
59 int irq = d->irq;
60
61 WARN(!PIC_IRQ_IS_IRT(irq), "Bad irq %d", irq);
62
63 spin_lock_irqsave(&nlm_pic_lock, flags);
64 reg = netlogic_read_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE);
65 netlogic_write_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE,
66 reg | (1 << 6) | (1 << 30) | (1 << 31));
67 spin_unlock_irqrestore(&nlm_pic_lock, flags);
68}
69
70static void xlr_pic_mask(struct irq_data *d)
71{
72 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
73 unsigned long flags;
74 nlm_reg_t reg;
75 int irq = d->irq;
76
77 WARN(!PIC_IRQ_IS_IRT(irq), "Bad irq %d", irq);
78
79 spin_lock_irqsave(&nlm_pic_lock, flags);
80 reg = netlogic_read_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE);
81 netlogic_write_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE,
82 reg | (1 << 6) | (1 << 30) | (0 << 31));
83 spin_unlock_irqrestore(&nlm_pic_lock, flags);
84}
85
86#ifdef CONFIG_PCI
87/* Extra ACK needed for XLR on chip PCI controller */
88static void xlr_pci_ack(struct irq_data *d)
89{
90 nlm_reg_t *pci_mmio = netlogic_io_mmio(NETLOGIC_IO_PCIX_OFFSET);
91
92 netlogic_read_reg(pci_mmio, (0x140 >> 2));
93}
94
95/* Extra ACK needed for XLS on chip PCIe controller */
96static void xls_pcie_ack(struct irq_data *d)
97{
98 nlm_reg_t *pcie_mmio_le = netlogic_io_mmio(NETLOGIC_IO_PCIE_1_OFFSET);
99
100 switch (d->irq) {
101 case PIC_PCIE_LINK0_IRQ:
102 netlogic_write_reg(pcie_mmio_le, (0x90 >> 2), 0xffffffff);
103 break;
104 case PIC_PCIE_LINK1_IRQ:
105 netlogic_write_reg(pcie_mmio_le, (0x94 >> 2), 0xffffffff);
106 break;
107 case PIC_PCIE_LINK2_IRQ:
108 netlogic_write_reg(pcie_mmio_le, (0x190 >> 2), 0xffffffff);
109 break;
110 case PIC_PCIE_LINK3_IRQ:
111 netlogic_write_reg(pcie_mmio_le, (0x194 >> 2), 0xffffffff);
112 break;
113 }
114}
115
116/* For XLS B silicon, the 3,4 PCI interrupts are different */
117static void xls_pcie_ack_b(struct irq_data *d)
118{
119 nlm_reg_t *pcie_mmio_le = netlogic_io_mmio(NETLOGIC_IO_PCIE_1_OFFSET);
120
121 switch (d->irq) {
122 case PIC_PCIE_LINK0_IRQ:
123 netlogic_write_reg(pcie_mmio_le, (0x90 >> 2), 0xffffffff);
124 break;
125 case PIC_PCIE_LINK1_IRQ:
126 netlogic_write_reg(pcie_mmio_le, (0x94 >> 2), 0xffffffff);
127 break;
128 case PIC_PCIE_XLSB0_LINK2_IRQ:
129 netlogic_write_reg(pcie_mmio_le, (0x190 >> 2), 0xffffffff);
130 break;
131 case PIC_PCIE_XLSB0_LINK3_IRQ:
132 netlogic_write_reg(pcie_mmio_le, (0x194 >> 2), 0xffffffff);
133 break;
134 }
135}
136#endif
137
138static void xlr_pic_ack(struct irq_data *d)
139{
140 unsigned long flags;
141 nlm_reg_t *mmio;
142 int irq = d->irq;
143 void *hd = irq_data_get_irq_handler_data(d);
144
145 WARN(!PIC_IRQ_IS_IRT(irq), "Bad irq %d", irq);
146
147 if (hd) {
148 void (*extra_ack)(void *) = hd;
149 extra_ack(d);
150 }
151 mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
152 spin_lock_irqsave(&nlm_pic_lock, flags);
153 netlogic_write_reg(mmio, PIC_INT_ACK, (1 << (irq - PIC_IRQ_BASE)));
154 spin_unlock_irqrestore(&nlm_pic_lock, flags);
155}
156
157/*
158 * This chip definition handles interrupts routed thru the XLR
159 * hardware PIC, currently IRQs 8-39 are mapped to hardware intr
160 * 0-31 wired the XLR PIC
161 */
162static struct irq_chip xlr_pic = {
163 .name = "XLR-PIC",
164 .irq_enable = xlr_pic_enable,
165 .irq_mask = xlr_pic_mask,
166 .irq_ack = xlr_pic_ack,
167};
168
169static void rsvd_irq_handler(struct irq_data *d)
170{
171 WARN(d->irq >= PIC_IRQ_BASE, "Bad irq %d", d->irq);
172}
173
174/*
175 * Chip definition for CPU originated interrupts(timer, msg) and
176 * IPIs
177 */
178struct irq_chip nlm_cpu_intr = {
179 .name = "XLR-CPU-INTR",
180 .irq_enable = rsvd_irq_handler,
181 .irq_mask = rsvd_irq_handler,
182 .irq_ack = rsvd_irq_handler,
183};
184
185void __init init_xlr_irqs(void)
186{
187 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
188 uint32_t thread_mask = 1;
189 int level, i;
190
191 pr_info("Interrupt thread mask [%x]\n", thread_mask);
192 for (i = 0; i < PIC_NUM_IRTS; i++) {
193 level = PIC_IRQ_IS_EDGE_TRIGGERED(i);
194
195 /* Bind all PIC irqs to boot cpu */
196 netlogic_write_reg(mmio, PIC_IRT_0_BASE + i, thread_mask);
197
198 /*
199 * Use local scheduling and high polarity for all IRTs
200 * Invalidate all IRTs, by default
201 */
202 netlogic_write_reg(mmio, PIC_IRT_1_BASE + i,
203 (level << 30) | (1 << 6) | (PIC_IRQ_BASE + i));
204 }
205
206 /* Make all IRQs as level triggered by default */
207 for (i = 0; i < NR_IRQS; i++) {
208 if (PIC_IRQ_IS_IRT(i))
209 irq_set_chip_and_handler(i, &xlr_pic, handle_level_irq);
210 else
211 irq_set_chip_and_handler(i, &nlm_cpu_intr,
212 handle_percpu_irq);
213 }
214#ifdef CONFIG_SMP
215 irq_set_chip_and_handler(IRQ_IPI_SMP_FUNCTION, &nlm_cpu_intr,
216 nlm_smp_function_ipi_handler);
217 irq_set_chip_and_handler(IRQ_IPI_SMP_RESCHEDULE, &nlm_cpu_intr,
218 nlm_smp_resched_ipi_handler);
219 nlm_irq_mask |=
220 ((1ULL << IRQ_IPI_SMP_FUNCTION) | (1ULL << IRQ_IPI_SMP_RESCHEDULE));
221#endif
222
223#ifdef CONFIG_PCI
224 /*
225 * For PCI interrupts, we need to ack the PIC controller too, overload
226 * irq handler data to do this
227 */
228 if (nlm_chip_is_xls()) {
229 if (nlm_chip_is_xls_b()) {
230 irq_set_handler_data(PIC_PCIE_LINK0_IRQ,
231 xls_pcie_ack_b);
232 irq_set_handler_data(PIC_PCIE_LINK1_IRQ,
233 xls_pcie_ack_b);
234 irq_set_handler_data(PIC_PCIE_XLSB0_LINK2_IRQ,
235 xls_pcie_ack_b);
236 irq_set_handler_data(PIC_PCIE_XLSB0_LINK3_IRQ,
237 xls_pcie_ack_b);
238 } else {
239 irq_set_handler_data(PIC_PCIE_LINK0_IRQ, xls_pcie_ack);
240 irq_set_handler_data(PIC_PCIE_LINK1_IRQ, xls_pcie_ack);
241 irq_set_handler_data(PIC_PCIE_LINK2_IRQ, xls_pcie_ack);
242 irq_set_handler_data(PIC_PCIE_LINK3_IRQ, xls_pcie_ack);
243 }
244 } else {
245 /* XLR PCI controller ACK */
246 irq_set_handler_data(PIC_PCIE_XLSB0_LINK3_IRQ, xlr_pci_ack);
247 }
248#endif
249 /* unmask all PIC related interrupts. If no handler is installed by the
250 * drivers, it'll just ack the interrupt and return
251 */
252 for (i = PIC_IRT_FIRST_IRQ; i <= PIC_IRT_LAST_IRQ; i++)
253 nlm_irq_mask |= (1ULL << i);
254
255 nlm_irq_mask |= (1ULL << IRQ_TIMER);
256}
257
258void __init arch_init_irq(void)
259{
260 /* Initialize the irq descriptors */
261 init_xlr_irqs();
262 write_c0_eimr(nlm_irq_mask);
263}
264
265void __cpuinit nlm_smp_irq_init(void)
266{
267 /* set interrupt mask for non-zero cpus */
268 write_c0_eimr(nlm_irq_mask);
269}
270
271asmlinkage void plat_irq_dispatch(void)
272{
273 uint64_t eirr;
274 int i;
275
276 eirr = read_c0_eirr() & read_c0_eimr();
277 if (!eirr)
278 return;
279
280 /* no need of EIRR here, writing compare clears interrupt */
281 if (eirr & (1 << IRQ_TIMER)) {
282 do_IRQ(IRQ_TIMER);
283 return;
284 }
285
286 /* use dcltz: optimize below code */
287 for (i = 63; i != -1; i--) {
288 if (eirr & (1ULL << i))
289 break;
290 }
291 if (i == -1) {
292 pr_err("no interrupt !!\n");
293 return;
294 }
295
296 /* Ack eirr */
297 write_c0_eirr(1ULL << i);
298
299 do_IRQ(i);
300}
diff --git a/arch/mips/netlogic/xlr/platform.c b/arch/mips/netlogic/xlr/platform.c
index 609ec2534642..eab64b45dffd 100644
--- a/arch/mips/netlogic/xlr/platform.c
+++ b/arch/mips/netlogic/xlr/platform.c
@@ -15,18 +15,19 @@
15#include <linux/serial_8250.h> 15#include <linux/serial_8250.h>
16#include <linux/serial_reg.h> 16#include <linux/serial_reg.h>
17 17
18#include <asm/netlogic/haldefs.h>
18#include <asm/netlogic/xlr/iomap.h> 19#include <asm/netlogic/xlr/iomap.h>
19#include <asm/netlogic/xlr/pic.h> 20#include <asm/netlogic/xlr/pic.h>
20#include <asm/netlogic/xlr/xlr.h> 21#include <asm/netlogic/xlr/xlr.h>
21 22
22unsigned int nlm_xlr_uart_in(struct uart_port *p, int offset) 23unsigned int nlm_xlr_uart_in(struct uart_port *p, int offset)
23{ 24{
24 nlm_reg_t *mmio; 25 uint64_t uartbase;
25 unsigned int value; 26 unsigned int value;
26 27
27 /* XLR uart does not need any mapping of regs */ 28 /* sign extend to 64 bits, if needed */
28 mmio = (nlm_reg_t *)(p->membase + (offset << p->regshift)); 29 uartbase = (uint64_t)(long)p->membase;
29 value = netlogic_read_reg(mmio, 0); 30 value = nlm_read_reg(uartbase, offset);
30 31
31 /* See XLR/XLS errata */ 32 /* See XLR/XLS errata */
32 if (offset == UART_MSR) 33 if (offset == UART_MSR)
@@ -39,10 +40,10 @@ unsigned int nlm_xlr_uart_in(struct uart_port *p, int offset)
39 40
40void nlm_xlr_uart_out(struct uart_port *p, int offset, int value) 41void nlm_xlr_uart_out(struct uart_port *p, int offset, int value)
41{ 42{
42 nlm_reg_t *mmio; 43 uint64_t uartbase;
43 44
44 /* XLR uart does not need any mapping of regs */ 45 /* sign extend to 64 bits, if needed */
45 mmio = (nlm_reg_t *)(p->membase + (offset << p->regshift)); 46 uartbase = (uint64_t)(long)p->membase;
46 47
47 /* See XLR/XLS errata */ 48 /* See XLR/XLS errata */
48 if (offset == UART_MSR) 49 if (offset == UART_MSR)
@@ -50,7 +51,7 @@ void nlm_xlr_uart_out(struct uart_port *p, int offset, int value)
50 else if (offset == UART_MCR) 51 else if (offset == UART_MCR)
51 value ^= 0x3; 52 value ^= 0x3;
52 53
53 netlogic_write_reg(mmio, 0, value); 54 nlm_write_reg(uartbase, offset, value);
54} 55}
55 56
56#define PORT(_irq) \ 57#define PORT(_irq) \
@@ -82,15 +83,15 @@ static struct platform_device uart_device = {
82 83
83static int __init nlm_uart_init(void) 84static int __init nlm_uart_init(void)
84{ 85{
85 nlm_reg_t *mmio; 86 unsigned long uartbase;
86 87
87 mmio = netlogic_io_mmio(NETLOGIC_IO_UART_0_OFFSET); 88 uartbase = (unsigned long)nlm_mmio_base(NETLOGIC_IO_UART_0_OFFSET);
88 xlr_uart_data[0].membase = (void __iomem *)mmio; 89 xlr_uart_data[0].membase = (void __iomem *)uartbase;
89 xlr_uart_data[0].mapbase = CPHYSADDR((unsigned long)mmio); 90 xlr_uart_data[0].mapbase = CPHYSADDR(uartbase);
90 91
91 mmio = netlogic_io_mmio(NETLOGIC_IO_UART_1_OFFSET); 92 uartbase = (unsigned long)nlm_mmio_base(NETLOGIC_IO_UART_1_OFFSET);
92 xlr_uart_data[1].membase = (void __iomem *)mmio; 93 xlr_uart_data[1].membase = (void __iomem *)uartbase;
93 xlr_uart_data[1].mapbase = CPHYSADDR((unsigned long)mmio); 94 xlr_uart_data[1].mapbase = CPHYSADDR(uartbase);
94 95
95 return platform_device_register(&uart_device); 96 return platform_device_register(&uart_device);
96} 97}
diff --git a/arch/mips/netlogic/xlr/setup.c b/arch/mips/netlogic/xlr/setup.c
index cee25ddd0887..c9d066dedc4e 100644
--- a/arch/mips/netlogic/xlr/setup.c
+++ b/arch/mips/netlogic/xlr/setup.c
@@ -39,26 +39,33 @@
39#include <asm/reboot.h> 39#include <asm/reboot.h>
40#include <asm/time.h> 40#include <asm/time.h>
41#include <asm/bootinfo.h> 41#include <asm/bootinfo.h>
42#include <asm/smp-ops.h>
43 42
44#include <asm/netlogic/interrupt.h> 43#include <asm/netlogic/interrupt.h>
45#include <asm/netlogic/psb-bootinfo.h> 44#include <asm/netlogic/psb-bootinfo.h>
45#include <asm/netlogic/haldefs.h>
46#include <asm/netlogic/common.h>
46 47
47#include <asm/netlogic/xlr/xlr.h> 48#include <asm/netlogic/xlr/xlr.h>
48#include <asm/netlogic/xlr/iomap.h> 49#include <asm/netlogic/xlr/iomap.h>
49#include <asm/netlogic/xlr/pic.h> 50#include <asm/netlogic/xlr/pic.h>
50#include <asm/netlogic/xlr/gpio.h> 51#include <asm/netlogic/xlr/gpio.h>
51 52
52unsigned long netlogic_io_base = (unsigned long)(DEFAULT_NETLOGIC_IO_BASE); 53uint64_t nlm_io_base = DEFAULT_NETLOGIC_IO_BASE;
53unsigned long nlm_common_ebase = 0x0; 54uint64_t nlm_pic_base;
54struct psb_info nlm_prom_info; 55struct psb_info nlm_prom_info;
55 56
57unsigned long nlm_common_ebase = 0x0;
58
59/* default to uniprocessor */
60uint32_t nlm_coremask = 1, nlm_cpumask = 1;
61int nlm_threads_per_core = 1;
62
56static void __init nlm_early_serial_setup(void) 63static void __init nlm_early_serial_setup(void)
57{ 64{
58 struct uart_port s; 65 struct uart_port s;
59 nlm_reg_t *uart_base; 66 unsigned long uart_base;
60 67
61 uart_base = netlogic_io_mmio(NETLOGIC_IO_UART_0_OFFSET); 68 uart_base = (unsigned long)nlm_mmio_base(NETLOGIC_IO_UART_0_OFFSET);
62 memset(&s, 0, sizeof(s)); 69 memset(&s, 0, sizeof(s));
63 s.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST; 70 s.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
64 s.iotype = UPIO_MEM32; 71 s.iotype = UPIO_MEM32;
@@ -67,18 +74,18 @@ static void __init nlm_early_serial_setup(void)
67 s.uartclk = PIC_CLKS_PER_SEC; 74 s.uartclk = PIC_CLKS_PER_SEC;
68 s.serial_in = nlm_xlr_uart_in; 75 s.serial_in = nlm_xlr_uart_in;
69 s.serial_out = nlm_xlr_uart_out; 76 s.serial_out = nlm_xlr_uart_out;
70 s.mapbase = (unsigned long)uart_base; 77 s.mapbase = uart_base;
71 s.membase = (unsigned char __iomem *)uart_base; 78 s.membase = (unsigned char __iomem *)uart_base;
72 early_serial_setup(&s); 79 early_serial_setup(&s);
73} 80}
74 81
75static void nlm_linux_exit(void) 82static void nlm_linux_exit(void)
76{ 83{
77 nlm_reg_t *mmio; 84 uint64_t gpiobase;
78 85
79 mmio = netlogic_io_mmio(NETLOGIC_IO_GPIO_OFFSET); 86 gpiobase = nlm_mmio_base(NETLOGIC_IO_GPIO_OFFSET);
80 /* trigger a chip reset by writing 1 to GPIO_SWRESET_REG */ 87 /* trigger a chip reset by writing 1 to GPIO_SWRESET_REG */
81 netlogic_write_reg(mmio, NETLOGIC_GPIO_SWRESET_REG, 1); 88 nlm_write_reg(gpiobase, NETLOGIC_GPIO_SWRESET_REG, 1);
82 for ( ; ; ) 89 for ( ; ; )
83 cpu_wait(); 90 cpu_wait();
84} 91}
@@ -96,6 +103,11 @@ const char *get_system_type(void)
96 return "Netlogic XLR/XLS Series"; 103 return "Netlogic XLR/XLS Series";
97} 104}
98 105
106unsigned int nlm_get_cpu_frequency(void)
107{
108 return (unsigned int)nlm_prom_info.cpu_frequency;
109}
110
99void __init prom_free_prom_memory(void) 111void __init prom_free_prom_memory(void)
100{ 112{
101 /* Nothing yet */ 113 /* Nothing yet */
@@ -175,6 +187,7 @@ void __init prom_init(void)
175 prom_infop = (struct psb_info *)(long)(int)fw_arg3; 187 prom_infop = (struct psb_info *)(long)(int)fw_arg3;
176 188
177 nlm_prom_info = *prom_infop; 189 nlm_prom_info = *prom_infop;
190 nlm_pic_base = nlm_mmio_base(NETLOGIC_IO_PIC_OFFSET);
178 191
179 nlm_early_serial_setup(); 192 nlm_early_serial_setup();
180 build_arcs_cmdline(argv); 193 build_arcs_cmdline(argv);
diff --git a/arch/mips/netlogic/xlr/smpboot.S b/arch/mips/netlogic/xlr/wakeup.c
index 8cb7889ce0cc..db5d987d4881 100644
--- a/arch/mips/netlogic/xlr/smpboot.S
+++ b/arch/mips/netlogic/xlr/wakeup.c
@@ -33,68 +33,36 @@
33 */ 33 */
34 34
35#include <linux/init.h> 35#include <linux/init.h>
36#include <linux/threads.h>
36 37
37#include <asm/asm.h> 38#include <asm/asm.h>
38#include <asm/asm-offsets.h> 39#include <asm/asm-offsets.h>
39#include <asm/regdef.h>
40#include <asm/mipsregs.h> 40#include <asm/mipsregs.h>
41#include <asm/addrspace.h>
42#include <asm/string.h>
41 43
42/* 44#include <asm/netlogic/haldefs.h>
43 * Early code for secondary CPUs. This will get them out of the bootloader 45#include <asm/netlogic/common.h>
44 * code and into linux. Needed because the bootloader area will be taken 46#include <asm/netlogic/mips-extns.h>
45 * and initialized by linux.
46 */
47 __CPUINIT
48NESTED(prom_pre_boot_secondary_cpus, 16, sp)
49 .set mips64
50 mfc0 t0, $15, 1 # read ebase
51 andi t0, 0x1f # t0 has the processor_id()
52 sll t0, 2 # offset in cpu array
53
54 PTR_LA t1, nlm_cpu_ready # mark CPU ready
55 PTR_ADDU t1, t0
56 li t2, 1
57 sw t2, 0(t1)
58
59 PTR_LA t1, nlm_cpu_unblock
60 PTR_ADDU t1, t0
611: lw t2, 0(t1) # wait till unblocked
62 beqz t2, 1b
63 nop
64 47
65 PTR_LA t1, nlm_next_sp 48#include <asm/netlogic/xlr/iomap.h>
66 PTR_L sp, 0(t1) 49#include <asm/netlogic/xlr/pic.h>
67 PTR_LA t1, nlm_next_gp
68 PTR_L gp, 0(t1)
69 50
70 PTR_LA t0, nlm_early_init_secondary 51int __cpuinit xlr_wakeup_secondary_cpus(void)
71 jalr t0 52{
72 nop 53 unsigned int i, boot_cpu;
73
74 PTR_LA t0, smp_bootstrap
75 jr t0
76 nop
77END(prom_pre_boot_secondary_cpus)
78 __FINIT
79
80/*
81 * NMI code, used for CPU wakeup, copied to reset entry
82 */
83NESTED(nlm_boot_smp_nmi, 0, sp)
84 .set push
85 .set noat
86 .set mips64
87 .set noreorder
88 54
89 /* Clear the NMI and BEV bits */ 55 /*
90 MFC0 k0, CP0_STATUS 56 * In case of RMI boot, hit with NMI to get the cores
91 li k1, 0xffb7ffff 57 * from bootloader to linux code.
92 and k0, k0, k1 58 */
93 MTC0 k0, CP0_STATUS 59 boot_cpu = hard_smp_processor_id();
60 nlm_set_nmi_handler(nlm_rmiboot_preboot);
61 for (i = 0; i < NR_CPUS; i++) {
62 if (i == boot_cpu || (nlm_cpumask & (1u << i)) == 0)
63 continue;
64 nlm_pic_send_ipi(nlm_pic_base, i, 1, 1); /* send NMI */
65 }
94 66
95 PTR_LA k1, secondary_entry_point 67 return 0;
96 PTR_L k0, 0(k1) 68}
97 jr k0
98 nop
99 .set pop
100END(nlm_boot_smp_nmi)
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index bb82cbdbc62a..c3ac4b086eb2 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o
19obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \ 19obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \
20 ops-bcm63xx.o 20 ops-bcm63xx.o
21obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o 21obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o
22obj-$(CONFIG_SOC_AR724X) += pci-ath724x.o
22 23
23# 24#
24# These are still pretty much in the old state, watch, go blind. 25# These are still pretty much in the old state, watch, go blind.
@@ -55,7 +56,7 @@ obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
55obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o 56obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
56obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o 57obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o
57obj-$(CONFIG_CPU_CAVIUM_OCTEON) += pci-octeon.o pcie-octeon.o 58obj-$(CONFIG_CPU_CAVIUM_OCTEON) += pci-octeon.o pcie-octeon.o
58obj-$(CONFIG_NLM_XLR) += pci-xlr.o 59obj-$(CONFIG_CPU_XLR) += pci-xlr.o
59 60
60ifdef CONFIG_PCI_MSI 61ifdef CONFIG_PCI_MSI
61obj-$(CONFIG_CPU_CAVIUM_OCTEON) += msi-octeon.o 62obj-$(CONFIG_CPU_CAVIUM_OCTEON) += msi-octeon.o
diff --git a/arch/mips/pci/msi-octeon.c b/arch/mips/pci/msi-octeon.c
index 5d530f89d872..d37be36dc659 100644
--- a/arch/mips/pci/msi-octeon.c
+++ b/arch/mips/pci/msi-octeon.c
@@ -162,7 +162,7 @@ msi_irq_allocated:
162 msg.address_hi = (0 + CVMX_NPEI_PCIE_MSI_RCV) >> 32; 162 msg.address_hi = (0 + CVMX_NPEI_PCIE_MSI_RCV) >> 32;
163 break; 163 break;
164 default: 164 default:
165 panic("arch_setup_msi_irq: Invalid octeon_dma_bar_type\n"); 165 panic("arch_setup_msi_irq: Invalid octeon_dma_bar_type");
166 } 166 }
167 msg.data = irq - OCTEON_IRQ_MSI_BIT0; 167 msg.data = irq - OCTEON_IRQ_MSI_BIT0;
168 168
diff --git a/arch/mips/pci/ops-pmcmsp.c b/arch/mips/pci/ops-pmcmsp.c
index 8fbfbf2b931c..389bf669d56e 100644
--- a/arch/mips/pci/ops-pmcmsp.c
+++ b/arch/mips/pci/ops-pmcmsp.c
@@ -405,7 +405,7 @@ int msp_pcibios_config_access(unsigned char access_type,
405 if (pciirqflag == 0) { 405 if (pciirqflag == 0) {
406 ret = request_irq(MSP_INT_PCI,/* Hardcoded internal MSP7120 wiring */ 406 ret = request_irq(MSP_INT_PCI,/* Hardcoded internal MSP7120 wiring */
407 bpci_interrupt, 407 bpci_interrupt,
408 IRQF_SHARED | IRQF_DISABLED, 408 IRQF_SHARED,
409 "PMC MSP PCI Host", 409 "PMC MSP PCI Host",
410 preg); 410 preg);
411 if (ret != 0) 411 if (ret != 0)
diff --git a/arch/mips/pci/ops-tx3927.c b/arch/mips/pci/ops-tx3927.c
index 6a3bdb5ffa80..02d64f77e967 100644
--- a/arch/mips/pci/ops-tx3927.c
+++ b/arch/mips/pci/ops-tx3927.c
@@ -225,7 +225,7 @@ void __init tx3927_setup_pcierr_irq(void)
225{ 225{
226 if (request_irq(TXX9_IRQ_BASE + TX3927_IR_PCI, 226 if (request_irq(TXX9_IRQ_BASE + TX3927_IR_PCI,
227 tx3927_pcierr_interrupt, 227 tx3927_pcierr_interrupt,
228 IRQF_DISABLED, "PCI error", 228 0, "PCI error",
229 (void *)TX3927_PCIC_REG)) 229 (void *)TX3927_PCIC_REG))
230 printk(KERN_WARNING "Failed to request irq for PCIERR\n"); 230 printk(KERN_WARNING "Failed to request irq for PCIERR\n");
231} 231}
diff --git a/arch/mips/pci/pci-alchemy.c b/arch/mips/pci/pci-alchemy.c
index b5ce041cdafb..ec125bed721c 100644
--- a/arch/mips/pci/pci-alchemy.c
+++ b/arch/mips/pci/pci-alchemy.c
@@ -13,9 +13,11 @@
13#include <linux/platform_device.h> 13#include <linux/platform_device.h>
14#include <linux/kernel.h> 14#include <linux/kernel.h>
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/syscore_ops.h>
16#include <linux/vmalloc.h> 17#include <linux/vmalloc.h>
17 18
18#include <asm/mach-au1x00/au1000.h> 19#include <asm/mach-au1x00/au1000.h>
20#include <asm/tlbmisc.h>
19 21
20#ifdef CONFIG_DEBUG_PCI 22#ifdef CONFIG_DEBUG_PCI
21#define DBG(x...) printk(KERN_DEBUG x) 23#define DBG(x...) printk(KERN_DEBUG x)
@@ -41,6 +43,12 @@ struct alchemy_pci_context {
41 int (*board_pci_idsel)(unsigned int devsel, int assert); 43 int (*board_pci_idsel)(unsigned int devsel, int assert);
42}; 44};
43 45
46/* for syscore_ops. There's only one PCI controller on Alchemy chips, so this
47 * should suffice for now.
48 */
49static struct alchemy_pci_context *__alchemy_pci_ctx;
50
51
44/* IO/MEM resources for PCI. Keep the memres in sync with __fixup_bigphys_addr 52/* IO/MEM resources for PCI. Keep the memres in sync with __fixup_bigphys_addr
45 * in arch/mips/alchemy/common/setup.c 53 * in arch/mips/alchemy/common/setup.c
46 */ 54 */
@@ -99,18 +107,6 @@ static int config_access(unsigned char access_type, struct pci_bus *bus,
99 return -1; 107 return -1;
100 } 108 }
101 109
102 /* YAMON on all db1xxx boards wipes the TLB and writes zero to C0_wired
103 * on resume, clearing our wired entry. Unfortunately the ->resume()
104 * callback is called way way way too late (and ->suspend() too early)
105 * to have them destroy and recreate it. Instead just test if c0_wired
106 * is now lower than the index we retrieved before suspending and then
107 * recreate the entry if necessary. Of course this is totally bonkers
108 * and breaks as soon as someone else adds another wired entry somewhere
109 * else. Anyone have any ideas how to handle this better?
110 */
111 if (unlikely(read_c0_wired() < ctx->wired_entry))
112 alchemy_pci_wired_entry(ctx);
113
114 local_irq_save(flags); 110 local_irq_save(flags);
115 r = __raw_readl(ctx->regs + PCI_REG_STATCMD) & 0x0000ffff; 111 r = __raw_readl(ctx->regs + PCI_REG_STATCMD) & 0x0000ffff;
116 r |= PCI_STATCMD_STATUS(0x2000); 112 r |= PCI_STATCMD_STATUS(0x2000);
@@ -304,6 +300,62 @@ static int alchemy_pci_def_idsel(unsigned int devsel, int assert)
304 return 1; /* success */ 300 return 1; /* success */
305} 301}
306 302
303/* save PCI controller register contents. */
304static int alchemy_pci_suspend(void)
305{
306 struct alchemy_pci_context *ctx = __alchemy_pci_ctx;
307 if (!ctx)
308 return 0;
309
310 ctx->pm[0] = __raw_readl(ctx->regs + PCI_REG_CMEM);
311 ctx->pm[1] = __raw_readl(ctx->regs + PCI_REG_CONFIG) & 0x0009ffff;
312 ctx->pm[2] = __raw_readl(ctx->regs + PCI_REG_B2BMASK_CCH);
313 ctx->pm[3] = __raw_readl(ctx->regs + PCI_REG_B2BBASE0_VID);
314 ctx->pm[4] = __raw_readl(ctx->regs + PCI_REG_B2BBASE1_SID);
315 ctx->pm[5] = __raw_readl(ctx->regs + PCI_REG_MWMASK_DEV);
316 ctx->pm[6] = __raw_readl(ctx->regs + PCI_REG_MWBASE_REV_CCL);
317 ctx->pm[7] = __raw_readl(ctx->regs + PCI_REG_ID);
318 ctx->pm[8] = __raw_readl(ctx->regs + PCI_REG_CLASSREV);
319 ctx->pm[9] = __raw_readl(ctx->regs + PCI_REG_PARAM);
320 ctx->pm[10] = __raw_readl(ctx->regs + PCI_REG_MBAR);
321 ctx->pm[11] = __raw_readl(ctx->regs + PCI_REG_TIMEOUT);
322
323 return 0;
324}
325
326static void alchemy_pci_resume(void)
327{
328 struct alchemy_pci_context *ctx = __alchemy_pci_ctx;
329 if (!ctx)
330 return;
331
332 __raw_writel(ctx->pm[0], ctx->regs + PCI_REG_CMEM);
333 __raw_writel(ctx->pm[2], ctx->regs + PCI_REG_B2BMASK_CCH);
334 __raw_writel(ctx->pm[3], ctx->regs + PCI_REG_B2BBASE0_VID);
335 __raw_writel(ctx->pm[4], ctx->regs + PCI_REG_B2BBASE1_SID);
336 __raw_writel(ctx->pm[5], ctx->regs + PCI_REG_MWMASK_DEV);
337 __raw_writel(ctx->pm[6], ctx->regs + PCI_REG_MWBASE_REV_CCL);
338 __raw_writel(ctx->pm[7], ctx->regs + PCI_REG_ID);
339 __raw_writel(ctx->pm[8], ctx->regs + PCI_REG_CLASSREV);
340 __raw_writel(ctx->pm[9], ctx->regs + PCI_REG_PARAM);
341 __raw_writel(ctx->pm[10], ctx->regs + PCI_REG_MBAR);
342 __raw_writel(ctx->pm[11], ctx->regs + PCI_REG_TIMEOUT);
343 wmb();
344 __raw_writel(ctx->pm[1], ctx->regs + PCI_REG_CONFIG);
345 wmb();
346
347 /* YAMON on all db1xxx boards wipes the TLB and writes zero to C0_wired
348 * on resume, making it necessary to recreate it as soon as possible.
349 */
350 ctx->wired_entry = 8191; /* impossibly high value */
351 alchemy_pci_wired_entry(ctx); /* install it */
352}
353
354static struct syscore_ops alchemy_pci_pmops = {
355 .suspend = alchemy_pci_suspend,
356 .resume = alchemy_pci_resume,
357};
358
307static int __devinit alchemy_pci_probe(struct platform_device *pdev) 359static int __devinit alchemy_pci_probe(struct platform_device *pdev)
308{ 360{
309 struct alchemy_pci_platdata *pd = pdev->dev.platform_data; 361 struct alchemy_pci_platdata *pd = pdev->dev.platform_data;
@@ -396,7 +448,8 @@ static int __devinit alchemy_pci_probe(struct platform_device *pdev)
396 ret = -ENOMEM; 448 ret = -ENOMEM;
397 goto out4; 449 goto out4;
398 } 450 }
399 ctx->wired_entry = 8192; /* impossibly high value */ 451 ctx->wired_entry = 8191; /* impossibly high value */
452 alchemy_pci_wired_entry(ctx); /* install it */
400 453
401 set_io_port_base((unsigned long)ctx->alchemy_pci_ctrl.io_map_base); 454 set_io_port_base((unsigned long)ctx->alchemy_pci_ctrl.io_map_base);
402 455
@@ -408,7 +461,9 @@ static int __devinit alchemy_pci_probe(struct platform_device *pdev)
408 __raw_writel(val, ctx->regs + PCI_REG_CONFIG); 461 __raw_writel(val, ctx->regs + PCI_REG_CONFIG);
409 wmb(); 462 wmb();
410 463
464 __alchemy_pci_ctx = ctx;
411 platform_set_drvdata(pdev, ctx); 465 platform_set_drvdata(pdev, ctx);
466 register_syscore_ops(&alchemy_pci_pmops);
412 register_pci_controller(&ctx->alchemy_pci_ctrl); 467 register_pci_controller(&ctx->alchemy_pci_ctrl);
413 468
414 return 0; 469 return 0;
@@ -425,68 +480,11 @@ out:
425 return ret; 480 return ret;
426} 481}
427 482
428
429#ifdef CONFIG_PM
430/* save PCI controller register contents. */
431static int alchemy_pci_suspend(struct device *dev)
432{
433 struct alchemy_pci_context *ctx = dev_get_drvdata(dev);
434
435 ctx->pm[0] = __raw_readl(ctx->regs + PCI_REG_CMEM);
436 ctx->pm[1] = __raw_readl(ctx->regs + PCI_REG_CONFIG) & 0x0009ffff;
437 ctx->pm[2] = __raw_readl(ctx->regs + PCI_REG_B2BMASK_CCH);
438 ctx->pm[3] = __raw_readl(ctx->regs + PCI_REG_B2BBASE0_VID);
439 ctx->pm[4] = __raw_readl(ctx->regs + PCI_REG_B2BBASE1_SID);
440 ctx->pm[5] = __raw_readl(ctx->regs + PCI_REG_MWMASK_DEV);
441 ctx->pm[6] = __raw_readl(ctx->regs + PCI_REG_MWBASE_REV_CCL);
442 ctx->pm[7] = __raw_readl(ctx->regs + PCI_REG_ID);
443 ctx->pm[8] = __raw_readl(ctx->regs + PCI_REG_CLASSREV);
444 ctx->pm[9] = __raw_readl(ctx->regs + PCI_REG_PARAM);
445 ctx->pm[10] = __raw_readl(ctx->regs + PCI_REG_MBAR);
446 ctx->pm[11] = __raw_readl(ctx->regs + PCI_REG_TIMEOUT);
447
448 return 0;
449}
450
451static int alchemy_pci_resume(struct device *dev)
452{
453 struct alchemy_pci_context *ctx = dev_get_drvdata(dev);
454
455 __raw_writel(ctx->pm[0], ctx->regs + PCI_REG_CMEM);
456 __raw_writel(ctx->pm[2], ctx->regs + PCI_REG_B2BMASK_CCH);
457 __raw_writel(ctx->pm[3], ctx->regs + PCI_REG_B2BBASE0_VID);
458 __raw_writel(ctx->pm[4], ctx->regs + PCI_REG_B2BBASE1_SID);
459 __raw_writel(ctx->pm[5], ctx->regs + PCI_REG_MWMASK_DEV);
460 __raw_writel(ctx->pm[6], ctx->regs + PCI_REG_MWBASE_REV_CCL);
461 __raw_writel(ctx->pm[7], ctx->regs + PCI_REG_ID);
462 __raw_writel(ctx->pm[8], ctx->regs + PCI_REG_CLASSREV);
463 __raw_writel(ctx->pm[9], ctx->regs + PCI_REG_PARAM);
464 __raw_writel(ctx->pm[10], ctx->regs + PCI_REG_MBAR);
465 __raw_writel(ctx->pm[11], ctx->regs + PCI_REG_TIMEOUT);
466 wmb();
467 __raw_writel(ctx->pm[1], ctx->regs + PCI_REG_CONFIG);
468 wmb();
469
470 return 0;
471}
472
473static const struct dev_pm_ops alchemy_pci_pmops = {
474 .suspend = alchemy_pci_suspend,
475 .resume = alchemy_pci_resume,
476};
477
478#define ALCHEMY_PCICTL_PM (&alchemy_pci_pmops)
479
480#else
481#define ALCHEMY_PCICTL_PM NULL
482#endif
483
484static struct platform_driver alchemy_pcictl_driver = { 483static struct platform_driver alchemy_pcictl_driver = {
485 .probe = alchemy_pci_probe, 484 .probe = alchemy_pci_probe,
486 .driver = { 485 .driver = {
487 .name = "alchemy-pci", 486 .name = "alchemy-pci",
488 .owner = THIS_MODULE, 487 .owner = THIS_MODULE,
489 .pm = ALCHEMY_PCICTL_PM,
490 }, 488 },
491}; 489};
492 490
diff --git a/arch/mips/pci/pci-ath724x.c b/arch/mips/pci/pci-ath724x.c
new file mode 100644
index 000000000000..a4dd24a4130b
--- /dev/null
+++ b/arch/mips/pci/pci-ath724x.c
@@ -0,0 +1,174 @@
1/*
2 * Atheros 724x PCI support
3 *
4 * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 */
10
11#include <linux/pci.h>
12#include <asm/mach-ath79/pci-ath724x.h>
13
14#define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys))
15#define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val))
16
17#define ATH724X_PCI_DEV_BASE 0x14000000
18#define ATH724X_PCI_MEM_BASE 0x10000000
19#define ATH724X_PCI_MEM_SIZE 0x08000000
20
21static DEFINE_SPINLOCK(ath724x_pci_lock);
22static struct ath724x_pci_data *pci_data;
23static int pci_data_size;
24
25static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
26 int size, uint32_t *value)
27{
28 unsigned long flags, addr, tval, mask;
29
30 if (devfn)
31 return PCIBIOS_DEVICE_NOT_FOUND;
32
33 if (where & (size - 1))
34 return PCIBIOS_BAD_REGISTER_NUMBER;
35
36 spin_lock_irqsave(&ath724x_pci_lock, flags);
37
38 switch (size) {
39 case 1:
40 addr = where & ~3;
41 mask = 0xff000000 >> ((where % 4) * 8);
42 tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
43 tval = tval & ~mask;
44 *value = (tval >> ((4 - (where % 4))*8));
45 break;
46 case 2:
47 addr = where & ~3;
48 mask = 0xffff0000 >> ((where % 4)*8);
49 tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
50 tval = tval & ~mask;
51 *value = (tval >> ((4 - (where % 4))*8));
52 break;
53 case 4:
54 *value = reg_read(ATH724X_PCI_DEV_BASE + where);
55 break;
56 default:
57 spin_unlock_irqrestore(&ath724x_pci_lock, flags);
58
59 return PCIBIOS_BAD_REGISTER_NUMBER;
60 }
61
62 spin_unlock_irqrestore(&ath724x_pci_lock, flags);
63
64 return PCIBIOS_SUCCESSFUL;
65}
66
67static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
68 int size, uint32_t value)
69{
70 unsigned long flags, tval, addr, mask;
71
72 if (devfn)
73 return PCIBIOS_DEVICE_NOT_FOUND;
74
75 if (where & (size - 1))
76 return PCIBIOS_BAD_REGISTER_NUMBER;
77
78 spin_lock_irqsave(&ath724x_pci_lock, flags);
79
80 switch (size) {
81 case 1:
82 addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
83 mask = 0xff000000 >> ((where % 4)*8);
84 tval = reg_read(addr);
85 tval = tval & ~mask;
86 tval |= (value << ((4 - (where % 4))*8)) & mask;
87 reg_write(addr, tval);
88 break;
89 case 2:
90 addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
91 mask = 0xffff0000 >> ((where % 4)*8);
92 tval = reg_read(addr);
93 tval = tval & ~mask;
94 tval |= (value << ((4 - (where % 4))*8)) & mask;
95 reg_write(addr, tval);
96 break;
97 case 4:
98 reg_write((ATH724X_PCI_DEV_BASE + where), value);
99 break;
100 default:
101 spin_unlock_irqrestore(&ath724x_pci_lock, flags);
102
103 return PCIBIOS_BAD_REGISTER_NUMBER;
104 }
105
106 spin_unlock_irqrestore(&ath724x_pci_lock, flags);
107
108 return PCIBIOS_SUCCESSFUL;
109}
110
111static struct pci_ops ath724x_pci_ops = {
112 .read = ath724x_pci_read,
113 .write = ath724x_pci_write,
114};
115
116static struct resource ath724x_io_resource = {
117 .name = "PCI IO space",
118 .start = 0,
119 .end = 0,
120 .flags = IORESOURCE_IO,
121};
122
123static struct resource ath724x_mem_resource = {
124 .name = "PCI memory space",
125 .start = ATH724X_PCI_MEM_BASE,
126 .end = ATH724X_PCI_MEM_BASE + ATH724X_PCI_MEM_SIZE - 1,
127 .flags = IORESOURCE_MEM,
128};
129
130static struct pci_controller ath724x_pci_controller = {
131 .pci_ops = &ath724x_pci_ops,
132 .io_resource = &ath724x_io_resource,
133 .mem_resource = &ath724x_mem_resource,
134};
135
136void ath724x_pci_add_data(struct ath724x_pci_data *data, int size)
137{
138 pci_data = data;
139 pci_data_size = size;
140}
141
142int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
143{
144 unsigned int devfn = dev->devfn;
145 int irq = -1;
146
147 if (devfn > pci_data_size - 1)
148 return irq;
149
150 irq = pci_data[devfn].irq;
151
152 return irq;
153}
154
155int pcibios_plat_dev_init(struct pci_dev *dev)
156{
157 unsigned int devfn = dev->devfn;
158
159 if (devfn > pci_data_size - 1)
160 return PCIBIOS_DEVICE_NOT_FOUND;
161
162 dev->dev.platform_data = pci_data[devfn].pdata;
163
164 return PCIBIOS_SUCCESSFUL;
165}
166
167static int __init ath724x_pcibios_init(void)
168{
169 register_pci_controller(&ath724x_pci_controller);
170
171 return PCIBIOS_SUCCESSFUL;
172}
173
174arch_initcall(ath724x_pcibios_init);
diff --git a/arch/mips/pci/pci-bcm63xx.c b/arch/mips/pci/pci-bcm63xx.c
index 82e0fde1dba0..39eb7c417e2f 100644
--- a/arch/mips/pci/pci-bcm63xx.c
+++ b/arch/mips/pci/pci-bcm63xx.c
@@ -99,7 +99,7 @@ static int __init bcm63xx_pci_init(void)
99 unsigned int mem_size; 99 unsigned int mem_size;
100 u32 val; 100 u32 val;
101 101
102 if (!BCMCPU_IS_6348() && !BCMCPU_IS_6358()) 102 if (!BCMCPU_IS_6348() && !BCMCPU_IS_6358() && !BCMCPU_IS_6368())
103 return -ENODEV; 103 return -ENODEV;
104 104
105 if (!bcm63xx_pci_enabled) 105 if (!bcm63xx_pci_enabled)
@@ -159,7 +159,7 @@ static int __init bcm63xx_pci_init(void)
159 /* setup PCI to local bus access, used by PCI device to target 159 /* setup PCI to local bus access, used by PCI device to target
160 * local RAM while bus mastering */ 160 * local RAM while bus mastering */
161 bcm63xx_int_cfg_writel(0, PCI_BASE_ADDRESS_3); 161 bcm63xx_int_cfg_writel(0, PCI_BASE_ADDRESS_3);
162 if (BCMCPU_IS_6358()) 162 if (BCMCPU_IS_6358() || BCMCPU_IS_6368())
163 val = MPI_SP0_REMAP_ENABLE_MASK; 163 val = MPI_SP0_REMAP_ENABLE_MASK;
164 else 164 else
165 val = 0; 165 val = 0;
diff --git a/arch/mips/pci/pci-tx4927.c b/arch/mips/pci/pci-tx4927.c
index a5807406a7f1..a032ae0a533d 100644
--- a/arch/mips/pci/pci-tx4927.c
+++ b/arch/mips/pci/pci-tx4927.c
@@ -85,7 +85,7 @@ void __init tx4927_setup_pcierr_irq(void)
85{ 85{
86 if (request_irq(TXX9_IRQ_BASE + TX4927_IR_PCIERR, 86 if (request_irq(TXX9_IRQ_BASE + TX4927_IR_PCIERR,
87 tx4927_pcierr_interrupt, 87 tx4927_pcierr_interrupt,
88 IRQF_DISABLED, "PCI error", 88 0, "PCI error",
89 (void *)TX4927_PCIC_REG)) 89 (void *)TX4927_PCIC_REG))
90 printk(KERN_WARNING "Failed to request irq for PCIERR\n"); 90 printk(KERN_WARNING "Failed to request irq for PCIERR\n");
91} 91}
diff --git a/arch/mips/pci/pci-tx4938.c b/arch/mips/pci/pci-tx4938.c
index 20e45f30b2ef..141bba562488 100644
--- a/arch/mips/pci/pci-tx4938.c
+++ b/arch/mips/pci/pci-tx4938.c
@@ -136,7 +136,7 @@ void __init tx4938_setup_pcierr_irq(void)
136{ 136{
137 if (request_irq(TXX9_IRQ_BASE + TX4938_IR_PCIERR, 137 if (request_irq(TXX9_IRQ_BASE + TX4938_IR_PCIERR,
138 tx4927_pcierr_interrupt, 138 tx4927_pcierr_interrupt,
139 IRQF_DISABLED, "PCI error", 139 0, "PCI error",
140 (void *)TX4927_PCIC_REG)) 140 (void *)TX4927_PCIC_REG))
141 printk(KERN_WARNING "Failed to request irq for PCIERR\n"); 141 printk(KERN_WARNING "Failed to request irq for PCIERR\n");
142} 142}
diff --git a/arch/mips/pci/pci-tx4939.c b/arch/mips/pci/pci-tx4939.c
index 9ef840693baf..c10fbf2a19dc 100644
--- a/arch/mips/pci/pci-tx4939.c
+++ b/arch/mips/pci/pci-tx4939.c
@@ -101,7 +101,7 @@ void __init tx4939_setup_pcierr_irq(void)
101{ 101{
102 if (request_irq(TXX9_IRQ_BASE + TX4939_IR_PCIERR, 102 if (request_irq(TXX9_IRQ_BASE + TX4939_IR_PCIERR,
103 tx4927_pcierr_interrupt, 103 tx4927_pcierr_interrupt,
104 IRQF_DISABLED, "PCI error", 104 0, "PCI error",
105 (void *)TX4939_PCIC_REG)) 105 (void *)TX4939_PCIC_REG))
106 pr_warning("Failed to request irq for PCIERR\n"); 106 pr_warning("Failed to request irq for PCIERR\n");
107} 107}
diff --git a/arch/mips/pci/pci-xlr.c b/arch/mips/pci/pci-xlr.c
index 38fece16c435..3d701a962ef4 100644
--- a/arch/mips/pci/pci-xlr.c
+++ b/arch/mips/pci/pci-xlr.c
@@ -36,12 +36,18 @@
36#include <linux/pci.h> 36#include <linux/pci.h>
37#include <linux/kernel.h> 37#include <linux/kernel.h>
38#include <linux/init.h> 38#include <linux/init.h>
39#include <linux/msi.h>
39#include <linux/mm.h> 40#include <linux/mm.h>
41#include <linux/irq.h>
42#include <linux/irqdesc.h>
40#include <linux/console.h> 43#include <linux/console.h>
41 44
42#include <asm/io.h> 45#include <asm/io.h>
43 46
44#include <asm/netlogic/interrupt.h> 47#include <asm/netlogic/interrupt.h>
48#include <asm/netlogic/haldefs.h>
49
50#include <asm/netlogic/xlr/msidef.h>
45#include <asm/netlogic/xlr/iomap.h> 51#include <asm/netlogic/xlr/iomap.h>
46#include <asm/netlogic/xlr/pic.h> 52#include <asm/netlogic/xlr/pic.h>
47#include <asm/netlogic/xlr/xlr.h> 53#include <asm/netlogic/xlr/xlr.h>
@@ -150,7 +156,7 @@ struct pci_controller nlm_pci_controller = {
150 .io_offset = 0x00000000UL, 156 .io_offset = 0x00000000UL,
151}; 157};
152 158
153int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 159static int get_irq_vector(const struct pci_dev *dev)
154{ 160{
155 if (!nlm_chip_is_xls()) 161 if (!nlm_chip_is_xls())
156 return PIC_PCIX_IRQ; /* for XLR just one IRQ*/ 162 return PIC_PCIX_IRQ; /* for XLR just one IRQ*/
@@ -182,6 +188,101 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
182 return 0; 188 return 0;
183} 189}
184 190
191#ifdef CONFIG_PCI_MSI
192void destroy_irq(unsigned int irq)
193{
194 /* nothing to do yet */
195}
196
197void arch_teardown_msi_irq(unsigned int irq)
198{
199 destroy_irq(irq);
200}
201
202int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
203{
204 struct msi_msg msg;
205 int irq, ret;
206
207 irq = get_irq_vector(dev);
208 if (irq <= 0)
209 return 1;
210
211 msg.address_hi = MSI_ADDR_BASE_HI;
212 msg.address_lo = MSI_ADDR_BASE_LO |
213 MSI_ADDR_DEST_MODE_PHYSICAL |
214 MSI_ADDR_REDIRECTION_CPU;
215
216 msg.data = MSI_DATA_TRIGGER_EDGE |
217 MSI_DATA_LEVEL_ASSERT |
218 MSI_DATA_DELIVERY_FIXED;
219
220 ret = irq_set_msi_desc(irq, desc);
221 if (ret < 0) {
222 destroy_irq(irq);
223 return ret;
224 }
225
226 write_msi_msg(irq, &msg);
227 return 0;
228}
229#endif
230
231/* Extra ACK needed for XLR on chip PCI controller */
232static void xlr_pci_ack(struct irq_data *d)
233{
234 uint64_t pcibase = nlm_mmio_base(NETLOGIC_IO_PCIX_OFFSET);
235
236 nlm_read_reg(pcibase, (0x140 >> 2));
237}
238
239/* Extra ACK needed for XLS on chip PCIe controller */
240static void xls_pcie_ack(struct irq_data *d)
241{
242 uint64_t pciebase_le = nlm_mmio_base(NETLOGIC_IO_PCIE_1_OFFSET);
243
244 switch (d->irq) {
245 case PIC_PCIE_LINK0_IRQ:
246 nlm_write_reg(pciebase_le, (0x90 >> 2), 0xffffffff);
247 break;
248 case PIC_PCIE_LINK1_IRQ:
249 nlm_write_reg(pciebase_le, (0x94 >> 2), 0xffffffff);
250 break;
251 case PIC_PCIE_LINK2_IRQ:
252 nlm_write_reg(pciebase_le, (0x190 >> 2), 0xffffffff);
253 break;
254 case PIC_PCIE_LINK3_IRQ:
255 nlm_write_reg(pciebase_le, (0x194 >> 2), 0xffffffff);
256 break;
257 }
258}
259
260/* For XLS B silicon, the 3,4 PCI interrupts are different */
261static void xls_pcie_ack_b(struct irq_data *d)
262{
263 uint64_t pciebase_le = nlm_mmio_base(NETLOGIC_IO_PCIE_1_OFFSET);
264
265 switch (d->irq) {
266 case PIC_PCIE_LINK0_IRQ:
267 nlm_write_reg(pciebase_le, (0x90 >> 2), 0xffffffff);
268 break;
269 case PIC_PCIE_LINK1_IRQ:
270 nlm_write_reg(pciebase_le, (0x94 >> 2), 0xffffffff);
271 break;
272 case PIC_PCIE_XLSB0_LINK2_IRQ:
273 nlm_write_reg(pciebase_le, (0x190 >> 2), 0xffffffff);
274 break;
275 case PIC_PCIE_XLSB0_LINK3_IRQ:
276 nlm_write_reg(pciebase_le, (0x194 >> 2), 0xffffffff);
277 break;
278 }
279}
280
281int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
282{
283 return get_irq_vector(dev);
284}
285
185/* Do platform specific device initialization at pci_enable_device() time */ 286/* Do platform specific device initialization at pci_enable_device() time */
186int pcibios_plat_dev_init(struct pci_dev *dev) 287int pcibios_plat_dev_init(struct pci_dev *dev)
187{ 288{
@@ -204,6 +305,31 @@ static int __init pcibios_init(void)
204 pr_info("Registering XLR/XLS PCIX/PCIE Controller.\n"); 305 pr_info("Registering XLR/XLS PCIX/PCIE Controller.\n");
205 register_pci_controller(&nlm_pci_controller); 306 register_pci_controller(&nlm_pci_controller);
206 307
308 /*
309 * For PCI interrupts, we need to ack the PCI controller too, overload
310 * irq handler data to do this
311 */
312 if (nlm_chip_is_xls()) {
313 if (nlm_chip_is_xls_b()) {
314 irq_set_handler_data(PIC_PCIE_LINK0_IRQ,
315 xls_pcie_ack_b);
316 irq_set_handler_data(PIC_PCIE_LINK1_IRQ,
317 xls_pcie_ack_b);
318 irq_set_handler_data(PIC_PCIE_XLSB0_LINK2_IRQ,
319 xls_pcie_ack_b);
320 irq_set_handler_data(PIC_PCIE_XLSB0_LINK3_IRQ,
321 xls_pcie_ack_b);
322 } else {
323 irq_set_handler_data(PIC_PCIE_LINK0_IRQ, xls_pcie_ack);
324 irq_set_handler_data(PIC_PCIE_LINK1_IRQ, xls_pcie_ack);
325 irq_set_handler_data(PIC_PCIE_LINK2_IRQ, xls_pcie_ack);
326 irq_set_handler_data(PIC_PCIE_LINK3_IRQ, xls_pcie_ack);
327 }
328 } else {
329 /* XLR PCI controller ACK */
330 irq_set_handler_data(PIC_PCIE_XLSB0_LINK3_IRQ, xlr_pci_ack);
331 }
332
207 return 0; 333 return 0;
208} 334}
209 335
diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index 41af7fa2887b..8ac0d4841852 100644
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -4,8 +4,11 @@
4 * Free Software Foundation; either version 2 of the License, or (at your 4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version. 5 * option) any later version.
6 * 6 *
7 * Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org) 7 * Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org)
8 * Copyright (C) 2011 Wind River Systems,
9 * written by Ralf Baechle (ralf@linux-mips.org)
8 */ 10 */
11#include <linux/bug.h>
9#include <linux/kernel.h> 12#include <linux/kernel.h>
10#include <linux/mm.h> 13#include <linux/mm.h>
11#include <linux/bootmem.h> 14#include <linux/bootmem.h>
@@ -14,6 +17,8 @@
14#include <linux/types.h> 17#include <linux/types.h>
15#include <linux/pci.h> 18#include <linux/pci.h>
16 19
20#include <asm/cpu-info.h>
21
17/* 22/*
18 * Indicate whether we respect the PCI setup left by the firmware. 23 * Indicate whether we respect the PCI setup left by the firmware.
19 * 24 *
@@ -150,10 +155,32 @@ out:
150 "Skipping PCI bus scan due to resource conflict\n"); 155 "Skipping PCI bus scan due to resource conflict\n");
151} 156}
152 157
158static void __init pcibios_set_cache_line_size(void)
159{
160 struct cpuinfo_mips *c = &current_cpu_data;
161 unsigned int lsize;
162
163 /*
164 * Set PCI cacheline size to that of the highest level in the
165 * cache hierarchy.
166 */
167 lsize = c->dcache.linesz;
168 lsize = c->scache.linesz ? : lsize;
169 lsize = c->tcache.linesz ? : lsize;
170
171 BUG_ON(!lsize);
172
173 pci_dfl_cache_line_size = lsize >> 2;
174
175 pr_debug("PCI: pci_cache_line_size set to %d bytes\n", lsize);
176}
177
153static int __init pcibios_init(void) 178static int __init pcibios_init(void)
154{ 179{
155 struct pci_controller *hose; 180 struct pci_controller *hose;
156 181
182 pcibios_set_cache_line_size();
183
157 /* Scan all of the recorded PCI controllers. */ 184 /* Scan all of the recorded PCI controllers. */
158 for (hose = hose_head; hose; hose = hose->next) 185 for (hose = hose_head; hose; hose = hose->next)
159 pcibios_scanbus(hose); 186 pcibios_scanbus(hose);
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c b/arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c
index c841f083a7f5..bb57ed9ea2bd 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c
@@ -149,7 +149,7 @@ static int msp_hwbutton_register(struct hwbutton_interrupt *hirq)
149 CIC_EXT_SET_ACTIVE_HI(cic_ext, hirq->eirq); 149 CIC_EXT_SET_ACTIVE_HI(cic_ext, hirq->eirq);
150 *CIC_EXT_CFG_REG = cic_ext; 150 *CIC_EXT_CFG_REG = cic_ext;
151 151
152 return request_irq(hirq->irq, hwbutton_handler, IRQF_DISABLED, 152 return request_irq(hirq->irq, hwbutton_handler, 0,
153 hirq->name, hirq); 153 hirq->name, hirq);
154} 154}
155 155
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_setup.c b/arch/mips/pmc-sierra/msp71xx/msp_setup.c
index 655308a4e1cd..7a834b2f8a5f 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_setup.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_setup.c
@@ -209,7 +209,7 @@ void __init prom_init(void)
209 default: 209 default:
210 /* we don't recognize the machine */ 210 /* we don't recognize the machine */
211 mips_machtype = MACH_UNKNOWN; 211 mips_machtype = MACH_UNKNOWN;
212 panic("***Bogosity factor five***, exiting\n"); 212 panic("***Bogosity factor five***, exiting");
213 break; 213 break;
214 } 214 }
215 215
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_smp.c b/arch/mips/pmc-sierra/msp71xx/msp_smp.c
index bec17901ff03..10170580a2de 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_smp.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_smp.c
@@ -51,13 +51,13 @@ static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
51 51
52static struct irqaction irq_resched = { 52static struct irqaction irq_resched = {
53 .handler = ipi_resched_interrupt, 53 .handler = ipi_resched_interrupt,
54 .flags = IRQF_DISABLED | IRQF_PERCPU, 54 .flags = IRQF_PERCPU,
55 .name = "IPI_resched" 55 .name = "IPI_resched"
56}; 56};
57 57
58static struct irqaction irq_call = { 58static struct irqaction irq_call = {
59 .handler = ipi_call_interrupt, 59 .handler = ipi_call_interrupt,
60 .flags = IRQF_DISABLED | IRQF_PERCPU, 60 .flags = IRQF_PERCPU,
61 .name = "IPI_call" 61 .name = "IPI_call"
62}; 62};
63 63
diff --git a/arch/mips/pnx8550/common/int.c b/arch/mips/pnx8550/common/int.c
index 1ebe22bdadc8..ec684b8c3f79 100644
--- a/arch/mips/pnx8550/common/int.c
+++ b/arch/mips/pnx8550/common/int.c
@@ -167,13 +167,13 @@ static struct irq_chip level_irq_type = {
167 167
168static struct irqaction gic_action = { 168static struct irqaction gic_action = {
169 .handler = no_action, 169 .handler = no_action,
170 .flags = IRQF_DISABLED | IRQF_NO_THREAD, 170 .flags = IRQF_NO_THREAD,
171 .name = "GIC", 171 .name = "GIC",
172}; 172};
173 173
174static struct irqaction timer_action = { 174static struct irqaction timer_action = {
175 .handler = no_action, 175 .handler = no_action,
176 .flags = IRQF_DISABLED | IRQF_TIMER, 176 .flags = IRQF_TIMER,
177 .name = "Timer", 177 .name = "Timer",
178}; 178};
179 179
diff --git a/arch/mips/pnx8550/common/time.c b/arch/mips/pnx8550/common/time.c
index 8836c6203df0..831d6b369e9c 100644
--- a/arch/mips/pnx8550/common/time.c
+++ b/arch/mips/pnx8550/common/time.c
@@ -59,7 +59,7 @@ static irqreturn_t pnx8xxx_timer_interrupt(int irq, void *dev_id)
59 59
60static struct irqaction pnx8xxx_timer_irq = { 60static struct irqaction pnx8xxx_timer_irq = {
61 .handler = pnx8xxx_timer_interrupt, 61 .handler = pnx8xxx_timer_interrupt,
62 .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER, 62 .flags = IRQF_PERCPU | IRQF_TIMER,
63 .name = "pnx8xxx_timer", 63 .name = "pnx8xxx_timer",
64}; 64};
65 65
@@ -72,7 +72,7 @@ static irqreturn_t monotonic_interrupt(int irq, void *dev_id)
72 72
73static struct irqaction monotonic_irqaction = { 73static struct irqaction monotonic_irqaction = {
74 .handler = monotonic_interrupt, 74 .handler = monotonic_interrupt,
75 .flags = IRQF_DISABLED | IRQF_TIMER, 75 .flags = IRQF_TIMER,
76 .name = "Monotonic timer", 76 .name = "Monotonic timer",
77}; 77};
78 78
diff --git a/arch/mips/sgi-ip22/Makefile b/arch/mips/sgi-ip22/Makefile
index cc538493cae1..411cda9ee030 100644
--- a/arch/mips/sgi-ip22/Makefile
+++ b/arch/mips/sgi-ip22/Makefile
@@ -4,7 +4,7 @@
4# 4#
5 5
6obj-y += ip22-mc.o ip22-hpc.o ip22-int.o ip22-time.o ip22-nvram.o \ 6obj-y += ip22-mc.o ip22-hpc.o ip22-int.o ip22-time.o ip22-nvram.o \
7 ip22-platform.o ip22-reset.o ip22-setup.o 7 ip22-platform.o ip22-reset.o ip22-setup.o ip22-gio.o
8 8
9obj-$(CONFIG_SGI_IP22) += ip22-berr.o 9obj-$(CONFIG_SGI_IP22) += ip22-berr.o
10obj-$(CONFIG_SGI_IP28) += ip28-berr.o 10obj-$(CONFIG_SGI_IP28) += ip28-berr.o
diff --git a/arch/mips/sgi-ip22/ip22-gio.c b/arch/mips/sgi-ip22/ip22-gio.c
new file mode 100644
index 000000000000..f5ebc092aed5
--- /dev/null
+++ b/arch/mips/sgi-ip22/ip22-gio.c
@@ -0,0 +1,428 @@
1#include <linux/export.h>
2#include <linux/kernel.h>
3#include <linux/init.h>
4#include <linux/slab.h>
5
6#include <asm/addrspace.h>
7#include <asm/paccess.h>
8#include <asm/gio_device.h>
9#include <asm/sgi/gio.h>
10#include <asm/sgi/hpc3.h>
11#include <asm/sgi/mc.h>
12#include <asm/sgi/ip22.h>
13
14static struct bus_type gio_bus_type;
15
16static struct {
17 const char *name;
18 __u8 id;
19} gio_name_table[] = {
20 { .name = "SGI Impact", .id = 0x10 },
21 { .name = "Phobos G160", .id = 0x35 },
22 /* fake IDs */
23 { .name = "SGI Newport", .id = 0x7e },
24 { .name = "SGI GR2/GR3", .id = 0x7f },
25};
26
27static struct device gio_bus = {
28 .init_name = "gio",
29};
30
31/**
32 * gio_match_device - Tell if an of_device structure has a matching
33 * gio_match structure
34 * @ids: array of of device match structures to search in
35 * @dev: the of device structure to match against
36 *
37 * Used by a driver to check whether an of_device present in the
38 * system is in its list of supported devices.
39 */
40const struct gio_device_id *gio_match_device(const struct gio_device_id *match,
41 const struct gio_device *dev)
42{
43 const struct gio_device_id *ids;
44
45 for (ids = match; ids->id != 0xff; ids++)
46 if (ids->id == dev->id.id)
47 return ids;
48
49 return NULL;
50}
51EXPORT_SYMBOL_GPL(gio_match_device);
52
53struct gio_device *gio_dev_get(struct gio_device *dev)
54{
55 struct device *tmp;
56
57 if (!dev)
58 return NULL;
59 tmp = get_device(&dev->dev);
60 if (tmp)
61 return to_gio_device(tmp);
62 else
63 return NULL;
64}
65EXPORT_SYMBOL_GPL(gio_dev_get);
66
67void gio_dev_put(struct gio_device *dev)
68{
69 if (dev)
70 put_device(&dev->dev);
71}
72EXPORT_SYMBOL_GPL(gio_dev_put);
73
74/**
75 * gio_release_dev - free an gio device structure when all users of it are finished.
76 * @dev: device that's been disconnected
77 *
78 * Will be called only by the device core when all users of this gio device are
79 * done.
80 */
81void gio_release_dev(struct device *dev)
82{
83 struct gio_device *giodev;
84
85 giodev = to_gio_device(dev);
86 kfree(giodev);
87}
88EXPORT_SYMBOL_GPL(gio_release_dev);
89
90int gio_device_register(struct gio_device *giodev)
91{
92 giodev->dev.bus = &gio_bus_type;
93 giodev->dev.parent = &gio_bus;
94 return device_register(&giodev->dev);
95}
96EXPORT_SYMBOL_GPL(gio_device_register);
97
98void gio_device_unregister(struct gio_device *giodev)
99{
100 device_unregister(&giodev->dev);
101}
102EXPORT_SYMBOL_GPL(gio_device_unregister);
103
104static int gio_bus_match(struct device *dev, struct device_driver *drv)
105{
106 struct gio_device *gio_dev = to_gio_device(dev);
107 struct gio_driver *gio_drv = to_gio_driver(drv);
108
109 return gio_match_device(gio_drv->id_table, gio_dev) != NULL;
110}
111
112static int gio_device_probe(struct device *dev)
113{
114 int error = -ENODEV;
115 struct gio_driver *drv;
116 struct gio_device *gio_dev;
117 const struct gio_device_id *match;
118
119 drv = to_gio_driver(dev->driver);
120 gio_dev = to_gio_device(dev);
121
122 if (!drv->probe)
123 return error;
124
125 gio_dev_get(gio_dev);
126
127 match = gio_match_device(drv->id_table, gio_dev);
128 if (match)
129 error = drv->probe(gio_dev, match);
130 if (error)
131 gio_dev_put(gio_dev);
132
133 return error;
134}
135
136static int gio_device_remove(struct device *dev)
137{
138 struct gio_device *gio_dev = to_gio_device(dev);
139 struct gio_driver *drv = to_gio_driver(dev->driver);
140
141 if (dev->driver && drv->remove)
142 drv->remove(gio_dev);
143 return 0;
144}
145
146static int gio_device_suspend(struct device *dev, pm_message_t state)
147{
148 struct gio_device *gio_dev = to_gio_device(dev);
149 struct gio_driver *drv = to_gio_driver(dev->driver);
150 int error = 0;
151
152 if (dev->driver && drv->suspend)
153 error = drv->suspend(gio_dev, state);
154 return error;
155}
156
157static int gio_device_resume(struct device *dev)
158{
159 struct gio_device *gio_dev = to_gio_device(dev);
160 struct gio_driver *drv = to_gio_driver(dev->driver);
161 int error = 0;
162
163 if (dev->driver && drv->resume)
164 error = drv->resume(gio_dev);
165 return error;
166}
167
168static void gio_device_shutdown(struct device *dev)
169{
170 struct gio_device *gio_dev = to_gio_device(dev);
171 struct gio_driver *drv = to_gio_driver(dev->driver);
172
173 if (dev->driver && drv->shutdown)
174 drv->shutdown(gio_dev);
175}
176
177static ssize_t modalias_show(struct device *dev, struct device_attribute *a,
178 char *buf)
179{
180 struct gio_device *gio_dev = to_gio_device(dev);
181 int len = snprintf(buf, PAGE_SIZE, "gio:%x\n", gio_dev->id.id);
182
183 return (len >= PAGE_SIZE) ? (PAGE_SIZE - 1) : len;
184}
185
186static ssize_t name_show(struct device *dev,
187 struct device_attribute *attr, char *buf)
188{
189 struct gio_device *giodev;
190
191 giodev = to_gio_device(dev);
192 return sprintf(buf, "%s", giodev->name);
193}
194
195static ssize_t id_show(struct device *dev,
196 struct device_attribute *attr, char *buf)
197{
198 struct gio_device *giodev;
199
200 giodev = to_gio_device(dev);
201 return sprintf(buf, "%x", giodev->id.id);
202}
203
204static struct device_attribute gio_dev_attrs[] = {
205 __ATTR_RO(modalias),
206 __ATTR_RO(name),
207 __ATTR_RO(id),
208 __ATTR_NULL,
209};
210
211static int gio_device_uevent(struct device *dev, struct kobj_uevent_env *env)
212{
213 struct gio_device *gio_dev = to_gio_device(dev);
214
215 add_uevent_var(env, "MODALIAS=gio:%x", gio_dev->id.id);
216 return 0;
217}
218
219int gio_register_driver(struct gio_driver *drv)
220{
221 /* initialize common driver fields */
222 if (!drv->driver.name)
223 drv->driver.name = drv->name;
224 if (!drv->driver.owner)
225 drv->driver.owner = drv->owner;
226 drv->driver.bus = &gio_bus_type;
227
228 /* register with core */
229 return driver_register(&drv->driver);
230}
231EXPORT_SYMBOL_GPL(gio_register_driver);
232
233void gio_unregister_driver(struct gio_driver *drv)
234{
235 driver_unregister(&drv->driver);
236}
237EXPORT_SYMBOL_GPL(gio_unregister_driver);
238
239void gio_set_master(struct gio_device *dev)
240{
241 u32 tmp = sgimc->giopar;
242
243 switch (dev->slotno) {
244 case 0:
245 tmp |= SGIMC_GIOPAR_MASTERGFX;
246 break;
247 case 1:
248 tmp |= SGIMC_GIOPAR_MASTEREXP0;
249 break;
250 case 2:
251 tmp |= SGIMC_GIOPAR_MASTEREXP1;
252 break;
253 }
254 sgimc->giopar = tmp;
255}
256EXPORT_SYMBOL_GPL(gio_set_master);
257
258void ip22_gio_set_64bit(int slotno)
259{
260 u32 tmp = sgimc->giopar;
261
262 switch (slotno) {
263 case 0:
264 tmp |= SGIMC_GIOPAR_GFX64;
265 break;
266 case 1:
267 tmp |= SGIMC_GIOPAR_EXP064;
268 break;
269 case 2:
270 tmp |= SGIMC_GIOPAR_EXP164;
271 break;
272 }
273 sgimc->giopar = tmp;
274}
275
276static int ip22_gio_id(unsigned long addr, u32 *res)
277{
278 u8 tmp8;
279 u8 tmp16;
280 u32 tmp32;
281 u8 *ptr8;
282 u16 *ptr16;
283 u32 *ptr32;
284
285 ptr32 = (void *)CKSEG1ADDR(addr);
286 if (!get_dbe(tmp32, ptr32)) {
287 /*
288 * We got no DBE, but this doesn't mean anything.
289 * If GIO is pipelined (which can't be disabled
290 * for GFX slot) we don't get a DBE, but we see
291 * the transfer size as data. So we do an 8bit
292 * and a 16bit access and check whether the common
293 * data matches
294 */
295 ptr8 = (void *)CKSEG1ADDR(addr + 3);
296 get_dbe(tmp8, ptr8);
297 ptr16 = (void *)CKSEG1ADDR(addr + 2);
298 get_dbe(tmp16, ptr16);
299 if (tmp8 == (tmp16 & 0xff) &&
300 tmp8 == (tmp32 & 0xff) &&
301 tmp16 == (tmp32 & 0xffff)) {
302 *res = tmp32;
303 return 1;
304 }
305 }
306 return 0; /* nothing here */
307}
308
309#define HQ2_MYSTERY_OFFS 0x6A07C
310#define NEWPORT_USTATUS_OFFS 0xF133C
311
312static int ip22_is_gr2(unsigned long addr)
313{
314 u32 tmp;
315 u32 *ptr;
316
317 /* HQ2 only allows 32bit accesses */
318 ptr = (void *)CKSEG1ADDR(addr + HQ2_MYSTERY_OFFS);
319 if (!get_dbe(tmp, ptr)) {
320 if (tmp == 0xdeadbeef)
321 return 1;
322 }
323 return 0;
324}
325
326
327static void ip22_check_gio(int slotno, unsigned long addr)
328{
329 const char *name = "Unknown";
330 struct gio_device *gio_dev;
331 u32 tmp;
332 __u8 id;
333 int i;
334
335 /* first look for GR2/GR3 by checking mystery register */
336 if (ip22_is_gr2(addr))
337 tmp = 0x7f;
338 else {
339 if (!ip22_gio_id(addr, &tmp)) {
340 /*
341 * no GIO signature at start address of slot, but
342 * Newport doesn't have one, so let's check usea
343 * status register
344 */
345 if (ip22_gio_id(addr + NEWPORT_USTATUS_OFFS, &tmp))
346 tmp = 0x7e;
347 else
348 tmp = 0;
349 }
350 }
351 if (tmp) {
352 id = GIO_ID(tmp);
353 if (tmp & GIO_32BIT_ID) {
354 if (tmp & GIO_64BIT_IFACE)
355 ip22_gio_set_64bit(slotno);
356 }
357 for (i = 0; i < ARRAY_SIZE(gio_name_table); i++) {
358 if (id == gio_name_table[i].id) {
359 name = gio_name_table[i].name;
360 break;
361 }
362 }
363 printk(KERN_INFO "GIO: slot %d : %s (id %x)\n",
364 slotno, name, id);
365 gio_dev = kzalloc(sizeof *gio_dev, GFP_KERNEL);
366 gio_dev->name = name;
367 gio_dev->slotno = slotno;
368 gio_dev->id.id = id;
369 gio_dev->resource.start = addr;
370 gio_dev->resource.end = addr + 0x3fffff;
371 gio_dev->resource.flags = IORESOURCE_MEM;
372 dev_set_name(&gio_dev->dev, "%d", slotno);
373 gio_device_register(gio_dev);
374 } else
375 printk(KERN_INFO "GIO: slot %d : Empty\n", slotno);
376}
377
378static struct bus_type gio_bus_type = {
379 .name = "gio",
380 .dev_attrs = gio_dev_attrs,
381 .match = gio_bus_match,
382 .probe = gio_device_probe,
383 .remove = gio_device_remove,
384 .suspend = gio_device_suspend,
385 .resume = gio_device_resume,
386 .shutdown = gio_device_shutdown,
387 .uevent = gio_device_uevent,
388};
389
390static struct resource gio_bus_resource = {
391 .start = GIO_SLOT_GFX_BASE,
392 .end = GIO_SLOT_GFX_BASE + 0x9fffff,
393 .name = "GIO Bus",
394 .flags = IORESOURCE_MEM,
395};
396
397int __init ip22_gio_init(void)
398{
399 unsigned int pbdma __maybe_unused;
400 int ret;
401
402 ret = device_register(&gio_bus);
403 if (ret)
404 return ret;
405
406 ret = bus_register(&gio_bus_type);
407 if (!ret) {
408 request_resource(&iomem_resource, &gio_bus_resource);
409 printk(KERN_INFO "GIO: Probing bus...\n");
410
411 if (ip22_is_fullhouse() ||
412 !get_dbe(pbdma, (unsigned int *)&hpc3c1->pbdma[1])) {
413 /* Indigo2 and ChallengeS */
414 ip22_check_gio(0, GIO_SLOT_GFX_BASE);
415 ip22_check_gio(1, GIO_SLOT_EXP0_BASE);
416 } else {
417 /* Indy */
418 ip22_check_gio(0, GIO_SLOT_GFX_BASE);
419 ip22_check_gio(1, GIO_SLOT_EXP0_BASE);
420 ip22_check_gio(2, GIO_SLOT_EXP1_BASE);
421 }
422 } else
423 device_unregister(&gio_bus);
424
425 return ret;
426}
427
428subsys_initcall(ip22_gio_init);
diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c
index f72c336ea27b..3f2b7633f946 100644
--- a/arch/mips/sgi-ip22/ip22-int.c
+++ b/arch/mips/sgi-ip22/ip22-int.c
@@ -155,32 +155,32 @@ static void __irq_entry indy_buserror_irq(void)
155 155
156static struct irqaction local0_cascade = { 156static struct irqaction local0_cascade = {
157 .handler = no_action, 157 .handler = no_action,
158 .flags = IRQF_DISABLED | IRQF_NO_THREAD, 158 .flags = IRQF_NO_THREAD,
159 .name = "local0 cascade", 159 .name = "local0 cascade",
160}; 160};
161 161
162static struct irqaction local1_cascade = { 162static struct irqaction local1_cascade = {
163 .handler = no_action, 163 .handler = no_action,
164 .flags = IRQF_DISABLED | IRQF_NO_THREAD, 164 .flags = IRQF_NO_THREAD,
165 .name = "local1 cascade", 165 .name = "local1 cascade",
166}; 166};
167 167
168static struct irqaction buserr = { 168static struct irqaction buserr = {
169 .handler = no_action, 169 .handler = no_action,
170 .flags = IRQF_DISABLED | IRQF_NO_THREAD, 170 .flags = IRQF_NO_THREAD,
171 .name = "Bus Error", 171 .name = "Bus Error",
172}; 172};
173 173
174static struct irqaction map0_cascade = { 174static struct irqaction map0_cascade = {
175 .handler = no_action, 175 .handler = no_action,
176 .flags = IRQF_DISABLED | IRQF_NO_THREAD, 176 .flags = IRQF_NO_THREAD,
177 .name = "mapable0 cascade", 177 .name = "mapable0 cascade",
178}; 178};
179 179
180#ifdef USE_LIO3_IRQ 180#ifdef USE_LIO3_IRQ
181static struct irqaction map1_cascade = { 181static struct irqaction map1_cascade = {
182 .handler = no_action, 182 .handler = no_action,
183 .flags = IRQF_DISABLED | IRQF_NO_THREAD, 183 .flags = IRQF_NO_THREAD,
184 .name = "mapable1 cascade", 184 .name = "mapable1 cascade",
185}; 185};
186#define SGI_INTERRUPTS SGINT_END 186#define SGI_INTERRUPTS SGINT_END
diff --git a/arch/mips/sgi-ip22/ip22-mc.c b/arch/mips/sgi-ip22/ip22-mc.c
index d22262ee6853..75ada8a9713b 100644
--- a/arch/mips/sgi-ip22/ip22-mc.c
+++ b/arch/mips/sgi-ip22/ip22-mc.c
@@ -139,11 +139,11 @@ void __init sgimc_init(void)
139 * zero. 139 * zero.
140 */ 140 */
141 /* don't touch parity settings for IP28 */ 141 /* don't touch parity settings for IP28 */
142#ifndef CONFIG_SGI_IP28
143 tmp = sgimc->cpuctrl0; 142 tmp = sgimc->cpuctrl0;
144 tmp |= (SGIMC_CCTRL0_EPERRGIO | SGIMC_CCTRL0_EPERRMEM | 143#ifndef CONFIG_SGI_IP28
145 SGIMC_CCTRL0_R4KNOCHKPARR); 144 tmp |= SGIMC_CCTRL0_EPERRGIO | SGIMC_CCTRL0_EPERRMEM;
146#endif 145#endif
146 tmp |= SGIMC_CCTRL0_R4KNOCHKPARR;
147 sgimc->cpuctrl0 = tmp; 147 sgimc->cpuctrl0 = tmp;
148 148
149 /* Step 3: Setup the MC write buffer depth, this is controlled 149 /* Step 3: Setup the MC write buffer depth, this is controlled
@@ -178,7 +178,8 @@ void __init sgimc_init(void)
178 */ 178 */
179 179
180 /* First the basic invariants across all GIO64 implementations. */ 180 /* First the basic invariants across all GIO64 implementations. */
181 tmp = SGIMC_GIOPAR_HPC64; /* All 1st HPC's interface at 64bits */ 181 tmp = sgimc->giopar & SGIMC_GIOPAR_GFX64; /* keep gfx 64bit settings */
182 tmp |= SGIMC_GIOPAR_HPC64; /* All 1st HPC's interface at 64bits */
182 tmp |= SGIMC_GIOPAR_ONEBUS; /* Only one physical GIO bus exists */ 183 tmp |= SGIMC_GIOPAR_ONEBUS; /* Only one physical GIO bus exists */
183 184
184 if (ip22_is_fullhouse()) { 185 if (ip22_is_fullhouse()) {
@@ -193,7 +194,6 @@ void __init sgimc_init(void)
193 tmp |= SGIMC_GIOPAR_PLINEEXP0; /* exp[01] pipelined */ 194 tmp |= SGIMC_GIOPAR_PLINEEXP0; /* exp[01] pipelined */
194 tmp |= SGIMC_GIOPAR_PLINEEXP1; 195 tmp |= SGIMC_GIOPAR_PLINEEXP1;
195 tmp |= SGIMC_GIOPAR_MASTEREISA; /* EISA masters */ 196 tmp |= SGIMC_GIOPAR_MASTEREISA; /* EISA masters */
196 tmp |= SGIMC_GIOPAR_GFX64; /* GFX at 64 bits */
197 } 197 }
198 } else { 198 } else {
199 /* Guiness specific settings. */ 199 /* Guiness specific settings. */
diff --git a/arch/mips/sgi-ip22/ip22-setup.c b/arch/mips/sgi-ip22/ip22-setup.c
index 5e6621349471..c7bdfe43df5b 100644
--- a/arch/mips/sgi-ip22/ip22-setup.c
+++ b/arch/mips/sgi-ip22/ip22-setup.c
@@ -26,9 +26,6 @@
26#include <asm/sgi/hpc3.h> 26#include <asm/sgi/hpc3.h>
27#include <asm/sgi/ip22.h> 27#include <asm/sgi/ip22.h>
28 28
29unsigned long sgi_gfxaddr;
30EXPORT_SYMBOL_GPL(sgi_gfxaddr);
31
32extern void ip22_be_init(void) __init; 29extern void ip22_be_init(void) __init;
33 30
34void __init plat_mem_setup(void) 31void __init plat_mem_setup(void)
@@ -78,22 +75,4 @@ void __init plat_mem_setup(void)
78 prom_flags |= PROM_FLAG_USE_AS_CONSOLE; 75 prom_flags |= PROM_FLAG_USE_AS_CONSOLE;
79 add_preferred_console("arc", 0, NULL); 76 add_preferred_console("arc", 0, NULL);
80 } 77 }
81
82#if defined(CONFIG_VT) && defined(CONFIG_SGI_NEWPORT_CONSOLE)
83 {
84 ULONG *gfxinfo;
85 ULONG * (*__vec)(void) = (void *) (long)
86 *((_PULONG *)(long)((PROMBLOCK)->pvector + 0x20));
87
88 gfxinfo = __vec();
89 sgi_gfxaddr = ((gfxinfo[1] >= 0xa0000000
90 && gfxinfo[1] <= 0xc0000000)
91 ? gfxinfo[1] - 0xa0000000 : 0);
92
93 /* newport addresses? */
94 if (sgi_gfxaddr == 0x1f0f0000 || sgi_gfxaddr == 0x1f4f0000) {
95 conswitchp = &newport_con;
96 }
97 }
98#endif
99} 78}
diff --git a/arch/mips/sgi-ip27/ip27-irq.c b/arch/mips/sgi-ip27/ip27-irq.c
index f90dce315e04..23642238c689 100644
--- a/arch/mips/sgi-ip27/ip27-irq.c
+++ b/arch/mips/sgi-ip27/ip27-irq.c
@@ -73,7 +73,7 @@ static inline int alloc_level(int cpu, int irq)
73 73
74 level = find_first_zero_bit(hub->irq_alloc_mask, LEVELS_PER_SLICE); 74 level = find_first_zero_bit(hub->irq_alloc_mask, LEVELS_PER_SLICE);
75 if (level >= LEVELS_PER_SLICE) 75 if (level >= LEVELS_PER_SLICE)
76 panic("Cpu %d flooded with devices\n", cpu); 76 panic("Cpu %d flooded with devices", cpu);
77 77
78 __set_bit(level, hub->irq_alloc_mask); 78 __set_bit(level, hub->irq_alloc_mask);
79 si->level_to_irq[level] = irq; 79 si->level_to_irq[level] = irq;
@@ -96,7 +96,7 @@ static inline int find_level(cpuid_t *cpunum, int irq)
96 } 96 }
97 } 97 }
98 98
99 panic("Could not identify cpu/level for irq %d\n", irq); 99 panic("Could not identify cpu/level for irq %d", irq);
100} 100}
101 101
102/* 102/*
@@ -116,7 +116,7 @@ static int ms1bit(unsigned long x)
116} 116}
117 117
118/* 118/*
119 * This code is unnecessarily complex, because we do IRQF_DISABLED 119 * This code is unnecessarily complex, because we do
120 * intr enabling. Basically, once we grab the set of intrs we need 120 * intr enabling. Basically, once we grab the set of intrs we need
121 * to service, we must mask _all_ these interrupts; firstly, to make 121 * to service, we must mask _all_ these interrupts; firstly, to make
122 * sure the same intr does not intr again, causing recursion that 122 * sure the same intr does not intr again, causing recursion that
diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c
index ef74f3267f91..13cfeab50528 100644
--- a/arch/mips/sgi-ip27/ip27-timer.c
+++ b/arch/mips/sgi-ip27/ip27-timer.c
@@ -91,7 +91,7 @@ static irqreturn_t hub_rt_counter_handler(int irq, void *dev_id)
91 91
92struct irqaction hub_rt_irqaction = { 92struct irqaction hub_rt_irqaction = {
93 .handler = hub_rt_counter_handler, 93 .handler = hub_rt_counter_handler,
94 .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER, 94 .flags = IRQF_PERCPU | IRQF_TIMER,
95 .name = "hub-rt", 95 .name = "hub-rt",
96}; 96};
97 97
diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c
index c65ea76d56c7..a092860d5196 100644
--- a/arch/mips/sgi-ip32/ip32-irq.c
+++ b/arch/mips/sgi-ip32/ip32-irq.c
@@ -113,13 +113,11 @@ extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id);
113 113
114static struct irqaction memerr_irq = { 114static struct irqaction memerr_irq = {
115 .handler = crime_memerr_intr, 115 .handler = crime_memerr_intr,
116 .flags = IRQF_DISABLED,
117 .name = "CRIME memory error", 116 .name = "CRIME memory error",
118}; 117};
119 118
120static struct irqaction cpuerr_irq = { 119static struct irqaction cpuerr_irq = {
121 .handler = crime_cpuerr_intr, 120 .handler = crime_cpuerr_intr,
122 .flags = IRQF_DISABLED,
123 .name = "CRIME CPU error", 121 .name = "CRIME CPU error",
124}; 122};
125 123
diff --git a/arch/mips/sni/irq.c b/arch/mips/sni/irq.c
index e8e72bb3a9af..5a4ec75382e2 100644
--- a/arch/mips/sni/irq.c
+++ b/arch/mips/sni/irq.c
@@ -42,7 +42,7 @@ static irqreturn_t sni_isa_irq_handler(int dummy, void *p)
42struct irqaction sni_isa_irq = { 42struct irqaction sni_isa_irq = {
43 .handler = sni_isa_irq_handler, 43 .handler = sni_isa_irq_handler,
44 .name = "ISA", 44 .name = "ISA",
45 .flags = IRQF_SHARED | IRQF_DISABLED 45 .flags = IRQF_SHARED
46}; 46};
47 47
48/* 48/*
diff --git a/arch/mips/sni/time.c b/arch/mips/sni/time.c
index ec0be14996a4..494c9e7847aa 100644
--- a/arch/mips/sni/time.c
+++ b/arch/mips/sni/time.c
@@ -68,7 +68,7 @@ static irqreturn_t a20r_interrupt(int irq, void *dev_id)
68 68
69static struct irqaction a20r_irqaction = { 69static struct irqaction a20r_irqaction = {
70 .handler = a20r_interrupt, 70 .handler = a20r_interrupt,
71 .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER, 71 .flags = IRQF_PERCPU | IRQF_TIMER,
72 .name = "a20r-timer", 72 .name = "a20r-timer",
73}; 73};
74 74
diff --git a/arch/mips/txx9/generic/pci.c b/arch/mips/txx9/generic/pci.c
index 85a87de17eb4..682efb0c108d 100644
--- a/arch/mips/txx9/generic/pci.c
+++ b/arch/mips/txx9/generic/pci.c
@@ -262,7 +262,7 @@ txx9_i8259_irq_setup(int irq)
262 int err; 262 int err;
263 263
264 init_i8259_irqs(); 264 init_i8259_irqs();
265 err = request_irq(irq, &i8259_interrupt, IRQF_DISABLED|IRQF_SHARED, 265 err = request_irq(irq, &i8259_interrupt, IRQF_SHARED,
266 "cascade(i8259)", (void *)(long)irq); 266 "cascade(i8259)", (void *)(long)irq);
267 if (!err) 267 if (!err)
268 printk(KERN_INFO "PCI-ISA bridge PIC (irq %d)\n", irq); 268 printk(KERN_INFO "PCI-ISA bridge PIC (irq %d)\n", irq);
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index a3afac4be734..cbe7a2fb779f 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -299,11 +299,11 @@ config I2C_AT91
299 unless your system can cope with those limitations. 299 unless your system can cope with those limitations.
300 300
301config I2C_AU1550 301config I2C_AU1550
302 tristate "Au1550/Au1200 SMBus interface" 302 tristate "Au1550/Au1200/Au1300 SMBus interface"
303 depends on MIPS_ALCHEMY 303 depends on MIPS_ALCHEMY
304 help 304 help
305 If you say yes to this option, support will be included for the 305 If you say yes to this option, support will be included for the
306 Au1550 and Au1200 SMBus interface. 306 Au1550/Au1200/Au1300 SMBus interface.
307 307
308 This driver can also be built as a module. If so, the module 308 This driver can also be built as a module. If so, the module
309 will be called i2c-au1550. 309 will be called i2c-au1550.
diff --git a/drivers/mmc/host/au1xmmc.c b/drivers/mmc/host/au1xmmc.c
index 5d3b9ae64523..dbd0c8a4e98a 100644
--- a/drivers/mmc/host/au1xmmc.c
+++ b/drivers/mmc/host/au1xmmc.c
@@ -153,6 +153,7 @@ static inline int has_dbdma(void)
153{ 153{
154 switch (alchemy_get_cputype()) { 154 switch (alchemy_get_cputype()) {
155 case ALCHEMY_CPU_AU1200: 155 case ALCHEMY_CPU_AU1200:
156 case ALCHEMY_CPU_AU1300:
156 return 1; 157 return 1;
157 default: 158 default:
158 return 0; 159 return 0;
@@ -768,11 +769,15 @@ static void au1xmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
768 769
769 config2 = au_readl(HOST_CONFIG2(host)); 770 config2 = au_readl(HOST_CONFIG2(host));
770 switch (ios->bus_width) { 771 switch (ios->bus_width) {
772 case MMC_BUS_WIDTH_8:
773 config2 |= SD_CONFIG2_BB;
774 break;
771 case MMC_BUS_WIDTH_4: 775 case MMC_BUS_WIDTH_4:
776 config2 &= ~SD_CONFIG2_BB;
772 config2 |= SD_CONFIG2_WB; 777 config2 |= SD_CONFIG2_WB;
773 break; 778 break;
774 case MMC_BUS_WIDTH_1: 779 case MMC_BUS_WIDTH_1:
775 config2 &= ~SD_CONFIG2_WB; 780 config2 &= ~(SD_CONFIG2_WB | SD_CONFIG2_BB);
776 break; 781 break;
777 } 782 }
778 au_writel(config2, HOST_CONFIG2(host)); 783 au_writel(config2, HOST_CONFIG2(host));
@@ -943,7 +948,7 @@ static int __devinit au1xmmc_probe(struct platform_device *pdev)
943 struct mmc_host *mmc; 948 struct mmc_host *mmc;
944 struct au1xmmc_host *host; 949 struct au1xmmc_host *host;
945 struct resource *r; 950 struct resource *r;
946 int ret; 951 int ret, iflag;
947 952
948 mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), &pdev->dev); 953 mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), &pdev->dev);
949 if (!mmc) { 954 if (!mmc) {
@@ -982,37 +987,43 @@ static int __devinit au1xmmc_probe(struct platform_device *pdev)
982 dev_err(&pdev->dev, "no IRQ defined\n"); 987 dev_err(&pdev->dev, "no IRQ defined\n");
983 goto out3; 988 goto out3;
984 } 989 }
985
986 host->irq = r->start; 990 host->irq = r->start;
987 /* IRQ is shared among both SD controllers */
988 ret = request_irq(host->irq, au1xmmc_irq, IRQF_SHARED,
989 DRIVER_NAME, host);
990 if (ret) {
991 dev_err(&pdev->dev, "cannot grab IRQ\n");
992 goto out3;
993 }
994 991
995 mmc->ops = &au1xmmc_ops; 992 mmc->ops = &au1xmmc_ops;
996 993
997 mmc->f_min = 450000; 994 mmc->f_min = 450000;
998 mmc->f_max = 24000000; 995 mmc->f_max = 24000000;
999 996
997 mmc->max_blk_size = 2048;
998 mmc->max_blk_count = 512;
999
1000 mmc->ocr_avail = AU1XMMC_OCR;
1001 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1002 mmc->max_segs = AU1XMMC_DESCRIPTOR_COUNT;
1003
1004 iflag = IRQF_SHARED; /* Au1100/Au1200: one int for both ctrls */
1005
1000 switch (alchemy_get_cputype()) { 1006 switch (alchemy_get_cputype()) {
1001 case ALCHEMY_CPU_AU1100: 1007 case ALCHEMY_CPU_AU1100:
1002 mmc->max_seg_size = AU1100_MMC_DESCRIPTOR_SIZE; 1008 mmc->max_seg_size = AU1100_MMC_DESCRIPTOR_SIZE;
1003 mmc->max_segs = AU1XMMC_DESCRIPTOR_COUNT;
1004 break; 1009 break;
1005 case ALCHEMY_CPU_AU1200: 1010 case ALCHEMY_CPU_AU1200:
1006 mmc->max_seg_size = AU1200_MMC_DESCRIPTOR_SIZE; 1011 mmc->max_seg_size = AU1200_MMC_DESCRIPTOR_SIZE;
1007 mmc->max_segs = AU1XMMC_DESCRIPTOR_COUNT; 1012 break;
1013 case ALCHEMY_CPU_AU1300:
1014 iflag = 0; /* nothing is shared */
1015 mmc->max_seg_size = AU1200_MMC_DESCRIPTOR_SIZE;
1016 mmc->f_max = 52000000;
1017 if (host->ioarea->start == AU1100_SD0_PHYS_ADDR)
1018 mmc->caps |= MMC_CAP_8_BIT_DATA;
1008 break; 1019 break;
1009 } 1020 }
1010 1021
1011 mmc->max_blk_size = 2048; 1022 ret = request_irq(host->irq, au1xmmc_irq, iflag, DRIVER_NAME, host);
1012 mmc->max_blk_count = 512; 1023 if (ret) {
1013 1024 dev_err(&pdev->dev, "cannot grab IRQ\n");
1014 mmc->ocr_avail = AU1XMMC_OCR; 1025 goto out3;
1015 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; 1026 }
1016 1027
1017 host->status = HOST_S_IDLE; 1028 host->status = HOST_S_IDLE;
1018 1029
diff --git a/drivers/mtd/nand/au1550nd.c b/drivers/mtd/nand/au1550nd.c
index 7dd3700f2303..73abbc3e093e 100644
--- a/drivers/mtd/nand/au1550nd.c
+++ b/drivers/mtd/nand/au1550nd.c
@@ -17,35 +17,19 @@
17#include <linux/mtd/mtd.h> 17#include <linux/mtd/mtd.h>
18#include <linux/mtd/nand.h> 18#include <linux/mtd/nand.h>
19#include <linux/mtd/partitions.h> 19#include <linux/mtd/partitions.h>
20#include <linux/platform_device.h>
20#include <asm/io.h> 21#include <asm/io.h>
22#include <asm/mach-au1x00/au1000.h>
23#include <asm/mach-au1x00/au1550nd.h>
21 24
22#ifdef CONFIG_MIPS_PB1550
23#include <asm/mach-pb1x00/pb1550.h>
24#elif defined(CONFIG_MIPS_DB1550)
25#include <asm/mach-db1x00/db1x00.h>
26#endif
27#include <asm/mach-db1x00/bcsr.h>
28 25
29/* 26struct au1550nd_ctx {
30 * MTD structure for NAND controller 27 struct mtd_info info;
31 */ 28 struct nand_chip chip;
32static struct mtd_info *au1550_mtd = NULL;
33static void __iomem *p_nand;
34static int nand_width = 1; /* default x8 */
35static void (*au1550_write_byte)(struct mtd_info *, u_char);
36 29
37/* 30 int cs;
38 * Define partitions for flash device 31 void __iomem *base;
39 */ 32 void (*write_byte)(struct mtd_info *, u_char);
40static const struct mtd_partition partition_info[] = {
41 {
42 .name = "NAND FS 0",
43 .offset = 0,
44 .size = 8 * 1024 * 1024},
45 {
46 .name = "NAND FS 1",
47 .offset = MTDPART_OFS_APPEND,
48 .size = MTDPART_SIZ_FULL}
49}; 33};
50 34
51/** 35/**
@@ -259,24 +243,25 @@ static int au_verify_buf16(struct mtd_info *mtd, const u_char *buf, int len)
259 243
260static void au1550_hwcontrol(struct mtd_info *mtd, int cmd) 244static void au1550_hwcontrol(struct mtd_info *mtd, int cmd)
261{ 245{
262 register struct nand_chip *this = mtd->priv; 246 struct au1550nd_ctx *ctx = container_of(mtd, struct au1550nd_ctx, info);
247 struct nand_chip *this = mtd->priv;
263 248
264 switch (cmd) { 249 switch (cmd) {
265 250
266 case NAND_CTL_SETCLE: 251 case NAND_CTL_SETCLE:
267 this->IO_ADDR_W = p_nand + MEM_STNAND_CMD; 252 this->IO_ADDR_W = ctx->base + MEM_STNAND_CMD;
268 break; 253 break;
269 254
270 case NAND_CTL_CLRCLE: 255 case NAND_CTL_CLRCLE:
271 this->IO_ADDR_W = p_nand + MEM_STNAND_DATA; 256 this->IO_ADDR_W = ctx->base + MEM_STNAND_DATA;
272 break; 257 break;
273 258
274 case NAND_CTL_SETALE: 259 case NAND_CTL_SETALE:
275 this->IO_ADDR_W = p_nand + MEM_STNAND_ADDR; 260 this->IO_ADDR_W = ctx->base + MEM_STNAND_ADDR;
276 break; 261 break;
277 262
278 case NAND_CTL_CLRALE: 263 case NAND_CTL_CLRALE:
279 this->IO_ADDR_W = p_nand + MEM_STNAND_DATA; 264 this->IO_ADDR_W = ctx->base + MEM_STNAND_DATA;
280 /* FIXME: Nobody knows why this is necessary, 265 /* FIXME: Nobody knows why this is necessary,
281 * but it works only that way */ 266 * but it works only that way */
282 udelay(1); 267 udelay(1);
@@ -284,7 +269,7 @@ static void au1550_hwcontrol(struct mtd_info *mtd, int cmd)
284 269
285 case NAND_CTL_SETNCE: 270 case NAND_CTL_SETNCE:
286 /* assert (force assert) chip enable */ 271 /* assert (force assert) chip enable */
287 au_writel((1 << (4 + NAND_CS)), MEM_STNDCTL); 272 au_writel((1 << (4 + ctx->cs)), MEM_STNDCTL);
288 break; 273 break;
289 274
290 case NAND_CTL_CLRNCE: 275 case NAND_CTL_CLRNCE:
@@ -331,9 +316,10 @@ static void au1550_select_chip(struct mtd_info *mtd, int chip)
331 */ 316 */
332static void au1550_command(struct mtd_info *mtd, unsigned command, int column, int page_addr) 317static void au1550_command(struct mtd_info *mtd, unsigned command, int column, int page_addr)
333{ 318{
334 register struct nand_chip *this = mtd->priv; 319 struct au1550nd_ctx *ctx = container_of(mtd, struct au1550nd_ctx, info);
320 struct nand_chip *this = mtd->priv;
335 int ce_override = 0, i; 321 int ce_override = 0, i;
336 ulong flags; 322 unsigned long flags = 0;
337 323
338 /* Begin command latch cycle */ 324 /* Begin command latch cycle */
339 au1550_hwcontrol(mtd, NAND_CTL_SETCLE); 325 au1550_hwcontrol(mtd, NAND_CTL_SETCLE);
@@ -354,9 +340,9 @@ static void au1550_command(struct mtd_info *mtd, unsigned command, int column, i
354 column -= 256; 340 column -= 256;
355 readcmd = NAND_CMD_READ1; 341 readcmd = NAND_CMD_READ1;
356 } 342 }
357 au1550_write_byte(mtd, readcmd); 343 ctx->write_byte(mtd, readcmd);
358 } 344 }
359 au1550_write_byte(mtd, command); 345 ctx->write_byte(mtd, command);
360 346
361 /* Set ALE and clear CLE to start address cycle */ 347 /* Set ALE and clear CLE to start address cycle */
362 au1550_hwcontrol(mtd, NAND_CTL_CLRCLE); 348 au1550_hwcontrol(mtd, NAND_CTL_CLRCLE);
@@ -369,10 +355,10 @@ static void au1550_command(struct mtd_info *mtd, unsigned command, int column, i
369 /* Adjust columns for 16 bit buswidth */ 355 /* Adjust columns for 16 bit buswidth */
370 if (this->options & NAND_BUSWIDTH_16) 356 if (this->options & NAND_BUSWIDTH_16)
371 column >>= 1; 357 column >>= 1;
372 au1550_write_byte(mtd, column); 358 ctx->write_byte(mtd, column);
373 } 359 }
374 if (page_addr != -1) { 360 if (page_addr != -1) {
375 au1550_write_byte(mtd, (u8)(page_addr & 0xff)); 361 ctx->write_byte(mtd, (u8)(page_addr & 0xff));
376 362
377 if (command == NAND_CMD_READ0 || 363 if (command == NAND_CMD_READ0 ||
378 command == NAND_CMD_READ1 || 364 command == NAND_CMD_READ1 ||
@@ -390,11 +376,12 @@ static void au1550_command(struct mtd_info *mtd, unsigned command, int column, i
390 au1550_hwcontrol(mtd, NAND_CTL_SETNCE); 376 au1550_hwcontrol(mtd, NAND_CTL_SETNCE);
391 } 377 }
392 378
393 au1550_write_byte(mtd, (u8)(page_addr >> 8)); 379 ctx->write_byte(mtd, (u8)(page_addr >> 8));
394 380
395 /* One more address cycle for devices > 32MiB */ 381 /* One more address cycle for devices > 32MiB */
396 if (this->chipsize > (32 << 20)) 382 if (this->chipsize > (32 << 20))
397 au1550_write_byte(mtd, (u8)((page_addr >> 16) & 0x0f)); 383 ctx->write_byte(mtd,
384 ((page_addr >> 16) & 0x0f));
398 } 385 }
399 /* Latch in address */ 386 /* Latch in address */
400 au1550_hwcontrol(mtd, NAND_CTL_CLRALE); 387 au1550_hwcontrol(mtd, NAND_CTL_CLRALE);
@@ -440,121 +427,79 @@ static void au1550_command(struct mtd_info *mtd, unsigned command, int column, i
440 while(!this->dev_ready(mtd)); 427 while(!this->dev_ready(mtd));
441} 428}
442 429
443 430static int __devinit find_nand_cs(unsigned long nand_base)
444/*
445 * Main initialization routine
446 */
447static int __init au1xxx_nand_init(void)
448{ 431{
449 struct nand_chip *this; 432 void __iomem *base =
450 u16 boot_swapboot = 0; /* default value */ 433 (void __iomem *)KSEG1ADDR(AU1000_STATIC_MEM_PHYS_ADDR);
451 int retval; 434 unsigned long addr, staddr, start, mask, end;
452 u32 mem_staddr; 435 int i;
453 u32 nand_phys;
454
455 /* Allocate memory for MTD device structure and private data */
456 au1550_mtd = kzalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
457 if (!au1550_mtd) {
458 printk("Unable to allocate NAND MTD dev structure.\n");
459 return -ENOMEM;
460 }
461
462 /* Get pointer to private data */
463 this = (struct nand_chip *)(&au1550_mtd[1]);
464
465 /* Link the private data with the MTD structure */
466 au1550_mtd->priv = this;
467 au1550_mtd->owner = THIS_MODULE;
468
469 436
470 /* MEM_STNDCTL: disable ints, disable nand boot */ 437 for (i = 0; i < 4; i++) {
471 au_writel(0, MEM_STNDCTL); 438 addr = 0x1000 + (i * 0x10); /* CSx */
439 staddr = __raw_readl(base + addr + 0x08); /* STADDRx */
440 /* figure out the decoded range of this CS */
441 start = (staddr << 4) & 0xfffc0000;
442 mask = (staddr << 18) & 0xfffc0000;
443 end = (start | (start - 1)) & ~(start ^ mask);
444 if ((nand_base >= start) && (nand_base < end))
445 return i;
446 }
472 447
473#ifdef CONFIG_MIPS_PB1550 448 return -ENODEV;
474 /* set gpio206 high */ 449}
475 gpio_direction_input(206);
476 450
477 boot_swapboot = (au_readl(MEM_STSTAT) & (0x7 << 1)) | ((bcsr_read(BCSR_STATUS) >> 6) & 0x1); 451static int __devinit au1550nd_probe(struct platform_device *pdev)
452{
453 struct au1550nd_platdata *pd;
454 struct au1550nd_ctx *ctx;
455 struct nand_chip *this;
456 struct resource *r;
457 int ret, cs;
478 458
479 switch (boot_swapboot) { 459 pd = pdev->dev.platform_data;
480 case 0: 460 if (!pd) {
481 case 2: 461 dev_err(&pdev->dev, "missing platform data\n");
482 case 8: 462 return -ENODEV;
483 case 0xC:
484 case 0xD:
485 /* x16 NAND Flash */
486 nand_width = 0;
487 break;
488 case 1:
489 case 9:
490 case 3:
491 case 0xE:
492 case 0xF:
493 /* x8 NAND Flash */
494 nand_width = 1;
495 break;
496 default:
497 printk("Pb1550 NAND: bad boot:swap\n");
498 retval = -EINVAL;
499 goto outmem;
500 } 463 }
501#endif 464
502 465 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
503 /* Configure chip-select; normally done by boot code, e.g. YAMON */ 466 if (!ctx) {
504#ifdef NAND_STCFG 467 dev_err(&pdev->dev, "no memory for NAND context\n");
505 if (NAND_CS == 0) { 468 return -ENOMEM;
506 au_writel(NAND_STCFG, MEM_STCFG0);
507 au_writel(NAND_STTIME, MEM_STTIME0);
508 au_writel(NAND_STADDR, MEM_STADDR0);
509 }
510 if (NAND_CS == 1) {
511 au_writel(NAND_STCFG, MEM_STCFG1);
512 au_writel(NAND_STTIME, MEM_STTIME1);
513 au_writel(NAND_STADDR, MEM_STADDR1);
514 } 469 }
515 if (NAND_CS == 2) { 470
516 au_writel(NAND_STCFG, MEM_STCFG2); 471 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
517 au_writel(NAND_STTIME, MEM_STTIME2); 472 if (!r) {
518 au_writel(NAND_STADDR, MEM_STADDR2); 473 dev_err(&pdev->dev, "no NAND memory resource\n");
474 ret = -ENODEV;
475 goto out1;
519 } 476 }
520 if (NAND_CS == 3) { 477 if (request_mem_region(r->start, resource_size(r), "au1550-nand")) {
521 au_writel(NAND_STCFG, MEM_STCFG3); 478 dev_err(&pdev->dev, "cannot claim NAND memory area\n");
522 au_writel(NAND_STTIME, MEM_STTIME3); 479 ret = -ENOMEM;
523 au_writel(NAND_STADDR, MEM_STADDR3); 480 goto out1;
524 } 481 }
525#endif 482
526 483 ctx->base = ioremap_nocache(r->start, 0x1000);
527 /* Locate NAND chip-select in order to determine NAND phys address */ 484 if (!ctx->base) {
528 mem_staddr = 0x00000000; 485 dev_err(&pdev->dev, "cannot remap NAND memory area\n");
529 if (((au_readl(MEM_STCFG0) & 0x7) == 0x5) && (NAND_CS == 0)) 486 ret = -ENODEV;
530 mem_staddr = au_readl(MEM_STADDR0); 487 goto out2;
531 else if (((au_readl(MEM_STCFG1) & 0x7) == 0x5) && (NAND_CS == 1))
532 mem_staddr = au_readl(MEM_STADDR1);
533 else if (((au_readl(MEM_STCFG2) & 0x7) == 0x5) && (NAND_CS == 2))
534 mem_staddr = au_readl(MEM_STADDR2);
535 else if (((au_readl(MEM_STCFG3) & 0x7) == 0x5) && (NAND_CS == 3))
536 mem_staddr = au_readl(MEM_STADDR3);
537
538 if (mem_staddr == 0x00000000) {
539 printk("Au1xxx NAND: ERROR WITH NAND CHIP-SELECT\n");
540 kfree(au1550_mtd);
541 return 1;
542 } 488 }
543 nand_phys = (mem_staddr << 4) & 0xFFFC0000;
544 489
545 p_nand = ioremap(nand_phys, 0x1000); 490 this = &ctx->chip;
491 ctx->info.priv = this;
492 ctx->info.owner = THIS_MODULE;
546 493
547 /* make controller and MTD agree */ 494 /* figure out which CS# r->start belongs to */
548 if (NAND_CS == 0) 495 cs = find_nand_cs(r->start);
549 nand_width = au_readl(MEM_STCFG0) & (1 << 22); 496 if (cs < 0) {
550 if (NAND_CS == 1) 497 dev_err(&pdev->dev, "cannot detect NAND chipselect\n");
551 nand_width = au_readl(MEM_STCFG1) & (1 << 22); 498 ret = -ENODEV;
552 if (NAND_CS == 2) 499 goto out3;
553 nand_width = au_readl(MEM_STCFG2) & (1 << 22); 500 }
554 if (NAND_CS == 3) 501 ctx->cs = cs;
555 nand_width = au_readl(MEM_STCFG3) & (1 << 22);
556 502
557 /* Set address of hardware control function */
558 this->dev_ready = au1550_device_ready; 503 this->dev_ready = au1550_device_ready;
559 this->select_chip = au1550_select_chip; 504 this->select_chip = au1550_select_chip;
560 this->cmdfunc = au1550_command; 505 this->cmdfunc = au1550_command;
@@ -565,54 +510,57 @@ static int __init au1xxx_nand_init(void)
565 510
566 this->options = NAND_NO_AUTOINCR; 511 this->options = NAND_NO_AUTOINCR;
567 512
568 if (!nand_width) 513 if (pd->devwidth)
569 this->options |= NAND_BUSWIDTH_16; 514 this->options |= NAND_BUSWIDTH_16;
570 515
571 this->read_byte = (!nand_width) ? au_read_byte16 : au_read_byte; 516 this->read_byte = (pd->devwidth) ? au_read_byte16 : au_read_byte;
572 au1550_write_byte = (!nand_width) ? au_write_byte16 : au_write_byte; 517 ctx->write_byte = (pd->devwidth) ? au_write_byte16 : au_write_byte;
573 this->read_word = au_read_word; 518 this->read_word = au_read_word;
574 this->write_buf = (!nand_width) ? au_write_buf16 : au_write_buf; 519 this->write_buf = (pd->devwidth) ? au_write_buf16 : au_write_buf;
575 this->read_buf = (!nand_width) ? au_read_buf16 : au_read_buf; 520 this->read_buf = (pd->devwidth) ? au_read_buf16 : au_read_buf;
576 this->verify_buf = (!nand_width) ? au_verify_buf16 : au_verify_buf; 521 this->verify_buf = (pd->devwidth) ? au_verify_buf16 : au_verify_buf;
577 522
578 /* Scan to find existence of the device */ 523 ret = nand_scan(&ctx->info, 1);
579 if (nand_scan(au1550_mtd, 1)) { 524 if (ret) {
580 retval = -ENXIO; 525 dev_err(&pdev->dev, "NAND scan failed with %d\n", ret);
581 goto outio; 526 goto out3;
582 } 527 }
583 528
584 /* Register the partitions */ 529 mtd_device_register(&ctx->info, pd->parts, pd->num_parts);
585 mtd_device_register(au1550_mtd, partition_info,
586 ARRAY_SIZE(partition_info));
587 530
588 return 0; 531 return 0;
589 532
590 outio: 533out3:
591 iounmap(p_nand); 534 iounmap(ctx->base);
592 535out2:
593 outmem: 536 release_mem_region(r->start, resource_size(r));
594 kfree(au1550_mtd); 537out1:
595 return retval; 538 kfree(ctx);
539 return ret;
596} 540}
597 541
598module_init(au1xxx_nand_init); 542static int __devexit au1550nd_remove(struct platform_device *pdev)
599
600/*
601 * Clean up routine
602 */
603static void __exit au1550_cleanup(void)
604{ 543{
605 /* Release resources, unregister device */ 544 struct au1550nd_ctx *ctx = platform_get_drvdata(pdev);
606 nand_release(au1550_mtd); 545 struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
607 546
608 /* Free the MTD device structure */ 547 nand_release(&ctx->info);
609 kfree(au1550_mtd); 548 iounmap(ctx->base);
610 549 release_mem_region(r->start, 0x1000);
611 /* Unmap */ 550 kfree(ctx);
612 iounmap(p_nand); 551 return 0;
613} 552}
614 553
615module_exit(au1550_cleanup); 554static struct platform_driver au1550nd_driver = {
555 .driver = {
556 .name = "au1550-nand",
557 .owner = THIS_MODULE,
558 },
559 .probe = au1550nd_probe,
560 .remove = __devexit_p(au1550nd_remove),
561};
562
563module_platform_driver(au1550nd_driver);
616 564
617MODULE_LICENSE("GPL"); 565MODULE_LICENSE("GPL");
618MODULE_AUTHOR("Embedded Edge, LLC"); 566MODULE_AUTHOR("Embedded Edge, LLC");
diff --git a/drivers/net/irda/Kconfig b/drivers/net/irda/Kconfig
index d423d18b4ad6..e535137eb2d0 100644
--- a/drivers/net/irda/Kconfig
+++ b/drivers/net/irda/Kconfig
@@ -313,8 +313,12 @@ config TOSHIBA_FIR
313 donauboe. 313 donauboe.
314 314
315config AU1000_FIR 315config AU1000_FIR
316 tristate "Alchemy Au1000 SIR/FIR" 316 tristate "Alchemy IrDA SIR/FIR"
317 depends on IRDA && MIPS_ALCHEMY 317 depends on IRDA && MIPS_ALCHEMY
318 help
319 Say Y/M here to build suppor the the IrDA peripheral on the
320 Alchemy Au1000 and Au1100 SoCs.
321 Say M to build a module; it will be called au1k_ir.ko
318 322
319config SMC_IRCC_FIR 323config SMC_IRCC_FIR
320 tristate "SMSC IrCC (EXPERIMENTAL)" 324 tristate "SMSC IrCC (EXPERIMENTAL)"
diff --git a/drivers/net/irda/au1000_ircc.h b/drivers/net/irda/au1000_ircc.h
deleted file mode 100644
index c072c09a8d91..000000000000
--- a/drivers/net/irda/au1000_ircc.h
+++ /dev/null
@@ -1,125 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Au1000 IrDA driver.
5 *
6 * Copyright 2001 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31#ifndef AU1000_IRCC_H
32#define AU1000_IRCC_H
33
34#include <linux/time.h>
35
36#include <linux/spinlock.h>
37#include <linux/pm.h>
38#include <asm/io.h>
39
40#define NUM_IR_IFF 1
41#define NUM_IR_DESC 64
42#define RING_SIZE_4 0x0
43#define RING_SIZE_16 0x3
44#define RING_SIZE_64 0xF
45#define MAX_NUM_IR_DESC 64
46#define MAX_BUF_SIZE 2048
47
48#define BPS_115200 0
49#define BPS_57600 1
50#define BPS_38400 2
51#define BPS_19200 5
52#define BPS_9600 11
53#define BPS_2400 47
54
55/* Ring descriptor flags */
56#define AU_OWN (1<<7) /* tx,rx */
57
58#define IR_DIS_CRC (1<<6) /* tx */
59#define IR_BAD_CRC (1<<5) /* tx */
60#define IR_NEED_PULSE (1<<4) /* tx */
61#define IR_FORCE_UNDER (1<<3) /* tx */
62#define IR_DISABLE_TX (1<<2) /* tx */
63#define IR_HW_UNDER (1<<0) /* tx */
64#define IR_TX_ERROR (IR_DIS_CRC|IR_BAD_CRC|IR_HW_UNDER)
65
66#define IR_PHY_ERROR (1<<6) /* rx */
67#define IR_CRC_ERROR (1<<5) /* rx */
68#define IR_MAX_LEN (1<<4) /* rx */
69#define IR_FIFO_OVER (1<<3) /* rx */
70#define IR_SIR_ERROR (1<<2) /* rx */
71#define IR_RX_ERROR (IR_PHY_ERROR|IR_CRC_ERROR| \
72 IR_MAX_LEN|IR_FIFO_OVER|IR_SIR_ERROR)
73
74typedef struct db_dest {
75 struct db_dest *pnext;
76 volatile u32 *vaddr;
77 dma_addr_t dma_addr;
78} db_dest_t;
79
80
81typedef struct ring_desc {
82 u8 count_0; /* 7:0 */
83 u8 count_1; /* 12:8 */
84 u8 reserved;
85 u8 flags;
86 u8 addr_0; /* 7:0 */
87 u8 addr_1; /* 15:8 */
88 u8 addr_2; /* 23:16 */
89 u8 addr_3; /* 31:24 */
90} ring_dest_t;
91
92
93/* Private data for each instance */
94struct au1k_private {
95
96 db_dest_t *pDBfree;
97 db_dest_t db[2*NUM_IR_DESC];
98 volatile ring_dest_t *rx_ring[NUM_IR_DESC];
99 volatile ring_dest_t *tx_ring[NUM_IR_DESC];
100 db_dest_t *rx_db_inuse[NUM_IR_DESC];
101 db_dest_t *tx_db_inuse[NUM_IR_DESC];
102 u32 rx_head;
103 u32 tx_head;
104 u32 tx_tail;
105 u32 tx_full;
106
107 iobuff_t rx_buff;
108
109 struct net_device *netdev;
110
111 struct timeval stamp;
112 struct timeval now;
113 struct qos_info qos;
114 struct irlap_cb *irlap;
115
116 u8 open;
117 u32 speed;
118 u32 newspeed;
119
120 u32 intr_work_done; /* number of Rx and Tx pkts processed in the isr */
121 struct timer_list timer;
122
123 spinlock_t lock; /* For serializing operations */
124};
125#endif /* AU1000_IRCC_H */
diff --git a/drivers/net/irda/au1k_ir.c b/drivers/net/irda/au1k_ir.c
index a3d696a9456a..fc503aa5288e 100644
--- a/drivers/net/irda/au1k_ir.c
+++ b/drivers/net/irda/au1k_ir.c
@@ -18,104 +18,220 @@
18 * with this program; if not, write to the Free Software Foundation, Inc., 18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 19 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 */ 20 */
21#include <linux/module.h> 21
22#include <linux/types.h>
23#include <linux/init.h> 22#include <linux/init.h>
24#include <linux/errno.h> 23#include <linux/module.h>
25#include <linux/netdevice.h> 24#include <linux/netdevice.h>
26#include <linux/slab.h>
27#include <linux/rtnetlink.h>
28#include <linux/interrupt.h> 25#include <linux/interrupt.h>
29#include <linux/pm.h> 26#include <linux/platform_device.h>
30#include <linux/bitops.h> 27#include <linux/slab.h>
31 28#include <linux/time.h>
32#include <asm/irq.h> 29#include <linux/types.h>
33#include <asm/io.h>
34#include <asm/au1000.h>
35#if defined(CONFIG_MIPS_PB1000) || defined(CONFIG_MIPS_PB1100)
36#include <asm/pb1000.h>
37#elif defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100)
38#include <asm/db1x00.h>
39#include <asm/mach-db1x00/bcsr.h>
40#else
41#error au1k_ir: unsupported board
42#endif
43 30
44#include <net/irda/irda.h> 31#include <net/irda/irda.h>
45#include <net/irda/irmod.h> 32#include <net/irda/irmod.h>
46#include <net/irda/wrapper.h> 33#include <net/irda/wrapper.h>
47#include <net/irda/irda_device.h> 34#include <net/irda/irda_device.h>
48#include "au1000_ircc.h" 35#include <asm/mach-au1x00/au1000.h>
36
37/* registers */
38#define IR_RING_PTR_STATUS 0x00
39#define IR_RING_BASE_ADDR_H 0x04
40#define IR_RING_BASE_ADDR_L 0x08
41#define IR_RING_SIZE 0x0C
42#define IR_RING_PROMPT 0x10
43#define IR_RING_ADDR_CMPR 0x14
44#define IR_INT_CLEAR 0x18
45#define IR_CONFIG_1 0x20
46#define IR_SIR_FLAGS 0x24
47#define IR_STATUS 0x28
48#define IR_READ_PHY_CONFIG 0x2C
49#define IR_WRITE_PHY_CONFIG 0x30
50#define IR_MAX_PKT_LEN 0x34
51#define IR_RX_BYTE_CNT 0x38
52#define IR_CONFIG_2 0x3C
53#define IR_ENABLE 0x40
54
55/* Config1 */
56#define IR_RX_INVERT_LED (1 << 0)
57#define IR_TX_INVERT_LED (1 << 1)
58#define IR_ST (1 << 2)
59#define IR_SF (1 << 3)
60#define IR_SIR (1 << 4)
61#define IR_MIR (1 << 5)
62#define IR_FIR (1 << 6)
63#define IR_16CRC (1 << 7)
64#define IR_TD (1 << 8)
65#define IR_RX_ALL (1 << 9)
66#define IR_DMA_ENABLE (1 << 10)
67#define IR_RX_ENABLE (1 << 11)
68#define IR_TX_ENABLE (1 << 12)
69#define IR_LOOPBACK (1 << 14)
70#define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \
71 IR_RX_ALL | IR_RX_ENABLE | IR_SF | \
72 IR_16CRC)
73
74/* ir_status */
75#define IR_RX_STATUS (1 << 9)
76#define IR_TX_STATUS (1 << 10)
77#define IR_PHYEN (1 << 15)
78
79/* ir_write_phy_config */
80#define IR_BR(x) (((x) & 0x3f) << 10) /* baud rate */
81#define IR_PW(x) (((x) & 0x1f) << 5) /* pulse width */
82#define IR_P(x) ((x) & 0x1f) /* preamble bits */
83
84/* Config2 */
85#define IR_MODE_INV (1 << 0)
86#define IR_ONE_PIN (1 << 1)
87#define IR_PHYCLK_40MHZ (0 << 2)
88#define IR_PHYCLK_48MHZ (1 << 2)
89#define IR_PHYCLK_56MHZ (2 << 2)
90#define IR_PHYCLK_64MHZ (3 << 2)
91#define IR_DP (1 << 4)
92#define IR_DA (1 << 5)
93#define IR_FLT_HIGH (0 << 6)
94#define IR_FLT_MEDHI (1 << 6)
95#define IR_FLT_MEDLO (2 << 6)
96#define IR_FLT_LO (3 << 6)
97#define IR_IEN (1 << 8)
98
99/* ir_enable */
100#define IR_HC (1 << 3) /* divide SBUS clock by 2 */
101#define IR_CE (1 << 2) /* clock enable */
102#define IR_C (1 << 1) /* coherency bit */
103#define IR_BE (1 << 0) /* set in big endian mode */
104
105#define NUM_IR_DESC 64
106#define RING_SIZE_4 0x0
107#define RING_SIZE_16 0x3
108#define RING_SIZE_64 0xF
109#define MAX_NUM_IR_DESC 64
110#define MAX_BUF_SIZE 2048
111
112/* Ring descriptor flags */
113#define AU_OWN (1 << 7) /* tx,rx */
114#define IR_DIS_CRC (1 << 6) /* tx */
115#define IR_BAD_CRC (1 << 5) /* tx */
116#define IR_NEED_PULSE (1 << 4) /* tx */
117#define IR_FORCE_UNDER (1 << 3) /* tx */
118#define IR_DISABLE_TX (1 << 2) /* tx */
119#define IR_HW_UNDER (1 << 0) /* tx */
120#define IR_TX_ERROR (IR_DIS_CRC | IR_BAD_CRC | IR_HW_UNDER)
121
122#define IR_PHY_ERROR (1 << 6) /* rx */
123#define IR_CRC_ERROR (1 << 5) /* rx */
124#define IR_MAX_LEN (1 << 4) /* rx */
125#define IR_FIFO_OVER (1 << 3) /* rx */
126#define IR_SIR_ERROR (1 << 2) /* rx */
127#define IR_RX_ERROR (IR_PHY_ERROR | IR_CRC_ERROR | \
128 IR_MAX_LEN | IR_FIFO_OVER | IR_SIR_ERROR)
129
130struct db_dest {
131 struct db_dest *pnext;
132 volatile u32 *vaddr;
133 dma_addr_t dma_addr;
134};
49 135
50static int au1k_irda_net_init(struct net_device *); 136struct ring_dest {
51static int au1k_irda_start(struct net_device *); 137 u8 count_0; /* 7:0 */
52static int au1k_irda_stop(struct net_device *dev); 138 u8 count_1; /* 12:8 */
53static int au1k_irda_hard_xmit(struct sk_buff *, struct net_device *); 139 u8 reserved;
54static int au1k_irda_rx(struct net_device *); 140 u8 flags;
55static void au1k_irda_interrupt(int, void *); 141 u8 addr_0; /* 7:0 */
56static void au1k_tx_timeout(struct net_device *); 142 u8 addr_1; /* 15:8 */
57static int au1k_irda_ioctl(struct net_device *, struct ifreq *, int); 143 u8 addr_2; /* 23:16 */
58static int au1k_irda_set_speed(struct net_device *dev, int speed); 144 u8 addr_3; /* 31:24 */
145};
59 146
60static void *dma_alloc(size_t, dma_addr_t *); 147/* Private data for each instance */
61static void dma_free(void *, size_t); 148struct au1k_private {
149 void __iomem *iobase;
150 int irq_rx, irq_tx;
151
152 struct db_dest *pDBfree;
153 struct db_dest db[2 * NUM_IR_DESC];
154 volatile struct ring_dest *rx_ring[NUM_IR_DESC];
155 volatile struct ring_dest *tx_ring[NUM_IR_DESC];
156 struct db_dest *rx_db_inuse[NUM_IR_DESC];
157 struct db_dest *tx_db_inuse[NUM_IR_DESC];
158 u32 rx_head;
159 u32 tx_head;
160 u32 tx_tail;
161 u32 tx_full;
162
163 iobuff_t rx_buff;
164
165 struct net_device *netdev;
166 struct timeval stamp;
167 struct timeval now;
168 struct qos_info qos;
169 struct irlap_cb *irlap;
170
171 u8 open;
172 u32 speed;
173 u32 newspeed;
174
175 struct timer_list timer;
176
177 struct resource *ioarea;
178 struct au1k_irda_platform_data *platdata;
179};
62 180
63static int qos_mtt_bits = 0x07; /* 1 ms or more */ 181static int qos_mtt_bits = 0x07; /* 1 ms or more */
64static struct net_device *ir_devs[NUM_IR_IFF];
65static char version[] __devinitdata =
66 "au1k_ircc:1.2 ppopov@mvista.com\n";
67 182
68#define RUN_AT(x) (jiffies + (x)) 183#define RUN_AT(x) (jiffies + (x))
69 184
70static DEFINE_SPINLOCK(ir_lock); 185static void au1k_irda_plat_set_phy_mode(struct au1k_private *p, int mode)
186{
187 if (p->platdata && p->platdata->set_phy_mode)
188 p->platdata->set_phy_mode(mode);
189}
71 190
72/* 191static inline unsigned long irda_read(struct au1k_private *p,
73 * IrDA peripheral bug. You have to read the register 192 unsigned long ofs)
74 * twice to get the right value. 193{
75 */ 194 /*
76u32 read_ir_reg(u32 addr) 195 * IrDA peripheral bug. You have to read the register
77{ 196 * twice to get the right value.
78 readl(addr); 197 */
79 return readl(addr); 198 (void)__raw_readl(p->iobase + ofs);
199 return __raw_readl(p->iobase + ofs);
80} 200}
81 201
202static inline void irda_write(struct au1k_private *p, unsigned long ofs,
203 unsigned long val)
204{
205 __raw_writel(val, p->iobase + ofs);
206 wmb();
207}
82 208
83/* 209/*
84 * Buffer allocation/deallocation routines. The buffer descriptor returned 210 * Buffer allocation/deallocation routines. The buffer descriptor returned
85 * has the virtual and dma address of a buffer suitable for 211 * has the virtual and dma address of a buffer suitable for
86 * both, receive and transmit operations. 212 * both, receive and transmit operations.
87 */ 213 */
88static db_dest_t *GetFreeDB(struct au1k_private *aup) 214static struct db_dest *GetFreeDB(struct au1k_private *aup)
89{ 215{
90 db_dest_t *pDB; 216 struct db_dest *db;
91 pDB = aup->pDBfree; 217 db = aup->pDBfree;
92
93 if (pDB) {
94 aup->pDBfree = pDB->pnext;
95 }
96 return pDB;
97}
98 218
99static void ReleaseDB(struct au1k_private *aup, db_dest_t *pDB) 219 if (db)
100{ 220 aup->pDBfree = db->pnext;
101 db_dest_t *pDBfree = aup->pDBfree; 221 return db;
102 if (pDBfree)
103 pDBfree->pnext = pDB;
104 aup->pDBfree = pDB;
105} 222}
106 223
107
108/* 224/*
109 DMA memory allocation, derived from pci_alloc_consistent. 225 DMA memory allocation, derived from pci_alloc_consistent.
110 However, the Au1000 data cache is coherent (when programmed 226 However, the Au1000 data cache is coherent (when programmed
111 so), therefore we return KSEG0 address, not KSEG1. 227 so), therefore we return KSEG0 address, not KSEG1.
112*/ 228*/
113static void *dma_alloc(size_t size, dma_addr_t * dma_handle) 229static void *dma_alloc(size_t size, dma_addr_t *dma_handle)
114{ 230{
115 void *ret; 231 void *ret;
116 int gfp = GFP_ATOMIC | GFP_DMA; 232 int gfp = GFP_ATOMIC | GFP_DMA;
117 233
118 ret = (void *) __get_free_pages(gfp, get_order(size)); 234 ret = (void *)__get_free_pages(gfp, get_order(size));
119 235
120 if (ret != NULL) { 236 if (ret != NULL) {
121 memset(ret, 0, size); 237 memset(ret, 0, size);
@@ -125,7 +241,6 @@ static void *dma_alloc(size_t size, dma_addr_t * dma_handle)
125 return ret; 241 return ret;
126} 242}
127 243
128
129static void dma_free(void *vaddr, size_t size) 244static void dma_free(void *vaddr, size_t size)
130{ 245{
131 vaddr = (void *)KSEG0ADDR(vaddr); 246 vaddr = (void *)KSEG0ADDR(vaddr);
@@ -133,206 +248,306 @@ static void dma_free(void *vaddr, size_t size)
133} 248}
134 249
135 250
136static void 251static void setup_hw_rings(struct au1k_private *aup, u32 rx_base, u32 tx_base)
137setup_hw_rings(struct au1k_private *aup, u32 rx_base, u32 tx_base)
138{ 252{
139 int i; 253 int i;
140 for (i=0; i<NUM_IR_DESC; i++) { 254 for (i = 0; i < NUM_IR_DESC; i++) {
141 aup->rx_ring[i] = (volatile ring_dest_t *) 255 aup->rx_ring[i] = (volatile struct ring_dest *)
142 (rx_base + sizeof(ring_dest_t)*i); 256 (rx_base + sizeof(struct ring_dest) * i);
143 } 257 }
144 for (i=0; i<NUM_IR_DESC; i++) { 258 for (i = 0; i < NUM_IR_DESC; i++) {
145 aup->tx_ring[i] = (volatile ring_dest_t *) 259 aup->tx_ring[i] = (volatile struct ring_dest *)
146 (tx_base + sizeof(ring_dest_t)*i); 260 (tx_base + sizeof(struct ring_dest) * i);
147 } 261 }
148} 262}
149 263
150static int au1k_irda_init(void)
151{
152 static unsigned version_printed = 0;
153 struct au1k_private *aup;
154 struct net_device *dev;
155 int err;
156
157 if (version_printed++ == 0) printk(version);
158
159 dev = alloc_irdadev(sizeof(struct au1k_private));
160 if (!dev)
161 return -ENOMEM;
162
163 dev->irq = AU1000_IRDA_RX_INT; /* TX has its own interrupt */
164 err = au1k_irda_net_init(dev);
165 if (err)
166 goto out;
167 err = register_netdev(dev);
168 if (err)
169 goto out1;
170 ir_devs[0] = dev;
171 printk(KERN_INFO "IrDA: Registered device %s\n", dev->name);
172 return 0;
173
174out1:
175 aup = netdev_priv(dev);
176 dma_free((void *)aup->db[0].vaddr,
177 MAX_BUF_SIZE * 2*NUM_IR_DESC);
178 dma_free((void *)aup->rx_ring[0],
179 2 * MAX_NUM_IR_DESC*(sizeof(ring_dest_t)));
180 kfree(aup->rx_buff.head);
181out:
182 free_netdev(dev);
183 return err;
184}
185
186static int au1k_irda_init_iobuf(iobuff_t *io, int size) 264static int au1k_irda_init_iobuf(iobuff_t *io, int size)
187{ 265{
188 io->head = kmalloc(size, GFP_KERNEL); 266 io->head = kmalloc(size, GFP_KERNEL);
189 if (io->head != NULL) { 267 if (io->head != NULL) {
190 io->truesize = size; 268 io->truesize = size;
191 io->in_frame = FALSE; 269 io->in_frame = FALSE;
192 io->state = OUTSIDE_FRAME; 270 io->state = OUTSIDE_FRAME;
193 io->data = io->head; 271 io->data = io->head;
194 } 272 }
195 return io->head ? 0 : -ENOMEM; 273 return io->head ? 0 : -ENOMEM;
196} 274}
197 275
198static const struct net_device_ops au1k_irda_netdev_ops = { 276/*
199 .ndo_open = au1k_irda_start, 277 * Set the IrDA communications speed.
200 .ndo_stop = au1k_irda_stop, 278 */
201 .ndo_start_xmit = au1k_irda_hard_xmit, 279static int au1k_irda_set_speed(struct net_device *dev, int speed)
202 .ndo_tx_timeout = au1k_tx_timeout,
203 .ndo_do_ioctl = au1k_irda_ioctl,
204};
205
206static int au1k_irda_net_init(struct net_device *dev)
207{ 280{
208 struct au1k_private *aup = netdev_priv(dev); 281 struct au1k_private *aup = netdev_priv(dev);
209 int i, retval = 0, err; 282 volatile struct ring_dest *ptxd;
210 db_dest_t *pDB, *pDBfree; 283 unsigned long control;
211 dma_addr_t temp; 284 int ret = 0, timeout = 10, i;
212 285
213 err = au1k_irda_init_iobuf(&aup->rx_buff, 14384); 286 if (speed == aup->speed)
214 if (err) 287 return ret;
215 goto out1;
216 288
217 dev->netdev_ops = &au1k_irda_netdev_ops; 289 /* disable PHY first */
290 au1k_irda_plat_set_phy_mode(aup, AU1000_IRDA_PHY_MODE_OFF);
291 irda_write(aup, IR_STATUS, irda_read(aup, IR_STATUS) & ~IR_PHYEN);
218 292
219 irda_init_max_qos_capabilies(&aup->qos); 293 /* disable RX/TX */
294 irda_write(aup, IR_CONFIG_1,
295 irda_read(aup, IR_CONFIG_1) & ~(IR_RX_ENABLE | IR_TX_ENABLE));
296 msleep(20);
297 while (irda_read(aup, IR_STATUS) & (IR_RX_STATUS | IR_TX_STATUS)) {
298 msleep(20);
299 if (!timeout--) {
300 printk(KERN_ERR "%s: rx/tx disable timeout\n",
301 dev->name);
302 break;
303 }
304 }
220 305
221 /* The only value we must override it the baudrate */ 306 /* disable DMA */
222 aup->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600| 307 irda_write(aup, IR_CONFIG_1,
223 IR_115200|IR_576000 |(IR_4000000 << 8); 308 irda_read(aup, IR_CONFIG_1) & ~IR_DMA_ENABLE);
224 309 msleep(20);
225 aup->qos.min_turn_time.bits = qos_mtt_bits;
226 irda_qos_bits_to_value(&aup->qos);
227 310
228 retval = -ENOMEM; 311 /* After we disable tx/rx. the index pointers go back to zero. */
312 aup->tx_head = aup->tx_tail = aup->rx_head = 0;
313 for (i = 0; i < NUM_IR_DESC; i++) {
314 ptxd = aup->tx_ring[i];
315 ptxd->flags = 0;
316 ptxd->count_0 = 0;
317 ptxd->count_1 = 0;
318 }
229 319
230 /* Tx ring follows rx ring + 512 bytes */ 320 for (i = 0; i < NUM_IR_DESC; i++) {
231 /* we need a 1k aligned buffer */ 321 ptxd = aup->rx_ring[i];
232 aup->rx_ring[0] = (ring_dest_t *) 322 ptxd->count_0 = 0;
233 dma_alloc(2*MAX_NUM_IR_DESC*(sizeof(ring_dest_t)), &temp); 323 ptxd->count_1 = 0;
234 if (!aup->rx_ring[0]) 324 ptxd->flags = AU_OWN;
235 goto out2; 325 }
236 326
237 /* allocate the data buffers */ 327 if (speed == 4000000)
238 aup->db[0].vaddr = 328 au1k_irda_plat_set_phy_mode(aup, AU1000_IRDA_PHY_MODE_FIR);
239 (void *)dma_alloc(MAX_BUF_SIZE * 2*NUM_IR_DESC, &temp); 329 else
240 if (!aup->db[0].vaddr) 330 au1k_irda_plat_set_phy_mode(aup, AU1000_IRDA_PHY_MODE_SIR);
241 goto out3;
242 331
243 setup_hw_rings(aup, (u32)aup->rx_ring[0], (u32)aup->rx_ring[0] + 512); 332 switch (speed) {
333 case 9600:
334 irda_write(aup, IR_WRITE_PHY_CONFIG, IR_BR(11) | IR_PW(12));
335 irda_write(aup, IR_CONFIG_1, IR_SIR_MODE);
336 break;
337 case 19200:
338 irda_write(aup, IR_WRITE_PHY_CONFIG, IR_BR(5) | IR_PW(12));
339 irda_write(aup, IR_CONFIG_1, IR_SIR_MODE);
340 break;
341 case 38400:
342 irda_write(aup, IR_WRITE_PHY_CONFIG, IR_BR(2) | IR_PW(12));
343 irda_write(aup, IR_CONFIG_1, IR_SIR_MODE);
344 break;
345 case 57600:
346 irda_write(aup, IR_WRITE_PHY_CONFIG, IR_BR(1) | IR_PW(12));
347 irda_write(aup, IR_CONFIG_1, IR_SIR_MODE);
348 break;
349 case 115200:
350 irda_write(aup, IR_WRITE_PHY_CONFIG, IR_PW(12));
351 irda_write(aup, IR_CONFIG_1, IR_SIR_MODE);
352 break;
353 case 4000000:
354 irda_write(aup, IR_WRITE_PHY_CONFIG, IR_P(15));
355 irda_write(aup, IR_CONFIG_1, IR_FIR | IR_DMA_ENABLE |
356 IR_RX_ENABLE);
357 break;
358 default:
359 printk(KERN_ERR "%s unsupported speed %x\n", dev->name, speed);
360 ret = -EINVAL;
361 break;
362 }
244 363
245 pDBfree = NULL; 364 aup->speed = speed;
246 pDB = aup->db; 365 irda_write(aup, IR_STATUS, irda_read(aup, IR_STATUS) | IR_PHYEN);
247 for (i=0; i<(2*NUM_IR_DESC); i++) { 366
248 pDB->pnext = pDBfree; 367 control = irda_read(aup, IR_STATUS);
249 pDBfree = pDB; 368 irda_write(aup, IR_RING_PROMPT, 0);
250 pDB->vaddr = 369
251 (u32 *)((unsigned)aup->db[0].vaddr + MAX_BUF_SIZE*i); 370 if (control & (1 << 14)) {
252 pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr); 371 printk(KERN_ERR "%s: configuration error\n", dev->name);
253 pDB++; 372 } else {
373 if (control & (1 << 11))
374 printk(KERN_DEBUG "%s Valid SIR config\n", dev->name);
375 if (control & (1 << 12))
376 printk(KERN_DEBUG "%s Valid MIR config\n", dev->name);
377 if (control & (1 << 13))
378 printk(KERN_DEBUG "%s Valid FIR config\n", dev->name);
379 if (control & (1 << 10))
380 printk(KERN_DEBUG "%s TX enabled\n", dev->name);
381 if (control & (1 << 9))
382 printk(KERN_DEBUG "%s RX enabled\n", dev->name);
254 } 383 }
255 aup->pDBfree = pDBfree;
256 384
257 /* attach a data buffer to each descriptor */ 385 return ret;
258 for (i=0; i<NUM_IR_DESC; i++) { 386}
259 pDB = GetFreeDB(aup); 387
260 if (!pDB) goto out; 388static void update_rx_stats(struct net_device *dev, u32 status, u32 count)
261 aup->rx_ring[i]->addr_0 = (u8)(pDB->dma_addr & 0xff); 389{
262 aup->rx_ring[i]->addr_1 = (u8)((pDB->dma_addr>>8) & 0xff); 390 struct net_device_stats *ps = &dev->stats;
263 aup->rx_ring[i]->addr_2 = (u8)((pDB->dma_addr>>16) & 0xff); 391
264 aup->rx_ring[i]->addr_3 = (u8)((pDB->dma_addr>>24) & 0xff); 392 ps->rx_packets++;
265 aup->rx_db_inuse[i] = pDB; 393
394 if (status & IR_RX_ERROR) {
395 ps->rx_errors++;
396 if (status & (IR_PHY_ERROR | IR_FIFO_OVER))
397 ps->rx_missed_errors++;
398 if (status & IR_MAX_LEN)
399 ps->rx_length_errors++;
400 if (status & IR_CRC_ERROR)
401 ps->rx_crc_errors++;
402 } else
403 ps->rx_bytes += count;
404}
405
406static void update_tx_stats(struct net_device *dev, u32 status, u32 pkt_len)
407{
408 struct net_device_stats *ps = &dev->stats;
409
410 ps->tx_packets++;
411 ps->tx_bytes += pkt_len;
412
413 if (status & IR_TX_ERROR) {
414 ps->tx_errors++;
415 ps->tx_aborted_errors++;
266 } 416 }
267 for (i=0; i<NUM_IR_DESC; i++) { 417}
268 pDB = GetFreeDB(aup); 418
269 if (!pDB) goto out; 419static void au1k_tx_ack(struct net_device *dev)
270 aup->tx_ring[i]->addr_0 = (u8)(pDB->dma_addr & 0xff); 420{
271 aup->tx_ring[i]->addr_1 = (u8)((pDB->dma_addr>>8) & 0xff); 421 struct au1k_private *aup = netdev_priv(dev);
272 aup->tx_ring[i]->addr_2 = (u8)((pDB->dma_addr>>16) & 0xff); 422 volatile struct ring_dest *ptxd;
273 aup->tx_ring[i]->addr_3 = (u8)((pDB->dma_addr>>24) & 0xff); 423
274 aup->tx_ring[i]->count_0 = 0; 424 ptxd = aup->tx_ring[aup->tx_tail];
275 aup->tx_ring[i]->count_1 = 0; 425 while (!(ptxd->flags & AU_OWN) && (aup->tx_tail != aup->tx_head)) {
276 aup->tx_ring[i]->flags = 0; 426 update_tx_stats(dev, ptxd->flags,
277 aup->tx_db_inuse[i] = pDB; 427 (ptxd->count_1 << 8) | ptxd->count_0);
428 ptxd->count_0 = 0;
429 ptxd->count_1 = 0;
430 wmb();
431 aup->tx_tail = (aup->tx_tail + 1) & (NUM_IR_DESC - 1);
432 ptxd = aup->tx_ring[aup->tx_tail];
433
434 if (aup->tx_full) {
435 aup->tx_full = 0;
436 netif_wake_queue(dev);
437 }
278 } 438 }
279 439
280#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) 440 if (aup->tx_tail == aup->tx_head) {
281 /* power on */ 441 if (aup->newspeed) {
282 bcsr_mod(BCSR_RESETS, BCSR_RESETS_IRDA_MODE_MASK, 442 au1k_irda_set_speed(dev, aup->newspeed);
283 BCSR_RESETS_IRDA_MODE_FULL); 443 aup->newspeed = 0;
284#endif 444 } else {
445 irda_write(aup, IR_CONFIG_1,
446 irda_read(aup, IR_CONFIG_1) & ~IR_TX_ENABLE);
447 irda_write(aup, IR_CONFIG_1,
448 irda_read(aup, IR_CONFIG_1) | IR_RX_ENABLE);
449 irda_write(aup, IR_RING_PROMPT, 0);
450 }
451 }
452}
285 453
286 return 0; 454static int au1k_irda_rx(struct net_device *dev)
455{
456 struct au1k_private *aup = netdev_priv(dev);
457 volatile struct ring_dest *prxd;
458 struct sk_buff *skb;
459 struct db_dest *pDB;
460 u32 flags, count;
287 461
288out3: 462 prxd = aup->rx_ring[aup->rx_head];
289 dma_free((void *)aup->rx_ring[0], 463 flags = prxd->flags;
290 2 * MAX_NUM_IR_DESC*(sizeof(ring_dest_t))); 464
291out2: 465 while (!(flags & AU_OWN)) {
292 kfree(aup->rx_buff.head); 466 pDB = aup->rx_db_inuse[aup->rx_head];
293out1: 467 count = (prxd->count_1 << 8) | prxd->count_0;
294 printk(KERN_ERR "au1k_init_module failed. Returns %d\n", retval); 468 if (!(flags & IR_RX_ERROR)) {
295 return retval; 469 /* good frame */
470 update_rx_stats(dev, flags, count);
471 skb = alloc_skb(count + 1, GFP_ATOMIC);
472 if (skb == NULL) {
473 dev->stats.rx_dropped++;
474 continue;
475 }
476 skb_reserve(skb, 1);
477 if (aup->speed == 4000000)
478 skb_put(skb, count);
479 else
480 skb_put(skb, count - 2);
481 skb_copy_to_linear_data(skb, (void *)pDB->vaddr,
482 count - 2);
483 skb->dev = dev;
484 skb_reset_mac_header(skb);
485 skb->protocol = htons(ETH_P_IRDA);
486 netif_rx(skb);
487 prxd->count_0 = 0;
488 prxd->count_1 = 0;
489 }
490 prxd->flags |= AU_OWN;
491 aup->rx_head = (aup->rx_head + 1) & (NUM_IR_DESC - 1);
492 irda_write(aup, IR_RING_PROMPT, 0);
493
494 /* next descriptor */
495 prxd = aup->rx_ring[aup->rx_head];
496 flags = prxd->flags;
497
498 }
499 return 0;
296} 500}
297 501
502static irqreturn_t au1k_irda_interrupt(int dummy, void *dev_id)
503{
504 struct net_device *dev = dev_id;
505 struct au1k_private *aup = netdev_priv(dev);
506
507 irda_write(aup, IR_INT_CLEAR, 0); /* ack irda interrupts */
508
509 au1k_irda_rx(dev);
510 au1k_tx_ack(dev);
511
512 return IRQ_HANDLED;
513}
298 514
299static int au1k_init(struct net_device *dev) 515static int au1k_init(struct net_device *dev)
300{ 516{
301 struct au1k_private *aup = netdev_priv(dev); 517 struct au1k_private *aup = netdev_priv(dev);
518 u32 enable, ring_address;
302 int i; 519 int i;
303 u32 control;
304 u32 ring_address;
305 520
306 /* bring the device out of reset */ 521 enable = IR_HC | IR_CE | IR_C;
307 control = 0xe; /* coherent, clock enable, one half system clock */
308
309#ifndef CONFIG_CPU_LITTLE_ENDIAN 522#ifndef CONFIG_CPU_LITTLE_ENDIAN
310 control |= 1; 523 enable |= IR_BE;
311#endif 524#endif
312 aup->tx_head = 0; 525 aup->tx_head = 0;
313 aup->tx_tail = 0; 526 aup->tx_tail = 0;
314 aup->rx_head = 0; 527 aup->rx_head = 0;
315 528
316 for (i=0; i<NUM_IR_DESC; i++) { 529 for (i = 0; i < NUM_IR_DESC; i++)
317 aup->rx_ring[i]->flags = AU_OWN; 530 aup->rx_ring[i]->flags = AU_OWN;
318 }
319 531
320 writel(control, IR_INTERFACE_CONFIG); 532 irda_write(aup, IR_ENABLE, enable);
321 au_sync_delay(10); 533 msleep(20);
322 534
323 writel(read_ir_reg(IR_ENABLE) & ~0x8000, IR_ENABLE); /* disable PHY */ 535 /* disable PHY */
324 au_sync_delay(1); 536 au1k_irda_plat_set_phy_mode(aup, AU1000_IRDA_PHY_MODE_OFF);
537 irda_write(aup, IR_STATUS, irda_read(aup, IR_STATUS) & ~IR_PHYEN);
538 msleep(20);
325 539
326 writel(MAX_BUF_SIZE, IR_MAX_PKT_LEN); 540 irda_write(aup, IR_MAX_PKT_LEN, MAX_BUF_SIZE);
327 541
328 ring_address = (u32)virt_to_phys((void *)aup->rx_ring[0]); 542 ring_address = (u32)virt_to_phys((void *)aup->rx_ring[0]);
329 writel(ring_address >> 26, IR_RING_BASE_ADDR_H); 543 irda_write(aup, IR_RING_BASE_ADDR_H, ring_address >> 26);
330 writel((ring_address >> 10) & 0xffff, IR_RING_BASE_ADDR_L); 544 irda_write(aup, IR_RING_BASE_ADDR_L, (ring_address >> 10) & 0xffff);
331 545
332 writel(RING_SIZE_64<<8 | RING_SIZE_64<<12, IR_RING_SIZE); 546 irda_write(aup, IR_RING_SIZE,
547 (RING_SIZE_64 << 8) | (RING_SIZE_64 << 12));
333 548
334 writel(1<<2 | IR_ONE_PIN, IR_CONFIG_2); /* 48MHz */ 549 irda_write(aup, IR_CONFIG_2, IR_PHYCLK_48MHZ | IR_ONE_PIN);
335 writel(0, IR_RING_ADDR_CMPR); 550 irda_write(aup, IR_RING_ADDR_CMPR, 0);
336 551
337 au1k_irda_set_speed(dev, 9600); 552 au1k_irda_set_speed(dev, 9600);
338 return 0; 553 return 0;
@@ -340,25 +555,28 @@ static int au1k_init(struct net_device *dev)
340 555
341static int au1k_irda_start(struct net_device *dev) 556static int au1k_irda_start(struct net_device *dev)
342{ 557{
343 int retval;
344 char hwname[32];
345 struct au1k_private *aup = netdev_priv(dev); 558 struct au1k_private *aup = netdev_priv(dev);
559 char hwname[32];
560 int retval;
346 561
347 if ((retval = au1k_init(dev))) { 562 retval = au1k_init(dev);
563 if (retval) {
348 printk(KERN_ERR "%s: error in au1k_init\n", dev->name); 564 printk(KERN_ERR "%s: error in au1k_init\n", dev->name);
349 return retval; 565 return retval;
350 } 566 }
351 567
352 if ((retval = request_irq(AU1000_IRDA_TX_INT, au1k_irda_interrupt, 568 retval = request_irq(aup->irq_tx, &au1k_irda_interrupt, 0,
353 0, dev->name, dev))) { 569 dev->name, dev);
354 printk(KERN_ERR "%s: unable to get IRQ %d\n", 570 if (retval) {
571 printk(KERN_ERR "%s: unable to get IRQ %d\n",
355 dev->name, dev->irq); 572 dev->name, dev->irq);
356 return retval; 573 return retval;
357 } 574 }
358 if ((retval = request_irq(AU1000_IRDA_RX_INT, au1k_irda_interrupt, 575 retval = request_irq(aup->irq_rx, &au1k_irda_interrupt, 0,
359 0, dev->name, dev))) { 576 dev->name, dev);
360 free_irq(AU1000_IRDA_TX_INT, dev); 577 if (retval) {
361 printk(KERN_ERR "%s: unable to get IRQ %d\n", 578 free_irq(aup->irq_tx, dev);
579 printk(KERN_ERR "%s: unable to get IRQ %d\n",
362 dev->name, dev->irq); 580 dev->name, dev->irq);
363 return retval; 581 return retval;
364 } 582 }
@@ -368,9 +586,13 @@ static int au1k_irda_start(struct net_device *dev)
368 aup->irlap = irlap_open(dev, &aup->qos, hwname); 586 aup->irlap = irlap_open(dev, &aup->qos, hwname);
369 netif_start_queue(dev); 587 netif_start_queue(dev);
370 588
371 writel(read_ir_reg(IR_CONFIG_2) | 1<<8, IR_CONFIG_2); /* int enable */ 589 /* int enable */
590 irda_write(aup, IR_CONFIG_2, irda_read(aup, IR_CONFIG_2) | IR_IEN);
591
592 /* power up */
593 au1k_irda_plat_set_phy_mode(aup, AU1000_IRDA_PHY_MODE_SIR);
372 594
373 aup->timer.expires = RUN_AT((3*HZ)); 595 aup->timer.expires = RUN_AT((3 * HZ));
374 aup->timer.data = (unsigned long)dev; 596 aup->timer.data = (unsigned long)dev;
375 return 0; 597 return 0;
376} 598}
@@ -379,11 +601,12 @@ static int au1k_irda_stop(struct net_device *dev)
379{ 601{
380 struct au1k_private *aup = netdev_priv(dev); 602 struct au1k_private *aup = netdev_priv(dev);
381 603
604 au1k_irda_plat_set_phy_mode(aup, AU1000_IRDA_PHY_MODE_OFF);
605
382 /* disable interrupts */ 606 /* disable interrupts */
383 writel(read_ir_reg(IR_CONFIG_2) & ~(1<<8), IR_CONFIG_2); 607 irda_write(aup, IR_CONFIG_2, irda_read(aup, IR_CONFIG_2) & ~IR_IEN);
384 writel(0, IR_CONFIG_1); 608 irda_write(aup, IR_CONFIG_1, 0);
385 writel(0, IR_INTERFACE_CONFIG); /* disable clock */ 609 irda_write(aup, IR_ENABLE, 0); /* disable clock */
386 au_sync();
387 610
388 if (aup->irlap) { 611 if (aup->irlap) {
389 irlap_close(aup->irlap); 612 irlap_close(aup->irlap);
@@ -394,83 +617,12 @@ static int au1k_irda_stop(struct net_device *dev)
394 del_timer(&aup->timer); 617 del_timer(&aup->timer);
395 618
396 /* disable the interrupt */ 619 /* disable the interrupt */
397 free_irq(AU1000_IRDA_TX_INT, dev); 620 free_irq(aup->irq_tx, dev);
398 free_irq(AU1000_IRDA_RX_INT, dev); 621 free_irq(aup->irq_rx, dev);
399 return 0;
400}
401
402static void __exit au1k_irda_exit(void)
403{
404 struct net_device *dev = ir_devs[0];
405 struct au1k_private *aup = netdev_priv(dev);
406 622
407 unregister_netdev(dev); 623 return 0;
408
409 dma_free((void *)aup->db[0].vaddr,
410 MAX_BUF_SIZE * 2*NUM_IR_DESC);
411 dma_free((void *)aup->rx_ring[0],
412 2 * MAX_NUM_IR_DESC*(sizeof(ring_dest_t)));
413 kfree(aup->rx_buff.head);
414 free_netdev(dev);
415}
416
417
418static inline void
419update_tx_stats(struct net_device *dev, u32 status, u32 pkt_len)
420{
421 struct au1k_private *aup = netdev_priv(dev);
422 struct net_device_stats *ps = &aup->stats;
423
424 ps->tx_packets++;
425 ps->tx_bytes += pkt_len;
426
427 if (status & IR_TX_ERROR) {
428 ps->tx_errors++;
429 ps->tx_aborted_errors++;
430 }
431}
432
433
434static void au1k_tx_ack(struct net_device *dev)
435{
436 struct au1k_private *aup = netdev_priv(dev);
437 volatile ring_dest_t *ptxd;
438
439 ptxd = aup->tx_ring[aup->tx_tail];
440 while (!(ptxd->flags & AU_OWN) && (aup->tx_tail != aup->tx_head)) {
441 update_tx_stats(dev, ptxd->flags,
442 ptxd->count_1<<8 | ptxd->count_0);
443 ptxd->count_0 = 0;
444 ptxd->count_1 = 0;
445 au_sync();
446
447 aup->tx_tail = (aup->tx_tail + 1) & (NUM_IR_DESC - 1);
448 ptxd = aup->tx_ring[aup->tx_tail];
449
450 if (aup->tx_full) {
451 aup->tx_full = 0;
452 netif_wake_queue(dev);
453 }
454 }
455
456 if (aup->tx_tail == aup->tx_head) {
457 if (aup->newspeed) {
458 au1k_irda_set_speed(dev, aup->newspeed);
459 aup->newspeed = 0;
460 }
461 else {
462 writel(read_ir_reg(IR_CONFIG_1) & ~IR_TX_ENABLE,
463 IR_CONFIG_1);
464 au_sync();
465 writel(read_ir_reg(IR_CONFIG_1) | IR_RX_ENABLE,
466 IR_CONFIG_1);
467 writel(0, IR_RING_PROMPT);
468 au_sync();
469 }
470 }
471} 624}
472 625
473
474/* 626/*
475 * Au1000 transmit routine. 627 * Au1000 transmit routine.
476 */ 628 */
@@ -478,15 +630,12 @@ static int au1k_irda_hard_xmit(struct sk_buff *skb, struct net_device *dev)
478{ 630{
479 struct au1k_private *aup = netdev_priv(dev); 631 struct au1k_private *aup = netdev_priv(dev);
480 int speed = irda_get_next_speed(skb); 632 int speed = irda_get_next_speed(skb);
481 volatile ring_dest_t *ptxd; 633 volatile struct ring_dest *ptxd;
482 u32 len; 634 struct db_dest *pDB;
483 635 u32 len, flags;
484 u32 flags;
485 db_dest_t *pDB;
486 636
487 if (speed != aup->speed && speed != -1) { 637 if (speed != aup->speed && speed != -1)
488 aup->newspeed = speed; 638 aup->newspeed = speed;
489 }
490 639
491 if ((skb->len == 0) && (aup->newspeed)) { 640 if ((skb->len == 0) && (aup->newspeed)) {
492 if (aup->tx_tail == aup->tx_head) { 641 if (aup->tx_tail == aup->tx_head) {
@@ -504,138 +653,47 @@ static int au1k_irda_hard_xmit(struct sk_buff *skb, struct net_device *dev)
504 printk(KERN_DEBUG "%s: tx_full\n", dev->name); 653 printk(KERN_DEBUG "%s: tx_full\n", dev->name);
505 netif_stop_queue(dev); 654 netif_stop_queue(dev);
506 aup->tx_full = 1; 655 aup->tx_full = 1;
507 return NETDEV_TX_BUSY; 656 return 1;
508 } 657 } else if (((aup->tx_head + 1) & (NUM_IR_DESC - 1)) == aup->tx_tail) {
509 else if (((aup->tx_head + 1) & (NUM_IR_DESC - 1)) == aup->tx_tail) {
510 printk(KERN_DEBUG "%s: tx_full\n", dev->name); 658 printk(KERN_DEBUG "%s: tx_full\n", dev->name);
511 netif_stop_queue(dev); 659 netif_stop_queue(dev);
512 aup->tx_full = 1; 660 aup->tx_full = 1;
513 return NETDEV_TX_BUSY; 661 return 1;
514 } 662 }
515 663
516 pDB = aup->tx_db_inuse[aup->tx_head]; 664 pDB = aup->tx_db_inuse[aup->tx_head];
517 665
518#if 0 666#if 0
519 if (read_ir_reg(IR_RX_BYTE_CNT) != 0) { 667 if (irda_read(aup, IR_RX_BYTE_CNT) != 0) {
520 printk("tx warning: rx byte cnt %x\n", 668 printk(KERN_DEBUG "tx warning: rx byte cnt %x\n",
521 read_ir_reg(IR_RX_BYTE_CNT)); 669 irda_read(aup, IR_RX_BYTE_CNT));
522 } 670 }
523#endif 671#endif
524 672
525 if (aup->speed == 4000000) { 673 if (aup->speed == 4000000) {
526 /* FIR */ 674 /* FIR */
527 skb_copy_from_linear_data(skb, pDB->vaddr, skb->len); 675 skb_copy_from_linear_data(skb, (void *)pDB->vaddr, skb->len);
528 ptxd->count_0 = skb->len & 0xff; 676 ptxd->count_0 = skb->len & 0xff;
529 ptxd->count_1 = (skb->len >> 8) & 0xff; 677 ptxd->count_1 = (skb->len >> 8) & 0xff;
530 678 } else {
531 }
532 else {
533 /* SIR */ 679 /* SIR */
534 len = async_wrap_skb(skb, (u8 *)pDB->vaddr, MAX_BUF_SIZE); 680 len = async_wrap_skb(skb, (u8 *)pDB->vaddr, MAX_BUF_SIZE);
535 ptxd->count_0 = len & 0xff; 681 ptxd->count_0 = len & 0xff;
536 ptxd->count_1 = (len >> 8) & 0xff; 682 ptxd->count_1 = (len >> 8) & 0xff;
537 ptxd->flags |= IR_DIS_CRC; 683 ptxd->flags |= IR_DIS_CRC;
538 au_writel(au_readl(0xae00000c) & ~(1<<13), 0xae00000c);
539 } 684 }
540 ptxd->flags |= AU_OWN; 685 ptxd->flags |= AU_OWN;
541 au_sync(); 686 wmb();
542 687
543 writel(read_ir_reg(IR_CONFIG_1) | IR_TX_ENABLE, IR_CONFIG_1); 688 irda_write(aup, IR_CONFIG_1,
544 writel(0, IR_RING_PROMPT); 689 irda_read(aup, IR_CONFIG_1) | IR_TX_ENABLE);
545 au_sync(); 690 irda_write(aup, IR_RING_PROMPT, 0);
546 691
547 dev_kfree_skb(skb); 692 dev_kfree_skb(skb);
548 aup->tx_head = (aup->tx_head + 1) & (NUM_IR_DESC - 1); 693 aup->tx_head = (aup->tx_head + 1) & (NUM_IR_DESC - 1);
549 return NETDEV_TX_OK; 694 return NETDEV_TX_OK;
550} 695}
551 696
552
553static inline void
554update_rx_stats(struct net_device *dev, u32 status, u32 count)
555{
556 struct au1k_private *aup = netdev_priv(dev);
557 struct net_device_stats *ps = &aup->stats;
558
559 ps->rx_packets++;
560
561 if (status & IR_RX_ERROR) {
562 ps->rx_errors++;
563 if (status & (IR_PHY_ERROR|IR_FIFO_OVER))
564 ps->rx_missed_errors++;
565 if (status & IR_MAX_LEN)
566 ps->rx_length_errors++;
567 if (status & IR_CRC_ERROR)
568 ps->rx_crc_errors++;
569 }
570 else
571 ps->rx_bytes += count;
572}
573
574/*
575 * Au1000 receive routine.
576 */
577static int au1k_irda_rx(struct net_device *dev)
578{
579 struct au1k_private *aup = netdev_priv(dev);
580 struct sk_buff *skb;
581 volatile ring_dest_t *prxd;
582 u32 flags, count;
583 db_dest_t *pDB;
584
585 prxd = aup->rx_ring[aup->rx_head];
586 flags = prxd->flags;
587
588 while (!(flags & AU_OWN)) {
589 pDB = aup->rx_db_inuse[aup->rx_head];
590 count = prxd->count_1<<8 | prxd->count_0;
591 if (!(flags & IR_RX_ERROR)) {
592 /* good frame */
593 update_rx_stats(dev, flags, count);
594 skb=alloc_skb(count+1,GFP_ATOMIC);
595 if (skb == NULL) {
596 aup->netdev->stats.rx_dropped++;
597 continue;
598 }
599 skb_reserve(skb, 1);
600 if (aup->speed == 4000000)
601 skb_put(skb, count);
602 else
603 skb_put(skb, count-2);
604 skb_copy_to_linear_data(skb, pDB->vaddr, count - 2);
605 skb->dev = dev;
606 skb_reset_mac_header(skb);
607 skb->protocol = htons(ETH_P_IRDA);
608 netif_rx(skb);
609 prxd->count_0 = 0;
610 prxd->count_1 = 0;
611 }
612 prxd->flags |= AU_OWN;
613 aup->rx_head = (aup->rx_head + 1) & (NUM_IR_DESC - 1);
614 writel(0, IR_RING_PROMPT);
615 au_sync();
616
617 /* next descriptor */
618 prxd = aup->rx_ring[aup->rx_head];
619 flags = prxd->flags;
620
621 }
622 return 0;
623}
624
625
626static irqreturn_t au1k_irda_interrupt(int dummy, void *dev_id)
627{
628 struct net_device *dev = dev_id;
629
630 writel(0, IR_INT_CLEAR); /* ack irda interrupts */
631
632 au1k_irda_rx(dev);
633 au1k_tx_ack(dev);
634
635 return IRQ_HANDLED;
636}
637
638
639/* 697/*
640 * The Tx ring has been full longer than the watchdog timeout 698 * The Tx ring has been full longer than the watchdog timeout
641 * value. The transmitter must be hung? 699 * value. The transmitter must be hung?
@@ -653,142 +711,7 @@ static void au1k_tx_timeout(struct net_device *dev)
653 netif_wake_queue(dev); 711 netif_wake_queue(dev);
654} 712}
655 713
656 714static int au1k_irda_ioctl(struct net_device *dev, struct ifreq *ifreq, int cmd)
657/*
658 * Set the IrDA communications speed.
659 */
660static int
661au1k_irda_set_speed(struct net_device *dev, int speed)
662{
663 unsigned long flags;
664 struct au1k_private *aup = netdev_priv(dev);
665 u32 control;
666 int ret = 0, timeout = 10, i;
667 volatile ring_dest_t *ptxd;
668#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100)
669 unsigned long irda_resets;
670#endif
671
672 if (speed == aup->speed)
673 return ret;
674
675 spin_lock_irqsave(&ir_lock, flags);
676
677 /* disable PHY first */
678 writel(read_ir_reg(IR_ENABLE) & ~0x8000, IR_ENABLE);
679
680 /* disable RX/TX */
681 writel(read_ir_reg(IR_CONFIG_1) & ~(IR_RX_ENABLE|IR_TX_ENABLE),
682 IR_CONFIG_1);
683 au_sync_delay(1);
684 while (read_ir_reg(IR_ENABLE) & (IR_RX_STATUS | IR_TX_STATUS)) {
685 mdelay(1);
686 if (!timeout--) {
687 printk(KERN_ERR "%s: rx/tx disable timeout\n",
688 dev->name);
689 break;
690 }
691 }
692
693 /* disable DMA */
694 writel(read_ir_reg(IR_CONFIG_1) & ~IR_DMA_ENABLE, IR_CONFIG_1);
695 au_sync_delay(1);
696
697 /*
698 * After we disable tx/rx. the index pointers
699 * go back to zero.
700 */
701 aup->tx_head = aup->tx_tail = aup->rx_head = 0;
702 for (i=0; i<NUM_IR_DESC; i++) {
703 ptxd = aup->tx_ring[i];
704 ptxd->flags = 0;
705 ptxd->count_0 = 0;
706 ptxd->count_1 = 0;
707 }
708
709 for (i=0; i<NUM_IR_DESC; i++) {
710 ptxd = aup->rx_ring[i];
711 ptxd->count_0 = 0;
712 ptxd->count_1 = 0;
713 ptxd->flags = AU_OWN;
714 }
715
716 if (speed == 4000000) {
717#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100)
718 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_FIR_SEL);
719#else /* Pb1000 and Pb1100 */
720 writel(1<<13, CPLD_AUX1);
721#endif
722 }
723 else {
724#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100)
725 bcsr_mod(BCSR_RESETS, BCSR_RESETS_FIR_SEL, 0);
726#else /* Pb1000 and Pb1100 */
727 writel(readl(CPLD_AUX1) & ~(1<<13), CPLD_AUX1);
728#endif
729 }
730
731 switch (speed) {
732 case 9600:
733 writel(11<<10 | 12<<5, IR_WRITE_PHY_CONFIG);
734 writel(IR_SIR_MODE, IR_CONFIG_1);
735 break;
736 case 19200:
737 writel(5<<10 | 12<<5, IR_WRITE_PHY_CONFIG);
738 writel(IR_SIR_MODE, IR_CONFIG_1);
739 break;
740 case 38400:
741 writel(2<<10 | 12<<5, IR_WRITE_PHY_CONFIG);
742 writel(IR_SIR_MODE, IR_CONFIG_1);
743 break;
744 case 57600:
745 writel(1<<10 | 12<<5, IR_WRITE_PHY_CONFIG);
746 writel(IR_SIR_MODE, IR_CONFIG_1);
747 break;
748 case 115200:
749 writel(12<<5, IR_WRITE_PHY_CONFIG);
750 writel(IR_SIR_MODE, IR_CONFIG_1);
751 break;
752 case 4000000:
753 writel(0xF, IR_WRITE_PHY_CONFIG);
754 writel(IR_FIR|IR_DMA_ENABLE|IR_RX_ENABLE, IR_CONFIG_1);
755 break;
756 default:
757 printk(KERN_ERR "%s unsupported speed %x\n", dev->name, speed);
758 ret = -EINVAL;
759 break;
760 }
761
762 aup->speed = speed;
763 writel(read_ir_reg(IR_ENABLE) | 0x8000, IR_ENABLE);
764 au_sync();
765
766 control = read_ir_reg(IR_ENABLE);
767 writel(0, IR_RING_PROMPT);
768 au_sync();
769
770 if (control & (1<<14)) {
771 printk(KERN_ERR "%s: configuration error\n", dev->name);
772 }
773 else {
774 if (control & (1<<11))
775 printk(KERN_DEBUG "%s Valid SIR config\n", dev->name);
776 if (control & (1<<12))
777 printk(KERN_DEBUG "%s Valid MIR config\n", dev->name);
778 if (control & (1<<13))
779 printk(KERN_DEBUG "%s Valid FIR config\n", dev->name);
780 if (control & (1<<10))
781 printk(KERN_DEBUG "%s TX enabled\n", dev->name);
782 if (control & (1<<9))
783 printk(KERN_DEBUG "%s RX enabled\n", dev->name);
784 }
785
786 spin_unlock_irqrestore(&ir_lock, flags);
787 return ret;
788}
789
790static int
791au1k_irda_ioctl(struct net_device *dev, struct ifreq *ifreq, int cmd)
792{ 715{
793 struct if_irda_req *rq = (struct if_irda_req *)ifreq; 716 struct if_irda_req *rq = (struct if_irda_req *)ifreq;
794 struct au1k_private *aup = netdev_priv(dev); 717 struct au1k_private *aup = netdev_priv(dev);
@@ -829,8 +752,218 @@ au1k_irda_ioctl(struct net_device *dev, struct ifreq *ifreq, int cmd)
829 return ret; 752 return ret;
830} 753}
831 754
755static const struct net_device_ops au1k_irda_netdev_ops = {
756 .ndo_open = au1k_irda_start,
757 .ndo_stop = au1k_irda_stop,
758 .ndo_start_xmit = au1k_irda_hard_xmit,
759 .ndo_tx_timeout = au1k_tx_timeout,
760 .ndo_do_ioctl = au1k_irda_ioctl,
761};
762
763static int __devinit au1k_irda_net_init(struct net_device *dev)
764{
765 struct au1k_private *aup = netdev_priv(dev);
766 struct db_dest *pDB, *pDBfree;
767 int i, err, retval = 0;
768 dma_addr_t temp;
769
770 err = au1k_irda_init_iobuf(&aup->rx_buff, 14384);
771 if (err)
772 goto out1;
773
774 dev->netdev_ops = &au1k_irda_netdev_ops;
775
776 irda_init_max_qos_capabilies(&aup->qos);
777
778 /* The only value we must override it the baudrate */
779 aup->qos.baud_rate.bits = IR_9600 | IR_19200 | IR_38400 |
780 IR_57600 | IR_115200 | IR_576000 | (IR_4000000 << 8);
781
782 aup->qos.min_turn_time.bits = qos_mtt_bits;
783 irda_qos_bits_to_value(&aup->qos);
784
785 retval = -ENOMEM;
786
787 /* Tx ring follows rx ring + 512 bytes */
788 /* we need a 1k aligned buffer */
789 aup->rx_ring[0] = (struct ring_dest *)
790 dma_alloc(2 * MAX_NUM_IR_DESC * (sizeof(struct ring_dest)),
791 &temp);
792 if (!aup->rx_ring[0])
793 goto out2;
794
795 /* allocate the data buffers */
796 aup->db[0].vaddr =
797 (void *)dma_alloc(MAX_BUF_SIZE * 2 * NUM_IR_DESC, &temp);
798 if (!aup->db[0].vaddr)
799 goto out3;
800
801 setup_hw_rings(aup, (u32)aup->rx_ring[0], (u32)aup->rx_ring[0] + 512);
802
803 pDBfree = NULL;
804 pDB = aup->db;
805 for (i = 0; i < (2 * NUM_IR_DESC); i++) {
806 pDB->pnext = pDBfree;
807 pDBfree = pDB;
808 pDB->vaddr =
809 (u32 *)((unsigned)aup->db[0].vaddr + (MAX_BUF_SIZE * i));
810 pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr);
811 pDB++;
812 }
813 aup->pDBfree = pDBfree;
814
815 /* attach a data buffer to each descriptor */
816 for (i = 0; i < NUM_IR_DESC; i++) {
817 pDB = GetFreeDB(aup);
818 if (!pDB)
819 goto out3;
820 aup->rx_ring[i]->addr_0 = (u8)(pDB->dma_addr & 0xff);
821 aup->rx_ring[i]->addr_1 = (u8)((pDB->dma_addr >> 8) & 0xff);
822 aup->rx_ring[i]->addr_2 = (u8)((pDB->dma_addr >> 16) & 0xff);
823 aup->rx_ring[i]->addr_3 = (u8)((pDB->dma_addr >> 24) & 0xff);
824 aup->rx_db_inuse[i] = pDB;
825 }
826 for (i = 0; i < NUM_IR_DESC; i++) {
827 pDB = GetFreeDB(aup);
828 if (!pDB)
829 goto out3;
830 aup->tx_ring[i]->addr_0 = (u8)(pDB->dma_addr & 0xff);
831 aup->tx_ring[i]->addr_1 = (u8)((pDB->dma_addr >> 8) & 0xff);
832 aup->tx_ring[i]->addr_2 = (u8)((pDB->dma_addr >> 16) & 0xff);
833 aup->tx_ring[i]->addr_3 = (u8)((pDB->dma_addr >> 24) & 0xff);
834 aup->tx_ring[i]->count_0 = 0;
835 aup->tx_ring[i]->count_1 = 0;
836 aup->tx_ring[i]->flags = 0;
837 aup->tx_db_inuse[i] = pDB;
838 }
839
840 return 0;
841
842out3:
843 dma_free((void *)aup->rx_ring[0],
844 2 * MAX_NUM_IR_DESC * (sizeof(struct ring_dest)));
845out2:
846 kfree(aup->rx_buff.head);
847out1:
848 printk(KERN_ERR "au1k_irda_net_init() failed. Returns %d\n", retval);
849 return retval;
850}
851
852static int __devinit au1k_irda_probe(struct platform_device *pdev)
853{
854 struct au1k_private *aup;
855 struct net_device *dev;
856 struct resource *r;
857 int err;
858
859 dev = alloc_irdadev(sizeof(struct au1k_private));
860 if (!dev)
861 return -ENOMEM;
862
863 aup = netdev_priv(dev);
864
865 aup->platdata = pdev->dev.platform_data;
866
867 err = -EINVAL;
868 r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
869 if (!r)
870 goto out;
871
872 aup->irq_tx = r->start;
873
874 r = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
875 if (!r)
876 goto out;
877
878 aup->irq_rx = r->start;
879
880 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
881 if (!r)
882 goto out;
883
884 err = -EBUSY;
885 aup->ioarea = request_mem_region(r->start, r->end - r->start + 1,
886 pdev->name);
887 if (!aup->ioarea)
888 goto out;
889
890 aup->iobase = ioremap_nocache(r->start, r->end - r->start + 1);
891 if (!aup->iobase)
892 goto out2;
893
894 dev->irq = aup->irq_rx;
895
896 err = au1k_irda_net_init(dev);
897 if (err)
898 goto out3;
899 err = register_netdev(dev);
900 if (err)
901 goto out4;
902
903 platform_set_drvdata(pdev, dev);
904
905 printk(KERN_INFO "IrDA: Registered device %s\n", dev->name);
906 return 0;
907
908out4:
909 dma_free((void *)aup->db[0].vaddr,
910 MAX_BUF_SIZE * 2 * NUM_IR_DESC);
911 dma_free((void *)aup->rx_ring[0],
912 2 * MAX_NUM_IR_DESC * (sizeof(struct ring_dest)));
913 kfree(aup->rx_buff.head);
914out3:
915 iounmap(aup->iobase);
916out2:
917 release_resource(aup->ioarea);
918 kfree(aup->ioarea);
919out:
920 free_netdev(dev);
921 return err;
922}
923
924static int __devexit au1k_irda_remove(struct platform_device *pdev)
925{
926 struct net_device *dev = platform_get_drvdata(pdev);
927 struct au1k_private *aup = netdev_priv(dev);
928
929 unregister_netdev(dev);
930
931 dma_free((void *)aup->db[0].vaddr,
932 MAX_BUF_SIZE * 2 * NUM_IR_DESC);
933 dma_free((void *)aup->rx_ring[0],
934 2 * MAX_NUM_IR_DESC * (sizeof(struct ring_dest)));
935 kfree(aup->rx_buff.head);
936
937 iounmap(aup->iobase);
938 release_resource(aup->ioarea);
939 kfree(aup->ioarea);
940
941 free_netdev(dev);
942
943 return 0;
944}
945
946static struct platform_driver au1k_irda_driver = {
947 .driver = {
948 .name = "au1000-irda",
949 .owner = THIS_MODULE,
950 },
951 .probe = au1k_irda_probe,
952 .remove = __devexit_p(au1k_irda_remove),
953};
954
955static int __init au1k_irda_load(void)
956{
957 return platform_driver_register(&au1k_irda_driver);
958}
959
960static void __exit au1k_irda_unload(void)
961{
962 return platform_driver_unregister(&au1k_irda_driver);
963}
964
832MODULE_AUTHOR("Pete Popov <ppopov@mvista.com>"); 965MODULE_AUTHOR("Pete Popov <ppopov@mvista.com>");
833MODULE_DESCRIPTION("Au1000 IrDA Device Driver"); 966MODULE_DESCRIPTION("Au1000 IrDA Device Driver");
834 967
835module_init(au1k_irda_init); 968module_init(au1k_irda_load);
836module_exit(au1k_irda_exit); 969module_exit(au1k_irda_unload);
diff --git a/drivers/pcmcia/Kconfig b/drivers/pcmcia/Kconfig
index 6e318ce41136..f9e3fb3a285b 100644
--- a/drivers/pcmcia/Kconfig
+++ b/drivers/pcmcia/Kconfig
@@ -155,18 +155,14 @@ config PCMCIA_M8XX
155 155
156 This driver is also available as a module called m8xx_pcmcia. 156 This driver is also available as a module called m8xx_pcmcia.
157 157
158config PCMCIA_AU1X00
159 tristate "Au1x00 pcmcia support"
160 depends on MIPS_ALCHEMY && PCMCIA
161
162config PCMCIA_ALCHEMY_DEVBOARD 158config PCMCIA_ALCHEMY_DEVBOARD
163 tristate "Alchemy Db/Pb1xxx PCMCIA socket services" 159 tristate "Alchemy Db/Pb1xxx PCMCIA socket services"
164 depends on MIPS_ALCHEMY && PCMCIA 160 depends on MIPS_ALCHEMY && PCMCIA
165 select 64BIT_PHYS_ADDR 161 select 64BIT_PHYS_ADDR
166 help 162 help
167 Enable this driver of you want PCMCIA support on your Alchemy 163 Enable this driver of you want PCMCIA support on your Alchemy
168 Db1000, Db/Pb1100, Db/Pb1500, Db/Pb1550, Db/Pb1200 board. 164 Db1000, Db/Pb1100, Db/Pb1500, Db/Pb1550, Db/Pb1200, DB1300
169 NOT suitable for the PB1000! 165 board. NOT suitable for the PB1000!
170 166
171 This driver is also available as a module called db1xxx_ss.ko 167 This driver is also available as a module called db1xxx_ss.ko
172 168
diff --git a/drivers/pcmcia/Makefile b/drivers/pcmcia/Makefile
index 29935ea921df..ec543a4ff2e4 100644
--- a/drivers/pcmcia/Makefile
+++ b/drivers/pcmcia/Makefile
@@ -29,7 +29,6 @@ obj-$(CONFIG_PCMCIA_SA1100) += sa11xx_base.o sa1100_cs.o
29obj-$(CONFIG_PCMCIA_SA1111) += sa11xx_base.o sa1111_cs.o 29obj-$(CONFIG_PCMCIA_SA1111) += sa11xx_base.o sa1111_cs.o
30obj-$(CONFIG_M32R_PCC) += m32r_pcc.o 30obj-$(CONFIG_M32R_PCC) += m32r_pcc.o
31obj-$(CONFIG_M32R_CFC) += m32r_cfc.o 31obj-$(CONFIG_M32R_CFC) += m32r_cfc.o
32obj-$(CONFIG_PCMCIA_AU1X00) += au1x00_ss.o
33obj-$(CONFIG_PCMCIA_BCM63XX) += bcm63xx_pcmcia.o 32obj-$(CONFIG_PCMCIA_BCM63XX) += bcm63xx_pcmcia.o
34obj-$(CONFIG_PCMCIA_VRC4171) += vrc4171_card.o 33obj-$(CONFIG_PCMCIA_VRC4171) += vrc4171_card.o
35obj-$(CONFIG_PCMCIA_VRC4173) += vrc4173_cardu.o 34obj-$(CONFIG_PCMCIA_VRC4173) += vrc4173_cardu.o
@@ -39,9 +38,6 @@ obj-$(CONFIG_AT91_CF) += at91_cf.o
39obj-$(CONFIG_ELECTRA_CF) += electra_cf.o 38obj-$(CONFIG_ELECTRA_CF) += electra_cf.o
40obj-$(CONFIG_PCMCIA_ALCHEMY_DEVBOARD) += db1xxx_ss.o 39obj-$(CONFIG_PCMCIA_ALCHEMY_DEVBOARD) += db1xxx_ss.o
41 40
42au1x00_ss-y += au1000_generic.o
43au1x00_ss-$(CONFIG_MIPS_PB1000) += au1000_pb1x00.o
44
45sa1111_cs-y += sa1111_generic.o 41sa1111_cs-y += sa1111_generic.o
46sa1111_cs-$(CONFIG_ASSABET_NEPONSET) += sa1100_neponset.o 42sa1111_cs-$(CONFIG_ASSABET_NEPONSET) += sa1100_neponset.o
47sa1111_cs-$(CONFIG_SA1100_BADGE4) += sa1100_badge4.o 43sa1111_cs-$(CONFIG_SA1100_BADGE4) += sa1100_badge4.o
diff --git a/drivers/pcmcia/au1000_generic.c b/drivers/pcmcia/au1000_generic.c
deleted file mode 100644
index 95dd7c62741f..000000000000
--- a/drivers/pcmcia/au1000_generic.c
+++ /dev/null
@@ -1,545 +0,0 @@
1/*
2 *
3 * Alchemy Semi Au1000 pcmcia driver
4 *
5 * Copyright 2001-2003 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc.
7 * ppopov@embeddedalley.com or source@mvista.com
8 *
9 * Copyright 2004 Pete Popov, Embedded Alley Solutions, Inc.
10 * Updated the driver to 2.6. Followed the sa11xx API and largely
11 * copied many of the hardware independent functions.
12 *
13 * ########################################################################
14 *
15 * This program is free software; you can distribute it and/or modify it
16 * under the terms of the GNU General Public License (Version 2) as
17 * published by the Free Software Foundation.
18 *
19 * This program is distributed in the hope it will be useful, but WITHOUT
20 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
21 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
22 * for more details.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
27 *
28 * ########################################################################
29 *
30 *
31 */
32
33#include <linux/module.h>
34#include <linux/moduleparam.h>
35#include <linux/init.h>
36#include <linux/cpufreq.h>
37#include <linux/ioport.h>
38#include <linux/kernel.h>
39#include <linux/timer.h>
40#include <linux/mm.h>
41#include <linux/notifier.h>
42#include <linux/interrupt.h>
43#include <linux/spinlock.h>
44#include <linux/mutex.h>
45#include <linux/platform_device.h>
46#include <linux/slab.h>
47
48#include <asm/io.h>
49#include <asm/irq.h>
50#include <asm/system.h>
51
52#include <asm/mach-au1x00/au1000.h>
53#include "au1000_generic.h"
54
55MODULE_LICENSE("GPL");
56MODULE_AUTHOR("Pete Popov <ppopov@embeddedalley.com>");
57MODULE_DESCRIPTION("Linux PCMCIA Card Services: Au1x00 Socket Controller");
58
59#if 0
60#define debug(x,args...) printk(KERN_DEBUG "%s: " x, __func__ , ##args)
61#else
62#define debug(x,args...)
63#endif
64
65#define MAP_SIZE 0x100000
66extern struct au1000_pcmcia_socket au1000_pcmcia_socket[];
67#define PCMCIA_SOCKET(x) (au1000_pcmcia_socket + (x))
68#define to_au1000_socket(x) container_of(x, struct au1000_pcmcia_socket, socket)
69
70/* Some boards like to support CF cards as IDE root devices, so they
71 * grab pcmcia sockets directly.
72 */
73u32 *pcmcia_base_vaddrs[2];
74extern const unsigned long mips_io_port_base;
75
76static DEFINE_MUTEX(pcmcia_sockets_lock);
77
78static int (*au1x00_pcmcia_hw_init[])(struct device *dev) = {
79 au1x_board_init,
80};
81
82static int
83au1x00_pcmcia_skt_state(struct au1000_pcmcia_socket *skt)
84{
85 struct pcmcia_state state;
86 unsigned int stat;
87
88 memset(&state, 0, sizeof(struct pcmcia_state));
89
90 skt->ops->socket_state(skt, &state);
91
92 stat = state.detect ? SS_DETECT : 0;
93 stat |= state.ready ? SS_READY : 0;
94 stat |= state.wrprot ? SS_WRPROT : 0;
95 stat |= state.vs_3v ? SS_3VCARD : 0;
96 stat |= state.vs_Xv ? SS_XVCARD : 0;
97 stat |= skt->cs_state.Vcc ? SS_POWERON : 0;
98
99 if (skt->cs_state.flags & SS_IOCARD)
100 stat |= state.bvd1 ? SS_STSCHG : 0;
101 else {
102 if (state.bvd1 == 0)
103 stat |= SS_BATDEAD;
104 else if (state.bvd2 == 0)
105 stat |= SS_BATWARN;
106 }
107 return stat;
108}
109
110/*
111 * au100_pcmcia_config_skt
112 *
113 * Convert PCMCIA socket state to our socket configure structure.
114 */
115static int
116au1x00_pcmcia_config_skt(struct au1000_pcmcia_socket *skt, socket_state_t *state)
117{
118 int ret;
119
120 ret = skt->ops->configure_socket(skt, state);
121 if (ret == 0) {
122 skt->cs_state = *state;
123 }
124
125 if (ret < 0)
126 debug("unable to configure socket %d\n", skt->nr);
127
128 return ret;
129}
130
131/* au1x00_pcmcia_sock_init()
132 *
133 * (Re-)Initialise the socket, turning on status interrupts
134 * and PCMCIA bus. This must wait for power to stabilise
135 * so that the card status signals report correctly.
136 *
137 * Returns: 0
138 */
139static int au1x00_pcmcia_sock_init(struct pcmcia_socket *sock)
140{
141 struct au1000_pcmcia_socket *skt = to_au1000_socket(sock);
142
143 debug("initializing socket %u\n", skt->nr);
144
145 skt->ops->socket_init(skt);
146 return 0;
147}
148
149/*
150 * au1x00_pcmcia_suspend()
151 *
152 * Remove power on the socket, disable IRQs from the card.
153 * Turn off status interrupts, and disable the PCMCIA bus.
154 *
155 * Returns: 0
156 */
157static int au1x00_pcmcia_suspend(struct pcmcia_socket *sock)
158{
159 struct au1000_pcmcia_socket *skt = to_au1000_socket(sock);
160
161 debug("suspending socket %u\n", skt->nr);
162
163 skt->ops->socket_suspend(skt);
164
165 return 0;
166}
167
168static DEFINE_SPINLOCK(status_lock);
169
170/*
171 * au1x00_check_status()
172 */
173static void au1x00_check_status(struct au1000_pcmcia_socket *skt)
174{
175 unsigned int events;
176
177 debug("entering PCMCIA monitoring thread\n");
178
179 do {
180 unsigned int status;
181 unsigned long flags;
182
183 status = au1x00_pcmcia_skt_state(skt);
184
185 spin_lock_irqsave(&status_lock, flags);
186 events = (status ^ skt->status) & skt->cs_state.csc_mask;
187 skt->status = status;
188 spin_unlock_irqrestore(&status_lock, flags);
189
190 debug("events: %s%s%s%s%s%s\n",
191 events == 0 ? "<NONE>" : "",
192 events & SS_DETECT ? "DETECT " : "",
193 events & SS_READY ? "READY " : "",
194 events & SS_BATDEAD ? "BATDEAD " : "",
195 events & SS_BATWARN ? "BATWARN " : "",
196 events & SS_STSCHG ? "STSCHG " : "");
197
198 if (events)
199 pcmcia_parse_events(&skt->socket, events);
200 } while (events);
201}
202
203/*
204 * au1x00_pcmcia_poll_event()
205 * Let's poll for events in addition to IRQs since IRQ only is unreliable...
206 */
207static void au1x00_pcmcia_poll_event(unsigned long dummy)
208{
209 struct au1000_pcmcia_socket *skt = (struct au1000_pcmcia_socket *)dummy;
210 debug("polling for events\n");
211
212 mod_timer(&skt->poll_timer, jiffies + AU1000_PCMCIA_POLL_PERIOD);
213
214 au1x00_check_status(skt);
215}
216
217/* au1x00_pcmcia_get_status()
218 *
219 * From the sa11xx_core.c:
220 * Implements the get_status() operation for the in-kernel PCMCIA
221 * service (formerly SS_GetStatus in Card Services). Essentially just
222 * fills in bits in `status' according to internal driver state or
223 * the value of the voltage detect chipselect register.
224 *
225 * As a debugging note, during card startup, the PCMCIA core issues
226 * three set_socket() commands in a row the first with RESET deasserted,
227 * the second with RESET asserted, and the last with RESET deasserted
228 * again. Following the third set_socket(), a get_status() command will
229 * be issued. The kernel is looking for the SS_READY flag (see
230 * setup_socket(), reset_socket(), and unreset_socket() in cs.c).
231 *
232 * Returns: 0
233 */
234static int
235au1x00_pcmcia_get_status(struct pcmcia_socket *sock, unsigned int *status)
236{
237 struct au1000_pcmcia_socket *skt = to_au1000_socket(sock);
238
239 skt->status = au1x00_pcmcia_skt_state(skt);
240 *status = skt->status;
241
242 return 0;
243}
244
245/* au1x00_pcmcia_set_socket()
246 * Implements the set_socket() operation for the in-kernel PCMCIA
247 * service (formerly SS_SetSocket in Card Services). We more or
248 * less punt all of this work and let the kernel handle the details
249 * of power configuration, reset, &c. We also record the value of
250 * `state' in order to regurgitate it to the PCMCIA core later.
251 *
252 * Returns: 0
253 */
254static int
255au1x00_pcmcia_set_socket(struct pcmcia_socket *sock, socket_state_t *state)
256{
257 struct au1000_pcmcia_socket *skt = to_au1000_socket(sock);
258
259 debug("for sock %u\n", skt->nr);
260
261 debug("\tmask: %s%s%s%s%s%s\n\tflags: %s%s%s%s%s%s\n",
262 (state->csc_mask==0)?"<NONE>":"",
263 (state->csc_mask&SS_DETECT)?"DETECT ":"",
264 (state->csc_mask&SS_READY)?"READY ":"",
265 (state->csc_mask&SS_BATDEAD)?"BATDEAD ":"",
266 (state->csc_mask&SS_BATWARN)?"BATWARN ":"",
267 (state->csc_mask&SS_STSCHG)?"STSCHG ":"",
268 (state->flags==0)?"<NONE>":"",
269 (state->flags&SS_PWR_AUTO)?"PWR_AUTO ":"",
270 (state->flags&SS_IOCARD)?"IOCARD ":"",
271 (state->flags&SS_RESET)?"RESET ":"",
272 (state->flags&SS_SPKR_ENA)?"SPKR_ENA ":"",
273 (state->flags&SS_OUTPUT_ENA)?"OUTPUT_ENA ":"");
274 debug("\tVcc %d Vpp %d irq %d\n",
275 state->Vcc, state->Vpp, state->io_irq);
276
277 return au1x00_pcmcia_config_skt(skt, state);
278}
279
280int
281au1x00_pcmcia_set_io_map(struct pcmcia_socket *sock, struct pccard_io_map *map)
282{
283 struct au1000_pcmcia_socket *skt = to_au1000_socket(sock);
284 unsigned int speed;
285
286 if(map->map>=MAX_IO_WIN){
287 debug("map (%d) out of range\n", map->map);
288 return -1;
289 }
290
291 if(map->flags&MAP_ACTIVE){
292 speed=(map->speed>0)?map->speed:AU1000_PCMCIA_IO_SPEED;
293 skt->spd_io[map->map] = speed;
294 }
295
296 map->start=(unsigned int)(u32)skt->virt_io;
297 map->stop=map->start+MAP_SIZE;
298 return 0;
299
300} /* au1x00_pcmcia_set_io_map() */
301
302
303static int
304au1x00_pcmcia_set_mem_map(struct pcmcia_socket *sock, struct pccard_mem_map *map)
305{
306 struct au1000_pcmcia_socket *skt = to_au1000_socket(sock);
307 unsigned short speed = map->speed;
308
309 if(map->map>=MAX_WIN){
310 debug("map (%d) out of range\n", map->map);
311 return -1;
312 }
313
314 if (map->flags & MAP_ATTRIB) {
315 skt->spd_attr[map->map] = speed;
316 skt->spd_mem[map->map] = 0;
317 } else {
318 skt->spd_attr[map->map] = 0;
319 skt->spd_mem[map->map] = speed;
320 }
321
322 if (map->flags & MAP_ATTRIB) {
323 map->static_start = skt->phys_attr + map->card_start;
324 }
325 else {
326 map->static_start = skt->phys_mem + map->card_start;
327 }
328
329 debug("set_mem_map %d start %08lx card_start %08x\n",
330 map->map, map->static_start, map->card_start);
331 return 0;
332
333} /* au1x00_pcmcia_set_mem_map() */
334
335static struct pccard_operations au1x00_pcmcia_operations = {
336 .init = au1x00_pcmcia_sock_init,
337 .suspend = au1x00_pcmcia_suspend,
338 .get_status = au1x00_pcmcia_get_status,
339 .set_socket = au1x00_pcmcia_set_socket,
340 .set_io_map = au1x00_pcmcia_set_io_map,
341 .set_mem_map = au1x00_pcmcia_set_mem_map,
342};
343
344static const char *skt_names[] = {
345 "PCMCIA socket 0",
346 "PCMCIA socket 1",
347};
348
349struct skt_dev_info {
350 int nskt;
351};
352
353int au1x00_pcmcia_socket_probe(struct device *dev, struct pcmcia_low_level *ops, int first, int nr)
354{
355 struct skt_dev_info *sinfo;
356 struct au1000_pcmcia_socket *skt;
357 int ret, i;
358
359 sinfo = kzalloc(sizeof(struct skt_dev_info), GFP_KERNEL);
360 if (!sinfo) {
361 ret = -ENOMEM;
362 goto out;
363 }
364
365 sinfo->nskt = nr;
366
367 /*
368 * Initialise the per-socket structure.
369 */
370 for (i = 0; i < nr; i++) {
371 skt = PCMCIA_SOCKET(i);
372 memset(skt, 0, sizeof(*skt));
373
374 skt->socket.resource_ops = &pccard_static_ops;
375 skt->socket.ops = &au1x00_pcmcia_operations;
376 skt->socket.owner = ops->owner;
377 skt->socket.dev.parent = dev;
378
379 init_timer(&skt->poll_timer);
380 skt->poll_timer.function = au1x00_pcmcia_poll_event;
381 skt->poll_timer.data = (unsigned long)skt;
382 skt->poll_timer.expires = jiffies + AU1000_PCMCIA_POLL_PERIOD;
383
384 skt->nr = first + i;
385 skt->irq = 255;
386 skt->dev = dev;
387 skt->ops = ops;
388
389 skt->res_skt.name = skt_names[skt->nr];
390 skt->res_io.name = "io";
391 skt->res_io.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
392 skt->res_mem.name = "memory";
393 skt->res_mem.flags = IORESOURCE_MEM;
394 skt->res_attr.name = "attribute";
395 skt->res_attr.flags = IORESOURCE_MEM;
396
397 /*
398 * PCMCIA client drivers use the inb/outb macros to access the
399 * IO registers. Since mips_io_port_base is added to the
400 * access address of the mips implementation of inb/outb,
401 * we need to subtract it here because we want to access the
402 * I/O or MEM address directly, without going through this
403 * "mips_io_port_base" mechanism.
404 */
405 if (i == 0) {
406 skt->virt_io = (void *)
407 (ioremap((phys_t)AU1X_SOCK0_IO, 0x1000) -
408 (u32)mips_io_port_base);
409 skt->phys_attr = AU1X_SOCK0_PHYS_ATTR;
410 skt->phys_mem = AU1X_SOCK0_PHYS_MEM;
411 }
412 else {
413 skt->virt_io = (void *)
414 (ioremap((phys_t)AU1X_SOCK1_IO, 0x1000) -
415 (u32)mips_io_port_base);
416 skt->phys_attr = AU1X_SOCK1_PHYS_ATTR;
417 skt->phys_mem = AU1X_SOCK1_PHYS_MEM;
418 }
419 pcmcia_base_vaddrs[i] = (u32 *)skt->virt_io;
420 ret = ops->hw_init(skt);
421
422 skt->socket.features = SS_CAP_STATIC_MAP|SS_CAP_PCCARD;
423 skt->socket.irq_mask = 0;
424 skt->socket.map_size = MAP_SIZE;
425 skt->socket.pci_irq = skt->irq;
426 skt->socket.io_offset = (unsigned long)skt->virt_io;
427
428 skt->status = au1x00_pcmcia_skt_state(skt);
429
430 ret = pcmcia_register_socket(&skt->socket);
431 if (ret)
432 goto out_err;
433
434 WARN_ON(skt->socket.sock != i);
435
436 add_timer(&skt->poll_timer);
437 }
438
439 dev_set_drvdata(dev, sinfo);
440 return 0;
441
442
443out_err:
444 ops->hw_shutdown(skt);
445 while (i-- > 0) {
446 skt = PCMCIA_SOCKET(i);
447
448 del_timer_sync(&skt->poll_timer);
449 pcmcia_unregister_socket(&skt->socket);
450 if (i == 0) {
451 iounmap(skt->virt_io + (u32)mips_io_port_base);
452 skt->virt_io = NULL;
453 }
454#ifndef CONFIG_MIPS_XXS1500
455 else {
456 iounmap(skt->virt_io + (u32)mips_io_port_base);
457 skt->virt_io = NULL;
458 }
459#endif
460 ops->hw_shutdown(skt);
461
462 }
463 kfree(sinfo);
464out:
465 return ret;
466}
467
468int au1x00_drv_pcmcia_remove(struct platform_device *dev)
469{
470 struct skt_dev_info *sinfo = platform_get_drvdata(dev);
471 int i;
472
473 mutex_lock(&pcmcia_sockets_lock);
474 platform_set_drvdata(dev, NULL);
475
476 for (i = 0; i < sinfo->nskt; i++) {
477 struct au1000_pcmcia_socket *skt = PCMCIA_SOCKET(i);
478
479 del_timer_sync(&skt->poll_timer);
480 pcmcia_unregister_socket(&skt->socket);
481 skt->ops->hw_shutdown(skt);
482 au1x00_pcmcia_config_skt(skt, &dead_socket);
483 iounmap(skt->virt_io + (u32)mips_io_port_base);
484 skt->virt_io = NULL;
485 }
486
487 kfree(sinfo);
488 mutex_unlock(&pcmcia_sockets_lock);
489 return 0;
490}
491
492
493/*
494 * PCMCIA "Driver" API
495 */
496
497static int au1x00_drv_pcmcia_probe(struct platform_device *dev)
498{
499 int i, ret = -ENODEV;
500
501 mutex_lock(&pcmcia_sockets_lock);
502 for (i=0; i < ARRAY_SIZE(au1x00_pcmcia_hw_init); i++) {
503 ret = au1x00_pcmcia_hw_init[i](&dev->dev);
504 if (ret == 0)
505 break;
506 }
507 mutex_unlock(&pcmcia_sockets_lock);
508 return ret;
509}
510
511static struct platform_driver au1x00_pcmcia_driver = {
512 .driver = {
513 .name = "au1x00-pcmcia",
514 .owner = THIS_MODULE,
515 },
516 .probe = au1x00_drv_pcmcia_probe,
517 .remove = au1x00_drv_pcmcia_remove,
518};
519
520
521/* au1x00_pcmcia_init()
522 *
523 * This routine performs low-level PCMCIA initialization and then
524 * registers this socket driver with Card Services.
525 *
526 * Returns: 0 on success, -ve error code on failure
527 */
528static int __init au1x00_pcmcia_init(void)
529{
530 int error = 0;
531 error = platform_driver_register(&au1x00_pcmcia_driver);
532 return error;
533}
534
535/* au1x00_pcmcia_exit()
536 * Invokes the low-level kernel service to free IRQs associated with this
537 * socket controller and reset GPIO edge detection.
538 */
539static void __exit au1x00_pcmcia_exit(void)
540{
541 platform_driver_unregister(&au1x00_pcmcia_driver);
542}
543
544module_init(au1x00_pcmcia_init);
545module_exit(au1x00_pcmcia_exit);
diff --git a/drivers/pcmcia/au1000_generic.h b/drivers/pcmcia/au1000_generic.h
deleted file mode 100644
index 5c36bda2963b..000000000000
--- a/drivers/pcmcia/au1000_generic.h
+++ /dev/null
@@ -1,135 +0,0 @@
1/*
2 * Alchemy Semi Au1000 pcmcia driver include file
3 *
4 * Copyright 2001 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc.
6 * ppopov@mvista.com or source@mvista.com
7 *
8 * This program is free software; you can distribute it and/or modify it
9 * under the terms of the GNU General Public License (Version 2) as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 */
21#ifndef __ASM_AU1000_PCMCIA_H
22#define __ASM_AU1000_PCMCIA_H
23
24/* include the world */
25
26#include <pcmcia/ss.h>
27#include <pcmcia/cistpl.h>
28#include "cs_internal.h"
29
30#define AU1000_PCMCIA_POLL_PERIOD (2*HZ)
31#define AU1000_PCMCIA_IO_SPEED (255)
32#define AU1000_PCMCIA_MEM_SPEED (300)
33
34#define AU1X_SOCK0_IO 0xF00000000ULL
35#define AU1X_SOCK0_PHYS_ATTR 0xF40000000ULL
36#define AU1X_SOCK0_PHYS_MEM 0xF80000000ULL
37
38/* pcmcia socket 1 needs external glue logic so the memory map
39 * differs from board to board.
40 */
41#if defined(CONFIG_MIPS_PB1000)
42#define AU1X_SOCK1_IO 0xF08000000ULL
43#define AU1X_SOCK1_PHYS_ATTR 0xF48000000ULL
44#define AU1X_SOCK1_PHYS_MEM 0xF88000000ULL
45#endif
46
47struct pcmcia_state {
48 unsigned detect: 1,
49 ready: 1,
50 wrprot: 1,
51 bvd1: 1,
52 bvd2: 1,
53 vs_3v: 1,
54 vs_Xv: 1;
55};
56
57struct pcmcia_configure {
58 unsigned sock: 8,
59 vcc: 8,
60 vpp: 8,
61 output: 1,
62 speaker: 1,
63 reset: 1;
64};
65
66struct pcmcia_irqs {
67 int sock;
68 int irq;
69 const char *str;
70};
71
72
73struct au1000_pcmcia_socket {
74 struct pcmcia_socket socket;
75
76 /*
77 * Info from low level handler
78 */
79 struct device *dev;
80 unsigned int nr;
81 unsigned int irq;
82
83 /*
84 * Core PCMCIA state
85 */
86 struct pcmcia_low_level *ops;
87
88 unsigned int status;
89 socket_state_t cs_state;
90
91 unsigned short spd_io[MAX_IO_WIN];
92 unsigned short spd_mem[MAX_WIN];
93 unsigned short spd_attr[MAX_WIN];
94
95 struct resource res_skt;
96 struct resource res_io;
97 struct resource res_mem;
98 struct resource res_attr;
99
100 void * virt_io;
101 unsigned int phys_io;
102 unsigned int phys_attr;
103 unsigned int phys_mem;
104 unsigned short speed_io, speed_attr, speed_mem;
105
106 unsigned int irq_state;
107
108 struct timer_list poll_timer;
109};
110
111struct pcmcia_low_level {
112 struct module *owner;
113
114 int (*hw_init)(struct au1000_pcmcia_socket *);
115 void (*hw_shutdown)(struct au1000_pcmcia_socket *);
116
117 void (*socket_state)(struct au1000_pcmcia_socket *, struct pcmcia_state *);
118 int (*configure_socket)(struct au1000_pcmcia_socket *, struct socket_state_t *);
119
120 /*
121 * Enable card status IRQs on (re-)initialisation. This can
122 * be called at initialisation, power management event, or
123 * pcmcia event.
124 */
125 void (*socket_init)(struct au1000_pcmcia_socket *);
126
127 /*
128 * Disable card status IRQs and PCMCIA bus on suspend.
129 */
130 void (*socket_suspend)(struct au1000_pcmcia_socket *);
131};
132
133extern int au1x_board_init(struct device *dev);
134
135#endif /* __ASM_AU1000_PCMCIA_H */
diff --git a/drivers/pcmcia/au1000_pb1x00.c b/drivers/pcmcia/au1000_pb1x00.c
deleted file mode 100644
index b2396647a165..000000000000
--- a/drivers/pcmcia/au1000_pb1x00.c
+++ /dev/null
@@ -1,294 +0,0 @@
1/*
2 *
3 * Alchemy Semi Pb1000 boards specific pcmcia routines.
4 *
5 * Copyright 2002 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc.
7 * ppopov@mvista.com or source@mvista.com
8 *
9 * ########################################################################
10 *
11 * This program is free software; you can distribute it and/or modify it
12 * under the terms of the GNU General Public License (Version 2) as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
23 */
24#include <linux/module.h>
25#include <linux/init.h>
26#include <linux/delay.h>
27#include <linux/ioport.h>
28#include <linux/kernel.h>
29#include <linux/timer.h>
30#include <linux/mm.h>
31#include <linux/proc_fs.h>
32#include <linux/types.h>
33
34#include <pcmcia/ss.h>
35#include <pcmcia/cistpl.h>
36
37#include <asm/io.h>
38#include <asm/irq.h>
39#include <asm/system.h>
40
41#include <asm/au1000.h>
42#include <asm/au1000_pcmcia.h>
43
44#define debug(fmt, arg...) do { } while (0)
45
46#include <asm/pb1000.h>
47#define PCMCIA_IRQ AU1000_GPIO_15
48
49static int pb1x00_pcmcia_init(struct pcmcia_init *init)
50{
51 u16 pcr;
52 pcr = PCR_SLOT_0_RST | PCR_SLOT_1_RST;
53
54 au_writel(0x8000, PB1000_MDR); /* clear pcmcia interrupt */
55 au_sync_delay(100);
56 au_writel(0x4000, PB1000_MDR); /* enable pcmcia interrupt */
57 au_sync();
58
59 pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,0);
60 pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,1);
61 au_writel(pcr, PB1000_PCR);
62 au_sync_delay(20);
63
64 return PCMCIA_NUM_SOCKS;
65}
66
67static int pb1x00_pcmcia_shutdown(void)
68{
69 u16 pcr;
70 pcr = PCR_SLOT_0_RST | PCR_SLOT_1_RST;
71 pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,0);
72 pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,1);
73 au_writel(pcr, PB1000_PCR);
74 au_sync_delay(20);
75 return 0;
76}
77
78static int
79pb1x00_pcmcia_socket_state(unsigned sock, struct pcmcia_state *state)
80{
81 u32 inserted0, inserted1;
82 u16 vs0, vs1;
83
84 vs0 = vs1 = (u16)au_readl(PB1000_ACR1);
85 inserted0 = !(vs0 & (ACR1_SLOT_0_CD1 | ACR1_SLOT_0_CD2));
86 inserted1 = !(vs1 & (ACR1_SLOT_1_CD1 | ACR1_SLOT_1_CD2));
87 vs0 = (vs0 >> 4) & 0x3;
88 vs1 = (vs1 >> 12) & 0x3;
89
90 state->ready = 0;
91 state->vs_Xv = 0;
92 state->vs_3v = 0;
93 state->detect = 0;
94
95 if (sock == 0) {
96 if (inserted0) {
97 switch (vs0) {
98 case 0:
99 case 2:
100 state->vs_3v=1;
101 break;
102 case 3: /* 5V */
103 break;
104 default:
105 /* return without setting 'detect' */
106 printk(KERN_ERR "pb1x00 bad VS (%d)\n",
107 vs0);
108 return 0;
109 }
110 state->detect = 1;
111 }
112 }
113 else {
114 if (inserted1) {
115 switch (vs1) {
116 case 0:
117 case 2:
118 state->vs_3v=1;
119 break;
120 case 3: /* 5V */
121 break;
122 default:
123 /* return without setting 'detect' */
124 printk(KERN_ERR "pb1x00 bad VS (%d)\n",
125 vs1);
126 return 0;
127 }
128 state->detect = 1;
129 }
130 }
131
132 if (state->detect) {
133 state->ready = 1;
134 }
135
136 state->bvd1=1;
137 state->bvd2=1;
138 state->wrprot=0;
139 return 1;
140}
141
142
143static int pb1x00_pcmcia_get_irq_info(struct pcmcia_irq_info *info)
144{
145
146 if(info->sock > PCMCIA_MAX_SOCK) return -1;
147
148 /*
149 * Even in the case of the Pb1000, both sockets are connected
150 * to the same irq line.
151 */
152 info->irq = PCMCIA_IRQ;
153
154 return 0;
155}
156
157
158static int
159pb1x00_pcmcia_configure_socket(const struct pcmcia_configure *configure)
160{
161 u16 pcr;
162
163 if(configure->sock > PCMCIA_MAX_SOCK) return -1;
164
165 pcr = au_readl(PB1000_PCR);
166
167 if (configure->sock == 0) {
168 pcr &= ~(PCR_SLOT_0_VCC0 | PCR_SLOT_0_VCC1 |
169 PCR_SLOT_0_VPP0 | PCR_SLOT_0_VPP1);
170 }
171 else {
172 pcr &= ~(PCR_SLOT_1_VCC0 | PCR_SLOT_1_VCC1 |
173 PCR_SLOT_1_VPP0 | PCR_SLOT_1_VPP1);
174 }
175
176 pcr &= ~PCR_SLOT_0_RST;
177 debug("Vcc %dV Vpp %dV, pcr %x\n",
178 configure->vcc, configure->vpp, pcr);
179 switch(configure->vcc){
180 case 0: /* Vcc 0 */
181 switch(configure->vpp) {
182 case 0:
183 pcr |= SET_VCC_VPP(VCC_HIZ,VPP_GND,
184 configure->sock);
185 break;
186 case 12:
187 pcr |= SET_VCC_VPP(VCC_HIZ,VPP_12V,
188 configure->sock);
189 break;
190 case 50:
191 pcr |= SET_VCC_VPP(VCC_HIZ,VPP_5V,
192 configure->sock);
193 break;
194 case 33:
195 pcr |= SET_VCC_VPP(VCC_HIZ,VPP_3V,
196 configure->sock);
197 break;
198 default:
199 pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,
200 configure->sock);
201 printk("%s: bad Vcc/Vpp (%d:%d)\n",
202 __func__,
203 configure->vcc,
204 configure->vpp);
205 break;
206 }
207 break;
208 case 50: /* Vcc 5V */
209 switch(configure->vpp) {
210 case 0:
211 pcr |= SET_VCC_VPP(VCC_5V,VPP_GND,
212 configure->sock);
213 break;
214 case 50:
215 pcr |= SET_VCC_VPP(VCC_5V,VPP_5V,
216 configure->sock);
217 break;
218 case 12:
219 pcr |= SET_VCC_VPP(VCC_5V,VPP_12V,
220 configure->sock);
221 break;
222 case 33:
223 pcr |= SET_VCC_VPP(VCC_5V,VPP_3V,
224 configure->sock);
225 break;
226 default:
227 pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,
228 configure->sock);
229 printk("%s: bad Vcc/Vpp (%d:%d)\n",
230 __func__,
231 configure->vcc,
232 configure->vpp);
233 break;
234 }
235 break;
236 case 33: /* Vcc 3.3V */
237 switch(configure->vpp) {
238 case 0:
239 pcr |= SET_VCC_VPP(VCC_3V,VPP_GND,
240 configure->sock);
241 break;
242 case 50:
243 pcr |= SET_VCC_VPP(VCC_3V,VPP_5V,
244 configure->sock);
245 break;
246 case 12:
247 pcr |= SET_VCC_VPP(VCC_3V,VPP_12V,
248 configure->sock);
249 break;
250 case 33:
251 pcr |= SET_VCC_VPP(VCC_3V,VPP_3V,
252 configure->sock);
253 break;
254 default:
255 pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,
256 configure->sock);
257 printk("%s: bad Vcc/Vpp (%d:%d)\n",
258 __func__,
259 configure->vcc,
260 configure->vpp);
261 break;
262 }
263 break;
264 default: /* what's this ? */
265 pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,configure->sock);
266 printk(KERN_ERR "%s: bad Vcc %d\n",
267 __func__, configure->vcc);
268 break;
269 }
270
271 if (configure->sock == 0) {
272 pcr &= ~(PCR_SLOT_0_RST);
273 if (configure->reset)
274 pcr |= PCR_SLOT_0_RST;
275 }
276 else {
277 pcr &= ~(PCR_SLOT_1_RST);
278 if (configure->reset)
279 pcr |= PCR_SLOT_1_RST;
280 }
281 au_writel(pcr, PB1000_PCR);
282 au_sync_delay(300);
283
284 return 0;
285}
286
287
288struct pcmcia_low_level pb1x00_pcmcia_ops = {
289 pb1x00_pcmcia_init,
290 pb1x00_pcmcia_shutdown,
291 pb1x00_pcmcia_socket_state,
292 pb1x00_pcmcia_get_irq_info,
293 pb1x00_pcmcia_configure_socket
294};
diff --git a/drivers/pcmcia/db1xxx_ss.c b/drivers/pcmcia/db1xxx_ss.c
index 3e49df6d5e3b..5b7c22784aff 100644
--- a/drivers/pcmcia/db1xxx_ss.c
+++ b/drivers/pcmcia/db1xxx_ss.c
@@ -7,7 +7,7 @@
7 7
8/* This is a fairly generic PCMCIA socket driver suitable for the 8/* This is a fairly generic PCMCIA socket driver suitable for the
9 * following Alchemy Development boards: 9 * following Alchemy Development boards:
10 * Db1000, Db/Pb1500, Db/Pb1100, Db/Pb1550, Db/Pb1200. 10 * Db1000, Db/Pb1500, Db/Pb1100, Db/Pb1550, Db/Pb1200, Db1300
11 * 11 *
12 * The Db1000 is used as a reference: Per-socket card-, carddetect- and 12 * The Db1000 is used as a reference: Per-socket card-, carddetect- and
13 * statuschange IRQs connected to SoC GPIOs, control and status register 13 * statuschange IRQs connected to SoC GPIOs, control and status register
@@ -18,6 +18,7 @@
18 * - Pb1100/Pb1500: single socket only; voltage key bits VS are 18 * - Pb1100/Pb1500: single socket only; voltage key bits VS are
19 * at STATUS[5:4] (instead of STATUS[1:0]). 19 * at STATUS[5:4] (instead of STATUS[1:0]).
20 * - Au1200-based: additional card-eject irqs, irqs not gpios! 20 * - Au1200-based: additional card-eject irqs, irqs not gpios!
21 * - Db1300: Db1200-like, no pwr ctrl, single socket (#1).
21 */ 22 */
22 23
23#include <linux/delay.h> 24#include <linux/delay.h>
@@ -59,11 +60,17 @@ struct db1x_pcmcia_sock {
59#define BOARD_TYPE_DEFAULT 0 /* most boards */ 60#define BOARD_TYPE_DEFAULT 0 /* most boards */
60#define BOARD_TYPE_DB1200 1 /* IRQs aren't gpios */ 61#define BOARD_TYPE_DB1200 1 /* IRQs aren't gpios */
61#define BOARD_TYPE_PB1100 2 /* VS bits slightly different */ 62#define BOARD_TYPE_PB1100 2 /* VS bits slightly different */
63#define BOARD_TYPE_DB1300 3 /* no power control */
62 int board_type; 64 int board_type;
63}; 65};
64 66
65#define to_db1x_socket(x) container_of(x, struct db1x_pcmcia_sock, socket) 67#define to_db1x_socket(x) container_of(x, struct db1x_pcmcia_sock, socket)
66 68
69static int db1300_card_inserted(struct db1x_pcmcia_sock *sock)
70{
71 return bcsr_read(BCSR_SIGSTAT) & (1 << 8);
72}
73
67/* DB/PB1200: check CPLD SIGSTATUS register bit 10/12 */ 74/* DB/PB1200: check CPLD SIGSTATUS register bit 10/12 */
68static int db1200_card_inserted(struct db1x_pcmcia_sock *sock) 75static int db1200_card_inserted(struct db1x_pcmcia_sock *sock)
69{ 76{
@@ -84,6 +91,8 @@ static int db1x_card_inserted(struct db1x_pcmcia_sock *sock)
84 switch (sock->board_type) { 91 switch (sock->board_type) {
85 case BOARD_TYPE_DB1200: 92 case BOARD_TYPE_DB1200:
86 return db1200_card_inserted(sock); 93 return db1200_card_inserted(sock);
94 case BOARD_TYPE_DB1300:
95 return db1300_card_inserted(sock);
87 default: 96 default:
88 return db1000_card_inserted(sock); 97 return db1000_card_inserted(sock);
89 } 98 }
@@ -160,7 +169,8 @@ static int db1x_pcmcia_setup_irqs(struct db1x_pcmcia_sock *sock)
160 * ejection handler have been registered and the currently 169 * ejection handler have been registered and the currently
161 * active one disabled. 170 * active one disabled.
162 */ 171 */
163 if (sock->board_type == BOARD_TYPE_DB1200) { 172 if ((sock->board_type == BOARD_TYPE_DB1200) ||
173 (sock->board_type == BOARD_TYPE_DB1300)) {
164 ret = request_irq(sock->insert_irq, db1200_pcmcia_cdirq, 174 ret = request_irq(sock->insert_irq, db1200_pcmcia_cdirq,
165 IRQF_DISABLED, "pcmcia_insert", sock); 175 IRQF_DISABLED, "pcmcia_insert", sock);
166 if (ret) 176 if (ret)
@@ -174,7 +184,7 @@ static int db1x_pcmcia_setup_irqs(struct db1x_pcmcia_sock *sock)
174 } 184 }
175 185
176 /* enable the currently silent one */ 186 /* enable the currently silent one */
177 if (db1200_card_inserted(sock)) 187 if (db1x_card_inserted(sock))
178 enable_irq(sock->eject_irq); 188 enable_irq(sock->eject_irq);
179 else 189 else
180 enable_irq(sock->insert_irq); 190 enable_irq(sock->insert_irq);
@@ -270,7 +280,8 @@ static int db1x_pcmcia_configure(struct pcmcia_socket *skt,
270 } 280 }
271 281
272 /* create new voltage code */ 282 /* create new voltage code */
273 cr_set |= ((v << 2) | p) << (sock->nr * 8); 283 if (sock->board_type != BOARD_TYPE_DB1300)
284 cr_set |= ((v << 2) | p) << (sock->nr * 8);
274 285
275 changed = state->flags ^ sock->old_flags; 286 changed = state->flags ^ sock->old_flags;
276 287
@@ -343,6 +354,10 @@ static int db1x_pcmcia_get_status(struct pcmcia_socket *skt,
343 /* if Vcc is not zero, we have applied power to a card */ 354 /* if Vcc is not zero, we have applied power to a card */
344 status |= GET_VCC(cr, sock->nr) ? SS_POWERON : 0; 355 status |= GET_VCC(cr, sock->nr) ? SS_POWERON : 0;
345 356
357 /* DB1300: power always on, but don't tell when no card present */
358 if ((sock->board_type == BOARD_TYPE_DB1300) && (status & SS_DETECT))
359 status = SS_POWERON | SS_3VCARD | SS_DETECT;
360
346 /* reset de-asserted? then we're ready */ 361 /* reset de-asserted? then we're ready */
347 status |= (GET_RESET(cr, sock->nr)) ? SS_READY : SS_RESET; 362 status |= (GET_RESET(cr, sock->nr)) ? SS_READY : SS_RESET;
348 363
@@ -419,6 +434,9 @@ static int __devinit db1x_pcmcia_socket_probe(struct platform_device *pdev)
419 case BCSR_WHOAMI_PB1200 ... BCSR_WHOAMI_DB1200: 434 case BCSR_WHOAMI_PB1200 ... BCSR_WHOAMI_DB1200:
420 sock->board_type = BOARD_TYPE_DB1200; 435 sock->board_type = BOARD_TYPE_DB1200;
421 break; 436 break;
437 case BCSR_WHOAMI_DB1300:
438 sock->board_type = BOARD_TYPE_DB1300;
439 break;
422 default: 440 default:
423 printk(KERN_INFO "db1xxx-ss: unknown board %d!\n", bid); 441 printk(KERN_INFO "db1xxx-ss: unknown board %d!\n", bid);
424 ret = -ENODEV; 442 ret = -ENODEV;
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index a1fd73df5416..369e092bf3d5 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -87,12 +87,12 @@ config SPI_BFIN_SPORT
87 Enable support for a SPI bus via the Blackfin SPORT peripheral. 87 Enable support for a SPI bus via the Blackfin SPORT peripheral.
88 88
89config SPI_AU1550 89config SPI_AU1550
90 tristate "Au1550/Au12x0 SPI Controller" 90 tristate "Au1550/Au1200/Au1300 SPI Controller"
91 depends on MIPS_ALCHEMY && EXPERIMENTAL 91 depends on MIPS_ALCHEMY && EXPERIMENTAL
92 select SPI_BITBANG 92 select SPI_BITBANG
93 help 93 help
94 If you say yes to this option, support will be included for the 94 If you say yes to this option, support will be included for the
95 Au1550 SPI controller (may also work with Au1200,Au1210,Au1250). 95 PSC SPI controller found on Au1550, Au1200 and Au1300 series.
96 96
97config SPI_BITBANG 97config SPI_BITBANG
98 tristate "Utilities for Bitbanging SPI masters" 98 tristate "Utilities for Bitbanging SPI masters"
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 925a1e547a83..95a0f5fe7d42 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -1610,4 +1610,27 @@ config SERIAL_XILINX_PS_UART_CONSOLE
1610 help 1610 help
1611 Enable a Xilinx PS UART port to be the system console. 1611 Enable a Xilinx PS UART port to be the system console.
1612 1612
1613config SERIAL_AR933X
1614 bool "AR933X serial port support"
1615 depends on SOC_AR933X
1616 select SERIAL_CORE
1617 help
1618 If you have an Atheros AR933X SOC based board and want to use the
1619 built-in UART of the SoC, say Y to this option.
1620
1621config SERIAL_AR933X_CONSOLE
1622 bool "Console on AR933X serial port"
1623 depends on SERIAL_AR933X=y
1624 select SERIAL_CORE_CONSOLE
1625 help
1626 Enable a built-in UART port of the AR933X to be the system console.
1627
1628config SERIAL_AR933X_NR_UARTS
1629 int "Maximum number of AR933X serial ports"
1630 depends on SERIAL_AR933X
1631 default "2"
1632 help
1633 Set this to the number of serial ports you want the driver
1634 to support.
1635
1613endmenu 1636endmenu
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
index e10cf5b54b6d..76811cc58591 100644
--- a/drivers/tty/serial/Makefile
+++ b/drivers/tty/serial/Makefile
@@ -94,3 +94,4 @@ obj-$(CONFIG_SERIAL_MSM_SMD) += msm_smd_tty.o
94obj-$(CONFIG_SERIAL_MXS_AUART) += mxs-auart.o 94obj-$(CONFIG_SERIAL_MXS_AUART) += mxs-auart.o
95obj-$(CONFIG_SERIAL_LANTIQ) += lantiq.o 95obj-$(CONFIG_SERIAL_LANTIQ) += lantiq.o
96obj-$(CONFIG_SERIAL_XILINX_PS_UART) += xilinx_uartps.o 96obj-$(CONFIG_SERIAL_XILINX_PS_UART) += xilinx_uartps.o
97obj-$(CONFIG_SERIAL_AR933X) += ar933x_uart.o
diff --git a/drivers/tty/serial/ar933x_uart.c b/drivers/tty/serial/ar933x_uart.c
new file mode 100644
index 000000000000..e4f60e2b87f3
--- /dev/null
+++ b/drivers/tty/serial/ar933x_uart.c
@@ -0,0 +1,688 @@
1/*
2 * Atheros AR933X SoC built-in UART driver
3 *
4 * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published
10 * by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/ioport.h>
15#include <linux/init.h>
16#include <linux/console.h>
17#include <linux/sysrq.h>
18#include <linux/delay.h>
19#include <linux/platform_device.h>
20#include <linux/tty.h>
21#include <linux/tty_flip.h>
22#include <linux/serial_core.h>
23#include <linux/serial.h>
24#include <linux/slab.h>
25#include <linux/io.h>
26#include <linux/irq.h>
27
28#include <asm/mach-ath79/ar933x_uart.h>
29#include <asm/mach-ath79/ar933x_uart_platform.h>
30
31#define DRIVER_NAME "ar933x-uart"
32
33#define AR933X_DUMMY_STATUS_RD 0x01
34
35static struct uart_driver ar933x_uart_driver;
36
37struct ar933x_uart_port {
38 struct uart_port port;
39 unsigned int ier; /* shadow Interrupt Enable Register */
40};
41
42static inline unsigned int ar933x_uart_read(struct ar933x_uart_port *up,
43 int offset)
44{
45 return readl(up->port.membase + offset);
46}
47
48static inline void ar933x_uart_write(struct ar933x_uart_port *up,
49 int offset, unsigned int value)
50{
51 writel(value, up->port.membase + offset);
52}
53
54static inline void ar933x_uart_rmw(struct ar933x_uart_port *up,
55 unsigned int offset,
56 unsigned int mask,
57 unsigned int val)
58{
59 unsigned int t;
60
61 t = ar933x_uart_read(up, offset);
62 t &= ~mask;
63 t |= val;
64 ar933x_uart_write(up, offset, t);
65}
66
67static inline void ar933x_uart_rmw_set(struct ar933x_uart_port *up,
68 unsigned int offset,
69 unsigned int val)
70{
71 ar933x_uart_rmw(up, offset, 0, val);
72}
73
74static inline void ar933x_uart_rmw_clear(struct ar933x_uart_port *up,
75 unsigned int offset,
76 unsigned int val)
77{
78 ar933x_uart_rmw(up, offset, val, 0);
79}
80
81static inline void ar933x_uart_start_tx_interrupt(struct ar933x_uart_port *up)
82{
83 up->ier |= AR933X_UART_INT_TX_EMPTY;
84 ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier);
85}
86
87static inline void ar933x_uart_stop_tx_interrupt(struct ar933x_uart_port *up)
88{
89 up->ier &= ~AR933X_UART_INT_TX_EMPTY;
90 ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier);
91}
92
93static inline void ar933x_uart_putc(struct ar933x_uart_port *up, int ch)
94{
95 unsigned int rdata;
96
97 rdata = ch & AR933X_UART_DATA_TX_RX_MASK;
98 rdata |= AR933X_UART_DATA_TX_CSR;
99 ar933x_uart_write(up, AR933X_UART_DATA_REG, rdata);
100}
101
102static unsigned int ar933x_uart_tx_empty(struct uart_port *port)
103{
104 struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
105 unsigned long flags;
106 unsigned int rdata;
107
108 spin_lock_irqsave(&up->port.lock, flags);
109 rdata = ar933x_uart_read(up, AR933X_UART_DATA_REG);
110 spin_unlock_irqrestore(&up->port.lock, flags);
111
112 return (rdata & AR933X_UART_DATA_TX_CSR) ? 0 : TIOCSER_TEMT;
113}
114
115static unsigned int ar933x_uart_get_mctrl(struct uart_port *port)
116{
117 return TIOCM_CAR;
118}
119
120static void ar933x_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
121{
122}
123
124static void ar933x_uart_start_tx(struct uart_port *port)
125{
126 struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
127
128 ar933x_uart_start_tx_interrupt(up);
129}
130
131static void ar933x_uart_stop_tx(struct uart_port *port)
132{
133 struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
134
135 ar933x_uart_stop_tx_interrupt(up);
136}
137
138static void ar933x_uart_stop_rx(struct uart_port *port)
139{
140 struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
141
142 up->ier &= ~AR933X_UART_INT_RX_VALID;
143 ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier);
144}
145
146static void ar933x_uart_break_ctl(struct uart_port *port, int break_state)
147{
148 struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
149 unsigned long flags;
150
151 spin_lock_irqsave(&up->port.lock, flags);
152 if (break_state == -1)
153 ar933x_uart_rmw_set(up, AR933X_UART_CS_REG,
154 AR933X_UART_CS_TX_BREAK);
155 else
156 ar933x_uart_rmw_clear(up, AR933X_UART_CS_REG,
157 AR933X_UART_CS_TX_BREAK);
158 spin_unlock_irqrestore(&up->port.lock, flags);
159}
160
161static void ar933x_uart_enable_ms(struct uart_port *port)
162{
163}
164
165static void ar933x_uart_set_termios(struct uart_port *port,
166 struct ktermios *new,
167 struct ktermios *old)
168{
169 struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
170 unsigned int cs;
171 unsigned long flags;
172 unsigned int baud, scale;
173
174 /* Only CS8 is supported */
175 new->c_cflag &= ~CSIZE;
176 new->c_cflag |= CS8;
177
178 /* Only one stop bit is supported */
179 new->c_cflag &= ~CSTOPB;
180
181 cs = 0;
182 if (new->c_cflag & PARENB) {
183 if (!(new->c_cflag & PARODD))
184 cs |= AR933X_UART_CS_PARITY_EVEN;
185 else
186 cs |= AR933X_UART_CS_PARITY_ODD;
187 } else {
188 cs |= AR933X_UART_CS_PARITY_NONE;
189 }
190
191 /* Mark/space parity is not supported */
192 new->c_cflag &= ~CMSPAR;
193
194 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
195 scale = (port->uartclk / (16 * baud)) - 1;
196
197 /*
198 * Ok, we're now changing the port state. Do it with
199 * interrupts disabled.
200 */
201 spin_lock_irqsave(&up->port.lock, flags);
202
203 /* Update the per-port timeout. */
204 uart_update_timeout(port, new->c_cflag, baud);
205
206 up->port.ignore_status_mask = 0;
207
208 /* ignore all characters if CREAD is not set */
209 if ((new->c_cflag & CREAD) == 0)
210 up->port.ignore_status_mask |= AR933X_DUMMY_STATUS_RD;
211
212 ar933x_uart_write(up, AR933X_UART_CLOCK_REG,
213 scale << AR933X_UART_CLOCK_SCALE_S | 8192);
214
215 /* setup configuration register */
216 ar933x_uart_rmw(up, AR933X_UART_CS_REG, AR933X_UART_CS_PARITY_M, cs);
217
218 /* enable host interrupt */
219 ar933x_uart_rmw_set(up, AR933X_UART_CS_REG,
220 AR933X_UART_CS_HOST_INT_EN);
221
222 spin_unlock_irqrestore(&up->port.lock, flags);
223
224 if (tty_termios_baud_rate(new))
225 tty_termios_encode_baud_rate(new, baud, baud);
226}
227
228static void ar933x_uart_rx_chars(struct ar933x_uart_port *up)
229{
230 struct tty_struct *tty;
231 int max_count = 256;
232
233 tty = tty_port_tty_get(&up->port.state->port);
234 do {
235 unsigned int rdata;
236 unsigned char ch;
237
238 rdata = ar933x_uart_read(up, AR933X_UART_DATA_REG);
239 if ((rdata & AR933X_UART_DATA_RX_CSR) == 0)
240 break;
241
242 /* remove the character from the FIFO */
243 ar933x_uart_write(up, AR933X_UART_DATA_REG,
244 AR933X_UART_DATA_RX_CSR);
245
246 if (!tty) {
247 /* discard the data if no tty available */
248 continue;
249 }
250
251 up->port.icount.rx++;
252 ch = rdata & AR933X_UART_DATA_TX_RX_MASK;
253
254 if (uart_handle_sysrq_char(&up->port, ch))
255 continue;
256
257 if ((up->port.ignore_status_mask & AR933X_DUMMY_STATUS_RD) == 0)
258 tty_insert_flip_char(tty, ch, TTY_NORMAL);
259 } while (max_count-- > 0);
260
261 if (tty) {
262 tty_flip_buffer_push(tty);
263 tty_kref_put(tty);
264 }
265}
266
267static void ar933x_uart_tx_chars(struct ar933x_uart_port *up)
268{
269 struct circ_buf *xmit = &up->port.state->xmit;
270 int count;
271
272 if (uart_tx_stopped(&up->port))
273 return;
274
275 count = up->port.fifosize;
276 do {
277 unsigned int rdata;
278
279 rdata = ar933x_uart_read(up, AR933X_UART_DATA_REG);
280 if ((rdata & AR933X_UART_DATA_TX_CSR) == 0)
281 break;
282
283 if (up->port.x_char) {
284 ar933x_uart_putc(up, up->port.x_char);
285 up->port.icount.tx++;
286 up->port.x_char = 0;
287 continue;
288 }
289
290 if (uart_circ_empty(xmit))
291 break;
292
293 ar933x_uart_putc(up, xmit->buf[xmit->tail]);
294
295 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
296 up->port.icount.tx++;
297 } while (--count > 0);
298
299 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
300 uart_write_wakeup(&up->port);
301
302 if (!uart_circ_empty(xmit))
303 ar933x_uart_start_tx_interrupt(up);
304}
305
306static irqreturn_t ar933x_uart_interrupt(int irq, void *dev_id)
307{
308 struct ar933x_uart_port *up = dev_id;
309 unsigned int status;
310
311 status = ar933x_uart_read(up, AR933X_UART_CS_REG);
312 if ((status & AR933X_UART_CS_HOST_INT) == 0)
313 return IRQ_NONE;
314
315 spin_lock(&up->port.lock);
316
317 status = ar933x_uart_read(up, AR933X_UART_INT_REG);
318 status &= ar933x_uart_read(up, AR933X_UART_INT_EN_REG);
319
320 if (status & AR933X_UART_INT_RX_VALID) {
321 ar933x_uart_write(up, AR933X_UART_INT_REG,
322 AR933X_UART_INT_RX_VALID);
323 ar933x_uart_rx_chars(up);
324 }
325
326 if (status & AR933X_UART_INT_TX_EMPTY) {
327 ar933x_uart_write(up, AR933X_UART_INT_REG,
328 AR933X_UART_INT_TX_EMPTY);
329 ar933x_uart_stop_tx_interrupt(up);
330 ar933x_uart_tx_chars(up);
331 }
332
333 spin_unlock(&up->port.lock);
334
335 return IRQ_HANDLED;
336}
337
338static int ar933x_uart_startup(struct uart_port *port)
339{
340 struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
341 unsigned long flags;
342 int ret;
343
344 ret = request_irq(up->port.irq, ar933x_uart_interrupt,
345 up->port.irqflags, dev_name(up->port.dev), up);
346 if (ret)
347 return ret;
348
349 spin_lock_irqsave(&up->port.lock, flags);
350
351 /* Enable HOST interrupts */
352 ar933x_uart_rmw_set(up, AR933X_UART_CS_REG,
353 AR933X_UART_CS_HOST_INT_EN);
354
355 /* Enable RX interrupts */
356 up->ier = AR933X_UART_INT_RX_VALID;
357 ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier);
358
359 spin_unlock_irqrestore(&up->port.lock, flags);
360
361 return 0;
362}
363
364static void ar933x_uart_shutdown(struct uart_port *port)
365{
366 struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
367
368 /* Disable all interrupts */
369 up->ier = 0;
370 ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier);
371
372 /* Disable break condition */
373 ar933x_uart_rmw_clear(up, AR933X_UART_CS_REG,
374 AR933X_UART_CS_TX_BREAK);
375
376 free_irq(up->port.irq, up);
377}
378
379static const char *ar933x_uart_type(struct uart_port *port)
380{
381 return (port->type == PORT_AR933X) ? "AR933X UART" : NULL;
382}
383
384static void ar933x_uart_release_port(struct uart_port *port)
385{
386 /* Nothing to release ... */
387}
388
389static int ar933x_uart_request_port(struct uart_port *port)
390{
391 /* UARTs always present */
392 return 0;
393}
394
395static void ar933x_uart_config_port(struct uart_port *port, int flags)
396{
397 if (flags & UART_CONFIG_TYPE)
398 port->type = PORT_AR933X;
399}
400
401static int ar933x_uart_verify_port(struct uart_port *port,
402 struct serial_struct *ser)
403{
404 if (ser->type != PORT_UNKNOWN &&
405 ser->type != PORT_AR933X)
406 return -EINVAL;
407
408 if (ser->irq < 0 || ser->irq >= NR_IRQS)
409 return -EINVAL;
410
411 if (ser->baud_base < 28800)
412 return -EINVAL;
413
414 return 0;
415}
416
417static struct uart_ops ar933x_uart_ops = {
418 .tx_empty = ar933x_uart_tx_empty,
419 .set_mctrl = ar933x_uart_set_mctrl,
420 .get_mctrl = ar933x_uart_get_mctrl,
421 .stop_tx = ar933x_uart_stop_tx,
422 .start_tx = ar933x_uart_start_tx,
423 .stop_rx = ar933x_uart_stop_rx,
424 .enable_ms = ar933x_uart_enable_ms,
425 .break_ctl = ar933x_uart_break_ctl,
426 .startup = ar933x_uart_startup,
427 .shutdown = ar933x_uart_shutdown,
428 .set_termios = ar933x_uart_set_termios,
429 .type = ar933x_uart_type,
430 .release_port = ar933x_uart_release_port,
431 .request_port = ar933x_uart_request_port,
432 .config_port = ar933x_uart_config_port,
433 .verify_port = ar933x_uart_verify_port,
434};
435
436#ifdef CONFIG_SERIAL_AR933X_CONSOLE
437
438static struct ar933x_uart_port *
439ar933x_console_ports[CONFIG_SERIAL_AR933X_NR_UARTS];
440
441static void ar933x_uart_wait_xmitr(struct ar933x_uart_port *up)
442{
443 unsigned int status;
444 unsigned int timeout = 60000;
445
446 /* Wait up to 60ms for the character(s) to be sent. */
447 do {
448 status = ar933x_uart_read(up, AR933X_UART_DATA_REG);
449 if (--timeout == 0)
450 break;
451 udelay(1);
452 } while ((status & AR933X_UART_DATA_TX_CSR) == 0);
453}
454
455static void ar933x_uart_console_putchar(struct uart_port *port, int ch)
456{
457 struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
458
459 ar933x_uart_wait_xmitr(up);
460 ar933x_uart_putc(up, ch);
461}
462
463static void ar933x_uart_console_write(struct console *co, const char *s,
464 unsigned int count)
465{
466 struct ar933x_uart_port *up = ar933x_console_ports[co->index];
467 unsigned long flags;
468 unsigned int int_en;
469 int locked = 1;
470
471 local_irq_save(flags);
472
473 if (up->port.sysrq)
474 locked = 0;
475 else if (oops_in_progress)
476 locked = spin_trylock(&up->port.lock);
477 else
478 spin_lock(&up->port.lock);
479
480 /*
481 * First save the IER then disable the interrupts
482 */
483 int_en = ar933x_uart_read(up, AR933X_UART_INT_EN_REG);
484 ar933x_uart_write(up, AR933X_UART_INT_EN_REG, 0);
485
486 uart_console_write(&up->port, s, count, ar933x_uart_console_putchar);
487
488 /*
489 * Finally, wait for transmitter to become empty
490 * and restore the IER
491 */
492 ar933x_uart_wait_xmitr(up);
493 ar933x_uart_write(up, AR933X_UART_INT_EN_REG, int_en);
494
495 ar933x_uart_write(up, AR933X_UART_INT_REG, AR933X_UART_INT_ALLINTS);
496
497 if (locked)
498 spin_unlock(&up->port.lock);
499
500 local_irq_restore(flags);
501}
502
503static int ar933x_uart_console_setup(struct console *co, char *options)
504{
505 struct ar933x_uart_port *up;
506 int baud = 115200;
507 int bits = 8;
508 int parity = 'n';
509 int flow = 'n';
510
511 if (co->index < 0 || co->index >= CONFIG_SERIAL_AR933X_NR_UARTS)
512 return -EINVAL;
513
514 up = ar933x_console_ports[co->index];
515 if (!up)
516 return -ENODEV;
517
518 if (options)
519 uart_parse_options(options, &baud, &parity, &bits, &flow);
520
521 return uart_set_options(&up->port, co, baud, parity, bits, flow);
522}
523
524static struct console ar933x_uart_console = {
525 .name = "ttyATH",
526 .write = ar933x_uart_console_write,
527 .device = uart_console_device,
528 .setup = ar933x_uart_console_setup,
529 .flags = CON_PRINTBUFFER,
530 .index = -1,
531 .data = &ar933x_uart_driver,
532};
533
534static void ar933x_uart_add_console_port(struct ar933x_uart_port *up)
535{
536 ar933x_console_ports[up->port.line] = up;
537}
538
539#define AR933X_SERIAL_CONSOLE (&ar933x_uart_console)
540
541#else
542
543static inline void ar933x_uart_add_console_port(struct ar933x_uart_port *up) {}
544
545#define AR933X_SERIAL_CONSOLE NULL
546
547#endif /* CONFIG_SERIAL_AR933X_CONSOLE */
548
549static struct uart_driver ar933x_uart_driver = {
550 .owner = THIS_MODULE,
551 .driver_name = DRIVER_NAME,
552 .dev_name = "ttyATH",
553 .nr = CONFIG_SERIAL_AR933X_NR_UARTS,
554 .cons = AR933X_SERIAL_CONSOLE,
555};
556
557static int __devinit ar933x_uart_probe(struct platform_device *pdev)
558{
559 struct ar933x_uart_platform_data *pdata;
560 struct ar933x_uart_port *up;
561 struct uart_port *port;
562 struct resource *mem_res;
563 struct resource *irq_res;
564 int id;
565 int ret;
566
567 pdata = pdev->dev.platform_data;
568 if (!pdata)
569 return -EINVAL;
570
571 id = pdev->id;
572 if (id == -1)
573 id = 0;
574
575 if (id > CONFIG_SERIAL_AR933X_NR_UARTS)
576 return -EINVAL;
577
578 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
579 if (!mem_res) {
580 dev_err(&pdev->dev, "no MEM resource\n");
581 return -EINVAL;
582 }
583
584 irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
585 if (!irq_res) {
586 dev_err(&pdev->dev, "no IRQ resource\n");
587 return -EINVAL;
588 }
589
590 up = kzalloc(sizeof(struct ar933x_uart_port), GFP_KERNEL);
591 if (!up)
592 return -ENOMEM;
593
594 port = &up->port;
595 port->mapbase = mem_res->start;
596
597 port->membase = ioremap(mem_res->start, AR933X_UART_REGS_SIZE);
598 if (!port->membase) {
599 ret = -ENOMEM;
600 goto err_free_up;
601 }
602
603 port->line = id;
604 port->irq = irq_res->start;
605 port->dev = &pdev->dev;
606 port->type = PORT_AR933X;
607 port->iotype = UPIO_MEM32;
608 port->uartclk = pdata->uartclk;
609
610 port->regshift = 2;
611 port->fifosize = AR933X_UART_FIFO_SIZE;
612 port->ops = &ar933x_uart_ops;
613
614 ar933x_uart_add_console_port(up);
615
616 ret = uart_add_one_port(&ar933x_uart_driver, &up->port);
617 if (ret)
618 goto err_unmap;
619
620 platform_set_drvdata(pdev, up);
621 return 0;
622
623err_unmap:
624 iounmap(up->port.membase);
625err_free_up:
626 kfree(up);
627 return ret;
628}
629
630static int __devexit ar933x_uart_remove(struct platform_device *pdev)
631{
632 struct ar933x_uart_port *up;
633
634 up = platform_get_drvdata(pdev);
635 platform_set_drvdata(pdev, NULL);
636
637 if (up) {
638 uart_remove_one_port(&ar933x_uart_driver, &up->port);
639 iounmap(up->port.membase);
640 kfree(up);
641 }
642
643 return 0;
644}
645
646static struct platform_driver ar933x_uart_platform_driver = {
647 .probe = ar933x_uart_probe,
648 .remove = __devexit_p(ar933x_uart_remove),
649 .driver = {
650 .name = DRIVER_NAME,
651 .owner = THIS_MODULE,
652 },
653};
654
655static int __init ar933x_uart_init(void)
656{
657 int ret;
658
659 ar933x_uart_driver.nr = CONFIG_SERIAL_AR933X_NR_UARTS;
660 ret = uart_register_driver(&ar933x_uart_driver);
661 if (ret)
662 goto err_out;
663
664 ret = platform_driver_register(&ar933x_uart_platform_driver);
665 if (ret)
666 goto err_unregister_uart_driver;
667
668 return 0;
669
670err_unregister_uart_driver:
671 uart_unregister_driver(&ar933x_uart_driver);
672err_out:
673 return ret;
674}
675
676static void __exit ar933x_uart_exit(void)
677{
678 platform_driver_unregister(&ar933x_uart_platform_driver);
679 uart_unregister_driver(&ar933x_uart_driver);
680}
681
682module_init(ar933x_uart_init);
683module_exit(ar933x_uart_exit);
684
685MODULE_DESCRIPTION("Atheros AR933X UART driver");
686MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
687MODULE_LICENSE("GPL v2");
688MODULE_ALIAS("platform:" DRIVER_NAME);
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 060e0e2b1ae6..8b094b4f6531 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -210,7 +210,7 @@ config USB_CNS3XXX_EHCI
210 210
211config USB_EHCI_ATH79 211config USB_EHCI_ATH79
212 bool "EHCI support for AR7XXX/AR9XXX SoCs" 212 bool "EHCI support for AR7XXX/AR9XXX SoCs"
213 depends on USB_EHCI_HCD && (SOC_AR71XX || SOC_AR724X || SOC_AR913X) 213 depends on USB_EHCI_HCD && (SOC_AR71XX || SOC_AR724X || SOC_AR913X || SOC_AR933X)
214 select USB_EHCI_ROOT_HUB_TT 214 select USB_EHCI_ROOT_HUB_TT
215 default y 215 default y
216 ---help--- 216 ---help---
diff --git a/drivers/usb/host/alchemy-common.c b/drivers/usb/host/alchemy-common.c
index b4192c964d0d..936af8359fb2 100644
--- a/drivers/usb/host/alchemy-common.c
+++ b/drivers/usb/host/alchemy-common.c
@@ -52,9 +52,263 @@
52 USBCFG_EBE | USBCFG_EME | USBCFG_OBE | \ 52 USBCFG_EBE | USBCFG_EME | USBCFG_OBE | \
53 USBCFG_OME) 53 USBCFG_OME)
54 54
55/* Au1300 USB config registers */
56#define USB_DWC_CTRL1 0x00
57#define USB_DWC_CTRL2 0x04
58#define USB_VBUS_TIMER 0x10
59#define USB_SBUS_CTRL 0x14
60#define USB_MSR_ERR 0x18
61#define USB_DWC_CTRL3 0x1C
62#define USB_DWC_CTRL4 0x20
63#define USB_OTG_STATUS 0x28
64#define USB_DWC_CTRL5 0x2C
65#define USB_DWC_CTRL6 0x30
66#define USB_DWC_CTRL7 0x34
67#define USB_PHY_STATUS 0xC0
68#define USB_INT_STATUS 0xC4
69#define USB_INT_ENABLE 0xC8
70
71#define USB_DWC_CTRL1_OTGD 0x04 /* set to DISable OTG */
72#define USB_DWC_CTRL1_HSTRS 0x02 /* set to ENable EHCI */
73#define USB_DWC_CTRL1_DCRS 0x01 /* set to ENable UDC */
74
75#define USB_DWC_CTRL2_PHY1RS 0x04 /* set to enable PHY1 */
76#define USB_DWC_CTRL2_PHY0RS 0x02 /* set to enable PHY0 */
77#define USB_DWC_CTRL2_PHYRS 0x01 /* set to enable PHY */
78
79#define USB_DWC_CTRL3_OHCI1_CKEN (1 << 19)
80#define USB_DWC_CTRL3_OHCI0_CKEN (1 << 18)
81#define USB_DWC_CTRL3_EHCI0_CKEN (1 << 17)
82#define USB_DWC_CTRL3_OTG0_CKEN (1 << 16)
83
84#define USB_SBUS_CTRL_SBCA 0x04 /* coherent access */
85
86#define USB_INTEN_FORCE 0x20
87#define USB_INTEN_PHY 0x10
88#define USB_INTEN_UDC 0x08
89#define USB_INTEN_EHCI 0x04
90#define USB_INTEN_OHCI1 0x02
91#define USB_INTEN_OHCI0 0x01
55 92
56static DEFINE_SPINLOCK(alchemy_usb_lock); 93static DEFINE_SPINLOCK(alchemy_usb_lock);
57 94
95static inline void __au1300_usb_phyctl(void __iomem *base, int enable)
96{
97 unsigned long r, s;
98
99 r = __raw_readl(base + USB_DWC_CTRL2);
100 s = __raw_readl(base + USB_DWC_CTRL3);
101
102 s &= USB_DWC_CTRL3_OHCI1_CKEN | USB_DWC_CTRL3_OHCI0_CKEN |
103 USB_DWC_CTRL3_EHCI0_CKEN | USB_DWC_CTRL3_OTG0_CKEN;
104
105 if (enable) {
106 /* simply enable all PHYs */
107 r |= USB_DWC_CTRL2_PHY1RS | USB_DWC_CTRL2_PHY0RS |
108 USB_DWC_CTRL2_PHYRS;
109 __raw_writel(r, base + USB_DWC_CTRL2);
110 wmb();
111 } else if (!s) {
112 /* no USB block active, do disable all PHYs */
113 r &= ~(USB_DWC_CTRL2_PHY1RS | USB_DWC_CTRL2_PHY0RS |
114 USB_DWC_CTRL2_PHYRS);
115 __raw_writel(r, base + USB_DWC_CTRL2);
116 wmb();
117 }
118}
119
120static inline void __au1300_ohci_control(void __iomem *base, int enable, int id)
121{
122 unsigned long r;
123
124 if (enable) {
125 __raw_writel(1, base + USB_DWC_CTRL7); /* start OHCI clock */
126 wmb();
127
128 r = __raw_readl(base + USB_DWC_CTRL3); /* enable OHCI block */
129 r |= (id == 0) ? USB_DWC_CTRL3_OHCI0_CKEN
130 : USB_DWC_CTRL3_OHCI1_CKEN;
131 __raw_writel(r, base + USB_DWC_CTRL3);
132 wmb();
133
134 __au1300_usb_phyctl(base, enable); /* power up the PHYs */
135
136 r = __raw_readl(base + USB_INT_ENABLE);
137 r |= (id == 0) ? USB_INTEN_OHCI0 : USB_INTEN_OHCI1;
138 __raw_writel(r, base + USB_INT_ENABLE);
139 wmb();
140
141 /* reset the OHCI start clock bit */
142 __raw_writel(0, base + USB_DWC_CTRL7);
143 wmb();
144 } else {
145 r = __raw_readl(base + USB_INT_ENABLE);
146 r &= ~((id == 0) ? USB_INTEN_OHCI0 : USB_INTEN_OHCI1);
147 __raw_writel(r, base + USB_INT_ENABLE);
148 wmb();
149
150 r = __raw_readl(base + USB_DWC_CTRL3);
151 r &= ~((id == 0) ? USB_DWC_CTRL3_OHCI0_CKEN
152 : USB_DWC_CTRL3_OHCI1_CKEN);
153 __raw_writel(r, base + USB_DWC_CTRL3);
154 wmb();
155
156 __au1300_usb_phyctl(base, enable);
157 }
158}
159
160static inline void __au1300_ehci_control(void __iomem *base, int enable)
161{
162 unsigned long r;
163
164 if (enable) {
165 r = __raw_readl(base + USB_DWC_CTRL3);
166 r |= USB_DWC_CTRL3_EHCI0_CKEN;
167 __raw_writel(r, base + USB_DWC_CTRL3);
168 wmb();
169
170 r = __raw_readl(base + USB_DWC_CTRL1);
171 r |= USB_DWC_CTRL1_HSTRS;
172 __raw_writel(r, base + USB_DWC_CTRL1);
173 wmb();
174
175 __au1300_usb_phyctl(base, enable);
176
177 r = __raw_readl(base + USB_INT_ENABLE);
178 r |= USB_INTEN_EHCI;
179 __raw_writel(r, base + USB_INT_ENABLE);
180 wmb();
181 } else {
182 r = __raw_readl(base + USB_INT_ENABLE);
183 r &= ~USB_INTEN_EHCI;
184 __raw_writel(r, base + USB_INT_ENABLE);
185 wmb();
186
187 r = __raw_readl(base + USB_DWC_CTRL1);
188 r &= ~USB_DWC_CTRL1_HSTRS;
189 __raw_writel(r, base + USB_DWC_CTRL1);
190 wmb();
191
192 r = __raw_readl(base + USB_DWC_CTRL3);
193 r &= ~USB_DWC_CTRL3_EHCI0_CKEN;
194 __raw_writel(r, base + USB_DWC_CTRL3);
195 wmb();
196
197 __au1300_usb_phyctl(base, enable);
198 }
199}
200
201static inline void __au1300_udc_control(void __iomem *base, int enable)
202{
203 unsigned long r;
204
205 if (enable) {
206 r = __raw_readl(base + USB_DWC_CTRL1);
207 r |= USB_DWC_CTRL1_DCRS;
208 __raw_writel(r, base + USB_DWC_CTRL1);
209 wmb();
210
211 __au1300_usb_phyctl(base, enable);
212
213 r = __raw_readl(base + USB_INT_ENABLE);
214 r |= USB_INTEN_UDC;
215 __raw_writel(r, base + USB_INT_ENABLE);
216 wmb();
217 } else {
218 r = __raw_readl(base + USB_INT_ENABLE);
219 r &= ~USB_INTEN_UDC;
220 __raw_writel(r, base + USB_INT_ENABLE);
221 wmb();
222
223 r = __raw_readl(base + USB_DWC_CTRL1);
224 r &= ~USB_DWC_CTRL1_DCRS;
225 __raw_writel(r, base + USB_DWC_CTRL1);
226 wmb();
227
228 __au1300_usb_phyctl(base, enable);
229 }
230}
231
232static inline void __au1300_otg_control(void __iomem *base, int enable)
233{
234 unsigned long r;
235 if (enable) {
236 r = __raw_readl(base + USB_DWC_CTRL3);
237 r |= USB_DWC_CTRL3_OTG0_CKEN;
238 __raw_writel(r, base + USB_DWC_CTRL3);
239 wmb();
240
241 r = __raw_readl(base + USB_DWC_CTRL1);
242 r &= ~USB_DWC_CTRL1_OTGD;
243 __raw_writel(r, base + USB_DWC_CTRL1);
244 wmb();
245
246 __au1300_usb_phyctl(base, enable);
247 } else {
248 r = __raw_readl(base + USB_DWC_CTRL1);
249 r |= USB_DWC_CTRL1_OTGD;
250 __raw_writel(r, base + USB_DWC_CTRL1);
251 wmb();
252
253 r = __raw_readl(base + USB_DWC_CTRL3);
254 r &= ~USB_DWC_CTRL3_OTG0_CKEN;
255 __raw_writel(r, base + USB_DWC_CTRL3);
256 wmb();
257
258 __au1300_usb_phyctl(base, enable);
259 }
260}
261
262static inline int au1300_usb_control(int block, int enable)
263{
264 void __iomem *base =
265 (void __iomem *)KSEG1ADDR(AU1300_USB_CTL_PHYS_ADDR);
266 int ret = 0;
267
268 switch (block) {
269 case ALCHEMY_USB_OHCI0:
270 __au1300_ohci_control(base, enable, 0);
271 break;
272 case ALCHEMY_USB_OHCI1:
273 __au1300_ohci_control(base, enable, 1);
274 break;
275 case ALCHEMY_USB_EHCI0:
276 __au1300_ehci_control(base, enable);
277 break;
278 case ALCHEMY_USB_UDC0:
279 __au1300_udc_control(base, enable);
280 break;
281 case ALCHEMY_USB_OTG0:
282 __au1300_otg_control(base, enable);
283 break;
284 default:
285 ret = -ENODEV;
286 }
287 return ret;
288}
289
290static inline void au1300_usb_init(void)
291{
292 void __iomem *base =
293 (void __iomem *)KSEG1ADDR(AU1300_USB_CTL_PHYS_ADDR);
294
295 /* set some sane defaults. Note: we don't fiddle with DWC_CTRL4
296 * here at all: Port 2 routing (EHCI or UDC) must be set either
297 * by boot firmware or platform init code; I can't autodetect
298 * a sane setting.
299 */
300 __raw_writel(0, base + USB_INT_ENABLE); /* disable all USB irqs */
301 wmb();
302 __raw_writel(0, base + USB_DWC_CTRL3); /* disable all clocks */
303 wmb();
304 __raw_writel(~0, base + USB_MSR_ERR); /* clear all errors */
305 wmb();
306 __raw_writel(~0, base + USB_INT_STATUS); /* clear int status */
307 wmb();
308 /* set coherent access bit */
309 __raw_writel(USB_SBUS_CTRL_SBCA, base + USB_SBUS_CTRL);
310 wmb();
311}
58 312
59static inline void __au1200_ohci_control(void __iomem *base, int enable) 313static inline void __au1200_ohci_control(void __iomem *base, int enable)
60{ 314{
@@ -233,6 +487,9 @@ int alchemy_usb_control(int block, int enable)
233 case ALCHEMY_CPU_AU1200: 487 case ALCHEMY_CPU_AU1200:
234 ret = au1200_usb_control(block, enable); 488 ret = au1200_usb_control(block, enable);
235 break; 489 break;
490 case ALCHEMY_CPU_AU1300:
491 ret = au1300_usb_control(block, enable);
492 break;
236 default: 493 default:
237 ret = -ENODEV; 494 ret = -ENODEV;
238 } 495 }
@@ -281,6 +538,20 @@ static void au1200_usb_pm(int susp)
281 } 538 }
282} 539}
283 540
541static void au1300_usb_pm(int susp)
542{
543 void __iomem *base =
544 (void __iomem *)KSEG1ADDR(AU1300_USB_CTL_PHYS_ADDR);
545 /* remember Port2 routing */
546 if (susp) {
547 alchemy_usb_pmdata[0] = __raw_readl(base + USB_DWC_CTRL4);
548 } else {
549 au1300_usb_init();
550 __raw_writel(alchemy_usb_pmdata[0], base + USB_DWC_CTRL4);
551 wmb();
552 }
553}
554
284static void alchemy_usb_pm(int susp) 555static void alchemy_usb_pm(int susp)
285{ 556{
286 switch (alchemy_get_cputype()) { 557 switch (alchemy_get_cputype()) {
@@ -295,6 +566,9 @@ static void alchemy_usb_pm(int susp)
295 case ALCHEMY_CPU_AU1200: 566 case ALCHEMY_CPU_AU1200:
296 au1200_usb_pm(susp); 567 au1200_usb_pm(susp);
297 break; 568 break;
569 case ALCHEMY_CPU_AU1300:
570 au1300_usb_pm(susp);
571 break;
298 } 572 }
299} 573}
300 574
@@ -328,6 +602,9 @@ static int __init alchemy_usb_init(void)
328 case ALCHEMY_CPU_AU1200: 602 case ALCHEMY_CPU_AU1200:
329 au1200_usb_init(); 603 au1200_usb_init();
330 break; 604 break;
605 case ALCHEMY_CPU_AU1300:
606 au1300_usb_init();
607 break;
331 } 608 }
332 609
333 register_syscore_ops(&alchemy_usb_pm_ops); 610 register_syscore_ops(&alchemy_usb_pm_ops);
diff --git a/drivers/usb/host/ehci-ath79.c b/drivers/usb/host/ehci-ath79.c
index afb6743cf094..f1424f9bc363 100644
--- a/drivers/usb/host/ehci-ath79.c
+++ b/drivers/usb/host/ehci-ath79.c
@@ -33,6 +33,10 @@ static const struct platform_device_id ehci_ath79_id_table[] = {
33 .driver_data = EHCI_ATH79_IP_V2, 33 .driver_data = EHCI_ATH79_IP_V2,
34 }, 34 },
35 { 35 {
36 .name = "ar933x-ehci",
37 .driver_data = EHCI_ATH79_IP_V2,
38 },
39 {
36 /* terminating entry */ 40 /* terminating entry */
37 }, 41 },
38}; 42};
diff --git a/drivers/usb/host/ohci-au1xxx.c b/drivers/usb/host/ohci-au1xxx.c
index 9b66df8278f3..95d1a71dccad 100644
--- a/drivers/usb/host/ohci-au1xxx.c
+++ b/drivers/usb/host/ohci-au1xxx.c
@@ -89,7 +89,7 @@ static const struct hc_driver ohci_au1xxx_hc_driver = {
89 89
90static int ohci_hcd_au1xxx_drv_probe(struct platform_device *pdev) 90static int ohci_hcd_au1xxx_drv_probe(struct platform_device *pdev)
91{ 91{
92 int ret; 92 int ret, unit;
93 struct usb_hcd *hcd; 93 struct usb_hcd *hcd;
94 94
95 if (usb_disabled()) 95 if (usb_disabled())
@@ -120,7 +120,9 @@ static int ohci_hcd_au1xxx_drv_probe(struct platform_device *pdev)
120 goto err2; 120 goto err2;
121 } 121 }
122 122
123 if (alchemy_usb_control(ALCHEMY_USB_OHCI0, 1)) { 123 unit = (hcd->rsrc_start == AU1300_USB_OHCI1_PHYS_ADDR) ?
124 ALCHEMY_USB_OHCI1 : ALCHEMY_USB_OHCI0;
125 if (alchemy_usb_control(unit, 1)) {
124 printk(KERN_INFO "%s: controller init failed!\n", pdev->name); 126 printk(KERN_INFO "%s: controller init failed!\n", pdev->name);
125 ret = -ENODEV; 127 ret = -ENODEV;
126 goto err3; 128 goto err3;
@@ -135,7 +137,7 @@ static int ohci_hcd_au1xxx_drv_probe(struct platform_device *pdev)
135 return ret; 137 return ret;
136 } 138 }
137 139
138 alchemy_usb_control(ALCHEMY_USB_OHCI0, 0); 140 alchemy_usb_control(unit, 0);
139err3: 141err3:
140 iounmap(hcd->regs); 142 iounmap(hcd->regs);
141err2: 143err2:
@@ -148,9 +150,12 @@ err1:
148static int ohci_hcd_au1xxx_drv_remove(struct platform_device *pdev) 150static int ohci_hcd_au1xxx_drv_remove(struct platform_device *pdev)
149{ 151{
150 struct usb_hcd *hcd = platform_get_drvdata(pdev); 152 struct usb_hcd *hcd = platform_get_drvdata(pdev);
153 int unit;
151 154
155 unit = (hcd->rsrc_start == AU1300_USB_OHCI1_PHYS_ADDR) ?
156 ALCHEMY_USB_OHCI1 : ALCHEMY_USB_OHCI0;
152 usb_remove_hcd(hcd); 157 usb_remove_hcd(hcd);
153 alchemy_usb_control(ALCHEMY_USB_OHCI0, 0); 158 alchemy_usb_control(unit, 0);
154 iounmap(hcd->regs); 159 iounmap(hcd->regs);
155 release_mem_region(hcd->rsrc_start, hcd->rsrc_len); 160 release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
156 usb_put_hcd(hcd); 161 usb_put_hcd(hcd);
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index d83e967e4e15..acd4ba555e3a 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -1763,16 +1763,16 @@ config FB_AU1100
1763 au1100fb:panel=<name>. 1763 au1100fb:panel=<name>.
1764 1764
1765config FB_AU1200 1765config FB_AU1200
1766 bool "Au1200 LCD Driver" 1766 bool "Au1200/Au1300 LCD Driver"
1767 depends on (FB = y) && MIPS_ALCHEMY 1767 depends on (FB = y) && MIPS_ALCHEMY
1768 select FB_SYS_FILLRECT 1768 select FB_SYS_FILLRECT
1769 select FB_SYS_COPYAREA 1769 select FB_SYS_COPYAREA
1770 select FB_SYS_IMAGEBLIT 1770 select FB_SYS_IMAGEBLIT
1771 select FB_SYS_FOPS 1771 select FB_SYS_FOPS
1772 help 1772 help
1773 This is the framebuffer driver for the AMD Au1200 SOC. It can drive 1773 This is the framebuffer driver for the Au1200/Au1300 SOCs.
1774 various panels and CRTs by passing in kernel cmd line option 1774 It can drive various panels and CRTs by passing in kernel cmd line
1775 au1200fb:panel=<name>. 1775 option au1200fb:panel=<name>.
1776 1776
1777config FB_VT8500 1777config FB_VT8500
1778 bool "VT8500 LCD Driver" 1778 bool "VT8500 LCD Driver"
diff --git a/drivers/video/au1100fb.c b/drivers/video/au1100fb.c
index 649cb35de4ed..de9da6774fd9 100644
--- a/drivers/video/au1100fb.c
+++ b/drivers/video/au1100fb.c
@@ -60,18 +60,6 @@
60 60
61#include "au1100fb.h" 61#include "au1100fb.h"
62 62
63/*
64 * Sanity check. If this is a new Au1100 based board, search for
65 * the PB1100 ifdefs to make sure you modify the code accordingly.
66 */
67#if defined(CONFIG_MIPS_PB1100)
68 #include <asm/mach-pb1x00/pb1100.h>
69#elif defined(CONFIG_MIPS_DB1100)
70 #include <asm/mach-db1x00/db1x00.h>
71#else
72 #error "Unknown Au1100 board, Au1100 FB driver not supported"
73#endif
74
75#define DRIVER_NAME "au1100fb" 63#define DRIVER_NAME "au1100fb"
76#define DRIVER_DESC "LCD controller driver for AU1100 processors" 64#define DRIVER_DESC "LCD controller driver for AU1100 processors"
77 65
diff --git a/drivers/video/au1200fb.c b/drivers/video/au1200fb.c
index 72005598040f..04e4479d5afd 100644
--- a/drivers/video/au1200fb.c
+++ b/drivers/video/au1200fb.c
@@ -44,6 +44,7 @@
44#include <linux/slab.h> 44#include <linux/slab.h>
45 45
46#include <asm/mach-au1x00/au1000.h> 46#include <asm/mach-au1x00/au1000.h>
47#include <asm/mach-au1x00/au1200fb.h> /* platform_data */
47#include "au1200fb.h" 48#include "au1200fb.h"
48 49
49#define DRIVER_NAME "au1200fb" 50#define DRIVER_NAME "au1200fb"
@@ -143,6 +144,7 @@ struct au1200_lcd_iodata_t {
143/* Private, per-framebuffer management information (independent of the panel itself) */ 144/* Private, per-framebuffer management information (independent of the panel itself) */
144struct au1200fb_device { 145struct au1200fb_device {
145 struct fb_info *fb_info; /* FB driver info record */ 146 struct fb_info *fb_info; /* FB driver info record */
147 struct au1200fb_platdata *pd;
146 148
147 int plane; 149 int plane;
148 unsigned char* fb_mem; /* FrameBuffer memory map */ 150 unsigned char* fb_mem; /* FrameBuffer memory map */
@@ -201,9 +203,6 @@ struct window_settings {
201#define LCD_WINCTRL1_PO_16BPP LCD_WINCTRL1_PO_01 203#define LCD_WINCTRL1_PO_16BPP LCD_WINCTRL1_PO_01
202#endif 204#endif
203 205
204extern int board_au1200fb_panel_init (void);
205extern int board_au1200fb_panel_shutdown (void);
206
207/* 206/*
208 * Default window configurations 207 * Default window configurations
209 */ 208 */
@@ -334,8 +333,6 @@ struct panel_settings
334 uint32 mode_toyclksrc; 333 uint32 mode_toyclksrc;
335 uint32 mode_backlight; 334 uint32 mode_backlight;
336 uint32 mode_auxpll; 335 uint32 mode_auxpll;
337 int (*device_init)(void);
338 int (*device_shutdown)(void);
339#define Xres min_xres 336#define Xres min_xres
340#define Yres min_yres 337#define Yres min_yres
341 u32 min_xres; /* Minimum horizontal resolution */ 338 u32 min_xres; /* Minimum horizontal resolution */
@@ -385,8 +382,6 @@ static struct panel_settings known_lcd_panels[] =
385 .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ 382 .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
386 .mode_backlight = 0x00000000, 383 .mode_backlight = 0x00000000,
387 .mode_auxpll = 8, /* 96MHz AUXPLL */ 384 .mode_auxpll = 8, /* 96MHz AUXPLL */
388 .device_init = NULL,
389 .device_shutdown = NULL,
390 320, 320, 385 320, 320,
391 240, 240, 386 240, 240,
392 }, 387 },
@@ -415,8 +410,6 @@ static struct panel_settings known_lcd_panels[] =
415 .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ 410 .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
416 .mode_backlight = 0x00000000, 411 .mode_backlight = 0x00000000,
417 .mode_auxpll = 8, /* 96MHz AUXPLL */ 412 .mode_auxpll = 8, /* 96MHz AUXPLL */
418 .device_init = NULL,
419 .device_shutdown = NULL,
420 640, 480, 413 640, 480,
421 640, 480, 414 640, 480,
422 }, 415 },
@@ -445,8 +438,6 @@ static struct panel_settings known_lcd_panels[] =
445 .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ 438 .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
446 .mode_backlight = 0x00000000, 439 .mode_backlight = 0x00000000,
447 .mode_auxpll = 8, /* 96MHz AUXPLL */ 440 .mode_auxpll = 8, /* 96MHz AUXPLL */
448 .device_init = NULL,
449 .device_shutdown = NULL,
450 800, 800, 441 800, 800,
451 600, 600, 442 600, 600,
452 }, 443 },
@@ -475,8 +466,6 @@ static struct panel_settings known_lcd_panels[] =
475 .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ 466 .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
476 .mode_backlight = 0x00000000, 467 .mode_backlight = 0x00000000,
477 .mode_auxpll = 6, /* 72MHz AUXPLL */ 468 .mode_auxpll = 6, /* 72MHz AUXPLL */
478 .device_init = NULL,
479 .device_shutdown = NULL,
480 1024, 1024, 469 1024, 1024,
481 768, 768, 470 768, 768,
482 }, 471 },
@@ -505,8 +494,6 @@ static struct panel_settings known_lcd_panels[] =
505 .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ 494 .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
506 .mode_backlight = 0x00000000, 495 .mode_backlight = 0x00000000,
507 .mode_auxpll = 10, /* 120MHz AUXPLL */ 496 .mode_auxpll = 10, /* 120MHz AUXPLL */
508 .device_init = NULL,
509 .device_shutdown = NULL,
510 1280, 1280, 497 1280, 1280,
511 1024, 1024, 498 1024, 1024,
512 }, 499 },
@@ -535,8 +522,6 @@ static struct panel_settings known_lcd_panels[] =
535 .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ 522 .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
536 .mode_backlight = 0x00000000, 523 .mode_backlight = 0x00000000,
537 .mode_auxpll = 8, /* 96MHz AUXPLL */ 524 .mode_auxpll = 8, /* 96MHz AUXPLL */
538 .device_init = board_au1200fb_panel_init,
539 .device_shutdown = board_au1200fb_panel_shutdown,
540 1024, 1024, 525 1024, 1024,
541 768, 768, 526 768, 768,
542 }, 527 },
@@ -568,8 +553,6 @@ static struct panel_settings known_lcd_panels[] =
568 .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ 553 .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
569 .mode_backlight = 0x00000000, 554 .mode_backlight = 0x00000000,
570 .mode_auxpll = 8, /* 96MHz AUXPLL */ 555 .mode_auxpll = 8, /* 96MHz AUXPLL */
571 .device_init = board_au1200fb_panel_init,
572 .device_shutdown = board_au1200fb_panel_shutdown,
573 640, 480, 556 640, 480,
574 640, 480, 557 640, 480,
575 }, 558 },
@@ -601,8 +584,6 @@ static struct panel_settings known_lcd_panels[] =
601 .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ 584 .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
602 .mode_backlight = 0x00000000, 585 .mode_backlight = 0x00000000,
603 .mode_auxpll = 8, /* 96MHz AUXPLL */ 586 .mode_auxpll = 8, /* 96MHz AUXPLL */
604 .device_init = board_au1200fb_panel_init,
605 .device_shutdown = board_au1200fb_panel_shutdown,
606 320, 320, 587 320, 320,
607 240, 240, 588 240, 240,
608 }, 589 },
@@ -634,11 +615,43 @@ static struct panel_settings known_lcd_panels[] =
634 .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ 615 .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
635 .mode_backlight = 0x00000000, 616 .mode_backlight = 0x00000000,
636 .mode_auxpll = 8, /* 96MHz AUXPLL */ 617 .mode_auxpll = 8, /* 96MHz AUXPLL */
637 .device_init = board_au1200fb_panel_init,
638 .device_shutdown = board_au1200fb_panel_shutdown,
639 856, 856, 618 856, 856,
640 480, 480, 619 480, 480,
641 }, 620 },
621 [9] = {
622 .name = "DB1300_800x480",
623 .monspecs = {
624 .modedb = NULL,
625 .modedb_len = 0,
626 .hfmin = 30000,
627 .hfmax = 70000,
628 .vfmin = 60,
629 .vfmax = 60,
630 .dclkmin = 6000000,
631 .dclkmax = 28000000,
632 .input = FB_DISP_RGB,
633 },
634 .mode_screen = LCD_SCREEN_SX_N(800) |
635 LCD_SCREEN_SY_N(480),
636 .mode_horztiming = LCD_HORZTIMING_HPW_N(5) |
637 LCD_HORZTIMING_HND1_N(16) |
638 LCD_HORZTIMING_HND2_N(8),
639 .mode_verttiming = LCD_VERTTIMING_VPW_N(4) |
640 LCD_VERTTIMING_VND1_N(8) |
641 LCD_VERTTIMING_VND2_N(5),
642 .mode_clkcontrol = LCD_CLKCONTROL_PCD_N(1) |
643 LCD_CLKCONTROL_IV |
644 LCD_CLKCONTROL_IH,
645 .mode_pwmdiv = 0x00000000,
646 .mode_pwmhi = 0x00000000,
647 .mode_outmask = 0x00FFFFFF,
648 .mode_fifoctrl = 0x2f2f2f2f,
649 .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
650 .mode_backlight = 0x00000000,
651 .mode_auxpll = (48/12) * 2,
652 800, 800,
653 480, 480,
654 },
642}; 655};
643 656
644#define NUM_PANELS (ARRAY_SIZE(known_lcd_panels)) 657#define NUM_PANELS (ARRAY_SIZE(known_lcd_panels))
@@ -764,7 +777,8 @@ static int au1200_setlocation (struct au1200fb_device *fbdev, int plane,
764 return 0; 777 return 0;
765} 778}
766 779
767static void au1200_setpanel (struct panel_settings *newpanel) 780static void au1200_setpanel(struct panel_settings *newpanel,
781 struct au1200fb_platdata *pd)
768{ 782{
769 /* 783 /*
770 * Perform global setup/init of LCD controller 784 * Perform global setup/init of LCD controller
@@ -798,8 +812,8 @@ static void au1200_setpanel (struct panel_settings *newpanel)
798 the controller, the clock cannot be turned off before first 812 the controller, the clock cannot be turned off before first
799 shutting down the controller. 813 shutting down the controller.
800 */ 814 */
801 if (panel->device_shutdown != NULL) 815 if (pd->panel_shutdown)
802 panel->device_shutdown(); 816 pd->panel_shutdown();
803 } 817 }
804 818
805 /* Newpanel == NULL indicates a shutdown operation only */ 819 /* Newpanel == NULL indicates a shutdown operation only */
@@ -852,7 +866,8 @@ static void au1200_setpanel (struct panel_settings *newpanel)
852 au_sync(); 866 au_sync();
853 867
854 /* Call init of panel */ 868 /* Call init of panel */
855 if (panel->device_init != NULL) panel->device_init(); 869 if (pd->panel_init)
870 pd->panel_init();
856 871
857 /* FIX!!!! not appropriate on panel change!!! Global setup/init */ 872 /* FIX!!!! not appropriate on panel change!!! Global setup/init */
858 lcd->intenable = 0; 873 lcd->intenable = 0;
@@ -1185,6 +1200,8 @@ static int au1200fb_fb_setcolreg(unsigned regno, unsigned red, unsigned green,
1185 */ 1200 */
1186static int au1200fb_fb_blank(int blank_mode, struct fb_info *fbi) 1201static int au1200fb_fb_blank(int blank_mode, struct fb_info *fbi)
1187{ 1202{
1203 struct au1200fb_device *fbdev = fbi->par;
1204
1188 /* Short-circuit screen blanking */ 1205 /* Short-circuit screen blanking */
1189 if (noblanking) 1206 if (noblanking)
1190 return 0; 1207 return 0;
@@ -1194,13 +1211,13 @@ static int au1200fb_fb_blank(int blank_mode, struct fb_info *fbi)
1194 case FB_BLANK_UNBLANK: 1211 case FB_BLANK_UNBLANK:
1195 case FB_BLANK_NORMAL: 1212 case FB_BLANK_NORMAL:
1196 /* printk("turn on panel\n"); */ 1213 /* printk("turn on panel\n"); */
1197 au1200_setpanel(panel); 1214 au1200_setpanel(panel, fbdev->pd);
1198 break; 1215 break;
1199 case FB_BLANK_VSYNC_SUSPEND: 1216 case FB_BLANK_VSYNC_SUSPEND:
1200 case FB_BLANK_HSYNC_SUSPEND: 1217 case FB_BLANK_HSYNC_SUSPEND:
1201 case FB_BLANK_POWERDOWN: 1218 case FB_BLANK_POWERDOWN:
1202 /* printk("turn off panel\n"); */ 1219 /* printk("turn off panel\n"); */
1203 au1200_setpanel(NULL); 1220 au1200_setpanel(NULL, fbdev->pd);
1204 break; 1221 break;
1205 default: 1222 default:
1206 break; 1223 break;
@@ -1428,6 +1445,7 @@ static void get_window(unsigned int plane,
1428static int au1200fb_ioctl(struct fb_info *info, unsigned int cmd, 1445static int au1200fb_ioctl(struct fb_info *info, unsigned int cmd,
1429 unsigned long arg) 1446 unsigned long arg)
1430{ 1447{
1448 struct au1200fb_device *fbdev = info->par;
1431 int plane; 1449 int plane;
1432 int val; 1450 int val;
1433 1451
@@ -1472,7 +1490,7 @@ static int au1200fb_ioctl(struct fb_info *info, unsigned int cmd,
1472 struct panel_settings *newpanel; 1490 struct panel_settings *newpanel;
1473 panel_index = iodata.global.panel_choice; 1491 panel_index = iodata.global.panel_choice;
1474 newpanel = &known_lcd_panels[panel_index]; 1492 newpanel = &known_lcd_panels[panel_index];
1475 au1200_setpanel(newpanel); 1493 au1200_setpanel(newpanel, fbdev->pd);
1476 } 1494 }
1477 break; 1495 break;
1478 1496
@@ -1588,22 +1606,102 @@ static int au1200fb_init_fbinfo(struct au1200fb_device *fbdev)
1588 1606
1589/*-------------------------------------------------------------------------*/ 1607/*-------------------------------------------------------------------------*/
1590 1608
1591/* AU1200 LCD controller device driver */
1592 1609
1610static int au1200fb_setup(struct au1200fb_platdata *pd)
1611{
1612 char *options = NULL;
1613 char *this_opt, *endptr;
1614 int num_panels = ARRAY_SIZE(known_lcd_panels);
1615 int panel_idx = -1;
1616
1617 fb_get_options(DRIVER_NAME, &options);
1618
1619 if (!options)
1620 goto out;
1621
1622 while ((this_opt = strsep(&options, ",")) != NULL) {
1623 /* Panel option - can be panel name,
1624 * "bs" for board-switch, or number/index */
1625 if (!strncmp(this_opt, "panel:", 6)) {
1626 int i;
1627 long int li;
1628 char *endptr;
1629 this_opt += 6;
1630 /* First check for index, which allows
1631 * to short circuit this mess */
1632 li = simple_strtol(this_opt, &endptr, 0);
1633 if (*endptr == '\0')
1634 panel_idx = (int)li;
1635 else if (strcmp(this_opt, "bs") == 0)
1636 panel_idx = pd->panel_index();
1637 else {
1638 for (i = 0; i < num_panels; i++) {
1639 if (!strcmp(this_opt,
1640 known_lcd_panels[i].name)) {
1641 panel_idx = i;
1642 break;
1643 }
1644 }
1645 }
1646 if ((panel_idx < 0) || (panel_idx >= num_panels))
1647 print_warn("Panel %s not supported!", this_opt);
1648 else
1649 panel_index = panel_idx;
1650
1651 } else if (strncmp(this_opt, "nohwcursor", 10) == 0)
1652 nohwcursor = 1;
1653 else if (strncmp(this_opt, "devices:", 8) == 0) {
1654 this_opt += 8;
1655 device_count = simple_strtol(this_opt, &endptr, 0);
1656 if ((device_count < 0) ||
1657 (device_count > MAX_DEVICE_COUNT))
1658 device_count = MAX_DEVICE_COUNT;
1659 } else if (strncmp(this_opt, "wincfg:", 7) == 0) {
1660 this_opt += 7;
1661 window_index = simple_strtol(this_opt, &endptr, 0);
1662 if ((window_index < 0) ||
1663 (window_index >= ARRAY_SIZE(windows)))
1664 window_index = DEFAULT_WINDOW_INDEX;
1665 } else if (strncmp(this_opt, "off", 3) == 0)
1666 return 1;
1667 else
1668 print_warn("Unsupported option \"%s\"", this_opt);
1669 }
1670
1671out:
1672 return 0;
1673}
1674
1675/* AU1200 LCD controller device driver */
1593static int __devinit au1200fb_drv_probe(struct platform_device *dev) 1676static int __devinit au1200fb_drv_probe(struct platform_device *dev)
1594{ 1677{
1595 struct au1200fb_device *fbdev; 1678 struct au1200fb_device *fbdev;
1679 struct au1200fb_platdata *pd;
1596 struct fb_info *fbi = NULL; 1680 struct fb_info *fbi = NULL;
1597 unsigned long page; 1681 unsigned long page;
1598 int bpp, plane, ret, irq; 1682 int bpp, plane, ret, irq;
1599 1683
1684 print_info("" DRIVER_DESC "");
1685
1686 pd = dev->dev.platform_data;
1687 if (!pd)
1688 return -ENODEV;
1689
1690 /* Setup driver with options */
1691 if (au1200fb_setup(pd))
1692 return -ENODEV;
1693
1694 /* Point to the panel selected */
1695 panel = &known_lcd_panels[panel_index];
1696 win = &windows[window_index];
1697
1698 printk(DRIVER_NAME ": Panel %d %s\n", panel_index, panel->name);
1699 printk(DRIVER_NAME ": Win %d %s\n", window_index, win->name);
1700
1600 /* shut gcc up */ 1701 /* shut gcc up */
1601 ret = 0; 1702 ret = 0;
1602 fbdev = NULL; 1703 fbdev = NULL;
1603 1704
1604 /* Kickstart the panel */
1605 au1200_setpanel(panel);
1606
1607 for (plane = 0; plane < device_count; ++plane) { 1705 for (plane = 0; plane < device_count; ++plane) {
1608 bpp = winbpp(win->w[plane].mode_winctrl1); 1706 bpp = winbpp(win->w[plane].mode_winctrl1);
1609 if (win->w[plane].xres == 0) 1707 if (win->w[plane].xres == 0)
@@ -1619,6 +1717,7 @@ static int __devinit au1200fb_drv_probe(struct platform_device *dev)
1619 _au1200fb_infos[plane] = fbi; 1717 _au1200fb_infos[plane] = fbi;
1620 fbdev = fbi->par; 1718 fbdev = fbi->par;
1621 fbdev->fb_info = fbi; 1719 fbdev->fb_info = fbi;
1720 fbdev->pd = pd;
1622 1721
1623 fbdev->plane = plane; 1722 fbdev->plane = plane;
1624 1723
@@ -1680,6 +1779,11 @@ static int __devinit au1200fb_drv_probe(struct platform_device *dev)
1680 goto failed; 1779 goto failed;
1681 } 1780 }
1682 1781
1782 platform_set_drvdata(dev, pd);
1783
1784 /* Kickstart the panel */
1785 au1200_setpanel(panel, pd);
1786
1683 return 0; 1787 return 0;
1684 1788
1685failed: 1789failed:
@@ -1699,12 +1803,13 @@ failed:
1699 1803
1700static int __devexit au1200fb_drv_remove(struct platform_device *dev) 1804static int __devexit au1200fb_drv_remove(struct platform_device *dev)
1701{ 1805{
1806 struct au1200fb_platdata *pd = platform_get_drvdata(dev);
1702 struct au1200fb_device *fbdev; 1807 struct au1200fb_device *fbdev;
1703 struct fb_info *fbi; 1808 struct fb_info *fbi;
1704 int plane; 1809 int plane;
1705 1810
1706 /* Turn off the panel */ 1811 /* Turn off the panel */
1707 au1200_setpanel(NULL); 1812 au1200_setpanel(NULL, pd);
1708 1813
1709 for (plane = 0; plane < device_count; ++plane) { 1814 for (plane = 0; plane < device_count; ++plane) {
1710 fbi = _au1200fb_infos[plane]; 1815 fbi = _au1200fb_infos[plane];
@@ -1732,7 +1837,8 @@ static int __devexit au1200fb_drv_remove(struct platform_device *dev)
1732#ifdef CONFIG_PM 1837#ifdef CONFIG_PM
1733static int au1200fb_drv_suspend(struct device *dev) 1838static int au1200fb_drv_suspend(struct device *dev)
1734{ 1839{
1735 au1200_setpanel(NULL); 1840 struct au1200fb_platdata *pd = dev_get_drvdata(dev);
1841 au1200_setpanel(NULL, pd);
1736 1842
1737 lcd->outmask = 0; 1843 lcd->outmask = 0;
1738 au_sync(); 1844 au_sync();
@@ -1742,11 +1848,12 @@ static int au1200fb_drv_suspend(struct device *dev)
1742 1848
1743static int au1200fb_drv_resume(struct device *dev) 1849static int au1200fb_drv_resume(struct device *dev)
1744{ 1850{
1851 struct au1200fb_platdata *pd = dev_get_drvdata(dev);
1745 struct fb_info *fbi; 1852 struct fb_info *fbi;
1746 int i; 1853 int i;
1747 1854
1748 /* Kickstart the panel */ 1855 /* Kickstart the panel */
1749 au1200_setpanel(panel); 1856 au1200_setpanel(panel, pd);
1750 1857
1751 for (i = 0; i < device_count; i++) { 1858 for (i = 0; i < device_count; i++) {
1752 fbi = _au1200fb_infos[i]; 1859 fbi = _au1200fb_infos[i];
@@ -1781,100 +1888,8 @@ static struct platform_driver au1200fb_driver = {
1781 1888
1782/*-------------------------------------------------------------------------*/ 1889/*-------------------------------------------------------------------------*/
1783 1890
1784/* Kernel driver */
1785
1786static int au1200fb_setup(void)
1787{
1788 char *options = NULL;
1789 char *this_opt, *endptr;
1790 int num_panels = ARRAY_SIZE(known_lcd_panels);
1791 int panel_idx = -1;
1792
1793 fb_get_options(DRIVER_NAME, &options);
1794
1795 if (options) {
1796 while ((this_opt = strsep(&options,",")) != NULL) {
1797 /* Panel option - can be panel name,
1798 * "bs" for board-switch, or number/index */
1799 if (!strncmp(this_opt, "panel:", 6)) {
1800 int i;
1801 long int li;
1802 char *endptr;
1803 this_opt += 6;
1804 /* First check for index, which allows
1805 * to short circuit this mess */
1806 li = simple_strtol(this_opt, &endptr, 0);
1807 if (*endptr == '\0') {
1808 panel_idx = (int)li;
1809 }
1810 else if (strcmp(this_opt, "bs") == 0) {
1811 extern int board_au1200fb_panel(void);
1812 panel_idx = board_au1200fb_panel();
1813 }
1814
1815 else
1816 for (i = 0; i < num_panels; i++) {
1817 if (!strcmp(this_opt, known_lcd_panels[i].name)) {
1818 panel_idx = i;
1819 break;
1820 }
1821 }
1822
1823 if ((panel_idx < 0) || (panel_idx >= num_panels)) {
1824 print_warn("Panel %s not supported!", this_opt);
1825 }
1826 else
1827 panel_index = panel_idx;
1828 }
1829
1830 else if (strncmp(this_opt, "nohwcursor", 10) == 0) {
1831 nohwcursor = 1;
1832 }
1833
1834 else if (strncmp(this_opt, "devices:", 8) == 0) {
1835 this_opt += 8;
1836 device_count = simple_strtol(this_opt,
1837 &endptr, 0);
1838 if ((device_count < 0) ||
1839 (device_count > MAX_DEVICE_COUNT))
1840 device_count = MAX_DEVICE_COUNT;
1841 }
1842
1843 else if (strncmp(this_opt, "wincfg:", 7) == 0) {
1844 this_opt += 7;
1845 window_index = simple_strtol(this_opt,
1846 &endptr, 0);
1847 if ((window_index < 0) ||
1848 (window_index >= ARRAY_SIZE(windows)))
1849 window_index = DEFAULT_WINDOW_INDEX;
1850 }
1851
1852 else if (strncmp(this_opt, "off", 3) == 0)
1853 return 1;
1854 /* Unsupported option */
1855 else {
1856 print_warn("Unsupported option \"%s\"", this_opt);
1857 }
1858 }
1859 }
1860 return 0;
1861}
1862
1863static int __init au1200fb_init(void) 1891static int __init au1200fb_init(void)
1864{ 1892{
1865 print_info("" DRIVER_DESC "");
1866
1867 /* Setup driver with options */
1868 if (au1200fb_setup())
1869 return -ENODEV;
1870
1871 /* Point to the panel selected */
1872 panel = &known_lcd_panels[panel_index];
1873 win = &windows[window_index];
1874
1875 printk(DRIVER_NAME ": Panel %d %s\n", panel_index, panel->name);
1876 printk(DRIVER_NAME ": Win %d %s\n", window_index, win->name);
1877
1878 return platform_driver_register(&au1200fb_driver); 1893 return platform_driver_register(&au1200fb_driver);
1879} 1894}
1880 1895
diff --git a/drivers/video/console/newport_con.c b/drivers/video/console/newport_con.c
index 93317b5b8740..a122d9287d16 100644
--- a/drivers/video/console/newport_con.c
+++ b/drivers/video/console/newport_con.c
@@ -25,14 +25,13 @@
25#include <asm/system.h> 25#include <asm/system.h>
26#include <asm/page.h> 26#include <asm/page.h>
27#include <asm/pgtable.h> 27#include <asm/pgtable.h>
28#include <asm/gio_device.h>
29
28#include <video/newport.h> 30#include <video/newport.h>
29 31
30#include <linux/linux_logo.h> 32#include <linux/linux_logo.h>
31#include <linux/font.h> 33#include <linux/font.h>
32 34
33
34extern unsigned long sgi_gfxaddr;
35
36#define FONT_DATA ((unsigned char *)font_vga_8x16.data) 35#define FONT_DATA ((unsigned char *)font_vga_8x16.data)
37 36
38/* borrowed from fbcon.c */ 37/* borrowed from fbcon.c */
@@ -304,12 +303,6 @@ static const char *newport_startup(void)
304{ 303{
305 int i; 304 int i;
306 305
307 if (!sgi_gfxaddr)
308 return NULL;
309
310 if (!npregs)
311 npregs = (struct newport_regs *)/* ioremap cannot fail */
312 ioremap(sgi_gfxaddr, sizeof(struct newport_regs));
313 npregs->cset.config = NPORT_CFG_GD0; 306 npregs->cset.config = NPORT_CFG_GD0;
314 307
315 if (newport_wait(npregs)) 308 if (newport_wait(npregs))
@@ -743,26 +736,58 @@ const struct consw newport_con = {
743 .con_save_screen = DUMMY 736 .con_save_screen = DUMMY
744}; 737};
745 738
746#ifdef MODULE 739static int newport_probe(struct gio_device *dev,
747static int __init newport_console_init(void) 740 const struct gio_device_id *id)
748{ 741{
749 if (!sgi_gfxaddr) 742 unsigned long newport_addr;
750 return 0;
751 743
752 if (!npregs) 744 if (!dev->resource.start)
753 npregs = (struct newport_regs *)/* ioremap cannot fail */ 745 return -EINVAL;
754 ioremap(sgi_gfxaddr, sizeof(struct newport_regs)); 746
747 if (npregs)
748 return -EBUSY; /* we only support one Newport as console */
749
750 newport_addr = dev->resource.start + 0xF0000;
751 if (!request_mem_region(newport_addr, 0x10000, "Newport"))
752 return -ENODEV;
753
754 npregs = (struct newport_regs *)/* ioremap cannot fail */
755 ioremap(newport_addr, sizeof(struct newport_regs));
755 756
756 return take_over_console(&newport_con, 0, MAX_NR_CONSOLES - 1, 1); 757 return take_over_console(&newport_con, 0, MAX_NR_CONSOLES - 1, 1);
757} 758}
758module_init(newport_console_init);
759 759
760static void __exit newport_console_exit(void) 760static void newport_remove(struct gio_device *dev)
761{ 761{
762 give_up_console(&newport_con); 762 give_up_console(&newport_con);
763 iounmap((void *)npregs); 763 iounmap((void *)npregs);
764} 764}
765
766static struct gio_device_id newport_ids[] = {
767 { .id = 0x7e },
768 { .id = 0xff }
769};
770
771MODULE_ALIAS("gio:7e");
772
773static struct gio_driver newport_driver = {
774 .name = "newport",
775 .id_table = newport_ids,
776 .probe = newport_probe,
777 .remove = newport_remove,
778};
779
780int __init newport_console_init(void)
781{
782 return gio_register_driver(&newport_driver);
783}
784
785void __exit newport_console_exit(void)
786{
787 gio_unregister_driver(&newport_driver);
788}
789
790module_init(newport_console_init);
765module_exit(newport_console_exit); 791module_exit(newport_console_exit);
766#endif
767 792
768MODULE_LICENSE("GPL"); 793MODULE_LICENSE("GPL");
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
index eadf33d0abba..3c35fb2f688f 100644
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -207,6 +207,10 @@
207/* Xilinx PSS UART */ 207/* Xilinx PSS UART */
208#define PORT_XUARTPS 98 208#define PORT_XUARTPS 98
209 209
210/* Atheros AR933X SoC */
211#define PORT_AR933X 99
212
213
210#ifdef __KERNEL__ 214#ifdef __KERNEL__
211 215
212#include <linux/compiler.h> 216#include <linux/compiler.h>
diff --git a/sound/soc/au1x/Kconfig b/sound/soc/au1x/Kconfig
index e908a8123110..a56104040e83 100644
--- a/sound/soc/au1x/Kconfig
+++ b/sound/soc/au1x/Kconfig
@@ -1,13 +1,13 @@
1## 1##
2## Au1200/Au1550 PSC + DBDMA 2## Au1200/Au1550/Au1300 PSC + DBDMA
3## 3##
4config SND_SOC_AU1XPSC 4config SND_SOC_AU1XPSC
5 tristate "SoC Audio for Au1200/Au1250/Au1550" 5 tristate "SoC Audio for Au12xx/Au13xx/Au1550"
6 depends on MIPS_ALCHEMY 6 depends on MIPS_ALCHEMY
7 help 7 help
8 This option enables support for the Programmable Serial 8 This option enables support for the Programmable Serial
9 Controllers in AC97 and I2S mode, and the Descriptor-Based DMA 9 Controllers in AC97 and I2S mode, and the Descriptor-Based DMA
10 Controller (DBDMA) as found on the Au1200/Au1250/Au1550 SoC. 10 Controller (DBDMA) as found on the Au12xx/Au13xx/Au1550 SoC.
11 11
12config SND_SOC_AU1XPSC_I2S 12config SND_SOC_AU1XPSC_I2S
13 tristate 13 tristate
@@ -51,12 +51,14 @@ config SND_SOC_DB1000
51 of boards (DB1000/DB1500/DB1100). 51 of boards (DB1000/DB1500/DB1100).
52 52
53config SND_SOC_DB1200 53config SND_SOC_DB1200
54 tristate "DB1200 AC97+I2S audio support" 54 tristate "DB1200/DB1300/DB1550 Audio support"
55 depends on SND_SOC_AU1XPSC 55 depends on SND_SOC_AU1XPSC
56 select SND_SOC_AU1XPSC_AC97 56 select SND_SOC_AU1XPSC_AC97
57 select SND_SOC_AC97_CODEC 57 select SND_SOC_AC97_CODEC
58 select SND_SOC_WM9712
58 select SND_SOC_AU1XPSC_I2S 59 select SND_SOC_AU1XPSC_I2S
59 select SND_SOC_WM8731 60 select SND_SOC_WM8731
60 help 61 help
61 Select this option to enable audio (AC97 or I2S) on the 62 Select this option to enable audio (AC97 and I2S) on the
62 Alchemy/AMD/RMI DB1200 demoboard. 63 Alchemy/AMD/RMI/NetLogic Db1200, Db1550 and Db1300 evaluation boards.
64 If you need Db1300 touchscreen support, you definitely want to say Y.
diff --git a/sound/soc/au1x/db1200.c b/sound/soc/au1x/db1200.c
index 289312c14b99..44ad11827364 100644
--- a/sound/soc/au1x/db1200.c
+++ b/sound/soc/au1x/db1200.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * DB1200 ASoC audio fabric support code. 2 * DB1200/DB1300/DB1550 ASoC audio fabric support code.
3 * 3 *
4 * (c) 2008-2011 Manuel Lauss <manuel.lauss@googlemail.com> 4 * (c) 2008-2011 Manuel Lauss <manuel.lauss@googlemail.com>
5 * 5 *
@@ -28,6 +28,18 @@ static struct platform_device_id db1200_pids[] = {
28 }, { 28 }, {
29 .name = "db1200-i2s", 29 .name = "db1200-i2s",
30 .driver_data = 1, 30 .driver_data = 1,
31 }, {
32 .name = "db1300-ac97",
33 .driver_data = 2,
34 }, {
35 .name = "db1300-i2s",
36 .driver_data = 3,
37 }, {
38 .name = "db1550-ac97",
39 .driver_data = 4,
40 }, {
41 .name = "db1550-i2s",
42 .driver_data = 5,
31 }, 43 },
32 {}, 44 {},
33}; 45};
@@ -49,6 +61,27 @@ static struct snd_soc_card db1200_ac97_machine = {
49 .num_links = 1, 61 .num_links = 1,
50}; 62};
51 63
64static struct snd_soc_dai_link db1300_ac97_dai = {
65 .name = "AC97",
66 .stream_name = "AC97 HiFi",
67 .codec_dai_name = "wm9712-hifi",
68 .cpu_dai_name = "au1xpsc_ac97.1",
69 .platform_name = "au1xpsc-pcm.1",
70 .codec_name = "wm9712-codec.1",
71};
72
73static struct snd_soc_card db1300_ac97_machine = {
74 .name = "DB1300_AC97",
75 .dai_link = &db1300_ac97_dai,
76 .num_links = 1,
77};
78
79static struct snd_soc_card db1550_ac97_machine = {
80 .name = "DB1550_AC97",
81 .dai_link = &db1200_ac97_dai,
82 .num_links = 1,
83};
84
52/*------------------------- I2S PART ---------------------------*/ 85/*------------------------- I2S PART ---------------------------*/
53 86
54static int db1200_i2s_startup(struct snd_pcm_substream *substream) 87static int db1200_i2s_startup(struct snd_pcm_substream *substream)
@@ -98,11 +131,47 @@ static struct snd_soc_card db1200_i2s_machine = {
98 .num_links = 1, 131 .num_links = 1,
99}; 132};
100 133
134static struct snd_soc_dai_link db1300_i2s_dai = {
135 .name = "WM8731",
136 .stream_name = "WM8731 PCM",
137 .codec_dai_name = "wm8731-hifi",
138 .cpu_dai_name = "au1xpsc_i2s.2",
139 .platform_name = "au1xpsc-pcm.2",
140 .codec_name = "wm8731.0-001b",
141 .ops = &db1200_i2s_wm8731_ops,
142};
143
144static struct snd_soc_card db1300_i2s_machine = {
145 .name = "DB1300_I2S",
146 .dai_link = &db1300_i2s_dai,
147 .num_links = 1,
148};
149
150static struct snd_soc_dai_link db1550_i2s_dai = {
151 .name = "WM8731",
152 .stream_name = "WM8731 PCM",
153 .codec_dai_name = "wm8731-hifi",
154 .cpu_dai_name = "au1xpsc_i2s.3",
155 .platform_name = "au1xpsc-pcm.3",
156 .codec_name = "wm8731.0-001b",
157 .ops = &db1200_i2s_wm8731_ops,
158};
159
160static struct snd_soc_card db1550_i2s_machine = {
161 .name = "DB1550_I2S",
162 .dai_link = &db1550_i2s_dai,
163 .num_links = 1,
164};
165
101/*------------------------- COMMON PART ---------------------------*/ 166/*------------------------- COMMON PART ---------------------------*/
102 167
103static struct snd_soc_card *db1200_cards[] __devinitdata = { 168static struct snd_soc_card *db1200_cards[] __devinitdata = {
104 &db1200_ac97_machine, 169 &db1200_ac97_machine,
105 &db1200_i2s_machine, 170 &db1200_i2s_machine,
171 &db1300_ac97_machine,
172 &db1300_i2s_machine,
173 &db1550_ac97_machine,
174 &db1550_i2s_machine,
106}; 175};
107 176
108static int __devinit db1200_audio_probe(struct platform_device *pdev) 177static int __devinit db1200_audio_probe(struct platform_device *pdev)
@@ -147,5 +216,5 @@ module_init(db1200_audio_load);
147module_exit(db1200_audio_unload); 216module_exit(db1200_audio_unload);
148 217
149MODULE_LICENSE("GPL"); 218MODULE_LICENSE("GPL");
150MODULE_DESCRIPTION("DB1200 ASoC audio support"); 219MODULE_DESCRIPTION("DB1200/DB1300/DB1550 ASoC audio support");
151MODULE_AUTHOR("Manuel Lauss"); 220MODULE_AUTHOR("Manuel Lauss");