diff options
-rw-r--r-- | drivers/net/mv643xx_eth.c | 61 |
1 files changed, 24 insertions, 37 deletions
diff --git a/drivers/net/mv643xx_eth.c b/drivers/net/mv643xx_eth.c index 8a9ee8e46a1a..d5c9ceb2f685 100644 --- a/drivers/net/mv643xx_eth.c +++ b/drivers/net/mv643xx_eth.c | |||
@@ -106,7 +106,14 @@ static char mv643xx_driver_version[] = "1.0"; | |||
106 | #define TXQ_COMMAND(p) (0x0448 + ((p) << 10)) | 106 | #define TXQ_COMMAND(p) (0x0448 + ((p) << 10)) |
107 | #define TX_BW_MTU(p) (0x0458 + ((p) << 10)) | 107 | #define TX_BW_MTU(p) (0x0458 + ((p) << 10)) |
108 | #define INT_CAUSE(p) (0x0460 + ((p) << 10)) | 108 | #define INT_CAUSE(p) (0x0460 + ((p) << 10)) |
109 | #define INT_RX 0x00000804 | ||
110 | #define INT_EXT 0x00000002 | ||
109 | #define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10)) | 111 | #define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10)) |
112 | #define INT_EXT_LINK 0x00100000 | ||
113 | #define INT_EXT_PHY 0x00010000 | ||
114 | #define INT_EXT_TX_ERROR_0 0x00000100 | ||
115 | #define INT_EXT_TX_0 0x00000001 | ||
116 | #define INT_EXT_TX 0x00000101 | ||
110 | #define INT_MASK(p) (0x0468 + ((p) << 10)) | 117 | #define INT_MASK(p) (0x0468 + ((p) << 10)) |
111 | #define INT_MASK_EXT(p) (0x046c + ((p) << 10)) | 118 | #define INT_MASK_EXT(p) (0x046c + ((p) << 10)) |
112 | #define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10)) | 119 | #define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10)) |
@@ -162,26 +169,6 @@ static char mv643xx_driver_version[] = "1.0"; | |||
162 | #define PORT_DEFAULT_TRANSMIT_QUEUE_SIZE 800 | 169 | #define PORT_DEFAULT_TRANSMIT_QUEUE_SIZE 800 |
163 | #define PORT_DEFAULT_RECEIVE_QUEUE_SIZE 400 | 170 | #define PORT_DEFAULT_RECEIVE_QUEUE_SIZE 400 |
164 | 171 | ||
165 | #define ETH_RX_QUEUES_ENABLED (1 << 0) /* use only Q0 for receive */ | ||
166 | #define ETH_TX_QUEUES_ENABLED (1 << 0) /* use only Q0 for transmit */ | ||
167 | |||
168 | #define ETH_INT_CAUSE_RX_DONE (ETH_RX_QUEUES_ENABLED << 2) | ||
169 | #define ETH_INT_CAUSE_RX_ERROR (ETH_RX_QUEUES_ENABLED << 9) | ||
170 | #define ETH_INT_CAUSE_RX (ETH_INT_CAUSE_RX_DONE | ETH_INT_CAUSE_RX_ERROR) | ||
171 | #define ETH_INT_CAUSE_EXT 0x00000002 | ||
172 | #define ETH_INT_UNMASK_ALL (ETH_INT_CAUSE_RX | ETH_INT_CAUSE_EXT) | ||
173 | |||
174 | #define ETH_INT_CAUSE_TX_DONE (ETH_TX_QUEUES_ENABLED << 0) | ||
175 | #define ETH_INT_CAUSE_TX_ERROR (ETH_TX_QUEUES_ENABLED << 8) | ||
176 | #define ETH_INT_CAUSE_TX (ETH_INT_CAUSE_TX_DONE | ETH_INT_CAUSE_TX_ERROR) | ||
177 | #define ETH_INT_CAUSE_PHY 0x00010000 | ||
178 | #define ETH_INT_CAUSE_STATE 0x00100000 | ||
179 | #define ETH_INT_UNMASK_ALL_EXT (ETH_INT_CAUSE_TX | ETH_INT_CAUSE_PHY | \ | ||
180 | ETH_INT_CAUSE_STATE) | ||
181 | |||
182 | #define ETH_INT_MASK_ALL 0x00000000 | ||
183 | #define ETH_INT_MASK_ALL_EXT 0x00000000 | ||
184 | |||
185 | #define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */ | 172 | #define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */ |
186 | #define PHY_WAIT_MICRO_SECONDS 10 | 173 | #define PHY_WAIT_MICRO_SECONDS 10 |
187 | 174 | ||
@@ -841,7 +828,7 @@ static int mv643xx_poll(struct napi_struct *napi, int budget) | |||
841 | netif_rx_complete(dev, napi); | 828 | netif_rx_complete(dev, napi); |
842 | wrl(mp, INT_CAUSE(port_num), 0); | 829 | wrl(mp, INT_CAUSE(port_num), 0); |
843 | wrl(mp, INT_CAUSE_EXT(port_num), 0); | 830 | wrl(mp, INT_CAUSE_EXT(port_num), 0); |
844 | wrl(mp, INT_MASK(port_num), ETH_INT_UNMASK_ALL); | 831 | wrl(mp, INT_MASK(port_num), INT_RX | INT_EXT); |
845 | } | 832 | } |
846 | 833 | ||
847 | return work_done; | 834 | return work_done; |
@@ -997,7 +984,7 @@ static void eth_tx_submit_descs_for_skb(struct mv643xx_private *mp, | |||
997 | 984 | ||
998 | /* ensure all descriptors are written before poking hardware */ | 985 | /* ensure all descriptors are written before poking hardware */ |
999 | wmb(); | 986 | wmb(); |
1000 | mv643xx_eth_port_enable_tx(mp, ETH_TX_QUEUES_ENABLED); | 987 | mv643xx_eth_port_enable_tx(mp, 1); |
1001 | 988 | ||
1002 | mp->tx_desc_count += nr_frags + 1; | 989 | mp->tx_desc_count += nr_frags + 1; |
1003 | } | 990 | } |
@@ -1980,21 +1967,21 @@ static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id) | |||
1980 | unsigned int port_num = mp->port_num; | 1967 | unsigned int port_num = mp->port_num; |
1981 | 1968 | ||
1982 | /* Read interrupt cause registers */ | 1969 | /* Read interrupt cause registers */ |
1983 | eth_int_cause = rdl(mp, INT_CAUSE(port_num)) & ETH_INT_UNMASK_ALL; | 1970 | eth_int_cause = rdl(mp, INT_CAUSE(port_num)) & (INT_RX | INT_EXT); |
1984 | if (eth_int_cause & ETH_INT_CAUSE_EXT) { | 1971 | if (eth_int_cause & INT_EXT) { |
1985 | eth_int_cause_ext = rdl(mp, INT_CAUSE_EXT(port_num)) | 1972 | eth_int_cause_ext = rdl(mp, INT_CAUSE_EXT(port_num)) |
1986 | & ETH_INT_UNMASK_ALL_EXT; | 1973 | & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX); |
1987 | wrl(mp, INT_CAUSE_EXT(port_num), ~eth_int_cause_ext); | 1974 | wrl(mp, INT_CAUSE_EXT(port_num), ~eth_int_cause_ext); |
1988 | } | 1975 | } |
1989 | 1976 | ||
1990 | /* PHY status changed */ | 1977 | /* PHY status changed */ |
1991 | if (eth_int_cause_ext & (ETH_INT_CAUSE_PHY | ETH_INT_CAUSE_STATE)) { | 1978 | if (eth_int_cause_ext & (INT_EXT_LINK | INT_EXT_PHY)) { |
1992 | struct ethtool_cmd cmd; | 1979 | struct ethtool_cmd cmd; |
1993 | 1980 | ||
1994 | if (mii_link_ok(&mp->mii)) { | 1981 | if (mii_link_ok(&mp->mii)) { |
1995 | mii_ethtool_gset(&mp->mii, &cmd); | 1982 | mii_ethtool_gset(&mp->mii, &cmd); |
1996 | mv643xx_eth_update_pscr(dev, &cmd); | 1983 | mv643xx_eth_update_pscr(dev, &cmd); |
1997 | mv643xx_eth_port_enable_tx(mp, ETH_TX_QUEUES_ENABLED); | 1984 | mv643xx_eth_port_enable_tx(mp, 1); |
1998 | if (!netif_carrier_ok(dev)) { | 1985 | if (!netif_carrier_ok(dev)) { |
1999 | netif_carrier_on(dev); | 1986 | netif_carrier_on(dev); |
2000 | if (mp->tx_ring_size - mp->tx_desc_count >= | 1987 | if (mp->tx_ring_size - mp->tx_desc_count >= |
@@ -2008,9 +1995,9 @@ static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id) | |||
2008 | } | 1995 | } |
2009 | 1996 | ||
2010 | #ifdef MV643XX_NAPI | 1997 | #ifdef MV643XX_NAPI |
2011 | if (eth_int_cause & ETH_INT_CAUSE_RX) { | 1998 | if (eth_int_cause & INT_RX) { |
2012 | /* schedule the NAPI poll routine to maintain port */ | 1999 | /* schedule the NAPI poll routine to maintain port */ |
2013 | wrl(mp, INT_MASK(port_num), ETH_INT_MASK_ALL); | 2000 | wrl(mp, INT_MASK(port_num), 0x00000000); |
2014 | 2001 | ||
2015 | /* wait for previous write to complete */ | 2002 | /* wait for previous write to complete */ |
2016 | rdl(mp, INT_MASK(port_num)); | 2003 | rdl(mp, INT_MASK(port_num)); |
@@ -2018,10 +2005,10 @@ static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id) | |||
2018 | netif_rx_schedule(dev, &mp->napi); | 2005 | netif_rx_schedule(dev, &mp->napi); |
2019 | } | 2006 | } |
2020 | #else | 2007 | #else |
2021 | if (eth_int_cause & ETH_INT_CAUSE_RX) | 2008 | if (eth_int_cause & INT_RX) |
2022 | mv643xx_eth_receive_queue(dev, INT_MAX); | 2009 | mv643xx_eth_receive_queue(dev, INT_MAX); |
2023 | #endif | 2010 | #endif |
2024 | if (eth_int_cause_ext & ETH_INT_CAUSE_TX) | 2011 | if (eth_int_cause_ext & INT_EXT_TX) |
2025 | mv643xx_eth_free_completed_tx_descs(dev); | 2012 | mv643xx_eth_free_completed_tx_descs(dev); |
2026 | 2013 | ||
2027 | /* | 2014 | /* |
@@ -2145,7 +2132,7 @@ static void eth_port_start(struct net_device *dev) | |||
2145 | wrl(mp, SDMA_CONFIG(port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE); | 2132 | wrl(mp, SDMA_CONFIG(port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE); |
2146 | 2133 | ||
2147 | /* Enable port Rx. */ | 2134 | /* Enable port Rx. */ |
2148 | mv643xx_eth_port_enable_rx(mp, ETH_RX_QUEUES_ENABLED); | 2135 | mv643xx_eth_port_enable_rx(mp, 1); |
2149 | 2136 | ||
2150 | /* Disable port bandwidth limits by clearing MTU register */ | 2137 | /* Disable port bandwidth limits by clearing MTU register */ |
2151 | wrl(mp, TX_BW_MTU(port_num), 0); | 2138 | wrl(mp, TX_BW_MTU(port_num), 0); |
@@ -2392,10 +2379,10 @@ static int mv643xx_eth_open(struct net_device *dev) | |||
2392 | eth_port_set_tx_coal(mp, MV643XX_TX_COAL); | 2379 | eth_port_set_tx_coal(mp, MV643XX_TX_COAL); |
2393 | 2380 | ||
2394 | /* Unmask phy and link status changes interrupts */ | 2381 | /* Unmask phy and link status changes interrupts */ |
2395 | wrl(mp, INT_MASK_EXT(port_num), ETH_INT_UNMASK_ALL_EXT); | 2382 | wrl(mp, INT_MASK_EXT(port_num), INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX); |
2396 | 2383 | ||
2397 | /* Unmask RX buffer and TX end interrupt */ | 2384 | /* Unmask RX buffer and TX end interrupt */ |
2398 | wrl(mp, INT_MASK(port_num), ETH_INT_UNMASK_ALL); | 2385 | wrl(mp, INT_MASK(port_num), INT_RX | INT_EXT); |
2399 | 2386 | ||
2400 | return 0; | 2387 | return 0; |
2401 | 2388 | ||
@@ -2462,7 +2449,7 @@ static int mv643xx_eth_stop(struct net_device *dev) | |||
2462 | unsigned int port_num = mp->port_num; | 2449 | unsigned int port_num = mp->port_num; |
2463 | 2450 | ||
2464 | /* Mask all interrupts on ethernet port */ | 2451 | /* Mask all interrupts on ethernet port */ |
2465 | wrl(mp, INT_MASK(port_num), ETH_INT_MASK_ALL); | 2452 | wrl(mp, INT_MASK(port_num), 0x00000000); |
2466 | /* wait for previous write to complete */ | 2453 | /* wait for previous write to complete */ |
2467 | rdl(mp, INT_MASK(port_num)); | 2454 | rdl(mp, INT_MASK(port_num)); |
2468 | 2455 | ||
@@ -2567,13 +2554,13 @@ static void mv643xx_netpoll(struct net_device *netdev) | |||
2567 | struct mv643xx_private *mp = netdev_priv(netdev); | 2554 | struct mv643xx_private *mp = netdev_priv(netdev); |
2568 | int port_num = mp->port_num; | 2555 | int port_num = mp->port_num; |
2569 | 2556 | ||
2570 | wrl(mp, INT_MASK(port_num), ETH_INT_MASK_ALL); | 2557 | wrl(mp, INT_MASK(port_num), 0x00000000); |
2571 | /* wait for previous write to complete */ | 2558 | /* wait for previous write to complete */ |
2572 | rdl(mp, INT_MASK(port_num)); | 2559 | rdl(mp, INT_MASK(port_num)); |
2573 | 2560 | ||
2574 | mv643xx_eth_int_handler(netdev->irq, netdev); | 2561 | mv643xx_eth_int_handler(netdev->irq, netdev); |
2575 | 2562 | ||
2576 | wrl(mp, INT_MASK(port_num), ETH_INT_UNMASK_ALL); | 2563 | wrl(mp, INT_MASK(port_num), INT_RX | INT_CAUSE_EXT); |
2577 | } | 2564 | } |
2578 | #endif | 2565 | #endif |
2579 | 2566 | ||