572 files changed, 14955 insertions, 5510 deletions

diff --git a/Documentation/arm/sunxi/clocks.txt b/Documentation/arm/sunxi/clocks.txt
new file mode 100644
index 000000000000..e09a88aa3136
--- /dev/null
+++ b/Documentation/arm/sunxi/clocks.txt
@@ -0,0 +1,56 @@
+Frequently asked questions about the sunxi clock system
+=======================================================
+
+This document contains useful bits of information that people tend to ask
+about the sunxi clock system, as well as accompanying ASCII art when adequate.
+
+Q: Why is the main 24MHz oscillator gatable? Wouldn't that break the
+   system?
+
+A: The 24MHz oscillator allows gating to save power. Indeed, if gated
+   carelessly the system would stop functioning, but with the right
+   steps, one can gate it and keep the system running. Consider this
+   simplified suspend example:
+
+   While the system is operational, you would see something like
+
+      24MHz         32kHz
+       |
+      PLL1
+       \
+        \_ CPU Mux
+             |
+           [CPU]
+
+   When you are about to suspend, you switch the CPU Mux to the 32kHz
+   oscillator:
+
+      24Mhz         32kHz
+       |              |
+      PLL1            |
+                     /
+           CPU Mux _/
+             |
+           [CPU]
+
+    Finally you can gate the main oscillator
+
+                    32kHz
+                      |
+                      |
+                     /
+           CPU Mux _/
+             |
+           [CPU]
+
+Q: Were can I learn more about the sunxi clocks?
+
+A: The linux-sunxi wiki contains a page documenting the clock registers,
+   you can find it at
+
+        http://linux-sunxi.org/A10/CCM
+
+   The authoritative source for information at this time is the ccmu driver
+   released by Allwinner, you can find it at
+
+        https://github.com/linux-sunxi/linux-sunxi/tree/sunxi-3.0/arch/arm/mach-sun4i/clock/ccmu
diff --git a/Documentation/clk.txt b/Documentation/clk.txt
index 1943fae014fd..4274a546eb57 100644
--- a/Documentation/clk.txt
+++ b/Documentation/clk.txt
@@ -174,9 +174,9 @@ int clk_foo_enable(struct clk_hw *hw)
 };
 
 Below is a matrix detailing which clk_ops are mandatory based upon the
-hardware capbilities of that clock.  A cell marked as "y" means
+hardware capabilities of that clock.  A cell marked as "y" means
 mandatory, a cell marked as "n" implies that either including that
-callback is invalid or otherwise uneccesary.  Empty cells are either
+callback is invalid or otherwise unnecessary.  Empty cells are either
 optional or must be evaluated on a case-by-case basis.
 
                            clock hardware characteristics
diff --git a/Documentation/devicetree/bindings/arm/primecell.txt b/Documentation/devicetree/bindings/arm/primecell.txt
index 64fc82bc8928..0df6acacfaea 100644
--- a/Documentation/devicetree/bindings/arm/primecell.txt
+++ b/Documentation/devicetree/bindings/arm/primecell.txt
@@ -16,14 +16,31 @@ Optional properties:
 - clocks : From common clock binding. First clock is phandle to clock for apb
         pclk. Additional clocks are optional and specific to those peripherals.
 - clock-names : From common clock binding. Shall be "apb_pclk" for first clock.
+- dmas : From common DMA binding. If present, refers to one or more dma channels.
+- dma-names : From common DMA binding, needs to match the 'dmas' property.
+              Devices with exactly one receive and transmit channel shall name
+              these "rx" and "tx", respectively.
+- pinctrl-<n> : Pinctrl states as described in bindings/pinctrl/pinctrl-bindings.txt
+- pinctrl-names : Names corresponding to the numbered pinctrl states
+- interrupts : one or more interrupt specifiers
+- interrupt-names : names corresponding to the interrupts properties
 
 Example:
 
 serial@fff36000 {
         compatible = "arm,pl011", "arm,primecell";
         arm,primecell-periphid = <0x00341011>;
+
         clocks = <&pclk>;
         clock-names = "apb_pclk";
-        
+
+        dmas = <&dma-controller 4>, <&dma-controller 5>;
+        dma-names = "rx", "tx"; 
+
+        pinctrl-0 = <&uart0_default_mux>, <&uart0_default_mode>;
+        pinctrl-1 = <&uart0_sleep_mode>;
+        pinctrl-names = "default","sleep";
+
+        interrupts = <0 11 0x4>;
 };
 
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
index b5846e21cc2e..1608a54e90e1 100644
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
@@ -1,19 +1,84 @@
 NVIDIA Tegra Power Management Controller (PMC)
 
-Properties:
+The PMC block interacts with an external Power Management Unit. The PMC
+mostly controls the entry and exit of the system from different sleep
+modes. It provides power-gating controllers for SoC and CPU power-islands.
+
+Required properties:
 - name : Should be pmc
 - compatible : Should contain "nvidia,tegra<chip>-pmc".
 - reg : Offset and length of the register set for the device
+- clocks : Must contain an entry for each entry in clock-names.
+- clock-names : Must include the following entries:
+  "pclk" (The Tegra clock of that name),
+  "clk32k_in" (The 32KHz clock input to Tegra).
+
+Optional properties:
 - nvidia,invert-interrupt : If present, inverts the PMU interrupt signal.
   The PMU is an external Power Management Unit, whose interrupt output
   signal is fed into the PMC. This signal is optionally inverted, and then
   fed into the ARM GIC. The PMC is not involved in the detection or
   handling of this interrupt signal, merely its inversion.
+- nvidia,suspend-mode : The suspend mode that the platform should use.
+  Valid values are 0, 1 and 2:
+  0 (LP0): CPU + Core voltage off and DRAM in self-refresh
+  1 (LP1): CPU voltage off and DRAM in self-refresh
+  2 (LP2): CPU voltage off
+- nvidia,core-power-req-active-high : Boolean, core power request active-high
+- nvidia,sys-clock-req-active-high : Boolean, system clock request active-high
+- nvidia,combined-power-req : Boolean, combined power request for CPU & Core
+- nvidia,cpu-pwr-good-en : Boolean, CPU power good signal (from PMIC to PMC)
+                           is enabled.
+
+Required properties when nvidia,suspend-mode is specified:
+- nvidia,cpu-pwr-good-time : CPU power good time in uS.
+- nvidia,cpu-pwr-off-time : CPU power off time in uS.
+- nvidia,core-pwr-good-time : <Oscillator-stable-time Power-stable-time>
+                              Core power good time in uS.
+- nvidia,core-pwr-off-time : Core power off time in uS.
+
+Required properties when nvidia,suspend-mode=<0>:
+- nvidia,lp0-vec : <start length> Starting address and length of LP0 vector
+  The LP0 vector contains the warm boot code that is executed by AVP when
+  resuming from the LP0 state. The AVP (Audio-Video Processor) is an ARM7
+  processor and always being the first boot processor when chip is power on
+  or resume from deep sleep mode. When the system is resumed from the deep
+  sleep mode, the warm boot code will restore some PLLs, clocks and then
+  bring up CPU0 for resuming the system.
 
 Example:
 
+/ SoC dts including file
 pmc@7000f400 {
         compatible = "nvidia,tegra20-pmc";
         reg = <0x7000e400 0x400>;
+        clocks = <&tegra_car 110>, <&clk32k_in>;
+        clock-names = "pclk", "clk32k_in";
         nvidia,invert-interrupt;
+        nvidia,suspend-mode = <1>;
+        nvidia,cpu-pwr-good-time = <2000>;
+        nvidia,cpu-pwr-off-time = <100>;
+        nvidia,core-pwr-good-time = <3845 3845>;
+        nvidia,core-pwr-off-time = <458>;
+        nvidia,core-power-req-active-high;
+        nvidia,sys-clock-req-active-high;
+        nvidia,lp0-vec = <0xbdffd000 0x2000>;
+};
+
+/ Tegra board dts file
+{
+        ...
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+        ...
 };
diff --git a/Documentation/devicetree/bindings/ata/pata-arasan.txt b/Documentation/devicetree/bindings/ata/pata-arasan.txt
index 95ec7f825ede..2aff154be84e 100644
--- a/Documentation/devicetree/bindings/ata/pata-arasan.txt
+++ b/Documentation/devicetree/bindings/ata/pata-arasan.txt
@@ -6,6 +6,26 @@ Required properties:
 - interrupt-parent: Should be the phandle for the interrupt controller
   that services interrupts for this device
 - interrupt: Should contain the CF interrupt number
+- clock-frequency: Interface clock rate, in Hz, one of
+       25000000
+       33000000
+       40000000
+       50000000
+       66000000
+       75000000
+      100000000
+      125000000
+      150000000
+      166000000
+      200000000
+
+Optional properties:
+- arasan,broken-udma: if present, UDMA mode is unusable
+- arasan,broken-mwdma: if present, MWDMA mode is unusable
+- arasan,broken-pio: if present, PIO mode is unusable
+- dmas: one DMA channel, as described in bindings/dma/dma.txt
+  required unless both UDMA and MWDMA mode are broken
+- dma-names: the corresponding channel name, must be "data"
 
 Example:
 
@@ -14,4 +34,6 @@ Example:
                 reg = <0xfc000000 0x1000>;
                 interrupt-parent = <&vic1>;
                 interrupts = <12>;
+                dmas = <&dma-controller 23>;
+                dma-names = "data";
         };
diff --git a/Documentation/devicetree/bindings/bus/ti-gpmc.txt b/Documentation/devicetree/bindings/bus/ti-gpmc.txt
index 5ddb2e9efaaa..4b87ea1194e3 100644
--- a/Documentation/devicetree/bindings/bus/ti-gpmc.txt
+++ b/Documentation/devicetree/bindings/bus/ti-gpmc.txt
@@ -35,36 +35,83 @@ Required properties:
 
 Timing properties for child nodes. All are optional and default to 0.
 
- - gpmc,sync-clk:       Minimum clock period for synchronous mode, in picoseconds
-
- Chip-select signal timings corresponding to GPMC_CONFIG2:
- - gpmc,cs-on:          Assertion time
- - gpmc,cs-rd-off:      Read deassertion time
- - gpmc,cs-wr-off:      Write deassertion time
-
- ADV signal timings corresponding to GPMC_CONFIG3:
- - gpmc,adv-on:         Assertion time
- - gpmc,adv-rd-off:     Read deassertion time
- - gpmc,adv-wr-off:     Write deassertion time
-
- WE signals timings corresponding to GPMC_CONFIG4:
- - gpmc,we-on:          Assertion time
- - gpmc,we-off:         Deassertion time
-
- OE signals timings corresponding to GPMC_CONFIG4:
- - gpmc,oe-on:          Assertion time
- - gpmc,oe-off:         Deassertion time
-
- Access time and cycle time timings corresponding to GPMC_CONFIG5:
- - gpmc,page-burst-access: Multiple access word delay
- - gpmc,access:         Start-cycle to first data valid delay
- - gpmc,rd-cycle:       Total read cycle time
- - gpmc,wr-cycle:       Total write cycle time
+ - gpmc,sync-clk-ps:    Minimum clock period for synchronous mode, in picoseconds
+
+ Chip-select signal timings (in nanoseconds) corresponding to GPMC_CONFIG2:
+ - gpmc,cs-on-ns:       Assertion time
+ - gpmc,cs-rd-off-ns:   Read deassertion time
+ - gpmc,cs-wr-off-ns:   Write deassertion time
+
+ ADV signal timings (in nanoseconds) corresponding to GPMC_CONFIG3:
+ - gpmc,adv-on-ns:      Assertion time
+ - gpmc,adv-rd-off-ns:  Read deassertion time
+ - gpmc,adv-wr-off-ns:  Write deassertion time
+
+ WE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4:
+ - gpmc,we-on-ns        Assertion time
+ - gpmc,we-off-ns:      Deassertion time
+
+ OE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4:
+ - gpmc,oe-on-ns:       Assertion time
+ - gpmc,oe-off-ns:      Deassertion time
+
+ Access time and cycle time timings (in nanoseconds) corresponding to
+ GPMC_CONFIG5:
+ - gpmc,page-burst-access-ns:   Multiple access word delay
+ - gpmc,access-ns:              Start-cycle to first data valid delay
+ - gpmc,rd-cycle-ns:            Total read cycle time
+ - gpmc,wr-cycle-ns:            Total write cycle time
+ - gpmc,bus-turnaround-ns:      Turn-around time between successive accesses
+ - gpmc,cycle2cycle-delay-ns:   Delay between chip-select pulses
+ - gpmc,clk-activation-ns:      GPMC clock activation time
+ - gpmc,wait-monitoring-ns:     Start of wait monitoring with regard to valid
+                                data
+
+Boolean timing parameters. If property is present parameter enabled and
+disabled if omitted:
+ - gpmc,adv-extra-delay:        ADV signal is delayed by half GPMC clock
+ - gpmc,cs-extra-delay:         CS signal is delayed by half GPMC clock
+ - gpmc,cycle2cycle-diffcsen:   Add "cycle2cycle-delay" between successive
+                                accesses to a different CS
+ - gpmc,cycle2cycle-samecsen:   Add "cycle2cycle-delay" between successive
+                                accesses to the same CS
+ - gpmc,oe-extra-delay:         OE signal is delayed by half GPMC clock
+ - gpmc,we-extra-delay:         WE signal is delayed by half GPMC clock
+ - gpmc,time-para-granularity:  Multiply all access times by 2
 
 The following are only applicable to OMAP3+ and AM335x:
- - gpmc,wr-access
- - gpmc,wr-data-mux-bus
-
+ - gpmc,wr-access-ns:           In synchronous write mode, for single or
+                                burst accesses, defines the number of
+                                GPMC_FCLK cycles from start access time
+                                to the GPMC_CLK rising edge used by the
+                                memory device for the first data capture.
+ - gpmc,wr-data-mux-bus-ns:     In address-data multiplex mode, specifies
+                                the time when the first data is driven on
+                                the address-data bus.
+
+GPMC chip-select settings properties for child nodes. All are optional.
+
+- gpmc,burst-length     Page/burst length. Must be 4, 8 or 16.
+- gpmc,burst-wrap       Enables wrap bursting
+- gpmc,burst-read       Enables read page/burst mode
+- gpmc,burst-write      Enables write page/burst mode
+- gpmc,device-nand      Device is NAND
+- gpmc,device-width     Total width of device(s) connected to a GPMC
+                        chip-select in bytes. The GPMC supports 8-bit
+                        and 16-bit devices and so this property must be
+                        1 or 2.
+- gpmc,mux-add-data     Address and data multiplexing configuration.
+                        Valid values are 1 for address-address-data
+                        multiplexing mode and 2 for address-data
+                        multiplexing mode.
+- gpmc,sync-read        Enables synchronous read. Defaults to asynchronous
+                        is this is not set.
+- gpmc,sync-write       Enables synchronous writes. Defaults to asynchronous
+                        is this is not set.
+- gpmc,wait-pin         Wait-pin used by client. Must be less than
+                        "gpmc,num-waitpins".
+- gpmc,wait-on-read     Enables wait monitoring on reads.
+- gpmc,wait-on-write    Enables wait monitoring on writes.
 
 Example for an AM33xx board:
 
diff --git a/Documentation/devicetree/bindings/clock/axi-clkgen.txt b/Documentation/devicetree/bindings/clock/axi-clkgen.txt
new file mode 100644
index 000000000000..028b493e97ff
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/axi-clkgen.txt
@@ -0,0 +1,22 @@
+Binding for the axi-clkgen clock generator
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be "adi,axi-clkgen".
+- #clock-cells : from common clock binding; Should always be set to 0.
+- reg : Address and length of the axi-clkgen register set.
+- clocks : Phandle and clock specifier for the parent clock.
+
+Optional properties:
+- clock-output-names : From common clock binding.
+
+Example:
+        clock@0xff000000 {
+                compatible = "adi,axi-clkgen";
+                #clock-cells = <0>;
+                reg = <0xff000000 0x1000>;
+                clocks = <&osc 1>;
+        };
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
new file mode 100644
index 000000000000..d6cb083b90a2
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
@@ -0,0 +1,303 @@
+NVIDIA Tegra114 Clock And Reset Controller
+
+This binding uses the common clock binding:
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
+for muxing and gating Tegra's clocks, and setting their rates.
+
+Required properties :
+- compatible : Should be "nvidia,tegra114-car"
+- reg : Should contain CAR registers location and length
+- clocks : Should contain phandle and clock specifiers for two clocks:
+  the 32 KHz "32k_in", and the board-specific oscillator "osc".
+- #clock-cells : Should be 1.
+  In clock consumers, this cell represents the clock ID exposed by the CAR.
+
+  The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
+  registers. These IDs often match those in the CAR's RST_DEVICES registers,
+  but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
+  this case, those clocks are assigned IDs above 160 in order to highlight
+  this issue. Implementations that interpret these clock IDs as bit values
+  within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
+  explicitly handle these special cases.
+
+  The balance of the clocks controlled by the CAR are assigned IDs of 160 and
+  above.
+
+  0     unassigned
+  1     unassigned
+  2     unassigned
+  3     unassigned
+  4     rtc
+  5     timer
+  6     uarta
+  7     unassigned      (register bit affects uartb and vfir)
+  8     unassigned
+  9     sdmmc2
+  10    unassigned      (register bit affects spdif_in and spdif_out)
+  11    i2s1
+  12    i2c1
+  13    ndflash
+  14    sdmmc1
+  15    sdmmc4
+  16    unassigned
+  17    pwm
+  18    i2s2
+  19    epp
+  20    unassigned      (register bit affects vi and vi_sensor)
+  21    2d
+  22    usbd
+  23    isp
+  24    3d
+  25    unassigned
+  26    disp2
+  27    disp1
+  28    host1x
+  29    vcp
+  30    i2s0
+  31    unassigned
+
+  32    unassigned
+  33    unassigned
+  34    apbdma
+  35    unassigned
+  36    kbc
+  37    unassigned
+  38    unassigned
+  39    unassigned      (register bit affects fuse and fuse_burn)
+  40    kfuse
+  41    sbc1
+  42    nor
+  43    unassigned
+  44    sbc2
+  45    unassigned
+  46    sbc3
+  47    i2c5
+  48    dsia
+  49    unassigned
+  50    mipi
+  51    hdmi
+  52    csi
+  53    unassigned
+  54    i2c2
+  55    uartc
+  56    mipi-cal
+  57    emc
+  58    usb2
+  59    usb3
+  60    msenc
+  61    vde
+  62    bsea
+  63    bsev
+
+  64    unassigned
+  65    uartd
+  66    unassigned
+  67    i2c3
+  68    sbc4
+  69    sdmmc3
+  70    unassigned
+  71    owr
+  72    afi
+  73    csite
+  74    unassigned
+  75    unassigned
+  76    la
+  77    trace
+  78    soc_therm
+  79    dtv
+  80    ndspeed
+  81    i2cslow
+  82    dsib
+  83    tsec
+  84    unassigned
+  85    unassigned
+  86    unassigned
+  87    unassigned
+  88    unassigned
+  89    xusb_host
+  90    unassigned
+  91    msenc
+  92    csus
+  93    unassigned
+  94    unassigned
+  95    unassigned      (bit affects xusb_dev and xusb_dev_src)
+
+  96    unassigned
+  97    unassigned
+  98    unassigned
+  99    mselect
+  100   tsensor
+  101   i2s3
+  102   i2s4
+  103   i2c4
+  104   sbc5
+  105   sbc6
+  106   d_audio
+  107   apbif
+  108   dam0
+  109   dam1
+  110   dam2
+  111   hda2codec_2x
+  112   unassigned
+  113   audio0_2x
+  114   audio1_2x
+  115   audio2_2x
+  116   audio3_2x
+  117   audio4_2x
+  118   spdif_2x
+  119   actmon
+  120   extern1
+  121   extern2
+  122   extern3
+  123   unassigned
+  124   unassigned
+  125   hda
+  126   unassigned
+  127   se
+
+  128   hda2hdmi
+  129   unassigned
+  130   unassigned
+  131   unassigned
+  132   unassigned
+  133   unassigned
+  134   unassigned
+  135   unassigned
+  136   unassigned
+  137   unassigned
+  138   unassigned
+  139   unassigned
+  140   unassigned
+  141   unassigned
+  142   unassigned
+  143   unassigned      (bit affects xusb_falcon_src, xusb_fs_src,
+                         xusb_host_src and xusb_ss_src)
+  144   cilab
+  145   cilcd
+  146   cile
+  147   dsialp
+  148   dsiblp
+  149   unassigned
+  150   dds
+  151   unassigned
+  152   dp2
+  153   amx
+  154   adx
+  155   unassigned      (bit affects dfll_ref and dfll_soc)
+  156   xusb_ss
+
+  192   uartb
+  193   vfir
+  194   spdif_in
+  195   spdif_out
+  196   vi
+  197   vi_sensor
+  198   fuse
+  199   fuse_burn
+  200   clk_32k
+  201   clk_m
+  202   clk_m_div2
+  203   clk_m_div4
+  204   pll_ref
+  205   pll_c
+  206   pll_c_out1
+  207   pll_c2
+  208   pll_c3
+  209   pll_m
+  210   pll_m_out1
+  211   pll_p
+  212   pll_p_out1
+  213   pll_p_out2
+  214   pll_p_out3
+  215   pll_p_out4
+  216   pll_a
+  217   pll_a_out0
+  218   pll_d
+  219   pll_d_out0
+  220   pll_d2
+  221   pll_d2_out0
+  222   pll_u
+  223   pll_u_480M
+  224   pll_u_60M
+  225   pll_u_48M
+  226   pll_u_12M
+  227   pll_x
+  228   pll_x_out0
+  229   pll_re_vco
+  230   pll_re_out
+  231   pll_e_out0
+  232   spdif_in_sync
+  233   i2s0_sync
+  234   i2s1_sync
+  235   i2s2_sync
+  236   i2s3_sync
+  237   i2s4_sync
+  238   vimclk_sync
+  239   audio0
+  240   audio1
+  241   audio2
+  242   audio3
+  243   audio4
+  244   spdif
+  245   clk_out_1
+  246   clk_out_2
+  247   clk_out_3
+  248   blink
+  252   xusb_host_src
+  253   xusb_falcon_src
+  254   xusb_fs_src
+  255   xusb_ss_src
+  256   xusb_dev_src
+  257   xusb_dev
+  258   xusb_hs_src
+  259   sclk
+  260   hclk
+  261   pclk
+  262   cclk_g
+  263   cclk_lp
+  264   dfll_ref
+  265   dfll_soc
+
+Example SoC include file:
+
+/ {
+        tegra_car: clock {
+                compatible = "nvidia,tegra114-car";
+                reg = <0x60006000 0x1000>;
+                #clock-cells = <1>;
+        };
+
+        usb@c5004000 {
+                clocks = <&tegra_car 58>; /* usb2 */
+        };
+};
+
+Example board file:
+
+/ {
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                osc: clock@0 {
+                        compatible = "fixed-clock";
+                        reg = <0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <12000000>;
+                };
+
+                clk_32k: clock@1 {
+                        compatible = "fixed-clock";
+                        reg = <1>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+
+        &tegra_car {
+                clocks = <&clk_32k> <&osc>;
+        };
+};
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
index 0921fac73528..e885680f6b45 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
@@ -120,8 +120,8 @@ Required properties :
   90    clk_d
   91    unassigned
   92    sus
-  93    cdev1
-  94    cdev2
+  93    cdev2
+  94    cdev1
   95    unassigned
 
   96    uart2
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
new file mode 100644
index 000000000000..20b8479c2760
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -0,0 +1,44 @@
+Device Tree Clock bindings for arch-sunxi
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be one of the following:
+        "allwinner,sun4i-osc-clk" - for a gatable oscillator
+        "allwinner,sun4i-pll1-clk" - for the main PLL clock
+        "allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
+        "allwinner,sun4i-axi-clk" - for the AXI clock
+        "allwinner,sun4i-ahb-clk" - for the AHB clock
+        "allwinner,sun4i-apb0-clk" - for the APB0 clock
+        "allwinner,sun4i-apb1-clk" - for the APB1 clock
+        "allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing
+
+Required properties for all clocks:
+- reg : shall be the control register address for the clock.
+- clocks : shall be the input parent clock(s) phandle for the clock
+- #clock-cells : from common clock binding; shall be set to 0.
+
+For example:
+
+osc24M: osc24M@01c20050 {
+        #clock-cells = <0>;
+        compatible = "allwinner,sun4i-osc-clk";
+        reg = <0x01c20050 0x4>;
+        clocks = <&osc24M_fixed>;
+};
+
+pll1: pll1@01c20000 {
+        #clock-cells = <0>;
+        compatible = "allwinner,sun4i-pll1-clk";
+        reg = <0x01c20000 0x4>;
+        clocks = <&osc24M>;
+};
+
+cpu: cpu@01c20054 {
+        #clock-cells = <0>;
+        compatible = "allwinner,sun4i-cpu-clk";
+        reg = <0x01c20054 0x4>;
+        clocks = <&osc32k>, <&osc24M>, <&pll1>;
+};
diff --git a/Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq.txt b/Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq.txt
new file mode 100644
index 000000000000..c54c5a9a2a90
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq.txt
@@ -0,0 +1,53 @@
+Samsung S3C24XX Interrupt Controllers
+
+The S3C24XX SoCs contain a custom set of interrupt controllers providing a
+varying number of interrupt sources. The set consists of a main- and sub-
+controller and on newer SoCs even a second main controller.
+
+Required properties:
+- compatible: Compatible property value should be "samsung,s3c2410-irq"
+  for machines before s3c2416 and "samsung,s3c2416-irq" for s3c2416 and later.
+
+- reg: Physical base address of the controller and length of memory mapped
+  region.
+
+- interrupt-controller : Identifies the node as an interrupt controller
+
+- #interrupt-cells : Specifies the number of cells needed to encode an
+  interrupt source. The value shall be 4 and interrupt descriptor shall
+  have the following format:
+      <ctrl_num parent_irq ctrl_irq type>
+
+  ctrl_num contains the controller to use:
+      - 0 ... main controller
+      - 1 ... sub controller
+      - 2 ... second main controller on s3c2416 and s3c2450
+  parent_irq contains the parent bit in the main controller and will be
+             ignored in main controllers
+  ctrl_irq contains the interrupt bit of the controller
+  type contains the trigger type to use
+
+Example:
+
+        interrupt-controller@4a000000 {
+                compatible = "samsung,s3c2410-irq";
+                reg = <0x4a000000 0x100>;
+                interrupt-controller;
+                #interrupt-cells=<4>;
+        };
+
+        [...]
+
+        serial@50000000 {
+                compatible = "samsung,s3c2410-uart";
+                reg = <0x50000000 0x4000>;
+                interrupt-parent = <&subintc>;
+                interrupts = <1 28 0 4>, <1 28 1 4>;
+        };
+
+        rtc@57000000 {
+                compatible = "samsung,s3c2410-rtc";
+                reg = <0x57000000 0x100>;
+                interrupt-parent = <&intc>;
+                interrupts = <0 30 0 3>, <0 8 0 3>;
+        };
diff --git a/Documentation/devicetree/bindings/mtd/gpmc-nor.txt b/Documentation/devicetree/bindings/mtd/gpmc-nor.txt
new file mode 100644
index 000000000000..420b3ab18890
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/gpmc-nor.txt
@@ -0,0 +1,98 @@
+Device tree bindings for NOR flash connect to TI GPMC
+
+NOR flash connected to the TI GPMC (found on OMAP boards) are represented as
+child nodes of the GPMC controller with a name of "nor".
+
+All timing relevant properties as well as generic GPMC child properties are
+explained in a separate documents. Please refer to
+Documentation/devicetree/bindings/bus/ti-gpmc.txt
+
+Required properties:
+- bank-width:           Width of NOR flash in bytes. GPMC supports 8-bit and
+                        16-bit devices and so must be either 1 or 2 bytes.
+- compatible:           Documentation/devicetree/bindings/mtd/mtd-physmap.txt
+- gpmc,cs-on-ns:                Chip-select assertion time
+- gpmc,cs-rd-off-ns:    Chip-select de-assertion time for reads
+- gpmc,cs-wr-off-ns:    Chip-select de-assertion time for writes
+- gpmc,oe-on-ns:        Output-enable assertion time
+- gpmc,oe-off-ns:       Output-enable de-assertion time
+- gpmc,we-on-ns         Write-enable assertion time
+- gpmc,we-off-ns:       Write-enable de-assertion time
+- gpmc,access-ns:       Start cycle to first data capture (read access)
+- gpmc,rd-cycle-ns:     Total read cycle time
+- gpmc,wr-cycle-ns:     Total write cycle time
+- linux,mtd-name:       Documentation/devicetree/bindings/mtd/mtd-physmap.txt
+- reg:                  Chip-select, base address (relative to chip-select)
+                        and size of NOR flash. Note that base address will be
+                        typically 0 as this is the start of the chip-select.
+
+Optional properties:
+- gpmc,XXX              Additional GPMC timings and settings parameters. See
+                        Documentation/devicetree/bindings/bus/ti-gpmc.txt
+
+Optional properties for partiton table parsing:
+- #address-cells: should be set to 1
+- #size-cells: should be set to 1
+
+Example:
+
+gpmc: gpmc@6e000000 {
+        compatible = "ti,omap3430-gpmc", "simple-bus";
+        ti,hwmods = "gpmc";
+        reg = <0x6e000000 0x1000>;
+        interrupts = <20>;
+        gpmc,num-cs = <8>;
+        gpmc,num-waitpins = <4>;
+        #address-cells = <2>;
+        #size-cells = <1>;
+
+        ranges = <0 0 0x10000000 0x08000000>;
+
+        nor@0,0 {
+                compatible = "cfi-flash";
+                linux,mtd-name= "intel,pf48f6000m0y1be";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                reg = <0 0 0x08000000>;
+                bank-width = <2>;
+
+                gpmc,mux-add-data;
+                gpmc,cs-on-ns = <0>;
+                gpmc,cs-rd-off-ns = <186>;
+                gpmc,cs-wr-off-ns = <186>;
+                gpmc,adv-on-ns = <12>;
+                gpmc,adv-rd-off-ns = <48>;
+                gpmc,adv-wr-off-ns = <48>;
+                gpmc,oe-on-ns = <54>;
+                gpmc,oe-off-ns = <168>;
+                gpmc,we-on-ns = <54>;
+                gpmc,we-off-ns = <168>;
+                gpmc,rd-cycle-ns = <186>;
+                gpmc,wr-cycle-ns = <186>;
+                gpmc,access-ns = <114>;
+                gpmc,page-burst-access-ns = <6>;
+                gpmc,bus-turnaround-ns = <12>;
+                gpmc,cycle2cycle-delay-ns = <18>;
+                gpmc,wr-data-mux-bus-ns = <90>;
+                gpmc,wr-access-ns = <186>;
+                gpmc,cycle2cycle-samecsen;
+                gpmc,cycle2cycle-diffcsen;
+
+                partition@0 {
+                        label = "bootloader-nor";
+                        reg = <0 0x40000>;
+                };
+                partition@0x40000 {
+                        label = "params-nor";
+                        reg = <0x40000 0x40000>;
+                };
+                partition@0x80000 {
+                        label = "kernel-nor";
+                        reg = <0x80000 0x200000>;
+                };
+                partition@0x280000 {
+                        label = "filesystem-nor";
+                        reg = <0x240000 0x7d80000>;
+                };
+        };
+};
diff --git a/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt b/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
index deec9da224a2..b7529424ac88 100644
--- a/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
+++ b/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
@@ -10,6 +10,8 @@ Documentation/devicetree/bindings/bus/ti-gpmc.txt
 Required properties:
 
  - reg:                 The CS line the peripheral is connected to
+ - gpmc,device-width    Width of the ONENAND device connected to the GPMC
+                        in bytes. Must be 1 or 2.
 
 Optional properties:
 
@@ -34,6 +36,7 @@ Example for an OMAP3430 board:
 
                 onenand@0 {
                         reg = <0 0 0>; /* CS0, offset 0 */
+                        gpmc,device-width = <2>;
 
                         #address-cells = <1>;
                         #size-cells = <1>;
diff --git a/Documentation/devicetree/bindings/net/gpmc-eth.txt b/Documentation/devicetree/bindings/net/gpmc-eth.txt
new file mode 100644
index 000000000000..24cb4e46f675
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/gpmc-eth.txt
@@ -0,0 +1,97 @@
+Device tree bindings for Ethernet chip connected to TI GPMC
+
+Besides being used to interface with external memory devices, the
+General-Purpose Memory Controller can be used to connect Pseudo-SRAM devices
+such as ethernet controllers to processors using the TI GPMC as a data bus.
+
+Ethernet controllers connected to TI GPMC are represented as child nodes of
+the GPMC controller with an "ethernet" name.
+
+All timing relevant properties as well as generic GPMC child properties are
+explained in a separate documents. Please refer to
+Documentation/devicetree/bindings/bus/ti-gpmc.txt
+
+For the properties relevant to the ethernet controller connected to the GPMC
+refer to the binding documentation of the device. For example, the documentation
+for the SMSC 911x is Documentation/devicetree/bindings/net/smsc911x.txt
+
+Child nodes need to specify the GPMC bus address width using the "bank-width"
+property but is possible that an ethernet controller also has a property to
+specify the I/O registers address width. Even when the GPMC has a maximum 16-bit
+address width, it supports devices with 32-bit word registers.
+For example with an SMSC LAN911x/912x controller connected to the TI GPMC on an
+OMAP2+ board, "bank-width = <2>;" and "reg-io-width = <4>;".
+
+Required properties:
+- bank-width:           Address width of the device in bytes. GPMC supports 8-bit
+                        and 16-bit devices and so must be either 1 or 2 bytes.
+- compatible:           Compatible string property for the ethernet child device.
+- gpmc,cs-on:           Chip-select assertion time
+- gpmc,cs-rd-off:       Chip-select de-assertion time for reads
+- gpmc,cs-wr-off:       Chip-select de-assertion time for writes
+- gpmc,oe-on:           Output-enable assertion time
+- gpmc,oe-off           Output-enable de-assertion time
+- gpmc,we-on:           Write-enable assertion time
+- gpmc,we-off:          Write-enable de-assertion time
+- gpmc,access:          Start cycle to first data capture (read access)
+- gpmc,rd-cycle:        Total read cycle time
+- gpmc,wr-cycle:        Total write cycle time
+- reg:                  Chip-select, base address (relative to chip-select)
+                        and size of the memory mapped for the device.
+                        Note that base address will be typically 0 as this
+                        is the start of the chip-select.
+
+Optional properties:
+- gpmc,XXX              Additional GPMC timings and settings parameters. See
+                        Documentation/devicetree/bindings/bus/ti-gpmc.txt
+
+Example:
+
+gpmc: gpmc@6e000000 {
+        compatible = "ti,omap3430-gpmc";
+        ti,hwmods = "gpmc";
+        reg = <0x6e000000 0x1000>;
+        interrupts = <20>;
+        gpmc,num-cs = <8>;
+        gpmc,num-waitpins = <4>;
+        #address-cells = <2>;
+        #size-cells = <1>;
+
+        ranges = <5 0 0x2c000000 0x1000000>;
+
+        ethernet@5,0 {
+                compatible = "smsc,lan9221", "smsc,lan9115";
+                reg = <5 0 0xff>;
+                bank-width = <2>;
+
+                gpmc,mux-add-data;
+                gpmc,cs-on = <0>;
+                gpmc,cs-rd-off = <186>;
+                gpmc,cs-wr-off = <186>;
+                gpmc,adv-on = <12>;
+                gpmc,adv-rd-off = <48>;
+                gpmc,adv-wr-off = <48>;
+                gpmc,oe-on = <54>;
+                gpmc,oe-off = <168>;
+                gpmc,we-on = <54>;
+                gpmc,we-off = <168>;
+                gpmc,rd-cycle = <186>;
+                gpmc,wr-cycle = <186>;
+                gpmc,access = <114>;
+                gpmc,page-burst-access = <6>;
+                gpmc,bus-turnaround = <12>;
+                gpmc,cycle2cycle-delay = <18>;
+                gpmc,wr-data-mux-bus = <90>;
+                gpmc,wr-access = <186>;
+                gpmc,cycle2cycle-samecsen;
+                gpmc,cycle2cycle-diffcsen;
+
+                interrupt-parent = <&gpio6>;
+                interrupts = <16>;
+                vmmc-supply = <&vddvario>;
+                vmmc_aux-supply = <&vdd33a>;
+                reg-io-width = <4>;
+
+                smsc,save-mac-address;
+        };
+};
diff --git a/Documentation/devicetree/bindings/serial/pl011.txt b/Documentation/devicetree/bindings/serial/pl011.txt
new file mode 100644
index 000000000000..5d2e840ae65c
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/pl011.txt
@@ -0,0 +1,17 @@
+* ARM AMBA Primecell PL011 serial UART
+
+Required properties:
+- compatible: must be "arm,primecell", "arm,pl011"
+- reg: exactly one register range with length 0x1000
+- interrupts: exactly one interrupt specifier
+
+Optional properties:
+- pinctrl: When present, must have one state named "sleep"
+           and one state named "default"
+- clocks:  When present, must refer to exactly one clock named
+           "apb_pclk"
+- dmas:    When present, may have one or two dma channels.
+           The first one must be named "rx", the second one
+           must be named "tx".
+
+See also bindings/arm/primecell.txt
diff --git a/Documentation/devicetree/bindings/spi/spi_pl022.txt b/Documentation/devicetree/bindings/spi/spi_pl022.txt
index f158fd31cfda..22ed6797216d 100644
--- a/Documentation/devicetree/bindings/spi/spi_pl022.txt
+++ b/Documentation/devicetree/bindings/spi/spi_pl022.txt
@@ -16,6 +16,11 @@ Optional properties:
                             device will be suspended immediately
 - pl022,rt : indicates the controller should run the message pump with realtime
              priority to minimise the transfer latency on the bus (boolean)
+- dmas : Two or more DMA channel specifiers following the convention outlined
+         in bindings/dma/dma.txt
+- dma-names: Names for the dma channels, if present. There must be at
+             least one channel named "tx" for transmit and named "rx" for
+             receive.
 
 
 SPI slave nodes must be children of the SPI master node and can
@@ -32,3 +37,34 @@ contain the following properties.
 - pl022,wait-state : Microwire interface: Wait state
 - pl022,duplex : Microwire interface: Full/Half duplex
 
+
+Example:
+
+        spi@e0100000 {
+                compatible = "arm,pl022", "arm,primecell";
+                reg = <0xe0100000 0x1000>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                interrupts = <0 31 0x4>;
+                dmas = <&dma-controller 23 1>,
+                        <&dma-controller 24 0>;
+                dma-names = "rx", "tx";
+
+                m25p80@1 {
+                        compatible = "st,m25p80";
+                        reg = <1>;
+                        spi-max-frequency = <12000000>;
+                        spi-cpol;
+                        spi-cpha;
+                        pl022,hierarchy = <0>;
+                        pl022,interface = <0>;
+                        pl022,slave-tx-disable;
+                        pl022,com-mode = <0x2>;
+                        pl022,rx-level-trig = <0>;
+                        pl022,tx-level-trig = <0>;
+                        pl022,ctrl-len = <0x11>;
+                        pl022,wait-state = <0>;
+                        pl022,duplex = <0>;
+                };
+        };
+        
diff --git a/Documentation/devicetree/bindings/timer/arm,sp804.txt b/Documentation/devicetree/bindings/timer/arm,sp804.txt
new file mode 100644
index 000000000000..5cd8eee74af1
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/arm,sp804.txt
@@ -0,0 +1,29 @@
+ARM sp804 Dual Timers
+---------------------------------------
+
+Required properties:
+- compatible: Should be "arm,sp804" & "arm,primecell"
+- interrupts: Should contain the list of Dual Timer interrupts. This is the
+        interrupt for timer 1 and timer 2. In the case of a single entry, it is
+        the combined interrupt or if "arm,sp804-has-irq" is present that
+        specifies which timer interrupt is connected.
+- reg: Should contain location and length for dual timer register.
+- clocks: clocks driving the dual timer hardware. This list should be 1 or 3
+        clocks. With 3 clocks, the order is timer0 clock, timer1 clock,
+        apb_pclk. A single clock can also be specified if the same clock is
+        used for all clock inputs.
+
+Optional properties:
+- arm,sp804-has-irq = <#>: In the case of only 1 timer irq line connected, this
+        specifies if the irq connection is for timer 1 or timer 2. A value of 1
+        or 2 should be used.
+
+Example:
+
+        timer0: timer@fc800000 {
+                compatible = "arm,sp804", "arm,primecell";
+                reg = <0xfc800000 0x1000>;
+                interrupts = <0 0 4>, <0 1 4>;
+                clocks = <&timclk1 &timclk2 &pclk>;
+                clock-names = "timer1", "timer2", "apb_pclk";
+        };
diff --git a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
new file mode 100644
index 000000000000..cb47bfbcaeea
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
@@ -0,0 +1,68 @@
+Samsung's Multi Core Timer (MCT)
+
+The Samsung's Multi Core Timer (MCT) module includes two main blocks, the
+global timer and CPU local timers. The global timer is a 64-bit free running
+up-counter and can generate 4 interrupts when the counter reaches one of the
+four preset counter values. The CPU local timers are 32-bit free running
+down-counters and generate an interrupt when the counter expires. There is
+one CPU local timer instantiated in MCT for every CPU in the system.
+
+Required properties:
+
+- compatible: should be "samsung,exynos4210-mct".
+  (a) "samsung,exynos4210-mct", for mct compatible with Exynos4210 mct.
+  (b) "samsung,exynos4412-mct", for mct compatible with Exynos4412 mct.
+
+- reg: base address of the mct controller and length of the address space
+  it occupies.
+
+- interrupts: the list of interrupts generated by the controller. The following
+  should be the order of the interrupts specified. The local timer interrupts
+  should be specified after the four global timer interrupts have been
+  specified.
+
+        0: Global Timer Interrupt 0
+        1: Global Timer Interrupt 1
+        2: Global Timer Interrupt 2
+        3: Global Timer Interrupt 3
+        4: Local Timer Interrupt 0
+        5: Local Timer Interrupt 1
+        6: ..
+        7: ..
+        i: Local Timer Interrupt n
+
+Example 1: In this example, the system uses only the first global timer
+           interrupt generated by MCT and the remaining three global timer
+           interrupts are unused. Two local timer interrupts have been
+           specified.
+
+        mct@10050000 {
+                compatible = "samsung,exynos4210-mct";
+                reg = <0x10050000 0x800>;
+                interrupts = <0 57 0>, <0 0 0>, <0 0 0>, <0 0 0>,
+                             <0 42 0>, <0 48 0>;
+        };
+
+Example 2: In this example, the MCT global and local timer interrupts are
+           connected to two seperate interrupt controllers. Hence, an
+           interrupt-map is created to map the interrupts to the respective
+           interrupt controllers.
+
+        mct@101C0000 {
+                compatible = "samsung,exynos4210-mct";
+                reg = <0x101C0000 0x800>;
+                interrupt-controller;
+                #interrups-cells = <2>;
+                interrupt-parent = <&mct_map>;
+                interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
+                             <4 0>, <5 0>;
+
+                mct_map: mct-map {
+                        #interrupt-cells = <2>;
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        interrupt-map = <0x0 0 &combiner 23 3>,
+                                        <0x4 0 &gic 0 120 0>,
+                                        <0x5 0 &gic 0 121 0>;
+                };
+        };
diff --git a/Documentation/sound/alsa/ALSA-Configuration.txt b/Documentation/sound/alsa/ALSA-Configuration.txt
index 4499bd948860..95731a08f257 100644
--- a/Documentation/sound/alsa/ALSA-Configuration.txt
+++ b/Documentation/sound/alsa/ALSA-Configuration.txt
@@ -890,9 +890,8 @@ Prior to version 0.9.0rc4 options had a 'snd_' prefix. This was removed.
     enable_msi  - Enable Message Signaled Interrupt (MSI) (default = off)
     power_save  - Automatic power-saving timeout (in second, 0 =
                 disable)
-    power_save_controller - Support runtime D3 of HD-audio controller
-                (-1 = on for supported chip (default), false = off,
-                 true = force to on even for unsupported hardware)
+    power_save_controller - Reset HD-audio controller in power-saving mode
+                (default = on)
     align_buffer_size - Force rounding of buffer/period sizes to multiples
                       of 128 bytes. This is more efficient in terms of memory
                       access but isn't required by the HDA spec and prevents
diff --git a/MAINTAINERS b/MAINTAINERS
index 74e58a4d035b..836a6183c37f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5065,9 +5065,8 @@ S:	Maintained
 F:      drivers/net/ethernet/marvell/sk*
 
 MARVELL LIBERTAS WIRELESS DRIVER
-M:      Dan Williams <dcbw@redhat.com>
 L:      libertas-dev@lists.infradead.org
-S:      Maintained
+S:      Orphan
 F:      drivers/net/wireless/libertas/
 
 MARVELL MV643XX ETHERNET DRIVER
@@ -5569,6 +5568,7 @@ F:	include/uapi/linux/if_*
 F:      include/uapi/linux/netdevice.h
 
 NETXEN (1/10) GbE SUPPORT
+M:      Manish Chopra <manish.chopra@qlogic.com>
 M:      Sony Chacko <sony.chacko@qlogic.com>
 M:      Rajesh Borundia <rajesh.borundia@qlogic.com>
 L:      netdev@vger.kernel.org
diff --git a/Makefile b/Makefile
index 58a165b02af1..6db672b15bda 100644
--- a/Makefile
+++ b/Makefile
@@ -1,7 +1,7 @@
 VERSION = 3
 PATCHLEVEL = 9
 SUBLEVEL = 0
-EXTRAVERSION = -rc5
+EXTRAVERSION = -rc6
 NAME = Unicycling Gorilla
 
 # *DOCUMENTATION*
diff --git a/arch/alpha/Makefile b/arch/alpha/Makefile
index 4759fe751aa1..2cc3cc519c54 100644
--- a/arch/alpha/Makefile
+++ b/arch/alpha/Makefile
@@ -12,7 +12,7 @@ NM := $(NM) -B
 
 LDFLAGS_vmlinux := -static -N #-relax
 CHECKFLAGS      += -D__alpha__ -m64
-cflags-y        := -pipe -mno-fp-regs -ffixed-8 -msmall-data
+cflags-y        := -pipe -mno-fp-regs -ffixed-8
 cflags-y        += $(call cc-option, -fno-jump-tables)
 
 cpuflags-$(CONFIG_ALPHA_EV4)            := -mcpu=ev4
diff --git a/arch/alpha/include/asm/floppy.h b/arch/alpha/include/asm/floppy.h
index 46cefbd50e73..bae97eb19d26 100644
--- a/arch/alpha/include/asm/floppy.h
+++ b/arch/alpha/include/asm/floppy.h
@@ -26,7 +26,7 @@
 #define fd_disable_irq()        disable_irq(FLOPPY_IRQ)
 #define fd_cacheflush(addr,size) /* nothing */
 #define fd_request_irq()        request_irq(FLOPPY_IRQ, floppy_interrupt,\
-                                            IRQF_DISABLED, "floppy", NULL)
+                                            0, "floppy", NULL)
 #define fd_free_irq()           free_irq(FLOPPY_IRQ, NULL)
 
 #ifdef CONFIG_PCI
diff --git a/arch/alpha/kernel/irq.c b/arch/alpha/kernel/irq.c
index 2872accd2215..7b2be251c30f 100644
--- a/arch/alpha/kernel/irq.c
+++ b/arch/alpha/kernel/irq.c
@@ -117,13 +117,6 @@ handle_irq(int irq)
                 return;
         }
 
-        /*
-         * From here we must proceed with IPL_MAX. Note that we do not
-         * explicitly enable interrupts afterwards - some MILO PALcode
-         * (namely LX164 one) seems to have severe problems with RTI
-         * at IPL 0.
-         */
-        local_irq_disable();
         irq_enter();
         generic_handle_irq_desc(irq, desc);
         irq_exit();
diff --git a/arch/alpha/kernel/irq_alpha.c b/arch/alpha/kernel/irq_alpha.c
index 772ddfdb71a8..f433fc11877a 100644
--- a/arch/alpha/kernel/irq_alpha.c
+++ b/arch/alpha/kernel/irq_alpha.c
@@ -45,6 +45,14 @@ do_entInt(unsigned long type, unsigned long vector,
           unsigned long la_ptr, struct pt_regs *regs)
 {
         struct pt_regs *old_regs;
+
+        /*
+         * Disable interrupts during IRQ handling.
+         * Note that there is no matching local_irq_enable() due to
+         * severe problems with RTI at IPL0 and some MILO PALcode
+         * (namely LX164).
+         */
+        local_irq_disable();
         switch (type) {
         case 0:
 #ifdef CONFIG_SMP
@@ -62,7 +70,6 @@ do_entInt(unsigned long type, unsigned long vector,
           {
                 long cpu;
 
-                local_irq_disable();
                 smp_percpu_timer_interrupt(regs);
                 cpu = smp_processor_id();
                 if (cpu != boot_cpuid) {
@@ -222,7 +229,6 @@ process_mcheck_info(unsigned long vector, unsigned long la_ptr,
 
 struct irqaction timer_irqaction = {
         .handler        = timer_interrupt,
-        .flags          = IRQF_DISABLED,
         .name           = "timer",
 };
 
diff --git a/arch/alpha/kernel/sys_nautilus.c b/arch/alpha/kernel/sys_nautilus.c
index 4d4c046f708d..1383f8601a93 100644
--- a/arch/alpha/kernel/sys_nautilus.c
+++ b/arch/alpha/kernel/sys_nautilus.c
@@ -188,6 +188,10 @@ nautilus_machine_check(unsigned long vector, unsigned long la_ptr)
 extern void free_reserved_mem(void *, void *);
 extern void pcibios_claim_one_bus(struct pci_bus *);
 
+static struct resource irongate_io = {
+        .name   = "Irongate PCI IO",
+        .flags  = IORESOURCE_IO,
+};
 static struct resource irongate_mem = {
         .name   = "Irongate PCI MEM",
         .flags  = IORESOURCE_MEM,
@@ -209,6 +213,7 @@ nautilus_init_pci(void)
 
         irongate = pci_get_bus_and_slot(0, 0);
         bus->self = irongate;
+        bus->resource[0] = &irongate_io;
         bus->resource[1] = &irongate_mem;
 
         pci_bus_size_bridges(bus);
diff --git a/arch/alpha/kernel/sys_titan.c b/arch/alpha/kernel/sys_titan.c
index 5cf4a481b8c5..a53cf03f49d5 100644
--- a/arch/alpha/kernel/sys_titan.c
+++ b/arch/alpha/kernel/sys_titan.c
@@ -280,15 +280,15 @@ titan_late_init(void)
          * all reported to the kernel as machine checks, so the handler
          * is a nop so it can be called to count the individual events.
          */
-        titan_request_irq(63+16, titan_intr_nop, IRQF_DISABLED,
+        titan_request_irq(63+16, titan_intr_nop, 0,
                     "CChip Error", NULL);
-        titan_request_irq(62+16, titan_intr_nop, IRQF_DISABLED,
+        titan_request_irq(62+16, titan_intr_nop, 0,
                     "PChip 0 H_Error", NULL);
-        titan_request_irq(61+16, titan_intr_nop, IRQF_DISABLED,
+        titan_request_irq(61+16, titan_intr_nop, 0,
                     "PChip 1 H_Error", NULL);
-        titan_request_irq(60+16, titan_intr_nop, IRQF_DISABLED,
+        titan_request_irq(60+16, titan_intr_nop, 0,
                     "PChip 0 C_Error", NULL);
-        titan_request_irq(59+16, titan_intr_nop, IRQF_DISABLED,
+        titan_request_irq(59+16, titan_intr_nop, 0,
                     "PChip 1 C_Error", NULL);
 
         /* 
@@ -348,9 +348,9 @@ privateer_init_pci(void)
          * Hook a couple of extra err interrupts that the
          * common titan code won't.
          */
-        titan_request_irq(53+16, titan_intr_nop, IRQF_DISABLED,
+        titan_request_irq(53+16, titan_intr_nop, 0,
                     "NMI", NULL);
-        titan_request_irq(50+16, titan_intr_nop, IRQF_DISABLED,
+        titan_request_irq(50+16, titan_intr_nop, 0,
                     "Temperature Warning", NULL);
 
         /*
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index eb91022b90ba..38b5d5dad8e4 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -673,6 +673,7 @@ config ARCH_TEGRA
         select HAVE_CLK
         select HAVE_SMP
         select MIGHT_HAVE_CACHE_L2X0
+        select SOC_BUS
         select SPARSE_IRQ
         select USE_OF
         help
@@ -777,6 +778,7 @@ config ARCH_S3C24XX
         select HAVE_S3C2410_I2C if I2C
         select HAVE_S3C2410_WATCHDOG if WATCHDOG
         select HAVE_S3C_RTC if RTC_CLASS
+        select MULTI_IRQ_HANDLER
         select NEED_MACH_GPIO_H
         select NEED_MACH_IO_H
         help
@@ -938,16 +940,8 @@ config ARCH_NOMADIK
         help
           Support for the Nomadik platform by ST-Ericsson
 
-config PLAT_SPEAR
+config PLAT_SPEAR_SINGLE
         bool "ST SPEAr"
-        select ARCH_HAS_CPUFREQ
-        select ARCH_REQUIRE_GPIOLIB
-        select ARM_AMBA
-        select CLKDEV_LOOKUP
-        select CLKSRC_MMIO
-        select COMMON_CLK
-        select GENERIC_CLOCKEVENTS
-        select HAVE_CLK
         help
           Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
 
@@ -1109,7 +1103,7 @@ source "arch/arm/plat-samsung/Kconfig"
 
 source "arch/arm/mach-socfpga/Kconfig"
 
-source "arch/arm/plat-spear/Kconfig"
+source "arch/arm/mach-spear/Kconfig"
 
 source "arch/arm/mach-s3c24xx/Kconfig"
 
@@ -1178,6 +1172,7 @@ config PLAT_VERSATILE
 config ARM_TIMER_SP804
         bool
         select CLKSRC_MMIO
+        select CLKSRC_OF if OF
         select HAVE_SCHED_CLOCK
 
 source arch/arm/mm/Kconfig
@@ -1188,9 +1183,9 @@ config ARM_NR_BANKS
         default 8
 
 config IWMMXT
-        bool "Enable iWMMXt support"
+        bool "Enable iWMMXt support" if !CPU_PJ4
         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
-        default y if PXA27x || PXA3xx || ARCH_MMP
+        default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
         help
           Enable support for iWMMXt context switching at run time if
           running on a CPU that supports it.
@@ -1444,6 +1439,16 @@ config ARM_ERRATA_775420
          to deadlock. This workaround puts DSB before executing ISB if
          an abort may occur on cache maintenance.
 
+config ARM_ERRATA_798181
+        bool "ARM errata: TLBI/DSB failure on Cortex-A15"
+        depends on CPU_V7 && SMP
+        help
+          On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
+          adequately shooting down all use of the old entries. This
+          option enables the Linux kernel workaround for this erratum
+          which sends an IPI to the CPUs that are running the same ASID
+          as the one being invalidated.
+
 endmenu
 
 source "arch/arm/common/Kconfig"
@@ -1652,7 +1657,7 @@ config LOCAL_TIMERS
         bool "Use local timer interrupts"
         depends on SMP
         default y
-        select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
+        select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !CLKSRC_EXYNOS_MCT)
         help
           Enable support for local timers on SMP platforms, rather then the
           legacy IPI broadcast method.  Local timers allows the system
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index ee4605f400b0..8276536815a8 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -191,9 +191,7 @@ machine-$(CONFIG_ARCH_VT8500)		+= vt8500
 machine-$(CONFIG_ARCH_W90X900)          += w90x900
 machine-$(CONFIG_FOOTBRIDGE)            += footbridge
 machine-$(CONFIG_ARCH_SOCFPGA)          += socfpga
-machine-$(CONFIG_ARCH_SPEAR13XX)        += spear13xx
-machine-$(CONFIG_ARCH_SPEAR3XX)         += spear3xx
-machine-$(CONFIG_MACH_SPEAR600)         += spear6xx
+machine-$(CONFIG_PLAT_SPEAR)            += spear
 machine-$(CONFIG_ARCH_VIRT)             += virt
 machine-$(CONFIG_ARCH_ZYNQ)             += zynq
 machine-$(CONFIG_ARCH_SUNXI)            += sunxi
@@ -207,7 +205,6 @@ plat-$(CONFIG_PLAT_ORION)	+= orion
 plat-$(CONFIG_PLAT_PXA)         += pxa
 plat-$(CONFIG_PLAT_S3C24XX)     += samsung
 plat-$(CONFIG_PLAT_S5P)         += samsung
-plat-$(CONFIG_PLAT_SPEAR)       += spear
 plat-$(CONFIG_PLAT_VERSATILE)   += versatile
 
 ifeq ($(CONFIG_ARCH_EBSA110),y)
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 9c6255884cbb..e35b0a7ac77b 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -31,6 +31,11 @@ dtb-$(CONFIG_ARCH_AT91) += at91sam9g25ek.dtb
 dtb-$(CONFIG_ARCH_AT91) += at91sam9g35ek.dtb
 dtb-$(CONFIG_ARCH_AT91) += at91sam9x25ek.dtb
 dtb-$(CONFIG_ARCH_AT91) += at91sam9x35ek.dtb
+# sama5d3
+dtb-$(CONFIG_ARCH_AT91) += sama5d31ek.dtb
+dtb-$(CONFIG_ARCH_AT91) += sama5d33ek.dtb
+dtb-$(CONFIG_ARCH_AT91) += sama5d34ek.dtb
+dtb-$(CONFIG_ARCH_AT91) += sama5d35ek.dtb
 
 dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
 dtb-$(CONFIG_ARCH_BCM) += bcm11351-brt.dtb
@@ -165,6 +170,8 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
         tegra30-cardhu-a04.dtb \
         tegra114-dalmore.dtb \
         tegra114-pluto.dtb
+dtb-$(CONFIG_ARCH_VERSATILE) += versatile-ab.dtb \
+        versatile-pb.dtb
 dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \
         vexpress-v2p-ca9.dtb \
         vexpress-v2p-ca15-tc1.dtb \
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index dd0c57dd9f30..3234875824dc 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -54,7 +54,7 @@
                 };
 
                 mvsdio@d00d4000 {
-                        pinctrl-0 = <&sdio_pins2>;
+                        pinctrl-0 = <&sdio_pins3>;
                         pinctrl-names = "default";
                         status = "okay";
                         /*
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 8188d138020e..a195debb67d3 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -59,6 +59,12 @@
                                              "mpp50", "mpp51", "mpp52";
                               marvell,function = "sd0";
                         };
+
+                        sdio_pins3: sdio-pins3 {
+                              marvell,pins = "mpp48", "mpp49", "mpp50",
+                                             "mpp51", "mpp52", "mpp53";
+                              marvell,function = "sd0";
+                        };
                 };
 
                 gpio0: gpio@d0018100 {
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 6b1d4cab24c2..2b6e30cbc48b 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -108,6 +108,7 @@
                                 compatible = "atmel,at91sam9g45-dma";
                                 reg = <0xffffec00 0x200>;
                                 interrupts = <21 4 0>;
+                                #dma-cells = <2>;
                         };
 
                         pinctrl@fffff200 {
@@ -512,6 +513,8 @@
                                 compatible = "atmel,hsmci";
                                 reg = <0xfff80000 0x600>;
                                 interrupts = <11 4 0>;
+                                dmas = <&dma 1 0>;
+                                dma-names = "rxtx";
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 status = "disabled";
@@ -521,6 +524,8 @@
                                 compatible = "atmel,hsmci";
                                 reg = <0xfffd0000 0x600>;
                                 interrupts = <29 4 0>;
+                                dmas = <&dma 1 13>;
+                                dma-names = "rxtx";
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 status = "disabled";
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 7750f98dd764..b0bd70485f87 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -89,6 +89,8 @@
                                 compatible = "atmel,hsmci";
                                 reg = <0xf0008000 0x600>;
                                 interrupts = <12 4 0>;
+                                dmas = <&dma 1 0>;
+                                dma-names = "rxtx";
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 status = "disabled";
@@ -110,6 +112,7 @@
                                 compatible = "atmel,at91sam9g45-dma";
                                 reg = <0xffffec00 0x200>;
                                 interrupts = <20 4 0>;
+                                #dma-cells = <2>;
                         };
 
                         pinctrl@fffff400 {
@@ -360,6 +363,9 @@
                                 compatible = "atmel,at91sam9x5-i2c";
                                 reg = <0xf8010000 0x100>;
                                 interrupts = <9 4 6>;
+                                dmas = <&dma 1 13>,
+                                       <&dma 1 14>;
+                                dma-names = "tx", "rx";
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 status = "disabled";
@@ -369,6 +375,9 @@
                                 compatible = "atmel,at91sam9x5-i2c";
                                 reg = <0xf8014000 0x100>;
                                 interrupts = <10 4 6>;
+                                dmas = <&dma 1 15>,
+                                       <&dma 1 16>;
+                                dma-names = "tx", "rx";
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 status = "disabled";
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index a98c0d50fbbe..cbb94732786c 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -104,12 +104,14 @@
                                 compatible = "atmel,at91sam9g45-dma";
                                 reg = <0xffffec00 0x200>;
                                 interrupts = <20 4 0>;
+                                #dma-cells = <2>;
                         };
 
                         dma1: dma-controller@ffffee00 {
                                 compatible = "atmel,at91sam9g45-dma";
                                 reg = <0xffffee00 0x200>;
                                 interrupts = <21 4 0>;
+                                #dma-cells = <2>;
                         };
 
                         pinctrl@fffff400 {
@@ -399,6 +401,8 @@
                                 compatible = "atmel,hsmci";
                                 reg = <0xf0008000 0x600>;
                                 interrupts = <12 4 0>;
+                                dmas = <&dma0 1 0>;
+                                dma-names = "rxtx";
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 status = "disabled";
@@ -408,6 +412,8 @@
                                 compatible = "atmel,hsmci";
                                 reg = <0xf000c000 0x600>;
                                 interrupts = <26 4 0>;
+                                dmas = <&dma1 1 0>;
+                                dma-names = "rxtx";
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 status = "disabled";
@@ -469,6 +475,9 @@
                                 compatible = "atmel,at91sam9x5-i2c";
                                 reg = <0xf8010000 0x100>;
                                 interrupts = <9 4 6>;
+                                dmas = <&dma0 1 7>,
+                                       <&dma0 1 8>;
+                                dma-names = "tx", "rx";
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 status = "disabled";
@@ -478,6 +487,9 @@
                                 compatible = "atmel,at91sam9x5-i2c";
                                 reg = <0xf8014000 0x100>;
                                 interrupts = <10 4 6>;
+                                dmas = <&dma1 1 5>,
+                                       <&dma1 1 6>;
+                                dma-names = "tx", "rx";
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 status = "disabled";
@@ -487,6 +499,9 @@
                                 compatible = "atmel,at91sam9x5-i2c";
                                 reg = <0xf8018000 0x100>;
                                 interrupts = <11 4 6>;
+                                dmas = <&dma0 1 9>,
+                                       <&dma0 1 10>;
+                                dma-names = "tx", "rx";
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 status = "disabled";
diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index 9de93096601a..aaa63d0a8096 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -191,8 +191,8 @@
 
                 prcmu: prcmu@80157000 {
                         compatible = "stericsson,db8500-prcmu";
-                        reg = <0x80157000 0x1000>;
-                        reg-names = "prcmu";
+                        reg = <0x80157000 0x1000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
+                        reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
                         interrupts = <0 47 0x4>;
                         #address-cells = <1>;
                         #size-cells = <1>;
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 2feffc70814c..49a2786e00b9 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -47,6 +47,28 @@
                              <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
         };
 
+        mct@10050000 {
+                compatible = "samsung,exynos4210-mct";
+                reg = <0x10050000 0x800>;
+                interrupt-controller;
+                #interrups-cells = <2>;
+                interrupt-parent = <&mct_map>;
+                interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
+                             <4 0>, <5 0>;
+
+                mct_map: mct-map {
+                        #interrupt-cells = <2>;
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        interrupt-map = <0x0 0 &gic 0 57 0>,
+                                        <0x1 0 &gic 0 69 0>,
+                                        <0x2 0 &combiner 12 6>,
+                                        <0x3 0 &combiner 12 7>,
+                                        <0x4 0 &gic 0 42 0>,
+                                        <0x5 0 &gic 0 48 0>;
+                };
+        };
+
         pinctrl_0: pinctrl@11400000 {
                 compatible = "samsung,exynos4210-pinctrl";
                 reg = <0x11400000 0x1000>;
diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi
index c6ae2005961f..36d4299789ef 100644
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -25,4 +25,26 @@
         gic:interrupt-controller@10490000 {
                 cpu-offset = <0x8000>;
         };
+
+        mct@10050000 {
+                compatible = "samsung,exynos4412-mct";
+                reg = <0x10050000 0x800>;
+                interrupt-controller;
+                #interrups-cells = <2>;
+                interrupt-parent = <&mct_map>;
+                interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
+                             <4 0>, <5 0>;
+
+                mct_map: mct-map {
+                        #interrupt-cells = <2>;
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        interrupt-map = <0x0 0 &gic 0 57 0>,
+                                        <0x1 0 &combiner 12 5>,
+                                        <0x2 0 &combiner 12 6>,
+                                        <0x3 0 &combiner 12 7>,
+                                        <0x4 0 &gic 1 12 0>,
+                                        <0x5 0 &gic 1 12 0>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index d7dfe312772a..821c9fdd1e3b 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -25,4 +25,28 @@
         gic:interrupt-controller@10490000 {
                 cpu-offset = <0x4000>;
         };
+
+        mct@10050000 {
+                compatible = "samsung,exynos4412-mct";
+                reg = <0x10050000 0x800>;
+                interrupt-controller;
+                #interrups-cells = <2>;
+                interrupt-parent = <&mct_map>;
+                interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
+                             <4 0>, <5 0>, <6 0>, <7 0>;
+
+                mct_map: mct-map {
+                        #interrupt-cells = <2>;
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        interrupt-map = <0x0 0 &gic 0 57 0>,
+                                        <0x1 0 &combiner 12 5>,
+                                        <0x2 0 &combiner 12 6>,
+                                        <0x3 0 &combiner 12 7>,
+                                        <0x4 0 &gic 1 12 0>,
+                                        <0x5 0 &gic 1 12 0>,
+                                        <0x6 0 &gic 1 12 0>,
+                                        <0x7 0 &gic 1 12 0>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index b1ac73e21c80..c60108e0d27e 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -69,6 +69,28 @@
                              <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
         };
 
+        mct@101C0000 {
+                compatible = "samsung,exynos4210-mct";
+                reg = <0x101C0000 0x800>;
+                interrupt-controller;
+                #interrups-cells = <2>;
+                interrupt-parent = <&mct_map>;
+                interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
+                             <4 0>, <5 0>;
+
+                mct_map: mct-map {
+                        #interrupt-cells = <2>;
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        interrupt-map = <0x0 0 &combiner 23 3>,
+                                        <0x1 0 &combiner 23 4>,
+                                        <0x2 0 &combiner 25 2>,
+                                        <0x3 0 &combiner 25 3>,
+                                        <0x4 0 &gic 0 120 0>,
+                                        <0x5 0 &gic 0 121 0>;
+                };
+        };
+
         watchdog {
                 compatible = "samsung,s3c2410-wdt";
                 reg = <0x101D0000 0x100>;
diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts
index 8b119399025a..ff1aea0ee043 100644
--- a/arch/arm/boot/dts/integratorcp.dts
+++ b/arch/arm/boot/dts/integratorcp.dts
@@ -24,15 +24,15 @@
         };
 
         timer0: timer@13000000 {
-                compatible = "arm,sp804", "arm,primecell";
+                compatible = "arm,integrator-cp-timer";
         };
 
         timer1: timer@13000100 {
-                compatible = "arm,sp804", "arm,primecell";
+                compatible = "arm,integrator-cp-timer";
         };
 
         timer2: timer@13000200 {
-                compatible = "arm,sp804", "arm,primecell";
+                compatible = "arm,integrator-cp-timer";
         };
 
         pic: pic@14000000 {
diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts
index bd83b8fc7c83..c3573be7b92c 100644
--- a/arch/arm/boot/dts/kirkwood-goflexnet.dts
+++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts
@@ -77,6 +77,7 @@
                 };
 
                 nand@3000000 {
+                        chip-delay = <40>;
                         status = "okay";
 
                         partition@0 {
diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
index 8aad00f81ed9..f7bec3b1ba32 100644
--- a/arch/arm/boot/dts/orion5x.dtsi
+++ b/arch/arm/boot/dts/orion5x.dtsi
@@ -13,6 +13,9 @@
         compatible = "marvell,orion5x";
         interrupt-parent = <&intc>;
 
+        aliases {
+                gpio0 = &gpio0;
+        };
         intc: interrupt-controller {
                 compatible = "marvell,orion-intc", "marvell,intc";
                 interrupt-controller;
@@ -32,7 +35,9 @@
                         #gpio-cells = <2>;
                         gpio-controller;
                         reg = <0x10100 0x40>;
-                        ngpio = <32>;
+                        ngpios = <32>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
                         interrupts = <6>, <7>, <8>, <9>;
                 };
 
@@ -91,7 +96,7 @@
                         reg = <0x90000 0x10000>,
                               <0xf2200000 0x800>;
                         reg-names = "regs", "sram";
-                        interrupts = <22>;
+                        interrupts = <28>;
                         status = "okay";
                 };
         };
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
new file mode 100644
index 000000000000..2e643ea51cce
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -0,0 +1,1046 @@
+/*
+ * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC
+ *                applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35 SoC
+ *
+ *  Copyright (C) 2013 Atmel,
+ *                2013 Ludovic Desroches <ludovic.desroches@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        model = "Atmel SAMA5D3 family SoC";
+        compatible = "atmel,sama5d3", "atmel,sama5";
+        interrupt-parent = <&aic>;
+
+        aliases {
+                serial0 = &dbgu;
+                serial1 = &usart0;
+                serial2 = &usart1;
+                serial3 = &usart2;
+                serial4 = &usart3;
+                gpio0 = &pioA;
+                gpio1 = &pioB;
+                gpio2 = &pioC;
+                gpio3 = &pioD;
+                gpio4 = &pioE;
+                tcb0 = &tcb0;
+                tcb1 = &tcb1;
+                i2c0 = &i2c0;
+                i2c1 = &i2c1;
+                i2c2 = &i2c2;
+                ssc0 = &ssc0;
+                ssc1 = &ssc1;
+        };
+        cpus {
+                cpu@0 {
+                        compatible = "arm,cortex-a5";
+                };
+        };
+
+        memory {
+                reg = <0x20000000 0x8000000>;
+        };
+
+        ahb {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                apb {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+
+                        mmc0: mmc@f0000000 {
+                                compatible = "atmel,hsmci";
+                                reg = <0xf0000000 0x600>;
+                                interrupts = <21 4 0>;
+                                dmas = <&dma0 2 0>;
+                                dma-names = "rxtx";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>;
+                                status = "disabled";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        spi0: spi@f0004000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "atmel,at91sam9x5-spi";
+                                reg = <0xf0004000 0x100>;
+                                interrupts = <24 4 3>;
+                                cs-gpios = <&pioD 13 0
+                                            &pioD 14 0 /* conflicts with SCK0 and CANRX0 */
+                                            &pioD 15 0 /* conflicts with CTS0 and CANTX0 */
+                                            &pioD 16 0 /* conflicts with RTS0 and PWMFI3 */
+                                           >;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_spi0>;
+                                status = "disabled";
+                        };
+
+                        ssc0: ssc@f0008000 {
+                                compatible = "atmel,at91sam9g45-ssc";
+                                reg = <0xf0008000 0x4000>;
+                                interrupts = <38 4 4>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
+                                status = "disabled";
+                        };
+
+                        can0: can@f000c000 {
+                                compatible = "atmel,at91sam9x5-can";
+                                reg = <0xf000c000 0x300>;
+                                interrupts = <40 4 3>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_can0_rx_tx>;
+                                status = "disabled";
+                        };
+
+                        tcb0: timer@f0010000 {
+                                compatible = "atmel,at91sam9x5-tcb";
+                                reg = <0xf0010000 0x100>;
+                                interrupts = <26 4 0>;
+                        };
+
+                        i2c0: i2c@f0014000 {
+                                compatible = "atmel,at91sam9x5-i2c";
+                                reg = <0xf0014000 0x4000>;
+                                interrupts = <18 4 6>;
+                                dmas = <&dma0 2 7>,
+                                       <&dma0 2 8>;
+                                dma-names = "tx", "rx";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_i2c0>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                status = "disabled";
+                        };
+
+                        i2c1: i2c@f0018000 {
+                                compatible = "atmel,at91sam9x5-i2c";
+                                reg = <0xf0018000 0x4000>;
+                                interrupts = <19 4 6>;
+                                dmas = <&dma0 2 9>,
+                                       <&dma0 2 10>;
+                                dma-names = "tx", "rx";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_i2c1>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                status = "disabled";
+                        };
+
+                        usart0: serial@f001c000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xf001c000 0x100>;
+                                interrupts = <12 4 5>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usart0>;
+                                status = "disabled";
+                        };
+
+                        usart1: serial@f0020000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xf0020000 0x100>;
+                                interrupts = <13 4 5>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usart1>;
+                                status = "disabled";
+                        };
+
+                        macb0: ethernet@f0028000 {
+                                compatible = "cnds,pc302-gem", "cdns,gem";
+                                reg = <0xf0028000 0x100>;
+                                interrupts = <34 4 3>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>;
+                                status = "disabled";
+                        };
+
+                        isi: isi@f0034000 {
+                                compatible = "atmel,at91sam9g45-isi";
+                                reg = <0xf0034000 0x4000>;
+                                interrupts = <37 4 5>;
+                                status = "disabled";
+                        };
+
+                        mmc1: mmc@f8000000 {
+                                compatible = "atmel,hsmci";
+                                reg = <0xf8000000 0x600>;
+                                interrupts = <22 4 0>;
+                                dmas = <&dma1 2 0>;
+                                dma-names = "rxtx";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
+                                status = "disabled";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        mmc2: mmc@f8004000 {
+                                compatible = "atmel,hsmci";
+                                reg = <0xf8004000 0x600>;
+                                interrupts = <23 4 0>;
+                                dmas = <&dma1 2 1>;
+                                dma-names = "rxtx";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>;
+                                status = "disabled";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        spi1: spi@f8008000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "atmel,at91sam9x5-spi";
+                                reg = <0xf8008000 0x100>;
+                                interrupts = <25 4 3>;
+                                cs-gpios = <&pioC 25 0
+                                            &pioC 26 0 /* conflitcs with TWD1 and ISI_D11 */
+                                            &pioC 27 0 /* conflitcs with TWCK1 and ISI_D10 */
+                                            &pioC 28 0 /* conflitcs with PWMFI0 and ISI_D9 */
+                                           >;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_spi1>;
+                                status = "disabled";
+                        };
+
+                        ssc1: ssc@f800c000 {
+                                compatible = "atmel,at91sam9g45-ssc";
+                                reg = <0xf800c000 0x4000>;
+                                interrupts = <39 4 4>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
+                                status = "disabled";
+                        };
+
+                        can1: can@f8010000 {
+                                compatible = "atmel,at91sam9x5-can";
+                                reg = <0xf8010000 0x300>;
+                                interrupts = <41 4 3>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_can1_rx_tx>;
+                        };
+
+                        tcb1: timer@f8014000 {
+                                compatible = "atmel,at91sam9x5-tcb";
+                                reg = <0xf8014000 0x100>;
+                                interrupts = <27 4 0>;
+                        };
+
+                        adc0: adc@f8018000 {
+                                compatible = "atmel,at91sam9260-adc";
+                                reg = <0xf8018000 0x100>;
+                                interrupts = <29 4 5>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <
+                                        &pinctrl_adc0_adtrg
+                                        &pinctrl_adc0_ad0
+                                        &pinctrl_adc0_ad1
+                                        &pinctrl_adc0_ad2
+                                        &pinctrl_adc0_ad3
+                                        &pinctrl_adc0_ad4
+                                        &pinctrl_adc0_ad5
+                                        &pinctrl_adc0_ad6
+                                        &pinctrl_adc0_ad7
+                                        &pinctrl_adc0_ad8
+                                        &pinctrl_adc0_ad9
+                                        &pinctrl_adc0_ad10
+                                        &pinctrl_adc0_ad11
+                                        >;
+                                atmel,adc-channel-base = <0x50>;
+                                atmel,adc-channels-used = <0xfff>;
+                                atmel,adc-drdy-mask = <0x1000000>;
+                                atmel,adc-num-channels = <12>;
+                                atmel,adc-startup-time = <40>;
+                                atmel,adc-status-register = <0x30>;
+                                atmel,adc-trigger-register = <0xc0>;
+                                atmel,adc-use-external;
+                                atmel,adc-vref = <3000>;
+                                atmel,adc-res = <10 12>;
+                                atmel,adc-res-names = "lowres", "highres";
+                                status = "disabled";
+
+                                trigger@0 {
+                                        trigger-name = "external-rising";
+                                        trigger-value = <0x1>;
+                                        trigger-external;
+                                };
+                                trigger@1 {
+                                        trigger-name = "external-falling";
+                                        trigger-value = <0x2>;
+                                        trigger-external;
+                                };
+                                trigger@2 {
+                                        trigger-name = "external-any";
+                                        trigger-value = <0x3>;
+                                        trigger-external;
+                                };
+                                trigger@3 {
+                                        trigger-name = "continuous";
+                                        trigger-value = <0x6>;
+                                };
+                        };
+
+                        tsadcc: tsadcc@f8018000 {
+                                compatible = "atmel,at91sam9x5-tsadcc";
+                                reg = <0xf8018000 0x4000>;
+                                interrupts = <29 4 5>;
+                                atmel,tsadcc_clock = <300000>;
+                                atmel,filtering_average = <0x03>;
+                                atmel,pendet_debounce = <0x08>;
+                                atmel,pendet_sensitivity = <0x02>;
+                                atmel,ts_sample_hold_time = <0x0a>;
+                                status = "disabled";
+                        };
+
+                        i2c2: i2c@f801c000 {
+                                compatible = "atmel,at91sam9x5-i2c";
+                                reg = <0xf801c000 0x4000>;
+                                interrupts = <20 4 6>;
+                                dmas = <&dma1 2 11>,
+                                       <&dma1 2 12>;
+                                dma-names = "tx", "rx";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                status = "disabled";
+                        };
+
+                        usart2: serial@f8020000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xf8020000 0x100>;
+                                interrupts = <14 4 5>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usart2>;
+                                status = "disabled";
+                        };
+
+                        usart3: serial@f8024000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xf8024000 0x100>;
+                                interrupts = <15 4 5>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usart3>;
+                                status = "disabled";
+                        };
+
+                        macb1: ethernet@f802c000 {
+                                compatible = "cdns,at32ap7000-macb", "cdns,macb";
+                                reg = <0xf802c000 0x100>;
+                                interrupts = <35 4 3>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_macb1_rmii>;
+                                status = "disabled";
+                        };
+
+                        sha@f8034000 {
+                                compatible = "atmel,sam9g46-sha";
+                                reg = <0xf8034000 0x100>;
+                                interrupts = <42 4 0>;
+                        };
+
+                        aes@f8038000 {
+                                compatible = "atmel,sam9g46-aes";
+                                reg = <0xf8038000 0x100>;
+                                interrupts = <43 4 0>;
+                        };
+
+                        tdes@f803c000 {
+                                compatible = "atmel,sam9g46-tdes";
+                                reg = <0xf803c000 0x100>;
+                                interrupts = <44 4 0>;
+                        };
+
+                        dma0: dma-controller@ffffe600 {
+                                compatible = "atmel,at91sam9g45-dma";
+                                reg = <0xffffe600 0x200>;
+                                interrupts = <30 4 0>;
+                                #dma-cells = <2>;
+                        };
+
+                        dma1: dma-controller@ffffe800 {
+                                compatible = "atmel,at91sam9g45-dma";
+                                reg = <0xffffe800 0x200>;
+                                interrupts = <31 4 0>;
+                                #dma-cells = <2>;
+                        };
+
+                        ramc0: ramc@ffffea00 {
+                                compatible = "atmel,at91sam9g45-ddramc";
+                                reg = <0xffffea00 0x200>;
+                        };
+
+                        dbgu: serial@ffffee00 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xffffee00 0x200>;
+                                interrupts = <2 4 7>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_dbgu>;
+                                status = "disabled";
+                        };
+
+                        aic: interrupt-controller@fffff000 {
+                                #interrupt-cells = <3>;
+                                compatible = "atmel,sama5d3-aic";
+                                interrupt-controller;
+                                reg = <0xfffff000 0x200>;
+                                atmel,external-irqs = <47>;
+                        };
+
+                        pinctrl@fffff200 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
+                                ranges = <0xfffff200 0xfffff200 0xa00>;
+                                atmel,mux-mask = <
+                                        /*   A          B          C  */
+                                        0xffffffff 0xc0fc0000 0xc0ff0000        /* pioA */
+                                        0xffffffff 0x0ff8ffff 0x00000000        /* pioB */
+                                        0xffffffff 0xbc00f1ff 0x7c00fc00        /* pioC */
+                                        0xffffffff 0xc001c0e0 0x0001c1e0        /* pioD */
+                                        0xffffffff 0xbf9f8000 0x18000000        /* pioE */
+                                        >;
+
+                                /* shared pinctrl settings */
+                                adc0 {
+                                        pinctrl_adc0_adtrg: adc0_adtrg {
+                                                atmel,pins =
+                                                        <3 19 0x1 0x0>; /* PD19 periph A ADTRG */
+                                        };
+                                        pinctrl_adc0_ad0: adc0_ad0 {
+                                                atmel,pins =
+                                                        <3 20 0x1 0x0>; /* PD20 periph A AD0 */
+                                        };
+                                        pinctrl_adc0_ad1: adc0_ad1 {
+                                                atmel,pins =
+                                                        <3 21 0x1 0x0>; /* PD21 periph A AD1 */
+                                        };
+                                        pinctrl_adc0_ad2: adc0_ad2 {
+                                                atmel,pins =
+                                                        <3 22 0x1 0x0>; /* PD22 periph A AD2 */
+                                        };
+                                        pinctrl_adc0_ad3: adc0_ad3 {
+                                                atmel,pins =
+                                                        <3 23 0x1 0x0>; /* PD23 periph A AD3 */
+                                        };
+                                        pinctrl_adc0_ad4: adc0_ad4 {
+                                                atmel,pins =
+                                                        <3 24 0x1 0x0>; /* PD24 periph A AD4 */
+                                        };
+                                        pinctrl_adc0_ad5: adc0_ad5 {
+                                                atmel,pins =
+                                                        <3 25 0x1 0x0>; /* PD25 periph A AD5 */
+                                        };
+                                        pinctrl_adc0_ad6: adc0_ad6 {
+                                                atmel,pins =
+                                                        <3 26 0x1 0x0>; /* PD26 periph A AD6 */
+                                        };
+                                        pinctrl_adc0_ad7: adc0_ad7 {
+                                                atmel,pins =
+                                                        <3 27 0x1 0x0>; /* PD27 periph A AD7 */
+                                        };
+                                        pinctrl_adc0_ad8: adc0_ad8 {
+                                                atmel,pins =
+                                                        <3 28 0x1 0x0>; /* PD28 periph A AD8 */
+                                        };
+                                        pinctrl_adc0_ad9: adc0_ad9 {
+                                                atmel,pins =
+                                                        <3 29 0x1 0x0>; /* PD29 periph A AD9 */
+                                        };
+                                        pinctrl_adc0_ad10: adc0_ad10 {
+                                                atmel,pins =
+                                                        <3 30 0x1 0x0>; /* PD30 periph A AD10, conflicts with PCK0 */
+                                        };
+                                        pinctrl_adc0_ad11: adc0_ad11 {
+                                                atmel,pins =
+                                                        <3 31 0x1 0x0>; /* PD31 periph A AD11, conflicts with PCK1 */
+                                        };
+                                };
+
+                                can0 {
+                                        pinctrl_can0_rx_tx: can0_rx_tx {
+                                                atmel,pins =
+                                                        <3 14 0x3 0x0   /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */
+                                                         3 15 0x3 0x0>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */
+                                        };
+                                };
+
+                                can1 {
+                                        pinctrl_can1_rx_tx: can1_rx_tx {
+                                                atmel,pins =
+                                                        <1 14 0x2 0x0   /* PB14 periph B RX, conflicts with GCRS */
+                                                         1 15 0x2 0x0>; /* PB15 periph B TX, conflicts with GCOL */
+                                        };
+                                };
+
+                                dbgu {
+                                        pinctrl_dbgu: dbgu-0 {
+                                                atmel,pins =
+                                                        <1 30 0x1 0x0   /* PB30 periph A */
+                                                         1 31 0x1 0x1>; /* PB31 periph A with pullup */
+                                        };
+                                };
+
+                                i2c0 {
+                                        pinctrl_i2c0: i2c0-0 {
+                                                atmel,pins =
+                                                        <0 30 0x1 0x0   /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */
+                                                         0 31 0x1 0x0>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */
+                                        };
+                                };
+
+                                i2c1 {
+                                        pinctrl_i2c1: i2c1-0 {
+                                                atmel,pins =
+                                                        <2 26 0x2 0x0   /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */
+                                                         2 27 0x2 0x0>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */
+                                        };
+                                };
+
+                                isi {
+                                        pinctrl_isi: isi-0 {
+                                                atmel,pins =
+                                                        <0 16 0x3 0x0   /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */
+                                                         0 17 0x3 0x0   /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */
+                                                         0 18 0x3 0x0   /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */
+                                                         0 19 0x3 0x0   /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */
+                                                         0 20 0x3 0x0   /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */
+                                                         0 21 0x3 0x0   /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */
+                                                         0 22 0x3 0x0   /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */
+                                                         0 23 0x3 0x0   /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */
+                                                         2 30 0x3 0x0   /* PC30 periph C ISI_PCK, conflicts with UTXD0 */
+                                                         0 31 0x3 0x0   /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */
+                                                         0 30 0x3 0x0   /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */
+                                                         2 29 0x3 0x0   /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */
+                                                         2 28 0x3 0x0>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */
+                                        };
+                                        pinctrl_isi_pck_as_mck: isi_pck_as_mck-0 {
+                                                atmel,pins =
+                                                        <3 31 0x2 0x0>; /* PD31 periph B ISI_MCK */
+                                        };
+                                };
+
+                                lcd {
+                                        pinctrl_lcd: lcd-0 {
+                                                atmel,pins =
+                                                        <0 24 0x1 0x0   /* PA24 periph A LCDPWM */
+                                                         0 26 0x1 0x0   /* PA26 periph A LCDVSYNC */
+                                                         0 27 0x1 0x0   /* PA27 periph A LCDHSYNC */
+                                                         0 25 0x1 0x0   /* PA25 periph A LCDDISP */
+                                                         0 29 0x1 0x0   /* PA29 periph A LCDDEN */
+                                                         0 28 0x1 0x0   /* PA28 periph A LCDPCK */
+                                                         0 0 0x1 0x0    /* PA0 periph A LCDD0 pin */
+                                                         0 1 0x1 0x0    /* PA1 periph A LCDD1 pin */
+                                                         0 2 0x1 0x0    /* PA2 periph A LCDD2 pin */
+                                                         0 3 0x1 0x0    /* PA3 periph A LCDD3 pin */
+                                                         0 4 0x1 0x0    /* PA4 periph A LCDD4 pin */
+                                                         0 5 0x1 0x0    /* PA5 periph A LCDD5 pin */
+                                                         0 6 0x1 0x0    /* PA6 periph A LCDD6 pin */
+                                                         0 7 0x1 0x0    /* PA7 periph A LCDD7 pin */
+                                                         0 8 0x1 0x0    /* PA8 periph A LCDD8 pin */
+                                                         0 9 0x1 0x0    /* PA9 periph A LCDD9 pin */
+                                                         0 10 0x1 0x0   /* PA10 periph A LCDD10 pin */
+                                                         0 11 0x1 0x0   /* PA11 periph A LCDD11 pin */
+                                                         0 12 0x1 0x0   /* PA12 periph A LCDD12 pin */
+                                                         0 13 0x1 0x0   /* PA13 periph A LCDD13 pin */
+                                                         0 14 0x1 0x0   /* PA14 periph A LCDD14 pin */
+                                                         0 15 0x1 0x0   /* PA15 periph A LCDD15 pin */
+                                                         2 14 0x3 0x0   /* PC14 periph C LCDD16 pin */
+                                                         2 13 0x3 0x0   /* PC13 periph C LCDD17 pin */
+                                                         2 12 0x3 0x0   /* PC12 periph C LCDD18 pin */
+                                                         2 11 0x3 0x0   /* PC11 periph C LCDD19 pin */
+                                                         2 10 0x3 0x0   /* PC10 periph C LCDD20 pin */
+                                                         2 15 0x3 0x0   /* PC15 periph C LCDD21 pin */
+                                                         4 27 0x3 0x0   /* PE27 periph C LCDD22 pin */
+                                                         4 28 0x3 0x0>; /* PE28 periph C LCDD23 pin */
+                                        };
+                                };
+
+                                macb0 {
+                                        pinctrl_macb0_data_rgmii: macb0_data_rgmii {
+                                                atmel,pins =
+                                                        <1 0 0x1 0x0    /* PB0 periph A GTX0, conflicts with PWMH0 */
+                                                         1 1 0x1 0x0    /* PB1 periph A GTX1, conflicts with PWML0 */
+                                                         1 2 0x1 0x0    /* PB2 periph A GTX2, conflicts with TK1 */
+                                                         1 3 0x1 0x0    /* PB3 periph A GTX3, conflicts with TF1 */
+                                                         1 4 0x1 0x0    /* PB4 periph A GRX0, conflicts with PWMH1 */
+                                                         1 5 0x1 0x0    /* PB5 periph A GRX1, conflicts with PWML1 */
+                                                         1 6 0x1 0x0    /* PB6 periph A GRX2, conflicts with TD1 */
+                                                         1 7 0x1 0x0>;  /* PB7 periph A GRX3, conflicts with RK1 */
+                                        };
+                                        pinctrl_macb0_data_gmii: macb0_data_gmii {
+                                                atmel,pins =
+                                                        <1 19 0x2 0x0   /* PB19 periph B GTX4, conflicts with MCI1_CDA */
+                                                         1 20 0x2 0x0   /* PB20 periph B GTX5, conflicts with MCI1_DA0 */
+                                                         1 21 0x2 0x0   /* PB21 periph B GTX6, conflicts with MCI1_DA1 */
+                                                         1 22 0x2 0x0   /* PB22 periph B GTX7, conflicts with MCI1_DA2 */
+                                                         1 23 0x2 0x0   /* PB23 periph B GRX4, conflicts with MCI1_DA3 */
+                                                         1 24 0x2 0x0   /* PB24 periph B GRX5, conflicts with MCI1_CK */
+                                                         1 25 0x2 0x0   /* PB25 periph B GRX6, conflicts with SCK1 */
+                                                         1 26 0x2 0x0>; /* PB26 periph B GRX7, conflicts with CTS1 */
+                                        };
+                                        pinctrl_macb0_signal_rgmii: macb0_signal_rgmii {
+                                                atmel,pins =
+                                                        <1 8 0x1 0x0    /* PB8 periph A GTXCK, conflicts with PWMH2 */
+                                                         1 9 0x1 0x0    /* PB9 periph A GTXEN, conflicts with PWML2 */
+                                                         1 11 0x1 0x0   /* PB11 periph A GRXCK, conflicts with RD1 */
+                                                         1 13 0x1 0x0   /* PB13 periph A GRXER, conflicts with PWML3 */
+                                                         1 16 0x1 0x0   /* PB16 periph A GMDC */
+                                                         1 17 0x1 0x0   /* PB17 periph A GMDIO */
+                                                         1 18 0x1 0x0>; /* PB18 periph A G125CK */
+                                        };
+                                        pinctrl_macb0_signal_gmii: macb0_signal_gmii {
+                                                atmel,pins =
+                                                        <1 9 0x1 0x0    /* PB9 periph A GTXEN, conflicts with PWML2 */
+                                                         1 10 0x1 0x0   /* PB10 periph A GTXER, conflicts with RF1 */
+                                                         1 11 0x1 0x0   /* PB11 periph A GRXCK, conflicts with RD1 */
+                                                         1 12 0x1 0x0   /* PB12 periph A GRXDV, conflicts with PWMH3 */
+                                                         1 13 0x1 0x0   /* PB13 periph A GRXER, conflicts with PWML3 */
+                                                         1 14 0x1 0x0   /* PB14 periph A GCRS, conflicts with CANRX1 */
+                                                         1 15 0x1 0x0   /* PB15 periph A GCOL, conflicts with CANTX1 */
+                                                         1 16 0x1 0x0   /* PB16 periph A GMDC */
+                                                         1 17 0x1 0x0   /* PB17 periph A GMDIO */
+                                                         1 27 0x2 0x0>; /* PB27 periph B G125CKO */
+                                        };
+
+                                };
+
+                                macb1 {
+                                        pinctrl_macb1_rmii: macb1_rmii-0 {
+                                                atmel,pins =
+                                                        <2 0 0x1 0x0    /* PC0 periph A ETX0, conflicts with TIOA3 */
+                                                         2 1 0x1 0x0    /* PC1 periph A ETX1, conflicts with TIOB3 */
+                                                         2 2 0x1 0x0    /* PC2 periph A ERX0, conflicts with TCLK3 */
+                                                         2 3 0x1 0x0    /* PC3 periph A ERX1, conflicts with TIOA4 */
+                                                         2 4 0x1 0x0    /* PC4 periph A ETXEN, conflicts with TIOB4 */
+                                                         2 5 0x1 0x0    /* PC5 periph A ECRSDV,conflicts with TCLK4 */
+                                                         2 6 0x1 0x0    /* PC6 periph A ERXER, conflicts with TIOA5 */
+                                                         2 7 0x1 0x0    /* PC7 periph A EREFCK, conflicts with TIOB5 */
+                                                         2 8 0x1 0x0    /* PC8 periph A EMDC, conflicts with TCLK5 */
+                                                         2 9 0x1 0x0>;  /* PC9 periph A EMDIO  */
+                                        };
+                                };
+
+                                mmc0 {
+                                        pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
+                                                atmel,pins =
+                                                        <3 9 0x1 0x0    /* PD9 periph A MCI0_CK */
+                                                         3 0 0x1 0x1    /* PD0 periph A MCI0_CDA with pullup */
+                                                         3 1 0x1 0x1>;  /* PD1 periph A MCI0_DA0 with pullup */
+                                        };
+                                        pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
+                                                atmel,pins =
+                                                        <3 2 0x1 0x1    /* PD2 periph A MCI0_DA1 with pullup */
+                                                         3 3 0x1 0x1    /* PD3 periph A MCI0_DA2 with pullup */
+                                                         3 4 0x1 0x1>;  /* PD4 periph A MCI0_DA3 with pullup */
+                                        };
+                                        pinctrl_mmc0_dat4_7: mmc0_dat4_7 {
+                                                atmel,pins =
+                                                        <3 5 0x1 0x1    /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */
+                                                         3 6 0x1 0x1    /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */
+                                                         3 7 0x1 0x1    /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */
+                                                         3 8 0x1 0x1>;  /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */
+                                        };
+                                };
+
+                                mmc1 {
+                                        pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
+                                                atmel,pins =
+                                                        <1 24 0x1 0x0   /* PB24 periph A MCI1_CK, conflicts with GRX5 */
+                                                         1 19 0x1 0x1   /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */
+                                                         1 20 0x1 0x1>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */
+                                        };
+                                        pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
+                                                atmel,pins =
+                                                        <1 21 0x1 0x1   /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */
+                                                         1 22 0x1 0x1   /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */
+                                                         1 23 0x1 0x1>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */
+                                        };
+                                };
+
+                                mmc2 {
+                                        pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 {
+                                                atmel,pins =
+                                                        <2 15 0x1 0x0   /* PC15 periph A MCI2_CK, conflicts with PCK2 */
+                                                         2 10 0x1 0x1   /* PC10 periph A MCI2_CDA with pullup */
+                                                         2 11 0x1 0x1>; /* PC11 periph A MCI2_DA0 with pullup */
+                                        };
+                                        pinctrl_mmc2_dat1_3: mmc2_dat1_3 {
+                                                atmel,pins =
+                                                        <2 12 0x1 0x0   /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */
+                                                         2 13 0x1 0x0   /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */
+                                                         2 14 0x1 0x0>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */
+                                        };
+                                };
+
+                                nand0 {
+                                        pinctrl_nand0_ale_cle: nand0_ale_cle-0 {
+                                                atmel,pins =
+                                                        <4 21 0x1 0x1   /* PE21 periph A with pullup */
+                                                         4 22 0x1 0x1>; /* PE22 periph A with pullup */
+                                        };
+                                };
+
+                                pioA: gpio@fffff200 {
+                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                        reg = <0xfffff200 0x100>;
+                                        interrupts = <6 4 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
+
+                                pioB: gpio@fffff400 {
+                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                        reg = <0xfffff400 0x100>;
+                                        interrupts = <7 4 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
+
+                                pioC: gpio@fffff600 {
+                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                        reg = <0xfffff600 0x100>;
+                                        interrupts = <8 4 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
+
+                                pioD: gpio@fffff800 {
+                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                        reg = <0xfffff800 0x100>;
+                                        interrupts = <9 4 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
+
+                                pioE: gpio@fffffa00 {
+                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                        reg = <0xfffffa00 0x100>;
+                                        interrupts = <10 4 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
+
+                                spi0 {
+                                        pinctrl_spi0: spi0-0 {
+                                                atmel,pins =
+                                                        <3 10 0x1 0x0   /* PD10 periph A SPI0_MISO pin */
+                                                         3 11 0x1 0x0   /* PD11 periph A SPI0_MOSI pin */
+                                                         3 12 0x1 0x0   /* PD12 periph A SPI0_SPCK pin */
+                                                         3 13 0x0 0x0>; /* PD13 GPIO SPI0_NPCS0 pin */
+                                        };
+                                };
+
+                                spi1 {
+                                        pinctrl_spi1: spi1-0 {
+                                                atmel,pins =
+                                                        <2 22 0x1 0x0   /* PC22 periph A SPI1_MISO pin */
+                                                         2 23 0x1 0x0   /* PC23 periph A SPI1_MOSI pin */
+                                                         2 24 0x1 0x0   /* PC24 periph A SPI1_SPCK pin */
+                                                         2 25 0x0 0x0>; /* PC25 GPIO SPI1_NPCS0 pin */
+                                        };
+                                };
+
+                                ssc0 {
+                                        pinctrl_ssc0_tx: ssc0_tx {
+                                                atmel,pins =
+                                                        <2 16 0x1 0x0   /* PC16 periph A TK0 */
+                                                         2 17 0x1 0x0   /* PC17 periph A TF0 */
+                                                         2 18 0x1 0x0>; /* PC18 periph A TD0 */
+                                        };
+
+                                        pinctrl_ssc0_rx: ssc0_rx {
+                                                atmel,pins =
+                                                        <2 19 0x1 0x0   /* PC19 periph A RK0 */
+                                                         2 20 0x1 0x0   /* PC20 periph A RF0 */
+                                                         2 21 0x1 0x0>; /* PC21 periph A RD0 */
+                                        };
+                                };
+
+                                ssc1 {
+                                        pinctrl_ssc1_tx: ssc1_tx {
+                                                atmel,pins =
+                                                        <1 2 0x2 0x0    /* PB2 periph B TK1, conflicts with GTX2 */
+                                                         1 3 0x2 0x0    /* PB3 periph B TF1, conflicts with GTX3 */
+                                                         1 6 0x2 0x0>;  /* PB6 periph B TD1, conflicts with TD1 */
+                                        };
+
+                                        pinctrl_ssc1_rx: ssc1_rx {
+                                                atmel,pins =
+                                                        <1 7 0x2 0x0    /* PB7 periph B RK1, conflicts with EREFCK */
+                                                         1 10 0x2 0x0   /* PB10 periph B RF1, conflicts with GTXER */
+                                                         1 11 0x2 0x0>; /* PB11 periph B RD1, conflicts with GRXCK */
+                                        };
+                                };
+
+                                uart0 {
+                                        pinctrl_uart0: uart0-0 {
+                                                atmel,pins =
+                                                        <2 29 0x1 0x0   /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */
+                                                         2 30 0x1 0x1>; /* PC30 periph A with pullup, conflicts with ISI_PCK */
+                                        };
+                                };
+
+                                uart1 {
+                                        pinctrl_uart1: uart1-0 {
+                                                atmel,pins =
+                                                        <0 30 0x2 0x0   /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */
+                                                         0 31 0x2 0x1>; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */
+                                        };
+                                };
+
+                                usart0 {
+                                        pinctrl_usart0: usart0-0 {
+                                                atmel,pins =
+                                                        <3 17 0x1 0x0   /* PD17 periph A */
+                                                         3 18 0x1 0x1>; /* PD18 periph A with pullup */
+                                        };
+
+                                        pinctrl_usart0_rts_cts: usart0_rts_cts-0 {
+                                                atmel,pins =
+                                                        <3 15 0x1 0x0   /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */
+                                                         3 16 0x1 0x0>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */
+                                        };
+                                };
+
+                                usart1 {
+                                        pinctrl_usart1: usart1-0 {
+                                                atmel,pins =
+                                                        <1 28 0x1 0x0   /* PB28 periph A */
+                                                         1 29 0x1 0x1>; /* PB29 periph A with pullup */
+                                        };
+
+                                        pinctrl_usart1_rts_cts: usart1_rts_cts-0 {
+                                                atmel,pins =
+                                                        <1 26 0x1 0x0   /* PB26 periph A, conflicts with GRX7 */
+                                                         1 27 0x1 0x0>; /* PB27 periph A, conflicts with G125CKO */
+                                        };
+                                };
+
+                                usart2 {
+                                        pinctrl_usart2: usart2-0 {
+                                                atmel,pins =
+                                                        <4 25 0x2 0x0   /* PE25 periph B, conflicts with A25 */
+                                                         4 26 0x2 0x1>; /* PE26 periph B with pullup, conflicts NCS0 */
+                                        };
+
+                                        pinctrl_usart2_rts_cts: usart2_rts_cts-0 {
+                                                atmel,pins =
+                                                        <4 23 0x2 0x0   /* PE23 periph B, conflicts with A23 */
+                                                         4 24 0x2 0x0>; /* PE24 periph B, conflicts with A24 */
+                                        };
+                                };
+
+                                usart3 {
+                                        pinctrl_usart3: usart3-0 {
+                                                atmel,pins =
+                                                        <4 18 0x2 0x0   /* PE18 periph B, conflicts with A18 */
+                                                         4 19 0x2 0x1>; /* PE19 periph B with pullup, conflicts with A19 */
+                                        };
+
+                                        pinctrl_usart3_rts_cts: usart3_rts_cts-0 {
+                                                atmel,pins =
+                                                        <4 16 0x2 0x0   /* PE16 periph B, conflicts with A16 */
+                                                         4 17 0x2 0x0>; /* PE17 periph B, conflicts with A17 */
+                                        };
+                                };
+                        };
+
+                        pmc: pmc@fffffc00 {
+                                compatible = "atmel,at91rm9200-pmc";
+                                reg = <0xfffffc00 0x120>;
+                        };
+
+                        rstc@fffffe00 {
+                                compatible = "atmel,at91sam9g45-rstc";
+                                reg = <0xfffffe00 0x10>;
+                        };
+
+                        pit: timer@fffffe30 {
+                                compatible = "atmel,at91sam9260-pit";
+                                reg = <0xfffffe30 0xf>;
+                                interrupts = <3 4 5>;
+                        };
+
+                        watchdog@fffffe40 {
+                                compatible = "atmel,at91sam9260-wdt";
+                                reg = <0xfffffe40 0x10>;
+                                status = "disabled";
+                        };
+
+                        rtc@fffffeb0 {
+                                compatible = "atmel,at91rm9200-rtc";
+                                reg = <0xfffffeb0 0x30>;
+                                interrupts = <1 4 7>;
+                        };
+                };
+
+                usb0: gadget@00500000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "atmel,at91sam9rl-udc";
+                        reg = <0x00500000 0x100000
+                               0xf8030000 0x4000>;
+                        interrupts = <33 4 2>;
+                        status = "disabled";
+
+                        ep0 {
+                                reg = <0>;
+                                atmel,fifo-size = <64>;
+                                atmel,nb-banks = <1>;
+                        };
+
+                        ep1 {
+                                reg = <1>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <3>;
+                                atmel,can-dma;
+                                atmel,can-isoc;
+                        };
+
+                        ep2 {
+                                reg = <2>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <3>;
+                                atmel,can-dma;
+                                atmel,can-isoc;
+                        };
+
+                        ep3 {
+                                reg = <3>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                                atmel,can-dma;
+                        };
+
+                        ep4 {
+                                reg = <4>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                                atmel,can-dma;
+                        };
+
+                        ep5 {
+                                reg = <5>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                                atmel,can-dma;
+                        };
+
+                        ep6 {
+                                reg = <6>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                                atmel,can-dma;
+                        };
+
+                        ep7 {
+                                reg = <7>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                                atmel,can-dma;
+                        };
+
+                        ep8 {
+                                reg = <8>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                        };
+
+                        ep9 {
+                                reg = <9>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                        };
+
+                        ep10 {
+                                reg = <10>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                        };
+
+                        ep11 {
+                                reg = <11>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                        };
+
+                        ep12 {
+                                reg = <12>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                        };
+
+                        ep13 {
+                                reg = <13>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                        };
+
+                        ep14 {
+                                reg = <14>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                        };
+
+                        ep15 {
+                                reg = <15>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                        };
+                };
+
+                usb1: ohci@00600000 {
+                        compatible = "atmel,at91rm9200-ohci", "usb-ohci";
+                        reg = <0x00600000 0x100000>;
+                        interrupts = <32 4 2>;
+                        status = "disabled";
+                };
+
+                usb2: ehci@00700000 {
+                        compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
+                        reg = <0x00700000 0x100000>;
+                        interrupts = <32 4 2>;
+                        status = "disabled";
+                };
+
+                nand0: nand@60000000 {
+                        compatible = "atmel,at91rm9200-nand";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = < 0x60000000 0x01000000   /* EBI CS3 */
+                                0xffffc070 0x00000490   /* SMC PMECC regs */
+                                0xffffc500 0x00000100   /* SMC PMECC Error Location regs */
+                                0x00100000 0x00100000   /* ROM code */
+                                0x70000000 0x10000000   /* NFC Command Registers */
+                                0xffffc000 0x00000070   /* NFC HSMC regs */
+                                0x00200000 0x00100000   /* NFC SRAM banks */
+                                >;
+                        interrupts = <5 4 6>;
+                        atmel,nand-addr-offset = <21>;
+                        atmel,nand-cmd-offset = <22>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_nand0_ale_cle>;
+                        atmel,pmecc-lookup-table-offset = <0x10000 0x18000>;
+                        status = "disabled";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sama5d31ek.dts b/arch/arm/boot/dts/sama5d31ek.dts
new file mode 100644
index 000000000000..fa5d216f1db7
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d31ek.dts
@@ -0,0 +1,51 @@
+/*
+ * sama5d31ek.dts - Device Tree file for SAMA5D31-EK board
+ *
+ *  Copyright (C) 2013 Atmel,
+ *                2013 Ludovic Desroches <ludovic.desroches@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+/include/ "sama5d3xmb.dtsi"
+/include/ "sama5d3xdm.dtsi"
+
+/ {
+        model = "Atmel SAMA5D31-EK";
+        compatible = "atmel,sama5d31ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5";
+
+        ahb {
+                apb {
+                        spi0: spi@f0004000 {
+                                status = "okay";
+                        };
+
+                        ssc0: ssc@f0008000 {
+                                status = "okay";
+                        };
+
+                        i2c0: i2c@f0014000 {
+                                status = "okay";
+                        };
+
+                        i2c1: i2c@f0018000 {
+                                status = "okay";
+                        };
+
+                        macb1: ethernet@f802c000 {
+                                status = "okay";
+                        };
+                };
+        };
+
+        leds {
+                d3 {
+                        label = "d3";
+                        gpios = <&pioE 24 0>;
+                };
+        };
+
+        sound {
+                status = "okay";
+        };
+};
diff --git a/arch/arm/boot/dts/sama5d33ek.dts b/arch/arm/boot/dts/sama5d33ek.dts
new file mode 100644
index 000000000000..c38c9433d7a5
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d33ek.dts
@@ -0,0 +1,44 @@
+/*
+ * sama5d33ek.dts - Device Tree file for SAMA5D33-EK board
+ *
+ *  Copyright (C) 2013 Atmel,
+ *                2013 Ludovic Desroches <ludovic.desroches@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+/include/ "sama5d3xmb.dtsi"
+/include/ "sama5d3xdm.dtsi"
+
+/ {
+        model = "Atmel SAMA5D33-EK";
+        compatible = "atmel,sama5d33ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5";
+
+        ahb {
+                apb {
+                        spi0: spi@f0004000 {
+                                status = "okay";
+                        };
+
+                        ssc0: ssc@f0008000 {
+                                status = "okay";
+                        };
+
+                        i2c0: i2c@f0014000 {
+                                status = "okay";
+                        };
+
+                        i2c1: i2c@f0018000 {
+                                status = "okay";
+                        };
+
+                        macb0: ethernet@f0028000 {
+                                status = "okay";
+                        };
+                };
+        };
+
+        sound {
+                status = "okay";
+        };
+};
diff --git a/arch/arm/boot/dts/sama5d34ek.dts b/arch/arm/boot/dts/sama5d34ek.dts
new file mode 100644
index 000000000000..6bebfcdcb1d1
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d34ek.dts
@@ -0,0 +1,61 @@
+/*
+ * sama5d34ek.dts - Device Tree file for SAMA5D34-EK board
+ *
+ *  Copyright (C) 2013 Atmel,
+ *                2013 Ludovic Desroches <ludovic.desroches@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+/include/ "sama5d3xmb.dtsi"
+/include/ "sama5d3xdm.dtsi"
+
+/ {
+        model = "Atmel SAMA5D34-EK";
+        compatible = "atmel,sama5d34ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5";
+
+        ahb {
+                apb {
+                        spi0: spi@f0004000 {
+                                status = "okay";
+                        };
+
+                        ssc0: ssc@f0008000 {
+                                status = "okay";
+                        };
+
+                        can0: can@f000c000 {
+                                status = "okay";
+                        };
+
+                        i2c0: i2c@f0014000 {
+                                status = "okay";
+                        };
+
+                        i2c1: i2c@f0018000 {
+                                status = "okay";
+
+                                24c256@50 {
+                                        compatible = "24c256";
+                                        reg = <0x50>;
+                                        pagesize = <64>;
+                                };
+                        };
+
+                        macb0: ethernet@f0028000 {
+                                status = "okay";
+                        };
+                };
+        };
+
+        leds {
+                d3 {
+                        label = "d3";
+                        gpios = <&pioE 24 0>;
+                };
+        };
+
+        sound {
+                status = "okay";
+        };
+};
diff --git a/arch/arm/boot/dts/sama5d35ek.dts b/arch/arm/boot/dts/sama5d35ek.dts
new file mode 100644
index 000000000000..a488fc4e9777
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d35ek.dts
@@ -0,0 +1,56 @@
+/*
+ * sama5d35ek.dts - Device Tree file for SAMA5D35-EK board
+ *
+ *  Copyright (C) 2013 Atmel,
+ *                2013 Ludovic Desroches <ludovic.desroches@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+/include/ "sama5d3xmb.dtsi"
+
+/ {
+        model = "Atmel SAMA5D35-EK";
+        compatible = "atmel,sama5d35ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5";
+
+        ahb {
+                apb {
+                        spi0: spi@f0004000 {
+                                status = "okay";
+                        };
+
+                        can0: can@f000c000 {
+                                status = "okay";
+                        };
+
+                        i2c1: i2c@f0018000 {
+                                status = "okay";
+                        };
+
+                        macb0: ethernet@f0028000 {
+                                status = "okay";
+                        };
+
+                        isi: isi@f0034000 {
+                                status = "okay";
+                        };
+
+                        macb1: ethernet@f802c000 {
+                                status = "okay";
+                        };
+                };
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                pb_user1 {
+                        label = "pb_user1";
+                        gpios = <&pioE 27 0>;
+                        linux,code = <0x100>;
+                        gpio-key,wakeup;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi
new file mode 100644
index 000000000000..1f8ed404626c
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
@@ -0,0 +1,91 @@
+/*
+ * sama5d3xcm.dtsi - Device Tree Include file for SAMA5D3x CPU Module
+ *
+ *  Copyright (C) 2013 Atmel,
+ *                2013 Ludovic Desroches <ludovic.desroches@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/include/ "sama5d3.dtsi"
+
+/ {
+        compatible = "atmel,samad3xcm", "atmel,sama5d3", "atmel,sama5";
+
+        chosen {
+                bootargs = "console=ttyS0,115200 rootfstype=ubifs ubi.mtd=5 root=ubi0:rootfs";
+        };
+
+        memory {
+                reg = <0x20000000 0x20000000>;
+        };
+
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                main_clock: clock@0 {
+                        compatible = "atmel,osc", "fixed-clock";
+                        clock-frequency = <12000000>;
+                };
+        };
+
+        ahb {
+                apb {
+                        macb0: ethernet@f0028000 {
+                                phy-mode = "rgmii";
+                        };
+                };
+
+                nand0: nand@60000000 {
+                        nand-bus-width = <8>;
+                        nand-ecc-mode = "hw";
+                        atmel,has-pmecc;
+                        atmel,pmecc-cap = <4>;
+                        atmel,pmecc-sector-size = <512>;
+                        atmel,has-nfc;
+                        atmel,use-nfc-sram;
+                        nand-on-flash-bbt;
+                        status = "okay";
+
+                        at91bootstrap@0 {
+                                label = "at91bootstrap";
+                                reg = <0x0 0x40000>;
+                        };
+
+                        bootloader@40000 {
+                                label = "bootloader";
+                                reg = <0x40000 0x80000>;
+                        };
+
+                        bootloaderenv@c0000 {
+                                label = "bootloader env";
+                                reg = <0xc0000 0xc0000>;
+                        };
+
+                        dtb@180000 {
+                                label = "device tree";
+                                reg = <0x180000 0x80000>;
+                        };
+
+                        kernel@200000 {
+                                label = "kernel";
+                                reg = <0x200000 0x600000>;
+                        };
+
+                        rootfs@800000 {
+                                label = "rootfs";
+                                reg = <0x800000 0x0f800000>;
+                        };
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                d2 {
+                        label = "d2";
+                        gpios = <&pioE 25 1>;   /* PE25, conflicts with A25, RXD2 */
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sama5d3xdm.dtsi b/arch/arm/boot/dts/sama5d3xdm.dtsi
new file mode 100644
index 000000000000..4b8830eb2060
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3xdm.dtsi
@@ -0,0 +1,42 @@
+/*
+ * sama5d3dm.dtsi - Device Tree file for SAMA5 display module
+ *
+ *  Copyright (C) 2013 Atmel,
+ *                2013 Ludovic Desroches <ludovic.desroches@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/ {
+        ahb {
+                apb {
+                        i2c1: i2c@f0018000 {
+                                qt1070: keyboard@1b {
+                                        compatible = "qt1070";
+                                        reg = <0x1b>;
+                                        interrupt-parent = <&pioE>;
+                                        interrupts = <31 0x0>;
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_qt1070_irq>;
+                                };
+                        };
+
+                        adc0: adc@f8018000 {
+                                status = "disabled";
+                        };
+
+                        tsadcc: tsadcc@f8018000 {
+                                status = "okay";
+                        };
+
+                        pinctrl@fffff200 {
+                                board {
+                                        pinctrl_qt1070_irq: qt1070_irq {
+                                                atmel,pins =
+                                                        <4 31 0x0 0x5>; /* PE31 GPIO with pull up deglith */
+                                        };
+                                };
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi b/arch/arm/boot/dts/sama5d3xmb.dtsi
new file mode 100644
index 000000000000..661d7ca9c309
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3xmb.dtsi
@@ -0,0 +1,166 @@
+/*
+ * sama5d3xmb.dts - Device Tree file for SAMA5D3x mother board
+ *
+ *  Copyright (C) 2013 Atmel,
+ *                2013 Ludovic Desroches <ludovic.desroches@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/include/ "sama5d3xcm.dtsi"
+
+/ {
+        compatible = "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5";
+
+        ahb {
+                apb {
+                        mmc0: mmc@f0000000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>;
+                                status = "okay";
+                                slot@0 {
+                                        reg = <0>;
+                                        bus-width = <4>;
+                                        cd-gpios = <&pioD 17 0>;
+                                };
+                        };
+
+                        spi0: spi@f0004000 {
+                                m25p80@0 {
+                                        compatible = "atmel,at25df321a";
+                                        spi-max-frequency = <50000000>;
+                                        reg = <0>;
+                                };
+                        };
+
+                        /*
+                         * i2c0 conflicts with ISI:
+                         * disable it to allow the use of ISI
+                         * can not enable audio when i2c0 disabled
+                         */
+                        i2c0: i2c@f0014000 {
+                                wm8904: wm8904@1a {
+                                        compatible = "wm8904";
+                                        reg = <0x1a>;
+                                };
+                        };
+
+                        usart1: serial@f0020000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>;
+                                status = "okay";
+                        };
+
+                        isi: isi@f0034000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_isi &pinctrl_isi_pck_as_mck &pinctrl_isi_power &pinctrl_isi_reset>;
+                        };
+
+                        mmc1: mmc@f8000000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>;
+                                status = "okay";
+                                slot@0 {
+                                        reg = <0>;
+                                        bus-width = <4>;
+                                        cd-gpios = <&pioD 18 0>;
+                                };
+                        };
+
+                        adc0: adc@f8018000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <
+                                        &pinctrl_adc0_adtrg
+                                        &pinctrl_adc0_ad0
+                                        &pinctrl_adc0_ad1
+                                        &pinctrl_adc0_ad2
+                                        &pinctrl_adc0_ad3
+                                        &pinctrl_adc0_ad4
+                                        >;
+                                status = "okay";
+                        };
+
+                        macb1: ethernet@f802c000 {
+                                phy-mode = "rmii";
+                        };
+
+                        pinctrl@fffff200 {
+                                board {
+                                        pinctrl_mmc0_cd: mmc0_cd {
+                                                atmel,pins =
+                                                        <3 17 0x0 0x5>; /* PD17 GPIO with pullup deglitch */
+                                        };
+
+                                        pinctrl_mmc1_cd: mmc1_cd {
+                                                atmel,pins =
+                                                        <3 18 0x0 0x5>; /* PD18 GPIO with pullup deglitch */
+                                        };
+
+                                        pinctrl_pck0_as_audio_mck: pck0_as_audio_mck {
+                                                atmel,pins =
+                                                        <3 30 0x2 0x0>; /* PD30 periph B */
+                                        };
+
+                                        pinctrl_isi_reset: isi_reset-0 {
+                                                atmel,pins =
+                                                        <4 24 0x0 0x0>;   /* PE24 gpio */
+                                        };
+
+                                        pinctrl_isi_power: isi_power-0 {
+                                                atmel,pins =
+                                                        <4 29 0x0 0x0>; /* PE29 gpio */
+                                        };
+
+                                        pinctrl_usba_vbus: usba_vbus {
+                                                atmel,pins =
+                                                        <3 29 0x0 0x4>; /* PD29 GPIO with deglitch */
+                                        };
+                                };
+                        };
+
+                        dbgu: serial@ffffee00 {
+                                status = "okay";
+                        };
+
+                        watchdog@fffffe40 {
+                                status = "okay";
+                        };
+                };
+
+                usb0: gadget@00500000 {
+                        atmel,vbus-gpio = <&pioD 29 0>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_usba_vbus>;
+                        status = "okay";
+                };
+
+                usb1: ohci@00600000 {
+                        num-ports = <3>;
+                        atmel,vbus-gpio = <&pioD 25 0
+                                           &pioD 26 1
+                                           &pioD 27 1
+                                          >;
+                        status = "okay";
+                };
+
+                usb2: ehci@00700000 {
+                        status = "okay";
+                };
+        };
+
+        sound {
+                compatible = "atmel,sama5d3ek-wm8904";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_pck0_as_audio_mck>;
+
+                atmel,model = "wm8904 @ SAMA5D3EK";
+                atmel,audio-routing =
+                        "Headphone Jack", "HPOUTL",
+                        "Headphone Jack", "HPOUTR",
+                        "IN2L", "Line In Jack",
+                        "IN2R", "Line In Jack",
+                        "IN1L", "Mic";
+
+                atmel,ssc-controller = <&ssc0>;
+                atmel,audio-codec = <&wm8904>;
+        };
+};
diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi
index 34da11aa6795..e1786a0b2fcd 100644
--- a/arch/arm/boot/dts/spear1340.dtsi
+++ b/arch/arm/boot/dts/spear1340.dtsi
@@ -113,6 +113,9 @@
                                 reg = <0xb4100000 0x1000>;
                                 interrupts = <0 105 0x4>;
                                 status = "disabled";
+                                dmas = <&dwdma0 0x600 0 0 1>, /* 0xC << 11 */
+                                        <&dwdma0 0x680 0 1 0>; /* 0xD << 7 */
+                                dma-names = "tx", "rx";
                         };
 
                         thermal@e07008c4 {
diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
index b4ca60f4eb42..45597fd91050 100644
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -98,13 +98,24 @@
                         reg = <0xb2800000 0x1000>;
                         interrupts = <0 29 0x4>;
                         status = "disabled";
+                        dmas = <&dwdma0 0 0 0 0>;
+                        dma-names = "data";
                 };
 
-                dma@ea800000 {
+                dwdma0: dma@ea800000 {
                         compatible = "snps,dma-spear1340";
                         reg = <0xea800000 0x1000>;
                         interrupts = <0 19 0x4>;
                         status = "disabled";
+
+                        dma-channels = <8>;
+                        #dma-cells = <3>;
+                        dma-requests = <32>;
+                        chan_allocation_order = <1>;
+                        chan_priority = <1>;
+                        block_size = <0xfff>;
+                        dma-masters = <2>;
+                        data_width = <3 3 0 0>;
                 };
 
                 dma@eb000000 {
@@ -112,6 +123,15 @@
                         reg = <0xeb000000 0x1000>;
                         interrupts = <0 59 0x4>;
                         status = "disabled";
+
+                        dma-requests = <32>;
+                        dma-channels = <8>;
+                        dma-masters = <2>;
+                        #dma-cells = <3>;
+                        chan_allocation_order = <1>;
+                        chan_priority = <1>;
+                        block_size = <0xfff>;
+                        data_width = <3 3 0 0>;
                 };
 
                 fsmc: flash@b0000000 {
@@ -261,6 +281,9 @@
                                 #size-cells = <0>;
                                 interrupts = <0 31 0x4>;
                                 status = "disabled";
+                                dmas = <&dwdma0 0x2000 0 0 0>, /* 0x4 << 11 */
+                                        <&dwdma0 0x0280 0 0 0>;  /* 0x5 << 7 */
+                                dma-names = "tx", "rx";
                         };
 
                         rtc@e0580000 {
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
index a30aca62658a..616990dc92db 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -12,10 +12,22 @@
 
         serial@70006300 {
                 status = "okay";
-                clock-frequency = <408000000>;
         };
 
         pmc {
                 nvidia,invert-interrupt;
         };
+
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/tegra114-pluto.dts b/arch/arm/boot/dts/tegra114-pluto.dts
index 9bea8f57aa47..6bbc8efae9c0 100644
--- a/arch/arm/boot/dts/tegra114-pluto.dts
+++ b/arch/arm/boot/dts/tegra114-pluto.dts
@@ -12,10 +12,22 @@
 
         serial@70006300 {
                 status = "okay";
-                clock-frequency = <408000000>;
         };
 
         pmc {
                 nvidia,invert-interrupt;
         };
+
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 1dfaf2874c57..c1110a9b2a91 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -24,10 +24,11 @@
                               0 42 0x04
                               0 121 0x04
                               0 122 0x04>;
+                clocks = <&tegra_car 5>;
         };
 
         tegra_car: clock {
-                compatible = "nvidia,tegra114-car, nvidia,tegra30-car";
+                compatible = "nvidia,tegra114-car";
                 reg = <0x60006000 0x1000>;
                 #clock-cells = <1>;
         };
@@ -66,6 +67,7 @@
                 reg-shift = <2>;
                 interrupts = <0 36 0x04>;
                 status = "disabled";
+                clocks = <&tegra_car 6>;
         };
 
         serial@70006040 {
@@ -74,6 +76,7 @@
                 reg-shift = <2>;
                 interrupts = <0 37 0x04>;
                 status = "disabled";
+                clocks = <&tegra_car 192>;
         };
 
         serial@70006200 {
@@ -82,6 +85,7 @@
                 reg-shift = <2>;
                 interrupts = <0 46 0x04>;
                 status = "disabled";
+                clocks = <&tegra_car 55>;
         };
 
         serial@70006300 {
@@ -90,17 +94,21 @@
                 reg-shift = <2>;
                 interrupts = <0 90 0x04>;
                 status = "disabled";
+                clocks = <&tegra_car 65>;
         };
 
         rtc {
                 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
                 reg = <0x7000e000 0x100>;
                 interrupts = <0 2 0x04>;
+                clocks = <&tegra_car 4>;
         };
 
         pmc {
-                compatible = "nvidia,tegra114-pmc", "nvidia,tegra30-pmc";
+                compatible = "nvidia,tegra114-pmc";
                 reg = <0x7000e400 0x400>;
+                clocks = <&tegra_car 261>, <&clk32k_in>;
+                clock-names = "pclk", "clk32k_in";
         };
 
         iommu {
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
index 444162090042..4e3afdef28a8 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -444,7 +444,20 @@
         };
 
         sdhci@c8000600 {
-                cd-gpios = <&gpio 23 0>; /* gpio PC7 */
+                cd-gpios = <&gpio 23 1>; /* gpio PC7 */
+        };
+
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
         };
 
         sound {
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index 61d027f03617..ae9d5a20834e 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -437,7 +437,7 @@
 
         sdhci@c8000200 {
                 status = "okay";
-                cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+                cd-gpios = <&gpio 69 1>; /* gpio PI5 */
                 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
                 power-gpios = <&gpio 155 0>; /* gpio PT3 */
                 bus-width = <4>;
@@ -445,12 +445,25 @@
 
         sdhci@c8000600 {
                 status = "okay";
-                cd-gpios = <&gpio 58 0>; /* gpio PH2 */
+                cd-gpios = <&gpio 58 1>; /* gpio PH2 */
                 wp-gpios = <&gpio 59 0>; /* gpio PH3 */
                 power-gpios = <&gpio 70 0>; /* gpio PI6 */
                 bus-width = <8>;
         };
 
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+
         kbc {
                 status = "okay";
                 nvidia,debounce-delay-ms = <2>;
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index 54d6fce00a59..fd60940e4063 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -436,7 +436,7 @@
 
         sdhci@c8000000 {
                 status = "okay";
-                cd-gpios = <&gpio 173 0>; /* gpio PV5 */
+                cd-gpios = <&gpio 173 1>; /* gpio PV5 */
                 wp-gpios = <&gpio 57 0>;  /* gpio PH1 */
                 power-gpios = <&gpio 169 0>; /* gpio PV1 */
                 bus-width = <4>;
@@ -447,6 +447,19 @@
                 bus-width = <8>;
         };
 
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+
         gpio-keys {
                 compatible = "gpio-keys";
 
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index 37b3a57ec0f1..4ee700a33ca5 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -584,7 +584,7 @@
 
         sdhci@c8000400 {
                 status = "okay";
-                cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+                cd-gpios = <&gpio 69 1>; /* gpio PI5 */
                 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
                 power-gpios = <&gpio 70 0>; /* gpio PI6 */
                 bus-width = <4>;
@@ -595,6 +595,19 @@
                 bus-width = <8>;
         };
 
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+
         gpio-keys {
                 compatible = "gpio-keys";
 
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
index 4766abae7a72..c19025725918 100644
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -465,12 +465,25 @@
         };
 
         sdhci@c8000600 {
-                cd-gpios = <&gpio 58 0>; /* gpio PH2 */
+                cd-gpios = <&gpio 58 1>; /* gpio PH2 */
                 wp-gpios = <&gpio 59 0>; /* gpio PH3 */
                 bus-width = <4>;
                 status = "okay";
         };
 
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+
         regulators {
                 compatible = "simple-bus";
 
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index 5d79e4fc49a6..a9f3f06580f5 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -325,11 +325,24 @@
 
         sdhci@c8000600 {
                 status = "okay";
-                cd-gpios = <&gpio 121 0>; /* gpio PP1 */
+                cd-gpios = <&gpio 121 1>; /* gpio PP1 */
                 wp-gpios = <&gpio 122 0>; /* gpio PP2 */
                 bus-width = <4>;
         };
 
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+
         poweroff {
                 compatible = "gpio-poweroff";
                 gpios = <&gpio 191 1>; /* gpio PX7, active low */
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index 425c89000c20..f544806e9618 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -520,7 +520,7 @@
 
         sdhci@c8000400 {
                 status = "okay";
-                cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+                cd-gpios = <&gpio 69 1>; /* gpio PI5 */
                 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
                 power-gpios = <&gpio 70 0>; /* gpio PI6 */
                 bus-width = <4>;
@@ -531,6 +531,19 @@
                 bus-width = <8>;
         };
 
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+
         regulators {
                 compatible = "simple-bus";
                 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index ea57c0f6dcce..258cf945f515 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -510,6 +510,7 @@
 
         sdhci@c8000400 {
                 status = "okay";
+                cd-gpios = <&gpio 69 1>; /* gpio PI5 */
                 wp-gpios = <&gpio 173 0>; /* gpio PV5 */
                 bus-width = <8>;
         };
@@ -519,6 +520,19 @@
                 bus-width = <8>;
         };
 
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+
         kbc {
                 status = "okay";
                 nvidia,debounce-delay-ms = <20>;
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 3d3f64d2111a..fc7febc2b386 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -145,6 +145,7 @@
                               0 1 0x04
                               0 41 0x04
                               0 42 0x04>;
+                clocks = <&tegra_car 5>;
         };
 
         tegra_car: clock {
@@ -304,6 +305,7 @@
                 compatible = "nvidia,tegra20-rtc";
                 reg = <0x7000e000 0x100>;
                 interrupts = <0 2 0x04>;
+                clocks = <&tegra_car 4>;
         };
 
         i2c@7000c000 {
@@ -416,6 +418,8 @@
         pmc {
                 compatible = "nvidia,tegra20-pmc";
                 reg = <0x7000e400 0x400>;
+                clocks = <&tegra_car 110>, <&clk32k_in>;
+                clock-names = "pclk", "clk32k_in";
         };
 
         memory-controller@7000f000 {
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index 8ff2ff20e4a3..6248b2445b32 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -257,7 +257,7 @@
 
         sdhci@78000000 {
                 status = "okay";
-                cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+                cd-gpios = <&gpio 69 1>; /* gpio PI5 */
                 wp-gpios = <&gpio 155 0>; /* gpio PT3 */
                 power-gpios = <&gpio 31 0>; /* gpio PD7 */
                 bus-width = <4>;
@@ -268,6 +268,19 @@
                 bus-width = <8>;
         };
 
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+
         regulators {
                 compatible = "simple-bus";
                 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index 17499272a4ef..65bf2b63174e 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -311,7 +311,7 @@
 
         sdhci@78000000 {
                 status = "okay";
-                cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+                cd-gpios = <&gpio 69 1>; /* gpio PI5 */
                 wp-gpios = <&gpio 155 0>; /* gpio PT3 */
                 power-gpios = <&gpio 31 0>; /* gpio PD7 */
                 bus-width = <4>;
@@ -322,6 +322,19 @@
                 bus-width = <8>;
         };
 
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+
         regulators {
                 compatible = "simple-bus";
                 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index dbf46c272562..9fe7a92b4c85 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -148,6 +148,7 @@
                               0 42 0x04
                               0 121 0x04
                               0 122 0x04>;
+                clocks = <&tegra_car 5>;
         };
 
         tegra_car: clock {
@@ -291,6 +292,7 @@
                 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
                 reg = <0x7000e000 0x100>;
                 interrupts = <0 2 0x04>;
+                clocks = <&tegra_car 4>;
         };
 
         i2c@7000c000 {
@@ -423,8 +425,10 @@
         };
 
         pmc {
-                compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
+                compatible = "nvidia,tegra30-pmc";
                 reg = <0x7000e400 0x400>;
+                clocks = <&tegra_car 218>, <&clk32k_in>;
+                clock-names = "pclk", "clk32k_in";
         };
 
         memory-controller {
diff --git a/arch/arm/boot/dts/versatile-ab.dts b/arch/arm/boot/dts/versatile-ab.dts
index e2fe3195c0d1..dde75ae8b4b1 100644
--- a/arch/arm/boot/dts/versatile-ab.dts
+++ b/arch/arm/boot/dts/versatile-ab.dts
@@ -121,6 +121,18 @@
                         interrupts = <0>;
                 };
 
+                timer@101e2000 {
+                        compatible = "arm,sp804", "arm,primecell";
+                        reg = <0x101e2000 0x1000>;
+                        interrupts = <4>;
+                };
+
+                timer@101e3000 {
+                        compatible = "arm,sp804", "arm,primecell";
+                        reg = <0x101e3000 0x1000>;
+                        interrupts = <5>;
+                };
+
                 gpio0: gpio@101e4000 {
                         compatible = "arm,pl061", "arm,primecell";
                         reg = <0x101e4000 0x1000>;
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
index 1420bb14d95c..62d9b225dcce 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca9.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
@@ -98,6 +98,7 @@
                              <0 49 4>;
                 clocks = <&oscclk2>, <&oscclk2>;
                 clock-names = "timclk", "apb_pclk";
+                status = "disabled";
         };
 
         watchdog@100e5000 {
diff --git a/arch/arm/common/timer-sp.c b/arch/arm/common/timer-sp.c
index 9d2d3ba339ff..ddc740769601 100644
--- a/arch/arm/common/timer-sp.c
+++ b/arch/arm/common/timer-sp.c
@@ -25,33 +25,29 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 
 #include <asm/sched_clock.h>
 #include <asm/hardware/arm_timer.h>
+#include <asm/hardware/timer-sp.h>
 
-static long __init sp804_get_clock_rate(const char *name)
+static long __init sp804_get_clock_rate(struct clk *clk)
 {
-        struct clk *clk;
         long rate;
         int err;
 
-        clk = clk_get_sys("sp804", name);
-        if (IS_ERR(clk)) {
-                pr_err("sp804: %s clock not found: %d\n", name,
-                        (int)PTR_ERR(clk));
-                return PTR_ERR(clk);
-        }
-
         err = clk_prepare(clk);
         if (err) {
-                pr_err("sp804: %s clock failed to prepare: %d\n", name, err);
+                pr_err("sp804: clock failed to prepare: %d\n", err);
                 clk_put(clk);
                 return err;
         }
 
         err = clk_enable(clk);
         if (err) {
-                pr_err("sp804: %s clock failed to enable: %d\n", name, err);
+                pr_err("sp804: clock failed to enable: %d\n", err);
                 clk_unprepare(clk);
                 clk_put(clk);
                 return err;
@@ -59,7 +55,7 @@ static long __init sp804_get_clock_rate(const char *name)
 
         rate = clk_get_rate(clk);
         if (rate < 0) {
-                pr_err("sp804: %s clock failed to get rate: %ld\n", name, rate);
+                pr_err("sp804: clock failed to get rate: %ld\n", rate);
                 clk_disable(clk);
                 clk_unprepare(clk);
                 clk_put(clk);
@@ -77,9 +73,21 @@ static u32 sp804_read(void)
 
 void __init __sp804_clocksource_and_sched_clock_init(void __iomem *base,
                                                      const char *name,
+                                                     struct clk *clk,
                                                      int use_sched_clock)
 {
-        long rate = sp804_get_clock_rate(name);
+        long rate;
+
+        if (!clk) {
+                clk = clk_get_sys("sp804", name);
+                if (IS_ERR(clk)) {
+                        pr_err("sp804: clock not found: %d\n",
+                               (int)PTR_ERR(clk));
+                        return;
+                }
+        }
+
+        rate = sp804_get_clock_rate(clk);
 
         if (rate < 0)
                 return;
@@ -171,12 +179,20 @@ static struct irqaction sp804_timer_irq = {
         .dev_id         = &sp804_clockevent,
 };
 
-void __init sp804_clockevents_init(void __iomem *base, unsigned int irq,
-        const char *name)
+void __init __sp804_clockevents_init(void __iomem *base, unsigned int irq, struct clk *clk, const char *name)
 {
         struct clock_event_device *evt = &sp804_clockevent;
-        long rate = sp804_get_clock_rate(name);
+        long rate;
 
+        if (!clk)
+                clk = clk_get_sys("sp804", name);
+        if (IS_ERR(clk)) {
+                pr_err("sp804: %s clock not found: %d\n", name,
+                        (int)PTR_ERR(clk));
+                return;
+        }
+
+        rate = sp804_get_clock_rate(clk);
         if (rate < 0)
                 return;
 
@@ -186,6 +202,98 @@ void __init sp804_clockevents_init(void __iomem *base, unsigned int irq,
         evt->irq = irq;
         evt->cpumask = cpu_possible_mask;
 
+        writel(0, base + TIMER_CTRL);
+
         setup_irq(irq, &sp804_timer_irq);
         clockevents_config_and_register(evt, rate, 0xf, 0xffffffff);
 }
+
+static void __init sp804_of_init(struct device_node *np)
+{
+        static bool initialized = false;
+        void __iomem *base;
+        int irq;
+        u32 irq_num = 0;
+        struct clk *clk1, *clk2;
+        const char *name = of_get_property(np, "compatible", NULL);
+
+        base = of_iomap(np, 0);
+        if (WARN_ON(!base))
+                return;
+
+        /* Ensure timers are disabled */
+        writel(0, base + TIMER_CTRL);
+        writel(0, base + TIMER_2_BASE + TIMER_CTRL);
+
+        if (initialized || !of_device_is_available(np))
+                goto err;
+
+        clk1 = of_clk_get(np, 0);
+        if (IS_ERR(clk1))
+                clk1 = NULL;
+
+        /* Get the 2nd clock if the timer has 2 timer clocks */
+        if (of_count_phandle_with_args(np, "clocks", "#clock-cells") == 3) {
+                clk2 = of_clk_get(np, 1);
+                if (IS_ERR(clk2)) {
+                        pr_err("sp804: %s clock not found: %d\n", np->name,
+                                (int)PTR_ERR(clk2));
+                        goto err;
+                }
+        } else
+                clk2 = clk1;
+
+        irq = irq_of_parse_and_map(np, 0);
+        if (irq <= 0)
+                goto err;
+
+        of_property_read_u32(np, "arm,sp804-has-irq", &irq_num);
+        if (irq_num == 2) {
+                __sp804_clockevents_init(base + TIMER_2_BASE, irq, clk2, name);
+                __sp804_clocksource_and_sched_clock_init(base, name, clk1, 1);
+        } else {
+                __sp804_clockevents_init(base, irq, clk1 , name);
+                __sp804_clocksource_and_sched_clock_init(base + TIMER_2_BASE,
+                                                         name, clk2, 1);
+        }
+        initialized = true;
+
+        return;
+err:
+        iounmap(base);
+}
+CLOCKSOURCE_OF_DECLARE(sp804, "arm,sp804", sp804_of_init);
+
+static void __init integrator_cp_of_init(struct device_node *np)
+{
+        static int init_count = 0;
+        void __iomem *base;
+        int irq;
+        const char *name = of_get_property(np, "compatible", NULL);
+
+        base = of_iomap(np, 0);
+        if (WARN_ON(!base))
+                return;
+
+        /* Ensure timer is disabled */
+        writel(0, base + TIMER_CTRL);
+
+        if (init_count == 2 || !of_device_is_available(np))
+                goto err;
+
+        if (!init_count)
+                sp804_clocksource_init(base, name);
+        else {
+                irq = irq_of_parse_and_map(np, 0);
+                if (irq <= 0)
+                        goto err;
+
+                sp804_clockevents_init(base, irq, name);
+        }
+
+        init_count++;
+        return;
+err:
+        iounmap(base);
+}
+CLOCKSOURCE_OF_DECLARE(intcp, "arm,integrator-cp-timer", integrator_cp_of_init);
diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig
index 1ea959019fcd..047f2a415309 100644
--- a/arch/arm/configs/at91_dt_defconfig
+++ b/arch/arm/configs/at91_dt_defconfig
@@ -20,7 +20,7 @@ CONFIG_SOC_AT91SAM9263=y
 CONFIG_SOC_AT91SAM9G45=y
 CONFIG_SOC_AT91SAM9X5=y
 CONFIG_SOC_AT91SAM9N12=y
-CONFIG_MACH_AT91SAM_DT=y
+CONFIG_MACH_AT91SAM9_DT=y
 CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
 CONFIG_AT91_TIMER_HZ=128
 CONFIG_AEABI=y
diff --git a/arch/arm/configs/at91sam9260_defconfig b/arch/arm/configs/at91sam9260_defconfig
index 0ea5d2c97fc4..05618eb694f8 100644
--- a/arch/arm/configs/at91sam9260_defconfig
+++ b/arch/arm/configs/at91sam9260_defconfig
@@ -22,7 +22,7 @@ CONFIG_MACH_QIL_A9260=y
 CONFIG_MACH_CPU9260=y
 CONFIG_MACH_FLEXIBITY=y
 CONFIG_MACH_SNAPPER_9260=y
-CONFIG_MACH_AT91SAM_DT=y
+CONFIG_MACH_AT91SAM9_DT=y
 CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_ZBOOT_ROM_TEXT=0x0
diff --git a/arch/arm/configs/at91sam9g20_defconfig b/arch/arm/configs/at91sam9g20_defconfig
index 3b1881033ad8..892e8287ed73 100644
--- a/arch/arm/configs/at91sam9g20_defconfig
+++ b/arch/arm/configs/at91sam9g20_defconfig
@@ -22,7 +22,7 @@ CONFIG_MACH_PCONTROL_G20=y
 CONFIG_MACH_GSIA18S=y
 CONFIG_MACH_USB_A9G20=y
 CONFIG_MACH_SNAPPER_9260=y
-CONFIG_MACH_AT91SAM_DT=y
+CONFIG_MACH_AT91SAM9_DT=y
 CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_AEABI=y
diff --git a/arch/arm/configs/at91sam9g45_defconfig b/arch/arm/configs/at91sam9g45_defconfig
index 606d48f3b8f8..5f551b76cb65 100644
--- a/arch/arm/configs/at91sam9g45_defconfig
+++ b/arch/arm/configs/at91sam9g45_defconfig
@@ -18,7 +18,7 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91SAM9G45=y
 CONFIG_MACH_AT91SAM9M10G45EK=y
-CONFIG_MACH_AT91SAM_DT=y
+CONFIG_MACH_AT91SAM9_DT=y
 CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
 CONFIG_AT91_SLOW_CLOCK=y
 CONFIG_AEABI=y
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index e31d442343c8..3bf0c543216a 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -10,6 +10,10 @@ CONFIG_ARCH_SUNXI=y
 # CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA is not set
 CONFIG_ARCH_ZYNQ=y
 CONFIG_ARM_ERRATA_754322=y
+CONFIG_PLAT_SPEAR=y
+CONFIG_ARCH_SPEAR13XX=y
+CONFIG_MACH_SPEAR1310=y
+CONFIG_MACH_SPEAR1340=y
 CONFIG_SMP=y
 CONFIG_ARM_ARCH_TIMER=y
 CONFIG_AEABI=y
@@ -23,6 +27,7 @@ CONFIG_BLK_DEV_SD=y
 CONFIG_ATA=y
 CONFIG_SATA_HIGHBANK=y
 CONFIG_SATA_MV=y
+CONFIG_SATA_AHCI_PLATFORM=y
 CONFIG_NETDEVICES=y
 CONFIG_NET_CALXEDA_XGMAC=y
 CONFIG_SMSC911X=y
@@ -31,6 +36,7 @@ CONFIG_SERIO_AMBAKMI=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_8250_DW=y
+CONFIG_KEYBOARD_SPEAR=y
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
 CONFIG_SERIAL_OF_PLATFORM=y
@@ -40,6 +46,7 @@ CONFIG_I2C=y
 CONFIG_I2C_DESIGNWARE_PLATFORM=y
 CONFIG_SPI=y
 CONFIG_SPI_PL022=y
+CONFIG_GPIO_PL061=y
 CONFIG_FB=y
 CONFIG_FB_ARMCLCD=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
@@ -50,6 +57,7 @@ CONFIG_MMC=y
 CONFIG_MMC_ARMMMCI=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_SPEAR=y
 CONFIG_EDAC=y
 CONFIG_EDAC_MM_EDAC=y
 CONFIG_EDAC_HIGHBANK_MC=y
@@ -58,3 +66,4 @@ CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_PL031=y
 CONFIG_DMADEVICES=y
 CONFIG_PL330_DMA=y
+CONFIG_DW_DMAC=y
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index bd07864f14a0..33903ca0d879 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -93,6 +93,7 @@ CONFIG_BLK_DEV_RAM_SIZE=16384
 CONFIG_SENSORS_LIS3LV02D=m
 CONFIG_SENSORS_TSL2550=m
 CONFIG_SENSORS_LIS3_I2C=m
+CONFIG_BMP085_I2C=m
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_SCSI_MULTI_LUN=y
diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig
new file mode 100644
index 000000000000..4d0dc3c16063
--- /dev/null
+++ b/arch/arm/configs/sama5_defconfig
@@ -0,0 +1,181 @@
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_IRQ_DOMAIN_DEBUG=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_ARCH_AT91=y
+CONFIG_SOC_SAM_V7=y
+CONFIG_SOC_SAMA5D3=y
+CONFIG_MACH_SAMA5_DT=y
+CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_UACCESS_WITH_MEMCPY=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw"
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_VFP=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_PM_DEBUG=y
+CONFIG_PM_ADVANCED_DEBUG=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+CONFIG_IPV6=y
+# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET6_XFRM_MODE_BEET is not set
+CONFIG_IPV6_SIT_6RD=y
+CONFIG_CAN=y
+CONFIG_CAN_AT91=y
+CONFIG_CFG80211=y
+CONFIG_MAC80211=y
+CONFIG_MAC80211_LEDS=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_STANDALONE is not set
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_ATMEL=y
+CONFIG_MTD_UBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=4
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_ATMEL_TCLIB=y
+CONFIG_ATMEL_SSC=y
+CONFIG_EEPROM_AT24=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_NETDEVICES=y
+CONFIG_MII=y
+CONFIG_MACB=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_MICREL_PHY=y
+# CONFIG_WLAN is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_QT1070=y
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ATMEL_MXT=y
+CONFIG_TOUCHSCREEN_ATMEL_TSADCC=y
+# CONFIG_SERIO is not set
+CONFIG_LEGACY_PTY_COUNT=4
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+CONFIG_HW_RANDOM=y
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_AT91=y
+CONFIG_I2C_GPIO=y
+CONFIG_SPI=y
+CONFIG_SPI_ATMEL=y
+CONFIG_SPI_GPIO=y
+CONFIG_GPIO_SYSFS=y
+# CONFIG_HWMON is not set
+CONFIG_SSB=m
+CONFIG_FB=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_GENERIC is not set
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_HID_GENERIC is not set
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_ACM=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_AT91=y
+CONFIG_USB_MASS_STORAGE=m
+CONFIG_MMC=y
+# CONFIG_MMC_BLOCK_BOUNCE is not set
+CONFIG_MMC_ATMELMCI=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_AT91RM9200=y
+CONFIG_DMADEVICES=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_IIO=y
+CONFIG_AT91_ADC=y
+CONFIG_EXT2_FS=y
+CONFIG_FANOTIFY=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_UBIFS_FS=y
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_DEBUG_FS=y
+# CONFIG_SCHED_DEBUG is not set
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_FTRACE is not set
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_LL=y
+CONFIG_EARLY_PRINTK=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_USER_API_HASH=m
+CONFIG_CRYPTO_USER_API_SKCIPHER=m
+CONFIG_CRYPTO_DEV_ATMEL_AES=y
+CONFIG_CRYPTO_DEV_ATMEL_TDES=y
+CONFIG_CRYPTO_DEV_ATMEL_SHA=y
+CONFIG_CRC_CCITT=m
+CONFIG_CRC_ITU_T=m
diff --git a/arch/arm/configs/spear3xx_defconfig b/arch/arm/configs/spear3xx_defconfig
index 865980c5f212..7ff23a077f5d 100644
--- a/arch/arm/configs/spear3xx_defconfig
+++ b/arch/arm/configs/spear3xx_defconfig
@@ -6,7 +6,9 @@ CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ARCH_MULTI_V7 is not set
 CONFIG_PLAT_SPEAR=y
+CONFIG_ARCH_SPEAR3XX=y
 CONFIG_MACH_SPEAR300=y
 CONFIG_MACH_SPEAR310=y
 CONFIG_MACH_SPEAR320=y
diff --git a/arch/arm/configs/spear6xx_defconfig b/arch/arm/configs/spear6xx_defconfig
index a2a1265f86b6..7822980d7d55 100644
--- a/arch/arm/configs/spear6xx_defconfig
+++ b/arch/arm/configs/spear6xx_defconfig
@@ -6,6 +6,7 @@ CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ARCH_MULTI_V7 is not set
 CONFIG_PLAT_SPEAR=y
 CONFIG_ARCH_SPEAR6XX=y
 CONFIG_BINFMT_MISC=y
diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h
index 7ade91d8cc6f..7c1bfc0aea0c 100644
--- a/arch/arm/include/asm/arch_timer.h
+++ b/arch/arm/include/asm/arch_timer.h
@@ -10,8 +10,7 @@
 #include <clocksource/arm_arch_timer.h>
 
 #ifdef CONFIG_ARM_ARCH_TIMER
-int arch_timer_of_register(void);
-int arch_timer_sched_clock_init(void);
+int arch_timer_arch_init(void);
 
 /*
  * These register accessors are marked inline so the compiler can
@@ -110,16 +109,6 @@ static inline void __cpuinit arch_counter_set_user_access(void)
 
         asm volatile("mcr p15, 0, %0, c14, c1, 0" : : "r" (cntkctl));
 }
-#else
-static inline int arch_timer_of_register(void)
-{
-        return -ENXIO;
-}
-
-static inline int arch_timer_sched_clock_init(void)
-{
-        return -ENXIO;
-}
 #endif
 
 #endif
diff --git a/arch/arm/include/asm/delay.h b/arch/arm/include/asm/delay.h
index 720799fd3a81..dff714d886d5 100644
--- a/arch/arm/include/asm/delay.h
+++ b/arch/arm/include/asm/delay.h
@@ -24,7 +24,7 @@ extern struct arm_delay_ops {
         void (*delay)(unsigned long);
         void (*const_udelay)(unsigned long);
         void (*udelay)(unsigned long);
-        bool const_clock;
+        unsigned long ticks_per_jiffy;
 } arm_delay_ops;
 
 #define __delay(n)              arm_delay_ops.delay(n)
diff --git a/arch/arm/include/asm/hardware/timer-sp.h b/arch/arm/include/asm/hardware/timer-sp.h
index 2dd9d3f83f29..bb28af7c32de 100644
--- a/arch/arm/include/asm/hardware/timer-sp.h
+++ b/arch/arm/include/asm/hardware/timer-sp.h
@@ -1,15 +1,23 @@
+struct clk;
+
 void __sp804_clocksource_and_sched_clock_init(void __iomem *,
-                                              const char *, int);
+                                              const char *, struct clk *, int);
+void __sp804_clockevents_init(void __iomem *, unsigned int,
+                              struct clk *, const char *);
 
 static inline void sp804_clocksource_init(void __iomem *base, const char *name)
 {
-        __sp804_clocksource_and_sched_clock_init(base, name, 0);
+        __sp804_clocksource_and_sched_clock_init(base, name, NULL, 0);
 }
 
 static inline void sp804_clocksource_and_sched_clock_init(void __iomem *base,
                                                           const char *name)
 {
-        __sp804_clocksource_and_sched_clock_init(base, name, 1);
+        __sp804_clocksource_and_sched_clock_init(base, name, NULL, 1);
 }
 
-void sp804_clockevents_init(void __iomem *, unsigned int, const char *);
+static inline void sp804_clockevents_init(void __iomem *base, unsigned int irq, const char *name)
+{
+        __sp804_clockevents_init(base, irq, NULL, name);
+
+}
diff --git a/arch/arm/include/asm/highmem.h b/arch/arm/include/asm/highmem.h
index 8c5e828f484d..91b99abe7a95 100644
--- a/arch/arm/include/asm/highmem.h
+++ b/arch/arm/include/asm/highmem.h
@@ -41,6 +41,13 @@ extern void kunmap_high(struct page *page);
 #endif
 #endif
 
+/*
+ * Needed to be able to broadcast the TLB invalidation for kmap.
+ */
+#ifdef CONFIG_ARM_ERRATA_798181
+#undef ARCH_NEEDS_KMAP_HIGH_GET
+#endif
+
 #ifdef ARCH_NEEDS_KMAP_HIGH_GET
 extern void *kmap_high_get(struct page *page);
 #else
diff --git a/arch/arm/include/asm/mmu_context.h b/arch/arm/include/asm/mmu_context.h
index 863a6611323c..a7b85e0d0cc1 100644
--- a/arch/arm/include/asm/mmu_context.h
+++ b/arch/arm/include/asm/mmu_context.h
@@ -27,6 +27,8 @@ void __check_vmalloc_seq(struct mm_struct *mm);
 void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk);
 #define init_new_context(tsk,mm)        ({ atomic64_set(&mm->context.id, 0); 0; })
 
+DECLARE_PER_CPU(atomic64_t, active_asids);
+
 #else   /* !CONFIG_CPU_HAS_ASID */
 
 #ifdef CONFIG_MMU
diff --git a/arch/arm/include/asm/sched_clock.h b/arch/arm/include/asm/sched_clock.h
index e3f757263438..3d520ddca61b 100644
--- a/arch/arm/include/asm/sched_clock.h
+++ b/arch/arm/include/asm/sched_clock.h
@@ -11,4 +11,6 @@
 extern void sched_clock_postinit(void);
 extern void setup_sched_clock(u32 (*read)(void), int bits, unsigned long rate);
 
+extern unsigned long long (*sched_clock_func)(void);
+
 #endif
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index 4db8c8820f0d..9e9c041358ca 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -450,6 +450,21 @@ static inline void local_flush_bp_all(void)
                 isb();
 }
 
+#ifdef CONFIG_ARM_ERRATA_798181
+static inline void dummy_flush_tlb_a15_erratum(void)
+{
+        /*
+         * Dummy TLBIMVAIS. Using the unmapped address 0 and ASID 0.
+         */
+        asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (0));
+        dsb();
+}
+#else
+static inline void dummy_flush_tlb_a15_erratum(void)
+{
+}
+#endif
+
 /*
  *      flush_pmd_entry
  *
diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c
index d957a51435d8..59dcdced6e30 100644
--- a/arch/arm/kernel/arch_timer.c
+++ b/arch/arm/kernel/arch_timer.c
@@ -22,9 +22,11 @@ static unsigned long arch_timer_read_counter_long(void)
         return arch_timer_read_counter();
 }
 
-static u32 arch_timer_read_counter_u32(void)
+static u32 sched_clock_mult __read_mostly;
+
+static unsigned long long notrace arch_timer_sched_clock(void)
 {
-        return arch_timer_read_counter();
+        return arch_timer_read_counter() * sched_clock_mult;
 }
 
 static struct delay_timer arch_delay_timer;
@@ -37,25 +39,20 @@ static void __init arch_timer_delay_timer_register(void)
         register_current_timer_delay(&arch_delay_timer);
 }
 
-int __init arch_timer_of_register(void)
+int __init arch_timer_arch_init(void)
 {
-        int ret;
+        u32 arch_timer_rate = arch_timer_get_rate();
 
-        ret = arch_timer_init();
-        if (ret)
-                return ret;
+        if (arch_timer_rate == 0)
+                return -ENXIO;
 
         arch_timer_delay_timer_register();
 
-        return 0;
-}
-
-int __init arch_timer_sched_clock_init(void)
-{
-        if (arch_timer_get_rate() == 0)
-                return -ENXIO;
+        /* Cache the sched_clock multiplier to save a divide in the hot path. */
+        sched_clock_mult = NSEC_PER_SEC / arch_timer_rate;
+        sched_clock_func = arch_timer_sched_clock;
+        pr_info("sched_clock: ARM arch timer >56 bits at %ukHz, resolution %uns\n",
+                arch_timer_rate / 1000, sched_clock_mult);
 
-        setup_sched_clock(arch_timer_read_counter_u32,
-                          32, arch_timer_get_rate());
         return 0;
 }
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 3248cde504ed..fefd7f971437 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -276,7 +276,13 @@ ENDPROC(ftrace_graph_caller_old)
  */
 
 .macro mcount_enter
+/*
+ * This pad compensates for the push {lr} at the call site.  Note that we are
+ * unable to unwind through a function which does not otherwise save its lr.
+ */
+ UNWIND(.pad    #4)
         stmdb   sp!, {r0-r3, lr}
+ UNWIND(.save   {r0-r3, lr})
 .endm
 
 .macro mcount_get_lr reg
@@ -289,6 +295,7 @@ ENDPROC(ftrace_graph_caller_old)
 .endm
 
 ENTRY(__gnu_mcount_nc)
+UNWIND(.fnstart)
 #ifdef CONFIG_DYNAMIC_FTRACE
         mov     ip, lr
         ldmia   sp!, {lr}
@@ -296,17 +303,22 @@ ENTRY(__gnu_mcount_nc)
 #else
         __mcount
 #endif
+UNWIND(.fnend)
 ENDPROC(__gnu_mcount_nc)
 
 #ifdef CONFIG_DYNAMIC_FTRACE
 ENTRY(ftrace_caller)
+UNWIND(.fnstart)
         __ftrace_caller
+UNWIND(.fnend)
 ENDPROC(ftrace_caller)
 #endif
 
 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
 ENTRY(ftrace_graph_caller)
+UNWIND(.fnstart)
         __ftrace_graph_caller
+UNWIND(.fnend)
 ENDPROC(ftrace_graph_caller)
 #endif
 
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index e0eb9a1cae77..8bac553fe213 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -267,7 +267,7 @@ __create_page_tables:
         addne   r6, r6, #1 << SECTION_SHIFT
         strne   r6, [r3]
 
-#if defined(CONFIG_LPAE) && defined(CONFIG_CPU_ENDIAN_BE8)
+#if defined(CONFIG_ARM_LPAE) && defined(CONFIG_CPU_ENDIAN_BE8)
         sub     r4, r4, #4                      @ Fixup page table pointer
                                                 @ for 64-bit descriptors
 #endif
diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
index 96093b75ab90..5dc1aa6f0f7d 100644
--- a/arch/arm/kernel/hw_breakpoint.c
+++ b/arch/arm/kernel/hw_breakpoint.c
@@ -966,7 +966,7 @@ static void reset_ctrl_regs(void *unused)
         }
 
         if (err) {
-                pr_warning("CPU %d debug is powered down!\n", cpu);
+                pr_warn_once("CPU %d debug is powered down!\n", cpu);
                 cpumask_or(&debug_err_mask, &debug_err_mask, cpumask_of(cpu));
                 return;
         }
@@ -987,7 +987,7 @@ clear_vcr:
         isb();
 
         if (cpumask_intersects(&debug_err_mask, cpumask_of(cpu))) {
-                pr_warning("CPU %d failed to disable vector catch\n", cpu);
+                pr_warn_once("CPU %d failed to disable vector catch\n", cpu);
                 return;
         }
 
@@ -1007,7 +1007,7 @@ clear_vcr:
         }
 
         if (cpumask_intersects(&debug_err_mask, cpumask_of(cpu))) {
-                pr_warning("CPU %d failed to clear debug register pairs\n", cpu);
+                pr_warn_once("CPU %d failed to clear debug register pairs\n", cpu);
                 return;
         }
 
diff --git a/arch/arm/kernel/sched_clock.c b/arch/arm/kernel/sched_clock.c
index bd6f56b9ec21..880584852fca 100644
--- a/arch/arm/kernel/sched_clock.c
+++ b/arch/arm/kernel/sched_clock.c
@@ -20,6 +20,7 @@ struct clock_data {
         u64 epoch_ns;
         u32 epoch_cyc;
         u32 epoch_cyc_copy;
+        unsigned long rate;
         u32 mult;
         u32 shift;
         bool suspended;
@@ -113,11 +114,14 @@ void __init setup_sched_clock(u32 (*read)(void), int bits, unsigned long rate)
         u64 res, wrap;
         char r_unit;
 
+        if (cd.rate > rate)
+                return;
+
         BUG_ON(bits > 32);
         WARN_ON(!irqs_disabled());
-        WARN_ON(read_sched_clock != jiffy_sched_clock_read);
         read_sched_clock = read;
         sched_clock_mask = (1 << bits) - 1;
+        cd.rate = rate;
 
         /* calculate the mult/shift to convert counter ticks to ns. */
         clocks_calc_mult_shift(&cd.mult, &cd.shift, rate, NSEC_PER_SEC, 0);
@@ -161,12 +165,19 @@ void __init setup_sched_clock(u32 (*read)(void), int bits, unsigned long rate)
         pr_debug("Registered %pF as sched_clock source\n", read);
 }
 
-unsigned long long notrace sched_clock(void)
+static unsigned long long notrace sched_clock_32(void)
 {
         u32 cyc = read_sched_clock();
         return cyc_to_sched_clock(cyc, sched_clock_mask);
 }
 
+unsigned long long __read_mostly (*sched_clock_func)(void) = sched_clock_32;
+
+unsigned long long notrace sched_clock(void)
+{
+        return sched_clock_func();
+}
+
 void __init sched_clock_postinit(void)
 {
         /*
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 3f6cbb2e3eda..d343a6c3a6d1 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -353,6 +353,23 @@ void __init early_print(const char *str, ...)
         printk("%s", buf);
 }
 
+static void __init cpuid_init_hwcaps(void)
+{
+        unsigned int divide_instrs;
+
+        if (cpu_architecture() < CPU_ARCH_ARMv7)
+                return;
+
+        divide_instrs = (read_cpuid_ext(CPUID_EXT_ISAR0) & 0x0f000000) >> 24;
+
+        switch (divide_instrs) {
+        case 2:
+                elf_hwcap |= HWCAP_IDIVA;
+        case 1:
+                elf_hwcap |= HWCAP_IDIVT;
+        }
+}
+
 static void __init feat_v6_fixup(void)
 {
         int id = read_cpuid_id();
@@ -483,8 +500,11 @@ static void __init setup_processor(void)
         snprintf(elf_platform, ELF_PLATFORM_SIZE, "%s%c",
                  list->elf_name, ENDIANNESS);
         elf_hwcap = list->elf_hwcap;
+
+        cpuid_init_hwcaps();
+
 #ifndef CONFIG_ARM_THUMB
-        elf_hwcap &= ~HWCAP_THUMB;
+        elf_hwcap &= ~(HWCAP_THUMB | HWCAP_IDIVT);
 #endif
 
         feat_v6_fixup();
@@ -524,7 +544,7 @@ int __init arm_add_memory(phys_addr_t start, phys_addr_t size)
         size -= start & ~PAGE_MASK;
         bank->start = PAGE_ALIGN(start);
 
-#ifndef CONFIG_LPAE
+#ifndef CONFIG_ARM_LPAE
         if (bank->start + size < bank->start) {
                 printk(KERN_CRIT "Truncating memory at 0x%08llx to fit in "
                         "32-bit physical address space\n", (long long)start);
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 79078edbb9bc..1f2ccccaf009 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -673,9 +673,6 @@ static int cpufreq_callback(struct notifier_block *nb,
         if (freq->flags & CPUFREQ_CONST_LOOPS)
                 return NOTIFY_OK;
 
-        if (arm_delay_ops.const_clock)
-                return NOTIFY_OK;
-
         if (!per_cpu(l_p_j_ref, cpu)) {
                 per_cpu(l_p_j_ref, cpu) =
                         per_cpu(cpu_data, cpu).loops_per_jiffy;
diff --git a/arch/arm/kernel/smp_tlb.c b/arch/arm/kernel/smp_tlb.c
index bd0300531399..e82e1d248772 100644
--- a/arch/arm/kernel/smp_tlb.c
+++ b/arch/arm/kernel/smp_tlb.c
@@ -12,6 +12,7 @@
 
 #include <asm/smp_plat.h>
 #include <asm/tlbflush.h>
+#include <asm/mmu_context.h>
 
 /**********************************************************************/
 
@@ -69,12 +70,72 @@ static inline void ipi_flush_bp_all(void *ignored)
         local_flush_bp_all();
 }
 
+#ifdef CONFIG_ARM_ERRATA_798181
+static int erratum_a15_798181(void)
+{
+        unsigned int midr = read_cpuid_id();
+
+        /* Cortex-A15 r0p0..r3p2 affected */
+        if ((midr & 0xff0ffff0) != 0x410fc0f0 || midr > 0x413fc0f2)
+                return 0;
+        return 1;
+}
+#else
+static int erratum_a15_798181(void)
+{
+        return 0;
+}
+#endif
+
+static void ipi_flush_tlb_a15_erratum(void *arg)
+{
+        dmb();
+}
+
+static void broadcast_tlb_a15_erratum(void)
+{
+        if (!erratum_a15_798181())
+                return;
+
+        dummy_flush_tlb_a15_erratum();
+        smp_call_function_many(cpu_online_mask, ipi_flush_tlb_a15_erratum,
+                               NULL, 1);
+}
+
+static void broadcast_tlb_mm_a15_erratum(struct mm_struct *mm)
+{
+        int cpu;
+        cpumask_t mask = { CPU_BITS_NONE };
+
+        if (!erratum_a15_798181())
+                return;
+
+        dummy_flush_tlb_a15_erratum();
+        for_each_online_cpu(cpu) {
+                if (cpu == smp_processor_id())
+                        continue;
+                /*
+                 * We only need to send an IPI if the other CPUs are running
+                 * the same ASID as the one being invalidated. There is no
+                 * need for locking around the active_asids check since the
+                 * switch_mm() function has at least one dmb() (as required by
+                 * this workaround) in case a context switch happens on
+                 * another CPU after the condition below.
+                 */
+                if (atomic64_read(&mm->context.id) ==
+                    atomic64_read(&per_cpu(active_asids, cpu)))
+                        cpumask_set_cpu(cpu, &mask);
+        }
+        smp_call_function_many(&mask, ipi_flush_tlb_a15_erratum, NULL, 1);
+}
+
 void flush_tlb_all(void)
 {
         if (tlb_ops_need_broadcast())
                 on_each_cpu(ipi_flush_tlb_all, NULL, 1);
         else
                 local_flush_tlb_all();
+        broadcast_tlb_a15_erratum();
 }
 
 void flush_tlb_mm(struct mm_struct *mm)
@@ -83,6 +144,7 @@ void flush_tlb_mm(struct mm_struct *mm)
                 on_each_cpu_mask(mm_cpumask(mm), ipi_flush_tlb_mm, mm, 1);
         else
                 local_flush_tlb_mm(mm);
+        broadcast_tlb_mm_a15_erratum(mm);
 }
 
 void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
@@ -95,6 +157,7 @@ void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
                                         &ta, 1);
         } else
                 local_flush_tlb_page(vma, uaddr);
+        broadcast_tlb_mm_a15_erratum(vma->vm_mm);
 }
 
 void flush_tlb_kernel_page(unsigned long kaddr)
@@ -105,6 +168,7 @@ void flush_tlb_kernel_page(unsigned long kaddr)
                 on_each_cpu(ipi_flush_tlb_kernel_page, &ta, 1);
         } else
                 local_flush_tlb_kernel_page(kaddr);
+        broadcast_tlb_a15_erratum();
 }
 
 void flush_tlb_range(struct vm_area_struct *vma,
@@ -119,6 +183,7 @@ void flush_tlb_range(struct vm_area_struct *vma,
                                         &ta, 1);
         } else
                 local_flush_tlb_range(vma, start, end);
+        broadcast_tlb_mm_a15_erratum(vma->vm_mm);
 }
 
 void flush_tlb_kernel_range(unsigned long start, unsigned long end)
@@ -130,6 +195,7 @@ void flush_tlb_kernel_range(unsigned long start, unsigned long end)
                 on_each_cpu(ipi_flush_tlb_kernel_range, &ta, 1);
         } else
                 local_flush_tlb_kernel_range(start, end);
+        broadcast_tlb_a15_erratum();
 }
 
 void flush_bp_all(void)
diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c
index 955d92d265e5..abff4e9aaee0 100644
--- a/arch/arm/kernel/time.c
+++ b/arch/arm/kernel/time.c
@@ -22,6 +22,7 @@
 #include <linux/errno.h>
 #include <linux/profile.h>
 #include <linux/timer.h>
+#include <linux/clocksource.h>
 #include <linux/irq.h>
 
 #include <asm/thread_info.h>
@@ -115,6 +116,10 @@ int __init register_persistent_clock(clock_access_fn read_boot,
 
 void __init time_init(void)
 {
-        machine_desc->init_time();
+        if (machine_desc->init_time)
+                machine_desc->init_time();
+        else
+                clocksource_of_init();
+
         sched_clock_postinit();
 }
diff --git a/arch/arm/kvm/vgic.c b/arch/arm/kvm/vgic.c
index c9a17316e9fe..0e4cfe123b38 100644
--- a/arch/arm/kvm/vgic.c
+++ b/arch/arm/kvm/vgic.c
@@ -883,8 +883,7 @@ static bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq)
                           lr, irq, vgic_cpu->vgic_lr[lr]);
                 BUG_ON(!test_bit(lr, vgic_cpu->lr_used));
                 vgic_cpu->vgic_lr[lr] |= GICH_LR_PENDING_BIT;
-
-                goto out;
+                return true;
         }
 
         /* Try to use another LR for this interrupt */
@@ -898,7 +897,6 @@ static bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq)
         vgic_cpu->vgic_irq_lr_map[irq] = lr;
         set_bit(lr, vgic_cpu->lr_used);
 
-out:
         if (!vgic_irq_is_edge(vcpu, irq))
                 vgic_cpu->vgic_lr[lr] |= GICH_LR_EOI;
 
@@ -1018,21 +1016,6 @@ static bool vgic_process_maintenance(struct kvm_vcpu *vcpu)
 
         kvm_debug("MISR = %08x\n", vgic_cpu->vgic_misr);
 
-        /*
-         * We do not need to take the distributor lock here, since the only
-         * action we perform is clearing the irq_active_bit for an EOIed
-         * level interrupt.  There is a potential race with
-         * the queuing of an interrupt in __kvm_vgic_flush_hwstate(), where we
-         * check if the interrupt is already active. Two possibilities:
-         *
-         * - The queuing is occurring on the same vcpu: cannot happen,
-         *   as we're already in the context of this vcpu, and
-         *   executing the handler
-         * - The interrupt has been migrated to another vcpu, and we
-         *   ignore this interrupt for this run. Big deal. It is still
-         *   pending though, and will get considered when this vcpu
-         *   exits.
-         */
         if (vgic_cpu->vgic_misr & GICH_MISR_EOI) {
                 /*
                  * Some level interrupts have been EOIed. Clear their
@@ -1054,6 +1037,13 @@ static bool vgic_process_maintenance(struct kvm_vcpu *vcpu)
                         } else {
                                 vgic_cpu_irq_clear(vcpu, irq);
                         }
+
+                        /*
+                         * Despite being EOIed, the LR may not have
+                         * been marked as empty.
+                         */
+                        set_bit(lr, (unsigned long *)vgic_cpu->vgic_elrsr);
+                        vgic_cpu->vgic_lr[lr] &= ~GICH_LR_ACTIVE_BIT;
                 }
         }
 
@@ -1064,9 +1054,8 @@ static bool vgic_process_maintenance(struct kvm_vcpu *vcpu)
 }
 
 /*
- * Sync back the VGIC state after a guest run. We do not really touch
- * the distributor here (the irq_pending_on_cpu bit is safe to set),
- * so there is no need for taking its lock.
+ * Sync back the VGIC state after a guest run. The distributor lock is
+ * needed so we don't get preempted in the middle of the state processing.
  */
 static void __kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
 {
@@ -1112,10 +1101,14 @@ void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu)
 
 void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
 {
+        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
+
         if (!irqchip_in_kernel(vcpu->kvm))
                 return;
 
+        spin_lock(&dist->lock);
         __kvm_vgic_sync_hwstate(vcpu);
+        spin_unlock(&dist->lock);
 }
 
 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
diff --git a/arch/arm/lib/delay.c b/arch/arm/lib/delay.c
index 6b93f6a1a3c7..64dbfa57204a 100644
--- a/arch/arm/lib/delay.c
+++ b/arch/arm/lib/delay.c
@@ -58,7 +58,7 @@ static void __timer_delay(unsigned long cycles)
 static void __timer_const_udelay(unsigned long xloops)
 {
         unsigned long long loops = xloops;
-        loops *= loops_per_jiffy;
+        loops *= arm_delay_ops.ticks_per_jiffy;
         __timer_delay(loops >> UDELAY_SHIFT);
 }
 
@@ -73,11 +73,13 @@ void __init register_current_timer_delay(const struct delay_timer *timer)
                 pr_info("Switching to timer-based delay loop\n");
                 delay_timer                     = timer;
                 lpj_fine                        = timer->freq / HZ;
-                loops_per_jiffy                 = lpj_fine;
+
+                /* cpufreq may scale loops_per_jiffy, so keep a private copy */
+                arm_delay_ops.ticks_per_jiffy   = lpj_fine;
                 arm_delay_ops.delay             = __timer_delay;
                 arm_delay_ops.const_udelay      = __timer_const_udelay;
                 arm_delay_ops.udelay            = __timer_udelay;
-                arm_delay_ops.const_clock       = true;
+
                 delay_calibrated                = true;
         } else {
                 pr_info("Ignoring duplicate/late registration of read_current_timer delay\n");
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 6071f4c3d654..02802386b894 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -1,14 +1,15 @@
 if ARCH_AT91
 
-config HAVE_AT91_DATAFLASH_CARD
-        bool
-
 config HAVE_AT91_DBGU0
         bool
 
 config HAVE_AT91_DBGU1
         bool
 
+config AT91_PMC_UNIT
+        bool
+        default !ARCH_AT91X40
+
 config AT91_SAM9_ALT_RESET
         bool
         default !ARCH_AT91X40
@@ -17,17 +18,59 @@ config AT91_SAM9G45_RESET
         bool
         default !ARCH_AT91X40
 
+config AT91_SAM9_TIME
+        bool
+
 config SOC_AT91SAM9
         bool
+        select AT91_SAM9_TIME
         select CPU_ARM926T
         select GENERIC_CLOCKEVENTS
         select MULTI_IRQ_HANDLER
         select SPARSE_IRQ
 
+config SOC_SAMA5
+        bool
+        select AT91_SAM9_TIME
+        select CPU_V7
+        select GENERIC_CLOCKEVENTS
+        select MULTI_IRQ_HANDLER
+        select SPARSE_IRQ
+
 menu "Atmel AT91 System-on-Chip"
 
+choice
+
+        prompt "Core type"
+
+config SOC_SAM_V4_V5
+        bool "ARM7/ARM9"
+        help
+          Select this if you are using one of Atmel's AT91SAM9, AT91RM9200
+          or AT91X40 SoC.
+
+config SOC_SAM_V7
+        bool "Cortex A5"
+        help
+          Select this if you are using one of Atmel's SAMA5D3 SoC.
+
+endchoice
+
 comment "Atmel AT91 Processor"
 
+if SOC_SAM_V7
+config SOC_SAMA5D3
+        bool "SAMA5D3 family"
+        depends on SOC_SAM_V7
+        select SOC_SAMA5
+        select HAVE_FB_ATMEL
+        select HAVE_AT91_DBGU1
+        help
+          Select this if you are using one of Atmel's SAMA5D3 family SoC.
+          This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35.
+endif
+
+if SOC_SAM_V4_V5
 config SOC_AT91RM9200
         bool "AT91RM9200"
         select CPU_ARM920T
@@ -93,394 +136,10 @@ config SOC_AT91SAM9N12
         help
           Select this if you are using Atmel's AT91SAM9N12 SoC.
 
-choice
-        prompt "Atmel AT91 Processor Devices for non DT boards"
-
-config ARCH_AT91_NONE
-        bool "None"
-
-config ARCH_AT91RM9200
-        bool "AT91RM9200"
-        select SOC_AT91RM9200
-
-config ARCH_AT91SAM9260
-        bool "AT91SAM9260 or AT91SAM9XE"
-        select SOC_AT91SAM9260
-
-config ARCH_AT91SAM9261
-        bool "AT91SAM9261"
-        select SOC_AT91SAM9261
-
-config ARCH_AT91SAM9G10
-        bool "AT91SAM9G10"
-        select SOC_AT91SAM9261
-
-config ARCH_AT91SAM9263
-        bool "AT91SAM9263"
-        select SOC_AT91SAM9263
-
-config ARCH_AT91SAM9RL
-        bool "AT91SAM9RL"
-        select SOC_AT91SAM9RL
-
-config ARCH_AT91SAM9G20
-        bool "AT91SAM9G20"
-        select SOC_AT91SAM9260
-
-config ARCH_AT91SAM9G45
-        bool "AT91SAM9G45"
-        select SOC_AT91SAM9G45
-
-config ARCH_AT91X40
-        bool "AT91x40"
-        depends on !MMU
-        select ARCH_USES_GETTIMEOFFSET
-        select MULTI_IRQ_HANDLER
-        select SPARSE_IRQ
-
-endchoice
-
-config AT91_PMC_UNIT
-        bool
-        default !ARCH_AT91X40
-
-# ----------------------------------------------------------
-
-if ARCH_AT91RM9200
-
-comment "AT91RM9200 Board Type"
-
-config MACH_ONEARM
-        bool "Ajeco 1ARM Single Board Computer"
-        help
-          Select this if you are using Ajeco's 1ARM Single Board Computer.
-          <http://www.ajeco.fi/>
-
-config ARCH_AT91RM9200DK
-        bool "Atmel AT91RM9200-DK Development board"
-        select HAVE_AT91_DATAFLASH_CARD
-        help
-          Select this if you are using Atmel's AT91RM9200-DK Development board.
-          (Discontinued)
-
-config MACH_AT91RM9200EK
-        bool "Atmel AT91RM9200-EK Evaluation Kit"
-        select HAVE_AT91_DATAFLASH_CARD
-        help
-          Select this if you are using Atmel's AT91RM9200-EK Evaluation Kit.
-          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3507>
-
-config MACH_CSB337
-        bool "Cogent CSB337"
-        help
-          Select this if you are using Cogent's CSB337 board.
-          <http://www.cogcomp.com/csb_csb337.htm>
-
-config MACH_CSB637
-        bool "Cogent CSB637"
-        help
-          Select this if you are using Cogent's CSB637 board.
-          <http://www.cogcomp.com/csb_csb637.htm>
-
-config MACH_CARMEVA
-        bool "Conitec ARM&EVA"
-        help
-          Select this if you are using Conitec's AT91RM9200-MCU-Module.
-          <http://www.conitec.net/english/linuxboard.php>
-
-config MACH_ATEB9200
-        bool "Embest ATEB9200"
-        help
-          Select this if you are using Embest's ATEB9200 board.
-          <http://www.embedinfo.com/english/product/ATEB9200.asp>
-
-config MACH_KB9200
-        bool "KwikByte KB920x"
-        help
-          Select this if you are using KwikByte's KB920x board.
-          <http://www.kwikbyte.com/KB9202.html>
-
-config MACH_PICOTUX2XX
-        bool "picotux 200"
-        help
-          Select this if you are using a picotux 200.
-          <http://www.picotux.com/>
-
-config MACH_KAFA
-        bool "Sperry-Sun KAFA board"
-        help
-          Select this if you are using Sperry-Sun's KAFA board.
-
-config MACH_ECBAT91
-        bool "emQbit ECB_AT91 SBC"
-        select HAVE_AT91_DATAFLASH_CARD
-        help
-          Select this if you are using emQbit's ECB_AT91 board.
-          <http://wiki.emqbit.com/free-ecb-at91>
-
-config MACH_YL9200
-        bool "ucDragon YL-9200"
-        help
-          Select this if you are using the ucDragon YL-9200 board.
-
-config MACH_CPUAT91
-        bool "Eukrea CPUAT91"
-        help
-          Select this if you are using the Eukrea Electromatique's
-          CPUAT91 board <http://www.eukrea.com/>.
-
-config MACH_ECO920
-        bool "eco920"
-        help
-          Select this if you are using the eco920 board
-
-config MACH_RSI_EWS
-        bool "RSI Embedded Webserver"
-        depends on ARCH_AT91RM9200
-        help
-          Select this if you are using RSIs EWS board.
-endif
-
-# ----------------------------------------------------------
-
-if ARCH_AT91SAM9260
-
-comment "AT91SAM9260 Variants"
-
-comment "AT91SAM9260 / AT91SAM9XE Board Type"
-
-config MACH_AT91SAM9260EK
-        bool "Atmel AT91SAM9260-EK / AT91SAM9XE Evaluation Kit"
-        select HAVE_AT91_DATAFLASH_CARD
-        help
-          Select this if you are using Atmel's AT91SAM9260-EK or AT91SAM9XE Evaluation Kit
-          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933>
-
-config MACH_CAM60
-        bool "KwikByte KB9260 (CAM60) board"
-        help
-          Select this if you are using KwikByte's KB9260 (CAM60) board based on the Atmel AT91SAM9260.
-          <http://www.kwikbyte.com/KB9260.html>
-
-config MACH_SAM9_L9260
-        bool "Olimex SAM9-L9260 board"
-        select HAVE_AT91_DATAFLASH_CARD
-        help
-          Select this if you are using Olimex's SAM9-L9260 board based on the Atmel AT91SAM9260.
-          <http://www.olimex.com/dev/sam9-L9260.html>
-
-config MACH_AFEB9260
-        bool "Custom afeb9260 board v1"
-        help
-          Select this if you are using custom afeb9260 board based on
-          open hardware design. Select this for revision 1 of the board.
-          <svn://194.85.238.22/home/users/george/svn/arm9eb>
-          <http://groups.google.com/group/arm9fpga-evolution-board>
-
-config MACH_USB_A9260
-        bool "CALAO USB-A9260"
-        help
-          Select this if you are using a Calao Systems USB-A9260.
-          <http://www.calao-systems.com>
-
-config MACH_QIL_A9260
-        bool "CALAO QIL-A9260 board"
-        help
-          Select this if you are using a Calao Systems QIL-A9260 Board.
-          <http://www.calao-systems.com>
-
-config MACH_CPU9260
-        bool "Eukrea CPU9260 board"
-        help
-          Select this if you are using a Eukrea Electromatique's
-          CPU9260 Board <http://www.eukrea.com/>
-
-config MACH_FLEXIBITY
-        bool "Flexibity Connect board"
-        help
-          Select this if you are using Flexibity Connect board
-          <http://www.flexibity.com>
-
-endif
-
-# ----------------------------------------------------------
-
-if ARCH_AT91SAM9261
-
-comment "AT91SAM9261 Board Type"
-
-config MACH_AT91SAM9261EK
-        bool "Atmel AT91SAM9261-EK Evaluation Kit"
-        select HAVE_AT91_DATAFLASH_CARD
-        help
-          Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit.
-          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3820>
-
-endif
-
-# ----------------------------------------------------------
-
-if ARCH_AT91SAM9G10
-
-comment "AT91SAM9G10 Board Type"
-
-config MACH_AT91SAM9G10EK
-        bool "Atmel AT91SAM9G10-EK Evaluation Kit"
-        select HAVE_AT91_DATAFLASH_CARD
-        help
-          Select this if you are using Atmel's AT91SAM9G10-EK Evaluation Kit.
-          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4588>
-
-endif
-
-# ----------------------------------------------------------
-
-if ARCH_AT91SAM9263
-
-comment "AT91SAM9263 Board Type"
-
-config MACH_AT91SAM9263EK
-        bool "Atmel AT91SAM9263-EK Evaluation Kit"
-        select HAVE_AT91_DATAFLASH_CARD
-        help
-          Select this if you are using Atmel's AT91SAM9263-EK Evaluation Kit.
-          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4057>
-
-config MACH_USB_A9263
-        bool "CALAO USB-A9263"
-        help
-          Select this if you are using a Calao Systems USB-A9263.
-          <http://www.calao-systems.com>
-
-endif
-
-# ----------------------------------------------------------
-
-if ARCH_AT91SAM9RL
-
-comment "AT91SAM9RL Board Type"
-
-config MACH_AT91SAM9RLEK
-        bool "Atmel AT91SAM9RL-EK Evaluation Kit"
-        help
-          Select this if you are using Atmel's AT91SAM9RL-EK Evaluation Kit.
-
-endif
-
 # ----------------------------------------------------------
 
-if ARCH_AT91SAM9G20
-
-comment "AT91SAM9G20 Board Type"
-
-config MACH_AT91SAM9G20EK
-        bool "Atmel AT91SAM9G20-EK Evaluation Kit"
-        select HAVE_AT91_DATAFLASH_CARD
-        help
-          Select this if you are using Atmel's AT91SAM9G20-EK Evaluation Kit
-          that embeds only one SD/MMC slot.
-
-config MACH_AT91SAM9G20EK_2MMC
-        depends on MACH_AT91SAM9G20EK
-        bool "Atmel AT91SAM9G20-EK Evaluation Kit with 2 SD/MMC Slots"
-        help
-          Select this if you are using an Atmel AT91SAM9G20-EK Evaluation Kit
-          with 2 SD/MMC Slots. This is the case for AT91SAM9G20-EK rev. C and
-          onwards.
-          <http://www.atmel.com/tools/SAM9G20-EK.aspx>
-
-config MACH_CPU9G20
-        bool "Eukrea CPU9G20 board"
-        help
-          Select this if you are using a Eukrea Electromatique's
-          CPU9G20 Board <http://www.eukrea.com/>
-
-config MACH_ACMENETUSFOXG20
-        bool "Acme Systems srl FOX Board G20"
-        help
-          Select this if you are using Acme Systems
-          FOX Board G20 <http://www.acmesystems.it>
-
-config MACH_PORTUXG20
-        bool "taskit PortuxG20"
-        help
-          Select this if you are using taskit's PortuxG20.
-          <http://www.taskit.de/en/>
-
-config MACH_STAMP9G20
-        bool "taskit Stamp9G20 CPU module"
-        help
-          Select this if you are using taskit's Stamp9G20 CPU module on its
-          evaluation board.
-          <http://www.taskit.de/en/>
-
-config MACH_PCONTROL_G20
-        bool "PControl G20 CPU module"
-        help
-          Select this if you are using taskit's Stamp9G20 CPU module on this
-          carrier board, beeing the decentralized unit of a building automation
-          system; featuring nvram, eth-switch, iso-rs485, display, io
-
-config MACH_GSIA18S
-        bool "GS_IA18_S board"
-        help
-          This enables support for the GS_IA18_S board
-          produced by GeoSIG Ltd company. This is an internet accelerograph.
-          <http://www.geosig.com>
-
-config MACH_USB_A9G20
-        bool "CALAO USB-A9G20"
-        depends on ARCH_AT91SAM9G20
-        help
-          Select this if you are using a Calao Systems USB-A9G20.
-          <http://www.calao-systems.com>
-
-endif
-
-if (ARCH_AT91SAM9260 || ARCH_AT91SAM9G20)
-comment "AT91SAM9260/AT91SAM9G20 boards"
-
-config MACH_SNAPPER_9260
-        bool "Bluewater Systems Snapper 9260/9G20 module"
-        help
-          Select this if you are using the Bluewater Systems Snapper 9260 or
-          Snapper 9G20 modules.
-          <http://www.bluewatersys.com/>
-endif
-
-# ----------------------------------------------------------
-
-if ARCH_AT91SAM9G45
-
-comment "AT91SAM9G45 Board Type"
-
-config MACH_AT91SAM9M10G45EK
-        bool "Atmel AT91SAM9M10G45-EK Evaluation Kits"
-        help
-          Select this if you are using Atmel's AT91SAM9M10G45-EK Evaluation Kit.
-          Those boards can be populated with any SoC of AT91SAM9G45 or AT91SAM9M10
-          families: AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11.
-          <http://www.atmel.com/tools/SAM9M10-G45-EK.aspx>
-
-endif
-
-# ----------------------------------------------------------
-
-if ARCH_AT91X40
-
-comment "AT91X40 Board Type"
-
-config MACH_AT91EB01
-        bool "Atmel AT91EB01 Evaluation Kit"
-        help
-          Select this if you are using Atmel's AT91EB01 Evaluation Kit.
-          It is also a popular target for simulators such as GDB's
-          ARM simulator (commonly known as the ARMulator) and the
-          Skyeye simulator.
-
-endif
-
-# ----------------------------------------------------------
+source arch/arm/mach-at91/Kconfig.non_dt
+endif # SOC_SAM_V4_V5
 
 comment "Generic Board Type"
 
@@ -492,7 +151,7 @@ config MACH_AT91RM9200_DT
           Select this if you want to experiment device-tree with
           an Atmel RM9200 Evaluation Kit.
 
-config MACH_AT91SAM_DT
+config MACH_AT91SAM9_DT
         bool "Atmel AT91SAM Evaluation Kits with device-tree support"
         depends on SOC_AT91SAM9
         select USE_OF
@@ -500,15 +159,13 @@ config MACH_AT91SAM_DT
           Select this if you want to experiment device-tree with
           an Atmel Evaluation Kit.
 
-# ----------------------------------------------------------
-
-comment "AT91 Board Options"
-
-config MTD_AT91_DATAFLASH_CARD
-        bool "Enable DataFlash Card support"
-        depends on HAVE_AT91_DATAFLASH_CARD
+config MACH_SAMA5_DT
+        bool "Atmel SAMA5 Evaluation Kits with device-tree support"
+        depends on SOC_SAMA5
+        select USE_OF
         help
-          Enable support for the DataFlash card.
+          Select this if you want to experiment device-tree with
+          an Atmel Evaluation Kit.
 
 # ----------------------------------------------------------
 
diff --git a/arch/arm/mach-at91/Kconfig.non_dt b/arch/arm/mach-at91/Kconfig.non_dt
new file mode 100644
index 000000000000..6c24985515a2
--- /dev/null
+++ b/arch/arm/mach-at91/Kconfig.non_dt
@@ -0,0 +1,399 @@
+menu "Atmel Non-DT world"
+
+config HAVE_AT91_DATAFLASH_CARD
+        bool
+
+choice
+        prompt "Atmel AT91 Processor Devices for non DT boards"
+
+config ARCH_AT91_NONE
+        bool "None"
+
+config ARCH_AT91RM9200
+        bool "AT91RM9200"
+        select SOC_AT91RM9200
+
+config ARCH_AT91SAM9260
+        bool "AT91SAM9260 or AT91SAM9XE"
+        select SOC_AT91SAM9260
+
+config ARCH_AT91SAM9261
+        bool "AT91SAM9261"
+        select SOC_AT91SAM9261
+
+config ARCH_AT91SAM9G10
+        bool "AT91SAM9G10"
+        select SOC_AT91SAM9261
+
+config ARCH_AT91SAM9263
+        bool "AT91SAM9263"
+        select SOC_AT91SAM9263
+
+config ARCH_AT91SAM9RL
+        bool "AT91SAM9RL"
+        select SOC_AT91SAM9RL
+
+config ARCH_AT91SAM9G20
+        bool "AT91SAM9G20"
+        select SOC_AT91SAM9260
+
+config ARCH_AT91SAM9G45
+        bool "AT91SAM9G45"
+        select SOC_AT91SAM9G45
+
+config ARCH_AT91X40
+        bool "AT91x40"
+        depends on !MMU
+        select ARCH_USES_GETTIMEOFFSET
+        select MULTI_IRQ_HANDLER
+        select SPARSE_IRQ
+
+endchoice
+
+# ----------------------------------------------------------
+
+if ARCH_AT91RM9200
+
+comment "AT91RM9200 Board Type"
+
+config MACH_ONEARM
+        bool "Ajeco 1ARM Single Board Computer"
+        help
+          Select this if you are using Ajeco's 1ARM Single Board Computer.
+          <http://www.ajeco.fi/>
+
+config ARCH_AT91RM9200DK
+        bool "Atmel AT91RM9200-DK Development board"
+        select HAVE_AT91_DATAFLASH_CARD
+        help
+          Select this if you are using Atmel's AT91RM9200-DK Development board.
+          (Discontinued)
+
+config MACH_AT91RM9200EK
+        bool "Atmel AT91RM9200-EK Evaluation Kit"
+        select HAVE_AT91_DATAFLASH_CARD
+        help
+          Select this if you are using Atmel's AT91RM9200-EK Evaluation Kit.
+          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3507>
+
+config MACH_CSB337
+        bool "Cogent CSB337"
+        help
+          Select this if you are using Cogent's CSB337 board.
+          <http://www.cogcomp.com/csb_csb337.htm>
+
+config MACH_CSB637
+        bool "Cogent CSB637"
+        help
+          Select this if you are using Cogent's CSB637 board.
+          <http://www.cogcomp.com/csb_csb637.htm>
+
+config MACH_CARMEVA
+        bool "Conitec ARM&EVA"
+        help
+          Select this if you are using Conitec's AT91RM9200-MCU-Module.
+          <http://www.conitec.net/english/linuxboard.php>
+
+config MACH_ATEB9200
+        bool "Embest ATEB9200"
+        help
+          Select this if you are using Embest's ATEB9200 board.
+          <http://www.embedinfo.com/english/product/ATEB9200.asp>
+
+config MACH_KB9200
+        bool "KwikByte KB920x"
+        help
+          Select this if you are using KwikByte's KB920x board.
+          <http://www.kwikbyte.com/KB9202.html>
+
+config MACH_PICOTUX2XX
+        bool "picotux 200"
+        help
+          Select this if you are using a picotux 200.
+          <http://www.picotux.com/>
+
+config MACH_KAFA
+        bool "Sperry-Sun KAFA board"
+        help
+          Select this if you are using Sperry-Sun's KAFA board.
+
+config MACH_ECBAT91
+        bool "emQbit ECB_AT91 SBC"
+        select HAVE_AT91_DATAFLASH_CARD
+        help
+          Select this if you are using emQbit's ECB_AT91 board.
+          <http://wiki.emqbit.com/free-ecb-at91>
+
+config MACH_YL9200
+        bool "ucDragon YL-9200"
+        help
+          Select this if you are using the ucDragon YL-9200 board.
+
+config MACH_CPUAT91
+        bool "Eukrea CPUAT91"
+        help
+          Select this if you are using the Eukrea Electromatique's
+          CPUAT91 board <http://www.eukrea.com/>.
+
+config MACH_ECO920
+        bool "eco920"
+        help
+          Select this if you are using the eco920 board
+
+config MACH_RSI_EWS
+        bool "RSI Embedded Webserver"
+        depends on ARCH_AT91RM9200
+        help
+          Select this if you are using RSIs EWS board.
+endif
+
+# ----------------------------------------------------------
+
+if ARCH_AT91SAM9260
+
+comment "AT91SAM9260 Variants"
+
+comment "AT91SAM9260 / AT91SAM9XE Board Type"
+
+config MACH_AT91SAM9260EK
+        bool "Atmel AT91SAM9260-EK / AT91SAM9XE Evaluation Kit"
+        select HAVE_AT91_DATAFLASH_CARD
+        help
+          Select this if you are using Atmel's AT91SAM9260-EK or AT91SAM9XE Evaluation Kit
+          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933>
+
+config MACH_CAM60
+        bool "KwikByte KB9260 (CAM60) board"
+        help
+          Select this if you are using KwikByte's KB9260 (CAM60) board based on the Atmel AT91SAM9260.
+          <http://www.kwikbyte.com/KB9260.html>
+
+config MACH_SAM9_L9260
+        bool "Olimex SAM9-L9260 board"
+        select HAVE_AT91_DATAFLASH_CARD
+        help
+          Select this if you are using Olimex's SAM9-L9260 board based on the Atmel AT91SAM9260.
+          <http://www.olimex.com/dev/sam9-L9260.html>
+
+config MACH_AFEB9260
+        bool "Custom afeb9260 board v1"
+        help
+          Select this if you are using custom afeb9260 board based on
+          open hardware design. Select this for revision 1 of the board.
+          <svn://194.85.238.22/home/users/george/svn/arm9eb>
+          <http://groups.google.com/group/arm9fpga-evolution-board>
+
+config MACH_USB_A9260
+        bool "CALAO USB-A9260"
+        help
+          Select this if you are using a Calao Systems USB-A9260.
+          <http://www.calao-systems.com>
+
+config MACH_QIL_A9260
+        bool "CALAO QIL-A9260 board"
+        help
+          Select this if you are using a Calao Systems QIL-A9260 Board.
+          <http://www.calao-systems.com>
+
+config MACH_CPU9260
+        bool "Eukrea CPU9260 board"
+        help
+          Select this if you are using a Eukrea Electromatique's
+          CPU9260 Board <http://www.eukrea.com/>
+
+config MACH_FLEXIBITY
+        bool "Flexibity Connect board"
+        help
+          Select this if you are using Flexibity Connect board
+          <http://www.flexibity.com>
+
+endif
+
+# ----------------------------------------------------------
+
+if ARCH_AT91SAM9261
+
+comment "AT91SAM9261 Board Type"
+
+config MACH_AT91SAM9261EK
+        bool "Atmel AT91SAM9261-EK Evaluation Kit"
+        select HAVE_AT91_DATAFLASH_CARD
+        help
+          Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit.
+          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3820>
+
+endif
+
+# ----------------------------------------------------------
+
+if ARCH_AT91SAM9G10
+
+comment "AT91SAM9G10 Board Type"
+
+config MACH_AT91SAM9G10EK
+        bool "Atmel AT91SAM9G10-EK Evaluation Kit"
+        select HAVE_AT91_DATAFLASH_CARD
+        help
+          Select this if you are using Atmel's AT91SAM9G10-EK Evaluation Kit.
+          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4588>
+
+endif
+
+# ----------------------------------------------------------
+
+if ARCH_AT91SAM9263
+
+comment "AT91SAM9263 Board Type"
+
+config MACH_AT91SAM9263EK
+        bool "Atmel AT91SAM9263-EK Evaluation Kit"
+        select HAVE_AT91_DATAFLASH_CARD
+        help
+          Select this if you are using Atmel's AT91SAM9263-EK Evaluation Kit.
+          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4057>
+
+config MACH_USB_A9263
+        bool "CALAO USB-A9263"
+        help
+          Select this if you are using a Calao Systems USB-A9263.
+          <http://www.calao-systems.com>
+
+endif
+
+# ----------------------------------------------------------
+
+if ARCH_AT91SAM9RL
+
+comment "AT91SAM9RL Board Type"
+
+config MACH_AT91SAM9RLEK
+        bool "Atmel AT91SAM9RL-EK Evaluation Kit"
+        help
+          Select this if you are using Atmel's AT91SAM9RL-EK Evaluation Kit.
+
+endif
+
+# ----------------------------------------------------------
+
+if ARCH_AT91SAM9G20
+
+comment "AT91SAM9G20 Board Type"
+
+config MACH_AT91SAM9G20EK
+        bool "Atmel AT91SAM9G20-EK Evaluation Kit"
+        select HAVE_AT91_DATAFLASH_CARD
+        help
+          Select this if you are using Atmel's AT91SAM9G20-EK Evaluation Kit
+          that embeds only one SD/MMC slot.
+
+config MACH_AT91SAM9G20EK_2MMC
+        depends on MACH_AT91SAM9G20EK
+        bool "Atmel AT91SAM9G20-EK Evaluation Kit with 2 SD/MMC Slots"
+        help
+          Select this if you are using an Atmel AT91SAM9G20-EK Evaluation Kit
+          with 2 SD/MMC Slots. This is the case for AT91SAM9G20-EK rev. C and
+          onwards.
+          <http://www.atmel.com/tools/SAM9G20-EK.aspx>
+
+config MACH_CPU9G20
+        bool "Eukrea CPU9G20 board"
+        help
+          Select this if you are using a Eukrea Electromatique's
+          CPU9G20 Board <http://www.eukrea.com/>
+
+config MACH_ACMENETUSFOXG20
+        bool "Acme Systems srl FOX Board G20"
+        help
+          Select this if you are using Acme Systems
+          FOX Board G20 <http://www.acmesystems.it>
+
+config MACH_PORTUXG20
+        bool "taskit PortuxG20"
+        help
+          Select this if you are using taskit's PortuxG20.
+          <http://www.taskit.de/en/>
+
+config MACH_STAMP9G20
+        bool "taskit Stamp9G20 CPU module"
+        help
+          Select this if you are using taskit's Stamp9G20 CPU module on its
+          evaluation board.
+          <http://www.taskit.de/en/>
+
+config MACH_PCONTROL_G20
+        bool "PControl G20 CPU module"
+        help
+          Select this if you are using taskit's Stamp9G20 CPU module on this
+          carrier board, beeing the decentralized unit of a building automation
+          system; featuring nvram, eth-switch, iso-rs485, display, io
+
+config MACH_GSIA18S
+        bool "GS_IA18_S board"
+        help
+          This enables support for the GS_IA18_S board
+          produced by GeoSIG Ltd company. This is an internet accelerograph.
+          <http://www.geosig.com>
+
+config MACH_USB_A9G20
+        bool "CALAO USB-A9G20"
+        depends on ARCH_AT91SAM9G20
+        help
+          Select this if you are using a Calao Systems USB-A9G20.
+          <http://www.calao-systems.com>
+
+endif
+
+if (ARCH_AT91SAM9260 || ARCH_AT91SAM9G20)
+comment "AT91SAM9260/AT91SAM9G20 boards"
+
+config MACH_SNAPPER_9260
+        bool "Bluewater Systems Snapper 9260/9G20 module"
+        help
+          Select this if you are using the Bluewater Systems Snapper 9260 or
+          Snapper 9G20 modules.
+          <http://www.bluewatersys.com/>
+endif
+
+# ----------------------------------------------------------
+
+if ARCH_AT91SAM9G45
+
+comment "AT91SAM9G45 Board Type"
+
+config MACH_AT91SAM9M10G45EK
+        bool "Atmel AT91SAM9M10G45-EK Evaluation Kits"
+        help
+          Select this if you are using Atmel's AT91SAM9M10G45-EK Evaluation Kit.
+          Those boards can be populated with any SoC of AT91SAM9G45 or AT91SAM9M10
+          families: AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11.
+          <http://www.atmel.com/tools/SAM9M10-G45-EK.aspx>
+
+endif
+
+# ----------------------------------------------------------
+
+if ARCH_AT91X40
+
+comment "AT91X40 Board Type"
+
+config MACH_AT91EB01
+        bool "Atmel AT91EB01 Evaluation Kit"
+        help
+          Select this if you are using Atmel's AT91EB01 Evaluation Kit.
+          It is also a popular target for simulators such as GDB's
+          ARM simulator (commonly known as the ARMulator) and the
+          Skyeye simulator.
+
+endif
+
+# ----------------------------------------------------------
+
+comment "AT91 Board Options"
+
+config MTD_AT91_DATAFLASH_CARD
+        bool "Enable DataFlash Card support"
+        depends on HAVE_AT91_DATAFLASH_CARD
+        help
+          Enable support for the DataFlash card.
+
+endmenu
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 39218ca6d8e8..788562dccb43 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -10,7 +10,8 @@ obj-		:=
 obj-$(CONFIG_AT91_PMC_UNIT)     += clock.o
 obj-$(CONFIG_AT91_SAM9_ALT_RESET) += at91sam9_alt_reset.o
 obj-$(CONFIG_AT91_SAM9G45_RESET) += at91sam9g45_reset.o
-obj-$(CONFIG_SOC_AT91SAM9)      += at91sam926x_time.o sam9_smc.o
+obj-$(CONFIG_AT91_SAM9_TIME)    += at91sam926x_time.o
+obj-$(CONFIG_SOC_AT91SAM9)      += sam9_smc.o
 
 # CPU-specific support
 obj-$(CONFIG_SOC_AT91RM9200)    += at91rm9200.o at91rm9200_time.o
@@ -21,6 +22,7 @@ obj-$(CONFIG_SOC_AT91SAM9G45)	+= at91sam9g45.o
 obj-$(CONFIG_SOC_AT91SAM9N12)   += at91sam9n12.o
 obj-$(CONFIG_SOC_AT91SAM9X5)    += at91sam9x5.o
 obj-$(CONFIG_SOC_AT91SAM9RL)    += at91sam9rl.o
+obj-$(CONFIG_SOC_SAMA5D3)       += sama5d3.o
 
 obj-$(CONFIG_ARCH_AT91RM9200)   += at91rm9200_devices.o
 obj-$(CONFIG_ARCH_AT91SAM9260)  += at91sam9260_devices.o
@@ -87,8 +89,11 @@ obj-$(CONFIG_MACH_SNAPPER_9260)	+= board-snapper9260.o
 obj-$(CONFIG_MACH_AT91SAM9M10G45EK) += board-sam9m10g45ek.o
 
 # AT91SAM board with device-tree
-obj-$(CONFIG_MACH_AT91RM9200_DT) += board-rm9200-dt.o
-obj-$(CONFIG_MACH_AT91SAM_DT) += board-dt.o
+obj-$(CONFIG_MACH_AT91RM9200_DT) += board-dt-rm9200.o
+obj-$(CONFIG_MACH_AT91SAM9_DT) += board-dt-sam9.o
+
+# SAMA5 board with device-tree
+obj-$(CONFIG_MACH_SAMA5_DT) += board-dt-sama5.o
 
 # AT91X40 board-specific support
 obj-$(CONFIG_MACH_AT91EB01)     += board-eb01.o
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index 9706c000f294..ccce7592dbd3 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -384,7 +384,7 @@ static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
         0       /* Advanced Interrupt Controller (IRQ6) */
 };
 
-AT91_SOC_START(rm9200)
+AT91_SOC_START(at91rm9200)
         .map_io = at91rm9200_map_io,
         .default_irq_priority = at91rm9200_default_irq_priority,
         .ioremap_registers = at91rm9200_ioremap_registers,
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index b67cd5374117..1833b4c365df 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -395,7 +395,7 @@ static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
         0,      /* Advanced Interrupt Controller */
 };
 
-AT91_SOC_START(sam9260)
+AT91_SOC_START(at91sam9260)
         .map_io = at91sam9260_map_io,
         .default_irq_priority = at91sam9260_default_irq_priority,
         .ioremap_registers = at91sam9260_ioremap_registers,
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index 0204f4cc9ebf..25efb5ac30f1 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -339,7 +339,7 @@ static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
         0,      /* Advanced Interrupt Controller */
 };
 
-AT91_SOC_START(sam9261)
+AT91_SOC_START(at91sam9261)
         .map_io = at91sam9261_map_io,
         .default_irq_priority = at91sam9261_default_irq_priority,
         .ioremap_registers = at91sam9261_ioremap_registers,
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index 2282fd7ad3e3..f44ffd2105a7 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -375,7 +375,7 @@ static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
         0,      /* Advanced Interrupt Controller (IRQ1) */
 };
 
-AT91_SOC_START(sam9263)
+AT91_SOC_START(at91sam9263)
         .map_io = at91sam9263_map_io,
         .default_irq_priority = at91sam9263_default_irq_priority,
         .ioremap_registers = at91sam9263_ioremap_registers,
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index c68960d82247..dc49c2c45d49 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -420,7 +420,7 @@ static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
         0,      /* Advanced Interrupt Controller (IRQ0) */
 };
 
-AT91_SOC_START(sam9g45)
+AT91_SOC_START(at91sam9g45)
         .map_io = at91sam9g45_map_io,
         .default_irq_priority = at91sam9g45_default_irq_priority,
         .ioremap_registers = at91sam9g45_ioremap_registers,
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
index 5dfc8fd87103..2c7a2f4a7568 100644
--- a/arch/arm/mach-at91/at91sam9n12.c
+++ b/arch/arm/mach-at91/at91sam9n12.c
@@ -226,7 +226,7 @@ void __init at91sam9n12_initialize(void)
         at91_extern_irq = (1 << AT91SAM9N12_ID_IRQ0);
 }
 
-AT91_SOC_START(sam9n12)
+AT91_SOC_START(at91sam9n12)
         .map_io = at91sam9n12_map_io,
         .register_clocks = at91sam9n12_register_clocks,
         .init = at91sam9n12_initialize,
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index 3de3e04d0f81..f77fae5591bc 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -341,7 +341,7 @@ static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
         0,      /* Advanced Interrupt Controller */
 };
 
-AT91_SOC_START(sam9rl)
+AT91_SOC_START(at91sam9rl)
         .map_io = at91sam9rl_map_io,
         .default_irq_priority = at91sam9rl_default_irq_priority,
         .ioremap_registers = at91sam9rl_ioremap_registers,
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index 44a9a62dcc13..3a1a7993c125 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -320,7 +320,7 @@ static void __init at91sam9x5_map_io(void)
  *  Interrupt initialization
  * -------------------------------------------------------------------- */
 
-AT91_SOC_START(sam9x5)
+AT91_SOC_START(at91sam9x5)
         .map_io = at91sam9x5_map_io,
         .register_clocks = at91sam9x5_register_clocks,
 AT91_SOC_END
diff --git a/arch/arm/mach-at91/board-rm9200-dt.c b/arch/arm/mach-at91/board-dt-rm9200.c
index 3fcb6623a33e..3fcb6623a33e 100644
--- a/arch/arm/mach-at91/board-rm9200-dt.c
+++ b/arch/arm/mach-at91/board-dt-rm9200.c
diff --git a/arch/arm/mach-at91/board-dt.c b/arch/arm/mach-at91/board-dt-sam9.c
index 8db30132abed..8db30132abed 100644
--- a/arch/arm/mach-at91/board-dt.c
+++ b/arch/arm/mach-at91/board-dt-sam9.c
diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
new file mode 100644
index 000000000000..705305e62bbc
--- /dev/null
+++ b/arch/arm/mach-at91/board-dt-sama5.c
@@ -0,0 +1,86 @@
+/*
+ *  Setup code for SAMA5 Evaluation Kits with Device Tree support
+ *
+ *  Copyright (C) 2013 Atmel,
+ *                2013 Ludovic Desroches <ludovic.desroches@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/gpio.h>
+#include <linux/micrel_phy.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/phy.h>
+
+#include <asm/setup.h>
+#include <asm/irq.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include "at91_aic.h"
+#include "generic.h"
+
+
+static const struct of_device_id irq_of_match[] __initconst = {
+
+        { .compatible = "atmel,sama5d3-aic", .data = at91_aic5_of_init },
+        { /*sentinel*/ }
+};
+
+static void __init at91_dt_init_irq(void)
+{
+        of_irq_init(irq_of_match);
+}
+
+static int ksz9021rn_phy_fixup(struct phy_device *phy)
+{
+        int value;
+
+#define GMII_RCCPSR     260
+#define GMII_RRDPSR     261
+#define GMII_ERCR       11
+#define GMII_ERDWR      12
+
+        /* Set delay values */
+        value = GMII_RCCPSR | 0x8000;
+        phy_write(phy, GMII_ERCR, value);
+        value = 0xF2F4;
+        phy_write(phy, GMII_ERDWR, value);
+        value = GMII_RRDPSR | 0x8000;
+        phy_write(phy, GMII_ERCR, value);
+        value = 0x2222;
+        phy_write(phy, GMII_ERDWR, value);
+
+        return 0;
+}
+
+static void __init sama5_dt_device_init(void)
+{
+        if (of_machine_is_compatible("atmel,sama5d3xcm"))
+                phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
+                        ksz9021rn_phy_fixup);
+
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static const char *sama5_dt_board_compat[] __initdata = {
+        "atmel,sama5",
+        NULL
+};
+
+DT_MACHINE_START(sama5_dt, "Atmel SAMA5 (Device Tree)")
+        /* Maintainer: Atmel */
+        .init_time      = at91sam926x_pit_init,
+        .map_io         = at91_map_io,
+        .handle_irq     = at91_aic5_handle_irq,
+        .init_early     = at91_dt_initialize,
+        .init_irq       = at91_dt_init_irq,
+        .init_machine   = sama5_dt_device_init,
+        .dt_compat      = sama5_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index 33361505c0cd..da841885d01c 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -54,7 +54,10 @@ EXPORT_SYMBOL_GPL(at91_pmc_base);
  */
 #define cpu_has_utmi()          (  cpu_is_at91sam9rl() \
                                 || cpu_is_at91sam9g45() \
-                                || cpu_is_at91sam9x5())
+                                || cpu_is_at91sam9x5() \
+                                || cpu_is_sama5d3())
+
+#define cpu_has_1056M_plla()    (cpu_is_sama5d3())
 
 #define cpu_has_800M_plla()     (  cpu_is_at91sam9g20() \
                                 || cpu_is_at91sam9g45() \
@@ -75,7 +78,8 @@ EXPORT_SYMBOL_GPL(at91_pmc_base);
                                 || cpu_is_at91sam9n12()))
 
 #define cpu_has_upll()          (cpu_is_at91sam9g45() \
-                                || cpu_is_at91sam9x5())
+                                || cpu_is_at91sam9x5() \
+                                || cpu_is_sama5d3())
 
 /* USB host HS & FS */
 #define cpu_has_uhp()           (!cpu_is_at91sam9rl())
@@ -83,18 +87,22 @@ EXPORT_SYMBOL_GPL(at91_pmc_base);
 /* USB device FS only */
 #define cpu_has_udpfs()         (!(cpu_is_at91sam9rl() \
                                 || cpu_is_at91sam9g45() \
-                                || cpu_is_at91sam9x5()))
+                                || cpu_is_at91sam9x5() \
+                                || cpu_is_sama5d3()))
 
 #define cpu_has_plladiv2()      (cpu_is_at91sam9g45() \
                                 || cpu_is_at91sam9x5() \
-                                || cpu_is_at91sam9n12())
+                                || cpu_is_at91sam9n12() \
+                                || cpu_is_sama5d3())
 
 #define cpu_has_mdiv3()         (cpu_is_at91sam9g45() \
                                 || cpu_is_at91sam9x5() \
-                                || cpu_is_at91sam9n12())
+                                || cpu_is_at91sam9n12() \
+                                || cpu_is_sama5d3())
 
 #define cpu_has_alt_prescaler() (cpu_is_at91sam9x5() \
-                                || cpu_is_at91sam9n12())
+                                || cpu_is_at91sam9n12() \
+                                || cpu_is_sama5d3())
 
 static LIST_HEAD(clocks);
 static DEFINE_SPINLOCK(clk_lock);
@@ -210,10 +218,26 @@ struct clk mck = {
 
 static void pmc_periph_mode(struct clk *clk, int is_on)
 {
-        if (is_on)
-                at91_pmc_write(AT91_PMC_PCER, clk->pmc_mask);
-        else
-                at91_pmc_write(AT91_PMC_PCDR, clk->pmc_mask);
+        u32 regval = 0;
+
+        /*
+         * With sama5d3 devices, we are managing clock division so we have to
+         * use the Peripheral Control Register introduced from at91sam9x5
+         * devices.
+         */
+        if (cpu_is_sama5d3()) {
+                regval |= AT91_PMC_PCR_CMD; /* write command */
+                regval |= clk->pid & AT91_PMC_PCR_PID; /* peripheral selection */
+                regval |= AT91_PMC_PCR_DIV(clk->div);
+                if (is_on)
+                        regval |= AT91_PMC_PCR_EN; /* enable clock */
+                at91_pmc_write(AT91_PMC_PCR, regval);
+        } else {
+                if (is_on)
+                        at91_pmc_write(AT91_PMC_PCER, clk->pmc_mask);
+                else
+                        at91_pmc_write(AT91_PMC_PCDR, clk->pmc_mask);
+        }
 }
 
 static struct clk __init *at91_css_to_clk(unsigned long css)
@@ -443,14 +467,18 @@ static void __init init_programmable_clock(struct clk *clk)
 
 static int at91_clk_show(struct seq_file *s, void *unused)
 {
-        u32             scsr, pcsr, uckr = 0, sr;
+        u32             scsr, pcsr, pcsr1 = 0, uckr = 0, sr;
         struct clk      *clk;
 
         scsr = at91_pmc_read(AT91_PMC_SCSR);
         pcsr = at91_pmc_read(AT91_PMC_PCSR);
+        if (cpu_is_sama5d3())
+                pcsr1 = at91_pmc_read(AT91_PMC_PCSR1);
         sr = at91_pmc_read(AT91_PMC_SR);
         seq_printf(s, "SCSR = %8x\n", scsr);
         seq_printf(s, "PCSR = %8x\n", pcsr);
+        if (cpu_is_sama5d3())
+                seq_printf(s, "PCSR1 = %8x\n", pcsr1);
         seq_printf(s, "MOR  = %8x\n", at91_pmc_read(AT91_CKGR_MOR));
         seq_printf(s, "MCFR = %8x\n", at91_pmc_read(AT91_CKGR_MCFR));
         seq_printf(s, "PLLA = %8x\n", at91_pmc_read(AT91_CKGR_PLLAR));
@@ -470,20 +498,30 @@ static int at91_clk_show(struct seq_file *s, void *unused)
         list_for_each_entry(clk, &clocks, node) {
                 char    *state;
 
-                if (clk->mode == pmc_sys_mode)
+                if (clk->mode == pmc_sys_mode) {
                         state = (scsr & clk->pmc_mask) ? "on" : "off";
-                else if (clk->mode == pmc_periph_mode)
-                        state = (pcsr & clk->pmc_mask) ? "on" : "off";
-                else if (clk->mode == pmc_uckr_mode)
+                } else if (clk->mode == pmc_periph_mode) {
+                        if (cpu_is_sama5d3()) {
+                                u32 pmc_mask = 1 << (clk->pid % 32);
+
+                                if (clk->pid > 31)
+                                        state = (pcsr1 & pmc_mask) ? "on" : "off";
+                                else
+                                        state = (pcsr & pmc_mask) ? "on" : "off";
+                        } else {
+                                state = (pcsr & clk->pmc_mask) ? "on" : "off";
+                        }
+                } else if (clk->mode == pmc_uckr_mode) {
                         state = (uckr & clk->pmc_mask) ? "on" : "off";
-                else if (clk->pmc_mask)
+                } else if (clk->pmc_mask) {
                         state = (sr & clk->pmc_mask) ? "on" : "off";
-                else if (clk == &clk32k || clk == &main_clk)
+                } else if (clk == &clk32k || clk == &main_clk) {
                         state = "on";
-                else
+                } else {
                         state = "";
+                }
 
-                seq_printf(s, "%-10s users=%2d %-3s %9ld Hz %s\n",
+                seq_printf(s, "%-10s users=%2d %-3s %9lu Hz %s\n",
                         clk->name, clk->users, state, clk_get_rate(clk),
                         clk->parent ? clk->parent->name : "");
         }
@@ -530,6 +568,9 @@ int __init clk_register(struct clk *clk)
         if (clk_is_peripheral(clk)) {
                 if (!clk->parent)
                         clk->parent = &mck;
+                if (cpu_is_sama5d3())
+                        clk->rate_hz = DIV_ROUND_UP(clk->parent->rate_hz,
+                                                    1 << clk->div);
                 clk->mode = pmc_periph_mode;
         }
         else if (clk_is_sys(clk)) {
@@ -555,7 +596,11 @@ static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg)
         unsigned mul, div;
 
         div = reg & 0xff;
-        mul = (reg >> 16) & 0x7ff;
+        if (cpu_is_sama5d3())
+                mul = AT91_PMC3_MUL_GET(reg);
+        else
+                mul = AT91_PMC_MUL_GET(reg);
+
         if (div && mul) {
                 freq /= div;
                 freq *= mul + 1;
@@ -706,12 +751,15 @@ static int __init at91_pmc_init(unsigned long main_clock)
 
         /* report if PLLA is more than mildly overclocked */
         plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_pmc_read(AT91_CKGR_PLLAR));
-        if (cpu_has_300M_plla()) {
-                if (plla.rate_hz > 300000000)
+        if (cpu_has_1056M_plla()) {
+                if (plla.rate_hz > 1056000000)
                         pll_overclock = true;
         } else if (cpu_has_800M_plla()) {
                 if (plla.rate_hz > 800000000)
                         pll_overclock = true;
+        } else if (cpu_has_300M_plla()) {
+                if (plla.rate_hz > 300000000)
+                        pll_overclock = true;
         } else if (cpu_has_240M_plla()) {
                 if (plla.rate_hz > 240000000)
                         pll_overclock = true;
@@ -872,6 +920,7 @@ int __init at91_clock_init(unsigned long main_clock)
 static int __init at91_clock_reset(void)
 {
         unsigned long pcdr = 0;
+        unsigned long pcdr1 = 0;
         unsigned long scdr = 0;
         struct clk *clk;
 
@@ -879,8 +928,17 @@ static int __init at91_clock_reset(void)
                 if (clk->users > 0)
                         continue;
 
-                if (clk->mode == pmc_periph_mode)
-                        pcdr |= clk->pmc_mask;
+                if (clk->mode == pmc_periph_mode) {
+                        if (cpu_is_sama5d3()) {
+                                u32 pmc_mask = 1 << (clk->pid % 32);
+
+                                if (clk->pid > 31)
+                                        pcdr1 |= pmc_mask;
+                                else
+                                        pcdr |= pmc_mask;
+                        } else
+                                pcdr |= clk->pmc_mask;
+                }
 
                 if (clk->mode == pmc_sys_mode)
                         scdr |= clk->pmc_mask;
@@ -888,8 +946,9 @@ static int __init at91_clock_reset(void)
                 pr_debug("Clocks: disable unused %s\n", clk->name);
         }
 
-        at91_pmc_write(AT91_PMC_PCDR, pcdr);
         at91_pmc_write(AT91_PMC_SCDR, scdr);
+        if (cpu_is_sama5d3())
+                at91_pmc_write(AT91_PMC_PCDR1, pcdr1);
 
         return 0;
 }
diff --git a/arch/arm/mach-at91/clock.h b/arch/arm/mach-at91/clock.h
index c2e63e47dcbe..a98a39bbd883 100644
--- a/arch/arm/mach-at91/clock.h
+++ b/arch/arm/mach-at91/clock.h
@@ -20,7 +20,9 @@ struct clk {
         const char      *name;          /* unique clock name */
         struct clk_lookup cl;
         unsigned long   rate_hz;
+        unsigned        div;            /* parent clock divider */
         struct clk      *parent;
+        unsigned        pid;            /* peripheral ID */
         u32             pmc_mask;
         void            (*mode)(struct clk *, int);
         unsigned        id:3;           /* PCK0..4, or 32k/main/a/b */
diff --git a/arch/arm/mach-at91/cpuidle.c b/arch/arm/mach-at91/cpuidle.c
index 0c6381516a5a..4c6794603780 100644
--- a/arch/arm/mach-at91/cpuidle.c
+++ b/arch/arm/mach-at91/cpuidle.c
@@ -38,6 +38,8 @@ static int at91_enter_idle(struct cpuidle_device *dev,
                 at91rm9200_standby();
         else if (cpu_is_at91sam9g45())
                 at91sam9g45_standby();
+        else if (cpu_is_at91sam9263())
+                at91sam9263_standby();
         else
                 at91sam9_standby();
 
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
index ea2c57a86ca6..31df12029c4e 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -75,6 +75,9 @@ extern void __iomem *at91_pmc_base;
 #define         AT91_PMC_PLLCOUNT       (0x3f  <<  8)           /* PLL Counter */
 #define         AT91_PMC_OUT            (3     << 14)           /* PLL Clock Frequency Range */
 #define         AT91_PMC_MUL            (0x7ff << 16)           /* PLL Multiplier */
+#define         AT91_PMC_MUL_GET(n)     ((n) >> 16 & 0x7ff)
+#define         AT91_PMC3_MUL           (0x7f  << 18)           /* PLL Multiplier [SAMA5 only] */
+#define         AT91_PMC3_MUL_GET(n)    ((n) >> 18 & 0x7f)
 #define         AT91_PMC_USBDIV         (3     << 28)           /* USB Divisor (PLLB only) */
 #define                 AT91_PMC_USBDIV_1               (0 << 28)
 #define                 AT91_PMC_USBDIV_2               (1 << 28)
@@ -167,11 +170,18 @@ extern void __iomem *at91_pmc_base;
 #define         AT91_PMC_WPVS           (0x1  <<  0)            /* Write Protect Violation Status */
 #define         AT91_PMC_WPVSRC         (0xffff  <<  8)         /* Write Protect Violation Source */
 
-#define AT91_PMC_PCR            0x10c                   /* Peripheral Control Register [some SAM9] */
+#define AT91_PMC_PCER1          0x100                   /* Peripheral Clock Enable Register 1 [SAMA5 only]*/
+#define AT91_PMC_PCDR1          0x104                   /* Peripheral Clock Enable Register 1 */
+#define AT91_PMC_PCSR1          0x108                   /* Peripheral Clock Enable Register 1 */
+
+#define AT91_PMC_PCR            0x10c                   /* Peripheral Control Register [some SAM9 and SAMA5] */
 #define         AT91_PMC_PCR_PID        (0x3f  <<  0)           /* Peripheral ID */
-#define         AT91_PMC_PCR_CMD        (0x1  <<  12)           /* Command */
-#define         AT91_PMC_PCR_DIV        (0x3  <<  16)           /* Divisor Value */
-#define         AT91_PMC_PCRDIV(n)      (((n) <<  16) & AT91_PMC_PCR_DIV)
+#define         AT91_PMC_PCR_CMD        (0x1  <<  12)           /* Command (read=0, write=1) */
+#define         AT91_PMC_PCR_DIV(n)     ((n)  <<  16)           /* Divisor Value */
+#define                 AT91_PMC_PCR_DIV0       0x0                     /* Peripheral clock is MCK */
+#define                 AT91_PMC_PCR_DIV2       0x2                     /* Peripheral clock is MCK/2 */
+#define                 AT91_PMC_PCR_DIV4       0x4                     /* Peripheral clock is MCK/4 */
+#define                 AT91_PMC_PCR_DIV8       0x8                     /* Peripheral clock is MCK/8 */
 #define         AT91_PMC_PCR_EN         (0x1  <<  28)           /* Enable */
 
 #endif
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
index b6504c19d55c..d3d7b993846b 100644
--- a/arch/arm/mach-at91/include/mach/cpu.h
+++ b/arch/arm/mach-at91/include/mach/cpu.h
@@ -36,6 +36,8 @@
 #define ARCH_ID_AT91M40807      0x14080745
 #define ARCH_ID_AT91R40008      0x44000840
 
+#define ARCH_ID_SAMA5D3         0x8A5C07C0
+
 #define ARCH_EXID_AT91SAM9M11   0x00000001
 #define ARCH_EXID_AT91SAM9M10   0x00000002
 #define ARCH_EXID_AT91SAM9G46   0x00000003
@@ -47,6 +49,11 @@
 #define ARCH_EXID_AT91SAM9G25   0x00000003
 #define ARCH_EXID_AT91SAM9X25   0x00000004
 
+#define ARCH_EXID_SAMA5D31      0x00444300
+#define ARCH_EXID_SAMA5D33      0x00414300
+#define ARCH_EXID_SAMA5D34      0x00414301
+#define ARCH_EXID_SAMA5D35      0x00584300
+
 #define ARCH_FAMILY_AT91X92     0x09200000
 #define ARCH_FAMILY_AT91SAM9    0x01900000
 #define ARCH_FAMILY_AT91SAM9XE  0x02900000
@@ -75,8 +82,11 @@ enum at91_soc_type {
         /* SAM9N12 */
         AT91_SOC_SAM9N12,
 
+        /* SAMA5D3 */
+        AT91_SOC_SAMA5D3,
+
         /* Unknown type */
-        AT91_SOC_NONE
+        AT91_SOC_UNKNOWN,
 };
 
 enum at91_soc_subtype {
@@ -93,8 +103,15 @@ enum at91_soc_subtype {
         AT91_SOC_SAM9G15, AT91_SOC_SAM9G35, AT91_SOC_SAM9X35,
         AT91_SOC_SAM9G25, AT91_SOC_SAM9X25,
 
+        /* SAMA5D3 */
+        AT91_SOC_SAMA5D31, AT91_SOC_SAMA5D33, AT91_SOC_SAMA5D34,
+        AT91_SOC_SAMA5D35,
+
+        /* No subtype for this SoC */
+        AT91_SOC_SUBTYPE_NONE,
+
         /* Unknown subtype */
-        AT91_SOC_SUBTYPE_NONE
+        AT91_SOC_SUBTYPE_UNKNOWN,
 };
 
 struct at91_socinfo {
@@ -108,7 +125,7 @@ const char *at91_get_soc_subtype(struct at91_socinfo *c);
 
 static inline int at91_soc_is_detected(void)
 {
-        return at91_soc_initdata.type != AT91_SOC_NONE;
+        return at91_soc_initdata.type != AT91_SOC_UNKNOWN;
 }
 
 #ifdef CONFIG_SOC_AT91RM9200
@@ -187,6 +204,12 @@ static inline int at91_soc_is_detected(void)
 #define cpu_is_at91sam9n12()    (0)
 #endif
 
+#ifdef CONFIG_SOC_SAMA5D3
+#define cpu_is_sama5d3()        (at91_soc_initdata.type == AT91_SOC_SAMA5D3)
+#else
+#define cpu_is_sama5d3()        (0)
+#endif
+
 /*
  * Since this is ARM, we will never run on any AVR32 CPU. But these
  * definitions may reduce clutter in common drivers.
diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h
new file mode 100644
index 000000000000..6dc81ee38048
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/sama5d3.h
@@ -0,0 +1,73 @@
+/*
+ * Chip-specific header file for the SAMA5D3 family
+ *
+ *  Copyright (C) 2013 Atmel,
+ *                2013 Ludovic Desroches <ludovic.desroches@atmel.com>
+ *
+ * Common definitions.
+ * Based on SAMA5D3 datasheet.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#ifndef SAMA5D3_H
+#define SAMA5D3_H
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define AT91_ID_FIQ              0      /* Advanced Interrupt Controller (FIQ) */
+#define AT91_ID_SYS              1      /* System Peripherals */
+#define SAMA5D3_ID_DBGU          2      /* debug Unit (usually no special interrupt line) */
+#define AT91_ID_PIT              3      /* PIT */
+#define SAMA5D3_ID_WDT           4      /* Watchdog Timer Interrupt */
+#define SAMA5D3_ID_HSMC          5      /* Static Memory Controller */
+#define SAMA5D3_ID_PIOA          6      /* PIOA */
+#define SAMA5D3_ID_PIOB          7      /* PIOB */
+#define SAMA5D3_ID_PIOC          8      /* PIOC */
+#define SAMA5D3_ID_PIOD          9      /* PIOD */
+#define SAMA5D3_ID_PIOE         10      /* PIOE */
+#define SAMA5D3_ID_SMD          11      /* SMD Soft Modem */
+#define SAMA5D3_ID_USART0       12      /* USART0 */
+#define SAMA5D3_ID_USART1       13      /* USART1 */
+#define SAMA5D3_ID_USART2       14      /* USART2 */
+#define SAMA5D3_ID_USART3       15      /* USART3 */
+#define SAMA5D3_ID_UART0        16      /* UART 0 */
+#define SAMA5D3_ID_UART1        17      /* UART 1 */
+#define SAMA5D3_ID_TWI0         18      /* Two-Wire Interface 0 */
+#define SAMA5D3_ID_TWI1         19      /* Two-Wire Interface 1 */
+#define SAMA5D3_ID_TWI2         20      /* Two-Wire Interface 2 */
+#define SAMA5D3_ID_HSMCI0       21      /* MCI */
+#define SAMA5D3_ID_HSMCI1       22      /* MCI */
+#define SAMA5D3_ID_HSMCI2       23      /* MCI */
+#define SAMA5D3_ID_SPI0         24      /* Serial Peripheral Interface 0 */
+#define SAMA5D3_ID_SPI1         25      /* Serial Peripheral Interface 1 */
+#define SAMA5D3_ID_TC0          26      /* Timer Counter 0 */
+#define SAMA5D3_ID_TC1          27      /* Timer Counter 2 */
+#define SAMA5D3_ID_PWM          28      /* Pulse Width Modulation Controller */
+#define SAMA5D3_ID_ADC          29      /* Touch Screen ADC Controller */
+#define SAMA5D3_ID_DMA0         30      /* DMA Controller 0 */
+#define SAMA5D3_ID_DMA1         31      /* DMA Controller 1 */
+#define SAMA5D3_ID_UHPHS        32      /* USB Host High Speed */
+#define SAMA5D3_ID_UDPHS        33      /* USB Device High Speed */
+#define SAMA5D3_ID_GMAC         34      /* Gigabit Ethernet MAC */
+#define SAMA5D3_ID_EMAC         35      /* Ethernet MAC */
+#define SAMA5D3_ID_LCDC         36      /* LCD Controller */
+#define SAMA5D3_ID_ISI          37      /* Image Sensor Interface */
+#define SAMA5D3_ID_SSC0         38      /* Synchronous Serial Controller 0 */
+#define SAMA5D3_ID_SSC1         39      /* Synchronous Serial Controller 1 */
+#define SAMA5D3_ID_CAN0         40      /* CAN Controller 0 */
+#define SAMA5D3_ID_CAN1         41      /* CAN Controller 1 */
+#define SAMA5D3_ID_SHA          42      /* Secure Hash Algorithm */
+#define SAMA5D3_ID_AES          43      /* Advanced Encryption Standard */
+#define SAMA5D3_ID_TDES         44      /* Triple Data Encryption Standard */
+#define SAMA5D3_ID_TRNG         45      /* True Random Generator Number */
+#define SAMA5D3_ID_IRQ0         47      /* Advanced Interrupt Controller (IRQ0) */
+
+/*
+ * Internal Memory
+ */
+#define SAMA5D3_SRAM_BASE       0x00300000      /* Internal SRAM base address */
+#define SAMA5D3_SRAM_SIZE       (128 * SZ_1K)   /* Internal SRAM size (128Kb) */
+
+#endif
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 73f1f250403a..530db304ec5e 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -270,6 +270,8 @@ static int at91_pm_enter(suspend_state_t state)
                                 at91rm9200_standby();
                         else if (cpu_is_at91sam9g45())
                                 at91sam9g45_standby();
+                        else if (cpu_is_at91sam9263())
+                                at91sam9263_standby();
                         else
                                 at91sam9_standby();
                         break;
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index 38f467c6b710..2f5908f0b8c5 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -70,13 +70,31 @@ static inline void at91sam9g45_standby(void)
         at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
 }
 
-#ifdef CONFIG_SOC_AT91SAM9263
-/*
- * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
- * handle those cases both here and in the Suspend-To-RAM support.
+/* We manage both DDRAM/SDRAM controllers, we need more than one value to
+ * remember.
  */
-#warning Assuming EB1 SDRAM controller is *NOT* used
-#endif
+static inline void at91sam9263_standby(void)
+{
+        u32 lpr0, lpr1;
+        u32 saved_lpr0, saved_lpr1;
+
+        saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
+        lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
+        lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
+
+        saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
+        lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
+        lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
+
+        /* self-refresh mode now */
+        at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
+        at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
+
+        cpu_do_idle();
+
+        at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
+        at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
+}
 
 static inline void at91sam9_standby(void)
 {
diff --git a/arch/arm/mach-at91/sama5d3.c b/arch/arm/mach-at91/sama5d3.c
new file mode 100644
index 000000000000..401279715ab1
--- /dev/null
+++ b/arch/arm/mach-at91/sama5d3.c
@@ -0,0 +1,377 @@
+/*
+ *  Chip-specific setup code for the SAMA5D3 family
+ *
+ *  Copyright (C) 2013 Atmel,
+ *                2013 Ludovic Desroches <ludovic.desroches@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <linux/module.h>
+#include <linux/dma-mapping.h>
+
+#include <asm/irq.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/sama5d3.h>
+#include <mach/at91_pmc.h>
+#include <mach/cpu.h>
+
+#include "soc.h"
+#include "generic.h"
+#include "clock.h"
+#include "sam9_smc.h"
+
+/* --------------------------------------------------------------------
+ *  Clocks
+ * -------------------------------------------------------------------- */
+
+/*
+ * The peripheral clocks.
+ */
+
+static struct clk pioA_clk = {
+        .name           = "pioA_clk",
+        .pid            = SAMA5D3_ID_PIOA,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pioB_clk = {
+        .name           = "pioB_clk",
+        .pid            = SAMA5D3_ID_PIOB,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pioC_clk = {
+        .name           = "pioC_clk",
+        .pid            = SAMA5D3_ID_PIOC,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pioD_clk = {
+        .name           = "pioD_clk",
+        .pid            = SAMA5D3_ID_PIOD,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pioE_clk = {
+        .name           = "pioE_clk",
+        .pid            = SAMA5D3_ID_PIOE,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart0_clk = {
+        .name           = "usart0_clk",
+        .pid            = SAMA5D3_ID_USART0,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV2,
+};
+static struct clk usart1_clk = {
+        .name           = "usart1_clk",
+        .pid            = SAMA5D3_ID_USART1,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV2,
+};
+static struct clk usart2_clk = {
+        .name           = "usart2_clk",
+        .pid            = SAMA5D3_ID_USART2,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV2,
+};
+static struct clk usart3_clk = {
+        .name           = "usart3_clk",
+        .pid            = SAMA5D3_ID_USART3,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV2,
+};
+static struct clk uart0_clk = {
+        .name           = "uart0_clk",
+        .pid            = SAMA5D3_ID_UART0,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV2,
+};
+static struct clk uart1_clk = {
+        .name           = "uart1_clk",
+        .pid            = SAMA5D3_ID_UART1,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV2,
+};
+static struct clk twi0_clk = {
+        .name           = "twi0_clk",
+        .pid            = SAMA5D3_ID_TWI0,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV2,
+};
+static struct clk twi1_clk = {
+        .name           = "twi1_clk",
+        .pid            = SAMA5D3_ID_TWI1,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV2,
+};
+static struct clk twi2_clk = {
+        .name           = "twi2_clk",
+        .pid            = SAMA5D3_ID_TWI2,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV2,
+};
+static struct clk mmc0_clk = {
+        .name           = "mci0_clk",
+        .pid            = SAMA5D3_ID_HSMCI0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk mmc1_clk = {
+        .name           = "mci1_clk",
+        .pid            = SAMA5D3_ID_HSMCI1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk mmc2_clk = {
+        .name           = "mci2_clk",
+        .pid            = SAMA5D3_ID_HSMCI2,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk spi0_clk = {
+        .name           = "spi0_clk",
+        .pid            = SAMA5D3_ID_SPI0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk spi1_clk = {
+        .name           = "spi1_clk",
+        .pid            = SAMA5D3_ID_SPI1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tcb0_clk = {
+        .name           = "tcb0_clk",
+        .pid            = SAMA5D3_ID_TC0,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV2,
+};
+static struct clk tcb1_clk = {
+        .name           = "tcb1_clk",
+        .pid            = SAMA5D3_ID_TC1,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV2,
+};
+static struct clk adc_clk = {
+        .name           = "adc_clk",
+        .pid            = SAMA5D3_ID_ADC,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV2,
+};
+static struct clk adc_op_clk = {
+        .name           = "adc_op_clk",
+        .type           = CLK_TYPE_PERIPHERAL,
+        .rate_hz        = 5000000,
+};
+static struct clk dma0_clk = {
+        .name           = "dma0_clk",
+        .pid            = SAMA5D3_ID_DMA0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk dma1_clk = {
+        .name           = "dma1_clk",
+        .pid            = SAMA5D3_ID_DMA1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk uhphs_clk = {
+        .name           = "uhphs",
+        .pid            = SAMA5D3_ID_UHPHS,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk udphs_clk = {
+        .name           = "udphs_clk",
+        .pid            = SAMA5D3_ID_UDPHS,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+/* gmac only for sama5d33, sama5d34, sama5d35 */
+static struct clk macb0_clk = {
+        .name           = "macb0_clk",
+        .pid            = SAMA5D3_ID_GMAC,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+/* emac only for sama5d31, sama5d35 */
+static struct clk macb1_clk = {
+        .name           = "macb1_clk",
+        .pid            = SAMA5D3_ID_EMAC,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+/* lcd only for sama5d31, sama5d33, sama5d34 */
+static struct clk lcdc_clk = {
+        .name           = "lcdc_clk",
+        .pid            = SAMA5D3_ID_LCDC,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+/* isi only for sama5d33, sama5d35 */
+static struct clk isi_clk = {
+        .name           = "isi_clk",
+        .pid            = SAMA5D3_ID_ISI,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk can0_clk = {
+        .name           = "can0_clk",
+        .pid            = SAMA5D3_ID_CAN0,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV2,
+};
+static struct clk can1_clk = {
+        .name           = "can1_clk",
+        .pid            = SAMA5D3_ID_CAN1,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV2,
+};
+static struct clk ssc0_clk = {
+        .name           = "ssc0_clk",
+        .pid            = SAMA5D3_ID_SSC0,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV2,
+};
+static struct clk ssc1_clk = {
+        .name           = "ssc1_clk",
+        .pid            = SAMA5D3_ID_SSC1,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV2,
+};
+static struct clk sha_clk = {
+        .name           = "sha_clk",
+        .pid            = SAMA5D3_ID_SHA,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV8,
+};
+static struct clk aes_clk = {
+        .name           = "aes_clk",
+        .pid            = SAMA5D3_ID_AES,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tdes_clk = {
+        .name           = "tdes_clk",
+        .pid            = SAMA5D3_ID_TDES,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+
+static struct clk *periph_clocks[] __initdata = {
+        &pioA_clk,
+        &pioB_clk,
+        &pioC_clk,
+        &pioD_clk,
+        &pioE_clk,
+        &usart0_clk,
+        &usart1_clk,
+        &usart2_clk,
+        &usart3_clk,
+        &uart0_clk,
+        &uart1_clk,
+        &twi0_clk,
+        &twi1_clk,
+        &twi2_clk,
+        &mmc0_clk,
+        &mmc1_clk,
+        &mmc2_clk,
+        &spi0_clk,
+        &spi1_clk,
+        &tcb0_clk,
+        &tcb1_clk,
+        &adc_clk,
+        &adc_op_clk,
+        &dma0_clk,
+        &dma1_clk,
+        &uhphs_clk,
+        &udphs_clk,
+        &macb0_clk,
+        &macb1_clk,
+        &lcdc_clk,
+        &isi_clk,
+        &can0_clk,
+        &can1_clk,
+        &ssc0_clk,
+        &ssc1_clk,
+        &sha_clk,
+        &aes_clk,
+        &tdes_clk,
+};
+
+static struct clk pck0 = {
+        .name           = "pck0",
+        .pmc_mask       = AT91_PMC_PCK0,
+        .type           = CLK_TYPE_PROGRAMMABLE,
+        .id             = 0,
+};
+
+static struct clk pck1 = {
+        .name           = "pck1",
+        .pmc_mask       = AT91_PMC_PCK1,
+        .type           = CLK_TYPE_PROGRAMMABLE,
+        .id             = 1,
+};
+
+static struct clk pck2 = {
+        .name           = "pck2",
+        .pmc_mask       = AT91_PMC_PCK2,
+        .type           = CLK_TYPE_PROGRAMMABLE,
+        .id             = 2,
+};
+
+static struct clk_lookup periph_clocks_lookups[] = {
+        /* lookup table for DT entries */
+        CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
+        CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioC_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioD_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioE_clk),
+        CLKDEV_CON_DEV_ID("usart", "f001c000.serial", &usart0_clk),
+        CLKDEV_CON_DEV_ID("usart", "f0020000.serial", &usart1_clk),
+        CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart2_clk),
+        CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart3_clk),
+        CLKDEV_CON_DEV_ID(NULL, "f0014000.i2c", &twi0_clk),
+        CLKDEV_CON_DEV_ID(NULL, "f0018000.i2c", &twi1_clk),
+        CLKDEV_CON_DEV_ID(NULL, "f801c000.i2c", &twi2_clk),
+        CLKDEV_CON_DEV_ID("mci_clk", "f0000000.mmc", &mmc0_clk),
+        CLKDEV_CON_DEV_ID("mci_clk", "f8000000.mmc", &mmc1_clk),
+        CLKDEV_CON_DEV_ID("mci_clk", "f8004000.mmc", &mmc2_clk),
+        CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi0_clk),
+        CLKDEV_CON_DEV_ID("spi_clk", "f8008000.spi", &spi1_clk),
+        CLKDEV_CON_DEV_ID("t0_clk", "f0010000.timer", &tcb0_clk),
+        CLKDEV_CON_DEV_ID("t0_clk", "f8014000.timer", &tcb1_clk),
+        CLKDEV_CON_DEV_ID("tsc_clk", "f8018000.tsadcc", &adc_clk),
+        CLKDEV_CON_DEV_ID("dma_clk", "ffffe600.dma-controller", &dma0_clk),
+        CLKDEV_CON_DEV_ID("dma_clk", "ffffe800.dma-controller", &dma1_clk),
+        CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk),
+        CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk),
+        CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk),
+        CLKDEV_CON_DEV_ID("pclk", "500000.gadget", &udphs_clk),
+        CLKDEV_CON_DEV_ID("hclk", "500000.gadget", &utmi_clk),
+        CLKDEV_CON_DEV_ID("hclk", "f0028000.ethernet", &macb0_clk),
+        CLKDEV_CON_DEV_ID("pclk", "f0028000.ethernet", &macb0_clk),
+        CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb1_clk),
+        CLKDEV_CON_DEV_ID("pclk", "f802c000.ethernet", &macb1_clk),
+        CLKDEV_CON_DEV_ID("pclk", "f0008000.ssc", &ssc0_clk),
+        CLKDEV_CON_DEV_ID("pclk", "f000c000.ssc", &ssc1_clk),
+        CLKDEV_CON_DEV_ID("can_clk", "f000c000.can", &can0_clk),
+        CLKDEV_CON_DEV_ID("can_clk", "f8010000.can", &can1_clk),
+        CLKDEV_CON_DEV_ID("sha_clk", "f8034000.sha", &sha_clk),
+        CLKDEV_CON_DEV_ID("aes_clk", "f8038000.aes", &aes_clk),
+        CLKDEV_CON_DEV_ID("tdes_clk", "f803c000.tdes", &tdes_clk),
+};
+
+static void __init sama5d3_register_clocks(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
+                clk_register(periph_clocks[i]);
+
+        clkdev_add_table(periph_clocks_lookups,
+                         ARRAY_SIZE(periph_clocks_lookups));
+
+        clk_register(&pck0);
+        clk_register(&pck1);
+        clk_register(&pck2);
+}
+
+/* --------------------------------------------------------------------
+ *  AT91SAM9x5 processor initialization
+ * -------------------------------------------------------------------- */
+
+static void __init sama5d3_map_io(void)
+{
+        at91_init_sram(0, SAMA5D3_SRAM_BASE, SAMA5D3_SRAM_SIZE);
+}
+
+AT91_SOC_START(sama5d3)
+        .map_io = sama5d3_map_io,
+        .register_clocks = sama5d3_register_clocks,
+AT91_SOC_END
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 4b678478cf95..fd00a09da86b 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -105,28 +105,32 @@ static void __init soc_detect(u32 dbgu_base)
         switch (socid) {
         case ARCH_ID_AT91RM9200:
                 at91_soc_initdata.type = AT91_SOC_RM9200;
-                if (at91_soc_initdata.subtype == AT91_SOC_SUBTYPE_NONE)
+                if (at91_soc_initdata.subtype == AT91_SOC_SUBTYPE_UNKNOWN)
                         at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
                 at91_boot_soc = at91rm9200_soc;
                 break;
 
         case ARCH_ID_AT91SAM9260:
                 at91_soc_initdata.type = AT91_SOC_SAM9260;
+                at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
                 at91_boot_soc = at91sam9260_soc;
                 break;
 
         case ARCH_ID_AT91SAM9261:
                 at91_soc_initdata.type = AT91_SOC_SAM9261;
+                at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
                 at91_boot_soc = at91sam9261_soc;
                 break;
 
         case ARCH_ID_AT91SAM9263:
                 at91_soc_initdata.type = AT91_SOC_SAM9263;
+                at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
                 at91_boot_soc = at91sam9263_soc;
                 break;
 
         case ARCH_ID_AT91SAM9G20:
                 at91_soc_initdata.type = AT91_SOC_SAM9G20;
+                at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
                 at91_boot_soc = at91sam9260_soc;
                 break;
 
@@ -139,6 +143,7 @@ static void __init soc_detect(u32 dbgu_base)
 
         case ARCH_ID_AT91SAM9RL64:
                 at91_soc_initdata.type = AT91_SOC_SAM9RL;
+                at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
                 at91_boot_soc = at91sam9rl_soc;
                 break;
 
@@ -151,11 +156,17 @@ static void __init soc_detect(u32 dbgu_base)
                 at91_soc_initdata.type = AT91_SOC_SAM9N12;
                 at91_boot_soc = at91sam9n12_soc;
                 break;
+
+        case ARCH_ID_SAMA5D3:
+                at91_soc_initdata.type = AT91_SOC_SAMA5D3;
+                at91_boot_soc = sama5d3_soc;
+                break;
         }
 
         /* at91sam9g10 */
         if ((socid & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
                 at91_soc_initdata.type = AT91_SOC_SAM9G10;
+                at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
                 at91_boot_soc = at91sam9261_soc;
         }
         /* at91sam9xe */
@@ -206,6 +217,23 @@ static void __init soc_detect(u32 dbgu_base)
                         break;
                 }
         }
+
+        if (at91_soc_initdata.type == AT91_SOC_SAMA5D3) {
+                switch (at91_soc_initdata.exid) {
+                case ARCH_EXID_SAMA5D31:
+                        at91_soc_initdata.subtype = AT91_SOC_SAMA5D31;
+                        break;
+                case ARCH_EXID_SAMA5D33:
+                        at91_soc_initdata.subtype = AT91_SOC_SAMA5D33;
+                        break;
+                case ARCH_EXID_SAMA5D34:
+                        at91_soc_initdata.subtype = AT91_SOC_SAMA5D34;
+                        break;
+                case ARCH_EXID_SAMA5D35:
+                        at91_soc_initdata.subtype = AT91_SOC_SAMA5D35;
+                        break;
+                }
+        }
 }
 
 static const char *soc_name[] = {
@@ -219,7 +247,8 @@ static const char *soc_name[] = {
         [AT91_SOC_SAM9RL]       = "at91sam9rl",
         [AT91_SOC_SAM9X5]       = "at91sam9x5",
         [AT91_SOC_SAM9N12]      = "at91sam9n12",
-        [AT91_SOC_NONE]         = "Unknown"
+        [AT91_SOC_SAMA5D3]      = "sama5d3",
+        [AT91_SOC_UNKNOWN]      = "Unknown",
 };
 
 const char *at91_get_soc_type(struct at91_socinfo *c)
@@ -241,7 +270,12 @@ static const char *soc_subtype_name[] = {
         [AT91_SOC_SAM9X35]      = "at91sam9x35",
         [AT91_SOC_SAM9G25]      = "at91sam9g25",
         [AT91_SOC_SAM9X25]      = "at91sam9x25",
-        [AT91_SOC_SUBTYPE_NONE] = "Unknown"
+        [AT91_SOC_SAMA5D31]     = "sama5d31",
+        [AT91_SOC_SAMA5D33]     = "sama5d33",
+        [AT91_SOC_SAMA5D34]     = "sama5d34",
+        [AT91_SOC_SAMA5D35]     = "sama5d35",
+        [AT91_SOC_SUBTYPE_NONE] = "None",
+        [AT91_SOC_SUBTYPE_UNKNOWN] = "Unknown",
 };
 
 const char *at91_get_soc_subtype(struct at91_socinfo *c)
@@ -255,8 +289,8 @@ void __init at91_map_io(void)
         /* Map peripherals */
         iotable_init(&at91_io_desc, 1);
 
-        at91_soc_initdata.type = AT91_SOC_NONE;
-        at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
+        at91_soc_initdata.type = AT91_SOC_UNKNOWN;
+        at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_UNKNOWN;
 
         soc_detect(AT91_BASE_DBGU0);
         if (!at91_soc_is_detected())
@@ -267,8 +301,9 @@ void __init at91_map_io(void)
 
         pr_info("AT91: Detected soc type: %s\n",
                 at91_get_soc_type(&at91_soc_initdata));
-        pr_info("AT91: Detected soc subtype: %s\n",
-                at91_get_soc_subtype(&at91_soc_initdata));
+        if (at91_soc_initdata.subtype != AT91_SOC_SUBTYPE_NONE)
+                pr_info("AT91: Detected soc subtype: %s\n",
+                        at91_get_soc_subtype(&at91_soc_initdata));
 
         if (!at91_soc_is_enabled())
                 panic("AT91: Soc not enabled");
diff --git a/arch/arm/mach-at91/soc.h b/arch/arm/mach-at91/soc.h
index 9c6d3d4f9a23..43a225f9e713 100644
--- a/arch/arm/mach-at91/soc.h
+++ b/arch/arm/mach-at91/soc.h
@@ -22,9 +22,10 @@ extern struct at91_init_soc at91sam9g45_soc;
 extern struct at91_init_soc at91sam9rl_soc;
 extern struct at91_init_soc at91sam9x5_soc;
 extern struct at91_init_soc at91sam9n12_soc;
+extern struct at91_init_soc sama5d3_soc;
 
 #define AT91_SOC_START(_name)                           \
-struct at91_init_soc __initdata at91##_name##_soc       \
+struct at91_init_soc __initdata _name##_soc             \
  __used                                                 \
                                                 = {     \
         .builtin        = 1,                            \
@@ -68,3 +69,7 @@ static inline int at91_soc_is_enabled(void)
 #if !defined(CONFIG_SOC_AT91SAM9N12)
 #define at91sam9n12_soc at91_boot_soc
 #endif
+
+#if !defined(CONFIG_SOC_SAMA5D3)
+#define sama5d3_soc     at91_boot_soc
+#endif
diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c
index e698f26cc0cb..52e4bb5cf12d 100644
--- a/arch/arm/mach-cns3xxx/core.c
+++ b/arch/arm/mach-cns3xxx/core.c
@@ -22,19 +22,9 @@
 
 static struct map_desc cns3xxx_io_desc[] __initdata = {
         {
-                .virtual        = CNS3XXX_TC11MP_TWD_BASE_VIRT,
-                .pfn            = __phys_to_pfn(CNS3XXX_TC11MP_TWD_BASE),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT,
-                .pfn            = __phys_to_pfn(CNS3XXX_TC11MP_GIC_CPU_BASE),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT,
-                .pfn            = __phys_to_pfn(CNS3XXX_TC11MP_GIC_DIST_BASE),
-                .length         = SZ_4K,
+                .virtual        = CNS3XXX_TC11MP_SCU_BASE_VIRT,
+                .pfn            = __phys_to_pfn(CNS3XXX_TC11MP_SCU_BASE),
+                .length         = SZ_8K,
                 .type           = MT_DEVICE,
         }, {
                 .virtual        = CNS3XXX_TIMER1_2_3_BASE_VIRT,
diff --git a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
index 191c8e57f289..b1021aafa481 100644
--- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
+++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
@@ -94,10 +94,10 @@
 #define RTC_INTR_STS_OFFSET                     0x34
 
 #define CNS3XXX_MISC_BASE                       0x76000000      /* Misc Control */
-#define CNS3XXX_MISC_BASE_VIRT                  0xFFF07000      /* Misc Control */
+#define CNS3XXX_MISC_BASE_VIRT                  0xFB000000      /* Misc Control */
 
 #define CNS3XXX_PM_BASE                         0x77000000      /* Power Management Control */
-#define CNS3XXX_PM_BASE_VIRT                    0xFFF08000
+#define CNS3XXX_PM_BASE_VIRT                    0xFB001000
 
 #define PM_CLK_GATE_OFFSET                      0x00
 #define PM_SOFT_RST_OFFSET                      0x04
@@ -109,7 +109,7 @@
 #define PM_PLL_HM_PD_OFFSET                     0x1C
 
 #define CNS3XXX_UART0_BASE                      0x78000000      /* UART 0 */
-#define CNS3XXX_UART0_BASE_VIRT                 0xFFF09000
+#define CNS3XXX_UART0_BASE_VIRT                 0xFB002000
 
 #define CNS3XXX_UART1_BASE                      0x78400000      /* UART 1 */
 #define CNS3XXX_UART1_BASE_VIRT                 0xFFF0A000
@@ -130,7 +130,7 @@
 #define CNS3XXX_I2S_BASE_VIRT                   0xFFF10000
 
 #define CNS3XXX_TIMER1_2_3_BASE                 0x7C800000      /* Timer */
-#define CNS3XXX_TIMER1_2_3_BASE_VIRT            0xFFF10800
+#define CNS3XXX_TIMER1_2_3_BASE_VIRT            0xFB003000
 
 #define TIMER1_COUNTER_OFFSET                   0x00
 #define TIMER1_AUTO_RELOAD_OFFSET               0x04
@@ -227,16 +227,16 @@
  * Testchip peripheral and fpga gic regions
  */
 #define CNS3XXX_TC11MP_SCU_BASE                 0x90000000      /* IRQ, Test chip */
-#define CNS3XXX_TC11MP_SCU_BASE_VIRT            0xFF000000
+#define CNS3XXX_TC11MP_SCU_BASE_VIRT            0xFB004000
 
 #define CNS3XXX_TC11MP_GIC_CPU_BASE             0x90000100      /* Test chip interrupt controller CPU interface */
-#define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT        0xFF000100
+#define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT        (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x100)
 
 #define CNS3XXX_TC11MP_TWD_BASE                 0x90000600
-#define CNS3XXX_TC11MP_TWD_BASE_VIRT            0xFF000600
+#define CNS3XXX_TC11MP_TWD_BASE_VIRT            (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x600)
 
 #define CNS3XXX_TC11MP_GIC_DIST_BASE            0x90001000      /* Test chip interrupt controller distributor */
-#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT       0xFF001000
+#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT       (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x1000)
 
 #define CNS3XXX_TC11MP_L220_BASE                0x92002000      /* L220 registers */
 #define CNS3XXX_TC11MP_L220_BASE_VIRT           0xFF002000
diff --git a/arch/arm/mach-ep93xx/include/mach/uncompress.h b/arch/arm/mach-ep93xx/include/mach/uncompress.h
index d2afb4dd82ab..b5cc77d2380b 100644
--- a/arch/arm/mach-ep93xx/include/mach/uncompress.h
+++ b/arch/arm/mach-ep93xx/include/mach/uncompress.h
@@ -47,9 +47,13 @@ static void __raw_writel(unsigned int value, unsigned int ptr)
 
 static inline void putc(int c)
 {
-        /* Transmit fifo not full?  */
-        while (__raw_readb(PHYS_UART_FLAG) & UART_FLAG_TXFF)
-                ;
+        int i;
+
+        for (i = 0; i < 10000; i++) {
+                /* Transmit fifo not full? */
+                if (!(__raw_readb(PHYS_UART_FLAG) & UART_FLAG_TXFF))
+                        break;
+        }
 
         __raw_writeb(c, PHYS_UART_DATA);
 }
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 2f45906d6ee5..faca4326b46a 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -79,12 +79,6 @@ config SOC_EXYNOS5440
         help
           Enable EXYNOS5440 SoC support
 
-config EXYNOS4_MCT
-        bool
-        default y
-        help
-          Use MCT (Multi Core Timer) as kernel timers
-
 config EXYNOS_DEV_DMA
         bool
         help
@@ -406,6 +400,7 @@ config MACH_EXYNOS4_DT
         bool "Samsung Exynos4 Machine using device tree"
         depends on ARCH_EXYNOS4
         select ARM_AMBA
+        select CLKSRC_OF
         select CPU_EXYNOS4210
         select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD
         select PINCTRL
@@ -422,6 +417,7 @@ config MACH_EXYNOS5_DT
         default y
         depends on ARCH_EXYNOS5
         select ARM_AMBA
+        select CLKSRC_OF
         select USE_OF
         help
           Machine support for Samsung EXYNOS5 machine with device tree enabled.
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 435757e57bb4..daf289b21486 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -26,8 +26,6 @@ obj-$(CONFIG_ARCH_EXYNOS)	+= pmu.o
 
 obj-$(CONFIG_SMP)               += platsmp.o headsmp.o
 
-obj-$(CONFIG_EXYNOS4_MCT)       += mct.o
-
 obj-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
 
 # machine support
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index bdd957978d9b..db7dbd0eb6b4 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -257,11 +257,6 @@ static struct map_desc exynos5_iodesc[] __initdata = {
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = (unsigned long)S5P_VA_SYSTIMER,
-                .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSTIMER),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
                 .length         = SZ_4K,
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 9339bb8954be..3b186eaaaa7b 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -12,7 +12,7 @@
 #ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
 #define __ARCH_ARM_MACH_EXYNOS_COMMON_H
 
-extern void exynos4_timer_init(void);
+extern void mct_init(void);
 
 struct map_desc;
 void exynos_init_io(struct map_desc *mach_desc, int size);
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index 1f4dc35cd4b9..c0e75d8dd737 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -30,8 +30,6 @@
 
 /* For EXYNOS4 and EXYNOS5 */
 
-#define EXYNOS_IRQ_MCT_LOCALTIMER       IRQ_PPI(12)
-
 #define EXYNOS_IRQ_EINT16_31            IRQ_SPI(32)
 
 /* For EXYNOS4 SoCs */
@@ -323,8 +321,6 @@
 #define EXYNOS5_IRQ_CEC                 IRQ_SPI(114)
 #define EXYNOS5_IRQ_SATA                IRQ_SPI(115)
 
-#define EXYNOS5_IRQ_MCT_L0              IRQ_SPI(120)
-#define EXYNOS5_IRQ_MCT_L1              IRQ_SPI(121)
 #define EXYNOS5_IRQ_MMC44               IRQ_SPI(123)
 #define EXYNOS5_IRQ_MDMA1               IRQ_SPI(124)
 #define EXYNOS5_IRQ_FIMC_LITE0          IRQ_SPI(125)
@@ -419,8 +415,6 @@
 #define EXYNOS5_IRQ_PMU_CPU1            COMBINER_IRQ(22, 4)
 
 #define EXYNOS5_IRQ_EINT0               COMBINER_IRQ(23, 0)
-#define EXYNOS5_IRQ_MCT_G0              COMBINER_IRQ(23, 3)
-#define EXYNOS5_IRQ_MCT_G1              COMBINER_IRQ(23, 4)
 
 #define EXYNOS5_IRQ_EINT1               COMBINER_IRQ(24, 0)
 #define EXYNOS5_IRQ_SYSMMU_LITE1_0      COMBINER_IRQ(24, 1)
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 1df6abbf53b8..7f99b7b187d6 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -65,7 +65,6 @@
 #define EXYNOS5_PA_CMU                  0x10010000
 
 #define EXYNOS4_PA_SYSTIMER             0x10050000
-#define EXYNOS5_PA_SYSTIMER             0x101C0000
 
 #define EXYNOS4_PA_WATCHDOG             0x10060000
 #define EXYNOS5_PA_WATCHDOG             0x101D0000
diff --git a/arch/arm/mach-exynos/include/mach/regs-mct.h b/arch/arm/mach-exynos/include/mach/regs-mct.h
deleted file mode 100644
index 80dd02ad6d61..000000000000
--- a/arch/arm/mach-exynos/include/mach/regs-mct.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* arch/arm/mach-exynos4/include/mach/regs-mct.h
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4 MCT configutation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_REGS_MCT_H
-#define __ASM_ARCH_REGS_MCT_H __FILE__
-
-#include <mach/map.h>
-
-#define EXYNOS4_MCTREG(x)               (S5P_VA_SYSTIMER + (x))
-
-#define EXYNOS4_MCT_G_CNT_L             EXYNOS4_MCTREG(0x100)
-#define EXYNOS4_MCT_G_CNT_U             EXYNOS4_MCTREG(0x104)
-#define EXYNOS4_MCT_G_CNT_WSTAT         EXYNOS4_MCTREG(0x110)
-
-#define EXYNOS4_MCT_G_COMP0_L           EXYNOS4_MCTREG(0x200)
-#define EXYNOS4_MCT_G_COMP0_U           EXYNOS4_MCTREG(0x204)
-#define EXYNOS4_MCT_G_COMP0_ADD_INCR    EXYNOS4_MCTREG(0x208)
-
-#define EXYNOS4_MCT_G_TCON              EXYNOS4_MCTREG(0x240)
-
-#define EXYNOS4_MCT_G_INT_CSTAT         EXYNOS4_MCTREG(0x244)
-#define EXYNOS4_MCT_G_INT_ENB           EXYNOS4_MCTREG(0x248)
-#define EXYNOS4_MCT_G_WSTAT             EXYNOS4_MCTREG(0x24C)
-
-#define _EXYNOS4_MCT_L_BASE             EXYNOS4_MCTREG(0x300)
-#define EXYNOS4_MCT_L_BASE(x)           (_EXYNOS4_MCT_L_BASE + (0x100 * x))
-#define EXYNOS4_MCT_L_MASK              (0xffffff00)
-
-#define MCT_L_TCNTB_OFFSET              (0x00)
-#define MCT_L_ICNTB_OFFSET              (0x08)
-#define MCT_L_TCON_OFFSET               (0x20)
-#define MCT_L_INT_CSTAT_OFFSET          (0x30)
-#define MCT_L_INT_ENB_OFFSET            (0x34)
-#define MCT_L_WSTAT_OFFSET              (0x40)
-
-#define MCT_G_TCON_START                (1 << 8)
-#define MCT_G_TCON_COMP0_AUTO_INC       (1 << 1)
-#define MCT_G_TCON_COMP0_ENABLE         (1 << 0)
-
-#define MCT_L_TCON_INTERVAL_MODE        (1 << 2)
-#define MCT_L_TCON_INT_START            (1 << 1)
-#define MCT_L_TCON_TIMER_START          (1 << 0)
-
-#endif /* __ASM_ARCH_REGS_MCT_H */
diff --git a/arch/arm/mach-exynos/mach-armlex4210.c b/arch/arm/mach-exynos/mach-armlex4210.c
index 685f29173afa..3b1a34742679 100644
--- a/arch/arm/mach-exynos/mach-armlex4210.c
+++ b/arch/arm/mach-exynos/mach-armlex4210.c
@@ -202,6 +202,6 @@ MACHINE_START(ARMLEX4210, "ARMLEX4210")
         .map_io         = armlex4210_map_io,
         .init_machine   = armlex4210_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = exynos4_timer_init,
+        .init_time      = mct_init,
         .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
index 3358088c822a..c4ae108e192d 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -13,6 +13,7 @@
 
 #include <linux/of_platform.h>
 #include <linux/serial_core.h>
+#include <linux/clocksource.h>
 
 #include <asm/mach/arch.h>
 #include <mach/map.h>
@@ -142,7 +143,7 @@ DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
         .map_io         = exynos4_dt_map_io,
         .init_machine   = exynos4_dt_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = exynos4_timer_init,
+        .init_time      = clocksource_of_init,
         .dt_compat      = exynos4_dt_compat,
         .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index acaeb14db54b..be7eaac0df01 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -14,6 +14,7 @@
 #include <linux/serial_core.h>
 #include <linux/memblock.h>
 #include <linux/io.h>
+#include <linux/clocksource.h>
 
 #include <asm/mach/arch.h>
 #include <mach/map.h>
@@ -216,7 +217,6 @@ DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
         .map_io         = exynos5_dt_map_io,
         .init_machine   = exynos5_dt_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = exynos4_timer_init,
         .dt_compat      = exynos5_dt_compat,
         .restart        = exynos5_restart,
         .reserve        = exynos5_reserve,
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index 1ea79730187f..da3605d15110 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -1380,7 +1380,7 @@ MACHINE_START(NURI, "NURI")
         .map_io         = nuri_map_io,
         .init_machine   = nuri_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = exynos4_timer_init,
+        .init_time      = mct_init,
         .reserve        = &nuri_reserve,
         .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index 579d2d171daa..1772cd284f4c 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -815,7 +815,7 @@ MACHINE_START(ORIGEN, "ORIGEN")
         .map_io         = origen_map_io,
         .init_machine   = origen_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = exynos4_timer_init,
+        .init_time      = mct_init,
         .reserve        = &origen_reserve,
         .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-smdk4x12.c b/arch/arm/mach-exynos/mach-smdk4x12.c
index fe6149624b84..34a6356364eb 100644
--- a/arch/arm/mach-exynos/mach-smdk4x12.c
+++ b/arch/arm/mach-exynos/mach-smdk4x12.c
@@ -376,7 +376,7 @@ MACHINE_START(SMDK4212, "SMDK4212")
         .init_irq       = exynos4_init_irq,
         .map_io         = smdk4x12_map_io,
         .init_machine   = smdk4x12_machine_init,
-        .init_time      = exynos4_timer_init,
+        .init_time      = mct_init,
         .restart        = exynos4_restart,
         .reserve        = &smdk4x12_reserve,
 MACHINE_END
@@ -390,7 +390,7 @@ MACHINE_START(SMDK4412, "SMDK4412")
         .map_io         = smdk4x12_map_io,
         .init_machine   = smdk4x12_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = exynos4_timer_init,
+        .init_time      = mct_init,
         .restart        = exynos4_restart,
         .reserve        = &smdk4x12_reserve,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
index d71672922b19..893b14e8c62a 100644
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -423,7 +423,7 @@ MACHINE_START(SMDKV310, "SMDKV310")
         .init_irq       = exynos4_init_irq,
         .map_io         = smdkv310_map_io,
         .init_machine   = smdkv310_machine_init,
-        .init_time      = exynos4_timer_init,
+        .init_time      = mct_init,
         .reserve        = &smdkv310_reserve,
         .restart        = exynos4_restart,
 MACHINE_END
@@ -436,7 +436,7 @@ MACHINE_START(SMDKC210, "SMDKC210")
         .map_io         = smdkv310_map_io,
         .init_machine   = smdkv310_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = exynos4_timer_init,
+        .init_time      = mct_init,
         .reserve        = &smdkv310_reserve,
         .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
index 76c1170b3528..e7df2dd43a40 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -15,6 +15,7 @@
  */
 #include <linux/clk.h>
 #include <linux/clkdev.h>
+#include <linux/clocksource.h>
 #include <linux/dma-mapping.h>
 #include <linux/io.h>
 #include <linux/irq.h>
@@ -28,12 +29,9 @@
 #include <linux/amba/bus.h>
 #include <linux/clk-provider.h>
 
-#include <asm/arch_timer.h>
 #include <asm/cacheflush.h>
 #include <asm/cputype.h>
 #include <asm/smp_plat.h>
-#include <asm/hardware/arm_timer.h>
-#include <asm/hardware/timer-sp.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -90,36 +88,16 @@ static void __init highbank_init_irq(void)
 #endif
 }
 
-static struct clk_lookup lookup = {
-        .dev_id = "sp804",
-        .con_id = NULL,
-};
-
 static void __init highbank_timer_init(void)
 {
-        int irq;
         struct device_node *np;
-        void __iomem *timer_base;
 
         /* Map system registers */
         np = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs");
         sregs_base = of_iomap(np, 0);
         WARN_ON(!sregs_base);
 
-        np = of_find_compatible_node(NULL, NULL, "arm,sp804");
-        timer_base = of_iomap(np, 0);
-        WARN_ON(!timer_base);
-        irq = irq_of_parse_and_map(np, 0);
-
         of_clk_init(NULL);
-        lookup.clk = of_clk_get(np, 0);
-        clkdev_add(&lookup);
-
-        sp804_clocksource_and_sched_clock_init(timer_base + 0x20, "timer1");
-        sp804_clockevents_init(timer_base, irq, "timer0");
-
-        arch_timer_of_register();
-        arch_timer_sched_clock_init();
 
         clocksource_of_init();
 }
diff --git a/arch/arm/mach-imx/clk-busy.c b/arch/arm/mach-imx/clk-busy.c
index 1ab91b5209e6..85b728cc27ab 100644
--- a/arch/arm/mach-imx/clk-busy.c
+++ b/arch/arm/mach-imx/clk-busy.c
@@ -169,7 +169,7 @@ struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
 
         busy->mux.reg = reg;
         busy->mux.shift = shift;
-        busy->mux.width = width;
+        busy->mux.mask = BIT(width) - 1;
         busy->mux.lock = &imx_ccm_lock;
         busy->mux_ops = &clk_mux_ops;
 
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 5a800bfcec5b..5bf4a97ab241 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -110,6 +110,8 @@ void tzic_handle_irq(struct pt_regs *);
 
 extern void imx_enable_cpu(int cpu, bool enable);
 extern void imx_set_cpu_jump(int cpu, void *jump_addr);
+extern u32 imx_get_cpu_arg(int cpu);
+extern void imx_set_cpu_arg(int cpu, u32 arg);
 extern void v7_cpu_resume(void);
 extern u32 *pl310_get_save_ptr(void);
 #ifdef CONFIG_SMP
diff --git a/arch/arm/mach-imx/hotplug.c b/arch/arm/mach-imx/hotplug.c
index 7bc5fe15dda2..361a253e2b63 100644
--- a/arch/arm/mach-imx/hotplug.c
+++ b/arch/arm/mach-imx/hotplug.c
@@ -46,11 +46,23 @@ static inline void cpu_enter_lowpower(void)
 void imx_cpu_die(unsigned int cpu)
 {
         cpu_enter_lowpower();
+        /*
+         * We use the cpu jumping argument register to sync with
+         * imx_cpu_kill() which is running on cpu0 and waiting for
+         * the register being cleared to kill the cpu.
+         */
+        imx_set_cpu_arg(cpu, ~0);
         cpu_do_idle();
 }
 
 int imx_cpu_kill(unsigned int cpu)
 {
+        unsigned long timeout = jiffies + msecs_to_jiffies(50);
+
+        while (imx_get_cpu_arg(cpu) == 0)
+                if (time_after(jiffies, timeout))
+                        return 0;
         imx_enable_cpu(cpu, false);
+        imx_set_cpu_arg(cpu, 0);
         return 1;
 }
diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c
index e15f1555c59b..09a742f8c7ab 100644
--- a/arch/arm/mach-imx/src.c
+++ b/arch/arm/mach-imx/src.c
@@ -43,6 +43,18 @@ void imx_set_cpu_jump(int cpu, void *jump_addr)
                        src_base + SRC_GPR1 + cpu * 8);
 }
 
+u32 imx_get_cpu_arg(int cpu)
+{
+        cpu = cpu_logical_map(cpu);
+        return readl_relaxed(src_base + SRC_GPR1 + cpu * 8 + 4);
+}
+
+void imx_set_cpu_arg(int cpu, u32 arg)
+{
+        cpu = cpu_logical_map(cpu);
+        writel_relaxed(arg, src_base + SRC_GPR1 + cpu * 8 + 4);
+}
+
 void imx_src_prepare_restart(void)
 {
         u32 val;
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index da1091be0887..8c60fcb08a98 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -250,39 +250,6 @@ static void __init intcp_init_early(void)
 }
 
 #ifdef CONFIG_OF
-
-static void __init cp_of_timer_init(void)
-{
-        struct device_node *node;
-        const char *path;
-        void __iomem *base;
-        int err;
-        int irq;
-
-        err = of_property_read_string(of_aliases,
-                                "arm,timer-primary", &path);
-        if (WARN_ON(err))
-                return;
-        node = of_find_node_by_path(path);
-        base = of_iomap(node, 0);
-        if (WARN_ON(!base))
-                return;
-        writel(0, base + TIMER_CTRL);
-        sp804_clocksource_init(base, node->name);
-
-        err = of_property_read_string(of_aliases,
-                                "arm,timer-secondary", &path);
-        if (WARN_ON(err))
-                return;
-        node = of_find_node_by_path(path);
-        base = of_iomap(node, 0);
-        if (WARN_ON(!base))
-                return;
-        irq = irq_of_parse_and_map(node, 0);
-        writel(0, base + TIMER_CTRL);
-        sp804_clockevents_init(base, irq, node->name);
-}
-
 static const struct of_device_id fpga_irq_of_match[] __initconst = {
         { .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
         { /* Sentinel */ }
@@ -383,7 +350,6 @@ DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
         .init_early     = intcp_init_early,
         .init_irq       = intcp_init_irq_of,
         .handle_irq     = fpga_handle_irq,
-        .init_time      = cp_of_timer_init,
         .init_machine   = intcp_init_of,
         .restart        = integrator_restart,
         .dt_compat      = intcp_dt_board_compat,
diff --git a/arch/arm/mach-kirkwood/guruplug-setup.c b/arch/arm/mach-kirkwood/guruplug-setup.c
index 1c6e736cbbf8..08dd739aa709 100644
--- a/arch/arm/mach-kirkwood/guruplug-setup.c
+++ b/arch/arm/mach-kirkwood/guruplug-setup.c
@@ -53,6 +53,8 @@ static struct mv_sata_platform_data guruplug_sata_data = {
 
 static struct mvsdio_platform_data guruplug_mvsdio_data = {
         /* unfortunately the CD signal has not been connected */
+        .gpio_card_detect = -1,
+        .gpio_write_protect = -1,
 };
 
 static struct gpio_led guruplug_led_pins[] = {
diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c
index 8ddd69fdc937..6a6eb548307d 100644
--- a/arch/arm/mach-kirkwood/openrd-setup.c
+++ b/arch/arm/mach-kirkwood/openrd-setup.c
@@ -55,6 +55,7 @@ static struct mv_sata_platform_data openrd_sata_data = {
 
 static struct mvsdio_platform_data openrd_mvsdio_data = {
         .gpio_card_detect = 29, /* MPP29 used as SD card detect */
+        .gpio_write_protect = -1,
 };
 
 static unsigned int openrd_mpp_config[] __initdata = {
diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c
index c7d93b48926b..d24223166e06 100644
--- a/arch/arm/mach-kirkwood/rd88f6281-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c
@@ -69,6 +69,7 @@ static struct mv_sata_platform_data rd88f6281_sata_data = {
 
 static struct mvsdio_platform_data rd88f6281_mvsdio_data = {
         .gpio_card_detect = 28,
+        .gpio_write_protect = -1,
 };
 
 static unsigned int rd88f6281_mpp_config[] __initdata = {
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index 2969027f02fa..f9fd77e8f1f5 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -62,7 +62,10 @@ static int msm_timer_set_next_event(unsigned long cycles,
 {
         u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
 
-        writel_relaxed(0, event_base + TIMER_CLEAR);
+        ctrl &= ~TIMER_ENABLE_EN;
+        writel_relaxed(ctrl, event_base + TIMER_ENABLE);
+
+        writel_relaxed(ctrl, event_base + TIMER_CLEAR);
         writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
         writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
         return 0;
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index da93bcbc74c1..c3be068f1c96 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -5,6 +5,6 @@ AFLAGS_coherency_ll.o		:= -Wa,-march=armv7-a
 
 obj-y                            += system-controller.o
 obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o
-obj-$(CONFIG_ARCH_MVEBU)         += addr-map.o coherency.o coherency_ll.o pmsu.o irq-armada-370-xp.o 
+obj-$(CONFIG_ARCH_MVEBU)         += addr-map.o coherency.o coherency_ll.o pmsu.o
 obj-$(CONFIG_SMP)                += platsmp.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)        += hotplug.o
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index a5ea616d6d12..433e8c5343b2 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -19,6 +19,8 @@
 #include <linux/time-armada-370-xp.h>
 #include <linux/clk/mvebu.h>
 #include <linux/dma-mapping.h>
+#include <linux/irqchip.h>
+#include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
@@ -54,6 +56,10 @@ void __init armada_370_xp_init_early(void)
          * to make sure such the allocations won't fail.
          */
         init_dma_coherent_pool_size(SZ_1M);
+
+#ifdef CONFIG_CACHE_L2X0
+        l2x0_of_init(0, ~0UL);
+#endif
 }
 
 static void __init armada_370_xp_dt_init(void)
@@ -72,8 +78,7 @@ DT_MACHINE_START(ARMADA_XP_DT, "Marvell Armada 370/XP (Device Tree)")
         .init_machine   = armada_370_xp_dt_init,
         .map_io         = armada_370_xp_map_io,
         .init_early     = armada_370_xp_init_early,
-        .init_irq       = armada_370_xp_init_irq,
-        .handle_irq     = armada_370_xp_handle_irq,
+        .init_irq       = irqchip_init,
         .init_time      = armada_370_xp_timer_and_clk_init,
         .restart        = mvebu_restart,
         .dt_compat      = armada_370_xp_dt_compat,
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c
index cb7c6ae2e3fc..6c4f766365a2 100644
--- a/arch/arm/mach-omap1/clock_data.c
+++ b/arch/arm/mach-omap1/clock_data.c
@@ -543,15 +543,6 @@ static struct clk usb_dc_ck = {
         /* Direct from ULPD, no parent */
         .rate           = 48000000,
         .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
-        .enable_bit     = USB_REQ_EN_SHIFT,
-};
-
-static struct clk usb_dc_ck7xx = {
-        .name           = "usb_dc_ck",
-        .ops            = &clkops_generic,
-        /* Direct from ULPD, no parent */
-        .rate           = 48000000,
-        .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
         .enable_bit     = SOFT_USB_OTG_DPLL_REQ_SHIFT,
 };
 
@@ -727,8 +718,7 @@ static struct omap_clk omap_clks[] = {
         CLK(NULL,       "usb_clko",     &usb_clko,      CK_16XX | CK_1510 | CK_310),
         CLK(NULL,       "usb_hhc_ck",   &usb_hhc_ck1510, CK_1510 | CK_310),
         CLK(NULL,       "usb_hhc_ck",   &usb_hhc_ck16xx, CK_16XX),
-        CLK(NULL,       "usb_dc_ck",    &usb_dc_ck,     CK_16XX),
-        CLK(NULL,       "usb_dc_ck",    &usb_dc_ck7xx,  CK_7XX),
+        CLK(NULL,       "usb_dc_ck",    &usb_dc_ck,     CK_16XX | CK_7XX),
         CLK(NULL,       "mclk",         &mclk_1510,     CK_1510 | CK_310),
         CLK(NULL,       "mclk",         &mclk_16xx,     CK_16XX),
         CLK(NULL,       "bclk",         &bclk_1510,     CK_1510 | CK_310),
diff --git a/arch/arm/mach-omap1/include/mach/usb.h b/arch/arm/mach-omap1/include/mach/usb.h
index 753cd5ce6949..45e5ac707cbb 100644
--- a/arch/arm/mach-omap1/include/mach/usb.h
+++ b/arch/arm/mach-omap1/include/mach/usb.h
@@ -2,7 +2,7 @@
  * FIXME correct answer depends on hmc_mode,
  * as does (on omap1) any nonzero value for config->otg port number
  */
-#ifdef  CONFIG_USB_GADGET_OMAP
+#if IS_ENABLED(CONFIG_USB_OMAP)
 #define is_usb0_device(config)  1
 #else
 #define is_usb0_device(config)  0
diff --git a/arch/arm/mach-omap1/usb.c b/arch/arm/mach-omap1/usb.c
index 1a1db5971cd9..4118db50d5e8 100644
--- a/arch/arm/mach-omap1/usb.c
+++ b/arch/arm/mach-omap1/usb.c
@@ -123,7 +123,7 @@ omap_otg_init(struct omap_usb_config *config)
         syscon = omap_readl(OTG_SYSCON_1);
         syscon |= HST_IDLE_EN|DEV_IDLE_EN|OTG_IDLE_EN;
 
-#ifdef  CONFIG_USB_GADGET_OMAP
+#if IS_ENABLED(CONFIG_USB_OMAP)
         if (config->otg || config->register_dev) {
                 struct platform_device *udc_device = config->udc_device;
                 int status;
@@ -169,7 +169,7 @@ omap_otg_init(struct omap_usb_config *config)
 void omap_otg_init(struct omap_usb_config *config) {}
 #endif
 
-#ifdef  CONFIG_USB_GADGET_OMAP
+#if IS_ENABLED(CONFIG_USB_OMAP)
 
 static struct resource udc_resources[] = {
         /* order is significant! */
@@ -600,7 +600,7 @@ static void __init omap_1510_usb_init(struct omap_usb_config *config)
         while (!(omap_readw(ULPD_DPLL_CTRL) & DPLL_LOCK))
                 cpu_relax();
 
-#ifdef  CONFIG_USB_GADGET_OMAP
+#if IS_ENABLED(CONFIG_USB_OMAP)
         if (config->register_dev) {
                 int status;
 
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index b068b7fe99ef..62bb352c2d37 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -229,7 +229,6 @@ obj-$(CONFIG_MACH_DEVKIT8000)     	+= board-devkit8000.o
 obj-$(CONFIG_MACH_OMAP_LDP)             += board-ldp.o
 obj-$(CONFIG_MACH_OMAP3530_LV_SOM)      += board-omap3logic.o
 obj-$(CONFIG_MACH_OMAP3_TORPEDO)        += board-omap3logic.o
-obj-$(CONFIG_MACH_ENCORE)               += board-omap3encore.o
 obj-$(CONFIG_MACH_OVERO)                += board-overo.o
 obj-$(CONFIG_MACH_OMAP3EVM)             += board-omap3evm.o
 obj-$(CONFIG_MACH_OMAP3_PANDORA)        += board-omap3pandora.o
@@ -255,8 +254,6 @@ obj-$(CONFIG_MACH_TOUCHBOOK)		+= board-omap3touchbook.o
 obj-$(CONFIG_MACH_OMAP_4430SDP)         += board-4430sdp.o
 obj-$(CONFIG_MACH_OMAP4_PANDA)          += board-omap4panda.o
 
-obj-$(CONFIG_MACH_PCM049)               += board-omap4pcm049.o
-
 obj-$(CONFIG_MACH_OMAP3517EVM)          += board-am3517evm.o
 
 obj-$(CONFIG_MACH_CRANEBOARD)           += board-am3517crane.o
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index cb0596b631cf..244d8a5aa54b 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -38,7 +38,7 @@
 #include "gpmc-smc91x.h"
 
 #include <video/omapdss.h>
-#include <video/omap-panel-generic-dpi.h>
+#include <video/omap-panel-data.h>
 
 #include "mux.h"
 #include "hsmmc.h"
@@ -108,24 +108,13 @@ static struct platform_device *sdp2430_devices[] __initdata = {
 #define SDP2430_LCD_PANEL_BACKLIGHT_GPIO        91
 #define SDP2430_LCD_PANEL_ENABLE_GPIO           154
 
-static int sdp2430_panel_enable_lcd(struct omap_dss_device *dssdev)
-{
-        gpio_direction_output(SDP2430_LCD_PANEL_ENABLE_GPIO, 1);
-        gpio_direction_output(SDP2430_LCD_PANEL_BACKLIGHT_GPIO, 1);
-
-        return 0;
-}
-
-static void sdp2430_panel_disable_lcd(struct omap_dss_device *dssdev)
-{
-        gpio_direction_output(SDP2430_LCD_PANEL_ENABLE_GPIO, 0);
-        gpio_direction_output(SDP2430_LCD_PANEL_BACKLIGHT_GPIO, 0);
-}
-
 static struct panel_generic_dpi_data sdp2430_panel_data = {
         .name                   = "nec_nl2432dr22-11b",
-        .platform_enable        = sdp2430_panel_enable_lcd,
-        .platform_disable       = sdp2430_panel_disable_lcd,
+        .num_gpios              = 2,
+        .gpios                  = {
+                SDP2430_LCD_PANEL_ENABLE_GPIO,
+                SDP2430_LCD_PANEL_BACKLIGHT_GPIO,
+        },
 };
 
 static struct omap_dss_device sdp2430_lcd_device = {
@@ -146,26 +135,6 @@ static struct omap_dss_board_info sdp2430_dss_data = {
         .default_device = &sdp2430_lcd_device,
 };
 
-static void __init sdp2430_display_init(void)
-{
-        int r;
-
-        static struct gpio gpios[] __initdata = {
-                { SDP2430_LCD_PANEL_ENABLE_GPIO, GPIOF_OUT_INIT_LOW,
-                        "LCD reset" },
-                { SDP2430_LCD_PANEL_BACKLIGHT_GPIO, GPIOF_OUT_INIT_LOW,
-                        "LCD Backlight" },
-        };
-
-        r = gpio_request_array(gpios, ARRAY_SIZE(gpios));
-        if (r) {
-                pr_err("Cannot request LCD GPIOs, error %d\n", r);
-                return;
-        }
-
-        omap_display_init(&sdp2430_dss_data);
-}
-
 #if IS_ENABLED(CONFIG_SMC91X)
 
 static struct omap_smc91x_platform_data board_smc91x_data = {
@@ -273,7 +242,7 @@ static void __init omap_2430sdp_init(void)
         gpio_request_one(SECONDARY_LCD_GPIO, GPIOF_OUT_INIT_LOW,
                          "Secondary LCD backlight");
 
-        sdp2430_display_init();
+        omap_display_init(&sdp2430_dss_data);
 }
 
 MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board")
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 7eb9651dd0f7..23b004afa3f8 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -35,7 +35,7 @@
 #include "common.h"
 #include <linux/omap-dma.h>
 #include <video/omapdss.h>
-#include <video/omap-panel-tfp410.h>
+#include <video/omap-panel-data.h>
 
 #include "gpmc.h"
 #include "gpmc-smc91x.h"
@@ -108,53 +108,38 @@ static struct twl4030_keypad_data sdp3430_kp_data = {
 #define SDP3430_LCD_PANEL_BACKLIGHT_GPIO        8
 #define SDP3430_LCD_PANEL_ENABLE_GPIO           5
 
-static struct gpio sdp3430_dss_gpios[] __initdata = {
-        {SDP3430_LCD_PANEL_ENABLE_GPIO,    GPIOF_OUT_INIT_LOW, "LCD reset"    },
-        {SDP3430_LCD_PANEL_BACKLIGHT_GPIO, GPIOF_OUT_INIT_LOW, "LCD Backlight"},
-};
-
 static void __init sdp3430_display_init(void)
 {
         int r;
 
-        r = gpio_request_array(sdp3430_dss_gpios,
-                               ARRAY_SIZE(sdp3430_dss_gpios));
+        /*
+         * the backlight GPIO doesn't directly go to the panel, it enables
+         * an internal circuit on 3430sdp to create the signal V_BKL_28V,
+         * this is connected to LED+ pin of the sharp panel. This GPIO
+         * is left enabled in the board file, and not passed to the panel
+         * as platform_data.
+         */
+        r = gpio_request_one(SDP3430_LCD_PANEL_BACKLIGHT_GPIO,
+                                GPIOF_OUT_INIT_HIGH, "LCD Backlight");
         if (r)
-                printk(KERN_ERR "failed to get LCD control GPIOs\n");
-
-}
+                pr_err("failed to get LCD Backlight GPIO\n");
 
-static int sdp3430_panel_enable_lcd(struct omap_dss_device *dssdev)
-{
-        gpio_direction_output(SDP3430_LCD_PANEL_ENABLE_GPIO, 1);
-        gpio_direction_output(SDP3430_LCD_PANEL_BACKLIGHT_GPIO, 1);
-
-        return 0;
-}
-
-static void sdp3430_panel_disable_lcd(struct omap_dss_device *dssdev)
-{
-        gpio_direction_output(SDP3430_LCD_PANEL_ENABLE_GPIO, 0);
-        gpio_direction_output(SDP3430_LCD_PANEL_BACKLIGHT_GPIO, 0);
-}
-
-static int sdp3430_panel_enable_tv(struct omap_dss_device *dssdev)
-{
-        return 0;
-}
-
-static void sdp3430_panel_disable_tv(struct omap_dss_device *dssdev)
-{
 }
 
+static struct panel_sharp_ls037v7dw01_data sdp3430_lcd_data = {
+        .resb_gpio = SDP3430_LCD_PANEL_ENABLE_GPIO,
+        .ini_gpio = -1,
+        .mo_gpio = -1,
+        .lr_gpio = -1,
+        .ud_gpio = -1,
+};
 
 static struct omap_dss_device sdp3430_lcd_device = {
         .name                   = "lcd",
         .driver_name            = "sharp_ls_panel",
         .type                   = OMAP_DISPLAY_TYPE_DPI,
         .phy.dpi.data_lines     = 16,
-        .platform_enable        = sdp3430_panel_enable_lcd,
-        .platform_disable       = sdp3430_panel_disable_lcd,
+        .data                   = &sdp3430_lcd_data,
 };
 
 static struct tfp410_platform_data dvi_panel = {
@@ -175,8 +160,6 @@ static struct omap_dss_device sdp3430_tv_device = {
         .driver_name            = "venc",
         .type                   = OMAP_DISPLAY_TYPE_VENC,
         .phy.venc.type          = OMAP_DSS_VENC_TYPE_SVIDEO,
-        .platform_enable        = sdp3430_panel_enable_tv,
-        .platform_disable       = sdp3430_panel_disable_tv,
 };
 
 
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 306df0b40935..56a9a4f855c7 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -291,6 +291,10 @@ static struct platform_device sdp4430_leds_pwm = {
         },
 };
 
+/* Dummy regulator for pwm-backlight driver */
+static struct regulator_consumer_supply backlight_supply =
+        REGULATOR_SUPPLY("enable", "pwm-backlight");
+
 static struct platform_pwm_backlight_data sdp4430_backlight_data = {
         .max_brightness = 127,
         .dft_brightness = 127,
@@ -718,6 +722,8 @@ static void __init omap_4430sdp_init(void)
 
         omap4_i2c_init();
         omap_sfh7741prox_init();
+        regulator_register_always_on(0, "backlight-enable",
+                                     &backlight_supply, 1, 0);
         platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices));
         omap_serial_init();
         omap_sdrc_init(NULL, NULL);
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 191f9762ba63..d63f14b534b5 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -35,8 +35,7 @@
 
 #include "common.h"
 #include <video/omapdss.h>
-#include <video/omap-panel-generic-dpi.h>
-#include <video/omap-panel-tfp410.h>
+#include <video/omap-panel-data.h>
 
 #include "am35xx-emac.h"
 #include "mux.h"
@@ -121,63 +120,14 @@ static int __init am3517_evm_i2c_init(void)
         return 0;
 }
 
-static int lcd_enabled;
-static int dvi_enabled;
-
-#if defined(CONFIG_PANEL_SHARP_LQ043T1DG01) || \
-                defined(CONFIG_PANEL_SHARP_LQ043T1DG01_MODULE)
-static struct gpio am3517_evm_dss_gpios[] __initdata = {
-        /* GPIO 182 = LCD Backlight Power */
-        { LCD_PANEL_BKLIGHT_PWR, GPIOF_OUT_INIT_HIGH, "lcd_backlight_pwr" },
-        /* GPIO 181 = LCD Panel PWM */
-        { LCD_PANEL_PWM,         GPIOF_OUT_INIT_HIGH, "lcd bl enable"     },
-        /* GPIO 176 = LCD Panel Power enable pin */
-        { LCD_PANEL_PWR,         GPIOF_OUT_INIT_HIGH, "dvi enable"        },
-};
-
-static void __init am3517_evm_display_init(void)
-{
-        int r;
-
-        omap_mux_init_gpio(LCD_PANEL_PWR, OMAP_PIN_INPUT_PULLUP);
-        omap_mux_init_gpio(LCD_PANEL_BKLIGHT_PWR, OMAP_PIN_INPUT_PULLDOWN);
-        omap_mux_init_gpio(LCD_PANEL_PWM, OMAP_PIN_INPUT_PULLDOWN);
-
-        r = gpio_request_array(am3517_evm_dss_gpios,
-                               ARRAY_SIZE(am3517_evm_dss_gpios));
-        if (r) {
-                printk(KERN_ERR "failed to get DSS panel control GPIOs\n");
-                return;
-        }
-
-        printk(KERN_INFO "Display initialized successfully\n");
-}
-#else
-static void __init am3517_evm_display_init(void) {}
-#endif
-
-static int am3517_evm_panel_enable_lcd(struct omap_dss_device *dssdev)
-{
-        if (dvi_enabled) {
-                printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
-                return -EINVAL;
-        }
-        gpio_set_value(LCD_PANEL_PWR, 1);
-        lcd_enabled = 1;
-
-        return 0;
-}
-
-static void am3517_evm_panel_disable_lcd(struct omap_dss_device *dssdev)
-{
-        gpio_set_value(LCD_PANEL_PWR, 0);
-        lcd_enabled = 0;
-}
-
 static struct panel_generic_dpi_data lcd_panel = {
         .name                   = "sharp_lq",
-        .platform_enable        = am3517_evm_panel_enable_lcd,
-        .platform_disable       = am3517_evm_panel_disable_lcd,
+        .num_gpios              = 3,
+        .gpios                  = {
+                LCD_PANEL_PWR,
+                LCD_PANEL_BKLIGHT_PWR,
+                LCD_PANEL_PWM,
+        },
 };
 
 static struct omap_dss_device am3517_evm_lcd_device = {
@@ -188,22 +138,11 @@ static struct omap_dss_device am3517_evm_lcd_device = {
         .phy.dpi.data_lines     = 16,
 };
 
-static int am3517_evm_panel_enable_tv(struct omap_dss_device *dssdev)
-{
-        return 0;
-}
-
-static void am3517_evm_panel_disable_tv(struct omap_dss_device *dssdev)
-{
-}
-
 static struct omap_dss_device am3517_evm_tv_device = {
         .type                   = OMAP_DISPLAY_TYPE_VENC,
         .name                   = "tv",
         .driver_name            = "venc",
         .phy.venc.type          = OMAP_DSS_VENC_TYPE_SVIDEO,
-        .platform_enable        = am3517_evm_panel_enable_tv,
-        .platform_disable       = am3517_evm_panel_disable_tv,
 };
 
 static struct tfp410_platform_data dvi_panel = {
@@ -366,8 +305,6 @@ static void __init am3517_evm_init(void)
         usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&usbhs_bdata);
         am3517_evm_hecc_init(&am3517_evm_hecc_pdata);
-        /* DSS */
-        am3517_evm_display_init();
 
         /* RTC - S35390A */
         am3517_evm_rtc_init();
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index 7fda3f5f8a7f..ee6218c74807 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -41,8 +41,7 @@
 
 #include <linux/platform_data/mtd-nand-omap2.h>
 #include <video/omapdss.h>
-#include <video/omap-panel-generic-dpi.h>
-#include <video/omap-panel-tfp410.h>
+#include <video/omap-panel-data.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
 
 #include "common.h"
@@ -191,45 +190,12 @@ static inline void cm_t35_init_nand(void) {}
 #define CM_T35_LCD_BL_GPIO 58
 #define CM_T35_DVI_EN_GPIO 54
 
-static int lcd_enabled;
-static int dvi_enabled;
-
-static int cm_t35_panel_enable_lcd(struct omap_dss_device *dssdev)
-{
-        if (dvi_enabled) {
-                printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
-                return -EINVAL;
-        }
-
-        gpio_set_value(CM_T35_LCD_EN_GPIO, 1);
-        gpio_set_value(CM_T35_LCD_BL_GPIO, 1);
-
-        lcd_enabled = 1;
-
-        return 0;
-}
-
-static void cm_t35_panel_disable_lcd(struct omap_dss_device *dssdev)
-{
-        lcd_enabled = 0;
-
-        gpio_set_value(CM_T35_LCD_BL_GPIO, 0);
-        gpio_set_value(CM_T35_LCD_EN_GPIO, 0);
-}
-
-static int cm_t35_panel_enable_tv(struct omap_dss_device *dssdev)
-{
-        return 0;
-}
-
-static void cm_t35_panel_disable_tv(struct omap_dss_device *dssdev)
-{
-}
-
 static struct panel_generic_dpi_data lcd_panel = {
         .name                   = "toppoly_tdo35s",
-        .platform_enable        = cm_t35_panel_enable_lcd,
-        .platform_disable       = cm_t35_panel_disable_lcd,
+        .num_gpios              = 1,
+        .gpios                  = {
+                CM_T35_LCD_BL_GPIO,
+        },
 };
 
 static struct omap_dss_device cm_t35_lcd_device = {
@@ -258,8 +224,6 @@ static struct omap_dss_device cm_t35_tv_device = {
         .driver_name            = "venc",
         .type                   = OMAP_DISPLAY_TYPE_VENC,
         .phy.venc.type          = OMAP_DSS_VENC_TYPE_SVIDEO,
-        .platform_enable        = cm_t35_panel_enable_tv,
-        .platform_disable       = cm_t35_panel_disable_tv,
 };
 
 static struct omap_dss_device *cm_t35_dss_devices[] = {
@@ -293,11 +257,6 @@ static struct spi_board_info cm_t35_lcd_spi_board_info[] __initdata = {
         },
 };
 
-static struct gpio cm_t35_dss_gpios[] __initdata = {
-        { CM_T35_LCD_EN_GPIO, GPIOF_OUT_INIT_LOW,  "lcd enable"    },
-        { CM_T35_LCD_BL_GPIO, GPIOF_OUT_INIT_LOW,  "lcd bl enable" },
-};
-
 static void __init cm_t35_init_display(void)
 {
         int err;
@@ -305,23 +264,21 @@ static void __init cm_t35_init_display(void)
         spi_register_board_info(cm_t35_lcd_spi_board_info,
                                 ARRAY_SIZE(cm_t35_lcd_spi_board_info));
 
-        err = gpio_request_array(cm_t35_dss_gpios,
-                                 ARRAY_SIZE(cm_t35_dss_gpios));
+
+        err = gpio_request_one(CM_T35_LCD_EN_GPIO, GPIOF_OUT_INIT_LOW,
+                        "lcd bl enable");
         if (err) {
-                pr_err("CM-T35: failed to request DSS control GPIOs\n");
+                pr_err("CM-T35: failed to request LCD EN GPIO\n");
                 return;
         }
 
-        gpio_export(CM_T35_LCD_EN_GPIO, 0);
-        gpio_export(CM_T35_LCD_BL_GPIO, 0);
-
         msleep(50);
         gpio_set_value(CM_T35_LCD_EN_GPIO, 1);
 
         err = omap_display_init(&cm_t35_dss_data);
         if (err) {
                 pr_err("CM-T35: failed to register DSS device\n");
-                gpio_free_array(cm_t35_dss_gpios, ARRAY_SIZE(cm_t35_dss_gpios));
+                gpio_free(CM_T35_LCD_EN_GPIO);
         }
 }
 
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 42fbf1ef12a9..576420544178 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -43,8 +43,7 @@
 #include "gpmc.h"
 #include <linux/platform_data/mtd-nand-omap2.h>
 #include <video/omapdss.h>
-#include <video/omap-panel-generic-dpi.h>
-#include <video/omap-panel-tfp410.h>
+#include <video/omap-panel-data.h>
 
 #include <linux/platform_data/spi-omap2-mcspi.h>
 #include <linux/input/matrix_keypad.h>
@@ -104,19 +103,6 @@ static struct omap2_hsmmc_info mmc[] = {
         {}      /* Terminator */
 };
 
-static int devkit8000_panel_enable_lcd(struct omap_dss_device *dssdev)
-{
-        if (gpio_is_valid(dssdev->reset_gpio))
-                gpio_set_value_cansleep(dssdev->reset_gpio, 1);
-        return 0;
-}
-
-static void devkit8000_panel_disable_lcd(struct omap_dss_device *dssdev)
-{
-        if (gpio_is_valid(dssdev->reset_gpio))
-                gpio_set_value_cansleep(dssdev->reset_gpio, 0);
-}
-
 static struct regulator_consumer_supply devkit8000_vmmc1_supply[] = {
         REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
 };
@@ -128,8 +114,7 @@ static struct regulator_consumer_supply devkit8000_vio_supply[] = {
 
 static struct panel_generic_dpi_data lcd_panel = {
         .name                   = "innolux_at070tn83",
-        .platform_enable        = devkit8000_panel_enable_lcd,
-        .platform_disable       = devkit8000_panel_disable_lcd,
+        /* gpios filled in code */
 };
 
 static struct omap_dss_device devkit8000_lcd_device = {
@@ -211,8 +196,6 @@ static struct gpio_led gpio_leds[];
 static int devkit8000_twl_gpio_setup(struct device *dev,
                 unsigned gpio, unsigned ngpio)
 {
-        int ret;
-
         /* gpio + 0 is "mmc0_cd" (input/IRQ) */
         mmc[0].gpio_cd = gpio + 0;
         omap_hsmmc_late_init(mmc);
@@ -221,13 +204,8 @@ static int devkit8000_twl_gpio_setup(struct device *dev,
         gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
 
         /* TWL4030_GPIO_MAX + 0 is "LCD_PWREN" (out, active high) */
-        devkit8000_lcd_device.reset_gpio = gpio + TWL4030_GPIO_MAX + 0;
-        ret = gpio_request_one(devkit8000_lcd_device.reset_gpio,
-                               GPIOF_OUT_INIT_LOW, "LCD_PWREN");
-        if (ret < 0) {
-                devkit8000_lcd_device.reset_gpio = -EINVAL;
-                printk(KERN_ERR "Failed to request GPIO for LCD_PWRN\n");
-        }
+        lcd_panel.num_gpios = 1;
+        lcd_panel.gpios[0] = gpio + TWL4030_GPIO_MAX + 0;
 
         /* gpio + 7 is "DVI_PD" (out, active low) */
         dvi_panel.power_down_gpio = gpio + 7;
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 5b4ec51c385f..69c0acf5aa63 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -34,7 +34,7 @@
 #include <asm/mach/map.h>
 
 #include <video/omapdss.h>
-#include <video/omap-panel-generic-dpi.h>
+#include <video/omap-panel-data.h>
 
 #include "common.h"
 #include "mux.h"
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 95ccec0eeab9..b54562d1235e 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -31,7 +31,7 @@
 #include <asm/mach/arch.h>
 
 #include <video/omapdss.h>
-#include <video/omap-panel-tfp410.h>
+#include <video/omap-panel-data.h>
 #include <linux/platform_data/mtd-onenand-omap2.h>
 
 #include "common.h"
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index b12fe966a7b9..d0d17bc58d9b 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -41,7 +41,7 @@
 #include "gpmc-smsc911x.h"
 
 #include <video/omapdss.h>
-#include <video/omap-panel-generic-dpi.h>
+#include <video/omap-panel-data.h>
 
 #include "board-flash.h"
 #include "mux.h"
@@ -181,34 +181,13 @@ static inline void __init ldp_init_smsc911x(void)
 
 /* LCD */
 
-static int ldp_backlight_gpio;
-static int ldp_lcd_enable_gpio;
-
 #define LCD_PANEL_RESET_GPIO            55
 #define LCD_PANEL_QVGA_GPIO             56
 
-static int ldp_panel_enable_lcd(struct omap_dss_device *dssdev)
-{
-        if (gpio_is_valid(ldp_lcd_enable_gpio))
-                gpio_direction_output(ldp_lcd_enable_gpio, 1);
-        if (gpio_is_valid(ldp_backlight_gpio))
-                gpio_direction_output(ldp_backlight_gpio, 1);
-
-        return 0;
-}
-
-static void ldp_panel_disable_lcd(struct omap_dss_device *dssdev)
-{
-        if (gpio_is_valid(ldp_lcd_enable_gpio))
-                gpio_direction_output(ldp_lcd_enable_gpio, 0);
-        if (gpio_is_valid(ldp_backlight_gpio))
-                gpio_direction_output(ldp_backlight_gpio, 0);
-}
-
 static struct panel_generic_dpi_data ldp_panel_data = {
         .name                   = "nec_nl2432dr22-11b",
-        .platform_enable        = ldp_panel_enable_lcd,
-        .platform_disable       = ldp_panel_disable_lcd,
+        .num_gpios              = 4,
+        /* gpios filled in code */
 };
 
 static struct omap_dss_device ldp_lcd_device = {
@@ -231,41 +210,19 @@ static struct omap_dss_board_info ldp_dss_data = {
 
 static void __init ldp_display_init(void)
 {
-        int r;
-
-        static struct gpio gpios[] __initdata = {
-                {LCD_PANEL_RESET_GPIO, GPIOF_OUT_INIT_HIGH, "LCD RESET"},
-                {LCD_PANEL_QVGA_GPIO, GPIOF_OUT_INIT_HIGH, "LCD QVGA"},
-        };
-
-        r = gpio_request_array(gpios, ARRAY_SIZE(gpios));
-        if (r) {
-                pr_err("Cannot request LCD GPIOs, error %d\n", r);
-                return;
-        }
+        ldp_panel_data.gpios[2] = LCD_PANEL_RESET_GPIO;
+        ldp_panel_data.gpios[3] = LCD_PANEL_QVGA_GPIO;
 
         omap_display_init(&ldp_dss_data);
 }
 
 static int ldp_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned ngpio)
 {
-        int r;
-
-        struct gpio gpios[] = {
-                {gpio + 7 , GPIOF_OUT_INIT_LOW, "LCD ENABLE"},
-                {gpio + 15, GPIOF_OUT_INIT_LOW, "LCD BACKLIGHT"},
-        };
-
-        r = gpio_request_array(gpios, ARRAY_SIZE(gpios));
-        if (r) {
-                pr_err("Cannot request LCD GPIOs, error %d\n", r);
-                ldp_backlight_gpio = -EINVAL;
-                ldp_lcd_enable_gpio = -EINVAL;
-                return r;
-        }
-
-        ldp_backlight_gpio = gpio + 15;
-        ldp_lcd_enable_gpio = gpio + 7;
+        ldp_panel_data.gpios[0] = gpio + 7;
+        ldp_panel_data.gpio_invert[0] = true;
+
+        ldp_panel_data.gpios[1] = gpio + 15;
+        ldp_panel_data.gpio_invert[1] = true;
 
         return 0;
 }
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 6955a428f534..6de78605c0af 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -44,7 +44,7 @@
 #include <asm/mach/flash.h>
 
 #include <video/omapdss.h>
-#include <video/omap-panel-tfp410.h>
+#include <video/omap-panel-data.h>
 #include <linux/platform_data/mtd-nand-omap2.h>
 
 #include "common.h"
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index 2de92facc8a3..f76d0de7b406 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -51,7 +51,7 @@
 #include "common.h"
 #include <linux/platform_data/spi-omap2-mcspi.h>
 #include <video/omapdss.h>
-#include <video/omap-panel-tfp410.h>
+#include <video/omap-panel-data.h>
 
 #include "soc.h"
 #include "mux.h"
@@ -155,61 +155,43 @@ static inline void __init omap3evm_init_smsc911x(void) { return; }
 #define OMAP3EVM_LCD_PANEL_LR           2
 #define OMAP3EVM_LCD_PANEL_UD           3
 #define OMAP3EVM_LCD_PANEL_INI          152
-#define OMAP3EVM_LCD_PANEL_ENVDD        153
 #define OMAP3EVM_LCD_PANEL_QVGA         154
 #define OMAP3EVM_LCD_PANEL_RESB         155
+
+#define OMAP3EVM_LCD_PANEL_ENVDD        153
 #define OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO 210
+
+/*
+ * OMAP3EVM DVI control signals
+ */
 #define OMAP3EVM_DVI_PANEL_EN_GPIO      199
 
-static struct gpio omap3_evm_dss_gpios[] __initdata = {
-        { OMAP3EVM_LCD_PANEL_RESB,  GPIOF_OUT_INIT_HIGH, "lcd_panel_resb"  },
-        { OMAP3EVM_LCD_PANEL_INI,   GPIOF_OUT_INIT_HIGH, "lcd_panel_ini"   },
-        { OMAP3EVM_LCD_PANEL_QVGA,  GPIOF_OUT_INIT_LOW,  "lcd_panel_qvga"  },
-        { OMAP3EVM_LCD_PANEL_LR,    GPIOF_OUT_INIT_HIGH, "lcd_panel_lr"    },
-        { OMAP3EVM_LCD_PANEL_UD,    GPIOF_OUT_INIT_HIGH, "lcd_panel_ud"    },
-        { OMAP3EVM_LCD_PANEL_ENVDD, GPIOF_OUT_INIT_LOW,  "lcd_panel_envdd" },
+static struct panel_sharp_ls037v7dw01_data omap3_evm_lcd_data = {
+        .resb_gpio = OMAP3EVM_LCD_PANEL_RESB,
+        .ini_gpio = OMAP3EVM_LCD_PANEL_INI,
+        .mo_gpio = OMAP3EVM_LCD_PANEL_QVGA,
+        .lr_gpio = OMAP3EVM_LCD_PANEL_LR,
+        .ud_gpio = OMAP3EVM_LCD_PANEL_UD,
 };
 
-static int lcd_enabled;
-static int dvi_enabled;
-
 static void __init omap3_evm_display_init(void)
 {
         int r;
 
-        r = gpio_request_array(omap3_evm_dss_gpios,
-                               ARRAY_SIZE(omap3_evm_dss_gpios));
+        r = gpio_request_one(OMAP3EVM_LCD_PANEL_ENVDD, GPIOF_OUT_INIT_LOW,
+                                "lcd_panel_envdd");
         if (r)
-                printk(KERN_ERR "failed to get lcd_panel_* gpios\n");
-}
+                pr_err("failed to get lcd_panel_envdd GPIO\n");
 
-static int omap3_evm_enable_lcd(struct omap_dss_device *dssdev)
-{
-        if (dvi_enabled) {
-                printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
-                return -EINVAL;
-        }
-        gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 0);
+        r = gpio_request_one(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO,
+                                GPIOF_OUT_INIT_LOW, "lcd_panel_bklight");
+        if (r)
+                pr_err("failed to get lcd_panel_bklight GPIO\n");
 
         if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
                 gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0);
         else
                 gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
-
-        lcd_enabled = 1;
-        return 0;
-}
-
-static void omap3_evm_disable_lcd(struct omap_dss_device *dssdev)
-{
-        gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 1);
-
-        if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
-                gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
-        else
-                gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0);
-
-        lcd_enabled = 0;
 }
 
 static struct omap_dss_device omap3_evm_lcd_device = {
@@ -217,26 +199,14 @@ static struct omap_dss_device omap3_evm_lcd_device = {
         .driver_name            = "sharp_ls_panel",
         .type                   = OMAP_DISPLAY_TYPE_DPI,
         .phy.dpi.data_lines     = 18,
-        .platform_enable        = omap3_evm_enable_lcd,
-        .platform_disable       = omap3_evm_disable_lcd,
+        .data                   = &omap3_evm_lcd_data,
 };
 
-static int omap3_evm_enable_tv(struct omap_dss_device *dssdev)
-{
-        return 0;
-}
-
-static void omap3_evm_disable_tv(struct omap_dss_device *dssdev)
-{
-}
-
 static struct omap_dss_device omap3_evm_tv_device = {
         .name                   = "tv",
         .driver_name            = "venc",
         .type                   = OMAP_DISPLAY_TYPE_VENC,
         .phy.venc.type          = OMAP_DSS_VENC_TYPE_SVIDEO,
-        .platform_enable        = omap3_evm_enable_tv,
-        .platform_disable       = omap3_evm_disable_tv,
 };
 
 static struct tfp410_platform_data dvi_panel = {
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index 1004d2aaa68f..28133d5b4fed 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -44,6 +44,7 @@
 
 #include "common.h"
 #include <video/omapdss.h>
+#include <video/omap-panel-data.h>
 #include <linux/platform_data/mtd-nand-omap2.h>
 
 #include "mux.h"
@@ -230,12 +231,16 @@ static struct twl4030_keypad_data pandora_kp_data = {
         .rep            = 1,
 };
 
+static struct panel_tpo_td043_data lcd_data = {
+        .nreset_gpio            = 157,
+};
+
 static struct omap_dss_device pandora_lcd_device = {
         .name                   = "lcd",
         .driver_name            = "tpo_td043mtea1_panel",
         .type                   = OMAP_DISPLAY_TYPE_DPI,
         .phy.dpi.data_lines     = 24,
-        .reset_gpio             = 157,
+        .data                   = &lcd_data,
 };
 
 static struct omap_dss_device pandora_tv_device = {
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index bf0956489899..d37e6b187ae4 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -44,8 +44,7 @@
 #include "gpmc.h"
 #include <linux/platform_data/mtd-nand-omap2.h>
 #include <video/omapdss.h>
-#include <video/omap-panel-generic-dpi.h>
-#include <video/omap-panel-tfp410.h>
+#include <video/omap-panel-data.h>
 
 #include <linux/platform_data/spi-omap2-mcspi.h>
 
@@ -95,15 +94,6 @@ static void __init omap3_stalker_display_init(void)
         return;
 }
 
-static int omap3_stalker_enable_tv(struct omap_dss_device *dssdev)
-{
-        return 0;
-}
-
-static void omap3_stalker_disable_tv(struct omap_dss_device *dssdev)
-{
-}
-
 static struct omap_dss_device omap3_stalker_tv_device = {
         .name                   = "tv",
         .driver_name            = "venc",
@@ -113,8 +103,6 @@ static struct omap_dss_device omap3_stalker_tv_device = {
 #elif defined(CONFIG_OMAP2_VENC_OUT_TYPE_COMPOSITE)
         .u.venc.type            = OMAP_DSS_VENC_TYPE_COMPOSITE,
 #endif
-        .platform_enable        = omap3_stalker_enable_tv,
-        .platform_disable       = omap3_stalker_disable_tv,
 };
 
 static struct tfp410_platform_data dvi_panel = {
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index ab79a4422bcc..4ca6b680aa72 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -47,8 +47,7 @@
 #include <asm/mach/map.h>
 
 #include <video/omapdss.h>
-#include <video/omap-panel-generic-dpi.h>
-#include <video/omap-panel-tfp410.h>
+#include <video/omap-panel-data.h>
 
 #include "common.h"
 #include "mux.h"
@@ -146,28 +145,9 @@ static inline void __init overo_init_smsc911x(void) { return; }
 #endif
 
 /* DSS */
-static int lcd_enabled;
-static int dvi_enabled;
-
 #define OVERO_GPIO_LCD_EN 144
 #define OVERO_GPIO_LCD_BL 145
 
-static struct gpio overo_dss_gpios[] __initdata = {
-        { OVERO_GPIO_LCD_EN, GPIOF_OUT_INIT_HIGH, "OVERO_GPIO_LCD_EN" },
-        { OVERO_GPIO_LCD_BL, GPIOF_OUT_INIT_HIGH, "OVERO_GPIO_LCD_BL" },
-};
-
-static void __init overo_display_init(void)
-{
-        if (gpio_request_array(overo_dss_gpios, ARRAY_SIZE(overo_dss_gpios))) {
-                printk(KERN_ERR "could not obtain DSS control GPIOs\n");
-                return;
-        }
-
-        gpio_export(OVERO_GPIO_LCD_EN, 0);
-        gpio_export(OVERO_GPIO_LCD_BL, 0);
-}
-
 static struct tfp410_platform_data dvi_panel = {
         .i2c_bus_num            = 3,
         .power_down_gpio        = -1,
@@ -188,30 +168,13 @@ static struct omap_dss_device overo_tv_device = {
         .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
 };
 
-static int overo_panel_enable_lcd(struct omap_dss_device *dssdev)
-{
-        if (dvi_enabled) {
-                printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
-                return -EINVAL;
-        }
-
-        gpio_set_value(OVERO_GPIO_LCD_EN, 1);
-        gpio_set_value(OVERO_GPIO_LCD_BL, 1);
-        lcd_enabled = 1;
-        return 0;
-}
-
-static void overo_panel_disable_lcd(struct omap_dss_device *dssdev)
-{
-        gpio_set_value(OVERO_GPIO_LCD_EN, 0);
-        gpio_set_value(OVERO_GPIO_LCD_BL, 0);
-        lcd_enabled = 0;
-}
-
 static struct panel_generic_dpi_data lcd43_panel = {
         .name                   = "samsung_lte430wq_f0c",
-        .platform_enable        = overo_panel_enable_lcd,
-        .platform_disable       = overo_panel_disable_lcd,
+        .num_gpios              = 2,
+        .gpios                  = {
+                OVERO_GPIO_LCD_EN,
+                OVERO_GPIO_LCD_BL
+        },
 };
 
 static struct omap_dss_device overo_lcd43_device = {
@@ -224,13 +187,20 @@ static struct omap_dss_device overo_lcd43_device = {
 
 #if defined(CONFIG_PANEL_LGPHILIPS_LB035Q02) || \
         defined(CONFIG_PANEL_LGPHILIPS_LB035Q02_MODULE)
+static struct panel_generic_dpi_data lcd35_panel = {
+        .num_gpios              = 2,
+        .gpios                  = {
+                OVERO_GPIO_LCD_EN,
+                OVERO_GPIO_LCD_BL
+        },
+};
+
 static struct omap_dss_device overo_lcd35_device = {
         .type                   = OMAP_DISPLAY_TYPE_DPI,
         .name                   = "lcd35",
         .driver_name            = "lgphilips_lb035q02_panel",
         .phy.dpi.data_lines     = 24,
-        .platform_enable        = overo_panel_enable_lcd,
-        .platform_disable       = overo_panel_disable_lcd,
+        .data                   = &lcd35_panel,
 };
 #endif
 
@@ -509,7 +479,6 @@ static void __init overo_init(void)
         usbhs_init(&usbhs_bdata);
         overo_spi_init();
         overo_init_smsc911x();
-        overo_display_init();
         overo_init_led();
         overo_init_keys();
         omap_twl4030_audio_init("overo", NULL);
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 3a077df6b8df..1a884670a6c4 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -547,12 +547,16 @@ static struct regulator_consumer_supply rx51_vio_supplies[] = {
         REGULATOR_SUPPLY("DVDD", "2-0019"),
         /* Si4713 IO supply */
         REGULATOR_SUPPLY("vio", "2-0063"),
+        /* lis3lv02d */
+        REGULATOR_SUPPLY("Vdd_IO", "3-001d"),
 };
 
 static struct regulator_consumer_supply rx51_vaux1_consumers[] = {
         REGULATOR_SUPPLY("vdds_sdi", "omapdss"),
         /* Si4713 supply */
         REGULATOR_SUPPLY("vdd", "2-0063"),
+        /* lis3lv02d */
+        REGULATOR_SUPPLY("Vdd", "3-001d"),
 };
 
 static struct regulator_init_data rx51_vaux1 = {
diff --git a/arch/arm/mach-omap2/board-rx51-video.c b/arch/arm/mach-omap2/board-rx51-video.c
index eb667261df08..bd74f9f6063b 100644
--- a/arch/arm/mach-omap2/board-rx51-video.c
+++ b/arch/arm/mach-omap2/board-rx51-video.c
@@ -16,6 +16,8 @@
 #include <linux/mm.h>
 #include <asm/mach-types.h>
 #include <video/omapdss.h>
+#include <video/omap-panel-data.h>
+
 #include <linux/platform_data/spi-omap2-mcspi.h>
 
 #include "soc.h"
@@ -27,25 +29,16 @@
 
 #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
 
-static int rx51_lcd_enable(struct omap_dss_device *dssdev)
-{
-        gpio_set_value(dssdev->reset_gpio, 1);
-        return 0;
-}
-
-static void rx51_lcd_disable(struct omap_dss_device *dssdev)
-{
-        gpio_set_value(dssdev->reset_gpio, 0);
-}
+static struct panel_acx565akm_data lcd_data = {
+        .reset_gpio     = RX51_LCD_RESET_GPIO,
+};
 
 static struct omap_dss_device rx51_lcd_device = {
         .name                   = "lcd",
         .driver_name            = "panel-acx565akm",
         .type                   = OMAP_DISPLAY_TYPE_SDI,
         .phy.sdi.datapairs      = 2,
-        .reset_gpio             = RX51_LCD_RESET_GPIO,
-        .platform_enable        = rx51_lcd_enable,
-        .platform_disable       = rx51_lcd_disable,
+        .data                   = &lcd_data,
 };
 
 static struct omap_dss_device  rx51_tv_device = {
@@ -76,13 +69,8 @@ static int __init rx51_video_init(void)
                 return 0;
         }
 
-        if (gpio_request_one(RX51_LCD_RESET_GPIO, GPIOF_OUT_INIT_HIGH,
-                             "LCD ACX565AKM reset")) {
-                pr_err("%s failed to get LCD Reset GPIO\n", __func__);
-                return 0;
-        }
-
         omap_display_init(&rx51_dss_board_info);
+
         return 0;
 }
 
diff --git a/arch/arm/mach-omap2/board-zoom-display.c b/arch/arm/mach-omap2/board-zoom-display.c
index 8cef477d6b00..c2a079cb76fc 100644
--- a/arch/arm/mach-omap2/board-zoom-display.c
+++ b/arch/arm/mach-omap2/board-zoom-display.c
@@ -12,12 +12,12 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
-#include <linux/i2c/twl.h>
 #include <linux/spi/spi.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
 #include <video/omapdss.h>
-#include "board-zoom.h"
+#include <video/omap-panel-data.h>
 
+#include "board-zoom.h"
 #include "soc.h"
 #include "common.h"
 
@@ -25,92 +25,17 @@
 #define LCD_PANEL_RESET_GPIO_PILOT      55
 #define LCD_PANEL_QVGA_GPIO             56
 
-static struct gpio zoom_lcd_gpios[] __initdata = {
-        { -EINVAL,              GPIOF_OUT_INIT_HIGH, "lcd reset" },
-        { LCD_PANEL_QVGA_GPIO,  GPIOF_OUT_INIT_HIGH, "lcd qvga"  },
+static struct panel_nec_nl8048_data zoom_lcd_data = {
+        /* res_gpio filled in code */
+        .qvga_gpio = LCD_PANEL_QVGA_GPIO,
 };
 
-static void __init zoom_lcd_panel_init(void)
-{
-        zoom_lcd_gpios[0].gpio = (omap_rev() > OMAP3430_REV_ES3_0) ?
-                        LCD_PANEL_RESET_GPIO_PROD :
-                        LCD_PANEL_RESET_GPIO_PILOT;
-
-        if (gpio_request_array(zoom_lcd_gpios, ARRAY_SIZE(zoom_lcd_gpios)))
-                pr_err("%s: Failed to get LCD GPIOs.\n", __func__);
-}
-
-static int zoom_panel_enable_lcd(struct omap_dss_device *dssdev)
-{
-        return 0;
-}
-
-static void zoom_panel_disable_lcd(struct omap_dss_device *dssdev)
-{
-}
-
-/* Register offsets in TWL4030_MODULE_INTBR */
-#define TWL_INTBR_PMBR1 0xD
-#define TWL_INTBR_GPBR1 0xC
-
-/* Register offsets in TWL_MODULE_PWM */
-#define TWL_LED_PWMON   0x3
-#define TWL_LED_PWMOFF  0x4
-
-static int zoom_set_bl_intensity(struct omap_dss_device *dssdev, int level)
-{
-#ifdef CONFIG_TWL4030_CORE
-        unsigned char c;
-        u8 mux_pwm, enb_pwm;
-
-        if (level > 100)
-                return -1;
-
-        twl_i2c_read_u8(TWL4030_MODULE_INTBR, &mux_pwm, TWL_INTBR_PMBR1);
-        twl_i2c_read_u8(TWL4030_MODULE_INTBR, &enb_pwm, TWL_INTBR_GPBR1);
-
-        if (level == 0) {
-                /* disable pwm1 output and clock */
-                enb_pwm = enb_pwm & 0xF5;
-                /* change pwm1 pin to gpio pin */
-                mux_pwm = mux_pwm & 0xCF;
-                twl_i2c_write_u8(TWL4030_MODULE_INTBR,
-                                        enb_pwm, TWL_INTBR_GPBR1);
-                twl_i2c_write_u8(TWL4030_MODULE_INTBR,
-                                        mux_pwm, TWL_INTBR_PMBR1);
-                return 0;
-        }
-
-        if (!((enb_pwm & 0xA) && (mux_pwm & 0x30))) {
-                /* change gpio pin to pwm1 pin */
-                mux_pwm = mux_pwm | 0x30;
-                /* enable pwm1 output and clock*/
-                enb_pwm = enb_pwm | 0x0A;
-                twl_i2c_write_u8(TWL4030_MODULE_INTBR,
-                                        mux_pwm, TWL_INTBR_PMBR1);
-                twl_i2c_write_u8(TWL4030_MODULE_INTBR,
-                                        enb_pwm, TWL_INTBR_GPBR1);
-        }
-
-        c = ((50 * (100 - level)) / 100) + 1;
-        twl_i2c_write_u8(TWL_MODULE_PWM, 0x7F, TWL_LED_PWMOFF);
-        twl_i2c_write_u8(TWL_MODULE_PWM, c, TWL_LED_PWMON);
-#else
-        pr_warn("Backlight not enabled\n");
-#endif
-
-        return 0;
-}
-
 static struct omap_dss_device zoom_lcd_device = {
         .name                   = "lcd",
         .driver_name            = "NEC_8048_panel",
         .type                   = OMAP_DISPLAY_TYPE_DPI,
         .phy.dpi.data_lines     = 24,
-        .platform_enable        = zoom_panel_enable_lcd,
-        .platform_disable       = zoom_panel_disable_lcd,
-        .max_backlight_level    = 100,
-        .set_backlight          = zoom_set_bl_intensity,
+        .data                   = &zoom_lcd_data,
 };
 
 static struct omap_dss_device *zoom_dss_devices[] = {
@@ -123,6 +48,13 @@ static struct omap_dss_board_info zoom_dss_data = {
         .default_device         = &zoom_lcd_device,
 };
 
+static void __init zoom_lcd_panel_init(void)
+{
+        zoom_lcd_data.res_gpio = (omap_rev() > OMAP3430_REV_ES3_0) ?
+                        LCD_PANEL_RESET_GPIO_PROD :
+                        LCD_PANEL_RESET_GPIO_PILOT;
+}
+
 static struct omap2_mcspi_device_config dss_lcd_mcspi_config = {
         .turbo_mode             = 1,
 };
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index cdc0c1021863..a90375d5b2b6 100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -22,6 +22,9 @@
 #include <linux/platform_data/gpio-omap.h>
 #include <linux/platform_data/omap-twl4030.h>
 #include <linux/usb/phy.h>
+#include <linux/pwm.h>
+#include <linux/leds_pwm.h>
+#include <linux/pwm_backlight.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -193,6 +196,53 @@ static struct platform_device omap_vwlan_device = {
         },
 };
 
+static struct pwm_lookup zoom_pwm_lookup[] = {
+        PWM_LOOKUP("twl-pwm", 0, "leds_pwm", "zoom::keypad"),
+        PWM_LOOKUP("twl-pwm", 1, "pwm-backlight", "backlight"),
+};
+
+static struct led_pwm zoom_pwm_leds[] = {
+        {
+                .name           = "zoom::keypad",
+                .max_brightness = 127,
+                .pwm_period_ns  = 7812500,
+        },
+};
+
+static struct led_pwm_platform_data zoom_pwm_data = {
+        .num_leds       = ARRAY_SIZE(zoom_pwm_leds),
+        .leds           = zoom_pwm_leds,
+};
+
+static struct platform_device zoom_leds_pwm = {
+        .name   = "leds_pwm",
+        .id     = -1,
+        .dev    = {
+                .platform_data = &zoom_pwm_data,
+        },
+};
+
+static struct platform_pwm_backlight_data zoom_backlight_data = {
+        .pwm_id = 1,
+        .max_brightness = 127,
+        .dft_brightness = 127,
+        .pwm_period_ns = 7812500,
+};
+
+static struct platform_device zoom_backlight_pwm = {
+        .name   = "pwm-backlight",
+        .id     = -1,
+        .dev    = {
+                .platform_data = &zoom_backlight_data,
+        },
+};
+
+static struct platform_device *zoom_devices[] __initdata = {
+        &omap_vwlan_device,
+        &zoom_leds_pwm,
+        &zoom_backlight_pwm,
+};
+
 static struct wl12xx_platform_data omap_zoom_wlan_data __initdata = {
         .board_ref_clock = WL12XX_REFCLOCK_26, /* 26 MHz */
 };
@@ -301,7 +351,8 @@ void __init zoom_peripherals_init(void)
 
         omap_hsmmc_init(mmc);
         omap_i2c_init();
-        platform_device_register(&omap_vwlan_device);
+        pwm_add_table(zoom_pwm_lookup, ARRAY_SIZE(zoom_pwm_lookup));
+        platform_add_devices(zoom_devices, ARRAY_SIZE(zoom_devices));
         usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
         usb_musb_init(NULL);
         enable_board_wakeup_source();
diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
index 3d58f335f173..0c6834ae1fc4 100644
--- a/arch/arm/mach-omap2/cclock44xx_data.c
+++ b/arch/arm/mach-omap2/cclock44xx_data.c
@@ -52,6 +52,13 @@
  */
 #define OMAP4_DPLL_ABE_DEFFREQ                          98304000
 
+/*
+ * OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section
+ * "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred
+ * locked frequency for the USB DPLL is 960MHz.
+ */
+#define OMAP4_DPLL_USB_DEFFREQ                          960000000
+
 /* Root clocks */
 
 DEFINE_CLK_FIXED_RATE(extalt_clkin_ck, CLK_IS_ROOT, 59000000, 0x0);
@@ -1011,6 +1018,10 @@ DEFINE_CLK_OMAP_MUX(hsmmc2_fclk, "l3_init_clkdm", hsmmc1_fclk_sel,
                     OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK,
                     hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops);
 
+DEFINE_CLK_GATE(ocp2scp_usb_phy_phy_48m, "func_48m_fclk", &func_48m_fclk, 0x0,
+                OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
+                OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, 0x0, NULL);
+
 DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0,
                 OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
@@ -1538,6 +1549,7 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "per_mcbsp4_gfclk",                     &per_mcbsp4_gfclk,      CK_443X),
         CLK(NULL,       "hsmmc1_fclk",                  &hsmmc1_fclk,   CK_443X),
         CLK(NULL,       "hsmmc2_fclk",                  &hsmmc2_fclk,   CK_443X),
+        CLK(NULL,       "ocp2scp_usb_phy_phy_48m",      &ocp2scp_usb_phy_phy_48m,       CK_443X),
         CLK(NULL,       "sha2md5_fck",                  &sha2md5_fck,   CK_443X),
         CLK(NULL,       "slimbus1_fclk_1",              &slimbus1_fclk_1,       CK_443X),
         CLK(NULL,       "slimbus1_fclk_0",              &slimbus1_fclk_0,       CK_443X),
@@ -1705,5 +1717,13 @@ int __init omap4xxx_clk_init(void)
         if (rc)
                 pr_err("%s: failed to configure ABE DPLL!\n", __func__);
 
+        /*
+         * Lock USB DPLL on OMAP4 devices so that the L3INIT power
+         * domain can transition to retention state when not in use.
+         */
+        rc = clk_set_rate(&dpll_usb_ck, OMAP4_DPLL_USB_DEFFREQ);
+        if (rc)
+                pr_err("%s: failed to configure USB DPLL!\n", __func__);
+
         return 0;
 }
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index bf70e2b57ff8..272490e72ee0 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -292,5 +292,8 @@ extern void omap_reserve(void);
 struct omap_hwmod;
 extern int omap_dss_reset(struct omap_hwmod *);
 
+/* SoC specific clock initializer */
+extern int (*omap_clk_init)(void);
+
 #endif /* __ASSEMBLER__ */
 #endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */
diff --git a/arch/arm/mach-omap2/dss-common.c b/arch/arm/mach-omap2/dss-common.c
index 4be5cfc81ab8..393aeefaebb0 100644
--- a/arch/arm/mach-omap2/dss-common.c
+++ b/arch/arm/mach-omap2/dss-common.c
@@ -27,9 +27,7 @@
 #include <linux/gpio.h>
 
 #include <video/omapdss.h>
-#include <video/omap-panel-tfp410.h>
-#include <video/omap-panel-nokia-dsi.h>
-#include <video/omap-panel-picodlp.h>
+#include <video/omap-panel-data.h>
 
 #include "soc.h"
 #include "dss-common.h"
@@ -54,7 +52,6 @@ static struct omap_dss_device omap4_panda_dvi_device = {
         .driver_name            = "tfp410",
         .data                   = &omap4_dvi_panel,
         .phy.dpi.data_lines     = 24,
-        .reset_gpio             = PANDA_DVI_TFP410_POWER_DOWN_GPIO,
         .channel                = OMAP_DSS_CHANNEL_LCD2,
 };
 
@@ -179,45 +176,12 @@ static struct picodlp_panel_data sdp4430_picodlp_pdata = {
         .pwrgood_gpio           = 45,
 };
 
-static void sdp4430_picodlp_init(void)
-{
-        int r;
-        const struct gpio picodlp_gpios[] = {
-                {DLP_POWER_ON_GPIO, GPIOF_OUT_INIT_LOW,
-                        "DLP POWER ON"},
-                {sdp4430_picodlp_pdata.emu_done_gpio, GPIOF_IN,
-                        "DLP EMU DONE"},
-                {sdp4430_picodlp_pdata.pwrgood_gpio, GPIOF_OUT_INIT_LOW,
-                        "DLP PWRGOOD"},
-        };
-
-        r = gpio_request_array(picodlp_gpios, ARRAY_SIZE(picodlp_gpios));
-        if (r)
-                pr_err("Cannot request PicoDLP GPIOs, error %d\n", r);
-}
-
-static int sdp4430_panel_enable_picodlp(struct omap_dss_device *dssdev)
-{
-        gpio_set_value(DISPLAY_SEL_GPIO, 0);
-        gpio_set_value(DLP_POWER_ON_GPIO, 1);
-
-        return 0;
-}
-
-static void sdp4430_panel_disable_picodlp(struct omap_dss_device *dssdev)
-{
-        gpio_set_value(DLP_POWER_ON_GPIO, 0);
-        gpio_set_value(DISPLAY_SEL_GPIO, 1);
-}
-
 static struct omap_dss_device sdp4430_picodlp_device = {
         .name                   = "picodlp",
         .driver_name            = "picodlp_panel",
         .type                   = OMAP_DISPLAY_TYPE_DPI,
         .phy.dpi.data_lines     = 24,
         .channel                = OMAP_DSS_CHANNEL_LCD2,
-        .platform_enable        = sdp4430_panel_enable_picodlp,
-        .platform_disable       = sdp4430_panel_disable_picodlp,
         .data                   = &sdp4430_picodlp_pdata,
 };
 
@@ -234,17 +198,26 @@ static struct omap_dss_board_info sdp4430_dss_data = {
         .default_device = &sdp4430_lcd_device,
 };
 
+/*
+ * we select LCD2 by default (instead of Pico DLP) by setting DISPLAY_SEL_GPIO.
+ * Setting DLP_POWER_ON gpio enables the VDLP_2V5 VDLP_1V8 and VDLP_1V0 rails
+ * used by picodlp on the 4430sdp platform. Keep this gpio disabled as LCD2 is
+ * selected by default
+ */
 void __init omap_4430sdp_display_init(void)
 {
         int r;
 
-        /* Enable LCD2 by default (instead of Pico DLP) */
         r = gpio_request_one(DISPLAY_SEL_GPIO, GPIOF_OUT_INIT_HIGH,
                         "display_sel");
         if (r)
                 pr_err("%s: Could not get display_sel GPIO\n", __func__);
 
-        sdp4430_picodlp_init();
+        r = gpio_request_one(DLP_POWER_ON_GPIO, GPIOF_OUT_INIT_LOW,
+                "DLP POWER ON");
+        if (r)
+                pr_err("%s: Could not get DLP POWER ON GPIO\n", __func__);
+
         omap_display_init(&sdp4430_dss_data);
         /*
          * OMAP4460SDP/Blaze and OMAP4430 ES2.3 SDP/Blaze boards and
@@ -264,12 +237,15 @@ void __init omap_4430sdp_display_init_of(void)
 {
         int r;
 
-        /* Enable LCD2 by default (instead of Pico DLP) */
         r = gpio_request_one(DISPLAY_SEL_GPIO, GPIOF_OUT_INIT_HIGH,
                         "display_sel");
         if (r)
                 pr_err("%s: Could not get display_sel GPIO\n", __func__);
 
-        sdp4430_picodlp_init();
+        r = gpio_request_one(DLP_POWER_ON_GPIO, GPIOF_OUT_INIT_LOW,
+                "DLP POWER ON");
+        if (r)
+                pr_err("%s: Could not get DLP POWER ON GPIO\n", __func__);
+
         omap_display_init(&sdp4430_dss_data);
 }
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index afc1e8c32d6c..d9c27195caf0 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -74,14 +74,6 @@ static int omap2_nand_gpmc_retime(
         t.cs_wr_off = gpmc_t->cs_wr_off;
         t.wr_cycle = gpmc_t->wr_cycle;
 
-        /* Configure GPMC */
-        if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
-                gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 1);
-        else
-                gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 0);
-        gpmc_cs_configure(gpmc_nand_data->cs,
-                        GPMC_CONFIG_DEV_TYPE, GPMC_DEVICETYPE_NAND);
-        gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_WP, 0);
         err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t);
         if (err)
                 return err;
@@ -115,14 +107,18 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
                    struct gpmc_timings *gpmc_t)
 {
         int err = 0;
+        struct gpmc_settings s;
         struct device *dev = &gpmc_nand_device.dev;
 
+        memset(&s, 0, sizeof(struct gpmc_settings));
+
         gpmc_nand_device.dev.platform_data = gpmc_nand_data;
 
         err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE,
                                 (unsigned long *)&gpmc_nand_resource[0].start);
         if (err < 0) {
-                dev_err(dev, "Cannot request GPMC CS\n");
+                dev_err(dev, "Cannot request GPMC CS %d, error %d\n",
+                        gpmc_nand_data->cs, err);
                 return err;
         }
 
@@ -140,11 +136,31 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
                         dev_err(dev, "Unable to set gpmc timings: %d\n", err);
                         return err;
                 }
-        }
 
-        /* Enable RD PIN Monitoring Reg */
-        if (gpmc_nand_data->dev_ready) {
-                gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_RDY_BSY, 1);
+                if (gpmc_nand_data->of_node) {
+                        gpmc_read_settings_dt(gpmc_nand_data->of_node, &s);
+                } else {
+                        s.device_nand = true;
+
+                        /* Enable RD PIN Monitoring Reg */
+                        if (gpmc_nand_data->dev_ready) {
+                                s.wait_on_read = true;
+                                s.wait_on_write = true;
+                        }
+                }
+
+                if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
+                        s.device_width = GPMC_DEVWIDTH_16BIT;
+                else
+                        s.device_width = GPMC_DEVWIDTH_8BIT;
+
+                err = gpmc_cs_program_settings(gpmc_nand_data->cs, &s);
+                if (err < 0)
+                        goto out_free_cs;
+
+                err = gpmc_configure(GPMC_CONFIG_WP, 0);
+                if (err < 0)
+                        goto out_free_cs;
         }
 
         gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs);
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index 0d75889c0a6f..64b5a8346982 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -47,11 +47,23 @@ static struct platform_device gpmc_onenand_device = {
         .resource       = &gpmc_onenand_resource,
 };
 
-static struct gpmc_timings omap2_onenand_calc_async_timings(void)
+static struct gpmc_settings onenand_async = {
+        .device_width   = GPMC_DEVWIDTH_16BIT,
+        .mux_add_data   = GPMC_MUX_AD,
+};
+
+static struct gpmc_settings onenand_sync = {
+        .burst_read     = true,
+        .burst_wrap     = true,
+        .burst_len      = GPMC_BURST_16,
+        .device_width   = GPMC_DEVWIDTH_16BIT,
+        .mux_add_data   = GPMC_MUX_AD,
+        .wait_pin       = 0,
+};
+
+static void omap2_onenand_calc_async_timings(struct gpmc_timings *t)
 {
         struct gpmc_device_timings dev_t;
-        struct gpmc_timings t;
-
         const int t_cer = 15;
         const int t_avdp = 12;
         const int t_aavdh = 7;
@@ -64,7 +76,6 @@ static struct gpmc_timings omap2_onenand_calc_async_timings(void)
 
         memset(&dev_t, 0, sizeof(dev_t));
 
-        dev_t.mux = true;
         dev_t.t_avdp_r = max_t(int, t_avdp, t_cer) * 1000;
         dev_t.t_avdp_w = dev_t.t_avdp_r;
         dev_t.t_aavdh = t_aavdh * 1000;
@@ -76,19 +87,7 @@ static struct gpmc_timings omap2_onenand_calc_async_timings(void)
         dev_t.t_wpl = t_wpl * 1000;
         dev_t.t_wph = t_wph * 1000;
 
-        gpmc_calc_timings(&t, &dev_t);
-
-        return t;
-}
-
-static int gpmc_set_async_mode(int cs, struct gpmc_timings *t)
-{
-        /* Configure GPMC for asynchronous read */
-        gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1,
-                          GPMC_CONFIG1_DEVICESIZE_16 |
-                          GPMC_CONFIG1_MUXADDDATA);
-
-        return gpmc_cs_set_timings(cs, t);
+        gpmc_calc_timings(t, &onenand_async, &dev_t);
 }
 
 static void omap2_onenand_set_async_mode(void __iomem *onenand_base)
@@ -158,12 +157,11 @@ static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg,
         return freq;
 }
 
-static struct gpmc_timings
-omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg,
-                                int freq)
+static void omap2_onenand_calc_sync_timings(struct gpmc_timings *t,
+                                            unsigned int flags,
+                                            int freq)
 {
         struct gpmc_device_timings dev_t;
-        struct gpmc_timings t;
         const int t_cer  = 15;
         const int t_avdp = 12;
         const int t_cez  = 20; /* max of t_cez, t_oez */
@@ -172,9 +170,9 @@ omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg,
         int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
         int div, gpmc_clk_ns;
 
-        if (cfg->flags & ONENAND_SYNC_READ)
+        if (flags & ONENAND_SYNC_READ)
                 onenand_flags = ONENAND_FLAG_SYNCREAD;
-        else if (cfg->flags & ONENAND_SYNC_READWRITE)
+        else if (flags & ONENAND_SYNC_READWRITE)
                 onenand_flags = ONENAND_FLAG_SYNCREAD | ONENAND_FLAG_SYNCWRITE;
 
         switch (freq) {
@@ -239,10 +237,11 @@ omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg,
         /* Set synchronous read timings */
         memset(&dev_t, 0, sizeof(dev_t));
 
-        dev_t.mux = true;
-        dev_t.sync_read = true;
+        if (onenand_flags & ONENAND_FLAG_SYNCREAD)
+                onenand_sync.sync_read = true;
         if (onenand_flags & ONENAND_FLAG_SYNCWRITE) {
-                dev_t.sync_write = true;
+                onenand_sync.sync_write = true;
+                onenand_sync.burst_write = true;
         } else {
                 dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000;
                 dev_t.t_wpl = t_wpl * 1000;
@@ -265,32 +264,7 @@ omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg,
         dev_t.cyc_aavdh_oe = 1;
         dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period;
 
-        gpmc_calc_timings(&t, &dev_t);
-
-        return t;
-}
-
-static int gpmc_set_sync_mode(int cs, struct gpmc_timings *t)
-{
-        unsigned sync_read = onenand_flags & ONENAND_FLAG_SYNCREAD;
-        unsigned sync_write = onenand_flags & ONENAND_FLAG_SYNCWRITE;
-
-        /* Configure GPMC for synchronous read */
-        gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1,
-                          GPMC_CONFIG1_WRAPBURST_SUPP |
-                          GPMC_CONFIG1_READMULTIPLE_SUPP |
-                          (sync_read ? GPMC_CONFIG1_READTYPE_SYNC : 0) |
-                          (sync_write ? GPMC_CONFIG1_WRITEMULTIPLE_SUPP : 0) |
-                          (sync_write ? GPMC_CONFIG1_WRITETYPE_SYNC : 0) |
-                          GPMC_CONFIG1_PAGE_LEN(2) |
-                          (cpu_is_omap34xx() ? 0 :
-                                (GPMC_CONFIG1_WAIT_READ_MON |
-                                 GPMC_CONFIG1_WAIT_PIN_SEL(0))) |
-                          GPMC_CONFIG1_DEVICESIZE_16 |
-                          GPMC_CONFIG1_DEVICETYPE_NOR |
-                          GPMC_CONFIG1_MUXADDDATA);
-
-        return gpmc_cs_set_timings(cs, t);
+        gpmc_calc_timings(t, &onenand_sync, &dev_t);
 }
 
 static int omap2_onenand_setup_async(void __iomem *onenand_base)
@@ -298,11 +272,19 @@ static int omap2_onenand_setup_async(void __iomem *onenand_base)
         struct gpmc_timings t;
         int ret;
 
+        if (gpmc_onenand_data->of_node)
+                gpmc_read_settings_dt(gpmc_onenand_data->of_node,
+                                      &onenand_async);
+
         omap2_onenand_set_async_mode(onenand_base);
 
-        t = omap2_onenand_calc_async_timings();
+        omap2_onenand_calc_async_timings(&t);
+
+        ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_async);
+        if (ret < 0)
+                return ret;
 
-        ret = gpmc_set_async_mode(gpmc_onenand_data->cs, &t);
+        ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t);
         if (ret < 0)
                 return ret;
 
@@ -322,9 +304,25 @@ static int omap2_onenand_setup_sync(void __iomem *onenand_base, int *freq_ptr)
                 set_onenand_cfg(onenand_base);
         }
 
-        t = omap2_onenand_calc_sync_timings(gpmc_onenand_data, freq);
+        if (gpmc_onenand_data->of_node) {
+                gpmc_read_settings_dt(gpmc_onenand_data->of_node,
+                                      &onenand_sync);
+        } else {
+                /*
+                 * FIXME: Appears to be legacy code from initial ONENAND commit.
+                 * Unclear what boards this is for and if this can be removed.
+                 */
+                if (!cpu_is_omap34xx())
+                        onenand_sync.wait_on_read = true;
+        }
 
-        ret = gpmc_set_sync_mode(gpmc_onenand_data->cs, &t);
+        omap2_onenand_calc_sync_timings(&t, gpmc_onenand_data->flags, freq);
+
+        ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_sync);
+        if (ret < 0)
+                return ret;
+
+        ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t);
         if (ret < 0)
                 return ret;
 
@@ -359,6 +357,7 @@ static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
 void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
 {
         int err;
+        struct device *dev = &gpmc_onenand_device.dev;
 
         gpmc_onenand_data = _onenand_data;
         gpmc_onenand_data->onenand_setup = gpmc_onenand_setup;
@@ -366,7 +365,7 @@ void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
 
         if (cpu_is_omap24xx() &&
                         (gpmc_onenand_data->flags & ONENAND_SYNC_READWRITE)) {
-                printk(KERN_ERR "Onenand using only SYNC_READ on 24xx\n");
+                dev_warn(dev, "OneNAND using only SYNC_READ on 24xx\n");
                 gpmc_onenand_data->flags &= ~ONENAND_SYNC_READWRITE;
                 gpmc_onenand_data->flags |= ONENAND_SYNC_READ;
         }
@@ -379,7 +378,8 @@ void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
         err = gpmc_cs_request(gpmc_onenand_data->cs, ONENAND_IO_SIZE,
                                 (unsigned long *)&gpmc_onenand_resource.start);
         if (err < 0) {
-                pr_err("%s: Cannot request GPMC CS\n", __func__);
+                dev_err(dev, "Cannot request GPMC CS %d, error %d\n",
+                        gpmc_onenand_data->cs, err);
                 return;
         }
 
@@ -387,7 +387,7 @@ void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
                                                         ONENAND_IO_SIZE - 1;
 
         if (platform_device_register(&gpmc_onenand_device) < 0) {
-                pr_err("%s: Unable to register OneNAND device\n", __func__);
+                dev_err(dev, "Unable to register OneNAND device\n");
                 gpmc_cs_free(gpmc_onenand_data->cs);
                 return;
         }
diff --git a/arch/arm/mach-omap2/gpmc-smc91x.c b/arch/arm/mach-omap2/gpmc-smc91x.c
index 11d0b756f098..61a063595e66 100644
--- a/arch/arm/mach-omap2/gpmc-smc91x.c
+++ b/arch/arm/mach-omap2/gpmc-smc91x.c
@@ -49,6 +49,10 @@ static struct platform_device gpmc_smc91x_device = {
         .resource       = gpmc_smc91x_resources,
 };
 
+static struct gpmc_settings smc91x_settings = {
+        .device_width = GPMC_DEVWIDTH_16BIT,
+};
+
 /*
  * Set the gpmc timings for smc91c96. The timings are taken
  * from the data sheet available at:
@@ -67,18 +71,6 @@ static int smc91c96_gpmc_retime(void)
         const int t7 = 5;       /* Figure 12.4 write */
         const int t8 = 5;       /* Figure 12.4 write */
         const int t20 = 185;    /* Figure 12.2 read and 12.4 write */
-        u32 l;
-
-        l = GPMC_CONFIG1_DEVICESIZE_16;
-        if (gpmc_cfg->flags & GPMC_MUX_ADD_DATA)
-                l |= GPMC_CONFIG1_MUXADDDATA;
-        if (gpmc_cfg->flags & GPMC_READ_MON)
-                l |= GPMC_CONFIG1_WAIT_READ_MON;
-        if (gpmc_cfg->flags & GPMC_WRITE_MON)
-                l |= GPMC_CONFIG1_WAIT_WRITE_MON;
-        if (gpmc_cfg->wait_pin)
-                l |= GPMC_CONFIG1_WAIT_PIN_SEL(gpmc_cfg->wait_pin);
-        gpmc_cs_write_reg(gpmc_cfg->cs, GPMC_CS_CONFIG1, l);
 
         /*
          * FIXME: Calculate the address and data bus muxed timings.
@@ -104,7 +96,7 @@ static int smc91c96_gpmc_retime(void)
         dev_t.t_cez_w = t4_w * 1000;
         dev_t.t_wr_cycle = (t20 - t3) * 1000;
 
-        gpmc_calc_timings(&t, &dev_t);
+        gpmc_calc_timings(&t, &smc91x_settings, &dev_t);
 
         return gpmc_cs_set_timings(gpmc_cfg->cs, &t);
 }
@@ -133,6 +125,18 @@ void __init gpmc_smc91x_init(struct omap_smc91x_platform_data *board_data)
         gpmc_smc91x_resources[0].end = cs_mem_base + 0x30f;
         gpmc_smc91x_resources[1].flags |= (gpmc_cfg->flags & IRQF_TRIGGER_MASK);
 
+        if (gpmc_cfg->flags & GPMC_MUX_ADD_DATA)
+                smc91x_settings.mux_add_data = GPMC_MUX_AD;
+        if (gpmc_cfg->flags & GPMC_READ_MON)
+                smc91x_settings.wait_on_read = true;
+        if (gpmc_cfg->flags & GPMC_WRITE_MON)
+                smc91x_settings.wait_on_write = true;
+        if (gpmc_cfg->wait_pin)
+                smc91x_settings.wait_pin = gpmc_cfg->wait_pin;
+        ret = gpmc_cs_program_settings(gpmc_cfg->cs, &smc91x_settings);
+        if (ret < 0)
+                goto free1;
+
         if (gpmc_cfg->retime) {
                 ret = gpmc_cfg->retime();
                 if (ret != 0)
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 6de31739b45c..ed946df5ad8a 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -26,6 +26,7 @@
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
 #include <linux/of.h>
+#include <linux/of_address.h>
 #include <linux/of_mtd.h>
 #include <linux/of_device.h>
 #include <linux/mtd/nand.h>
@@ -91,9 +92,7 @@
 #define GPMC_CS_SIZE            0x30
 #define GPMC_BCH_SIZE           0x10
 
-#define GPMC_MEM_START          0x00000000
 #define GPMC_MEM_END            0x3FFFFFFF
-#define BOOT_ROM_SPACE          0x100000        /* 1MB */
 
 #define GPMC_CHUNK_SHIFT        24              /* 16 MB */
 #define GPMC_SECTION_SHIFT      28              /* 128 MB */
@@ -107,6 +106,9 @@
 
 #define GPMC_HAS_WR_ACCESS              0x1
 #define GPMC_HAS_WR_DATA_MUX_BUS        0x2
+#define GPMC_HAS_MUX_AAD                0x4
+
+#define GPMC_NR_WAITPINS                4
 
 /* XXX: Only NAND irq has been considered,currently these are the only ones used
  */
@@ -153,6 +155,7 @@ static struct resource	gpmc_cs_mem[GPMC_CS_NUM];
 static DEFINE_SPINLOCK(gpmc_mem_lock);
 /* Define chip-selects as reserved by default until probe completes */
 static unsigned int gpmc_cs_map = ((1 << GPMC_CS_NUM) - 1);
+static unsigned int gpmc_nr_waitpins;
 static struct device *gpmc_dev;
 static int gpmc_irq;
 static resource_size_t phys_base, mem_size;
@@ -181,7 +184,7 @@ void gpmc_cs_write_reg(int cs, int idx, u32 val)
         __raw_writel(val, reg_addr);
 }
 
-u32 gpmc_cs_read_reg(int cs, int idx)
+static u32 gpmc_cs_read_reg(int cs, int idx)
 {
         void __iomem *reg_addr;
 
@@ -190,7 +193,7 @@ u32 gpmc_cs_read_reg(int cs, int idx)
 }
 
 /* TODO: Add support for gpmc_fck to clock framework and use it */
-unsigned long gpmc_get_fclk_period(void)
+static unsigned long gpmc_get_fclk_period(void)
 {
         unsigned long rate = clk_get_rate(gpmc_l3_clk);
 
@@ -205,7 +208,7 @@ unsigned long gpmc_get_fclk_period(void)
         return rate;
 }
 
-unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
+static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
 {
         unsigned long tick_ps;
 
@@ -215,7 +218,7 @@ unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
         return (time_ns * 1000 + tick_ps - 1) / tick_ps;
 }
 
-unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
+static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
 {
         unsigned long tick_ps;
 
@@ -230,13 +233,6 @@ unsigned int gpmc_ticks_to_ns(unsigned int ticks)
         return ticks * gpmc_get_fclk_period() / 1000;
 }
 
-unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
-{
-        unsigned long ticks = gpmc_ns_to_ticks(time_ns);
-
-        return ticks * gpmc_get_fclk_period() / 1000;
-}
-
 static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
 {
         return ticks * gpmc_get_fclk_period();
@@ -405,11 +401,18 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
         return 0;
 }
 
-static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
+static int gpmc_cs_enable_mem(int cs, u32 base, u32 size)
 {
         u32 l;
         u32 mask;
 
+        /*
+         * Ensure that base address is aligned on a
+         * boundary equal to or greater than size.
+         */
+        if (base & (size - 1))
+                return -EINVAL;
+
         mask = (1 << GPMC_SECTION_SHIFT) - size;
         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
         l &= ~0x3f;
@@ -418,6 +421,8 @@ static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
         l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
         l |= GPMC_CONFIG7_CSVALID;
         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
+
+        return 0;
 }
 
 static void gpmc_cs_disable_mem(int cs)
@@ -448,22 +453,14 @@ static int gpmc_cs_mem_enabled(int cs)
         return l & GPMC_CONFIG7_CSVALID;
 }
 
-int gpmc_cs_set_reserved(int cs, int reserved)
+static void gpmc_cs_set_reserved(int cs, int reserved)
 {
-        if (cs > GPMC_CS_NUM)
-                return -ENODEV;
-
         gpmc_cs_map &= ~(1 << cs);
         gpmc_cs_map |= (reserved ? 1 : 0) << cs;
-
-        return 0;
 }
 
-int gpmc_cs_reserved(int cs)
+static bool gpmc_cs_reserved(int cs)
 {
-        if (cs > GPMC_CS_NUM)
-                return -ENODEV;
-
         return gpmc_cs_map & (1 << cs);
 }
 
@@ -510,6 +507,39 @@ static int gpmc_cs_delete_mem(int cs)
         return r;
 }
 
+/**
+ * gpmc_cs_remap - remaps a chip-select physical base address
+ * @cs:         chip-select to remap
+ * @base:       physical base address to re-map chip-select to
+ *
+ * Re-maps a chip-select to a new physical base address specified by
+ * "base". Returns 0 on success and appropriate negative error code
+ * on failure.
+ */
+static int gpmc_cs_remap(int cs, u32 base)
+{
+        int ret;
+        u32 old_base, size;
+
+        if (cs > GPMC_CS_NUM)
+                return -ENODEV;
+        gpmc_cs_get_memconf(cs, &old_base, &size);
+        if (base == old_base)
+                return 0;
+        gpmc_cs_disable_mem(cs);
+        ret = gpmc_cs_delete_mem(cs);
+        if (ret < 0)
+                return ret;
+        ret = gpmc_cs_insert_mem(cs, base, size);
+        if (ret < 0)
+                return ret;
+        ret = gpmc_cs_enable_mem(cs, base, size);
+        if (ret < 0)
+                return ret;
+
+        return 0;
+}
+
 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
 {
         struct resource *res = &gpmc_cs_mem[cs];
@@ -535,7 +565,12 @@ int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
         if (r < 0)
                 goto out;
 
-        gpmc_cs_enable_mem(cs, res->start, resource_size(res));
+        r = gpmc_cs_enable_mem(cs, res->start, resource_size(res));
+        if (r < 0) {
+                release_resource(res);
+                goto out;
+        }
+
         *base = res->start;
         gpmc_cs_set_reserved(cs, 1);
 out:
@@ -561,16 +596,14 @@ void gpmc_cs_free(int cs)
 EXPORT_SYMBOL(gpmc_cs_free);
 
 /**
- * gpmc_cs_configure - write request to configure gpmc
- * @cs: chip select number
+ * gpmc_configure - write request to configure gpmc
  * @cmd: command type
  * @wval: value to write
  * @return status of the operation
  */
-int gpmc_cs_configure(int cs, int cmd, int wval)
+int gpmc_configure(int cmd, int wval)
 {
-        int err = 0;
-        u32 regval = 0;
+        u32 regval;
 
         switch (cmd) {
         case GPMC_ENABLE_IRQ:
@@ -590,43 +623,14 @@ int gpmc_cs_configure(int cs, int cmd, int wval)
                 gpmc_write_reg(GPMC_CONFIG, regval);
                 break;
 
-        case GPMC_CONFIG_RDY_BSY:
-                regval  = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
-                if (wval)
-                        regval |= WR_RD_PIN_MONITORING;
-                else
-                        regval &= ~WR_RD_PIN_MONITORING;
-                gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
-                break;
-
-        case GPMC_CONFIG_DEV_SIZE:
-                regval  = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
-
-                /* clear 2 target bits */
-                regval &= ~GPMC_CONFIG1_DEVICESIZE(3);
-
-                /* set the proper value */
-                regval |= GPMC_CONFIG1_DEVICESIZE(wval);
-
-                gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
-                break;
-
-        case GPMC_CONFIG_DEV_TYPE:
-                regval  = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
-                regval |= GPMC_CONFIG1_DEVICETYPE(wval);
-                if (wval == GPMC_DEVICETYPE_NOR)
-                        regval |= GPMC_CONFIG1_MUXADDDATA;
-                gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
-                break;
-
         default:
-                printk(KERN_ERR "gpmc_configure_cs: Not supported\n");
-                err = -EINVAL;
+                pr_err("%s: command not supported\n", __func__);
+                return -EINVAL;
         }
 
-        return err;
+        return 0;
 }
-EXPORT_SYMBOL(gpmc_cs_configure);
+EXPORT_SYMBOL(gpmc_configure);
 
 void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
 {
@@ -781,16 +785,16 @@ static void gpmc_mem_exit(void)
 
 }
 
-static int gpmc_mem_init(void)
+static void gpmc_mem_init(void)
 {
-        int cs, rc;
-        unsigned long boot_rom_space = 0;
+        int cs;
 
-        /* never allocate the first page, to facilitate bug detection;
-         * even if we didn't boot from ROM.
+        /*
+         * The first 1MB of GPMC address space is typically mapped to
+         * the internal ROM. Never allocate the first page, to
+         * facilitate bug detection; even if we didn't boot from ROM.
          */
-        boot_rom_space = BOOT_ROM_SPACE;
-        gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
+        gpmc_mem_root.start = SZ_1M;
         gpmc_mem_root.end = GPMC_MEM_END;
 
         /* Reserve all regions that has been set up by bootloader */
@@ -800,16 +804,12 @@ static int gpmc_mem_init(void)
                 if (!gpmc_cs_mem_enabled(cs))
                         continue;
                 gpmc_cs_get_memconf(cs, &base, &size);
-                rc = gpmc_cs_insert_mem(cs, base, size);
-                if (rc < 0) {
-                        while (--cs >= 0)
-                                if (gpmc_cs_mem_enabled(cs))
-                                        gpmc_cs_delete_mem(cs);
-                        return rc;
+                if (gpmc_cs_insert_mem(cs, base, size)) {
+                        pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
+                                __func__, cs, base, base + size);
+                        gpmc_cs_disable_mem(cs);
                 }
         }
-
-        return 0;
 }
 
 static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
@@ -825,9 +825,9 @@ static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
 
 /* XXX: can the cycles be avoided ? */
 static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
-                                struct gpmc_device_timings *dev_t)
+                                       struct gpmc_device_timings *dev_t,
+                                       bool mux)
 {
-        bool mux = dev_t->mux;
         u32 temp;
 
         /* adv_rd_off */
@@ -880,9 +880,9 @@ static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
 }
 
 static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
-                                struct gpmc_device_timings *dev_t)
+                                        struct gpmc_device_timings *dev_t,
+                                        bool mux)
 {
-        bool mux = dev_t->mux;
         u32 temp;
 
         /* adv_wr_off */
@@ -942,9 +942,9 @@ static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
 }
 
 static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
-                                struct gpmc_device_timings *dev_t)
+                                        struct gpmc_device_timings *dev_t,
+                                        bool mux)
 {
-        bool mux = dev_t->mux;
         u32 temp;
 
         /* adv_rd_off */
@@ -982,9 +982,9 @@ static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
 }
 
 static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
-                                struct gpmc_device_timings *dev_t)
+                                         struct gpmc_device_timings *dev_t,
+                                         bool mux)
 {
-        bool mux = dev_t->mux;
         u32 temp;
 
         /* adv_wr_off */
@@ -1054,7 +1054,8 @@ static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
 }
 
 static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
-                        struct gpmc_device_timings *dev_t)
+                                    struct gpmc_device_timings *dev_t,
+                                    bool sync)
 {
         u32 temp;
 
@@ -1068,7 +1069,7 @@ static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
                                 gpmc_t->cs_on + dev_t->t_ce_avd);
         gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
 
-        if (dev_t->sync_write || dev_t->sync_read)
+        if (sync)
                 gpmc_calc_sync_common_timings(gpmc_t, dev_t);
 
         return 0;
@@ -1103,21 +1104,29 @@ static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
 }
 
 int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
-                        struct gpmc_device_timings *dev_t)
+                      struct gpmc_settings *gpmc_s,
+                      struct gpmc_device_timings *dev_t)
 {
+        bool mux = false, sync = false;
+
+        if (gpmc_s) {
+                mux = gpmc_s->mux_add_data ? true : false;
+                sync = (gpmc_s->sync_read || gpmc_s->sync_write);
+        }
+
         memset(gpmc_t, 0, sizeof(*gpmc_t));
 
-        gpmc_calc_common_timings(gpmc_t, dev_t);
+        gpmc_calc_common_timings(gpmc_t, dev_t, sync);
 
-        if (dev_t->sync_read)
-                gpmc_calc_sync_read_timings(gpmc_t, dev_t);
+        if (gpmc_s && gpmc_s->sync_read)
+                gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux);
         else
-                gpmc_calc_async_read_timings(gpmc_t, dev_t);
+                gpmc_calc_async_read_timings(gpmc_t, dev_t, mux);
 
-        if (dev_t->sync_write)
-                gpmc_calc_sync_write_timings(gpmc_t, dev_t);
+        if (gpmc_s && gpmc_s->sync_write)
+                gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux);
         else
-                gpmc_calc_async_write_timings(gpmc_t, dev_t);
+                gpmc_calc_async_write_timings(gpmc_t, dev_t, mux);
 
         /* TODO: remove, see function definition */
         gpmc_convert_ps_to_ns(gpmc_t);
@@ -1125,6 +1134,90 @@ int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
         return 0;
 }
 
+/**
+ * gpmc_cs_program_settings - programs non-timing related settings
+ * @cs:         GPMC chip-select to program
+ * @p:          pointer to GPMC settings structure
+ *
+ * Programs non-timing related settings for a GPMC chip-select, such as
+ * bus-width, burst configuration, etc. Function should be called once
+ * for each chip-select that is being used and must be called before
+ * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
+ * register will be initialised to zero by this function. Returns 0 on
+ * success and appropriate negative error code on failure.
+ */
+int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
+{
+        u32 config1;
+
+        if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) {
+                pr_err("%s: invalid width %d!", __func__, p->device_width);
+                return -EINVAL;
+        }
+
+        /* Address-data multiplexing not supported for NAND devices */
+        if (p->device_nand && p->mux_add_data) {
+                pr_err("%s: invalid configuration!\n", __func__);
+                return -EINVAL;
+        }
+
+        if ((p->mux_add_data > GPMC_MUX_AD) ||
+            ((p->mux_add_data == GPMC_MUX_AAD) &&
+             !(gpmc_capability & GPMC_HAS_MUX_AAD))) {
+                pr_err("%s: invalid multiplex configuration!\n", __func__);
+                return -EINVAL;
+        }
+
+        /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
+        if (p->burst_read || p->burst_write) {
+                switch (p->burst_len) {
+                case GPMC_BURST_4:
+                case GPMC_BURST_8:
+                case GPMC_BURST_16:
+                        break;
+                default:
+                        pr_err("%s: invalid page/burst-length (%d)\n",
+                               __func__, p->burst_len);
+                        return -EINVAL;
+                }
+        }
+
+        if ((p->wait_on_read || p->wait_on_write) &&
+            (p->wait_pin > gpmc_nr_waitpins)) {
+                pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
+                return -EINVAL;
+        }
+
+        config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
+
+        if (p->sync_read)
+                config1 |= GPMC_CONFIG1_READTYPE_SYNC;
+        if (p->sync_write)
+                config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
+        if (p->wait_on_read)
+                config1 |= GPMC_CONFIG1_WAIT_READ_MON;
+        if (p->wait_on_write)
+                config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
+        if (p->wait_on_read || p->wait_on_write)
+                config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
+        if (p->device_nand)
+                config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
+        if (p->mux_add_data)
+                config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
+        if (p->burst_read)
+                config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
+        if (p->burst_write)
+                config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
+        if (p->burst_read || p->burst_write) {
+                config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
+                config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
+        }
+
+        gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
+
+        return 0;
+}
+
 #ifdef CONFIG_OF
 static struct of_device_id gpmc_dt_ids[] = {
         { .compatible = "ti,omap2420-gpmc" },
@@ -1136,70 +1229,110 @@ static struct of_device_id gpmc_dt_ids[] = {
 };
 MODULE_DEVICE_TABLE(of, gpmc_dt_ids);
 
+/**
+ * gpmc_read_settings_dt - read gpmc settings from device-tree
+ * @np:         pointer to device-tree node for a gpmc child device
+ * @p:          pointer to gpmc settings structure
+ *
+ * Reads the GPMC settings for a GPMC child device from device-tree and
+ * stores them in the GPMC settings structure passed. The GPMC settings
+ * structure is initialised to zero by this function and so any
+ * previously stored settings will be cleared.
+ */
+void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
+{
+        memset(p, 0, sizeof(struct gpmc_settings));
+
+        p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
+        p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
+        p->device_nand = of_property_read_bool(np, "gpmc,device-nand");
+        of_property_read_u32(np, "gpmc,device-width", &p->device_width);
+        of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
+
+        if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
+                p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap");
+                p->burst_read = of_property_read_bool(np, "gpmc,burst-read");
+                p->burst_write = of_property_read_bool(np, "gpmc,burst-write");
+                if (!p->burst_read && !p->burst_write)
+                        pr_warn("%s: page/burst-length set but not used!\n",
+                                __func__);
+        }
+
+        if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
+                p->wait_on_read = of_property_read_bool(np,
+                                                        "gpmc,wait-on-read");
+                p->wait_on_write = of_property_read_bool(np,
+                                                         "gpmc,wait-on-write");
+                if (!p->wait_on_read && !p->wait_on_write)
+                        pr_warn("%s: read/write wait monitoring not enabled!\n",
+                                __func__);
+        }
+}
+
 static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
                                                 struct gpmc_timings *gpmc_t)
 {
-        u32 val;
+        struct gpmc_bool_timings *p;
+
+        if (!np || !gpmc_t)
+                return;
 
         memset(gpmc_t, 0, sizeof(*gpmc_t));
 
         /* minimum clock period for syncronous mode */
-        if (!of_property_read_u32(np, "gpmc,sync-clk", &val))
-                gpmc_t->sync_clk = val;
+        of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
 
         /* chip select timtings */
-        if (!of_property_read_u32(np, "gpmc,cs-on", &val))
-                gpmc_t->cs_on = val;
-
-        if (!of_property_read_u32(np, "gpmc,cs-rd-off", &val))
-                gpmc_t->cs_rd_off = val;
-
-        if (!of_property_read_u32(np, "gpmc,cs-wr-off", &val))
-                gpmc_t->cs_wr_off = val;
+        of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
+        of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
+        of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
 
         /* ADV signal timings */
-        if (!of_property_read_u32(np, "gpmc,adv-on", &val))
-                gpmc_t->adv_on = val;
-
-        if (!of_property_read_u32(np, "gpmc,adv-rd-off", &val))
-                gpmc_t->adv_rd_off = val;
-
-        if (!of_property_read_u32(np, "gpmc,adv-wr-off", &val))
-                gpmc_t->adv_wr_off = val;
+        of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
+        of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
+        of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
 
         /* WE signal timings */
-        if (!of_property_read_u32(np, "gpmc,we-on", &val))
-                gpmc_t->we_on = val;
-
-        if (!of_property_read_u32(np, "gpmc,we-off", &val))
-                gpmc_t->we_off = val;
+        of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
+        of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
 
         /* OE signal timings */
-        if (!of_property_read_u32(np, "gpmc,oe-on", &val))
-                gpmc_t->oe_on = val;
-
-        if (!of_property_read_u32(np, "gpmc,oe-off", &val))
-                gpmc_t->oe_off = val;
+        of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
+        of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
 
         /* access and cycle timings */
-        if (!of_property_read_u32(np, "gpmc,page-burst-access", &val))
-                gpmc_t->page_burst_access = val;
-
-        if (!of_property_read_u32(np, "gpmc,access", &val))
-                gpmc_t->access = val;
-
-        if (!of_property_read_u32(np, "gpmc,rd-cycle", &val))
-                gpmc_t->rd_cycle = val;
-
-        if (!of_property_read_u32(np, "gpmc,wr-cycle", &val))
-                gpmc_t->wr_cycle = val;
-
-        /* only for OMAP3430 */
-        if (!of_property_read_u32(np, "gpmc,wr-access", &val))
-                gpmc_t->wr_access = val;
-
-        if (!of_property_read_u32(np, "gpmc,wr-data-mux-bus", &val))
-                gpmc_t->wr_data_mux_bus = val;
+        of_property_read_u32(np, "gpmc,page-burst-access-ns",
+                             &gpmc_t->page_burst_access);
+        of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
+        of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
+        of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
+        of_property_read_u32(np, "gpmc,bus-turnaround-ns",
+                             &gpmc_t->bus_turnaround);
+        of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns",
+                             &gpmc_t->cycle2cycle_delay);
+        of_property_read_u32(np, "gpmc,wait-monitoring-ns",
+                             &gpmc_t->wait_monitoring);
+        of_property_read_u32(np, "gpmc,clk-activation-ns",
+                             &gpmc_t->clk_activation);
+
+        /* only applicable to OMAP3+ */
+        of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
+        of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns",
+                             &gpmc_t->wr_data_mux_bus);
+
+        /* bool timing parameters */
+        p = &gpmc_t->bool_timings;
+
+        p->cycle2cyclediffcsen =
+                of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen");
+        p->cycle2cyclesamecsen =
+                of_property_read_bool(np, "gpmc,cycle2cycle-samecsen");
+        p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay");
+        p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay");
+        p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay");
+        p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay");
+        p->time_para_granularity =
+                of_property_read_bool(np, "gpmc,time-para-granularity");
 }
 
 #ifdef CONFIG_MTD_NAND
@@ -1295,6 +1428,81 @@ static int gpmc_probe_onenand_child(struct platform_device *pdev,
 }
 #endif
 
+/**
+ * gpmc_probe_generic_child - configures the gpmc for a child device
+ * @pdev:       pointer to gpmc platform device
+ * @child:      pointer to device-tree node for child device
+ *
+ * Allocates and configures a GPMC chip-select for a child device.
+ * Returns 0 on success and appropriate negative error code on failure.
+ */
+static int gpmc_probe_generic_child(struct platform_device *pdev,
+                                struct device_node *child)
+{
+        struct gpmc_settings gpmc_s;
+        struct gpmc_timings gpmc_t;
+        struct resource res;
+        unsigned long base;
+        int ret, cs;
+
+        if (of_property_read_u32(child, "reg", &cs) < 0) {
+                dev_err(&pdev->dev, "%s has no 'reg' property\n",
+                        child->full_name);
+                return -ENODEV;
+        }
+
+        if (of_address_to_resource(child, 0, &res) < 0) {
+                dev_err(&pdev->dev, "%s has malformed 'reg' property\n",
+                        child->full_name);
+                return -ENODEV;
+        }
+
+        ret = gpmc_cs_request(cs, resource_size(&res), &base);
+        if (ret < 0) {
+                dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
+                return ret;
+        }
+
+        /*
+         * FIXME: gpmc_cs_request() will map the CS to an arbitary
+         * location in the gpmc address space. When booting with
+         * device-tree we want the NOR flash to be mapped to the
+         * location specified in the device-tree blob. So remap the
+         * CS to this location. Once DT migration is complete should
+         * just make gpmc_cs_request() map a specific address.
+         */
+        ret = gpmc_cs_remap(cs, res.start);
+        if (ret < 0) {
+                dev_err(&pdev->dev, "cannot remap GPMC CS %d to 0x%x\n",
+                        cs, res.start);
+                goto err;
+        }
+
+        gpmc_read_settings_dt(child, &gpmc_s);
+
+        ret = of_property_read_u32(child, "bank-width", &gpmc_s.device_width);
+        if (ret < 0)
+                goto err;
+
+        ret = gpmc_cs_program_settings(cs, &gpmc_s);
+        if (ret < 0)
+                goto err;
+
+        gpmc_read_timings_dt(child, &gpmc_t);
+        gpmc_cs_set_timings(cs, &gpmc_t);
+
+        if (of_platform_device_create(child, NULL, &pdev->dev))
+                return 0;
+
+        dev_err(&pdev->dev, "failed to create gpmc child %s\n", child->name);
+        ret = -ENODEV;
+
+err:
+        gpmc_cs_free(cs);
+
+        return ret;
+}
+
 static int gpmc_probe_dt(struct platform_device *pdev)
 {
         int ret;
@@ -1305,6 +1513,13 @@ static int gpmc_probe_dt(struct platform_device *pdev)
         if (!of_id)
                 return 0;
 
+        ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
+                                   &gpmc_nr_waitpins);
+        if (ret < 0) {
+                pr_err("%s: number of wait pins not found!\n", __func__);
+                return ret;
+        }
+
         for_each_node_by_name(child, "nand") {
                 ret = gpmc_probe_nand_child(pdev, child);
                 if (ret < 0) {
@@ -1320,6 +1535,23 @@ static int gpmc_probe_dt(struct platform_device *pdev)
                         return ret;
                 }
         }
+
+        for_each_node_by_name(child, "nor") {
+                ret = gpmc_probe_generic_child(pdev, child);
+                if (ret < 0) {
+                        of_node_put(child);
+                        return ret;
+                }
+        }
+
+        for_each_node_by_name(child, "ethernet") {
+                ret = gpmc_probe_generic_child(pdev, child);
+                if (ret < 0) {
+                        of_node_put(child);
+                        return ret;
+                }
+        }
+
         return 0;
 }
 #else
@@ -1364,18 +1596,27 @@ static int gpmc_probe(struct platform_device *pdev)
         gpmc_dev = &pdev->dev;
 
         l = gpmc_read_reg(GPMC_REVISION);
+
+        /*
+         * FIXME: Once device-tree migration is complete the below flags
+         * should be populated based upon the device-tree compatible
+         * string. For now just use the IP revision. OMAP3+ devices have
+         * the wr_access and wr_data_mux_bus register fields. OMAP4+
+         * devices support the addr-addr-data multiplex protocol.
+         *
+         * GPMC IP revisions:
+         * - OMAP24xx                   = 2.0
+         * - OMAP3xxx                   = 5.0
+         * - OMAP44xx/54xx/AM335x       = 6.0
+         */
         if (GPMC_REVISION_MAJOR(l) > 0x4)
                 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
+        if (GPMC_REVISION_MAJOR(l) > 0x5)
+                gpmc_capability |= GPMC_HAS_MUX_AAD;
         dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
                  GPMC_REVISION_MINOR(l));
 
-        rc = gpmc_mem_init();
-        if (rc < 0) {
-                clk_disable_unprepare(gpmc_l3_clk);
-                clk_put(gpmc_l3_clk);
-                dev_err(gpmc_dev, "failed to reserve memory\n");
-                return rc;
-        }
+        gpmc_mem_init();
 
         if (gpmc_setup_irq() < 0)
                 dev_warn(gpmc_dev, "gpmc_setup_irq failed\n");
@@ -1383,6 +1624,9 @@ static int gpmc_probe(struct platform_device *pdev)
         /* Now the GPMC is initialised, unreserve the chip-selects */
         gpmc_cs_map = 0;
 
+        if (!pdev->dev.of_node)
+                gpmc_nr_waitpins = GPMC_NR_WAITPINS;
+
         rc = gpmc_probe_dt(pdev);
         if (rc < 0) {
                 clk_disable_unprepare(gpmc_l3_clk);
diff --git a/arch/arm/mach-omap2/gpmc.h b/arch/arm/mach-omap2/gpmc.h
index fe0a844d5007..707f6d58edd5 100644
--- a/arch/arm/mach-omap2/gpmc.h
+++ b/arch/arm/mach-omap2/gpmc.h
@@ -58,7 +58,7 @@
 #define GPMC_CONFIG1_DEVICESIZE_16      GPMC_CONFIG1_DEVICESIZE(1)
 #define GPMC_CONFIG1_DEVICETYPE(val)    ((val & 3) << 10)
 #define GPMC_CONFIG1_DEVICETYPE_NOR     GPMC_CONFIG1_DEVICETYPE(0)
-#define GPMC_CONFIG1_MUXADDDATA         (1 << 9)
+#define GPMC_CONFIG1_MUXTYPE(val)       ((val & 3) << 8)
 #define GPMC_CONFIG1_TIME_PARA_GRAN     (1 << 4)
 #define GPMC_CONFIG1_FCLK_DIV(val)      (val & 3)
 #define GPMC_CONFIG1_FCLK_DIV2          (GPMC_CONFIG1_FCLK_DIV(1))
@@ -73,6 +73,13 @@
 #define GPMC_IRQ_FIFOEVENTENABLE        0x01
 #define GPMC_IRQ_COUNT_EVENT            0x02
 
+#define GPMC_BURST_4                    4       /* 4 word burst */
+#define GPMC_BURST_8                    8       /* 8 word burst */
+#define GPMC_BURST_16                   16      /* 16 word burst */
+#define GPMC_DEVWIDTH_8BIT              1       /* 8-bit device width */
+#define GPMC_DEVWIDTH_16BIT             2       /* 16-bit device width */
+#define GPMC_MUX_AAD                    1       /* Addr-Addr-Data multiplex */
+#define GPMC_MUX_AD                     2       /* Addr-Data multiplex */
 
 /* bool type time settings */
 struct gpmc_bool_timings {
@@ -178,10 +185,6 @@ struct gpmc_device_timings {
         u8 cyc_wpl;     /* write deassertion time in cycles */
         u32 cyc_iaa;    /* initial access time in cycles */
 
-        bool mux;       /* address & data muxed */
-        bool sync_write;/* synchronous write */
-        bool sync_read; /* synchronous read */
-
         /* extra delays */
         bool ce_xdelay;
         bool avd_xdelay;
@@ -189,28 +192,40 @@ struct gpmc_device_timings {
         bool we_xdelay;
 };
 
+struct gpmc_settings {
+        bool burst_wrap;        /* enables wrap bursting */
+        bool burst_read;        /* enables read page/burst mode */
+        bool burst_write;       /* enables write page/burst mode */
+        bool device_nand;       /* device is NAND */
+        bool sync_read;         /* enables synchronous reads */
+        bool sync_write;        /* enables synchronous writes */
+        bool wait_on_read;      /* monitor wait on reads */
+        bool wait_on_write;     /* monitor wait on writes */
+        u32 burst_len;          /* page/burst length */
+        u32 device_width;       /* device bus width (8 or 16 bit) */
+        u32 mux_add_data;       /* multiplex address & data */
+        u32 wait_pin;           /* wait-pin to be used */
+};
+
 extern int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
-                                struct gpmc_device_timings *dev_t);
+                             struct gpmc_settings *gpmc_s,
+                             struct gpmc_device_timings *dev_t);
 
 extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs);
 extern int gpmc_get_client_irq(unsigned irq_config);
 
-extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
-extern unsigned int gpmc_ps_to_ticks(unsigned int time_ps);
 extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
-extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns);
-extern unsigned long gpmc_get_fclk_period(void);
 
 extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
-extern u32 gpmc_cs_read_reg(int cs, int idx);
 extern int gpmc_calc_divider(unsigned int sync_clk);
 extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
+extern int gpmc_cs_program_settings(int cs, struct gpmc_settings *p);
 extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
 extern void gpmc_cs_free(int cs);
-extern int gpmc_cs_set_reserved(int cs, int reserved);
-extern int gpmc_cs_reserved(int cs);
 extern void omap3_gpmc_save_context(void);
 extern void omap3_gpmc_restore_context(void);
-extern int gpmc_cs_configure(int cs, int cmd, int wval);
+extern int gpmc_configure(int cmd, int wval);
+extern void gpmc_read_settings_dt(struct device_node *np,
+                                  struct gpmc_settings *p);
 
 #endif
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 2bef5a7e6af8..e210fa830f8d 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -55,6 +55,12 @@
 #include "prm44xx.h"
 
 /*
+ * omap_clk_init: points to a function that does the SoC-specific
+ * clock initializations
+ */
+int (*omap_clk_init)(void);
+
+/*
  * The machine specific code may provide the extra mapping besides the
  * default mapping provided here.
  */
@@ -406,7 +412,7 @@ void __init omap2420_init_early(void)
         omap242x_clockdomains_init();
         omap2420_hwmod_init();
         omap_hwmod_init_postsetup();
-        omap2420_clk_init();
+        omap_clk_init = omap2420_clk_init;
 }
 
 void __init omap2420_init_late(void)
@@ -436,7 +442,7 @@ void __init omap2430_init_early(void)
         omap243x_clockdomains_init();
         omap2430_hwmod_init();
         omap_hwmod_init_postsetup();
-        omap2430_clk_init();
+        omap_clk_init = omap2430_clk_init;
 }
 
 void __init omap2430_init_late(void)
@@ -471,7 +477,7 @@ void __init omap3_init_early(void)
         omap3xxx_clockdomains_init();
         omap3xxx_hwmod_init();
         omap_hwmod_init_postsetup();
-        omap3xxx_clk_init();
+        omap_clk_init = omap3xxx_clk_init;
 }
 
 void __init omap3430_init_early(void)
@@ -509,7 +515,7 @@ void __init ti81xx_init_early(void)
         omap3xxx_clockdomains_init();
         omap3xxx_hwmod_init();
         omap_hwmod_init_postsetup();
-        omap3xxx_clk_init();
+        omap_clk_init = omap3xxx_clk_init;
 }
 
 void __init omap3_init_late(void)
@@ -577,7 +583,7 @@ void __init am33xx_init_early(void)
         am33xx_clockdomains_init();
         am33xx_hwmod_init();
         omap_hwmod_init_postsetup();
-        am33xx_clk_init();
+        omap_clk_init = am33xx_clk_init;
 }
 #endif
 
@@ -602,7 +608,7 @@ void __init omap4430_init_early(void)
         omap44xx_clockdomains_init();
         omap44xx_hwmod_init();
         omap_hwmod_init_postsetup();
-        omap4xxx_clk_init();
+        omap_clk_init = omap4xxx_clk_init;
 }
 
 void __init omap4430_init_late(void)
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 2520d46c8508..3f50f680372e 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1364,7 +1364,9 @@ static void _enable_sysc(struct omap_hwmod *oh)
         }
 
         if (sf & SYSC_HAS_MIDLEMODE) {
-                if (oh->flags & HWMOD_SWSUP_MSTANDBY) {
+                if (oh->flags & HWMOD_FORCE_MSTANDBY) {
+                        idlemode = HWMOD_IDLEMODE_FORCE;
+                } else if (oh->flags & HWMOD_SWSUP_MSTANDBY) {
                         idlemode = HWMOD_IDLEMODE_NO;
                 } else {
                         if (sf & SYSC_HAS_ENAWAKEUP)
@@ -1436,7 +1438,8 @@ static void _idle_sysc(struct omap_hwmod *oh)
         }
 
         if (sf & SYSC_HAS_MIDLEMODE) {
-                if (oh->flags & HWMOD_SWSUP_MSTANDBY) {
+                if ((oh->flags & HWMOD_SWSUP_MSTANDBY) ||
+                    (oh->flags & HWMOD_FORCE_MSTANDBY)) {
                         idlemode = HWMOD_IDLEMODE_FORCE;
                 } else {
                         if (sf & SYSC_HAS_ENAWAKEUP)
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index 28f4dea0512e..fe5962921f07 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -427,8 +427,8 @@ struct omap_hwmod_omap4_prcm {
  *
  * HWMOD_SWSUP_SIDLE: omap_hwmod code should manually bring module in and out
  *     of idle, rather than relying on module smart-idle
- * HWMOD_SWSUP_MSTDBY: omap_hwmod code should manually bring module in and out
- *     of standby, rather than relying on module smart-standby
+ * HWMOD_SWSUP_MSTANDBY: omap_hwmod code should manually bring module in and
+ *     out of standby, rather than relying on module smart-standby
  * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for
  *     SDRAM controller, etc. XXX probably belongs outside the main hwmod file
  *     XXX Should be HWMOD_SETUP_NO_RESET
@@ -459,6 +459,10 @@ struct omap_hwmod_omap4_prcm {
  *     correctly, or this is being abused to deal with some PM latency
  *     issues -- but we're currently suffering from a shortage of
  *     folks who are able to track these issues down properly.
+ * HWMOD_FORCE_MSTANDBY: Always keep MIDLEMODE bits cleared so that device
+ *     is kept in force-standby mode. Failing to do so causes PM problems
+ *     with musb on OMAP3630 at least. Note that musb has a dedicated register
+ *     to control MSTANDBY signal when MIDLEMODE is set to force-standby.
  */
 #define HWMOD_SWSUP_SIDLE                       (1 << 0)
 #define HWMOD_SWSUP_MSTANDBY                    (1 << 1)
@@ -471,6 +475,7 @@ struct omap_hwmod_omap4_prcm {
 #define HWMOD_16BIT_REG                         (1 << 8)
 #define HWMOD_EXT_OPT_MAIN_CLK                  (1 << 9)
 #define HWMOD_BLOCK_WFI                         (1 << 10)
+#define HWMOD_FORCE_MSTANDBY                    (1 << 11)
 
 /*
  * omap_hwmod._int_flags definitions
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index ac7e03ec952f..5112d04e7b79 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -1707,9 +1707,14 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
          * broken when autoidle is enabled
          * workaround is to disable the autoidle bit at module level.
+         *
+         * Enabling the device in any other MIDLEMODE setting but force-idle
+         * causes core_pwrdm not enter idle states at least on OMAP3630.
+         * Note that musb has OTG_FORCESTDBY register that controls MSTANDBY
+         * signal when MIDLEMODE is set to force-idle.
          */
         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
-                                | HWMOD_SWSUP_MSTANDBY,
+                                | HWMOD_FORCE_MSTANDBY,
 };
 
 /* usb_otg_hs */
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 0e47d2e1687c..9e0576569e07 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -2714,6 +2714,10 @@ static struct omap_ocp2scp_dev ocp2scp_dev_attr[] = {
         { }
 };
 
+static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks[] = {
+        { .role = "48mhz", .clk = "ocp2scp_usb_phy_phy_48m" },
+};
+
 /* ocp2scp_usb_phy */
 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
         .name           = "ocp2scp_usb_phy",
@@ -2728,6 +2732,8 @@ static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
                 },
         },
         .dev_attr       = ocp2scp_dev_attr,
+        .opt_clks       = ocp2scp_usb_phy_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(ocp2scp_usb_phy_opt_clks),
 };
 
 /*
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 31ae76481737..fdf1c039062c 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -46,7 +46,6 @@
 #include <asm/smp_twd.h>
 #include <asm/sched_clock.h>
 
-#include <asm/arch_timer.h>
 #include "omap_hwmod.h"
 #include "omap_device.h"
 #include <plat/counter-32k.h>
@@ -626,14 +625,10 @@ void __init omap4_local_timer_init(void)
 #ifdef CONFIG_SOC_OMAP5
 void __init omap5_realtime_timer_init(void)
 {
-        int err;
-
         omap4_sync32k_timer_init();
         realtime_counter_init();
 
-        err = arch_timer_of_register();
-        if (err)
-                pr_err("%s: arch_timer_register failed %d\n", __func__, err);
+        clocksource_of_init();
 }
 #endif /* CONFIG_SOC_OMAP5 */
 
diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c
index c5a3c6f9504e..e832bc7b8e2d 100644
--- a/arch/arm/mach-omap2/usb-tusb6010.c
+++ b/arch/arm/mach-omap2/usb-tusb6010.c
@@ -8,6 +8,7 @@
  * published by the Free Software Foundation.
  */
 
+#include <linux/err.h>
 #include <linux/string.h>
 #include <linux/types.h>
 #include <linux/errno.h>
@@ -26,6 +27,24 @@
 static u8               async_cs, sync_cs;
 static unsigned         refclk_psec;
 
+static struct gpmc_settings tusb_async = {
+        .wait_on_read   = true,
+        .wait_on_write  = true,
+        .device_width   = GPMC_DEVWIDTH_16BIT,
+        .mux_add_data   = GPMC_MUX_AD,
+};
+
+static struct gpmc_settings tusb_sync = {
+        .burst_read     = true,
+        .burst_write    = true,
+        .sync_read      = true,
+        .sync_write     = true,
+        .wait_on_read   = true,
+        .wait_on_write  = true,
+        .burst_len      = GPMC_BURST_16,
+        .device_width   = GPMC_DEVWIDTH_16BIT,
+        .mux_add_data   = GPMC_MUX_AD,
+};
 
 /* NOTE:  timings are from tusb 6010 datasheet Rev 1.8, 12-Sept 2006 */
 
@@ -37,8 +56,6 @@ static int tusb_set_async_mode(unsigned sysclk_ps)
 
         memset(&dev_t, 0, sizeof(dev_t));
 
-        dev_t.mux = true;
-
         dev_t.t_ceasu = 8 * 1000;
         dev_t.t_avdasu = t_acsnh_advnh - 7000;
         dev_t.t_ce_avd = 1000;
@@ -52,7 +69,7 @@ static int tusb_set_async_mode(unsigned sysclk_ps)
         dev_t.t_wpl = 300;
         dev_t.cyc_aavdh_we = 1;
 
-        gpmc_calc_timings(&t, &dev_t);
+        gpmc_calc_timings(&t, &tusb_async, &dev_t);
 
         return gpmc_cs_set_timings(async_cs, &t);
 }
@@ -65,10 +82,6 @@ static int tusb_set_sync_mode(unsigned sysclk_ps)
 
         memset(&dev_t, 0, sizeof(dev_t));
 
-        dev_t.mux = true;
-        dev_t.sync_read = true;
-        dev_t.sync_write = true;
-
         dev_t.clk = 11100;
         dev_t.t_bacc = 1000;
         dev_t.t_ces = 1000;
@@ -84,7 +97,7 @@ static int tusb_set_sync_mode(unsigned sysclk_ps)
         dev_t.cyc_wpl = 6;
         dev_t.t_ce_rdyz = 7000;
 
-        gpmc_calc_timings(&t, &dev_t);
+        gpmc_calc_timings(&t, &tusb_sync, &dev_t);
 
         return gpmc_cs_set_timings(sync_cs, &t);
 }
@@ -165,18 +178,12 @@ tusb6010_setup_interface(struct musb_hdrc_platform_data *data,
                 return status;
         }
         tusb_resources[0].end = tusb_resources[0].start + 0x9ff;
+        tusb_async.wait_pin = waitpin;
         async_cs = async;
-        gpmc_cs_write_reg(async, GPMC_CS_CONFIG1,
-                          GPMC_CONFIG1_PAGE_LEN(2)
-                        | GPMC_CONFIG1_WAIT_READ_MON
-                        | GPMC_CONFIG1_WAIT_WRITE_MON
-                        | GPMC_CONFIG1_WAIT_PIN_SEL(waitpin)
-                        | GPMC_CONFIG1_READTYPE_ASYNC
-                        | GPMC_CONFIG1_WRITETYPE_ASYNC
-                        | GPMC_CONFIG1_DEVICESIZE_16
-                        | GPMC_CONFIG1_DEVICETYPE_NOR
-                        | GPMC_CONFIG1_MUXADDDATA);
 
+        status = gpmc_cs_program_settings(async_cs, &tusb_async);
+        if (status < 0)
+                return status;
 
         /* SYNC region, primarily for DMA */
         status = gpmc_cs_request(sync, SZ_16M, (unsigned long *)
@@ -186,21 +193,12 @@ tusb6010_setup_interface(struct musb_hdrc_platform_data *data,
                 return status;
         }
         tusb_resources[1].end = tusb_resources[1].start + 0x9ff;
+        tusb_sync.wait_pin = waitpin;
         sync_cs = sync;
-        gpmc_cs_write_reg(sync, GPMC_CS_CONFIG1,
-                          GPMC_CONFIG1_READMULTIPLE_SUPP
-                        | GPMC_CONFIG1_READTYPE_SYNC
-                        | GPMC_CONFIG1_WRITEMULTIPLE_SUPP
-                        | GPMC_CONFIG1_WRITETYPE_SYNC
-                        | GPMC_CONFIG1_PAGE_LEN(2)
-                        | GPMC_CONFIG1_WAIT_READ_MON
-                        | GPMC_CONFIG1_WAIT_WRITE_MON
-                        | GPMC_CONFIG1_WAIT_PIN_SEL(waitpin)
-                        | GPMC_CONFIG1_DEVICESIZE_16
-                        | GPMC_CONFIG1_DEVICETYPE_NOR
-                        | GPMC_CONFIG1_MUXADDDATA
-                        /* fclk divider gets set later */
-                        );
+
+        status = gpmc_cs_program_settings(sync_cs, &tusb_sync);
+        if (status < 0)
+                return status;
 
         /* IRQ */
         status = gpio_request_one(irq, GPIOF_IN, "TUSB6010 irq");
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile
index be6e4d0e6f1a..6f46ecfc8396 100644
--- a/arch/arm/mach-s3c24xx/Makefile
+++ b/arch/arm/mach-s3c24xx/Makefile
@@ -14,7 +14,7 @@ obj-				:=
 
 # core
 
-obj-y                           += common.o irq.o
+obj-y                           += common.o
 
 obj-$(CONFIG_CPU_S3C2410)       += s3c2410.o
 obj-$(CONFIG_S3C2410_CPUFREQ)   += cpufreq-s3c2410.o
diff --git a/arch/arm/mach-s3c24xx/common.h b/arch/arm/mach-s3c24xx/common.h
index abefeb38bba4..307c3714be55 100644
--- a/arch/arm/mach-s3c24xx/common.h
+++ b/arch/arm/mach-s3c24xx/common.h
@@ -21,6 +21,7 @@ extern void s3c2410_map_io(void);
 extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void s3c2410_init_clocks(int xtal);
 extern void s3c2410_restart(char mode, const char *cmd);
+extern void s3c2410_init_irq(void);
 #else
 #define s3c2410_init_clocks NULL
 #define s3c2410_init_uarts NULL
diff --git a/arch/arm/mach-s3c24xx/include/mach/entry-macro.S b/arch/arm/mach-s3c24xx/include/mach/entry-macro.S
deleted file mode 100644
index 6a21beeba1da..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/entry-macro.S
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * arch/arm/mach-s3c2410/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for S3C2410-based platforms
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
-*/
-
-/* We have a problem that the INTOFFSET register does not always
- * show one interrupt. Occasionally we get two interrupts through
- * the prioritiser, and this causes the INTOFFSET register to show
- * what looks like the logical-or of the two interrupt numbers.
- *
- * Thanks to Klaus, Shannon, et al for helping to debug this problem
-*/
-
-#define INTPND          (0x10)
-#define INTOFFSET       (0x14)
-
-#include <mach/hardware.h>
-#include <asm/irq.h>
-
-        .macro  get_irqnr_preamble, base, tmp
-        .endm
-
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-
-                mov     \base, #S3C24XX_VA_IRQ
-
-                @@ try the interrupt offset register, since it is there
-
-                ldr     \irqstat, [\base, #INTPND ]
-                teq     \irqstat, #0
-                beq     1002f
-                ldr     \irqnr, [\base, #INTOFFSET ]
-                mov     \tmp, #1
-                tst     \irqstat, \tmp, lsl \irqnr
-                bne     1001f
-
-                @@ the number specified is not a valid irq, so try
-                @@ and work it out for ourselves
-
-                mov     \irqnr, #0              @@ start here
-
-                @@ work out which irq (if any) we got
-
-                movs    \tmp, \irqstat, lsl#16
-                addeq   \irqnr, \irqnr, #16
-                moveq   \irqstat, \irqstat, lsr#16
-                tst     \irqstat, #0xff
-                addeq   \irqnr, \irqnr, #8
-                moveq   \irqstat, \irqstat, lsr#8
-                tst     \irqstat, #0xf
-                addeq   \irqnr, \irqnr, #4
-                moveq   \irqstat, \irqstat, lsr#4
-                tst     \irqstat, #0x3
-                addeq   \irqnr, \irqnr, #2
-                moveq   \irqstat, \irqstat, lsr#2
-                tst     \irqstat, #0x1
-                addeq   \irqnr, \irqnr, #1
-
-                @@ we have the value
-1001:
-                adds    \irqnr, \irqnr, #IRQ_EINT0
-1002:
-                @@ exit here, Z flag unset if IRQ
-
-        .endm
diff --git a/arch/arm/mach-s3c24xx/mach-amlm5900.c b/arch/arm/mach-s3c24xx/mach-amlm5900.c
index 432144cb54ae..e27b5c91b3db 100644
--- a/arch/arm/mach-s3c24xx/mach-amlm5900.c
+++ b/arch/arm/mach-s3c24xx/mach-amlm5900.c
@@ -238,7 +238,7 @@ static void __init amlm5900_init(void)
 MACHINE_START(AML_M5900, "AML_M5900")
         .atag_offset    = 0x100,
         .map_io         = amlm5900_map_io,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2410_init_irq,
         .init_machine   = amlm5900_init,
         .init_time      = samsung_timer_init,
         .restart        = s3c2410_restart,
diff --git a/arch/arm/mach-s3c24xx/mach-bast.c b/arch/arm/mach-s3c24xx/mach-bast.c
index eabe2db42ef6..22d6ae926d91 100644
--- a/arch/arm/mach-s3c24xx/mach-bast.c
+++ b/arch/arm/mach-s3c24xx/mach-bast.c
@@ -605,7 +605,7 @@ MACHINE_START(BAST, "Simtec-BAST")
         /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
         .atag_offset    = 0x100,
         .map_io         = bast_map_io,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2410_init_irq,
         .init_machine   = bast_init,
         .init_time      = samsung_timer_init,
         .restart        = s3c2410_restart,
diff --git a/arch/arm/mach-s3c24xx/mach-h1940.c b/arch/arm/mach-s3c24xx/mach-h1940.c
index 8dd660102846..af4334d6b4d5 100644
--- a/arch/arm/mach-s3c24xx/mach-h1940.c
+++ b/arch/arm/mach-s3c24xx/mach-h1940.c
@@ -667,11 +667,6 @@ static void __init h1940_reserve(void)
         memblock_reserve(0x30081000, 0x1000);
 }
 
-static void __init h1940_init_irq(void)
-{
-        s3c24xx_init_irq();
-}
-
 static void __init h1940_init(void)
 {
         u32 tmp;
@@ -740,7 +735,7 @@ MACHINE_START(H1940, "IPAQ-H1940")
         .atag_offset    = 0x100,
         .map_io         = h1940_map_io,
         .reserve        = h1940_reserve,
-        .init_irq       = h1940_init_irq,
+        .init_irq       = s3c2410_init_irq,
         .init_machine   = h1940_init,
         .init_time      = samsung_timer_init,
         .restart        = s3c2410_restart,
diff --git a/arch/arm/mach-s3c24xx/mach-n30.c b/arch/arm/mach-s3c24xx/mach-n30.c
index 73a690f431e6..2cb46c37c920 100644
--- a/arch/arm/mach-s3c24xx/mach-n30.c
+++ b/arch/arm/mach-s3c24xx/mach-n30.c
@@ -592,7 +592,7 @@ MACHINE_START(N30, "Acer-N30")
         .atag_offset    = 0x100,
         .init_time      = samsung_timer_init,
         .init_machine   = n30_init,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2410_init_irq,
         .map_io         = n30_map_io,
         .restart        = s3c2410_restart,
 MACHINE_END
@@ -603,7 +603,7 @@ MACHINE_START(N35, "Acer-N35")
         .atag_offset    = 0x100,
         .init_time      = samsung_timer_init,
         .init_machine   = n30_init,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2410_init_irq,
         .map_io         = n30_map_io,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-otom.c b/arch/arm/mach-s3c24xx/mach-otom.c
index 7b8670746b6a..7e16b0740ec1 100644
--- a/arch/arm/mach-s3c24xx/mach-otom.c
+++ b/arch/arm/mach-s3c24xx/mach-otom.c
@@ -116,7 +116,7 @@ MACHINE_START(OTOM, "Nex Vision - Otom 1.1")
         .atag_offset    = 0x100,
         .map_io         = otom11_map_io,
         .init_machine   = otom11_init,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2410_init_irq,
         .init_time      = samsung_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-qt2410.c b/arch/arm/mach-s3c24xx/mach-qt2410.c
index 71cf29b12d1f..f8feaeadb55a 100644
--- a/arch/arm/mach-s3c24xx/mach-qt2410.c
+++ b/arch/arm/mach-s3c24xx/mach-qt2410.c
@@ -343,7 +343,7 @@ static void __init qt2410_machine_init(void)
 MACHINE_START(QT2410, "QT2410")
         .atag_offset    = 0x100,
         .map_io         = qt2410_map_io,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2410_init_irq,
         .init_machine   = qt2410_machine_init,
         .init_time      = samsung_timer_init,
         .restart        = s3c2410_restart,
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2410.c b/arch/arm/mach-s3c24xx/mach-smdk2410.c
index fd96f7fc330c..a773789e4f38 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2410.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2410.c
@@ -116,7 +116,7 @@ MACHINE_START(SMDK2410, "SMDK2410") /* @TODO: request a new identifier and switc
         /* Maintainer: Jonas Dietsche */
         .atag_offset    = 0x100,
         .map_io         = smdk2410_map_io,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2410_init_irq,
         .init_machine   = smdk2410_init,
         .init_time      = samsung_timer_init,
         .restart        = s3c2410_restart,
diff --git a/arch/arm/mach-s3c24xx/mach-tct_hammer.c b/arch/arm/mach-s3c24xx/mach-tct_hammer.c
index 31dfe589e349..7fad8f055cab 100644
--- a/arch/arm/mach-s3c24xx/mach-tct_hammer.c
+++ b/arch/arm/mach-s3c24xx/mach-tct_hammer.c
@@ -149,7 +149,7 @@ static void __init tct_hammer_init(void)
 MACHINE_START(TCT_HAMMER, "TCT_HAMMER")
         .atag_offset    = 0x100,
         .map_io         = tct_hammer_map_io,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2410_init_irq,
         .init_machine   = tct_hammer_init,
         .init_time      = samsung_timer_init,
         .restart        = s3c2410_restart,
diff --git a/arch/arm/mach-s3c24xx/mach-vr1000.c b/arch/arm/mach-s3c24xx/mach-vr1000.c
index deeb8a0a4034..42e7187fed60 100644
--- a/arch/arm/mach-s3c24xx/mach-vr1000.c
+++ b/arch/arm/mach-s3c24xx/mach-vr1000.c
@@ -355,7 +355,7 @@ MACHINE_START(VR1000, "Thorcom-VR1000")
         .atag_offset    = 0x100,
         .map_io         = vr1000_map_io,
         .init_machine   = vr1000_init,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2410_init_irq,
         .init_time      = samsung_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-kzm9d.c b/arch/arm/mach-shmobile/board-kzm9d.c
index c254782aa727..c016ccd92433 100644
--- a/arch/arm/mach-shmobile/board-kzm9d.c
+++ b/arch/arm/mach-shmobile/board-kzm9d.c
@@ -90,6 +90,5 @@ DT_MACHINE_START(KZM9D_DT, "kzm9d")
         .init_irq       = emev2_init_irq,
         .init_machine   = kzm9d_add_standard_devices,
         .init_late      = shmobile_init_late,
-        .init_time      = shmobile_timer_init,
         .dt_compat      = kzm9d_boards_compat_dt,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c
index e4545c152722..899a86c31ec9 100644
--- a/arch/arm/mach-shmobile/setup-emev2.c
+++ b/arch/arm/mach-shmobile/setup-emev2.c
@@ -456,7 +456,6 @@ DT_MACHINE_START(EMEV2_DT, "Generic Emma Mobile EV2 (Flattened Device Tree)")
         .nr_irqs        = NR_IRQS_LEGACY,
         .init_irq       = irqchip_init,
         .init_machine   = emev2_add_standard_devices_dt,
-        .init_time      = shmobile_timer_init,
         .dt_compat      = emev2_boards_compat_dt,
 MACHINE_END
 
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 8b85d4d8fab6..104b474a2ccf 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -906,7 +906,6 @@ DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
         .init_irq       = r8a7740_init_irq,
         .handle_irq     = shmobile_handle_irq_intc,
         .init_machine   = r8a7740_add_standard_devices_dt,
-        .init_time      = shmobile_timer_init,
         .dt_compat      = r8a7740_boards_compat_dt,
 MACHINE_END
 
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index 59c7146bf66f..5502d624aca6 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -1175,7 +1175,6 @@ DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)")
         .init_irq       = sh7372_init_irq,
         .handle_irq     = shmobile_handle_irq_intc,
         .init_machine   = sh7372_add_standard_devices_dt,
-        .init_time      = shmobile_timer_init,
         .dt_compat      = sh7372_boards_compat_dt,
 MACHINE_END
 
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index e8cd93a5c550..fdf3894b1cc3 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -1037,7 +1037,6 @@ DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
         .nr_irqs        = NR_IRQS_LEGACY,
         .init_irq       = irqchip_init,
         .init_machine   = sh73a0_add_standard_devices_dt,
-        .init_time      = shmobile_timer_init,
         .dt_compat      = sh73a0_boards_compat_dt,
 MACHINE_END
 #endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/timer.c b/arch/arm/mach-shmobile/timer.c
index 3d16d4dff01b..f321dbeb2379 100644
--- a/arch/arm/mach-shmobile/timer.c
+++ b/arch/arm/mach-shmobile/timer.c
@@ -19,10 +19,8 @@
  *
  */
 #include <linux/platform_device.h>
+#include <linux/clocksource.h>
 #include <linux/delay.h>
-#include <asm/arch_timer.h>
-#include <asm/mach/time.h>
-#include <asm/smp_twd.h>
 
 void __init shmobile_setup_delay(unsigned int max_cpu_core_mhz,
                                  unsigned int mult, unsigned int div)
@@ -63,6 +61,5 @@ void __init shmobile_earlytimer_init(void)
 
 void __init shmobile_timer_init(void)
 {
-        arch_timer_of_register();
-        arch_timer_sched_clock_init();
+        clocksource_of_init();
 }
diff --git a/arch/arm/mach-spear/Kconfig b/arch/arm/mach-spear/Kconfig
new file mode 100644
index 000000000000..5412aeb377ac
--- /dev/null
+++ b/arch/arm/mach-spear/Kconfig
@@ -0,0 +1,103 @@
+#
+# SPEAr Platform configuration file
+#
+
+menuconfig PLAT_SPEAR
+        bool "ST SPEAr Family" if ARCH_MULTI_V7 || ARCH_MULTI_V5
+        default PLAT_SPEAR_SINGLE
+        select ARCH_REQUIRE_GPIOLIB
+        select ARM_AMBA
+        select CLKDEV_LOOKUP
+        select CLKSRC_MMIO
+        select COMMON_CLK
+        select GENERIC_CLOCKEVENTS
+        select HAVE_CLK
+
+if PLAT_SPEAR
+
+config ARCH_SPEAR13XX
+        bool "ST SPEAr13xx"
+        depends on ARCH_MULTI_V7 || PLAT_SPEAR_SINGLE
+        select ARCH_HAS_CPUFREQ
+        select ARM_GIC
+        select CPU_V7
+        select GPIO_SPEAR_SPICS
+        select HAVE_SMP
+        select MIGHT_HAVE_CACHE_L2X0
+        select PINCTRL
+        select USE_OF
+        help
+          Supports for ARM's SPEAR13XX family
+
+if ARCH_SPEAR13XX
+
+config MACH_SPEAR1310
+        bool "SPEAr1310 Machine support with Device Tree"
+        select PINCTRL_SPEAR1310
+        help
+          Supports ST SPEAr1310 machine configured via the device-tree
+
+config MACH_SPEAR1340
+        bool "SPEAr1340 Machine support with Device Tree"
+        select PINCTRL_SPEAR1340
+        help
+          Supports ST SPEAr1340 machine configured via the device-tree
+
+endif #ARCH_SPEAR13XX
+
+config ARCH_SPEAR3XX
+        bool "ST SPEAr3xx"
+        depends on ARCH_MULTI_V5 || PLAT_SPEAR_SINGLE
+        depends on !ARCH_SPEAR13XX
+        select ARM_VIC
+        select CPU_ARM926T
+        select PINCTRL
+        select USE_OF
+        help
+          Supports for ARM's SPEAR3XX family
+
+if ARCH_SPEAR3XX
+
+config MACH_SPEAR300
+        bool "SPEAr300 Machine support with Device Tree"
+        select PINCTRL_SPEAR300
+        help
+          Supports ST SPEAr300 machine configured via the device-tree
+
+config MACH_SPEAR310
+        bool "SPEAr310 Machine support with Device Tree"
+        select PINCTRL_SPEAR310
+        help
+          Supports ST SPEAr310 machine configured via the device-tree
+
+config MACH_SPEAR320
+        bool "SPEAr320 Machine support with Device Tree"
+        select PINCTRL_SPEAR320
+        help
+          Supports ST SPEAr320 machine configured via the device-tree
+
+endif
+
+config ARCH_SPEAR6XX
+        bool "ST SPEAr6XX"
+        depends on ARCH_MULTI_V5 || PLAT_SPEAR_SINGLE
+        depends on !ARCH_SPEAR13XX
+        select ARM_VIC
+        select CPU_ARM926T
+        help
+          Supports for ARM's SPEAR6XX family
+
+config MACH_SPEAR600
+        def_bool y
+        depends on ARCH_SPEAR6XX
+        select USE_OF
+        help
+          Supports ST SPEAr600 boards configured via the device-treesource "arch/arm/mach-spear6xx/Kconfig"
+
+config ARCH_SPEAR_AUTO
+        def_bool PLAT_SPEAR_SINGLE
+        depends on !ARCH_SPEAR13XX && !ARCH_SPEAR6XX
+        select ARCH_SPEAR3XX
+
+endif
+
diff --git a/arch/arm/mach-spear/Makefile b/arch/arm/mach-spear/Makefile
new file mode 100644
index 000000000000..8aaf724e1ea4
--- /dev/null
+++ b/arch/arm/mach-spear/Makefile
@@ -0,0 +1,24 @@
+#
+# SPEAr Platform specific Makefile
+#
+
+ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
+
+# Common support
+obj-y   := restart.o time.o
+
+smp-$(CONFIG_SMP)               += headsmp.o platsmp.o
+smp-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
+
+obj-$(CONFIG_ARCH_SPEAR13XX)    += spear13xx.o $(smp-y)
+obj-$(CONFIG_MACH_SPEAR1310)    += spear1310.o
+obj-$(CONFIG_MACH_SPEAR1340)    += spear1340.o
+
+obj-$(CONFIG_ARCH_SPEAR3XX)     += spear3xx.o
+obj-$(CONFIG_ARCH_SPEAR3XX)     += pl080.o
+obj-$(CONFIG_MACH_SPEAR300)     += spear300.o
+obj-$(CONFIG_MACH_SPEAR310)     += spear310.o
+obj-$(CONFIG_MACH_SPEAR320)     += spear320.o
+
+obj-$(CONFIG_ARCH_SPEAR6XX)     += spear6xx.o
+obj-$(CONFIG_ARCH_SPEAR6XX)     += pl080.o
diff --git a/arch/arm/mach-spear13xx/Makefile.boot b/arch/arm/mach-spear/Makefile.boot
index 4674a4c221db..4674a4c221db 100644
--- a/arch/arm/mach-spear13xx/Makefile.boot
+++ b/arch/arm/mach-spear/Makefile.boot
diff --git a/arch/arm/mach-spear13xx/include/mach/generic.h b/arch/arm/mach-spear/generic.h
index 633e678e01a3..a9fd45362fee 100644
--- a/arch/arm/mach-spear13xx/include/mach/generic.h
+++ b/arch/arm/mach-spear/generic.h
@@ -1,9 +1,8 @@
 /*
- * arch/arm/mach-spear13xx/include/mach/generic.h
+ * spear machine family generic header file
  *
- * spear13xx machine family generic header file
- *
- * Copyright (C) 2012 ST Microelectronics
+ * Copyright (C) 2009-2012 ST Microelectronics
+ * Rajeev Kumar <rajeev-dlh.kumar@st.com>
  * Viresh Kumar <viresh.linux@gmail.com>
  *
  * This file is licensed under the terms of the GNU General Public
@@ -15,37 +14,41 @@
 #define __MACH_GENERIC_H
 
 #include <linux/dmaengine.h>
+#include <linux/amba/pl08x.h>
+#include <linux/init.h>
 #include <asm/mach/time.h>
 
-/* Add spear13xx structure declarations here */
 extern void spear13xx_timer_init(void);
+extern void spear3xx_timer_init(void);
 extern struct pl022_ssp_controller pl022_plat_data;
-extern struct dw_dma_platform_data dmac_plat_data;
-extern struct dw_dma_slave cf_dma_priv;
-extern struct dw_dma_slave nand_read_dma_priv;
-extern struct dw_dma_slave nand_write_dma_priv;
+extern struct pl08x_platform_data pl080_plat_data;
 
-/* Add spear13xx family function declarations here */
 void __init spear_setup_of_timer(void);
+void __init spear3xx_clk_init(void __iomem *misc_base,
+                              void __iomem *soc_config_base);
+void __init spear3xx_map_io(void);
+void __init spear3xx_dt_init_irq(void);
+void __init spear6xx_clk_init(void __iomem *misc_base);
 void __init spear13xx_map_io(void);
 void __init spear13xx_l2x0_init(void);
-bool dw_dma_filter(struct dma_chan *chan, void *slave);
+
 void spear_restart(char, const char *);
+
 void spear13xx_secondary_startup(void);
 void __cpuinit spear13xx_cpu_die(unsigned int cpu);
 
 extern struct smp_operations spear13xx_smp_ops;
 
 #ifdef CONFIG_MACH_SPEAR1310
-void __init spear1310_clk_init(void);
+void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base);
 #else
-static inline void spear1310_clk_init(void) {}
+static inline void spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base) {}
 #endif
 
 #ifdef CONFIG_MACH_SPEAR1340
-void __init spear1340_clk_init(void);
+void __init spear1340_clk_init(void __iomem *misc_base);
 #else
-static inline void spear1340_clk_init(void) {}
+static inline void spear1340_clk_init(void __iomem *misc_base) {}
 #endif
 
 #endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-spear13xx/headsmp.S b/arch/arm/mach-spear/headsmp.S
index ed85473a047f..ed85473a047f 100644
--- a/arch/arm/mach-spear13xx/headsmp.S
+++ b/arch/arm/mach-spear/headsmp.S
diff --git a/arch/arm/mach-spear13xx/hotplug.c b/arch/arm/mach-spear/hotplug.c
index a7d2dd11a4f2..a7d2dd11a4f2 100644
--- a/arch/arm/mach-spear13xx/hotplug.c
+++ b/arch/arm/mach-spear/hotplug.c
diff --git a/arch/arm/plat-spear/include/plat/debug-macro.S b/arch/arm/mach-spear/include/mach/debug-macro.S
index 75b05ad0fbad..75b05ad0fbad 100644
--- a/arch/arm/plat-spear/include/plat/debug-macro.S
+++ b/arch/arm/mach-spear/include/mach/debug-macro.S
diff --git a/arch/arm/mach-spear6xx/include/mach/irqs.h b/arch/arm/mach-spear/include/mach/irqs.h
index 37a5c411a866..92da0a8c6bce 100644
--- a/arch/arm/mach-spear6xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear/include/mach/irqs.h
@@ -1,10 +1,9 @@
 /*
- * arch/arm/mach-spear6xx/include/mach/irqs.h
+ * IRQ helper macros for spear machine family
  *
- * IRQ helper macros for SPEAr6xx machine family
- *
- * Copyright (C) 2009 ST Microelectronics
- * Rajeev Kumar<rajeev-dlh.kumar@st.com>
+ * Copyright (C) 2009-2012 ST Microelectronics
+ * Rajeev Kumar <rajeev-dlh.kumar@st.com>
+ * Viresh Kumar <viresh.linux@gmail.com>
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
@@ -14,6 +13,11 @@
 #ifndef __MACH_IRQS_H
 #define __MACH_IRQS_H
 
+#ifdef CONFIG_ARCH_SPEAR3XX
+#define NR_IRQS                 256
+#endif
+
+#ifdef CONFIG_ARCH_SPEAR6XX
 /* IRQ definitions */
 /* VIC 1 */
 #define IRQ_VIC_END                             64
@@ -21,5 +25,11 @@
 /* GPIO pins virtual irqs */
 #define VIRTUAL_IRQS                            24
 #define NR_IRQS                                 (IRQ_VIC_END + VIRTUAL_IRQS)
+#endif
+
+#ifdef CONFIG_ARCH_SPEAR13XX
+#define IRQ_GIC_END                     160
+#define NR_IRQS                         IRQ_GIC_END
+#endif
 
-#endif  /* __MACH_IRQS_H */
+#endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/misc_regs.h b/arch/arm/mach-spear/include/mach/misc_regs.h
index 6309bf68d6f8..935639ce59ba 100644
--- a/arch/arm/mach-spear3xx/include/mach/misc_regs.h
+++ b/arch/arm/mach-spear/include/mach/misc_regs.h
@@ -16,7 +16,7 @@
 
 #include <mach/spear.h>
 
-#define MISC_BASE               IOMEM(VA_SPEAR3XX_ICM3_MISC_REG_BASE)
+#define MISC_BASE               (VA_SPEAR_ICM3_MISC_REG_BASE)
 #define DMA_CHN_CFG             (MISC_BASE + 0x0A0)
 
 #endif /* __MACH_MISC_REGS_H */
diff --git a/arch/arm/mach-spear/include/mach/spear.h b/arch/arm/mach-spear/include/mach/spear.h
new file mode 100644
index 000000000000..cf3a5369eeca
--- /dev/null
+++ b/arch/arm/mach-spear/include/mach/spear.h
@@ -0,0 +1,93 @@
+/*
+ * SPEAr3xx/6xx Machine family specific definition
+ *
+ * Copyright (C) 2009,2012 ST Microelectronics
+ * Rajeev Kumar<rajeev-dlh.kumar@st.com>
+ * Viresh Kumar <viresh.linux@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_SPEAR_H
+#define __MACH_SPEAR_H
+
+#include <asm/memory.h>
+
+#if defined(CONFIG_ARCH_SPEAR3XX) || defined (CONFIG_ARCH_SPEAR6XX)
+
+/* ICM1 - Low speed connection */
+#define SPEAR_ICM1_2_BASE               UL(0xD0000000)
+#define VA_SPEAR_ICM1_2_BASE            IOMEM(0xFD000000)
+#define SPEAR_ICM1_UART_BASE            UL(0xD0000000)
+#define VA_SPEAR_ICM1_UART_BASE         (VA_SPEAR_ICM1_2_BASE - SPEAR_ICM1_2_BASE + SPEAR_ICM1_UART_BASE)
+#define SPEAR3XX_ICM1_SSP_BASE          UL(0xD0100000)
+
+/* ML-1, 2 - Multi Layer CPU Subsystem */
+#define SPEAR_ICM3_ML1_2_BASE           UL(0xF0000000)
+#define VA_SPEAR6XX_ML_CPU_BASE         IOMEM(0xF0000000)
+
+/* ICM3 - Basic Subsystem */
+#define SPEAR_ICM3_SMI_CTRL_BASE        UL(0xFC000000)
+#define VA_SPEAR_ICM3_SMI_CTRL_BASE     IOMEM(0xFC000000)
+#define SPEAR_ICM3_DMA_BASE             UL(0xFC400000)
+#define SPEAR_ICM3_SYS_CTRL_BASE        UL(0xFCA00000)
+#define VA_SPEAR_ICM3_SYS_CTRL_BASE     (VA_SPEAR_ICM3_SMI_CTRL_BASE - SPEAR_ICM3_SMI_CTRL_BASE + SPEAR_ICM3_SYS_CTRL_BASE)
+#define SPEAR_ICM3_MISC_REG_BASE        UL(0xFCA80000)
+#define VA_SPEAR_ICM3_MISC_REG_BASE     (VA_SPEAR_ICM3_SMI_CTRL_BASE - SPEAR_ICM3_SMI_CTRL_BASE + SPEAR_ICM3_MISC_REG_BASE)
+
+/* Debug uart for linux, will be used for debug and uncompress messages */
+#define SPEAR_DBG_UART_BASE             SPEAR_ICM1_UART_BASE
+#define VA_SPEAR_DBG_UART_BASE          VA_SPEAR_ICM1_UART_BASE
+
+/* Sysctl base for spear platform */
+#define SPEAR_SYS_CTRL_BASE             SPEAR_ICM3_SYS_CTRL_BASE
+#define VA_SPEAR_SYS_CTRL_BASE          VA_SPEAR_ICM3_SYS_CTRL_BASE
+#endif /* SPEAR3xx || SPEAR6XX */
+
+/* SPEAr320 Macros */
+#define SPEAR320_SOC_CONFIG_BASE        UL(0xB3000000)
+#define VA_SPEAR320_SOC_CONFIG_BASE     IOMEM(0xFE000000)
+
+#ifdef CONFIG_ARCH_SPEAR13XX
+
+#define PERIP_GRP2_BASE                         UL(0xB3000000)
+#define VA_PERIP_GRP2_BASE                      IOMEM(0xFE000000)
+#define MCIF_SDHCI_BASE                         UL(0xB3000000)
+#define SYSRAM0_BASE                            UL(0xB3800000)
+#define VA_SYSRAM0_BASE                         IOMEM(0xFE800000)
+#define SYS_LOCATION                            (VA_SYSRAM0_BASE + 0x600)
+
+#define PERIP_GRP1_BASE                         UL(0xE0000000)
+#define VA_PERIP_GRP1_BASE                      IOMEM(0xFD000000)
+#define UART_BASE                               UL(0xE0000000)
+#define VA_UART_BASE                            IOMEM(0xFD000000)
+#define SSP_BASE                                UL(0xE0100000)
+#define MISC_BASE                               UL(0xE0700000)
+#define VA_MISC_BASE                            IOMEM(0xFD700000)
+
+#define A9SM_AND_MPMC_BASE                      UL(0xEC000000)
+#define VA_A9SM_AND_MPMC_BASE                   IOMEM(0xFC000000)
+
+#define SPEAR1310_RAS_BASE                      UL(0xD8400000)
+#define VA_SPEAR1310_RAS_BASE                   IOMEM(UL(0xFA400000))
+
+/* A9SM peripheral offsets */
+#define A9SM_PERIP_BASE                         UL(0xEC800000)
+#define VA_A9SM_PERIP_BASE                      IOMEM(0xFC800000)
+#define VA_SCU_BASE                             (VA_A9SM_PERIP_BASE + 0x00)
+
+#define L2CC_BASE                               UL(0xED000000)
+#define VA_L2CC_BASE                            IOMEM(UL(0xFB000000))
+
+/* others */
+#define MCIF_CF_BASE                            UL(0xB2800000)
+
+/* Debug uart for linux, will be used for debug and uncompress messages */
+#define SPEAR_DBG_UART_BASE                     UART_BASE
+#define VA_SPEAR_DBG_UART_BASE                  VA_UART_BASE
+
+#endif /* SPEAR13XX */
+
+#endif /* __MACH_SPEAR_H */
diff --git a/arch/arm/plat-spear/include/plat/timex.h b/arch/arm/mach-spear/include/mach/timex.h
index ef95e5b780bd..ef95e5b780bd 100644
--- a/arch/arm/plat-spear/include/plat/timex.h
+++ b/arch/arm/mach-spear/include/mach/timex.h
diff --git a/arch/arm/plat-spear/include/plat/uncompress.h b/arch/arm/mach-spear/include/mach/uncompress.h
index 51b2dc93e4da..51b2dc93e4da 100644
--- a/arch/arm/plat-spear/include/plat/uncompress.h
+++ b/arch/arm/mach-spear/include/mach/uncompress.h
diff --git a/arch/arm/plat-spear/pl080.c b/arch/arm/mach-spear/pl080.c
index cfa1199d0f4a..cfa1199d0f4a 100644
--- a/arch/arm/plat-spear/pl080.c
+++ b/arch/arm/mach-spear/pl080.c
diff --git a/arch/arm/plat-spear/include/plat/pl080.h b/arch/arm/mach-spear/pl080.h
index eb6590ded40d..eb6590ded40d 100644
--- a/arch/arm/plat-spear/include/plat/pl080.h
+++ b/arch/arm/mach-spear/pl080.h
diff --git a/arch/arm/mach-spear13xx/platsmp.c b/arch/arm/mach-spear/platsmp.c
index af4ade61cd95..927979e26b4d 100644
--- a/arch/arm/mach-spear13xx/platsmp.c
+++ b/arch/arm/mach-spear/platsmp.c
@@ -19,7 +19,7 @@
 #include <asm/cacheflush.h>
 #include <asm/smp_scu.h>
 #include <mach/spear.h>
-#include <mach/generic.h>
+#include "generic.h"
 
 static DEFINE_SPINLOCK(boot_lock);
 
diff --git a/arch/arm/plat-spear/restart.c b/arch/arm/mach-spear/restart.c
index 7d4616d5df11..2b44500bb718 100644
--- a/arch/arm/plat-spear/restart.c
+++ b/arch/arm/mach-spear/restart.c
@@ -14,7 +14,7 @@
 #include <linux/amba/sp810.h>
 #include <asm/system_misc.h>
 #include <mach/spear.h>
-#include <mach/generic.h>
+#include "generic.h"
 
 #define SPEAR13XX_SYS_SW_RES                    (VA_MISC_BASE + 0x204)
 void spear_restart(char mode, const char *cmd)
@@ -26,7 +26,8 @@ void spear_restart(char mode, const char *cmd)
                 /* hardware reset, Use on-chip reset capability */
 #ifdef CONFIG_ARCH_SPEAR13XX
                 writel_relaxed(0x01, SPEAR13XX_SYS_SW_RES);
-#else
+#endif
+#if defined(CONFIG_ARCH_SPEAR3XX) || defined(CONFIG_ARCH_SPEAR6XX)
                 sysctl_soft_reset((void __iomem *)VA_SPEAR_SYS_CTRL_BASE);
 #endif
         }
diff --git a/arch/arm/mach-spear13xx/spear1310.c b/arch/arm/mach-spear/spear1310.c
index 56214d1076ef..9eaac2c881ea 100644
--- a/arch/arm/mach-spear13xx/spear1310.c
+++ b/arch/arm/mach-spear/spear1310.c
@@ -19,46 +19,16 @@
 #include <linux/pata_arasan_cf_data.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <mach/generic.h>
+#include "generic.h"
 #include <mach/spear.h>
 
 /* Base addresses */
-#define SPEAR1310_SSP1_BASE                     UL(0x5D400000)
-#define SPEAR1310_SATA0_BASE                    UL(0xB1000000)
-#define SPEAR1310_SATA1_BASE                    UL(0xB1800000)
-#define SPEAR1310_SATA2_BASE                    UL(0xB4000000)
-
 #define SPEAR1310_RAS_GRP1_BASE                 UL(0xD8000000)
 #define VA_SPEAR1310_RAS_GRP1_BASE              UL(0xFA000000)
-#define SPEAR1310_RAS_BASE                      UL(0xD8400000)
-#define VA_SPEAR1310_RAS_BASE                   IOMEM(UL(0xFA400000))
-
-static struct arasan_cf_pdata cf_pdata = {
-        .cf_if_clk = CF_IF_CLK_166M,
-        .quirk = CF_BROKEN_UDMA,
-        .dma_priv = &cf_dma_priv,
-};
-
-/* ssp device registration */
-static struct pl022_ssp_controller ssp1_plat_data = {
-        .enable_dma = 0,
-};
-
-/* Add SPEAr1310 auxdata to pass platform data */
-static struct of_dev_auxdata spear1310_auxdata_lookup[] __initdata = {
-        OF_DEV_AUXDATA("arasan,cf-spear1340", MCIF_CF_BASE, NULL, &cf_pdata),
-        OF_DEV_AUXDATA("snps,dma-spear1340", DMAC0_BASE, NULL, &dmac_plat_data),
-        OF_DEV_AUXDATA("snps,dma-spear1340", DMAC1_BASE, NULL, &dmac_plat_data),
-        OF_DEV_AUXDATA("arm,pl022", SSP_BASE, NULL, &pl022_plat_data),
-
-        OF_DEV_AUXDATA("arm,pl022", SPEAR1310_SSP1_BASE, NULL, &ssp1_plat_data),
-        {}
-};
 
 static void __init spear1310_dt_init(void)
 {
-        of_platform_populate(NULL, of_default_bus_match_table,
-                        spear1310_auxdata_lookup, NULL);
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
 static const char * const spear1310_dt_board_compat[] = {
diff --git a/arch/arm/mach-spear13xx/spear1340.c b/arch/arm/mach-spear/spear1340.c
index 9a28beb2a113..a04a7fe76f71 100644
--- a/arch/arm/mach-spear13xx/spear1340.c
+++ b/arch/arm/mach-spear/spear1340.c
@@ -16,17 +16,16 @@
 #include <linux/ahci_platform.h>
 #include <linux/amba/serial.h>
 #include <linux/delay.h>
-#include <linux/dw_dmac.h>
 #include <linux/of_platform.h>
 #include <linux/irqchip.h>
 #include <asm/mach/arch.h>
-#include <mach/dma.h>
-#include <mach/generic.h>
+#include "generic.h"
 #include <mach/spear.h>
 
+/* FIXME: Move SATA PHY code into a standalone driver */
+
 /* Base addresses */
 #define SPEAR1340_SATA_BASE                     UL(0xB1000000)
-#define SPEAR1340_UART1_BASE                    UL(0xB4100000)
 
 /* Power Management Registers */
 #define SPEAR1340_PCM_CFG                       (VA_MISC_BASE + 0x100)
@@ -78,28 +77,6 @@
                         (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
                         SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
 
-static struct dw_dma_slave uart1_dma_param[] = {
-        {
-                /* Tx */
-                .cfg_hi = DWC_CFGH_DST_PER(SPEAR1340_DMA_REQ_UART1_TX),
-                .cfg_lo = 0,
-                .src_master = DMA_MASTER_MEMORY,
-                .dst_master = SPEAR1340_DMA_MASTER_UART1,
-        }, {
-                /* Rx */
-                .cfg_hi = DWC_CFGH_SRC_PER(SPEAR1340_DMA_REQ_UART1_RX),
-                .cfg_lo = 0,
-                .src_master = SPEAR1340_DMA_MASTER_UART1,
-                .dst_master = DMA_MASTER_MEMORY,
-        }
-};
-
-static struct amba_pl011_data uart1_data = {
-        .dma_filter = dw_dma_filter,
-        .dma_tx_param = &uart1_dma_param[0],
-        .dma_rx_param = &uart1_dma_param[1],
-};
-
 /* SATA device registration */
 static int sata_miphy_init(struct device *dev, void __iomem *addr)
 {
@@ -158,14 +135,8 @@ static struct ahci_platform_data sata_pdata = {
 
 /* Add SPEAr1340 auxdata to pass platform data */
 static struct of_dev_auxdata spear1340_auxdata_lookup[] __initdata = {
-        OF_DEV_AUXDATA("arasan,cf-spear1340", MCIF_CF_BASE, NULL, &cf_dma_priv),
-        OF_DEV_AUXDATA("snps,dma-spear1340", DMAC0_BASE, NULL, &dmac_plat_data),
-        OF_DEV_AUXDATA("snps,dma-spear1340", DMAC1_BASE, NULL, &dmac_plat_data),
-        OF_DEV_AUXDATA("arm,pl022", SSP_BASE, NULL, &pl022_plat_data),
-
         OF_DEV_AUXDATA("snps,spear-ahci", SPEAR1340_SATA_BASE, NULL,
                         &sata_pdata),
-        OF_DEV_AUXDATA("arm,pl011", SPEAR1340_UART1_BASE, NULL, &uart1_data),
         {}
 };
 
diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear/spear13xx.c
index 25a10191b021..3621599c38ad 100644
--- a/arch/arm/mach-spear13xx/spear13xx.c
+++ b/arch/arm/mach-spear/spear13xx.c
@@ -16,69 +16,12 @@
 #include <linux/amba/pl022.h>
 #include <linux/clk.h>
 #include <linux/clocksource.h>
-#include <linux/dw_dmac.h>
 #include <linux/err.h>
 #include <linux/of.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/map.h>
-#include <mach/dma.h>
-#include <mach/generic.h>
 #include <mach/spear.h>
-
-/* common dw_dma filter routine to be used by peripherals */
-bool dw_dma_filter(struct dma_chan *chan, void *slave)
-{
-        struct dw_dma_slave *dws = (struct dw_dma_slave *)slave;
-
-        if (chan->device->dev == dws->dma_dev) {
-                chan->private = slave;
-                return true;
-        } else {
-                return false;
-        }
-}
-
-/* ssp device registration */
-static struct dw_dma_slave ssp_dma_param[] = {
-        {
-                /* Tx */
-                .cfg_hi = DWC_CFGH_DST_PER(DMA_REQ_SSP0_TX),
-                .cfg_lo = 0,
-                .src_master = DMA_MASTER_MEMORY,
-                .dst_master = DMA_MASTER_SSP0,
-        }, {
-                /* Rx */
-                .cfg_hi = DWC_CFGH_SRC_PER(DMA_REQ_SSP0_RX),
-                .cfg_lo = 0,
-                .src_master = DMA_MASTER_SSP0,
-                .dst_master = DMA_MASTER_MEMORY,
-        }
-};
-
-struct pl022_ssp_controller pl022_plat_data = {
-        .enable_dma = 1,
-        .dma_filter = dw_dma_filter,
-        .dma_rx_param = &ssp_dma_param[1],
-        .dma_tx_param = &ssp_dma_param[0],
-};
-
-/* CF device registration */
-struct dw_dma_slave cf_dma_priv = {
-        .cfg_hi = 0,
-        .cfg_lo = 0,
-        .src_master = 0,
-        .dst_master = 0,
-};
-
-/* dmac device registeration */
-struct dw_dma_platform_data dmac_plat_data = {
-        .nr_channels = 8,
-        .chan_allocation_order = CHAN_ALLOCATION_DESCENDING,
-        .chan_priority = CHAN_PRIORITY_DESCENDING,
-        .block_size = 4095U,
-        .nr_masters = 2,
-        .data_width = { 3, 3, 0, 0 },
-};
+#include "generic.h"
 
 void __init spear13xx_l2x0_init(void)
 {
@@ -145,9 +88,9 @@ void __init spear13xx_map_io(void)
 static void __init spear13xx_clk_init(void)
 {
         if (of_machine_is_compatible("st,spear1310"))
-                spear1310_clk_init();
+                spear1310_clk_init(VA_MISC_BASE, VA_SPEAR1310_RAS_BASE);
         else if (of_machine_is_compatible("st,spear1340"))
-                spear1340_clk_init();
+                spear1340_clk_init(VA_MISC_BASE);
         else
                 pr_err("%s: Unknown machine\n", __func__);
 }
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear/spear300.c
index bbc9b7e9c62c..bac56e845f7a 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear/spear300.c
@@ -17,7 +17,7 @@
 #include <linux/irqchip.h>
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>
-#include <mach/generic.h>
+#include "generic.h"
 #include <mach/spear.h>
 
 /* DMAC platform data's slave info */
@@ -185,7 +185,7 @@ struct pl08x_channel_data spear300_dma_info[] = {
 static struct of_dev_auxdata spear300_auxdata_lookup[] __initdata = {
         OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
                         &pl022_plat_data),
-        OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
+        OF_DEV_AUXDATA("arm,pl080", SPEAR_ICM3_DMA_BASE, NULL,
                         &pl080_plat_data),
         {}
 };
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear/spear310.c
index c13a434a8195..6ffbc63d516d 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear/spear310.c
@@ -18,7 +18,7 @@
 #include <linux/irqchip.h>
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>
-#include <mach/generic.h>
+#include "generic.h"
 #include <mach/spear.h>
 
 #define SPEAR310_UART1_BASE             UL(0xB2000000)
@@ -217,7 +217,7 @@ static struct amba_pl011_data spear310_uart_data[] = {
 static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = {
         OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
                         &pl022_plat_data),
-        OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
+        OF_DEV_AUXDATA("arm,pl080", SPEAR_ICM3_DMA_BASE, NULL,
                         &pl080_plat_data),
         OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART1_BASE, NULL,
                         &spear310_uart_data[0]),
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear/spear320.c
index e1c77079a3e5..6eb3eec65f96 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear/spear320.c
@@ -19,7 +19,8 @@
 #include <linux/irqchip.h>
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>
-#include <mach/generic.h>
+#include <asm/mach/map.h>
+#include "generic.h"
 #include <mach/spear.h>
 
 #define SPEAR320_UART1_BASE             UL(0xA3000000)
@@ -222,7 +223,7 @@ static struct amba_pl011_data spear320_uart_data[] = {
 static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = {
         OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
                         &pl022_plat_data),
-        OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
+        OF_DEV_AUXDATA("arm,pl080", SPEAR_ICM3_DMA_BASE, NULL,
                         &pl080_plat_data),
         OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP0_BASE, NULL,
                         &spear320_ssp_data[0]),
@@ -253,7 +254,7 @@ static const char * const spear320_dt_board_compat[] = {
 
 struct map_desc spear320_io_desc[] __initdata = {
         {
-                .virtual        = VA_SPEAR320_SOC_CONFIG_BASE,
+                .virtual        = (unsigned long)VA_SPEAR320_SOC_CONFIG_BASE,
                 .pfn            = __phys_to_pfn(SPEAR320_SOC_CONFIG_BASE),
                 .length         = SZ_16M,
                 .type           = MT_DEVICE
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear/spear3xx.c
index d2b3937c4014..0227c97797cd 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear/spear3xx.c
@@ -15,10 +15,13 @@
 
 #include <linux/amba/pl022.h>
 #include <linux/amba/pl080.h>
+#include <linux/clk.h>
 #include <linux/io.h>
-#include <plat/pl080.h>
-#include <mach/generic.h>
+#include <asm/mach/map.h>
+#include "pl080.h"
+#include "generic.h"
 #include <mach/spear.h>
+#include <mach/misc_regs.h>
 
 /* ssp device registration */
 struct pl022_ssp_controller pl022_plat_data = {
@@ -65,13 +68,13 @@ struct pl08x_platform_data pl080_plat_data = {
  */
 struct map_desc spear3xx_io_desc[] __initdata = {
         {
-                .virtual        = VA_SPEAR3XX_ICM1_2_BASE,
-                .pfn            = __phys_to_pfn(SPEAR3XX_ICM1_2_BASE),
+                .virtual        = (unsigned long)VA_SPEAR_ICM1_2_BASE,
+                .pfn            = __phys_to_pfn(SPEAR_ICM1_2_BASE),
                 .length         = SZ_16M,
                 .type           = MT_DEVICE
         }, {
-                .virtual        = VA_SPEAR3XX_ICM3_SMI_CTRL_BASE,
-                .pfn            = __phys_to_pfn(SPEAR3XX_ICM3_SMI_CTRL_BASE),
+                .virtual        = (unsigned long)VA_SPEAR_ICM3_SMI_CTRL_BASE,
+                .pfn            = __phys_to_pfn(SPEAR_ICM3_SMI_CTRL_BASE),
                 .length         = SZ_16M,
                 .type           = MT_DEVICE
         },
@@ -88,7 +91,7 @@ void __init spear3xx_timer_init(void)
         char pclk_name[] = "pll3_clk";
         struct clk *gpt_clk, *pclk;
 
-        spear3xx_clk_init();
+        spear3xx_clk_init(MISC_BASE, VA_SPEAR320_SOC_CONFIG_BASE);
 
         /* get the system timer clock */
         gpt_clk = clk_get_sys("gpt0", NULL);
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear/spear6xx.c
index 8904d8a52d84..ec8eefbbdfad 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear/spear6xx.c
@@ -24,9 +24,10 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
-#include <plat/pl080.h>
-#include <mach/generic.h>
+#include "pl080.h"
+#include "generic.h"
 #include <mach/spear.h>
+#include <mach/misc_regs.h>
 
 /* dmac device registration */
 static struct pl08x_channel_data spear600_dma_info[] = {
@@ -321,7 +322,7 @@ static struct pl08x_channel_data spear600_dma_info[] = {
         },
 };
 
-struct pl08x_platform_data pl080_plat_data = {
+static struct pl08x_platform_data spear6xx_pl080_plat_data = {
         .memcpy_channel = {
                 .bus_id = "memcpy",
                 .cctl_memcpy =
@@ -350,18 +351,18 @@ struct pl08x_platform_data pl080_plat_data = {
  */
 struct map_desc spear6xx_io_desc[] __initdata = {
         {
-                .virtual        = VA_SPEAR6XX_ML_CPU_BASE,
-                .pfn            = __phys_to_pfn(SPEAR6XX_ML_CPU_BASE),
+                .virtual        = (unsigned long)VA_SPEAR6XX_ML_CPU_BASE,
+                .pfn            = __phys_to_pfn(SPEAR_ICM3_ML1_2_BASE),
                 .length         = 2 * SZ_16M,
                 .type           = MT_DEVICE
         },      {
-                .virtual        = VA_SPEAR6XX_ICM1_BASE,
-                .pfn            = __phys_to_pfn(SPEAR6XX_ICM1_BASE),
+                .virtual        = (unsigned long)VA_SPEAR_ICM1_2_BASE,
+                .pfn            = __phys_to_pfn(SPEAR_ICM1_2_BASE),
                 .length         = SZ_16M,
                 .type           = MT_DEVICE
         }, {
-                .virtual        = VA_SPEAR6XX_ICM3_SMI_CTRL_BASE,
-                .pfn            = __phys_to_pfn(SPEAR6XX_ICM3_SMI_CTRL_BASE),
+                .virtual        = (unsigned long)VA_SPEAR_ICM3_SMI_CTRL_BASE,
+                .pfn            = __phys_to_pfn(SPEAR_ICM3_SMI_CTRL_BASE),
                 .length         = SZ_16M,
                 .type           = MT_DEVICE
         },
@@ -378,7 +379,7 @@ void __init spear6xx_timer_init(void)
         char pclk_name[] = "pll3_clk";
         struct clk *gpt_clk, *pclk;
 
-        spear6xx_clk_init();
+        spear6xx_clk_init(MISC_BASE);
 
         /* get the system timer clock */
         gpt_clk = clk_get_sys("gpt0", NULL);
@@ -404,8 +405,8 @@ void __init spear6xx_timer_init(void)
 
 /* Add auxdata to pass platform data */
 struct of_dev_auxdata spear6xx_auxdata_lookup[] __initdata = {
-        OF_DEV_AUXDATA("arm,pl080", SPEAR6XX_ICM3_DMA_BASE, NULL,
-                        &pl080_plat_data),
+        OF_DEV_AUXDATA("arm,pl080", SPEAR_ICM3_DMA_BASE, NULL,
+                        &spear6xx_pl080_plat_data),
         {}
 };
 
diff --git a/arch/arm/plat-spear/time.c b/arch/arm/mach-spear/time.c
index bd5c53cd6962..d449673e40f7 100644
--- a/arch/arm/plat-spear/time.c
+++ b/arch/arm/mach-spear/time.c
@@ -23,7 +23,7 @@
 #include <linux/time.h>
 #include <linux/irq.h>
 #include <asm/mach/time.h>
-#include <mach/generic.h>
+#include "generic.h"
 
 /*
  * We would use TIMER0 and TIMER1 as clockevent and clocksource.
diff --git a/arch/arm/mach-spear13xx/Kconfig b/arch/arm/mach-spear13xx/Kconfig
deleted file mode 100644
index eaadc66d96b3..000000000000
--- a/arch/arm/mach-spear13xx/Kconfig
+++ /dev/null
@@ -1,20 +0,0 @@
-#
-# SPEAr13XX Machine configuration file
-#
-
-if ARCH_SPEAR13XX
-
-menu "SPEAr13xx Implementations"
-config MACH_SPEAR1310
-        bool "SPEAr1310 Machine support with Device Tree"
-        select PINCTRL_SPEAR1310
-        help
-          Supports ST SPEAr1310 machine configured via the device-tree
-
-config MACH_SPEAR1340
-        bool "SPEAr1340 Machine support with Device Tree"
-        select PINCTRL_SPEAR1340
-        help
-          Supports ST SPEAr1340 machine configured via the device-tree
-endmenu
-endif #ARCH_SPEAR13XX
diff --git a/arch/arm/mach-spear13xx/Makefile b/arch/arm/mach-spear13xx/Makefile
deleted file mode 100644
index 3435ea78c15d..000000000000
--- a/arch/arm/mach-spear13xx/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# Makefile for SPEAr13XX machine series
-#
-
-obj-$(CONFIG_SMP)               += headsmp.o platsmp.o
-obj-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
-
-obj-$(CONFIG_ARCH_SPEAR13XX)    += spear13xx.o
-obj-$(CONFIG_MACH_SPEAR1310)    += spear1310.o
-obj-$(CONFIG_MACH_SPEAR1340)    += spear1340.o
diff --git a/arch/arm/mach-spear13xx/include/mach/debug-macro.S b/arch/arm/mach-spear13xx/include/mach/debug-macro.S
deleted file mode 100644
index 9e3ae6bfe50d..000000000000
--- a/arch/arm/mach-spear13xx/include/mach/debug-macro.S
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * arch/arm/mach-spear13xx/include/mach/debug-macro.S
- *
- * Debugging macro include header spear13xx machine family
- *
- * Copyright (C) 2012 ST Microelectronics
- * Viresh Kumar <viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-spear13xx/include/mach/dma.h b/arch/arm/mach-spear13xx/include/mach/dma.h
deleted file mode 100644
index d50bdb605925..000000000000
--- a/arch/arm/mach-spear13xx/include/mach/dma.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * arch/arm/mach-spear13xx/include/mach/dma.h
- *
- * DMA information for SPEAr13xx machine family
- *
- * Copyright (C) 2012 ST Microelectronics
- * Viresh Kumar <viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_DMA_H
-#define __MACH_DMA_H
-
-/* request id of all the peripherals */
-enum dma_master_info {
-        /* Accessible from only one master */
-        DMA_MASTER_MCIF = 0,
-        DMA_MASTER_FSMC = 1,
-        /* Accessible from both 0 & 1 */
-        DMA_MASTER_MEMORY = 0,
-        DMA_MASTER_ADC = 0,
-        DMA_MASTER_UART0 = 0,
-        DMA_MASTER_SSP0 = 0,
-        DMA_MASTER_I2C0 = 0,
-
-#ifdef CONFIG_MACH_SPEAR1310
-        /* Accessible from only one master */
-        SPEAR1310_DMA_MASTER_JPEG = 1,
-
-        /* Accessible from both 0 & 1 */
-        SPEAR1310_DMA_MASTER_I2S = 0,
-        SPEAR1310_DMA_MASTER_UART1 = 0,
-        SPEAR1310_DMA_MASTER_UART2 = 0,
-        SPEAR1310_DMA_MASTER_UART3 = 0,
-        SPEAR1310_DMA_MASTER_UART4 = 0,
-        SPEAR1310_DMA_MASTER_UART5 = 0,
-        SPEAR1310_DMA_MASTER_I2C1 = 0,
-        SPEAR1310_DMA_MASTER_I2C2 = 0,
-        SPEAR1310_DMA_MASTER_I2C3 = 0,
-        SPEAR1310_DMA_MASTER_I2C4 = 0,
-        SPEAR1310_DMA_MASTER_I2C5 = 0,
-        SPEAR1310_DMA_MASTER_I2C6 = 0,
-        SPEAR1310_DMA_MASTER_I2C7 = 0,
-        SPEAR1310_DMA_MASTER_SSP1 = 0,
-#endif
-
-#ifdef CONFIG_MACH_SPEAR1340
-        /* Accessible from only one master */
-        SPEAR1340_DMA_MASTER_I2S_PLAY = 1,
-        SPEAR1340_DMA_MASTER_I2S_REC = 1,
-        SPEAR1340_DMA_MASTER_I2C1 = 1,
-        SPEAR1340_DMA_MASTER_UART1 = 1,
-
-        /* following are accessible from both master 0 & 1 */
-        SPEAR1340_DMA_MASTER_SPDIF = 0,
-        SPEAR1340_DMA_MASTER_CAM = 1,
-        SPEAR1340_DMA_MASTER_VIDEO_IN = 0,
-        SPEAR1340_DMA_MASTER_MALI = 0,
-#endif
-};
-
-enum request_id {
-        DMA_REQ_ADC = 0,
-        DMA_REQ_SSP0_TX = 4,
-        DMA_REQ_SSP0_RX = 5,
-        DMA_REQ_UART0_TX = 6,
-        DMA_REQ_UART0_RX = 7,
-        DMA_REQ_I2C0_TX = 8,
-        DMA_REQ_I2C0_RX = 9,
-
-#ifdef CONFIG_MACH_SPEAR1310
-        SPEAR1310_DMA_REQ_FROM_JPEG = 2,
-        SPEAR1310_DMA_REQ_TO_JPEG = 3,
-        SPEAR1310_DMA_REQ_I2S_TX = 10,
-        SPEAR1310_DMA_REQ_I2S_RX = 11,
-
-        SPEAR1310_DMA_REQ_I2C1_RX = 0,
-        SPEAR1310_DMA_REQ_I2C1_TX = 1,
-        SPEAR1310_DMA_REQ_I2C2_RX = 2,
-        SPEAR1310_DMA_REQ_I2C2_TX = 3,
-        SPEAR1310_DMA_REQ_I2C3_RX = 4,
-        SPEAR1310_DMA_REQ_I2C3_TX = 5,
-        SPEAR1310_DMA_REQ_I2C4_RX = 6,
-        SPEAR1310_DMA_REQ_I2C4_TX = 7,
-        SPEAR1310_DMA_REQ_I2C5_RX = 8,
-        SPEAR1310_DMA_REQ_I2C5_TX = 9,
-        SPEAR1310_DMA_REQ_I2C6_RX = 10,
-        SPEAR1310_DMA_REQ_I2C6_TX = 11,
-        SPEAR1310_DMA_REQ_UART1_RX = 12,
-        SPEAR1310_DMA_REQ_UART1_TX = 13,
-        SPEAR1310_DMA_REQ_UART2_RX = 14,
-        SPEAR1310_DMA_REQ_UART2_TX = 15,
-        SPEAR1310_DMA_REQ_UART5_RX = 16,
-        SPEAR1310_DMA_REQ_UART5_TX = 17,
-        SPEAR1310_DMA_REQ_SSP1_RX = 18,
-        SPEAR1310_DMA_REQ_SSP1_TX = 19,
-        SPEAR1310_DMA_REQ_I2C7_RX = 20,
-        SPEAR1310_DMA_REQ_I2C7_TX = 21,
-        SPEAR1310_DMA_REQ_UART3_RX = 28,
-        SPEAR1310_DMA_REQ_UART3_TX = 29,
-        SPEAR1310_DMA_REQ_UART4_RX = 30,
-        SPEAR1310_DMA_REQ_UART4_TX = 31,
-#endif
-
-#ifdef CONFIG_MACH_SPEAR1340
-        SPEAR1340_DMA_REQ_SPDIF_TX = 2,
-        SPEAR1340_DMA_REQ_SPDIF_RX = 3,
-        SPEAR1340_DMA_REQ_I2S_TX = 10,
-        SPEAR1340_DMA_REQ_I2S_RX = 11,
-        SPEAR1340_DMA_REQ_UART1_TX = 12,
-        SPEAR1340_DMA_REQ_UART1_RX = 13,
-        SPEAR1340_DMA_REQ_I2C1_TX = 14,
-        SPEAR1340_DMA_REQ_I2C1_RX = 15,
-        SPEAR1340_DMA_REQ_CAM0_EVEN = 0,
-        SPEAR1340_DMA_REQ_CAM0_ODD = 1,
-        SPEAR1340_DMA_REQ_CAM1_EVEN = 2,
-        SPEAR1340_DMA_REQ_CAM1_ODD = 3,
-        SPEAR1340_DMA_REQ_CAM2_EVEN = 4,
-        SPEAR1340_DMA_REQ_CAM2_ODD = 5,
-        SPEAR1340_DMA_REQ_CAM3_EVEN = 6,
-        SPEAR1340_DMA_REQ_CAM3_ODD = 7,
-#endif
-};
-
-#endif /* __MACH_DMA_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/hardware.h b/arch/arm/mach-spear13xx/include/mach/hardware.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/arm/mach-spear13xx/include/mach/hardware.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-spear13xx/include/mach/irqs.h b/arch/arm/mach-spear13xx/include/mach/irqs.h
deleted file mode 100644
index 271a62b4cd31..000000000000
--- a/arch/arm/mach-spear13xx/include/mach/irqs.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * arch/arm/mach-spear13xx/include/mach/irqs.h
- *
- * IRQ helper macros for spear13xx machine family
- *
- * Copyright (C) 2012 ST Microelectronics
- * Viresh Kumar <viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_IRQS_H
-#define __MACH_IRQS_H
-
-#define IRQ_GIC_END                     160
-#define NR_IRQS                         IRQ_GIC_END
-
-#endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/spear.h b/arch/arm/mach-spear13xx/include/mach/spear.h
deleted file mode 100644
index 7cfa6818865a..000000000000
--- a/arch/arm/mach-spear13xx/include/mach/spear.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * arch/arm/mach-spear13xx/include/mach/spear.h
- *
- * spear13xx Machine family specific definition
- *
- * Copyright (C) 2012 ST Microelectronics
- * Viresh Kumar <viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_SPEAR13XX_H
-#define __MACH_SPEAR13XX_H
-
-#include <asm/memory.h>
-
-#define PERIP_GRP2_BASE                         UL(0xB3000000)
-#define VA_PERIP_GRP2_BASE                      IOMEM(0xFE000000)
-#define MCIF_SDHCI_BASE                         UL(0xB3000000)
-#define SYSRAM0_BASE                            UL(0xB3800000)
-#define VA_SYSRAM0_BASE                         IOMEM(0xFE800000)
-#define SYS_LOCATION                            (VA_SYSRAM0_BASE + 0x600)
-
-#define PERIP_GRP1_BASE                         UL(0xE0000000)
-#define VA_PERIP_GRP1_BASE                      IOMEM(0xFD000000)
-#define UART_BASE                               UL(0xE0000000)
-#define VA_UART_BASE                            IOMEM(0xFD000000)
-#define SSP_BASE                                UL(0xE0100000)
-#define MISC_BASE                               UL(0xE0700000)
-#define VA_MISC_BASE                            IOMEM(0xFD700000)
-
-#define A9SM_AND_MPMC_BASE                      UL(0xEC000000)
-#define VA_A9SM_AND_MPMC_BASE                   IOMEM(0xFC000000)
-
-/* A9SM peripheral offsets */
-#define A9SM_PERIP_BASE                         UL(0xEC800000)
-#define VA_A9SM_PERIP_BASE                      IOMEM(0xFC800000)
-#define VA_SCU_BASE                             (VA_A9SM_PERIP_BASE + 0x00)
-
-#define L2CC_BASE                               UL(0xED000000)
-#define VA_L2CC_BASE                            IOMEM(UL(0xFB000000))
-
-/* others */
-#define DMAC0_BASE                              UL(0xEA800000)
-#define DMAC1_BASE                              UL(0xEB000000)
-#define MCIF_CF_BASE                            UL(0xB2800000)
-
-/* Debug uart for linux, will be used for debug and uncompress messages */
-#define SPEAR_DBG_UART_BASE                     UART_BASE
-#define VA_SPEAR_DBG_UART_BASE                  VA_UART_BASE
-
-#endif /* __MACH_SPEAR13XX_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/timex.h b/arch/arm/mach-spear13xx/include/mach/timex.h
deleted file mode 100644
index 3a58b8284a6a..000000000000
--- a/arch/arm/mach-spear13xx/include/mach/timex.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/timex.h
- *
- * SPEAr3XX machine family specific timex definitions
- *
- * Copyright (C) 2012 ST Microelectronics
- * Viresh Kumar <viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_TIMEX_H
-#define __MACH_TIMEX_H
-
-#include <plat/timex.h>
-
-#endif /* __MACH_TIMEX_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/uncompress.h b/arch/arm/mach-spear13xx/include/mach/uncompress.h
deleted file mode 100644
index 70fe72f05dea..000000000000
--- a/arch/arm/mach-spear13xx/include/mach/uncompress.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-spear13xx/include/mach/uncompress.h
- *
- * Serial port stubs for kernel decompress status messages
- *
- * Copyright (C) 2012 ST Microelectronics
- * Viresh Kumar <viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_UNCOMPRESS_H
-#define __MACH_UNCOMPRESS_H
-
-#include <plat/uncompress.h>
-
-#endif /* __MACH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-spear3xx/Kconfig b/arch/arm/mach-spear3xx/Kconfig
deleted file mode 100644
index 8bd37291fa4f..000000000000
--- a/arch/arm/mach-spear3xx/Kconfig
+++ /dev/null
@@ -1,26 +0,0 @@
-#
-# SPEAr3XX Machine configuration file
-#
-
-if ARCH_SPEAR3XX
-
-menu "SPEAr3xx Implementations"
-config MACH_SPEAR300
-        bool "SPEAr300 Machine support with Device Tree"
-        select PINCTRL_SPEAR300
-        help
-          Supports ST SPEAr300 machine configured via the device-tree
-
-config MACH_SPEAR310
-        bool "SPEAr310 Machine support with Device Tree"
-        select PINCTRL_SPEAR310
-        help
-          Supports ST SPEAr310 machine configured via the device-tree
-
-config MACH_SPEAR320
-        bool "SPEAr320 Machine support with Device Tree"
-        select PINCTRL_SPEAR320
-        help
-          Supports ST SPEAr320 machine configured via the device-tree
-endmenu
-endif #ARCH_SPEAR3XX
diff --git a/arch/arm/mach-spear3xx/Makefile b/arch/arm/mach-spear3xx/Makefile
deleted file mode 100644
index 8d12faa178fd..000000000000
--- a/arch/arm/mach-spear3xx/Makefile
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# Makefile for SPEAr3XX machine series
-#
-
-# common files
-obj-$(CONFIG_ARCH_SPEAR3XX)     += spear3xx.o
-
-# spear300 specific files
-obj-$(CONFIG_MACH_SPEAR300) += spear300.o
-
-# spear310 specific files
-obj-$(CONFIG_MACH_SPEAR310) += spear310.o
-
-# spear320 specific files
-obj-$(CONFIG_MACH_SPEAR320) += spear320.o
diff --git a/arch/arm/mach-spear3xx/Makefile.boot b/arch/arm/mach-spear3xx/Makefile.boot
deleted file mode 100644
index 4674a4c221db..000000000000
--- a/arch/arm/mach-spear3xx/Makefile.boot
+++ /dev/null
@@ -1,3 +0,0 @@
-zreladdr-y      += 0x00008000
-params_phys-y   := 0x00000100
-initrd_phys-y   := 0x00800000
diff --git a/arch/arm/mach-spear3xx/include/mach/debug-macro.S b/arch/arm/mach-spear3xx/include/mach/debug-macro.S
deleted file mode 100644
index 0a6381fad5d9..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/debug-macro.S
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/debug-macro.S
- *
- * Debugging macro include header spear3xx machine family
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
deleted file mode 100644
index df310799e416..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/generic.h
- *
- * SPEAr3XX machine family generic header file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_GENERIC_H
-#define __MACH_GENERIC_H
-
-#include <linux/amba/pl08x.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/amba/bus.h>
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
-
-/* Add spear3xx family device structure declarations here */
-extern void spear3xx_timer_init(void);
-extern struct pl022_ssp_controller pl022_plat_data;
-extern struct pl08x_platform_data pl080_plat_data;
-
-/* Add spear3xx family function declarations here */
-void __init spear_setup_of_timer(void);
-void __init spear3xx_clk_init(void);
-void __init spear3xx_map_io(void);
-
-void spear_restart(char, const char *);
-
-#endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/hardware.h b/arch/arm/mach-spear3xx/include/mach/hardware.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/hardware.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-spear3xx/include/mach/irqs.h b/arch/arm/mach-spear3xx/include/mach/irqs.h
deleted file mode 100644
index f95e5b2b6686..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/irqs.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/irqs.h
- *
- * IRQ helper macros for SPEAr3xx machine family
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar <viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_IRQS_H
-#define __MACH_IRQS_H
-
-#define NR_IRQS                 256
-
-#endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear.h b/arch/arm/mach-spear3xx/include/mach/spear.h
deleted file mode 100644
index 8cca95193d4d..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/spear.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/spear.h
- *
- * SPEAr3xx Machine family specific definition
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar <viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_SPEAR3XX_H
-#define __MACH_SPEAR3XX_H
-
-#include <asm/memory.h>
-
-/* ICM1 - Low speed connection */
-#define SPEAR3XX_ICM1_2_BASE            UL(0xD0000000)
-#define VA_SPEAR3XX_ICM1_2_BASE         UL(0xFD000000)
-#define SPEAR3XX_ICM1_UART_BASE         UL(0xD0000000)
-#define VA_SPEAR3XX_ICM1_UART_BASE      (VA_SPEAR3XX_ICM1_2_BASE | SPEAR3XX_ICM1_UART_BASE)
-#define SPEAR3XX_ICM1_SSP_BASE          UL(0xD0100000)
-
-/* ML1 - Multi Layer CPU Subsystem */
-#define SPEAR3XX_ICM3_ML1_2_BASE        UL(0xF0000000)
-#define VA_SPEAR6XX_ML_CPU_BASE         UL(0xF0000000)
-
-/* ICM3 - Basic Subsystem */
-#define SPEAR3XX_ICM3_SMI_CTRL_BASE     UL(0xFC000000)
-#define VA_SPEAR3XX_ICM3_SMI_CTRL_BASE  UL(0xFC000000)
-#define SPEAR3XX_ICM3_DMA_BASE          UL(0xFC400000)
-#define SPEAR3XX_ICM3_SYS_CTRL_BASE     UL(0xFCA00000)
-#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE  (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_SYS_CTRL_BASE)
-#define SPEAR3XX_ICM3_MISC_REG_BASE     UL(0xFCA80000)
-#define VA_SPEAR3XX_ICM3_MISC_REG_BASE  (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_MISC_REG_BASE)
-
-/* Debug uart for linux, will be used for debug and uncompress messages */
-#define SPEAR_DBG_UART_BASE             SPEAR3XX_ICM1_UART_BASE
-#define VA_SPEAR_DBG_UART_BASE          VA_SPEAR3XX_ICM1_UART_BASE
-
-/* Sysctl base for spear platform */
-#define SPEAR_SYS_CTRL_BASE             SPEAR3XX_ICM3_SYS_CTRL_BASE
-#define VA_SPEAR_SYS_CTRL_BASE          VA_SPEAR3XX_ICM3_SYS_CTRL_BASE
-
-/* SPEAr320 Macros */
-#define SPEAR320_SOC_CONFIG_BASE        UL(0xB3000000)
-#define VA_SPEAR320_SOC_CONFIG_BASE     UL(0xFE000000)
-#define SPEAR320_CONTROL_REG            IOMEM(VA_SPEAR320_SOC_CONFIG_BASE)
-#define SPEAR320_EXT_CTRL_REG           IOMEM(VA_SPEAR320_SOC_CONFIG_BASE + 0x0018)
-        #define SPEAR320_UARTX_PCLK_MASK                0x1
-        #define SPEAR320_UART2_PCLK_SHIFT               8
-        #define SPEAR320_UART3_PCLK_SHIFT               9
-        #define SPEAR320_UART4_PCLK_SHIFT               10
-        #define SPEAR320_UART5_PCLK_SHIFT               11
-        #define SPEAR320_UART6_PCLK_SHIFT               12
-        #define SPEAR320_RS485_PCLK_SHIFT               13
-
-#endif /* __MACH_SPEAR3XX_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/timex.h b/arch/arm/mach-spear3xx/include/mach/timex.h
deleted file mode 100644
index 9f5d08bd0c44..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/timex.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/timex.h
- *
- * SPEAr3XX machine family specific timex definitions
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar <viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_TIMEX_H
-#define __MACH_TIMEX_H
-
-#include <plat/timex.h>
-
-#endif /* __MACH_TIMEX_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/uncompress.h b/arch/arm/mach-spear3xx/include/mach/uncompress.h
deleted file mode 100644
index b909b011f7c8..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/uncompress.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/uncompress.h
- *
- * Serial port stubs for kernel decompress status messages
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar <viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_UNCOMPRESS_H
-#define __MACH_UNCOMPRESS_H
-
-#include <plat/uncompress.h>
-
-#endif /* __MACH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-spear6xx/Kconfig b/arch/arm/mach-spear6xx/Kconfig
deleted file mode 100644
index 339f397dea70..000000000000
--- a/arch/arm/mach-spear6xx/Kconfig
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# SPEAr6XX Machine configuration file
-#
-
-config MACH_SPEAR600
-        def_bool y
-        depends on ARCH_SPEAR6XX
-        select USE_OF
-        help
-          Supports ST SPEAr600 boards configured via the device-tree
diff --git a/arch/arm/mach-spear6xx/Makefile b/arch/arm/mach-spear6xx/Makefile
deleted file mode 100644
index 898831d93f37..000000000000
--- a/arch/arm/mach-spear6xx/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# Makefile for SPEAr6XX machine series
-#
-
-# common files
-obj-y   += spear6xx.o
diff --git a/arch/arm/mach-spear6xx/Makefile.boot b/arch/arm/mach-spear6xx/Makefile.boot
deleted file mode 100644
index 4674a4c221db..000000000000
--- a/arch/arm/mach-spear6xx/Makefile.boot
+++ /dev/null
@@ -1,3 +0,0 @@
-zreladdr-y      += 0x00008000
-params_phys-y   := 0x00000100
-initrd_phys-y   := 0x00800000
diff --git a/arch/arm/mach-spear6xx/include/mach/debug-macro.S b/arch/arm/mach-spear6xx/include/mach/debug-macro.S
deleted file mode 100644
index 0f3ea39edd96..000000000000
--- a/arch/arm/mach-spear6xx/include/mach/debug-macro.S
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * arch/arm/mach-spear6xx/include/mach/debug-macro.S
- *
- * Debugging macro include header for SPEAr6xx machine family
- *
- * Copyright (C) 2009 ST Microelectronics
- * Rajeev Kumar<rajeev-dlh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-spear6xx/include/mach/generic.h b/arch/arm/mach-spear6xx/include/mach/generic.h
deleted file mode 100644
index 65514b159370..000000000000
--- a/arch/arm/mach-spear6xx/include/mach/generic.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * arch/arm/mach-spear6xx/include/mach/generic.h
- *
- * SPEAr6XX machine family specific generic header file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Rajeev Kumar<rajeev-dlh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_GENERIC_H
-#define __MACH_GENERIC_H
-
-#include <linux/init.h>
-
-void __init spear_setup_of_timer(void);
-void spear_restart(char, const char *);
-void __init spear6xx_clk_init(void);
-
-#endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/hardware.h b/arch/arm/mach-spear6xx/include/mach/hardware.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/arm/mach-spear6xx/include/mach/hardware.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-spear6xx/include/mach/misc_regs.h b/arch/arm/mach-spear6xx/include/mach/misc_regs.h
deleted file mode 100644
index c34acc201d34..000000000000
--- a/arch/arm/mach-spear6xx/include/mach/misc_regs.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * arch/arm/mach-spear6xx/include/mach/misc_regs.h
- *
- * Miscellaneous registers definitions for SPEAr6xx machine family
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar <viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_MISC_REGS_H
-#define __MACH_MISC_REGS_H
-
-#include <mach/spear.h>
-
-#define MISC_BASE               IOMEM(VA_SPEAR6XX_ICM3_MISC_REG_BASE)
-#define DMA_CHN_CFG             (MISC_BASE + 0x0A0)
-
-#endif /* __MACH_MISC_REGS_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/spear.h b/arch/arm/mach-spear6xx/include/mach/spear.h
deleted file mode 100644
index cb8ed2f4dc85..000000000000
--- a/arch/arm/mach-spear6xx/include/mach/spear.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * arch/arm/mach-spear6xx/include/mach/spear.h
- *
- * SPEAr6xx Machine family specific definition
- *
- * Copyright (C) 2009 ST Microelectronics
- * Rajeev Kumar<rajeev-dlh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_SPEAR6XX_H
-#define __MACH_SPEAR6XX_H
-
-#include <asm/memory.h>
-
-/* ICM1 - Low speed connection */
-#define SPEAR6XX_ICM1_BASE              UL(0xD0000000)
-#define VA_SPEAR6XX_ICM1_BASE           UL(0xFD000000)
-#define SPEAR6XX_ICM1_UART0_BASE        UL(0xD0000000)
-#define VA_SPEAR6XX_ICM1_UART0_BASE     (VA_SPEAR6XX_ICM1_2_BASE | SPEAR6XX_ICM1_UART0_BASE)
-
-/* ML-1, 2 - Multi Layer CPU Subsystem */
-#define SPEAR6XX_ML_CPU_BASE            UL(0xF0000000)
-#define VA_SPEAR6XX_ML_CPU_BASE         UL(0xF0000000)
-
-/* ICM3 - Basic Subsystem */
-#define SPEAR6XX_ICM3_SMI_CTRL_BASE     UL(0xFC000000)
-#define VA_SPEAR6XX_ICM3_SMI_CTRL_BASE  UL(0xFC000000)
-#define SPEAR6XX_ICM3_DMA_BASE          UL(0xFC400000)
-#define SPEAR6XX_ICM3_SYS_CTRL_BASE     UL(0xFCA00000)
-#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE  (VA_SPEAR6XX_ICM3_SMI_CTRL_BASE | SPEAR6XX_ICM3_SYS_CTRL_BASE)
-#define SPEAR6XX_ICM3_MISC_REG_BASE     UL(0xFCA80000)
-#define VA_SPEAR6XX_ICM3_MISC_REG_BASE  (VA_SPEAR6XX_ICM3_SMI_CTRL_BASE | SPEAR6XX_ICM3_MISC_REG_BASE)
-
-/* Debug uart for linux, will be used for debug and uncompress messages */
-#define SPEAR_DBG_UART_BASE             SPEAR6XX_ICM1_UART0_BASE
-#define VA_SPEAR_DBG_UART_BASE          VA_SPEAR6XX_ICM1_UART0_BASE
-
-/* Sysctl base for spear platform */
-#define SPEAR_SYS_CTRL_BASE             SPEAR6XX_ICM3_SYS_CTRL_BASE
-#define VA_SPEAR_SYS_CTRL_BASE          VA_SPEAR6XX_ICM3_SYS_CTRL_BASE
-
-#endif /* __MACH_SPEAR6XX_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/timex.h b/arch/arm/mach-spear6xx/include/mach/timex.h
deleted file mode 100644
index ac1c5b005695..000000000000
--- a/arch/arm/mach-spear6xx/include/mach/timex.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-spear6xx/include/mach/timex.h
- *
- * SPEAr6XX machine family specific timex definitions
- *
- * Copyright (C) 2009 ST Microelectronics
- * Rajeev Kumar<rajeev-dlh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_TIMEX_H
-#define __MACH_TIMEX_H
-
-#include <plat/timex.h>
-
-#endif  /* __MACH_TIMEX_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/uncompress.h b/arch/arm/mach-spear6xx/include/mach/uncompress.h
deleted file mode 100644
index 77f0765e21e1..000000000000
--- a/arch/arm/mach-spear6xx/include/mach/uncompress.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-spear6xx/include/mach/uncompress.h
- *
- * Serial port stubs for kernel decompress status messages
- *
- * Copyright (C) 2009 ST Microelectronics
- * Rajeev Kumar<rajeev-dlh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_UNCOMPRESS_H
-#define __MACH_UNCOMPRESS_H
-
-#include <plat/uncompress.h>
-
-#endif  /* __MACH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index f6b46ae2b7f8..e40326d0e29f 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -10,6 +10,7 @@ obj-y					+= pm.o
 obj-y                                   += reset.o
 obj-y                                   += reset-handler.o
 obj-y                                   += sleep.o
+obj-y                                   += tegra.o
 obj-$(CONFIG_CPU_IDLE)                  += cpuidle.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra20_speedo.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_emc.o
@@ -27,9 +28,7 @@ obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
 obj-$(CONFIG_CPU_FREQ)                  += cpu-tegra.o
 obj-$(CONFIG_TEGRA_PCI)                 += pcie.o
 
-obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += board-dt-tegra20.o
-obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += board-dt-tegra30.o
-obj-$(CONFIG_ARCH_TEGRA_114_SOC)        += board-dt-tegra114.o
+obj-$(CONFIG_ARCH_TEGRA_114_SOC)        += tegra114_speedo.o
 ifeq ($(CONFIG_CPU_IDLE),y)
 obj-$(CONFIG_ARCH_TEGRA_114_SOC)        += cpuidle-tegra114.o
 endif
diff --git a/arch/arm/mach-tegra/board-dt-tegra114.c b/arch/arm/mach-tegra/board-dt-tegra114.c
deleted file mode 100644
index 085d63637b62..000000000000
--- a/arch/arm/mach-tegra/board-dt-tegra114.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * NVIDIA Tegra114 device tree board support
- *
- * Copyright (C) 2013 NVIDIA Corporation
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/of.h>
-#include <linux/of_platform.h>
-#include <linux/clocksource.h>
-
-#include <asm/mach/arch.h>
-
-#include "board.h"
-#include "common.h"
-
-static void __init tegra114_dt_init(void)
-{
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
-
-static const char * const tegra114_dt_board_compat[] = {
-        "nvidia,tegra114",
-        NULL,
-};
-
-DT_MACHINE_START(TEGRA114_DT, "NVIDIA Tegra114 (Flattened Device Tree)")
-        .smp            = smp_ops(tegra_smp_ops),
-        .map_io         = tegra_map_common_io,
-        .init_early     = tegra114_init_early,
-        .init_irq       = tegra_dt_init_irq,
-        .init_time      = clocksource_of_init,
-        .init_machine   = tegra114_dt_init,
-        .init_late      = tegra_init_late,
-        .restart        = tegra_assert_system_reset,
-        .dt_compat      = tegra114_dt_board_compat,
-MACHINE_END
diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c
deleted file mode 100644
index bf68567e549d..000000000000
--- a/arch/arm/mach-tegra/board-dt-tegra30.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * arch/arm/mach-tegra/board-dt-tegra30.c
- *
- * NVIDIA Tegra30 device tree board support
- *
- * Copyright (C) 2011 NVIDIA Corporation
- *
- * Derived from:
- *
- * arch/arm/mach-tegra/board-dt-tegra20.c
- *
- * Copyright (C) 2010 Secret Lab Technologies, Ltd.
- * Copyright (C) 2010 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/clocksource.h>
-#include <linux/kernel.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_fdt.h>
-#include <linux/of_irq.h>
-#include <linux/of_platform.h>
-
-#include <asm/mach/arch.h>
-
-#include "board.h"
-#include "common.h"
-#include "iomap.h"
-
-static void __init tegra30_dt_init(void)
-{
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
-
-static const char *tegra30_dt_board_compat[] = {
-        "nvidia,tegra30",
-        NULL
-};
-
-DT_MACHINE_START(TEGRA30_DT, "NVIDIA Tegra30 (Flattened Device Tree)")
-        .smp            = smp_ops(tegra_smp_ops),
-        .map_io         = tegra_map_common_io,
-        .init_early     = tegra30_init_early,
-        .init_irq       = tegra_dt_init_irq,
-        .init_time      = clocksource_of_init,
-        .init_machine   = tegra30_dt_init,
-        .init_late      = tegra_init_late,
-        .restart        = tegra_assert_system_reset,
-        .dt_compat      = tegra30_dt_board_compat,
-MACHINE_END
diff --git a/arch/arm/mach-tegra/board-harmony-pcie.c b/arch/arm/mach-tegra/board-harmony-pcie.c
index 6d29e6a39540..035b240b9e15 100644
--- a/arch/arm/mach-tegra/board-harmony-pcie.c
+++ b/arch/arm/mach-tegra/board-harmony-pcie.c
@@ -62,7 +62,11 @@ int __init harmony_pcie_init(void)
                 goto err_reg;
         }
 
-        regulator_enable(regulator);
+        err = regulator_enable(regulator);
+        if (err) {
+                pr_err("%s: regulator_enable failed: %d\n", __func__, err);
+                goto err_en;
+        }
 
         err = tegra_pcie_init(true, true);
         if (err) {
@@ -74,6 +78,7 @@ int __init harmony_pcie_init(void)
 
 err_pcie:
         regulator_disable(regulator);
+err_en:
         regulator_put(regulator);
 err_reg:
         gpio_free(en_vdd_1v05);
diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h
index 86851c81a350..60431de585ca 100644
--- a/arch/arm/mach-tegra/board.h
+++ b/arch/arm/mach-tegra/board.h
@@ -26,9 +26,7 @@
 
 void tegra_assert_system_reset(char mode, const char *cmd);
 
-void __init tegra20_init_early(void);
-void __init tegra30_init_early(void);
-void __init tegra114_init_early(void);
+void __init tegra_init_early(void);
 void __init tegra_map_common_io(void);
 void __init tegra_init_irq(void);
 void __init tegra_dt_init_irq(void);
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 5449a3f2977b..eb1f3c8c74cc 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -33,6 +33,7 @@
 #include "common.h"
 #include "fuse.h"
 #include "iomap.h"
+#include "irq.h"
 #include "pmc.h"
 #include "apbio.h"
 #include "sleep.h"
@@ -61,8 +62,10 @@ u32 tegra_uart_config[4] = {
 void __init tegra_dt_init_irq(void)
 {
         tegra_clocks_init();
+        tegra_pmc_init();
         tegra_init_irq();
         irqchip_init();
+        tegra_legacy_irq_syscore_init();
 }
 #endif
 
@@ -94,40 +97,18 @@ static void __init tegra_init_cache(void)
 
 }
 
-static void __init tegra_init_early(void)
+void __init tegra_init_early(void)
 {
         tegra_cpu_reset_handler_init();
         tegra_apb_io_init();
         tegra_init_fuse();
         tegra_init_cache();
-        tegra_pmc_init();
         tegra_powergate_init();
+        tegra_hotplug_init();
 }
 
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
-void __init tegra20_init_early(void)
-{
-        tegra_init_early();
-        tegra20_hotplug_init();
-}
-#endif
-
-#ifdef CONFIG_ARCH_TEGRA_3x_SOC
-void __init tegra30_init_early(void)
-{
-        tegra_init_early();
-        tegra30_hotplug_init();
-}
-#endif
-
-#ifdef CONFIG_ARCH_TEGRA_114_SOC
-void __init tegra114_init_early(void)
-{
-        tegra_init_early();
-}
-#endif
-
 void __init tegra_init_late(void)
 {
+        tegra_init_suspend();
         tegra_powergate_debugfs_init();
 }
diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c
index 825ced4f7a40..8bbbdebed882 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra20.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra20.c
@@ -130,10 +130,6 @@ static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev,
                                            struct cpuidle_driver *drv,
                                            int index)
 {
-        struct cpuidle_state *state = &drv->states[index];
-        u32 cpu_on_time = state->exit_latency;
-        u32 cpu_off_time = state->target_residency - state->exit_latency;
-
         while (tegra20_cpu_is_resettable_soon())
                 cpu_relax();
 
@@ -142,7 +138,7 @@ static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev,
 
         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
 
-        tegra_idle_lp2_last(cpu_on_time, cpu_off_time);
+        tegra_idle_lp2_last();
 
         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
 
diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c
index 8b50cf4ddd6f..c0931c8bb3e5 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra30.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra30.c
@@ -72,10 +72,6 @@ static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev,
                                            struct cpuidle_driver *drv,
                                            int index)
 {
-        struct cpuidle_state *state = &drv->states[index];
-        u32 cpu_on_time = state->exit_latency;
-        u32 cpu_off_time = state->target_residency - state->exit_latency;
-
         /* All CPUs entering LP2 is not working.
          * Don't let CPU0 enter LP2 when any secondary CPU is online.
          */
@@ -86,7 +82,7 @@ static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev,
 
         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
 
-        tegra_idle_lp2_last(cpu_on_time, cpu_off_time);
+        tegra_idle_lp2_last();
 
         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
 
@@ -102,12 +98,8 @@ static bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
 
         smp_wmb();
 
-        save_cpu_arch_register();
-
         cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
 
-        restore_cpu_arch_register();
-
         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
 
         return true;
diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c
index f7db0782a6b6..e035cd284a6e 100644
--- a/arch/arm/mach-tegra/fuse.c
+++ b/arch/arm/mach-tegra/fuse.c
@@ -2,6 +2,7 @@
  * arch/arm/mach-tegra/fuse.c
  *
  * Copyright (C) 2010 Google, Inc.
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
  *
  * Author:
  *      Colin Cross <ccross@android.com>
@@ -137,6 +138,9 @@ void tegra_init_fuse(void)
                 tegra_fuse_spare_bit = TEGRA30_FUSE_SPARE_BIT;
                 tegra_init_speedo_data = &tegra30_init_speedo_data;
                 break;
+        case TEGRA114:
+                tegra_init_speedo_data = &tegra114_init_speedo_data;
+                break;
         default:
                 pr_warn("Tegra: unknown chip id %d\n", tegra_chip_id);
                 tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h
index da78434678c7..aacc00d05980 100644
--- a/arch/arm/mach-tegra/fuse.h
+++ b/arch/arm/mach-tegra/fuse.h
@@ -1,5 +1,6 @@
 /*
  * Copyright (C) 2010 Google, Inc.
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
  *
  * Author:
  *      Colin Cross <ccross@android.com>
@@ -66,4 +67,10 @@ void tegra30_init_speedo_data(void);
 static inline void tegra30_init_speedo_data(void) {}
 #endif
 
+#ifdef CONFIG_ARCH_TEGRA_114_SOC
+void tegra114_init_speedo_data(void);
+#else
+static inline void tegra114_init_speedo_data(void) {}
+#endif
+
 #endif
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
index fd473f2b4c3d..045c16f2dd51 100644
--- a/arch/arm/mach-tegra/headsmp.S
+++ b/arch/arm/mach-tegra/headsmp.S
@@ -7,8 +7,5 @@
 
 ENTRY(tegra_secondary_startup)
         bl      v7_invalidate_l1
-        /* Enable coresight */
-        mov32   r0, 0xC5ACCE55
-        mcr     p14, 0, r0, c7, c12, 6
         b       secondary_startup
 ENDPROC(tegra_secondary_startup)
diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c
index a599f6e36dea..8da9f78475da 100644
--- a/arch/arm/mach-tegra/hotplug.c
+++ b/arch/arm/mach-tegra/hotplug.c
@@ -1,8 +1,7 @@
 /*
- *
  *  Copyright (C) 2002 ARM Ltd.
  *  All Rights Reserved
- *  Copyright (c) 2010, 2012 NVIDIA Corporation. All rights reserved.
+ *  Copyright (c) 2010, 2012-2013, NVIDIA Corporation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -15,6 +14,7 @@
 #include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
 
+#include "fuse.h"
 #include "sleep.h"
 
 static void (*tegra_hotplug_shutdown)(void);
@@ -56,18 +56,13 @@ int tegra_cpu_disable(unsigned int cpu)
         return cpu == 0 ? -EPERM : 0;
 }
 
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
-extern void tegra20_hotplug_shutdown(void);
-void __init tegra20_hotplug_init(void)
+void __init tegra_hotplug_init(void)
 {
-        tegra_hotplug_shutdown = tegra20_hotplug_shutdown;
-}
-#endif
+        if (!IS_ENABLED(CONFIG_HOTPLUG_CPU))
+                return;
 
-#ifdef CONFIG_ARCH_TEGRA_3x_SOC
-extern void tegra30_hotplug_shutdown(void);
-void __init tegra30_hotplug_init(void)
-{
-        tegra_hotplug_shutdown = tegra30_hotplug_shutdown;
+        if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && tegra_chip_id == TEGRA20)
+                tegra_hotplug_shutdown = tegra20_hotplug_shutdown;
+        if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && tegra_chip_id == TEGRA30)
+                tegra_hotplug_shutdown = tegra30_hotplug_shutdown;
 }
-#endif
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 1952e82797cc..0de4eed1493d 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -4,7 +4,7 @@
  * Author:
  *      Colin Cross <ccross@android.com>
  *
- * Copyright (C) 2010, NVIDIA Corporation
+ * Copyright (C) 2010,2013, NVIDIA Corporation
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -23,6 +23,7 @@
 #include <linux/io.h>
 #include <linux/of.h>
 #include <linux/irqchip/arm-gic.h>
+#include <linux/syscore_ops.h>
 
 #include "board.h"
 #include "iomap.h"
@@ -43,6 +44,7 @@
 #define ICTLR_COP_IEP_CLASS     0x3c
 
 #define FIRST_LEGACY_IRQ 32
+#define TEGRA_MAX_NUM_ICTLRS    5
 
 #define SGI_MASK 0xFFFF
 
@@ -56,6 +58,15 @@ static void __iomem *ictlr_reg_base[] = {
         IO_ADDRESS(TEGRA_QUINARY_ICTLR_BASE),
 };
 
+#ifdef CONFIG_PM_SLEEP
+static u32 cop_ier[TEGRA_MAX_NUM_ICTLRS];
+static u32 cop_iep[TEGRA_MAX_NUM_ICTLRS];
+static u32 cpu_ier[TEGRA_MAX_NUM_ICTLRS];
+static u32 cpu_iep[TEGRA_MAX_NUM_ICTLRS];
+
+static u32 ictlr_wake_mask[TEGRA_MAX_NUM_ICTLRS];
+#endif
+
 bool tegra_pending_sgi(void)
 {
         u32 pending_set;
@@ -125,6 +136,87 @@ static int tegra_retrigger(struct irq_data *d)
         return 1;
 }
 
+#ifdef CONFIG_PM_SLEEP
+static int tegra_set_wake(struct irq_data *d, unsigned int enable)
+{
+        u32 irq = d->irq;
+        u32 index, mask;
+
+        if (irq < FIRST_LEGACY_IRQ ||
+                irq >= FIRST_LEGACY_IRQ + num_ictlrs * 32)
+                return -EINVAL;
+
+        index = ((irq - FIRST_LEGACY_IRQ) / 32);
+        mask = BIT((irq - FIRST_LEGACY_IRQ) % 32);
+        if (enable)
+                ictlr_wake_mask[index] |= mask;
+        else
+                ictlr_wake_mask[index] &= ~mask;
+
+        return 0;
+}
+
+static int tegra_legacy_irq_suspend(void)
+{
+        unsigned long flags;
+        int i;
+
+        local_irq_save(flags);
+        for (i = 0; i < num_ictlrs; i++) {
+                void __iomem *ictlr = ictlr_reg_base[i];
+                /* Save interrupt state */
+                cpu_ier[i] = readl_relaxed(ictlr + ICTLR_CPU_IER);
+                cpu_iep[i] = readl_relaxed(ictlr + ICTLR_CPU_IEP_CLASS);
+                cop_ier[i] = readl_relaxed(ictlr + ICTLR_COP_IER);
+                cop_iep[i] = readl_relaxed(ictlr + ICTLR_COP_IEP_CLASS);
+
+                /* Disable COP interrupts */
+                writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
+
+                /* Disable CPU interrupts */
+                writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR);
+
+                /* Enable the wakeup sources of ictlr */
+                writel_relaxed(ictlr_wake_mask[i], ictlr + ICTLR_CPU_IER_SET);
+        }
+        local_irq_restore(flags);
+
+        return 0;
+}
+
+static void tegra_legacy_irq_resume(void)
+{
+        unsigned long flags;
+        int i;
+
+        local_irq_save(flags);
+        for (i = 0; i < num_ictlrs; i++) {
+                void __iomem *ictlr = ictlr_reg_base[i];
+                writel_relaxed(cpu_iep[i], ictlr + ICTLR_CPU_IEP_CLASS);
+                writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR);
+                writel_relaxed(cpu_ier[i], ictlr + ICTLR_CPU_IER_SET);
+                writel_relaxed(cop_iep[i], ictlr + ICTLR_COP_IEP_CLASS);
+                writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
+                writel_relaxed(cop_ier[i], ictlr + ICTLR_COP_IER_SET);
+        }
+        local_irq_restore(flags);
+}
+
+static struct syscore_ops tegra_legacy_irq_syscore_ops = {
+        .suspend = tegra_legacy_irq_suspend,
+        .resume = tegra_legacy_irq_resume,
+};
+
+int tegra_legacy_irq_syscore_init(void)
+{
+        register_syscore_ops(&tegra_legacy_irq_syscore_ops);
+
+        return 0;
+}
+#else
+#define tegra_set_wake NULL
+#endif
+
 void __init tegra_init_irq(void)
 {
         int i;
@@ -150,6 +242,8 @@ void __init tegra_init_irq(void)
         gic_arch_extn.irq_mask = tegra_mask;
         gic_arch_extn.irq_unmask = tegra_unmask;
         gic_arch_extn.irq_retrigger = tegra_retrigger;
+        gic_arch_extn.irq_set_wake = tegra_set_wake;
+        gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND;
 
         /*
          * Check if there is a devicetree present, since the GIC will be
diff --git a/arch/arm/mach-tegra/irq.h b/arch/arm/mach-tegra/irq.h
index 5142649bba05..bc05ce5613fb 100644
--- a/arch/arm/mach-tegra/irq.h
+++ b/arch/arm/mach-tegra/irq.h
@@ -19,4 +19,10 @@
 
 bool tegra_pending_sgi(void);
 
+#ifdef CONFIG_PM_SLEEP
+int tegra_legacy_irq_syscore_init(void);
+#else
+static inline int tegra_legacy_irq_syscore_init(void) { return 0; }
+#endif
+
 #endif
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 2c6b3d55213b..516aab28fe34 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -26,22 +26,16 @@
 #include <asm/smp_scu.h>
 #include <asm/smp_plat.h>
 
-#include <mach/powergate.h>
-
 #include "fuse.h"
 #include "flowctrl.h"
 #include "reset.h"
+#include "pmc.h"
 
 #include "common.h"
 #include "iomap.h"
 
-extern void tegra_secondary_startup(void);
-
 static cpumask_t tegra_cpu_init_mask;
 
-#define EVP_CPU_RESET_VECTOR \
-        (IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100)
-
 static void __cpuinit tegra_secondary_init(unsigned int cpu)
 {
         /*
@@ -54,25 +48,43 @@ static void __cpuinit tegra_secondary_init(unsigned int cpu)
         cpumask_set_cpu(cpu, &tegra_cpu_init_mask);
 }
 
-static int tegra20_power_up_cpu(unsigned int cpu)
+
+static int tegra20_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
-        /* Enable the CPU clock. */
-        tegra_enable_cpu_clock(cpu);
+        cpu = cpu_logical_map(cpu);
+
+        /*
+         * Force the CPU into reset. The CPU must remain in reset when
+         * the flow controller state is cleared (which will cause the
+         * flow controller to stop driving reset if the CPU has been
+         * power-gated via the flow controller). This will have no
+         * effect on first boot of the CPU since it should already be
+         * in reset.
+         */
+        tegra_put_cpu_in_reset(cpu);
 
-        /* Clear flow controller CSR. */
-        flowctrl_write_cpu_csr(cpu, 0);
+        /*
+         * Unhalt the CPU. If the flow controller was used to
+         * power-gate the CPU this will cause the flow controller to
+         * stop driving reset. The CPU will remain in reset because the
+         * clock and reset block is now driving reset.
+         */
+        flowctrl_write_cpu_halt(cpu, 0);
 
+        tegra_enable_cpu_clock(cpu);
+        flowctrl_write_cpu_csr(cpu, 0); /* Clear flow controller CSR. */
+        tegra_cpu_out_of_reset(cpu);
         return 0;
 }
 
-static int tegra30_power_up_cpu(unsigned int cpu)
+static int tegra30_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
-        int ret, pwrgateid;
+        int ret;
         unsigned long timeout;
 
-        pwrgateid = tegra_cpu_powergate_id(cpu);
-        if (pwrgateid < 0)
-                return pwrgateid;
+        cpu = cpu_logical_map(cpu);
+        tegra_put_cpu_in_reset(cpu);
+        flowctrl_write_cpu_halt(cpu, 0);
 
         /*
          * The power up sequence of cold boot CPU and warm boot CPU
@@ -85,13 +97,13 @@ static int tegra30_power_up_cpu(unsigned int cpu)
          * the IO clamps.
          * For cold boot CPU, do not wait. After the cold boot CPU be
          * booted, it will run to tegra_secondary_init() and set
-         * tegra_cpu_init_mask which influences what tegra30_power_up_cpu()
+         * tegra_cpu_init_mask which influences what tegra30_boot_secondary()
          * next time around.
          */
         if (cpumask_test_cpu(cpu, &tegra_cpu_init_mask)) {
                 timeout = jiffies + msecs_to_jiffies(50);
                 do {
-                        if (!tegra_powergate_is_powered(pwrgateid))
+                        if (tegra_pmc_cpu_is_powered(cpu))
                                 goto remove_clamps;
                         udelay(10);
                 } while (time_before(jiffies, timeout));
@@ -103,14 +115,14 @@ static int tegra30_power_up_cpu(unsigned int cpu)
          * be un-gated by un-toggling the power gate register
          * manually.
          */
-        if (!tegra_powergate_is_powered(pwrgateid)) {
-                ret = tegra_powergate_power_on(pwrgateid);
+        if (!tegra_pmc_cpu_is_powered(cpu)) {
+                ret = tegra_pmc_cpu_power_on(cpu);
                 if (ret)
                         return ret;
 
                 /* Wait for the power to come up. */
                 timeout = jiffies + msecs_to_jiffies(100);
-                while (tegra_powergate_is_powered(pwrgateid)) {
+                while (tegra_pmc_cpu_is_powered(cpu)) {
                         if (time_after(jiffies, timeout))
                                 return -ETIMEDOUT;
                         udelay(10);
@@ -123,57 +135,34 @@ remove_clamps:
         udelay(10);
 
         /* Remove I/O clamps. */
-        ret = tegra_powergate_remove_clamping(pwrgateid);
-        udelay(10);
+        ret = tegra_pmc_cpu_remove_clamping(cpu);
+        if (ret)
+                return ret;
 
-        /* Clear flow controller CSR. */
-        flowctrl_write_cpu_csr(cpu, 0);
+        udelay(10);
 
+        flowctrl_write_cpu_csr(cpu, 0); /* Clear flow controller CSR. */
+        tegra_cpu_out_of_reset(cpu);
         return 0;
 }
 
-static int __cpuinit tegra_boot_secondary(unsigned int cpu, struct task_struct *idle)
+static int tegra114_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
-        int status;
-
         cpu = cpu_logical_map(cpu);
+        return tegra_pmc_cpu_power_on(cpu);
+}
 
-        /*
-         * Force the CPU into reset. The CPU must remain in reset when the
-         * flow controller state is cleared (which will cause the flow
-         * controller to stop driving reset if the CPU has been power-gated
-         * via the flow controller). This will have no effect on first boot
-         * of the CPU since it should already be in reset.
-         */
-        tegra_put_cpu_in_reset(cpu);
-
-        /*
-         * Unhalt the CPU. If the flow controller was used to power-gate the
-         * CPU this will cause the flow controller to stop driving reset.
-         * The CPU will remain in reset because the clock and reset block
-         * is now driving reset.
-         */
-        flowctrl_write_cpu_halt(cpu, 0);
-
-        switch (tegra_chip_id) {
-        case TEGRA20:
-                status = tegra20_power_up_cpu(cpu);
-                break;
-        case TEGRA30:
-                status = tegra30_power_up_cpu(cpu);
-                break;
-        default:
-                status = -EINVAL;
-                break;
-        }
-
-        if (status)
-                goto done;
-
-        /* Take the CPU out of reset. */
-        tegra_cpu_out_of_reset(cpu);
-done:
-        return status;
+static int __cpuinit tegra_boot_secondary(unsigned int cpu,
+                                          struct task_struct *idle)
+{
+        if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && tegra_chip_id == TEGRA20)
+                return tegra20_boot_secondary(cpu, idle);
+        if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && tegra_chip_id == TEGRA30)
+                return tegra30_boot_secondary(cpu, idle);
+        if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) && tegra_chip_id == TEGRA114)
+                return tegra114_boot_secondary(cpu, idle);
+
+        return -EINVAL;
 }
 
 static void __init tegra_smp_prepare_cpus(unsigned int max_cpus)
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index 523604de666f..d0b7400e4606 100644
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -22,7 +22,7 @@
 #include <linux/cpumask.h>
 #include <linux/delay.h>
 #include <linux/cpu_pm.h>
-#include <linux/clk.h>
+#include <linux/suspend.h>
 #include <linux/err.h>
 #include <linux/clk/tegra.h>
 
@@ -37,67 +37,13 @@
 #include "reset.h"
 #include "flowctrl.h"
 #include "fuse.h"
+#include "pmc.h"
 #include "sleep.h"
 
-#define TEGRA_POWER_CPU_PWRREQ_OE       (1 << 16)  /* CPU pwr req enable */
-
-#define PMC_CTRL                0x0
-#define PMC_CPUPWRGOOD_TIMER    0xc8
-#define PMC_CPUPWROFF_TIMER     0xcc
-
 #ifdef CONFIG_PM_SLEEP
-static unsigned int g_diag_reg;
 static DEFINE_SPINLOCK(tegra_lp2_lock);
-static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
-static struct clk *tegra_pclk;
 void (*tegra_tear_down_cpu)(void);
 
-void save_cpu_arch_register(void)
-{
-        /* read diagnostic register */
-        asm("mrc p15, 0, %0, c15, c0, 1" : "=r"(g_diag_reg) : : "cc");
-        return;
-}
-
-void restore_cpu_arch_register(void)
-{
-        /* write diagnostic register */
-        asm("mcr p15, 0, %0, c15, c0, 1" : : "r"(g_diag_reg) : "cc");
-        return;
-}
-
-static void set_power_timers(unsigned long us_on, unsigned long us_off)
-{
-        unsigned long long ticks;
-        unsigned long long pclk;
-        unsigned long rate;
-        static unsigned long tegra_last_pclk;
-
-        if (tegra_pclk == NULL) {
-                tegra_pclk = clk_get_sys(NULL, "pclk");
-                WARN_ON(IS_ERR(tegra_pclk));
-        }
-
-        rate = clk_get_rate(tegra_pclk);
-
-        if (WARN_ON_ONCE(rate <= 0))
-                pclk = 100000000;
-        else
-                pclk = rate;
-
-        if ((rate != tegra_last_pclk)) {
-                ticks = (us_on * pclk) + 999999ull;
-                do_div(ticks, 1000000);
-                writel((unsigned long)ticks, pmc + PMC_CPUPWRGOOD_TIMER);
-
-                ticks = (us_off * pclk) + 999999ull;
-                do_div(ticks, 1000000);
-                writel((unsigned long)ticks, pmc + PMC_CPUPWROFF_TIMER);
-                wmb();
-        }
-        tegra_last_pclk = pclk;
-}
-
 /*
  * restore_cpu_complex
  *
@@ -119,8 +65,6 @@ static void restore_cpu_complex(void)
         tegra_cpu_clock_resume();
 
         flowctrl_cpu_suspend_exit(cpu);
-
-        restore_cpu_arch_register();
 }
 
 /*
@@ -145,8 +89,6 @@ static void suspend_cpu_complex(void)
         tegra_cpu_clock_suspend();
 
         flowctrl_cpu_suspend_enter(cpu);
-
-        save_cpu_arch_register();
 }
 
 void tegra_clear_cpu_in_lp2(int phy_cpu_id)
@@ -197,16 +139,9 @@ static int tegra_sleep_cpu(unsigned long v2p)
         return 0;
 }
 
-void tegra_idle_lp2_last(u32 cpu_on_time, u32 cpu_off_time)
+void tegra_idle_lp2_last(void)
 {
-        u32 mode;
-
-        /* Only the last cpu down does the final suspend steps */
-        mode = readl(pmc + PMC_CTRL);
-        mode |= TEGRA_POWER_CPU_PWRREQ_OE;
-        writel(mode, pmc + PMC_CTRL);
-
-        set_power_timers(cpu_on_time, cpu_off_time);
+        tegra_pmc_pm_set(TEGRA_SUSPEND_LP2);
 
         cpu_cluster_pm_enter();
         suspend_cpu_complex();
@@ -216,4 +151,81 @@ void tegra_idle_lp2_last(u32 cpu_on_time, u32 cpu_off_time)
         restore_cpu_complex();
         cpu_cluster_pm_exit();
 }
+
+enum tegra_suspend_mode tegra_pm_validate_suspend_mode(
+                                enum tegra_suspend_mode mode)
+{
+        /* Tegra114 didn't support any suspending mode yet. */
+        if (tegra_chip_id == TEGRA114)
+                return TEGRA_SUSPEND_NONE;
+
+        /*
+         * The Tegra devices only support suspending to LP2 currently.
+         */
+        if (mode > TEGRA_SUSPEND_LP2)
+                return TEGRA_SUSPEND_LP2;
+
+        return mode;
+}
+
+static const char *lp_state[TEGRA_MAX_SUSPEND_MODE] = {
+        [TEGRA_SUSPEND_NONE] = "none",
+        [TEGRA_SUSPEND_LP2] = "LP2",
+        [TEGRA_SUSPEND_LP1] = "LP1",
+        [TEGRA_SUSPEND_LP0] = "LP0",
+};
+
+static int __cpuinit tegra_suspend_enter(suspend_state_t state)
+{
+        enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode();
+
+        if (WARN_ON(mode < TEGRA_SUSPEND_NONE ||
+                    mode >= TEGRA_MAX_SUSPEND_MODE))
+                return -EINVAL;
+
+        pr_info("Entering suspend state %s\n", lp_state[mode]);
+
+        tegra_pmc_pm_set(mode);
+
+        local_fiq_disable();
+
+        suspend_cpu_complex();
+        switch (mode) {
+        case TEGRA_SUSPEND_LP2:
+                tegra_set_cpu_in_lp2(0);
+                break;
+        default:
+                break;
+        }
+
+        cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu);
+
+        switch (mode) {
+        case TEGRA_SUSPEND_LP2:
+                tegra_clear_cpu_in_lp2(0);
+                break;
+        default:
+                break;
+        }
+        restore_cpu_complex();
+
+        local_fiq_enable();
+
+        return 0;
+}
+
+static const struct platform_suspend_ops tegra_suspend_ops = {
+        .valid          = suspend_valid_only_mem,
+        .enter          = tegra_suspend_enter,
+};
+
+void __init tegra_init_suspend(void)
+{
+        if (tegra_pmc_get_suspend_mode() == TEGRA_SUSPEND_NONE)
+                return;
+
+        tegra_pmc_suspend_init();
+
+        suspend_set_ops(&tegra_suspend_ops);
+}
 #endif
diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h
index 787335cc964c..9d2d038bf12e 100644
--- a/arch/arm/mach-tegra/pm.h
+++ b/arch/arm/mach-tegra/pm.h
@@ -21,6 +21,8 @@
 #ifndef _MACH_TEGRA_PM_H_
 #define _MACH_TEGRA_PM_H_
 
+#include "pmc.h"
+
 extern unsigned long l2x0_saved_regs_addr;
 
 void save_cpu_arch_register(void);
@@ -29,7 +31,20 @@ void restore_cpu_arch_register(void);
 void tegra_clear_cpu_in_lp2(int phy_cpu_id);
 bool tegra_set_cpu_in_lp2(int phy_cpu_id);
 
-void tegra_idle_lp2_last(u32 cpu_on_time, u32 cpu_off_time);
+void tegra_idle_lp2_last(void);
 extern void (*tegra_tear_down_cpu)(void);
 
+#ifdef CONFIG_PM_SLEEP
+enum tegra_suspend_mode tegra_pm_validate_suspend_mode(
+                                enum tegra_suspend_mode mode);
+void tegra_init_suspend(void);
+#else
+enum tegra_suspend_mode tegra_pm_validate_suspend_mode(
+                                enum tegra_suspend_mode mode)
+{
+        return TEGRA_SUSPEND_NONE;
+}
+static inline void tegra_init_suspend(void) {}
+#endif
+
 #endif /* _MACH_TEGRA_PM_H_ */
diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c
index d4fdb5fcec20..32360e540ce6 100644
--- a/arch/arm/mach-tegra/pmc.c
+++ b/arch/arm/mach-tegra/pmc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
+ * Copyright (C) 2012,2013 NVIDIA CORPORATION. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -16,59 +16,313 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/of.h>
+#include <linux/of_address.h>
 
-#include "iomap.h"
+#include "fuse.h"
+#include "pm.h"
+#include "pmc.h"
+#include "sleep.h"
 
-#define PMC_CTRL                0x0
-#define PMC_CTRL_INTR_LOW       (1 << 17)
+#define TEGRA_POWER_EFFECT_LP0          (1 << 14)  /* LP0 when CPU pwr gated */
+#define TEGRA_POWER_CPU_PWRREQ_POLARITY (1 << 15)  /* CPU pwr req polarity */
+#define TEGRA_POWER_CPU_PWRREQ_OE       (1 << 16)  /* CPU pwr req enable */
+
+#define PMC_CTRL                        0x0
+#define PMC_CTRL_INTR_LOW               (1 << 17)
+#define PMC_PWRGATE_TOGGLE              0x30
+#define PMC_PWRGATE_TOGGLE_START        (1 << 8)
+#define PMC_REMOVE_CLAMPING             0x34
+#define PMC_PWRGATE_STATUS              0x38
+
+#define PMC_CPUPWRGOOD_TIMER    0xc8
+#define PMC_CPUPWROFF_TIMER     0xcc
+
+#define TEGRA_POWERGATE_PCIE    3
+#define TEGRA_POWERGATE_VDEC    4
+#define TEGRA_POWERGATE_CPU1    9
+#define TEGRA_POWERGATE_CPU2    10
+#define TEGRA_POWERGATE_CPU3    11
+
+static u8 tegra_cpu_domains[] = {
+        0xFF,                   /* not available for CPU0 */
+        TEGRA_POWERGATE_CPU1,
+        TEGRA_POWERGATE_CPU2,
+        TEGRA_POWERGATE_CPU3,
+};
+static DEFINE_SPINLOCK(tegra_powergate_lock);
+
+static void __iomem *tegra_pmc_base;
+static bool tegra_pmc_invert_interrupt;
+static struct clk *tegra_pclk;
+
+struct pmc_pm_data {
+        u32 cpu_good_time;      /* CPU power good time in uS */
+        u32 cpu_off_time;       /* CPU power off time in uS */
+        u32 core_osc_time;      /* Core power good osc time in uS */
+        u32 core_pmu_time;      /* Core power good pmu time in uS */
+        u32 core_off_time;      /* Core power off time in uS */
+        bool corereq_high;      /* Core power request active-high */
+        bool sysclkreq_high;    /* System clock request active-high */
+        bool combined_req;      /* Combined pwr req for CPU & Core */
+        bool cpu_pwr_good_en;   /* CPU power good signal is enabled */
+        u32 lp0_vec_phy_addr;   /* The phy addr of LP0 warm boot code */
+        u32 lp0_vec_size;       /* The size of LP0 warm boot code */
+        enum tegra_suspend_mode suspend_mode;
+};
+static struct pmc_pm_data pmc_pm_data;
 
 static inline u32 tegra_pmc_readl(u32 reg)
 {
-        return readl(IO_ADDRESS(TEGRA_PMC_BASE + reg));
+        return readl(tegra_pmc_base + reg);
 }
 
 static inline void tegra_pmc_writel(u32 val, u32 reg)
 {
-        writel(val, IO_ADDRESS(TEGRA_PMC_BASE + reg));
+        writel(val, tegra_pmc_base + reg);
+}
+
+static int tegra_pmc_get_cpu_powerdomain_id(int cpuid)
+{
+        if (cpuid <= 0 || cpuid >= num_possible_cpus())
+                return -EINVAL;
+        return tegra_cpu_domains[cpuid];
+}
+
+static bool tegra_pmc_powergate_is_powered(int id)
+{
+        return (tegra_pmc_readl(PMC_PWRGATE_STATUS) >> id) & 1;
+}
+
+static int tegra_pmc_powergate_set(int id, bool new_state)
+{
+        bool old_state;
+        unsigned long flags;
+
+        spin_lock_irqsave(&tegra_powergate_lock, flags);
+
+        old_state = tegra_pmc_powergate_is_powered(id);
+        WARN_ON(old_state == new_state);
+
+        tegra_pmc_writel(PMC_PWRGATE_TOGGLE_START | id, PMC_PWRGATE_TOGGLE);
+
+        spin_unlock_irqrestore(&tegra_powergate_lock, flags);
+
+        return 0;
+}
+
+static int tegra_pmc_powergate_remove_clamping(int id)
+{
+        u32 mask;
+
+        /*
+         * Tegra has a bug where PCIE and VDE clamping masks are
+         * swapped relatively to the partition ids.
+         */
+        if (id ==  TEGRA_POWERGATE_VDEC)
+                mask = (1 << TEGRA_POWERGATE_PCIE);
+        else if (id == TEGRA_POWERGATE_PCIE)
+                mask = (1 << TEGRA_POWERGATE_VDEC);
+        else
+                mask = (1 << id);
+
+        tegra_pmc_writel(mask, PMC_REMOVE_CLAMPING);
+
+        return 0;
+}
+
+bool tegra_pmc_cpu_is_powered(int cpuid)
+{
+        int id;
+
+        id = tegra_pmc_get_cpu_powerdomain_id(cpuid);
+        if (id < 0)
+                return false;
+        return tegra_pmc_powergate_is_powered(id);
 }
 
-#ifdef CONFIG_OF
+int tegra_pmc_cpu_power_on(int cpuid)
+{
+        int id;
+
+        id = tegra_pmc_get_cpu_powerdomain_id(cpuid);
+        if (id < 0)
+                return id;
+        return tegra_pmc_powergate_set(id, true);
+}
+
+int tegra_pmc_cpu_remove_clamping(int cpuid)
+{
+        int id;
+
+        id = tegra_pmc_get_cpu_powerdomain_id(cpuid);
+        if (id < 0)
+                return id;
+        return tegra_pmc_powergate_remove_clamping(id);
+}
+
+#ifdef CONFIG_PM_SLEEP
+static void set_power_timers(u32 us_on, u32 us_off, unsigned long rate)
+{
+        unsigned long long ticks;
+        unsigned long long pclk;
+        static unsigned long tegra_last_pclk;
+
+        if (WARN_ON_ONCE(rate <= 0))
+                pclk = 100000000;
+        else
+                pclk = rate;
+
+        if ((rate != tegra_last_pclk)) {
+                ticks = (us_on * pclk) + 999999ull;
+                do_div(ticks, 1000000);
+                tegra_pmc_writel((unsigned long)ticks, PMC_CPUPWRGOOD_TIMER);
+
+                ticks = (us_off * pclk) + 999999ull;
+                do_div(ticks, 1000000);
+                tegra_pmc_writel((unsigned long)ticks, PMC_CPUPWROFF_TIMER);
+                wmb();
+        }
+        tegra_last_pclk = pclk;
+}
+
+enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
+{
+        return pmc_pm_data.suspend_mode;
+}
+
+void tegra_pmc_pm_set(enum tegra_suspend_mode mode)
+{
+        u32 reg;
+        unsigned long rate = 0;
+
+        reg = tegra_pmc_readl(PMC_CTRL);
+        reg |= TEGRA_POWER_CPU_PWRREQ_OE;
+        reg &= ~TEGRA_POWER_EFFECT_LP0;
+
+        switch (mode) {
+        case TEGRA_SUSPEND_LP2:
+                rate = clk_get_rate(tegra_pclk);
+                break;
+        default:
+                break;
+        }
+
+        set_power_timers(pmc_pm_data.cpu_good_time, pmc_pm_data.cpu_off_time,
+                         rate);
+
+        tegra_pmc_writel(reg, PMC_CTRL);
+}
+
+void tegra_pmc_suspend_init(void)
+{
+        u32 reg;
+
+        /* Always enable CPU power request */
+        reg = tegra_pmc_readl(PMC_CTRL);
+        reg |= TEGRA_POWER_CPU_PWRREQ_OE;
+        tegra_pmc_writel(reg, PMC_CTRL);
+}
+#endif
+
 static const struct of_device_id matches[] __initconst = {
+        { .compatible = "nvidia,tegra114-pmc" },
+        { .compatible = "nvidia,tegra30-pmc" },
         { .compatible = "nvidia,tegra20-pmc" },
         { }
 };
-#endif
 
-void __init tegra_pmc_init(void)
+static void tegra_pmc_parse_dt(void)
 {
-        /*
-         * For now, Harmony is the only board that uses the PMC, and it wants
-         * the signal inverted. Seaboard would too if it used the PMC.
-         * Hopefully by the time other boards want to use the PMC, everything
-         * will be device-tree, or they also want it inverted.
-         */
-        bool invert_interrupt = true;
-        u32 val;
+        struct device_node *np;
+        u32 prop;
+        enum tegra_suspend_mode suspend_mode;
+        u32 core_good_time[2] = {0, 0};
+        u32 lp0_vec[2] = {0, 0};
 
-#ifdef CONFIG_OF
-        if (of_have_populated_dt()) {
-                struct device_node *np;
+        np = of_find_matching_node(NULL, matches);
+        BUG_ON(!np);
 
-                invert_interrupt = false;
+        tegra_pmc_base = of_iomap(np, 0);
 
-                np = of_find_matching_node(NULL, matches);
-                if (np) {
-                        if (of_find_property(np, "nvidia,invert-interrupt",
-                                                NULL))
-                                invert_interrupt = true;
+        tegra_pmc_invert_interrupt = of_property_read_bool(np,
+                                     "nvidia,invert-interrupt");
+        tegra_pclk = of_clk_get_by_name(np, "pclk");
+        WARN_ON(IS_ERR(tegra_pclk));
+
+        /* Grabbing the power management configurations */
+        if (of_property_read_u32(np, "nvidia,suspend-mode", &prop)) {
+                suspend_mode = TEGRA_SUSPEND_NONE;
+        } else {
+                switch (prop) {
+                case 0:
+                        suspend_mode = TEGRA_SUSPEND_LP0;
+                        break;
+                case 1:
+                        suspend_mode = TEGRA_SUSPEND_LP1;
+                        break;
+                case 2:
+                        suspend_mode = TEGRA_SUSPEND_LP2;
+                        break;
+                default:
+                        suspend_mode = TEGRA_SUSPEND_NONE;
+                        break;
                 }
         }
-#endif
+        suspend_mode = tegra_pm_validate_suspend_mode(suspend_mode);
+
+        if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &prop))
+                suspend_mode = TEGRA_SUSPEND_NONE;
+        pmc_pm_data.cpu_good_time = prop;
+
+        if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &prop))
+                suspend_mode = TEGRA_SUSPEND_NONE;
+        pmc_pm_data.cpu_off_time = prop;
+
+        if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time",
+                        core_good_time, ARRAY_SIZE(core_good_time)))
+                suspend_mode = TEGRA_SUSPEND_NONE;
+        pmc_pm_data.core_osc_time = core_good_time[0];
+        pmc_pm_data.core_pmu_time = core_good_time[1];
+
+        if (of_property_read_u32(np, "nvidia,core-pwr-off-time",
+                                 &prop))
+                suspend_mode = TEGRA_SUSPEND_NONE;
+        pmc_pm_data.core_off_time = prop;
+
+        pmc_pm_data.corereq_high = of_property_read_bool(np,
+                                "nvidia,core-power-req-active-high");
+
+        pmc_pm_data.sysclkreq_high = of_property_read_bool(np,
+                                "nvidia,sys-clock-req-active-high");
+
+        pmc_pm_data.combined_req = of_property_read_bool(np,
+                                "nvidia,combined-power-req");
+
+        pmc_pm_data.cpu_pwr_good_en = of_property_read_bool(np,
+                                "nvidia,cpu-pwr-good-en");
+
+        if (of_property_read_u32_array(np, "nvidia,lp0-vec", lp0_vec,
+                                       ARRAY_SIZE(lp0_vec)))
+                if (suspend_mode == TEGRA_SUSPEND_LP0)
+                        suspend_mode = TEGRA_SUSPEND_LP1;
+
+        pmc_pm_data.lp0_vec_phy_addr = lp0_vec[0];
+        pmc_pm_data.lp0_vec_size = lp0_vec[1];
+
+        pmc_pm_data.suspend_mode = suspend_mode;
+}
+
+void __init tegra_pmc_init(void)
+{
+        u32 val;
+
+        tegra_pmc_parse_dt();
 
         val = tegra_pmc_readl(PMC_CTRL);
-        if (invert_interrupt)
+        if (tegra_pmc_invert_interrupt)
                 val |= PMC_CTRL_INTR_LOW;
         else
                 val &= ~PMC_CTRL_INTR_LOW;
diff --git a/arch/arm/mach-tegra/pmc.h b/arch/arm/mach-tegra/pmc.h
index 8995ee4a8768..e1c2df272f7d 100644
--- a/arch/arm/mach-tegra/pmc.h
+++ b/arch/arm/mach-tegra/pmc.h
@@ -18,6 +18,24 @@
 #ifndef __MACH_TEGRA_PMC_H
 #define __MACH_TEGRA_PMC_H
 
+enum tegra_suspend_mode {
+        TEGRA_SUSPEND_NONE = 0,
+        TEGRA_SUSPEND_LP2,      /* CPU voltage off */
+        TEGRA_SUSPEND_LP1,      /* CPU voltage off, DRAM self-refresh */
+        TEGRA_SUSPEND_LP0,      /* CPU + core voltage off, DRAM self-refresh */
+        TEGRA_MAX_SUSPEND_MODE,
+};
+
+#ifdef CONFIG_PM_SLEEP
+enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void);
+void tegra_pmc_pm_set(enum tegra_suspend_mode mode);
+void tegra_pmc_suspend_init(void);
+#endif
+
+bool tegra_pmc_cpu_is_powered(int cpuid);
+int tegra_pmc_cpu_power_on(int cpuid);
+int tegra_pmc_cpu_remove_clamping(int cpuid);
+
 void tegra_pmc_init(void);
 
 #endif
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S
index 54382ceade4a..1676aba5e7b8 100644
--- a/arch/arm/mach-tegra/reset-handler.S
+++ b/arch/arm/mach-tegra/reset-handler.S
@@ -41,9 +41,6 @@
  */
 ENTRY(tegra_resume)
         bl      v7_invalidate_l1
-        /* Enable coresight */
-        mov32   r0, 0xC5ACCE55
-        mcr     p14, 0, r0, c7, c12, 6
 
         cpu_id  r0
         cmp     r0, #0                          @ CPU0?
@@ -99,6 +96,8 @@ ENTRY(__tegra_cpu_reset_handler_start)
  *
  * Register usage within the reset handler:
  *
+ *      Others: scratch
+ *      R6  = SoC ID << 8
  *      R7  = CPU present (to the OS) mask
  *      R8  = CPU in LP1 state mask
  *      R9  = CPU in LP2 state mask
@@ -114,6 +113,40 @@ ENTRY(__tegra_cpu_reset_handler_start)
 ENTRY(__tegra_cpu_reset_handler)
 
         cpsid   aif, 0x13                       @ SVC mode, interrupts disabled
+
+        mov32   r6, TEGRA_APB_MISC_BASE
+        ldr     r6, [r6, #APB_MISC_GP_HIDREV]
+        and     r6, r6, #0xff00
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+t20_check:
+        cmp     r6, #(0x20 << 8)
+        bne     after_t20_check
+t20_errata:
+        # Tegra20 is a Cortex-A9 r1p1
+        mrc     p15, 0, r0, c1, c0, 0   @ read system control register
+        orr     r0, r0, #1 << 14        @ erratum 716044
+        mcr     p15, 0, r0, c1, c0, 0   @ write system control register
+        mrc     p15, 0, r0, c15, c0, 1  @ read diagnostic register
+        orr     r0, r0, #1 << 4         @ erratum 742230
+        orr     r0, r0, #1 << 11        @ erratum 751472
+        mcr     p15, 0, r0, c15, c0, 1  @ write diagnostic register
+        b       after_errata
+after_t20_check:
+#endif
+#ifdef CONFIG_ARCH_TEGRA_3x_SOC
+t30_check:
+        cmp     r6, #(0x30 << 8)
+        bne     after_t30_check
+t30_errata:
+        # Tegra30 is a Cortex-A9 r2p9
+        mrc     p15, 0, r0, c15, c0, 1  @ read diagnostic register
+        orr     r0, r0, #1 << 6         @ erratum 743622
+        orr     r0, r0, #1 << 11        @ erratum 751472
+        mcr     p15, 0, r0, c15, c0, 1  @ write diagnostic register
+        b       after_errata
+after_t30_check:
+#endif
+after_errata:
         mrc     p15, 0, r10, c0, c0, 5          @ MPIDR
         and     r10, r10, #0x3                  @ R10 = CPU number
         mov     r11, #1
@@ -129,16 +162,13 @@ ENTRY(__tegra_cpu_reset_handler)
 
 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
         /* Are we on Tegra20? */
-        mov32   r6, TEGRA_APB_MISC_BASE
-        ldr     r0, [r6, #APB_MISC_GP_HIDREV]
-        and     r0, r0, #0xff00
-        cmp     r0, #(0x20 << 8)
+        cmp     r6, #(0x20 << 8)
         bne     1f
         /* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */
-        mov32   r6, TEGRA_PMC_BASE
+        mov32   r5, TEGRA_PMC_BASE
         mov     r0, #0
         cmp     r10, #0
-        strne   r0, [r6, #PMC_SCRATCH41]
+        strne   r0, [r5, #PMC_SCRATCH41]
 1:
 #endif
 
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index 4ffae541726e..970ebd5138b9 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
+ * Copyright (c) 2010-2013, NVIDIA Corporation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -124,11 +124,11 @@ int tegra_sleep_cpu_finish(unsigned long);
 void tegra_disable_clean_inv_dcache(void);
 
 #ifdef CONFIG_HOTPLUG_CPU
-void tegra20_hotplug_init(void);
-void tegra30_hotplug_init(void);
+void tegra20_hotplug_shutdown(void);
+void tegra30_hotplug_shutdown(void);
+void tegra_hotplug_init(void);
 #else
-static inline void tegra20_hotplug_init(void) {}
-static inline void tegra30_hotplug_init(void) {}
+static inline void tegra_hotplug_init(void) {}
 #endif
 
 void tegra20_cpu_shutdown(int cpu);
diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/tegra.c
index a0edf2510280..61749e2d8111 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/tegra.c
@@ -1,6 +1,7 @@
 /*
- * nVidia Tegra device tree board support
+ * NVIDIA Tegra SoC device tree board support
  *
+ * Copyright (C) 2011, 2013, NVIDIA Corporation
  * Copyright (C) 2010 Secret Lab Technologies, Ltd.
  * Copyright (C) 2010 Google, Inc.
  *
@@ -32,7 +33,10 @@
 #include <linux/io.h>
 #include <linux/i2c.h>
 #include <linux/i2c-tegra.h>
+#include <linux/slab.h>
+#include <linux/sys_soc.h>
 #include <linux/usb/tegra_usb_phy.h>
+#include <linux/clk/tegra.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -41,6 +45,7 @@
 
 #include "board.h"
 #include "common.h"
+#include "fuse.h"
 #include "iomap.h"
 
 static struct tegra_ehci_platform_data tegra_ehci1_pdata = {
@@ -79,12 +84,38 @@ static struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
 
 static void __init tegra_dt_init(void)
 {
+        struct soc_device_attribute *soc_dev_attr;
+        struct soc_device *soc_dev;
+        struct device *parent = NULL;
+
+        tegra_clocks_apply_init_table();
+
+        soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
+        if (!soc_dev_attr)
+                goto out;
+
+        soc_dev_attr->family = kasprintf(GFP_KERNEL, "Tegra");
+        soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d", tegra_revision);
+        soc_dev_attr->soc_id = kasprintf(GFP_KERNEL, "%d", tegra_chip_id);
+
+        soc_dev = soc_device_register(soc_dev_attr);
+        if (IS_ERR(soc_dev)) {
+                kfree(soc_dev_attr->family);
+                kfree(soc_dev_attr->revision);
+                kfree(soc_dev_attr->soc_id);
+                kfree(soc_dev_attr);
+                goto out;
+        }
+
+        parent = soc_device_to_device(soc_dev);
+
         /*
          * Finished with the static registrations now; fill in the missing
          * devices
          */
+out:
         of_platform_populate(NULL, of_default_bus_match_table,
-                                tegra20_auxdata_lookup, NULL);
+                                tegra20_auxdata_lookup, parent);
 }
 
 static void __init trimslice_init(void)
@@ -111,7 +142,8 @@ static void __init harmony_init(void)
 
 static void __init paz00_init(void)
 {
-        tegra_paz00_wifikill_init();
+        if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
+                tegra_paz00_wifikill_init();
 }
 
 static struct {
@@ -137,19 +169,21 @@ static void __init tegra_dt_init_late(void)
         }
 }
 
-static const char *tegra20_dt_board_compat[] = {
+static const char * const tegra_dt_board_compat[] = {
+        "nvidia,tegra114",
+        "nvidia,tegra30",
         "nvidia,tegra20",
         NULL
 };
 
-DT_MACHINE_START(TEGRA_DT, "nVidia Tegra20 (Flattened Device Tree)")
+DT_MACHINE_START(TEGRA_DT, "NVIDIA Tegra SoC (Flattened Device Tree)")
         .map_io         = tegra_map_common_io,
         .smp            = smp_ops(tegra_smp_ops),
-        .init_early     = tegra20_init_early,
+        .init_early     = tegra_init_early,
         .init_irq       = tegra_dt_init_irq,
         .init_time      = clocksource_of_init,
         .init_machine   = tegra_dt_init,
         .init_late      = tegra_dt_init_late,
         .restart        = tegra_assert_system_reset,
-        .dt_compat      = tegra20_dt_board_compat,
+        .dt_compat      = tegra_dt_board_compat,
 MACHINE_END
diff --git a/arch/arm/mach-tegra/tegra114_speedo.c b/arch/arm/mach-tegra/tegra114_speedo.c
new file mode 100644
index 000000000000..5218d4853cd3
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra114_speedo.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+#include <linux/bug.h>
+
+#include "fuse.h"
+
+#define CORE_PROCESS_CORNERS_NUM        2
+#define CPU_PROCESS_CORNERS_NUM         2
+
+enum {
+        THRESHOLD_INDEX_0,
+        THRESHOLD_INDEX_1,
+        THRESHOLD_INDEX_COUNT,
+};
+
+static const u32 core_process_speedos[][CORE_PROCESS_CORNERS_NUM] = {
+        {1123,     UINT_MAX},
+        {0,        UINT_MAX},
+};
+
+static const u32 cpu_process_speedos[][CPU_PROCESS_CORNERS_NUM] = {
+        {1695,     UINT_MAX},
+        {0,        UINT_MAX},
+};
+
+static void rev_sku_to_speedo_ids(int rev, int sku, int *threshold)
+{
+        u32 tmp;
+
+        switch (sku) {
+        case 0x00:
+        case 0x10:
+        case 0x05:
+        case 0x06:
+                tegra_cpu_speedo_id = 1;
+                tegra_soc_speedo_id = 0;
+                *threshold = THRESHOLD_INDEX_0;
+                break;
+
+        case 0x03:
+        case 0x04:
+                tegra_cpu_speedo_id = 2;
+                tegra_soc_speedo_id = 1;
+                *threshold = THRESHOLD_INDEX_1;
+                break;
+
+        default:
+                pr_err("Tegra114 Unknown SKU %d\n", sku);
+                tegra_cpu_speedo_id = 0;
+                tegra_soc_speedo_id = 0;
+                *threshold = THRESHOLD_INDEX_0;
+                break;
+        }
+
+        if (rev == TEGRA_REVISION_A01) {
+                tmp = tegra_fuse_readl(0x270) << 1;
+                tmp |= tegra_fuse_readl(0x26c);
+                if (!tmp)
+                        tegra_cpu_speedo_id = 0;
+        }
+}
+
+void tegra114_init_speedo_data(void)
+{
+        u32 cpu_speedo_val;
+        u32 core_speedo_val;
+        int threshold;
+        int i;
+
+        BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) !=
+                        THRESHOLD_INDEX_COUNT);
+        BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) !=
+                        THRESHOLD_INDEX_COUNT);
+
+        rev_sku_to_speedo_ids(tegra_revision, tegra_sku_id, &threshold);
+
+        cpu_speedo_val = tegra_fuse_readl(0x12c) + 1024;
+        core_speedo_val = tegra_fuse_readl(0x134);
+
+        for (i = 0; i < CPU_PROCESS_CORNERS_NUM; i++)
+                if (cpu_speedo_val < cpu_process_speedos[threshold][i])
+                        break;
+        tegra_cpu_process_id = i;
+
+        for (i = 0; i < CORE_PROCESS_CORNERS_NUM; i++)
+                if (core_speedo_val < core_process_speedos[threshold][i])
+                        break;
+        tegra_core_process_id = i;
+}
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
index 0a3f30df1eb8..152ae38cd18c 100644
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -48,8 +48,12 @@ BIAS(slpm_in_nopull_wkup, PIN_SLEEPMODE_ENABLED|
         PIN_SLPM_DIR_INPUT|PIN_SLPM_PULL_NONE|PIN_SLPM_WAKEUP_ENABLE);
 BIAS(slpm_in_wkup_pdis, PIN_SLEEPMODE_ENABLED|
         PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
+BIAS(slpm_in_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|
+        PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED);
 BIAS(slpm_wkup_pdis, PIN_SLEEPMODE_ENABLED|
         PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
+BIAS(slpm_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|
+        PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED);
 BIAS(slpm_out_lo_pdis, PIN_SLEEPMODE_ENABLED|
         PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE|PIN_SLPM_PDIS_DISABLED);
 BIAS(slpm_out_lo_wkup, PIN_SLEEPMODE_ENABLED|
@@ -78,9 +82,6 @@ BIAS(out_wkup_pdis, PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|
         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-db8500", group, func)
 #define DB8500_PIN_HOG(pin,conf) \
         PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-db8500", pin, conf)
-#define DB8500_PIN_SLEEP(pin, conf, dev) \
-        PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \
-                            pin, conf)
 
 /* These are default states associated with device and changed runtime */
 #define DB8500_MUX(group,func,dev) \
@@ -309,8 +310,23 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = {
         DB8500_PIN_SLEEP("GPIO207_AJ23", slpm_in_wkup_pdis, "sdi4"), /* DAT4 */
 
         /* Mux in USB pins, drive STP high */
-        DB8500_MUX("usb_a_1", "usb", "musb-ux500.0"),
-        DB8500_PIN("GPIO257_AE29", out_hi, "musb-ux500.0"), /* STP */
+        /* USB default state */
+        DB8500_MUX("usb_a_1", "usb", "ab8500-usb.0"),
+        DB8500_PIN("GPIO257_AE29", out_hi, "ab8500-usb.0"), /* STP */
+        /* USB sleep state */
+        DB8500_PIN_SLEEP("GPIO256_AF28", slpm_wkup_pdis_en, "ab8500-usb.0"), /* NXT */
+        DB8500_PIN_SLEEP("GPIO257_AE29", slpm_out_hi_wkup_pdis, "ab8500-usb.0"), /* STP */
+        DB8500_PIN_SLEEP("GPIO258_AD29", slpm_wkup_pdis_en, "ab8500-usb.0"), /* XCLK */
+        DB8500_PIN_SLEEP("GPIO259_AC29", slpm_wkup_pdis_en, "ab8500-usb.0"), /* DIR */
+        DB8500_PIN_SLEEP("GPIO260_AD28", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT7 */
+        DB8500_PIN_SLEEP("GPIO261_AD26", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT6 */
+        DB8500_PIN_SLEEP("GPIO262_AE26", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT5 */
+        DB8500_PIN_SLEEP("GPIO263_AG29", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT4 */
+        DB8500_PIN_SLEEP("GPIO264_AE27", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT3 */
+        DB8500_PIN_SLEEP("GPIO265_AD27", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT2 */
+        DB8500_PIN_SLEEP("GPIO266_AC28", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT1 */
+        DB8500_PIN_SLEEP("GPIO267_AC27", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT0 */
+
         /* Mux in SPI2 pins on the "other C1" altfunction */
         DB8500_MUX("spi2_oc1_2", "spi2", "spi2"),
         DB8500_PIN("GPIO216_AG12", gpio_out_hi, "spi2"), /* FRM */
@@ -318,9 +334,9 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = {
         DB8500_PIN("GPIO215_AH13", out_lo, "spi2"), /* TXD */
         DB8500_PIN("GPIO217_AH12", out_lo, "spi2"), /* CLK */
         /* SPI2 idle state */
-        DB8500_PIN_SLEEP("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */
-        DB8500_PIN_SLEEP("GPIO215_AH13", slpm_out_lo_wkup_pdis, "spi2"), /* TXD */
-        DB8500_PIN_SLEEP("GPIO217_AH12", slpm_wkup_pdis, "spi2"), /* CLK */
+        DB8500_PIN_IDLE("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */
+        DB8500_PIN_IDLE("GPIO215_AH13", slpm_out_lo_wkup_pdis, "spi2"), /* TXD */
+        DB8500_PIN_IDLE("GPIO217_AH12", slpm_wkup_pdis, "spi2"), /* CLK */
         /* SPI2 sleep state */
         DB8500_PIN_SLEEP("GPIO216_AG12", slpm_in_wkup_pdis, "spi2"), /* FRM */
         DB8500_PIN_SLEEP("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */
@@ -747,6 +763,8 @@ static struct pinctrl_map __initdata snowball_pinmap[] = {
         DB8500_PIN_HOG("GPIO21_AB3", out_hi),
         /* Mux in "SM" which is used for the SMSC911x Ethernet adapter */
         DB8500_MUX_HOG("sm_b_1", "sm"),
+        /* User LED */
+        DB8500_PIN_HOG("GPIO142_C11", gpio_out_hi),
         /* Drive RSTn_LAN high */
         DB8500_PIN_HOG("GPIO141_C12", gpio_out_hi),
         /*  Accelerometer/Magnetometer */
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index 051b62c27102..7f2cb6c5e2c1 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -81,7 +81,6 @@ static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = {
 #endif
 
 struct mmci_platform_data mop500_sdi0_data = {
-        .ios_handler    = mop500_sdi0_ios_handler,
         .ocr_mask       = MMC_VDD_29_30,
         .f_max          = 50000000,
         .capabilities   = MMC_CAP_4_BIT_DATA |
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index b03457881c4b..87d2d7b38ce9 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -12,6 +12,7 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
+#include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/i2c.h>
 #include <linux/platform_data/i2c-nomadik.h>
@@ -439,6 +440,15 @@ static void mop500_prox_deactivate(struct device *dev)
         regulator_put(prox_regulator);
 }
 
+void mop500_snowball_ethernet_clock_enable(void)
+{
+        struct clk *clk;
+
+        clk = clk_get_sys("fsmc", NULL);
+        if (!IS_ERR(clk))
+                clk_prepare_enable(clk);
+}
+
 static struct cryp_platform_data u8500_cryp1_platform_data = {
                 .mem_to_engine = {
                                 .dir = STEDMA40_MEM_TO_PERIPH,
@@ -683,6 +693,8 @@ static void __init snowball_init_machine(void)
         mop500_audio_init(parent);
         mop500_uart_init(parent);
 
+        mop500_snowball_ethernet_clock_enable();
+
         /* This board has full regulator constraints */
         regulator_has_full_constraints();
 }
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index eaa605f5d90d..d38951be70df 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -104,6 +104,7 @@ void __init mop500_pinmaps_init(void);
 void __init snowball_pinmaps_init(void);
 void __init hrefv60_pinmaps_init(void);
 void mop500_audio_init(struct device *parent);
+void mop500_snowball_ethernet_clock_enable(void);
 
 int __init mop500_uib_init(void);
 void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info,
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 19235cf7bbe3..f1a581844372 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -312,9 +312,10 @@ static void __init u8500_init_machine(void)
         /* Pinmaps must be in place before devices register */
         if (of_machine_is_compatible("st-ericsson,mop500"))
                 mop500_pinmaps_init();
-        else if (of_machine_is_compatible("calaosystems,snowball-a9500"))
+        else if (of_machine_is_compatible("calaosystems,snowball-a9500")) {
                 snowball_pinmaps_init();
-        else if (of_machine_is_compatible("st-ericsson,hrefv60+"))
+                mop500_snowball_ethernet_clock_enable();
+        } else if (of_machine_is_compatible("st-ericsson,hrefv60+"))
                 hrefv60_pinmaps_init();
         else if (of_machine_is_compatible("st-ericsson,ccu9540")) {}
                 /* TODO: Add pinmaps for ccu9540 board. */
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 25160aeaa3b7..54bb80b012ac 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -749,12 +749,25 @@ void versatile_restart(char mode, const char *cmd)
 /* Early initializations */
 void __init versatile_init_early(void)
 {
+        u32 val;
         void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
 
         osc4_clk.vcoreg = sys + VERSATILE_SYS_OSCCLCD_OFFSET;
         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
         versatile_sched_clock_init(sys + VERSATILE_SYS_24MHz_OFFSET, 24000000);
+
+        /*
+         * set clock frequency:
+         *      VERSATILE_REFCLK is 32KHz
+         *      VERSATILE_TIMCLK is 1MHz
+         */
+        val = readl(__io_address(VERSATILE_SCTL_BASE));
+        writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
+               (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
+               (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
+               (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
+               __io_address(VERSATILE_SCTL_BASE));
 }
 
 void __init versatile_init(void)
@@ -785,19 +798,6 @@ void __init versatile_init(void)
  */
 void __init versatile_timer_init(void)
 {
-        u32 val;
-
-        /* 
-         * set clock frequency: 
-         *      VERSATILE_REFCLK is 32KHz
-         *      VERSATILE_TIMCLK is 1MHz
-         */
-        val = readl(__io_address(VERSATILE_SCTL_BASE));
-        writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
-               (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) | 
-               (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
-               (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
-               __io_address(VERSATILE_SCTL_BASE));
 
         /*
          * Initialise to a known state (all timers off)
diff --git a/arch/arm/mach-versatile/versatile_dt.c b/arch/arm/mach-versatile/versatile_dt.c
index 2558f2e957c3..3621b000a0f6 100644
--- a/arch/arm/mach-versatile/versatile_dt.c
+++ b/arch/arm/mach-versatile/versatile_dt.c
@@ -45,7 +45,6 @@ DT_MACHINE_START(VERSATILE_PB, "ARM-Versatile (Device Tree Support)")
         .map_io         = versatile_map_io,
         .init_early     = versatile_init_early,
         .init_irq       = versatile_init_irq,
-        .init_time      = versatile_timer_init,
         .init_machine   = versatile_dt_init,
         .dt_compat      = versatile_dt_match,
         .restart        = versatile_restart,
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index d0ad78998cb6..09e571ddc984 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -1,6 +1,7 @@
 /*
  * Versatile Express V2M Motherboard Support
  */
+#include <linux/clocksource.h>
 #include <linux/device.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/mmci.h>
@@ -23,7 +24,6 @@
 #include <linux/regulator/machine.h>
 #include <linux/vexpress.h>
 
-#include <asm/arch_timer.h>
 #include <asm/mach-types.h>
 #include <asm/sizes.h>
 #include <asm/mach/arch.h>
@@ -61,9 +61,6 @@ static void __init v2m_sp804_init(void __iomem *base, unsigned int irq)
         if (WARN_ON(!base || irq == NO_IRQ))
                 return;
 
-        writel(0, base + TIMER_1_BASE + TIMER_CTRL);
-        writel(0, base + TIMER_2_BASE + TIMER_CTRL);
-
         sp804_clocksource_init(base + TIMER_2_BASE, "v2m-timer1");
         sp804_clockevents_init(base + TIMER_1_BASE, irq, "v2m-timer0");
 }
@@ -431,25 +428,11 @@ void __init v2m_dt_init_early(void)
 
 static void __init v2m_dt_timer_init(void)
 {
-        struct device_node *node = NULL;
-
         vexpress_clk_of_init();
 
         clocksource_of_init();
-        do {
-                node = of_find_compatible_node(node, NULL, "arm,sp804");
-        } while (node && vexpress_get_site_by_node(node) != VEXPRESS_SITE_MB);
-        if (node) {
-                pr_info("Using SP804 '%s' as a clock & events source\n",
-                                node->full_name);
-                v2m_sp804_init(of_iomap(node, 0),
-                                irq_of_parse_and_map(node, 0));
-        }
-
-        arch_timer_of_register();
 
-        if (arch_timer_sched_clock_init() != 0)
-                versatile_sched_clock_init(vexpress_get_24mhz_clock_base(),
+        versatile_sched_clock_init(vexpress_get_24mhz_clock_base(),
                                 24000000);
 }
 
diff --git a/arch/arm/mach-virt/virt.c b/arch/arm/mach-virt/virt.c
index 31666f6b4373..adc0945255ae 100644
--- a/arch/arm/mach-virt/virt.c
+++ b/arch/arm/mach-virt/virt.c
@@ -23,21 +23,13 @@
 #include <linux/of_platform.h>
 #include <linux/smp.h>
 
-#include <asm/arch_timer.h>
 #include <asm/mach/arch.h>
-#include <asm/mach/time.h>
 
 static void __init virt_init(void)
 {
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
-static void __init virt_timer_init(void)
-{
-        WARN_ON(arch_timer_of_register() != 0);
-        WARN_ON(arch_timer_sched_clock_init() != 0);
-}
-
 static const char *virt_dt_match[] = {
         "linux,dummy-virt",
         NULL
@@ -47,7 +39,6 @@ extern struct smp_operations virt_smp_ops;
 
 DT_MACHINE_START(VIRT, "Dummy Virtual Machine")
         .init_irq       = irqchip_init,
-        .init_time      = virt_timer_init,
         .init_machine   = virt_init,
         .smp            = smp_ops(virt_smp_ops),
         .dt_compat      = virt_dt_match,
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index c2f37390308a..c465faca51b0 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -299,7 +299,7 @@ static void l2x0_unlock(u32 cache_id)
         int lockregs;
         int i;
 
-        switch (cache_id) {
+        switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
         case L2X0_CACHE_ID_PART_L310:
                 lockregs = 8;
                 break;
@@ -333,15 +333,14 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
         if (cache_id_part_number_from_dt)
                 cache_id = cache_id_part_number_from_dt;
         else
-                cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID)
-                        & L2X0_CACHE_ID_PART_MASK;
+                cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
         aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
 
         aux &= aux_mask;
         aux |= aux_val;
 
         /* Determine the number of ways */
-        switch (cache_id) {
+        switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
         case L2X0_CACHE_ID_PART_L310:
                 if (aux & (1 << 16))
                         ways = 16;
@@ -725,7 +724,6 @@ static const struct l2x0_of_data pl310_data = {
                 .flush_all   = l2x0_flush_all,
                 .inv_all     = l2x0_inv_all,
                 .disable     = l2x0_disable,
-                .set_debug   = pl310_set_debug,
         },
 };
 
@@ -814,9 +812,8 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
                 data->save();
 
         of_init = true;
-        l2x0_init(l2x0_base, aux_val, aux_mask);
-
         memcpy(&outer_cache, &data->outer_cache, sizeof(outer_cache));
+        l2x0_init(l2x0_base, aux_val, aux_mask);
 
         return 0;
 }
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index a5a4b2bc42ba..2ac37372ef52 100644
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -48,7 +48,7 @@ static DEFINE_RAW_SPINLOCK(cpu_asid_lock);
 static atomic64_t asid_generation = ATOMIC64_INIT(ASID_FIRST_VERSION);
 static DECLARE_BITMAP(asid_map, NUM_USER_ASIDS);
 
-static DEFINE_PER_CPU(atomic64_t, active_asids);
+DEFINE_PER_CPU(atomic64_t, active_asids);
 static DEFINE_PER_CPU(u64, reserved_asids);
 static cpumask_t tlb_flush_pending;
 
@@ -215,6 +215,7 @@ void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk)
         if (cpumask_test_and_clear_cpu(cpu, &tlb_flush_pending)) {
                 local_flush_bp_all();
                 local_flush_tlb_all();
+                dummy_flush_tlb_a15_erratum();
         }
 
         atomic64_set(&per_cpu(active_asids, cpu), asid);
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index e95a996ab78f..78978945492a 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -598,39 +598,60 @@ static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
         } while (pte++, addr += PAGE_SIZE, addr != end);
 }
 
-static void __init alloc_init_section(pud_t *pud, unsigned long addr,
-                                      unsigned long end, phys_addr_t phys,
-                                      const struct mem_type *type)
+static void __init map_init_section(pmd_t *pmd, unsigned long addr,
+                        unsigned long end, phys_addr_t phys,
+                        const struct mem_type *type)
 {
-        pmd_t *pmd = pmd_offset(pud, addr);
-
+#ifndef CONFIG_ARM_LPAE
         /*
-         * Try a section mapping - end, addr and phys must all be aligned
-         * to a section boundary.  Note that PMDs refer to the individual
-         * L1 entries, whereas PGDs refer to a group of L1 entries making
-         * up one logical pointer to an L2 table.
+         * In classic MMU format, puds and pmds are folded in to
+         * the pgds. pmd_offset gives the PGD entry. PGDs refer to a
+         * group of L1 entries making up one logical pointer to
+         * an L2 table (2MB), where as PMDs refer to the individual
+         * L1 entries (1MB). Hence increment to get the correct
+         * offset for odd 1MB sections.
+         * (See arch/arm/include/asm/pgtable-2level.h)
          */
-        if (type->prot_sect && ((addr | end | phys) & ~SECTION_MASK) == 0) {
-                pmd_t *p = pmd;
-
-#ifndef CONFIG_ARM_LPAE
-                if (addr & SECTION_SIZE)
-                        pmd++;
+        if (addr & SECTION_SIZE)
+                pmd++;
 #endif
+        do {
+                *pmd = __pmd(phys | type->prot_sect);
+                phys += SECTION_SIZE;
+        } while (pmd++, addr += SECTION_SIZE, addr != end);
 
-                do {
-                        *pmd = __pmd(phys | type->prot_sect);
-                        phys += SECTION_SIZE;
-                } while (pmd++, addr += SECTION_SIZE, addr != end);
+        flush_pmd_entry(pmd);
+}
 
-                flush_pmd_entry(p);
-        } else {
+static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
+                                      unsigned long end, phys_addr_t phys,
+                                      const struct mem_type *type)
+{
+        pmd_t *pmd = pmd_offset(pud, addr);
+        unsigned long next;
+
+        do {
                 /*
-                 * No need to loop; pte's aren't interested in the
-                 * individual L1 entries.
+                 * With LPAE, we must loop over to map
+                 * all the pmds for the given range.
                  */
-                alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type);
-        }
+                next = pmd_addr_end(addr, end);
+
+                /*
+                 * Try a section mapping - addr, next and phys must all be
+                 * aligned to a section boundary.
+                 */
+                if (type->prot_sect &&
+                                ((addr | next | phys) & ~SECTION_MASK) == 0) {
+                        map_init_section(pmd, addr, next, phys, type);
+                } else {
+                        alloc_init_pte(pmd, addr, next,
+                                                __phys_to_pfn(phys), type);
+                }
+
+                phys += next - addr;
+
+        } while (pmd++, addr = next, addr != end);
 }
 
 static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
@@ -641,7 +662,7 @@ static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
 
         do {
                 next = pud_addr_end(addr, end);
-                alloc_init_section(pud, addr, next, phys, type);
+                alloc_init_pmd(pud, addr, next, phys, type);
                 phys += next - addr;
         } while (pud++, addr = next, addr != end);
 }
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 3a3c015f8d5c..f584d3f5b37c 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -420,7 +420,7 @@ __v7_pj4b_proc_info:
 __v7_ca7mp_proc_info:
         .long   0x410fc070
         .long   0xff0ffff0
-        __v7_proc __v7_ca7mp_setup, hwcaps = HWCAP_IDIV
+        __v7_proc __v7_ca7mp_setup
         .size   __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
 
         /*
@@ -430,10 +430,25 @@ __v7_ca7mp_proc_info:
 __v7_ca15mp_proc_info:
         .long   0x410fc0f0
         .long   0xff0ffff0
-        __v7_proc __v7_ca15mp_setup, hwcaps = HWCAP_IDIV
+        __v7_proc __v7_ca15mp_setup
         .size   __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
 
         /*
+         * Qualcomm Inc. Krait processors.
+         */
+        .type   __krait_proc_info, #object
+__krait_proc_info:
+        .long   0x510f0400              @ Required ID value
+        .long   0xff0ffc00              @ Mask for ID
+        /*
+         * Some Krait processors don't indicate support for SDIV and UDIV
+         * instructions in the ARM instruction set, even though they actually
+         * do support them.
+         */
+        __v7_proc __v7_setup, hwcaps = HWCAP_IDIV
+        .size   __krait_proc_info, . - __krait_proc_info
+
+        /*
          * Match any ARMv7 processor core.
          */
         .type   __v7_proc_info, #object
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 0f6c47a6475b..989fefe18be6 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -183,7 +183,6 @@ extern void s3c_init_cpu(unsigned long idcode,
 
 /* core initialisation functions */
 
-extern void s3c24xx_init_irq(void);
 extern void s5p_init_irq(u32 *vic, u32 num_vic);
 
 extern void s3c24xx_init_io(struct map_desc *mach_desc, int size);
diff --git a/arch/arm/plat-spear/Kconfig b/arch/arm/plat-spear/Kconfig
deleted file mode 100644
index 8a08c31b5e20..000000000000
--- a/arch/arm/plat-spear/Kconfig
+++ /dev/null
@@ -1,47 +0,0 @@
-#
-# SPEAr Platform configuration file
-#
-
-if PLAT_SPEAR
-
-choice
-        prompt "ST SPEAr Family"
-        default ARCH_SPEAR3XX
-
-config ARCH_SPEAR13XX
-        bool "ST SPEAr13xx with Device Tree"
-        select ARCH_HAS_CPUFREQ
-        select ARM_GIC
-        select CPU_V7
-        select GPIO_SPEAR_SPICS
-        select HAVE_SMP
-        select MIGHT_HAVE_CACHE_L2X0
-        select PINCTRL
-        select USE_OF
-        help
-          Supports for ARM's SPEAR13XX family
-
-config ARCH_SPEAR3XX
-        bool "ST SPEAr3xx with Device Tree"
-        select ARM_VIC
-        select CPU_ARM926T
-        select PINCTRL
-        select USE_OF
-        help
-          Supports for ARM's SPEAR3XX family
-
-config ARCH_SPEAR6XX
-        bool "SPEAr6XX"
-        select ARM_VIC
-        select CPU_ARM926T
-        help
-          Supports for ARM's SPEAR6XX family
-
-endchoice
-
-# Adding SPEAr machine specific configuration files
-source "arch/arm/mach-spear13xx/Kconfig"
-source "arch/arm/mach-spear3xx/Kconfig"
-source "arch/arm/mach-spear6xx/Kconfig"
-
-endif
diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile
deleted file mode 100644
index 01e88532a5db..000000000000
--- a/arch/arm/plat-spear/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# SPEAr Platform specific Makefile
-#
-
-# Common support
-obj-y   := restart.o time.o
-
-obj-$(CONFIG_ARCH_SPEAR3XX)     += pl080.o
-obj-$(CONFIG_ARCH_SPEAR6XX)     += pl080.o
diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h
index 91e2a6a6fcd4..bf6ab242f047 100644
--- a/arch/arm64/include/asm/arch_timer.h
+++ b/arch/arm64/include/asm/arch_timer.h
@@ -130,4 +130,9 @@ static inline u64 arch_counter_get_cntvct(void)
         return cval;
 }
 
+static inline int arch_timer_arch_init(void)
+{
+        return 0;
+}
+
 #endif
diff --git a/arch/arm64/kernel/time.c b/arch/arm64/kernel/time.c
index b0ef18d14c3b..a551f88ae2c1 100644
--- a/arch/arm64/kernel/time.c
+++ b/arch/arm64/kernel/time.c
@@ -32,6 +32,7 @@
 #include <linux/timer.h>
 #include <linux/irq.h>
 #include <linux/delay.h>
+#include <linux/clocksource.h>
 
 #include <clocksource/arm_arch_timer.h>
 
@@ -77,10 +78,11 @@ void __init time_init(void)
 {
         u32 arch_timer_rate;
 
-        if (arch_timer_init())
-                panic("Unable to initialise architected timer.\n");
+        clocksource_of_init();
 
         arch_timer_rate = arch_timer_get_rate();
+        if (!arch_timer_rate)
+                panic("Unable to initialise architected timer.\n");
 
         /* Cache the sched_clock multiplier to save a divide in the hot path. */
         sched_clock_mult = NSEC_PER_SEC / arch_timer_rate;
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index cd2e21ff562a..51244bf97271 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -18,7 +18,7 @@ config MIPS
         select HAVE_KRETPROBES
         select HAVE_DEBUG_KMEMLEAK
         select ARCH_BINFMT_ELF_RANDOMIZE_PIE
-        select HAVE_ARCH_TRANSPARENT_HUGEPAGE
+        select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES && 64BIT
         select RTC_LIB if !MACH_LOONGSON
         select GENERIC_ATOMIC64 if !64BIT
         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
@@ -657,7 +657,7 @@ config SNI_RM
         bool "SNI RM200/300/400"
         select FW_ARC if CPU_LITTLE_ENDIAN
         select FW_ARC32 if CPU_LITTLE_ENDIAN
-        select SNIPROM if CPU_BIG_ENDIAN
+        select FW_SNIPROM if CPU_BIG_ENDIAN
         select ARCH_MAY_HAVE_PC_FDC
         select BOOT_ELF32
         select CEVT_R4K
@@ -1144,7 +1144,7 @@ config DEFAULT_SGI_PARTITION
 config FW_ARC32
         bool
 
-config SNIPROM
+config FW_SNIPROM
         bool
 
 config BOOT_ELF32
@@ -1493,7 +1493,6 @@ config CPU_XLP
         select CPU_SUPPORTS_32BIT_KERNEL
         select CPU_SUPPORTS_64BIT_KERNEL
         select CPU_SUPPORTS_HIGHMEM
-        select CPU_HAS_LLSC
         select WEAK_ORDERING
         select WEAK_REORDERING_BEYOND_LLSC
         select CPU_HAS_PREFETCH
diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c
index ed1949c29508..9aa7d44898ed 100644
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
@@ -745,10 +745,7 @@ void __init board_prom_init(void)
                 strcpy(cfe_version, "unknown");
         printk(KERN_INFO PFX "CFE version: %s\n", cfe_version);
 
-        if (bcm63xx_nvram_init(boot_addr + BCM963XX_NVRAM_OFFSET)) {
-                printk(KERN_ERR PFX "invalid nvram checksum\n");
-                return;
-        }
+        bcm63xx_nvram_init(boot_addr + BCM963XX_NVRAM_OFFSET);
 
         board_name = bcm63xx_nvram_get_name();
         /* find board by name */
diff --git a/arch/mips/bcm63xx/nvram.c b/arch/mips/bcm63xx/nvram.c
index 620611680839..a4b8864f9307 100644
--- a/arch/mips/bcm63xx/nvram.c
+++ b/arch/mips/bcm63xx/nvram.c
@@ -38,7 +38,7 @@ struct bcm963xx_nvram {
 static struct bcm963xx_nvram nvram;
 static int mac_addr_used;
 
-int __init bcm63xx_nvram_init(void *addr)
+void __init bcm63xx_nvram_init(void *addr)
 {
         unsigned int check_len;
         u32 crc, expected_crc;
@@ -60,9 +60,8 @@ int __init bcm63xx_nvram_init(void *addr)
         crc = crc32_le(~0, (u8 *)&nvram, check_len);
 
         if (crc != expected_crc)
-                return -EINVAL;
-
-        return 0;
+                pr_warn("nvram checksum failed, contents may be invalid (expected %08x, got %08x)\n",
+                        expected_crc, crc);
 }
 
 u8 *bcm63xx_nvram_get_name(void)
diff --git a/arch/mips/bcm63xx/setup.c b/arch/mips/bcm63xx/setup.c
index 314231be788c..35e18e98beb9 100644
--- a/arch/mips/bcm63xx/setup.c
+++ b/arch/mips/bcm63xx/setup.c
@@ -157,4 +157,4 @@ int __init bcm63xx_register_devices(void)
         return board_register_devices();
 }
 
-device_initcall(bcm63xx_register_devices);
+arch_initcall(bcm63xx_register_devices);
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index c594a3d4f743..b0baa299f899 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -174,7 +174,10 @@ static int octeon_kexec_prepare(struct kimage *image)
 
 static void octeon_generic_shutdown(void)
 {
-        int cpu, i;
+        int i;
+#ifdef CONFIG_SMP
+        int cpu;
+#endif
         struct cvmx_bootmem_desc *bootmem_desc;
         void *named_block_array_ptr;
 
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h
index 62d6a3b4d3b7..4e0b6bc1165e 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h
@@ -9,10 +9,8 @@
  *
  * Initialized the local nvram copy from the target address and checks
  * its checksum.
- *
- * Returns 0 on success.
  */
-int __init bcm63xx_nvram_init(void *nvram);
+void bcm63xx_nvram_init(void *nvram);
 
 /**
  * bcm63xx_nvram_get_name() - returns the board name according to nvram
diff --git a/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h b/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h
index d9c828419037..193c0912d38e 100644
--- a/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h
@@ -28,11 +28,7 @@
 /* #define cpu_has_prefetch     ? */
 #define cpu_has_mcheck          1
 /* #define cpu_has_ejtag        ? */
-#ifdef CONFIG_CPU_HAS_LLSC
 #define cpu_has_llsc            1
-#else
-#define cpu_has_llsc            0
-#endif
 /* #define cpu_has_vtag_icache  ? */
 /* #define cpu_has_dc_aliases   ? */
 /* #define cpu_has_ic_fills_f_dc ? */
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 12b70c25906a..0da44d422f5b 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -1166,7 +1166,10 @@ do {									\
         unsigned int __dspctl;                                          \
                                                                         \
         __asm__ __volatile__(                                           \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
         "       rddsp   %0, %x1                                 \n"     \
+        "       .set pop                                        \n"     \
         : "=r" (__dspctl)                                               \
         : "i" (mask));                                                  \
         __dspctl;                                                       \
@@ -1175,30 +1178,198 @@ do {									\
 #define wrdsp(val, mask)                                                \
 do {                                                                    \
         __asm__ __volatile__(                                           \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
         "       wrdsp   %0, %x1                                 \n"     \
+        "       .set pop                                        \n"     \
         :                                                               \
         : "r" (val), "i" (mask));                                       \
 } while (0)
 
-#define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;})
-#define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;})
-#define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;})
-#define mflo3() ({ long mflo3; __asm__("mflo %0, $ac3" : "=r" (mflo3)); mflo3;})
-
-#define mfhi0() ({ long mfhi0; __asm__("mfhi %0, $ac0" : "=r" (mfhi0)); mfhi0;})
-#define mfhi1() ({ long mfhi1; __asm__("mfhi %0, $ac1" : "=r" (mfhi1)); mfhi1;})
-#define mfhi2() ({ long mfhi2; __asm__("mfhi %0, $ac2" : "=r" (mfhi2)); mfhi2;})
-#define mfhi3() ({ long mfhi3; __asm__("mfhi %0, $ac3" : "=r" (mfhi3)); mfhi3;})
-
-#define mtlo0(x) __asm__("mtlo %0, $ac0" ::"r" (x))
-#define mtlo1(x) __asm__("mtlo %0, $ac1" ::"r" (x))
-#define mtlo2(x) __asm__("mtlo %0, $ac2" ::"r" (x))
-#define mtlo3(x) __asm__("mtlo %0, $ac3" ::"r" (x))
-
-#define mthi0(x) __asm__("mthi %0, $ac0" ::"r" (x))
-#define mthi1(x) __asm__("mthi %0, $ac1" ::"r" (x))
-#define mthi2(x) __asm__("mthi %0, $ac2" ::"r" (x))
-#define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x))
+#define mflo0()                                                         \
+({                                                                      \
+        long mflo0;                                                     \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
+        "       mflo %0, $ac0                                   \n"     \
+        "       .set pop                                        \n"     \
+        : "=r" (mflo0));                                                \
+        mflo0;                                                          \
+})
+
+#define mflo1()                                                         \
+({                                                                      \
+        long mflo1;                                                     \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
+        "       mflo %0, $ac1                                   \n"     \
+        "       .set pop                                        \n"     \
+        : "=r" (mflo1));                                                \
+        mflo1;                                                          \
+})
+
+#define mflo2()                                                         \
+({                                                                      \
+        long mflo2;                                                     \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
+        "       mflo %0, $ac2                                   \n"     \
+        "       .set pop                                        \n"     \
+        : "=r" (mflo2));                                                \
+        mflo2;                                                          \
+})
+
+#define mflo3()                                                         \
+({                                                                      \
+        long mflo3;                                                     \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
+        "       mflo %0, $ac3                                   \n"     \
+        "       .set pop                                        \n"     \
+        : "=r" (mflo3));                                                \
+        mflo3;                                                          \
+})
+
+#define mfhi0()                                                         \
+({                                                                      \
+        long mfhi0;                                                     \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
+        "       mfhi %0, $ac0                                   \n"     \
+        "       .set pop                                        \n"     \
+        : "=r" (mfhi0));                                                \
+        mfhi0;                                                          \
+})
+
+#define mfhi1()                                                         \
+({                                                                      \
+        long mfhi1;                                                     \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
+        "       mfhi %0, $ac1                                   \n"     \
+        "       .set pop                                        \n"     \
+        : "=r" (mfhi1));                                                \
+        mfhi1;                                                          \
+})
+
+#define mfhi2()                                                         \
+({                                                                      \
+        long mfhi2;                                                     \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
+        "       mfhi %0, $ac2                                   \n"     \
+        "       .set pop                                        \n"     \
+        : "=r" (mfhi2));                                                \
+        mfhi2;                                                          \
+})
+
+#define mfhi3()                                                         \
+({                                                                      \
+        long mfhi3;                                                     \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
+        "       mfhi %0, $ac3                                   \n"     \
+        "       .set pop                                        \n"     \
+        : "=r" (mfhi3));                                                \
+        mfhi3;                                                          \
+})
+
+
+#define mtlo0(x)                                                        \
+({                                                                      \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
+        "       mtlo %0, $ac0                                   \n"     \
+        "       .set pop                                        \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+})
+
+#define mtlo1(x)                                                        \
+({                                                                      \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
+        "       mtlo %0, $ac1                                   \n"     \
+        "       .set pop                                        \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+})
+
+#define mtlo2(x)                                                        \
+({                                                                      \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
+        "       mtlo %0, $ac2                                   \n"     \
+        "       .set pop                                        \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+})
+
+#define mtlo3(x)                                                        \
+({                                                                      \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
+        "       mtlo %0, $ac3                                   \n"     \
+        "       .set pop                                        \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+})
+
+#define mthi0(x)                                                        \
+({                                                                      \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
+        "       mthi %0, $ac0                                   \n"     \
+        "       .set pop                                        \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+})
+
+#define mthi1(x)                                                        \
+({                                                                      \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
+        "       mthi %0, $ac1                                   \n"     \
+        "       .set pop                                        \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+})
+
+#define mthi2(x)                                                        \
+({                                                                      \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
+        "       mthi %0, $ac2                                   \n"     \
+        "       .set pop                                        \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+})
+
+#define mthi3(x)                                                        \
+({                                                                      \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
+        "       mthi %0, $ac3                                   \n"     \
+        "       .set pop                                        \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+})
 
 #else
 
diff --git a/arch/mips/include/asm/signal.h b/arch/mips/include/asm/signal.h
index 197f6367c201..8efe5a9e2c3e 100644
--- a/arch/mips/include/asm/signal.h
+++ b/arch/mips/include/asm/signal.h
@@ -21,6 +21,6 @@
 #include <asm/sigcontext.h>
 #include <asm/siginfo.h>
 
-#define __ARCH_HAS_ODD_SIGACTION
+#define __ARCH_HAS_IRIX_SIGACTION
 
 #endif /* _ASM_SIGNAL_H */
diff --git a/arch/mips/include/uapi/asm/signal.h b/arch/mips/include/uapi/asm/signal.h
index d6b18b4d0f3a..addb9f556b71 100644
--- a/arch/mips/include/uapi/asm/signal.h
+++ b/arch/mips/include/uapi/asm/signal.h
@@ -72,6 +72,12 @@ typedef unsigned long old_sigset_t;		/* at least 32 bits */
  *
  * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
  * Unix names RESETHAND and NODEFER respectively.
+ *
+ * SA_RESTORER used to be defined as 0x04000000 but only the O32 ABI ever
+ * supported its use and no libc was using it, so the entire sa-restorer
+ * functionality was removed with lmo commit 39bffc12c3580ab for 2.5.48
+ * retaining only the SA_RESTORER definition as a reminder to avoid
+ * accidental reuse of the mask bit.
  */
 #define SA_ONSTACK      0x08000000
 #define SA_RESETHAND    0x80000000
@@ -84,8 +90,6 @@ typedef unsigned long old_sigset_t;		/* at least 32 bits */
 #define SA_NOMASK       SA_NODEFER
 #define SA_ONESHOT      SA_RESETHAND
 
-#define SA_RESTORER     0x04000000      /* Only for o32 */
-
 #define MINSIGSTKSZ    2048
 #define SIGSTKSZ       8192
 
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index f81d98f6184c..de75fb50562b 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -100,29 +100,16 @@ obj-$(CONFIG_HW_PERF_EVENTS)	+= perf_event_mipsxx.o
 obj-$(CONFIG_JUMP_LABEL)        += jump_label.o
 
 #
-# DSP ASE supported for MIPS32 or MIPS64 Release 2 cores only. It is safe
-# to enable DSP assembler support here even if the MIPS Release 2 CPU we
-# are targetting does not support DSP because all code-paths making use of
-# it properly check that the running CPU *actually does* support these
-# instructions.
+# DSP ASE supported for MIPS32 or MIPS64 Release 2 cores only. It is not
+# safe to unconditionnaly use the assembler -mdsp / -mdspr2 switches
+# here because the compiler may use DSP ASE instructions (such as lwx) in
+# code paths where we cannot check that the CPU we are running on supports it.
+# Proper abstraction using HAVE_AS_DSP and macros is done in
+# arch/mips/include/asm/mipsregs.h.
 #
 ifeq ($(CONFIG_CPU_MIPSR2), y)
 CFLAGS_DSP                      = -DHAVE_AS_DSP
 
-#
-# Check if assembler supports DSP ASE
-#
-ifeq ($(call cc-option-yn,-mdsp), y)
-CFLAGS_DSP                      += -mdsp
-endif
-
-#
-# Check if assembler supports DSP ASE Rev2
-#
-ifeq ($(call cc-option-yn,-mdspr2), y)
-CFLAGS_DSP                      += -mdspr2
-endif
-
 CFLAGS_signal.o                 = $(CFLAGS_DSP)
 CFLAGS_signal32.o               = $(CFLAGS_DSP)
 CFLAGS_process.o                = $(CFLAGS_DSP)
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 6bfccc227a95..5fe66a0c3224 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -580,6 +580,9 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
                 c->tlbsize = 48;
                 break;
         case PRID_IMP_VR41XX:
+                set_isa(c, MIPS_CPU_ISA_III);
+                c->options = R4K_OPTS;
+                c->tlbsize = 32;
                 switch (c->processor_id & 0xf0) {
                 case PRID_REV_VR4111:
                         c->cputype = CPU_VR4111;
@@ -604,6 +607,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
                                 __cpu_name[cpu] = "NEC VR4131";
                         } else {
                                 c->cputype = CPU_VR4133;
+                                c->options |= MIPS_CPU_LLSC;
                                 __cpu_name[cpu] = "NEC VR4133";
                         }
                         break;
@@ -613,9 +617,6 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
                         __cpu_name[cpu] = "NEC Vr41xx";
                         break;
                 }
-                set_isa(c, MIPS_CPU_ISA_III);
-                c->options = R4K_OPTS;
-                c->tlbsize = 32;
                 break;
         case PRID_IMP_R4300:
                 c->cputype = CPU_R4300;
@@ -1226,10 +1227,8 @@ __cpuinit void cpu_probe(void)
         if (c->options & MIPS_CPU_FPU) {
                 c->fpu_id = cpu_get_fpu_id();
 
-                if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
-                    c->isa_level == MIPS_CPU_ISA_M32R2 ||
-                    c->isa_level == MIPS_CPU_ISA_M64R1 ||
-                    c->isa_level == MIPS_CPU_ISA_M64R2) {
+                if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
+                                    MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
                         if (c->fpu_id & MIPS_FPIR_3D)
                                 c->ases |= MIPS_ASE_MIPS3D;
                 }
diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c
index 8eeee1c860c0..db9655f08892 100644
--- a/arch/mips/kernel/linux32.c
+++ b/arch/mips/kernel/linux32.c
@@ -171,7 +171,7 @@ SYSCALL_DEFINE6(32_ipc, u32, call, long, first, long, second, long, third,
                 err = compat_sys_shmctl(first, second, compat_ptr(ptr));
                 break;
         default:
-                err = -EINVAL;
+                err = -ENOSYS;
                 break;
         }
 
diff --git a/arch/mips/kernel/mcount.S b/arch/mips/kernel/mcount.S
index 165867673357..33d067148e61 100644
--- a/arch/mips/kernel/mcount.S
+++ b/arch/mips/kernel/mcount.S
@@ -46,10 +46,9 @@
         PTR_L   a5, PT_R9(sp)
         PTR_L   a6, PT_R10(sp)
         PTR_L   a7, PT_R11(sp)
-#else
-        PTR_ADDIU       sp, PT_SIZE
 #endif
-.endm
+        PTR_ADDIU       sp, PT_SIZE
+        .endm
 
         .macro RETURN_BACK
         jr ra
@@ -68,7 +67,11 @@ NESTED(ftrace_caller, PT_SIZE, ra)
         .globl _mcount
 _mcount:
         b       ftrace_stub
-        addiu sp,sp,8
+#ifdef CONFIG_32BIT
+         addiu sp,sp,8
+#else
+         nop
+#endif
 
         /* When tracing is activated, it calls ftrace_caller+8 (aka here) */
         lw      t1, function_trace_stop
diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
index 135c4aadccbe..7a54f74b7818 100644
--- a/arch/mips/kernel/proc.c
+++ b/arch/mips/kernel/proc.c
@@ -67,7 +67,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
         if (cpu_has_mips_r) {
                 seq_printf(m, "isa\t\t\t:");
                 if (cpu_has_mips_1)
-                        seq_printf(m, "%s", "mips1");
+                        seq_printf(m, "%s", " mips1");
                 if (cpu_has_mips_2)
                         seq_printf(m, "%s", " mips2");
                 if (cpu_has_mips_3)
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index a200b5bdbb87..c3abb88170fc 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1571,7 +1571,7 @@ void __cpuinit per_cpu_trap_init(bool is_boot_cpu)
 #ifdef CONFIG_64BIT
         status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
 #endif
-        if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
+        if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV)
                 status_set |= ST0_XX;
         if (cpu_has_dsp)
                 status_set |= ST0_MX;
diff --git a/arch/mips/lib/bitops.c b/arch/mips/lib/bitops.c
index 81f1dcfdcab8..a64daee740ee 100644
--- a/arch/mips/lib/bitops.c
+++ b/arch/mips/lib/bitops.c
@@ -90,12 +90,12 @@ int __mips_test_and_set_bit(unsigned long nr,
         unsigned bit = nr & SZLONG_MASK;
         unsigned long mask;
         unsigned long flags;
-        unsigned long res;
+        int res;
 
         a += nr >> SZLONG_LOG;
         mask = 1UL << bit;
         raw_local_irq_save(flags);
-        res = (mask & *a);
+        res = (mask & *a) != 0;
         *a |= mask;
         raw_local_irq_restore(flags);
         return res;
@@ -116,12 +116,12 @@ int __mips_test_and_set_bit_lock(unsigned long nr,
         unsigned bit = nr & SZLONG_MASK;
         unsigned long mask;
         unsigned long flags;
-        unsigned long res;
+        int res;
 
         a += nr >> SZLONG_LOG;
         mask = 1UL << bit;
         raw_local_irq_save(flags);
-        res = (mask & *a);
+        res = (mask & *a) != 0;
         *a |= mask;
         raw_local_irq_restore(flags);
         return res;
@@ -141,12 +141,12 @@ int __mips_test_and_clear_bit(unsigned long nr, volatile unsigned long *addr)
         unsigned bit = nr & SZLONG_MASK;
         unsigned long mask;
         unsigned long flags;
-        unsigned long res;
+        int res;
 
         a += nr >> SZLONG_LOG;
         mask = 1UL << bit;
         raw_local_irq_save(flags);
-        res = (mask & *a);
+        res = (mask & *a) != 0;
         *a &= ~mask;
         raw_local_irq_restore(flags);
         return res;
@@ -166,12 +166,12 @@ int __mips_test_and_change_bit(unsigned long nr, volatile unsigned long *addr)
         unsigned bit = nr & SZLONG_MASK;
         unsigned long mask;
         unsigned long flags;
-        unsigned long res;
+        int res;
 
         a += nr >> SZLONG_LOG;
         mask = 1UL << bit;
         raw_local_irq_save(flags);
-        res = (mask & *a);
+        res = (mask & *a) != 0;
         *a ^= mask;
         raw_local_irq_restore(flags);
         return res;
diff --git a/arch/mips/lib/csum_partial.S b/arch/mips/lib/csum_partial.S
index 507147aebd41..a6adffbb4e5f 100644
--- a/arch/mips/lib/csum_partial.S
+++ b/arch/mips/lib/csum_partial.S
@@ -270,7 +270,7 @@ LEAF(csum_partial)
 #endif
 
         /* odd buffer alignment? */
-#ifdef CPU_MIPSR2
+#ifdef CONFIG_CPU_MIPSR2
         wsbh    v1, sum
         movn    sum, v1, t7
 #else
@@ -670,7 +670,7 @@ EXC(	sb	t0, NBYTES-2(dst), .Ls_exc)
         addu    sum, v1
 #endif
 
-#ifdef CPU_MIPSR2
+#ifdef CONFIG_CPU_MIPSR2
         wsbh    v1, sum
         movn    sum, v1, odd
 #else
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index ecca559b8d7b..2078915eacb9 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1247,10 +1247,8 @@ static void __cpuinit setup_scache(void)
                 return;
 
         default:
-                if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
-                    c->isa_level == MIPS_CPU_ISA_M32R2 ||
-                    c->isa_level == MIPS_CPU_ISA_M64R1 ||
-                    c->isa_level == MIPS_CPU_ISA_M64R2) {
+                if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
+                                    MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
 #ifdef CONFIG_MIPS_CPU_SCACHE
                         if (mips_sc_init ()) {
                                 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index 93d937b4b1ba..df96da7e939b 100644
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -98,10 +98,8 @@ static inline int __init mips_sc_probe(void)
         c->scache.flags |= MIPS_CACHE_NOT_PRESENT;
 
         /* Ignore anything but MIPSxx processors */
-        if (c->isa_level != MIPS_CPU_ISA_M32R1 &&
-            c->isa_level != MIPS_CPU_ISA_M32R2 &&
-            c->isa_level != MIPS_CPU_ISA_M64R1 &&
-            c->isa_level != MIPS_CPU_ISA_M64R2)
+        if (!(c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
+                              MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)))
                 return 0;
 
         /* Does this MIPS32/MIPS64 CPU have a config2 register? */
diff --git a/arch/mips/pci/pci-alchemy.c b/arch/mips/pci/pci-alchemy.c
index 38a80c83fd67..d1faece21b6a 100644
--- a/arch/mips/pci/pci-alchemy.c
+++ b/arch/mips/pci/pci-alchemy.c
@@ -19,7 +19,7 @@
 #include <asm/mach-au1x00/au1000.h>
 #include <asm/tlbmisc.h>
 
-#ifdef CONFIG_DEBUG_PCI
+#ifdef CONFIG_PCI_DEBUG
 #define DBG(x...) printk(KERN_DEBUG x)
 #else
 #define DBG(x...) do {} while (0)
@@ -162,7 +162,7 @@ static int config_access(unsigned char access_type, struct pci_bus *bus,
         if (status & (1 << 29)) {
                 *data = 0xffffffff;
                 error = -1;
-                DBG("alchemy-pci: master abort on cfg access %d bus %d dev %d",
+                DBG("alchemy-pci: master abort on cfg access %d bus %d dev %d\n",
                     access_type, bus->number, device);
         } else if ((status >> 28) & 0xf) {
                 DBG("alchemy-pci: PCI ERR detected: dev %d, status %lx\n",
diff --git a/arch/s390/include/asm/pgtable.h b/arch/s390/include/asm/pgtable.h
index 4a2930844d43..4a5443118cfb 100644
--- a/arch/s390/include/asm/pgtable.h
+++ b/arch/s390/include/asm/pgtable.h
@@ -344,6 +344,7 @@ extern unsigned long MODULES_END;
 #define _REGION3_ENTRY_CO       0x100   /* change-recording override        */
 
 /* Bits in the segment table entry */
+#define _SEGMENT_ENTRY_ORIGIN_LARGE ~0xfffffUL /* large page address        */
 #define _SEGMENT_ENTRY_ORIGIN   ~0x7ffUL/* segment table origin             */
 #define _SEGMENT_ENTRY_RO       0x200   /* page protection bit              */
 #define _SEGMENT_ENTRY_INV      0x20    /* invalid segment table entry      */
@@ -1531,7 +1532,8 @@ extern int s390_enable_sie(void);
 /*
  * No page table caches to initialise
  */
-#define pgtable_cache_init()    do { } while (0)
+static inline void pgtable_cache_init(void) { }
+static inline void check_pgt_cache(void) { }
 
 #include <asm-generic/pgtable.h>
 
diff --git a/arch/s390/lib/uaccess_pt.c b/arch/s390/lib/uaccess_pt.c
index dff631d34b45..466fb3383960 100644
--- a/arch/s390/lib/uaccess_pt.c
+++ b/arch/s390/lib/uaccess_pt.c
@@ -77,42 +77,69 @@ static size_t copy_in_kernel(size_t count, void __user *to,
  * >= -4095 (IS_ERR_VALUE(x) returns true), a fault has occured and the address
  * contains the (negative) exception code.
  */
-static __always_inline unsigned long follow_table(struct mm_struct *mm,
-                                                  unsigned long addr, int write)
+#ifdef CONFIG_64BIT
+static unsigned long follow_table(struct mm_struct *mm,
+                                  unsigned long address, int write)
 {
-        pgd_t *pgd;
-        pud_t *pud;
-        pmd_t *pmd;
-        pte_t *ptep;
+        unsigned long *table = (unsigned long *)__pa(mm->pgd);
+
+        switch (mm->context.asce_bits & _ASCE_TYPE_MASK) {
+        case _ASCE_TYPE_REGION1:
+                table = table + ((address >> 53) & 0x7ff);
+                if (unlikely(*table & _REGION_ENTRY_INV))
+                        return -0x39UL;
+                table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
+        case _ASCE_TYPE_REGION2:
+                table = table + ((address >> 42) & 0x7ff);
+                if (unlikely(*table & _REGION_ENTRY_INV))
+                        return -0x3aUL;
+                table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
+        case _ASCE_TYPE_REGION3:
+                table = table + ((address >> 31) & 0x7ff);
+                if (unlikely(*table & _REGION_ENTRY_INV))
+                        return -0x3bUL;
+                table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
+        case _ASCE_TYPE_SEGMENT:
+                table = table + ((address >> 20) & 0x7ff);
+                if (unlikely(*table & _SEGMENT_ENTRY_INV))
+                        return -0x10UL;
+                if (unlikely(*table & _SEGMENT_ENTRY_LARGE)) {
+                        if (write && (*table & _SEGMENT_ENTRY_RO))
+                                return -0x04UL;
+                        return (*table & _SEGMENT_ENTRY_ORIGIN_LARGE) +
+                                (address & ~_SEGMENT_ENTRY_ORIGIN_LARGE);
+                }
+                table = (unsigned long *)(*table & _SEGMENT_ENTRY_ORIGIN);
+        }
+        table = table + ((address >> 12) & 0xff);
+        if (unlikely(*table & _PAGE_INVALID))
+                return -0x11UL;
+        if (write && (*table & _PAGE_RO))
+                return -0x04UL;
+        return (*table & PAGE_MASK) + (address & ~PAGE_MASK);
+}
 
-        pgd = pgd_offset(mm, addr);
-        if (pgd_none(*pgd) || unlikely(pgd_bad(*pgd)))
-                return -0x3aUL;
+#else /* CONFIG_64BIT */
 
-        pud = pud_offset(pgd, addr);
-        if (pud_none(*pud) || unlikely(pud_bad(*pud)))
-                return -0x3bUL;
+static unsigned long follow_table(struct mm_struct *mm,
+                                  unsigned long address, int write)
+{
+        unsigned long *table = (unsigned long *)__pa(mm->pgd);
 
-        pmd = pmd_offset(pud, addr);
-        if (pmd_none(*pmd))
+        table = table + ((address >> 20) & 0x7ff);
+        if (unlikely(*table & _SEGMENT_ENTRY_INV))
                 return -0x10UL;
-        if (pmd_large(*pmd)) {
-                if (write && (pmd_val(*pmd) & _SEGMENT_ENTRY_RO))
-                        return -0x04UL;
-                return (pmd_val(*pmd) & HPAGE_MASK) + (addr & ~HPAGE_MASK);
-        }
-        if (unlikely(pmd_bad(*pmd)))
-                return -0x10UL;
-
-        ptep = pte_offset_map(pmd, addr);
-        if (!pte_present(*ptep))
+        table = (unsigned long *)(*table & _SEGMENT_ENTRY_ORIGIN);
+        table = table + ((address >> 12) & 0xff);
+        if (unlikely(*table & _PAGE_INVALID))
                 return -0x11UL;
-        if (write && (!pte_write(*ptep) || !pte_dirty(*ptep)))
+        if (write && (*table & _PAGE_RO))
                 return -0x04UL;
-
-        return (pte_val(*ptep) & PAGE_MASK) + (addr & ~PAGE_MASK);
+        return (*table & PAGE_MASK) + (address & ~PAGE_MASK);
 }
 
+#endif /* CONFIG_64BIT */
+
 static __always_inline size_t __user_copy_pt(unsigned long uaddr, void *kptr,
                                              size_t n, int write_user)
 {
@@ -197,7 +224,7 @@ size_t copy_to_user_pt(size_t n, void __user *to, const void *from)
 
 static size_t clear_user_pt(size_t n, void __user *to)
 {
-        void *zpage = &empty_zero_page;
+        void *zpage = (void *) empty_zero_page;
         long done, size, ret;
 
         done = 0;
diff --git a/arch/tile/kernel/setup.c b/arch/tile/kernel/setup.c
index d1e15f7b59c6..7a5aa1a7864e 100644
--- a/arch/tile/kernel/setup.c
+++ b/arch/tile/kernel/setup.c
@@ -1004,15 +1004,8 @@ void __cpuinit setup_cpu(int boot)
 
 #ifdef CONFIG_BLK_DEV_INITRD
 
-/*
- * Note that the kernel can potentially support other compression
- * techniques than gz, though we don't do so by default.  If we ever
- * decide to do so we can either look for other filename extensions,
- * or just allow a file with this name to be compressed with an
- * arbitrary compressor (somewhat counterintuitively).
- */
 static int __initdata set_initramfs_file;
-static char __initdata initramfs_file[128] = "initramfs.cpio.gz";
+static char __initdata initramfs_file[128] = "initramfs";
 
 static int __init setup_initramfs_file(char *str)
 {
@@ -1026,9 +1019,9 @@ static int __init setup_initramfs_file(char *str)
 early_param("initramfs_file", setup_initramfs_file);
 
 /*
- * We look for an "initramfs.cpio.gz" file in the hvfs.
- * If there is one, we allocate some memory for it and it will be
- * unpacked to the initramfs.
+ * We look for a file called "initramfs" in the hvfs.  If there is one, we
+ * allocate some memory for it and it will be unpacked to the initramfs.
+ * If it's compressed, the initd code will uncompress it first.
  */
 static void __init load_hv_initrd(void)
 {
@@ -1038,10 +1031,16 @@ static void __init load_hv_initrd(void)
 
         fd = hv_fs_findfile((HV_VirtAddr) initramfs_file);
         if (fd == HV_ENOENT) {
-                if (set_initramfs_file)
+                if (set_initramfs_file) {
                         pr_warning("No such hvfs initramfs file '%s'\n",
                                    initramfs_file);
-                return;
+                        return;
+                } else {
+                        /* Try old backwards-compatible name. */
+                        fd = hv_fs_findfile((HV_VirtAddr)"initramfs.cpio.gz");
+                        if (fd == HV_ENOENT)
+                                return;
+                }
         }
         BUG_ON(fd < 0);
         stat = hv_fs_fstat(fd);
diff --git a/arch/x86/boot/compressed/Makefile b/arch/x86/boot/compressed/Makefile
index 8a84501acb1b..5ef205c5f37b 100644
--- a/arch/x86/boot/compressed/Makefile
+++ b/arch/x86/boot/compressed/Makefile
@@ -4,7 +4,7 @@
 # create a compressed vmlinux image from the original vmlinux
 #
 
-targets := vmlinux.lds vmlinux vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma vmlinux.bin.xz vmlinux.bin.lzo head_$(BITS).o misc.o string.o cmdline.o early_serial_console.o piggy.o
+targets := vmlinux vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma vmlinux.bin.xz vmlinux.bin.lzo
 
 KBUILD_CFLAGS := -m$(BITS) -D__KERNEL__ $(LINUX_INCLUDE) -O2
 KBUILD_CFLAGS += -fno-strict-aliasing -fPIC
@@ -29,7 +29,6 @@ VMLINUX_OBJS = $(obj)/vmlinux.lds $(obj)/head_$(BITS).o $(obj)/misc.o \
         $(obj)/piggy.o
 
 $(obj)/eboot.o: KBUILD_CFLAGS += -fshort-wchar -mno-red-zone
-$(obj)/efi_stub_$(BITS).o: KBUILD_CLFAGS += -fshort-wchar -mno-red-zone
 
 ifeq ($(CONFIG_EFI_STUB), y)
         VMLINUX_OBJS += $(obj)/eboot.o $(obj)/efi_stub_$(BITS).o
@@ -43,7 +42,7 @@ OBJCOPYFLAGS_vmlinux.bin :=  -R .comment -S
 $(obj)/vmlinux.bin: vmlinux FORCE
         $(call if_changed,objcopy)
 
-targets += vmlinux.bin.all vmlinux.relocs
+targets += $(patsubst $(obj)/%,%,$(VMLINUX_OBJS)) vmlinux.bin.all vmlinux.relocs
 
 CMD_RELOCS = arch/x86/tools/relocs
 quiet_cmd_relocs = RELOCS  $@
diff --git a/arch/x86/include/asm/syscall.h b/arch/x86/include/asm/syscall.h
index 1ace47b62592..2e188d68397c 100644
--- a/arch/x86/include/asm/syscall.h
+++ b/arch/x86/include/asm/syscall.h
@@ -29,13 +29,13 @@ extern const unsigned long sys_call_table[];
  */
 static inline int syscall_get_nr(struct task_struct *task, struct pt_regs *regs)
 {
-        return regs->orig_ax & __SYSCALL_MASK;
+        return regs->orig_ax;
 }
 
 static inline void syscall_rollback(struct task_struct *task,
                                     struct pt_regs *regs)
 {
-        regs->ax = regs->orig_ax & __SYSCALL_MASK;
+        regs->ax = regs->orig_ax;
 }
 
 static inline long syscall_get_error(struct task_struct *task,
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index 02b51dd4e4ad..f77df1c5de6e 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -1857,7 +1857,7 @@ int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
         if (!pv_eoi_enabled(vcpu))
                 return 0;
         return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
-                                         addr);
+                                         addr, sizeof(u8));
 }
 
 void kvm_lapic_init(void)
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index f19ac0aca60d..e1721324c271 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -1823,7 +1823,8 @@ static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
                 return 0;
         }
 
-        if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
+        if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
+                                        sizeof(u32)))
                 return 1;
 
         vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
@@ -1952,12 +1953,9 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 
                 gpa_offset = data & ~(PAGE_MASK | 1);
 
-                /* Check that the address is 32-byte aligned. */
-                if (gpa_offset & (sizeof(struct pvclock_vcpu_time_info) - 1))
-                        break;
-
                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
-                     &vcpu->arch.pv_time, data & ~1ULL))
+                     &vcpu->arch.pv_time, data & ~1ULL,
+                     sizeof(struct pvclock_vcpu_time_info)))
                         vcpu->arch.pv_time_enabled = false;
                 else
                         vcpu->arch.pv_time_enabled = true;
@@ -1977,7 +1975,8 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
                         return 1;
 
                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
-                                                        data & KVM_STEAL_VALID_BITS))
+                                                data & KVM_STEAL_VALID_BITS,
+                                                sizeof(struct kvm_steal_time)))
                         return 1;
 
                 vcpu->arch.st.msr_val = data;
diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig
index 92ed9692c47e..4bf68c8d4797 100644
--- a/drivers/acpi/Kconfig
+++ b/drivers/acpi/Kconfig
@@ -396,7 +396,7 @@ config ACPI_CUSTOM_METHOD
 
 config ACPI_BGRT
         bool "Boottime Graphics Resource Table support"
-        depends on EFI
+        depends on EFI && X86
         help
           This driver adds support for exposing the ACPI Boottime Graphics
           Resource Table, which allows the operating system to obtain
diff --git a/drivers/acpi/acpi_i2c.c b/drivers/acpi/acpi_i2c.c
index 82045e3f5cac..a82c7626aa9b 100644
--- a/drivers/acpi/acpi_i2c.c
+++ b/drivers/acpi/acpi_i2c.c
@@ -90,7 +90,7 @@ void acpi_i2c_register_devices(struct i2c_adapter *adapter)
         acpi_handle handle;
         acpi_status status;
 
-        handle = ACPI_HANDLE(&adapter->dev);
+        handle = ACPI_HANDLE(adapter->dev.parent);
         if (!handle)
                 return;
 
diff --git a/drivers/acpi/pci_root.c b/drivers/acpi/pci_root.c
index 5ff173066127..6ae5e440436e 100644
--- a/drivers/acpi/pci_root.c
+++ b/drivers/acpi/pci_root.c
@@ -415,7 +415,6 @@ static int acpi_pci_root_add(struct acpi_device *device,
         struct acpi_pci_root *root;
         struct acpi_pci_driver *driver;
         u32 flags, base_flags;
-        bool is_osc_granted = false;
 
         root = kzalloc(sizeof(struct acpi_pci_root), GFP_KERNEL);
         if (!root)
@@ -476,6 +475,30 @@ static int acpi_pci_root_add(struct acpi_device *device,
         flags = base_flags = OSC_PCI_SEGMENT_GROUPS_SUPPORT;
         acpi_pci_osc_support(root, flags);
 
+        /*
+         * TBD: Need PCI interface for enumeration/configuration of roots.
+         */
+
+        mutex_lock(&acpi_pci_root_lock);
+        list_add_tail(&root->node, &acpi_pci_roots);
+        mutex_unlock(&acpi_pci_root_lock);
+
+        /*
+         * Scan the Root Bridge
+         * --------------------
+         * Must do this prior to any attempt to bind the root device, as the
+         * PCI namespace does not get created until this call is made (and
+         * thus the root bridge's pci_dev does not exist).
+         */
+        root->bus = pci_acpi_scan_root(root);
+        if (!root->bus) {
+                printk(KERN_ERR PREFIX
+                            "Bus %04x:%02x not present in PCI namespace\n",
+                            root->segment, (unsigned int)root->secondary.start);
+                result = -ENODEV;
+                goto out_del_root;
+        }
+
         /* Indicate support for various _OSC capabilities. */
         if (pci_ext_cfg_avail())
                 flags |= OSC_EXT_PCI_CONFIG_SUPPORT;
@@ -494,6 +517,7 @@ static int acpi_pci_root_add(struct acpi_device *device,
                         flags = base_flags;
                 }
         }
+
         if (!pcie_ports_disabled
             && (flags & ACPI_PCIE_REQ_SUPPORT) == ACPI_PCIE_REQ_SUPPORT) {
                 flags = OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL
@@ -514,54 +538,28 @@ static int acpi_pci_root_add(struct acpi_device *device,
                 status = acpi_pci_osc_control_set(device->handle, &flags,
                                        OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL);
                 if (ACPI_SUCCESS(status)) {
-                        is_osc_granted = true;
                         dev_info(&device->dev,
                                 "ACPI _OSC control (0x%02x) granted\n", flags);
+                        if (acpi_gbl_FADT.boot_flags & ACPI_FADT_NO_ASPM) {
+                                /*
+                                 * We have ASPM control, but the FADT indicates
+                                 * that it's unsupported. Clear it.
+                                 */
+                                pcie_clear_aspm(root->bus);
+                        }
                 } else {
-                        is_osc_granted = false;
                         dev_info(&device->dev,
                                 "ACPI _OSC request failed (%s), "
                                 "returned control mask: 0x%02x\n",
                                 acpi_format_exception(status), flags);
+                        pr_info("ACPI _OSC control for PCIe not granted, "
+                                "disabling ASPM\n");
+                        pcie_no_aspm();
                 }
         } else {
                 dev_info(&device->dev,
-                        "Unable to request _OSC control "
-                        "(_OSC support mask: 0x%02x)\n", flags);
-        }
-
-        /*
-         * TBD: Need PCI interface for enumeration/configuration of roots.
-         */
-
-        mutex_lock(&acpi_pci_root_lock);
-        list_add_tail(&root->node, &acpi_pci_roots);
-        mutex_unlock(&acpi_pci_root_lock);
-
-        /*
-         * Scan the Root Bridge
-         * --------------------
-         * Must do this prior to any attempt to bind the root device, as the
-         * PCI namespace does not get created until this call is made (and 
-         * thus the root bridge's pci_dev does not exist).
-         */
-        root->bus = pci_acpi_scan_root(root);
-        if (!root->bus) {
-                printk(KERN_ERR PREFIX
-                            "Bus %04x:%02x not present in PCI namespace\n",
-                            root->segment, (unsigned int)root->secondary.start);
-                result = -ENODEV;
-                goto out_del_root;
-        }
-
-        /* ASPM setting */
-        if (is_osc_granted) {
-                if (acpi_gbl_FADT.boot_flags & ACPI_FADT_NO_ASPM)
-                        pcie_clear_aspm(root->bus);
-        } else {
-                pr_info("ACPI _OSC control for PCIe not granted, "
-                        "disabling ASPM\n");
-                pcie_no_aspm();
+                         "Unable to request _OSC control "
+                         "(_OSC support mask: 0x%02x)\n", flags);
         }
 
         pci_acpi_add_bus_pm_notifier(device, root->bus);
diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c
index fc95308e9a11..ee255c60bdac 100644
--- a/drivers/acpi/processor_idle.c
+++ b/drivers/acpi/processor_idle.c
@@ -66,7 +66,8 @@ module_param(latency_factor, uint, 0644);
 
 static DEFINE_PER_CPU(struct cpuidle_device *, acpi_cpuidle_device);
 
-static struct acpi_processor_cx *acpi_cstate[CPUIDLE_STATE_MAX];
+static DEFINE_PER_CPU(struct acpi_processor_cx * [CPUIDLE_STATE_MAX],
+                                                                acpi_cstate);
 
 static int disabled_by_idle_boot_param(void)
 {
@@ -722,7 +723,7 @@ static int acpi_idle_enter_c1(struct cpuidle_device *dev,
                 struct cpuidle_driver *drv, int index)
 {
         struct acpi_processor *pr;
-        struct acpi_processor_cx *cx = acpi_cstate[index];
+        struct acpi_processor_cx *cx = per_cpu(acpi_cstate[index], dev->cpu);
 
         pr = __this_cpu_read(processors);
 
@@ -745,7 +746,7 @@ static int acpi_idle_enter_c1(struct cpuidle_device *dev,
  */
 static int acpi_idle_play_dead(struct cpuidle_device *dev, int index)
 {
-        struct acpi_processor_cx *cx = acpi_cstate[index];
+        struct acpi_processor_cx *cx = per_cpu(acpi_cstate[index], dev->cpu);
 
         ACPI_FLUSH_CPU_CACHE();
 
@@ -775,7 +776,7 @@ static int acpi_idle_enter_simple(struct cpuidle_device *dev,
                 struct cpuidle_driver *drv, int index)
 {
         struct acpi_processor *pr;
-        struct acpi_processor_cx *cx = acpi_cstate[index];
+        struct acpi_processor_cx *cx = per_cpu(acpi_cstate[index], dev->cpu);
 
         pr = __this_cpu_read(processors);
 
@@ -833,7 +834,7 @@ static int acpi_idle_enter_bm(struct cpuidle_device *dev,
                 struct cpuidle_driver *drv, int index)
 {
         struct acpi_processor *pr;
-        struct acpi_processor_cx *cx = acpi_cstate[index];
+        struct acpi_processor_cx *cx = per_cpu(acpi_cstate[index], dev->cpu);
 
         pr = __this_cpu_read(processors);
 
@@ -960,7 +961,7 @@ static int acpi_processor_setup_cpuidle_cx(struct acpi_processor *pr,
                     !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED))
                         continue;
 #endif
-                acpi_cstate[count] = cx;
+                per_cpu(acpi_cstate[count], dev->cpu) = cx;
 
                 count++;
                 if (count == CPUIDLE_STATE_MAX)
diff --git a/drivers/ata/pata_arasan_cf.c b/drivers/ata/pata_arasan_cf.c
index 405022d302c3..7638121cb5d1 100644
--- a/drivers/ata/pata_arasan_cf.c
+++ b/drivers/ata/pata_arasan_cf.c
@@ -209,8 +209,6 @@ struct arasan_cf_dev {
         struct dma_chan *dma_chan;
         /* Mask for DMA transfers */
         dma_cap_mask_t mask;
-        /* dma channel private data */
-        void *dma_priv;
         /* DMA transfer work */
         struct work_struct work;
         /* DMA delayed finish work */
@@ -308,6 +306,7 @@ static void cf_card_detect(struct arasan_cf_dev *acdev, bool hotplugged)
 static int cf_init(struct arasan_cf_dev *acdev)
 {
         struct arasan_cf_pdata *pdata = dev_get_platdata(acdev->host->dev);
+        unsigned int if_clk;
         unsigned long flags;
         int ret = 0;
 
@@ -325,8 +324,12 @@ static int cf_init(struct arasan_cf_dev *acdev)
 
         spin_lock_irqsave(&acdev->host->lock, flags);
         /* configure CF interface clock */
-        writel((pdata->cf_if_clk <= CF_IF_CLK_200M) ? pdata->cf_if_clk :
-                        CF_IF_CLK_166M, acdev->vbase + CLK_CFG);
+        /* TODO: read from device tree */
+        if_clk = CF_IF_CLK_166M;
+        if (pdata && pdata->cf_if_clk <= CF_IF_CLK_200M)
+                if_clk = pdata->cf_if_clk;
+
+        writel(if_clk, acdev->vbase + CLK_CFG);
 
         writel(TRUE_IDE_MODE | CFHOST_ENB, acdev->vbase + OP_MODE);
         cf_interrupt_enable(acdev, CARD_DETECT_IRQ, 1);
@@ -357,12 +360,6 @@ static void dma_callback(void *dev)
         complete(&acdev->dma_completion);
 }
 
-static bool filter(struct dma_chan *chan, void *slave)
-{
-        chan->private = slave;
-        return true;
-}
-
 static inline void dma_complete(struct arasan_cf_dev *acdev)
 {
         struct ata_queued_cmd *qc = acdev->qc;
@@ -530,8 +527,7 @@ static void data_xfer(struct work_struct *work)
 
         /* request dma channels */
         /* dma_request_channel may sleep, so calling from process context */
-        acdev->dma_chan = dma_request_channel(acdev->mask, filter,
-                        acdev->dma_priv);
+        acdev->dma_chan = dma_request_slave_channel(acdev->host->dev, "data");
         if (!acdev->dma_chan) {
                 dev_err(acdev->host->dev, "Unable to get dma_chan\n");
                 goto chan_request_fail;
@@ -798,6 +794,7 @@ static int arasan_cf_probe(struct platform_device *pdev)
         struct ata_host *host;
         struct ata_port *ap;
         struct resource *res;
+        u32 quirk;
         irq_handler_t irq_handler = NULL;
         int ret = 0;
 
@@ -817,12 +814,17 @@ static int arasan_cf_probe(struct platform_device *pdev)
                 return -ENOMEM;
         }
 
+        if (pdata)
+                quirk = pdata->quirk;
+        else
+                quirk = CF_BROKEN_UDMA; /* as it is on spear1340 */
+
         /* if irq is 0, support only PIO */
         acdev->irq = platform_get_irq(pdev, 0);
         if (acdev->irq)
                 irq_handler = arasan_cf_interrupt;
         else
-                pdata->quirk |= CF_BROKEN_MWDMA | CF_BROKEN_UDMA;
+                quirk |= CF_BROKEN_MWDMA | CF_BROKEN_UDMA;
 
         acdev->pbase = res->start;
         acdev->vbase = devm_ioremap_nocache(&pdev->dev, res->start,
@@ -859,17 +861,16 @@ static int arasan_cf_probe(struct platform_device *pdev)
         INIT_WORK(&acdev->work, data_xfer);
         INIT_DELAYED_WORK(&acdev->dwork, delayed_finish);
         dma_cap_set(DMA_MEMCPY, acdev->mask);
-        acdev->dma_priv = pdata->dma_priv;
 
         /* Handle platform specific quirks */
-        if (pdata->quirk) {
-                if (pdata->quirk & CF_BROKEN_PIO) {
+        if (quirk) {
+                if (quirk & CF_BROKEN_PIO) {
                         ap->ops->set_piomode = NULL;
                         ap->pio_mask = 0;
                 }
-                if (pdata->quirk & CF_BROKEN_MWDMA)
+                if (quirk & CF_BROKEN_MWDMA)
                         ap->mwdma_mask = 0;
-                if (pdata->quirk & CF_BROKEN_UDMA)
+                if (quirk & CF_BROKEN_UDMA)
                         ap->udma_mask = 0;
         }
         ap->flags |= ATA_FLAG_PIO_POLLING | ATA_FLAG_NO_ATAPI;
diff --git a/drivers/base/power/qos.c b/drivers/base/power/qos.c
index 5f74587ef258..71671c42ef45 100644
--- a/drivers/base/power/qos.c
+++ b/drivers/base/power/qos.c
@@ -46,6 +46,7 @@
 #include "power.h"
 
 static DEFINE_MUTEX(dev_pm_qos_mtx);
+static DEFINE_MUTEX(dev_pm_qos_sysfs_mtx);
 
 static BLOCKING_NOTIFIER_HEAD(dev_pm_notifiers);
 
@@ -216,12 +217,17 @@ void dev_pm_qos_constraints_destroy(struct device *dev)
         struct pm_qos_constraints *c;
         struct pm_qos_flags *f;
 
-        mutex_lock(&dev_pm_qos_mtx);
+        mutex_lock(&dev_pm_qos_sysfs_mtx);
 
         /*
          * If the device's PM QoS resume latency limit or PM QoS flags have been
          * exposed to user space, they have to be hidden at this point.
          */
+        pm_qos_sysfs_remove_latency(dev);
+        pm_qos_sysfs_remove_flags(dev);
+
+        mutex_lock(&dev_pm_qos_mtx);
+
         __dev_pm_qos_hide_latency_limit(dev);
         __dev_pm_qos_hide_flags(dev);
 
@@ -254,6 +260,8 @@ void dev_pm_qos_constraints_destroy(struct device *dev)
 
  out:
         mutex_unlock(&dev_pm_qos_mtx);
+
+        mutex_unlock(&dev_pm_qos_sysfs_mtx);
 }
 
 /**
@@ -558,6 +566,14 @@ static void __dev_pm_qos_drop_user_request(struct device *dev,
         kfree(req);
 }
 
+static void dev_pm_qos_drop_user_request(struct device *dev,
+                                         enum dev_pm_qos_req_type type)
+{
+        mutex_lock(&dev_pm_qos_mtx);
+        __dev_pm_qos_drop_user_request(dev, type);
+        mutex_unlock(&dev_pm_qos_mtx);
+}
+
 /**
  * dev_pm_qos_expose_latency_limit - Expose PM QoS latency limit to user space.
  * @dev: Device whose PM QoS latency limit is to be exposed to user space.
@@ -581,6 +597,8 @@ int dev_pm_qos_expose_latency_limit(struct device *dev, s32 value)
                 return ret;
         }
 
+        mutex_lock(&dev_pm_qos_sysfs_mtx);
+
         mutex_lock(&dev_pm_qos_mtx);
 
         if (IS_ERR_OR_NULL(dev->power.qos))
@@ -591,26 +609,27 @@ int dev_pm_qos_expose_latency_limit(struct device *dev, s32 value)
         if (ret < 0) {
                 __dev_pm_qos_remove_request(req);
                 kfree(req);
+                mutex_unlock(&dev_pm_qos_mtx);
                 goto out;
         }
-
         dev->power.qos->latency_req = req;
+
+        mutex_unlock(&dev_pm_qos_mtx);
+
         ret = pm_qos_sysfs_add_latency(dev);
         if (ret)
-                __dev_pm_qos_drop_user_request(dev, DEV_PM_QOS_LATENCY);
+                dev_pm_qos_drop_user_request(dev, DEV_PM_QOS_LATENCY);
 
  out:
-        mutex_unlock(&dev_pm_qos_mtx);
+        mutex_unlock(&dev_pm_qos_sysfs_mtx);
         return ret;
 }
 EXPORT_SYMBOL_GPL(dev_pm_qos_expose_latency_limit);
 
 static void __dev_pm_qos_hide_latency_limit(struct device *dev)
 {
-        if (!IS_ERR_OR_NULL(dev->power.qos) && dev->power.qos->latency_req) {
-                pm_qos_sysfs_remove_latency(dev);
+        if (!IS_ERR_OR_NULL(dev->power.qos) && dev->power.qos->latency_req)
                 __dev_pm_qos_drop_user_request(dev, DEV_PM_QOS_LATENCY);
-        }
 }
 
 /**
@@ -619,9 +638,15 @@ static void __dev_pm_qos_hide_latency_limit(struct device *dev)
  */
 void dev_pm_qos_hide_latency_limit(struct device *dev)
 {
+        mutex_lock(&dev_pm_qos_sysfs_mtx);
+
+        pm_qos_sysfs_remove_latency(dev);
+
         mutex_lock(&dev_pm_qos_mtx);
         __dev_pm_qos_hide_latency_limit(dev);
         mutex_unlock(&dev_pm_qos_mtx);
+
+        mutex_unlock(&dev_pm_qos_sysfs_mtx);
 }
 EXPORT_SYMBOL_GPL(dev_pm_qos_hide_latency_limit);
 
@@ -649,6 +674,8 @@ int dev_pm_qos_expose_flags(struct device *dev, s32 val)
         }
 
         pm_runtime_get_sync(dev);
+        mutex_lock(&dev_pm_qos_sysfs_mtx);
+
         mutex_lock(&dev_pm_qos_mtx);
 
         if (IS_ERR_OR_NULL(dev->power.qos))
@@ -659,16 +686,19 @@ int dev_pm_qos_expose_flags(struct device *dev, s32 val)
         if (ret < 0) {
                 __dev_pm_qos_remove_request(req);
                 kfree(req);
+                mutex_unlock(&dev_pm_qos_mtx);
                 goto out;
         }
-
         dev->power.qos->flags_req = req;
+
+        mutex_unlock(&dev_pm_qos_mtx);
+
         ret = pm_qos_sysfs_add_flags(dev);
         if (ret)
-                __dev_pm_qos_drop_user_request(dev, DEV_PM_QOS_FLAGS);
+                dev_pm_qos_drop_user_request(dev, DEV_PM_QOS_FLAGS);
 
  out:
-        mutex_unlock(&dev_pm_qos_mtx);
+        mutex_unlock(&dev_pm_qos_sysfs_mtx);
         pm_runtime_put(dev);
         return ret;
 }
@@ -676,10 +706,8 @@ EXPORT_SYMBOL_GPL(dev_pm_qos_expose_flags);
 
 static void __dev_pm_qos_hide_flags(struct device *dev)
 {
-        if (!IS_ERR_OR_NULL(dev->power.qos) && dev->power.qos->flags_req) {
-                pm_qos_sysfs_remove_flags(dev);
+        if (!IS_ERR_OR_NULL(dev->power.qos) && dev->power.qos->flags_req)
                 __dev_pm_qos_drop_user_request(dev, DEV_PM_QOS_FLAGS);
-        }
 }
 
 /**
@@ -689,9 +717,15 @@ static void __dev_pm_qos_hide_flags(struct device *dev)
 void dev_pm_qos_hide_flags(struct device *dev)
 {
         pm_runtime_get_sync(dev);
+        mutex_lock(&dev_pm_qos_sysfs_mtx);
+
+        pm_qos_sysfs_remove_flags(dev);
+
         mutex_lock(&dev_pm_qos_mtx);
         __dev_pm_qos_hide_flags(dev);
         mutex_unlock(&dev_pm_qos_mtx);
+
+        mutex_unlock(&dev_pm_qos_sysfs_mtx);
         pm_runtime_put(dev);
 }
 EXPORT_SYMBOL_GPL(dev_pm_qos_hide_flags);
diff --git a/drivers/base/regmap/regcache-rbtree.c b/drivers/base/regmap/regcache-rbtree.c
index e6732cf7c06e..79f4fca9877a 100644
--- a/drivers/base/regmap/regcache-rbtree.c
+++ b/drivers/base/regmap/regcache-rbtree.c
@@ -398,7 +398,7 @@ static int regcache_rbtree_sync(struct regmap *map, unsigned int min,
                         base = 0;
 
                 if (max < rbnode->base_reg + rbnode->blklen)
-                        end = rbnode->base_reg + rbnode->blklen - max;
+                        end = max - rbnode->base_reg + 1;
                 else
                         end = rbnode->blklen;
 
diff --git a/drivers/base/regmap/regmap.c b/drivers/base/regmap/regmap.c
index 3d2367501fd0..d34adef1e63e 100644
--- a/drivers/base/regmap/regmap.c
+++ b/drivers/base/regmap/regmap.c
@@ -710,12 +710,12 @@ skip_format_initialization:
                 }
         }
 
+        regmap_debugfs_init(map, config->name);
+
         ret = regcache_init(map, config);
         if (ret != 0)
                 goto err_range;
 
-        regmap_debugfs_init(map, config->name);
-
         /* Add a devres resource for dev_get_regmap() */
         m = devres_alloc(dev_get_regmap_release, sizeof(*m), GFP_KERNEL);
         if (!m) {
@@ -943,8 +943,7 @@ static int _regmap_raw_write(struct regmap *map, unsigned int reg,
                 unsigned int ival;
                 int val_bytes = map->format.val_bytes;
                 for (i = 0; i < val_len / val_bytes; i++) {
-                        memcpy(map->work_buf, val + (i * val_bytes), val_bytes);
-                        ival = map->format.parse_val(map->work_buf);
+                        ival = map->format.parse_val(val + (i * val_bytes));
                         ret = regcache_write(map, reg + (i * map->reg_stride),
                                              ival);
                         if (ret) {
@@ -1036,6 +1035,8 @@ static int _regmap_raw_write(struct regmap *map, unsigned int reg,
                         kfree(async->work_buf);
                         kfree(async);
                 }
+
+                return ret;
         }
 
         trace_regmap_hw_write_start(map->dev, reg,
diff --git a/drivers/block/aoe/aoecmd.c b/drivers/block/aoe/aoecmd.c
index 25ef5c014fca..92b6d7c51e39 100644
--- a/drivers/block/aoe/aoecmd.c
+++ b/drivers/block/aoe/aoecmd.c
@@ -51,8 +51,9 @@ new_skb(ulong len)
 {
         struct sk_buff *skb;
 
-        skb = alloc_skb(len, GFP_ATOMIC);
+        skb = alloc_skb(len + MAX_HEADER, GFP_ATOMIC);
         if (skb) {
+                skb_reserve(skb, MAX_HEADER);
                 skb_reset_mac_header(skb);
                 skb_reset_network_header(skb);
                 skb->protocol = __constant_htons(ETH_P_AOE);
diff --git a/drivers/block/loop.c b/drivers/block/loop.c
index fe5f6403417f..2c127f9c3f3b 100644
--- a/drivers/block/loop.c
+++ b/drivers/block/loop.c
@@ -922,6 +922,11 @@ static int loop_set_fd(struct loop_device *lo, fmode_t mode,
                 lo->lo_flags |= LO_FLAGS_PARTSCAN;
         if (lo->lo_flags & LO_FLAGS_PARTSCAN)
                 ioctl_by_bdev(bdev, BLKRRPART, 0);
+
+        /* Grab the block_device to prevent its destruction after we
+         * put /dev/loopXX inode. Later in loop_clr_fd() we bdput(bdev).
+         */
+        bdgrab(bdev);
         return 0;
 
 out_clr:
@@ -1031,8 +1036,10 @@ static int loop_clr_fd(struct loop_device *lo)
         memset(lo->lo_encrypt_key, 0, LO_KEY_SIZE);
         memset(lo->lo_crypt_name, 0, LO_NAME_SIZE);
         memset(lo->lo_file_name, 0, LO_NAME_SIZE);
-        if (bdev)
+        if (bdev) {
+                bdput(bdev);
                 invalidate_bdev(bdev);
+        }
         set_capacity(lo->lo_disk, 0);
         loop_sysfs_exit(lo);
         if (bdev) {
diff --git a/drivers/char/hw_random/core.c b/drivers/char/hw_random/core.c
index 69ae5972713c..a0f7724852eb 100644
--- a/drivers/char/hw_random/core.c
+++ b/drivers/char/hw_random/core.c
@@ -380,6 +380,15 @@ void hwrng_unregister(struct hwrng *rng)
 }
 EXPORT_SYMBOL_GPL(hwrng_unregister);
 
+static void __exit hwrng_exit(void)
+{
+        mutex_lock(&rng_mutex);
+        BUG_ON(current_rng);
+        kfree(rng_buffer);
+        mutex_unlock(&rng_mutex);
+}
+
+module_exit(hwrng_exit);
 
 MODULE_DESCRIPTION("H/W Random Number Generator (RNG) driver");
 MODULE_LICENSE("GPL");
diff --git a/drivers/char/virtio_console.c b/drivers/char/virtio_console.c
index e905d5f53051..ce5f3fc25d6d 100644
--- a/drivers/char/virtio_console.c
+++ b/drivers/char/virtio_console.c
@@ -149,7 +149,8 @@ struct ports_device {
         spinlock_t ports_lock;
 
         /* To protect the vq operations for the control channel */
-        spinlock_t cvq_lock;
+        spinlock_t c_ivq_lock;
+        spinlock_t c_ovq_lock;
 
         /* The current config space is stored here */
         struct virtio_console_config config;
@@ -569,11 +570,14 @@ static ssize_t __send_control_msg(struct ports_device *portdev, u32 port_id,
         vq = portdev->c_ovq;
 
         sg_init_one(sg, &cpkt, sizeof(cpkt));
+
+        spin_lock(&portdev->c_ovq_lock);
         if (virtqueue_add_buf(vq, sg, 1, 0, &cpkt, GFP_ATOMIC) == 0) {
                 virtqueue_kick(vq);
                 while (!virtqueue_get_buf(vq, &len))
                         cpu_relax();
         }
+        spin_unlock(&portdev->c_ovq_lock);
         return 0;
 }
 
@@ -1436,7 +1440,7 @@ static int add_port(struct ports_device *portdev, u32 id)
                  * rproc_serial does not want the console port, only
                  * the generic port implementation.
                  */
-                port->host_connected = port->guest_connected = true;
+                port->host_connected = true;
         else if (!use_multiport(port->portdev)) {
                 /*
                  * If we're not using multiport support,
@@ -1709,23 +1713,23 @@ static void control_work_handler(struct work_struct *work)
         portdev = container_of(work, struct ports_device, control_work);
         vq = portdev->c_ivq;
 
-        spin_lock(&portdev->cvq_lock);
+        spin_lock(&portdev->c_ivq_lock);
         while ((buf = virtqueue_get_buf(vq, &len))) {
-                spin_unlock(&portdev->cvq_lock);
+                spin_unlock(&portdev->c_ivq_lock);
 
                 buf->len = len;
                 buf->offset = 0;
 
                 handle_control_message(portdev, buf);
 
-                spin_lock(&portdev->cvq_lock);
+                spin_lock(&portdev->c_ivq_lock);
                 if (add_inbuf(portdev->c_ivq, buf) < 0) {
                         dev_warn(&portdev->vdev->dev,
                                  "Error adding buffer to queue\n");
                         free_buf(buf, false);
                 }
         }
-        spin_unlock(&portdev->cvq_lock);
+        spin_unlock(&portdev->c_ivq_lock);
 }
 
 static void out_intr(struct virtqueue *vq)
@@ -1752,13 +1756,23 @@ static void in_intr(struct virtqueue *vq)
         port->inbuf = get_inbuf(port);
 
         /*
-         * Don't queue up data when port is closed.  This condition
+         * Normally the port should not accept data when the port is
+         * closed. For generic serial ports, the host won't (shouldn't)
+         * send data till the guest is connected. But this condition
          * can be reached when a console port is not yet connected (no
-         * tty is spawned) and the host sends out data to console
-         * ports.  For generic serial ports, the host won't
-         * (shouldn't) send data till the guest is connected.
+         * tty is spawned) and the other side sends out data over the
+         * vring, or when a remote devices start sending data before
+         * the ports are opened.
+         *
+         * A generic serial port will discard data if not connected,
+         * while console ports and rproc-serial ports accepts data at
+         * any time. rproc-serial is initiated with guest_connected to
+         * false because port_fops_open expects this. Console ports are
+         * hooked up with an HVC console and is initialized with
+         * guest_connected to true.
          */
-        if (!port->guest_connected)
+
+        if (!port->guest_connected && !is_rproc_serial(port->portdev->vdev))
                 discard_port_data(port);
 
         spin_unlock_irqrestore(&port->inbuf_lock, flags);
@@ -1986,10 +2000,12 @@ static int virtcons_probe(struct virtio_device *vdev)
         if (multiport) {
                 unsigned int nr_added_bufs;
 
-                spin_lock_init(&portdev->cvq_lock);
+                spin_lock_init(&portdev->c_ivq_lock);
+                spin_lock_init(&portdev->c_ovq_lock);
                 INIT_WORK(&portdev->control_work, &control_work_handler);
 
-                nr_added_bufs = fill_queue(portdev->c_ivq, &portdev->cvq_lock);
+                nr_added_bufs = fill_queue(portdev->c_ivq,
+                                           &portdev->c_ivq_lock);
                 if (!nr_added_bufs) {
                         dev_err(&vdev->dev,
                                 "Error allocating buffers for control queue\n");
@@ -2140,7 +2156,7 @@ static int virtcons_restore(struct virtio_device *vdev)
                 return ret;
 
         if (use_multiport(portdev))
-                fill_queue(portdev->c_ivq, &portdev->cvq_lock);
+                fill_queue(portdev->c_ivq, &portdev->c_ivq_lock);
 
         list_for_each_entry(port, &portdev->ports, list) {
                 port->in_vq = portdev->in_vqs[port->id];
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index a47e6ee98b8c..a64caefdba12 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -63,6 +63,14 @@ config CLK_TWL6040
           McPDM. McPDM module is using the external bit clock on the McPDM bus
           as functional clock.
 
+config COMMON_CLK_AXI_CLKGEN
+        tristate "AXI clkgen driver"
+        depends on ARCH_ZYNQ || MICROBLAZE
+        help
+        ---help---
+          Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx
+          FPGAs. It is commonly used in Analog Devices' reference designs.
+
 endmenu
 
 source "drivers/clk/mvebu/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 300d4775d926..79e98e416724 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_COMMON_CLK)	+= clk-fixed-factor.o
 obj-$(CONFIG_COMMON_CLK)        += clk-fixed-rate.o
 obj-$(CONFIG_COMMON_CLK)        += clk-gate.o
 obj-$(CONFIG_COMMON_CLK)        += clk-mux.o
+obj-$(CONFIG_COMMON_CLK)        += clk-composite.o
 
 # SoCs specific
 obj-$(CONFIG_ARCH_BCM2835)      += clk-bcm2835.o
@@ -23,6 +24,7 @@ ifeq ($(CONFIG_COMMON_CLK), y)
 obj-$(CONFIG_ARCH_MMP)          += mmp/
 endif
 obj-$(CONFIG_MACH_LOONGSON1)    += clk-ls1x.o
+obj-$(CONFIG_ARCH_SUNXI)        += sunxi/
 obj-$(CONFIG_ARCH_U8500)        += ux500/
 obj-$(CONFIG_ARCH_VT8500)       += clk-vt8500.o
 obj-$(CONFIG_ARCH_ZYNQ)         += clk-zynq.o
@@ -31,6 +33,7 @@ obj-$(CONFIG_ARCH_TEGRA)	+= tegra/
 obj-$(CONFIG_X86)               += x86/
 
 # Chip specific
+obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN) += clk-axi-clkgen.o
 obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
 obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o
 obj-$(CONFIG_CLK_TWL6040)       += clk-twl6040.o
diff --git a/drivers/clk/clk-axi-clkgen.c b/drivers/clk/clk-axi-clkgen.c
new file mode 100644
index 000000000000..8137327847c3
--- /dev/null
+++ b/drivers/clk/clk-axi-clkgen.c
@@ -0,0 +1,331 @@
+/*
+ * AXI clkgen driver
+ *
+ * Copyright 2012-2013 Analog Devices Inc.
+ *  Author: Lars-Peter Clausen <lars@metafoo.de>
+ *
+ * Licensed under the GPL-2.
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <linux/clk-provider.h>
+#include <linux/clk.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/module.h>
+#include <linux/err.h>
+
+#define AXI_CLKGEN_REG_UPDATE_ENABLE    0x04
+#define AXI_CLKGEN_REG_CLK_OUT1         0x08
+#define AXI_CLKGEN_REG_CLK_OUT2         0x0c
+#define AXI_CLKGEN_REG_CLK_DIV          0x10
+#define AXI_CLKGEN_REG_CLK_FB1          0x14
+#define AXI_CLKGEN_REG_CLK_FB2          0x18
+#define AXI_CLKGEN_REG_LOCK1            0x1c
+#define AXI_CLKGEN_REG_LOCK2            0x20
+#define AXI_CLKGEN_REG_LOCK3            0x24
+#define AXI_CLKGEN_REG_FILTER1          0x28
+#define AXI_CLKGEN_REG_FILTER2          0x2c
+
+struct axi_clkgen {
+        void __iomem *base;
+        struct clk_hw clk_hw;
+};
+
+static uint32_t axi_clkgen_lookup_filter(unsigned int m)
+{
+        switch (m) {
+        case 0:
+                return 0x01001990;
+        case 1:
+                return 0x01001190;
+        case 2:
+                return 0x01009890;
+        case 3:
+                return 0x01001890;
+        case 4:
+                return 0x01008890;
+        case 5 ... 8:
+                return 0x01009090;
+        case 9 ... 11:
+                return 0x01000890;
+        case 12:
+                return 0x08009090;
+        case 13 ... 22:
+                return 0x01001090;
+        case 23 ... 36:
+                return 0x01008090;
+        case 37 ... 46:
+                return 0x08001090;
+        default:
+                return 0x08008090;
+        }
+}
+
+static const uint32_t axi_clkgen_lock_table[] = {
+        0x060603e8, 0x060603e8, 0x080803e8, 0x0b0b03e8,
+        0x0e0e03e8, 0x111103e8, 0x131303e8, 0x161603e8,
+        0x191903e8, 0x1c1c03e8, 0x1f1f0384, 0x1f1f0339,
+        0x1f1f02ee, 0x1f1f02bc, 0x1f1f028a, 0x1f1f0271,
+        0x1f1f023f, 0x1f1f0226, 0x1f1f020d, 0x1f1f01f4,
+        0x1f1f01db, 0x1f1f01c2, 0x1f1f01a9, 0x1f1f0190,
+        0x1f1f0190, 0x1f1f0177, 0x1f1f015e, 0x1f1f015e,
+        0x1f1f0145, 0x1f1f0145, 0x1f1f012c, 0x1f1f012c,
+        0x1f1f012c, 0x1f1f0113, 0x1f1f0113, 0x1f1f0113,
+};
+
+static uint32_t axi_clkgen_lookup_lock(unsigned int m)
+{
+        if (m < ARRAY_SIZE(axi_clkgen_lock_table))
+                return axi_clkgen_lock_table[m];
+        return 0x1f1f00fa;
+}
+
+static const unsigned int fpfd_min = 10000;
+static const unsigned int fpfd_max = 300000;
+static const unsigned int fvco_min = 600000;
+static const unsigned int fvco_max = 1200000;
+
+static void axi_clkgen_calc_params(unsigned long fin, unsigned long fout,
+        unsigned int *best_d, unsigned int *best_m, unsigned int *best_dout)
+{
+        unsigned long d, d_min, d_max, _d_min, _d_max;
+        unsigned long m, m_min, m_max;
+        unsigned long f, dout, best_f, fvco;
+
+        fin /= 1000;
+        fout /= 1000;
+
+        best_f = ULONG_MAX;
+        *best_d = 0;
+        *best_m = 0;
+        *best_dout = 0;
+
+        d_min = max_t(unsigned long, DIV_ROUND_UP(fin, fpfd_max), 1);
+        d_max = min_t(unsigned long, fin / fpfd_min, 80);
+
+        m_min = max_t(unsigned long, DIV_ROUND_UP(fvco_min, fin) * d_min, 1);
+        m_max = min_t(unsigned long, fvco_max * d_max / fin, 64);
+
+        for (m = m_min; m <= m_max; m++) {
+                _d_min = max(d_min, DIV_ROUND_UP(fin * m, fvco_max));
+                _d_max = min(d_max, fin * m / fvco_min);
+
+                for (d = _d_min; d <= _d_max; d++) {
+                        fvco = fin * m / d;
+
+                        dout = DIV_ROUND_CLOSEST(fvco, fout);
+                        dout = clamp_t(unsigned long, dout, 1, 128);
+                        f = fvco / dout;
+                        if (abs(f - fout) < abs(best_f - fout)) {
+                                best_f = f;
+                                *best_d = d;
+                                *best_m = m;
+                                *best_dout = dout;
+                                if (best_f == fout)
+                                        return;
+                        }
+                }
+        }
+}
+
+static void axi_clkgen_calc_clk_params(unsigned int divider, unsigned int *low,
+        unsigned int *high, unsigned int *edge, unsigned int *nocount)
+{
+        if (divider == 1)
+                *nocount = 1;
+        else
+                *nocount = 0;
+
+        *high = divider / 2;
+        *edge = divider % 2;
+        *low = divider - *high;
+}
+
+static void axi_clkgen_write(struct axi_clkgen *axi_clkgen,
+        unsigned int reg, unsigned int val)
+{
+        writel(val, axi_clkgen->base + reg);
+}
+
+static void axi_clkgen_read(struct axi_clkgen *axi_clkgen,
+        unsigned int reg, unsigned int *val)
+{
+        *val = readl(axi_clkgen->base + reg);
+}
+
+static struct axi_clkgen *clk_hw_to_axi_clkgen(struct clk_hw *clk_hw)
+{
+        return container_of(clk_hw, struct axi_clkgen, clk_hw);
+}
+
+static int axi_clkgen_set_rate(struct clk_hw *clk_hw,
+        unsigned long rate, unsigned long parent_rate)
+{
+        struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
+        unsigned int d, m, dout;
+        unsigned int nocount;
+        unsigned int high;
+        unsigned int edge;
+        unsigned int low;
+        uint32_t filter;
+        uint32_t lock;
+
+        if (parent_rate == 0 || rate == 0)
+                return -EINVAL;
+
+        axi_clkgen_calc_params(parent_rate, rate, &d, &m, &dout);
+
+        if (d == 0 || dout == 0 || m == 0)
+                return -EINVAL;
+
+        filter = axi_clkgen_lookup_filter(m - 1);
+        lock = axi_clkgen_lookup_lock(m - 1);
+
+        axi_clkgen_write(axi_clkgen, AXI_CLKGEN_REG_UPDATE_ENABLE, 0);
+
+        axi_clkgen_calc_clk_params(dout, &low, &high, &edge, &nocount);
+        axi_clkgen_write(axi_clkgen, AXI_CLKGEN_REG_CLK_OUT1,
+                (high << 6) | low);
+        axi_clkgen_write(axi_clkgen, AXI_CLKGEN_REG_CLK_OUT2,
+                (edge << 7) | (nocount << 6));
+
+        axi_clkgen_calc_clk_params(d, &low, &high, &edge, &nocount);
+        axi_clkgen_write(axi_clkgen, AXI_CLKGEN_REG_CLK_DIV,
+                (edge << 13) | (nocount << 12) | (high << 6) | low);
+
+        axi_clkgen_calc_clk_params(m, &low, &high, &edge, &nocount);
+        axi_clkgen_write(axi_clkgen, AXI_CLKGEN_REG_CLK_FB1,
+                (high << 6) | low);
+        axi_clkgen_write(axi_clkgen, AXI_CLKGEN_REG_CLK_FB2,
+                (edge << 7) | (nocount << 6));
+
+        axi_clkgen_write(axi_clkgen, AXI_CLKGEN_REG_LOCK1, lock & 0x3ff);
+        axi_clkgen_write(axi_clkgen, AXI_CLKGEN_REG_LOCK2,
+                (((lock >> 16) & 0x1f) << 10) | 0x1);
+        axi_clkgen_write(axi_clkgen, AXI_CLKGEN_REG_LOCK3,
+                (((lock >> 24) & 0x1f) << 10) | 0x3e9);
+        axi_clkgen_write(axi_clkgen, AXI_CLKGEN_REG_FILTER1, filter >> 16);
+        axi_clkgen_write(axi_clkgen, AXI_CLKGEN_REG_FILTER2, filter);
+
+        axi_clkgen_write(axi_clkgen, AXI_CLKGEN_REG_UPDATE_ENABLE, 1);
+
+        return 0;
+}
+
+static long axi_clkgen_round_rate(struct clk_hw *hw, unsigned long rate,
+        unsigned long *parent_rate)
+{
+        unsigned int d, m, dout;
+
+        axi_clkgen_calc_params(*parent_rate, rate, &d, &m, &dout);
+
+        if (d == 0 || dout == 0 || m == 0)
+                return -EINVAL;
+
+        return *parent_rate / d * m / dout;
+}
+
+static unsigned long axi_clkgen_recalc_rate(struct clk_hw *clk_hw,
+        unsigned long parent_rate)
+{
+        struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
+        unsigned int d, m, dout;
+        unsigned int reg;
+        unsigned long long tmp;
+
+        axi_clkgen_read(axi_clkgen, AXI_CLKGEN_REG_CLK_OUT1, &reg);
+        dout = (reg & 0x3f) + ((reg >> 6) & 0x3f);
+        axi_clkgen_read(axi_clkgen, AXI_CLKGEN_REG_CLK_DIV, &reg);
+        d = (reg & 0x3f) + ((reg >> 6) & 0x3f);
+        axi_clkgen_read(axi_clkgen, AXI_CLKGEN_REG_CLK_FB1, &reg);
+        m = (reg & 0x3f) + ((reg >> 6) & 0x3f);
+
+        if (d == 0 || dout == 0)
+                return 0;
+
+        tmp = (unsigned long long)(parent_rate / d) * m;
+        do_div(tmp, dout);
+
+        if (tmp > ULONG_MAX)
+                return ULONG_MAX;
+
+        return tmp;
+}
+
+static const struct clk_ops axi_clkgen_ops = {
+        .recalc_rate = axi_clkgen_recalc_rate,
+        .round_rate = axi_clkgen_round_rate,
+        .set_rate = axi_clkgen_set_rate,
+};
+
+static int axi_clkgen_probe(struct platform_device *pdev)
+{
+        struct axi_clkgen *axi_clkgen;
+        struct clk_init_data init;
+        const char *parent_name;
+        const char *clk_name;
+        struct resource *mem;
+        struct clk *clk;
+
+        axi_clkgen = devm_kzalloc(&pdev->dev, sizeof(*axi_clkgen), GFP_KERNEL);
+        if (!axi_clkgen)
+                return -ENOMEM;
+
+        mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        axi_clkgen->base = devm_ioremap_resource(&pdev->dev, mem);
+        if (IS_ERR(axi_clkgen->base))
+                return PTR_ERR(axi_clkgen->base);
+
+        parent_name = of_clk_get_parent_name(pdev->dev.of_node, 0);
+        if (!parent_name)
+                return -EINVAL;
+
+        clk_name = pdev->dev.of_node->name;
+        of_property_read_string(pdev->dev.of_node, "clock-output-names",
+                &clk_name);
+
+        init.name = clk_name;
+        init.ops = &axi_clkgen_ops;
+        init.flags = 0;
+        init.parent_names = &parent_name;
+        init.num_parents = 1;
+
+        axi_clkgen->clk_hw.init = &init;
+        clk = devm_clk_register(&pdev->dev, &axi_clkgen->clk_hw);
+        if (IS_ERR(clk))
+                return PTR_ERR(clk);
+
+        return of_clk_add_provider(pdev->dev.of_node, of_clk_src_simple_get,
+                                    clk);
+}
+
+static int axi_clkgen_remove(struct platform_device *pdev)
+{
+        of_clk_del_provider(pdev->dev.of_node);
+
+        return 0;
+}
+
+static const struct of_device_id axi_clkgen_ids[] = {
+        { .compatible = "adi,axi-clkgen-1.00.a" },
+        { },
+};
+MODULE_DEVICE_TABLE(of, axi_clkgen_ids);
+
+static struct platform_driver axi_clkgen_driver = {
+        .driver = {
+                .name = "adi-axi-clkgen",
+                .owner = THIS_MODULE,
+                .of_match_table = axi_clkgen_ids,
+        },
+        .probe = axi_clkgen_probe,
+        .remove = axi_clkgen_remove,
+};
+module_platform_driver(axi_clkgen_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
+MODULE_DESCRIPTION("Driver for the Analog Devices' AXI clkgen pcore clock generator");
diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
new file mode 100644
index 000000000000..097dee4fd209
--- /dev/null
+++ b/drivers/clk/clk-composite.c
@@ -0,0 +1,201 @@
+/*
+ * Copyright (c) 2013 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+
+#define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
+
+static u8 clk_composite_get_parent(struct clk_hw *hw)
+{
+        struct clk_composite *composite = to_clk_composite(hw);
+        const struct clk_ops *mux_ops = composite->mux_ops;
+        struct clk_hw *mux_hw = composite->mux_hw;
+
+        mux_hw->clk = hw->clk;
+
+        return mux_ops->get_parent(mux_hw);
+}
+
+static int clk_composite_set_parent(struct clk_hw *hw, u8 index)
+{
+        struct clk_composite *composite = to_clk_composite(hw);
+        const struct clk_ops *mux_ops = composite->mux_ops;
+        struct clk_hw *mux_hw = composite->mux_hw;
+
+        mux_hw->clk = hw->clk;
+
+        return mux_ops->set_parent(mux_hw, index);
+}
+
+static unsigned long clk_composite_recalc_rate(struct clk_hw *hw,
+                                            unsigned long parent_rate)
+{
+        struct clk_composite *composite = to_clk_composite(hw);
+        const struct clk_ops *div_ops = composite->div_ops;
+        struct clk_hw *div_hw = composite->div_hw;
+
+        div_hw->clk = hw->clk;
+
+        return div_ops->recalc_rate(div_hw, parent_rate);
+}
+
+static long clk_composite_round_rate(struct clk_hw *hw, unsigned long rate,
+                                  unsigned long *prate)
+{
+        struct clk_composite *composite = to_clk_composite(hw);
+        const struct clk_ops *div_ops = composite->div_ops;
+        struct clk_hw *div_hw = composite->div_hw;
+
+        div_hw->clk = hw->clk;
+
+        return div_ops->round_rate(div_hw, rate, prate);
+}
+
+static int clk_composite_set_rate(struct clk_hw *hw, unsigned long rate,
+                               unsigned long parent_rate)
+{
+        struct clk_composite *composite = to_clk_composite(hw);
+        const struct clk_ops *div_ops = composite->div_ops;
+        struct clk_hw *div_hw = composite->div_hw;
+
+        div_hw->clk = hw->clk;
+
+        return div_ops->set_rate(div_hw, rate, parent_rate);
+}
+
+static int clk_composite_is_enabled(struct clk_hw *hw)
+{
+        struct clk_composite *composite = to_clk_composite(hw);
+        const struct clk_ops *gate_ops = composite->gate_ops;
+        struct clk_hw *gate_hw = composite->gate_hw;
+
+        gate_hw->clk = hw->clk;
+
+        return gate_ops->is_enabled(gate_hw);
+}
+
+static int clk_composite_enable(struct clk_hw *hw)
+{
+        struct clk_composite *composite = to_clk_composite(hw);
+        const struct clk_ops *gate_ops = composite->gate_ops;
+        struct clk_hw *gate_hw = composite->gate_hw;
+
+        gate_hw->clk = hw->clk;
+
+        return gate_ops->enable(gate_hw);
+}
+
+static void clk_composite_disable(struct clk_hw *hw)
+{
+        struct clk_composite *composite = to_clk_composite(hw);
+        const struct clk_ops *gate_ops = composite->gate_ops;
+        struct clk_hw *gate_hw = composite->gate_hw;
+
+        gate_hw->clk = hw->clk;
+
+        gate_ops->disable(gate_hw);
+}
+
+struct clk *clk_register_composite(struct device *dev, const char *name,
+                        const char **parent_names, int num_parents,
+                        struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
+                        struct clk_hw *div_hw, const struct clk_ops *div_ops,
+                        struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
+                        unsigned long flags)
+{
+        struct clk *clk;
+        struct clk_init_data init;
+        struct clk_composite *composite;
+        struct clk_ops *clk_composite_ops;
+
+        composite = kzalloc(sizeof(*composite), GFP_KERNEL);
+        if (!composite) {
+                pr_err("%s: could not allocate composite clk\n", __func__);
+                return ERR_PTR(-ENOMEM);
+        }
+
+        init.name = name;
+        init.flags = flags | CLK_IS_BASIC;
+        init.parent_names = parent_names;
+        init.num_parents = num_parents;
+
+        clk_composite_ops = &composite->ops;
+
+        if (mux_hw && mux_ops) {
+                if (!mux_ops->get_parent || !mux_ops->set_parent) {
+                        clk = ERR_PTR(-EINVAL);
+                        goto err;
+                }
+
+                composite->mux_hw = mux_hw;
+                composite->mux_ops = mux_ops;
+                clk_composite_ops->get_parent = clk_composite_get_parent;
+                clk_composite_ops->set_parent = clk_composite_set_parent;
+        }
+
+        if (div_hw && div_ops) {
+                if (!div_ops->recalc_rate || !div_ops->round_rate ||
+                    !div_ops->set_rate) {
+                        clk = ERR_PTR(-EINVAL);
+                        goto err;
+                }
+
+                composite->div_hw = div_hw;
+                composite->div_ops = div_ops;
+                clk_composite_ops->recalc_rate = clk_composite_recalc_rate;
+                clk_composite_ops->round_rate = clk_composite_round_rate;
+                clk_composite_ops->set_rate = clk_composite_set_rate;
+        }
+
+        if (gate_hw && gate_ops) {
+                if (!gate_ops->is_enabled || !gate_ops->enable ||
+                    !gate_ops->disable) {
+                        clk = ERR_PTR(-EINVAL);
+                        goto err;
+                }
+
+                composite->gate_hw = gate_hw;
+                composite->gate_ops = gate_ops;
+                clk_composite_ops->is_enabled = clk_composite_is_enabled;
+                clk_composite_ops->enable = clk_composite_enable;
+                clk_composite_ops->disable = clk_composite_disable;
+        }
+
+        init.ops = clk_composite_ops;
+        composite->hw.init = &init;
+
+        clk = clk_register(dev, &composite->hw);
+        if (IS_ERR(clk))
+                goto err;
+
+        if (composite->mux_hw)
+                composite->mux_hw->clk = clk;
+
+        if (composite->div_hw)
+                composite->div_hw->clk = clk;
+
+        if (composite->gate_hw)
+                composite->gate_hw->clk = clk;
+
+        return clk;
+
+err:
+        kfree(composite);
+        return clk;
+}
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 508c032edce4..25b1734560d0 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -32,6 +32,7 @@
 static u8 clk_mux_get_parent(struct clk_hw *hw)
 {
         struct clk_mux *mux = to_clk_mux(hw);
+        int num_parents = __clk_get_num_parents(hw->clk);
         u32 val;
 
         /*
@@ -42,7 +43,16 @@ static u8 clk_mux_get_parent(struct clk_hw *hw)
          * val = 0x4 really means "bit 2, index starts at bit 0"
          */
         val = readl(mux->reg) >> mux->shift;
-        val &= (1 << mux->width) - 1;
+        val &= mux->mask;
+
+        if (mux->table) {
+                int i;
+
+                for (i = 0; i < num_parents; i++)
+                        if (mux->table[i] == val)
+                                return i;
+                return -EINVAL;
+        }
 
         if (val && (mux->flags & CLK_MUX_INDEX_BIT))
                 val = ffs(val) - 1;
@@ -50,7 +60,7 @@ static u8 clk_mux_get_parent(struct clk_hw *hw)
         if (val && (mux->flags & CLK_MUX_INDEX_ONE))
                 val--;
 
-        if (val >= __clk_get_num_parents(hw->clk))
+        if (val >= num_parents)
                 return -EINVAL;
 
         return val;
@@ -62,17 +72,22 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
         u32 val;
         unsigned long flags = 0;
 
-        if (mux->flags & CLK_MUX_INDEX_BIT)
-                index = (1 << ffs(index));
+        if (mux->table)
+                index = mux->table[index];
 
-        if (mux->flags & CLK_MUX_INDEX_ONE)
-                index++;
+        else {
+                if (mux->flags & CLK_MUX_INDEX_BIT)
+                        index = (1 << ffs(index));
+
+                if (mux->flags & CLK_MUX_INDEX_ONE)
+                        index++;
+        }
 
         if (mux->lock)
                 spin_lock_irqsave(mux->lock, flags);
 
         val = readl(mux->reg);
-        val &= ~(((1 << mux->width) - 1) << mux->shift);
+        val &= ~(mux->mask << mux->shift);
         val |= index << mux->shift;
         writel(val, mux->reg);
 
@@ -88,10 +103,10 @@ const struct clk_ops clk_mux_ops = {
 };
 EXPORT_SYMBOL_GPL(clk_mux_ops);
 
-struct clk *clk_register_mux(struct device *dev, const char *name,
+struct clk *clk_register_mux_table(struct device *dev, const char *name,
                 const char **parent_names, u8 num_parents, unsigned long flags,
-                void __iomem *reg, u8 shift, u8 width,
-                u8 clk_mux_flags, spinlock_t *lock)
+                void __iomem *reg, u8 shift, u32 mask,
+                u8 clk_mux_flags, u32 *table, spinlock_t *lock)
 {
         struct clk_mux *mux;
         struct clk *clk;
@@ -113,9 +128,10 @@ struct clk *clk_register_mux(struct device *dev, const char *name,
         /* struct clk_mux assignments */
         mux->reg = reg;
         mux->shift = shift;
-        mux->width = width;
+        mux->mask = mask;
         mux->flags = clk_mux_flags;
         mux->lock = lock;
+        mux->table = table;
         mux->hw.init = &init;
 
         clk = clk_register(dev, &mux->hw);
@@ -125,3 +141,15 @@ struct clk *clk_register_mux(struct device *dev, const char *name,
 
         return clk;
 }
+
+struct clk *clk_register_mux(struct device *dev, const char *name,
+                const char **parent_names, u8 num_parents, unsigned long flags,
+                void __iomem *reg, u8 shift, u8 width,
+                u8 clk_mux_flags, spinlock_t *lock)
+{
+        u32 mask = BIT(width) - 1;
+
+        return clk_register_mux_table(dev, name, parent_names, num_parents,
+                                      flags, reg, shift, mask, clk_mux_flags,
+                                      NULL, lock);
+}
diff --git a/drivers/clk/clk-prima2.c b/drivers/clk/clk-prima2.c
index f8e9d0c27be2..643ca653fef0 100644
--- a/drivers/clk/clk-prima2.c
+++ b/drivers/clk/clk-prima2.c
@@ -1113,7 +1113,7 @@ void __init sirfsoc_of_clk_init(void)
 
         for (i = pll1; i < maxclk; i++) {
                 prima2_clks[i] = clk_register(NULL, prima2_clk_hw_array[i]);
-                BUG_ON(!prima2_clks[i]);
+                BUG_ON(IS_ERR(prima2_clks[i]));
         }
         clk_register_clkdev(prima2_clks[cpu], NULL, "cpu");
         clk_register_clkdev(prima2_clks[io],  NULL, "io");
diff --git a/drivers/clk/clk-zynq.c b/drivers/clk/clk-zynq.c
index b14a25f39255..32062977f453 100644
--- a/drivers/clk/clk-zynq.c
+++ b/drivers/clk/clk-zynq.c
@@ -20,6 +20,7 @@
 #include <linux/slab.h>
 #include <linux/kernel.h>
 #include <linux/clk-provider.h>
+#include <linux/clk/zynq.h>
 
 static void __iomem *slcr_base;
 
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index ed87b2405806..0230c9d95975 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -19,14 +19,77 @@
 #include <linux/of.h>
 #include <linux/device.h>
 #include <linux/init.h>
+#include <linux/sched.h>
 
 static DEFINE_SPINLOCK(enable_lock);
 static DEFINE_MUTEX(prepare_lock);
 
+static struct task_struct *prepare_owner;
+static struct task_struct *enable_owner;
+
+static int prepare_refcnt;
+static int enable_refcnt;
+
 static HLIST_HEAD(clk_root_list);
 static HLIST_HEAD(clk_orphan_list);
 static LIST_HEAD(clk_notifier_list);
 
+/***           locking             ***/
+static void clk_prepare_lock(void)
+{
+        if (!mutex_trylock(&prepare_lock)) {
+                if (prepare_owner == current) {
+                        prepare_refcnt++;
+                        return;
+                }
+                mutex_lock(&prepare_lock);
+        }
+        WARN_ON_ONCE(prepare_owner != NULL);
+        WARN_ON_ONCE(prepare_refcnt != 0);
+        prepare_owner = current;
+        prepare_refcnt = 1;
+}
+
+static void clk_prepare_unlock(void)
+{
+        WARN_ON_ONCE(prepare_owner != current);
+        WARN_ON_ONCE(prepare_refcnt == 0);
+
+        if (--prepare_refcnt)
+                return;
+        prepare_owner = NULL;
+        mutex_unlock(&prepare_lock);
+}
+
+static unsigned long clk_enable_lock(void)
+{
+        unsigned long flags;
+
+        if (!spin_trylock_irqsave(&enable_lock, flags)) {
+                if (enable_owner == current) {
+                        enable_refcnt++;
+                        return flags;
+                }
+                spin_lock_irqsave(&enable_lock, flags);
+        }
+        WARN_ON_ONCE(enable_owner != NULL);
+        WARN_ON_ONCE(enable_refcnt != 0);
+        enable_owner = current;
+        enable_refcnt = 1;
+        return flags;
+}
+
+static void clk_enable_unlock(unsigned long flags)
+{
+        WARN_ON_ONCE(enable_owner != current);
+        WARN_ON_ONCE(enable_refcnt == 0);
+
+        if (--enable_refcnt)
+                return;
+        enable_owner = NULL;
+        spin_unlock_irqrestore(&enable_lock, flags);
+}
+
 /***        debugfs support        ***/
 
 #ifdef CONFIG_COMMON_CLK_DEBUG
@@ -69,7 +132,7 @@ static int clk_summary_show(struct seq_file *s, void *data)
         seq_printf(s, "   clock                        enable_cnt  prepare_cnt  rate\n");
         seq_printf(s, "---------------------------------------------------------------------\n");
 
-        mutex_lock(&prepare_lock);
+        clk_prepare_lock();
 
         hlist_for_each_entry(c, &clk_root_list, child_node)
                 clk_summary_show_subtree(s, c, 0);
@@ -77,7 +140,7 @@ static int clk_summary_show(struct seq_file *s, void *data)
         hlist_for_each_entry(c, &clk_orphan_list, child_node)
                 clk_summary_show_subtree(s, c, 0);
 
-        mutex_unlock(&prepare_lock);
+        clk_prepare_unlock();
 
         return 0;
 }
@@ -130,7 +193,7 @@ static int clk_dump(struct seq_file *s, void *data)
 
         seq_printf(s, "{");
 
-        mutex_lock(&prepare_lock);
+        clk_prepare_lock();
 
         hlist_for_each_entry(c, &clk_root_list, child_node) {
                 if (!first_node)
@@ -144,7 +207,7 @@ static int clk_dump(struct seq_file *s, void *data)
                 clk_dump_subtree(s, c, 0);
         }
 
-        mutex_unlock(&prepare_lock);
+        clk_prepare_unlock();
 
         seq_printf(s, "}");
         return 0;
@@ -316,7 +379,7 @@ static int __init clk_debug_init(void)
         if (!orphandir)
                 return -ENOMEM;
 
-        mutex_lock(&prepare_lock);
+        clk_prepare_lock();
 
         hlist_for_each_entry(clk, &clk_root_list, child_node)
                 clk_debug_create_subtree(clk, rootdir);
@@ -326,7 +389,7 @@ static int __init clk_debug_init(void)
 
         inited = 1;
 
-        mutex_unlock(&prepare_lock);
+        clk_prepare_unlock();
 
         return 0;
 }
@@ -336,6 +399,31 @@ static inline int clk_debug_register(struct clk *clk) { return 0; }
 #endif
 
 /* caller must hold prepare_lock */
+static void clk_unprepare_unused_subtree(struct clk *clk)
+{
+        struct clk *child;
+
+        if (!clk)
+                return;
+
+        hlist_for_each_entry(child, &clk->children, child_node)
+                clk_unprepare_unused_subtree(child);
+
+        if (clk->prepare_count)
+                return;
+
+        if (clk->flags & CLK_IGNORE_UNUSED)
+                return;
+
+        if (__clk_is_prepared(clk)) {
+                if (clk->ops->unprepare_unused)
+                        clk->ops->unprepare_unused(clk->hw);
+                else if (clk->ops->unprepare)
+                        clk->ops->unprepare(clk->hw);
+        }
+}
+
+/* caller must hold prepare_lock */
 static void clk_disable_unused_subtree(struct clk *clk)
 {
         struct clk *child;
@@ -347,7 +435,7 @@ static void clk_disable_unused_subtree(struct clk *clk)
         hlist_for_each_entry(child, &clk->children, child_node)
                 clk_disable_unused_subtree(child);
 
-        spin_lock_irqsave(&enable_lock, flags);
+        flags = clk_enable_lock();
 
         if (clk->enable_count)
                 goto unlock_out;
@@ -368,7 +456,7 @@ static void clk_disable_unused_subtree(struct clk *clk)
         }
 
 unlock_out:
-        spin_unlock_irqrestore(&enable_lock, flags);
+        clk_enable_unlock(flags);
 
 out:
         return;
@@ -378,7 +466,7 @@ static int clk_disable_unused(void)
 {
         struct clk *clk;
 
-        mutex_lock(&prepare_lock);
+        clk_prepare_lock();
 
         hlist_for_each_entry(clk, &clk_root_list, child_node)
                 clk_disable_unused_subtree(clk);
@@ -386,7 +474,13 @@ static int clk_disable_unused(void)
         hlist_for_each_entry(clk, &clk_orphan_list, child_node)
                 clk_disable_unused_subtree(clk);
 
-        mutex_unlock(&prepare_lock);
+        hlist_for_each_entry(clk, &clk_root_list, child_node)
+                clk_unprepare_unused_subtree(clk);
+
+        hlist_for_each_entry(clk, &clk_orphan_list, child_node)
+                clk_unprepare_unused_subtree(clk);
+
+        clk_prepare_unlock();
 
         return 0;
 }
@@ -451,6 +545,27 @@ unsigned long __clk_get_flags(struct clk *clk)
         return !clk ? 0 : clk->flags;
 }
 
+bool __clk_is_prepared(struct clk *clk)
+{
+        int ret;
+
+        if (!clk)
+                return false;
+
+        /*
+         * .is_prepared is optional for clocks that can prepare
+         * fall back to software usage counter if it is missing
+         */
+        if (!clk->ops->is_prepared) {
+                ret = clk->prepare_count ? 1 : 0;
+                goto out;
+        }
+
+        ret = clk->ops->is_prepared(clk->hw);
+out:
+        return !!ret;
+}
+
 bool __clk_is_enabled(struct clk *clk)
 {
         int ret;
@@ -548,9 +663,9 @@ void __clk_unprepare(struct clk *clk)
  */
 void clk_unprepare(struct clk *clk)
 {
-        mutex_lock(&prepare_lock);
+        clk_prepare_lock();
         __clk_unprepare(clk);
-        mutex_unlock(&prepare_lock);
+        clk_prepare_unlock();
 }
 EXPORT_SYMBOL_GPL(clk_unprepare);
 
@@ -596,9 +711,9 @@ int clk_prepare(struct clk *clk)
 {
         int ret;
 
-        mutex_lock(&prepare_lock);
+        clk_prepare_lock();
         ret = __clk_prepare(clk);
-        mutex_unlock(&prepare_lock);
+        clk_prepare_unlock();
 
         return ret;
 }
@@ -640,9 +755,9 @@ void clk_disable(struct clk *clk)
 {
         unsigned long flags;
 
-        spin_lock_irqsave(&enable_lock, flags);
+        flags = clk_enable_lock();
         __clk_disable(clk);
-        spin_unlock_irqrestore(&enable_lock, flags);
+        clk_enable_unlock(flags);
 }
 EXPORT_SYMBOL_GPL(clk_disable);
 
@@ -693,9 +808,9 @@ int clk_enable(struct clk *clk)
         unsigned long flags;
         int ret;
 
-        spin_lock_irqsave(&enable_lock, flags);
+        flags = clk_enable_lock();
         ret = __clk_enable(clk);
-        spin_unlock_irqrestore(&enable_lock, flags);
+        clk_enable_unlock(flags);
 
         return ret;
 }
@@ -740,9 +855,9 @@ long clk_round_rate(struct clk *clk, unsigned long rate)
 {
         unsigned long ret;
 
-        mutex_lock(&prepare_lock);
+        clk_prepare_lock();
         ret = __clk_round_rate(clk, rate);
-        mutex_unlock(&prepare_lock);
+        clk_prepare_unlock();
 
         return ret;
 }
@@ -837,13 +952,13 @@ unsigned long clk_get_rate(struct clk *clk)
 {
         unsigned long rate;
 
-        mutex_lock(&prepare_lock);
+        clk_prepare_lock();
 
         if (clk && (clk->flags & CLK_GET_RATE_NOCACHE))
                 __clk_recalc_rates(clk, 0);
 
         rate = __clk_get_rate(clk);
-        mutex_unlock(&prepare_lock);
+        clk_prepare_unlock();
 
         return rate;
 }
@@ -974,7 +1089,7 @@ static struct clk *clk_propagate_rate_change(struct clk *clk, unsigned long even
         int ret = NOTIFY_DONE;
 
         if (clk->rate == clk->new_rate)
-                return 0;
+                return NULL;
 
         if (clk->notifier_count) {
                 ret = __clk_notify(clk, event, clk->rate, clk->new_rate);
@@ -1048,7 +1163,7 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
         int ret = 0;
 
         /* prevent racing with updates to the clock topology */
-        mutex_lock(&prepare_lock);
+        clk_prepare_lock();
 
         /* bail early if nothing to do */
         if (rate == clk->rate)
@@ -1080,7 +1195,7 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
         clk_change_rate(top);
 
 out:
-        mutex_unlock(&prepare_lock);
+        clk_prepare_unlock();
 
         return ret;
 }
@@ -1096,9 +1211,9 @@ struct clk *clk_get_parent(struct clk *clk)
 {
         struct clk *parent;
 
-        mutex_lock(&prepare_lock);
+        clk_prepare_lock();
         parent = __clk_get_parent(clk);
-        mutex_unlock(&prepare_lock);
+        clk_prepare_unlock();
 
         return parent;
 }
@@ -1242,19 +1357,19 @@ static int __clk_set_parent(struct clk *clk, struct clk *parent)
                 __clk_prepare(parent);
 
         /* FIXME replace with clk_is_enabled(clk) someday */
-        spin_lock_irqsave(&enable_lock, flags);
+        flags = clk_enable_lock();
         if (clk->enable_count)
                 __clk_enable(parent);
-        spin_unlock_irqrestore(&enable_lock, flags);
+        clk_enable_unlock(flags);
 
         /* change clock input source */
         ret = clk->ops->set_parent(clk->hw, i);
 
         /* clean up old prepare and enable */
-        spin_lock_irqsave(&enable_lock, flags);
+        flags = clk_enable_lock();
         if (clk->enable_count)
                 __clk_disable(old_parent);
-        spin_unlock_irqrestore(&enable_lock, flags);
+        clk_enable_unlock(flags);
 
         if (clk->prepare_count)
                 __clk_unprepare(old_parent);
@@ -1286,7 +1401,7 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
                 return -ENOSYS;
 
         /* prevent racing with updates to the clock topology */
-        mutex_lock(&prepare_lock);
+        clk_prepare_lock();
 
         if (clk->parent == parent)
                 goto out;
@@ -1315,7 +1430,7 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
         __clk_reparent(clk, parent);
 
 out:
-        mutex_unlock(&prepare_lock);
+        clk_prepare_unlock();
 
         return ret;
 }
@@ -1338,7 +1453,7 @@ int __clk_init(struct device *dev, struct clk *clk)
         if (!clk)
                 return -EINVAL;
 
-        mutex_lock(&prepare_lock);
+        clk_prepare_lock();
 
         /* check to see if a clock with this name is already registered */
         if (__clk_lookup(clk->name)) {
@@ -1462,7 +1577,7 @@ int __clk_init(struct device *dev, struct clk *clk)
         clk_debug_register(clk);
 
 out:
-        mutex_unlock(&prepare_lock);
+        clk_prepare_unlock();
 
         return ret;
 }
@@ -1696,7 +1811,7 @@ int clk_notifier_register(struct clk *clk, struct notifier_block *nb)
         if (!clk || !nb)
                 return -EINVAL;
 
-        mutex_lock(&prepare_lock);
+        clk_prepare_lock();
 
         /* search the list of notifiers for this clk */
         list_for_each_entry(cn, &clk_notifier_list, node)
@@ -1720,7 +1835,7 @@ int clk_notifier_register(struct clk *clk, struct notifier_block *nb)
         clk->notifier_count++;
 
 out:
-        mutex_unlock(&prepare_lock);
+        clk_prepare_unlock();
 
         return ret;
 }
@@ -1745,7 +1860,7 @@ int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb)
         if (!clk || !nb)
                 return -EINVAL;
 
-        mutex_lock(&prepare_lock);
+        clk_prepare_lock();
 
         list_for_each_entry(cn, &clk_notifier_list, node)
                 if (cn->clk == clk)
@@ -1766,7 +1881,7 @@ int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb)
                 ret = -ENOENT;
         }
 
-        mutex_unlock(&prepare_lock);
+        clk_prepare_unlock();
 
         return ret;
 }
diff --git a/drivers/clk/mxs/clk.c b/drivers/clk/mxs/clk.c
index b24d56067c80..5301bce8957b 100644
--- a/drivers/clk/mxs/clk.c
+++ b/drivers/clk/mxs/clk.c
@@ -13,6 +13,7 @@
 #include <linux/io.h>
 #include <linux/jiffies.h>
 #include <linux/spinlock.h>
+#include "clk.h"
 
 DEFINE_SPINLOCK(mxs_lock);
 
diff --git a/drivers/clk/spear/spear1310_clock.c b/drivers/clk/spear/spear1310_clock.c
index ed9af4278619..aedbbe12f321 100644
--- a/drivers/clk/spear/spear1310_clock.c
+++ b/drivers/clk/spear/spear1310_clock.c
@@ -17,12 +17,10 @@
 #include <linux/io.h>
 #include <linux/of_platform.h>
 #include <linux/spinlock_types.h>
-#include <mach/spear.h>
 #include "clk.h"
 
-#define VA_SPEAR1310_RAS_BASE                   IOMEM(UL(0xFA400000))
 /* PLL related registers and bit values */
-#define SPEAR1310_PLL_CFG                       (VA_MISC_BASE + 0x210)
+#define SPEAR1310_PLL_CFG                       (misc_base + 0x210)
         /* PLL_CFG bit values */
         #define SPEAR1310_CLCD_SYNT_CLK_MASK            1
         #define SPEAR1310_CLCD_SYNT_CLK_SHIFT           31
@@ -35,15 +33,15 @@
         #define SPEAR1310_PLL2_CLK_SHIFT                22
         #define SPEAR1310_PLL1_CLK_SHIFT                20
 
-#define SPEAR1310_PLL1_CTR                      (VA_MISC_BASE + 0x214)
-#define SPEAR1310_PLL1_FRQ                      (VA_MISC_BASE + 0x218)
-#define SPEAR1310_PLL2_CTR                      (VA_MISC_BASE + 0x220)
-#define SPEAR1310_PLL2_FRQ                      (VA_MISC_BASE + 0x224)
-#define SPEAR1310_PLL3_CTR                      (VA_MISC_BASE + 0x22C)
-#define SPEAR1310_PLL3_FRQ                      (VA_MISC_BASE + 0x230)
-#define SPEAR1310_PLL4_CTR                      (VA_MISC_BASE + 0x238)
-#define SPEAR1310_PLL4_FRQ                      (VA_MISC_BASE + 0x23C)
-#define SPEAR1310_PERIP_CLK_CFG                 (VA_MISC_BASE + 0x244)
+#define SPEAR1310_PLL1_CTR                      (misc_base + 0x214)
+#define SPEAR1310_PLL1_FRQ                      (misc_base + 0x218)
+#define SPEAR1310_PLL2_CTR                      (misc_base + 0x220)
+#define SPEAR1310_PLL2_FRQ                      (misc_base + 0x224)
+#define SPEAR1310_PLL3_CTR                      (misc_base + 0x22C)
+#define SPEAR1310_PLL3_FRQ                      (misc_base + 0x230)
+#define SPEAR1310_PLL4_CTR                      (misc_base + 0x238)
+#define SPEAR1310_PLL4_FRQ                      (misc_base + 0x23C)
+#define SPEAR1310_PERIP_CLK_CFG                 (misc_base + 0x244)
         /* PERIP_CLK_CFG bit values */
         #define SPEAR1310_GPT_OSC24_VAL                 0
         #define SPEAR1310_GPT_APB_VAL                   1
@@ -65,7 +63,7 @@
         #define SPEAR1310_C3_CLK_MASK                   1
         #define SPEAR1310_C3_CLK_SHIFT                  1
 
-#define SPEAR1310_GMAC_CLK_CFG                  (VA_MISC_BASE + 0x248)
+#define SPEAR1310_GMAC_CLK_CFG                  (misc_base + 0x248)
         #define SPEAR1310_GMAC_PHY_IF_SEL_MASK          3
         #define SPEAR1310_GMAC_PHY_IF_SEL_SHIFT         4
         #define SPEAR1310_GMAC_PHY_CLK_MASK             1
@@ -73,7 +71,7 @@
         #define SPEAR1310_GMAC_PHY_INPUT_CLK_MASK       2
         #define SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT      1
 
-#define SPEAR1310_I2S_CLK_CFG                   (VA_MISC_BASE + 0x24C)
+#define SPEAR1310_I2S_CLK_CFG                   (misc_base + 0x24C)
         /* I2S_CLK_CFG register mask */
         #define SPEAR1310_I2S_SCLK_X_MASK               0x1F
         #define SPEAR1310_I2S_SCLK_X_SHIFT              27
@@ -91,21 +89,21 @@
         #define SPEAR1310_I2S_SRC_CLK_MASK              2
         #define SPEAR1310_I2S_SRC_CLK_SHIFT             0
 
-#define SPEAR1310_C3_CLK_SYNT                   (VA_MISC_BASE + 0x250)
-#define SPEAR1310_UART_CLK_SYNT                 (VA_MISC_BASE + 0x254)
-#define SPEAR1310_GMAC_CLK_SYNT                 (VA_MISC_BASE + 0x258)
-#define SPEAR1310_SDHCI_CLK_SYNT                (VA_MISC_BASE + 0x25C)
-#define SPEAR1310_CFXD_CLK_SYNT                 (VA_MISC_BASE + 0x260)
-#define SPEAR1310_ADC_CLK_SYNT                  (VA_MISC_BASE + 0x264)
-#define SPEAR1310_AMBA_CLK_SYNT                 (VA_MISC_BASE + 0x268)
-#define SPEAR1310_CLCD_CLK_SYNT                 (VA_MISC_BASE + 0x270)
-#define SPEAR1310_RAS_CLK_SYNT0                 (VA_MISC_BASE + 0x280)
-#define SPEAR1310_RAS_CLK_SYNT1                 (VA_MISC_BASE + 0x288)
-#define SPEAR1310_RAS_CLK_SYNT2                 (VA_MISC_BASE + 0x290)
-#define SPEAR1310_RAS_CLK_SYNT3                 (VA_MISC_BASE + 0x298)
+#define SPEAR1310_C3_CLK_SYNT                   (misc_base + 0x250)
+#define SPEAR1310_UART_CLK_SYNT                 (misc_base + 0x254)
+#define SPEAR1310_GMAC_CLK_SYNT                 (misc_base + 0x258)
+#define SPEAR1310_SDHCI_CLK_SYNT                (misc_base + 0x25C)
+#define SPEAR1310_CFXD_CLK_SYNT                 (misc_base + 0x260)
+#define SPEAR1310_ADC_CLK_SYNT                  (misc_base + 0x264)
+#define SPEAR1310_AMBA_CLK_SYNT                 (misc_base + 0x268)
+#define SPEAR1310_CLCD_CLK_SYNT                 (misc_base + 0x270)
+#define SPEAR1310_RAS_CLK_SYNT0                 (misc_base + 0x280)
+#define SPEAR1310_RAS_CLK_SYNT1                 (misc_base + 0x288)
+#define SPEAR1310_RAS_CLK_SYNT2                 (misc_base + 0x290)
+#define SPEAR1310_RAS_CLK_SYNT3                 (misc_base + 0x298)
         /* Check Fractional synthesizer reg masks */
 
-#define SPEAR1310_PERIP1_CLK_ENB                (VA_MISC_BASE + 0x300)
+#define SPEAR1310_PERIP1_CLK_ENB                (misc_base + 0x300)
         /* PERIP1_CLK_ENB register masks */
         #define SPEAR1310_RTC_CLK_ENB                   31
         #define SPEAR1310_ADC_CLK_ENB                   30
@@ -138,7 +136,7 @@
         #define SPEAR1310_SYSROM_CLK_ENB                1
         #define SPEAR1310_BUS_CLK_ENB                   0
 
-#define SPEAR1310_PERIP2_CLK_ENB                (VA_MISC_BASE + 0x304)
+#define SPEAR1310_PERIP2_CLK_ENB                (misc_base + 0x304)
         /* PERIP2_CLK_ENB register masks */
         #define SPEAR1310_THSENS_CLK_ENB                8
         #define SPEAR1310_I2S_REF_PAD_CLK_ENB           7
@@ -150,7 +148,7 @@
         #define SPEAR1310_DDR_CORE_CLK_ENB              1
         #define SPEAR1310_DDR_CTRL_CLK_ENB              0
 
-#define SPEAR1310_RAS_CLK_ENB                   (VA_MISC_BASE + 0x310)
+#define SPEAR1310_RAS_CLK_ENB                   (misc_base + 0x310)
         /* RAS_CLK_ENB register masks */
         #define SPEAR1310_SYNT3_CLK_ENB                 17
         #define SPEAR1310_SYNT2_CLK_ENB                 16
@@ -172,7 +170,7 @@
         #define SPEAR1310_ACLK_CLK_ENB                  0
 
 /* RAS Area Control Register */
-#define SPEAR1310_RAS_CTRL_REG0                 (VA_SPEAR1310_RAS_BASE + 0x000)
+#define SPEAR1310_RAS_CTRL_REG0                 (ras_base + 0x000)
         #define SPEAR1310_SSP1_CLK_MASK                 3
         #define SPEAR1310_SSP1_CLK_SHIFT                26
         #define SPEAR1310_TDM_CLK_MASK                  1
@@ -197,12 +195,12 @@
         #define SPEAR1310_PCI_CLK_MASK                  1
         #define SPEAR1310_PCI_CLK_SHIFT                 0
 
-#define SPEAR1310_RAS_CTRL_REG1                 (VA_SPEAR1310_RAS_BASE + 0x004)
+#define SPEAR1310_RAS_CTRL_REG1                 (ras_base + 0x004)
         #define SPEAR1310_PHY_CLK_MASK                  0x3
         #define SPEAR1310_RMII_PHY_CLK_SHIFT            0
         #define SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT      2
 
-#define SPEAR1310_RAS_SW_CLK_CTRL               (VA_SPEAR1310_RAS_BASE + 0x0148)
+#define SPEAR1310_RAS_SW_CLK_CTRL               (ras_base + 0x0148)
         #define SPEAR1310_CAN1_CLK_ENB                  25
         #define SPEAR1310_CAN0_CLK_ENB                  24
         #define SPEAR1310_GPT64_CLK_ENB                 23
@@ -385,7 +383,7 @@ static const char *ssp1_parents[] = { "ras_apb_clk", "gen_syn1_clk",
 static const char *pci_parents[] = { "ras_pll3_clk", "gen_syn2_clk", };
 static const char *tdm_parents[] = { "ras_pll3_clk", "gen_syn1_clk", };
 
-void __init spear1310_clk_init(void)
+void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 {
         struct clk *clk, *clk1;
 
diff --git a/drivers/clk/spear/spear1340_clock.c b/drivers/clk/spear/spear1340_clock.c
index 82abea366b78..9d0b3949db30 100644
--- a/drivers/clk/spear/spear1340_clock.c
+++ b/drivers/clk/spear/spear1340_clock.c
@@ -17,18 +17,17 @@
 #include <linux/io.h>
 #include <linux/of_platform.h>
 #include <linux/spinlock_types.h>
-#include <mach/spear.h>
 #include "clk.h"
 
 /* Clock Configuration Registers */
-#define SPEAR1340_SYS_CLK_CTRL                  (VA_MISC_BASE + 0x200)
+#define SPEAR1340_SYS_CLK_CTRL                  (misc_base + 0x200)
         #define SPEAR1340_HCLK_SRC_SEL_SHIFT    27
         #define SPEAR1340_HCLK_SRC_SEL_MASK     1
         #define SPEAR1340_SCLK_SRC_SEL_SHIFT    23
         #define SPEAR1340_SCLK_SRC_SEL_MASK     3
 
 /* PLL related registers and bit values */
-#define SPEAR1340_PLL_CFG                       (VA_MISC_BASE + 0x210)
+#define SPEAR1340_PLL_CFG                       (misc_base + 0x210)
         /* PLL_CFG bit values */
         #define SPEAR1340_CLCD_SYNT_CLK_MASK            1
         #define SPEAR1340_CLCD_SYNT_CLK_SHIFT           31
@@ -40,15 +39,15 @@
         #define SPEAR1340_PLL2_CLK_SHIFT                22
         #define SPEAR1340_PLL1_CLK_SHIFT                20
 
-#define SPEAR1340_PLL1_CTR                      (VA_MISC_BASE + 0x214)
-#define SPEAR1340_PLL1_FRQ                      (VA_MISC_BASE + 0x218)
-#define SPEAR1340_PLL2_CTR                      (VA_MISC_BASE + 0x220)
-#define SPEAR1340_PLL2_FRQ                      (VA_MISC_BASE + 0x224)
-#define SPEAR1340_PLL3_CTR                      (VA_MISC_BASE + 0x22C)
-#define SPEAR1340_PLL3_FRQ                      (VA_MISC_BASE + 0x230)
-#define SPEAR1340_PLL4_CTR                      (VA_MISC_BASE + 0x238)
-#define SPEAR1340_PLL4_FRQ                      (VA_MISC_BASE + 0x23C)
-#define SPEAR1340_PERIP_CLK_CFG                 (VA_MISC_BASE + 0x244)
+#define SPEAR1340_PLL1_CTR                      (misc_base + 0x214)
+#define SPEAR1340_PLL1_FRQ                      (misc_base + 0x218)
+#define SPEAR1340_PLL2_CTR                      (misc_base + 0x220)
+#define SPEAR1340_PLL2_FRQ                      (misc_base + 0x224)
+#define SPEAR1340_PLL3_CTR                      (misc_base + 0x22C)
+#define SPEAR1340_PLL3_FRQ                      (misc_base + 0x230)
+#define SPEAR1340_PLL4_CTR                      (misc_base + 0x238)
+#define SPEAR1340_PLL4_FRQ                      (misc_base + 0x23C)
+#define SPEAR1340_PERIP_CLK_CFG                 (misc_base + 0x244)
         /* PERIP_CLK_CFG bit values */
         #define SPEAR1340_SPDIF_CLK_MASK                1
         #define SPEAR1340_SPDIF_OUT_CLK_SHIFT           15
@@ -66,13 +65,13 @@
         #define SPEAR1340_C3_CLK_MASK                   1
         #define SPEAR1340_C3_CLK_SHIFT                  1
 
-#define SPEAR1340_GMAC_CLK_CFG                  (VA_MISC_BASE + 0x248)
+#define SPEAR1340_GMAC_CLK_CFG                  (misc_base + 0x248)
         #define SPEAR1340_GMAC_PHY_CLK_MASK             1
         #define SPEAR1340_GMAC_PHY_CLK_SHIFT            2
         #define SPEAR1340_GMAC_PHY_INPUT_CLK_MASK       2
         #define SPEAR1340_GMAC_PHY_INPUT_CLK_SHIFT      0
 
-#define SPEAR1340_I2S_CLK_CFG                   (VA_MISC_BASE + 0x24C)
+#define SPEAR1340_I2S_CLK_CFG                   (misc_base + 0x24C)
         /* I2S_CLK_CFG register mask */
         #define SPEAR1340_I2S_SCLK_X_MASK               0x1F
         #define SPEAR1340_I2S_SCLK_X_SHIFT              27
@@ -90,21 +89,21 @@
         #define SPEAR1340_I2S_SRC_CLK_MASK              2
         #define SPEAR1340_I2S_SRC_CLK_SHIFT             0
 
-#define SPEAR1340_C3_CLK_SYNT                   (VA_MISC_BASE + 0x250)
-#define SPEAR1340_UART0_CLK_SYNT                (VA_MISC_BASE + 0x254)
-#define SPEAR1340_UART1_CLK_SYNT                (VA_MISC_BASE + 0x258)
-#define SPEAR1340_GMAC_CLK_SYNT                 (VA_MISC_BASE + 0x25C)
-#define SPEAR1340_SDHCI_CLK_SYNT                (VA_MISC_BASE + 0x260)
-#define SPEAR1340_CFXD_CLK_SYNT                 (VA_MISC_BASE + 0x264)
-#define SPEAR1340_ADC_CLK_SYNT                  (VA_MISC_BASE + 0x270)
-#define SPEAR1340_AMBA_CLK_SYNT                 (VA_MISC_BASE + 0x274)
-#define SPEAR1340_CLCD_CLK_SYNT                 (VA_MISC_BASE + 0x27C)
-#define SPEAR1340_SYS_CLK_SYNT                  (VA_MISC_BASE + 0x284)
-#define SPEAR1340_GEN_CLK_SYNT0                 (VA_MISC_BASE + 0x28C)
-#define SPEAR1340_GEN_CLK_SYNT1                 (VA_MISC_BASE + 0x294)
-#define SPEAR1340_GEN_CLK_SYNT2                 (VA_MISC_BASE + 0x29C)
-#define SPEAR1340_GEN_CLK_SYNT3                 (VA_MISC_BASE + 0x304)
-#define SPEAR1340_PERIP1_CLK_ENB                (VA_MISC_BASE + 0x30C)
+#define SPEAR1340_C3_CLK_SYNT                   (misc_base + 0x250)
+#define SPEAR1340_UART0_CLK_SYNT                (misc_base + 0x254)
+#define SPEAR1340_UART1_CLK_SYNT                (misc_base + 0x258)
+#define SPEAR1340_GMAC_CLK_SYNT                 (misc_base + 0x25C)
+#define SPEAR1340_SDHCI_CLK_SYNT                (misc_base + 0x260)
+#define SPEAR1340_CFXD_CLK_SYNT                 (misc_base + 0x264)
+#define SPEAR1340_ADC_CLK_SYNT                  (misc_base + 0x270)
+#define SPEAR1340_AMBA_CLK_SYNT                 (misc_base + 0x274)
+#define SPEAR1340_CLCD_CLK_SYNT                 (misc_base + 0x27C)
+#define SPEAR1340_SYS_CLK_SYNT                  (misc_base + 0x284)
+#define SPEAR1340_GEN_CLK_SYNT0                 (misc_base + 0x28C)
+#define SPEAR1340_GEN_CLK_SYNT1                 (misc_base + 0x294)
+#define SPEAR1340_GEN_CLK_SYNT2                 (misc_base + 0x29C)
+#define SPEAR1340_GEN_CLK_SYNT3                 (misc_base + 0x304)
+#define SPEAR1340_PERIP1_CLK_ENB                (misc_base + 0x30C)
         #define SPEAR1340_RTC_CLK_ENB                   31
         #define SPEAR1340_ADC_CLK_ENB                   30
         #define SPEAR1340_C3_CLK_ENB                    29
@@ -133,7 +132,7 @@
         #define SPEAR1340_SYSROM_CLK_ENB                1
         #define SPEAR1340_BUS_CLK_ENB                   0
 
-#define SPEAR1340_PERIP2_CLK_ENB                (VA_MISC_BASE + 0x310)
+#define SPEAR1340_PERIP2_CLK_ENB                (misc_base + 0x310)
         #define SPEAR1340_THSENS_CLK_ENB                8
         #define SPEAR1340_I2S_REF_PAD_CLK_ENB           7
         #define SPEAR1340_ACP_CLK_ENB                   6
@@ -144,7 +143,7 @@
         #define SPEAR1340_DDR_CORE_CLK_ENB              1
         #define SPEAR1340_DDR_CTRL_CLK_ENB              0
 
-#define SPEAR1340_PERIP3_CLK_ENB                (VA_MISC_BASE + 0x314)
+#define SPEAR1340_PERIP3_CLK_ENB                (misc_base + 0x314)
         #define SPEAR1340_PLGPIO_CLK_ENB                18
         #define SPEAR1340_VIDEO_DEC_CLK_ENB             16
         #define SPEAR1340_VIDEO_ENC_CLK_ENB             15
@@ -441,7 +440,7 @@ static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk",
 static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco2div2_clk",
         "pll2_clk", };
 
-void __init spear1340_clk_init(void)
+void __init spear1340_clk_init(void __iomem *misc_base)
 {
         struct clk *clk, *clk1;
 
@@ -960,47 +959,47 @@ void __init spear1340_clk_init(void)
                         SPEAR1340_SPDIF_IN_CLK_ENB, 0, &_lock);
         clk_register_clkdev(clk, NULL, "d0100000.spdif-in");
 
-        clk = clk_register_gate(NULL, "acp_clk", "acp_mclk", 0,
+        clk = clk_register_gate(NULL, "acp_clk", "ahb_clk", 0,
                         SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_ACP_CLK_ENB, 0,
                         &_lock);
         clk_register_clkdev(clk, NULL, "acp_clk");
 
-        clk = clk_register_gate(NULL, "plgpio_clk", "plgpio_mclk", 0,
+        clk = clk_register_gate(NULL, "plgpio_clk", "ahb_clk", 0,
                         SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PLGPIO_CLK_ENB, 0,
                         &_lock);
         clk_register_clkdev(clk, NULL, "e2800000.gpio");
 
-        clk = clk_register_gate(NULL, "video_dec_clk", "video_dec_mclk", 0,
+        clk = clk_register_gate(NULL, "video_dec_clk", "ahb_clk", 0,
                         SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_DEC_CLK_ENB,
                         0, &_lock);
         clk_register_clkdev(clk, NULL, "video_dec");
 
-        clk = clk_register_gate(NULL, "video_enc_clk", "video_enc_mclk", 0,
+        clk = clk_register_gate(NULL, "video_enc_clk", "ahb_clk", 0,
                         SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_ENC_CLK_ENB,
                         0, &_lock);
         clk_register_clkdev(clk, NULL, "video_enc");
 
-        clk = clk_register_gate(NULL, "video_in_clk", "video_in_mclk", 0,
+        clk = clk_register_gate(NULL, "video_in_clk", "ahb_clk", 0,
                         SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_IN_CLK_ENB, 0,
                         &_lock);
         clk_register_clkdev(clk, NULL, "spear_vip");
 
-        clk = clk_register_gate(NULL, "cam0_clk", "cam0_mclk", 0,
+        clk = clk_register_gate(NULL, "cam0_clk", "ahb_clk", 0,
                         SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM0_CLK_ENB, 0,
                         &_lock);
         clk_register_clkdev(clk, NULL, "d0200000.cam0");
 
-        clk = clk_register_gate(NULL, "cam1_clk", "cam1_mclk", 0,
+        clk = clk_register_gate(NULL, "cam1_clk", "ahb_clk", 0,
                         SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM1_CLK_ENB, 0,
                         &_lock);
         clk_register_clkdev(clk, NULL, "d0300000.cam1");
 
-        clk = clk_register_gate(NULL, "cam2_clk", "cam2_mclk", 0,
+        clk = clk_register_gate(NULL, "cam2_clk", "ahb_clk", 0,
                         SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM2_CLK_ENB, 0,
                         &_lock);
         clk_register_clkdev(clk, NULL, "d0400000.cam2");
 
-        clk = clk_register_gate(NULL, "cam3_clk", "cam3_mclk", 0,
+        clk = clk_register_gate(NULL, "cam3_clk", "ahb_clk", 0,
                         SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM3_CLK_ENB, 0,
                         &_lock);
         clk_register_clkdev(clk, NULL, "d0500000.cam3");
diff --git a/drivers/clk/spear/spear3xx_clock.c b/drivers/clk/spear/spear3xx_clock.c
index 33d3ac588da7..f9ec43fd1320 100644
--- a/drivers/clk/spear/spear3xx_clock.c
+++ b/drivers/clk/spear/spear3xx_clock.c
@@ -15,21 +15,20 @@
 #include <linux/io.h>
 #include <linux/of_platform.h>
 #include <linux/spinlock_types.h>
-#include <mach/misc_regs.h>
 #include "clk.h"
 
 static DEFINE_SPINLOCK(_lock);
 
-#define PLL1_CTR                        (MISC_BASE + 0x008)
-#define PLL1_FRQ                        (MISC_BASE + 0x00C)
-#define PLL2_CTR                        (MISC_BASE + 0x014)
-#define PLL2_FRQ                        (MISC_BASE + 0x018)
-#define PLL_CLK_CFG                     (MISC_BASE + 0x020)
+#define PLL1_CTR                        (misc_base + 0x008)
+#define PLL1_FRQ                        (misc_base + 0x00C)
+#define PLL2_CTR                        (misc_base + 0x014)
+#define PLL2_FRQ                        (misc_base + 0x018)
+#define PLL_CLK_CFG                     (misc_base + 0x020)
         /* PLL_CLK_CFG register masks */
         #define MCTR_CLK_SHIFT          28
         #define MCTR_CLK_MASK           3
 
-#define CORE_CLK_CFG                    (MISC_BASE + 0x024)
+#define CORE_CLK_CFG                    (misc_base + 0x024)
         /* CORE CLK CFG register masks */
         #define GEN_SYNTH2_3_CLK_SHIFT  18
         #define GEN_SYNTH2_3_CLK_MASK   1
@@ -39,7 +38,7 @@ static DEFINE_SPINLOCK(_lock);
         #define PCLK_RATIO_SHIFT        8
         #define PCLK_RATIO_MASK         2
 
-#define PERIP_CLK_CFG                   (MISC_BASE + 0x028)
+#define PERIP_CLK_CFG                   (misc_base + 0x028)
         /* PERIP_CLK_CFG register masks */
         #define UART_CLK_SHIFT          4
         #define UART_CLK_MASK           1
@@ -50,7 +49,7 @@ static DEFINE_SPINLOCK(_lock);
         #define GPT2_CLK_SHIFT          12
         #define GPT_CLK_MASK            1
 
-#define PERIP1_CLK_ENB                  (MISC_BASE + 0x02C)
+#define PERIP1_CLK_ENB                  (misc_base + 0x02C)
         /* PERIP1_CLK_ENB register masks */
         #define UART_CLK_ENB            3
         #define SSP_CLK_ENB             5
@@ -69,7 +68,7 @@ static DEFINE_SPINLOCK(_lock);
         #define USBH_CLK_ENB            25
         #define C3_CLK_ENB              31
 
-#define RAS_CLK_ENB                     (MISC_BASE + 0x034)
+#define RAS_CLK_ENB                     (misc_base + 0x034)
         #define RAS_AHB_CLK_ENB         0
         #define RAS_PLL1_CLK_ENB        1
         #define RAS_APB_CLK_ENB         2
@@ -82,20 +81,20 @@ static DEFINE_SPINLOCK(_lock);
         #define RAS_SYNT2_CLK_ENB       10
         #define RAS_SYNT3_CLK_ENB       11
 
-#define PRSC0_CLK_CFG                   (MISC_BASE + 0x044)
-#define PRSC1_CLK_CFG                   (MISC_BASE + 0x048)
-#define PRSC2_CLK_CFG                   (MISC_BASE + 0x04C)
-#define AMEM_CLK_CFG                    (MISC_BASE + 0x050)
+#define PRSC0_CLK_CFG                   (misc_base + 0x044)
+#define PRSC1_CLK_CFG                   (misc_base + 0x048)
+#define PRSC2_CLK_CFG                   (misc_base + 0x04C)
+#define AMEM_CLK_CFG                    (misc_base + 0x050)
         #define AMEM_CLK_ENB            0
 
-#define CLCD_CLK_SYNT                   (MISC_BASE + 0x05C)
-#define FIRDA_CLK_SYNT                  (MISC_BASE + 0x060)
-#define UART_CLK_SYNT                   (MISC_BASE + 0x064)
-#define GMAC_CLK_SYNT                   (MISC_BASE + 0x068)
-#define GEN0_CLK_SYNT                   (MISC_BASE + 0x06C)
-#define GEN1_CLK_SYNT                   (MISC_BASE + 0x070)
-#define GEN2_CLK_SYNT                   (MISC_BASE + 0x074)
-#define GEN3_CLK_SYNT                   (MISC_BASE + 0x078)
+#define CLCD_CLK_SYNT                   (misc_base + 0x05C)
+#define FIRDA_CLK_SYNT                  (misc_base + 0x060)
+#define UART_CLK_SYNT                   (misc_base + 0x064)
+#define GMAC_CLK_SYNT                   (misc_base + 0x068)
+#define GEN0_CLK_SYNT                   (misc_base + 0x06C)
+#define GEN1_CLK_SYNT                   (misc_base + 0x070)
+#define GEN2_CLK_SYNT                   (misc_base + 0x074)
+#define GEN3_CLK_SYNT                   (misc_base + 0x078)
 
 /* pll rate configuration table, in ascending order of rates */
 static struct pll_rate_tbl pll_rtbl[] = {
@@ -211,6 +210,17 @@ static inline void spear310_clk_init(void) { }
 
 /* array of all spear 320 clock lookups */
 #ifdef CONFIG_MACH_SPEAR320
+
+#define SPEAR320_CONTROL_REG            (soc_config_base + 0x0000)
+#define SPEAR320_EXT_CTRL_REG           (soc_config_base + 0x0018)
+
+        #define SPEAR320_UARTX_PCLK_MASK                0x1
+        #define SPEAR320_UART2_PCLK_SHIFT               8
+        #define SPEAR320_UART3_PCLK_SHIFT               9
+        #define SPEAR320_UART4_PCLK_SHIFT               10
+        #define SPEAR320_UART5_PCLK_SHIFT               11
+        #define SPEAR320_UART6_PCLK_SHIFT               12
+        #define SPEAR320_RS485_PCLK_SHIFT               13
         #define SMII_PCLK_SHIFT                         18
         #define SMII_PCLK_MASK                          2
         #define SMII_PCLK_VAL_PAD                       0x0
@@ -235,7 +245,7 @@ static const char *smii0_parents[] = { "smii_125m_pad", "ras_pll2_clk",
         "ras_syn0_gclk", };
 static const char *uartx_parents[] = { "ras_syn1_gclk", "ras_apb_clk", };
 
-static void __init spear320_clk_init(void)
+static void __init spear320_clk_init(void __iomem *soc_config_base)
 {
         struct clk *clk;
 
@@ -362,7 +372,7 @@ static void __init spear320_clk_init(void)
 static inline void spear320_clk_init(void) { }
 #endif
 
-void __init spear3xx_clk_init(void)
+void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_base)
 {
         struct clk *clk, *clk1;
 
@@ -634,5 +644,5 @@ void __init spear3xx_clk_init(void)
         else if (of_machine_is_compatible("st,spear310"))
                 spear310_clk_init();
         else if (of_machine_is_compatible("st,spear320"))
-                spear320_clk_init();
+                spear320_clk_init(soc_config_base);
 }
diff --git a/drivers/clk/spear/spear6xx_clock.c b/drivers/clk/spear/spear6xx_clock.c
index e862a333ad30..9406f2426d64 100644
--- a/drivers/clk/spear/spear6xx_clock.c
+++ b/drivers/clk/spear/spear6xx_clock.c
@@ -13,28 +13,27 @@
 #include <linux/clkdev.h>
 #include <linux/io.h>
 #include <linux/spinlock_types.h>
-#include <mach/misc_regs.h>
 #include "clk.h"
 
 static DEFINE_SPINLOCK(_lock);
 
-#define PLL1_CTR                        (MISC_BASE + 0x008)
-#define PLL1_FRQ                        (MISC_BASE + 0x00C)
-#define PLL2_CTR                        (MISC_BASE + 0x014)
-#define PLL2_FRQ                        (MISC_BASE + 0x018)
-#define PLL_CLK_CFG                     (MISC_BASE + 0x020)
+#define PLL1_CTR                        (misc_base + 0x008)
+#define PLL1_FRQ                        (misc_base + 0x00C)
+#define PLL2_CTR                        (misc_base + 0x014)
+#define PLL2_FRQ                        (misc_base + 0x018)
+#define PLL_CLK_CFG                     (misc_base + 0x020)
         /* PLL_CLK_CFG register masks */
         #define MCTR_CLK_SHIFT          28
         #define MCTR_CLK_MASK           3
 
-#define CORE_CLK_CFG                    (MISC_BASE + 0x024)
+#define CORE_CLK_CFG                    (misc_base + 0x024)
         /* CORE CLK CFG register masks */
         #define HCLK_RATIO_SHIFT        10
         #define HCLK_RATIO_MASK         2
         #define PCLK_RATIO_SHIFT        8
         #define PCLK_RATIO_MASK         2
 
-#define PERIP_CLK_CFG                   (MISC_BASE + 0x028)
+#define PERIP_CLK_CFG                   (misc_base + 0x028)
         /* PERIP_CLK_CFG register masks */
         #define CLCD_CLK_SHIFT          2
         #define CLCD_CLK_MASK           2
@@ -48,7 +47,7 @@ static DEFINE_SPINLOCK(_lock);
         #define GPT3_CLK_SHIFT          12
         #define GPT_CLK_MASK            1
 
-#define PERIP1_CLK_ENB                  (MISC_BASE + 0x02C)
+#define PERIP1_CLK_ENB                  (misc_base + 0x02C)
         /* PERIP1_CLK_ENB register masks */
         #define UART0_CLK_ENB           3
         #define UART1_CLK_ENB           4
@@ -74,13 +73,13 @@ static DEFINE_SPINLOCK(_lock);
         #define USBH0_CLK_ENB           25
         #define USBH1_CLK_ENB           26
 
-#define PRSC0_CLK_CFG                   (MISC_BASE + 0x044)
-#define PRSC1_CLK_CFG                   (MISC_BASE + 0x048)
-#define PRSC2_CLK_CFG                   (MISC_BASE + 0x04C)
+#define PRSC0_CLK_CFG                   (misc_base + 0x044)
+#define PRSC1_CLK_CFG                   (misc_base + 0x048)
+#define PRSC2_CLK_CFG                   (misc_base + 0x04C)
 
-#define CLCD_CLK_SYNT                   (MISC_BASE + 0x05C)
-#define FIRDA_CLK_SYNT                  (MISC_BASE + 0x060)
-#define UART_CLK_SYNT                   (MISC_BASE + 0x064)
+#define CLCD_CLK_SYNT                   (misc_base + 0x05C)
+#define FIRDA_CLK_SYNT                  (misc_base + 0x060)
+#define UART_CLK_SYNT                   (misc_base + 0x064)
 
 /* vco rate configuration table, in ascending order of rates */
 static struct pll_rate_tbl pll_rtbl[] = {
@@ -115,7 +114,7 @@ static struct gpt_rate_tbl gpt_rtbl[] = {
         {.mscale = 1, .nscale = 0}, /* 83 MHz */
 };
 
-void __init spear6xx_clk_init(void)
+void __init spear6xx_clk_init(void __iomem *misc_base)
 {
         struct clk *clk, *clk1;
 
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
new file mode 100644
index 000000000000..b5bac917612c
--- /dev/null
+++ b/drivers/clk/sunxi/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for sunxi specific clk
+#
+
+obj-y += clk-sunxi.o clk-factors.o
diff --git a/drivers/clk/sunxi/clk-factors.c b/drivers/clk/sunxi/clk-factors.c
new file mode 100644
index 000000000000..88523f91d9b7
--- /dev/null
+++ b/drivers/clk/sunxi/clk-factors.c
@@ -0,0 +1,180 @@
+/*
+ * Copyright (C) 2013 Emilio López <emilio@elopez.com.ar>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Adjustable factor-based clock implementation
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/string.h>
+
+#include <linux/delay.h>
+
+#include "clk-factors.h"
+
+/*
+ * DOC: basic adjustable factor-based clock that cannot gate
+ *
+ * Traits of this clock:
+ * prepare - clk_prepare only ensures that parents are prepared
+ * enable - clk_enable only ensures that parents are enabled
+ * rate - rate is adjustable.
+ *        clk->rate = (parent->rate * N * (K + 1) >> P) / (M + 1)
+ * parent - fixed parent.  No clk_set_parent support
+ */
+
+struct clk_factors {
+        struct clk_hw hw;
+        void __iomem *reg;
+        struct clk_factors_config *config;
+        void (*get_factors) (u32 *rate, u32 parent, u8 *n, u8 *k, u8 *m, u8 *p);
+        spinlock_t *lock;
+};
+
+#define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw)
+
+#define SETMASK(len, pos)               (((-1U) >> (31-len))  << (pos))
+#define CLRMASK(len, pos)               (~(SETMASK(len, pos)))
+#define FACTOR_GET(bit, len, reg)       (((reg) & SETMASK(len, bit)) >> (bit))
+
+#define FACTOR_SET(bit, len, reg, val) \
+        (((reg) & CLRMASK(len, bit)) | (val << (bit)))
+
+static unsigned long clk_factors_recalc_rate(struct clk_hw *hw,
+                                             unsigned long parent_rate)
+{
+        u8 n = 1, k = 0, p = 0, m = 0;
+        u32 reg;
+        unsigned long rate;
+        struct clk_factors *factors = to_clk_factors(hw);
+        struct clk_factors_config *config = factors->config;
+
+        /* Fetch the register value */
+        reg = readl(factors->reg);
+
+        /* Get each individual factor if applicable */
+        if (config->nwidth != SUNXI_FACTORS_NOT_APPLICABLE)
+                n = FACTOR_GET(config->nshift, config->nwidth, reg);
+        if (config->kwidth != SUNXI_FACTORS_NOT_APPLICABLE)
+                k = FACTOR_GET(config->kshift, config->kwidth, reg);
+        if (config->mwidth != SUNXI_FACTORS_NOT_APPLICABLE)
+                m = FACTOR_GET(config->mshift, config->mwidth, reg);
+        if (config->pwidth != SUNXI_FACTORS_NOT_APPLICABLE)
+                p = FACTOR_GET(config->pshift, config->pwidth, reg);
+
+        /* Calculate the rate */
+        rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
+
+        return rate;
+}
+
+static long clk_factors_round_rate(struct clk_hw *hw, unsigned long rate,
+                                   unsigned long *parent_rate)
+{
+        struct clk_factors *factors = to_clk_factors(hw);
+        factors->get_factors((u32 *)&rate, (u32)*parent_rate,
+                             NULL, NULL, NULL, NULL);
+
+        return rate;
+}
+
+static int clk_factors_set_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long parent_rate)
+{
+        u8 n, k, m, p;
+        u32 reg;
+        struct clk_factors *factors = to_clk_factors(hw);
+        struct clk_factors_config *config = factors->config;
+        unsigned long flags = 0;
+
+        factors->get_factors((u32 *)&rate, (u32)parent_rate, &n, &k, &m, &p);
+
+        if (factors->lock)
+                spin_lock_irqsave(factors->lock, flags);
+
+        /* Fetch the register value */
+        reg = readl(factors->reg);
+
+        /* Set up the new factors - macros do not do anything if width is 0 */
+        reg = FACTOR_SET(config->nshift, config->nwidth, reg, n);
+        reg = FACTOR_SET(config->kshift, config->kwidth, reg, k);
+        reg = FACTOR_SET(config->mshift, config->mwidth, reg, m);
+        reg = FACTOR_SET(config->pshift, config->pwidth, reg, p);
+
+        /* Apply them now */
+        writel(reg, factors->reg);
+
+        /* delay 500us so pll stabilizes */
+        __delay((rate >> 20) * 500 / 2);
+
+        if (factors->lock)
+                spin_unlock_irqrestore(factors->lock, flags);
+
+        return 0;
+}
+
+static const struct clk_ops clk_factors_ops = {
+        .recalc_rate = clk_factors_recalc_rate,
+        .round_rate = clk_factors_round_rate,
+        .set_rate = clk_factors_set_rate,
+};
+
+/**
+ * clk_register_factors - register a factors clock with
+ * the clock framework
+ * @dev: device registering this clock
+ * @name: name of this clock
+ * @parent_name: name of clock's parent
+ * @flags: framework-specific flags
+ * @reg: register address to adjust factors
+ * @config: shift and width of factors n, k, m and p
+ * @get_factors: function to calculate the factors for a given frequency
+ * @lock: shared register lock for this clock
+ */
+struct clk *clk_register_factors(struct device *dev, const char *name,
+                                 const char *parent_name,
+                                 unsigned long flags, void __iomem *reg,
+                                 struct clk_factors_config *config,
+                                 void (*get_factors)(u32 *rate, u32 parent,
+                                                     u8 *n, u8 *k, u8 *m, u8 *p),
+                                 spinlock_t *lock)
+{
+        struct clk_factors *factors;
+        struct clk *clk;
+        struct clk_init_data init;
+
+        /* allocate the factors */
+        factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL);
+        if (!factors) {
+                pr_err("%s: could not allocate factors clk\n", __func__);
+                return ERR_PTR(-ENOMEM);
+        }
+
+        init.name = name;
+        init.ops = &clk_factors_ops;
+        init.flags = flags;
+        init.parent_names = (parent_name ? &parent_name : NULL);
+        init.num_parents = (parent_name ? 1 : 0);
+
+        /* struct clk_factors assignments */
+        factors->reg = reg;
+        factors->config = config;
+        factors->lock = lock;
+        factors->hw.init = &init;
+        factors->get_factors = get_factors;
+
+        /* register the clock */
+        clk = clk_register(dev, &factors->hw);
+
+        if (IS_ERR(clk))
+                kfree(factors);
+
+        return clk;
+}
diff --git a/drivers/clk/sunxi/clk-factors.h b/drivers/clk/sunxi/clk-factors.h
new file mode 100644
index 000000000000..f49851cc4380
--- /dev/null
+++ b/drivers/clk/sunxi/clk-factors.h
@@ -0,0 +1,27 @@
+#ifndef __MACH_SUNXI_CLK_FACTORS_H
+#define __MACH_SUNXI_CLK_FACTORS_H
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+
+#define SUNXI_FACTORS_NOT_APPLICABLE    (0)
+
+struct clk_factors_config {
+        u8 nshift;
+        u8 nwidth;
+        u8 kshift;
+        u8 kwidth;
+        u8 mshift;
+        u8 mwidth;
+        u8 pshift;
+        u8 pwidth;
+};
+
+struct clk *clk_register_factors(struct device *dev, const char *name,
+                                 const char *parent_name,
+                                 unsigned long flags, void __iomem *reg,
+                                 struct clk_factors_config *config,
+                                 void (*get_factors) (u32 *rate, u32 parent_rate,
+                                                      u8 *n, u8 *k, u8 *m, u8 *p),
+                                 spinlock_t *lock);
+#endif
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
new file mode 100644
index 000000000000..d528a2496690
--- /dev/null
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -0,0 +1,362 @@
+/*
+ * Copyright 2013 Emilio López
+ *
+ * Emilio López <emilio@elopez.com.ar>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/sunxi.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include "clk-factors.h"
+
+static DEFINE_SPINLOCK(clk_lock);
+
+/**
+ * sunxi_osc_clk_setup() - Setup function for gatable oscillator
+ */
+
+#define SUNXI_OSC24M_GATE       0
+
+static void __init sunxi_osc_clk_setup(struct device_node *node)
+{
+        struct clk *clk;
+        const char *clk_name = node->name;
+        const char *parent;
+        void *reg;
+
+        reg = of_iomap(node, 0);
+
+        parent = of_clk_get_parent_name(node, 0);
+
+        clk = clk_register_gate(NULL, clk_name, parent, CLK_IGNORE_UNUSED,
+                                reg, SUNXI_OSC24M_GATE, 0, &clk_lock);
+
+        if (clk) {
+                of_clk_add_provider(node, of_clk_src_simple_get, clk);
+                clk_register_clkdev(clk, clk_name, NULL);
+        }
+}
+
+
+
+/**
+ * sunxi_get_pll1_factors() - calculates n, k, m, p factors for PLL1
+ * PLL1 rate is calculated as follows
+ * rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
+ * parent_rate is always 24Mhz
+ */
+
+static void sunxi_get_pll1_factors(u32 *freq, u32 parent_rate,
+                                   u8 *n, u8 *k, u8 *m, u8 *p)
+{
+        u8 div;
+
+        /* Normalize value to a 6M multiple */
+        div = *freq / 6000000;
+        *freq = 6000000 * div;
+
+        /* we were called to round the frequency, we can now return */
+        if (n == NULL)
+                return;
+
+        /* m is always zero for pll1 */
+        *m = 0;
+
+        /* k is 1 only on these cases */
+        if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000)
+                *k = 1;
+        else
+                *k = 0;
+
+        /* p will be 3 for divs under 10 */
+        if (div < 10)
+                *p = 3;
+
+        /* p will be 2 for divs between 10 - 20 and odd divs under 32 */
+        else if (div < 20 || (div < 32 && (div & 1)))
+                *p = 2;
+
+        /* p will be 1 for even divs under 32, divs under 40 and odd pairs
+         * of divs between 40-62 */
+        else if (div < 40 || (div < 64 && (div & 2)))
+                *p = 1;
+
+        /* any other entries have p = 0 */
+        else
+                *p = 0;
+
+        /* calculate a suitable n based on k and p */
+        div <<= *p;
+        div /= (*k + 1);
+        *n = div / 4;
+}
+
+
+
+/**
+ * sunxi_get_apb1_factors() - calculates m, p factors for APB1
+ * APB1 rate is calculated as follows
+ * rate = (parent_rate >> p) / (m + 1);
+ */
+
+static void sunxi_get_apb1_factors(u32 *freq, u32 parent_rate,
+                                   u8 *n, u8 *k, u8 *m, u8 *p)
+{
+        u8 calcm, calcp;
+
+        if (parent_rate < *freq)
+                *freq = parent_rate;
+
+        parent_rate = (parent_rate + (*freq - 1)) / *freq;
+
+        /* Invalid rate! */
+        if (parent_rate > 32)
+                return;
+
+        if (parent_rate <= 4)
+                calcp = 0;
+        else if (parent_rate <= 8)
+                calcp = 1;
+        else if (parent_rate <= 16)
+                calcp = 2;
+        else
+                calcp = 3;
+
+        calcm = (parent_rate >> calcp) - 1;
+
+        *freq = (parent_rate >> calcp) / (calcm + 1);
+
+        /* we were called to round the frequency, we can now return */
+        if (n == NULL)
+                return;
+
+        *m = calcm;
+        *p = calcp;
+}
+
+
+
+/**
+ * sunxi_factors_clk_setup() - Setup function for factor clocks
+ */
+
+struct factors_data {
+        struct clk_factors_config *table;
+        void (*getter) (u32 *rate, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p);
+};
+
+static struct clk_factors_config pll1_config = {
+        .nshift = 8,
+        .nwidth = 5,
+        .kshift = 4,
+        .kwidth = 2,
+        .mshift = 0,
+        .mwidth = 2,
+        .pshift = 16,
+        .pwidth = 2,
+};
+
+static struct clk_factors_config apb1_config = {
+        .mshift = 0,
+        .mwidth = 5,
+        .pshift = 16,
+        .pwidth = 2,
+};
+
+static const __initconst struct factors_data pll1_data = {
+        .table = &pll1_config,
+        .getter = sunxi_get_pll1_factors,
+};
+
+static const __initconst struct factors_data apb1_data = {
+        .table = &apb1_config,
+        .getter = sunxi_get_apb1_factors,
+};
+
+static void __init sunxi_factors_clk_setup(struct device_node *node,
+                                           struct factors_data *data)
+{
+        struct clk *clk;
+        const char *clk_name = node->name;
+        const char *parent;
+        void *reg;
+
+        reg = of_iomap(node, 0);
+
+        parent = of_clk_get_parent_name(node, 0);
+
+        clk = clk_register_factors(NULL, clk_name, parent, CLK_IGNORE_UNUSED,
+                                   reg, data->table, data->getter, &clk_lock);
+
+        if (clk) {
+                of_clk_add_provider(node, of_clk_src_simple_get, clk);
+                clk_register_clkdev(clk, clk_name, NULL);
+        }
+}
+
+
+
+/**
+ * sunxi_mux_clk_setup() - Setup function for muxes
+ */
+
+#define SUNXI_MUX_GATE_WIDTH    2
+
+struct mux_data {
+        u8 shift;
+};
+
+static const __initconst struct mux_data cpu_data = {
+        .shift = 16,
+};
+
+static const __initconst struct mux_data apb1_mux_data = {
+        .shift = 24,
+};
+
+static void __init sunxi_mux_clk_setup(struct device_node *node,
+                                       struct mux_data *data)
+{
+        struct clk *clk;
+        const char *clk_name = node->name;
+        const char **parents = kmalloc(sizeof(char *) * 5, GFP_KERNEL);
+        void *reg;
+        int i = 0;
+
+        reg = of_iomap(node, 0);
+
+        while (i < 5 && (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
+                i++;
+
+        clk = clk_register_mux(NULL, clk_name, parents, i, 0, reg,
+                               data->shift, SUNXI_MUX_GATE_WIDTH,
+                               0, &clk_lock);
+
+        if (clk) {
+                of_clk_add_provider(node, of_clk_src_simple_get, clk);
+                clk_register_clkdev(clk, clk_name, NULL);
+        }
+}
+
+
+
+/**
+ * sunxi_divider_clk_setup() - Setup function for simple divider clocks
+ */
+
+#define SUNXI_DIVISOR_WIDTH     2
+
+struct div_data {
+        u8 shift;
+        u8 pow;
+};
+
+static const __initconst struct div_data axi_data = {
+        .shift = 0,
+        .pow = 0,
+};
+
+static const __initconst struct div_data ahb_data = {
+        .shift = 4,
+        .pow = 1,
+};
+
+static const __initconst struct div_data apb0_data = {
+        .shift = 8,
+        .pow = 1,
+};
+
+static void __init sunxi_divider_clk_setup(struct device_node *node,
+                                           struct div_data *data)
+{
+        struct clk *clk;
+        const char *clk_name = node->name;
+        const char *clk_parent;
+        void *reg;
+
+        reg = of_iomap(node, 0);
+
+        clk_parent = of_clk_get_parent_name(node, 0);
+
+        clk = clk_register_divider(NULL, clk_name, clk_parent, 0,
+                                   reg, data->shift, SUNXI_DIVISOR_WIDTH,
+                                   data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0,
+                                   &clk_lock);
+        if (clk) {
+                of_clk_add_provider(node, of_clk_src_simple_get, clk);
+                clk_register_clkdev(clk, clk_name, NULL);
+        }
+}
+
+
+/* Matches for of_clk_init */
+static const __initconst struct of_device_id clk_match[] = {
+        {.compatible = "fixed-clock", .data = of_fixed_clk_setup,},
+        {.compatible = "allwinner,sun4i-osc-clk", .data = sunxi_osc_clk_setup,},
+        {}
+};
+
+/* Matches for factors clocks */
+static const __initconst struct of_device_id clk_factors_match[] = {
+        {.compatible = "allwinner,sun4i-pll1-clk", .data = &pll1_data,},
+        {.compatible = "allwinner,sun4i-apb1-clk", .data = &apb1_data,},
+        {}
+};
+
+/* Matches for divider clocks */
+static const __initconst struct of_device_id clk_div_match[] = {
+        {.compatible = "allwinner,sun4i-axi-clk", .data = &axi_data,},
+        {.compatible = "allwinner,sun4i-ahb-clk", .data = &ahb_data,},
+        {.compatible = "allwinner,sun4i-apb0-clk", .data = &apb0_data,},
+        {}
+};
+
+/* Matches for mux clocks */
+static const __initconst struct of_device_id clk_mux_match[] = {
+        {.compatible = "allwinner,sun4i-cpu-clk", .data = &cpu_data,},
+        {.compatible = "allwinner,sun4i-apb1-mux-clk", .data = &apb1_mux_data,},
+        {}
+};
+
+static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match,
+                                              void *function)
+{
+        struct device_node *np;
+        const struct div_data *data;
+        const struct of_device_id *match;
+        void (*setup_function)(struct device_node *, const void *) = function;
+
+        for_each_matching_node(np, clk_match) {
+                match = of_match_node(clk_match, np);
+                data = match->data;
+                setup_function(np, data);
+        }
+}
+
+void __init sunxi_init_clocks(void)
+{
+        /* Register all the simple sunxi clocks on DT */
+        of_clk_init(clk_match);
+
+        /* Register factor clocks */
+        of_sunxi_table_clock_setup(clk_factors_match, sunxi_factors_clk_setup);
+
+        /* Register divider clocks */
+        of_sunxi_table_clock_setup(clk_div_match, sunxi_divider_clk_setup);
+
+        /* Register mux clocks */
+        of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
+}
diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile
index 2b41b0f4f731..f49fac2d193a 100644
--- a/drivers/clk/tegra/Makefile
+++ b/drivers/clk/tegra/Makefile
@@ -9,3 +9,4 @@ obj-y					+= clk-super.o
 
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += clk-tegra20.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += clk-tegra30.o
+obj-$(CONFIG_ARCH_TEGRA_114_SOC)        += clk-tegra114.o
diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c
index 6dd533251e7b..bafee9895a24 100644
--- a/drivers/clk/tegra/clk-periph-gate.c
+++ b/drivers/clk/tegra/clk-periph-gate.c
@@ -41,7 +41,9 @@ static DEFINE_SPINLOCK(periph_ref_lock);
 #define write_rst_clr(val, gate) \
         writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
 
-#define periph_clk_to_bit(periph) (1 << (gate->clk_num % 32))
+#define periph_clk_to_bit(gate) (1 << (gate->clk_num % 32))
+
+#define LVL2_CLK_GATE_OVRE 0x554
 
 /* Peripheral gate clock ops */
 static int clk_periph_is_enabled(struct clk_hw *hw)
@@ -83,6 +85,13 @@ static int clk_periph_enable(struct clk_hw *hw)
                 }
         }
 
+        if (gate->flags & TEGRA_PERIPH_WAR_1005168) {
+                writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE);
+                writel_relaxed(BIT(22), gate->clk_base + LVL2_CLK_GATE_OVRE);
+                udelay(1);
+                writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE);
+        }
+
         spin_unlock_irqrestore(&periph_ref_lock, flags);
 
         return 0;
diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c
index 788486e6331a..b2309d37a963 100644
--- a/drivers/clk/tegra/clk-periph.c
+++ b/drivers/clk/tegra/clk-periph.c
@@ -16,6 +16,7 @@
 
 #include <linux/clk.h>
 #include <linux/clk-provider.h>
+#include <linux/export.h>
 #include <linux/slab.h>
 #include <linux/err.h>
 
@@ -128,6 +129,7 @@ void tegra_periph_reset_deassert(struct clk *c)
 
         tegra_periph_reset(gate, 0);
 }
+EXPORT_SYMBOL(tegra_periph_reset_deassert);
 
 void tegra_periph_reset_assert(struct clk *c)
 {
@@ -147,6 +149,7 @@ void tegra_periph_reset_assert(struct clk *c)
 
         tegra_periph_reset(gate, 1);
 }
+EXPORT_SYMBOL(tegra_periph_reset_assert);
 
 const struct clk_ops tegra_clk_periph_ops = {
         .get_parent = clk_periph_get_parent,
@@ -170,14 +173,15 @@ const struct clk_ops tegra_clk_periph_nodiv_ops = {
 static struct clk *_tegra_clk_register_periph(const char *name,
                         const char **parent_names, int num_parents,
                         struct tegra_clk_periph *periph,
-                        void __iomem *clk_base, u32 offset, bool div)
+                        void __iomem *clk_base, u32 offset, bool div,
+                        unsigned long flags)
 {
         struct clk *clk;
         struct clk_init_data init;
 
         init.name = name;
         init.ops = div ? &tegra_clk_periph_ops : &tegra_clk_periph_nodiv_ops;
-        init.flags = div ? 0 : CLK_SET_RATE_PARENT;
+        init.flags = flags;
         init.parent_names = parent_names;
         init.num_parents = num_parents;
 
@@ -202,10 +206,10 @@ static struct clk *_tegra_clk_register_periph(const char *name,
 struct clk *tegra_clk_register_periph(const char *name,
                 const char **parent_names, int num_parents,
                 struct tegra_clk_periph *periph, void __iomem *clk_base,
-                u32 offset)
+                u32 offset, unsigned long flags)
 {
         return _tegra_clk_register_periph(name, parent_names, num_parents,
-                        periph, clk_base, offset, true);
+                        periph, clk_base, offset, true, flags);
 }
 
 struct clk *tegra_clk_register_periph_nodiv(const char *name,
@@ -214,5 +218,5 @@ struct clk *tegra_clk_register_periph_nodiv(const char *name,
                 u32 offset)
 {
         return _tegra_clk_register_periph(name, parent_names, num_parents,
-                        periph, clk_base, offset, false);
+                        periph, clk_base, offset, false, CLK_SET_RATE_PARENT);
 }
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 165f24734c1b..17c2cc086eb4 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2012, 2013, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -79,6 +79,48 @@
 #define PLLE_SS_CTRL 0x68
 #define PLLE_SS_DISABLE (7 << 10)
 
+#define PLLE_AUX_PLLP_SEL       BIT(2)
+#define PLLE_AUX_ENABLE_SWCTL   BIT(4)
+#define PLLE_AUX_SEQ_ENABLE     BIT(24)
+#define PLLE_AUX_PLLRE_SEL      BIT(28)
+
+#define PLLE_MISC_PLLE_PTS      BIT(8)
+#define PLLE_MISC_IDDQ_SW_VALUE BIT(13)
+#define PLLE_MISC_IDDQ_SW_CTRL  BIT(14)
+#define PLLE_MISC_VREG_BG_CTRL_SHIFT    4
+#define PLLE_MISC_VREG_BG_CTRL_MASK     (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT)
+#define PLLE_MISC_VREG_CTRL_SHIFT       2
+#define PLLE_MISC_VREG_CTRL_MASK        (2 << PLLE_MISC_VREG_CTRL_SHIFT)
+
+#define PLLCX_MISC_STROBE       BIT(31)
+#define PLLCX_MISC_RESET        BIT(30)
+#define PLLCX_MISC_SDM_DIV_SHIFT 28
+#define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT)
+#define PLLCX_MISC_FILT_DIV_SHIFT 26
+#define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT)
+#define PLLCX_MISC_ALPHA_SHIFT 18
+#define PLLCX_MISC_DIV_LOW_RANGE \
+                ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | \
+                (0x1 << PLLCX_MISC_FILT_DIV_SHIFT))
+#define PLLCX_MISC_DIV_HIGH_RANGE \
+                ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | \
+                (0x2 << PLLCX_MISC_FILT_DIV_SHIFT))
+#define PLLCX_MISC_COEF_LOW_RANGE \
+                ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT))
+#define PLLCX_MISC_KA_SHIFT 2
+#define PLLCX_MISC_KB_SHIFT 9
+#define PLLCX_MISC_DEFAULT (PLLCX_MISC_COEF_LOW_RANGE | \
+                            (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \
+                            PLLCX_MISC_DIV_LOW_RANGE | \
+                            PLLCX_MISC_RESET)
+#define PLLCX_MISC1_DEFAULT 0x000d2308
+#define PLLCX_MISC2_DEFAULT 0x30211200
+#define PLLCX_MISC3_DEFAULT 0x200
+
+#define PMC_PLLM_WB0_OVERRIDE   0x1dc
+#define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
+#define PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK BIT(27)
+
 #define PMC_SATA_PWRGT 0x1ac
 #define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5)
 #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4)
@@ -101,6 +143,24 @@
 #define divn_max(p) (divn_mask(p))
 #define divp_max(p) (1 << (divp_mask(p)))
 
+
+#ifdef CONFIG_ARCH_TEGRA_114_SOC
+/* PLLXC has 4-bit PDIV, but entry 15 is not allowed in h/w */
+#define PLLXC_PDIV_MAX                  14
+
+/* non-monotonic mapping below is not a typo */
+static u8 pllxc_p[PLLXC_PDIV_MAX + 1] = {
+        /* PDIV: 0, 1, 2, 3, 4, 5, 6,  7,  8,  9, 10, 11, 12, 13, 14 */
+        /* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32
+};
+
+#define PLLCX_PDIV_MAX 7
+static u8 pllcx_p[PLLCX_PDIV_MAX + 1] = {
+        /* PDIV: 0, 1, 2, 3, 4, 5,  6,  7 */
+        /* p: */ 1, 2, 3, 4, 6, 8, 12, 16
+};
+#endif
+
 static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
 {
         u32 val;
@@ -108,25 +168,36 @@ static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
         if (!(pll->flags & TEGRA_PLL_USE_LOCK))
                 return;
 
+        if (!(pll->flags & TEGRA_PLL_HAS_LOCK_ENABLE))
+                return;
+
         val = pll_readl_misc(pll);
         val |= BIT(pll->params->lock_enable_bit_idx);
         pll_writel_misc(val, pll);
 }
 
-static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll,
-                                 void __iomem *lock_addr, u32 lock_bit_idx)
+static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
 {
         int i;
-        u32 val;
+        u32 val, lock_mask;
+        void __iomem *lock_addr;
 
         if (!(pll->flags & TEGRA_PLL_USE_LOCK)) {
                 udelay(pll->params->lock_delay);
                 return 0;
         }
 
+        lock_addr = pll->clk_base;
+        if (pll->flags & TEGRA_PLL_LOCK_MISC)
+                lock_addr += pll->params->misc_reg;
+        else
+                lock_addr += pll->params->base_reg;
+
+        lock_mask = pll->params->lock_mask;
+
         for (i = 0; i < pll->params->lock_delay; i++) {
                 val = readl_relaxed(lock_addr);
-                if (val & BIT(lock_bit_idx)) {
+                if ((val & lock_mask) == lock_mask) {
                         udelay(PLL_POST_LOCK_DELAY);
                         return 0;
                 }
@@ -155,7 +226,7 @@ static int clk_pll_is_enabled(struct clk_hw *hw)
         return val & PLL_BASE_ENABLE ? 1 : 0;
 }
 
-static int _clk_pll_enable(struct clk_hw *hw)
+static void _clk_pll_enable(struct clk_hw *hw)
 {
         struct tegra_clk_pll *pll = to_clk_pll(hw);
         u32 val;
@@ -163,7 +234,8 @@ static int _clk_pll_enable(struct clk_hw *hw)
         clk_pll_enable_lock(pll);
 
         val = pll_readl_base(pll);
-        val &= ~PLL_BASE_BYPASS;
+        if (pll->flags & TEGRA_PLL_BYPASS)
+                val &= ~PLL_BASE_BYPASS;
         val |= PLL_BASE_ENABLE;
         pll_writel_base(val, pll);
 
@@ -172,11 +244,6 @@ static int _clk_pll_enable(struct clk_hw *hw)
                 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
                 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
         }
-
-        clk_pll_wait_for_lock(pll, pll->clk_base + pll->params->base_reg,
-                              pll->params->lock_bit_idx);
-
-        return 0;
 }
 
 static void _clk_pll_disable(struct clk_hw *hw)
@@ -185,7 +252,9 @@ static void _clk_pll_disable(struct clk_hw *hw)
         u32 val;
 
         val = pll_readl_base(pll);
-        val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
+        if (pll->flags & TEGRA_PLL_BYPASS)
+                val &= ~PLL_BASE_BYPASS;
+        val &= ~PLL_BASE_ENABLE;
         pll_writel_base(val, pll);
 
         if (pll->flags & TEGRA_PLLM) {
@@ -204,7 +273,9 @@ static int clk_pll_enable(struct clk_hw *hw)
         if (pll->lock)
                 spin_lock_irqsave(pll->lock, flags);
 
-        ret = _clk_pll_enable(hw);
+        _clk_pll_enable(hw);
+
+        ret = clk_pll_wait_for_lock(pll);
 
         if (pll->lock)
                 spin_unlock_irqrestore(pll->lock, flags);
@@ -241,8 +312,6 @@ static int _get_table_rate(struct clk_hw *hw,
         if (sel->input_rate == 0)
                 return -EINVAL;
 
-        BUG_ON(sel->p < 1);
-
         cfg->input_rate = sel->input_rate;
         cfg->output_rate = sel->output_rate;
         cfg->m = sel->m;
@@ -257,6 +326,7 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
                       unsigned long rate, unsigned long parent_rate)
 {
         struct tegra_clk_pll *pll = to_clk_pll(hw);
+        struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
         unsigned long cfreq;
         u32 p_div = 0;
 
@@ -290,88 +360,119 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
              cfg->output_rate <<= 1)
                 p_div++;
 
-        cfg->p = 1 << p_div;
         cfg->m = parent_rate / cfreq;
         cfg->n = cfg->output_rate / cfreq;
         cfg->cpcon = OUT_OF_TABLE_CPCON;
 
         if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) ||
-            cfg->p > divp_max(pll) || cfg->output_rate > pll->params->vco_max) {
+            (1 << p_div) > divp_max(pll)
+            || cfg->output_rate > pll->params->vco_max) {
                 pr_err("%s: Failed to set %s rate %lu\n",
                        __func__, __clk_get_name(hw->clk), rate);
                 return -EINVAL;
         }
 
+        if (p_tohw) {
+                p_div = 1 << p_div;
+                while (p_tohw->pdiv) {
+                        if (p_div <= p_tohw->pdiv) {
+                                cfg->p = p_tohw->hw_val;
+                                break;
+                        }
+                        p_tohw++;
+                }
+                if (!p_tohw->pdiv)
+                        return -EINVAL;
+        } else
+                cfg->p = p_div;
+
         return 0;
 }
 
-static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
-                        unsigned long rate)
+static void _update_pll_mnp(struct tegra_clk_pll *pll,
+                            struct tegra_clk_pll_freq_table *cfg)
 {
-        struct tegra_clk_pll *pll = to_clk_pll(hw);
-        unsigned long flags = 0;
-        u32 divp, val, old_base;
-        int state;
-
-        divp = __ffs(cfg->p);
-
-        if (pll->flags & TEGRA_PLLU)
-                divp ^= 1;
+        u32 val;
 
-        if (pll->lock)
-                spin_lock_irqsave(pll->lock, flags);
+        val = pll_readl_base(pll);
 
-        old_base = val = pll_readl_base(pll);
         val &= ~((divm_mask(pll) << pll->divm_shift) |
                  (divn_mask(pll) << pll->divn_shift) |
                  (divp_mask(pll) << pll->divp_shift));
         val |= ((cfg->m << pll->divm_shift) |
                 (cfg->n << pll->divn_shift) |
-                (divp << pll->divp_shift));
-        if (val == old_base) {
-                if (pll->lock)
-                        spin_unlock_irqrestore(pll->lock, flags);
-                return 0;
+                (cfg->p << pll->divp_shift));
+
+        pll_writel_base(val, pll);
+}
+
+static void _get_pll_mnp(struct tegra_clk_pll *pll,
+                         struct tegra_clk_pll_freq_table *cfg)
+{
+        u32 val;
+
+        val = pll_readl_base(pll);
+
+        cfg->m = (val >> pll->divm_shift) & (divm_mask(pll));
+        cfg->n = (val >> pll->divn_shift) & (divn_mask(pll));
+        cfg->p = (val >> pll->divp_shift) & (divp_mask(pll));
+}
+
+static void _update_pll_cpcon(struct tegra_clk_pll *pll,
+                              struct tegra_clk_pll_freq_table *cfg,
+                              unsigned long rate)
+{
+        u32 val;
+
+        val = pll_readl_misc(pll);
+
+        val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT);
+        val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT;
+
+        if (pll->flags & TEGRA_PLL_SET_LFCON) {
+                val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT);
+                if (cfg->n >= PLLDU_LFCON_SET_DIVN)
+                        val |= 1 << PLL_MISC_LFCON_SHIFT;
+        } else if (pll->flags & TEGRA_PLL_SET_DCCON) {
+                val &= ~(1 << PLL_MISC_DCCON_SHIFT);
+                if (rate >= (pll->params->vco_max >> 1))
+                        val |= 1 << PLL_MISC_DCCON_SHIFT;
         }
 
+        pll_writel_misc(val, pll);
+}
+
+static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
+                        unsigned long rate)
+{
+        struct tegra_clk_pll *pll = to_clk_pll(hw);
+        int state, ret = 0;
+
         state = clk_pll_is_enabled(hw);
 
-        if (state) {
+        if (state)
                 _clk_pll_disable(hw);
-                val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
-        }
-        pll_writel_base(val, pll);
 
-        if (pll->flags & TEGRA_PLL_HAS_CPCON) {
-                val = pll_readl_misc(pll);
-                val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT);
-                val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT;
-                if (pll->flags & TEGRA_PLL_SET_LFCON) {
-                        val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT);
-                        if (cfg->n >= PLLDU_LFCON_SET_DIVN)
-                                val |= 0x1 << PLL_MISC_LFCON_SHIFT;
-                } else if (pll->flags & TEGRA_PLL_SET_DCCON) {
-                        val &= ~(0x1 << PLL_MISC_DCCON_SHIFT);
-                        if (rate >= (pll->params->vco_max >> 1))
-                                val |= 0x1 << PLL_MISC_DCCON_SHIFT;
-                }
-                pll_writel_misc(val, pll);
-        }
+        _update_pll_mnp(pll, cfg);
 
-        if (pll->lock)
-                spin_unlock_irqrestore(pll->lock, flags);
+        if (pll->flags & TEGRA_PLL_HAS_CPCON)
+                _update_pll_cpcon(pll, cfg, rate);
 
-        if (state)
-                clk_pll_enable(hw);
+        if (state) {
+                _clk_pll_enable(hw);
+                ret = clk_pll_wait_for_lock(pll);
+        }
 
-        return 0;
+        return ret;
 }
 
 static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
                         unsigned long parent_rate)
 {
         struct tegra_clk_pll *pll = to_clk_pll(hw);
-        struct tegra_clk_pll_freq_table cfg;
+        struct tegra_clk_pll_freq_table cfg, old_cfg;
+        unsigned long flags = 0;
+        int ret = 0;
 
         if (pll->flags & TEGRA_PLL_FIXED) {
                 if (rate != pll->fixed_rate) {
@@ -387,7 +488,18 @@ static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
             _calc_rate(hw, &cfg, rate, parent_rate))
                 return -EINVAL;
 
-        return _program_pll(hw, &cfg, rate);
+        if (pll->lock)
+                spin_lock_irqsave(pll->lock, flags);
+
+        _get_pll_mnp(pll, &old_cfg);
+
+        if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p)
+                ret = _program_pll(hw, &cfg, rate);
+
+        if (pll->lock)
+                spin_unlock_irqrestore(pll->lock, flags);
+
+        return ret;
 }
 
 static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
@@ -409,7 +521,7 @@ static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
                 return -EINVAL;
 
         output_rate *= cfg.n;
-        do_div(output_rate, cfg.m * cfg.p);
+        do_div(output_rate, cfg.m * (1 << cfg.p));
 
         return output_rate;
 }
@@ -418,11 +530,15 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
                                          unsigned long parent_rate)
 {
         struct tegra_clk_pll *pll = to_clk_pll(hw);
-        u32 val = pll_readl_base(pll);
-        u32 divn = 0, divm = 0, divp = 0;
+        struct tegra_clk_pll_freq_table cfg;
+        struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
+        u32 val;
         u64 rate = parent_rate;
+        int pdiv;
+
+        val = pll_readl_base(pll);
 
-        if (val & PLL_BASE_BYPASS)
+        if ((pll->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS))
                 return parent_rate;
 
         if ((pll->flags & TEGRA_PLL_FIXED) && !(val & PLL_BASE_OVERRIDE)) {
@@ -435,16 +551,29 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
                 return pll->fixed_rate;
         }
 
-        divp = (val >> pll->divp_shift) & (divp_mask(pll));
-        if (pll->flags & TEGRA_PLLU)
-                divp ^= 1;
+        _get_pll_mnp(pll, &cfg);
 
-        divn = (val >> pll->divn_shift) & (divn_mask(pll));
-        divm = (val >> pll->divm_shift) & (divm_mask(pll));
-        divm *= (1 << divp);
+        if (p_tohw) {
+                while (p_tohw->pdiv) {
+                        if (cfg.p == p_tohw->hw_val) {
+                                pdiv = p_tohw->pdiv;
+                                break;
+                        }
+                        p_tohw++;
+                }
+
+                if (!p_tohw->pdiv) {
+                        WARN_ON(1);
+                        pdiv = 1;
+                }
+        } else
+                pdiv = 1 << cfg.p;
+
+        cfg.m *= pdiv;
+
+        rate *= cfg.n;
+        do_div(rate, cfg.m);
 
-        rate *= divn;
-        do_div(rate, divm);
         return rate;
 }
 
@@ -538,8 +667,8 @@ static int clk_plle_enable(struct clk_hw *hw)
         val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE);
         pll_writel_base(val, pll);
 
-        clk_pll_wait_for_lock(pll, pll->clk_base + pll->params->misc_reg,
-                              pll->params->lock_bit_idx);
+        clk_pll_wait_for_lock(pll);
+
         return 0;
 }
 
@@ -577,28 +706,531 @@ const struct clk_ops tegra_clk_plle_ops = {
         .enable = clk_plle_enable,
 };
 
-static struct clk *_tegra_clk_register_pll(const char *name,
-                const char *parent_name, void __iomem *clk_base,
-                void __iomem *pmc, unsigned long flags,
-                unsigned long fixed_rate,
-                struct tegra_clk_pll_params *pll_params, u8 pll_flags,
-                struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock,
-                const struct clk_ops *ops)
+#ifdef CONFIG_ARCH_TEGRA_114_SOC
+
+static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,
+                           unsigned long parent_rate)
+{
+        if (parent_rate > pll_params->cf_max)
+                return 2;
+        else
+                return 1;
+}
+
+static int clk_pll_iddq_enable(struct clk_hw *hw)
+{
+        struct tegra_clk_pll *pll = to_clk_pll(hw);
+        unsigned long flags = 0;
+
+        u32 val;
+        int ret;
+
+        if (pll->lock)
+                spin_lock_irqsave(pll->lock, flags);
+
+        val = pll_readl(pll->params->iddq_reg, pll);
+        val &= ~BIT(pll->params->iddq_bit_idx);
+        pll_writel(val, pll->params->iddq_reg, pll);
+        udelay(2);
+
+        _clk_pll_enable(hw);
+
+        ret = clk_pll_wait_for_lock(pll);
+
+        if (pll->lock)
+                spin_unlock_irqrestore(pll->lock, flags);
+
+        return 0;
+}
+
+static void clk_pll_iddq_disable(struct clk_hw *hw)
+{
+        struct tegra_clk_pll *pll = to_clk_pll(hw);
+        unsigned long flags = 0;
+        u32 val;
+
+        if (pll->lock)
+                spin_lock_irqsave(pll->lock, flags);
+
+        _clk_pll_disable(hw);
+
+        val = pll_readl(pll->params->iddq_reg, pll);
+        val |= BIT(pll->params->iddq_bit_idx);
+        pll_writel(val, pll->params->iddq_reg, pll);
+        udelay(2);
+
+        if (pll->lock)
+                spin_unlock_irqrestore(pll->lock, flags);
+}
+
+static int _calc_dynamic_ramp_rate(struct clk_hw *hw,
+                                struct tegra_clk_pll_freq_table *cfg,
+                                unsigned long rate, unsigned long parent_rate)
+{
+        struct tegra_clk_pll *pll = to_clk_pll(hw);
+        unsigned int p;
+
+        if (!rate)
+                return -EINVAL;
+
+        p = DIV_ROUND_UP(pll->params->vco_min, rate);
+        cfg->m = _pll_fixed_mdiv(pll->params, parent_rate);
+        cfg->p = p;
+        cfg->output_rate = rate * cfg->p;
+        cfg->n = cfg->output_rate * cfg->m / parent_rate;
+
+        if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max)
+                return -EINVAL;
+
+        return 0;
+}
+
+static int _pll_ramp_calc_pll(struct clk_hw *hw,
+                              struct tegra_clk_pll_freq_table *cfg,
+                              unsigned long rate, unsigned long parent_rate)
+{
+        struct tegra_clk_pll *pll = to_clk_pll(hw);
+        int err = 0;
+
+        err = _get_table_rate(hw, cfg, rate, parent_rate);
+        if (err < 0)
+                err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate);
+        else if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) {
+                        WARN_ON(1);
+                        err = -EINVAL;
+                        goto out;
+        }
+
+        if (!cfg->p || (cfg->p >  pll->params->max_p))
+                err = -EINVAL;
+
+out:
+        return err;
+}
+
+static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long parent_rate)
+{
+        struct tegra_clk_pll *pll = to_clk_pll(hw);
+        struct tegra_clk_pll_freq_table cfg, old_cfg;
+        unsigned long flags = 0;
+        int ret = 0;
+        u8 old_p;
+
+        ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
+        if (ret < 0)
+                return ret;
+
+        if (pll->lock)
+                spin_lock_irqsave(pll->lock, flags);
+
+        _get_pll_mnp(pll, &old_cfg);
+
+        old_p = pllxc_p[old_cfg.p];
+        if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_p != cfg.p) {
+                cfg.p -= 1;
+                ret = _program_pll(hw, &cfg, rate);
+        }
+
+        if (pll->lock)
+                spin_unlock_irqrestore(pll->lock, flags);
+
+        return ret;
+}
+
+static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long *prate)
+{
+        struct tegra_clk_pll_freq_table cfg;
+        int ret = 0;
+        u64 output_rate = *prate;
+
+        ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate);
+        if (ret < 0)
+                return ret;
+
+        output_rate *= cfg.n;
+        do_div(output_rate, cfg.m * cfg.p);
+
+        return output_rate;
+}
+
+static int clk_pllm_set_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long parent_rate)
+{
+        struct tegra_clk_pll_freq_table cfg;
+        struct tegra_clk_pll *pll = to_clk_pll(hw);
+        unsigned long flags = 0;
+        int state, ret = 0;
+        u32 val;
+
+        if (pll->lock)
+                spin_lock_irqsave(pll->lock, flags);
+
+        state = clk_pll_is_enabled(hw);
+        if (state) {
+                if (rate != clk_get_rate(hw->clk)) {
+                        pr_err("%s: Cannot change active PLLM\n", __func__);
+                        ret = -EINVAL;
+                        goto out;
+                }
+                goto out;
+        }
+
+        ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
+        if (ret < 0)
+                goto out;
+
+        cfg.p -= 1;
+
+        val = readl_relaxed(pll->pmc + PMC_PLLM_WB0_OVERRIDE);
+        if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) {
+                val = readl_relaxed(pll->pmc + PMC_PLLM_WB0_OVERRIDE_2);
+                val = cfg.p ? (val | PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK) :
+                        (val & ~PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK);
+                writel_relaxed(val, pll->pmc + PMC_PLLM_WB0_OVERRIDE_2);
+
+                val = readl_relaxed(pll->pmc + PMC_PLLM_WB0_OVERRIDE);
+                val &= ~(divn_mask(pll) | divm_mask(pll));
+                val |= (cfg.m << pll->divm_shift) | (cfg.n << pll->divn_shift);
+                writel_relaxed(val, pll->pmc + PMC_PLLM_WB0_OVERRIDE);
+        } else
+                _update_pll_mnp(pll, &cfg);
+
+
+out:
+        if (pll->lock)
+                spin_unlock_irqrestore(pll->lock, flags);
+
+        return ret;
+}
+
+static void _pllcx_strobe(struct tegra_clk_pll *pll)
+{
+        u32 val;
+
+        val = pll_readl_misc(pll);
+        val |= PLLCX_MISC_STROBE;
+        pll_writel_misc(val, pll);
+        udelay(2);
+
+        val &= ~PLLCX_MISC_STROBE;
+        pll_writel_misc(val, pll);
+}
+
+static int clk_pllc_enable(struct clk_hw *hw)
+{
+        struct tegra_clk_pll *pll = to_clk_pll(hw);
+        u32 val;
+        int ret = 0;
+        unsigned long flags = 0;
+
+        if (pll->lock)
+                spin_lock_irqsave(pll->lock, flags);
+
+        _clk_pll_enable(hw);
+        udelay(2);
+
+        val = pll_readl_misc(pll);
+        val &= ~PLLCX_MISC_RESET;
+        pll_writel_misc(val, pll);
+        udelay(2);
+
+        _pllcx_strobe(pll);
+
+        ret = clk_pll_wait_for_lock(pll);
+
+        if (pll->lock)
+                spin_unlock_irqrestore(pll->lock, flags);
+
+        return ret;
+}
+
+static void _clk_pllc_disable(struct clk_hw *hw)
+{
+        struct tegra_clk_pll *pll = to_clk_pll(hw);
+        u32 val;
+
+        _clk_pll_disable(hw);
+
+        val = pll_readl_misc(pll);
+        val |= PLLCX_MISC_RESET;
+        pll_writel_misc(val, pll);
+        udelay(2);
+}
+
+static void clk_pllc_disable(struct clk_hw *hw)
+{
+        struct tegra_clk_pll *pll = to_clk_pll(hw);
+        unsigned long flags = 0;
+
+        if (pll->lock)
+                spin_lock_irqsave(pll->lock, flags);
+
+        _clk_pllc_disable(hw);
+
+        if (pll->lock)
+                spin_unlock_irqrestore(pll->lock, flags);
+}
+
+static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll,
+                                        unsigned long input_rate, u32 n)
+{
+        u32 val, n_threshold;
+
+        switch (input_rate) {
+        case 12000000:
+                n_threshold = 70;
+                break;
+        case 13000000:
+        case 26000000:
+                n_threshold = 71;
+                break;
+        case 16800000:
+                n_threshold = 55;
+                break;
+        case 19200000:
+                n_threshold = 48;
+                break;
+        default:
+                pr_err("%s: Unexpected reference rate %lu\n",
+                        __func__, input_rate);
+                return -EINVAL;
+        }
+
+        val = pll_readl_misc(pll);
+        val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK);
+        val |= n <= n_threshold ?
+                PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE;
+        pll_writel_misc(val, pll);
+
+        return 0;
+}
+
+static int clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long parent_rate)
+{
+        struct tegra_clk_pll_freq_table cfg;
+        struct tegra_clk_pll *pll = to_clk_pll(hw);
+        unsigned long flags = 0;
+        int state, ret = 0;
+        u32 val;
+        u16 old_m, old_n;
+        u8 old_p;
+
+        if (pll->lock)
+                spin_lock_irqsave(pll->lock, flags);
+
+        ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
+        if (ret < 0)
+                goto out;
+
+        val = pll_readl_base(pll);
+        old_m = (val >> pll->divm_shift) & (divm_mask(pll));
+        old_n = (val >> pll->divn_shift) & (divn_mask(pll));
+        old_p = pllcx_p[(val >> pll->divp_shift) & (divp_mask(pll))];
+
+        if (cfg.m != old_m) {
+                WARN_ON(1);
+                goto out;
+        }
+
+        if (old_n == cfg.n && old_p == cfg.p)
+                goto out;
+
+        cfg.p -= 1;
+
+        state = clk_pll_is_enabled(hw);
+        if (state)
+                _clk_pllc_disable(hw);
+
+        ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
+        if (ret < 0)
+                goto out;
+
+        _update_pll_mnp(pll, &cfg);
+
+        if (state)
+                ret = clk_pllc_enable(hw);
+
+out:
+        if (pll->lock)
+                spin_unlock_irqrestore(pll->lock, flags);
+
+        return ret;
+}
+
+static long _pllre_calc_rate(struct tegra_clk_pll *pll,
+                             struct tegra_clk_pll_freq_table *cfg,
+                             unsigned long rate, unsigned long parent_rate)
+{
+        u16 m, n;
+        u64 output_rate = parent_rate;
+
+        m = _pll_fixed_mdiv(pll->params, parent_rate);
+        n = rate * m / parent_rate;
+
+        output_rate *= n;
+        do_div(output_rate, m);
+
+        if (cfg) {
+                cfg->m = m;
+                cfg->n = n;
+        }
+
+        return output_rate;
+}
+static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long parent_rate)
+{
+        struct tegra_clk_pll_freq_table cfg, old_cfg;
+        struct tegra_clk_pll *pll = to_clk_pll(hw);
+        unsigned long flags = 0;
+        int state, ret = 0;
+
+        if (pll->lock)
+                spin_lock_irqsave(pll->lock, flags);
+
+        _pllre_calc_rate(pll, &cfg, rate, parent_rate);
+        _get_pll_mnp(pll, &old_cfg);
+        cfg.p = old_cfg.p;
+
+        if (cfg.m != old_cfg.m || cfg.n != old_cfg.n) {
+                state = clk_pll_is_enabled(hw);
+                if (state)
+                        _clk_pll_disable(hw);
+
+                _update_pll_mnp(pll, &cfg);
+
+                if (state) {
+                        _clk_pll_enable(hw);
+                        ret = clk_pll_wait_for_lock(pll);
+                }
+        }
+
+        if (pll->lock)
+                spin_unlock_irqrestore(pll->lock, flags);
+
+        return ret;
+}
+
+static unsigned long clk_pllre_recalc_rate(struct clk_hw *hw,
+                                         unsigned long parent_rate)
+{
+        struct tegra_clk_pll_freq_table cfg;
+        struct tegra_clk_pll *pll = to_clk_pll(hw);
+        u64 rate = parent_rate;
+
+        _get_pll_mnp(pll, &cfg);
+
+        rate *= cfg.n;
+        do_div(rate, cfg.m);
+
+        return rate;
+}
+
+static long clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate,
+                                 unsigned long *prate)
+{
+        struct tegra_clk_pll *pll = to_clk_pll(hw);
+
+        return _pllre_calc_rate(pll, NULL, rate, *prate);
+}
+
+static int clk_plle_tegra114_enable(struct clk_hw *hw)
+{
+        struct tegra_clk_pll *pll = to_clk_pll(hw);
+        struct tegra_clk_pll_freq_table sel;
+        u32 val;
+        int ret;
+        unsigned long flags = 0;
+        unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));
+
+        if (_get_table_rate(hw, &sel, pll->fixed_rate, input_rate))
+                return -EINVAL;
+
+        if (pll->lock)
+                spin_lock_irqsave(pll->lock, flags);
+
+        val = pll_readl_base(pll);
+        val &= ~BIT(29); /* Disable lock override */
+        pll_writel_base(val, pll);
+
+        val = pll_readl(pll->params->aux_reg, pll);
+        val |= PLLE_AUX_ENABLE_SWCTL;
+        val &= ~PLLE_AUX_SEQ_ENABLE;
+        pll_writel(val, pll->params->aux_reg, pll);
+        udelay(1);
+
+        val = pll_readl_misc(pll);
+        val |= PLLE_MISC_LOCK_ENABLE;
+        val |= PLLE_MISC_IDDQ_SW_CTRL;
+        val &= ~PLLE_MISC_IDDQ_SW_VALUE;
+        val |= PLLE_MISC_PLLE_PTS;
+        val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK;
+        pll_writel_misc(val, pll);
+        udelay(5);
+
+        val = pll_readl(PLLE_SS_CTRL, pll);
+        val |= PLLE_SS_DISABLE;
+        pll_writel(val, PLLE_SS_CTRL, pll);
+
+        val = pll_readl_base(pll);
+        val &= ~(divm_mask(pll) | divn_mask(pll) | divp_mask(pll));
+        val &= ~(PLLE_BASE_DIVCML_WIDTH << PLLE_BASE_DIVCML_SHIFT);
+        val |= sel.m << pll->divm_shift;
+        val |= sel.n << pll->divn_shift;
+        val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
+        pll_writel_base(val, pll);
+        udelay(1);
+
+        _clk_pll_enable(hw);
+        ret = clk_pll_wait_for_lock(pll);
+
+        if (ret < 0)
+                goto out;
+
+        /* TODO: enable hw control of xusb brick pll */
+
+out:
+        if (pll->lock)
+                spin_unlock_irqrestore(pll->lock, flags);
+
+        return ret;
+}
+
+static void clk_plle_tegra114_disable(struct clk_hw *hw)
+{
+        struct tegra_clk_pll *pll = to_clk_pll(hw);
+        unsigned long flags = 0;
+        u32 val;
+
+        if (pll->lock)
+                spin_lock_irqsave(pll->lock, flags);
+
+        _clk_pll_disable(hw);
+
+        val = pll_readl_misc(pll);
+        val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
+        pll_writel_misc(val, pll);
+        udelay(1);
+
+        if (pll->lock)
+                spin_unlock_irqrestore(pll->lock, flags);
+}
+#endif
+
+static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base,
+                void __iomem *pmc, unsigned long fixed_rate,
+                struct tegra_clk_pll_params *pll_params, u32 pll_flags,
+                struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock)
 {
         struct tegra_clk_pll *pll;
-        struct clk *clk;
-        struct clk_init_data init;
 
         pll = kzalloc(sizeof(*pll), GFP_KERNEL);
         if (!pll)
                 return ERR_PTR(-ENOMEM);
 
-        init.name = name;
-        init.ops = ops;
-        init.flags = flags;
-        init.parent_names = (parent_name ? &parent_name : NULL);
-        init.num_parents = (parent_name ? 1 : 0);
-
         pll->clk_base = clk_base;
         pll->pmc = pmc;
 
@@ -615,34 +1247,336 @@ static struct clk *_tegra_clk_register_pll(const char *name,
         pll->divm_shift = PLL_BASE_DIVM_SHIFT;
         pll->divm_width = PLL_BASE_DIVM_WIDTH;
 
+        return pll;
+}
+
+static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll,
+                const char *name, const char *parent_name, unsigned long flags,
+                const struct clk_ops *ops)
+{
+        struct clk_init_data init;
+
+        init.name = name;
+        init.ops = ops;
+        init.flags = flags;
+        init.parent_names = (parent_name ? &parent_name : NULL);
+        init.num_parents = (parent_name ? 1 : 0);
+
         /* Data in .init is copied by clk_register(), so stack variable OK */
         pll->hw.init = &init;
 
-        clk = clk_register(NULL, &pll->hw);
-        if (IS_ERR(clk))
-                kfree(pll);
-
-        return clk;
+        return clk_register(NULL, &pll->hw);
 }
 
 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
                 void __iomem *clk_base, void __iomem *pmc,
                 unsigned long flags, unsigned long fixed_rate,
-                struct tegra_clk_pll_params *pll_params, u8 pll_flags,
+                struct tegra_clk_pll_params *pll_params, u32 pll_flags,
                 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock)
 {
-        return _tegra_clk_register_pll(name, parent_name, clk_base, pmc,
-                        flags, fixed_rate, pll_params, pll_flags, freq_table,
-                        lock, &tegra_clk_pll_ops);
+        struct tegra_clk_pll *pll;
+        struct clk *clk;
+
+        pll_flags |= TEGRA_PLL_BYPASS;
+        pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
+        pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
+                              freq_table, lock);
+        if (IS_ERR(pll))
+                return ERR_CAST(pll);
+
+        clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
+                                      &tegra_clk_pll_ops);
+        if (IS_ERR(clk))
+                kfree(pll);
+
+        return clk;
 }
 
 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
                 void __iomem *clk_base, void __iomem *pmc,
                 unsigned long flags, unsigned long fixed_rate,
-                struct tegra_clk_pll_params *pll_params, u8 pll_flags,
+                struct tegra_clk_pll_params *pll_params, u32 pll_flags,
                 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock)
 {
-        return _tegra_clk_register_pll(name, parent_name, clk_base, pmc,
-                        flags, fixed_rate, pll_params, pll_flags, freq_table,
-                        lock, &tegra_clk_plle_ops);
+        struct tegra_clk_pll *pll;
+        struct clk *clk;
+
+        pll_flags |= TEGRA_PLL_LOCK_MISC | TEGRA_PLL_BYPASS;
+        pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
+        pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
+                              freq_table, lock);
+        if (IS_ERR(pll))
+                return ERR_CAST(pll);
+
+        clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
+                                      &tegra_clk_plle_ops);
+        if (IS_ERR(clk))
+                kfree(pll);
+
+        return clk;
+}
+
+#ifdef CONFIG_ARCH_TEGRA_114_SOC
+const struct clk_ops tegra_clk_pllxc_ops = {
+        .is_enabled = clk_pll_is_enabled,
+        .enable = clk_pll_iddq_enable,
+        .disable = clk_pll_iddq_disable,
+        .recalc_rate = clk_pll_recalc_rate,
+        .round_rate = clk_pll_ramp_round_rate,
+        .set_rate = clk_pllxc_set_rate,
+};
+
+const struct clk_ops tegra_clk_pllm_ops = {
+        .is_enabled = clk_pll_is_enabled,
+        .enable = clk_pll_iddq_enable,
+        .disable = clk_pll_iddq_disable,
+        .recalc_rate = clk_pll_recalc_rate,
+        .round_rate = clk_pll_ramp_round_rate,
+        .set_rate = clk_pllm_set_rate,
+};
+
+const struct clk_ops tegra_clk_pllc_ops = {
+        .is_enabled = clk_pll_is_enabled,
+        .enable = clk_pllc_enable,
+        .disable = clk_pllc_disable,
+        .recalc_rate = clk_pll_recalc_rate,
+        .round_rate = clk_pll_ramp_round_rate,
+        .set_rate = clk_pllc_set_rate,
+};
+
+const struct clk_ops tegra_clk_pllre_ops = {
+        .is_enabled = clk_pll_is_enabled,
+        .enable = clk_pll_iddq_enable,
+        .disable = clk_pll_iddq_disable,
+        .recalc_rate = clk_pllre_recalc_rate,
+        .round_rate = clk_pllre_round_rate,
+        .set_rate = clk_pllre_set_rate,
+};
+
+const struct clk_ops tegra_clk_plle_tegra114_ops = {
+        .is_enabled =  clk_pll_is_enabled,
+        .enable = clk_plle_tegra114_enable,
+        .disable = clk_plle_tegra114_disable,
+        .recalc_rate = clk_pll_recalc_rate,
+};
+
+
+struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
+                          void __iomem *clk_base, void __iomem *pmc,
+                          unsigned long flags, unsigned long fixed_rate,
+                          struct tegra_clk_pll_params *pll_params,
+                          u32 pll_flags,
+                          struct tegra_clk_pll_freq_table *freq_table,
+                          spinlock_t *lock)
+{
+        struct tegra_clk_pll *pll;
+        struct clk *clk;
+
+        if (!pll_params->pdiv_tohw)
+                return ERR_PTR(-EINVAL);
+
+        pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
+        pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
+                              freq_table, lock);
+        if (IS_ERR(pll))
+                return ERR_CAST(pll);
+
+        clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
+                                      &tegra_clk_pllxc_ops);
+        if (IS_ERR(clk))
+                kfree(pll);
+
+        return clk;
+}
+
+struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
+                          void __iomem *clk_base, void __iomem *pmc,
+                          unsigned long flags, unsigned long fixed_rate,
+                          struct tegra_clk_pll_params *pll_params,
+                          u32 pll_flags,
+                          struct tegra_clk_pll_freq_table *freq_table,
+                          spinlock_t *lock, unsigned long parent_rate)
+{
+        u32 val;
+        struct tegra_clk_pll *pll;
+        struct clk *clk;
+
+        pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
+        pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
+                              freq_table, lock);
+        if (IS_ERR(pll))
+                return ERR_CAST(pll);
+
+        /* program minimum rate by default */
+
+        val = pll_readl_base(pll);
+        if (val & PLL_BASE_ENABLE)
+                WARN_ON(val & pll_params->iddq_bit_idx);
+        else {
+                int m;
+
+                m = _pll_fixed_mdiv(pll_params, parent_rate);
+                val = m << PLL_BASE_DIVM_SHIFT;
+                val |= (pll_params->vco_min / parent_rate)
+                                << PLL_BASE_DIVN_SHIFT;
+                pll_writel_base(val, pll);
+        }
+
+        /* disable lock override */
+
+        val = pll_readl_misc(pll);
+        val &= ~BIT(29);
+        pll_writel_misc(val, pll);
+
+        pll_flags |= TEGRA_PLL_LOCK_MISC;
+        clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
+                                      &tegra_clk_pllre_ops);
+        if (IS_ERR(clk))
+                kfree(pll);
+
+        return clk;
+}
+
+struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
+                          void __iomem *clk_base, void __iomem *pmc,
+                          unsigned long flags, unsigned long fixed_rate,
+                          struct tegra_clk_pll_params *pll_params,
+                          u32 pll_flags,
+                          struct tegra_clk_pll_freq_table *freq_table,
+                          spinlock_t *lock)
+{
+        struct tegra_clk_pll *pll;
+        struct clk *clk;
+
+        if (!pll_params->pdiv_tohw)
+                return ERR_PTR(-EINVAL);
+
+        pll_flags |= TEGRA_PLL_BYPASS;
+        pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
+        pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
+                              freq_table, lock);
+        if (IS_ERR(pll))
+                return ERR_CAST(pll);
+
+        clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
+                                      &tegra_clk_pllm_ops);
+        if (IS_ERR(clk))
+                kfree(pll);
+
+        return clk;
+}
+
+struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
+                          void __iomem *clk_base, void __iomem *pmc,
+                          unsigned long flags, unsigned long fixed_rate,
+                          struct tegra_clk_pll_params *pll_params,
+                          u32 pll_flags,
+                          struct tegra_clk_pll_freq_table *freq_table,
+                          spinlock_t *lock)
+{
+        struct clk *parent, *clk;
+        struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
+        struct tegra_clk_pll *pll;
+        struct tegra_clk_pll_freq_table cfg;
+        unsigned long parent_rate;
+
+        if (!p_tohw)
+                return ERR_PTR(-EINVAL);
+
+        parent = __clk_lookup(parent_name);
+        if (IS_ERR(parent)) {
+                WARN(1, "parent clk %s of %s must be registered first\n",
+                        name, parent_name);
+                return ERR_PTR(-EINVAL);
+        }
+
+        pll_flags |= TEGRA_PLL_BYPASS;
+        pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
+                              freq_table, lock);
+        if (IS_ERR(pll))
+                return ERR_CAST(pll);
+
+        parent_rate = __clk_get_rate(parent);
+
+        /*
+         * Most of PLLC register fields are shadowed, and can not be read
+         * directly from PLL h/w. Hence, actual PLLC boot state is unknown.
+         * Initialize PLL to default state: disabled, reset; shadow registers
+         * loaded with default parameters; dividers are preset for half of
+         * minimum VCO rate (the latter assured that shadowed divider settings
+         * are within supported range).
+         */
+
+        cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
+        cfg.n = cfg.m * pll_params->vco_min / parent_rate;
+
+        while (p_tohw->pdiv) {
+                if (p_tohw->pdiv == 2) {
+                        cfg.p = p_tohw->hw_val;
+                        break;
+                }
+                p_tohw++;
+        }
+
+        if (!p_tohw->pdiv) {
+                WARN_ON(1);
+                return ERR_PTR(-EINVAL);
+        }
+
+        pll_writel_base(0, pll);
+        _update_pll_mnp(pll, &cfg);
+
+        pll_writel_misc(PLLCX_MISC_DEFAULT, pll);
+        pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll);
+        pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll);
+        pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll);
+
+        _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
+
+        clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
+                                      &tegra_clk_pllc_ops);
+        if (IS_ERR(clk))
+                kfree(pll);
+
+        return clk;
+}
+
+struct clk *tegra_clk_register_plle_tegra114(const char *name,
+                                const char *parent_name,
+                                void __iomem *clk_base, unsigned long flags,
+                                unsigned long fixed_rate,
+                                struct tegra_clk_pll_params *pll_params,
+                                struct tegra_clk_pll_freq_table *freq_table,
+                                spinlock_t *lock)
+{
+        struct tegra_clk_pll *pll;
+        struct clk *clk;
+        u32 val, val_aux;
+
+        pll = _tegra_init_pll(clk_base, NULL, fixed_rate, pll_params,
+                              TEGRA_PLL_HAS_LOCK_ENABLE, freq_table, lock);
+        if (IS_ERR(pll))
+                return ERR_CAST(pll);
+
+        /* ensure parent is set to pll_re_vco */
+
+        val = pll_readl_base(pll);
+        val_aux = pll_readl(pll_params->aux_reg, pll);
+
+        if (val & PLL_BASE_ENABLE) {
+                if (!(val_aux & PLLE_AUX_PLLRE_SEL))
+                        WARN(1, "pll_e enabled with unsupported parent %s\n",
+                          (val & PLLE_AUX_PLLP_SEL) ? "pllp_out0" : "pll_ref");
+        } else {
+                val_aux |= PLLE_AUX_PLLRE_SEL;
+                pll_writel(val, pll_params->aux_reg, pll);
+        }
+
+        clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
+                                      &tegra_clk_plle_tegra114_ops);
+        if (IS_ERR(clk))
+                kfree(pll);
+
+        return clk;
 }
+#endif
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
new file mode 100644
index 000000000000..d78e16ee161c
--- /dev/null
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -0,0 +1,2085 @@
+/*
+ * Copyright (c) 2012, 2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/delay.h>
+#include <linux/clk/tegra.h>
+
+#include "clk.h"
+
+#define RST_DEVICES_L                   0x004
+#define RST_DEVICES_H                   0x008
+#define RST_DEVICES_U                   0x00C
+#define RST_DEVICES_V                   0x358
+#define RST_DEVICES_W                   0x35C
+#define RST_DEVICES_X                   0x28C
+#define RST_DEVICES_SET_L               0x300
+#define RST_DEVICES_CLR_L               0x304
+#define RST_DEVICES_SET_H               0x308
+#define RST_DEVICES_CLR_H               0x30c
+#define RST_DEVICES_SET_U               0x310
+#define RST_DEVICES_CLR_U               0x314
+#define RST_DEVICES_SET_V               0x430
+#define RST_DEVICES_CLR_V               0x434
+#define RST_DEVICES_SET_W               0x438
+#define RST_DEVICES_CLR_W               0x43c
+#define RST_DEVICES_NUM                 5
+
+#define CLK_OUT_ENB_L                   0x010
+#define CLK_OUT_ENB_H                   0x014
+#define CLK_OUT_ENB_U                   0x018
+#define CLK_OUT_ENB_V                   0x360
+#define CLK_OUT_ENB_W                   0x364
+#define CLK_OUT_ENB_X                   0x280
+#define CLK_OUT_ENB_SET_L               0x320
+#define CLK_OUT_ENB_CLR_L               0x324
+#define CLK_OUT_ENB_SET_H               0x328
+#define CLK_OUT_ENB_CLR_H               0x32c
+#define CLK_OUT_ENB_SET_U               0x330
+#define CLK_OUT_ENB_CLR_U               0x334
+#define CLK_OUT_ENB_SET_V               0x440
+#define CLK_OUT_ENB_CLR_V               0x444
+#define CLK_OUT_ENB_SET_W               0x448
+#define CLK_OUT_ENB_CLR_W               0x44c
+#define CLK_OUT_ENB_SET_X               0x284
+#define CLK_OUT_ENB_CLR_X               0x288
+#define CLK_OUT_ENB_NUM                 6
+
+#define PLLC_BASE 0x80
+#define PLLC_MISC2 0x88
+#define PLLC_MISC 0x8c
+#define PLLC2_BASE 0x4e8
+#define PLLC2_MISC 0x4ec
+#define PLLC3_BASE 0x4fc
+#define PLLC3_MISC 0x500
+#define PLLM_BASE 0x90
+#define PLLM_MISC 0x9c
+#define PLLP_BASE 0xa0
+#define PLLP_MISC 0xac
+#define PLLX_BASE 0xe0
+#define PLLX_MISC 0xe4
+#define PLLX_MISC2 0x514
+#define PLLX_MISC3 0x518
+#define PLLD_BASE 0xd0
+#define PLLD_MISC 0xdc
+#define PLLD2_BASE 0x4b8
+#define PLLD2_MISC 0x4bc
+#define PLLE_BASE 0xe8
+#define PLLE_MISC 0xec
+#define PLLA_BASE 0xb0
+#define PLLA_MISC 0xbc
+#define PLLU_BASE 0xc0
+#define PLLU_MISC 0xcc
+#define PLLRE_BASE 0x4c4
+#define PLLRE_MISC 0x4c8
+
+#define PLL_MISC_LOCK_ENABLE 18
+#define PLLC_MISC_LOCK_ENABLE 24
+#define PLLDU_MISC_LOCK_ENABLE 22
+#define PLLE_MISC_LOCK_ENABLE 9
+#define PLLRE_MISC_LOCK_ENABLE 30
+
+#define PLLC_IDDQ_BIT 26
+#define PLLX_IDDQ_BIT 3
+#define PLLRE_IDDQ_BIT 16
+
+#define PLL_BASE_LOCK BIT(27)
+#define PLLE_MISC_LOCK BIT(11)
+#define PLLRE_MISC_LOCK BIT(24)
+#define PLLCX_BASE_LOCK (BIT(26)|BIT(27))
+
+#define PLLE_AUX 0x48c
+#define PLLC_OUT 0x84
+#define PLLM_OUT 0x94
+#define PLLP_OUTA 0xa4
+#define PLLP_OUTB 0xa8
+#define PLLA_OUT 0xb4
+
+#define AUDIO_SYNC_CLK_I2S0 0x4a0
+#define AUDIO_SYNC_CLK_I2S1 0x4a4
+#define AUDIO_SYNC_CLK_I2S2 0x4a8
+#define AUDIO_SYNC_CLK_I2S3 0x4ac
+#define AUDIO_SYNC_CLK_I2S4 0x4b0
+#define AUDIO_SYNC_CLK_SPDIF 0x4b4
+
+#define AUDIO_SYNC_DOUBLER 0x49c
+
+#define PMC_CLK_OUT_CNTRL 0x1a8
+#define PMC_DPD_PADS_ORIDE 0x1c
+#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20
+#define PMC_CTRL 0
+#define PMC_CTRL_BLINK_ENB 7
+
+#define OSC_CTRL                        0x50
+#define OSC_CTRL_OSC_FREQ_SHIFT         28
+#define OSC_CTRL_PLL_REF_DIV_SHIFT      26
+
+#define PLLXC_SW_MAX_P                  6
+
+#define CCLKG_BURST_POLICY 0x368
+#define CCLKLP_BURST_POLICY 0x370
+#define SCLK_BURST_POLICY 0x028
+#define SYSTEM_CLK_RATE 0x030
+
+#define UTMIP_PLL_CFG2 0x488
+#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6)
+#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
+#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
+#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
+#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
+
+#define UTMIP_PLL_CFG1 0x484
+#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6)
+#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
+#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)
+#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
+#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)
+#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
+#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
+
+#define UTMIPLL_HW_PWRDN_CFG0                   0x52c
+#define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE   BIT(25)
+#define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE        BIT(24)
+#define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET       BIT(6)
+#define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE     BIT(5)
+#define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL      BIT(4)
+#define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL  BIT(2)
+#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE     BIT(1)
+#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL        BIT(0)
+
+#define CLK_SOURCE_I2S0 0x1d8
+#define CLK_SOURCE_I2S1 0x100
+#define CLK_SOURCE_I2S2 0x104
+#define CLK_SOURCE_NDFLASH 0x160
+#define CLK_SOURCE_I2S3 0x3bc
+#define CLK_SOURCE_I2S4 0x3c0
+#define CLK_SOURCE_SPDIF_OUT 0x108
+#define CLK_SOURCE_SPDIF_IN 0x10c
+#define CLK_SOURCE_PWM 0x110
+#define CLK_SOURCE_ADX 0x638
+#define CLK_SOURCE_AMX 0x63c
+#define CLK_SOURCE_HDA 0x428
+#define CLK_SOURCE_HDA2CODEC_2X 0x3e4
+#define CLK_SOURCE_SBC1 0x134
+#define CLK_SOURCE_SBC2 0x118
+#define CLK_SOURCE_SBC3 0x11c
+#define CLK_SOURCE_SBC4 0x1b4
+#define CLK_SOURCE_SBC5 0x3c8
+#define CLK_SOURCE_SBC6 0x3cc
+#define CLK_SOURCE_SATA_OOB 0x420
+#define CLK_SOURCE_SATA 0x424
+#define CLK_SOURCE_NDSPEED 0x3f8
+#define CLK_SOURCE_VFIR 0x168
+#define CLK_SOURCE_SDMMC1 0x150
+#define CLK_SOURCE_SDMMC2 0x154
+#define CLK_SOURCE_SDMMC3 0x1bc
+#define CLK_SOURCE_SDMMC4 0x164
+#define CLK_SOURCE_VDE 0x1c8
+#define CLK_SOURCE_CSITE 0x1d4
+#define CLK_SOURCE_LA 0x1f8
+#define CLK_SOURCE_TRACE 0x634
+#define CLK_SOURCE_OWR 0x1cc
+#define CLK_SOURCE_NOR 0x1d0
+#define CLK_SOURCE_MIPI 0x174
+#define CLK_SOURCE_I2C1 0x124
+#define CLK_SOURCE_I2C2 0x198
+#define CLK_SOURCE_I2C3 0x1b8
+#define CLK_SOURCE_I2C4 0x3c4
+#define CLK_SOURCE_I2C5 0x128
+#define CLK_SOURCE_UARTA 0x178
+#define CLK_SOURCE_UARTB 0x17c
+#define CLK_SOURCE_UARTC 0x1a0
+#define CLK_SOURCE_UARTD 0x1c0
+#define CLK_SOURCE_UARTE 0x1c4
+#define CLK_SOURCE_UARTA_DBG 0x178
+#define CLK_SOURCE_UARTB_DBG 0x17c
+#define CLK_SOURCE_UARTC_DBG 0x1a0
+#define CLK_SOURCE_UARTD_DBG 0x1c0
+#define CLK_SOURCE_UARTE_DBG 0x1c4
+#define CLK_SOURCE_3D 0x158
+#define CLK_SOURCE_2D 0x15c
+#define CLK_SOURCE_VI_SENSOR 0x1a8
+#define CLK_SOURCE_VI 0x148
+#define CLK_SOURCE_EPP 0x16c
+#define CLK_SOURCE_MSENC 0x1f0
+#define CLK_SOURCE_TSEC 0x1f4
+#define CLK_SOURCE_HOST1X 0x180
+#define CLK_SOURCE_HDMI 0x18c
+#define CLK_SOURCE_DISP1 0x138
+#define CLK_SOURCE_DISP2 0x13c
+#define CLK_SOURCE_CILAB 0x614
+#define CLK_SOURCE_CILCD 0x618
+#define CLK_SOURCE_CILE 0x61c
+#define CLK_SOURCE_DSIALP 0x620
+#define CLK_SOURCE_DSIBLP 0x624
+#define CLK_SOURCE_TSENSOR 0x3b8
+#define CLK_SOURCE_D_AUDIO 0x3d0
+#define CLK_SOURCE_DAM0 0x3d8
+#define CLK_SOURCE_DAM1 0x3dc
+#define CLK_SOURCE_DAM2 0x3e0
+#define CLK_SOURCE_ACTMON 0x3e8
+#define CLK_SOURCE_EXTERN1 0x3ec
+#define CLK_SOURCE_EXTERN2 0x3f0
+#define CLK_SOURCE_EXTERN3 0x3f4
+#define CLK_SOURCE_I2CSLOW 0x3fc
+#define CLK_SOURCE_SE 0x42c
+#define CLK_SOURCE_MSELECT 0x3b4
+#define CLK_SOURCE_SOC_THERM 0x644
+#define CLK_SOURCE_XUSB_HOST_SRC 0x600
+#define CLK_SOURCE_XUSB_FALCON_SRC 0x604
+#define CLK_SOURCE_XUSB_FS_SRC 0x608
+#define CLK_SOURCE_XUSB_SS_SRC 0x610
+#define CLK_SOURCE_XUSB_DEV_SRC 0x60c
+#define CLK_SOURCE_EMC 0x19c
+
+static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32];
+
+static void __iomem *clk_base;
+static void __iomem *pmc_base;
+
+static DEFINE_SPINLOCK(pll_d_lock);
+static DEFINE_SPINLOCK(pll_d2_lock);
+static DEFINE_SPINLOCK(pll_u_lock);
+static DEFINE_SPINLOCK(pll_div_lock);
+static DEFINE_SPINLOCK(pll_re_lock);
+static DEFINE_SPINLOCK(clk_doubler_lock);
+static DEFINE_SPINLOCK(clk_out_lock);
+static DEFINE_SPINLOCK(sysrate_lock);
+
+static struct pdiv_map pllxc_p[] = {
+        { .pdiv = 1, .hw_val = 0 },
+        { .pdiv = 2, .hw_val = 1 },
+        { .pdiv = 3, .hw_val = 2 },
+        { .pdiv = 4, .hw_val = 3 },
+        { .pdiv = 5, .hw_val = 4 },
+        { .pdiv = 6, .hw_val = 5 },
+        { .pdiv = 8, .hw_val = 6 },
+        { .pdiv = 10, .hw_val = 7 },
+        { .pdiv = 12, .hw_val = 8 },
+        { .pdiv = 16, .hw_val = 9 },
+        { .pdiv = 12, .hw_val = 10 },
+        { .pdiv = 16, .hw_val = 11 },
+        { .pdiv = 20, .hw_val = 12 },
+        { .pdiv = 24, .hw_val = 13 },
+        { .pdiv = 32, .hw_val = 14 },
+        { .pdiv = 0, .hw_val = 0 },
+};
+
+static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
+        { 12000000, 624000000, 104, 0, 2},
+        { 12000000, 600000000, 100, 0, 2},
+        { 13000000, 600000000,  92, 0, 2},      /* actual: 598.0 MHz */
+        { 16800000, 600000000,  71, 0, 2},      /* actual: 596.4 MHz */
+        { 19200000, 600000000,  62, 0, 2},      /* actual: 595.2 MHz */
+        { 26000000, 600000000,  92, 1, 2},      /* actual: 598.0 MHz */
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+static struct tegra_clk_pll_params pll_c_params = {
+        .input_min = 12000000,
+        .input_max = 800000000,
+        .cf_min = 12000000,
+        .cf_max = 19200000,     /* s/w policy, h/w capability 50 MHz */
+        .vco_min = 600000000,
+        .vco_max = 1400000000,
+        .base_reg = PLLC_BASE,
+        .misc_reg = PLLC_MISC,
+        .lock_mask = PLL_BASE_LOCK,
+        .lock_enable_bit_idx = PLLC_MISC_LOCK_ENABLE,
+        .lock_delay = 300,
+        .iddq_reg = PLLC_MISC,
+        .iddq_bit_idx = PLLC_IDDQ_BIT,
+        .max_p = PLLXC_SW_MAX_P,
+        .dyn_ramp_reg = PLLC_MISC2,
+        .stepa_shift = 17,
+        .stepb_shift = 9,
+        .pdiv_tohw = pllxc_p,
+};
+
+static struct pdiv_map pllc_p[] = {
+        { .pdiv = 1, .hw_val = 0 },
+        { .pdiv = 2, .hw_val = 1 },
+        { .pdiv = 4, .hw_val = 3 },
+        { .pdiv = 8, .hw_val = 5 },
+        { .pdiv = 16, .hw_val = 7 },
+        { .pdiv = 0, .hw_val = 0 },
+};
+
+static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {
+        {12000000, 600000000, 100, 0, 2},
+        {13000000, 600000000, 92, 0, 2},        /* actual: 598.0 MHz */
+        {16800000, 600000000, 71, 0, 2},        /* actual: 596.4 MHz */
+        {19200000, 600000000, 62, 0, 2},        /* actual: 595.2 MHz */
+        {26000000, 600000000, 92, 1, 2},        /* actual: 598.0 MHz */
+        {0, 0, 0, 0, 0, 0},
+};
+
+static struct tegra_clk_pll_params pll_c2_params = {
+        .input_min = 12000000,
+        .input_max = 48000000,
+        .cf_min = 12000000,
+        .cf_max = 19200000,
+        .vco_min = 600000000,
+        .vco_max = 1200000000,
+        .base_reg = PLLC2_BASE,
+        .misc_reg = PLLC2_MISC,
+        .lock_mask = PLL_BASE_LOCK,
+        .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
+        .lock_delay = 300,
+        .pdiv_tohw = pllc_p,
+        .ext_misc_reg[0] = 0x4f0,
+        .ext_misc_reg[1] = 0x4f4,
+        .ext_misc_reg[2] = 0x4f8,
+};
+
+static struct tegra_clk_pll_params pll_c3_params = {
+        .input_min = 12000000,
+        .input_max = 48000000,
+        .cf_min = 12000000,
+        .cf_max = 19200000,
+        .vco_min = 600000000,
+        .vco_max = 1200000000,
+        .base_reg = PLLC3_BASE,
+        .misc_reg = PLLC3_MISC,
+        .lock_mask = PLL_BASE_LOCK,
+        .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
+        .lock_delay = 300,
+        .pdiv_tohw = pllc_p,
+        .ext_misc_reg[0] = 0x504,
+        .ext_misc_reg[1] = 0x508,
+        .ext_misc_reg[2] = 0x50c,
+};
+
+static struct pdiv_map pllm_p[] = {
+        { .pdiv = 1, .hw_val = 0 },
+        { .pdiv = 2, .hw_val = 1 },
+        { .pdiv = 0, .hw_val = 0 },
+};
+
+static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
+        {12000000, 800000000, 66, 0, 1},        /* actual: 792.0 MHz */
+        {13000000, 800000000, 61, 0, 1},        /* actual: 793.0 MHz */
+        {16800000, 800000000, 47, 0, 1},        /* actual: 789.6 MHz */
+        {19200000, 800000000, 41, 0, 1},        /* actual: 787.2 MHz */
+        {26000000, 800000000, 61, 1, 1},        /* actual: 793.0 MHz */
+        {0, 0, 0, 0, 0, 0},
+};
+
+static struct tegra_clk_pll_params pll_m_params = {
+        .input_min = 12000000,
+        .input_max = 500000000,
+        .cf_min = 12000000,
+        .cf_max = 19200000,     /* s/w policy, h/w capability 50 MHz */
+        .vco_min = 400000000,
+        .vco_max = 1066000000,
+        .base_reg = PLLM_BASE,
+        .misc_reg = PLLM_MISC,
+        .lock_mask = PLL_BASE_LOCK,
+        .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
+        .lock_delay = 300,
+        .max_p = 2,
+        .pdiv_tohw = pllm_p,
+};
+
+static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
+        {12000000, 216000000, 432, 12, 1, 8},
+        {13000000, 216000000, 432, 13, 1, 8},
+        {16800000, 216000000, 360, 14, 1, 8},
+        {19200000, 216000000, 360, 16, 1, 8},
+        {26000000, 216000000, 432, 26, 1, 8},
+        {0, 0, 0, 0, 0, 0},
+};
+
+static struct tegra_clk_pll_params pll_p_params = {
+        .input_min = 2000000,
+        .input_max = 31000000,
+        .cf_min = 1000000,
+        .cf_max = 6000000,
+        .vco_min = 200000000,
+        .vco_max = 700000000,
+        .base_reg = PLLP_BASE,
+        .misc_reg = PLLP_MISC,
+        .lock_mask = PLL_BASE_LOCK,
+        .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
+        .lock_delay = 300,
+};
+
+static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
+        {9600000, 282240000, 147, 5, 0, 4},
+        {9600000, 368640000, 192, 5, 0, 4},
+        {9600000, 240000000, 200, 8, 0, 8},
+
+        {28800000, 282240000, 245, 25, 0, 8},
+        {28800000, 368640000, 320, 25, 0, 8},
+        {28800000, 240000000, 200, 24, 0, 8},
+        {0, 0, 0, 0, 0, 0},
+};
+
+
+static struct tegra_clk_pll_params pll_a_params = {
+        .input_min = 2000000,
+        .input_max = 31000000,
+        .cf_min = 1000000,
+        .cf_max = 6000000,
+        .vco_min = 200000000,
+        .vco_max = 700000000,
+        .base_reg = PLLA_BASE,
+        .misc_reg = PLLA_MISC,
+        .lock_mask = PLL_BASE_LOCK,
+        .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
+        .lock_delay = 300,
+};
+
+static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
+        {12000000, 216000000, 864, 12, 2, 12},
+        {13000000, 216000000, 864, 13, 2, 12},
+        {16800000, 216000000, 720, 14, 2, 12},
+        {19200000, 216000000, 720, 16, 2, 12},
+        {26000000, 216000000, 864, 26, 2, 12},
+
+        {12000000, 594000000, 594, 12, 0, 12},
+        {13000000, 594000000, 594, 13, 0, 12},
+        {16800000, 594000000, 495, 14, 0, 12},
+        {19200000, 594000000, 495, 16, 0, 12},
+        {26000000, 594000000, 594, 26, 0, 12},
+
+        {12000000, 1000000000, 1000, 12, 0, 12},
+        {13000000, 1000000000, 1000, 13, 0, 12},
+        {19200000, 1000000000, 625, 12, 0, 12},
+        {26000000, 1000000000, 1000, 26, 0, 12},
+
+        {0, 0, 0, 0, 0, 0},
+};
+
+static struct tegra_clk_pll_params pll_d_params = {
+        .input_min = 2000000,
+        .input_max = 40000000,
+        .cf_min = 1000000,
+        .cf_max = 6000000,
+        .vco_min = 500000000,
+        .vco_max = 1000000000,
+        .base_reg = PLLD_BASE,
+        .misc_reg = PLLD_MISC,
+        .lock_mask = PLL_BASE_LOCK,
+        .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
+        .lock_delay = 1000,
+};
+
+static struct tegra_clk_pll_params pll_d2_params = {
+        .input_min = 2000000,
+        .input_max = 40000000,
+        .cf_min = 1000000,
+        .cf_max = 6000000,
+        .vco_min = 500000000,
+        .vco_max = 1000000000,
+        .base_reg = PLLD2_BASE,
+        .misc_reg = PLLD2_MISC,
+        .lock_mask = PLL_BASE_LOCK,
+        .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
+        .lock_delay = 1000,
+};
+
+static struct pdiv_map pllu_p[] = {
+        { .pdiv = 1, .hw_val = 1 },
+        { .pdiv = 2, .hw_val = 0 },
+        { .pdiv = 0, .hw_val = 0 },
+};
+
+static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
+        {12000000, 480000000, 960, 12, 0, 12},
+        {13000000, 480000000, 960, 13, 0, 12},
+        {16800000, 480000000, 400, 7, 0, 5},
+        {19200000, 480000000, 200, 4, 0, 3},
+        {26000000, 480000000, 960, 26, 0, 12},
+        {0, 0, 0, 0, 0, 0},
+};
+
+static struct tegra_clk_pll_params pll_u_params = {
+        .input_min = 2000000,
+        .input_max = 40000000,
+        .cf_min = 1000000,
+        .cf_max = 6000000,
+        .vco_min = 480000000,
+        .vco_max = 960000000,
+        .base_reg = PLLU_BASE,
+        .misc_reg = PLLU_MISC,
+        .lock_mask = PLL_BASE_LOCK,
+        .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
+        .lock_delay = 1000,
+        .pdiv_tohw = pllu_p,
+};
+
+static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
+        /* 1 GHz */
+        {12000000, 1000000000, 83, 0, 1},       /* actual: 996.0 MHz */
+        {13000000, 1000000000, 76, 0, 1},       /* actual: 988.0 MHz */
+        {16800000, 1000000000, 59, 0, 1},       /* actual: 991.2 MHz */
+        {19200000, 1000000000, 52, 0, 1},       /* actual: 998.4 MHz */
+        {26000000, 1000000000, 76, 1, 1},       /* actual: 988.0 MHz */
+
+        {0, 0, 0, 0, 0, 0},
+};
+
+static struct tegra_clk_pll_params pll_x_params = {
+        .input_min = 12000000,
+        .input_max = 800000000,
+        .cf_min = 12000000,
+        .cf_max = 19200000,     /* s/w policy, h/w capability 50 MHz */
+        .vco_min = 700000000,
+        .vco_max = 2400000000U,
+        .base_reg = PLLX_BASE,
+        .misc_reg = PLLX_MISC,
+        .lock_mask = PLL_BASE_LOCK,
+        .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
+        .lock_delay = 300,
+        .iddq_reg = PLLX_MISC3,
+        .iddq_bit_idx = PLLX_IDDQ_BIT,
+        .max_p = PLLXC_SW_MAX_P,
+        .dyn_ramp_reg = PLLX_MISC2,
+        .stepa_shift = 16,
+        .stepb_shift = 24,
+        .pdiv_tohw = pllxc_p,
+};
+
+static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
+        /* PLLE special case: use cpcon field to store cml divider value */
+        {336000000, 100000000, 100, 21, 16, 11},
+        {312000000, 100000000, 200, 26, 24, 13},
+        {0, 0, 0, 0, 0, 0},
+};
+
+static struct tegra_clk_pll_params pll_e_params = {
+        .input_min = 12000000,
+        .input_max = 1000000000,
+        .cf_min = 12000000,
+        .cf_max = 75000000,
+        .vco_min = 1600000000,
+        .vco_max = 2400000000U,
+        .base_reg = PLLE_BASE,
+        .misc_reg = PLLE_MISC,
+        .aux_reg = PLLE_AUX,
+        .lock_mask = PLLE_MISC_LOCK,
+        .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
+        .lock_delay = 300,
+};
+
+static struct tegra_clk_pll_params pll_re_vco_params = {
+        .input_min = 12000000,
+        .input_max = 1000000000,
+        .cf_min = 12000000,
+        .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
+        .vco_min = 300000000,
+        .vco_max = 600000000,
+        .base_reg = PLLRE_BASE,
+        .misc_reg = PLLRE_MISC,
+        .lock_mask = PLLRE_MISC_LOCK,
+        .lock_enable_bit_idx = PLLRE_MISC_LOCK_ENABLE,
+        .lock_delay = 300,
+        .iddq_reg = PLLRE_MISC,
+        .iddq_bit_idx = PLLRE_IDDQ_BIT,
+};
+
+/* Peripheral clock registers */
+
+static struct tegra_clk_periph_regs periph_l_regs = {
+        .enb_reg = CLK_OUT_ENB_L,
+        .enb_set_reg = CLK_OUT_ENB_SET_L,
+        .enb_clr_reg = CLK_OUT_ENB_CLR_L,
+        .rst_reg = RST_DEVICES_L,
+        .rst_set_reg = RST_DEVICES_SET_L,
+        .rst_clr_reg = RST_DEVICES_CLR_L,
+};
+
+static struct tegra_clk_periph_regs periph_h_regs = {
+        .enb_reg = CLK_OUT_ENB_H,
+        .enb_set_reg = CLK_OUT_ENB_SET_H,
+        .enb_clr_reg = CLK_OUT_ENB_CLR_H,
+        .rst_reg = RST_DEVICES_H,
+        .rst_set_reg = RST_DEVICES_SET_H,
+        .rst_clr_reg = RST_DEVICES_CLR_H,
+};
+
+static struct tegra_clk_periph_regs periph_u_regs = {
+        .enb_reg = CLK_OUT_ENB_U,
+        .enb_set_reg = CLK_OUT_ENB_SET_U,
+        .enb_clr_reg = CLK_OUT_ENB_CLR_U,
+        .rst_reg = RST_DEVICES_U,
+        .rst_set_reg = RST_DEVICES_SET_U,
+        .rst_clr_reg = RST_DEVICES_CLR_U,
+};
+
+static struct tegra_clk_periph_regs periph_v_regs = {
+        .enb_reg = CLK_OUT_ENB_V,
+        .enb_set_reg = CLK_OUT_ENB_SET_V,
+        .enb_clr_reg = CLK_OUT_ENB_CLR_V,
+        .rst_reg = RST_DEVICES_V,
+        .rst_set_reg = RST_DEVICES_SET_V,
+        .rst_clr_reg = RST_DEVICES_CLR_V,
+};
+
+static struct tegra_clk_periph_regs periph_w_regs = {
+        .enb_reg = CLK_OUT_ENB_W,
+        .enb_set_reg = CLK_OUT_ENB_SET_W,
+        .enb_clr_reg = CLK_OUT_ENB_CLR_W,
+        .rst_reg = RST_DEVICES_W,
+        .rst_set_reg = RST_DEVICES_SET_W,
+        .rst_clr_reg = RST_DEVICES_CLR_W,
+};
+
+/* possible OSC frequencies in Hz */
+static unsigned long tegra114_input_freq[] = {
+        [0] = 13000000,
+        [1] = 16800000,
+        [4] = 19200000,
+        [5] = 38400000,
+        [8] = 12000000,
+        [9] = 48000000,
+        [12] = 260000000,
+};
+
+#define MASK(x) (BIT(x) - 1)
+
+#define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \
+                            _clk_num, _regs, _gate_flags, _clk_id)      \
+        TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
+                        30, MASK(2), 0, 0, 8, 1, 0, _regs, _clk_num,    \
+                        periph_clk_enb_refcnt, _gate_flags, _clk_id,    \
+                        _parents##_idx, 0)
+
+#define TEGRA_INIT_DATA_MUX_FLAGS(_name, _con_id, _dev_id, _parents, _offset,\
+                            _clk_num, _regs, _gate_flags, _clk_id, flags)\
+        TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
+                        30, MASK(2), 0, 0, 8, 1, 0, _regs, _clk_num,    \
+                        periph_clk_enb_refcnt, _gate_flags, _clk_id,    \
+                        _parents##_idx, flags)
+
+#define TEGRA_INIT_DATA_MUX8(_name, _con_id, _dev_id, _parents, _offset, \
+                             _clk_num, _regs, _gate_flags, _clk_id)     \
+        TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
+                        29, MASK(3), 0, 0, 8, 1, 0, _regs, _clk_num,    \
+                        periph_clk_enb_refcnt, _gate_flags, _clk_id,    \
+                        _parents##_idx, 0)
+
+#define TEGRA_INIT_DATA_INT(_name, _con_id, _dev_id, _parents, _offset, \
+                            _clk_num, _regs, _gate_flags, _clk_id)      \
+        TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
+                        30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,\
+                        _clk_num, periph_clk_enb_refcnt, _gate_flags,   \
+                        _clk_id, _parents##_idx, 0)
+
+#define TEGRA_INIT_DATA_INT_FLAGS(_name, _con_id, _dev_id, _parents, _offset,\
+                            _clk_num, _regs, _gate_flags, _clk_id, flags)\
+        TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
+                        30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,\
+                        _clk_num, periph_clk_enb_refcnt, _gate_flags,   \
+                        _clk_id, _parents##_idx, flags)
+
+#define TEGRA_INIT_DATA_INT8(_name, _con_id, _dev_id, _parents, _offset,\
+                            _clk_num, _regs, _gate_flags, _clk_id)      \
+        TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
+                        29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,\
+                        _clk_num, periph_clk_enb_refcnt, _gate_flags,   \
+                        _clk_id, _parents##_idx, 0)
+
+#define TEGRA_INIT_DATA_UART(_name, _con_id, _dev_id, _parents, _offset,\
+                             _clk_num, _regs, _clk_id)                  \
+        TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
+                        30, MASK(2), 0, 0, 16, 1, TEGRA_DIVIDER_UART, _regs,\
+                        _clk_num, periph_clk_enb_refcnt, 0, _clk_id,    \
+                        _parents##_idx, 0)
+
+#define TEGRA_INIT_DATA_I2C(_name, _con_id, _dev_id, _parents, _offset,\
+                             _clk_num, _regs, _clk_id)                  \
+        TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
+                        30, MASK(2), 0, 0, 16, 0, 0, _regs, _clk_num,   \
+                        periph_clk_enb_refcnt, 0, _clk_id, _parents##_idx, 0)
+
+#define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \
+                              _mux_shift, _mux_mask, _clk_num, _regs,   \
+                              _gate_flags, _clk_id)                     \
+        TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
+                        _mux_shift, _mux_mask, 0, 0, 0, 0, 0, _regs,    \
+                        _clk_num, periph_clk_enb_refcnt, _gate_flags,   \
+                        _clk_id, _parents##_idx, 0)
+
+#define TEGRA_INIT_DATA_XUSB(_name, _con_id, _dev_id, _parents, _offset, \
+                             _clk_num, _regs, _gate_flags, _clk_id)      \
+        TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset, \
+                        29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs, \
+                        _clk_num, periph_clk_enb_refcnt, _gate_flags,    \
+                        _clk_id, _parents##_idx, 0)
+
+#define TEGRA_INIT_DATA_AUDIO(_name, _con_id, _dev_id, _offset,  _clk_num,\
+                                 _regs, _gate_flags, _clk_id)           \
+        TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, mux_d_audio_clk, \
+                        _offset, 16, 0xE01F, 0, 0, 8, 1, 0, _regs, _clk_num, \
+                        periph_clk_enb_refcnt, _gate_flags , _clk_id,   \
+                        mux_d_audio_clk_idx, 0)
+
+enum tegra114_clk {
+        rtc = 4, timer = 5, uarta = 6, sdmmc2 = 9, i2s1 = 11, i2c1 = 12,
+        ndflash = 13, sdmmc1 = 14, sdmmc4 = 15, pwm = 17, i2s2 = 18, epp = 19,
+        gr_2d = 21, usbd = 22, isp = 23, gr_3d = 24, disp2 = 26, disp1 = 27,
+        host1x = 28, vcp = 29, i2s0 = 30, apbdma = 34, kbc = 36, kfuse = 40,
+        sbc1 = 41, nor = 42, sbc2 = 44, sbc3 = 46, i2c5 = 47, dsia = 48,
+        mipi = 50, hdmi = 51, csi = 52, i2c2 = 54, uartc = 55, mipi_cal = 56,
+        emc, usb2, usb3, vde = 61, bsea = 62, bsev = 63, uartd = 65,
+        i2c3 = 67, sbc4 = 68, sdmmc3 = 69, owr = 71, csite = 73,
+        la = 76, trace = 77, soc_therm = 78, dtv = 79, ndspeed = 80,
+        i2cslow = 81, dsib = 82, tsec = 83, xusb_host = 89, msenc = 91,
+        csus = 92, mselect = 99, tsensor = 100, i2s3 = 101, i2s4 = 102,
+        i2c4 = 103, sbc5 = 104, sbc6 = 105, d_audio, apbif = 107, dam0, dam1,
+        dam2, hda2codec_2x = 111, audio0_2x = 113, audio1_2x, audio2_2x,
+        audio3_2x, audio4_2x, spdif_2x, actmon = 119, extern1 = 120,
+        extern2 = 121, extern3 = 122, hda = 125, se = 127, hda2hdmi = 128,
+        cilab = 144, cilcd = 145, cile = 146, dsialp = 147, dsiblp = 148,
+        dds = 150, dp2 = 152, amx = 153, adx = 154, xusb_ss = 156, uartb = 192,
+        vfir, spdif_in, spdif_out, vi, vi_sensor, fuse, fuse_burn, clk_32k,
+        clk_m, clk_m_div2, clk_m_div4, pll_ref, pll_c, pll_c_out1, pll_c2,
+        pll_c3, pll_m, pll_m_out1, pll_p, pll_p_out1, pll_p_out2, pll_p_out3,
+        pll_p_out4, pll_a, pll_a_out0, pll_d, pll_d_out0, pll_d2, pll_d2_out0,
+        pll_u, pll_u_480M, pll_u_60M, pll_u_48M, pll_u_12M, pll_x, pll_x_out0,
+        pll_re_vco, pll_re_out, pll_e_out0, spdif_in_sync, i2s0_sync,
+        i2s1_sync, i2s2_sync, i2s3_sync, i2s4_sync, vimclk_sync, audio0,
+        audio1, audio2, audio3, audio4, spdif, clk_out_1, clk_out_2, clk_out_3,
+        blink, xusb_host_src = 252, xusb_falcon_src, xusb_fs_src, xusb_ss_src,
+        xusb_dev_src, xusb_dev, xusb_hs_src, sclk, hclk, pclk, cclk_g, cclk_lp,
+
+        /* Mux clocks */
+
+        audio0_mux = 300, audio1_mux, audio2_mux, audio3_mux, audio4_mux,
+        spdif_mux, clk_out_1_mux, clk_out_2_mux, clk_out_3_mux, dsia_mux,
+        dsib_mux, clk_max,
+};
+
+struct utmi_clk_param {
+        /* Oscillator Frequency in KHz */
+        u32 osc_frequency;
+        /* UTMIP PLL Enable Delay Count  */
+        u8 enable_delay_count;
+        /* UTMIP PLL Stable count */
+        u8 stable_count;
+        /*  UTMIP PLL Active delay count */
+        u8 active_delay_count;
+        /* UTMIP PLL Xtal frequency count */
+        u8 xtal_freq_count;
+};
+
+static const struct utmi_clk_param utmi_parameters[] = {
+        {.osc_frequency = 13000000, .enable_delay_count = 0x02,
+         .stable_count = 0x33, .active_delay_count = 0x05,
+         .xtal_freq_count = 0x7F},
+        {.osc_frequency = 19200000, .enable_delay_count = 0x03,
+         .stable_count = 0x4B, .active_delay_count = 0x06,
+         .xtal_freq_count = 0xBB},
+        {.osc_frequency = 12000000, .enable_delay_count = 0x02,
+         .stable_count = 0x2F, .active_delay_count = 0x04,
+         .xtal_freq_count = 0x76},
+        {.osc_frequency = 26000000, .enable_delay_count = 0x04,
+         .stable_count = 0x66, .active_delay_count = 0x09,
+         .xtal_freq_count = 0xFE},
+        {.osc_frequency = 16800000, .enable_delay_count = 0x03,
+         .stable_count = 0x41, .active_delay_count = 0x0A,
+         .xtal_freq_count = 0xA4},
+};
+
+/* peripheral mux definitions */
+
+#define MUX_I2S_SPDIF(_id)                                              \
+static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { "pll_a_out0", \
+                                                           #_id, "pll_p",\
+                                                           "clk_m"};
+MUX_I2S_SPDIF(audio0)
+MUX_I2S_SPDIF(audio1)
+MUX_I2S_SPDIF(audio2)
+MUX_I2S_SPDIF(audio3)
+MUX_I2S_SPDIF(audio4)
+MUX_I2S_SPDIF(audio)
+
+#define mux_pllaout0_audio0_2x_pllp_clkm_idx NULL
+#define mux_pllaout0_audio1_2x_pllp_clkm_idx NULL
+#define mux_pllaout0_audio2_2x_pllp_clkm_idx NULL
+#define mux_pllaout0_audio3_2x_pllp_clkm_idx NULL
+#define mux_pllaout0_audio4_2x_pllp_clkm_idx NULL
+#define mux_pllaout0_audio_2x_pllp_clkm_idx NULL
+
+static const char *mux_pllp_pllc_pllm_clkm[] = {
+        "pll_p", "pll_c", "pll_m", "clk_m"
+};
+#define mux_pllp_pllc_pllm_clkm_idx NULL
+
+static const char *mux_pllp_pllc_pllm[] = { "pll_p", "pll_c", "pll_m" };
+#define mux_pllp_pllc_pllm_idx NULL
+
+static const char *mux_pllp_pllc_clk32_clkm[] = {
+        "pll_p", "pll_c", "clk_32k", "clk_m"
+};
+#define mux_pllp_pllc_clk32_clkm_idx NULL
+
+static const char *mux_plla_pllc_pllp_clkm[] = {
+        "pll_a_out0", "pll_c", "pll_p", "clk_m"
+};
+#define mux_plla_pllc_pllp_clkm_idx mux_pllp_pllc_pllm_clkm_idx
+
+static const char *mux_pllp_pllc2_c_c3_pllm_clkm[] = {
+        "pll_p", "pll_c2", "pll_c", "pll_c3", "pll_m", "clk_m"
+};
+static u32 mux_pllp_pllc2_c_c3_pllm_clkm_idx[] = {
+        [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6,
+};
+
+static const char *mux_pllp_clkm[] = {
+        "pll_p", "clk_m"
+};
+static u32 mux_pllp_clkm_idx[] = {
+        [0] = 0, [1] = 3,
+};
+
+static const char *mux_pllm_pllc2_c_c3_pllp_plla[] = {
+        "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0"
+};
+#define mux_pllm_pllc2_c_c3_pllp_plla_idx mux_pllp_pllc2_c_c3_pllm_clkm_idx
+
+static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
+        "pll_p", "pll_m", "pll_d_out0", "pll_a_out0", "pll_c",
+        "pll_d2_out0", "clk_m"
+};
+#define mux_pllp_pllm_plld_plla_pllc_plld2_clkm_idx NULL
+
+static const char *mux_pllm_pllc_pllp_plla[] = {
+        "pll_m", "pll_c", "pll_p", "pll_a_out0"
+};
+#define mux_pllm_pllc_pllp_plla_idx mux_pllp_pllc_pllm_clkm_idx
+
+static const char *mux_pllp_pllc_clkm[] = {
+        "pll_p", "pll_c", "pll_m"
+};
+static u32 mux_pllp_pllc_clkm_idx[] = {
+        [0] = 0, [1] = 1, [2] = 3,
+};
+
+static const char *mux_pllp_pllc_clkm_clk32[] = {
+        "pll_p", "pll_c", "clk_m", "clk_32k"
+};
+#define mux_pllp_pllc_clkm_clk32_idx NULL
+
+static const char *mux_plla_clk32_pllp_clkm_plle[] = {
+        "pll_a_out0", "clk_32k", "pll_p", "clk_m", "pll_e_out0"
+};
+#define mux_plla_clk32_pllp_clkm_plle_idx NULL
+
+static const char *mux_clkm_pllp_pllc_pllre[] = {
+        "clk_m", "pll_p", "pll_c", "pll_re_out"
+};
+static u32 mux_clkm_pllp_pllc_pllre_idx[] = {
+        [0] = 0, [1] = 1, [2] = 3, [3] = 5,
+};
+
+static const char *mux_clkm_48M_pllp_480M[] = {
+        "clk_m", "pll_u_48M", "pll_p", "pll_u_480M"
+};
+#define mux_clkm_48M_pllp_480M_idx NULL
+
+static const char *mux_clkm_pllre_clk32_480M_pllc_ref[] = {
+        "clk_m", "pll_re_out", "clk_32k", "pll_u_480M", "pll_c", "pll_ref"
+};
+static u32 mux_clkm_pllre_clk32_480M_pllc_ref_idx[] = {
+        [0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 4, [5] = 7,
+};
+
+static const char *mux_plld_out0_plld2_out0[] = {
+        "pll_d_out0", "pll_d2_out0",
+};
+#define mux_plld_out0_plld2_out0_idx NULL
+
+static const char *mux_d_audio_clk[] = {
+        "pll_a_out0", "pll_p", "clk_m", "spdif_in_sync", "i2s0_sync",
+        "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",
+};
+static u32 mux_d_audio_clk_idx[] = {
+        [0] = 0, [1] = 0x8000, [2] = 0xc000, [3] = 0xE000, [4] = 0xE001,
+        [5] = 0xE002, [6] = 0xE003, [7] = 0xE004, [8] = 0xE005, [9] = 0xE007,
+};
+
+static const char *mux_pllmcp_clkm[] = {
+        "pll_m_out0", "pll_c_out0", "pll_p_out0", "clk_m", "pll_m_ud",
+};
+
+static const struct clk_div_table pll_re_div_table[] = {
+        { .val = 0, .div = 1 },
+        { .val = 1, .div = 2 },
+        { .val = 2, .div = 3 },
+        { .val = 3, .div = 4 },
+        { .val = 4, .div = 5 },
+        { .val = 5, .div = 6 },
+        { .val = 0, .div = 0 },
+};
+
+static struct clk *clks[clk_max];
+static struct clk_onecell_data clk_data;
+
+static unsigned long osc_freq;
+static unsigned long pll_ref_freq;
+
+static int __init tegra114_osc_clk_init(void __iomem *clk_base)
+{
+        struct clk *clk;
+        u32 val, pll_ref_div;
+
+        val = readl_relaxed(clk_base + OSC_CTRL);
+
+        osc_freq = tegra114_input_freq[val >> OSC_CTRL_OSC_FREQ_SHIFT];
+        if (!osc_freq) {
+                WARN_ON(1);
+                return -EINVAL;
+        }
+
+        /* clk_m */
+        clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT,
+                                      osc_freq);
+        clk_register_clkdev(clk, "clk_m", NULL);
+        clks[clk_m] = clk;
+
+        /* pll_ref */
+        val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3;
+        pll_ref_div = 1 << val;
+        clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m",
+                                        CLK_SET_RATE_PARENT, 1, pll_ref_div);
+        clk_register_clkdev(clk, "pll_ref", NULL);
+        clks[pll_ref] = clk;
+
+        pll_ref_freq = osc_freq / pll_ref_div;
+
+        return 0;
+}
+
+static void __init tegra114_fixed_clk_init(void __iomem *clk_base)
+{
+        struct clk *clk;
+
+        /* clk_32k */
+        clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT,
+                                      32768);
+        clk_register_clkdev(clk, "clk_32k", NULL);
+        clks[clk_32k] = clk;
+
+        /* clk_m_div2 */
+        clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m",
+                                        CLK_SET_RATE_PARENT, 1, 2);
+        clk_register_clkdev(clk, "clk_m_div2", NULL);
+        clks[clk_m_div2] = clk;
+
+        /* clk_m_div4 */
+        clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m",
+                                        CLK_SET_RATE_PARENT, 1, 4);
+        clk_register_clkdev(clk, "clk_m_div4", NULL);
+        clks[clk_m_div4] = clk;
+
+}
+
+static __init void tegra114_utmi_param_configure(void __iomem *clk_base)
+{
+        u32 reg;
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
+                if (osc_freq == utmi_parameters[i].osc_frequency)
+                        break;
+        }
+
+        if (i >= ARRAY_SIZE(utmi_parameters)) {
+                pr_err("%s: Unexpected oscillator freq %lu\n", __func__,
+                       osc_freq);
+                return;
+        }
+
+        reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
+
+        /* Program UTMIP PLL stable and active counts */
+        /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */
+        reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
+        reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count);
+
+        reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
+
+        reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i].
+                                            active_delay_count);
+
+        /* Remove power downs from UTMIP PLL control bits */
+        reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
+        reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
+        reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
+
+        writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
+
+        /* Program UTMIP PLL delay and oscillator frequency counts */
+        reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
+        reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
+
+        reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i].
+                                            enable_delay_count);
+
+        reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
+        reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters[i].
+                                           xtal_freq_count);
+
+        /* Remove power downs from UTMIP PLL control bits */
+        reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
+        reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
+        reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
+        reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
+        writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
+
+        /* Setup HW control of UTMIPLL */
+        reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
+        reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
+        reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
+        reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;
+        writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
+
+        reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
+        reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
+        reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
+        writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
+
+        udelay(1);
+
+        /* Setup SW override of UTMIPLL assuming USB2.0
+           ports are assigned to USB2 */
+        reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
+        reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
+        reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
+        writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
+
+        udelay(1);
+
+        /* Enable HW control UTMIPLL */
+        reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
+        reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
+        writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
+}
+
+static void __init _clip_vco_min(struct tegra_clk_pll_params *pll_params)
+{
+        pll_params->vco_min =
+                DIV_ROUND_UP(pll_params->vco_min, pll_ref_freq) * pll_ref_freq;
+}
+
+static int __init _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params,
+                                      void __iomem *clk_base)
+{
+        u32 val;
+        u32 step_a, step_b;
+
+        switch (pll_ref_freq) {
+        case 12000000:
+        case 13000000:
+        case 26000000:
+                step_a = 0x2B;
+                step_b = 0x0B;
+                break;
+        case 16800000:
+                step_a = 0x1A;
+                step_b = 0x09;
+                break;
+        case 19200000:
+                step_a = 0x12;
+                step_b = 0x08;
+                break;
+        default:
+                pr_err("%s: Unexpected reference rate %lu\n",
+                        __func__, pll_ref_freq);
+                WARN_ON(1);
+                return -EINVAL;
+        }
+
+        val = step_a << pll_params->stepa_shift;
+        val |= step_b << pll_params->stepb_shift;
+        writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg);
+
+        return 0;
+}
+
+static void __init _init_iddq(struct tegra_clk_pll_params *pll_params,
+                              void __iomem *clk_base)
+{
+        u32 val, val_iddq;
+
+        val = readl_relaxed(clk_base + pll_params->base_reg);
+        val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
+
+        if (val & BIT(30))
+                WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx));
+        else {
+                val_iddq |= BIT(pll_params->iddq_bit_idx);
+                writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);
+        }
+}
+
+static void __init tegra114_pll_init(void __iomem *clk_base,
+                                     void __iomem *pmc)
+{
+        u32 val;
+        struct clk *clk;
+
+        /* PLLC */
+        _clip_vco_min(&pll_c_params);
+        if (_setup_dynamic_ramp(&pll_c_params, clk_base) >= 0) {
+                _init_iddq(&pll_c_params, clk_base);
+                clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base,
+                                pmc, 0, 0, &pll_c_params, TEGRA_PLL_USE_LOCK,
+                                pll_c_freq_table, NULL);
+                clk_register_clkdev(clk, "pll_c", NULL);
+                clks[pll_c] = clk;
+
+                /* PLLC_OUT1 */
+                clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
+                                clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
+                                8, 8, 1, NULL);
+                clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
+                                        clk_base + PLLC_OUT, 1, 0,
+                                        CLK_SET_RATE_PARENT, 0, NULL);
+                clk_register_clkdev(clk, "pll_c_out1", NULL);
+                clks[pll_c_out1] = clk;
+        }
+
+        /* PLLC2 */
+        _clip_vco_min(&pll_c2_params);
+        clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0, 0,
+                             &pll_c2_params, TEGRA_PLL_USE_LOCK,
+                             pll_cx_freq_table, NULL);
+        clk_register_clkdev(clk, "pll_c2", NULL);
+        clks[pll_c2] = clk;
+
+        /* PLLC3 */
+        _clip_vco_min(&pll_c3_params);
+        clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0, 0,
+                             &pll_c3_params, TEGRA_PLL_USE_LOCK,
+                             pll_cx_freq_table, NULL);
+        clk_register_clkdev(clk, "pll_c3", NULL);
+        clks[pll_c3] = clk;
+
+        /* PLLP */
+        clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, pmc, 0,
+                            408000000, &pll_p_params,
+                            TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK,
+                            pll_p_freq_table, NULL);
+        clk_register_clkdev(clk, "pll_p", NULL);
+        clks[pll_p] = clk;
+
+        /* PLLP_OUT1 */
+        clk = tegra_clk_register_divider("pll_p_out1_div", "pll_p",
+                                clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED |
+                                TEGRA_DIVIDER_ROUND_UP, 8, 8, 1, &pll_div_lock);
+        clk = tegra_clk_register_pll_out("pll_p_out1", "pll_p_out1_div",
+                                clk_base + PLLP_OUTA, 1, 0,
+                                CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
+                                &pll_div_lock);
+        clk_register_clkdev(clk, "pll_p_out1", NULL);
+        clks[pll_p_out1] = clk;
+
+        /* PLLP_OUT2 */
+        clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p",
+                                clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED |
+                                TEGRA_DIVIDER_ROUND_UP, 24, 8, 1,
+                                &pll_div_lock);
+        clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div",
+                                clk_base + PLLP_OUTA, 17, 16,
+                                CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
+                                &pll_div_lock);
+        clk_register_clkdev(clk, "pll_p_out2", NULL);
+        clks[pll_p_out2] = clk;
+
+        /* PLLP_OUT3 */
+        clk = tegra_clk_register_divider("pll_p_out3_div", "pll_p",
+                                clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED |
+                                TEGRA_DIVIDER_ROUND_UP, 8, 8, 1, &pll_div_lock);
+        clk = tegra_clk_register_pll_out("pll_p_out3", "pll_p_out3_div",
+                                clk_base + PLLP_OUTB, 1, 0,
+                                CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
+                                &pll_div_lock);
+        clk_register_clkdev(clk, "pll_p_out3", NULL);
+        clks[pll_p_out3] = clk;
+
+        /* PLLP_OUT4 */
+        clk = tegra_clk_register_divider("pll_p_out4_div", "pll_p",
+                                clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED |
+                                TEGRA_DIVIDER_ROUND_UP, 24, 8, 1,
+                                &pll_div_lock);
+        clk = tegra_clk_register_pll_out("pll_p_out4", "pll_p_out4_div",
+                                clk_base + PLLP_OUTB, 17, 16,
+                                CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
+                                &pll_div_lock);
+        clk_register_clkdev(clk, "pll_p_out4", NULL);
+        clks[pll_p_out4] = clk;
+
+        /* PLLM */
+        _clip_vco_min(&pll_m_params);
+        clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,
+                             CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, 0,
+                             &pll_m_params, TEGRA_PLL_USE_LOCK,
+                             pll_m_freq_table, NULL);
+        clk_register_clkdev(clk, "pll_m", NULL);
+        clks[pll_m] = clk;
+
+        /* PLLM_OUT1 */
+        clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
+                                clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
+                                8, 8, 1, NULL);
+        clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
+                                clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
+                                CLK_SET_RATE_PARENT, 0, NULL);
+        clk_register_clkdev(clk, "pll_m_out1", NULL);
+        clks[pll_m_out1] = clk;
+
+        /* PLLM_UD */
+        clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",
+                                        CLK_SET_RATE_PARENT, 1, 1);
+
+        /* PLLX */
+        _clip_vco_min(&pll_x_params);
+        if (_setup_dynamic_ramp(&pll_x_params, clk_base) >= 0) {
+                _init_iddq(&pll_x_params, clk_base);
+                clk = tegra_clk_register_pllxc("pll_x", "pll_ref", clk_base,
+                                pmc, CLK_IGNORE_UNUSED, 0, &pll_x_params,
+                                TEGRA_PLL_USE_LOCK, pll_x_freq_table, NULL);
+                clk_register_clkdev(clk, "pll_x", NULL);
+                clks[pll_x] = clk;
+        }
+
+        /* PLLX_OUT0 */
+        clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x",
+                                        CLK_SET_RATE_PARENT, 1, 2);
+        clk_register_clkdev(clk, "pll_x_out0", NULL);
+        clks[pll_x_out0] = clk;
+
+        /* PLLU */
+        val = readl(clk_base + pll_u_params.base_reg);
+        val &= ~BIT(24); /* disable PLLU_OVERRIDE */
+        writel(val, clk_base + pll_u_params.base_reg);
+
+        clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc, 0,
+                            0, &pll_u_params, TEGRA_PLLU |
+                            TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
+                            TEGRA_PLL_USE_LOCK, pll_u_freq_table, &pll_u_lock);
+        clk_register_clkdev(clk, "pll_u", NULL);
+        clks[pll_u] = clk;
+
+        tegra114_utmi_param_configure(clk_base);
+
+        /* PLLU_480M */
+        clk = clk_register_gate(NULL, "pll_u_480M", "pll_u",
+                                CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
+                                22, 0, &pll_u_lock);
+        clk_register_clkdev(clk, "pll_u_480M", NULL);
+        clks[pll_u_480M] = clk;
+
+        /* PLLU_60M */
+        clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u",
+                                        CLK_SET_RATE_PARENT, 1, 8);
+        clk_register_clkdev(clk, "pll_u_60M", NULL);
+        clks[pll_u_60M] = clk;
+
+        /* PLLU_48M */
+        clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u",
+                                        CLK_SET_RATE_PARENT, 1, 10);
+        clk_register_clkdev(clk, "pll_u_48M", NULL);
+        clks[pll_u_48M] = clk;
+
+        /* PLLU_12M */
+        clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u",
+                                        CLK_SET_RATE_PARENT, 1, 40);
+        clk_register_clkdev(clk, "pll_u_12M", NULL);
+        clks[pll_u_12M] = clk;
+
+        /* PLLD */
+        clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,
+                            0, &pll_d_params,
+                            TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
+                            TEGRA_PLL_USE_LOCK, pll_d_freq_table, &pll_d_lock);
+        clk_register_clkdev(clk, "pll_d", NULL);
+        clks[pll_d] = clk;
+
+        /* PLLD_OUT0 */
+        clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
+                                        CLK_SET_RATE_PARENT, 1, 2);
+        clk_register_clkdev(clk, "pll_d_out0", NULL);
+        clks[pll_d_out0] = clk;
+
+        /* PLLD2 */
+        clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc, 0,
+                            0, &pll_d2_params,
+                            TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
+                            TEGRA_PLL_USE_LOCK, pll_d_freq_table, &pll_d2_lock);
+        clk_register_clkdev(clk, "pll_d2", NULL);
+        clks[pll_d2] = clk;
+
+        /* PLLD2_OUT0 */
+        clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
+                                        CLK_SET_RATE_PARENT, 1, 2);
+        clk_register_clkdev(clk, "pll_d2_out0", NULL);
+        clks[pll_d2_out0] = clk;
+
+        /* PLLA */
+        clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, pmc, 0,
+                            0, &pll_a_params, TEGRA_PLL_HAS_CPCON |
+                            TEGRA_PLL_USE_LOCK, pll_a_freq_table, NULL);
+        clk_register_clkdev(clk, "pll_a", NULL);
+        clks[pll_a] = clk;
+
+        /* PLLA_OUT0 */
+        clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a",
+                                clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
+                                8, 8, 1, NULL);
+        clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div",
+                                clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED |
+                                CLK_SET_RATE_PARENT, 0, NULL);
+        clk_register_clkdev(clk, "pll_a_out0", NULL);
+        clks[pll_a_out0] = clk;
+
+        /* PLLRE */
+        _clip_vco_min(&pll_re_vco_params);
+        clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc,
+                             0, 0, &pll_re_vco_params, TEGRA_PLL_USE_LOCK,
+                             NULL, &pll_re_lock, pll_ref_freq);
+        clk_register_clkdev(clk, "pll_re_vco", NULL);
+        clks[pll_re_vco] = clk;
+
+        clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0,
+                                         clk_base + PLLRE_BASE, 16, 4, 0,
+                                         pll_re_div_table, &pll_re_lock);
+        clk_register_clkdev(clk, "pll_re_out", NULL);
+        clks[pll_re_out] = clk;
+
+        /* PLLE */
+        clk = tegra_clk_register_plle_tegra114("pll_e_out0", "pll_re_vco",
+                                      clk_base, 0, 100000000, &pll_e_params,
+                                      pll_e_freq_table, NULL);
+        clk_register_clkdev(clk, "pll_e_out0", NULL);
+        clks[pll_e_out0] = clk;
+}
+
+static const char *mux_audio_sync_clk[] = { "spdif_in_sync", "i2s0_sync",
+        "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",
+};
+
+static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2",
+        "clk_m_div4", "extern1",
+};
+
+static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2",
+        "clk_m_div4", "extern2",
+};
+
+static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2",
+        "clk_m_div4", "extern3",
+};
+
+static void __init tegra114_audio_clk_init(void __iomem *clk_base)
+{
+        struct clk *clk;
+
+        /* spdif_in_sync */
+        clk = tegra_clk_register_sync_source("spdif_in_sync", 24000000,
+                                             24000000);
+        clk_register_clkdev(clk, "spdif_in_sync", NULL);
+        clks[spdif_in_sync] = clk;
+
+        /* i2s0_sync */
+        clk = tegra_clk_register_sync_source("i2s0_sync", 24000000, 24000000);
+        clk_register_clkdev(clk, "i2s0_sync", NULL);
+        clks[i2s0_sync] = clk;
+
+        /* i2s1_sync */
+        clk = tegra_clk_register_sync_source("i2s1_sync", 24000000, 24000000);
+        clk_register_clkdev(clk, "i2s1_sync", NULL);
+        clks[i2s1_sync] = clk;
+
+        /* i2s2_sync */
+        clk = tegra_clk_register_sync_source("i2s2_sync", 24000000, 24000000);
+        clk_register_clkdev(clk, "i2s2_sync", NULL);
+        clks[i2s2_sync] = clk;
+
+        /* i2s3_sync */
+        clk = tegra_clk_register_sync_source("i2s3_sync", 24000000, 24000000);
+        clk_register_clkdev(clk, "i2s3_sync", NULL);
+        clks[i2s3_sync] = clk;
+
+        /* i2s4_sync */
+        clk = tegra_clk_register_sync_source("i2s4_sync", 24000000, 24000000);
+        clk_register_clkdev(clk, "i2s4_sync", NULL);
+        clks[i2s4_sync] = clk;
+
+        /* vimclk_sync */
+        clk = tegra_clk_register_sync_source("vimclk_sync", 24000000, 24000000);
+        clk_register_clkdev(clk, "vimclk_sync", NULL);
+        clks[vimclk_sync] = clk;
+
+        /* audio0 */
+        clk = clk_register_mux(NULL, "audio0_mux", mux_audio_sync_clk,
+                               ARRAY_SIZE(mux_audio_sync_clk), 0,
+                               clk_base + AUDIO_SYNC_CLK_I2S0, 0, 3, 0,
+                               NULL);
+        clks[audio0_mux] = clk;
+        clk = clk_register_gate(NULL, "audio0", "audio0_mux", 0,
+                                clk_base + AUDIO_SYNC_CLK_I2S0, 4,
+                                CLK_GATE_SET_TO_DISABLE, NULL);
+        clk_register_clkdev(clk, "audio0", NULL);
+        clks[audio0] = clk;
+
+        /* audio1 */
+        clk = clk_register_mux(NULL, "audio1_mux", mux_audio_sync_clk,
+                               ARRAY_SIZE(mux_audio_sync_clk), 0,
+                               clk_base + AUDIO_SYNC_CLK_I2S1, 0, 3, 0,
+                               NULL);
+        clks[audio1_mux] = clk;
+        clk = clk_register_gate(NULL, "audio1", "audio1_mux", 0,
+                                clk_base + AUDIO_SYNC_CLK_I2S1, 4,
+                                CLK_GATE_SET_TO_DISABLE, NULL);
+        clk_register_clkdev(clk, "audio1", NULL);
+        clks[audio1] = clk;
+
+        /* audio2 */
+        clk = clk_register_mux(NULL, "audio2_mux", mux_audio_sync_clk,
+                               ARRAY_SIZE(mux_audio_sync_clk), 0,
+                               clk_base + AUDIO_SYNC_CLK_I2S2, 0, 3, 0,
+                               NULL);
+        clks[audio2_mux] = clk;
+        clk = clk_register_gate(NULL, "audio2", "audio2_mux", 0,
+                                clk_base + AUDIO_SYNC_CLK_I2S2, 4,
+                                CLK_GATE_SET_TO_DISABLE, NULL);
+        clk_register_clkdev(clk, "audio2", NULL);
+        clks[audio2] = clk;
+
+        /* audio3 */
+        clk = clk_register_mux(NULL, "audio3_mux", mux_audio_sync_clk,
+                               ARRAY_SIZE(mux_audio_sync_clk), 0,
+                               clk_base + AUDIO_SYNC_CLK_I2S3, 0, 3, 0,
+                               NULL);
+        clks[audio3_mux] = clk;
+        clk = clk_register_gate(NULL, "audio3", "audio3_mux", 0,
+                                clk_base + AUDIO_SYNC_CLK_I2S3, 4,
+                                CLK_GATE_SET_TO_DISABLE, NULL);
+        clk_register_clkdev(clk, "audio3", NULL);
+        clks[audio3] = clk;
+
+        /* audio4 */
+        clk = clk_register_mux(NULL, "audio4_mux", mux_audio_sync_clk,
+                               ARRAY_SIZE(mux_audio_sync_clk), 0,
+                               clk_base + AUDIO_SYNC_CLK_I2S4, 0, 3, 0,
+                               NULL);
+        clks[audio4_mux] = clk;
+        clk = clk_register_gate(NULL, "audio4", "audio4_mux", 0,
+                                clk_base + AUDIO_SYNC_CLK_I2S4, 4,
+                                CLK_GATE_SET_TO_DISABLE, NULL);
+        clk_register_clkdev(clk, "audio4", NULL);
+        clks[audio4] = clk;
+
+        /* spdif */
+        clk = clk_register_mux(NULL, "spdif_mux", mux_audio_sync_clk,
+                               ARRAY_SIZE(mux_audio_sync_clk), 0,
+                               clk_base + AUDIO_SYNC_CLK_SPDIF, 0, 3, 0,
+                               NULL);
+        clks[spdif_mux] = clk;
+        clk = clk_register_gate(NULL, "spdif", "spdif_mux", 0,
+                                clk_base + AUDIO_SYNC_CLK_SPDIF, 4,
+                                CLK_GATE_SET_TO_DISABLE, NULL);
+        clk_register_clkdev(clk, "spdif", NULL);
+        clks[spdif] = clk;
+
+        /* audio0_2x */
+        clk = clk_register_fixed_factor(NULL, "audio0_doubler", "audio0",
+                                        CLK_SET_RATE_PARENT, 2, 1);
+        clk = tegra_clk_register_divider("audio0_div", "audio0_doubler",
+                                clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 24, 1,
+                                0, &clk_doubler_lock);
+        clk = tegra_clk_register_periph_gate("audio0_2x", "audio0_div",
+                                  TEGRA_PERIPH_NO_RESET, clk_base,
+                                  CLK_SET_RATE_PARENT, 113, &periph_v_regs,
+                                  periph_clk_enb_refcnt);
+        clk_register_clkdev(clk, "audio0_2x", NULL);
+        clks[audio0_2x] = clk;
+
+        /* audio1_2x */
+        clk = clk_register_fixed_factor(NULL, "audio1_doubler", "audio1",
+                                        CLK_SET_RATE_PARENT, 2, 1);
+        clk = tegra_clk_register_divider("audio1_div", "audio1_doubler",
+                                clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 25, 1,
+                                0, &clk_doubler_lock);
+        clk = tegra_clk_register_periph_gate("audio1_2x", "audio1_div",
+                                  TEGRA_PERIPH_NO_RESET, clk_base,
+                                  CLK_SET_RATE_PARENT, 114, &periph_v_regs,
+                                  periph_clk_enb_refcnt);
+        clk_register_clkdev(clk, "audio1_2x", NULL);
+        clks[audio1_2x] = clk;
+
+        /* audio2_2x */
+        clk = clk_register_fixed_factor(NULL, "audio2_doubler", "audio2",
+                                        CLK_SET_RATE_PARENT, 2, 1);
+        clk = tegra_clk_register_divider("audio2_div", "audio2_doubler",
+                                clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 26, 1,
+                                0, &clk_doubler_lock);
+        clk = tegra_clk_register_periph_gate("audio2_2x", "audio2_div",
+                                  TEGRA_PERIPH_NO_RESET, clk_base,
+                                  CLK_SET_RATE_PARENT, 115, &periph_v_regs,
+                                  periph_clk_enb_refcnt);
+        clk_register_clkdev(clk, "audio2_2x", NULL);
+        clks[audio2_2x] = clk;
+
+        /* audio3_2x */
+        clk = clk_register_fixed_factor(NULL, "audio3_doubler", "audio3",
+                                        CLK_SET_RATE_PARENT, 2, 1);
+        clk = tegra_clk_register_divider("audio3_div", "audio3_doubler",
+                                clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 27, 1,
+                                0, &clk_doubler_lock);
+        clk = tegra_clk_register_periph_gate("audio3_2x", "audio3_div",
+                                  TEGRA_PERIPH_NO_RESET, clk_base,
+                                  CLK_SET_RATE_PARENT, 116, &periph_v_regs,
+                                  periph_clk_enb_refcnt);
+        clk_register_clkdev(clk, "audio3_2x", NULL);
+        clks[audio3_2x] = clk;
+
+        /* audio4_2x */
+        clk = clk_register_fixed_factor(NULL, "audio4_doubler", "audio4",
+                                        CLK_SET_RATE_PARENT, 2, 1);
+        clk = tegra_clk_register_divider("audio4_div", "audio4_doubler",
+                                clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 28, 1,
+                                0, &clk_doubler_lock);
+        clk = tegra_clk_register_periph_gate("audio4_2x", "audio4_div",
+                                  TEGRA_PERIPH_NO_RESET, clk_base,
+                                  CLK_SET_RATE_PARENT, 117, &periph_v_regs,
+                                  periph_clk_enb_refcnt);
+        clk_register_clkdev(clk, "audio4_2x", NULL);
+        clks[audio4_2x] = clk;
+
+        /* spdif_2x */
+        clk = clk_register_fixed_factor(NULL, "spdif_doubler", "spdif",
+                                        CLK_SET_RATE_PARENT, 2, 1);
+        clk = tegra_clk_register_divider("spdif_div", "spdif_doubler",
+                                clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 29, 1,
+                                0, &clk_doubler_lock);
+        clk = tegra_clk_register_periph_gate("spdif_2x", "spdif_div",
+                                  TEGRA_PERIPH_NO_RESET, clk_base,
+                                  CLK_SET_RATE_PARENT, 118,
+                                  &periph_v_regs, periph_clk_enb_refcnt);
+        clk_register_clkdev(clk, "spdif_2x", NULL);
+        clks[spdif_2x] = clk;
+}
+
+static void __init tegra114_pmc_clk_init(void __iomem *pmc_base)
+{
+        struct clk *clk;
+
+        /* clk_out_1 */
+        clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents,
+                               ARRAY_SIZE(clk_out1_parents), 0,
+                               pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0,
+                               &clk_out_lock);
+        clks[clk_out_1_mux] = clk;
+        clk = clk_register_gate(NULL, "clk_out_1", "clk_out_1_mux", 0,
+                                pmc_base + PMC_CLK_OUT_CNTRL, 2, 0,
+                                &clk_out_lock);
+        clk_register_clkdev(clk, "extern1", "clk_out_1");
+        clks[clk_out_1] = clk;
+
+        /* clk_out_2 */
+        clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents,
+                               ARRAY_SIZE(clk_out1_parents), 0,
+                               pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0,
+                               &clk_out_lock);
+        clks[clk_out_2_mux] = clk;
+        clk = clk_register_gate(NULL, "clk_out_2", "clk_out_2_mux", 0,
+                                pmc_base + PMC_CLK_OUT_CNTRL, 10, 0,
+                                &clk_out_lock);
+        clk_register_clkdev(clk, "extern2", "clk_out_2");
+        clks[clk_out_2] = clk;
+
+        /* clk_out_3 */
+        clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents,
+                               ARRAY_SIZE(clk_out1_parents), 0,
+                               pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0,
+                               &clk_out_lock);
+        clks[clk_out_3_mux] = clk;
+        clk = clk_register_gate(NULL, "clk_out_3", "clk_out_3_mux", 0,
+                                pmc_base + PMC_CLK_OUT_CNTRL, 18, 0,
+                                &clk_out_lock);
+        clk_register_clkdev(clk, "extern3", "clk_out_3");
+        clks[clk_out_3] = clk;
+
+        /* blink */
+        clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0,
+                                pmc_base + PMC_DPD_PADS_ORIDE,
+                                PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL);
+        clk = clk_register_gate(NULL, "blink", "blink_override", 0,
+                                pmc_base + PMC_CTRL,
+                                PMC_CTRL_BLINK_ENB, 0, NULL);
+        clk_register_clkdev(clk, "blink", NULL);
+        clks[blink] = clk;
+
+}
+
+static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
+                               "pll_p_out3", "pll_p_out2", "unused",
+                               "clk_32k", "pll_m_out1" };
+
+static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
+                                        "pll_p", "pll_p_out4", "unused",
+                                        "unused", "pll_x" };
+
+static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
+                                         "pll_p", "pll_p_out4", "unused",
+                                         "unused", "pll_x", "pll_x_out0" };
+
+static void __init tegra114_super_clk_init(void __iomem *clk_base)
+{
+        struct clk *clk;
+
+        /* CCLKG */
+        clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents,
+                                        ARRAY_SIZE(cclk_g_parents),
+                                        CLK_SET_RATE_PARENT,
+                                        clk_base + CCLKG_BURST_POLICY,
+                                        0, 4, 0, 0, NULL);
+        clk_register_clkdev(clk, "cclk_g", NULL);
+        clks[cclk_g] = clk;
+
+        /* CCLKLP */
+        clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents,
+                                        ARRAY_SIZE(cclk_lp_parents),
+                                        CLK_SET_RATE_PARENT,
+                                        clk_base + CCLKLP_BURST_POLICY,
+                                        0, 4, 8, 9, NULL);
+        clk_register_clkdev(clk, "cclk_lp", NULL);
+        clks[cclk_lp] = clk;
+
+        /* SCLK */
+        clk = tegra_clk_register_super_mux("sclk", sclk_parents,
+                                        ARRAY_SIZE(sclk_parents),
+                                        CLK_SET_RATE_PARENT,
+                                        clk_base + SCLK_BURST_POLICY,
+                                        0, 4, 0, 0, NULL);
+        clk_register_clkdev(clk, "sclk", NULL);
+        clks[sclk] = clk;
+
+        /* HCLK */
+        clk = clk_register_divider(NULL, "hclk_div", "sclk", 0,
+                                   clk_base + SYSTEM_CLK_RATE, 4, 2, 0,
+                                   &sysrate_lock);
+        clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT |
+                                CLK_IGNORE_UNUSED, clk_base + SYSTEM_CLK_RATE,
+                                7, CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
+        clk_register_clkdev(clk, "hclk", NULL);
+        clks[hclk] = clk;
+
+        /* PCLK */
+        clk = clk_register_divider(NULL, "pclk_div", "hclk", 0,
+                                   clk_base + SYSTEM_CLK_RATE, 0, 2, 0,
+                                   &sysrate_lock);
+        clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT |
+                                CLK_IGNORE_UNUSED, clk_base + SYSTEM_CLK_RATE,
+                                3, CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
+        clk_register_clkdev(clk, "pclk", NULL);
+        clks[pclk] = clk;
+}
+
+static struct tegra_periph_init_data tegra_periph_clk_list[] = {
+        TEGRA_INIT_DATA_MUX("i2s0", NULL, "tegra30-i2s.0", mux_pllaout0_audio0_2x_pllp_clkm, CLK_SOURCE_I2S0, 30, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s0),
+        TEGRA_INIT_DATA_MUX("i2s1", NULL, "tegra30-i2s.1", mux_pllaout0_audio1_2x_pllp_clkm, CLK_SOURCE_I2S1, 11, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s1),
+        TEGRA_INIT_DATA_MUX("i2s2", NULL, "tegra30-i2s.2", mux_pllaout0_audio2_2x_pllp_clkm, CLK_SOURCE_I2S2, 18, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s2),
+        TEGRA_INIT_DATA_MUX("i2s3", NULL, "tegra30-i2s.3", mux_pllaout0_audio3_2x_pllp_clkm, CLK_SOURCE_I2S3, 101, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s3),
+        TEGRA_INIT_DATA_MUX("i2s4", NULL, "tegra30-i2s.4", mux_pllaout0_audio4_2x_pllp_clkm, CLK_SOURCE_I2S4, 102, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s4),
+        TEGRA_INIT_DATA_MUX("spdif_out", "spdif_out", "tegra30-spdif", mux_pllaout0_audio_2x_pllp_clkm, CLK_SOURCE_SPDIF_OUT, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_out),
+        TEGRA_INIT_DATA_MUX("spdif_in", "spdif_in", "tegra30-spdif", mux_pllp_pllc_pllm, CLK_SOURCE_SPDIF_IN, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_in),
+        TEGRA_INIT_DATA_MUX("pwm", NULL, "pwm", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_PWM, 17, &periph_l_regs, TEGRA_PERIPH_ON_APB, pwm),
+        TEGRA_INIT_DATA_MUX("adx", NULL, "adx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX, 154, &periph_w_regs, TEGRA_PERIPH_ON_APB, adx),
+        TEGRA_INIT_DATA_MUX("amx", NULL, "amx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX, 153, &periph_w_regs, TEGRA_PERIPH_ON_APB, amx),
+        TEGRA_INIT_DATA_MUX("hda", "hda", "tegra30-hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA, 125, &periph_v_regs, TEGRA_PERIPH_ON_APB, hda),
+        TEGRA_INIT_DATA_MUX("hda2codec_2x", "hda2codec", "tegra30-hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, &periph_v_regs, TEGRA_PERIPH_ON_APB, hda2codec_2x),
+        TEGRA_INIT_DATA_MUX("sbc1", NULL, "tegra11-spi.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC1, 41, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc1),
+        TEGRA_INIT_DATA_MUX("sbc2", NULL, "tegra11-spi.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC2, 44, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc2),
+        TEGRA_INIT_DATA_MUX("sbc3", NULL, "tegra11-spi.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC3, 46, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc3),
+        TEGRA_INIT_DATA_MUX("sbc4", NULL, "tegra11-spi.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC4, 68, &periph_u_regs, TEGRA_PERIPH_ON_APB, sbc4),
+        TEGRA_INIT_DATA_MUX("sbc5", NULL, "tegra11-spi.4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC5, 104, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc5),
+        TEGRA_INIT_DATA_MUX("sbc6", NULL, "tegra11-spi.5", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC6, 105, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc6),
+        TEGRA_INIT_DATA_MUX8("ndflash", NULL, "tegra_nand", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDFLASH, 13, &periph_u_regs, TEGRA_PERIPH_ON_APB, ndspeed),
+        TEGRA_INIT_DATA_MUX8("ndspeed", NULL, "tegra_nand_speed", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDSPEED, 80, &periph_u_regs, TEGRA_PERIPH_ON_APB, ndspeed),
+        TEGRA_INIT_DATA_MUX("vfir", NULL, "vfir", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VFIR, 7, &periph_l_regs, TEGRA_PERIPH_ON_APB, vfir),
+        TEGRA_INIT_DATA_MUX("sdmmc1", NULL, "sdhci-tegra.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC1, 14, &periph_l_regs, 0, sdmmc1),
+        TEGRA_INIT_DATA_MUX("sdmmc2", NULL, "sdhci-tegra.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC2, 9, &periph_l_regs, 0, sdmmc2),
+        TEGRA_INIT_DATA_MUX("sdmmc3", NULL, "sdhci-tegra.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, &periph_u_regs, 0, sdmmc3),
+        TEGRA_INIT_DATA_MUX("sdmmc4", NULL, "sdhci-tegra.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, &periph_l_regs, 0, sdmmc4),
+        TEGRA_INIT_DATA_INT("vde", NULL, "vde", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_VDE, 61, &periph_h_regs, 0, vde),
+        TEGRA_INIT_DATA_MUX_FLAGS("csite", NULL, "csite", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_CSITE, 73, &periph_u_regs, TEGRA_PERIPH_ON_APB, csite, CLK_IGNORE_UNUSED),
+        TEGRA_INIT_DATA_MUX("la", NULL, "la", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, &periph_u_regs, TEGRA_PERIPH_ON_APB, la),
+        TEGRA_INIT_DATA_MUX("trace", NULL, "trace", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, &periph_u_regs, TEGRA_PERIPH_ON_APB, trace),
+        TEGRA_INIT_DATA_MUX("owr", NULL, "tegra_w1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_OWR, 71, &periph_u_regs, TEGRA_PERIPH_ON_APB, owr),
+        TEGRA_INIT_DATA_MUX("nor", NULL, "tegra-nor", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NOR, 42, &periph_h_regs, 0, nor),
+        TEGRA_INIT_DATA_MUX("mipi", NULL, "mipi", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_MIPI, 50, &periph_h_regs, TEGRA_PERIPH_ON_APB, mipi),
+        TEGRA_INIT_DATA_I2C("i2c1", "div-clk", "tegra11-i2c.0", mux_pllp_clkm, CLK_SOURCE_I2C1, 12, &periph_l_regs, i2c1),
+        TEGRA_INIT_DATA_I2C("i2c2", "div-clk", "tegra11-i2c.1", mux_pllp_clkm, CLK_SOURCE_I2C2, 54, &periph_h_regs, i2c2),
+        TEGRA_INIT_DATA_I2C("i2c3", "div-clk", "tegra11-i2c.2", mux_pllp_clkm, CLK_SOURCE_I2C3, 67, &periph_u_regs, i2c3),
+        TEGRA_INIT_DATA_I2C("i2c4", "div-clk", "tegra11-i2c.3", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, &periph_v_regs, i2c4),
+        TEGRA_INIT_DATA_I2C("i2c5", "div-clk", "tegra11-i2c.4", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, &periph_h_regs, i2c5),
+        TEGRA_INIT_DATA_UART("uarta", NULL, "tegra_uart.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTA, 6, &periph_l_regs, uarta),
+        TEGRA_INIT_DATA_UART("uartb", NULL, "tegra_uart.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, &periph_l_regs, uartb),
+        TEGRA_INIT_DATA_UART("uartc", NULL, "tegra_uart.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, &periph_h_regs, uartc),
+        TEGRA_INIT_DATA_UART("uartd", NULL, "tegra_uart.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, &periph_u_regs, uartd),
+        TEGRA_INIT_DATA_INT("3d", NULL, "3d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_3D, 24, &periph_l_regs, 0, gr_3d),
+        TEGRA_INIT_DATA_INT("2d", NULL, "2d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_2D, 21, &periph_l_regs, 0, gr_2d),
+        TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor", "tegra_camera", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, &periph_l_regs, TEGRA_PERIPH_NO_RESET, vi_sensor),
+        TEGRA_INIT_DATA_INT8("vi", "vi", "tegra_camera", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI, 20, &periph_l_regs, 0, vi),
+        TEGRA_INIT_DATA_INT8("epp", NULL, "epp", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_EPP, 19, &periph_l_regs, 0, epp),
+        TEGRA_INIT_DATA_INT8("msenc", NULL, "msenc", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_MSENC, 91, &periph_h_regs, TEGRA_PERIPH_WAR_1005168, msenc),
+        TEGRA_INIT_DATA_INT8("tsec", NULL, "tsec", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_TSEC, 83, &periph_u_regs, 0, tsec),
+        TEGRA_INIT_DATA_INT8("host1x", NULL, "host1x", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_HOST1X, 28, &periph_l_regs, 0, host1x),
+        TEGRA_INIT_DATA_MUX8("hdmi", NULL, "hdmi", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_HDMI, 51, &periph_h_regs, 0, hdmi),
+        TEGRA_INIT_DATA_MUX("cilab", "cilab", "tegra_camera", mux_pllp_pllc_clkm, CLK_SOURCE_CILAB, 144, &periph_w_regs, 0, cilab),
+        TEGRA_INIT_DATA_MUX("cilcd", "cilcd", "tegra_camera", mux_pllp_pllc_clkm, CLK_SOURCE_CILCD, 145, &periph_w_regs, 0, cilcd),
+        TEGRA_INIT_DATA_MUX("cile", "cile", "tegra_camera", mux_pllp_pllc_clkm, CLK_SOURCE_CILE, 146, &periph_w_regs, 0, cile),
+        TEGRA_INIT_DATA_MUX("dsialp", "dsialp", "tegradc.0", mux_pllp_pllc_clkm, CLK_SOURCE_DSIALP, 147, &periph_w_regs, 0, dsialp),
+        TEGRA_INIT_DATA_MUX("dsiblp", "dsiblp", "tegradc.1", mux_pllp_pllc_clkm, CLK_SOURCE_DSIBLP, 148, &periph_w_regs, 0, dsiblp),
+        TEGRA_INIT_DATA_MUX("tsensor", NULL, "tegra-tsensor", mux_pllp_pllc_clkm_clk32, CLK_SOURCE_TSENSOR, 100, &periph_v_regs, TEGRA_PERIPH_ON_APB, tsensor),
+        TEGRA_INIT_DATA_MUX("actmon", NULL, "actmon", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_ACTMON, 119, &periph_v_regs, 0, actmon),
+        TEGRA_INIT_DATA_MUX8("extern1", NULL, "extern1", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, &periph_v_regs, 0, extern1),
+        TEGRA_INIT_DATA_MUX8("extern2", NULL, "extern2", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, &periph_v_regs, 0, extern2),
+        TEGRA_INIT_DATA_MUX8("extern3", NULL, "extern3", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, &periph_v_regs, 0, extern3),
+        TEGRA_INIT_DATA_MUX("i2cslow", NULL, "i2cslow", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_I2CSLOW, 81, &periph_u_regs, TEGRA_PERIPH_ON_APB, i2cslow),
+        TEGRA_INIT_DATA_INT8("se", NULL, "se", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SE, 127, &periph_v_regs, TEGRA_PERIPH_ON_APB, se),
+        TEGRA_INIT_DATA_INT_FLAGS("mselect", NULL, "mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, &periph_v_regs, 0, mselect, CLK_IGNORE_UNUSED),
+        TEGRA_INIT_DATA_MUX8("soc_therm", NULL, "soc_therm", mux_pllm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, &periph_u_regs, TEGRA_PERIPH_ON_APB, soc_therm),
+        TEGRA_INIT_DATA_XUSB("xusb_host_src", "host_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, &periph_w_regs, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, xusb_host_src),
+        TEGRA_INIT_DATA_XUSB("xusb_falcon_src", "falcon_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, &periph_w_regs, TEGRA_PERIPH_NO_RESET, xusb_falcon_src),
+        TEGRA_INIT_DATA_XUSB("xusb_fs_src", "fs_src", "tegra_xhci", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, &periph_w_regs, TEGRA_PERIPH_NO_RESET, xusb_fs_src),
+        TEGRA_INIT_DATA_XUSB("xusb_ss_src", "ss_src", "tegra_xhci", mux_clkm_pllre_clk32_480M_pllc_ref, CLK_SOURCE_XUSB_SS_SRC, 143, &periph_w_regs, TEGRA_PERIPH_NO_RESET, xusb_ss_src),
+        TEGRA_INIT_DATA_XUSB("xusb_dev_src", "dev_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, &periph_u_regs, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, xusb_dev_src),
+        TEGRA_INIT_DATA_AUDIO("d_audio", "d_audio", "tegra30-ahub", CLK_SOURCE_D_AUDIO, 106, &periph_v_regs, TEGRA_PERIPH_ON_APB, d_audio),
+        TEGRA_INIT_DATA_AUDIO("dam0", NULL, "tegra30-dam.0", CLK_SOURCE_DAM0, 108, &periph_v_regs, TEGRA_PERIPH_ON_APB, dam0),
+        TEGRA_INIT_DATA_AUDIO("dam1", NULL, "tegra30-dam.1", CLK_SOURCE_DAM1, 109, &periph_v_regs, TEGRA_PERIPH_ON_APB, dam1),
+        TEGRA_INIT_DATA_AUDIO("dam2", NULL, "tegra30-dam.2", CLK_SOURCE_DAM2, 110, &periph_v_regs, TEGRA_PERIPH_ON_APB, dam2),
+};
+
+static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {
+        TEGRA_INIT_DATA_NODIV("disp1", NULL, "tegradc.0", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, &periph_l_regs, 0, disp1),
+        TEGRA_INIT_DATA_NODIV("disp2", NULL, "tegradc.1", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, &periph_l_regs, 0, disp2),
+};
+
+static __init void tegra114_periph_clk_init(void __iomem *clk_base)
+{
+        struct tegra_periph_init_data *data;
+        struct clk *clk;
+        int i;
+        u32 val;
+
+        /* apbdma */
+        clk = tegra_clk_register_periph_gate("apbdma", "clk_m", 0, clk_base,
+                                  0, 34, &periph_h_regs,
+                                  periph_clk_enb_refcnt);
+        clks[apbdma] = clk;
+
+        /* rtc */
+        clk = tegra_clk_register_periph_gate("rtc", "clk_32k",
+                                    TEGRA_PERIPH_ON_APB |
+                                    TEGRA_PERIPH_NO_RESET, clk_base,
+                                    0, 4, &periph_l_regs,
+                                    periph_clk_enb_refcnt);
+        clk_register_clkdev(clk, NULL, "rtc-tegra");
+        clks[rtc] = clk;
+
+        /* kbc */
+        clk = tegra_clk_register_periph_gate("kbc", "clk_32k",
+                                    TEGRA_PERIPH_ON_APB |
+                                    TEGRA_PERIPH_NO_RESET, clk_base,
+                                    0, 36, &periph_h_regs,
+                                    periph_clk_enb_refcnt);
+        clks[kbc] = clk;
+
+        /* timer */
+        clk = tegra_clk_register_periph_gate("timer", "clk_m", 0, clk_base,
+                                  0, 5, &periph_l_regs,
+                                  periph_clk_enb_refcnt);
+        clk_register_clkdev(clk, NULL, "timer");
+        clks[timer] = clk;
+
+        /* kfuse */
+        clk = tegra_clk_register_periph_gate("kfuse", "clk_m",
+                                  TEGRA_PERIPH_ON_APB, clk_base,  0, 40,
+                                  &periph_h_regs, periph_clk_enb_refcnt);
+        clks[kfuse] = clk;
+
+        /* fuse */
+        clk = tegra_clk_register_periph_gate("fuse", "clk_m",
+                                  TEGRA_PERIPH_ON_APB, clk_base,  0, 39,
+                                  &periph_h_regs, periph_clk_enb_refcnt);
+        clks[fuse] = clk;
+
+        /* fuse_burn */
+        clk = tegra_clk_register_periph_gate("fuse_burn", "clk_m",
+                                  TEGRA_PERIPH_ON_APB, clk_base,  0, 39,
+                                  &periph_h_regs, periph_clk_enb_refcnt);
+        clks[fuse_burn] = clk;
+
+        /* apbif */
+        clk = tegra_clk_register_periph_gate("apbif", "clk_m",
+                                  TEGRA_PERIPH_ON_APB, clk_base,  0, 107,
+                                  &periph_v_regs, periph_clk_enb_refcnt);
+        clks[apbif] = clk;
+
+        /* hda2hdmi */
+        clk = tegra_clk_register_periph_gate("hda2hdmi", "clk_m",
+                                    TEGRA_PERIPH_ON_APB, clk_base,  0, 128,
+                                    &periph_w_regs, periph_clk_enb_refcnt);
+        clks[hda2hdmi] = clk;
+
+        /* vcp */
+        clk = tegra_clk_register_periph_gate("vcp", "clk_m", 0, clk_base,  0,
+                                  29, &periph_l_regs,
+                                  periph_clk_enb_refcnt);
+        clks[vcp] = clk;
+
+        /* bsea */
+        clk = tegra_clk_register_periph_gate("bsea", "clk_m", 0, clk_base,
+                                  0, 62, &periph_h_regs,
+                                  periph_clk_enb_refcnt);
+        clks[bsea] = clk;
+
+        /* bsev */
+        clk = tegra_clk_register_periph_gate("bsev", "clk_m", 0, clk_base,
+                                  0, 63, &periph_h_regs,
+                                  periph_clk_enb_refcnt);
+        clks[bsev] = clk;
+
+        /* mipi-cal */
+        clk = tegra_clk_register_periph_gate("mipi-cal", "clk_m", 0, clk_base,
+                                   0, 56, &periph_h_regs,
+                                  periph_clk_enb_refcnt);
+        clks[mipi_cal] = clk;
+
+        /* usbd */
+        clk = tegra_clk_register_periph_gate("usbd", "clk_m", 0, clk_base,
+                                  0, 22, &periph_l_regs,
+                                  periph_clk_enb_refcnt);
+        clks[usbd] = clk;
+
+        /* usb2 */
+        clk = tegra_clk_register_periph_gate("usb2", "clk_m", 0, clk_base,
+                                  0, 58, &periph_h_regs,
+                                  periph_clk_enb_refcnt);
+        clks[usb2] = clk;
+
+        /* usb3 */
+        clk = tegra_clk_register_periph_gate("usb3", "clk_m", 0, clk_base,
+                                  0, 59, &periph_h_regs,
+                                  periph_clk_enb_refcnt);
+        clks[usb3] = clk;
+
+        /* csi */
+        clk = tegra_clk_register_periph_gate("csi", "pll_p_out3", 0, clk_base,
+                                   0, 52, &periph_h_regs,
+                                  periph_clk_enb_refcnt);
+        clks[csi] = clk;
+
+        /* isp */
+        clk = tegra_clk_register_periph_gate("isp", "clk_m", 0, clk_base, 0,
+                                  23, &periph_l_regs,
+                                  periph_clk_enb_refcnt);
+        clks[isp] = clk;
+
+        /* csus */
+        clk = tegra_clk_register_periph_gate("csus", "clk_m",
+                                  TEGRA_PERIPH_NO_RESET, clk_base, 0, 92,
+                                  &periph_u_regs, periph_clk_enb_refcnt);
+        clks[csus] = clk;
+
+        /* dds */
+        clk = tegra_clk_register_periph_gate("dds", "clk_m",
+                                  TEGRA_PERIPH_ON_APB, clk_base, 0, 150,
+                                  &periph_w_regs, periph_clk_enb_refcnt);
+        clks[dds] = clk;
+
+        /* dp2 */
+        clk = tegra_clk_register_periph_gate("dp2", "clk_m",
+                                  TEGRA_PERIPH_ON_APB, clk_base, 0, 152,
+                                  &periph_w_regs, periph_clk_enb_refcnt);
+        clks[dp2] = clk;
+
+        /* dtv */
+        clk = tegra_clk_register_periph_gate("dtv", "clk_m",
+                                    TEGRA_PERIPH_ON_APB, clk_base, 0, 79,
+                                    &periph_u_regs, periph_clk_enb_refcnt);
+        clks[dtv] = clk;
+
+        /* dsia */
+        clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0,
+                               ARRAY_SIZE(mux_plld_out0_plld2_out0), 0,
+                               clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock);
+        clks[dsia_mux] = clk;
+        clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base,
+                                    0, 48, &periph_h_regs,
+                                    periph_clk_enb_refcnt);
+        clks[dsia] = clk;
+
+        /* dsib */
+        clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0,
+                               ARRAY_SIZE(mux_plld_out0_plld2_out0), 0,
+                               clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock);
+        clks[dsib_mux] = clk;
+        clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base,
+                                    0, 82, &periph_u_regs,
+                                    periph_clk_enb_refcnt);
+        clks[dsib] = clk;
+
+        /* xusb_hs_src */
+        val = readl(clk_base + CLK_SOURCE_XUSB_SS_SRC);
+        val |= BIT(25); /* always select PLLU_60M */
+        writel(val, clk_base + CLK_SOURCE_XUSB_SS_SRC);
+
+        clk = clk_register_fixed_factor(NULL, "xusb_hs_src", "pll_u_60M", 0,
+                                        1, 1);
+        clks[xusb_hs_src] = clk;
+
+        /* xusb_host */
+        clk = tegra_clk_register_periph_gate("xusb_host", "xusb_host_src", 0,
+                                    clk_base, 0, 89, &periph_u_regs,
+                                    periph_clk_enb_refcnt);
+        clks[xusb_host] = clk;
+
+        /* xusb_ss */
+        clk = tegra_clk_register_periph_gate("xusb_ss", "xusb_ss_src", 0,
+                                    clk_base, 0, 156, &periph_w_regs,
+                                    periph_clk_enb_refcnt);
+        clks[xusb_host] = clk;
+
+        /* xusb_dev */
+        clk = tegra_clk_register_periph_gate("xusb_dev", "xusb_dev_src", 0,
+                                    clk_base, 0, 95, &periph_u_regs,
+                                    periph_clk_enb_refcnt);
+        clks[xusb_dev] = clk;
+
+        /* emc */
+        clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
+                               ARRAY_SIZE(mux_pllmcp_clkm), 0,
+                               clk_base + CLK_SOURCE_EMC,
+                               29, 3, 0, NULL);
+        clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base,
+                                CLK_IGNORE_UNUSED, 57, &periph_h_regs,
+                                periph_clk_enb_refcnt);
+        clks[emc] = clk;
+
+        for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
+                data = &tegra_periph_clk_list[i];
+                clk = tegra_clk_register_periph(data->name, data->parent_names,
+                                data->num_parents, &data->periph,
+                                clk_base, data->offset, data->flags);
+                clks[data->clk_id] = clk;
+        }
+
+        for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) {
+                data = &tegra_periph_nodiv_clk_list[i];
+                clk = tegra_clk_register_periph_nodiv(data->name,
+                                data->parent_names, data->num_parents,
+                                &data->periph, clk_base, data->offset);
+                clks[data->clk_id] = clk;
+        }
+}
+
+static struct tegra_cpu_car_ops tegra114_cpu_car_ops;
+
+static const struct of_device_id pmc_match[] __initconst = {
+        { .compatible = "nvidia,tegra114-pmc" },
+        {},
+};
+
+static __initdata struct tegra_clk_init_table init_table[] = {
+        {uarta, pll_p, 408000000, 0},
+        {uartb, pll_p, 408000000, 0},
+        {uartc, pll_p, 408000000, 0},
+        {uartd, pll_p, 408000000, 0},
+        {pll_a, clk_max, 564480000, 1},
+        {pll_a_out0, clk_max, 11289600, 1},
+        {extern1, pll_a_out0, 0, 1},
+        {clk_out_1_mux, extern1, 0, 1},
+        {clk_out_1, clk_max, 0, 1},
+        {i2s0, pll_a_out0, 11289600, 0},
+        {i2s1, pll_a_out0, 11289600, 0},
+        {i2s2, pll_a_out0, 11289600, 0},
+        {i2s3, pll_a_out0, 11289600, 0},
+        {i2s4, pll_a_out0, 11289600, 0},
+        {clk_max, clk_max, 0, 0}, /* This MUST be the last entry. */
+};
+
+static void __init tegra114_clock_apply_init_table(void)
+{
+        tegra_init_from_table(init_table, clks, clk_max);
+}
+
+void __init tegra114_clock_init(struct device_node *np)
+{
+        struct device_node *node;
+        int i;
+
+        clk_base = of_iomap(np, 0);
+        if (!clk_base) {
+                pr_err("ioremap tegra114 CAR failed\n");
+                return;
+        }
+
+        node = of_find_matching_node(NULL, pmc_match);
+        if (!node) {
+                pr_err("Failed to find pmc node\n");
+                WARN_ON(1);
+                return;
+        }
+
+        pmc_base = of_iomap(node, 0);
+        if (!pmc_base) {
+                pr_err("Can't map pmc registers\n");
+                WARN_ON(1);
+                return;
+        }
+
+        if (tegra114_osc_clk_init(clk_base) < 0)
+                return;
+
+        tegra114_fixed_clk_init(clk_base);
+        tegra114_pll_init(clk_base, pmc_base);
+        tegra114_periph_clk_init(clk_base);
+        tegra114_audio_clk_init(clk_base);
+        tegra114_pmc_clk_init(pmc_base);
+        tegra114_super_clk_init(clk_base);
+
+        for (i = 0; i < ARRAY_SIZE(clks); i++) {
+                if (IS_ERR(clks[i])) {
+                        pr_err
+                            ("Tegra114 clk %d: register failed with %ld\n",
+                             i, PTR_ERR(clks[i]));
+                }
+                if (!clks[i])
+                        clks[i] = ERR_PTR(-EINVAL);
+        }
+
+        clk_data.clks = clks;
+        clk_data.clk_num = ARRAY_SIZE(clks);
+        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+
+        tegra_clk_apply_init_table = tegra114_clock_apply_init_table;
+
+        tegra_cpu_car_ops = &tegra114_cpu_car_ops;
+}
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 1e2de7305362..8292a00c3de9 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -86,8 +86,8 @@
 #define PLLE_BASE 0xe8
 #define PLLE_MISC 0xec
 
-#define PLL_BASE_LOCK 27
-#define PLLE_MISC_LOCK 11
+#define PLL_BASE_LOCK BIT(27)
+#define PLLE_MISC_LOCK BIT(11)
 
 #define PLL_MISC_LOCK_ENABLE 18
 #define PLLDU_MISC_LOCK_ENABLE 22
@@ -236,7 +236,7 @@ enum tegra20_clk {
         dvc, dsi, mipi = 50, hdmi, csi, tvdac, i2c2, uartc, emc = 57, usb2,
         usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3,
         pex, owr, afi, csite, pcie_xclk, avpucq = 75, la, irama = 84, iramb,
-        iramc, iramd, cram2, audio_2x, clk_d, csus = 92, cdev1, cdev2,
+        iramc, iramd, cram2, audio_2x, clk_d, csus = 92, cdev2, cdev1,
         uartb = 96, vfir, spdif_in, spdif_out, vi, vi_sensor, tvo, cve,
         osc, clk_32k, clk_m, sclk, cclk, hclk, pclk, blink, pll_a, pll_a_out0,
         pll_c, pll_c_out1, pll_d, pll_d_out0, pll_e, pll_m, pll_m_out1,
@@ -248,125 +248,125 @@ static struct clk *clks[clk_max];
 static struct clk_onecell_data clk_data;
 
 static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
-        { 12000000, 600000000, 600, 12, 1, 8 },
-        { 13000000, 600000000, 600, 13, 1, 8 },
-        { 19200000, 600000000, 500, 16, 1, 6 },
-        { 26000000, 600000000, 600, 26, 1, 8 },
+        { 12000000, 600000000, 600, 12, 0, 8 },
+        { 13000000, 600000000, 600, 13, 0, 8 },
+        { 19200000, 600000000, 500, 16, 0, 6 },
+        { 26000000, 600000000, 600, 26, 0, 8 },
         { 0, 0, 0, 0, 0, 0 },
 };
 
 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
-        { 12000000, 666000000, 666, 12, 1, 8},
-        { 13000000, 666000000, 666, 13, 1, 8},
-        { 19200000, 666000000, 555, 16, 1, 8},
-        { 26000000, 666000000, 666, 26, 1, 8},
-        { 12000000, 600000000, 600, 12, 1, 8},
-        { 13000000, 600000000, 600, 13, 1, 8},
-        { 19200000, 600000000, 375, 12, 1, 6},
-        { 26000000, 600000000, 600, 26, 1, 8},
+        { 12000000, 666000000, 666, 12, 0, 8},
+        { 13000000, 666000000, 666, 13, 0, 8},
+        { 19200000, 666000000, 555, 16, 0, 8},
+        { 26000000, 666000000, 666, 26, 0, 8},
+        { 12000000, 600000000, 600, 12, 0, 8},
+        { 13000000, 600000000, 600, 13, 0, 8},
+        { 19200000, 600000000, 375, 12, 0, 6},
+        { 26000000, 600000000, 600, 26, 0, 8},
         { 0, 0, 0, 0, 0, 0 },
 };
 
 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
-        { 12000000, 216000000, 432, 12, 2, 8},
-        { 13000000, 216000000, 432, 13, 2, 8},
-        { 19200000, 216000000, 90,   4, 2, 1},
-        { 26000000, 216000000, 432, 26, 2, 8},
-        { 12000000, 432000000, 432, 12, 1, 8},
-        { 13000000, 432000000, 432, 13, 1, 8},
-        { 19200000, 432000000, 90,   4, 1, 1},
-        { 26000000, 432000000, 432, 26, 1, 8},
+        { 12000000, 216000000, 432, 12, 1, 8},
+        { 13000000, 216000000, 432, 13, 1, 8},
+        { 19200000, 216000000, 90,   4, 1, 1},
+        { 26000000, 216000000, 432, 26, 1, 8},
+        { 12000000, 432000000, 432, 12, 0, 8},
+        { 13000000, 432000000, 432, 13, 0, 8},
+        { 19200000, 432000000, 90,   4, 0, 1},
+        { 26000000, 432000000, 432, 26, 0, 8},
         { 0, 0, 0, 0, 0, 0 },
 };
 
 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
-        { 28800000, 56448000, 49, 25, 1, 1},
-        { 28800000, 73728000, 64, 25, 1, 1},
-        { 28800000, 24000000,  5,  6, 1, 1},
+        { 28800000, 56448000, 49, 25, 0, 1},
+        { 28800000, 73728000, 64, 25, 0, 1},
+        { 28800000, 24000000,  5,  6, 0, 1},
         { 0, 0, 0, 0, 0, 0 },
 };
 
 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
-        { 12000000, 216000000, 216, 12, 1, 4},
-        { 13000000, 216000000, 216, 13, 1, 4},
-        { 19200000, 216000000, 135, 12, 1, 3},
-        { 26000000, 216000000, 216, 26, 1, 4},
+        { 12000000, 216000000, 216, 12, 0, 4},
+        { 13000000, 216000000, 216, 13, 0, 4},
+        { 19200000, 216000000, 135, 12, 0, 3},
+        { 26000000, 216000000, 216, 26, 0, 4},
 
-        { 12000000, 594000000, 594, 12, 1, 8},
-        { 13000000, 594000000, 594, 13, 1, 8},
-        { 19200000, 594000000, 495, 16, 1, 8},
-        { 26000000, 594000000, 594, 26, 1, 8},
+        { 12000000, 594000000, 594, 12, 0, 8},
+        { 13000000, 594000000, 594, 13, 0, 8},
+        { 19200000, 594000000, 495, 16, 0, 8},
+        { 26000000, 594000000, 594, 26, 0, 8},
 
-        { 12000000, 1000000000, 1000, 12, 1, 12},
-        { 13000000, 1000000000, 1000, 13, 1, 12},
-        { 19200000, 1000000000, 625,  12, 1, 8},
-        { 26000000, 1000000000, 1000, 26, 1, 12},
+        { 12000000, 1000000000, 1000, 12, 0, 12},
+        { 13000000, 1000000000, 1000, 13, 0, 12},
+        { 19200000, 1000000000, 625,  12, 0, 8},
+        { 26000000, 1000000000, 1000, 26, 0, 12},
 
         { 0, 0, 0, 0, 0, 0 },
 };
 
 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
-        { 12000000, 480000000, 960, 12, 2, 0},
-        { 13000000, 480000000, 960, 13, 2, 0},
-        { 19200000, 480000000, 200, 4,  2, 0},
-        { 26000000, 480000000, 960, 26, 2, 0},
+        { 12000000, 480000000, 960, 12, 0, 0},
+        { 13000000, 480000000, 960, 13, 0, 0},
+        { 19200000, 480000000, 200, 4,  0, 0},
+        { 26000000, 480000000, 960, 26, 0, 0},
         { 0, 0, 0, 0, 0, 0 },
 };
 
 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
         /* 1 GHz */
-        { 12000000, 1000000000, 1000, 12, 1, 12},
-        { 13000000, 1000000000, 1000, 13, 1, 12},
-        { 19200000, 1000000000, 625,  12, 1, 8},
-        { 26000000, 1000000000, 1000, 26, 1, 12},
+        { 12000000, 1000000000, 1000, 12, 0, 12},
+        { 13000000, 1000000000, 1000, 13, 0, 12},
+        { 19200000, 1000000000, 625,  12, 0, 8},
+        { 26000000, 1000000000, 1000, 26, 0, 12},
 
         /* 912 MHz */
-        { 12000000, 912000000,  912,  12, 1, 12},
-        { 13000000, 912000000,  912,  13, 1, 12},
-        { 19200000, 912000000,  760,  16, 1, 8},
-        { 26000000, 912000000,  912,  26, 1, 12},
+        { 12000000, 912000000,  912,  12, 0, 12},
+        { 13000000, 912000000,  912,  13, 0, 12},
+        { 19200000, 912000000,  760,  16, 0, 8},
+        { 26000000, 912000000,  912,  26, 0, 12},
 
         /* 816 MHz */
-        { 12000000, 816000000,  816,  12, 1, 12},
-        { 13000000, 816000000,  816,  13, 1, 12},
-        { 19200000, 816000000,  680,  16, 1, 8},
-        { 26000000, 816000000,  816,  26, 1, 12},
+        { 12000000, 816000000,  816,  12, 0, 12},
+        { 13000000, 816000000,  816,  13, 0, 12},
+        { 19200000, 816000000,  680,  16, 0, 8},
+        { 26000000, 816000000,  816,  26, 0, 12},
 
         /* 760 MHz */
-        { 12000000, 760000000,  760,  12, 1, 12},
-        { 13000000, 760000000,  760,  13, 1, 12},
-        { 19200000, 760000000,  950,  24, 1, 8},
-        { 26000000, 760000000,  760,  26, 1, 12},
+        { 12000000, 760000000,  760,  12, 0, 12},
+        { 13000000, 760000000,  760,  13, 0, 12},
+        { 19200000, 760000000,  950,  24, 0, 8},
+        { 26000000, 760000000,  760,  26, 0, 12},
 
         /* 750 MHz */
-        { 12000000, 750000000,  750,  12, 1, 12},
-        { 13000000, 750000000,  750,  13, 1, 12},
-        { 19200000, 750000000,  625,  16, 1, 8},
-        { 26000000, 750000000,  750,  26, 1, 12},
+        { 12000000, 750000000,  750,  12, 0, 12},
+        { 13000000, 750000000,  750,  13, 0, 12},
+        { 19200000, 750000000,  625,  16, 0, 8},
+        { 26000000, 750000000,  750,  26, 0, 12},
 
         /* 608 MHz */
-        { 12000000, 608000000,  608,  12, 1, 12},
-        { 13000000, 608000000,  608,  13, 1, 12},
-        { 19200000, 608000000,  380,  12, 1, 8},
-        { 26000000, 608000000,  608,  26, 1, 12},
+        { 12000000, 608000000,  608,  12, 0, 12},
+        { 13000000, 608000000,  608,  13, 0, 12},
+        { 19200000, 608000000,  380,  12, 0, 8},
+        { 26000000, 608000000,  608,  26, 0, 12},
 
         /* 456 MHz */
-        { 12000000, 456000000,  456,  12, 1, 12},
-        { 13000000, 456000000,  456,  13, 1, 12},
-        { 19200000, 456000000,  380,  16, 1, 8},
-        { 26000000, 456000000,  456,  26, 1, 12},
+        { 12000000, 456000000,  456,  12, 0, 12},
+        { 13000000, 456000000,  456,  13, 0, 12},
+        { 19200000, 456000000,  380,  16, 0, 8},
+        { 26000000, 456000000,  456,  26, 0, 12},
 
         /* 312 MHz */
-        { 12000000, 312000000,  312,  12, 1, 12},
-        { 13000000, 312000000,  312,  13, 1, 12},
-        { 19200000, 312000000,  260,  16, 1, 8},
-        { 26000000, 312000000,  312,  26, 1, 12},
+        { 12000000, 312000000,  312,  12, 0, 12},
+        { 13000000, 312000000,  312,  13, 0, 12},
+        { 19200000, 312000000,  260,  16, 0, 8},
+        { 26000000, 312000000,  312,  26, 0, 12},
 
         { 0, 0, 0, 0, 0, 0 },
 };
 
 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
-        { 12000000, 100000000,  200,  24, 1, 0 },
+        { 12000000, 100000000,  200,  24, 0, 0 },
         { 0, 0, 0, 0, 0, 0 },
 };
 
@@ -380,7 +380,7 @@ static struct tegra_clk_pll_params pll_c_params = {
         .vco_max = 1400000000,
         .base_reg = PLLC_BASE,
         .misc_reg = PLLC_MISC,
-        .lock_bit_idx = PLL_BASE_LOCK,
+        .lock_mask = PLL_BASE_LOCK,
         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
         .lock_delay = 300,
 };
@@ -394,7 +394,7 @@ static struct tegra_clk_pll_params pll_m_params = {
         .vco_max = 1200000000,
         .base_reg = PLLM_BASE,
         .misc_reg = PLLM_MISC,
-        .lock_bit_idx = PLL_BASE_LOCK,
+        .lock_mask = PLL_BASE_LOCK,
         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
         .lock_delay = 300,
 };
@@ -408,7 +408,7 @@ static struct tegra_clk_pll_params pll_p_params = {
         .vco_max = 1400000000,
         .base_reg = PLLP_BASE,
         .misc_reg = PLLP_MISC,
-        .lock_bit_idx = PLL_BASE_LOCK,
+        .lock_mask = PLL_BASE_LOCK,
         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
         .lock_delay = 300,
 };
@@ -422,7 +422,7 @@ static struct tegra_clk_pll_params pll_a_params = {
         .vco_max = 1400000000,
         .base_reg = PLLA_BASE,
         .misc_reg = PLLA_MISC,
-        .lock_bit_idx = PLL_BASE_LOCK,
+        .lock_mask = PLL_BASE_LOCK,
         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
         .lock_delay = 300,
 };
@@ -436,11 +436,17 @@ static struct tegra_clk_pll_params pll_d_params = {
         .vco_max = 1000000000,
         .base_reg = PLLD_BASE,
         .misc_reg = PLLD_MISC,
-        .lock_bit_idx = PLL_BASE_LOCK,
+        .lock_mask = PLL_BASE_LOCK,
         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
         .lock_delay = 1000,
 };
 
+static struct pdiv_map pllu_p[] = {
+        { .pdiv = 1, .hw_val = 1 },
+        { .pdiv = 2, .hw_val = 0 },
+        { .pdiv = 0, .hw_val = 0 },
+};
+
 static struct tegra_clk_pll_params pll_u_params = {
         .input_min = 2000000,
         .input_max = 40000000,
@@ -450,9 +456,10 @@ static struct tegra_clk_pll_params pll_u_params = {
         .vco_max = 960000000,
         .base_reg = PLLU_BASE,
         .misc_reg = PLLU_MISC,
-        .lock_bit_idx = PLL_BASE_LOCK,
+        .lock_mask = PLL_BASE_LOCK,
         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
         .lock_delay = 1000,
+        .pdiv_tohw = pllu_p,
 };
 
 static struct tegra_clk_pll_params pll_x_params = {
@@ -464,7 +471,7 @@ static struct tegra_clk_pll_params pll_x_params = {
         .vco_max = 1200000000,
         .base_reg = PLLX_BASE,
         .misc_reg = PLLX_MISC,
-        .lock_bit_idx = PLL_BASE_LOCK,
+        .lock_mask = PLL_BASE_LOCK,
         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
         .lock_delay = 300,
 };
@@ -478,7 +485,7 @@ static struct tegra_clk_pll_params pll_e_params = {
         .vco_max = 0,
         .base_reg = PLLE_BASE,
         .misc_reg = PLLE_MISC,
-        .lock_bit_idx = PLLE_MISC_LOCK,
+        .lock_mask = PLLE_MISC_LOCK,
         .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
         .lock_delay = 0,
 };
@@ -703,7 +710,7 @@ static void tegra20_pll_init(void)
         clks[pll_a_out0] = clk;
 
         /* PLLE */
-        clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, NULL,
+        clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base,
                              0, 100000000, &pll_e_params,
                              0, pll_e_freq_table, NULL);
         clk_register_clkdev(clk, "pll_e", NULL);
@@ -711,8 +718,8 @@ static void tegra20_pll_init(void)
 }
 
 static const char *cclk_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
-                                      "pll_p_cclk", "pll_p_out4_cclk",
-                                      "pll_p_out3_cclk", "clk_d", "pll_x" };
+                                      "pll_p", "pll_p_out4",
+                                      "pll_p_out3", "clk_d", "pll_x" };
 static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
                                       "pll_p_out3", "pll_p_out2", "clk_d",
                                       "clk_32k", "pll_m_out1" };
@@ -721,38 +728,6 @@ static void tegra20_super_clk_init(void)
 {
         struct clk *clk;
 
-        /*
-         * DIV_U71 dividers for CCLK, these dividers are used only
-         * if parent clock is fixed rate.
-         */
-
-        /*
-         * Clock input to cclk divided from pll_p using
-         * U71 divider of cclk.
-         */
-        clk = tegra_clk_register_divider("pll_p_cclk", "pll_p",
-                                clk_base + SUPER_CCLK_DIVIDER, 0,
-                                TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
-        clk_register_clkdev(clk, "pll_p_cclk", NULL);
-
-        /*
-         * Clock input to cclk divided from pll_p_out3 using
-         * U71 divider of cclk.
-         */
-        clk = tegra_clk_register_divider("pll_p_out3_cclk", "pll_p_out3",
-                                clk_base + SUPER_CCLK_DIVIDER, 0,
-                                TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
-        clk_register_clkdev(clk, "pll_p_out3_cclk", NULL);
-
-        /*
-         * Clock input to cclk divided from pll_p_out4 using
-         * U71 divider of cclk.
-         */
-        clk = tegra_clk_register_divider("pll_p_out4_cclk", "pll_p_out4",
-                                clk_base + SUPER_CCLK_DIVIDER, 0,
-                                TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
-        clk_register_clkdev(clk, "pll_p_out4_cclk", NULL);
-
         /* CCLK */
         clk = tegra_clk_register_super_mux("cclk", cclk_parents,
                               ARRAY_SIZE(cclk_parents), CLK_SET_RATE_PARENT,
@@ -1044,7 +1019,7 @@ static void __init tegra20_periph_clk_init(void)
                 data = &tegra_periph_clk_list[i];
                 clk = tegra_clk_register_periph(data->name, data->parent_names,
                                 data->num_parents, &data->periph,
-                                clk_base, data->offset);
+                                clk_base, data->offset, data->flags);
                 clk_register_clkdev(clk, data->con_id, data->dev_id);
                 clks[data->clk_id] = clk;
         }
@@ -1279,9 +1254,16 @@ static __initdata struct tegra_clk_init_table init_table[] = {
         {host1x, pll_c, 150000000, 0},
         {disp1, pll_p, 600000000, 0},
         {disp2, pll_p, 600000000, 0},
+        {gr2d, pll_c, 300000000, 0},
+        {gr3d, pll_c, 300000000, 0},
         {clk_max, clk_max, 0, 0}, /* This MUST be the last entry */
 };
 
+static void __init tegra20_clock_apply_init_table(void)
+{
+        tegra_init_from_table(init_table, clks, clk_max);
+}
+
 /*
  * Some clocks may be used by different drivers depending on the board
  * configuration.  List those here to register them twice in the clock lookup
@@ -1348,7 +1330,7 @@ void __init tegra20_clock_init(struct device_node *np)
         clk_data.clk_num = ARRAY_SIZE(clks);
         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 
-        tegra_init_from_table(init_table, clks, clk_max);
+        tegra_clk_apply_init_table = tegra20_clock_apply_init_table;
 
         tegra_cpu_car_ops = &tegra20_cpu_car_ops;
 }
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index ba6f51bc9f3b..2dc0c5602613 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -116,8 +116,8 @@
 #define PLLDU_MISC_LOCK_ENABLE 22
 #define PLLE_MISC_LOCK_ENABLE 9
 
-#define PLL_BASE_LOCK 27
-#define PLLE_MISC_LOCK 11
+#define PLL_BASE_LOCK BIT(27)
+#define PLLE_MISC_LOCK BIT(11)
 
 #define PLLE_AUX 0x48c
 #define PLLC_OUT 0x84
@@ -330,7 +330,7 @@ enum tegra30_clk {
         usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3,
         pcie, owr, afi, csite, pciex, avpucq, la, dtv = 79, ndspeed, i2cslow,
         dsib, irama = 84, iramb, iramc, iramd, cram2, audio_2x = 90, csus = 92,
-        cdev1, cdev2, cpu_g = 96, cpu_lp, gr3d2, mselect, tsensor, i2s3, i2s4,
+        cdev2, cdev1, cpu_g = 96, cpu_lp, gr3d2, mselect, tsensor, i2s3, i2s4,
         i2c4, sbc5, sbc6, d_audio, apbif, dam0, dam1, dam2, hda2codec_2x,
         atomics, audio0_2x, audio1_2x, audio2_2x, audio3_2x, audio4_2x,
         spdif_2x, actmon, extern1, extern2, extern3, sata_oob, sata, hda,
@@ -374,164 +374,170 @@ static const struct utmi_clk_param utmi_parameters[] = {
 };
 
 static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
-        { 12000000, 1040000000, 520,  6, 1, 8},
-        { 13000000, 1040000000, 480,  6, 1, 8},
-        { 16800000, 1040000000, 495,  8, 1, 8}, /* actual: 1039.5 MHz */
-        { 19200000, 1040000000, 325,  6, 1, 6},
-        { 26000000, 1040000000, 520, 13, 1, 8},
-
-        { 12000000, 832000000, 416,  6, 1, 8},
-        { 13000000, 832000000, 832, 13, 1, 8},
-        { 16800000, 832000000, 396,  8, 1, 8},  /* actual: 831.6 MHz */
-        { 19200000, 832000000, 260,  6, 1, 8},
-        { 26000000, 832000000, 416, 13, 1, 8},
-
-        { 12000000, 624000000, 624, 12, 1, 8},
-        { 13000000, 624000000, 624, 13, 1, 8},
-        { 16800000, 600000000, 520, 14, 1, 8},
-        { 19200000, 624000000, 520, 16, 1, 8},
-        { 26000000, 624000000, 624, 26, 1, 8},
-
-        { 12000000, 600000000, 600, 12, 1, 8},
-        { 13000000, 600000000, 600, 13, 1, 8},
-        { 16800000, 600000000, 500, 14, 1, 8},
-        { 19200000, 600000000, 375, 12, 1, 6},
-        { 26000000, 600000000, 600, 26, 1, 8},
-
-        { 12000000, 520000000, 520, 12, 1, 8},
-        { 13000000, 520000000, 520, 13, 1, 8},
-        { 16800000, 520000000, 495, 16, 1, 8},  /* actual: 519.75 MHz */
-        { 19200000, 520000000, 325, 12, 1, 6},
-        { 26000000, 520000000, 520, 26, 1, 8},
-
-        { 12000000, 416000000, 416, 12, 1, 8},
-        { 13000000, 416000000, 416, 13, 1, 8},
-        { 16800000, 416000000, 396, 16, 1, 8},  /* actual: 415.8 MHz */
-        { 19200000, 416000000, 260, 12, 1, 6},
-        { 26000000, 416000000, 416, 26, 1, 8},
+        { 12000000, 1040000000, 520,  6, 0, 8},
+        { 13000000, 1040000000, 480,  6, 0, 8},
+        { 16800000, 1040000000, 495,  8, 0, 8}, /* actual: 1039.5 MHz */
+        { 19200000, 1040000000, 325,  6, 0, 6},
+        { 26000000, 1040000000, 520, 13, 0, 8},
+
+        { 12000000, 832000000, 416,  6, 0, 8},
+        { 13000000, 832000000, 832, 13, 0, 8},
+        { 16800000, 832000000, 396,  8, 0, 8},  /* actual: 831.6 MHz */
+        { 19200000, 832000000, 260,  6, 0, 8},
+        { 26000000, 832000000, 416, 13, 0, 8},
+
+        { 12000000, 624000000, 624, 12, 0, 8},
+        { 13000000, 624000000, 624, 13, 0, 8},
+        { 16800000, 600000000, 520, 14, 0, 8},
+        { 19200000, 624000000, 520, 16, 0, 8},
+        { 26000000, 624000000, 624, 26, 0, 8},
+
+        { 12000000, 600000000, 600, 12, 0, 8},
+        { 13000000, 600000000, 600, 13, 0, 8},
+        { 16800000, 600000000, 500, 14, 0, 8},
+        { 19200000, 600000000, 375, 12, 0, 6},
+        { 26000000, 600000000, 600, 26, 0, 8},
+
+        { 12000000, 520000000, 520, 12, 0, 8},
+        { 13000000, 520000000, 520, 13, 0, 8},
+        { 16800000, 520000000, 495, 16, 0, 8},  /* actual: 519.75 MHz */
+        { 19200000, 520000000, 325, 12, 0, 6},
+        { 26000000, 520000000, 520, 26, 0, 8},
+
+        { 12000000, 416000000, 416, 12, 0, 8},
+        { 13000000, 416000000, 416, 13, 0, 8},
+        { 16800000, 416000000, 396, 16, 0, 8},  /* actual: 415.8 MHz */
+        { 19200000, 416000000, 260, 12, 0, 6},
+        { 26000000, 416000000, 416, 26, 0, 8},
         { 0, 0, 0, 0, 0, 0 },
 };
 
 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
-        { 12000000, 666000000, 666, 12, 1, 8},
-        { 13000000, 666000000, 666, 13, 1, 8},
-        { 16800000, 666000000, 555, 14, 1, 8},
-        { 19200000, 666000000, 555, 16, 1, 8},
-        { 26000000, 666000000, 666, 26, 1, 8},
-        { 12000000, 600000000, 600, 12, 1, 8},
-        { 13000000, 600000000, 600, 13, 1, 8},
-        { 16800000, 600000000, 500, 14, 1, 8},
-        { 19200000, 600000000, 375, 12, 1, 6},
-        { 26000000, 600000000, 600, 26, 1, 8},
+        { 12000000, 666000000, 666, 12, 0, 8},
+        { 13000000, 666000000, 666, 13, 0, 8},
+        { 16800000, 666000000, 555, 14, 0, 8},
+        { 19200000, 666000000, 555, 16, 0, 8},
+        { 26000000, 666000000, 666, 26, 0, 8},
+        { 12000000, 600000000, 600, 12, 0, 8},
+        { 13000000, 600000000, 600, 13, 0, 8},
+        { 16800000, 600000000, 500, 14, 0, 8},
+        { 19200000, 600000000, 375, 12, 0, 6},
+        { 26000000, 600000000, 600, 26, 0, 8},
         { 0, 0, 0, 0, 0, 0 },
 };
 
 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
-        { 12000000, 216000000, 432, 12, 2, 8},
-        { 13000000, 216000000, 432, 13, 2, 8},
-        { 16800000, 216000000, 360, 14, 2, 8},
-        { 19200000, 216000000, 360, 16, 2, 8},
-        { 26000000, 216000000, 432, 26, 2, 8},
+        { 12000000, 216000000, 432, 12, 1, 8},
+        { 13000000, 216000000, 432, 13, 1, 8},
+        { 16800000, 216000000, 360, 14, 1, 8},
+        { 19200000, 216000000, 360, 16, 1, 8},
+        { 26000000, 216000000, 432, 26, 1, 8},
         { 0, 0, 0, 0, 0, 0 },
 };
 
 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
-        { 9600000, 564480000, 294, 5, 1, 4},
-        { 9600000, 552960000, 288, 5, 1, 4},
-        { 9600000, 24000000,  5,   2, 1, 1},
+        { 9600000, 564480000, 294, 5, 0, 4},
+        { 9600000, 552960000, 288, 5, 0, 4},
+        { 9600000, 24000000,  5,   2, 0, 1},
 
-        { 28800000, 56448000, 49, 25, 1, 1},
-        { 28800000, 73728000, 64, 25, 1, 1},
-        { 28800000, 24000000,  5,  6, 1, 1},
+        { 28800000, 56448000, 49, 25, 0, 1},
+        { 28800000, 73728000, 64, 25, 0, 1},
+        { 28800000, 24000000,  5,  6, 0, 1},
         { 0, 0, 0, 0, 0, 0 },
 };
 
 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
-        { 12000000, 216000000, 216, 12, 1, 4},
-        { 13000000, 216000000, 216, 13, 1, 4},
-        { 16800000, 216000000, 180, 14, 1, 4},
-        { 19200000, 216000000, 180, 16, 1, 4},
-        { 26000000, 216000000, 216, 26, 1, 4},
-
-        { 12000000, 594000000, 594, 12, 1, 8},
-        { 13000000, 594000000, 594, 13, 1, 8},
-        { 16800000, 594000000, 495, 14, 1, 8},
-        { 19200000, 594000000, 495, 16, 1, 8},
-        { 26000000, 594000000, 594, 26, 1, 8},
-
-        { 12000000, 1000000000, 1000, 12, 1, 12},
-        { 13000000, 1000000000, 1000, 13, 1, 12},
-        { 19200000, 1000000000, 625,  12, 1, 8},
-        { 26000000, 1000000000, 1000, 26, 1, 12},
+        { 12000000, 216000000, 216, 12, 0, 4},
+        { 13000000, 216000000, 216, 13, 0, 4},
+        { 16800000, 216000000, 180, 14, 0, 4},
+        { 19200000, 216000000, 180, 16, 0, 4},
+        { 26000000, 216000000, 216, 26, 0, 4},
+
+        { 12000000, 594000000, 594, 12, 0, 8},
+        { 13000000, 594000000, 594, 13, 0, 8},
+        { 16800000, 594000000, 495, 14, 0, 8},
+        { 19200000, 594000000, 495, 16, 0, 8},
+        { 26000000, 594000000, 594, 26, 0, 8},
+
+        { 12000000, 1000000000, 1000, 12, 0, 12},
+        { 13000000, 1000000000, 1000, 13, 0, 12},
+        { 19200000, 1000000000, 625,  12, 0, 8},
+        { 26000000, 1000000000, 1000, 26, 0, 12},
 
         { 0, 0, 0, 0, 0, 0 },
 };
 
+static struct pdiv_map pllu_p[] = {
+        { .pdiv = 1, .hw_val = 1 },
+        { .pdiv = 2, .hw_val = 0 },
+        { .pdiv = 0, .hw_val = 0 },
+};
+
 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
-        { 12000000, 480000000, 960, 12, 2, 12},
-        { 13000000, 480000000, 960, 13, 2, 12},
-        { 16800000, 480000000, 400, 7,  2, 5},
-        { 19200000, 480000000, 200, 4,  2, 3},
-        { 26000000, 480000000, 960, 26, 2, 12},
+        { 12000000, 480000000, 960, 12, 0, 12},
+        { 13000000, 480000000, 960, 13, 0, 12},
+        { 16800000, 480000000, 400, 7,  0, 5},
+        { 19200000, 480000000, 200, 4,  0, 3},
+        { 26000000, 480000000, 960, 26, 0, 12},
         { 0, 0, 0, 0, 0, 0 },
 };
 
 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
         /* 1.7 GHz */
-        { 12000000, 1700000000, 850,  6,  1, 8},
-        { 13000000, 1700000000, 915,  7,  1, 8},        /* actual: 1699.2 MHz */
-        { 16800000, 1700000000, 708,  7,  1, 8},        /* actual: 1699.2 MHz */
-        { 19200000, 1700000000, 885,  10, 1, 8},        /* actual: 1699.2 MHz */
-        { 26000000, 1700000000, 850,  13, 1, 8},
+        { 12000000, 1700000000, 850,  6,  0, 8},
+        { 13000000, 1700000000, 915,  7,  0, 8},        /* actual: 1699.2 MHz */
+        { 16800000, 1700000000, 708,  7,  0, 8},        /* actual: 1699.2 MHz */
+        { 19200000, 1700000000, 885,  10, 0, 8},        /* actual: 1699.2 MHz */
+        { 26000000, 1700000000, 850,  13, 0, 8},
 
         /* 1.6 GHz */
-        { 12000000, 1600000000, 800,  6,  1, 8},
-        { 13000000, 1600000000, 738,  6,  1, 8},        /* actual: 1599.0 MHz */
-        { 16800000, 1600000000, 857,  9,  1, 8},        /* actual: 1599.7 MHz */
-        { 19200000, 1600000000, 500,  6,  1, 8},
-        { 26000000, 1600000000, 800,  13, 1, 8},
+        { 12000000, 1600000000, 800,  6,  0, 8},
+        { 13000000, 1600000000, 738,  6,  0, 8},        /* actual: 1599.0 MHz */
+        { 16800000, 1600000000, 857,  9,  0, 8},        /* actual: 1599.7 MHz */
+        { 19200000, 1600000000, 500,  6,  0, 8},
+        { 26000000, 1600000000, 800,  13, 0, 8},
 
         /* 1.5 GHz */
-        { 12000000, 1500000000, 750,  6,  1, 8},
-        { 13000000, 1500000000, 923,  8,  1, 8},        /* actual: 1499.8 MHz */
-        { 16800000, 1500000000, 625,  7,  1, 8},
-        { 19200000, 1500000000, 625,  8,  1, 8},
-        { 26000000, 1500000000, 750,  13, 1, 8},
+        { 12000000, 1500000000, 750,  6,  0, 8},
+        { 13000000, 1500000000, 923,  8,  0, 8},        /* actual: 1499.8 MHz */
+        { 16800000, 1500000000, 625,  7,  0, 8},
+        { 19200000, 1500000000, 625,  8,  0, 8},
+        { 26000000, 1500000000, 750,  13, 0, 8},
 
         /* 1.4 GHz */
-        { 12000000, 1400000000, 700,  6,  1, 8},
-        { 13000000, 1400000000, 969,  9,  1, 8},        /* actual: 1399.7 MHz */
-        { 16800000, 1400000000, 1000, 12, 1, 8},
-        { 19200000, 1400000000, 875,  12, 1, 8},
-        { 26000000, 1400000000, 700,  13, 1, 8},
+        { 12000000, 1400000000, 700,  6,  0, 8},
+        { 13000000, 1400000000, 969,  9,  0, 8},        /* actual: 1399.7 MHz */
+        { 16800000, 1400000000, 1000, 12, 0, 8},
+        { 19200000, 1400000000, 875,  12, 0, 8},
+        { 26000000, 1400000000, 700,  13, 0, 8},
 
         /* 1.3 GHz */
-        { 12000000, 1300000000, 975,  9,  1, 8},
-        { 13000000, 1300000000, 1000, 10, 1, 8},
-        { 16800000, 1300000000, 928,  12, 1, 8},        /* actual: 1299.2 MHz */
-        { 19200000, 1300000000, 812,  12, 1, 8},        /* actual: 1299.2 MHz */
-        { 26000000, 1300000000, 650,  13, 1, 8},
+        { 12000000, 1300000000, 975,  9,  0, 8},
+        { 13000000, 1300000000, 1000, 10, 0, 8},
+        { 16800000, 1300000000, 928,  12, 0, 8},        /* actual: 1299.2 MHz */
+        { 19200000, 1300000000, 812,  12, 0, 8},        /* actual: 1299.2 MHz */
+        { 26000000, 1300000000, 650,  13, 0, 8},
 
         /* 1.2 GHz */
-        { 12000000, 1200000000, 1000, 10, 1, 8},
-        { 13000000, 1200000000, 923,  10, 1, 8},        /* actual: 1199.9 MHz */
-        { 16800000, 1200000000, 1000, 14, 1, 8},
-        { 19200000, 1200000000, 1000, 16, 1, 8},
-        { 26000000, 1200000000, 600,  13, 1, 8},
+        { 12000000, 1200000000, 1000, 10, 0, 8},
+        { 13000000, 1200000000, 923,  10, 0, 8},        /* actual: 1199.9 MHz */
+        { 16800000, 1200000000, 1000, 14, 0, 8},
+        { 19200000, 1200000000, 1000, 16, 0, 8},
+        { 26000000, 1200000000, 600,  13, 0, 8},
 
         /* 1.1 GHz */
-        { 12000000, 1100000000, 825,  9,  1, 8},
-        { 13000000, 1100000000, 846,  10, 1, 8},        /* actual: 1099.8 MHz */
-        { 16800000, 1100000000, 982,  15, 1, 8},        /* actual: 1099.8 MHz */
-        { 19200000, 1100000000, 859,  15, 1, 8},        /* actual: 1099.5 MHz */
-        { 26000000, 1100000000, 550,  13, 1, 8},
+        { 12000000, 1100000000, 825,  9,  0, 8},
+        { 13000000, 1100000000, 846,  10, 0, 8},        /* actual: 1099.8 MHz */
+        { 16800000, 1100000000, 982,  15, 0, 8},        /* actual: 1099.8 MHz */
+        { 19200000, 1100000000, 859,  15, 0, 8},        /* actual: 1099.5 MHz */
+        { 26000000, 1100000000, 550,  13, 0, 8},
 
         /* 1 GHz */
-        { 12000000, 1000000000, 1000, 12, 1, 8},
-        { 13000000, 1000000000, 1000, 13, 1, 8},
-        { 16800000, 1000000000, 833,  14, 1, 8},        /* actual: 999.6 MHz */
-        { 19200000, 1000000000, 625,  12, 1, 8},
-        { 26000000, 1000000000, 1000, 26, 1, 8},
+        { 12000000, 1000000000, 1000, 12, 0, 8},
+        { 13000000, 1000000000, 1000, 13, 0, 8},
+        { 16800000, 1000000000, 833,  14, 0, 8},        /* actual: 999.6 MHz */
+        { 19200000, 1000000000, 625,  12, 0, 8},
+        { 26000000, 1000000000, 1000, 26, 0, 8},
 
         { 0, 0, 0, 0, 0, 0 },
 };
@@ -553,7 +559,7 @@ static struct tegra_clk_pll_params pll_c_params = {
         .vco_max = 1400000000,
         .base_reg = PLLC_BASE,
         .misc_reg = PLLC_MISC,
-        .lock_bit_idx = PLL_BASE_LOCK,
+        .lock_mask = PLL_BASE_LOCK,
         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
         .lock_delay = 300,
 };
@@ -567,7 +573,7 @@ static struct tegra_clk_pll_params pll_m_params = {
         .vco_max = 1200000000,
         .base_reg = PLLM_BASE,
         .misc_reg = PLLM_MISC,
-        .lock_bit_idx = PLL_BASE_LOCK,
+        .lock_mask = PLL_BASE_LOCK,
         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
         .lock_delay = 300,
 };
@@ -581,7 +587,7 @@ static struct tegra_clk_pll_params pll_p_params = {
         .vco_max = 1400000000,
         .base_reg = PLLP_BASE,
         .misc_reg = PLLP_MISC,
-        .lock_bit_idx = PLL_BASE_LOCK,
+        .lock_mask = PLL_BASE_LOCK,
         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
         .lock_delay = 300,
 };
@@ -595,7 +601,7 @@ static struct tegra_clk_pll_params pll_a_params = {
         .vco_max = 1400000000,
         .base_reg = PLLA_BASE,
         .misc_reg = PLLA_MISC,
-        .lock_bit_idx = PLL_BASE_LOCK,
+        .lock_mask = PLL_BASE_LOCK,
         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
         .lock_delay = 300,
 };
@@ -609,7 +615,7 @@ static struct tegra_clk_pll_params pll_d_params = {
         .vco_max = 1000000000,
         .base_reg = PLLD_BASE,
         .misc_reg = PLLD_MISC,
-        .lock_bit_idx = PLL_BASE_LOCK,
+        .lock_mask = PLL_BASE_LOCK,
         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
         .lock_delay = 1000,
 };
@@ -623,7 +629,7 @@ static struct tegra_clk_pll_params pll_d2_params = {
         .vco_max = 1000000000,
         .base_reg = PLLD2_BASE,
         .misc_reg = PLLD2_MISC,
-        .lock_bit_idx = PLL_BASE_LOCK,
+        .lock_mask = PLL_BASE_LOCK,
         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
         .lock_delay = 1000,
 };
@@ -637,9 +643,10 @@ static struct tegra_clk_pll_params pll_u_params = {
         .vco_max = 960000000,
         .base_reg = PLLU_BASE,
         .misc_reg = PLLU_MISC,
-        .lock_bit_idx = PLL_BASE_LOCK,
+        .lock_mask = PLL_BASE_LOCK,
         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
         .lock_delay = 1000,
+        .pdiv_tohw = pllu_p,
 };
 
 static struct tegra_clk_pll_params pll_x_params = {
@@ -651,7 +658,7 @@ static struct tegra_clk_pll_params pll_x_params = {
         .vco_max = 1700000000,
         .base_reg = PLLX_BASE,
         .misc_reg = PLLX_MISC,
-        .lock_bit_idx = PLL_BASE_LOCK,
+        .lock_mask = PLL_BASE_LOCK,
         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
         .lock_delay = 300,
 };
@@ -665,7 +672,7 @@ static struct tegra_clk_pll_params pll_e_params = {
         .vco_max = 2400000000U,
         .base_reg = PLLE_BASE,
         .misc_reg = PLLE_MISC,
-        .lock_bit_idx = PLLE_MISC_LOCK,
+        .lock_mask = PLLE_MISC_LOCK,
         .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
         .lock_delay = 300,
 };
@@ -1661,7 +1668,7 @@ static void __init tegra30_periph_clk_init(void)
                 data = &tegra_periph_clk_list[i];
                 clk = tegra_clk_register_periph(data->name, data->parent_names,
                                 data->num_parents, &data->periph,
-                                clk_base, data->offset);
+                                clk_base, data->offset, data->flags);
                 clk_register_clkdev(clk, data->con_id, data->dev_id);
                 clks[data->clk_id] = clk;
         }
@@ -1911,9 +1918,16 @@ static __initdata struct tegra_clk_init_table init_table[] = {
         {disp1, pll_p, 600000000, 0},
         {disp2, pll_p, 600000000, 0},
         {twd, clk_max, 0, 1},
+        {gr2d, pll_c, 300000000, 0},
+        {gr3d, pll_c, 300000000, 0},
         {clk_max, clk_max, 0, 0}, /* This MUST be the last entry. */
 };
 
+static void __init tegra30_clock_apply_init_table(void)
+{
+        tegra_init_from_table(init_table, clks, clk_max);
+}
+
 /*
  * Some clocks may be used by different drivers depending on the board
  * configuration.  List those here to register them twice in the clock lookup
@@ -1987,7 +2001,7 @@ void __init tegra30_clock_init(struct device_node *np)
         clk_data.clk_num = ARRAY_SIZE(clks);
         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 
-        tegra_init_from_table(init_table, clks, clk_max);
+        tegra_clk_apply_init_table = tegra30_clock_apply_init_table;
 
         tegra_cpu_car_ops = &tegra30_cpu_car_ops;
 }
diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c
index a603b9af0ad3..923ca7ee4694 100644
--- a/drivers/clk/tegra/clk.c
+++ b/drivers/clk/tegra/clk.c
@@ -22,7 +22,8 @@
 #include "clk.h"
 
 /* Global data of Tegra CPU CAR ops */
-struct tegra_cpu_car_ops *tegra_cpu_car_ops;
+static struct tegra_cpu_car_ops dummy_car_ops;
+struct tegra_cpu_car_ops *tegra_cpu_car_ops = &dummy_car_ops;
 
 void __init tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
                                 struct clk *clks[], int clk_max)
@@ -76,6 +77,7 @@ void __init tegra_init_from_table(struct tegra_clk_init_table *tbl,
 static const struct of_device_id tegra_dt_clk_match[] = {
         { .compatible = "nvidia,tegra20-car", .data = tegra20_clock_init },
         { .compatible = "nvidia,tegra30-car", .data = tegra30_clock_init },
+        { .compatible = "nvidia,tegra114-car", .data = tegra114_clock_init },
         { }
 };
 
@@ -83,3 +85,13 @@ void __init tegra_clocks_init(void)
 {
         of_clk_init(tegra_dt_clk_match);
 }
+
+tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
+
+void __init tegra_clocks_apply_init_table(void)
+{
+        if (!tegra_clk_apply_init_table)
+                return;
+
+        tegra_clk_apply_init_table();
+}
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 0744731c6229..e0565620d68e 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -1,4 +1,4 @@
-/*
+        /*
  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
@@ -117,6 +117,17 @@ struct tegra_clk_pll_freq_table {
 };
 
 /**
+ * struct pdiv_map - map post divider to hw value
+ *
+ * @pdiv:               post divider
+ * @hw_val:             value to be written to the PLL hw
+ */
+struct pdiv_map {
+        u8 pdiv;
+        u8 hw_val;
+};
+
+/**
  * struct clk_pll_params - PLL parameters
  *
  * @input_min:                  Minimum input frequency
@@ -143,9 +154,18 @@ struct tegra_clk_pll_params {
         u32             base_reg;
         u32             misc_reg;
         u32             lock_reg;
-        u32             lock_bit_idx;
+        u32             lock_mask;
         u32             lock_enable_bit_idx;
+        u32             iddq_reg;
+        u32             iddq_bit_idx;
+        u32             aux_reg;
+        u32             dyn_ramp_reg;
+        u32             ext_misc_reg[3];
+        int             stepa_shift;
+        int             stepb_shift;
         int             lock_delay;
+        int             max_p;
+        struct pdiv_map *pdiv_tohw;
 };
 
 /**
@@ -182,12 +202,16 @@ struct tegra_clk_pll_params {
  * TEGRA_PLL_FIXED - We are not supposed to change output frequency
  *     of some plls.
  * TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling.
+ * TEGRA_PLL_LOCK_MISC - Lock bit is in the misc register instead of the
+ *     base register.
+ * TEGRA_PLL_BYPASS - PLL has bypass bit
+ * TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring
  */
 struct tegra_clk_pll {
         struct clk_hw   hw;
         void __iomem    *clk_base;
         void __iomem    *pmc;
-        u8              flags;
+        u32             flags;
         unsigned long   fixed_rate;
         spinlock_t      *lock;
         u8              divn_shift;
@@ -210,20 +234,64 @@ struct tegra_clk_pll {
 #define TEGRA_PLLM BIT(5)
 #define TEGRA_PLL_FIXED BIT(6)
 #define TEGRA_PLLE_CONFIGURE BIT(7)
+#define TEGRA_PLL_LOCK_MISC BIT(8)
+#define TEGRA_PLL_BYPASS BIT(9)
+#define TEGRA_PLL_HAS_LOCK_ENABLE BIT(10)
 
 extern const struct clk_ops tegra_clk_pll_ops;
 extern const struct clk_ops tegra_clk_plle_ops;
 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
                 void __iomem *clk_base, void __iomem *pmc,
                 unsigned long flags, unsigned long fixed_rate,
-                struct tegra_clk_pll_params *pll_params, u8 pll_flags,
+                struct tegra_clk_pll_params *pll_params, u32 pll_flags,
                 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock);
+
 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
                 void __iomem *clk_base, void __iomem *pmc,
                 unsigned long flags, unsigned long fixed_rate,
-                struct tegra_clk_pll_params *pll_params, u8 pll_flags,
+                struct tegra_clk_pll_params *pll_params, u32 pll_flags,
                 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock);
 
+struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
+                            void __iomem *clk_base, void __iomem *pmc,
+                            unsigned long flags, unsigned long fixed_rate,
+                            struct tegra_clk_pll_params *pll_params,
+                            u32 pll_flags,
+                            struct tegra_clk_pll_freq_table *freq_table,
+                            spinlock_t *lock);
+
+struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
+                           void __iomem *clk_base, void __iomem *pmc,
+                           unsigned long flags, unsigned long fixed_rate,
+                           struct tegra_clk_pll_params *pll_params,
+                           u32 pll_flags,
+                           struct tegra_clk_pll_freq_table *freq_table,
+                           spinlock_t *lock);
+
+struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
+                           void __iomem *clk_base, void __iomem *pmc,
+                           unsigned long flags, unsigned long fixed_rate,
+                           struct tegra_clk_pll_params *pll_params,
+                           u32 pll_flags,
+                           struct tegra_clk_pll_freq_table *freq_table,
+                           spinlock_t *lock);
+
+struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
+                           void __iomem *clk_base, void __iomem *pmc,
+                           unsigned long flags, unsigned long fixed_rate,
+                           struct tegra_clk_pll_params *pll_params,
+                           u32 pll_flags,
+                           struct tegra_clk_pll_freq_table *freq_table,
+                           spinlock_t *lock, unsigned long parent_rate);
+
+struct clk *tegra_clk_register_plle_tegra114(const char *name,
+                                const char *parent_name,
+                                void __iomem *clk_base, unsigned long flags,
+                                unsigned long fixed_rate,
+                                struct tegra_clk_pll_params *pll_params,
+                                struct tegra_clk_pll_freq_table *freq_table,
+                                spinlock_t *lock);
+
 /**
  * struct tegra_clk_pll_out - PLL divider down clock
  *
@@ -290,6 +358,7 @@ struct tegra_clk_periph_regs {
  * TEGRA_PERIPH_ON_APB - If peripheral is in the APB bus then read the
  *     bus to flush the write operation in apb bus. This flag indicates
  *     that this peripheral is in apb bus.
+ * TEGRA_PERIPH_WAR_1005168 - Apply workaround for Tegra114 MSENC bug
  */
 struct tegra_clk_periph_gate {
         u32                     magic;
@@ -309,6 +378,7 @@ struct tegra_clk_periph_gate {
 #define TEGRA_PERIPH_NO_RESET BIT(0)
 #define TEGRA_PERIPH_MANUAL_RESET BIT(1)
 #define TEGRA_PERIPH_ON_APB BIT(2)
+#define TEGRA_PERIPH_WAR_1005168 BIT(3)
 
 void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert);
 extern const struct clk_ops tegra_clk_periph_gate_ops;
@@ -349,21 +419,22 @@ extern const struct clk_ops tegra_clk_periph_ops;
 struct clk *tegra_clk_register_periph(const char *name,
                 const char **parent_names, int num_parents,
                 struct tegra_clk_periph *periph, void __iomem *clk_base,
-                u32 offset);
+                u32 offset, unsigned long flags);
 struct clk *tegra_clk_register_periph_nodiv(const char *name,
                 const char **parent_names, int num_parents,
                 struct tegra_clk_periph *periph, void __iomem *clk_base,
                 u32 offset);
 
-#define TEGRA_CLK_PERIPH(_mux_shift, _mux_width, _mux_flags,            \
+#define TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, _mux_flags,             \
                          _div_shift, _div_width, _div_frac_width,       \
                          _div_flags, _clk_num, _enb_refcnt, _regs,      \
-                         _gate_flags)                                   \
+                         _gate_flags, _table)                           \
         {                                                               \
                 .mux = {                                                \
                         .flags = _mux_flags,                            \
                         .shift = _mux_shift,                            \
-                        .width = _mux_width,                            \
+                        .mask = _mux_mask,                              \
+                        .table = _table,                                \
                 },                                                      \
                 .divider = {                                            \
                         .flags = _div_flags,                            \
@@ -391,28 +462,41 @@ struct tegra_periph_init_data {
         u32 offset;
         const char *con_id;
         const char *dev_id;
+        unsigned long flags;
 };
 
-#define TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parent_names, _offset, \
-                        _mux_shift, _mux_width, _mux_flags, _div_shift, \
+#define TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\
+                        _mux_shift, _mux_mask, _mux_flags, _div_shift,  \
                         _div_width, _div_frac_width, _div_flags, _regs, \
-                        _clk_num, _enb_refcnt, _gate_flags, _clk_id)    \
+                        _clk_num, _enb_refcnt, _gate_flags, _clk_id, _table,\
+                        _flags) \
         {                                                               \
                 .name = _name,                                          \
                 .clk_id = _clk_id,                                      \
                 .parent_names = _parent_names,                          \
                 .num_parents = ARRAY_SIZE(_parent_names),               \
-                .periph = TEGRA_CLK_PERIPH(_mux_shift, _mux_width,      \
+                .periph = TEGRA_CLK_PERIPH(_mux_shift, _mux_mask,       \
                                            _mux_flags, _div_shift,      \
                                            _div_width, _div_frac_width, \
                                            _div_flags, _clk_num,        \
                                            _enb_refcnt, _regs,          \
-                                           _gate_flags),                \
+                                           _gate_flags, _table),        \
                 .offset = _offset,                                      \
                 .con_id = _con_id,                                      \
                 .dev_id = _dev_id,                                      \
+                .flags = _flags                                         \
         }
 
+#define TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parent_names, _offset,\
+                        _mux_shift, _mux_width, _mux_flags, _div_shift, \
+                        _div_width, _div_frac_width, _div_flags, _regs, \
+                        _clk_num, _enb_refcnt, _gate_flags, _clk_id)    \
+        TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\
+                        _mux_shift, BIT(_mux_width) - 1, _mux_flags,    \
+                        _div_shift, _div_width, _div_frac_width, _div_flags, \
+                        _regs, _clk_num, _enb_refcnt, _gate_flags, _clk_id,\
+                        NULL, 0)
+
 /**
  * struct clk_super_mux - super clock
  *
@@ -499,4 +583,13 @@ void tegra30_clock_init(struct device_node *np);
 static inline void tegra30_clock_init(struct device_node *np) {}
 #endif /* CONFIG_ARCH_TEGRA_3x_SOC */
 
+#ifdef CONFIG_ARCH_TEGRA_114_SOC
+void tegra114_clock_init(struct device_node *np);
+#else
+static inline void tegra114_clock_init(struct device_node *np) {}
+#endif /* CONFIG_ARCH_TEGRA114_SOC */
+
+typedef void (*tegra_clk_apply_init_table_func)(void);
+extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
+
 #endif /* TEGRA_CLK_H */
diff --git a/drivers/clk/ux500/clk-prcmu.c b/drivers/clk/ux500/clk-prcmu.c
index 74faa7e3cf59..293a28854417 100644
--- a/drivers/clk/ux500/clk-prcmu.c
+++ b/drivers/clk/ux500/clk-prcmu.c
@@ -20,15 +20,23 @@
 struct clk_prcmu {
         struct clk_hw hw;
         u8 cg_sel;
+        int is_prepared;
         int is_enabled;
+        int opp_requested;
 };
 
 /* PRCMU clock operations. */
 
 static int clk_prcmu_prepare(struct clk_hw *hw)
 {
+        int ret;
         struct clk_prcmu *clk = to_clk_prcmu(hw);
-        return prcmu_request_clock(clk->cg_sel, true);
+
+        ret = prcmu_request_clock(clk->cg_sel, true);
+        if (!ret)
+                clk->is_prepared = 1;
+
+        return ret;;
 }
 
 static void clk_prcmu_unprepare(struct clk_hw *hw)
@@ -36,7 +44,15 @@ static void clk_prcmu_unprepare(struct clk_hw *hw)
         struct clk_prcmu *clk = to_clk_prcmu(hw);
         if (prcmu_request_clock(clk->cg_sel, false))
                 pr_err("clk_prcmu: %s failed to disable %s.\n", __func__,
-                        hw->init->name);
+                        __clk_get_name(hw->clk));
+        else
+                clk->is_prepared = 0;
+}
+
+static int clk_prcmu_is_prepared(struct clk_hw *hw)
+{
+        struct clk_prcmu *clk = to_clk_prcmu(hw);
+        return clk->is_prepared;
 }
 
 static int clk_prcmu_enable(struct clk_hw *hw)
@@ -79,58 +95,52 @@ static int clk_prcmu_set_rate(struct clk_hw *hw, unsigned long rate,
         return prcmu_set_clock_rate(clk->cg_sel, rate);
 }
 
-static int request_ape_opp100(bool enable)
-{
-        static int reqs;
-        int err = 0;
-
-        if (enable) {
-                if (!reqs)
-                        err = prcmu_qos_add_requirement(PRCMU_QOS_APE_OPP,
-                                                        "clock", 100);
-                if (!err)
-                        reqs++;
-        } else {
-                reqs--;
-                if (!reqs)
-                        prcmu_qos_remove_requirement(PRCMU_QOS_APE_OPP,
-                                                "clock");
-        }
-        return err;
-}
-
 static int clk_prcmu_opp_prepare(struct clk_hw *hw)
 {
         int err;
         struct clk_prcmu *clk = to_clk_prcmu(hw);
 
-        err = request_ape_opp100(true);
-        if (err) {
-                pr_err("clk_prcmu: %s failed to request APE OPP100 for %s.\n",
-                        __func__, hw->init->name);
-                return err;
+        if (!clk->opp_requested) {
+                err = prcmu_qos_add_requirement(PRCMU_QOS_APE_OPP,
+                                                (char *)__clk_get_name(hw->clk),
+                                                100);
+                if (err) {
+                        pr_err("clk_prcmu: %s fail req APE OPP for %s.\n",
+                                __func__, __clk_get_name(hw->clk));
+                        return err;
+                }
+                clk->opp_requested = 1;
         }
 
         err = prcmu_request_clock(clk->cg_sel, true);
-        if (err)
-                request_ape_opp100(false);
+        if (err) {
+                prcmu_qos_remove_requirement(PRCMU_QOS_APE_OPP,
+                                        (char *)__clk_get_name(hw->clk));
+                clk->opp_requested = 0;
+                return err;
+        }
 
-        return err;
+        clk->is_prepared = 1;
+        return 0;
 }
 
 static void clk_prcmu_opp_unprepare(struct clk_hw *hw)
 {
         struct clk_prcmu *clk = to_clk_prcmu(hw);
 
-        if (prcmu_request_clock(clk->cg_sel, false))
-                goto out_error;
-        if (request_ape_opp100(false))
-                goto out_error;
-        return;
-
-out_error:
-        pr_err("clk_prcmu: %s failed to disable %s.\n", __func__,
-                hw->init->name);
+        if (prcmu_request_clock(clk->cg_sel, false)) {
+                pr_err("clk_prcmu: %s failed to disable %s.\n", __func__,
+                        __clk_get_name(hw->clk));
+                return;
+        }
+
+        if (clk->opp_requested) {
+                prcmu_qos_remove_requirement(PRCMU_QOS_APE_OPP,
+                                        (char *)__clk_get_name(hw->clk));
+                clk->opp_requested = 0;
+        }
+
+        clk->is_prepared = 0;
 }
 
 static int clk_prcmu_opp_volt_prepare(struct clk_hw *hw)
@@ -138,38 +148,49 @@ static int clk_prcmu_opp_volt_prepare(struct clk_hw *hw)
         int err;
         struct clk_prcmu *clk = to_clk_prcmu(hw);
 
-        err = prcmu_request_ape_opp_100_voltage(true);
-        if (err) {
-                pr_err("clk_prcmu: %s failed to request APE OPP VOLT for %s.\n",
-                        __func__, hw->init->name);
-                return err;
+        if (!clk->opp_requested) {
+                err = prcmu_request_ape_opp_100_voltage(true);
+                if (err) {
+                        pr_err("clk_prcmu: %s fail req APE OPP VOLT for %s.\n",
+                                __func__, __clk_get_name(hw->clk));
+                        return err;
+                }
+                clk->opp_requested = 1;
         }
 
         err = prcmu_request_clock(clk->cg_sel, true);
-        if (err)
+        if (err) {
                 prcmu_request_ape_opp_100_voltage(false);
+                clk->opp_requested = 0;
+                return err;
+        }
 
-        return err;
+        clk->is_prepared = 1;
+        return 0;
 }
 
 static void clk_prcmu_opp_volt_unprepare(struct clk_hw *hw)
 {
         struct clk_prcmu *clk = to_clk_prcmu(hw);
 
-        if (prcmu_request_clock(clk->cg_sel, false))
-                goto out_error;
-        if (prcmu_request_ape_opp_100_voltage(false))
-                goto out_error;
-        return;
-
-out_error:
-        pr_err("clk_prcmu: %s failed to disable %s.\n", __func__,
-                hw->init->name);
+        if (prcmu_request_clock(clk->cg_sel, false)) {
+                pr_err("clk_prcmu: %s failed to disable %s.\n", __func__,
+                        __clk_get_name(hw->clk));
+                return;
+        }
+
+        if (clk->opp_requested) {
+                prcmu_request_ape_opp_100_voltage(false);
+                clk->opp_requested = 0;
+        }
+
+        clk->is_prepared = 0;
 }
 
 static struct clk_ops clk_prcmu_scalable_ops = {
         .prepare = clk_prcmu_prepare,
         .unprepare = clk_prcmu_unprepare,
+        .is_prepared = clk_prcmu_is_prepared,
         .enable = clk_prcmu_enable,
         .disable = clk_prcmu_disable,
         .is_enabled = clk_prcmu_is_enabled,
@@ -181,6 +202,7 @@ static struct clk_ops clk_prcmu_scalable_ops = {
 static struct clk_ops clk_prcmu_gate_ops = {
         .prepare = clk_prcmu_prepare,
         .unprepare = clk_prcmu_unprepare,
+        .is_prepared = clk_prcmu_is_prepared,
         .enable = clk_prcmu_enable,
         .disable = clk_prcmu_disable,
         .is_enabled = clk_prcmu_is_enabled,
@@ -202,6 +224,7 @@ static struct clk_ops clk_prcmu_rate_ops = {
 static struct clk_ops clk_prcmu_opp_gate_ops = {
         .prepare = clk_prcmu_opp_prepare,
         .unprepare = clk_prcmu_opp_unprepare,
+        .is_prepared = clk_prcmu_is_prepared,
         .enable = clk_prcmu_enable,
         .disable = clk_prcmu_disable,
         .is_enabled = clk_prcmu_is_enabled,
@@ -211,6 +234,7 @@ static struct clk_ops clk_prcmu_opp_gate_ops = {
 static struct clk_ops clk_prcmu_opp_volt_scalable_ops = {
         .prepare = clk_prcmu_opp_volt_prepare,
         .unprepare = clk_prcmu_opp_volt_unprepare,
+        .is_prepared = clk_prcmu_is_prepared,
         .enable = clk_prcmu_enable,
         .disable = clk_prcmu_disable,
         .is_enabled = clk_prcmu_is_enabled,
@@ -242,7 +266,9 @@ static struct clk *clk_reg_prcmu(const char *name,
         }
 
         clk->cg_sel = cg_sel;
+        clk->is_prepared = 1;
         clk->is_enabled = 1;
+        clk->opp_requested = 0;
         /* "rate" can be used for changing the initial frequency */
         if (rate)
                 prcmu_set_clock_rate(cg_sel, rate);
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 3167fda9bbb3..29ba35e6a143 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -65,8 +65,14 @@ config CLKSRC_DBX500_PRCMU_SCHED_CLOCK
 
 config ARM_ARCH_TIMER
         bool
+        select CLKSRC_OF if OF
 
 config CLKSRC_METAG_GENERIC
         def_bool y if METAG
         help
           This option enables support for the Meta per-thread timers.
+
+config CLKSRC_EXYNOS_MCT
+        def_bool y if ARCH_EXYNOS
+        help
+          Support for Multi Core Timer controller on Exynos SoCs.
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index e74c8ce26bf0..cd1f09cbd61a 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -19,7 +19,8 @@ obj-$(CONFIG_ARCH_BCM2835)	+= bcm2835_timer.o
 obj-$(CONFIG_SUNXI_TIMER)       += sunxi_timer.o
 obj-$(CONFIG_ARCH_TEGRA)        += tegra20_timer.o
 obj-$(CONFIG_VT8500_TIMER)      += vt8500_timer.o
-obj-$(CONFIG_CADENCE_TTC_TIMER)         += cadence_ttc_timer.o
+obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence_ttc_timer.o
+obj-$(CONFIG_CLKSRC_EXYNOS_MCT) += exynos_mct.o
 
 obj-$(CONFIG_ARM_ARCH_TIMER)            += arm_arch_timer.o
 obj-$(CONFIG_CLKSRC_METAG_GENERIC)      += metag_generic.o
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index d7ad425ab9b3..a2b254189782 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -248,14 +248,16 @@ static void __cpuinit arch_timer_stop(struct clock_event_device *clk)
 static int __cpuinit arch_timer_cpu_notify(struct notifier_block *self,
                                            unsigned long action, void *hcpu)
 {
-        struct clock_event_device *evt = this_cpu_ptr(arch_timer_evt);
-
+        /*
+         * Grab cpu pointer in each case to avoid spurious
+         * preemptible warnings
+         */
         switch (action & ~CPU_TASKS_FROZEN) {
         case CPU_STARTING:
-                arch_timer_setup(evt);
+                arch_timer_setup(this_cpu_ptr(arch_timer_evt));
                 break;
         case CPU_DYING:
-                arch_timer_stop(evt);
+                arch_timer_stop(this_cpu_ptr(arch_timer_evt));
                 break;
         }
 
@@ -337,22 +339,14 @@ out:
         return err;
 }
 
-static const struct of_device_id arch_timer_of_match[] __initconst = {
-        { .compatible   = "arm,armv7-timer",    },
-        { .compatible   = "arm,armv8-timer",    },
-        {},
-};
-
-int __init arch_timer_init(void)
+static void __init arch_timer_init(struct device_node *np)
 {
-        struct device_node *np;
         u32 freq;
         int i;
 
-        np = of_find_matching_node(NULL, arch_timer_of_match);
-        if (!np) {
-                pr_err("arch_timer: can't find DT node\n");
-                return -ENODEV;
+        if (arch_timer_get_rate()) {
+                pr_warn("arch_timer: multiple nodes in dt, skipping\n");
+                return;
         }
 
         /* Try to determine the frequency from the device tree or CNTFRQ */
@@ -378,7 +372,7 @@ int __init arch_timer_init(void)
                 if (!arch_timer_ppi[PHYS_SECURE_PPI] ||
                     !arch_timer_ppi[PHYS_NONSECURE_PPI]) {
                         pr_warn("arch_timer: No interrupt available, giving up\n");
-                        return -EINVAL;
+                        return;
                 }
         }
 
@@ -387,5 +381,8 @@ int __init arch_timer_init(void)
         else
                 arch_timer_read_counter = arch_counter_get_cntpct;
 
-        return arch_timer_register();
+        arch_timer_register();
+        arch_timer_arch_init();
 }
+CLOCKSOURCE_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_init);
+CLOCKSOURCE_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_init);
diff --git a/arch/arm/mach-exynos/mct.c b/drivers/clocksource/exynos_mct.c
index c9d6650f9b5d..b078d7cbc930 100644
--- a/arch/arm/mach-exynos/mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -20,17 +20,46 @@
 #include <linux/delay.h>
 #include <linux/percpu.h>
 #include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/clocksource.h>
 
-#include <asm/arch_timer.h>
 #include <asm/localtimer.h>
 
 #include <plat/cpu.h>
 
 #include <mach/map.h>
 #include <mach/irqs.h>
-#include <mach/regs-mct.h>
 #include <asm/mach/time.h>
 
+#define EXYNOS4_MCTREG(x)               (x)
+#define EXYNOS4_MCT_G_CNT_L             EXYNOS4_MCTREG(0x100)
+#define EXYNOS4_MCT_G_CNT_U             EXYNOS4_MCTREG(0x104)
+#define EXYNOS4_MCT_G_CNT_WSTAT         EXYNOS4_MCTREG(0x110)
+#define EXYNOS4_MCT_G_COMP0_L           EXYNOS4_MCTREG(0x200)
+#define EXYNOS4_MCT_G_COMP0_U           EXYNOS4_MCTREG(0x204)
+#define EXYNOS4_MCT_G_COMP0_ADD_INCR    EXYNOS4_MCTREG(0x208)
+#define EXYNOS4_MCT_G_TCON              EXYNOS4_MCTREG(0x240)
+#define EXYNOS4_MCT_G_INT_CSTAT         EXYNOS4_MCTREG(0x244)
+#define EXYNOS4_MCT_G_INT_ENB           EXYNOS4_MCTREG(0x248)
+#define EXYNOS4_MCT_G_WSTAT             EXYNOS4_MCTREG(0x24C)
+#define _EXYNOS4_MCT_L_BASE             EXYNOS4_MCTREG(0x300)
+#define EXYNOS4_MCT_L_BASE(x)           (_EXYNOS4_MCT_L_BASE + (0x100 * x))
+#define EXYNOS4_MCT_L_MASK              (0xffffff00)
+
+#define MCT_L_TCNTB_OFFSET              (0x00)
+#define MCT_L_ICNTB_OFFSET              (0x08)
+#define MCT_L_TCON_OFFSET               (0x20)
+#define MCT_L_INT_CSTAT_OFFSET          (0x30)
+#define MCT_L_INT_ENB_OFFSET            (0x34)
+#define MCT_L_WSTAT_OFFSET              (0x40)
+#define MCT_G_TCON_START                (1 << 8)
+#define MCT_G_TCON_COMP0_AUTO_INC       (1 << 1)
+#define MCT_G_TCON_COMP0_ENABLE         (1 << 0)
+#define MCT_L_TCON_INTERVAL_MODE        (1 << 2)
+#define MCT_L_TCON_INT_START            (1 << 1)
+#define MCT_L_TCON_TIMER_START          (1 << 0)
+
 #define TICK_BASE_CNT   1
 
 enum {
@@ -38,64 +67,75 @@ enum {
         MCT_INT_PPI
 };
 
+enum {
+        MCT_G0_IRQ,
+        MCT_G1_IRQ,
+        MCT_G2_IRQ,
+        MCT_G3_IRQ,
+        MCT_L0_IRQ,
+        MCT_L1_IRQ,
+        MCT_L2_IRQ,
+        MCT_L3_IRQ,
+        MCT_NR_IRQS,
+};
+
+static void __iomem *reg_base;
 static unsigned long clk_rate;
 static unsigned int mct_int_type;
+static int mct_irqs[MCT_NR_IRQS];
 
 struct mct_clock_event_device {
         struct clock_event_device *evt;
-        void __iomem *base;
+        unsigned long base;
         char name[10];
 };
 
-static void exynos4_mct_write(unsigned int value, void *addr)
+static void exynos4_mct_write(unsigned int value, unsigned long offset)
 {
-        void __iomem *stat_addr;
+        unsigned long stat_addr;
         u32 mask;
         u32 i;
 
-        __raw_writel(value, addr);
+        __raw_writel(value, reg_base + offset);
 
-        if (likely(addr >= EXYNOS4_MCT_L_BASE(0))) {
-                u32 base = (u32) addr & EXYNOS4_MCT_L_MASK;
-                switch ((u32) addr & ~EXYNOS4_MCT_L_MASK) {
-                case (u32) MCT_L_TCON_OFFSET:
-                        stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
+        if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) {
+                stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
+                switch (offset & EXYNOS4_MCT_L_MASK) {
+                case MCT_L_TCON_OFFSET:
                         mask = 1 << 3;          /* L_TCON write status */
                         break;
-                case (u32) MCT_L_ICNTB_OFFSET:
-                        stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
+                case MCT_L_ICNTB_OFFSET:
                         mask = 1 << 1;          /* L_ICNTB write status */
                         break;
-                case (u32) MCT_L_TCNTB_OFFSET:
-                        stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
+                case MCT_L_TCNTB_OFFSET:
                         mask = 1 << 0;          /* L_TCNTB write status */
                         break;
                 default:
                         return;
                 }
         } else {
-                switch ((u32) addr) {
-                case (u32) EXYNOS4_MCT_G_TCON:
+                switch (offset) {
+                case EXYNOS4_MCT_G_TCON:
                         stat_addr = EXYNOS4_MCT_G_WSTAT;
                         mask = 1 << 16;         /* G_TCON write status */
                         break;
-                case (u32) EXYNOS4_MCT_G_COMP0_L:
+                case EXYNOS4_MCT_G_COMP0_L:
                         stat_addr = EXYNOS4_MCT_G_WSTAT;
                         mask = 1 << 0;          /* G_COMP0_L write status */
                         break;
-                case (u32) EXYNOS4_MCT_G_COMP0_U:
+                case EXYNOS4_MCT_G_COMP0_U:
                         stat_addr = EXYNOS4_MCT_G_WSTAT;
                         mask = 1 << 1;          /* G_COMP0_U write status */
                         break;
-                case (u32) EXYNOS4_MCT_G_COMP0_ADD_INCR:
+                case EXYNOS4_MCT_G_COMP0_ADD_INCR:
                         stat_addr = EXYNOS4_MCT_G_WSTAT;
                         mask = 1 << 2;          /* G_COMP0_ADD_INCR w status */
                         break;
-                case (u32) EXYNOS4_MCT_G_CNT_L:
+                case EXYNOS4_MCT_G_CNT_L:
                         stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
                         mask = 1 << 0;          /* G_CNT_L write status */
                         break;
-                case (u32) EXYNOS4_MCT_G_CNT_U:
+                case EXYNOS4_MCT_G_CNT_U:
                         stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
                         mask = 1 << 1;          /* G_CNT_U write status */
                         break;
@@ -106,12 +146,12 @@ static void exynos4_mct_write(unsigned int value, void *addr)
 
         /* Wait maximum 1 ms until written values are applied */
         for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
-                if (__raw_readl(stat_addr) & mask) {
-                        __raw_writel(mask, stat_addr);
+                if (__raw_readl(reg_base + stat_addr) & mask) {
+                        __raw_writel(mask, reg_base + stat_addr);
                         return;
                 }
 
-        panic("MCT hangs after writing %d (addr:0x%08x)\n", value, (u32)addr);
+        panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset);
 }
 
 /* Clocksource handling */
@@ -122,7 +162,7 @@ static void exynos4_mct_frc_start(u32 hi, u32 lo)
         exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
         exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
 
-        reg = __raw_readl(EXYNOS4_MCT_G_TCON);
+        reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
         reg |= MCT_G_TCON_START;
         exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
 }
@@ -130,12 +170,12 @@ static void exynos4_mct_frc_start(u32 hi, u32 lo)
 static cycle_t exynos4_frc_read(struct clocksource *cs)
 {
         unsigned int lo, hi;
-        u32 hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
+        u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
 
         do {
                 hi = hi2;
-                lo = __raw_readl(EXYNOS4_MCT_G_CNT_L);
-                hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
+                lo = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L);
+                hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
         } while (hi != hi2);
 
         return ((cycle_t)hi << 32) | lo;
@@ -167,7 +207,7 @@ static void exynos4_mct_comp0_stop(void)
 {
         unsigned int tcon;
 
-        tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
+        tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
         tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
 
         exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
@@ -180,7 +220,7 @@ static void exynos4_mct_comp0_start(enum clock_event_mode mode,
         unsigned int tcon;
         cycle_t comp_cycle;
 
-        tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
+        tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
 
         if (mode == CLOCK_EVT_MODE_PERIODIC) {
                 tcon |= MCT_G_TCON_COMP0_AUTO_INC;
@@ -257,11 +297,7 @@ static void exynos4_clockevent_init(void)
         mct_comp_device.cpumask = cpumask_of(0);
         clockevents_config_and_register(&mct_comp_device, clk_rate,
                                         0xf, 0xffffffff);
-
-        if (soc_is_exynos5250())
-                setup_irq(EXYNOS5_IRQ_MCT_G0, &mct_comp_event_irq);
-        else
-                setup_irq(EXYNOS4_IRQ_MCT_G0, &mct_comp_event_irq);
+        setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq);
 }
 
 #ifdef CONFIG_LOCAL_TIMERS
@@ -273,12 +309,12 @@ static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
 {
         unsigned long tmp;
         unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
-        void __iomem *addr = mevt->base + MCT_L_TCON_OFFSET;
+        unsigned long offset = mevt->base + MCT_L_TCON_OFFSET;
 
-        tmp = __raw_readl(addr);
+        tmp = __raw_readl(reg_base + offset);
         if (tmp & mask) {
                 tmp &= ~mask;
-                exynos4_mct_write(tmp, addr);
+                exynos4_mct_write(tmp, offset);
         }
 }
 
@@ -297,7 +333,7 @@ static void exynos4_mct_tick_start(unsigned long cycles,
         /* enable MCT tick interrupt */
         exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
 
-        tmp = __raw_readl(mevt->base + MCT_L_TCON_OFFSET);
+        tmp = __raw_readl(reg_base + mevt->base + MCT_L_TCON_OFFSET);
         tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
                MCT_L_TCON_INTERVAL_MODE;
         exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
@@ -349,7 +385,7 @@ static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
                 exynos4_mct_tick_stop(mevt);
 
         /* Clear the MCT tick interrupt */
-        if (__raw_readl(mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
+        if (__raw_readl(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
                 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
                 return 1;
         } else {
@@ -385,7 +421,6 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
 {
         struct mct_clock_event_device *mevt;
         unsigned int cpu = smp_processor_id();
-        int mct_lx_irq;
 
         mevt = this_cpu_ptr(&percpu_mct_tick);
         mevt->evt = evt;
@@ -406,21 +441,17 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
 
         if (mct_int_type == MCT_INT_SPI) {
                 if (cpu == 0) {
-                        mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L0 :
-                                                EXYNOS5_IRQ_MCT_L0;
                         mct_tick0_event_irq.dev_id = mevt;
-                        evt->irq = mct_lx_irq;
-                        setup_irq(mct_lx_irq, &mct_tick0_event_irq);
+                        evt->irq = mct_irqs[MCT_L0_IRQ];
+                        setup_irq(evt->irq, &mct_tick0_event_irq);
                 } else {
-                        mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L1 :
-                                                EXYNOS5_IRQ_MCT_L1;
                         mct_tick1_event_irq.dev_id = mevt;
-                        evt->irq = mct_lx_irq;
-                        setup_irq(mct_lx_irq, &mct_tick1_event_irq);
-                        irq_set_affinity(mct_lx_irq, cpumask_of(1));
+                        evt->irq = mct_irqs[MCT_L1_IRQ];
+                        setup_irq(evt->irq, &mct_tick1_event_irq);
+                        irq_set_affinity(evt->irq, cpumask_of(1));
                 }
         } else {
-                enable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, 0);
+                enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
         }
 
         return 0;
@@ -436,7 +467,7 @@ static void exynos4_local_timer_stop(struct clock_event_device *evt)
                 else
                         remove_irq(evt->irq, &mct_tick1_event_irq);
         else
-                disable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER);
+                disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);
 }
 
 static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = {
@@ -445,41 +476,80 @@ static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = {
 };
 #endif /* CONFIG_LOCAL_TIMERS */
 
-static void __init exynos4_timer_resources(void)
+static void __init exynos4_timer_resources(void __iomem *base)
 {
         struct clk *mct_clk;
         mct_clk = clk_get(NULL, "xtal");
 
         clk_rate = clk_get_rate(mct_clk);
 
+        reg_base = base;
+        if (!reg_base)
+                panic("%s: unable to ioremap mct address space\n", __func__);
+
 #ifdef CONFIG_LOCAL_TIMERS
         if (mct_int_type == MCT_INT_PPI) {
                 int err;
 
-                err = request_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER,
+                err = request_percpu_irq(mct_irqs[MCT_L0_IRQ],
                                          exynos4_mct_tick_isr, "MCT",
                                          &percpu_mct_tick);
                 WARN(err, "MCT: can't request IRQ %d (%d)\n",
-                     EXYNOS_IRQ_MCT_LOCALTIMER, err);
+                     mct_irqs[MCT_L0_IRQ], err);
         }
 
         local_timer_register(&exynos4_mct_tick_ops);
 #endif /* CONFIG_LOCAL_TIMERS */
 }
 
-void __init exynos4_timer_init(void)
+void __init mct_init(void)
 {
-        if (soc_is_exynos5440()) {
-                arch_timer_of_register();
-                return;
+        if (soc_is_exynos4210()) {
+                mct_irqs[MCT_G0_IRQ] = EXYNOS4_IRQ_MCT_G0;
+                mct_irqs[MCT_L0_IRQ] = EXYNOS4_IRQ_MCT_L0;
+                mct_irqs[MCT_L1_IRQ] = EXYNOS4_IRQ_MCT_L1;
+                mct_int_type = MCT_INT_SPI;
+        } else {
+                panic("unable to determine mct controller type\n");
         }
 
-        if ((soc_is_exynos4210()) || (soc_is_exynos5250()))
-                mct_int_type = MCT_INT_SPI;
-        else
-                mct_int_type = MCT_INT_PPI;
+        exynos4_timer_resources(S5P_VA_SYSTIMER);
+        exynos4_clocksource_init();
+        exynos4_clockevent_init();
+}
 
-        exynos4_timer_resources();
+static void __init mct_init_dt(struct device_node *np, unsigned int int_type)
+{
+        u32 nr_irqs, i;
+
+        mct_int_type = int_type;
+
+        /* This driver uses only one global timer interrupt */
+        mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ);
+
+        /*
+         * Find out the number of local irqs specified. The local
+         * timer irqs are specified after the four global timer
+         * irqs are specified.
+         */
+        nr_irqs = of_irq_count(np);
+        for (i = MCT_L0_IRQ; i < nr_irqs; i++)
+                mct_irqs[i] = irq_of_parse_and_map(np, i);
+
+        exynos4_timer_resources(of_iomap(np, 0));
         exynos4_clocksource_init();
         exynos4_clockevent_init();
 }
+
+
+static void __init mct_init_spi(struct device_node *np)
+{
+        return mct_init_dt(np, MCT_INT_SPI);
+}
+
+static void __init mct_init_ppi(struct device_node *np)
+{
+        return mct_init_dt(np, MCT_INT_PPI);
+}
+CLOCKSOURCE_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi);
+CLOCKSOURCE_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi);
diff --git a/drivers/clocksource/sunxi_timer.c b/drivers/clocksource/sunxi_timer.c
index 4086b9167159..0ce85e29769b 100644
--- a/drivers/clocksource/sunxi_timer.c
+++ b/drivers/clocksource/sunxi_timer.c
@@ -23,7 +23,7 @@
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/sunxi_timer.h>
-#include <linux/clk-provider.h>
+#include <linux/clk/sunxi.h>
 
 #define TIMER_CTL_REG           0x00
 #define TIMER_CTL_ENABLE                (1 << 0)
@@ -123,7 +123,7 @@ void __init sunxi_timer_init(void)
         if (irq <= 0)
                 panic("Can't parse IRQ");
 
-        of_clk_init(NULL);
+        sunxi_init_clocks();
 
         clk = of_clk_get(node, 0);
         if (IS_ERR(clk))
diff --git a/drivers/clocksource/tegra20_timer.c b/drivers/clocksource/tegra20_timer.c
index 2e4d8a666c36..ae877b021b54 100644
--- a/drivers/clocksource/tegra20_timer.c
+++ b/drivers/clocksource/tegra20_timer.c
@@ -172,7 +172,7 @@ static void __init tegra20_init_timer(struct device_node *np)
                 BUG();
         }
 
-        clk = clk_get_sys("timer", NULL);
+        clk = of_clk_get(np, 0);
         if (IS_ERR(clk)) {
                 pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n");
                 rate = 12000000;
@@ -235,7 +235,7 @@ static void __init tegra20_init_rtc(struct device_node *np)
          * rtc registers are used by read_persistent_clock, keep the rtc clock
          * enabled
          */
-        clk = clk_get_sys("rtc-tegra", NULL);
+        clk = of_clk_get(np, 0);
         if (IS_ERR(clk))
                 pr_warn("Unable to get rtc-tegra clock\n");
         else
diff --git a/drivers/cpufreq/cpufreq-cpu0.c b/drivers/cpufreq/cpufreq-cpu0.c
index 4e5b7fb8927c..37d23a0f8c56 100644
--- a/drivers/cpufreq/cpufreq-cpu0.c
+++ b/drivers/cpufreq/cpufreq-cpu0.c
@@ -178,10 +178,16 @@ static struct cpufreq_driver cpu0_cpufreq_driver = {
 
 static int cpu0_cpufreq_probe(struct platform_device *pdev)
 {
-        struct device_node *np;
+        struct device_node *np, *parent;
         int ret;
 
-        for_each_child_of_node(of_find_node_by_path("/cpus"), np) {
+        parent = of_find_node_by_path("/cpus");
+        if (!parent) {
+                pr_err("failed to find OF /cpus\n");
+                return -ENOENT;
+        }
+
+        for_each_child_of_node(parent, np) {
                 if (of_get_property(np, "operating-points", NULL))
                         break;
         }
diff --git a/drivers/cpufreq/cpufreq_governor.h b/drivers/cpufreq/cpufreq_governor.h
index 46bde01eee62..cc4bd2f6838a 100644
--- a/drivers/cpufreq/cpufreq_governor.h
+++ b/drivers/cpufreq/cpufreq_governor.h
@@ -14,8 +14,8 @@
  * published by the Free Software Foundation.
  */
 
-#ifndef _CPUFREQ_GOVERNER_H
-#define _CPUFREQ_GOVERNER_H
+#ifndef _CPUFREQ_GOVERNOR_H
+#define _CPUFREQ_GOVERNOR_H
 
 #include <linux/cpufreq.h>
 #include <linux/kobject.h>
@@ -175,4 +175,4 @@ bool need_load_eval(struct cpu_dbs_common_info *cdbs,
                 unsigned int sampling_rate);
 int cpufreq_governor_dbs(struct dbs_data *dbs_data,
                 struct cpufreq_policy *policy, unsigned int event);
-#endif /* _CPUFREQ_GOVERNER_H */
+#endif /* _CPUFREQ_GOVERNOR_H */
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 80b69971cf28..aeaea32bcfda 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -83,6 +83,7 @@ config INTEL_IOP_ADMA
 
 config DW_DMAC
         tristate "Synopsys DesignWare AHB DMA support"
+        depends on GENERIC_HARDIRQS
         select DMA_ENGINE
         default y if CPU_AT32AP7000
         help
diff --git a/drivers/eisa/pci_eisa.c b/drivers/eisa/pci_eisa.c
index cdae207028a7..6c3fca97d346 100644
--- a/drivers/eisa/pci_eisa.c
+++ b/drivers/eisa/pci_eisa.c
@@ -19,10 +19,10 @@
 /* There is only *one* pci_eisa device per machine, right ? */
 static struct eisa_root_device pci_eisa_root;
 
-static int __init pci_eisa_init(struct pci_dev *pdev,
-                                const struct pci_device_id *ent)
+static int __init pci_eisa_init(struct pci_dev *pdev)
 {
-        int rc;
+        int rc, i;
+        struct resource *res, *bus_res = NULL;
 
         if ((rc = pci_enable_device (pdev))) {
                 printk (KERN_ERR "pci_eisa : Could not enable device %s\n",
@@ -30,9 +30,30 @@ static int __init pci_eisa_init(struct pci_dev *pdev,
                 return rc;
         }
 
+        /*
+         * The Intel 82375 PCI-EISA bridge is a subtractive-decode PCI
+         * device, so the resources available on EISA are the same as those
+         * available on the 82375 bus.  This works the same as a PCI-PCI
+         * bridge in subtractive-decode mode (see pci_read_bridge_bases()).
+         * We assume other PCI-EISA bridges are similar.
+         *
+         * eisa_root_register() can only deal with a single io port resource,
+        *  so we use the first valid io port resource.
+         */
+        pci_bus_for_each_resource(pdev->bus, res, i)
+                if (res && (res->flags & IORESOURCE_IO)) {
+                        bus_res = res;
+                        break;
+                }
+
+        if (!bus_res) {
+                dev_err(&pdev->dev, "No resources available\n");
+                return -1;
+        }
+
         pci_eisa_root.dev              = &pdev->dev;
-        pci_eisa_root.res              = pdev->bus->resource[0];
-        pci_eisa_root.bus_base_addr    = pdev->bus->resource[0]->start;
+        pci_eisa_root.res              = bus_res;
+        pci_eisa_root.bus_base_addr    = bus_res->start;
         pci_eisa_root.slots            = EISA_MAX_SLOTS;
         pci_eisa_root.dma_mask         = pdev->dma_mask;
         dev_set_drvdata(pci_eisa_root.dev, &pci_eisa_root);
@@ -45,22 +66,26 @@ static int __init pci_eisa_init(struct pci_dev *pdev,
         return 0;
 }
 
-static struct pci_device_id pci_eisa_pci_tbl[] = {
-        { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
-          PCI_CLASS_BRIDGE_EISA << 8, 0xffff00, 0 },
-        { 0, }
-};
+/*
+ * We have to call pci_eisa_init_early() before pnpacpi_init()/isapnp_init().
+ *   Otherwise pnp resource will get enabled early and could prevent eisa
+ *   to be initialized.
+ * Also need to make sure pci_eisa_init_early() is called after
+ * x86/pci_subsys_init().
+ * So need to use subsys_initcall_sync with it.
+ */
+static int __init pci_eisa_init_early(void)
+{
+        struct pci_dev *dev = NULL;
+        int ret;
 
-static struct pci_driver __refdata pci_eisa_driver = {
-        .name           = "pci_eisa",
-        .id_table       = pci_eisa_pci_tbl,
-        .probe          = pci_eisa_init,
-};
+        for_each_pci_dev(dev)
+                if ((dev->class >> 8) == PCI_CLASS_BRIDGE_EISA) {
+                        ret = pci_eisa_init(dev);
+                        if (ret)
+                                return ret;
+                }
 
-static int __init pci_eisa_init_module (void)
-{
-        return pci_register_driver (&pci_eisa_driver);
+        return 0;
 }
-
-device_initcall(pci_eisa_init_module);
-MODULE_DEVICE_TABLE(pci, pci_eisa_pci_tbl);
+subsys_initcall_sync(pci_eisa_init_early);
diff --git a/drivers/gpio/gpio-ich.c b/drivers/gpio/gpio-ich.c
index f9dbd503fc40..de3c317bd3e2 100644
--- a/drivers/gpio/gpio-ich.c
+++ b/drivers/gpio/gpio-ich.c
@@ -214,7 +214,7 @@ static int ichx_gpio_request(struct gpio_chip *chip, unsigned nr)
          * If it can't be trusted, assume that the pin can be used as a GPIO.
          */
         if (ichx_priv.desc->use_sel_ignore[nr / 32] & (1 << (nr & 0x1f)))
-                return 1;
+                return 0;
 
         return ichx_read_bit(GPIO_USE_SEL, nr) ? 0 : -ENODEV;
 }
diff --git a/drivers/gpio/gpio-stmpe.c b/drivers/gpio/gpio-stmpe.c
index 770476a9da87..3ce5bc38ac31 100644
--- a/drivers/gpio/gpio-stmpe.c
+++ b/drivers/gpio/gpio-stmpe.c
@@ -307,11 +307,15 @@ static const struct irq_domain_ops stmpe_gpio_irq_simple_ops = {
         .xlate = irq_domain_xlate_twocell,
 };
 
-static int stmpe_gpio_irq_init(struct stmpe_gpio *stmpe_gpio)
+static int stmpe_gpio_irq_init(struct stmpe_gpio *stmpe_gpio,
+                struct device_node *np)
 {
-        int base = stmpe_gpio->irq_base;
+        int base = 0;
 
-        stmpe_gpio->domain = irq_domain_add_simple(NULL,
+        if (!np)
+                base = stmpe_gpio->irq_base;
+
+        stmpe_gpio->domain = irq_domain_add_simple(np,
                                 stmpe_gpio->chip.ngpio, base,
                                 &stmpe_gpio_irq_simple_ops, stmpe_gpio);
         if (!stmpe_gpio->domain) {
@@ -346,6 +350,9 @@ static int stmpe_gpio_probe(struct platform_device *pdev)
         stmpe_gpio->chip = template_chip;
         stmpe_gpio->chip.ngpio = stmpe->num_gpios;
         stmpe_gpio->chip.dev = &pdev->dev;
+#ifdef CONFIG_OF
+        stmpe_gpio->chip.of_node = np;
+#endif
         stmpe_gpio->chip.base = pdata ? pdata->gpio_base : -1;
 
         if (pdata)
@@ -366,7 +373,7 @@ static int stmpe_gpio_probe(struct platform_device *pdev)
                 goto out_free;
 
         if (irq >= 0) {
-                ret = stmpe_gpio_irq_init(stmpe_gpio);
+                ret = stmpe_gpio_irq_init(stmpe_gpio, np);
                 if (ret)
                         goto out_disable;
 
diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
index 414ad912232f..e3956359202c 100644
--- a/drivers/gpio/gpio-tegra.c
+++ b/drivers/gpio/gpio-tegra.c
@@ -72,6 +72,7 @@ struct tegra_gpio_bank {
         u32 oe[4];
         u32 int_enb[4];
         u32 int_lvl[4];
+        u32 wake_enb[4];
 #endif
 };
 
@@ -333,15 +334,31 @@ static int tegra_gpio_suspend(struct device *dev)
                         bank->oe[p] = tegra_gpio_readl(GPIO_OE(gpio));
                         bank->int_enb[p] = tegra_gpio_readl(GPIO_INT_ENB(gpio));
                         bank->int_lvl[p] = tegra_gpio_readl(GPIO_INT_LVL(gpio));
+
+                        /* Enable gpio irq for wake up source */
+                        tegra_gpio_writel(bank->wake_enb[p],
+                                          GPIO_INT_ENB(gpio));
                 }
         }
         local_irq_restore(flags);
         return 0;
 }
 
-static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable)
+static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
 {
         struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
+        int gpio = d->hwirq;
+        u32 port, bit, mask;
+
+        port = GPIO_PORT(gpio);
+        bit = GPIO_BIT(gpio);
+        mask = BIT(bit);
+
+        if (enable)
+                bank->wake_enb[port] |= mask;
+        else
+                bank->wake_enb[port] &= ~mask;
+
         return irq_set_irq_wake(bank->irq, enable);
 }
 #endif
@@ -353,7 +370,7 @@ static struct irq_chip tegra_gpio_irq_chip = {
         .irq_unmask     = tegra_gpio_irq_unmask,
         .irq_set_type   = tegra_gpio_irq_set_type,
 #ifdef CONFIG_PM_SLEEP
-        .irq_set_wake   = tegra_gpio_wake_enable,
+        .irq_set_wake   = tegra_gpio_irq_set_wake,
 #endif
 };
 
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 792c3e3795ca..dd64a06dc5b4 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -2326,7 +2326,6 @@ int drm_mode_addfb(struct drm_device *dev,
         fb = dev->mode_config.funcs->fb_create(dev, file_priv, &r);
         if (IS_ERR(fb)) {
                 DRM_DEBUG_KMS("could not create framebuffer\n");
-                drm_modeset_unlock_all(dev);
                 return PTR_ERR(fb);
         }
 
@@ -2506,7 +2505,6 @@ int drm_mode_addfb2(struct drm_device *dev,
         fb = dev->mode_config.funcs->fb_create(dev, file_priv, r);
         if (IS_ERR(fb)) {
                 DRM_DEBUG_KMS("could not create framebuffer\n");
-                drm_modeset_unlock_all(dev);
                 return PTR_ERR(fb);
         }
 
diff --git a/drivers/gpu/drm/drm_fops.c b/drivers/gpu/drm/drm_fops.c
index 13fdcd10a605..429e07d0b0f1 100644
--- a/drivers/gpu/drm/drm_fops.c
+++ b/drivers/gpu/drm/drm_fops.c
@@ -123,6 +123,7 @@ int drm_open(struct inode *inode, struct file *filp)
         int retcode = 0;
         int need_setup = 0;
         struct address_space *old_mapping;
+        struct address_space *old_imapping;
 
         minor = idr_find(&drm_minors_idr, minor_id);
         if (!minor)
@@ -137,6 +138,7 @@ int drm_open(struct inode *inode, struct file *filp)
         if (!dev->open_count++)
                 need_setup = 1;
         mutex_lock(&dev->struct_mutex);
+        old_imapping = inode->i_mapping;
         old_mapping = dev->dev_mapping;
         if (old_mapping == NULL)
                 dev->dev_mapping = &inode->i_data;
@@ -159,8 +161,8 @@ int drm_open(struct inode *inode, struct file *filp)
 
 err_undo:
         mutex_lock(&dev->struct_mutex);
-        filp->f_mapping = old_mapping;
-        inode->i_mapping = old_mapping;
+        filp->f_mapping = old_imapping;
+        inode->i_mapping = old_imapping;
         iput(container_of(dev->dev_mapping, struct inode, i_data));
         dev->dev_mapping = old_mapping;
         mutex_unlock(&dev->struct_mutex);
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 3b11ab0fbc96..9a48e1a2d417 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -57,7 +57,7 @@ eb_create(struct drm_i915_gem_execbuffer2 *args)
         if (eb == NULL) {
                 int size = args->buffer_count;
                 int count = PAGE_SIZE / sizeof(struct hlist_head) / 2;
-                BUILD_BUG_ON(!is_power_of_2(PAGE_SIZE / sizeof(struct hlist_head)));
+                BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head));
                 while (count > 2*size)
                         count >>= 1;
                 eb = kzalloc(count*sizeof(struct hlist_head) +
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 32a3693905ec..1ce45a0a2d3e 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -45,6 +45,9 @@
 
 struct intel_crt {
         struct intel_encoder base;
+        /* DPMS state is stored in the connector, which we need in the
+         * encoder's enable/disable callbacks */
+        struct intel_connector *connector;
         bool force_hotplug_required;
         u32 adpa_reg;
 };
@@ -81,29 +84,6 @@ static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
         return true;
 }
 
-static void intel_disable_crt(struct intel_encoder *encoder)
-{
-        struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
-        struct intel_crt *crt = intel_encoder_to_crt(encoder);
-        u32 temp;
-
-        temp = I915_READ(crt->adpa_reg);
-        temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
-        temp &= ~ADPA_DAC_ENABLE;
-        I915_WRITE(crt->adpa_reg, temp);
-}
-
-static void intel_enable_crt(struct intel_encoder *encoder)
-{
-        struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
-        struct intel_crt *crt = intel_encoder_to_crt(encoder);
-        u32 temp;
-
-        temp = I915_READ(crt->adpa_reg);
-        temp |= ADPA_DAC_ENABLE;
-        I915_WRITE(crt->adpa_reg, temp);
-}
-
 /* Note: The caller is required to filter out dpms modes not supported by the
  * platform. */
 static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
@@ -135,6 +115,19 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
         I915_WRITE(crt->adpa_reg, temp);
 }
 
+static void intel_disable_crt(struct intel_encoder *encoder)
+{
+        intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF);
+}
+
+static void intel_enable_crt(struct intel_encoder *encoder)
+{
+        struct intel_crt *crt = intel_encoder_to_crt(encoder);
+
+        intel_crt_set_dpms(encoder, crt->connector->base.dpms);
+}
+
+
 static void intel_crt_dpms(struct drm_connector *connector, int mode)
 {
         struct drm_device *dev = connector->dev;
@@ -746,6 +739,7 @@ void intel_crt_init(struct drm_device *dev)
         }
 
         connector = &intel_connector->base;
+        crt->connector = intel_connector;
         drm_connector_init(dev, &intel_connector->base,
                            &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
 
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index d7d4afe01341..8fc93f90a7cd 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2559,12 +2559,15 @@ void intel_dp_encoder_destroy(struct drm_encoder *encoder)
 {
         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
         struct intel_dp *intel_dp = &intel_dig_port->dp;
+        struct drm_device *dev = intel_dp_to_dev(intel_dp);
 
         i2c_del_adapter(&intel_dp->adapter);
         drm_encoder_cleanup(encoder);
         if (is_edp(intel_dp)) {
                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
+                mutex_lock(&dev->mode_config.mutex);
                 ironlake_panel_vdd_off_sync(intel_dp);
+                mutex_unlock(&dev->mode_config.mutex);
         }
         kfree(intel_dig_port);
 }
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/base.c b/drivers/gpu/drm/nouveau/core/subdev/bios/base.c
index e816f06637a7..0e2c1a4f1659 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/base.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/bios/base.c
@@ -248,6 +248,22 @@ nouveau_bios_shadow_pci(struct nouveau_bios *bios)
         }
 }
 
+static void
+nouveau_bios_shadow_platform(struct nouveau_bios *bios)
+{
+        struct pci_dev *pdev = nv_device(bios)->pdev;
+        size_t size;
+
+        void __iomem *rom = pci_platform_rom(pdev, &size);
+        if (rom && size) {
+                bios->data = kmalloc(size, GFP_KERNEL);
+                if (bios->data) {
+                        memcpy_fromio(bios->data, rom, size);
+                        bios->size = size;
+                }
+        }
+}
+
 static int
 nouveau_bios_score(struct nouveau_bios *bios, const bool writeable)
 {
@@ -288,6 +304,7 @@ nouveau_bios_shadow(struct nouveau_bios *bios)
                 { "PROM", nouveau_bios_shadow_prom, false, 0, 0, NULL },
                 { "ACPI", nouveau_bios_shadow_acpi, true, 0, 0, NULL },
                 { "PCIROM", nouveau_bios_shadow_pci, true, 0, 0, NULL },
+                { "PLATFORM", nouveau_bios_shadow_platform, true, 0, 0, NULL },
                 {}
         };
         struct methods *mthd, *best;
diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.c b/drivers/gpu/drm/nouveau/nouveau_abi16.c
index 3b6dc883e150..5eb3e0da7c6e 100644
--- a/drivers/gpu/drm/nouveau/nouveau_abi16.c
+++ b/drivers/gpu/drm/nouveau/nouveau_abi16.c
@@ -391,7 +391,7 @@ nouveau_abi16_ioctl_notifierobj_alloc(ABI16_IOCTL_ARGS)
         struct nouveau_drm *drm = nouveau_drm(dev);
         struct nouveau_device *device = nv_device(drm->device);
         struct nouveau_abi16 *abi16 = nouveau_abi16_get(file_priv, dev);
-        struct nouveau_abi16_chan *chan, *temp;
+        struct nouveau_abi16_chan *chan = NULL, *temp;
         struct nouveau_abi16_ntfy *ntfy;
         struct nouveau_object *object;
         struct nv_dma_class args = {};
@@ -404,10 +404,11 @@ nouveau_abi16_ioctl_notifierobj_alloc(ABI16_IOCTL_ARGS)
         if (unlikely(nv_device(abi16->device)->card_type >= NV_C0))
                 return nouveau_abi16_put(abi16, -EINVAL);
 
-        list_for_each_entry_safe(chan, temp, &abi16->channels, head) {
-                if (chan->chan->handle == (NVDRM_CHAN | info->channel))
+        list_for_each_entry(temp, &abi16->channels, head) {
+                if (temp->chan->handle == (NVDRM_CHAN | info->channel)) {
+                        chan = temp;
                         break;
-                chan = NULL;
+                }
         }
 
         if (!chan)
@@ -459,17 +460,18 @@ nouveau_abi16_ioctl_gpuobj_free(ABI16_IOCTL_ARGS)
 {
         struct drm_nouveau_gpuobj_free *fini = data;
         struct nouveau_abi16 *abi16 = nouveau_abi16_get(file_priv, dev);
-        struct nouveau_abi16_chan *chan, *temp;
+        struct nouveau_abi16_chan *chan = NULL, *temp;
         struct nouveau_abi16_ntfy *ntfy;
         int ret;
 
         if (unlikely(!abi16))
                 return -ENOMEM;
 
-        list_for_each_entry_safe(chan, temp, &abi16->channels, head) {
-                if (chan->chan->handle == (NVDRM_CHAN | fini->channel))
+        list_for_each_entry(temp, &abi16->channels, head) {
+                if (temp->chan->handle == (NVDRM_CHAN | fini->channel)) {
+                        chan = temp;
                         break;
-                chan = NULL;
+                }
         }
 
         if (!chan)
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c
index d1099365bfc1..c95decf543e9 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
@@ -72,11 +72,25 @@ module_param_named(modeset, nouveau_modeset, int, 0400);
 static struct drm_driver driver;
 
 static int
+nouveau_drm_vblank_handler(struct nouveau_eventh *event, int head)
+{
+        struct nouveau_drm *drm =
+                container_of(event, struct nouveau_drm, vblank[head]);
+        drm_handle_vblank(drm->dev, head);
+        return NVKM_EVENT_KEEP;
+}
+
+static int
 nouveau_drm_vblank_enable(struct drm_device *dev, int head)
 {
         struct nouveau_drm *drm = nouveau_drm(dev);
         struct nouveau_disp *pdisp = nouveau_disp(drm->device);
-        nouveau_event_get(pdisp->vblank, head, &drm->vblank);
+
+        if (WARN_ON_ONCE(head > ARRAY_SIZE(drm->vblank)))
+                return -EIO;
+        WARN_ON_ONCE(drm->vblank[head].func);
+        drm->vblank[head].func = nouveau_drm_vblank_handler;
+        nouveau_event_get(pdisp->vblank, head, &drm->vblank[head]);
         return 0;
 }
 
@@ -85,16 +99,11 @@ nouveau_drm_vblank_disable(struct drm_device *dev, int head)
 {
         struct nouveau_drm *drm = nouveau_drm(dev);
         struct nouveau_disp *pdisp = nouveau_disp(drm->device);
-        nouveau_event_put(pdisp->vblank, head, &drm->vblank);
-}
-
-static int
-nouveau_drm_vblank_handler(struct nouveau_eventh *event, int head)
-{
-        struct nouveau_drm *drm =
-                container_of(event, struct nouveau_drm, vblank);
-        drm_handle_vblank(drm->dev, head);
-        return NVKM_EVENT_KEEP;
+        if (drm->vblank[head].func)
+                nouveau_event_put(pdisp->vblank, head, &drm->vblank[head]);
+        else
+                WARN_ON_ONCE(1);
+        drm->vblank[head].func = NULL;
 }
 
 static u64
@@ -292,7 +301,6 @@ nouveau_drm_load(struct drm_device *dev, unsigned long flags)
 
         dev->dev_private = drm;
         drm->dev = dev;
-        drm->vblank.func = nouveau_drm_vblank_handler;
 
         INIT_LIST_HEAD(&drm->clients);
         spin_lock_init(&drm->tile.lock);
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.h b/drivers/gpu/drm/nouveau/nouveau_drm.h
index b25df374c901..9c39bafbef2c 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drm.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.h
@@ -113,7 +113,7 @@ struct nouveau_drm {
         struct nvbios vbios;
         struct nouveau_display *display;
         struct backlight_device *backlight;
-        struct nouveau_eventh vblank;
+        struct nouveau_eventh vblank[4];
 
         /* power management */
         struct nouveau_pm *pm;
diff --git a/drivers/gpu/drm/radeon/radeon_bios.c b/drivers/gpu/drm/radeon/radeon_bios.c
index b8015913d382..fa3c56fba294 100644
--- a/drivers/gpu/drm/radeon/radeon_bios.c
+++ b/drivers/gpu/drm/radeon/radeon_bios.c
@@ -99,6 +99,29 @@ static bool radeon_read_bios(struct radeon_device *rdev)
         return true;
 }
 
+static bool radeon_read_platform_bios(struct radeon_device *rdev)
+{
+        uint8_t __iomem *bios;
+        size_t size;
+
+        rdev->bios = NULL;
+
+        bios = pci_platform_rom(rdev->pdev, &size);
+        if (!bios) {
+                return false;
+        }
+
+        if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
+                return false;
+        }
+        rdev->bios = kmemdup(bios, size, GFP_KERNEL);
+        if (rdev->bios == NULL) {
+                return false;
+        }
+
+        return true;
+}
+
 #ifdef CONFIG_ACPI
 /* ATRM is used to get the BIOS on the discrete cards in
  * dual-gpu systems.
@@ -620,6 +643,9 @@ bool radeon_get_bios(struct radeon_device *rdev)
         if (r == false) {
                 r = radeon_read_disabled_bios(rdev);
         }
+        if (r == false) {
+                r = radeon_read_platform_bios(rdev);
+        }
         if (r == false || rdev->bios == NULL) {
                 DRM_ERROR("Unable to locate a BIOS ROM\n");
                 rdev->bios = NULL;
diff --git a/drivers/hid/hid-core.c b/drivers/hid/hid-core.c
index 512b01c04ea7..aa341d135867 100644
--- a/drivers/hid/hid-core.c
+++ b/drivers/hid/hid-core.c
@@ -2077,7 +2077,6 @@ static const struct hid_device_id hid_ignore_list[] = {
         { HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_HYBRID) },
         { HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_HEATCONTROL) },
         { HID_USB_DEVICE(USB_VENDOR_ID_MADCATZ, USB_DEVICE_ID_MADCATZ_BEATPAD) },
-        { HID_USB_DEVICE(USB_VENDOR_ID_MASTERKIT, USB_DEVICE_ID_MASTERKIT_MA901RADIO) },
         { HID_USB_DEVICE(USB_VENDOR_ID_MCC, USB_DEVICE_ID_MCC_PMD1024LS) },
         { HID_USB_DEVICE(USB_VENDOR_ID_MCC, USB_DEVICE_ID_MCC_PMD1208LS) },
         { HID_USB_DEVICE(USB_VENDOR_ID_MICROCHIP, USB_DEVICE_ID_PICKIT1) },
@@ -2244,6 +2243,18 @@ bool hid_ignore(struct hid_device *hdev)
                      hdev->product <= USB_DEVICE_ID_VELLEMAN_K8061_LAST))
                         return true;
                 break;
+        case USB_VENDOR_ID_ATMEL_V_USB:
+                /* Masterkit MA901 usb radio based on Atmel tiny85 chip and
+                 * it has the same USB ID as many Atmel V-USB devices. This
+                 * usb radio is handled by radio-ma901.c driver so we want
+                 * ignore the hid. Check the name, bus, product and ignore
+                 * if we have MA901 usb radio.
+                 */
+                if (hdev->product == USB_DEVICE_ID_ATMEL_V_USB &&
+                        hdev->bus == BUS_USB &&
+                        strncmp(hdev->name, "www.masterkit.ru MA901", 22) == 0)
+                        return true;
+                break;
         }
 
         if (hdev->type == HID_TYPE_USBMOUSE &&
diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h
index c4388776f4e4..5309fd5eb0eb 100644
--- a/drivers/hid/hid-ids.h
+++ b/drivers/hid/hid-ids.h
@@ -158,6 +158,8 @@
 #define USB_VENDOR_ID_ATMEL             0x03eb
 #define USB_DEVICE_ID_ATMEL_MULTITOUCH  0x211c
 #define USB_DEVICE_ID_ATMEL_MXT_DIGITIZER       0x2118
+#define USB_VENDOR_ID_ATMEL_V_USB       0x16c0
+#define USB_DEVICE_ID_ATMEL_V_USB       0x05df
 
 #define USB_VENDOR_ID_AUREAL            0x0755
 #define USB_DEVICE_ID_AUREAL_W01RN      0x2626
@@ -557,9 +559,6 @@
 #define USB_VENDOR_ID_MADCATZ           0x0738
 #define USB_DEVICE_ID_MADCATZ_BEATPAD   0x4540
 
-#define USB_VENDOR_ID_MASTERKIT                 0x16c0
-#define USB_DEVICE_ID_MASTERKIT_MA901RADIO      0x05df
-
 #define USB_VENDOR_ID_MCC               0x09db
 #define USB_DEVICE_ID_MCC_PMD1024LS     0x0076
 #define USB_DEVICE_ID_MCC_PMD1208LS     0x007a
diff --git a/drivers/hid/hid-magicmouse.c b/drivers/hid/hid-magicmouse.c
index f7f113ba083e..a8ce44296cfd 100644
--- a/drivers/hid/hid-magicmouse.c
+++ b/drivers/hid/hid-magicmouse.c
@@ -462,6 +462,21 @@ static int magicmouse_input_mapping(struct hid_device *hdev,
         return 0;
 }
 
+static void magicmouse_input_configured(struct hid_device *hdev,
+                struct hid_input *hi)
+
+{
+        struct magicmouse_sc *msc = hid_get_drvdata(hdev);
+
+        int ret = magicmouse_setup_input(msc->input, hdev);
+        if (ret) {
+                hid_err(hdev, "magicmouse setup input failed (%d)\n", ret);
+                /* clean msc->input to notify probe() of the failure */
+                msc->input = NULL;
+        }
+}
+
+
 static int magicmouse_probe(struct hid_device *hdev,
         const struct hid_device_id *id)
 {
@@ -493,15 +508,10 @@ static int magicmouse_probe(struct hid_device *hdev,
                 goto err_free;
         }
 
-        /* We do this after hid-input is done parsing reports so that
-         * hid-input uses the most natural button and axis IDs.
-         */
-        if (msc->input) {
-                ret = magicmouse_setup_input(msc->input, hdev);
-                if (ret) {
-                        hid_err(hdev, "magicmouse setup input failed (%d)\n", ret);
-                        goto err_stop_hw;
-                }
+        if (!msc->input) {
+                hid_err(hdev, "magicmouse input not registered\n");
+                ret = -ENOMEM;
+                goto err_stop_hw;
         }
 
         if (id->product == USB_DEVICE_ID_APPLE_MAGICMOUSE)
@@ -568,6 +578,7 @@ static struct hid_driver magicmouse_driver = {
         .remove = magicmouse_remove,
         .raw_event = magicmouse_raw_event,
         .input_mapping = magicmouse_input_mapping,
+        .input_configured = magicmouse_input_configured,
 };
 module_hid_driver(magicmouse_driver);
 
diff --git a/drivers/i2c/busses/i2c-designware-platdrv.c b/drivers/i2c/busses/i2c-designware-platdrv.c
index 0ceb6e1b0f65..e3085c487ace 100644
--- a/drivers/i2c/busses/i2c-designware-platdrv.c
+++ b/drivers/i2c/busses/i2c-designware-platdrv.c
@@ -182,7 +182,6 @@ static int dw_i2c_probe(struct platform_device *pdev)
         adap->algo = &i2c_dw_algo;
         adap->dev.parent = &pdev->dev;
         adap->dev.of_node = pdev->dev.of_node;
-        ACPI_HANDLE_SET(&adap->dev, ACPI_HANDLE(&pdev->dev));
 
         r = i2c_add_numbered_adapter(adap);
         if (r) {
diff --git a/drivers/infiniband/hw/qib/qib_sd7220.c b/drivers/infiniband/hw/qib/qib_sd7220.c
index 08a6c6d39e56..911205d3d5a0 100644
--- a/drivers/infiniband/hw/qib/qib_sd7220.c
+++ b/drivers/infiniband/hw/qib/qib_sd7220.c
@@ -44,7 +44,7 @@
 #include "qib.h"
 #include "qib_7220.h"
 
-#define SD7220_FW_NAME "intel/sd7220.fw"
+#define SD7220_FW_NAME "qlogic/sd7220.fw"
 MODULE_FIRMWARE(SD7220_FW_NAME);
 
 /*
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index e41ceb9bec22..154722aa26cb 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -2,6 +2,8 @@ obj-$(CONFIG_IRQCHIP)			+= irqchip.o
 
 obj-$(CONFIG_ARCH_BCM2835)              += irq-bcm2835.o
 obj-$(CONFIG_ARCH_EXYNOS)               += exynos-combiner.o
+obj-$(CONFIG_ARCH_MVEBU)                += irq-armada-370-xp.o
+obj-$(CONFIG_ARCH_S3C24XX)              += irq-s3c24xx.o
 obj-$(CONFIG_METAG)                     += irq-metag-ext.o
 obj-$(CONFIG_METAG_PERFCOUNTER_IRQS)    += irq-metag.o
 obj-$(CONFIG_ARCH_SUNXI)                += irq-sunxi.o
diff --git a/arch/arm/mach-mvebu/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c
index 274ff58271de..ad1e6422a732 100644
--- a/arch/arm/mach-mvebu/irq-armada-370-xp.c
+++ b/drivers/irqchip/irq-armada-370-xp.c
@@ -25,7 +25,9 @@
 #include <asm/mach/arch.h>
 #include <asm/exception.h>
 #include <asm/smp_plat.h>
-#include <asm/hardware/cache-l2x0.h>
+#include <asm/mach/irq.h>
+
+#include "irqchip.h"
 
 /* Interrupt Controller Registers Map */
 #define ARMADA_370_XP_INT_SET_MASK_OFFS         (0x48)
@@ -44,7 +46,11 @@
 
 #define ARMADA_370_XP_MAX_PER_CPU_IRQS          (28)
 
-#define ACTIVE_DOORBELLS                        (8)
+#define ARMADA_370_XP_TIMER0_PER_CPU_IRQ        (5)
+
+#define IPI_DOORBELL_START                      (0)
+#define IPI_DOORBELL_END                        (8)
+#define IPI_DOORBELL_MASK                       0xFF
 
 static DEFINE_RAW_SPINLOCK(irq_controller_lock);
 
@@ -62,7 +68,7 @@ static void armada_370_xp_irq_mask(struct irq_data *d)
 #ifdef CONFIG_SMP
         irq_hw_number_t hwirq = irqd_to_hwirq(d);
 
-        if (hwirq > ARMADA_370_XP_MAX_PER_CPU_IRQS)
+        if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
                 writel(hwirq, main_int_base +
                                 ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
         else
@@ -79,7 +85,7 @@ static void armada_370_xp_irq_unmask(struct irq_data *d)
 #ifdef CONFIG_SMP
         irq_hw_number_t hwirq = irqd_to_hwirq(d);
 
-        if (hwirq > ARMADA_370_XP_MAX_PER_CPU_IRQS)
+        if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
                 writel(hwirq, main_int_base +
                                 ARMADA_370_XP_INT_SET_ENABLE_OFFS);
         else
@@ -147,7 +153,7 @@ static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
         writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
         irq_set_status_flags(virq, IRQ_LEVEL);
 
-        if (hw < ARMADA_370_XP_MAX_PER_CPU_IRQS) {
+        if (hw == ARMADA_370_XP_TIMER0_PER_CPU_IRQ) {
                 irq_set_percpu_devid(virq);
                 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
                                         handle_percpu_devid_irq);
@@ -188,7 +194,7 @@ void armada_xp_mpic_smp_cpu_init(void)
         writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
 
         /* Enable first 8 IPIs */
-        writel((1 << ACTIVE_DOORBELLS) - 1, per_cpu_int_base +
+        writel(IPI_DOORBELL_MASK, per_cpu_int_base +
                 ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
 
         /* Unmask IPI interrupt */
@@ -201,46 +207,8 @@ static struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
         .xlate = irq_domain_xlate_onecell,
 };
 
-static int __init armada_370_xp_mpic_of_init(struct device_node *node,
-                                             struct device_node *parent)
-{
-        u32 control;
-
-        main_int_base = of_iomap(node, 0);
-        per_cpu_int_base = of_iomap(node, 1);
-
-        BUG_ON(!main_int_base);
-        BUG_ON(!per_cpu_int_base);
-
-        control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
-
-        armada_370_xp_mpic_domain =
-                irq_domain_add_linear(node, (control >> 2) & 0x3ff,
-                                &armada_370_xp_mpic_irq_ops, NULL);
-
-        if (!armada_370_xp_mpic_domain)
-                panic("Unable to add Armada_370_Xp MPIC irq domain (DT)\n");
-
-        irq_set_default_host(armada_370_xp_mpic_domain);
-
-#ifdef CONFIG_SMP
-        armada_xp_mpic_smp_cpu_init();
-
-        /*
-         * Set the default affinity from all CPUs to the boot cpu.
-         * This is required since the MPIC doesn't limit several CPUs
-         * from acknowledging the same interrupt.
-         */
-        cpumask_clear(irq_default_affinity);
-        cpumask_set_cpu(smp_processor_id(), irq_default_affinity);
-
-#endif
-
-        return 0;
-}
-
-asmlinkage void __exception_irq_entry armada_370_xp_handle_irq(struct pt_regs
-                                                               *regs)
+static asmlinkage void __exception_irq_entry
+armada_370_xp_handle_irq(struct pt_regs *regs)
 {
         u32 irqstat, irqnr;
 
@@ -265,13 +233,14 @@ asmlinkage void __exception_irq_entry armada_370_xp_handle_irq(struct pt_regs
 
                         ipimask = readl_relaxed(per_cpu_int_base +
                                                 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
-                                & 0xFF;
+                                & IPI_DOORBELL_MASK;
 
-                        writel(0x0, per_cpu_int_base +
+                        writel(~IPI_DOORBELL_MASK, per_cpu_int_base +
                                 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
 
                         /* Handle all pending doorbells */
-                        for (ipinr = 0; ipinr < ACTIVE_DOORBELLS; ipinr++) {
+                        for (ipinr = IPI_DOORBELL_START;
+                             ipinr < IPI_DOORBELL_END; ipinr++) {
                                 if (ipimask & (0x1 << ipinr))
                                         handle_IPI(ipinr, regs);
                         }
@@ -282,15 +251,44 @@ asmlinkage void __exception_irq_entry armada_370_xp_handle_irq(struct pt_regs
         } while (1);
 }
 
-static const struct of_device_id mpic_of_match[] __initconst = {
-        {.compatible = "marvell,mpic", .data = armada_370_xp_mpic_of_init},
-        {},
-};
-
-void __init armada_370_xp_init_irq(void)
+static int __init armada_370_xp_mpic_of_init(struct device_node *node,
+                                             struct device_node *parent)
 {
-        of_irq_init(mpic_of_match);
-#ifdef CONFIG_CACHE_L2X0
-        l2x0_of_init(0, ~0UL);
+        u32 control;
+
+        main_int_base = of_iomap(node, 0);
+        per_cpu_int_base = of_iomap(node, 1);
+
+        BUG_ON(!main_int_base);
+        BUG_ON(!per_cpu_int_base);
+
+        control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
+
+        armada_370_xp_mpic_domain =
+                irq_domain_add_linear(node, (control >> 2) & 0x3ff,
+                                &armada_370_xp_mpic_irq_ops, NULL);
+
+        if (!armada_370_xp_mpic_domain)
+                panic("Unable to add Armada_370_Xp MPIC irq domain (DT)\n");
+
+        irq_set_default_host(armada_370_xp_mpic_domain);
+
+#ifdef CONFIG_SMP
+        armada_xp_mpic_smp_cpu_init();
+
+        /*
+         * Set the default affinity from all CPUs to the boot cpu.
+         * This is required since the MPIC doesn't limit several CPUs
+         * from acknowledging the same interrupt.
+         */
+        cpumask_clear(irq_default_affinity);
+        cpumask_set_cpu(smp_processor_id(), irq_default_affinity);
+
 #endif
+
+        set_handle_irq(armada_370_xp_handle_irq);
+
+        return 0;
 }
+
+IRQCHIP_DECLARE(armada_370_xp_mpic, "marvell,mpic", armada_370_xp_mpic_of_init);
diff --git a/arch/arm/mach-s3c24xx/irq.c b/drivers/irqchip/irq-s3c24xx.c
index 3f3de7492094..5e40b3424df8 100644
--- a/arch/arm/mach-s3c24xx/irq.c
+++ b/drivers/irqchip/irq-s3c24xx.c
@@ -25,7 +25,11 @@
 #include <linux/ioport.h>
 #include <linux/device.h>
 #include <linux/irqdomain.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
 
+#include <asm/exception.h>
 #include <asm/mach/irq.h>
 
 #include <mach/regs-irq.h>
@@ -35,6 +39,8 @@
 #include <plat/regs-irqtype.h>
 #include <plat/pm.h>
 
+#include "irqchip.h"
+
 #define S3C_IRQTYPE_NONE        0
 #define S3C_IRQTYPE_EINT        1
 #define S3C_IRQTYPE_EDGE        2
@@ -42,6 +48,7 @@
 
 struct s3c_irq_data {
         unsigned int type;
+        unsigned long offset;
         unsigned long parent_irq;
 
         /* data gets filled during init */
@@ -68,23 +75,34 @@ struct s3c_irq_intc {
         struct s3c_irq_data     *irqs;
 };
 
+/*
+ * Array holding pointers to the global controller structs
+ * [0] ... main_intc
+ * [1] ... sub_intc
+ * [2] ... main_intc2 on s3c2416
+ */
+static struct s3c_irq_intc *s3c_intc[3];
+
 static void s3c_irq_mask(struct irq_data *data)
 {
-        struct s3c_irq_intc *intc = data->domain->host_data;
+        struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data);
+        struct s3c_irq_intc *intc = irq_data->intc;
         struct s3c_irq_intc *parent_intc = intc->parent;
-        struct s3c_irq_data *irq_data = &intc->irqs[data->hwirq];
         struct s3c_irq_data *parent_data;
         unsigned long mask;
         unsigned int irqno;
 
         mask = __raw_readl(intc->reg_mask);
-        mask |= (1UL << data->hwirq);
+        mask |= (1UL << irq_data->offset);
         __raw_writel(mask, intc->reg_mask);
 
-        if (parent_intc && irq_data->parent_irq) {
+        if (parent_intc) {
                 parent_data = &parent_intc->irqs[irq_data->parent_irq];
 
-                /* check to see if we need to mask the parent IRQ */
+                /* check to see if we need to mask the parent IRQ
+                 * The parent_irq is always in main_intc, so the hwirq
+                 * for find_mapping does not need an offset in any case.
+                 */
                 if ((mask & parent_data->sub_bits) == parent_data->sub_bits) {
                         irqno = irq_find_mapping(parent_intc->domain,
                                          irq_data->parent_irq);
@@ -95,17 +113,17 @@ static void s3c_irq_mask(struct irq_data *data)
 
 static void s3c_irq_unmask(struct irq_data *data)
 {
-        struct s3c_irq_intc *intc = data->domain->host_data;
+        struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data);
+        struct s3c_irq_intc *intc = irq_data->intc;
         struct s3c_irq_intc *parent_intc = intc->parent;
-        struct s3c_irq_data *irq_data = &intc->irqs[data->hwirq];
         unsigned long mask;
         unsigned int irqno;
 
         mask = __raw_readl(intc->reg_mask);
-        mask &= ~(1UL << data->hwirq);
+        mask &= ~(1UL << irq_data->offset);
         __raw_writel(mask, intc->reg_mask);
 
-        if (parent_intc && irq_data->parent_irq) {
+        if (parent_intc) {
                 irqno = irq_find_mapping(parent_intc->domain,
                                          irq_data->parent_irq);
                 s3c_irq_unmask(irq_get_irq_data(irqno));
@@ -114,14 +132,37 @@ static void s3c_irq_unmask(struct irq_data *data)
 
 static inline void s3c_irq_ack(struct irq_data *data)
 {
-        struct s3c_irq_intc *intc = data->domain->host_data;
-        unsigned long bitval = 1UL << data->hwirq;
+        struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data);
+        struct s3c_irq_intc *intc = irq_data->intc;
+        unsigned long bitval = 1UL << irq_data->offset;
 
         __raw_writel(bitval, intc->reg_pending);
         if (intc->reg_intpnd)
                 __raw_writel(bitval, intc->reg_intpnd);
 }
 
+static int s3c_irq_type(struct irq_data *data, unsigned int type)
+{
+        switch (type) {
+        case IRQ_TYPE_NONE:
+                break;
+        case IRQ_TYPE_EDGE_RISING:
+        case IRQ_TYPE_EDGE_FALLING:
+        case IRQ_TYPE_EDGE_BOTH:
+                irq_set_handler(data->irq, handle_edge_irq);
+                break;
+        case IRQ_TYPE_LEVEL_LOW:
+        case IRQ_TYPE_LEVEL_HIGH:
+                irq_set_handler(data->irq, handle_level_irq);
+                break;
+        default:
+                pr_err("No such irq type %d", type);
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
 static int s3c_irqext_type_set(void __iomem *gpcon_reg,
                                void __iomem *extint_reg,
                                unsigned long gpcon_offset,
@@ -227,6 +268,7 @@ static struct irq_chip s3c_irq_chip = {
         .irq_ack        = s3c_irq_ack,
         .irq_mask       = s3c_irq_mask,
         .irq_unmask     = s3c_irq_unmask,
+        .irq_set_type   = s3c_irq_type,
         .irq_set_wake   = s3c_irq_wake
 };
 
@@ -235,6 +277,7 @@ static struct irq_chip s3c_irq_level_chip = {
         .irq_mask       = s3c_irq_mask,
         .irq_unmask     = s3c_irq_unmask,
         .irq_ack        = s3c_irq_ack,
+        .irq_set_type   = s3c_irq_type,
 };
 
 static struct irq_chip s3c_irqext_chip = {
@@ -258,12 +301,19 @@ static struct irq_chip s3c_irq_eint0t4 = {
 static void s3c_irq_demux(unsigned int irq, struct irq_desc *desc)
 {
         struct irq_chip *chip = irq_desc_get_chip(desc);
-        struct s3c_irq_intc *intc = desc->irq_data.domain->host_data;
-        struct s3c_irq_data *irq_data = &intc->irqs[desc->irq_data.hwirq];
+        struct s3c_irq_data *irq_data = irq_desc_get_chip_data(desc);
+        struct s3c_irq_intc *intc = irq_data->intc;
         struct s3c_irq_intc *sub_intc = irq_data->sub_intc;
         unsigned long src;
         unsigned long msk;
         unsigned int n;
+        unsigned int offset;
+
+        /* we're using individual domains for the non-dt case
+         * and one big domain for the dt case where the subintc
+         * starts at hwirq number 32.
+         */
+        offset = (intc->domain->of_node) ? 32 : 0;
 
         chained_irq_enter(chip, desc);
 
@@ -276,12 +326,64 @@ static void s3c_irq_demux(unsigned int irq, struct irq_desc *desc)
         while (src) {
                 n = __ffs(src);
                 src &= ~(1 << n);
-                generic_handle_irq(irq_find_mapping(sub_intc->domain, n));
+                irq = irq_find_mapping(sub_intc->domain, offset + n);
+                generic_handle_irq(irq);
         }
 
         chained_irq_exit(chip, desc);
 }
 
+static inline int s3c24xx_handle_intc(struct s3c_irq_intc *intc,
+                                      struct pt_regs *regs, int intc_offset)
+{
+        int pnd;
+        int offset;
+        int irq;
+
+        pnd = __raw_readl(intc->reg_intpnd);
+        if (!pnd)
+                return false;
+
+        /* non-dt machines use individual domains */
+        if (!intc->domain->of_node)
+                intc_offset = 0;
+
+        /* We have a problem that the INTOFFSET register does not always
+         * show one interrupt. Occasionally we get two interrupts through
+         * the prioritiser, and this causes the INTOFFSET register to show
+         * what looks like the logical-or of the two interrupt numbers.
+         *
+         * Thanks to Klaus, Shannon, et al for helping to debug this problem
+         */
+        offset = __raw_readl(intc->reg_intpnd + 4);
+
+        /* Find the bit manually, when the offset is wrong.
+         * The pending register only ever contains the one bit of the next
+         * interrupt to handle.
+         */
+        if (!(pnd & (1 << offset)))
+                offset =  __ffs(pnd);
+
+        irq = irq_find_mapping(intc->domain, intc_offset + offset);
+        handle_IRQ(irq, regs);
+        return true;
+}
+
+asmlinkage void __exception_irq_entry s3c24xx_handle_irq(struct pt_regs *regs)
+{
+        do {
+                if (likely(s3c_intc[0]))
+                        if (s3c24xx_handle_intc(s3c_intc[0], regs, 0))
+                                continue;
+
+                if (s3c_intc[2])
+                        if (s3c24xx_handle_intc(s3c_intc[2], regs, 64))
+                                continue;
+
+                break;
+        } while (1);
+}
+
 #ifdef CONFIG_FIQ
 /**
  * s3c24xx_set_fiq - set the FIQ routing
@@ -324,18 +426,11 @@ static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq,
         struct s3c_irq_data *parent_irq_data;
         unsigned int irqno;
 
-        if (!intc) {
-                pr_err("irq-s3c24xx: no controller found for hwirq %lu\n", hw);
-                return -EINVAL;
-        }
-
-        if (!irq_data) {
-                pr_err("irq-s3c24xx: no irq data found for hwirq %lu\n", hw);
-                return -EINVAL;
-        }
-
         /* attach controller pointer to irq_data */
         irq_data->intc = intc;
+        irq_data->offset = hw;
+
+        parent_intc = intc->parent;
 
         /* set handler and flags */
         switch (irq_data->type) {
@@ -345,7 +440,7 @@ static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq,
                 /* On the S3C2412, the EINT0to3 have a parent irq
                  * but need the s3c_irq_eint0t4 chip
                  */
-                if (irq_data->parent_irq && (!soc_is_s3c2412() || hw >= 4))
+                if (parent_intc && (!soc_is_s3c2412() || hw >= 4))
                         irq_set_chip_and_handler(virq, &s3c_irqext_chip,
                                                  handle_edge_irq);
                 else
@@ -353,8 +448,7 @@ static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq,
                                                  handle_edge_irq);
                 break;
         case S3C_IRQTYPE_EDGE:
-                if (irq_data->parent_irq ||
-                    intc->reg_pending == S3C2416_SRCPND2)
+                if (parent_intc || intc->reg_pending == S3C2416_SRCPND2)
                         irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
                                                  handle_edge_irq);
                 else
@@ -362,7 +456,7 @@ static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq,
                                                  handle_edge_irq);
                 break;
         case S3C_IRQTYPE_LEVEL:
-                if (irq_data->parent_irq)
+                if (parent_intc)
                         irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
                                                  handle_level_irq);
                 else
@@ -373,23 +467,19 @@ static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq,
                 pr_err("irq-s3c24xx: unsupported irqtype %d\n", irq_data->type);
                 return -EINVAL;
         }
+
+        irq_set_chip_data(virq, irq_data);
+
         set_irq_flags(virq, IRQF_VALID);
 
-        if (irq_data->parent_irq) {
-                parent_intc = intc->parent;
-                if (!parent_intc) {
-                        pr_err("irq-s3c24xx: no parent controller found for hwirq %lu\n",
-                               hw);
+        if (parent_intc && irq_data->type != S3C_IRQTYPE_NONE) {
+                if (irq_data->parent_irq > 31) {
+                        pr_err("irq-s3c24xx: parent irq %lu is out of range\n",
+                               irq_data->parent_irq);
                         goto err;
                 }
 
                 parent_irq_data = &parent_intc->irqs[irq_data->parent_irq];
-                if (!irq_data) {
-                        pr_err("irq-s3c24xx: no irq data found for hwirq %lu\n",
-                               hw);
-                        goto err;
-                }
-
                 parent_irq_data->sub_intc = intc;
                 parent_irq_data->sub_bits |= (1UL << hw);
 
@@ -444,7 +534,7 @@ static void s3c24xx_clear_intc(struct s3c_irq_intc *intc)
         }
 }
 
-struct s3c_irq_intc *s3c24xx_init_intc(struct device_node *np,
+static struct s3c_irq_intc *s3c24xx_init_intc(struct device_node *np,
                                        struct s3c_irq_data *irq_data,
                                        struct s3c_irq_intc *parent,
                                        unsigned long address)
@@ -518,6 +608,8 @@ struct s3c_irq_intc *s3c24xx_init_intc(struct device_node *np,
                 goto err;
         }
 
+        set_handle_irq(s3c24xx_handle_irq);
+
         return intc;
 
 err:
@@ -525,12 +617,35 @@ err:
         return ERR_PTR(ret);
 }
 
-/* s3c24xx_init_irq
- *
- * Initialise S3C2410 IRQ system
-*/
+static struct s3c_irq_data init_eint[32] = {
+        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
+        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
+        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
+        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
+};
 
-static struct s3c_irq_data init_base[32] = {
+#ifdef CONFIG_CPU_S3C2410
+static struct s3c_irq_data init_s3c2410base[32] = {
         { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
         { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
         { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
@@ -565,34 +680,7 @@ static struct s3c_irq_data init_base[32] = {
         { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
 };
 
-static struct s3c_irq_data init_eint[32] = {
-        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
-        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
-        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
-        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
-};
-
-static struct s3c_irq_data init_subint[32] = {
+static struct s3c_irq_data init_s3c2410subint[32] = {
         { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
         { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
         { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
@@ -606,23 +694,24 @@ static struct s3c_irq_data init_subint[32] = {
         { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
 };
 
-void __init s3c24xx_init_irq(void)
+void __init s3c2410_init_irq(void)
 {
-        struct s3c_irq_intc *main_intc;
-
 #ifdef CONFIG_FIQ
         init_FIQ(FIQ_START);
 #endif
 
-        main_intc = s3c24xx_init_intc(NULL, &init_base[0], NULL, 0x4a000000);
-        if (IS_ERR(main_intc)) {
+        s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2410base[0], NULL,
+                                        0x4a000000);
+        if (IS_ERR(s3c_intc[0])) {
                 pr_err("irq: could not create main interrupt controller\n");
                 return;
         }
 
-        s3c24xx_init_intc(NULL, &init_subint[0], main_intc, 0x4a000018);
-        s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
+        s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2410subint[0],
+                                        s3c_intc[0], 0x4a000018);
+        s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
 }
+#endif
 
 #ifdef CONFIG_CPU_S3C2412
 static struct s3c_irq_data init_s3c2412base[32] = {
@@ -707,22 +796,22 @@ static struct s3c_irq_data init_s3c2412subint[32] = {
 
 void s3c2412_init_irq(void)
 {
-        struct s3c_irq_intc *main_intc;
-
         pr_info("S3C2412: IRQ Support\n");
 
 #ifdef CONFIG_FIQ
         init_FIQ(FIQ_START);
 #endif
 
-        main_intc = s3c24xx_init_intc(NULL, &init_s3c2412base[0], NULL, 0x4a000000);
-        if (IS_ERR(main_intc)) {
+        s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2412base[0], NULL,
+                                        0x4a000000);
+        if (IS_ERR(s3c_intc[0])) {
                 pr_err("irq: could not create main interrupt controller\n");
                 return;
         }
 
-        s3c24xx_init_intc(NULL, &init_s3c2412eint[0], main_intc, 0x560000a4);
-        s3c24xx_init_intc(NULL, &init_s3c2412subint[0], main_intc, 0x4a000018);
+        s3c24xx_init_intc(NULL, &init_s3c2412eint[0], s3c_intc[0], 0x560000a4);
+        s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2412subint[0],
+                                        s3c_intc[0], 0x4a000018);
 }
 #endif
 
@@ -796,35 +885,35 @@ static struct s3c_irq_data init_s3c2416subint[32] = {
 
 static struct s3c_irq_data init_s3c2416_second[32] = {
         { .type = S3C_IRQTYPE_EDGE }, /* 2D */
-        { .type = S3C_IRQTYPE_EDGE }, /* IIC1 */
+        { .type = S3C_IRQTYPE_NONE }, /* reserved */
         { .type = S3C_IRQTYPE_NONE }, /* reserved */
         { .type = S3C_IRQTYPE_NONE }, /* reserved */
         { .type = S3C_IRQTYPE_EDGE }, /* PCM0 */
-        { .type = S3C_IRQTYPE_EDGE }, /* PCM1 */
+        { .type = S3C_IRQTYPE_NONE }, /* reserved */
         { .type = S3C_IRQTYPE_EDGE }, /* I2S0 */
-        { .type = S3C_IRQTYPE_EDGE }, /* I2S1 */
 };
 
 void __init s3c2416_init_irq(void)
 {
-        struct s3c_irq_intc *main_intc;
-
         pr_info("S3C2416: IRQ Support\n");
 
 #ifdef CONFIG_FIQ
         init_FIQ(FIQ_START);
 #endif
 
-        main_intc = s3c24xx_init_intc(NULL, &init_s3c2416base[0], NULL, 0x4a000000);
-        if (IS_ERR(main_intc)) {
+        s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2416base[0], NULL,
+                                        0x4a000000);
+        if (IS_ERR(s3c_intc[0])) {
                 pr_err("irq: could not create main interrupt controller\n");
                 return;
         }
 
-        s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
-        s3c24xx_init_intc(NULL, &init_s3c2416subint[0], main_intc, 0x4a000018);
+        s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
+        s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2416subint[0],
+                                        s3c_intc[0], 0x4a000018);
 
-        s3c24xx_init_intc(NULL, &init_s3c2416_second[0], NULL, 0x4a000040);
+        s3c_intc[2] = s3c24xx_init_intc(NULL, &init_s3c2416_second[0],
+                                        NULL, 0x4a000040);
 }
 
 #endif
@@ -877,30 +966,30 @@ static struct s3c_irq_data init_s3c2440subint[32] = {
         { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
         { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
         { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* TC */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* ADC */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
         { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
         { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
 };
 
 void __init s3c2440_init_irq(void)
 {
-        struct s3c_irq_intc *main_intc;
-
         pr_info("S3C2440: IRQ Support\n");
 
 #ifdef CONFIG_FIQ
         init_FIQ(FIQ_START);
 #endif
 
-        main_intc = s3c24xx_init_intc(NULL, &init_s3c2440base[0], NULL, 0x4a000000);
-        if (IS_ERR(main_intc)) {
+        s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2440base[0], NULL,
+                                        0x4a000000);
+        if (IS_ERR(s3c_intc[0])) {
                 pr_err("irq: could not create main interrupt controller\n");
                 return;
         }
 
-        s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
-        s3c24xx_init_intc(NULL, &init_s3c2440subint[0], main_intc, 0x4a000018);
+        s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
+        s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2440subint[0],
+                                        s3c_intc[0], 0x4a000018);
 }
 #endif
 
@@ -952,28 +1041,28 @@ static struct s3c_irq_data init_s3c2442subint[32] = {
         { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
         { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
         { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* TC */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* ADC */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
 };
 
 void __init s3c2442_init_irq(void)
 {
-        struct s3c_irq_intc *main_intc;
-
         pr_info("S3C2442: IRQ Support\n");
 
 #ifdef CONFIG_FIQ
         init_FIQ(FIQ_START);
 #endif
 
-        main_intc = s3c24xx_init_intc(NULL, &init_s3c2442base[0], NULL, 0x4a000000);
-        if (IS_ERR(main_intc)) {
+        s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2442base[0], NULL,
+                                        0x4a000000);
+        if (IS_ERR(s3c_intc[0])) {
                 pr_err("irq: could not create main interrupt controller\n");
                 return;
         }
 
-        s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
-        s3c24xx_init_intc(NULL, &init_s3c2442subint[0], main_intc, 0x4a000018);
+        s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
+        s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2442subint[0],
+                                        s3c_intc[0], 0x4a000018);
 }
 #endif
 
@@ -1048,21 +1137,219 @@ static struct s3c_irq_data init_s3c2443subint[32] = {
 
 void __init s3c2443_init_irq(void)
 {
-        struct s3c_irq_intc *main_intc;
-
         pr_info("S3C2443: IRQ Support\n");
 
 #ifdef CONFIG_FIQ
         init_FIQ(FIQ_START);
 #endif
 
-        main_intc = s3c24xx_init_intc(NULL, &init_s3c2443base[0], NULL, 0x4a000000);
-        if (IS_ERR(main_intc)) {
+        s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2443base[0], NULL,
+                                        0x4a000000);
+        if (IS_ERR(s3c_intc[0])) {
                 pr_err("irq: could not create main interrupt controller\n");
                 return;
         }
 
-        s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
-        s3c24xx_init_intc(NULL, &init_s3c2443subint[0], main_intc, 0x4a000018);
+        s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
+        s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2443subint[0],
+                                        s3c_intc[0], 0x4a000018);
+}
+#endif
+
+#ifdef CONFIG_OF
+static int s3c24xx_irq_map_of(struct irq_domain *h, unsigned int virq,
+                                                        irq_hw_number_t hw)
+{
+        unsigned int ctrl_num = hw / 32;
+        unsigned int intc_hw = hw % 32;
+        struct s3c_irq_intc *intc = s3c_intc[ctrl_num];
+        struct s3c_irq_intc *parent_intc = intc->parent;
+        struct s3c_irq_data *irq_data = &intc->irqs[intc_hw];
+
+        /* attach controller pointer to irq_data */
+        irq_data->intc = intc;
+        irq_data->offset = intc_hw;
+
+        if (!parent_intc)
+                irq_set_chip_and_handler(virq, &s3c_irq_chip, handle_edge_irq);
+        else
+                irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
+                                         handle_edge_irq);
+
+        irq_set_chip_data(virq, irq_data);
+
+        set_irq_flags(virq, IRQF_VALID);
+
+        return 0;
+}
+
+/* Translate our of irq notation
+ * format: <ctrl_num ctrl_irq parent_irq type>
+ */
+static int s3c24xx_irq_xlate_of(struct irq_domain *d, struct device_node *n,
+                        const u32 *intspec, unsigned int intsize,
+                        irq_hw_number_t *out_hwirq, unsigned int *out_type)
+{
+        struct s3c_irq_intc *intc;
+        struct s3c_irq_intc *parent_intc;
+        struct s3c_irq_data *irq_data;
+        struct s3c_irq_data *parent_irq_data;
+        int irqno;
+
+        if (WARN_ON(intsize < 4))
+                return -EINVAL;
+
+        if (intspec[0] > 2 || !s3c_intc[intspec[0]]) {
+                pr_err("controller number %d invalid\n", intspec[0]);
+                return -EINVAL;
+        }
+        intc = s3c_intc[intspec[0]];
+
+        *out_hwirq = intspec[0] * 32 + intspec[2];
+        *out_type = intspec[3] & IRQ_TYPE_SENSE_MASK;
+
+        parent_intc = intc->parent;
+        if (parent_intc) {
+                irq_data = &intc->irqs[intspec[2]];
+                irq_data->parent_irq = intspec[1];
+                parent_irq_data = &parent_intc->irqs[irq_data->parent_irq];
+                parent_irq_data->sub_intc = intc;
+                parent_irq_data->sub_bits |= (1UL << intspec[2]);
+
+                /* parent_intc is always s3c_intc[0], so no offset */
+                irqno = irq_create_mapping(parent_intc->domain, intspec[1]);
+                if (irqno < 0) {
+                        pr_err("irq: could not map parent interrupt\n");
+                        return irqno;
+                }
+
+                irq_set_chained_handler(irqno, s3c_irq_demux);
+        }
+
+        return 0;
+}
+
+static struct irq_domain_ops s3c24xx_irq_ops_of = {
+        .map = s3c24xx_irq_map_of,
+        .xlate = s3c24xx_irq_xlate_of,
+};
+
+struct s3c24xx_irq_of_ctrl {
+        char                    *name;
+        unsigned long           offset;
+        struct s3c_irq_intc     **handle;
+        struct s3c_irq_intc     **parent;
+        struct irq_domain_ops   *ops;
+};
+
+static int __init s3c_init_intc_of(struct device_node *np,
+                        struct device_node *interrupt_parent,
+                        struct s3c24xx_irq_of_ctrl *s3c_ctrl, int num_ctrl)
+{
+        struct s3c_irq_intc *intc;
+        struct s3c24xx_irq_of_ctrl *ctrl;
+        struct irq_domain *domain;
+        void __iomem *reg_base;
+        int i;
+
+        reg_base = of_iomap(np, 0);
+        if (!reg_base) {
+                pr_err("irq-s3c24xx: could not map irq registers\n");
+                return -EINVAL;
+        }
+
+        domain = irq_domain_add_linear(np, num_ctrl * 32,
+                                                     &s3c24xx_irq_ops_of, NULL);
+        if (!domain) {
+                pr_err("irq: could not create irq-domain\n");
+                return -EINVAL;
+        }
+
+        for (i = 0; i < num_ctrl; i++) {
+                ctrl = &s3c_ctrl[i];
+
+                pr_debug("irq: found controller %s\n", ctrl->name);
+
+                intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL);
+                if (!intc)
+                        return -ENOMEM;
+
+                intc->domain = domain;
+                intc->irqs = kzalloc(sizeof(struct s3c_irq_data) * 32,
+                                     GFP_KERNEL);
+                if (!intc->irqs) {
+                        kfree(intc);
+                        return -ENOMEM;
+                }
+
+                if (ctrl->parent) {
+                        intc->reg_pending = reg_base + ctrl->offset;
+                        intc->reg_mask = reg_base + ctrl->offset + 0x4;
+
+                        if (*(ctrl->parent)) {
+                                intc->parent = *(ctrl->parent);
+                        } else {
+                                pr_warn("irq: parent of %s missing\n",
+                                        ctrl->name);
+                                kfree(intc->irqs);
+                                kfree(intc);
+                                continue;
+                        }
+                } else {
+                        intc->reg_pending = reg_base + ctrl->offset;
+                        intc->reg_mask = reg_base + ctrl->offset + 0x08;
+                        intc->reg_intpnd = reg_base + ctrl->offset + 0x10;
+                }
+
+                s3c24xx_clear_intc(intc);
+                s3c_intc[i] = intc;
+        }
+
+        set_handle_irq(s3c24xx_handle_irq);
+
+        return 0;
+}
+
+static struct s3c24xx_irq_of_ctrl s3c2410_ctrl[] = {
+        {
+                .name = "intc",
+                .offset = 0,
+        }, {
+                .name = "subintc",
+                .offset = 0x18,
+                .parent = &s3c_intc[0],
+        }
+};
+
+int __init s3c2410_init_intc_of(struct device_node *np,
+                        struct device_node *interrupt_parent,
+                        struct s3c24xx_irq_of_ctrl *ctrl, int num_ctrl)
+{
+        return s3c_init_intc_of(np, interrupt_parent,
+                                s3c2410_ctrl, ARRAY_SIZE(s3c2410_ctrl));
+}
+IRQCHIP_DECLARE(s3c2410_irq, "samsung,s3c2410-irq", s3c2410_init_intc_of);
+
+static struct s3c24xx_irq_of_ctrl s3c2416_ctrl[] = {
+        {
+                .name = "intc",
+                .offset = 0,
+        }, {
+                .name = "subintc",
+                .offset = 0x18,
+                .parent = &s3c_intc[0],
+        }, {
+                .name = "intc2",
+                .offset = 0x40,
+        }
+};
+
+int __init s3c2416_init_intc_of(struct device_node *np,
+                        struct device_node *interrupt_parent,
+                        struct s3c24xx_irq_of_ctrl *ctrl, int num_ctrl)
+{
+        return s3c_init_intc_of(np, interrupt_parent,
+                                s3c2416_ctrl, ARRAY_SIZE(s3c2416_ctrl));
 }
+IRQCHIP_DECLARE(s3c2416_irq, "samsung,s3c2416-irq", s3c2416_init_intc_of);
 #endif
diff --git a/drivers/md/dm-cache-target.c b/drivers/md/dm-cache-target.c
index 66120bd46d15..10744091e6ca 100644
--- a/drivers/md/dm-cache-target.c
+++ b/drivers/md/dm-cache-target.c
@@ -6,6 +6,7 @@
 
 #include "dm.h"
 #include "dm-bio-prison.h"
+#include "dm-bio-record.h"
 #include "dm-cache-metadata.h"
 
 #include <linux/dm-io.h>
@@ -201,10 +202,15 @@ struct per_bio_data {
         unsigned req_nr:2;
         struct dm_deferred_entry *all_io_entry;
 
-        /* writethrough fields */
+        /*
+         * writethrough fields.  These MUST remain at the end of this
+         * structure and the 'cache' member must be the first as it
+         * is used to determine the offsetof the writethrough fields.
+         */
         struct cache *cache;
         dm_cblock_t cblock;
         bio_end_io_t *saved_bi_end_io;
+        struct dm_bio_details bio_details;
 };
 
 struct dm_cache_migration {
@@ -513,16 +519,28 @@ static void save_stats(struct cache *cache)
 /*----------------------------------------------------------------
  * Per bio data
  *--------------------------------------------------------------*/
-static struct per_bio_data *get_per_bio_data(struct bio *bio)
+
+/*
+ * If using writeback, leave out struct per_bio_data's writethrough fields.
+ */
+#define PB_DATA_SIZE_WB (offsetof(struct per_bio_data, cache))
+#define PB_DATA_SIZE_WT (sizeof(struct per_bio_data))
+
+static size_t get_per_bio_data_size(struct cache *cache)
+{
+        return cache->features.write_through ? PB_DATA_SIZE_WT : PB_DATA_SIZE_WB;
+}
+
+static struct per_bio_data *get_per_bio_data(struct bio *bio, size_t data_size)
 {
-        struct per_bio_data *pb = dm_per_bio_data(bio, sizeof(struct per_bio_data));
+        struct per_bio_data *pb = dm_per_bio_data(bio, data_size);
         BUG_ON(!pb);
         return pb;
 }
 
-static struct per_bio_data *init_per_bio_data(struct bio *bio)
+static struct per_bio_data *init_per_bio_data(struct bio *bio, size_t data_size)
 {
-        struct per_bio_data *pb = get_per_bio_data(bio);
+        struct per_bio_data *pb = get_per_bio_data(bio, data_size);
 
         pb->tick = false;
         pb->req_nr = dm_bio_get_target_bio_nr(bio);
@@ -556,7 +574,8 @@ static void remap_to_cache(struct cache *cache, struct bio *bio,
 static void check_if_tick_bio_needed(struct cache *cache, struct bio *bio)
 {
         unsigned long flags;
-        struct per_bio_data *pb = get_per_bio_data(bio);
+        size_t pb_data_size = get_per_bio_data_size(cache);
+        struct per_bio_data *pb = get_per_bio_data(bio, pb_data_size);
 
         spin_lock_irqsave(&cache->lock, flags);
         if (cache->need_tick_bio &&
@@ -635,7 +654,7 @@ static void defer_writethrough_bio(struct cache *cache, struct bio *bio)
 
 static void writethrough_endio(struct bio *bio, int err)
 {
-        struct per_bio_data *pb = get_per_bio_data(bio);
+        struct per_bio_data *pb = get_per_bio_data(bio, PB_DATA_SIZE_WT);
         bio->bi_end_io = pb->saved_bi_end_io;
 
         if (err) {
@@ -643,6 +662,7 @@ static void writethrough_endio(struct bio *bio, int err)
                 return;
         }
 
+        dm_bio_restore(&pb->bio_details, bio);
         remap_to_cache(pb->cache, bio, pb->cblock);
 
         /*
@@ -662,11 +682,12 @@ static void writethrough_endio(struct bio *bio, int err)
 static void remap_to_origin_then_cache(struct cache *cache, struct bio *bio,
                                        dm_oblock_t oblock, dm_cblock_t cblock)
 {
-        struct per_bio_data *pb = get_per_bio_data(bio);
+        struct per_bio_data *pb = get_per_bio_data(bio, PB_DATA_SIZE_WT);
 
         pb->cache = cache;
         pb->cblock = cblock;
         pb->saved_bi_end_io = bio->bi_end_io;
+        dm_bio_record(&pb->bio_details, bio);
         bio->bi_end_io = writethrough_endio;
 
         remap_to_origin_clear_discard(pb->cache, bio, oblock);
@@ -1035,7 +1056,8 @@ static void defer_bio(struct cache *cache, struct bio *bio)
 
 static void process_flush_bio(struct cache *cache, struct bio *bio)
 {
-        struct per_bio_data *pb = get_per_bio_data(bio);
+        size_t pb_data_size = get_per_bio_data_size(cache);
+        struct per_bio_data *pb = get_per_bio_data(bio, pb_data_size);
 
         BUG_ON(bio->bi_size);
         if (!pb->req_nr)
@@ -1107,7 +1129,8 @@ static void process_bio(struct cache *cache, struct prealloc *structs,
         dm_oblock_t block = get_bio_block(cache, bio);
         struct dm_bio_prison_cell *cell_prealloc, *old_ocell, *new_ocell;
         struct policy_result lookup_result;
-        struct per_bio_data *pb = get_per_bio_data(bio);
+        size_t pb_data_size = get_per_bio_data_size(cache);
+        struct per_bio_data *pb = get_per_bio_data(bio, pb_data_size);
         bool discarded_block = is_discarded_oblock(cache, block);
         bool can_migrate = discarded_block || spare_migration_bandwidth(cache);
 
@@ -1881,7 +1904,6 @@ static int cache_create(struct cache_args *ca, struct cache **result)
 
         cache->ti = ca->ti;
         ti->private = cache;
-        ti->per_bio_data_size = sizeof(struct per_bio_data);
         ti->num_flush_bios = 2;
         ti->flush_supported = true;
 
@@ -1890,6 +1912,7 @@ static int cache_create(struct cache_args *ca, struct cache **result)
         ti->discard_zeroes_data_unsupported = true;
 
         memcpy(&cache->features, &ca->features, sizeof(cache->features));
+        ti->per_bio_data_size = get_per_bio_data_size(cache);
 
         cache->callbacks.congested_fn = cache_is_congested;
         dm_table_add_target_callbacks(ti->table, &cache->callbacks);
@@ -2092,6 +2115,7 @@ static int cache_map(struct dm_target *ti, struct bio *bio)
 
         int r;
         dm_oblock_t block = get_bio_block(cache, bio);
+        size_t pb_data_size = get_per_bio_data_size(cache);
         bool can_migrate = false;
         bool discarded_block;
         struct dm_bio_prison_cell *cell;
@@ -2108,7 +2132,7 @@ static int cache_map(struct dm_target *ti, struct bio *bio)
                 return DM_MAPIO_REMAPPED;
         }
 
-        pb = init_per_bio_data(bio);
+        pb = init_per_bio_data(bio, pb_data_size);
 
         if (bio->bi_rw & (REQ_FLUSH | REQ_FUA | REQ_DISCARD)) {
                 defer_bio(cache, bio);
@@ -2193,7 +2217,8 @@ static int cache_end_io(struct dm_target *ti, struct bio *bio, int error)
 {
         struct cache *cache = ti->private;
         unsigned long flags;
-        struct per_bio_data *pb = get_per_bio_data(bio);
+        size_t pb_data_size = get_per_bio_data_size(cache);
+        struct per_bio_data *pb = get_per_bio_data(bio, pb_data_size);
 
         if (pb->tick) {
                 policy_tick(cache->policy);
diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig
index 05d7b6333461..a0639e779973 100644
--- a/drivers/media/platform/Kconfig
+++ b/drivers/media/platform/Kconfig
@@ -204,7 +204,7 @@ config VIDEO_SAMSUNG_EXYNOS_GSC
 
 config VIDEO_SH_VEU
         tristate "SuperH VEU mem2mem video processing driver"
-        depends on VIDEO_DEV && VIDEO_V4L2
+        depends on VIDEO_DEV && VIDEO_V4L2 && GENERIC_HARDIRQS
         select VIDEOBUF2_DMA_CONTIG
         select V4L2_MEM2MEM_DEV
         help
diff --git a/drivers/media/radio/radio-ma901.c b/drivers/media/radio/radio-ma901.c
index c61f590029ad..348dafc0318a 100644
--- a/drivers/media/radio/radio-ma901.c
+++ b/drivers/media/radio/radio-ma901.c
@@ -347,9 +347,20 @@ static void usb_ma901radio_release(struct v4l2_device *v4l2_dev)
 static int usb_ma901radio_probe(struct usb_interface *intf,
                                 const struct usb_device_id *id)
 {
+        struct usb_device *dev = interface_to_usbdev(intf);
         struct ma901radio_device *radio;
         int retval = 0;
 
+        /* Masterkit MA901 usb radio has the same USB ID as many others
+         * Atmel V-USB devices. Let's make additional checks to be sure
+         * that this is our device.
+         */
+
+        if (dev->product && dev->manufacturer &&
+                (strncmp(dev->product, "MA901", 5) != 0
+                || strncmp(dev->manufacturer, "www.masterkit.ru", 16) != 0))
+                return -ENODEV;
+
         radio = kzalloc(sizeof(struct ma901radio_device), GFP_KERNEL);
         if (!radio) {
                 dev_err(&intf->dev, "kzalloc for ma901radio_device failed\n");
diff --git a/drivers/net/bonding/bond_main.c b/drivers/net/bonding/bond_main.c
index 6bbd90e1123c..171b10f167a5 100644
--- a/drivers/net/bonding/bond_main.c
+++ b/drivers/net/bonding/bond_main.c
@@ -1976,12 +1976,11 @@ static int __bond_release_one(struct net_device *bond_dev,
                 return -EINVAL;
         }
 
+        write_unlock_bh(&bond->lock);
         /* unregister rx_handler early so bond_handle_frame wouldn't be called
          * for this slave anymore.
          */
         netdev_rx_handler_unregister(slave_dev);
-        write_unlock_bh(&bond->lock);
-        synchronize_net();
         write_lock_bh(&bond->lock);
 
         if (!all && !bond->params.fail_over_mac) {
@@ -4903,8 +4902,8 @@ static void __exit bonding_exit(void)
 
         bond_destroy_debugfs();
 
-        rtnl_link_unregister(&bond_link_ops);
         unregister_pernet_subsys(&bond_net_ops);
+        rtnl_link_unregister(&bond_link_ops);
 
 #ifdef CONFIG_NET_POLL_CONTROLLER
         /*
diff --git a/drivers/net/bonding/bond_sysfs.c b/drivers/net/bonding/bond_sysfs.c
index db103e03ba05..ea7a388f4843 100644
--- a/drivers/net/bonding/bond_sysfs.c
+++ b/drivers/net/bonding/bond_sysfs.c
@@ -527,7 +527,7 @@ static ssize_t bonding_store_arp_interval(struct device *d,
                 goto out;
         }
         if (new_value < 0) {
-                pr_err("%s: Invalid arp_interval value %d not in range 1-%d; rejected.\n",
+                pr_err("%s: Invalid arp_interval value %d not in range 0-%d; rejected.\n",
                        bond->dev->name, new_value, INT_MAX);
                 ret = -EINVAL;
                 goto out;
@@ -542,14 +542,15 @@ static ssize_t bonding_store_arp_interval(struct device *d,
         pr_info("%s: Setting ARP monitoring interval to %d.\n",
                 bond->dev->name, new_value);
         bond->params.arp_interval = new_value;
-        if (bond->params.miimon) {
-                pr_info("%s: ARP monitoring cannot be used with MII monitoring. %s Disabling MII monitoring.\n",
-                        bond->dev->name, bond->dev->name);
-                bond->params.miimon = 0;
-        }
-        if (!bond->params.arp_targets[0]) {
-                pr_info("%s: ARP monitoring has been set up, but no ARP targets have been specified.\n",
-                        bond->dev->name);
+        if (new_value) {
+                if (bond->params.miimon) {
+                        pr_info("%s: ARP monitoring cannot be used with MII monitoring. %s Disabling MII monitoring.\n",
+                                bond->dev->name, bond->dev->name);
+                        bond->params.miimon = 0;
+                }
+                if (!bond->params.arp_targets[0])
+                        pr_info("%s: ARP monitoring has been set up, but no ARP targets have been specified.\n",
+                                bond->dev->name);
         }
         if (bond->dev->flags & IFF_UP) {
                 /* If the interface is up, we may need to fire off
@@ -557,10 +558,13 @@ static ssize_t bonding_store_arp_interval(struct device *d,
                  * timer will get fired off when the open function
                  * is called.
                  */
-                cancel_delayed_work_sync(&bond->mii_work);
-                queue_delayed_work(bond->wq, &bond->arp_work, 0);
+                if (!new_value) {
+                        cancel_delayed_work_sync(&bond->arp_work);
+                } else {
+                        cancel_delayed_work_sync(&bond->mii_work);
+                        queue_delayed_work(bond->wq, &bond->arp_work, 0);
+                }
         }
-
 out:
         rtnl_unlock();
         return ret;
@@ -702,7 +706,7 @@ static ssize_t bonding_store_downdelay(struct device *d,
         }
         if (new_value < 0) {
                 pr_err("%s: Invalid down delay value %d not in range %d-%d; rejected.\n",
-                       bond->dev->name, new_value, 1, INT_MAX);
+                       bond->dev->name, new_value, 0, INT_MAX);
                 ret = -EINVAL;
                 goto out;
         } else {
@@ -757,8 +761,8 @@ static ssize_t bonding_store_updelay(struct device *d,
                 goto out;
         }
         if (new_value < 0) {
-                pr_err("%s: Invalid down delay value %d not in range %d-%d; rejected.\n",
-                       bond->dev->name, new_value, 1, INT_MAX);
+                pr_err("%s: Invalid up delay value %d not in range %d-%d; rejected.\n",
+                       bond->dev->name, new_value, 0, INT_MAX);
                 ret = -EINVAL;
                 goto out;
         } else {
@@ -968,37 +972,37 @@ static ssize_t bonding_store_miimon(struct device *d,
         }
         if (new_value < 0) {
                 pr_err("%s: Invalid miimon value %d not in range %d-%d; rejected.\n",
-                       bond->dev->name, new_value, 1, INT_MAX);
+                       bond->dev->name, new_value, 0, INT_MAX);
                 ret = -EINVAL;
                 goto out;
-        } else {
-                pr_info("%s: Setting MII monitoring interval to %d.\n",
-                        bond->dev->name, new_value);
-                bond->params.miimon = new_value;
-                if (bond->params.updelay)
-                        pr_info("%s: Note: Updating updelay (to %d) since it is a multiple of the miimon value.\n",
-                                bond->dev->name,
-                                bond->params.updelay * bond->params.miimon);
-                if (bond->params.downdelay)
-                        pr_info("%s: Note: Updating downdelay (to %d) since it is a multiple of the miimon value.\n",
-                                bond->dev->name,
-                                bond->params.downdelay * bond->params.miimon);
-                if (bond->params.arp_interval) {
-                        pr_info("%s: MII monitoring cannot be used with ARP monitoring. Disabling ARP monitoring...\n",
-                                bond->dev->name);
-                        bond->params.arp_interval = 0;
-                        if (bond->params.arp_validate) {
-                                bond->params.arp_validate =
-                                        BOND_ARP_VALIDATE_NONE;
-                        }
-                }
-
-                if (bond->dev->flags & IFF_UP) {
-                        /* If the interface is up, we may need to fire off
-                         * the MII timer. If the interface is down, the
-                         * timer will get fired off when the open function
-                         * is called.
-                         */
+        }
+        pr_info("%s: Setting MII monitoring interval to %d.\n",
+                bond->dev->name, new_value);
+        bond->params.miimon = new_value;
+        if (bond->params.updelay)
+                pr_info("%s: Note: Updating updelay (to %d) since it is a multiple of the miimon value.\n",
+                        bond->dev->name,
+                        bond->params.updelay * bond->params.miimon);
+        if (bond->params.downdelay)
+                pr_info("%s: Note: Updating downdelay (to %d) since it is a multiple of the miimon value.\n",
+                        bond->dev->name,
+                        bond->params.downdelay * bond->params.miimon);
+        if (new_value && bond->params.arp_interval) {
+                pr_info("%s: MII monitoring cannot be used with ARP monitoring. Disabling ARP monitoring...\n",
+                        bond->dev->name);
+                bond->params.arp_interval = 0;
+                if (bond->params.arp_validate)
+                        bond->params.arp_validate = BOND_ARP_VALIDATE_NONE;
+        }
+        if (bond->dev->flags & IFF_UP) {
+                /* If the interface is up, we may need to fire off
+                 * the MII timer. If the interface is down, the
+                 * timer will get fired off when the open function
+                 * is called.
+                 */
+                if (!new_value) {
+                        cancel_delayed_work_sync(&bond->mii_work);
+                } else {
                         cancel_delayed_work_sync(&bond->arp_work);
                         queue_delayed_work(bond->wq, &bond->mii_work, 0);
                 }
diff --git a/drivers/net/can/sja1000/Kconfig b/drivers/net/can/sja1000/Kconfig
index b39ca5b3ea7f..ff2ba86cd4a4 100644
--- a/drivers/net/can/sja1000/Kconfig
+++ b/drivers/net/can/sja1000/Kconfig
@@ -46,6 +46,7 @@ config CAN_EMS_PCI
 config CAN_PEAK_PCMCIA
         tristate "PEAK PCAN-PC Card"
         depends on PCMCIA
+        depends on HAS_IOPORT
         ---help---
           This driver is for the PCAN-PC Card PCMCIA adapter (1 or 2 channels)
           from PEAK-System (http://www.peak-system.com). To compile this
diff --git a/drivers/net/can/sja1000/plx_pci.c b/drivers/net/can/sja1000/plx_pci.c
index a042cdc260dc..3c18d7d000ed 100644
--- a/drivers/net/can/sja1000/plx_pci.c
+++ b/drivers/net/can/sja1000/plx_pci.c
@@ -348,7 +348,7 @@ static inline int plx_pci_check_sja1000(const struct sja1000_priv *priv)
          */
         if ((priv->read_reg(priv, REG_CR) & REG_CR_BASICCAN_INITIAL_MASK) ==
             REG_CR_BASICCAN_INITIAL &&
-            (priv->read_reg(priv, REG_SR) == REG_SR_BASICCAN_INITIAL) &&
+            (priv->read_reg(priv, SJA1000_REG_SR) == REG_SR_BASICCAN_INITIAL) &&
             (priv->read_reg(priv, REG_IR) == REG_IR_BASICCAN_INITIAL))
                 flag = 1;
 
@@ -360,7 +360,7 @@ static inline int plx_pci_check_sja1000(const struct sja1000_priv *priv)
          * See states on p. 23 of the Datasheet.
          */
         if (priv->read_reg(priv, REG_MOD) == REG_MOD_PELICAN_INITIAL &&
-            priv->read_reg(priv, REG_SR) == REG_SR_PELICAN_INITIAL &&
+            priv->read_reg(priv, SJA1000_REG_SR) == REG_SR_PELICAN_INITIAL &&
             priv->read_reg(priv, REG_IR) == REG_IR_PELICAN_INITIAL)
                 return flag;
 
diff --git a/drivers/net/can/sja1000/sja1000.c b/drivers/net/can/sja1000/sja1000.c
index daf4013a8fc7..e4df307eaa90 100644
--- a/drivers/net/can/sja1000/sja1000.c
+++ b/drivers/net/can/sja1000/sja1000.c
@@ -92,7 +92,7 @@ static void sja1000_write_cmdreg(struct sja1000_priv *priv, u8 val)
          */
         spin_lock_irqsave(&priv->cmdreg_lock, flags);
         priv->write_reg(priv, REG_CMR, val);
-        priv->read_reg(priv, REG_SR);
+        priv->read_reg(priv, SJA1000_REG_SR);
         spin_unlock_irqrestore(&priv->cmdreg_lock, flags);
 }
 
@@ -502,7 +502,7 @@ irqreturn_t sja1000_interrupt(int irq, void *dev_id)
 
         while ((isrc = priv->read_reg(priv, REG_IR)) && (n < SJA1000_MAX_IRQ)) {
                 n++;
-                status = priv->read_reg(priv, REG_SR);
+                status = priv->read_reg(priv, SJA1000_REG_SR);
                 /* check for absent controller due to hw unplug */
                 if (status == 0xFF && sja1000_is_absent(priv))
                         return IRQ_NONE;
@@ -530,7 +530,7 @@ irqreturn_t sja1000_interrupt(int irq, void *dev_id)
                         /* receive interrupt */
                         while (status & SR_RBS) {
                                 sja1000_rx(dev);
-                                status = priv->read_reg(priv, REG_SR);
+                                status = priv->read_reg(priv, SJA1000_REG_SR);
                                 /* check for absent controller */
                                 if (status == 0xFF && sja1000_is_absent(priv))
                                         return IRQ_NONE;
diff --git a/drivers/net/can/sja1000/sja1000.h b/drivers/net/can/sja1000/sja1000.h
index afa99847a510..aa48e053da27 100644
--- a/drivers/net/can/sja1000/sja1000.h
+++ b/drivers/net/can/sja1000/sja1000.h
@@ -56,7 +56,7 @@
 /* SJA1000 registers - manual section 6.4 (Pelican Mode) */
 #define REG_MOD         0x00
 #define REG_CMR         0x01
-#define REG_SR          0x02
+#define SJA1000_REG_SR          0x02
 #define REG_IR          0x03
 #define REG_IER         0x04
 #define REG_ALC         0x0B
diff --git a/drivers/net/ethernet/atheros/atl1e/atl1e.h b/drivers/net/ethernet/atheros/atl1e/atl1e.h
index 829b5ad71d0d..b5fd934585e9 100644
--- a/drivers/net/ethernet/atheros/atl1e/atl1e.h
+++ b/drivers/net/ethernet/atheros/atl1e/atl1e.h
@@ -186,7 +186,7 @@ struct atl1e_tpd_desc {
 /* how about 0x2000 */
 #define MAX_TX_BUF_LEN      0x2000
 #define MAX_TX_BUF_SHIFT    13
-/*#define MAX_TX_BUF_LEN  0x3000 */
+#define MAX_TSO_SEG_SIZE    0x3c00
 
 /* rrs word 1 bit 0:31 */
 #define RRS_RX_CSUM_MASK        0xFFFF
@@ -438,7 +438,6 @@ struct atl1e_adapter {
         struct atl1e_hw        hw;
         struct atl1e_hw_stats  hw_stats;
 
-        bool have_msi;
         u32 wol;
         u16 link_speed;
         u16 link_duplex;
diff --git a/drivers/net/ethernet/atheros/atl1e/atl1e_main.c b/drivers/net/ethernet/atheros/atl1e/atl1e_main.c
index 92f4734f860d..ac25f05ff68f 100644
--- a/drivers/net/ethernet/atheros/atl1e/atl1e_main.c
+++ b/drivers/net/ethernet/atheros/atl1e/atl1e_main.c
@@ -1849,34 +1849,19 @@ static void atl1e_free_irq(struct atl1e_adapter *adapter)
         struct net_device *netdev = adapter->netdev;
 
         free_irq(adapter->pdev->irq, netdev);
-
-        if (adapter->have_msi)
-                pci_disable_msi(adapter->pdev);
 }
 
 static int atl1e_request_irq(struct atl1e_adapter *adapter)
 {
         struct pci_dev    *pdev   = adapter->pdev;
         struct net_device *netdev = adapter->netdev;
-        int flags = 0;
         int err = 0;
 
-        adapter->have_msi = true;
-        err = pci_enable_msi(pdev);
-        if (err) {
-                netdev_dbg(netdev,
-                           "Unable to allocate MSI interrupt Error: %d\n", err);
-                adapter->have_msi = false;
-        }
-
-        if (!adapter->have_msi)
-                flags |= IRQF_SHARED;
-        err = request_irq(pdev->irq, atl1e_intr, flags, netdev->name, netdev);
+        err = request_irq(pdev->irq, atl1e_intr, IRQF_SHARED, netdev->name,
+                          netdev);
         if (err) {
                 netdev_dbg(adapter->netdev,
                            "Unable to allocate interrupt Error: %d\n", err);
-                if (adapter->have_msi)
-                        pci_disable_msi(pdev);
                 return err;
         }
         netdev_dbg(netdev, "atl1e_request_irq OK\n");
@@ -2344,6 +2329,7 @@ static int atl1e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 
         INIT_WORK(&adapter->reset_task, atl1e_reset_task);
         INIT_WORK(&adapter->link_chg_task, atl1e_link_chg_task);
+        netif_set_gso_max_size(netdev, MAX_TSO_SEG_SIZE);
         err = register_netdev(netdev);
         if (err) {
                 netdev_err(netdev, "register netdevice failed\n");
diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c
index 67d2663b3974..17a972734ba7 100644
--- a/drivers/net/ethernet/broadcom/tg3.c
+++ b/drivers/net/ethernet/broadcom/tg3.c
@@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
                 if (j + len > block_end)
                         goto partno;
 
-                memcpy(tp->fw_ver, &vpd_data[j], len);
-                strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+                if (len >= sizeof(tp->fw_ver))
+                        len = sizeof(tp->fw_ver) - 1;
+                memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+                snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+                         &vpd_data[j]);
         }
 
 partno:
diff --git a/drivers/net/ethernet/calxeda/xgmac.c b/drivers/net/ethernet/calxeda/xgmac.c
index a170065b5973..b0ebc9f6d55e 100644
--- a/drivers/net/ethernet/calxeda/xgmac.c
+++ b/drivers/net/ethernet/calxeda/xgmac.c
@@ -163,6 +163,7 @@
 #define XGMAC_FLOW_CTRL_FCB_BPA 0x00000001      /* Flow Control Busy ... */
 
 /* XGMAC_INT_STAT reg */
+#define XGMAC_INT_STAT_PMTIM    0x00800000      /* PMT Interrupt Mask */
 #define XGMAC_INT_STAT_PMT      0x0080          /* PMT Interrupt Status */
 #define XGMAC_INT_STAT_LPI      0x0040          /* LPI Interrupt Status */
 
@@ -960,6 +961,9 @@ static int xgmac_hw_init(struct net_device *dev)
         writel(DMA_INTR_DEFAULT_MASK, ioaddr + XGMAC_DMA_STATUS);
         writel(DMA_INTR_DEFAULT_MASK, ioaddr + XGMAC_DMA_INTR_ENA);
 
+        /* Mask power mgt interrupt */
+        writel(XGMAC_INT_STAT_PMTIM, ioaddr + XGMAC_INT_STAT);
+
         /* XGMAC requires AXI bus init. This is a 'magic number' for now */
         writel(0x0077000E, ioaddr + XGMAC_DMA_AXI_BUS);
 
@@ -1141,6 +1145,9 @@ static int xgmac_rx(struct xgmac_priv *priv, int limit)
                 struct sk_buff *skb;
                 int frame_len;
 
+                if (!dma_ring_cnt(priv->rx_head, priv->rx_tail, DMA_RX_RING_SZ))
+                        break;
+
                 entry = priv->rx_tail;
                 p = priv->dma_rx + entry;
                 if (desc_get_owner(p))
@@ -1825,7 +1832,7 @@ static void xgmac_pmt(void __iomem *ioaddr, unsigned long mode)
         unsigned int pmt = 0;
 
         if (mode & WAKE_MAGIC)
-                pmt |= XGMAC_PMT_POWERDOWN | XGMAC_PMT_MAGIC_PKT;
+                pmt |= XGMAC_PMT_POWERDOWN | XGMAC_PMT_MAGIC_PKT_EN;
         if (mode & WAKE_UCAST)
                 pmt |= XGMAC_PMT_POWERDOWN | XGMAC_PMT_GLBL_UNICAST;
 
diff --git a/drivers/net/ethernet/davicom/dm9000.c b/drivers/net/ethernet/davicom/dm9000.c
index 8cdf02503d13..9eada8e86078 100644
--- a/drivers/net/ethernet/davicom/dm9000.c
+++ b/drivers/net/ethernet/davicom/dm9000.c
@@ -257,6 +257,107 @@ static void dm9000_dumpblk_32bit(void __iomem *reg, int count)
                 tmp = readl(reg);
 }
 
+/*
+ * Sleep, either by using msleep() or if we are suspending, then
+ * use mdelay() to sleep.
+ */
+static void dm9000_msleep(board_info_t *db, unsigned int ms)
+{
+        if (db->in_suspend)
+                mdelay(ms);
+        else
+                msleep(ms);
+}
+
+/* Read a word from phyxcer */
+static int
+dm9000_phy_read(struct net_device *dev, int phy_reg_unused, int reg)
+{
+        board_info_t *db = netdev_priv(dev);
+        unsigned long flags;
+        unsigned int reg_save;
+        int ret;
+
+        mutex_lock(&db->addr_lock);
+
+        spin_lock_irqsave(&db->lock, flags);
+
+        /* Save previous register address */
+        reg_save = readb(db->io_addr);
+
+        /* Fill the phyxcer register into REG_0C */
+        iow(db, DM9000_EPAR, DM9000_PHY | reg);
+
+        /* Issue phyxcer read command */
+        iow(db, DM9000_EPCR, EPCR_ERPRR | EPCR_EPOS);
+
+        writeb(reg_save, db->io_addr);
+        spin_unlock_irqrestore(&db->lock, flags);
+
+        dm9000_msleep(db, 1);           /* Wait read complete */
+
+        spin_lock_irqsave(&db->lock, flags);
+        reg_save = readb(db->io_addr);
+
+        iow(db, DM9000_EPCR, 0x0);      /* Clear phyxcer read command */
+
+        /* The read data keeps on REG_0D & REG_0E */
+        ret = (ior(db, DM9000_EPDRH) << 8) | ior(db, DM9000_EPDRL);
+
+        /* restore the previous address */
+        writeb(reg_save, db->io_addr);
+        spin_unlock_irqrestore(&db->lock, flags);
+
+        mutex_unlock(&db->addr_lock);
+
+        dm9000_dbg(db, 5, "phy_read[%02x] -> %04x\n", reg, ret);
+        return ret;
+}
+
+/* Write a word to phyxcer */
+static void
+dm9000_phy_write(struct net_device *dev,
+                 int phyaddr_unused, int reg, int value)
+{
+        board_info_t *db = netdev_priv(dev);
+        unsigned long flags;
+        unsigned long reg_save;
+
+        dm9000_dbg(db, 5, "phy_write[%02x] = %04x\n", reg, value);
+        mutex_lock(&db->addr_lock);
+
+        spin_lock_irqsave(&db->lock, flags);
+
+        /* Save previous register address */
+        reg_save = readb(db->io_addr);
+
+        /* Fill the phyxcer register into REG_0C */
+        iow(db, DM9000_EPAR, DM9000_PHY | reg);
+
+        /* Fill the written data into REG_0D & REG_0E */
+        iow(db, DM9000_EPDRL, value);
+        iow(db, DM9000_EPDRH, value >> 8);
+
+        /* Issue phyxcer write command */
+        iow(db, DM9000_EPCR, EPCR_EPOS | EPCR_ERPRW);
+
+        writeb(reg_save, db->io_addr);
+        spin_unlock_irqrestore(&db->lock, flags);
+
+        dm9000_msleep(db, 1);           /* Wait write complete */
+
+        spin_lock_irqsave(&db->lock, flags);
+        reg_save = readb(db->io_addr);
+
+        iow(db, DM9000_EPCR, 0x0);      /* Clear phyxcer write command */
+
+        /* restore the previous address */
+        writeb(reg_save, db->io_addr);
+
+        spin_unlock_irqrestore(&db->lock, flags);
+        mutex_unlock(&db->addr_lock);
+}
+
 /* dm9000_set_io
  *
  * select the specified set of io routines to use with the
@@ -795,6 +896,9 @@ dm9000_init_dm9000(struct net_device *dev)
 
         iow(db, DM9000_GPCR, GPCR_GEP_CNTL);    /* Let GPIO0 output */
 
+        dm9000_phy_write(dev, 0, MII_BMCR, BMCR_RESET); /* PHY RESET */
+        dm9000_phy_write(dev, 0, MII_DM_DSPCR, DSPCR_INIT_PARAM); /* Init */
+
         ncr = (db->flags & DM9000_PLATF_EXT_PHY) ? NCR_EXT_PHY : 0;
 
         /* if wol is needed, then always set NCR_WAKEEN otherwise we end
@@ -1201,109 +1305,6 @@ dm9000_open(struct net_device *dev)
         return 0;
 }
 
-/*
- * Sleep, either by using msleep() or if we are suspending, then
- * use mdelay() to sleep.
- */
-static void dm9000_msleep(board_info_t *db, unsigned int ms)
-{
-        if (db->in_suspend)
-                mdelay(ms);
-        else
-                msleep(ms);
-}
-
-/*
- *   Read a word from phyxcer
- */
-static int
-dm9000_phy_read(struct net_device *dev, int phy_reg_unused, int reg)
-{
-        board_info_t *db = netdev_priv(dev);
-        unsigned long flags;
-        unsigned int reg_save;
-        int ret;
-
-        mutex_lock(&db->addr_lock);
-
-        spin_lock_irqsave(&db->lock,flags);
-
-        /* Save previous register address */
-        reg_save = readb(db->io_addr);
-
-        /* Fill the phyxcer register into REG_0C */
-        iow(db, DM9000_EPAR, DM9000_PHY | reg);
-
-        iow(db, DM9000_EPCR, EPCR_ERPRR | EPCR_EPOS);   /* Issue phyxcer read command */
-
-        writeb(reg_save, db->io_addr);
-        spin_unlock_irqrestore(&db->lock,flags);
-
-        dm9000_msleep(db, 1);           /* Wait read complete */
-
-        spin_lock_irqsave(&db->lock,flags);
-        reg_save = readb(db->io_addr);
-
-        iow(db, DM9000_EPCR, 0x0);      /* Clear phyxcer read command */
-
-        /* The read data keeps on REG_0D & REG_0E */
-        ret = (ior(db, DM9000_EPDRH) << 8) | ior(db, DM9000_EPDRL);
-
-        /* restore the previous address */
-        writeb(reg_save, db->io_addr);
-        spin_unlock_irqrestore(&db->lock,flags);
-
-        mutex_unlock(&db->addr_lock);
-
-        dm9000_dbg(db, 5, "phy_read[%02x] -> %04x\n", reg, ret);
-        return ret;
-}
-
-/*
- *   Write a word to phyxcer
- */
-static void
-dm9000_phy_write(struct net_device *dev,
-                 int phyaddr_unused, int reg, int value)
-{
-        board_info_t *db = netdev_priv(dev);
-        unsigned long flags;
-        unsigned long reg_save;
-
-        dm9000_dbg(db, 5, "phy_write[%02x] = %04x\n", reg, value);
-        mutex_lock(&db->addr_lock);
-
-        spin_lock_irqsave(&db->lock,flags);
-
-        /* Save previous register address */
-        reg_save = readb(db->io_addr);
-
-        /* Fill the phyxcer register into REG_0C */
-        iow(db, DM9000_EPAR, DM9000_PHY | reg);
-
-        /* Fill the written data into REG_0D & REG_0E */
-        iow(db, DM9000_EPDRL, value);
-        iow(db, DM9000_EPDRH, value >> 8);
-
-        iow(db, DM9000_EPCR, EPCR_EPOS | EPCR_ERPRW);   /* Issue phyxcer write command */
-
-        writeb(reg_save, db->io_addr);
-        spin_unlock_irqrestore(&db->lock, flags);
-
-        dm9000_msleep(db, 1);           /* Wait write complete */
-
-        spin_lock_irqsave(&db->lock,flags);
-        reg_save = readb(db->io_addr);
-
-        iow(db, DM9000_EPCR, 0x0);      /* Clear phyxcer write command */
-
-        /* restore the previous address */
-        writeb(reg_save, db->io_addr);
-
-        spin_unlock_irqrestore(&db->lock, flags);
-        mutex_unlock(&db->addr_lock);
-}
-
 static void
 dm9000_shutdown(struct net_device *dev)
 {
@@ -1502,7 +1503,12 @@ dm9000_probe(struct platform_device *pdev)
         db->flags |= DM9000_PLATF_SIMPLE_PHY;
 #endif
 
-        dm9000_reset(db);
+        /* Fixing bug on dm9000_probe, takeover dm9000_reset(db),
+         * Need 'NCR_MAC_LBK' bit to indeed stable our DM9000 fifo
+         * while probe stage.
+         */
+
+        iow(db, DM9000_NCR, NCR_MAC_LBK | NCR_RST);
 
         /* try multiple times, DM9000 sometimes gets the read wrong */
         for (i = 0; i < 8; i++) {
diff --git a/drivers/net/ethernet/davicom/dm9000.h b/drivers/net/ethernet/davicom/dm9000.h
index 55688bd1a3ef..9ce058adabab 100644
--- a/drivers/net/ethernet/davicom/dm9000.h
+++ b/drivers/net/ethernet/davicom/dm9000.h
@@ -69,7 +69,9 @@
 #define NCR_WAKEEN          (1<<6)
 #define NCR_FCOL            (1<<4)
 #define NCR_FDX             (1<<3)
-#define NCR_LBK             (3<<1)
+
+#define NCR_RESERVED        (3<<1)
+#define NCR_MAC_LBK         (1<<1)
 #define NCR_RST             (1<<0)
 
 #define NSR_SPEED           (1<<7)
@@ -167,5 +169,12 @@
 #define ISR_LNKCHNG             (1<<5)
 #define ISR_UNDERRUN            (1<<4)
 
+/* Davicom MII registers.
+ */
+
+#define MII_DM_DSPCR            0x1b    /* DSP Control Register */
+
+#define DSPCR_INIT_PARAM        0xE100  /* DSP init parameter */
+
 #endif /* _DM9000X_H_ */
 
diff --git a/drivers/net/ethernet/freescale/fec.c b/drivers/net/ethernet/freescale/fec.c
index 911d0253dbb2..f292c3aa423f 100644
--- a/drivers/net/ethernet/freescale/fec.c
+++ b/drivers/net/ethernet/freescale/fec.c
@@ -345,6 +345,53 @@ fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
         return NETDEV_TX_OK;
 }
 
+/* Init RX & TX buffer descriptors
+ */
+static void fec_enet_bd_init(struct net_device *dev)
+{
+        struct fec_enet_private *fep = netdev_priv(dev);
+        struct bufdesc *bdp;
+        unsigned int i;
+
+        /* Initialize the receive buffer descriptors. */
+        bdp = fep->rx_bd_base;
+        for (i = 0; i < RX_RING_SIZE; i++) {
+
+                /* Initialize the BD for every fragment in the page. */
+                if (bdp->cbd_bufaddr)
+                        bdp->cbd_sc = BD_ENET_RX_EMPTY;
+                else
+                        bdp->cbd_sc = 0;
+                bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
+        }
+
+        /* Set the last buffer to wrap */
+        bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
+        bdp->cbd_sc |= BD_SC_WRAP;
+
+        fep->cur_rx = fep->rx_bd_base;
+
+        /* ...and the same for transmit */
+        bdp = fep->tx_bd_base;
+        fep->cur_tx = bdp;
+        for (i = 0; i < TX_RING_SIZE; i++) {
+
+                /* Initialize the BD for every fragment in the page. */
+                bdp->cbd_sc = 0;
+                if (bdp->cbd_bufaddr && fep->tx_skbuff[i]) {
+                        dev_kfree_skb_any(fep->tx_skbuff[i]);
+                        fep->tx_skbuff[i] = NULL;
+                }
+                bdp->cbd_bufaddr = 0;
+                bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
+        }
+
+        /* Set the last buffer to wrap */
+        bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
+        bdp->cbd_sc |= BD_SC_WRAP;
+        fep->dirty_tx = bdp;
+}
+
 /* This function is called to start or restart the FEC during a link
  * change.  This only happens when switching between half and full
  * duplex.
@@ -388,6 +435,8 @@ fec_restart(struct net_device *ndev, int duplex)
         /* Set maximum receive buffer size. */
         writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
 
+        fec_enet_bd_init(ndev);
+
         /* Set receive and transmit descriptor base. */
         writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
         if (fep->bufdesc_ex)
@@ -397,7 +446,6 @@ fec_restart(struct net_device *ndev, int duplex)
                 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc)
                         * RX_RING_SIZE, fep->hwp + FEC_X_DES_START);
 
-        fep->cur_rx = fep->rx_bd_base;
 
         for (i = 0; i <= TX_RING_MOD_MASK; i++) {
                 if (fep->tx_skbuff[i]) {
@@ -1597,8 +1645,6 @@ static int fec_enet_init(struct net_device *ndev)
 {
         struct fec_enet_private *fep = netdev_priv(ndev);
         struct bufdesc *cbd_base;
-        struct bufdesc *bdp;
-        unsigned int i;
 
         /* Allocate memory for buffer descriptors. */
         cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma,
@@ -1608,6 +1654,7 @@ static int fec_enet_init(struct net_device *ndev)
                 return -ENOMEM;
         }
 
+        memset(cbd_base, 0, PAGE_SIZE);
         spin_lock_init(&fep->hw_lock);
 
         fep->netdev = ndev;
@@ -1631,35 +1678,6 @@ static int fec_enet_init(struct net_device *ndev)
         writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
         netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, FEC_NAPI_WEIGHT);
 
-        /* Initialize the receive buffer descriptors. */
-        bdp = fep->rx_bd_base;
-        for (i = 0; i < RX_RING_SIZE; i++) {
-
-                /* Initialize the BD for every fragment in the page. */
-                bdp->cbd_sc = 0;
-                bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
-        }
-
-        /* Set the last buffer to wrap */
-        bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
-        bdp->cbd_sc |= BD_SC_WRAP;
-
-        /* ...and the same for transmit */
-        bdp = fep->tx_bd_base;
-        fep->cur_tx = bdp;
-        for (i = 0; i < TX_RING_SIZE; i++) {
-
-                /* Initialize the BD for every fragment in the page. */
-                bdp->cbd_sc = 0;
-                bdp->cbd_bufaddr = 0;
-                bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
-        }
-
-        /* Set the last buffer to wrap */
-        bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
-        bdp->cbd_sc |= BD_SC_WRAP;
-        fep->dirty_tx = bdp;
-
         fec_restart(ndev, 0);
 
         return 0;
diff --git a/drivers/net/ethernet/intel/e1000/e1000_ethtool.c b/drivers/net/ethernet/intel/e1000/e1000_ethtool.c
index 43462d596a4e..ffd287196bf8 100644
--- a/drivers/net/ethernet/intel/e1000/e1000_ethtool.c
+++ b/drivers/net/ethernet/intel/e1000/e1000_ethtool.c
@@ -1053,6 +1053,10 @@ static int e1000_setup_desc_rings(struct e1000_adapter *adapter)
                 txdr->buffer_info[i].dma =
                         dma_map_single(&pdev->dev, skb->data, skb->len,
                                        DMA_TO_DEVICE);
+                if (dma_mapping_error(&pdev->dev, txdr->buffer_info[i].dma)) {
+                        ret_val = 4;
+                        goto err_nomem;
+                }
                 tx_desc->buffer_addr = cpu_to_le64(txdr->buffer_info[i].dma);
                 tx_desc->lower.data = cpu_to_le32(skb->len);
                 tx_desc->lower.data |= cpu_to_le32(E1000_TXD_CMD_EOP |
@@ -1069,7 +1073,7 @@ static int e1000_setup_desc_rings(struct e1000_adapter *adapter)
         rxdr->buffer_info = kcalloc(rxdr->count, sizeof(struct e1000_buffer),
                                     GFP_KERNEL);
         if (!rxdr->buffer_info) {
-                ret_val = 4;
+                ret_val = 5;
                 goto err_nomem;
         }
 
@@ -1077,7 +1081,7 @@ static int e1000_setup_desc_rings(struct e1000_adapter *adapter)
         rxdr->desc = dma_alloc_coherent(&pdev->dev, rxdr->size, &rxdr->dma,
                                         GFP_KERNEL);
         if (!rxdr->desc) {
-                ret_val = 5;
+                ret_val = 6;
                 goto err_nomem;
         }
         memset(rxdr->desc, 0, rxdr->size);
@@ -1101,7 +1105,7 @@ static int e1000_setup_desc_rings(struct e1000_adapter *adapter)
 
                 skb = alloc_skb(E1000_RXBUFFER_2048 + NET_IP_ALIGN, GFP_KERNEL);
                 if (!skb) {
-                        ret_val = 6;
+                        ret_val = 7;
                         goto err_nomem;
                 }
                 skb_reserve(skb, NET_IP_ALIGN);
@@ -1110,6 +1114,10 @@ static int e1000_setup_desc_rings(struct e1000_adapter *adapter)
                 rxdr->buffer_info[i].dma =
                         dma_map_single(&pdev->dev, skb->data,
                                        E1000_RXBUFFER_2048, DMA_FROM_DEVICE);
+                if (dma_mapping_error(&pdev->dev, rxdr->buffer_info[i].dma)) {
+                        ret_val = 8;
+                        goto err_nomem;
+                }
                 rx_desc->buffer_addr = cpu_to_le64(rxdr->buffer_info[i].dma);
                 memset(skb->data, 0x00, skb->len);
         }
diff --git a/drivers/net/ethernet/intel/e1000e/netdev.c b/drivers/net/ethernet/intel/e1000e/netdev.c
index 948b86ffa4f0..7e615e2bf7e6 100644
--- a/drivers/net/ethernet/intel/e1000e/netdev.c
+++ b/drivers/net/ethernet/intel/e1000e/netdev.c
@@ -848,11 +848,16 @@ check_page:
                         }
                 }
 
-                if (!buffer_info->dma)
+                if (!buffer_info->dma) {
                         buffer_info->dma = dma_map_page(&pdev->dev,
                                                         buffer_info->page, 0,
                                                         PAGE_SIZE,
                                                         DMA_FROM_DEVICE);
+                        if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
+                                adapter->alloc_rx_buff_failed++;
+                                break;
+                        }
+                }
 
                 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
                 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
diff --git a/drivers/net/ethernet/intel/ixgb/ixgb_main.c b/drivers/net/ethernet/intel/ixgb/ixgb_main.c
index ea4808373435..b5f94abe3cff 100644
--- a/drivers/net/ethernet/intel/ixgb/ixgb_main.c
+++ b/drivers/net/ethernet/intel/ixgb/ixgb_main.c
@@ -2159,6 +2159,10 @@ map_skb:
                                                   skb->data,
                                                   adapter->rx_buffer_len,
                                                   DMA_FROM_DEVICE);
+                if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
+                        adapter->alloc_rx_buff_failed++;
+                        break;
+                }
 
                 rx_desc = IXGB_RX_DESC(*rx_ring, i);
                 rx_desc->buff_addr = cpu_to_le64(buffer_info->dma);
@@ -2168,7 +2172,8 @@ map_skb:
                 rx_desc->status = 0;
 
 
-                if (++i == rx_ring->count) i = 0;
+                if (++i == rx_ring->count)
+                        i = 0;
                 buffer_info = &rx_ring->buffer_info[i];
         }
 
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
index db5611ae407e..79f4a26ea6cc 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
@@ -7922,12 +7922,19 @@ static int __init ixgbe_init_module(void)
         ixgbe_dbg_init();
 #endif /* CONFIG_DEBUG_FS */
 
+        ret = pci_register_driver(&ixgbe_driver);
+        if (ret) {
+#ifdef CONFIG_DEBUG_FS
+                ixgbe_dbg_exit();
+#endif /* CONFIG_DEBUG_FS */
+                return ret;
+        }
+
 #ifdef CONFIG_IXGBE_DCA
         dca_register_notify(&dca_notifier);
 #endif
 
-        ret = pci_register_driver(&ixgbe_driver);
-        return ret;
+        return 0;
 }
 
 module_init(ixgbe_init_module);
diff --git a/drivers/net/ethernet/marvell/sky2.c b/drivers/net/ethernet/marvell/sky2.c
index fc07ca35721b..6a0e671fcecd 100644
--- a/drivers/net/ethernet/marvell/sky2.c
+++ b/drivers/net/ethernet/marvell/sky2.c
@@ -1067,7 +1067,7 @@ static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
                 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
                 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
 
-                tp = space - 2048/8;
+                tp = space - 8192/8;
                 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
                 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
         } else {
diff --git a/drivers/net/ethernet/marvell/sky2.h b/drivers/net/ethernet/marvell/sky2.h
index 615ac63ea860..ec6dcd80152b 100644
--- a/drivers/net/ethernet/marvell/sky2.h
+++ b/drivers/net/ethernet/marvell/sky2.h
@@ -2074,7 +2074,7 @@ enum {
         GM_IS_RX_FF_OR  = 1<<1, /* Receive FIFO Overrun */
         GM_IS_RX_COMPL  = 1<<0, /* Frame Reception Complete */
 
-#define GMAC_DEF_MSK     GM_IS_TX_FF_UR
+#define GMAC_DEF_MSK     (GM_IS_TX_FF_UR | GM_IS_RX_FF_OR)
 };
 
 /*      GMAC_LINK_CTRL  16 bit  GMAC Link Control Reg (YUKON only) */
diff --git a/drivers/net/ethernet/mellanox/mlx4/en_netdev.c b/drivers/net/ethernet/mellanox/mlx4/en_netdev.c
index f278b10ef714..30d78f806dc3 100644
--- a/drivers/net/ethernet/mellanox/mlx4/en_netdev.c
+++ b/drivers/net/ethernet/mellanox/mlx4/en_netdev.c
@@ -411,8 +411,8 @@ static int mlx4_en_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
 
 static void mlx4_en_u64_to_mac(unsigned char dst_mac[ETH_ALEN + 2], u64 src_mac)
 {
-        unsigned int i;
-        for (i = ETH_ALEN - 1; i; --i) {
+        int i;
+        for (i = ETH_ALEN - 1; i >= 0; --i) {
                 dst_mac[i] = src_mac & 0xff;
                 src_mac >>= 8;
         }
diff --git a/drivers/net/ethernet/micrel/ks8851.c b/drivers/net/ethernet/micrel/ks8851.c
index 33bcb63d56a2..8fb481252e2c 100644
--- a/drivers/net/ethernet/micrel/ks8851.c
+++ b/drivers/net/ethernet/micrel/ks8851.c
@@ -528,7 +528,7 @@ static void ks8851_rx_pkts(struct ks8851_net *ks)
         for (; rxfc != 0; rxfc--) {
                 rxh = ks8851_rdreg32(ks, KS_RXFHSR);
                 rxstat = rxh & 0xffff;
-                rxlen = rxh >> 16;
+                rxlen = (rxh >> 16) & 0xfff;
 
                 netif_dbg(ks, rx_status, ks->netdev,
                           "rx: stat 0x%04x, len 0x%04x\n", rxstat, rxlen);
diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169.c
index 28fb50a1e9c3..4ecbe64a758d 100644
--- a/drivers/net/ethernet/realtek/r8169.c
+++ b/drivers/net/ethernet/realtek/r8169.c
@@ -3818,6 +3818,30 @@ static void rtl_init_mdio_ops(struct rtl8169_private *tp)
         }
 }
 
+static void rtl_speed_down(struct rtl8169_private *tp)
+{
+        u32 adv;
+        int lpa;
+
+        rtl_writephy(tp, 0x1f, 0x0000);
+        lpa = rtl_readphy(tp, MII_LPA);
+
+        if (lpa & (LPA_10HALF | LPA_10FULL))
+                adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
+        else if (lpa & (LPA_100HALF | LPA_100FULL))
+                adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
+                      ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
+        else
+                adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
+                      ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
+                      (tp->mii.supports_gmii ?
+                       ADVERTISED_1000baseT_Half |
+                       ADVERTISED_1000baseT_Full : 0);
+
+        rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
+                          adv);
+}
+
 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
 {
         void __iomem *ioaddr = tp->mmio_addr;
@@ -3848,9 +3872,7 @@ static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
         if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
                 return false;
 
-        rtl_writephy(tp, 0x1f, 0x0000);
-        rtl_writephy(tp, MII_BMCR, 0x0000);
-
+        rtl_speed_down(tp);
         rtl_wol_suspend_quirk(tp);
 
         return true;
diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
index bf5e3cf97c4d..6ed333fe5c04 100644
--- a/drivers/net/ethernet/renesas/sh_eth.c
+++ b/drivers/net/ethernet/renesas/sh_eth.c
@@ -1216,10 +1216,7 @@ static void sh_eth_error(struct net_device *ndev, int intr_status)
                 if (felic_stat & ECSR_LCHNG) {
                         /* Link Changed */
                         if (mdp->cd->no_psr || mdp->no_ether_link) {
-                                if (mdp->link == PHY_DOWN)
-                                        link_stat = 0;
-                                else
-                                        link_stat = PHY_ST_LINK;
+                                goto ignore_link;
                         } else {
                                 link_stat = (sh_eth_read(ndev, PSR));
                                 if (mdp->ether_link_active_low)
@@ -1242,6 +1239,7 @@ static void sh_eth_error(struct net_device *ndev, int intr_status)
                 }
         }
 
+ignore_link:
         if (intr_status & EESR_TWB) {
                 /* Write buck end. unused write back interrupt */
                 if (intr_status & EESR_TABT)    /* Transmit Abort int */
@@ -1326,12 +1324,18 @@ static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
         struct sh_eth_private *mdp = netdev_priv(ndev);
         struct sh_eth_cpu_data *cd = mdp->cd;
         irqreturn_t ret = IRQ_NONE;
-        u32 intr_status = 0;
+        unsigned long intr_status;
 
         spin_lock(&mdp->lock);
 
-        /* Get interrpt stat */
+        /* Get interrupt status */
         intr_status = sh_eth_read(ndev, EESR);
+        /* Mask it with the interrupt mask, forcing ECI interrupt to be always
+         * enabled since it's the one that  comes thru regardless of the mask,
+         * and we need to fully handle it in sh_eth_error() in order to quench
+         * it as it doesn't get cleared by just writing 1 to the ECI bit...
+         */
+        intr_status &= sh_eth_read(ndev, EESIPR) | DMAC_M_ECI;
         /* Clear interrupt */
         if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF |
                         EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF |
@@ -1373,7 +1377,7 @@ static void sh_eth_adjust_link(struct net_device *ndev)
         struct phy_device *phydev = mdp->phydev;
         int new_state = 0;
 
-        if (phydev->link != PHY_DOWN) {
+        if (phydev->link) {
                 if (phydev->duplex != mdp->duplex) {
                         new_state = 1;
                         mdp->duplex = phydev->duplex;
@@ -1387,17 +1391,21 @@ static void sh_eth_adjust_link(struct net_device *ndev)
                         if (mdp->cd->set_rate)
                                 mdp->cd->set_rate(ndev);
                 }
-                if (mdp->link == PHY_DOWN) {
+                if (!mdp->link) {
                         sh_eth_write(ndev,
                                 (sh_eth_read(ndev, ECMR) & ~ECMR_TXF), ECMR);
                         new_state = 1;
                         mdp->link = phydev->link;
+                        if (mdp->cd->no_psr || mdp->no_ether_link)
+                                sh_eth_rcv_snd_enable(ndev);
                 }
         } else if (mdp->link) {
                 new_state = 1;
-                mdp->link = PHY_DOWN;
+                mdp->link = 0;
                 mdp->speed = 0;
                 mdp->duplex = -1;
+                if (mdp->cd->no_psr || mdp->no_ether_link)
+                        sh_eth_rcv_snd_disable(ndev);
         }
 
         if (new_state && netif_msg_link(mdp))
@@ -1414,7 +1422,7 @@ static int sh_eth_phy_init(struct net_device *ndev)
         snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
                 mdp->mii_bus->id , mdp->phy_id);
 
-        mdp->link = PHY_DOWN;
+        mdp->link = 0;
         mdp->speed = 0;
         mdp->duplex = -1;
 
diff --git a/drivers/net/ethernet/renesas/sh_eth.h b/drivers/net/ethernet/renesas/sh_eth.h
index e6655678458e..828be4515008 100644
--- a/drivers/net/ethernet/renesas/sh_eth.h
+++ b/drivers/net/ethernet/renesas/sh_eth.h
@@ -723,7 +723,7 @@ struct sh_eth_private {
         u32 phy_id;                                     /* PHY ID */
         struct mii_bus *mii_bus;        /* MDIO bus control */
         struct phy_device *phydev;      /* PHY device control */
-        enum phy_state link;
+        int link;
         phy_interface_t phy_interface;
         int msg_enable;
         int speed;
diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index df32a090d08e..80cad06e5eb2 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -436,7 +436,7 @@ void cpsw_tx_handler(void *token, int len, int status)
          * queue is stopped then start the queue as we have free desc for tx
          */
         if (unlikely(netif_queue_stopped(ndev)))
-                netif_start_queue(ndev);
+                netif_wake_queue(ndev);
         cpts_tx_timestamp(priv->cpts, skb);
         priv->stats.tx_packets++;
         priv->stats.tx_bytes += len;
diff --git a/drivers/net/ethernet/ti/davinci_emac.c b/drivers/net/ethernet/ti/davinci_emac.c
index ae1b77aa199f..72300bc9e378 100644
--- a/drivers/net/ethernet/ti/davinci_emac.c
+++ b/drivers/net/ethernet/ti/davinci_emac.c
@@ -1053,7 +1053,7 @@ static void emac_tx_handler(void *token, int len, int status)
          * queue is stopped then start the queue as we have free desc for tx
          */
         if (unlikely(netif_queue_stopped(ndev)))
-                netif_start_queue(ndev);
+                netif_wake_queue(ndev);
         ndev->stats.tx_packets++;
         ndev->stats.tx_bytes += len;
         dev_kfree_skb_any(skb);
diff --git a/drivers/net/usb/smsc75xx.c b/drivers/net/usb/smsc75xx.c
index 9abe51710f22..1a15ec14c386 100644
--- a/drivers/net/usb/smsc75xx.c
+++ b/drivers/net/usb/smsc75xx.c
@@ -914,8 +914,12 @@ static int smsc75xx_set_rx_max_frame_length(struct usbnet *dev, int size)
 static int smsc75xx_change_mtu(struct net_device *netdev, int new_mtu)
 {
         struct usbnet *dev = netdev_priv(netdev);
+        int ret;
+
+        if (new_mtu > MAX_SINGLE_PACKET_SIZE)
+                return -EINVAL;
 
-        int ret = smsc75xx_set_rx_max_frame_length(dev, new_mtu);
+        ret = smsc75xx_set_rx_max_frame_length(dev, new_mtu + ETH_HLEN);
         if (ret < 0) {
                 netdev_warn(dev->net, "Failed to set mac rx frame length\n");
                 return ret;
@@ -1324,7 +1328,7 @@ static int smsc75xx_reset(struct usbnet *dev)
 
         netif_dbg(dev, ifup, dev->net, "FCT_TX_CTL set to 0x%08x\n", buf);
 
-        ret = smsc75xx_set_rx_max_frame_length(dev, 1514);
+        ret = smsc75xx_set_rx_max_frame_length(dev, dev->net->mtu + ETH_HLEN);
         if (ret < 0) {
                 netdev_warn(dev->net, "Failed to set max rx frame length\n");
                 return ret;
@@ -2134,8 +2138,8 @@ static int smsc75xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
                         else if (rx_cmd_a & (RX_CMD_A_LONG | RX_CMD_A_RUNT))
                                 dev->net->stats.rx_frame_errors++;
                 } else {
-                        /* ETH_FRAME_LEN + 4(CRC) + 2(COE) + 4(Vlan) */
-                        if (unlikely(size > (ETH_FRAME_LEN + 12))) {
+                        /* MAX_SINGLE_PACKET_SIZE + 4(CRC) + 2(COE) + 4(Vlan) */
+                        if (unlikely(size > (MAX_SINGLE_PACKET_SIZE + ETH_HLEN + 12))) {
                                 netif_dbg(dev, rx_err, dev->net,
                                           "size err rx_cmd_a=0x%08x\n",
                                           rx_cmd_a);
diff --git a/drivers/net/wireless/ath/ath9k/link.c b/drivers/net/wireless/ath/ath9k/link.c
index 39c84ecf6a42..7fdac6c7b3ea 100644
--- a/drivers/net/wireless/ath/ath9k/link.c
+++ b/drivers/net/wireless/ath/ath9k/link.c
@@ -170,7 +170,8 @@ void ath_rx_poll(unsigned long data)
 {
         struct ath_softc *sc = (struct ath_softc *)data;
 
-        ieee80211_queue_work(sc->hw, &sc->hw_check_work);
+        if (!test_bit(SC_OP_INVALID, &sc->sc_flags))
+                ieee80211_queue_work(sc->hw, &sc->hw_check_work);
 }
 
 /*
diff --git a/drivers/net/wireless/b43/dma.c b/drivers/net/wireless/b43/dma.c
index 38bc5a7997ff..122146943bf2 100644
--- a/drivers/net/wireless/b43/dma.c
+++ b/drivers/net/wireless/b43/dma.c
@@ -1487,8 +1487,12 @@ void b43_dma_handle_txstatus(struct b43_wldev *dev,
         const struct b43_dma_ops *ops;
         struct b43_dmaring *ring;
         struct b43_dmadesc_meta *meta;
+        static const struct b43_txstatus fake; /* filled with 0 */
+        const struct b43_txstatus *txstat;
         int slot, firstused;
         bool frame_succeed;
+        int skip;
+        static u8 err_out1, err_out2;
 
         ring = parse_cookie(dev, status->cookie, &slot);
         if (unlikely(!ring))
@@ -1501,13 +1505,36 @@ void b43_dma_handle_txstatus(struct b43_wldev *dev,
         firstused = ring->current_slot - ring->used_slots + 1;
         if (firstused < 0)
                 firstused = ring->nr_slots + firstused;
+
+        skip = 0;
         if (unlikely(slot != firstused)) {
                 /* This possibly is a firmware bug and will result in
-                 * malfunction, memory leaks and/or stall of DMA functionality. */
-                b43dbg(dev->wl, "Out of order TX status report on DMA ring %d. "
-                       "Expected %d, but got %d\n",
-                       ring->index, firstused, slot);
-                return;
+                 * malfunction, memory leaks and/or stall of DMA functionality.
+                 */
+                if (slot == next_slot(ring, next_slot(ring, firstused))) {
+                        /* If a single header/data pair was missed, skip over
+                         * the first two slots in an attempt to recover.
+                         */
+                        slot = firstused;
+                        skip = 2;
+                        if (!err_out1) {
+                                /* Report the error once. */
+                                b43dbg(dev->wl,
+                                       "Skip on DMA ring %d slot %d.\n",
+                                       ring->index, slot);
+                                err_out1 = 1;
+                        }
+                } else {
+                        /* More than a single header/data pair were missed.
+                         * Report this error once.
+                         */
+                        if (!err_out2)
+                                b43dbg(dev->wl,
+                                       "Out of order TX status report on DMA ring %d. Expected %d, but got %d\n",
+                                       ring->index, firstused, slot);
+                        err_out2 = 1;
+                        return;
+                }
         }
 
         ops = ring->ops;
@@ -1522,11 +1549,13 @@ void b43_dma_handle_txstatus(struct b43_wldev *dev,
                                slot, firstused, ring->index);
                         break;
                 }
+
                 if (meta->skb) {
                         struct b43_private_tx_info *priv_info =
-                                b43_get_priv_tx_info(IEEE80211_SKB_CB(meta->skb));
+                             b43_get_priv_tx_info(IEEE80211_SKB_CB(meta->skb));
 
-                        unmap_descbuffer(ring, meta->dmaaddr, meta->skb->len, 1);
+                        unmap_descbuffer(ring, meta->dmaaddr,
+                                         meta->skb->len, 1);
                         kfree(priv_info->bouncebuffer);
                         priv_info->bouncebuffer = NULL;
                 } else {
@@ -1538,8 +1567,9 @@ void b43_dma_handle_txstatus(struct b43_wldev *dev,
                         struct ieee80211_tx_info *info;
 
                         if (unlikely(!meta->skb)) {
-                                /* This is a scatter-gather fragment of a frame, so
-                                 * the skb pointer must not be NULL. */
+                                /* This is a scatter-gather fragment of a frame,
+                                 * so the skb pointer must not be NULL.
+                                 */
                                 b43dbg(dev->wl, "TX status unexpected NULL skb "
                                        "at slot %d (first=%d) on ring %d\n",
                                        slot, firstused, ring->index);
@@ -1550,9 +1580,18 @@ void b43_dma_handle_txstatus(struct b43_wldev *dev,
 
                         /*
                          * Call back to inform the ieee80211 subsystem about
-                         * the status of the transmission.
+                         * the status of the transmission. When skipping over
+                         * a missed TX status report, use a status structure
+                         * filled with zeros to indicate that the frame was not
+                         * sent (frame_count 0) and not acknowledged
                          */
-                        frame_succeed = b43_fill_txstatus_report(dev, info, status);
+                        if (unlikely(skip))
+                                txstat = &fake;
+                        else
+                                txstat = status;
+
+                        frame_succeed = b43_fill_txstatus_report(dev, info,
+                                                                 txstat);
 #ifdef CONFIG_B43_DEBUG
                         if (frame_succeed)
                                 ring->nr_succeed_tx_packets++;
@@ -1580,12 +1619,14 @@ void b43_dma_handle_txstatus(struct b43_wldev *dev,
                 /* Everything unmapped and free'd. So it's not used anymore. */
                 ring->used_slots--;
 
-                if (meta->is_last_fragment) {
+                if (meta->is_last_fragment && !skip) {
                         /* This is the last scatter-gather
                          * fragment of the frame. We are done. */
                         break;
                 }
                 slot = next_slot(ring, slot);
+                if (skip > 0)
+                        --skip;
         }
         if (ring->stopped) {
                 B43_WARN_ON(free_slots(ring) < TX_SLOTS_PER_FRAME);
diff --git a/drivers/net/wireless/b43/phy_n.c b/drivers/net/wireless/b43/phy_n.c
index 3c35382ee6c2..e8486c1e091a 100644
--- a/drivers/net/wireless/b43/phy_n.c
+++ b/drivers/net/wireless/b43/phy_n.c
@@ -1564,7 +1564,7 @@ static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
         u16 clip_off[2] = { 0xFFFF, 0xFFFF };
 
         u8 vcm_final = 0;
-        s8 offset[4];
+        s32 offset[4];
         s32 results[8][4] = { };
         s32 results_min[4] = { };
         s32 poll_results[4] = { };
@@ -1615,7 +1615,7 @@ static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
                 }
                 for (i = 0; i < 4; i += 2) {
                         s32 curr;
-                        s32 mind = 40;
+                        s32 mind = 0x100000;
                         s32 minpoll = 249;
                         u8 minvcm = 0;
                         if (2 * core != i)
@@ -1732,7 +1732,7 @@ static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
         u8 regs_save_radio[2];
         u16 regs_save_phy[2];
 
-        s8 offset[4];
+        s32 offset[4];
         u8 core;
         u8 rail;
 
@@ -1799,7 +1799,7 @@ static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
         }
 
         for (i = 0; i < 4; i++) {
-                s32 mind = 40;
+                s32 mind = 0x100000;
                 u8 minvcm = 0;
                 s32 minpoll = 249;
                 s32 curr;
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_lcn.c b/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_lcn.c
index 21a824232478..18d37645e2cd 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_lcn.c
+++ b/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_lcn.c
@@ -1137,9 +1137,8 @@ wlc_lcnphy_set_rx_gain_by_distribution(struct brcms_phy *pi,
         gain0_15 = ((biq1 & 0xf) << 12) |
                    ((tia & 0xf) << 8) |
                    ((lna2 & 0x3) << 6) |
-                   ((lna2 & 0x3) << 4) |
-                   ((lna1 & 0x3) << 2) |
-                   ((lna1 & 0x3) << 0);
+                   ((lna2 &
+                     0x3) << 4) | ((lna1 & 0x3) << 2) | ((lna1 & 0x3) << 0);
 
         mod_phy_reg(pi, 0x4b6, (0xffff << 0), gain0_15 << 0);
         mod_phy_reg(pi, 0x4b7, (0xf << 0), gain16_19 << 0);
@@ -1157,8 +1156,6 @@ wlc_lcnphy_set_rx_gain_by_distribution(struct brcms_phy *pi,
         }
 
         mod_phy_reg(pi, 0x44d, (0x1 << 0), (!trsw) << 0);
-        mod_phy_reg(pi, 0x4b1, (0x3 << 11), lna1 << 11);
-        mod_phy_reg(pi, 0x4e6, (0x3 << 3), lna1 << 3);
 
 }
 
@@ -1331,43 +1328,6 @@ static u32 wlc_lcnphy_measure_digital_power(struct brcms_phy *pi, u16 nsamples)
         return (iq_est.i_pwr + iq_est.q_pwr) / nsamples;
 }
 
-static bool wlc_lcnphy_rx_iq_cal_gain(struct brcms_phy *pi, u16 biq1_gain,
-                                      u16 tia_gain, u16 lna2_gain)
-{
-        u32 i_thresh_l, q_thresh_l;
-        u32 i_thresh_h, q_thresh_h;
-        struct lcnphy_iq_est iq_est_h, iq_est_l;
-
-        wlc_lcnphy_set_rx_gain_by_distribution(pi, 0, 0, 0, biq1_gain, tia_gain,
-                                               lna2_gain, 0);
-
-        wlc_lcnphy_rx_gain_override_enable(pi, true);
-        wlc_lcnphy_start_tx_tone(pi, 2000, (40 >> 1), 0);
-        udelay(500);
-        write_radio_reg(pi, RADIO_2064_REG112, 0);
-        if (!wlc_lcnphy_rx_iq_est(pi, 1024, 32, &iq_est_l))
-                return false;
-
-        wlc_lcnphy_start_tx_tone(pi, 2000, 40, 0);
-        udelay(500);
-        write_radio_reg(pi, RADIO_2064_REG112, 0);
-        if (!wlc_lcnphy_rx_iq_est(pi, 1024, 32, &iq_est_h))
-                return false;
-
-        i_thresh_l = (iq_est_l.i_pwr << 1);
-        i_thresh_h = (iq_est_l.i_pwr << 2) + iq_est_l.i_pwr;
-
-        q_thresh_l = (iq_est_l.q_pwr << 1);
-        q_thresh_h = (iq_est_l.q_pwr << 2) + iq_est_l.q_pwr;
-        if ((iq_est_h.i_pwr > i_thresh_l) &&
-            (iq_est_h.i_pwr < i_thresh_h) &&
-            (iq_est_h.q_pwr > q_thresh_l) &&
-            (iq_est_h.q_pwr < q_thresh_h))
-                return true;
-
-        return false;
-}
-
 static bool
 wlc_lcnphy_rx_iq_cal(struct brcms_phy *pi,
                      const struct lcnphy_rx_iqcomp *iqcomp,
@@ -1382,8 +1342,8 @@ wlc_lcnphy_rx_iq_cal(struct brcms_phy *pi,
             RFOverrideVal0_old, rfoverride2_old, rfoverride2val_old,
             rfoverride3_old, rfoverride3val_old, rfoverride4_old,
             rfoverride4val_old, afectrlovr_old, afectrlovrval_old;
-        int tia_gain, lna2_gain, biq1_gain;
-        bool set_gain;
+        int tia_gain;
+        u32 received_power, rx_pwr_threshold;
         u16 old_sslpnCalibClkEnCtrl, old_sslpnRxFeClkEnCtrl;
         u16 values_to_save[11];
         s16 *ptr;
@@ -1408,134 +1368,126 @@ wlc_lcnphy_rx_iq_cal(struct brcms_phy *pi,
                 goto cal_done;
         }
 
-        WARN_ON(module != 1);
-        tx_pwr_ctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi);
-        wlc_lcnphy_set_tx_pwr_ctrl(pi, LCNPHY_TX_PWR_CTRL_OFF);
-
-        for (i = 0; i < 11; i++)
-                values_to_save[i] =
-                        read_radio_reg(pi, rxiq_cal_rf_reg[i]);
-        Core1TxControl_old = read_phy_reg(pi, 0x631);
-
-        or_phy_reg(pi, 0x631, 0x0015);
-
-        RFOverride0_old = read_phy_reg(pi, 0x44c);
-        RFOverrideVal0_old = read_phy_reg(pi, 0x44d);
-        rfoverride2_old = read_phy_reg(pi, 0x4b0);
-        rfoverride2val_old = read_phy_reg(pi, 0x4b1);
-        rfoverride3_old = read_phy_reg(pi, 0x4f9);
-        rfoverride3val_old = read_phy_reg(pi, 0x4fa);
-        rfoverride4_old = read_phy_reg(pi, 0x938);
-        rfoverride4val_old = read_phy_reg(pi, 0x939);
-        afectrlovr_old = read_phy_reg(pi, 0x43b);
-        afectrlovrval_old = read_phy_reg(pi, 0x43c);
-        old_sslpnCalibClkEnCtrl = read_phy_reg(pi, 0x6da);
-        old_sslpnRxFeClkEnCtrl = read_phy_reg(pi, 0x6db);
-
-        tx_gain_override_old = wlc_lcnphy_tx_gain_override_enabled(pi);
-        if (tx_gain_override_old) {
-                wlc_lcnphy_get_tx_gain(pi, &old_gains);
-                tx_gain_index_old = pi_lcn->lcnphy_current_index;
-        }
-
-        wlc_lcnphy_set_tx_pwr_by_index(pi, tx_gain_idx);
+        if (module == 1) {
 
-        mod_phy_reg(pi, 0x4f9, (0x1 << 0), 1 << 0);
-        mod_phy_reg(pi, 0x4fa, (0x1 << 0), 0 << 0);
+                tx_pwr_ctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi);
+                wlc_lcnphy_set_tx_pwr_ctrl(pi, LCNPHY_TX_PWR_CTRL_OFF);
 
-        mod_phy_reg(pi, 0x43b, (0x1 << 1), 1 << 1);
-        mod_phy_reg(pi, 0x43c, (0x1 << 1), 0 << 1);
+                for (i = 0; i < 11; i++)
+                        values_to_save[i] =
+                                read_radio_reg(pi, rxiq_cal_rf_reg[i]);
+                Core1TxControl_old = read_phy_reg(pi, 0x631);
+
+                or_phy_reg(pi, 0x631, 0x0015);
+
+                RFOverride0_old = read_phy_reg(pi, 0x44c);
+                RFOverrideVal0_old = read_phy_reg(pi, 0x44d);
+                rfoverride2_old = read_phy_reg(pi, 0x4b0);
+                rfoverride2val_old = read_phy_reg(pi, 0x4b1);
+                rfoverride3_old = read_phy_reg(pi, 0x4f9);
+                rfoverride3val_old = read_phy_reg(pi, 0x4fa);
+                rfoverride4_old = read_phy_reg(pi, 0x938);
+                rfoverride4val_old = read_phy_reg(pi, 0x939);
+                afectrlovr_old = read_phy_reg(pi, 0x43b);
+                afectrlovrval_old = read_phy_reg(pi, 0x43c);
+                old_sslpnCalibClkEnCtrl = read_phy_reg(pi, 0x6da);
+                old_sslpnRxFeClkEnCtrl = read_phy_reg(pi, 0x6db);
+
+                tx_gain_override_old = wlc_lcnphy_tx_gain_override_enabled(pi);
+                if (tx_gain_override_old) {
+                        wlc_lcnphy_get_tx_gain(pi, &old_gains);
+                        tx_gain_index_old = pi_lcn->lcnphy_current_index;
+                }
 
-        write_radio_reg(pi, RADIO_2064_REG116, 0x06);
-        write_radio_reg(pi, RADIO_2064_REG12C, 0x07);
-        write_radio_reg(pi, RADIO_2064_REG06A, 0xd3);
-        write_radio_reg(pi, RADIO_2064_REG098, 0x03);
-        write_radio_reg(pi, RADIO_2064_REG00B, 0x7);
-        mod_radio_reg(pi, RADIO_2064_REG113, 1 << 4, 1 << 4);
-        write_radio_reg(pi, RADIO_2064_REG01D, 0x01);
-        write_radio_reg(pi, RADIO_2064_REG114, 0x01);
-        write_radio_reg(pi, RADIO_2064_REG02E, 0x10);
-        write_radio_reg(pi, RADIO_2064_REG12A, 0x08);
-
-        mod_phy_reg(pi, 0x938, (0x1 << 0), 1 << 0);
-        mod_phy_reg(pi, 0x939, (0x1 << 0), 0 << 0);
-        mod_phy_reg(pi, 0x938, (0x1 << 1), 1 << 1);
-        mod_phy_reg(pi, 0x939, (0x1 << 1), 1 << 1);
-        mod_phy_reg(pi, 0x938, (0x1 << 2), 1 << 2);
-        mod_phy_reg(pi, 0x939, (0x1 << 2), 1 << 2);
-        mod_phy_reg(pi, 0x938, (0x1 << 3), 1 << 3);
-        mod_phy_reg(pi, 0x939, (0x1 << 3), 1 << 3);
-        mod_phy_reg(pi, 0x938, (0x1 << 5), 1 << 5);
-        mod_phy_reg(pi, 0x939, (0x1 << 5), 0 << 5);
+                wlc_lcnphy_set_tx_pwr_by_index(pi, tx_gain_idx);
 
-        mod_phy_reg(pi, 0x43b, (0x1 << 0), 1 << 0);
-        mod_phy_reg(pi, 0x43c, (0x1 << 0), 0 << 0);
+                mod_phy_reg(pi, 0x4f9, (0x1 << 0), 1 << 0);
+                mod_phy_reg(pi, 0x4fa, (0x1 << 0), 0 << 0);
 
-        write_phy_reg(pi, 0x6da, 0xffff);
-        or_phy_reg(pi, 0x6db, 0x3);
+                mod_phy_reg(pi, 0x43b, (0x1 << 1), 1 << 1);
+                mod_phy_reg(pi, 0x43c, (0x1 << 1), 0 << 1);
 
-        wlc_lcnphy_set_trsw_override(pi, tx_switch, rx_switch);
-        set_gain = false;
-
-        lna2_gain = 3;
-        while ((lna2_gain >= 0) && !set_gain) {
-                tia_gain = 4;
-
-                while ((tia_gain >= 0) && !set_gain) {
-                        biq1_gain = 6;
-
-                        while ((biq1_gain >= 0) && !set_gain) {
-                                set_gain = wlc_lcnphy_rx_iq_cal_gain(pi,
-                                                                     (u16)
-                                                                     biq1_gain,
-                                                                     (u16)
-                                                                     tia_gain,
-                                                                     (u16)
-                                                                     lna2_gain);
-                                biq1_gain -= 1;
-                        }
+                write_radio_reg(pi, RADIO_2064_REG116, 0x06);
+                write_radio_reg(pi, RADIO_2064_REG12C, 0x07);
+                write_radio_reg(pi, RADIO_2064_REG06A, 0xd3);
+                write_radio_reg(pi, RADIO_2064_REG098, 0x03);
+                write_radio_reg(pi, RADIO_2064_REG00B, 0x7);
+                mod_radio_reg(pi, RADIO_2064_REG113, 1 << 4, 1 << 4);
+                write_radio_reg(pi, RADIO_2064_REG01D, 0x01);
+                write_radio_reg(pi, RADIO_2064_REG114, 0x01);
+                write_radio_reg(pi, RADIO_2064_REG02E, 0x10);
+                write_radio_reg(pi, RADIO_2064_REG12A, 0x08);
+
+                mod_phy_reg(pi, 0x938, (0x1 << 0), 1 << 0);
+                mod_phy_reg(pi, 0x939, (0x1 << 0), 0 << 0);
+                mod_phy_reg(pi, 0x938, (0x1 << 1), 1 << 1);
+                mod_phy_reg(pi, 0x939, (0x1 << 1), 1 << 1);
+                mod_phy_reg(pi, 0x938, (0x1 << 2), 1 << 2);
+                mod_phy_reg(pi, 0x939, (0x1 << 2), 1 << 2);
+                mod_phy_reg(pi, 0x938, (0x1 << 3), 1 << 3);
+                mod_phy_reg(pi, 0x939, (0x1 << 3), 1 << 3);
+                mod_phy_reg(pi, 0x938, (0x1 << 5), 1 << 5);
+                mod_phy_reg(pi, 0x939, (0x1 << 5), 0 << 5);
+
+                mod_phy_reg(pi, 0x43b, (0x1 << 0), 1 << 0);
+                mod_phy_reg(pi, 0x43c, (0x1 << 0), 0 << 0);
+
+                wlc_lcnphy_start_tx_tone(pi, 2000, 120, 0);
+                write_phy_reg(pi, 0x6da, 0xffff);
+                or_phy_reg(pi, 0x6db, 0x3);
+                wlc_lcnphy_set_trsw_override(pi, tx_switch, rx_switch);
+                wlc_lcnphy_rx_gain_override_enable(pi, true);
+
+                tia_gain = 8;
+                rx_pwr_threshold = 950;
+                while (tia_gain > 0) {
                         tia_gain -= 1;
+                        wlc_lcnphy_set_rx_gain_by_distribution(pi,
+                                                               0, 0, 2, 2,
+                                                               (u16)
+                                                               tia_gain, 1, 0);
+                        udelay(500);
+
+                        received_power =
+                                wlc_lcnphy_measure_digital_power(pi, 2000);
+                        if (received_power < rx_pwr_threshold)
+                                break;
                 }
-                lna2_gain -= 1;
-        }
+                result = wlc_lcnphy_calc_rx_iq_comp(pi, 0xffff);
 
-        if (set_gain)
-                result = wlc_lcnphy_calc_rx_iq_comp(pi, 1024);
-        else
-                result = false;
+                wlc_lcnphy_stop_tx_tone(pi);
 
-        wlc_lcnphy_stop_tx_tone(pi);
+                write_phy_reg(pi, 0x631, Core1TxControl_old);
 
-        write_phy_reg(pi, 0x631, Core1TxControl_old);
-
-        write_phy_reg(pi, 0x44c, RFOverrideVal0_old);
-        write_phy_reg(pi, 0x44d, RFOverrideVal0_old);
-        write_phy_reg(pi, 0x4b0, rfoverride2_old);
-        write_phy_reg(pi, 0x4b1, rfoverride2val_old);
-        write_phy_reg(pi, 0x4f9, rfoverride3_old);
-        write_phy_reg(pi, 0x4fa, rfoverride3val_old);
-        write_phy_reg(pi, 0x938, rfoverride4_old);
-        write_phy_reg(pi, 0x939, rfoverride4val_old);
-        write_phy_reg(pi, 0x43b, afectrlovr_old);
-        write_phy_reg(pi, 0x43c, afectrlovrval_old);
-        write_phy_reg(pi, 0x6da, old_sslpnCalibClkEnCtrl);
-        write_phy_reg(pi, 0x6db, old_sslpnRxFeClkEnCtrl);
+                write_phy_reg(pi, 0x44c, RFOverrideVal0_old);
+                write_phy_reg(pi, 0x44d, RFOverrideVal0_old);
+                write_phy_reg(pi, 0x4b0, rfoverride2_old);
+                write_phy_reg(pi, 0x4b1, rfoverride2val_old);
+                write_phy_reg(pi, 0x4f9, rfoverride3_old);
+                write_phy_reg(pi, 0x4fa, rfoverride3val_old);
+                write_phy_reg(pi, 0x938, rfoverride4_old);
+                write_phy_reg(pi, 0x939, rfoverride4val_old);
+                write_phy_reg(pi, 0x43b, afectrlovr_old);
+                write_phy_reg(pi, 0x43c, afectrlovrval_old);
+                write_phy_reg(pi, 0x6da, old_sslpnCalibClkEnCtrl);
+                write_phy_reg(pi, 0x6db, old_sslpnRxFeClkEnCtrl);
 
-        wlc_lcnphy_clear_trsw_override(pi);
+                wlc_lcnphy_clear_trsw_override(pi);
 
-        mod_phy_reg(pi, 0x44c, (0x1 << 2), 0 << 2);
+                mod_phy_reg(pi, 0x44c, (0x1 << 2), 0 << 2);
 
-        for (i = 0; i < 11; i++)
-                write_radio_reg(pi, rxiq_cal_rf_reg[i],
-                                values_to_save[i]);
+                for (i = 0; i < 11; i++)
+                        write_radio_reg(pi, rxiq_cal_rf_reg[i],
+                                        values_to_save[i]);
 
-        if (tx_gain_override_old)
-                wlc_lcnphy_set_tx_pwr_by_index(pi, tx_gain_index_old);
-        else
-                wlc_lcnphy_disable_tx_gain_override(pi);
+                if (tx_gain_override_old)
+                        wlc_lcnphy_set_tx_pwr_by_index(pi, tx_gain_index_old);
+                else
+                        wlc_lcnphy_disable_tx_gain_override(pi);
 
-        wlc_lcnphy_set_tx_pwr_ctrl(pi, tx_pwr_ctrl);
-        wlc_lcnphy_rx_gain_override_enable(pi, false);
+                wlc_lcnphy_set_tx_pwr_ctrl(pi, tx_pwr_ctrl);
+                wlc_lcnphy_rx_gain_override_enable(pi, false);
+        }
 
 cal_done:
         kfree(ptr);
@@ -1829,17 +1781,6 @@ wlc_lcnphy_radio_2064_channel_tune_4313(struct brcms_phy *pi, u8 channel)
                 write_radio_reg(pi, RADIO_2064_REG038, 3);
                 write_radio_reg(pi, RADIO_2064_REG091, 7);
         }
-
-        if (!(pi->sh->boardflags & BFL_FEM)) {
-                u8 reg038[14] = {0xd, 0xe, 0xd, 0xd, 0xd, 0xc,
-                        0xa, 0xb, 0xb, 0x3, 0x3, 0x2, 0x0, 0x0};
-
-                write_radio_reg(pi, RADIO_2064_REG02A, 0xf);
-                write_radio_reg(pi, RADIO_2064_REG091, 0x3);
-                write_radio_reg(pi, RADIO_2064_REG038, 0x3);
-
-                write_radio_reg(pi, RADIO_2064_REG038, reg038[channel - 1]);
-        }
 }
 
 static int
@@ -2034,16 +1975,6 @@ wlc_lcnphy_set_tssi_mux(struct brcms_phy *pi, enum lcnphy_tssi_mode pos)
                 } else {
                         mod_radio_reg(pi, RADIO_2064_REG03A, 1, 0x1);
                         mod_radio_reg(pi, RADIO_2064_REG11A, 0x8, 0x8);
-                        mod_radio_reg(pi, RADIO_2064_REG028, 0x1, 0x0);
-                        mod_radio_reg(pi, RADIO_2064_REG11A, 0x4, 1<<2);
-                        mod_radio_reg(pi, RADIO_2064_REG036, 0x10, 0x0);
-                        mod_radio_reg(pi, RADIO_2064_REG11A, 0x10, 1<<4);
-                        mod_radio_reg(pi, RADIO_2064_REG036, 0x3, 0x0);
-                        mod_radio_reg(pi, RADIO_2064_REG035, 0xff, 0x77);
-                        mod_radio_reg(pi, RADIO_2064_REG028, 0x1e, 0xe<<1);
-                        mod_radio_reg(pi, RADIO_2064_REG112, 0x80, 1<<7);
-                        mod_radio_reg(pi, RADIO_2064_REG005, 0x7, 1<<1);
-                        mod_radio_reg(pi, RADIO_2064_REG029, 0xf0, 0<<4);
                 }
         } else {
                 mod_phy_reg(pi, 0x4d9, (0x1 << 2), (0x1) << 2);
@@ -2130,14 +2061,12 @@ static void wlc_lcnphy_pwrctrl_rssiparams(struct brcms_phy *pi)
                     (auxpga_vmid_temp << 0) | (auxpga_gain_temp << 12));
 
         mod_radio_reg(pi, RADIO_2064_REG082, (1 << 5), (1 << 5));
-        mod_radio_reg(pi, RADIO_2064_REG07C, (1 << 0), (1 << 0));
 }
 
 static void wlc_lcnphy_tssi_setup(struct brcms_phy *pi)
 {
         struct phytbl_info tab;
         u32 rfseq, ind;
-        u8 tssi_sel;
 
         tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
         tab.tbl_width = 32;
@@ -2159,13 +2088,7 @@ static void wlc_lcnphy_tssi_setup(struct brcms_phy *pi)
 
         mod_phy_reg(pi, 0x503, (0x1 << 4), (1) << 4);
 
-        if (pi->sh->boardflags & BFL_FEM) {
-                tssi_sel = 0x1;
-                wlc_lcnphy_set_tssi_mux(pi, LCNPHY_TSSI_EXT);
-        } else {
-                tssi_sel = 0xe;
-                wlc_lcnphy_set_tssi_mux(pi, LCNPHY_TSSI_POST_PA);
-        }
+        wlc_lcnphy_set_tssi_mux(pi, LCNPHY_TSSI_EXT);
         mod_phy_reg(pi, 0x4a4, (0x1 << 14), (0) << 14);
 
         mod_phy_reg(pi, 0x4a4, (0x1 << 15), (1) << 15);
@@ -2201,10 +2124,9 @@ static void wlc_lcnphy_tssi_setup(struct brcms_phy *pi)
         mod_phy_reg(pi, 0x49a, (0x1ff << 0), (0xff) << 0);
 
         if (LCNREV_IS(pi->pubpi.phy_rev, 2)) {
-                mod_radio_reg(pi, RADIO_2064_REG028, 0xf, tssi_sel);
+                mod_radio_reg(pi, RADIO_2064_REG028, 0xf, 0xe);
                 mod_radio_reg(pi, RADIO_2064_REG086, 0x4, 0x4);
         } else {
-                mod_radio_reg(pi, RADIO_2064_REG028, 0x1e, tssi_sel << 1);
                 mod_radio_reg(pi, RADIO_2064_REG03A, 0x1, 1);
                 mod_radio_reg(pi, RADIO_2064_REG11A, 0x8, 1 << 3);
         }
@@ -2251,10 +2173,6 @@ static void wlc_lcnphy_tssi_setup(struct brcms_phy *pi)
 
         mod_phy_reg(pi, 0x4d7, (0xf << 8), (0) << 8);
 
-        mod_radio_reg(pi, RADIO_2064_REG035, 0xff, 0x0);
-        mod_radio_reg(pi, RADIO_2064_REG036, 0x3, 0x0);
-        mod_radio_reg(pi, RADIO_2064_REG11A, 0x8, 0x8);
-
         wlc_lcnphy_pwrctrl_rssiparams(pi);
 }
 
@@ -2873,8 +2791,6 @@ static void wlc_lcnphy_idle_tssi_est(struct brcms_phy_pub *ppi)
                 read_radio_reg(pi, RADIO_2064_REG007) & 1;
         u16 SAVE_jtag_auxpga = read_radio_reg(pi, RADIO_2064_REG0FF) & 0x10;
         u16 SAVE_iqadc_aux_en = read_radio_reg(pi, RADIO_2064_REG11F) & 4;
-        u8 SAVE_bbmult = wlc_lcnphy_get_bbmult(pi);
-
         idleTssi = read_phy_reg(pi, 0x4ab);
         suspend = (0 == (bcma_read32(pi->d11core, D11REGOFFS(maccontrol)) &
                          MCTL_EN_MAC));
@@ -2892,12 +2808,6 @@ static void wlc_lcnphy_idle_tssi_est(struct brcms_phy_pub *ppi)
         mod_radio_reg(pi, RADIO_2064_REG0FF, 0x10, 1 << 4);
         mod_radio_reg(pi, RADIO_2064_REG11F, 0x4, 1 << 2);
         wlc_lcnphy_tssi_setup(pi);
-
-        mod_phy_reg(pi, 0x4d7, (0x1 << 0), (1 << 0));
-        mod_phy_reg(pi, 0x4d7, (0x1 << 6), (1 << 6));
-
-        wlc_lcnphy_set_bbmult(pi, 0x0);
-
         wlc_phy_do_dummy_tx(pi, true, OFF);
         idleTssi = ((read_phy_reg(pi, 0x4ab) & (0x1ff << 0))
                     >> 0);
@@ -2919,7 +2829,6 @@ static void wlc_lcnphy_idle_tssi_est(struct brcms_phy_pub *ppi)
 
         mod_phy_reg(pi, 0x44c, (0x1 << 12), (0) << 12);
 
-        wlc_lcnphy_set_bbmult(pi, SAVE_bbmult);
         wlc_lcnphy_set_tx_gain_override(pi, tx_gain_override_old);
         wlc_lcnphy_set_tx_gain(pi, &old_gains);
         wlc_lcnphy_set_tx_pwr_ctrl(pi, SAVE_txpwrctrl);
@@ -3133,11 +3042,6 @@ static void wlc_lcnphy_tx_pwr_ctrl_init(struct brcms_phy_pub *ppi)
                         wlc_lcnphy_write_table(pi, &tab);
                         tab.tbl_offset++;
                 }
-                mod_phy_reg(pi, 0x4d0, (0x1 << 0), (0) << 0);
-                mod_phy_reg(pi, 0x4d3, (0xff << 0), (0) << 0);
-                mod_phy_reg(pi, 0x4d3, (0xff << 8), (0) << 8);
-                mod_phy_reg(pi, 0x4d0, (0x1 << 4), (0) << 4);
-                mod_phy_reg(pi, 0x4d0, (0x1 << 2), (0) << 2);
 
                 mod_phy_reg(pi, 0x410, (0x1 << 7), (0) << 7);
 
@@ -3939,6 +3843,7 @@ static void wlc_lcnphy_txpwrtbl_iqlo_cal(struct brcms_phy *pi)
         target_gains.pad_gain = 21;
         target_gains.dac_gain = 0;
         wlc_lcnphy_set_tx_gain(pi, &target_gains);
+        wlc_lcnphy_set_tx_pwr_by_index(pi, 16);
 
         if (LCNREV_IS(pi->pubpi.phy_rev, 1) || pi_lcn->lcnphy_hw_iqcal_en) {
 
@@ -3949,7 +3854,6 @@ static void wlc_lcnphy_txpwrtbl_iqlo_cal(struct brcms_phy *pi)
                                         lcnphy_recal ? LCNPHY_CAL_RECAL :
                                         LCNPHY_CAL_FULL), false);
         } else {
-                wlc_lcnphy_set_tx_pwr_by_index(pi, 16);
                 wlc_lcnphy_tx_iqlo_soft_cal_full(pi);
         }
 
@@ -4374,22 +4278,17 @@ wlc_lcnphy_load_tx_gain_table(struct brcms_phy *pi,
         if (CHSPEC_IS5G(pi->radio_chanspec))
                 pa_gain = 0x70;
         else
-                pa_gain = 0x60;
+                pa_gain = 0x70;
 
         if (pi->sh->boardflags & BFL_FEM)
                 pa_gain = 0x10;
-
         tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
         tab.tbl_width = 32;
         tab.tbl_len = 1;
         tab.tbl_ptr = &val;
 
         for (j = 0; j < 128; j++) {
-                if (pi->sh->boardflags & BFL_FEM)
-                        gm_gain = gain_table[j].gm;
-                else
-                        gm_gain = 15;
-
+                gm_gain = gain_table[j].gm;
                 val = (((u32) pa_gain << 24) |
                        (gain_table[j].pad << 16) |
                        (gain_table[j].pga << 8) | gm_gain);
@@ -4600,10 +4499,7 @@ static void wlc_radio_2064_init(struct brcms_phy *pi)
 
         write_phy_reg(pi, 0x4ea, 0x4688);
 
-        if (pi->sh->boardflags & BFL_FEM)
-                mod_phy_reg(pi, 0x4eb, (0x7 << 0), 2 << 0);
-        else
-                mod_phy_reg(pi, 0x4eb, (0x7 << 0), 3 << 0);
+        mod_phy_reg(pi, 0x4eb, (0x7 << 0), 2 << 0);
 
         mod_phy_reg(pi, 0x4eb, (0x7 << 6), 0 << 6);
 
@@ -4614,13 +4510,6 @@ static void wlc_radio_2064_init(struct brcms_phy *pi)
         wlc_lcnphy_rcal(pi);
 
         wlc_lcnphy_rc_cal(pi);
-
-        if (!(pi->sh->boardflags & BFL_FEM)) {
-                write_radio_reg(pi, RADIO_2064_REG032, 0x6f);
-                write_radio_reg(pi, RADIO_2064_REG033, 0x19);
-                write_radio_reg(pi, RADIO_2064_REG039, 0xe);
-        }
-
 }
 
 static void wlc_lcnphy_radio_init(struct brcms_phy *pi)
@@ -4650,20 +4539,22 @@ static void wlc_lcnphy_tbl_init(struct brcms_phy *pi)
                 wlc_lcnphy_write_table(pi, &tab);
         }
 
-        if (!(pi->sh->boardflags & BFL_FEM)) {
-                tab.tbl_id = LCNPHY_TBL_ID_RFSEQ;
-                tab.tbl_width = 16;
-                tab.tbl_ptr = &val;
-                tab.tbl_len = 1;
+        tab.tbl_id = LCNPHY_TBL_ID_RFSEQ;
+        tab.tbl_width = 16;
+        tab.tbl_ptr = &val;
+        tab.tbl_len = 1;
 
-                val = 150;
-                tab.tbl_offset = 0;
-                wlc_lcnphy_write_table(pi, &tab);
+        val = 114;
+        tab.tbl_offset = 0;
+        wlc_lcnphy_write_table(pi, &tab);
 
-                val = 220;
-                tab.tbl_offset = 1;
-                wlc_lcnphy_write_table(pi, &tab);
-        }
+        val = 130;
+        tab.tbl_offset = 1;
+        wlc_lcnphy_write_table(pi, &tab);
+
+        val = 6;
+        tab.tbl_offset = 8;
+        wlc_lcnphy_write_table(pi, &tab);
 
         if (CHSPEC_IS2G(pi->radio_chanspec)) {
                 if (pi->sh->boardflags & BFL_FEM)
@@ -5055,7 +4946,6 @@ void wlc_phy_chanspec_set_lcnphy(struct brcms_phy *pi, u16 chanspec)
                 wlc_lcnphy_load_tx_iir_filter(pi, true, 3);
 
         mod_phy_reg(pi, 0x4eb, (0x7 << 3), (1) << 3);
-        wlc_lcnphy_tssi_setup(pi);
 }
 
 void wlc_phy_detach_lcnphy(struct brcms_phy *pi)
@@ -5094,7 +4984,8 @@ bool wlc_phy_attach_lcnphy(struct brcms_phy *pi)
         if (!wlc_phy_txpwr_srom_read_lcnphy(pi))
                 return false;
 
-        if (LCNREV_IS(pi->pubpi.phy_rev, 1)) {
+        if ((pi->sh->boardflags & BFL_FEM) &&
+            (LCNREV_IS(pi->pubpi.phy_rev, 1))) {
                 if (pi_lcn->lcnphy_tempsense_option == 3) {
                         pi->hwpwrctrl = true;
                         pi->hwpwrctrl_capable = true;
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/phy/phytbl_lcn.c b/drivers/net/wireless/brcm80211/brcmsmac/phy/phytbl_lcn.c
index b7e95acc2084..622c01ca72c5 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/phy/phytbl_lcn.c
+++ b/drivers/net/wireless/brcm80211/brcmsmac/phy/phytbl_lcn.c
@@ -1992,70 +1992,70 @@ static const u16 dot11lcn_sw_ctrl_tbl_4313_epa_rev0[] = {
 };
 
 static const u16 dot11lcn_sw_ctrl_tbl_4313_rev0[] = {
-        0x0009,
         0x000a,
-        0x0005,
-        0x0006,
         0x0009,
-        0x000a,
-        0x0005,
         0x0006,
-        0x0009,
-        0x000a,
         0x0005,
-        0x0006,
-        0x0009,
         0x000a,
-        0x0005,
-        0x0006,
         0x0009,
-        0x000a,
-        0x0005,
         0x0006,
-        0x0009,
-        0x000a,
         0x0005,
-        0x0006,
-        0x0009,
         0x000a,
-        0x0005,
-        0x0006,
         0x0009,
-        0x000a,
-        0x0005,
         0x0006,
-        0x0009,
-        0x000a,
         0x0005,
-        0x0006,
-        0x0009,
         0x000a,
-        0x0005,
-        0x0006,
         0x0009,
-        0x000a,
-        0x0005,
         0x0006,
-        0x0009,
-        0x000a,
         0x0005,
-        0x0006,
+        0x000a,
         0x0009,
+        0x0006,
+        0x0005,
         0x000a,
+        0x0009,
+        0x0006,
         0x0005,
+        0x000a,
+        0x0009,
         0x0006,
+        0x0005,
+        0x000a,
         0x0009,
+        0x0006,
+        0x0005,
         0x000a,
+        0x0009,
+        0x0006,
         0x0005,
+        0x000a,
+        0x0009,
         0x0006,
+        0x0005,
+        0x000a,
         0x0009,
+        0x0006,
+        0x0005,
         0x000a,
+        0x0009,
+        0x0006,
         0x0005,
+        0x000a,
+        0x0009,
         0x0006,
+        0x0005,
+        0x000a,
         0x0009,
+        0x0006,
+        0x0005,
         0x000a,
+        0x0009,
+        0x0006,
         0x0005,
+        0x000a,
+        0x0009,
         0x0006,
+        0x0005,
 };
 
 static const u16 dot11lcn_sw_ctrl_tbl_rev0[] = {
diff --git a/drivers/net/wireless/iwlegacy/4965-rs.c b/drivers/net/wireless/iwlegacy/4965-rs.c
index e8324b5e5bfe..6c7493c2d698 100644
--- a/drivers/net/wireless/iwlegacy/4965-rs.c
+++ b/drivers/net/wireless/iwlegacy/4965-rs.c
@@ -2152,7 +2152,7 @@ il4965_rs_initialize_lq(struct il_priv *il, struct ieee80211_conf *conf,
         int rate_idx;
         int i;
         u32 rate;
-        u8 use_green = il4965_rs_use_green(il, sta);
+        u8 use_green;
         u8 active_tbl = 0;
         u8 valid_tx_ant;
         struct il_station_priv *sta_priv;
@@ -2160,6 +2160,7 @@ il4965_rs_initialize_lq(struct il_priv *il, struct ieee80211_conf *conf,
         if (!sta || !lq_sta)
                 return;
 
+        use_green = il4965_rs_use_green(il, sta);
         sta_priv = (void *)sta->drv_priv;
 
         i = lq_sta->last_txrate_idx;
diff --git a/drivers/net/wireless/iwlwifi/dvm/lib.c b/drivers/net/wireless/iwlwifi/dvm/lib.c
index 86ea5f4c3939..44ca0e57f9f7 100644
--- a/drivers/net/wireless/iwlwifi/dvm/lib.c
+++ b/drivers/net/wireless/iwlwifi/dvm/lib.c
@@ -1262,6 +1262,15 @@ int iwl_dvm_send_cmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
         }
 
         /*
+         * This can happen upon FW ASSERT: we clear the STATUS_FW_ERROR flag
+         * in iwl_down but cancel the workers only later.
+         */
+        if (!priv->ucode_loaded) {
+                IWL_ERR(priv, "Fw not loaded - dropping CMD: %x\n", cmd->id);
+                return -EIO;
+        }
+
+        /*
          * Synchronous commands from this op-mode must hold
          * the mutex, this ensures we don't try to send two
          * (or more) synchronous commands at a time.
diff --git a/drivers/net/wireless/iwlwifi/dvm/rxon.c b/drivers/net/wireless/iwlwifi/dvm/rxon.c
index 23be948cf162..a82b6b39d4ff 100644
--- a/drivers/net/wireless/iwlwifi/dvm/rxon.c
+++ b/drivers/net/wireless/iwlwifi/dvm/rxon.c
@@ -1419,6 +1419,14 @@ void iwlagn_bss_info_changed(struct ieee80211_hw *hw,
 
         mutex_lock(&priv->mutex);
 
+        if (changes & BSS_CHANGED_IDLE && bss_conf->idle) {
+                /*
+                 * If we go idle, then clearly no "passive-no-rx"
+                 * workaround is needed any more, this is a reset.
+                 */
+                iwlagn_lift_passive_no_rx(priv);
+        }
+
         if (unlikely(!iwl_is_ready(priv))) {
                 IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
                 mutex_unlock(&priv->mutex);
@@ -1450,16 +1458,6 @@ void iwlagn_bss_info_changed(struct ieee80211_hw *hw,
                         priv->timestamp = bss_conf->sync_tsf;
                         ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
                 } else {
-                        /*
-                         * If we disassociate while there are pending
-                         * frames, just wake up the queues and let the
-                         * frames "escape" ... This shouldn't really
-                         * be happening to start with, but we should
-                         * not get stuck in this case either since it
-                         * can happen if userspace gets confused.
-                         */
-                        iwlagn_lift_passive_no_rx(priv);
-
                         ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
 
                         if (ctx->ctxid == IWL_RXON_CTX_BSS)
diff --git a/drivers/net/wireless/iwlwifi/dvm/tx.c b/drivers/net/wireless/iwlwifi/dvm/tx.c
index 6aec2df3bb27..d1a670d7b10c 100644
--- a/drivers/net/wireless/iwlwifi/dvm/tx.c
+++ b/drivers/net/wireless/iwlwifi/dvm/tx.c
@@ -1192,7 +1192,7 @@ int iwlagn_rx_reply_tx(struct iwl_priv *priv, struct iwl_rx_cmd_buffer *rxb,
                         memset(&info->status, 0, sizeof(info->status));
 
                         if (status == TX_STATUS_FAIL_PASSIVE_NO_RX &&
-                            iwl_is_associated_ctx(ctx) && ctx->vif &&
+                            ctx->vif &&
                             ctx->vif->type == NL80211_IFTYPE_STATION) {
                                 /* block and stop all queues */
                                 priv->passive_no_rx = true;
diff --git a/drivers/net/wireless/iwlwifi/dvm/ucode.c b/drivers/net/wireless/iwlwifi/dvm/ucode.c
index 736fe9bb140e..1a4ac9236a44 100644
--- a/drivers/net/wireless/iwlwifi/dvm/ucode.c
+++ b/drivers/net/wireless/iwlwifi/dvm/ucode.c
@@ -367,6 +367,8 @@ int iwl_load_ucode_wait_alive(struct iwl_priv *priv,
                 return -EIO;
         }
 
+        priv->ucode_loaded = true;
+
         if (ucode_type != IWL_UCODE_WOWLAN) {
                 /* delay a bit to give rfkill time to run */
                 msleep(5);
@@ -380,8 +382,6 @@ int iwl_load_ucode_wait_alive(struct iwl_priv *priv,
                 return ret;
         }
 
-        priv->ucode_loaded = true;
-
         return 0;
 }
 
diff --git a/drivers/net/wireless/iwlwifi/pcie/trans.c b/drivers/net/wireless/iwlwifi/pcie/trans.c
index 17bedc50e753..12c4f31ca8fb 100644
--- a/drivers/net/wireless/iwlwifi/pcie/trans.c
+++ b/drivers/net/wireless/iwlwifi/pcie/trans.c
@@ -475,6 +475,10 @@ static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
 
         /* If platform's RF_KILL switch is NOT set to KILL */
         hw_rfkill = iwl_is_rfkill_set(trans);
+        if (hw_rfkill)
+                set_bit(STATUS_RFKILL, &trans_pcie->status);
+        else
+                clear_bit(STATUS_RFKILL, &trans_pcie->status);
         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
         if (hw_rfkill && !run_in_rfkill)
                 return -ERFKILL;
@@ -641,6 +645,7 @@ static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
 
 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
 {
+        struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
         bool hw_rfkill;
         int err;
 
@@ -656,6 +661,10 @@ static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
         iwl_enable_rfkill_int(trans);
 
         hw_rfkill = iwl_is_rfkill_set(trans);
+        if (hw_rfkill)
+                set_bit(STATUS_RFKILL, &trans_pcie->status);
+        else
+                clear_bit(STATUS_RFKILL, &trans_pcie->status);
         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
 
         return 0;
@@ -694,6 +703,10 @@ static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans,
                  * op_mode.
                  */
                 hw_rfkill = iwl_is_rfkill_set(trans);
+                if (hw_rfkill)
+                        set_bit(STATUS_RFKILL, &trans_pcie->status);
+                else
+                        clear_bit(STATUS_RFKILL, &trans_pcie->status);
                 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
         }
 }
diff --git a/drivers/net/wireless/iwlwifi/pcie/tx.c b/drivers/net/wireless/iwlwifi/pcie/tx.c
index 8595c16f74de..cb5c6792e3a8 100644
--- a/drivers/net/wireless/iwlwifi/pcie/tx.c
+++ b/drivers/net/wireless/iwlwifi/pcie/tx.c
@@ -1264,7 +1264,7 @@ static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
         for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
                 int copy = 0;
 
-                if (!cmd->len)
+                if (!cmd->len[i])
                         continue;
 
                 /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */
diff --git a/drivers/net/wireless/mwifiex/cfg80211.c b/drivers/net/wireless/mwifiex/cfg80211.c
index a44023a7bd57..8aaf56ade4d9 100644
--- a/drivers/net/wireless/mwifiex/cfg80211.c
+++ b/drivers/net/wireless/mwifiex/cfg80211.c
@@ -1892,7 +1892,8 @@ mwifiex_cfg80211_scan(struct wiphy *wiphy,
                 }
         }
 
-        for (i = 0; i < request->n_channels; i++) {
+        for (i = 0; i < min_t(u32, request->n_channels,
+                              MWIFIEX_USER_SCAN_CHAN_MAX); i++) {
                 chan = request->channels[i];
                 priv->user_scan_cfg->chan_list[i].chan_number = chan->hw_value;
                 priv->user_scan_cfg->chan_list[i].radio_type = chan->band;
diff --git a/drivers/net/wireless/mwifiex/pcie.c b/drivers/net/wireless/mwifiex/pcie.c
index 5c395e2e6a2b..feb204613397 100644
--- a/drivers/net/wireless/mwifiex/pcie.c
+++ b/drivers/net/wireless/mwifiex/pcie.c
@@ -1508,6 +1508,7 @@ static int mwifiex_pcie_process_cmd_complete(struct mwifiex_adapter *adapter)
                 }
                 memcpy(adapter->upld_buf, skb->data,
                        min_t(u32, MWIFIEX_SIZE_OF_CMD_BUFFER, skb->len));
+                skb_push(skb, INTF_HEADER_LEN);
                 if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE,
                                            PCI_DMA_FROMDEVICE))
                         return -1;
diff --git a/drivers/nfc/microread/mei.c b/drivers/nfc/microread/mei.c
index eef38cfd812e..ca33ae193935 100644
--- a/drivers/nfc/microread/mei.c
+++ b/drivers/nfc/microread/mei.c
@@ -22,7 +22,7 @@
 #include <linux/slab.h>
 #include <linux/interrupt.h>
 #include <linux/gpio.h>
-#include <linux/mei_bus.h>
+#include <linux/mei_cl_bus.h>
 
 #include <linux/nfc.h>
 #include <net/nfc/hci.h>
@@ -32,9 +32,6 @@
 
 #define MICROREAD_DRIVER_NAME "microread"
 
-#define MICROREAD_UUID UUID_LE(0x0bb17a78, 0x2a8e, 0x4c50, 0x94, \
-                               0xd4, 0x50, 0x26, 0x67, 0x23, 0x77, 0x5c)
-
 struct mei_nfc_hdr {
         u8 cmd;
         u8 status;
@@ -48,7 +45,7 @@ struct mei_nfc_hdr {
 #define MEI_NFC_MAX_READ (MEI_NFC_HEADER_SIZE + MEI_NFC_MAX_HCI_PAYLOAD)
 
 struct microread_mei_phy {
-        struct mei_device *mei_device;
+        struct mei_cl_device *device;
         struct nfc_hci_dev *hdev;
 
         int powered;
@@ -105,14 +102,14 @@ static int microread_mei_write(void *phy_id, struct sk_buff *skb)
 
         MEI_DUMP_SKB_OUT("mei frame sent", skb);
 
-        r = mei_send(phy->device, skb->data, skb->len);
+        r = mei_cl_send(phy->device, skb->data, skb->len);
         if (r > 0)
                 r = 0;
 
         return r;
 }
 
-static void microread_event_cb(struct mei_device *device, u32 events,
+static void microread_event_cb(struct mei_cl_device *device, u32 events,
                                void *context)
 {
         struct microread_mei_phy *phy = context;
@@ -120,7 +117,7 @@ static void microread_event_cb(struct mei_device *device, u32 events,
         if (phy->hard_fault != 0)
                 return;
 
-        if (events & BIT(MEI_EVENT_RX)) {
+        if (events & BIT(MEI_CL_EVENT_RX)) {
                 struct sk_buff *skb;
                 int reply_size;
 
@@ -128,7 +125,7 @@ static void microread_event_cb(struct mei_device *device, u32 events,
                 if (!skb)
                         return;
 
-                reply_size = mei_recv(device, skb->data, MEI_NFC_MAX_READ);
+                reply_size = mei_cl_recv(device, skb->data, MEI_NFC_MAX_READ);
                 if (reply_size < MEI_NFC_HEADER_SIZE) {
                         kfree(skb);
                         return;
@@ -149,8 +146,8 @@ static struct nfc_phy_ops mei_phy_ops = {
         .disable = microread_mei_disable,
 };
 
-static int microread_mei_probe(struct mei_device *device,
-                               const struct mei_id *id)
+static int microread_mei_probe(struct mei_cl_device *device,
+                               const struct mei_cl_device_id *id)
 {
         struct microread_mei_phy *phy;
         int r;
@@ -164,9 +161,9 @@ static int microread_mei_probe(struct mei_device *device,
         }
 
         phy->device = device;
-        mei_set_clientdata(device, phy);
+        mei_cl_set_drvdata(device, phy);
 
-        r = mei_register_event_cb(device, microread_event_cb, phy);
+        r = mei_cl_register_event_cb(device, microread_event_cb, phy);
         if (r) {
                 pr_err(MICROREAD_DRIVER_NAME ": event cb registration failed\n");
                 goto err_out;
@@ -186,9 +183,9 @@ err_out:
         return r;
 }
 
-static int microread_mei_remove(struct mei_device *device)
+static int microread_mei_remove(struct mei_cl_device *device)
 {
-        struct microread_mei_phy *phy = mei_get_clientdata(device);
+        struct microread_mei_phy *phy = mei_cl_get_drvdata(device);
 
         pr_info("Removing microread\n");
 
@@ -202,16 +199,15 @@ static int microread_mei_remove(struct mei_device *device)
         return 0;
 }
 
-static struct mei_id microread_mei_tbl[] = {
-        { MICROREAD_DRIVER_NAME, MICROREAD_UUID },
+static struct mei_cl_device_id microread_mei_tbl[] = {
+        { MICROREAD_DRIVER_NAME },
 
         /* required last entry */
         { }
 };
-
 MODULE_DEVICE_TABLE(mei, microread_mei_tbl);
 
-static struct mei_driver microread_driver = {
+static struct mei_cl_driver microread_driver = {
         .id_table = microread_mei_tbl,
         .name = MICROREAD_DRIVER_NAME,
 
@@ -225,7 +221,7 @@ static int microread_mei_init(void)
 
         pr_debug(DRIVER_DESC ": %s\n", __func__);
 
-        r = mei_driver_register(&microread_driver);
+        r = mei_cl_driver_register(&microread_driver);
         if (r) {
                 pr_err(MICROREAD_DRIVER_NAME ": driver registration failed\n");
                 return r;
@@ -236,7 +232,7 @@ static int microread_mei_init(void)
 
 static void microread_mei_exit(void)
 {
-        mei_driver_unregister(&microread_driver);
+        mei_cl_driver_unregister(&microread_driver);
 }
 
 module_init(microread_mei_init);
diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c
index dee5dddaa292..5147c210df52 100644
--- a/drivers/pci/pci-acpi.c
+++ b/drivers/pci/pci-acpi.c
@@ -53,14 +53,15 @@ static void pci_acpi_wake_dev(acpi_handle handle, u32 event, void *context)
                 return;
         }
 
-        if (!pci_dev->pm_cap || !pci_dev->pme_support
-             || pci_check_pme_status(pci_dev)) {
-                if (pci_dev->pme_poll)
-                        pci_dev->pme_poll = false;
+        /* Clear PME Status if set. */
+        if (pci_dev->pme_support)
+                pci_check_pme_status(pci_dev);
 
-                pci_wakeup_event(pci_dev);
-                pm_runtime_resume(&pci_dev->dev);
-        }
+        if (pci_dev->pme_poll)
+                pci_dev->pme_poll = false;
+
+        pci_wakeup_event(pci_dev);
+        pm_runtime_resume(&pci_dev->dev);
 
         if (pci_dev->subordinate)
                 pci_pme_wakeup_bus(pci_dev->subordinate);
diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c
index 1fa1e482a999..79277fb36c6b 100644
--- a/drivers/pci/pci-driver.c
+++ b/drivers/pci/pci-driver.c
@@ -390,9 +390,10 @@ static void pci_device_shutdown(struct device *dev)
 
         /*
          * Turn off Bus Master bit on the device to tell it to not
-         * continue to do DMA
+         * continue to do DMA. Don't touch devices in D3cold or unknown states.
          */
-        pci_clear_master(pci_dev);
+        if (pci_dev->current_state <= PCI_D3hot)
+                pci_clear_master(pci_dev);
 }
 
 #ifdef CONFIG_PM
diff --git a/drivers/pci/pcie/portdrv_pci.c b/drivers/pci/pcie/portdrv_pci.c
index 08c243ab034e..ed4d09498337 100644
--- a/drivers/pci/pcie/portdrv_pci.c
+++ b/drivers/pci/pcie/portdrv_pci.c
@@ -185,14 +185,6 @@ static const struct dev_pm_ops pcie_portdrv_pm_ops = {
 #endif /* !PM */
 
 /*
- * PCIe port runtime suspend is broken for some chipsets, so use a
- * black list to disable runtime PM for these chipsets.
- */
-static const struct pci_device_id port_runtime_pm_black_list[] = {
-        { /* end: all zeroes */ }
-};
-
-/*
  * pcie_portdrv_probe - Probe PCI-Express port devices
  * @dev: PCI-Express port device being probed
  *
@@ -225,16 +217,11 @@ static int pcie_portdrv_probe(struct pci_dev *dev,
          * it by default.
          */
         dev->d3cold_allowed = false;
-        if (!pci_match_id(port_runtime_pm_black_list, dev))
-                pm_runtime_put_noidle(&dev->dev);
-
         return 0;
 }
 
 static void pcie_portdrv_remove(struct pci_dev *dev)
 {
-        if (!pci_match_id(port_runtime_pm_black_list, dev))
-                pm_runtime_get_noresume(&dev->dev);
         pcie_port_device_remove(dev);
         pci_disable_device(dev);
 }
diff --git a/drivers/pci/rom.c b/drivers/pci/rom.c
index b41ac7756a4b..c5d0a08a8747 100644
--- a/drivers/pci/rom.c
+++ b/drivers/pci/rom.c
@@ -100,27 +100,6 @@ size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size)
         return min((size_t)(image - rom), size);
 }
 
-static loff_t pci_find_rom(struct pci_dev *pdev, size_t *size)
-{
-        struct resource *res = &pdev->resource[PCI_ROM_RESOURCE];
-        loff_t start;
-
-        /* assign the ROM an address if it doesn't have one */
-        if (res->parent == NULL && pci_assign_resource(pdev, PCI_ROM_RESOURCE))
-                return 0;
-        start = pci_resource_start(pdev, PCI_ROM_RESOURCE);
-        *size = pci_resource_len(pdev, PCI_ROM_RESOURCE);
-
-        if (*size == 0)
-                return 0;
-
-        /* Enable ROM space decodes */
-        if (pci_enable_rom(pdev))
-                return 0;
-
-        return start;
-}
-
 /**
  * pci_map_rom - map a PCI ROM to kernel space
  * @pdev: pointer to pci device struct
@@ -135,7 +114,7 @@ static loff_t pci_find_rom(struct pci_dev *pdev, size_t *size)
 void __iomem *pci_map_rom(struct pci_dev *pdev, size_t *size)
 {
         struct resource *res = &pdev->resource[PCI_ROM_RESOURCE];
-        loff_t start = 0;
+        loff_t start;
         void __iomem *rom;
 
         /*
@@ -154,21 +133,21 @@ void __iomem *pci_map_rom(struct pci_dev *pdev, size_t *size)
                         return (void __iomem *)(unsigned long)
                                 pci_resource_start(pdev, PCI_ROM_RESOURCE);
                 } else {
-                        start = pci_find_rom(pdev, size);
-                }
-        }
+                        /* assign the ROM an address if it doesn't have one */
+                        if (res->parent == NULL &&
+                            pci_assign_resource(pdev,PCI_ROM_RESOURCE))
+                                return NULL;
+                        start = pci_resource_start(pdev, PCI_ROM_RESOURCE);
+                        *size = pci_resource_len(pdev, PCI_ROM_RESOURCE);
+                        if (*size == 0)
+                                return NULL;
 
-        /*
-         * Some devices may provide ROMs via a source other than the BAR
-         */
-        if (!start && pdev->rom && pdev->romlen) {
-                *size = pdev->romlen;
-                return phys_to_virt(pdev->rom);
+                        /* Enable ROM space decodes */
+                        if (pci_enable_rom(pdev))
+                                return NULL;
+                }
         }
 
-        if (!start)
-                return NULL;
-
         rom = ioremap(start, *size);
         if (!rom) {
                 /* restore enable if ioremap fails */
@@ -202,8 +181,7 @@ void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom)
         if (res->flags & (IORESOURCE_ROM_COPY | IORESOURCE_ROM_BIOS_COPY))
                 return;
 
-        if (!pdev->rom || !pdev->romlen)
-                iounmap(rom);
+        iounmap(rom);
 
         /* Disable again before continuing, leave enabled if pci=rom */
         if (!(res->flags & (IORESOURCE_ROM_ENABLE | IORESOURCE_ROM_SHADOW)))
@@ -227,7 +205,24 @@ void pci_cleanup_rom(struct pci_dev *pdev)
         }
 }
 
+/**
+ * pci_platform_rom - provides a pointer to any ROM image provided by the
+ * platform
+ * @pdev: pointer to pci device struct
+ * @size: pointer to receive size of pci window over ROM
+ */
+void __iomem *pci_platform_rom(struct pci_dev *pdev, size_t *size)
+{
+        if (pdev->rom && pdev->romlen) {
+                *size = pdev->romlen;
+                return phys_to_virt((phys_addr_t)pdev->rom);
+        }
+
+        return NULL;
+}
+
 EXPORT_SYMBOL(pci_map_rom);
 EXPORT_SYMBOL(pci_unmap_rom);
 EXPORT_SYMBOL_GPL(pci_enable_rom);
 EXPORT_SYMBOL_GPL(pci_disable_rom);
+EXPORT_SYMBOL(pci_platform_rom);
diff --git a/drivers/rtc/rtc-at91rm9200.c b/drivers/rtc/rtc-at91rm9200.c
index 0a9f27e094ea..434ebc3a99dc 100644
--- a/drivers/rtc/rtc-at91rm9200.c
+++ b/drivers/rtc/rtc-at91rm9200.c
@@ -44,7 +44,6 @@ static DECLARE_COMPLETION(at91_rtc_updated);
 static unsigned int at91_alarm_year = AT91_RTC_EPOCH;
 static void __iomem *at91_rtc_regs;
 static int irq;
-static u32 at91_rtc_imr;
 
 /*
  * Decode time/date into rtc_time structure
@@ -109,11 +108,9 @@ static int at91_rtc_settime(struct device *dev, struct rtc_time *tm)
         cr = at91_rtc_read(AT91_RTC_CR);
         at91_rtc_write(AT91_RTC_CR, cr | AT91_RTC_UPDCAL | AT91_RTC_UPDTIM);
 
-        at91_rtc_imr |= AT91_RTC_ACKUPD;
         at91_rtc_write(AT91_RTC_IER, AT91_RTC_ACKUPD);
         wait_for_completion(&at91_rtc_updated); /* wait for ACKUPD interrupt */
         at91_rtc_write(AT91_RTC_IDR, AT91_RTC_ACKUPD);
-        at91_rtc_imr &= ~AT91_RTC_ACKUPD;
 
         at91_rtc_write(AT91_RTC_TIMR,
                           bin2bcd(tm->tm_sec) << 0
@@ -145,7 +142,7 @@ static int at91_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
         tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year);
         tm->tm_year = at91_alarm_year - 1900;
 
-        alrm->enabled = (at91_rtc_imr & AT91_RTC_ALARM)
+        alrm->enabled = (at91_rtc_read(AT91_RTC_IMR) & AT91_RTC_ALARM)
                         ? 1 : 0;
 
         dev_dbg(dev, "%s(): %4d-%02d-%02d %02d:%02d:%02d\n", __func__,
@@ -171,7 +168,6 @@ static int at91_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
         tm.tm_sec = alrm->time.tm_sec;
 
         at91_rtc_write(AT91_RTC_IDR, AT91_RTC_ALARM);
-        at91_rtc_imr &= ~AT91_RTC_ALARM;
         at91_rtc_write(AT91_RTC_TIMALR,
                   bin2bcd(tm.tm_sec) << 0
                 | bin2bcd(tm.tm_min) << 8
@@ -184,7 +180,6 @@ static int at91_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
 
         if (alrm->enabled) {
                 at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_ALARM);
-                at91_rtc_imr |= AT91_RTC_ALARM;
                 at91_rtc_write(AT91_RTC_IER, AT91_RTC_ALARM);
         }
 
@@ -201,12 +196,9 @@ static int at91_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
 
         if (enabled) {
                 at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_ALARM);
-                at91_rtc_imr |= AT91_RTC_ALARM;
                 at91_rtc_write(AT91_RTC_IER, AT91_RTC_ALARM);
-        } else {
+        } else
                 at91_rtc_write(AT91_RTC_IDR, AT91_RTC_ALARM);
-                at91_rtc_imr &= ~AT91_RTC_ALARM;
-        }
 
         return 0;
 }
@@ -215,10 +207,12 @@ static int at91_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
  */
 static int at91_rtc_proc(struct device *dev, struct seq_file *seq)
 {
+        unsigned long imr = at91_rtc_read(AT91_RTC_IMR);
+
         seq_printf(seq, "update_IRQ\t: %s\n",
-                        (at91_rtc_imr & AT91_RTC_ACKUPD) ? "yes" : "no");
+                        (imr & AT91_RTC_ACKUPD) ? "yes" : "no");
         seq_printf(seq, "periodic_IRQ\t: %s\n",
-                        (at91_rtc_imr & AT91_RTC_SECEV) ? "yes" : "no");
+                        (imr & AT91_RTC_SECEV) ? "yes" : "no");
 
         return 0;
 }
@@ -233,7 +227,7 @@ static irqreturn_t at91_rtc_interrupt(int irq, void *dev_id)
         unsigned int rtsr;
         unsigned long events = 0;
 
-        rtsr = at91_rtc_read(AT91_RTC_SR) & at91_rtc_imr;
+        rtsr = at91_rtc_read(AT91_RTC_SR) & at91_rtc_read(AT91_RTC_IMR);
         if (rtsr) {             /* this interrupt is shared!  Is it ours? */
                 if (rtsr & AT91_RTC_ALARM)
                         events |= (RTC_AF | RTC_IRQF);
@@ -297,7 +291,6 @@ static int __init at91_rtc_probe(struct platform_device *pdev)
         at91_rtc_write(AT91_RTC_IDR, AT91_RTC_ACKUPD | AT91_RTC_ALARM |
                                         AT91_RTC_SECEV | AT91_RTC_TIMEV |
                                         AT91_RTC_CALEV);
-        at91_rtc_imr = 0;
 
         ret = request_irq(irq, at91_rtc_interrupt,
                                 IRQF_SHARED,
@@ -336,7 +329,6 @@ static int __exit at91_rtc_remove(struct platform_device *pdev)
         at91_rtc_write(AT91_RTC_IDR, AT91_RTC_ACKUPD | AT91_RTC_ALARM |
                                         AT91_RTC_SECEV | AT91_RTC_TIMEV |
                                         AT91_RTC_CALEV);
-        at91_rtc_imr = 0;
         free_irq(irq, pdev);
 
         rtc_device_unregister(rtc);
@@ -349,35 +341,31 @@ static int __exit at91_rtc_remove(struct platform_device *pdev)
 
 /* AT91RM9200 RTC Power management control */
 
-static u32 at91_rtc_bkpimr;
-
+static u32 at91_rtc_imr;
 
 static int at91_rtc_suspend(struct device *dev)
 {
         /* this IRQ is shared with DBGU and other hardware which isn't
          * necessarily doing PM like we are...
          */
-        at91_rtc_bkpimr = at91_rtc_imr & (AT91_RTC_ALARM|AT91_RTC_SECEV);
-        if (at91_rtc_bkpimr) {
-                if (device_may_wakeup(dev)) {
+        at91_rtc_imr = at91_rtc_read(AT91_RTC_IMR)
+                        & (AT91_RTC_ALARM|AT91_RTC_SECEV);
+        if (at91_rtc_imr) {
+                if (device_may_wakeup(dev))
                         enable_irq_wake(irq);
-                } else {
-                        at91_rtc_write(AT91_RTC_IDR, at91_rtc_bkpimr);
-                        at91_rtc_imr &= ~at91_rtc_bkpimr;
-                }
-}
+                else
+                        at91_rtc_write(AT91_RTC_IDR, at91_rtc_imr);
+        }
         return 0;
 }
 
 static int at91_rtc_resume(struct device *dev)
 {
-        if (at91_rtc_bkpimr) {
-                if (device_may_wakeup(dev)) {
+        if (at91_rtc_imr) {
+                if (device_may_wakeup(dev))
                         disable_irq_wake(irq);
-                } else {
-                        at91_rtc_imr |= at91_rtc_bkpimr;
-                        at91_rtc_write(AT91_RTC_IER, at91_rtc_bkpimr);
-                }
+                else
+                        at91_rtc_write(AT91_RTC_IER, at91_rtc_imr);
         }
         return 0;
 }
diff --git a/drivers/rtc/rtc-at91rm9200.h b/drivers/rtc/rtc-at91rm9200.h
index 5f940b6844cb..da1945e5f714 100644
--- a/drivers/rtc/rtc-at91rm9200.h
+++ b/drivers/rtc/rtc-at91rm9200.h
@@ -64,6 +64,7 @@
 #define AT91_RTC_SCCR           0x1c                    /* Status Clear Command Register */
 #define AT91_RTC_IER            0x20                    /* Interrupt Enable Register */
 #define AT91_RTC_IDR            0x24                    /* Interrupt Disable Register */
+#define AT91_RTC_IMR            0x28                    /* Interrupt Mask Register */
 
 #define AT91_RTC_VER            0x2c                    /* Valid Entry Register */
 #define         AT91_RTC_NVTIM          (1 <<  0)               /* Non valid Time */
diff --git a/drivers/s390/block/scm_blk.c b/drivers/s390/block/scm_blk.c
index 5ac9c935c151..e9b9c8392832 100644
--- a/drivers/s390/block/scm_blk.c
+++ b/drivers/s390/block/scm_blk.c
@@ -307,7 +307,7 @@ static void scm_blk_handle_error(struct scm_request *scmrq)
         case EQC_WR_PROHIBIT:
                 spin_lock_irqsave(&bdev->lock, flags);
                 if (bdev->state != SCM_WR_PROHIBIT)
-                        pr_info("%lu: Write access to the SCM increment is suspended\n",
+                        pr_info("%lx: Write access to the SCM increment is suspended\n",
                                 (unsigned long) bdev->scmdev->address);
                 bdev->state = SCM_WR_PROHIBIT;
                 spin_unlock_irqrestore(&bdev->lock, flags);
@@ -445,7 +445,7 @@ void scm_blk_set_available(struct scm_blk_dev *bdev)
 
         spin_lock_irqsave(&bdev->lock, flags);
         if (bdev->state == SCM_WR_PROHIBIT)
-                pr_info("%lu: Write access to the SCM increment is restored\n",
+                pr_info("%lx: Write access to the SCM increment is restored\n",
                         (unsigned long) bdev->scmdev->address);
         bdev->state = SCM_OPER;
         spin_unlock_irqrestore(&bdev->lock, flags);
@@ -463,12 +463,15 @@ static int __init scm_blk_init(void)
                 goto out;
 
         scm_major = ret;
-        if (scm_alloc_rqs(nr_requests))
+        ret = scm_alloc_rqs(nr_requests);
+        if (ret)
                 goto out_unreg;
 
         scm_debug = debug_register("scm_log", 16, 1, 16);
-        if (!scm_debug)
+        if (!scm_debug) {
+                ret = -ENOMEM;
                 goto out_free;
+        }
 
         debug_register_view(scm_debug, &debug_hex_ascii_view);
         debug_set_level(scm_debug, 2);
diff --git a/drivers/s390/block/scm_drv.c b/drivers/s390/block/scm_drv.c
index 5f6180d6ff08..c98cf52d78d1 100644
--- a/drivers/s390/block/scm_drv.c
+++ b/drivers/s390/block/scm_drv.c
@@ -19,7 +19,7 @@ static void scm_notify(struct scm_device *scmdev, enum scm_event event)
 
         switch (event) {
         case SCM_CHANGE:
-                pr_info("%lu: The capabilities of the SCM increment changed\n",
+                pr_info("%lx: The capabilities of the SCM increment changed\n",
                         (unsigned long) scmdev->address);
                 SCM_LOG(2, "State changed");
                 SCM_LOG_STATE(2, scmdev);
diff --git a/drivers/s390/char/tty3270.c b/drivers/s390/char/tty3270.c
index b907dba24025..cee69dac3e18 100644
--- a/drivers/s390/char/tty3270.c
+++ b/drivers/s390/char/tty3270.c
@@ -915,7 +915,7 @@ static int tty3270_install(struct tty_driver *driver, struct tty_struct *tty)
         int i, rc;
 
         /* Check if the tty3270 is already there. */
-        view = raw3270_find_view(&tty3270_fn, tty->index);
+        view = raw3270_find_view(&tty3270_fn, tty->index + RAW3270_FIRSTMINOR);
         if (!IS_ERR(view)) {
                 tp = container_of(view, struct tty3270, view);
                 tty->driver_data = tp;
@@ -927,15 +927,16 @@ static int tty3270_install(struct tty_driver *driver, struct tty_struct *tty)
                 tp->inattr = TF_INPUT;
                 return tty_port_install(&tp->port, driver, tty);
         }
-        if (tty3270_max_index < tty->index)
-                tty3270_max_index = tty->index;
+        if (tty3270_max_index < tty->index + 1)
+                tty3270_max_index = tty->index + 1;
 
         /* Allocate tty3270 structure on first open. */
         tp = tty3270_alloc_view();
         if (IS_ERR(tp))
                 return PTR_ERR(tp);
 
-        rc = raw3270_add_view(&tp->view, &tty3270_fn, tty->index);
+        rc = raw3270_add_view(&tp->view, &tty3270_fn,
+                              tty->index + RAW3270_FIRSTMINOR);
         if (rc) {
                 tty3270_free_view(tp);
                 return rc;
@@ -1846,12 +1847,12 @@ static const struct tty_operations tty3270_ops = {
 
 void tty3270_create_cb(int minor)
 {
-        tty_register_device(tty3270_driver, minor, NULL);
+        tty_register_device(tty3270_driver, minor - RAW3270_FIRSTMINOR, NULL);
 }
 
 void tty3270_destroy_cb(int minor)
 {
-        tty_unregister_device(tty3270_driver, minor);
+        tty_unregister_device(tty3270_driver, minor - RAW3270_FIRSTMINOR);
 }
 
 struct raw3270_notifier tty3270_notifier =
@@ -1884,7 +1885,8 @@ static int __init tty3270_init(void)
         driver->driver_name = "tty3270";
         driver->name = "3270/tty";
         driver->major = IBM_TTY3270_MAJOR;
-        driver->minor_start = 0;
+        driver->minor_start = RAW3270_FIRSTMINOR;
+        driver->name_base = RAW3270_FIRSTMINOR;
         driver->type = TTY_DRIVER_TYPE_SYSTEM;
         driver->subtype = SYSTEM_TYPE_TTY;
         driver->init_termios = tty_std_termios;
diff --git a/drivers/scsi/bnx2fc/bnx2fc_fcoe.c b/drivers/scsi/bnx2fc/bnx2fc_fcoe.c
index 2daf4b0da434..90bc7bd00966 100644
--- a/drivers/scsi/bnx2fc/bnx2fc_fcoe.c
+++ b/drivers/scsi/bnx2fc/bnx2fc_fcoe.c
@@ -940,6 +940,7 @@ static int bnx2fc_libfc_config(struct fc_lport *lport)
         fc_exch_init(lport);
         fc_rport_init(lport);
         fc_disc_init(lport);
+        fc_disc_config(lport, lport);
         return 0;
 }
 
@@ -2133,6 +2134,7 @@ static int _bnx2fc_create(struct net_device *netdev,
         }
 
         ctlr = bnx2fc_to_ctlr(interface);
+        cdev = fcoe_ctlr_to_ctlr_dev(ctlr);
         interface->vlan_id = vlan_id;
 
         interface->timer_work_queue =
@@ -2143,7 +2145,7 @@ static int _bnx2fc_create(struct net_device *netdev,
                 goto ifput_err;
         }
 
-        lport = bnx2fc_if_create(interface, &interface->hba->pcidev->dev, 0);
+        lport = bnx2fc_if_create(interface, &cdev->dev, 0);
         if (!lport) {
                 printk(KERN_ERR PFX "Failed to create interface (%s)\n",
                         netdev->name);
@@ -2159,8 +2161,6 @@ static int _bnx2fc_create(struct net_device *netdev,
         /* Make this master N_port */
         ctlr->lp = lport;
 
-        cdev = fcoe_ctlr_to_ctlr_dev(ctlr);
-
         if (link_state == BNX2FC_CREATE_LINK_UP)
                 cdev->enabled = FCOE_CTLR_ENABLED;
         else
diff --git a/drivers/scsi/fcoe/fcoe.c b/drivers/scsi/fcoe/fcoe.c
index b5d92fc93c70..9bfdc9a3f897 100644
--- a/drivers/scsi/fcoe/fcoe.c
+++ b/drivers/scsi/fcoe/fcoe.c
@@ -490,7 +490,6 @@ static void fcoe_interface_cleanup(struct fcoe_interface *fcoe)
 {
         struct net_device *netdev = fcoe->netdev;
         struct fcoe_ctlr *fip = fcoe_to_ctlr(fcoe);
-        struct fcoe_ctlr_device *ctlr_dev = fcoe_ctlr_to_ctlr_dev(fip);
 
         rtnl_lock();
         if (!fcoe->removed)
@@ -501,7 +500,6 @@ static void fcoe_interface_cleanup(struct fcoe_interface *fcoe)
         /* tear-down the FCoE controller */
         fcoe_ctlr_destroy(fip);
         scsi_host_put(fip->lp->host);
-        fcoe_ctlr_device_delete(ctlr_dev);
         dev_put(netdev);
         module_put(THIS_MODULE);
 }
@@ -2194,6 +2192,8 @@ out_nodev:
  */
 static void fcoe_destroy_work(struct work_struct *work)
 {
+        struct fcoe_ctlr_device *cdev;
+        struct fcoe_ctlr *ctlr;
         struct fcoe_port *port;
         struct fcoe_interface *fcoe;
         struct Scsi_Host *shost;
@@ -2224,10 +2224,15 @@ static void fcoe_destroy_work(struct work_struct *work)
         mutex_lock(&fcoe_config_mutex);
 
         fcoe = port->priv;
+        ctlr = fcoe_to_ctlr(fcoe);
+        cdev = fcoe_ctlr_to_ctlr_dev(ctlr);
+
         fcoe_if_destroy(port->lport);
         fcoe_interface_cleanup(fcoe);
 
         mutex_unlock(&fcoe_config_mutex);
+
+        fcoe_ctlr_device_delete(cdev);
 }
 
 /**
@@ -2335,7 +2340,9 @@ static int _fcoe_create(struct net_device *netdev, enum fip_state fip_mode,
                 rc = -EIO;
                 rtnl_unlock();
                 fcoe_interface_cleanup(fcoe);
-                goto out_nortnl;
+                mutex_unlock(&fcoe_config_mutex);
+                fcoe_ctlr_device_delete(ctlr_dev);
+                goto out;
         }
 
         /* Make this the "master" N_Port */
@@ -2375,8 +2382,8 @@ static int _fcoe_create(struct net_device *netdev, enum fip_state fip_mode,
 
 out_nodev:
         rtnl_unlock();
-out_nortnl:
         mutex_unlock(&fcoe_config_mutex);
+out:
         return rc;
 }
 
diff --git a/drivers/scsi/fcoe/fcoe_ctlr.c b/drivers/scsi/fcoe/fcoe_ctlr.c
index 08c3bc398da2..a76247201be5 100644
--- a/drivers/scsi/fcoe/fcoe_ctlr.c
+++ b/drivers/scsi/fcoe/fcoe_ctlr.c
@@ -2815,6 +2815,47 @@ unlock:
 }
 
 /**
+ * fcoe_ctlr_mode_set() - Set or reset the ctlr's mode
+ * @lport: The local port to be (re)configured
+ * @fip:   The FCoE controller whose mode is changing
+ * @fip_mode: The new fip mode
+ *
+ * Note that the we shouldn't be changing the libfc discovery settings
+ * (fc_disc_config) while an lport is going through the libfc state
+ * machine. The mode can only be changed when a fcoe_ctlr device is
+ * disabled, so that should ensure that this routine is only called
+ * when nothing is happening.
+ */
+void fcoe_ctlr_mode_set(struct fc_lport *lport, struct fcoe_ctlr *fip,
+                        enum fip_state fip_mode)
+{
+        void *priv;
+
+        WARN_ON(lport->state != LPORT_ST_RESET &&
+                lport->state != LPORT_ST_DISABLED);
+
+        if (fip_mode == FIP_MODE_VN2VN) {
+                lport->rport_priv_size = sizeof(struct fcoe_rport);
+                lport->point_to_multipoint = 1;
+                lport->tt.disc_recv_req = fcoe_ctlr_disc_recv;
+                lport->tt.disc_start = fcoe_ctlr_disc_start;
+                lport->tt.disc_stop = fcoe_ctlr_disc_stop;
+                lport->tt.disc_stop_final = fcoe_ctlr_disc_stop_final;
+                priv = fip;
+        } else {
+                lport->rport_priv_size = 0;
+                lport->point_to_multipoint = 0;
+                lport->tt.disc_recv_req = NULL;
+                lport->tt.disc_start = NULL;
+                lport->tt.disc_stop = NULL;
+                lport->tt.disc_stop_final = NULL;
+                priv = lport;
+        }
+
+        fc_disc_config(lport, priv);
+}
+
+/**
  * fcoe_libfc_config() - Sets up libfc related properties for local port
  * @lport:    The local port to configure libfc for
  * @fip:      The FCoE controller in use by the local port
@@ -2833,21 +2874,9 @@ int fcoe_libfc_config(struct fc_lport *lport, struct fcoe_ctlr *fip,
         fc_exch_init(lport);
         fc_elsct_init(lport);
         fc_lport_init(lport);
-        if (fip->mode == FIP_MODE_VN2VN)
-                lport->rport_priv_size = sizeof(struct fcoe_rport);
         fc_rport_init(lport);
-        if (fip->mode == FIP_MODE_VN2VN) {
-                lport->point_to_multipoint = 1;
-                lport->tt.disc_recv_req = fcoe_ctlr_disc_recv;
-                lport->tt.disc_start = fcoe_ctlr_disc_start;
-                lport->tt.disc_stop = fcoe_ctlr_disc_stop;
-                lport->tt.disc_stop_final = fcoe_ctlr_disc_stop_final;
-                mutex_init(&lport->disc.disc_mutex);
-                INIT_LIST_HEAD(&lport->disc.rports);
-                lport->disc.priv = fip;
-        } else {
-                fc_disc_init(lport);
-        }
+        fc_disc_init(lport);
+        fcoe_ctlr_mode_set(lport, fip, fip->mode);
         return 0;
 }
 EXPORT_SYMBOL_GPL(fcoe_libfc_config);
@@ -2875,6 +2904,7 @@ EXPORT_SYMBOL(fcoe_fcf_get_selected);
 void fcoe_ctlr_set_fip_mode(struct fcoe_ctlr_device *ctlr_dev)
 {
         struct fcoe_ctlr *ctlr = fcoe_ctlr_device_priv(ctlr_dev);
+        struct fc_lport *lport = ctlr->lp;
 
         mutex_lock(&ctlr->ctlr_mutex);
         switch (ctlr_dev->mode) {
@@ -2888,5 +2918,7 @@ void fcoe_ctlr_set_fip_mode(struct fcoe_ctlr_device *ctlr_dev)
         }
 
         mutex_unlock(&ctlr->ctlr_mutex);
+
+        fcoe_ctlr_mode_set(lport, ctlr, ctlr->mode);
 }
 EXPORT_SYMBOL(fcoe_ctlr_set_fip_mode);
diff --git a/drivers/scsi/libfc/fc_disc.c b/drivers/scsi/libfc/fc_disc.c
index 8e561e6a557c..880a9068ca12 100644
--- a/drivers/scsi/libfc/fc_disc.c
+++ b/drivers/scsi/libfc/fc_disc.c
@@ -712,12 +712,13 @@ static void fc_disc_stop_final(struct fc_lport *lport)
 }
 
 /**
- * fc_disc_init() - Initialize the discovery layer for a local port
- * @lport: The local port that needs the discovery layer to be initialized
+ * fc_disc_config() - Configure the discovery layer for a local port
+ * @lport: The local port that needs the discovery layer to be configured
+ * @priv: Private data structre for users of the discovery layer
  */
-int fc_disc_init(struct fc_lport *lport)
+void fc_disc_config(struct fc_lport *lport, void *priv)
 {
-        struct fc_disc *disc;
+        struct fc_disc *disc = &lport->disc;
 
         if (!lport->tt.disc_start)
                 lport->tt.disc_start = fc_disc_start;
@@ -732,12 +733,21 @@ int fc_disc_init(struct fc_lport *lport)
                 lport->tt.disc_recv_req = fc_disc_recv_req;
 
         disc = &lport->disc;
+
+        disc->priv = priv;
+}
+EXPORT_SYMBOL(fc_disc_config);
+
+/**
+ * fc_disc_init() - Initialize the discovery layer for a local port
+ * @lport: The local port that needs the discovery layer to be initialized
+ */
+void fc_disc_init(struct fc_lport *lport)
+{
+        struct fc_disc *disc = &lport->disc;
+
         INIT_DELAYED_WORK(&disc->disc_work, fc_disc_timeout);
         mutex_init(&disc->disc_mutex);
         INIT_LIST_HEAD(&disc->rports);
-
-        disc->priv = lport;
-
-        return 0;
 }
 EXPORT_SYMBOL(fc_disc_init);
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index f80eee74a311..2be0de920d67 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -55,6 +55,7 @@ comment "SPI Master Controller Drivers"
 
 config SPI_ALTERA
         tristate "Altera SPI Controller"
+        depends on GENERIC_HARDIRQS
         select SPI_BITBANG
         help
           This is the driver for the Altera SPI Controller.
@@ -310,7 +311,7 @@ config SPI_PXA2XX_DMA
 
 config SPI_PXA2XX
         tristate "PXA2xx SSP SPI master"
-        depends on ARCH_PXA || PCI || ACPI
+        depends on (ARCH_PXA || PCI || ACPI) && GENERIC_HARDIRQS
         select PXA_SSP if ARCH_PXA
         help
           This enables using a PXA2xx or Sodaville SSP port as a SPI master
diff --git a/drivers/spi/spi-bcm63xx.c b/drivers/spi/spi-bcm63xx.c
index 9578af782a77..d7df435d962e 100644
--- a/drivers/spi/spi-bcm63xx.c
+++ b/drivers/spi/spi-bcm63xx.c
@@ -152,7 +152,6 @@ static void bcm63xx_spi_setup_transfer(struct spi_device *spi,
 static int bcm63xx_spi_setup(struct spi_device *spi)
 {
         struct bcm63xx_spi *bs;
-        int ret;
 
         bs = spi_master_get_devdata(spi->master);
 
@@ -490,7 +489,7 @@ static int bcm63xx_spi_probe(struct platform_device *pdev)
         default:
                 dev_err(dev, "unsupported MSG_CTL width: %d\n",
                          bs->msg_ctl_width);
-                goto out_clk_disable;
+                goto out_err;
         }
 
         /* Initialize hardware */
diff --git a/drivers/spi/spi-mpc512x-psc.c b/drivers/spi/spi-mpc512x-psc.c
index 89480b281d74..3e490ee7f275 100644
--- a/drivers/spi/spi-mpc512x-psc.c
+++ b/drivers/spi/spi-mpc512x-psc.c
@@ -164,7 +164,7 @@ static int mpc512x_psc_spi_transfer_rxtx(struct spi_device *spi,
 
                 for (i = count; i > 0; i--) {
                         data = tx_buf ? *tx_buf++ : 0;
-                        if (len == EOFBYTE)
+                        if (len == EOFBYTE && t->cs_change)
                                 setbits32(&fifo->txcmd, MPC512x_PSC_FIFO_EOF);
                         out_8(&fifo->txdata_8, data);
                         len--;
diff --git a/drivers/spi/spi-pl022.c b/drivers/spi/spi-pl022.c
index b0fe393c882c..371cc66f1a0e 100644
--- a/drivers/spi/spi-pl022.c
+++ b/drivers/spi/spi-pl022.c
@@ -1139,6 +1139,35 @@ err_no_rxchan:
         return -ENODEV;
 }
 
+static int pl022_dma_autoprobe(struct pl022 *pl022)
+{
+        struct device *dev = &pl022->adev->dev;
+
+        /* automatically configure DMA channels from platform, normally using DT */
+        pl022->dma_rx_channel = dma_request_slave_channel(dev, "rx");
+        if (!pl022->dma_rx_channel)
+                goto err_no_rxchan;
+
+        pl022->dma_tx_channel = dma_request_slave_channel(dev, "tx");
+        if (!pl022->dma_tx_channel)
+                goto err_no_txchan;
+
+        pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL);
+        if (!pl022->dummypage)
+                goto err_no_dummypage;
+
+        return 0;
+
+err_no_dummypage:
+        dma_release_channel(pl022->dma_tx_channel);
+        pl022->dma_tx_channel = NULL;
+err_no_txchan:
+        dma_release_channel(pl022->dma_rx_channel);
+        pl022->dma_rx_channel = NULL;
+err_no_rxchan:
+        return -ENODEV;
+}
+                
 static void terminate_dma(struct pl022 *pl022)
 {
         struct dma_chan *rxchan = pl022->dma_rx_channel;
@@ -1167,6 +1196,11 @@ static inline int configure_dma(struct pl022 *pl022)
         return -ENODEV;
 }
 
+static inline int pl022_dma_autoprobe(struct pl022 *pl022)
+{
+        return 0;
+}
+
 static inline int pl022_dma_probe(struct pl022 *pl022)
 {
         return 0;
@@ -2226,8 +2260,13 @@ static int pl022_probe(struct amba_device *adev, const struct amba_id *id)
                 goto err_no_irq;
         }
 
-        /* Get DMA channels */
-        if (platform_info->enable_dma) {
+        /* Get DMA channels, try autoconfiguration first */
+        status = pl022_dma_autoprobe(pl022);
+
+        /* If that failed, use channels from platform_info */
+        if (status == 0)
+                platform_info->enable_dma = 1;
+        else if (platform_info->enable_dma) {
                 status = pl022_dma_probe(pl022);
                 if (status != 0)
                         platform_info->enable_dma = 0;
diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
index 90b27a3508a6..810413883c79 100644
--- a/drivers/spi/spi-pxa2xx.c
+++ b/drivers/spi/spi-pxa2xx.c
@@ -1168,7 +1168,6 @@ static int pxa2xx_spi_probe(struct platform_device *pdev)
 
         master->dev.parent = &pdev->dev;
         master->dev.of_node = pdev->dev.of_node;
-        ACPI_HANDLE_SET(&master->dev, ACPI_HANDLE(&pdev->dev));
         /* the spi->mode bits understood by this driver: */
         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
 
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index e862ab8853aa..4188b2faac5c 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -994,25 +994,30 @@ static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
 {
         struct s3c64xx_spi_driver_data *sdd = data;
         struct spi_master *spi = sdd->master;
-        unsigned int val;
+        unsigned int val, clr = 0;
 
-        val = readl(sdd->regs + S3C64XX_SPI_PENDING_CLR);
+        val = readl(sdd->regs + S3C64XX_SPI_STATUS);
 
-        val &= S3C64XX_SPI_PND_RX_OVERRUN_CLR |
-                S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
-                S3C64XX_SPI_PND_TX_OVERRUN_CLR |
-                S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
-
-        writel(val, sdd->regs + S3C64XX_SPI_PENDING_CLR);
-
-        if (val & S3C64XX_SPI_PND_RX_OVERRUN_CLR)
+        if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) {
+                clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR;
                 dev_err(&spi->dev, "RX overrun\n");
-        if (val & S3C64XX_SPI_PND_RX_UNDERRUN_CLR)
+        }
+        if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) {
+                clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR;
                 dev_err(&spi->dev, "RX underrun\n");
-        if (val & S3C64XX_SPI_PND_TX_OVERRUN_CLR)
+        }
+        if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) {
+                clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR;
                 dev_err(&spi->dev, "TX overrun\n");
-        if (val & S3C64XX_SPI_PND_TX_UNDERRUN_CLR)
+        }
+        if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) {
+                clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
                 dev_err(&spi->dev, "TX underrun\n");
+        }
+
+        /* Clear the pending irq by setting and then clearing it */
+        writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR);
+        writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR);
 
         return IRQ_HANDLED;
 }
@@ -1036,9 +1041,13 @@ static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
         writel(0, regs + S3C64XX_SPI_MODE_CFG);
         writel(0, regs + S3C64XX_SPI_PACKET_CNT);
 
-        /* Clear any irq pending bits */
-        writel(readl(regs + S3C64XX_SPI_PENDING_CLR),
-                                regs + S3C64XX_SPI_PENDING_CLR);
+        /* Clear any irq pending bits, should set and clear the bits */
+        val = S3C64XX_SPI_PND_RX_OVERRUN_CLR |
+                S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
+                S3C64XX_SPI_PND_TX_OVERRUN_CLR |
+                S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
+        writel(val, regs + S3C64XX_SPI_PENDING_CLR);
+        writel(0, regs + S3C64XX_SPI_PENDING_CLR);
 
         writel(0, regs + S3C64XX_SPI_SWAP_CFG);
 
diff --git a/drivers/spi/spi-tegra20-slink.c b/drivers/spi/spi-tegra20-slink.c
index b8698b389ef3..a829563f4713 100644
--- a/drivers/spi/spi-tegra20-slink.c
+++ b/drivers/spi/spi-tegra20-slink.c
@@ -858,21 +858,6 @@ static int tegra_slink_setup(struct spi_device *spi)
         return 0;
 }
 
-static int tegra_slink_prepare_transfer(struct spi_master *master)
-{
-        struct tegra_slink_data *tspi = spi_master_get_devdata(master);
-
-        return pm_runtime_get_sync(tspi->dev);
-}
-
-static int tegra_slink_unprepare_transfer(struct spi_master *master)
-{
-        struct tegra_slink_data *tspi = spi_master_get_devdata(master);
-
-        pm_runtime_put(tspi->dev);
-        return 0;
-}
-
 static int tegra_slink_transfer_one_message(struct spi_master *master,
                         struct spi_message *msg)
 {
@@ -885,6 +870,12 @@ static int tegra_slink_transfer_one_message(struct spi_master *master,
 
         msg->status = 0;
         msg->actual_length = 0;
+        ret = pm_runtime_get_sync(tspi->dev);
+        if (ret < 0) {
+                dev_err(tspi->dev, "runtime get failed: %d\n", ret);
+                goto done;
+        }
+
         single_xfer = list_is_singular(&msg->transfers);
         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
                 INIT_COMPLETION(tspi->xfer_completion);
@@ -921,6 +912,8 @@ static int tegra_slink_transfer_one_message(struct spi_master *master,
 exit:
         tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND);
         tegra_slink_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2);
+        pm_runtime_put(tspi->dev);
+done:
         msg->status = ret;
         spi_finalize_current_message(master);
         return ret;
@@ -1148,9 +1141,7 @@ static int tegra_slink_probe(struct platform_device *pdev)
         /* the spi->mode bits understood by this driver: */
         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
         master->setup = tegra_slink_setup;
-        master->prepare_transfer_hardware = tegra_slink_prepare_transfer;
         master->transfer_one_message = tegra_slink_transfer_one_message;
-        master->unprepare_transfer_hardware = tegra_slink_unprepare_transfer;
         master->num_chipselect = MAX_CHIP_SELECT;
         master->bus_num = -1;
 
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index f996c600eb8c..004b10f184d4 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -543,17 +543,16 @@ static void spi_pump_messages(struct kthread_work *work)
         /* Lock queue and check for queue work */
         spin_lock_irqsave(&master->queue_lock, flags);
         if (list_empty(&master->queue) || !master->running) {
-                if (master->busy && master->unprepare_transfer_hardware) {
-                        ret = master->unprepare_transfer_hardware(master);
-                        if (ret) {
-                                spin_unlock_irqrestore(&master->queue_lock, flags);
-                                dev_err(&master->dev,
-                                        "failed to unprepare transfer hardware\n");
-                                return;
-                        }
+                if (!master->busy) {
+                        spin_unlock_irqrestore(&master->queue_lock, flags);
+                        return;
                 }
                 master->busy = false;
                 spin_unlock_irqrestore(&master->queue_lock, flags);
+                if (master->unprepare_transfer_hardware &&
+                    master->unprepare_transfer_hardware(master))
+                        dev_err(&master->dev,
+                                "failed to unprepare transfer hardware\n");
                 return;
         }
 
@@ -984,7 +983,7 @@ static void acpi_register_spi_devices(struct spi_master *master)
         acpi_status status;
         acpi_handle handle;
 
-        handle = ACPI_HANDLE(&master->dev);
+        handle = ACPI_HANDLE(master->dev.parent);
         if (!handle)
                 return;
 
diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
index 3ea5408fcbeb..1c1942b5cee9 100644
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -245,7 +245,7 @@ static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg,
         }
 }
 
-static void pl011_dma_probe_initcall(struct uart_amba_port *uap)
+static void pl011_dma_probe_initcall(struct device *dev, struct uart_amba_port *uap)
 {
         /* DMA is the sole user of the platform data right now */
         struct amba_pl011_data *plat = uap->port.dev->platform_data;
@@ -259,20 +259,25 @@ static void pl011_dma_probe_initcall(struct uart_amba_port *uap)
         struct dma_chan *chan;
         dma_cap_mask_t mask;
 
-        /* We need platform data */
-        if (!plat || !plat->dma_filter) {
-                dev_info(uap->port.dev, "no DMA platform data\n");
-                return;
-        }
+        chan = dma_request_slave_channel(dev, "tx");
 
-        /* Try to acquire a generic DMA engine slave TX channel */
-        dma_cap_zero(mask);
-        dma_cap_set(DMA_SLAVE, mask);
-
-        chan = dma_request_channel(mask, plat->dma_filter, plat->dma_tx_param);
         if (!chan) {
-                dev_err(uap->port.dev, "no TX DMA channel!\n");
-                return;
+                /* We need platform data */
+                if (!plat || !plat->dma_filter) {
+                        dev_info(uap->port.dev, "no DMA platform data\n");
+                        return;
+                }
+
+                /* Try to acquire a generic DMA engine slave TX channel */
+                dma_cap_zero(mask);
+                dma_cap_set(DMA_SLAVE, mask);
+
+                chan = dma_request_channel(mask, plat->dma_filter,
+                                                plat->dma_tx_param);
+                if (!chan) {
+                        dev_err(uap->port.dev, "no TX DMA channel!\n");
+                        return;
+                }
         }
 
         dmaengine_slave_config(chan, &tx_conf);
@@ -282,7 +287,18 @@ static void pl011_dma_probe_initcall(struct uart_amba_port *uap)
                  dma_chan_name(uap->dmatx.chan));
 
         /* Optionally make use of an RX channel as well */
-        if (plat->dma_rx_param) {
+        chan = dma_request_slave_channel(dev, "rx");
+        
+        if (!chan && plat->dma_rx_param) {
+                chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
+
+                if (!chan) {
+                        dev_err(uap->port.dev, "no RX DMA channel!\n");
+                        return;
+                }
+        }
+
+        if (chan) {
                 struct dma_slave_config rx_conf = {
                         .src_addr = uap->port.mapbase + UART01x_DR,
                         .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
@@ -291,12 +307,6 @@ static void pl011_dma_probe_initcall(struct uart_amba_port *uap)
                         .device_fc = false,
                 };
 
-                chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
-                if (!chan) {
-                        dev_err(uap->port.dev, "no RX DMA channel!\n");
-                        return;
-                }
-
                 dmaengine_slave_config(chan, &rx_conf);
                 uap->dmarx.chan = chan;
 
@@ -315,6 +325,7 @@ static void pl011_dma_probe_initcall(struct uart_amba_port *uap)
 struct dma_uap {
         struct list_head node;
         struct uart_amba_port *uap;
+        struct device *dev;
 };
 
 static LIST_HEAD(pl011_dma_uarts);
@@ -325,7 +336,7 @@ static int __init pl011_dma_initcall(void)
 
         list_for_each_safe(node, tmp, &pl011_dma_uarts) {
                 struct dma_uap *dmau = list_entry(node, struct dma_uap, node);
-                pl011_dma_probe_initcall(dmau->uap);
+                pl011_dma_probe_initcall(dmau->dev, dmau->uap);
                 list_del(node);
                 kfree(dmau);
         }
@@ -334,18 +345,19 @@ static int __init pl011_dma_initcall(void)
 
 device_initcall(pl011_dma_initcall);
 
-static void pl011_dma_probe(struct uart_amba_port *uap)
+static void pl011_dma_probe(struct device *dev, struct uart_amba_port *uap)
 {
         struct dma_uap *dmau = kzalloc(sizeof(struct dma_uap), GFP_KERNEL);
         if (dmau) {
                 dmau->uap = uap;
+                dmau->dev = dev;
                 list_add_tail(&dmau->node, &pl011_dma_uarts);
         }
 }
 #else
-static void pl011_dma_probe(struct uart_amba_port *uap)
+static void pl011_dma_probe(struct device *dev, struct uart_amba_port *uap)
 {
-        pl011_dma_probe_initcall(uap);
+        pl011_dma_probe_initcall(dev, uap);
 }
 #endif
 
@@ -979,7 +991,7 @@ static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
 
 #else
 /* Blank functions if the DMA engine is not available */
-static inline void pl011_dma_probe(struct uart_amba_port *uap)
+static inline void pl011_dma_probe(struct device *dev, struct uart_amba_port *uap)
 {
 }
 
@@ -2020,7 +2032,7 @@ static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
         uap->port.ops = &amba_pl011_pops;
         uap->port.flags = UPF_BOOT_AUTOCONF;
         uap->port.line = i;
-        pl011_dma_probe(uap);
+        pl011_dma_probe(&dev->dev, uap);
 
         /* Ensure interrupts from this UART are masked and cleared */
         writew(0, uap->port.membase + UART011_IMSC);
diff --git a/drivers/usb/core/port.c b/drivers/usb/core/port.c
index 797f9d514732..65d4e55552c6 100644
--- a/drivers/usb/core/port.c
+++ b/drivers/usb/core/port.c
@@ -67,7 +67,6 @@ static void usb_port_device_release(struct device *dev)
 {
         struct usb_port *port_dev = to_usb_port(dev);
 
-        dev_pm_qos_hide_flags(dev);
         kfree(port_dev);
 }
 
diff --git a/drivers/video/fbmon.c b/drivers/video/fbmon.c
index 94ad0f71383c..7f6709991a5c 100644
--- a/drivers/video/fbmon.c
+++ b/drivers/video/fbmon.c
@@ -1400,7 +1400,7 @@ int fb_videomode_from_videomode(const struct videomode *vm,
         fbmode->vmode = 0;
         if (vm->dmt_flags & VESA_DMT_HSYNC_HIGH)
                 fbmode->sync |= FB_SYNC_HOR_HIGH_ACT;
-        if (vm->dmt_flags & VESA_DMT_HSYNC_HIGH)
+        if (vm->dmt_flags & VESA_DMT_VSYNC_HIGH)
                 fbmode->sync |= FB_SYNC_VERT_HIGH_ACT;
         if (vm->data_flags & DISPLAY_FLAGS_INTERLACED)
                 fbmode->vmode |= FB_VMODE_INTERLACED;
diff --git a/drivers/video/omap2/displays/panel-generic-dpi.c b/drivers/video/omap2/displays/panel-generic-dpi.c
index c904f42d81c1..a0c9396ca43f 100644
--- a/drivers/video/omap2/displays/panel-generic-dpi.c
+++ b/drivers/video/omap2/displays/panel-generic-dpi.c
@@ -35,7 +35,7 @@
 #include <linux/slab.h>
 #include <video/omapdss.h>
 
-#include <video/omap-panel-generic-dpi.h>
+#include <video/omap-panel-data.h>
 
 struct panel_config {
         struct omap_video_timings timings;
diff --git a/drivers/video/omap2/displays/panel-n8x0.c b/drivers/video/omap2/displays/panel-n8x0.c
index dd1294750802..9c6b5fafeb2e 100644
--- a/drivers/video/omap2/displays/panel-n8x0.c
+++ b/drivers/video/omap2/displays/panel-n8x0.c
@@ -9,7 +9,7 @@
 #include <linux/fb.h>
 
 #include <video/omapdss.h>
-#include <video/omap-panel-n8x0.h>
+#include <video/omap-panel-data.h>
 
 #define BLIZZARD_REV_CODE                      0x00
 #define BLIZZARD_CONFIG                        0x02
diff --git a/drivers/video/omap2/displays/panel-picodlp.c b/drivers/video/omap2/displays/panel-picodlp.c
index 1b94018aac3e..974ac29236aa 100644
--- a/drivers/video/omap2/displays/panel-picodlp.c
+++ b/drivers/video/omap2/displays/panel-picodlp.c
@@ -31,7 +31,7 @@
 #include <linux/gpio.h>
 
 #include <video/omapdss.h>
-#include <video/omap-panel-picodlp.h>
+#include <video/omap-panel-data.h>
 
 #include "panel-picodlp.h"
 
diff --git a/drivers/video/omap2/displays/panel-taal.c b/drivers/video/omap2/displays/panel-taal.c
index a32407a5735a..031d4069f332 100644
--- a/drivers/video/omap2/displays/panel-taal.c
+++ b/drivers/video/omap2/displays/panel-taal.c
@@ -33,7 +33,7 @@
 #include <linux/mutex.h>
 
 #include <video/omapdss.h>
-#include <video/omap-panel-nokia-dsi.h>
+#include <video/omap-panel-data.h>
 #include <video/mipi_display.h>
 
 /* DSI Virtual channel. Hardcoded for now. */
diff --git a/drivers/video/omap2/displays/panel-tfp410.c b/drivers/video/omap2/displays/panel-tfp410.c
index 8281baafe1ef..a1dba868cef1 100644
--- a/drivers/video/omap2/displays/panel-tfp410.c
+++ b/drivers/video/omap2/displays/panel-tfp410.c
@@ -24,7 +24,7 @@
 #include <linux/gpio.h>
 #include <drm/drm_edid.h>
 
-#include <video/omap-panel-tfp410.h>
+#include <video/omap-panel-data.h>
 
 static const struct omap_video_timings tfp410_default_timings = {
         .x_res          = 640,
diff --git a/drivers/video/sh_mobile_lcdcfb.c b/drivers/video/sh_mobile_lcdcfb.c
index 63203acef812..0264704a52be 100644
--- a/drivers/video/sh_mobile_lcdcfb.c
+++ b/drivers/video/sh_mobile_lcdcfb.c
@@ -858,6 +858,7 @@ static void sh_mobile_lcdc_geometry(struct sh_mobile_lcdc_chan *ch)
         tmp = ((mode->xres & 7) << 24) | ((display_h_total & 7) << 16)
             | ((mode->hsync_len & 7) << 8) | (hsync_pos & 7);
         lcdc_write_chan(ch, LDHAJR, tmp);
+        lcdc_write_chan_mirror(ch, LDHAJR, tmp);
 }
 
 static void sh_mobile_lcdc_overlay_setup(struct sh_mobile_lcdc_overlay *ovl)
diff --git a/drivers/video/uvesafb.c b/drivers/video/uvesafb.c
index b75db0186488..d4284458377e 100644
--- a/drivers/video/uvesafb.c
+++ b/drivers/video/uvesafb.c
@@ -1973,7 +1973,8 @@ static int uvesafb_init(void)
                         err = -ENOMEM;
 
                 if (err) {
-                        platform_device_put(uvesafb_device);
+                        if (uvesafb_device)
+                                platform_device_put(uvesafb_device);
                         platform_driver_unregister(&uvesafb_driver);
                         cn_del_callback(&uvesafb_cn_id);
                         return err;
diff --git a/firmware/Makefile b/firmware/Makefile
index 5d8ee1319b5c..cbb09ce9730a 100644
--- a/firmware/Makefile
+++ b/firmware/Makefile
@@ -82,7 +82,7 @@ fw-shipped-$(CONFIG_SCSI_ADVANSYS) += advansys/mcode.bin advansys/38C1600.bin \
 fw-shipped-$(CONFIG_SCSI_QLOGIC_1280) += qlogic/1040.bin qlogic/1280.bin \
                                          qlogic/12160.bin
 fw-shipped-$(CONFIG_SCSI_QLOGICPTI) += qlogic/isp1000.bin
-fw-shipped-$(CONFIG_INFINIBAND_QIB) += intel/sd7220.fw
+fw-shipped-$(CONFIG_INFINIBAND_QIB) += qlogic/sd7220.fw
 fw-shipped-$(CONFIG_SND_KORG1212) += korg/k1212.dsp
 fw-shipped-$(CONFIG_SND_MAESTRO3) += ess/maestro3_assp_kernel.fw \
                                      ess/maestro3_assp_minisrc.fw
diff --git a/firmware/intel/sd7220.fw.ihex b/firmware/qlogic/sd7220.fw.ihex
index a33636319112..a33636319112 100644
--- a/firmware/intel/sd7220.fw.ihex
+++ b/firmware/qlogic/sd7220.fw.ihex
diff --git a/fs/block_dev.c b/fs/block_dev.c
index aea605c98ba6..aae187a7f94a 100644
--- a/fs/block_dev.c
+++ b/fs/block_dev.c
@@ -551,6 +551,7 @@ struct block_device *bdgrab(struct block_device *bdev)
         ihold(bdev->bd_inode);
         return bdev;
 }
+EXPORT_SYMBOL(bdgrab);
 
 long nr_blockdev_pages(void)
 {
diff --git a/fs/ext4/extents.c b/fs/ext4/extents.c
index 56efcaadf848..9c6d06dcef8b 100644
--- a/fs/ext4/extents.c
+++ b/fs/ext4/extents.c
@@ -2999,20 +2999,23 @@ static int ext4_split_extent_at(handle_t *handle,
                         if (split_flag & EXT4_EXT_DATA_VALID1) {
                                 err = ext4_ext_zeroout(inode, ex2);
                                 zero_ex.ee_block = ex2->ee_block;
-                                zero_ex.ee_len = ext4_ext_get_actual_len(ex2);
+                                zero_ex.ee_len = cpu_to_le16(
+                                                ext4_ext_get_actual_len(ex2));
                                 ext4_ext_store_pblock(&zero_ex,
                                                       ext4_ext_pblock(ex2));
                         } else {
                                 err = ext4_ext_zeroout(inode, ex);
                                 zero_ex.ee_block = ex->ee_block;
-                                zero_ex.ee_len = ext4_ext_get_actual_len(ex);
+                                zero_ex.ee_len = cpu_to_le16(
+                                                ext4_ext_get_actual_len(ex));
                                 ext4_ext_store_pblock(&zero_ex,
                                                       ext4_ext_pblock(ex));
                         }
                 } else {
                         err = ext4_ext_zeroout(inode, &orig_ex);
                         zero_ex.ee_block = orig_ex.ee_block;
-                        zero_ex.ee_len = ext4_ext_get_actual_len(&orig_ex);
+                        zero_ex.ee_len = cpu_to_le16(
+                                                ext4_ext_get_actual_len(&orig_ex));
                         ext4_ext_store_pblock(&zero_ex,
                                               ext4_ext_pblock(&orig_ex));
                 }
@@ -3272,7 +3275,7 @@ static int ext4_ext_convert_to_initialized(handle_t *handle,
                 if (err)
                         goto out;
                 zero_ex.ee_block = ex->ee_block;
-                zero_ex.ee_len = ext4_ext_get_actual_len(ex);
+                zero_ex.ee_len = cpu_to_le16(ext4_ext_get_actual_len(ex));
                 ext4_ext_store_pblock(&zero_ex, ext4_ext_pblock(ex));
 
                 err = ext4_ext_get_access(handle, inode, path + depth);
diff --git a/fs/ext4/indirect.c b/fs/ext4/indirect.c
index b505a145a593..a04183127ef0 100644
--- a/fs/ext4/indirect.c
+++ b/fs/ext4/indirect.c
@@ -1539,9 +1539,9 @@ static int free_hole_blocks(handle_t *handle, struct inode *inode,
                 blk = *i_data;
                 if (level > 0) {
                         ext4_lblk_t first2;
-                        bh = sb_bread(inode->i_sb, blk);
+                        bh = sb_bread(inode->i_sb, le32_to_cpu(blk));
                         if (!bh) {
-                                EXT4_ERROR_INODE_BLOCK(inode, blk,
+                                EXT4_ERROR_INODE_BLOCK(inode, le32_to_cpu(blk),
                                                        "Read failure");
                                 return -EIO;
                         }
diff --git a/fs/gfs2/file.c b/fs/gfs2/file.c
index 019f45e45097..d79c2dadc536 100644
--- a/fs/gfs2/file.c
+++ b/fs/gfs2/file.c
@@ -923,8 +923,11 @@ static int gfs2_lock(struct file *file, int cmd, struct file_lock *fl)
                 cmd = F_SETLK;
                 fl->fl_type = F_UNLCK;
         }
-        if (unlikely(test_bit(SDF_SHUTDOWN, &sdp->sd_flags)))
+        if (unlikely(test_bit(SDF_SHUTDOWN, &sdp->sd_flags))) {
+                if (fl->fl_type == F_UNLCK)
+                        posix_lock_file_wait(file, fl);
                 return -EIO;
+        }
         if (IS_GETLK(cmd))
                 return dlm_posix_get(ls->ls_dlm, ip->i_no_addr, file, fl);
         else if (fl->fl_type == F_UNLCK)
diff --git a/fs/gfs2/incore.h b/fs/gfs2/incore.h
index 156e42ec84ea..5c29216e9cc1 100644
--- a/fs/gfs2/incore.h
+++ b/fs/gfs2/incore.h
@@ -588,6 +588,7 @@ struct lm_lockstruct {
         struct dlm_lksb ls_control_lksb; /* control_lock */
         char ls_control_lvb[GDLM_LVB_SIZE]; /* control_lock lvb */
         struct completion ls_sync_wait; /* {control,mounted}_{lock,unlock} */
+        char *ls_lvb_bits;
 
         spinlock_t ls_recover_spin; /* protects following fields */
         unsigned long ls_recover_flags; /* DFL_ */
diff --git a/fs/gfs2/lock_dlm.c b/fs/gfs2/lock_dlm.c
index 9802de0f85e6..c8423d6de6c3 100644
--- a/fs/gfs2/lock_dlm.c
+++ b/fs/gfs2/lock_dlm.c
@@ -483,12 +483,8 @@ static void control_lvb_write(struct lm_lockstruct *ls, uint32_t lvb_gen,
 
 static int all_jid_bits_clear(char *lvb)
 {
-        int i;
-        for (i = JID_BITMAP_OFFSET; i < GDLM_LVB_SIZE; i++) {
-                if (lvb[i])
-                        return 0;
-        }
-        return 1;
+        return !memchr_inv(lvb + JID_BITMAP_OFFSET, 0,
+                        GDLM_LVB_SIZE - JID_BITMAP_OFFSET);
 }
 
 static void sync_wait_cb(void *arg)
@@ -580,7 +576,6 @@ static void gfs2_control_func(struct work_struct *work)
 {
         struct gfs2_sbd *sdp = container_of(work, struct gfs2_sbd, sd_control_work.work);
         struct lm_lockstruct *ls = &sdp->sd_lockstruct;
-        char lvb_bits[GDLM_LVB_SIZE];
         uint32_t block_gen, start_gen, lvb_gen, flags;
         int recover_set = 0;
         int write_lvb = 0;
@@ -634,7 +629,7 @@ static void gfs2_control_func(struct work_struct *work)
                 return;
         }
 
-        control_lvb_read(ls, &lvb_gen, lvb_bits);
+        control_lvb_read(ls, &lvb_gen, ls->ls_lvb_bits);
 
         spin_lock(&ls->ls_recover_spin);
         if (block_gen != ls->ls_recover_block ||
@@ -664,10 +659,10 @@ static void gfs2_control_func(struct work_struct *work)
 
                         ls->ls_recover_result[i] = 0;
 
-                        if (!test_bit_le(i, lvb_bits + JID_BITMAP_OFFSET))
+                        if (!test_bit_le(i, ls->ls_lvb_bits + JID_BITMAP_OFFSET))
                                 continue;
 
-                        __clear_bit_le(i, lvb_bits + JID_BITMAP_OFFSET);
+                        __clear_bit_le(i, ls->ls_lvb_bits + JID_BITMAP_OFFSET);
                         write_lvb = 1;
                 }
         }
@@ -691,7 +686,7 @@ static void gfs2_control_func(struct work_struct *work)
                                 continue;
                         if (ls->ls_recover_submit[i] < start_gen) {
                                 ls->ls_recover_submit[i] = 0;
-                                __set_bit_le(i, lvb_bits + JID_BITMAP_OFFSET);
+                                __set_bit_le(i, ls->ls_lvb_bits + JID_BITMAP_OFFSET);
                         }
                 }
                 /* even if there are no bits to set, we need to write the
@@ -705,7 +700,7 @@ static void gfs2_control_func(struct work_struct *work)
         spin_unlock(&ls->ls_recover_spin);
 
         if (write_lvb) {
-                control_lvb_write(ls, start_gen, lvb_bits);
+                control_lvb_write(ls, start_gen, ls->ls_lvb_bits);
                 flags = DLM_LKF_CONVERT | DLM_LKF_VALBLK;
         } else {
                 flags = DLM_LKF_CONVERT;
@@ -725,7 +720,7 @@ static void gfs2_control_func(struct work_struct *work)
          */
 
         for (i = 0; i < recover_size; i++) {
-                if (test_bit_le(i, lvb_bits + JID_BITMAP_OFFSET)) {
+                if (test_bit_le(i, ls->ls_lvb_bits + JID_BITMAP_OFFSET)) {
                         fs_info(sdp, "recover generation %u jid %d\n",
                                 start_gen, i);
                         gfs2_recover_set(sdp, i);
@@ -758,7 +753,6 @@ static void gfs2_control_func(struct work_struct *work)
 static int control_mount(struct gfs2_sbd *sdp)
 {
         struct lm_lockstruct *ls = &sdp->sd_lockstruct;
-        char lvb_bits[GDLM_LVB_SIZE];
         uint32_t start_gen, block_gen, mount_gen, lvb_gen;
         int mounted_mode;
         int retries = 0;
@@ -857,7 +851,7 @@ locks_done:
          * lvb_gen will be non-zero.
          */
 
-        control_lvb_read(ls, &lvb_gen, lvb_bits);
+        control_lvb_read(ls, &lvb_gen, ls->ls_lvb_bits);
 
         if (lvb_gen == 0xFFFFFFFF) {
                 /* special value to force mount attempts to fail */
@@ -887,7 +881,7 @@ locks_done:
          * and all lvb bits to be clear (no pending journal recoveries.)
          */
 
-        if (!all_jid_bits_clear(lvb_bits)) {
+        if (!all_jid_bits_clear(ls->ls_lvb_bits)) {
                 /* journals need recovery, wait until all are clear */
                 fs_info(sdp, "control_mount wait for journal recovery\n");
                 goto restart;
@@ -949,7 +943,6 @@ static int dlm_recovery_wait(void *word)
 static int control_first_done(struct gfs2_sbd *sdp)
 {
         struct lm_lockstruct *ls = &sdp->sd_lockstruct;
-        char lvb_bits[GDLM_LVB_SIZE];
         uint32_t start_gen, block_gen;
         int error;
 
@@ -991,8 +984,8 @@ restart:
         memset(ls->ls_recover_result, 0, ls->ls_recover_size*sizeof(uint32_t));
         spin_unlock(&ls->ls_recover_spin);
 
-        memset(lvb_bits, 0, sizeof(lvb_bits));
-        control_lvb_write(ls, start_gen, lvb_bits);
+        memset(ls->ls_lvb_bits, 0, GDLM_LVB_SIZE);
+        control_lvb_write(ls, start_gen, ls->ls_lvb_bits);
 
         error = mounted_lock(sdp, DLM_LOCK_PR, DLM_LKF_CONVERT);
         if (error)
@@ -1022,6 +1015,12 @@ static int set_recover_size(struct gfs2_sbd *sdp, struct dlm_slot *slots,
         uint32_t old_size, new_size;
         int i, max_jid;
 
+        if (!ls->ls_lvb_bits) {
+                ls->ls_lvb_bits = kzalloc(GDLM_LVB_SIZE, GFP_NOFS);
+                if (!ls->ls_lvb_bits)
+                        return -ENOMEM;
+        }
+
         max_jid = 0;
         for (i = 0; i < num_slots; i++) {
                 if (max_jid < slots[i].slot - 1)
@@ -1057,6 +1056,7 @@ static int set_recover_size(struct gfs2_sbd *sdp, struct dlm_slot *slots,
 
 static void free_recover_size(struct lm_lockstruct *ls)
 {
+        kfree(ls->ls_lvb_bits);
         kfree(ls->ls_recover_submit);
         kfree(ls->ls_recover_result);
         ls->ls_recover_submit = NULL;
@@ -1205,6 +1205,7 @@ static int gdlm_mount(struct gfs2_sbd *sdp, const char *table)
         ls->ls_recover_size = 0;
         ls->ls_recover_submit = NULL;
         ls->ls_recover_result = NULL;
+        ls->ls_lvb_bits = NULL;
 
         error = set_recover_size(sdp, NULL, 0);
         if (error)
diff --git a/fs/gfs2/rgrp.c b/fs/gfs2/rgrp.c
index d1f51fd73f86..5a51265a4341 100644
--- a/fs/gfs2/rgrp.c
+++ b/fs/gfs2/rgrp.c
@@ -576,7 +576,7 @@ int gfs2_rs_alloc(struct gfs2_inode *ip)
         RB_CLEAR_NODE(&ip->i_res->rs_node);
 out:
         up_write(&ip->i_rw_mutex);
-        return 0;
+        return error;
 }
 
 static void dump_rs(struct seq_file *seq, const struct gfs2_blkreserv *rs)
@@ -1181,12 +1181,9 @@ int gfs2_rgrp_send_discards(struct gfs2_sbd *sdp, u64 offset,
                              const struct gfs2_bitmap *bi, unsigned minlen, u64 *ptrimmed)
 {
         struct super_block *sb = sdp->sd_vfs;
-        struct block_device *bdev = sb->s_bdev;
-        const unsigned int sects_per_blk = sdp->sd_sb.sb_bsize /
-                                           bdev_logical_block_size(sb->s_bdev);
         u64 blk;
         sector_t start = 0;
-        sector_t nr_sects = 0;
+        sector_t nr_blks = 0;
         int rv;
         unsigned int x;
         u32 trimmed = 0;
@@ -1206,35 +1203,34 @@ int gfs2_rgrp_send_discards(struct gfs2_sbd *sdp, u64 offset,
                 if (diff == 0)
                         continue;
                 blk = offset + ((bi->bi_start + x) * GFS2_NBBY);
-                blk *= sects_per_blk; /* convert to sectors */
                 while(diff) {
                         if (diff & 1) {
-                                if (nr_sects == 0)
+                                if (nr_blks == 0)
                                         goto start_new_extent;
-                                if ((start + nr_sects) != blk) {
-                                        if (nr_sects >= minlen) {
-                                                rv = blkdev_issue_discard(bdev,
-                                                        start, nr_sects,
+                                if ((start + nr_blks) != blk) {
+                                        if (nr_blks >= minlen) {
+                                                rv = sb_issue_discard(sb,
+                                                        start, nr_blks,
                                                         GFP_NOFS, 0);
                                                 if (rv)
                                                         goto fail;
-                                                trimmed += nr_sects;
+                                                trimmed += nr_blks;
                                         }
-                                        nr_sects = 0;
+                                        nr_blks = 0;
 start_new_extent:
                                         start = blk;
                                 }
-                                nr_sects += sects_per_blk;
+                                nr_blks++;
                         }
                         diff >>= 2;
-                        blk += sects_per_blk;
+                        blk++;
                 }
         }
-        if (nr_sects >= minlen) {
-                rv = blkdev_issue_discard(bdev, start, nr_sects, GFP_NOFS, 0);
+        if (nr_blks >= minlen) {
+                rv = sb_issue_discard(sb, start, nr_blks, GFP_NOFS, 0);
                 if (rv)
                         goto fail;
-                trimmed += nr_sects;
+                trimmed += nr_blks;
         }
         if (ptrimmed)
                 *ptrimmed = trimmed;
diff --git a/fs/nfsd/nfs4xdr.c b/fs/nfsd/nfs4xdr.c
index 01168865dd37..a2720071f282 100644
--- a/fs/nfsd/nfs4xdr.c
+++ b/fs/nfsd/nfs4xdr.c
@@ -264,7 +264,7 @@ nfsd4_decode_fattr(struct nfsd4_compoundargs *argp, u32 *bmval,
                 iattr->ia_valid |= ATTR_SIZE;
         }
         if (bmval[0] & FATTR4_WORD0_ACL) {
-                int nace;
+                u32 nace;
                 struct nfs4_ace *ace;
 
                 READ_BUF(4); len += 4;
diff --git a/fs/reiserfs/xattr.c b/fs/reiserfs/xattr.c
index c196369fe408..4cce1d9552fb 100644
--- a/fs/reiserfs/xattr.c
+++ b/fs/reiserfs/xattr.c
@@ -187,8 +187,8 @@ fill_with_dentries(void *buf, const char *name, int namelen, loff_t offset,
         if (dbuf->count == ARRAY_SIZE(dbuf->dentries))
                 return -ENOSPC;
 
-        if (name[0] == '.' && (name[1] == '\0' ||
-                               (name[1] == '.' && name[2] == '\0')))
+        if (name[0] == '.' && (namelen < 2 ||
+                               (namelen == 2 && name[1] == '.')))
                 return 0;
 
         dentry = lookup_one_len(name, dbuf->xadir, namelen);
diff --git a/fs/ubifs/super.c b/fs/ubifs/super.c
index ac838b844936..f21acf0ef01f 100644
--- a/fs/ubifs/super.c
+++ b/fs/ubifs/super.c
@@ -1568,6 +1568,12 @@ static int ubifs_remount_rw(struct ubifs_info *c)
         c->remounting_rw = 1;
         c->ro_mount = 0;
 
+        if (c->space_fixup) {
+                err = ubifs_fixup_free_space(c);
+                if (err)
+                        return err;
+        }
+
         err = check_free_space(c);
         if (err)
                 goto out;
@@ -1684,12 +1690,6 @@ static int ubifs_remount_rw(struct ubifs_info *c)
                 err = dbg_check_space_info(c);
         }
 
-        if (c->space_fixup) {
-                err = ubifs_fixup_free_space(c);
-                if (err)
-                        goto out;
-        }
-
         mutex_unlock(&c->umount_mutex);
         return err;
 
diff --git a/include/clocksource/arm_arch_timer.h b/include/clocksource/arm_arch_timer.h
index 2603267b1a29..e6c9c4cc9b23 100644
--- a/include/clocksource/arm_arch_timer.h
+++ b/include/clocksource/arm_arch_timer.h
@@ -31,18 +31,12 @@
 
 #ifdef CONFIG_ARM_ARCH_TIMER
 
-extern int arch_timer_init(void);
 extern u32 arch_timer_get_rate(void);
 extern u64 (*arch_timer_read_counter)(void);
 extern struct timecounter *arch_timer_get_timecounter(void);
 
 #else
 
-static inline int arch_timer_init(void)
-{
-        return -ENXIO;
-}
-
 static inline u32 arch_timer_get_rate(void)
 {
         return 0;
diff --git a/include/linux/clk-private.h b/include/linux/clk-private.h
index 9c7f5807824b..dd7adff76e81 100644
--- a/include/linux/clk-private.h
+++ b/include/linux/clk-private.h
@@ -152,7 +152,7 @@ struct clk {
                 },                                              \
                 .reg = _reg,                                    \
                 .shift = _shift,                                \
-                .width = _width,                                \
+                .mask = BIT(_width) - 1,                        \
                 .flags = _mux_flags,                            \
                 .lock = _lock,                                  \
         };                                                      \
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 7f197d7addb0..1f0352802794 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -45,6 +45,14 @@ struct clk_hw;
  *              undo any work done in the @prepare callback. Called with
  *              prepare_lock held.
  *
+ * @is_prepared: Queries the hardware to determine if the clock is prepared.
+ *              This function is allowed to sleep. Optional, if this op is not
+ *              set then the prepare count will be used.
+ *
+ * @unprepare_unused: Unprepare the clock atomically.  Only called from
+ *              clk_disable_unused for prepare clocks with special needs.
+ *              Called with prepare mutex held. This function may sleep.
+ *
  * @enable:     Enable the clock atomically. This must not return until the
  *              clock is generating a valid clock signal, usable by consumer
  *              devices. Called with enable_lock held. This function must not
@@ -108,6 +116,8 @@ struct clk_hw;
 struct clk_ops {
         int             (*prepare)(struct clk_hw *hw);
         void            (*unprepare)(struct clk_hw *hw);
+        int             (*is_prepared)(struct clk_hw *hw);
+        void            (*unprepare_unused)(struct clk_hw *hw);
         int             (*enable)(struct clk_hw *hw);
         void            (*disable)(struct clk_hw *hw);
         int             (*is_enabled)(struct clk_hw *hw);
@@ -287,8 +297,9 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name,
 struct clk_mux {
         struct clk_hw   hw;
         void __iomem    *reg;
+        u32             *table;
+        u32             mask;
         u8              shift;
-        u8              width;
         u8              flags;
         spinlock_t      *lock;
 };
@@ -297,11 +308,17 @@ struct clk_mux {
 #define CLK_MUX_INDEX_BIT               BIT(1)
 
 extern const struct clk_ops clk_mux_ops;
+
 struct clk *clk_register_mux(struct device *dev, const char *name,
                 const char **parent_names, u8 num_parents, unsigned long flags,
                 void __iomem *reg, u8 shift, u8 width,
                 u8 clk_mux_flags, spinlock_t *lock);
 
+struct clk *clk_register_mux_table(struct device *dev, const char *name,
+                const char **parent_names, u8 num_parents, unsigned long flags,
+                void __iomem *reg, u8 shift, u32 mask,
+                u8 clk_mux_flags, u32 *table, spinlock_t *lock);
+
 /**
  * struct clk_fixed_factor - fixed multiplier and divider clock
  *
@@ -325,6 +342,37 @@ struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
                 const char *parent_name, unsigned long flags,
                 unsigned int mult, unsigned int div);
 
+/***
+ * struct clk_composite - aggregate clock of mux, divider and gate clocks
+ *
+ * @hw:         handle between common and hardware-specific interfaces
+ * @mux_hw:     handle between composite and hardware-specifix mux clock
+ * @div_hw:     handle between composite and hardware-specifix divider clock
+ * @gate_hw:    handle between composite and hardware-specifix gate clock
+ * @mux_ops:    clock ops for mux
+ * @div_ops:    clock ops for divider
+ * @gate_ops:   clock ops for gate
+ */
+struct clk_composite {
+        struct clk_hw   hw;
+        struct clk_ops  ops;
+
+        struct clk_hw   *mux_hw;
+        struct clk_hw   *div_hw;
+        struct clk_hw   *gate_hw;
+
+        const struct clk_ops    *mux_ops;
+        const struct clk_ops    *div_ops;
+        const struct clk_ops    *gate_ops;
+};
+
+struct clk *clk_register_composite(struct device *dev, const char *name,
+                const char **parent_names, int num_parents,
+                struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
+                struct clk_hw *div_hw, const struct clk_ops *div_ops,
+                struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
+                unsigned long flags);
+
 /**
  * clk_register - allocate a new clock, register it and return an opaque cookie
  * @dev: device that is registering this clock
@@ -351,6 +399,7 @@ unsigned int __clk_get_enable_count(struct clk *clk);
 unsigned int __clk_get_prepare_count(struct clk *clk);
 unsigned long __clk_get_rate(struct clk *clk);
 unsigned long __clk_get_flags(struct clk *clk);
+bool __clk_is_prepared(struct clk *clk);
 bool __clk_is_enabled(struct clk *clk);
 struct clk *__clk_lookup(const char *name);
 
diff --git a/include/linux/clk/sunxi.h b/include/linux/clk/sunxi.h
new file mode 100644
index 000000000000..e074fdd5a236
--- /dev/null
+++ b/include/linux/clk/sunxi.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __LINUX_CLK_SUNXI_H_
+#define __LINUX_CLK_SUNXI_H_
+
+void __init sunxi_init_clocks(void);
+
+#endif
diff --git a/include/linux/clk/tegra.h b/include/linux/clk/tegra.h
index 404d6f940872..642789baec74 100644
--- a/include/linux/clk/tegra.h
+++ b/include/linux/clk/tegra.h
@@ -123,5 +123,6 @@ static inline void tegra_cpu_clock_resume(void)
 void tegra_periph_reset_deassert(struct clk *c);
 void tegra_periph_reset_assert(struct clk *c);
 void tegra_clocks_init(void);
+void tegra_clocks_apply_init_table(void);
 
 #endif /* __LINUX_CLK_TEGRA_H_ */
diff --git a/include/linux/compat.h b/include/linux/compat.h
index 76a87fb57ac2..377cd8c3395e 100644
--- a/include/linux/compat.h
+++ b/include/linux/compat.h
@@ -141,11 +141,11 @@ typedef struct {
 } compat_sigset_t;
 
 struct compat_sigaction {
-#ifndef __ARCH_HAS_ODD_SIGACTION
+#ifndef __ARCH_HAS_IRIX_SIGACTION
         compat_uptr_t                   sa_handler;
         compat_ulong_t                  sa_flags;
 #else
-        compat_ulong_t                  sa_flags;
+        compat_uint_t                   sa_flags;
         compat_uptr_t                   sa_handler;
 #endif
 #ifdef __ARCH_HAS_SA_RESTORER
diff --git a/include/linux/devfreq.h b/include/linux/devfreq.h
index e83ef39b3bea..fe8c4476f7e4 100644
--- a/include/linux/devfreq.h
+++ b/include/linux/devfreq.h
@@ -213,7 +213,7 @@ struct devfreq_simple_ondemand_data {
 #endif
 
 #else /* !CONFIG_PM_DEVFREQ */
-static struct devfreq *devfreq_add_device(struct device *dev,
+static inline struct devfreq *devfreq_add_device(struct device *dev,
                                           struct devfreq_dev_profile *profile,
                                           const char *governor_name,
                                           void *data)
@@ -221,34 +221,34 @@ static struct devfreq *devfreq_add_device(struct device *dev,
         return NULL;
 }
 
-static int devfreq_remove_device(struct devfreq *devfreq)
+static inline int devfreq_remove_device(struct devfreq *devfreq)
 {
         return 0;
 }
 
-static int devfreq_suspend_device(struct devfreq *devfreq)
+static inline int devfreq_suspend_device(struct devfreq *devfreq)
 {
         return 0;
 }
 
-static int devfreq_resume_device(struct devfreq *devfreq)
+static inline int devfreq_resume_device(struct devfreq *devfreq)
 {
         return 0;
 }
 
-static struct opp *devfreq_recommended_opp(struct device *dev,
+static inline struct opp *devfreq_recommended_opp(struct device *dev,
                                            unsigned long *freq, u32 flags)
 {
-        return -EINVAL;
+        return ERR_PTR(-EINVAL);
 }
 
-static int devfreq_register_opp_notifier(struct device *dev,
+static inline int devfreq_register_opp_notifier(struct device *dev,
                                          struct devfreq *devfreq)
 {
         return -EINVAL;
 }
 
-static int devfreq_unregister_opp_notifier(struct device *dev,
+static inline int devfreq_unregister_opp_notifier(struct device *dev,
                                            struct devfreq *devfreq)
 {
         return -EINVAL;
diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h
index cad77fe09d77..c13958251927 100644
--- a/include/linux/kvm_host.h
+++ b/include/linux/kvm_host.h
@@ -518,7 +518,7 @@ int kvm_write_guest(struct kvm *kvm, gpa_t gpa, const void *data,
 int kvm_write_guest_cached(struct kvm *kvm, struct gfn_to_hva_cache *ghc,
                            void *data, unsigned long len);
 int kvm_gfn_to_hva_cache_init(struct kvm *kvm, struct gfn_to_hva_cache *ghc,
-                              gpa_t gpa);
+                              gpa_t gpa, unsigned long len);
 int kvm_clear_guest_page(struct kvm *kvm, gfn_t gfn, int offset, int len);
 int kvm_clear_guest(struct kvm *kvm, gpa_t gpa, unsigned long len);
 struct kvm_memory_slot *gfn_to_memslot(struct kvm *kvm, gfn_t gfn);
diff --git a/include/linux/kvm_types.h b/include/linux/kvm_types.h
index fa7cc7244cbd..b0bcce0ddc95 100644
--- a/include/linux/kvm_types.h
+++ b/include/linux/kvm_types.h
@@ -71,6 +71,7 @@ struct gfn_to_hva_cache {
         u64 generation;
         gpa_t gpa;
         unsigned long hva;
+        unsigned long len;
         struct kvm_memory_slot *memslot;
 };
 
diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h
index b3d00fa4b314..6151e903eef0 100644
--- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h
@@ -210,9 +210,9 @@ struct netdev_hw_addr {
 #define NETDEV_HW_ADDR_T_SLAVE          3
 #define NETDEV_HW_ADDR_T_UNICAST        4
 #define NETDEV_HW_ADDR_T_MULTICAST      5
-        bool                    synced;
         bool                    global_use;
         int                     refcount;
+        int                     synced;
         struct rcu_head         rcu_head;
 };
 
@@ -895,7 +895,7 @@ struct netdev_fcoe_hbainfo {
  *
  * int (*ndo_bridge_setlink)(struct net_device *dev, struct nlmsghdr *nlh)
  * int (*ndo_bridge_getlink)(struct sk_buff *skb, u32 pid, u32 seq,
- *                           struct net_device *dev)
+ *                           struct net_device *dev, u32 filter_mask)
  *
  * int (*ndo_change_carrier)(struct net_device *dev, bool new_carrier);
  *      Called to change device carrier. Soft-devices (like dummy, team, etc)
diff --git a/include/linux/of.h b/include/linux/of.h
index c0747a44eaff..b0f3bbd0216b 100644
--- a/include/linux/of.h
+++ b/include/linux/of.h
@@ -382,6 +382,11 @@ static inline int of_device_is_compatible(const struct device_node *device,
         return 0;
 }
 
+static inline int of_device_is_available(const struct device_node *device)
+{
+        return 0;
+}
+
 static inline struct property *of_find_property(const struct device_node *np,
                                                 const char *name,
                                                 int *lenp)
diff --git a/include/linux/pata_arasan_cf_data.h b/include/linux/pata_arasan_cf_data.h
index a7b4fc386e63..3cc21c9cc1e8 100644
--- a/include/linux/pata_arasan_cf_data.h
+++ b/include/linux/pata_arasan_cf_data.h
@@ -37,8 +37,6 @@ struct arasan_cf_pdata {
         #define CF_BROKEN_PIO                   (1)
         #define CF_BROKEN_MWDMA                 (1 << 1)
         #define CF_BROKEN_UDMA                  (1 << 2)
-        /* This is platform specific data for the DMA controller */
-        void *dma_priv;
 };
 
 static inline void
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 2461033a7987..710067f3618c 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -916,6 +916,7 @@ void pci_disable_rom(struct pci_dev *pdev);
 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
+void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
 
 /* Power management related routines */
 int pci_save_state(struct pci_dev *dev);
diff --git a/include/linux/signal.h b/include/linux/signal.h
index a2dcb94ea49d..9475c5cb28bc 100644
--- a/include/linux/signal.h
+++ b/include/linux/signal.h
@@ -250,11 +250,11 @@ extern int show_unhandled_signals;
 extern int sigsuspend(sigset_t *);
 
 struct sigaction {
-#ifndef __ARCH_HAS_ODD_SIGACTION
+#ifndef __ARCH_HAS_IRIX_SIGACTION
         __sighandler_t  sa_handler;
         unsigned long   sa_flags;
 #else
-        unsigned long   sa_flags;
+        unsigned int    sa_flags;
         __sighandler_t  sa_handler;
 #endif
 #ifdef __ARCH_HAS_SA_RESTORER
diff --git a/include/linux/skbuff.h b/include/linux/skbuff.h
index 441f5bfdab8e..b8292d8cc9fa 100644
--- a/include/linux/skbuff.h
+++ b/include/linux/skbuff.h
@@ -2643,6 +2643,13 @@ static inline void nf_reset(struct sk_buff *skb)
 #endif
 }
 
+static inline void nf_reset_trace(struct sk_buff *skb)
+{
+#if IS_ENABLED(CONFIG_NETFILTER_XT_TARGET_TRACE)
+        skb->nf_trace = 0;
+#endif
+}
+
 /* Note: This doesn't put any conntrack and bridge info in dst. */
 static inline void __nf_copy(struct sk_buff *dst, const struct sk_buff *src)
 {
diff --git a/include/scsi/libfc.h b/include/scsi/libfc.h
index 399162b50a8d..e1379b4e8faf 100644
--- a/include/scsi/libfc.h
+++ b/include/scsi/libfc.h
@@ -1074,7 +1074,8 @@ void fc_rport_terminate_io(struct fc_rport *);
 /*
  * DISCOVERY LAYER
  *****************************/
-int fc_disc_init(struct fc_lport *);
+void fc_disc_init(struct fc_lport *);
+void fc_disc_config(struct fc_lport *, void *);
 
 static inline struct fc_lport *fc_disc_lport(struct fc_disc *disc)
 {
diff --git a/include/sound/max98090.h b/include/sound/max98090.h
index 95efb13f8478..95efb13f8478 100755..100644
--- a/include/sound/max98090.h
+++ b/include/sound/max98090.h
diff --git a/include/sound/soc-dapm.h b/include/sound/soc-dapm.h
index e1ef63d4a5c4..44a30b108683 100644
--- a/include/sound/soc-dapm.h
+++ b/include/sound/soc-dapm.h
@@ -488,6 +488,7 @@ struct snd_soc_dapm_path {
         /* status */
         u32 connect:1;  /* source and sink widgets are connected */
         u32 walked:1;   /* path has been walked */
+        u32 walking:1;  /* path is in the process of being walked */
         u32 weak:1;     /* path ignored for power management */
 
         int (*connected)(struct snd_soc_dapm_widget *source,
diff --git a/include/video/omap-panel-data.h b/include/video/omap-panel-data.h
new file mode 100644
index 000000000000..6b55839b73fc
--- /dev/null
+++ b/include/video/omap-panel-data.h
@@ -0,0 +1,152 @@
+/*
+ * Header containing platform_data structs for omap panels
+ *
+ * Copyright (C) 2013 Texas Instruments
+ * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
+ *         Archit Taneja <archit@ti.com>
+ *
+ * Copyright (C) 2011 Texas Instruments
+ * Author: Mayuresh Janorkar <mayur@ti.com>
+ *
+ * Copyright (C) 2010 Canonical Ltd.
+ * Author: Bryan Wu <bryan.wu@canonical.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __OMAP_PANEL_DATA_H
+#define __OMAP_PANEL_DATA_H
+
+struct omap_dss_device;
+
+/**
+ * struct panel_generic_dpi_data - panel driver configuration data
+ * @name: panel name
+ * @platform_enable: platform specific panel enable function
+ * @platform_disable: platform specific panel disable function
+ * @num_gpios: number of gpios connected to panel
+ * @gpios: gpio numbers on the platform
+ * @gpio_invert: configure gpio as active high or low
+ */
+struct panel_generic_dpi_data {
+        const char *name;
+        int (*platform_enable)(struct omap_dss_device *dssdev);
+        void (*platform_disable)(struct omap_dss_device *dssdev);
+
+        int num_gpios;
+        int gpios[10];
+        bool gpio_invert[10];
+};
+
+/**
+ * struct panel_n8x0_data - N800 panel driver configuration data
+ */
+struct panel_n8x0_data {
+        int (*platform_enable)(struct omap_dss_device *dssdev);
+        void (*platform_disable)(struct omap_dss_device *dssdev);
+        int panel_reset;
+        int ctrl_pwrdown;
+
+        int (*set_backlight)(struct omap_dss_device *dssdev, int level);
+};
+
+/**
+ * struct nokia_dsi_panel_data - Nokia DSI panel driver configuration data
+ * @name: panel name
+ * @use_ext_te: use external TE
+ * @ext_te_gpio: external TE GPIO
+ * @esd_interval: interval of ESD checks, 0 = disabled (ms)
+ * @ulps_timeout: time to wait before entering ULPS, 0 = disabled (ms)
+ * @use_dsi_backlight: true if panel uses DSI command to control backlight
+ * @pin_config: DSI pin configuration
+ */
+
+struct nokia_dsi_panel_data {
+        const char *name;
+
+        int reset_gpio;
+
+        bool use_ext_te;
+        int ext_te_gpio;
+
+        unsigned esd_interval;
+        unsigned ulps_timeout;
+
+        bool use_dsi_backlight;
+
+        struct omap_dsi_pin_config pin_config;
+};
+
+/**
+ * struct picodlp_panel_data - picodlp panel driver configuration data
+ * @picodlp_adapter_id: i2c_adapter number for picodlp
+ */
+struct picodlp_panel_data {
+        int picodlp_adapter_id;
+        int emu_done_gpio;
+        int pwrgood_gpio;
+};
+
+/**
+ * struct tfp410_platform_data - tfp410 panel driver configuration data
+ * @i2c_bus_num: i2c bus id for the panel
+ * @power_down_gpio: gpio number for PD pin (or -1 if not available)
+ */
+struct tfp410_platform_data {
+        int i2c_bus_num;
+        int power_down_gpio;
+};
+
+/**
+ * sharp ls panel driver configuration data
+ * @resb_gpio: reset signal
+ * @ini_gpio: power on control
+ * @mo_gpio: selection for resolution(VGA/QVGA)
+ * @lr_gpio: selection for horizontal scanning direction
+ * @ud_gpio: selection for vertical scanning direction
+ */
+struct panel_sharp_ls037v7dw01_data {
+        int resb_gpio;
+        int ini_gpio;
+        int mo_gpio;
+        int lr_gpio;
+        int ud_gpio;
+};
+
+/**
+ * acx565akm panel driver configuration data
+ * @reset_gpio: reset signal
+ */
+struct panel_acx565akm_data {
+        int reset_gpio;
+};
+
+/**
+ * nec nl8048 panel driver configuration data
+ * @res_gpio: reset signal
+ * @qvga_gpio: selection for resolution(QVGA/WVGA)
+ */
+struct panel_nec_nl8048_data {
+        int res_gpio;
+        int qvga_gpio;
+};
+
+/**
+ * tpo td043 panel driver configuration data
+ * @nreset_gpio: reset signal
+ */
+struct panel_tpo_td043_data {
+        int nreset_gpio;
+};
+
+#endif /* __OMAP_PANEL_DATA_H */
diff --git a/include/video/omap-panel-generic-dpi.h b/include/video/omap-panel-generic-dpi.h
deleted file mode 100644
index 127e3f20328e..000000000000
--- a/include/video/omap-panel-generic-dpi.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Header for generic DPI panel driver
- *
- * Copyright (C) 2010 Canonical Ltd.
- * Author: Bryan Wu <bryan.wu@canonical.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef __OMAP_PANEL_GENERIC_DPI_H
-#define __OMAP_PANEL_GENERIC_DPI_H
-
-struct omap_dss_device;
-
-/**
- * struct panel_generic_dpi_data - panel driver configuration data
- * @name: panel name
- * @platform_enable: platform specific panel enable function
- * @platform_disable: platform specific panel disable function
- */
-struct panel_generic_dpi_data {
-        const char *name;
-        int (*platform_enable)(struct omap_dss_device *dssdev);
-        void (*platform_disable)(struct omap_dss_device *dssdev);
-};
-
-#endif /* __OMAP_PANEL_GENERIC_DPI_H */
diff --git a/include/video/omap-panel-n8x0.h b/include/video/omap-panel-n8x0.h
deleted file mode 100644
index 50a1302e2cfd..000000000000
--- a/include/video/omap-panel-n8x0.h
+++ /dev/null
@@ -1,15 +0,0 @@
-#ifndef __OMAP_PANEL_N8X0_H
-#define __OMAP_PANEL_N8X0_H
-
-struct omap_dss_device;
-
-struct panel_n8x0_data {
-        int (*platform_enable)(struct omap_dss_device *dssdev);
-        void (*platform_disable)(struct omap_dss_device *dssdev);
-        int panel_reset;
-        int ctrl_pwrdown;
-
-        int (*set_backlight)(struct omap_dss_device *dssdev, int level);
-};
-
-#endif
diff --git a/include/video/omap-panel-nokia-dsi.h b/include/video/omap-panel-nokia-dsi.h
deleted file mode 100644
index 04219a295539..000000000000
--- a/include/video/omap-panel-nokia-dsi.h
+++ /dev/null
@@ -1,32 +0,0 @@
-#ifndef __OMAP_NOKIA_DSI_PANEL_H
-#define __OMAP_NOKIA_DSI_PANEL_H
-
-struct omap_dss_device;
-
-/**
- * struct nokia_dsi_panel_data - Nokia DSI panel driver configuration
- * @name: panel name
- * @use_ext_te: use external TE
- * @ext_te_gpio: external TE GPIO
- * @esd_interval: interval of ESD checks, 0 = disabled (ms)
- * @ulps_timeout: time to wait before entering ULPS, 0 = disabled (ms)
- * @use_dsi_backlight: true if panel uses DSI command to control backlight
- * @pin_config: DSI pin configuration
- */
-struct nokia_dsi_panel_data {
-        const char *name;
-
-        int reset_gpio;
-
-        bool use_ext_te;
-        int ext_te_gpio;
-
-        unsigned esd_interval;
-        unsigned ulps_timeout;
-
-        bool use_dsi_backlight;
-
-        struct omap_dsi_pin_config pin_config;
-};
-
-#endif /* __OMAP_NOKIA_DSI_PANEL_H */
diff --git a/include/video/omap-panel-picodlp.h b/include/video/omap-panel-picodlp.h
deleted file mode 100644
index 1c342ef6f3a1..000000000000
--- a/include/video/omap-panel-picodlp.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * panel data for picodlp panel
- *
- * Copyright (C) 2011 Texas Instruments
- *
- * Author: Mayuresh Janorkar <mayur@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __PANEL_PICODLP_H
-#define __PANEL_PICODLP_H
-/**
- * struct : picodlp panel data
- * picodlp_adapter_id:  i2c_adapter number for picodlp
- */
-struct picodlp_panel_data {
-        int picodlp_adapter_id;
-        int emu_done_gpio;
-        int pwrgood_gpio;
-};
-#endif /* __PANEL_PICODLP_H */
diff --git a/include/video/omap-panel-tfp410.h b/include/video/omap-panel-tfp410.h
deleted file mode 100644
index aef35e48bc7e..000000000000
--- a/include/video/omap-panel-tfp410.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Header for TFP410 chip driver
- *
- * Copyright (C) 2011 Texas Instruments Inc
- * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef __OMAP_PANEL_TFP410_H
-#define __OMAP_PANEL_TFP410_H
-
-struct omap_dss_device;
-
-/**
- * struct tfp410_platform_data - panel driver configuration data
- * @i2c_bus_num: i2c bus id for the panel
- * @power_down_gpio: gpio number for PD pin (or -1 if not available)
- */
-struct tfp410_platform_data {
-        int i2c_bus_num;
-        int power_down_gpio;
-};
-
-#endif /* __OMAP_PANEL_TFP410_H */
diff --git a/ipc/msg.c b/ipc/msg.c
index 31cd1bf6af27..fede1d06ef30 100644
--- a/ipc/msg.c
+++ b/ipc/msg.c
@@ -872,6 +872,7 @@ long do_msgrcv(int msqid, void __user *buf, size_t bufsz, long msgtyp,
                                                         goto out_unlock;
                                                 break;
                                         }
+                                        msg = ERR_PTR(-EAGAIN);
                                 } else
                                         break;
                                 msg_counter++;
diff --git a/mm/mmap.c b/mm/mmap.c
index 6466699b16cb..0db0de1c2fbe 100644
--- a/mm/mmap.c
+++ b/mm/mmap.c
@@ -1940,7 +1940,7 @@ struct vm_area_struct *find_vma(struct mm_struct *mm, unsigned long addr)
 
         /* Check the cache first. */
         /* (Cache hit rate is typically around 35%.) */
-        vma = mm->mmap_cache;
+        vma = ACCESS_ONCE(mm->mmap_cache);
         if (!(vma && vma->vm_end > addr && vma->vm_start <= addr)) {
                 struct rb_node *rb_node;
 
diff --git a/mm/nommu.c b/mm/nommu.c
index e19328087534..2f3ea749c318 100644
--- a/mm/nommu.c
+++ b/mm/nommu.c
@@ -821,7 +821,7 @@ struct vm_area_struct *find_vma(struct mm_struct *mm, unsigned long addr)
         struct vm_area_struct *vma;
 
         /* check the cache first */
-        vma = mm->mmap_cache;
+        vma = ACCESS_ONCE(mm->mmap_cache);
         if (vma && vma->vm_start <= addr && vma->vm_end > addr)
                 return vma;
 
diff --git a/net/core/dev.c b/net/core/dev.c
index b13e5c766c11..e7d68ed8aafe 100644
--- a/net/core/dev.c
+++ b/net/core/dev.c
@@ -1624,7 +1624,6 @@ int dev_forward_skb(struct net_device *dev, struct sk_buff *skb)
         }
 
         skb_orphan(skb);
-        nf_reset(skb);
 
         if (unlikely(!is_skb_forwardable(dev, skb))) {
                 atomic_long_inc(&dev->rx_dropped);
@@ -1640,6 +1639,7 @@ int dev_forward_skb(struct net_device *dev, struct sk_buff *skb)
         skb->mark = 0;
         secpath_reset(skb);
         nf_reset(skb);
+        nf_reset_trace(skb);
         return netif_rx(skb);
 }
 EXPORT_SYMBOL_GPL(dev_forward_skb);
@@ -3314,6 +3314,7 @@ int netdev_rx_handler_register(struct net_device *dev,
         if (dev->rx_handler)
                 return -EBUSY;
 
+        /* Note: rx_handler_data must be set before rx_handler */
         rcu_assign_pointer(dev->rx_handler_data, rx_handler_data);
         rcu_assign_pointer(dev->rx_handler, rx_handler);
 
@@ -3334,6 +3335,11 @@ void netdev_rx_handler_unregister(struct net_device *dev)
 
         ASSERT_RTNL();
         RCU_INIT_POINTER(dev->rx_handler, NULL);
+        /* a reader seeing a non NULL rx_handler in a rcu_read_lock()
+         * section has a guarantee to see a non NULL rx_handler_data
+         * as well.
+         */
+        synchronize_net();
         RCU_INIT_POINTER(dev->rx_handler_data, NULL);
 }
 EXPORT_SYMBOL_GPL(netdev_rx_handler_unregister);
diff --git a/net/core/dev_addr_lists.c b/net/core/dev_addr_lists.c
index bd2eb9d3e369..abdc9e6ef33e 100644
--- a/net/core/dev_addr_lists.c
+++ b/net/core/dev_addr_lists.c
@@ -37,7 +37,7 @@ static int __hw_addr_create_ex(struct netdev_hw_addr_list *list,
         ha->type = addr_type;
         ha->refcount = 1;
         ha->global_use = global;
-        ha->synced = false;
+        ha->synced = 0;
         list_add_tail_rcu(&ha->list, &list->list);
         list->count++;
 
@@ -165,7 +165,7 @@ int __hw_addr_sync(struct netdev_hw_addr_list *to_list,
                                             addr_len, ha->type);
                         if (err)
                                 break;
-                        ha->synced = true;
+                        ha->synced++;
                         ha->refcount++;
                 } else if (ha->refcount == 1) {
                         __hw_addr_del(to_list, ha->addr, addr_len, ha->type);
@@ -186,7 +186,7 @@ void __hw_addr_unsync(struct netdev_hw_addr_list *to_list,
                 if (ha->synced) {
                         __hw_addr_del(to_list, ha->addr,
                                       addr_len, ha->type);
-                        ha->synced = false;
+                        ha->synced--;
                         __hw_addr_del(from_list, ha->addr,
                                       addr_len, ha->type);
                 }
diff --git a/net/core/flow.c b/net/core/flow.c
index c56ea6f7f6c7..2bfd081c59f7 100644
--- a/net/core/flow.c
+++ b/net/core/flow.c
@@ -328,7 +328,7 @@ static void flow_cache_flush_per_cpu(void *data)
         struct flow_flush_info *info = data;
         struct tasklet_struct *tasklet;
 
-        tasklet = this_cpu_ptr(&info->cache->percpu->flush_tasklet);
+        tasklet = &this_cpu_ptr(info->cache->percpu)->flush_tasklet;
         tasklet->data = (unsigned long)info;
         tasklet_schedule(tasklet);
 }
diff --git a/net/core/rtnetlink.c b/net/core/rtnetlink.c
index 5fb8d7e47294..b65441da74ab 100644
--- a/net/core/rtnetlink.c
+++ b/net/core/rtnetlink.c
@@ -496,8 +496,10 @@ static int rtnl_link_fill(struct sk_buff *skb, const struct net_device *dev)
         }
         if (ops->fill_info) {
                 data = nla_nest_start(skb, IFLA_INFO_DATA);
-                if (data == NULL)
+                if (data == NULL) {
+                        err = -EMSGSIZE;
                         goto err_cancel_link;
+                }
                 err = ops->fill_info(skb, dev);
                 if (err < 0)
                         goto err_cancel_data;
diff --git a/net/ipv4/devinet.c b/net/ipv4/devinet.c
index f678507bc829..96083b7a436b 100644
--- a/net/ipv4/devinet.c
+++ b/net/ipv4/devinet.c
@@ -802,8 +802,10 @@ static int inet_rtm_newaddr(struct sk_buff *skb, struct nlmsghdr *nlh, void *arg
                 if (nlh->nlmsg_flags & NLM_F_EXCL ||
                     !(nlh->nlmsg_flags & NLM_F_REPLACE))
                         return -EEXIST;
-
-                set_ifa_lifetime(ifa_existing, valid_lft, prefered_lft);
+                ifa = ifa_existing;
+                set_ifa_lifetime(ifa, valid_lft, prefered_lft);
+                rtmsg_ifa(RTM_NEWADDR, ifa, nlh, NETLINK_CB(skb).portid);
+                blocking_notifier_call_chain(&inetaddr_chain, NETDEV_UP, ifa);
         }
         return 0;
 }
diff --git a/net/ipv6/addrconf.c b/net/ipv6/addrconf.c
index 26512250e095..a459c4f5b769 100644
--- a/net/ipv6/addrconf.c
+++ b/net/ipv6/addrconf.c
@@ -2529,6 +2529,9 @@ static void sit_add_v4_addrs(struct inet6_dev *idev)
 static void init_loopback(struct net_device *dev)
 {
         struct inet6_dev  *idev;
+        struct net_device *sp_dev;
+        struct inet6_ifaddr *sp_ifa;
+        struct rt6_info *sp_rt;
 
         /* ::1 */
 
@@ -2540,6 +2543,30 @@ static void init_loopback(struct net_device *dev)
         }
 
         add_addr(idev, &in6addr_loopback, 128, IFA_HOST);
+
+        /* Add routes to other interface's IPv6 addresses */
+        for_each_netdev(dev_net(dev), sp_dev) {
+                if (!strcmp(sp_dev->name, dev->name))
+                        continue;
+
+                idev = __in6_dev_get(sp_dev);
+                if (!idev)
+                        continue;
+
+                read_lock_bh(&idev->lock);
+                list_for_each_entry(sp_ifa, &idev->addr_list, if_list) {
+
+                        if (sp_ifa->flags & (IFA_F_DADFAILED | IFA_F_TENTATIVE))
+                                continue;
+
+                        sp_rt = addrconf_dst_alloc(idev, &sp_ifa->addr, 0);
+
+                        /* Failure cases are ignored */
+                        if (!IS_ERR(sp_rt))
+                                ip6_ins_rt(sp_rt);
+                }
+                read_unlock_bh(&idev->lock);
+        }
 }
 
 static void addrconf_add_linklocal(struct inet6_dev *idev, const struct in6_addr *addr)
diff --git a/net/ipv6/ip6_input.c b/net/ipv6/ip6_input.c
index e33fe0ab2568..2bab2aa59745 100644
--- a/net/ipv6/ip6_input.c
+++ b/net/ipv6/ip6_input.c
@@ -118,6 +118,18 @@ int ipv6_rcv(struct sk_buff *skb, struct net_device *dev, struct packet_type *pt
             ipv6_addr_loopback(&hdr->daddr))
                 goto err;
 
+        /* RFC4291 Errata ID: 3480
+         * Interface-Local scope spans only a single interface on a
+         * node and is useful only for loopback transmission of
+         * multicast.  Packets with interface-local scope received
+         * from another node must be discarded.
+         */
+        if (!(skb->pkt_type == PACKET_LOOPBACK ||
+              dev->flags & IFF_LOOPBACK) &&
+            ipv6_addr_is_multicast(&hdr->daddr) &&
+            IPV6_ADDR_MC_SCOPE(&hdr->daddr) == 1)
+                goto err;
+
         /* RFC4291 2.7
          * Nodes must not originate a packet to a multicast address whose scope
          * field contains the reserved value 0; if such a packet is received, it
diff --git a/net/ipv6/netfilter/ip6t_NPT.c b/net/ipv6/netfilter/ip6t_NPT.c
index 33608c610276..cb631143721c 100644
--- a/net/ipv6/netfilter/ip6t_NPT.c
+++ b/net/ipv6/netfilter/ip6t_NPT.c
@@ -57,7 +57,7 @@ static bool ip6t_npt_map_pfx(const struct ip6t_npt_tginfo *npt,
                 if (pfx_len - i >= 32)
                         mask = 0;
                 else
-                        mask = htonl(~((1 << (pfx_len - i)) - 1));
+                        mask = htonl((1 << (i - pfx_len + 32)) - 1);
 
                 idx = i / 32;
                 addr->s6_addr32[idx] &= mask;
diff --git a/net/key/af_key.c b/net/key/af_key.c
index 8555f331ea60..5b1e5af25713 100644
--- a/net/key/af_key.c
+++ b/net/key/af_key.c
@@ -2693,6 +2693,7 @@ static int key_notify_policy_flush(const struct km_event *c)
         hdr->sadb_msg_pid = c->portid;
         hdr->sadb_msg_version = PF_KEY_V2;
         hdr->sadb_msg_errno = (uint8_t) 0;
+        hdr->sadb_msg_satype = SADB_SATYPE_UNSPEC;
         hdr->sadb_msg_len = (sizeof(struct sadb_msg) / sizeof(uint64_t));
         pfkey_broadcast(skb_out, GFP_ATOMIC, BROADCAST_ALL, NULL, c->net);
         return 0;
diff --git a/net/mac80211/cfg.c b/net/mac80211/cfg.c
index fb306814576a..a6893602f87a 100644
--- a/net/mac80211/cfg.c
+++ b/net/mac80211/cfg.c
@@ -2582,7 +2582,7 @@ static int ieee80211_cancel_roc(struct ieee80211_local *local,
                         list_del(&dep->list);
                         mutex_unlock(&local->mtx);
 
-                        ieee80211_roc_notify_destroy(dep);
+                        ieee80211_roc_notify_destroy(dep, true);
                         return 0;
                 }
 
@@ -2622,7 +2622,7 @@ static int ieee80211_cancel_roc(struct ieee80211_local *local,
                         ieee80211_start_next_roc(local);
                 mutex_unlock(&local->mtx);
 
-                ieee80211_roc_notify_destroy(found);
+                ieee80211_roc_notify_destroy(found, true);
         } else {
                 /* work may be pending so use it all the time */
                 found->abort = true;
@@ -2632,6 +2632,8 @@ static int ieee80211_cancel_roc(struct ieee80211_local *local,
 
                 /* work will clean up etc */
                 flush_delayed_work(&found->work);
+                WARN_ON(!found->to_be_freed);
+                kfree(found);
         }
 
         return 0;
diff --git a/net/mac80211/chan.c b/net/mac80211/chan.c
index 78c0d90dd641..931be419ab5a 100644
--- a/net/mac80211/chan.c
+++ b/net/mac80211/chan.c
@@ -63,6 +63,7 @@ ieee80211_new_chanctx(struct ieee80211_local *local,
                       enum ieee80211_chanctx_mode mode)
 {
         struct ieee80211_chanctx *ctx;
+        u32 changed;
         int err;
 
         lockdep_assert_held(&local->chanctx_mtx);
@@ -76,6 +77,13 @@ ieee80211_new_chanctx(struct ieee80211_local *local,
         ctx->conf.rx_chains_dynamic = 1;
         ctx->mode = mode;
 
+        /* acquire mutex to prevent idle from changing */
+        mutex_lock(&local->mtx);
+        /* turn idle off *before* setting channel -- some drivers need that */
+        changed = ieee80211_idle_off(local);
+        if (changed)
+                ieee80211_hw_config(local, changed);
+
         if (!local->use_chanctx) {
                 local->_oper_channel_type =
                         cfg80211_get_chandef_type(chandef);
@@ -85,14 +93,17 @@ ieee80211_new_chanctx(struct ieee80211_local *local,
                 err = drv_add_chanctx(local, ctx);
                 if (err) {
                         kfree(ctx);
-                        return ERR_PTR(err);
+                        ctx = ERR_PTR(err);
+
+                        ieee80211_recalc_idle(local);
+                        goto out;
                 }
         }
 
+        /* and keep the mutex held until the new chanctx is on the list */
         list_add_rcu(&ctx->list, &local->chanctx_list);
 
-        mutex_lock(&local->mtx);
-        ieee80211_recalc_idle(local);
+ out:
         mutex_unlock(&local->mtx);
 
         return ctx;
diff --git a/net/mac80211/ieee80211_i.h b/net/mac80211/ieee80211_i.h
index 388580a1bada..5672533a0832 100644
--- a/net/mac80211/ieee80211_i.h
+++ b/net/mac80211/ieee80211_i.h
@@ -309,6 +309,7 @@ struct ieee80211_roc_work {
         struct ieee80211_channel *chan;
 
         bool started, abort, hw_begun, notified;
+        bool to_be_freed;
 
         unsigned long hw_start_time;
 
@@ -1347,7 +1348,7 @@ void ieee80211_offchannel_return(struct ieee80211_local *local);
 void ieee80211_roc_setup(struct ieee80211_local *local);
 void ieee80211_start_next_roc(struct ieee80211_local *local);
 void ieee80211_roc_purge(struct ieee80211_sub_if_data *sdata);
-void ieee80211_roc_notify_destroy(struct ieee80211_roc_work *roc);
+void ieee80211_roc_notify_destroy(struct ieee80211_roc_work *roc, bool free);
 void ieee80211_sw_roc_work(struct work_struct *work);
 void ieee80211_handle_roc_started(struct ieee80211_roc_work *roc);
 
@@ -1361,6 +1362,7 @@ int ieee80211_if_change_type(struct ieee80211_sub_if_data *sdata,
                              enum nl80211_iftype type);
 void ieee80211_if_remove(struct ieee80211_sub_if_data *sdata);
 void ieee80211_remove_interfaces(struct ieee80211_local *local);
+u32 ieee80211_idle_off(struct ieee80211_local *local);
 void ieee80211_recalc_idle(struct ieee80211_local *local);
 void ieee80211_adjust_monitor_flags(struct ieee80211_sub_if_data *sdata,
                                     const int offset);
diff --git a/net/mac80211/iface.c b/net/mac80211/iface.c
index baaa8608e52d..58150f877ec3 100644
--- a/net/mac80211/iface.c
+++ b/net/mac80211/iface.c
@@ -78,7 +78,7 @@ void ieee80211_recalc_txpower(struct ieee80211_sub_if_data *sdata)
                 ieee80211_bss_info_change_notify(sdata, BSS_CHANGED_TXPOWER);
 }
 
-static u32 ieee80211_idle_off(struct ieee80211_local *local)
+u32 ieee80211_idle_off(struct ieee80211_local *local)
 {
         if (!(local->hw.conf.flags & IEEE80211_CONF_IDLE))
                 return 0;
@@ -349,21 +349,19 @@ static void ieee80211_set_default_queues(struct ieee80211_sub_if_data *sdata)
 static int ieee80211_add_virtual_monitor(struct ieee80211_local *local)
 {
         struct ieee80211_sub_if_data *sdata;
-        int ret = 0;
+        int ret;
 
         if (!(local->hw.flags & IEEE80211_HW_WANT_MONITOR_VIF))
                 return 0;
 
-        mutex_lock(&local->iflist_mtx);
+        ASSERT_RTNL();
 
         if (local->monitor_sdata)
-                goto out_unlock;
+                return 0;
 
         sdata = kzalloc(sizeof(*sdata) + local->hw.vif_data_size, GFP_KERNEL);
-        if (!sdata) {
-                ret = -ENOMEM;
-                goto out_unlock;
-        }
+        if (!sdata)
+                return -ENOMEM;
 
         /* set up data */
         sdata->local = local;
@@ -377,13 +375,13 @@ static int ieee80211_add_virtual_monitor(struct ieee80211_local *local)
         if (WARN_ON(ret)) {
                 /* ok .. stupid driver, it asked for this! */
                 kfree(sdata);
-                goto out_unlock;
+                return ret;
         }
 
         ret = ieee80211_check_queues(sdata);
         if (ret) {
                 kfree(sdata);
-                goto out_unlock;
+                return ret;
         }
 
         ret = ieee80211_vif_use_channel(sdata, &local->monitor_chandef,
@@ -391,13 +389,14 @@ static int ieee80211_add_virtual_monitor(struct ieee80211_local *local)
         if (ret) {
                 drv_remove_interface(local, sdata);
                 kfree(sdata);
-                goto out_unlock;
+                return ret;
         }
 
+        mutex_lock(&local->iflist_mtx);
         rcu_assign_pointer(local->monitor_sdata, sdata);
- out_unlock:
         mutex_unlock(&local->iflist_mtx);
-        return ret;
+
+        return 0;
 }
 
 static void ieee80211_del_virtual_monitor(struct ieee80211_local *local)
@@ -407,14 +406,20 @@ static void ieee80211_del_virtual_monitor(struct ieee80211_local *local)
         if (!(local->hw.flags & IEEE80211_HW_WANT_MONITOR_VIF))
                 return;
 
+        ASSERT_RTNL();
+
         mutex_lock(&local->iflist_mtx);
 
         sdata = rcu_dereference_protected(local->monitor_sdata,
                                           lockdep_is_held(&local->iflist_mtx));
-        if (!sdata)
-                goto out_unlock;
+        if (!sdata) {
+                mutex_unlock(&local->iflist_mtx);
+                return;
+        }
 
         rcu_assign_pointer(local->monitor_sdata, NULL);
+        mutex_unlock(&local->iflist_mtx);
+
         synchronize_net();
 
         ieee80211_vif_release_channel(sdata);
@@ -422,8 +427,6 @@ static void ieee80211_del_virtual_monitor(struct ieee80211_local *local)
         drv_remove_interface(local, sdata);
 
         kfree(sdata);
- out_unlock:
-        mutex_unlock(&local->iflist_mtx);
 }
 
 /*
diff --git a/net/mac80211/mesh.c b/net/mac80211/mesh.c
index 29ce2aa87e7b..4749b3858695 100644
--- a/net/mac80211/mesh.c
+++ b/net/mac80211/mesh.c
@@ -1060,7 +1060,8 @@ void ieee80211_mesh_notify_scan_completed(struct ieee80211_local *local)
 
         rcu_read_lock();
         list_for_each_entry_rcu(sdata, &local->interfaces, list)
-                if (ieee80211_vif_is_mesh(&sdata->vif))
+                if (ieee80211_vif_is_mesh(&sdata->vif) &&
+                    ieee80211_sdata_running(sdata))
                         ieee80211_queue_work(&local->hw, &sdata->work);
         rcu_read_unlock();
 }
diff --git a/net/mac80211/mlme.c b/net/mac80211/mlme.c
index 141577412d84..82cc30318a86 100644
--- a/net/mac80211/mlme.c
+++ b/net/mac80211/mlme.c
@@ -3608,8 +3608,10 @@ void ieee80211_mlme_notify_scan_completed(struct ieee80211_local *local)
 
         /* Restart STA timers */
         rcu_read_lock();
-        list_for_each_entry_rcu(sdata, &local->interfaces, list)
-                ieee80211_restart_sta_timer(sdata);
+        list_for_each_entry_rcu(sdata, &local->interfaces, list) {
+                if (ieee80211_sdata_running(sdata))
+                        ieee80211_restart_sta_timer(sdata);
+        }
         rcu_read_unlock();
 }
 
diff --git a/net/mac80211/offchannel.c b/net/mac80211/offchannel.c
index cc79b4a2e821..430bd254e496 100644
--- a/net/mac80211/offchannel.c
+++ b/net/mac80211/offchannel.c
@@ -297,10 +297,13 @@ void ieee80211_start_next_roc(struct ieee80211_local *local)
         }
 }
 
-void ieee80211_roc_notify_destroy(struct ieee80211_roc_work *roc)
+void ieee80211_roc_notify_destroy(struct ieee80211_roc_work *roc, bool free)
 {
         struct ieee80211_roc_work *dep, *tmp;
 
+        if (WARN_ON(roc->to_be_freed))
+                return;
+
         /* was never transmitted */
         if (roc->frame) {
                 cfg80211_mgmt_tx_status(&roc->sdata->wdev,
@@ -316,9 +319,12 @@ void ieee80211_roc_notify_destroy(struct ieee80211_roc_work *roc)
                                                    GFP_KERNEL);
 
         list_for_each_entry_safe(dep, tmp, &roc->dependents, list)
-                ieee80211_roc_notify_destroy(dep);
+                ieee80211_roc_notify_destroy(dep, true);
 
-        kfree(roc);
+        if (free)
+                kfree(roc);
+        else
+                roc->to_be_freed = true;
 }
 
 void ieee80211_sw_roc_work(struct work_struct *work)
@@ -331,6 +337,9 @@ void ieee80211_sw_roc_work(struct work_struct *work)
 
         mutex_lock(&local->mtx);
 
+        if (roc->to_be_freed)
+                goto out_unlock;
+
         if (roc->abort)
                 goto finish;
 
@@ -370,7 +379,7 @@ void ieee80211_sw_roc_work(struct work_struct *work)
  finish:
                 list_del(&roc->list);
                 started = roc->started;
-                ieee80211_roc_notify_destroy(roc);
+                ieee80211_roc_notify_destroy(roc, !roc->abort);
 
                 if (started) {
                         drv_flush(local, false);
@@ -410,7 +419,7 @@ static void ieee80211_hw_roc_done(struct work_struct *work)
 
         list_del(&roc->list);
 
-        ieee80211_roc_notify_destroy(roc);
+        ieee80211_roc_notify_destroy(roc, true);
 
         /* if there's another roc, start it now */
         ieee80211_start_next_roc(local);
@@ -460,12 +469,14 @@ void ieee80211_roc_purge(struct ieee80211_sub_if_data *sdata)
         list_for_each_entry_safe(roc, tmp, &tmp_list, list) {
                 if (local->ops->remain_on_channel) {
                         list_del(&roc->list);
-                        ieee80211_roc_notify_destroy(roc);
+                        ieee80211_roc_notify_destroy(roc, true);
                 } else {
                         ieee80211_queue_delayed_work(&local->hw, &roc->work, 0);
 
                         /* work will clean up etc */
                         flush_delayed_work(&roc->work);
+                        WARN_ON(!roc->to_be_freed);
+                        kfree(roc);
                 }
         }
 
diff --git a/net/mac80211/rx.c b/net/mac80211/rx.c
index bb73ed2d20b9..c6844ad080be 100644
--- a/net/mac80211/rx.c
+++ b/net/mac80211/rx.c
@@ -2675,7 +2675,19 @@ ieee80211_rx_h_action_return(struct ieee80211_rx_data *rx)
 
                 memset(nskb->cb, 0, sizeof(nskb->cb));
 
-                ieee80211_tx_skb(rx->sdata, nskb);
+                if (rx->sdata->vif.type == NL80211_IFTYPE_P2P_DEVICE) {
+                        struct ieee80211_tx_info *info = IEEE80211_SKB_CB(nskb);
+
+                        info->flags = IEEE80211_TX_CTL_TX_OFFCHAN |
+                                      IEEE80211_TX_INTFL_OFFCHAN_TX_OK |
+                                      IEEE80211_TX_CTL_NO_CCK_RATE;
+                        if (local->hw.flags & IEEE80211_HW_QUEUE_CONTROL)
+                                info->hw_queue =
+                                        local->hw.offchannel_tx_hw_queue;
+                }
+
+                __ieee80211_tx_skb_tid_band(rx->sdata, nskb, 7,
+                                            status->band);
         }
         dev_kfree_skb(rx->skb);
         return RX_QUEUED;
diff --git a/net/mac80211/sta_info.c b/net/mac80211/sta_info.c
index a79ce820cb50..238a0cca320e 100644
--- a/net/mac80211/sta_info.c
+++ b/net/mac80211/sta_info.c
@@ -766,6 +766,7 @@ int __must_check __sta_info_destroy(struct sta_info *sta)
         struct ieee80211_local *local;
         struct ieee80211_sub_if_data *sdata;
         int ret, i;
+        bool have_key = false;
 
         might_sleep();
 
@@ -793,12 +794,19 @@ int __must_check __sta_info_destroy(struct sta_info *sta)
         list_del_rcu(&sta->list);
 
         mutex_lock(&local->key_mtx);
-        for (i = 0; i < NUM_DEFAULT_KEYS; i++)
+        for (i = 0; i < NUM_DEFAULT_KEYS; i++) {
                 __ieee80211_key_free(key_mtx_dereference(local, sta->gtk[i]));
-        if (sta->ptk)
+                have_key = true;
+        }
+        if (sta->ptk) {
                 __ieee80211_key_free(key_mtx_dereference(local, sta->ptk));
+                have_key = true;
+        }
         mutex_unlock(&local->key_mtx);
 
+        if (!have_key)
+                synchronize_net();
+
         sta->dead = true;
 
         local->num_sta--;
diff --git a/net/netfilter/nf_conntrack_standalone.c b/net/netfilter/nf_conntrack_standalone.c
index 6bcce401fd1c..fedee3943661 100644
--- a/net/netfilter/nf_conntrack_standalone.c
+++ b/net/netfilter/nf_conntrack_standalone.c
@@ -568,6 +568,7 @@ static int __init nf_conntrack_standalone_init(void)
                 register_net_sysctl(&init_net, "net", nf_ct_netfilter_table);
         if (!nf_ct_netfilter_header) {
                 pr_err("nf_conntrack: can't register to sysctl.\n");
+                ret = -ENOMEM;
                 goto out_sysctl;
         }
 #endif
diff --git a/net/netfilter/nfnetlink_acct.c b/net/netfilter/nfnetlink_acct.c
index 589d686f0b4c..dc3fd5d44464 100644
--- a/net/netfilter/nfnetlink_acct.c
+++ b/net/netfilter/nfnetlink_acct.c
@@ -49,6 +49,8 @@ nfnl_acct_new(struct sock *nfnl, struct sk_buff *skb,
                 return -EINVAL;
 
         acct_name = nla_data(tb[NFACCT_NAME]);
+        if (strlen(acct_name) == 0)
+                return -EINVAL;
 
         list_for_each_entry(nfacct, &nfnl_acct_list, head) {
                 if (strncmp(nfacct->name, acct_name, NFACCT_NAME_MAX) != 0)
diff --git a/net/netfilter/nfnetlink_queue_core.c b/net/netfilter/nfnetlink_queue_core.c
index 1cb48540f86a..42680b2baa11 100644
--- a/net/netfilter/nfnetlink_queue_core.c
+++ b/net/netfilter/nfnetlink_queue_core.c
@@ -1062,8 +1062,10 @@ static int __init nfnetlink_queue_init(void)
 
 #ifdef CONFIG_PROC_FS
         if (!proc_create("nfnetlink_queue", 0440,
-                         proc_net_netfilter, &nfqnl_file_ops))
+                         proc_net_netfilter, &nfqnl_file_ops)) {
+                status = -ENOMEM;
                 goto cleanup_subsys;
+        }
 #endif
 
         register_netdevice_notifier(&nfqnl_dev_notifier);
diff --git a/net/nfc/llcp/llcp.c b/net/nfc/llcp/llcp.c
index b530afadd76c..ee25f25f0cd6 100644
--- a/net/nfc/llcp/llcp.c
+++ b/net/nfc/llcp/llcp.c
@@ -107,8 +107,6 @@ static void nfc_llcp_socket_release(struct nfc_llcp_local *local, bool listen,
                                 accept_sk->sk_state_change(sk);
 
                                 bh_unlock_sock(accept_sk);
-
-                                sock_orphan(accept_sk);
                         }
 
                         if (listen == true) {
@@ -134,8 +132,6 @@ static void nfc_llcp_socket_release(struct nfc_llcp_local *local, bool listen,
 
                 bh_unlock_sock(sk);
 
-                sock_orphan(sk);
-
                 sk_del_node_init(sk);
         }
 
@@ -164,8 +160,6 @@ static void nfc_llcp_socket_release(struct nfc_llcp_local *local, bool listen,
 
                 bh_unlock_sock(sk);
 
-                sock_orphan(sk);
-
                 sk_del_node_init(sk);
         }
 
@@ -827,7 +821,6 @@ static void nfc_llcp_recv_ui(struct nfc_llcp_local *local,
                 skb_get(skb);
         } else {
                 pr_err("Receive queue is full\n");
-                kfree_skb(skb);
         }
 
         nfc_llcp_sock_put(llcp_sock);
@@ -1028,7 +1021,6 @@ static void nfc_llcp_recv_hdlc(struct nfc_llcp_local *local,
                         skb_get(skb);
                 } else {
                         pr_err("Receive queue is full\n");
-                        kfree_skb(skb);
                 }
         }
 
diff --git a/net/nfc/llcp/sock.c b/net/nfc/llcp/sock.c
index 5c7cdf3f2a83..8f025746f337 100644
--- a/net/nfc/llcp/sock.c
+++ b/net/nfc/llcp/sock.c
@@ -270,7 +270,9 @@ struct sock *nfc_llcp_accept_dequeue(struct sock *parent,
                 }
 
                 if (sk->sk_state == LLCP_CONNECTED || !newsock) {
-                        nfc_llcp_accept_unlink(sk);
+                        list_del_init(&lsk->accept_queue);
+                        sock_put(sk);
+
                         if (newsock)
                                 sock_graft(sk, newsock);
 
@@ -464,8 +466,6 @@ static int llcp_sock_release(struct socket *sock)
                         nfc_llcp_accept_unlink(accept_sk);
 
                         release_sock(accept_sk);
-
-                        sock_orphan(accept_sk);
                 }
         }
 
diff --git a/net/sched/sch_cbq.c b/net/sched/sch_cbq.c
index 13aa47aa2ffb..1bc210ffcba2 100644
--- a/net/sched/sch_cbq.c
+++ b/net/sched/sch_cbq.c
@@ -962,8 +962,11 @@ cbq_dequeue(struct Qdisc *sch)
                 cbq_update(q);
                 if ((incr -= incr2) < 0)
                         incr = 0;
+                q->now += incr;
+        } else {
+                if (now > q->now)
+                        q->now = now;
         }
-        q->now += incr;
         q->now_rt = now;
 
         for (;;) {
diff --git a/net/sched/sch_fq_codel.c b/net/sched/sch_fq_codel.c
index 4e606fcb2534..55786283a3df 100644
--- a/net/sched/sch_fq_codel.c
+++ b/net/sched/sch_fq_codel.c
@@ -195,7 +195,7 @@ static int fq_codel_enqueue(struct sk_buff *skb, struct Qdisc *sch)
                 flow->deficit = q->quantum;
                 flow->dropped = 0;
         }
-        if (++sch->q.qlen < sch->limit)
+        if (++sch->q.qlen <= sch->limit)
                 return NET_XMIT_SUCCESS;
 
         q->drop_overlimit++;
diff --git a/net/sched/sch_generic.c b/net/sched/sch_generic.c
index ffad48109a22..eac7e0ee23c1 100644
--- a/net/sched/sch_generic.c
+++ b/net/sched/sch_generic.c
@@ -904,7 +904,7 @@ void psched_ratecfg_precompute(struct psched_ratecfg *r, u32 rate)
         u64 mult;
         int shift;
 
-        r->rate_bps = rate << 3;
+        r->rate_bps = (u64)rate << 3;
         r->shift = 0;
         r->mult = 1;
         /*
diff --git a/net/unix/af_unix.c b/net/unix/af_unix.c
index 971282b6f6a3..2db702d82e7d 100644
--- a/net/unix/af_unix.c
+++ b/net/unix/af_unix.c
@@ -1412,8 +1412,8 @@ static void maybe_add_creds(struct sk_buff *skb, const struct socket *sock,
         if (UNIXCB(skb).cred)
                 return;
         if (test_bit(SOCK_PASSCRED, &sock->flags) ||
-            (other->sk_socket &&
-            test_bit(SOCK_PASSCRED, &other->sk_socket->flags))) {
+            !other->sk_socket ||
+            test_bit(SOCK_PASSCRED, &other->sk_socket->flags)) {
                 UNIXCB(skb).pid  = get_pid(task_tgid(current));
                 UNIXCB(skb).cred = get_current_cred();
         }
@@ -1993,7 +1993,7 @@ again:
                         if ((UNIXCB(skb).pid  != siocb->scm->pid) ||
                             (UNIXCB(skb).cred != siocb->scm->cred))
                                 break;
-                } else {
+                } else if (test_bit(SOCK_PASSCRED, &sock->flags)) {
                         /* Copy credentials */
                         scm_set_cred(siocb->scm, UNIXCB(skb).pid, UNIXCB(skb).cred);
                         check_creds = 1;
diff --git a/net/vmw_vsock/af_vsock.c b/net/vmw_vsock/af_vsock.c
index ca511c4f388a..d8079daf1bde 100644
--- a/net/vmw_vsock/af_vsock.c
+++ b/net/vmw_vsock/af_vsock.c
@@ -207,7 +207,7 @@ static struct sock *__vsock_find_bound_socket(struct sockaddr_vm *addr)
         struct vsock_sock *vsk;
 
         list_for_each_entry(vsk, vsock_bound_sockets(addr), bound_table)
-                if (vsock_addr_equals_addr_any(addr, &vsk->local_addr))
+                if (addr->svm_port == vsk->local_addr.svm_port)
                         return sk_vsock(vsk);
 
         return NULL;
@@ -220,8 +220,8 @@ static struct sock *__vsock_find_connected_socket(struct sockaddr_vm *src,
 
         list_for_each_entry(vsk, vsock_connected_sockets(src, dst),
                             connected_table) {
-                if (vsock_addr_equals_addr(src, &vsk->remote_addr)
-                    && vsock_addr_equals_addr(dst, &vsk->local_addr)) {
+                if (vsock_addr_equals_addr(src, &vsk->remote_addr) &&
+                    dst->svm_port == vsk->local_addr.svm_port) {
                         return sk_vsock(vsk);
                 }
         }
diff --git a/net/vmw_vsock/vmci_transport.c b/net/vmw_vsock/vmci_transport.c
index a70ace83a153..1f6508e249ae 100644
--- a/net/vmw_vsock/vmci_transport.c
+++ b/net/vmw_vsock/vmci_transport.c
@@ -464,19 +464,16 @@ static struct sock *vmci_transport_get_pending(
         struct vsock_sock *vlistener;
         struct vsock_sock *vpending;
         struct sock *pending;
+        struct sockaddr_vm src;
+
+        vsock_addr_init(&src, pkt->dg.src.context, pkt->src_port);
 
         vlistener = vsock_sk(listener);
 
         list_for_each_entry(vpending, &vlistener->pending_links,
                             pending_links) {
-                struct sockaddr_vm src;
-                struct sockaddr_vm dst;
-
-                vsock_addr_init(&src, pkt->dg.src.context, pkt->src_port);
-                vsock_addr_init(&dst, pkt->dg.dst.context, pkt->dst_port);
-
                 if (vsock_addr_equals_addr(&src, &vpending->remote_addr) &&
-                    vsock_addr_equals_addr(&dst, &vpending->local_addr)) {
+                    pkt->dst_port == vpending->local_addr.svm_port) {
                         pending = sk_vsock(vpending);
                         sock_hold(pending);
                         goto found;
@@ -739,10 +736,15 @@ static int vmci_transport_recv_stream_cb(void *data, struct vmci_datagram *dg)
          */
         bh_lock_sock(sk);
 
-        if (!sock_owned_by_user(sk) && sk->sk_state == SS_CONNECTED)
-                vmci_trans(vsk)->notify_ops->handle_notify_pkt(
-                                sk, pkt, true, &dst, &src,
-                                &bh_process_pkt);
+        if (!sock_owned_by_user(sk)) {
+                /* The local context ID may be out of date, update it. */
+                vsk->local_addr.svm_cid = dst.svm_cid;
+
+                if (sk->sk_state == SS_CONNECTED)
+                        vmci_trans(vsk)->notify_ops->handle_notify_pkt(
+                                        sk, pkt, true, &dst, &src,
+                                        &bh_process_pkt);
+        }
 
         bh_unlock_sock(sk);
 
@@ -902,6 +904,9 @@ static void vmci_transport_recv_pkt_work(struct work_struct *work)
 
         lock_sock(sk);
 
+        /* The local context ID may be out of date. */
+        vsock_sk(sk)->local_addr.svm_cid = pkt->dg.dst.context;
+
         switch (sk->sk_state) {
         case SS_LISTEN:
                 vmci_transport_recv_listen(sk, pkt);
@@ -958,6 +963,10 @@ static int vmci_transport_recv_listen(struct sock *sk,
         pending = vmci_transport_get_pending(sk, pkt);
         if (pending) {
                 lock_sock(pending);
+
+                /* The local context ID may be out of date. */
+                vsock_sk(pending)->local_addr.svm_cid = pkt->dg.dst.context;
+
                 switch (pending->sk_state) {
                 case SS_CONNECTING:
                         err = vmci_transport_recv_connecting_server(sk,
diff --git a/net/vmw_vsock/vsock_addr.c b/net/vmw_vsock/vsock_addr.c
index b7df1aea7c59..ec2611b4ea0e 100644
--- a/net/vmw_vsock/vsock_addr.c
+++ b/net/vmw_vsock/vsock_addr.c
@@ -64,16 +64,6 @@ bool vsock_addr_equals_addr(const struct sockaddr_vm *addr,
 }
 EXPORT_SYMBOL_GPL(vsock_addr_equals_addr);
 
-bool vsock_addr_equals_addr_any(const struct sockaddr_vm *addr,
-                                const struct sockaddr_vm *other)
-{
-        return (addr->svm_cid == VMADDR_CID_ANY ||
-                other->svm_cid == VMADDR_CID_ANY ||
-                addr->svm_cid == other->svm_cid) &&
-               addr->svm_port == other->svm_port;
-}
-EXPORT_SYMBOL_GPL(vsock_addr_equals_addr_any);
-
 int vsock_addr_cast(const struct sockaddr *addr,
                     size_t len, struct sockaddr_vm **out_addr)
 {
diff --git a/net/vmw_vsock/vsock_addr.h b/net/vmw_vsock/vsock_addr.h
index cdfbcefdf843..9ccd5316eac0 100644
--- a/net/vmw_vsock/vsock_addr.h
+++ b/net/vmw_vsock/vsock_addr.h
@@ -24,8 +24,6 @@ bool vsock_addr_bound(const struct sockaddr_vm *addr);
 void vsock_addr_unbind(struct sockaddr_vm *addr);
 bool vsock_addr_equals_addr(const struct sockaddr_vm *addr,
                             const struct sockaddr_vm *other);
-bool vsock_addr_equals_addr_any(const struct sockaddr_vm *addr,
-                                const struct sockaddr_vm *other);
 int vsock_addr_cast(const struct sockaddr *addr, size_t len,
                     struct sockaddr_vm **out_addr);
 
diff --git a/net/wireless/core.c b/net/wireless/core.c
index ea4155fe9733..6ddf74f0ae1e 100644
--- a/net/wireless/core.c
+++ b/net/wireless/core.c
@@ -212,6 +212,39 @@ static void cfg80211_rfkill_poll(struct rfkill *rfkill, void *data)
         rdev_rfkill_poll(rdev);
 }
 
+void cfg80211_stop_p2p_device(struct cfg80211_registered_device *rdev,
+                              struct wireless_dev *wdev)
+{
+        lockdep_assert_held(&rdev->devlist_mtx);
+        lockdep_assert_held(&rdev->sched_scan_mtx);
+
+        if (WARN_ON(wdev->iftype != NL80211_IFTYPE_P2P_DEVICE))
+                return;
+
+        if (!wdev->p2p_started)
+                return;
+
+        rdev_stop_p2p_device(rdev, wdev);
+        wdev->p2p_started = false;
+
+        rdev->opencount--;
+
+        if (rdev->scan_req && rdev->scan_req->wdev == wdev) {
+                bool busy = work_busy(&rdev->scan_done_wk);
+
+                /*
+                 * If the work isn't pending or running (in which case it would
+                 * be waiting for the lock we hold) the driver didn't properly
+                 * cancel the scan when the interface was removed. In this case
+                 * warn and leak the scan request object to not crash later.
+                 */
+                WARN_ON(!busy);
+
+                rdev->scan_req->aborted = true;
+                ___cfg80211_scan_done(rdev, !busy);
+        }
+}
+
 static int cfg80211_rfkill_set_block(void *data, bool blocked)
 {
         struct cfg80211_registered_device *rdev = data;
@@ -221,7 +254,8 @@ static int cfg80211_rfkill_set_block(void *data, bool blocked)
                 return 0;
 
         rtnl_lock();
-        mutex_lock(&rdev->devlist_mtx);
+
+        /* read-only iteration need not hold the devlist_mtx */
 
         list_for_each_entry(wdev, &rdev->wdev_list, list) {
                 if (wdev->netdev) {
@@ -231,18 +265,18 @@ static int cfg80211_rfkill_set_block(void *data, bool blocked)
                 /* otherwise, check iftype */
                 switch (wdev->iftype) {
                 case NL80211_IFTYPE_P2P_DEVICE:
-                        if (!wdev->p2p_started)
-                                break;
-                        rdev_stop_p2p_device(rdev, wdev);
-                        wdev->p2p_started = false;
-                        rdev->opencount--;
+                        /* but this requires it */
+                        mutex_lock(&rdev->devlist_mtx);
+                        mutex_lock(&rdev->sched_scan_mtx);
+                        cfg80211_stop_p2p_device(rdev, wdev);
+                        mutex_unlock(&rdev->sched_scan_mtx);
+                        mutex_unlock(&rdev->devlist_mtx);
                         break;
                 default:
                         break;
                 }
         }
 
-        mutex_unlock(&rdev->devlist_mtx);
         rtnl_unlock();
 
         return 0;
@@ -745,17 +779,13 @@ static void wdev_cleanup_work(struct work_struct *work)
         wdev = container_of(work, struct wireless_dev, cleanup_work);
         rdev = wiphy_to_dev(wdev->wiphy);
 
-        cfg80211_lock_rdev(rdev);
+        mutex_lock(&rdev->sched_scan_mtx);
 
         if (WARN_ON(rdev->scan_req && rdev->scan_req->wdev == wdev)) {
                 rdev->scan_req->aborted = true;
                 ___cfg80211_scan_done(rdev, true);
         }
 
-        cfg80211_unlock_rdev(rdev);
-
-        mutex_lock(&rdev->sched_scan_mtx);
-
         if (WARN_ON(rdev->sched_scan_req &&
                     rdev->sched_scan_req->dev == wdev->netdev)) {
                 __cfg80211_stop_sched_scan(rdev, false);
@@ -781,21 +811,19 @@ void cfg80211_unregister_wdev(struct wireless_dev *wdev)
                 return;
 
         mutex_lock(&rdev->devlist_mtx);
+        mutex_lock(&rdev->sched_scan_mtx);
         list_del_rcu(&wdev->list);
         rdev->devlist_generation++;
 
         switch (wdev->iftype) {
         case NL80211_IFTYPE_P2P_DEVICE:
-                if (!wdev->p2p_started)
-                        break;
-                rdev_stop_p2p_device(rdev, wdev);
-                wdev->p2p_started = false;
-                rdev->opencount--;
+                cfg80211_stop_p2p_device(rdev, wdev);
                 break;
         default:
                 WARN_ON_ONCE(1);
                 break;
         }
+        mutex_unlock(&rdev->sched_scan_mtx);
         mutex_unlock(&rdev->devlist_mtx);
 }
 EXPORT_SYMBOL(cfg80211_unregister_wdev);
@@ -936,6 +964,7 @@ static int cfg80211_netdev_notifier_call(struct notifier_block *nb,
                 cfg80211_update_iface_num(rdev, wdev->iftype, 1);
                 cfg80211_lock_rdev(rdev);
                 mutex_lock(&rdev->devlist_mtx);
+                mutex_lock(&rdev->sched_scan_mtx);
                 wdev_lock(wdev);
                 switch (wdev->iftype) {
 #ifdef CONFIG_CFG80211_WEXT
@@ -967,6 +996,7 @@ static int cfg80211_netdev_notifier_call(struct notifier_block *nb,
                         break;
                 }
                 wdev_unlock(wdev);
+                mutex_unlock(&rdev->sched_scan_mtx);
                 rdev->opencount++;
                 mutex_unlock(&rdev->devlist_mtx);
                 cfg80211_unlock_rdev(rdev);
diff --git a/net/wireless/core.h b/net/wireless/core.h
index 3aec0e429d8a..5845c2b37aa8 100644
--- a/net/wireless/core.h
+++ b/net/wireless/core.h
@@ -503,6 +503,9 @@ int cfg80211_validate_beacon_int(struct cfg80211_registered_device *rdev,
 void cfg80211_update_iface_num(struct cfg80211_registered_device *rdev,
                                enum nl80211_iftype iftype, int num);
 
+void cfg80211_stop_p2p_device(struct cfg80211_registered_device *rdev,
+                              struct wireless_dev *wdev);
+
 #define CFG80211_MAX_NUM_DIFFERENT_CHANNELS 10
 
 #ifdef CONFIG_CFG80211_DEVELOPER_WARNINGS
diff --git a/net/wireless/nl80211.c b/net/wireless/nl80211.c
index d44ab216c0ec..58e13a8c95f9 100644
--- a/net/wireless/nl80211.c
+++ b/net/wireless/nl80211.c
@@ -4702,14 +4702,19 @@ static int nl80211_trigger_scan(struct sk_buff *skb, struct genl_info *info)
         if (!rdev->ops->scan)
                 return -EOPNOTSUPP;
 
-        if (rdev->scan_req)
-                return -EBUSY;
+        mutex_lock(&rdev->sched_scan_mtx);
+        if (rdev->scan_req) {
+                err = -EBUSY;
+                goto unlock;
+        }
 
         if (info->attrs[NL80211_ATTR_SCAN_FREQUENCIES]) {
                 n_channels = validate_scan_freqs(
                                 info->attrs[NL80211_ATTR_SCAN_FREQUENCIES]);
-                if (!n_channels)
-                        return -EINVAL;
+                if (!n_channels) {
+                        err = -EINVAL;
+                        goto unlock;
+                }
         } else {
                 enum ieee80211_band band;
                 n_channels = 0;
@@ -4723,23 +4728,29 @@ static int nl80211_trigger_scan(struct sk_buff *skb, struct genl_info *info)
                 nla_for_each_nested(attr, info->attrs[NL80211_ATTR_SCAN_SSIDS], tmp)
                         n_ssids++;
 
-        if (n_ssids > wiphy->max_scan_ssids)
-                return -EINVAL;
+        if (n_ssids > wiphy->max_scan_ssids) {
+                err = -EINVAL;
+                goto unlock;
+        }
 
         if (info->attrs[NL80211_ATTR_IE])
                 ie_len = nla_len(info->attrs[NL80211_ATTR_IE]);
         else
                 ie_len = 0;
 
-        if (ie_len > wiphy->max_scan_ie_len)
-                return -EINVAL;
+        if (ie_len > wiphy->max_scan_ie_len) {
+                err = -EINVAL;
+                goto unlock;
+        }
 
         request = kzalloc(sizeof(*request)
                         + sizeof(*request->ssids) * n_ssids
                         + sizeof(*request->channels) * n_channels
                         + ie_len, GFP_KERNEL);
-        if (!request)
-                return -ENOMEM;
+        if (!request) {
+                err = -ENOMEM;
+                goto unlock;
+        }
 
         if (n_ssids)
                 request->ssids = (void *)&request->channels[n_channels];
@@ -4876,6 +4887,8 @@ static int nl80211_trigger_scan(struct sk_buff *skb, struct genl_info *info)
                 kfree(request);
         }
 
+ unlock:
+        mutex_unlock(&rdev->sched_scan_mtx);
         return err;
 }
 
@@ -7749,20 +7762,9 @@ static int nl80211_stop_p2p_device(struct sk_buff *skb, struct genl_info *info)
         if (!rdev->ops->stop_p2p_device)
                 return -EOPNOTSUPP;
 
-        if (!wdev->p2p_started)
-                return 0;
-
-        rdev_stop_p2p_device(rdev, wdev);
-        wdev->p2p_started = false;
-
-        mutex_lock(&rdev->devlist_mtx);
-        rdev->opencount--;
-        mutex_unlock(&rdev->devlist_mtx);
-
-        if (WARN_ON(rdev->scan_req && rdev->scan_req->wdev == wdev)) {
-                rdev->scan_req->aborted = true;
-                ___cfg80211_scan_done(rdev, true);
-        }
+        mutex_lock(&rdev->sched_scan_mtx);
+        cfg80211_stop_p2p_device(rdev, wdev);
+        mutex_unlock(&rdev->sched_scan_mtx);
 
         return 0;
 }
@@ -8486,7 +8488,7 @@ static int nl80211_add_scan_req(struct sk_buff *msg,
         struct nlattr *nest;
         int i;
 
-        ASSERT_RDEV_LOCK(rdev);
+        lockdep_assert_held(&rdev->sched_scan_mtx);
 
         if (WARN_ON(!req))
                 return 0;
diff --git a/net/wireless/scan.c b/net/wireless/scan.c
index 674aadca0079..fd99ea495b7e 100644
--- a/net/wireless/scan.c
+++ b/net/wireless/scan.c
@@ -169,7 +169,7 @@ void ___cfg80211_scan_done(struct cfg80211_registered_device *rdev, bool leak)
         union iwreq_data wrqu;
 #endif
 
-        ASSERT_RDEV_LOCK(rdev);
+        lockdep_assert_held(&rdev->sched_scan_mtx);
 
         request = rdev->scan_req;
 
@@ -230,9 +230,9 @@ void __cfg80211_scan_done(struct work_struct *wk)
         rdev = container_of(wk, struct cfg80211_registered_device,
                             scan_done_wk);
 
-        cfg80211_lock_rdev(rdev);
+        mutex_lock(&rdev->sched_scan_mtx);
         ___cfg80211_scan_done(rdev, false);
-        cfg80211_unlock_rdev(rdev);
+        mutex_unlock(&rdev->sched_scan_mtx);
 }
 
 void cfg80211_scan_done(struct cfg80211_scan_request *request, bool aborted)
@@ -698,11 +698,6 @@ cfg80211_bss_update(struct cfg80211_registered_device *dev,
         found = rb_find_bss(dev, tmp, BSS_CMP_REGULAR);
 
         if (found) {
-                found->pub.beacon_interval = tmp->pub.beacon_interval;
-                found->pub.signal = tmp->pub.signal;
-                found->pub.capability = tmp->pub.capability;
-                found->ts = tmp->ts;
-
                 /* Update IEs */
                 if (rcu_access_pointer(tmp->pub.proberesp_ies)) {
                         const struct cfg80211_bss_ies *old;
@@ -723,6 +718,8 @@ cfg80211_bss_update(struct cfg80211_registered_device *dev,
 
                         if (found->pub.hidden_beacon_bss &&
                             !list_empty(&found->hidden_list)) {
+                                const struct cfg80211_bss_ies *f;
+
                                 /*
                                  * The found BSS struct is one of the probe
                                  * response members of a group, but we're
@@ -732,6 +729,10 @@ cfg80211_bss_update(struct cfg80211_registered_device *dev,
                                  * SSID to showing it, which is confusing so
                                  * drop this information.
                                  */
+
+                                f = rcu_access_pointer(tmp->pub.beacon_ies);
+                                kfree_rcu((struct cfg80211_bss_ies *)f,
+                                          rcu_head);
                                 goto drop;
                         }
 
@@ -761,6 +762,11 @@ cfg80211_bss_update(struct cfg80211_registered_device *dev,
                                 kfree_rcu((struct cfg80211_bss_ies *)old,
                                           rcu_head);
                 }
+
+                found->pub.beacon_interval = tmp->pub.beacon_interval;
+                found->pub.signal = tmp->pub.signal;
+                found->pub.capability = tmp->pub.capability;
+                found->ts = tmp->ts;
         } else {
                 struct cfg80211_internal_bss *new;
                 struct cfg80211_internal_bss *hidden;
@@ -1056,6 +1062,7 @@ int cfg80211_wext_siwscan(struct net_device *dev,
         if (IS_ERR(rdev))
                 return PTR_ERR(rdev);
 
+        mutex_lock(&rdev->sched_scan_mtx);
         if (rdev->scan_req) {
                 err = -EBUSY;
                 goto out;
@@ -1162,6 +1169,7 @@ int cfg80211_wext_siwscan(struct net_device *dev,
                 dev_hold(dev);
         }
  out:
+        mutex_unlock(&rdev->sched_scan_mtx);
         kfree(creq);
         cfg80211_unlock_rdev(rdev);
         return err;
diff --git a/net/wireless/sme.c b/net/wireless/sme.c
index f432bd3755b1..09d994d192ff 100644
--- a/net/wireless/sme.c
+++ b/net/wireless/sme.c
@@ -85,6 +85,7 @@ static int cfg80211_conn_scan(struct wireless_dev *wdev)
         ASSERT_RTNL();
         ASSERT_RDEV_LOCK(rdev);
         ASSERT_WDEV_LOCK(wdev);
+        lockdep_assert_held(&rdev->sched_scan_mtx);
 
         if (rdev->scan_req)
                 return -EBUSY;
@@ -320,11 +321,9 @@ void cfg80211_sme_scan_done(struct net_device *dev)
 {
         struct wireless_dev *wdev = dev->ieee80211_ptr;
 
-        mutex_lock(&wiphy_to_dev(wdev->wiphy)->devlist_mtx);
         wdev_lock(wdev);
         __cfg80211_sme_scan_done(dev);
         wdev_unlock(wdev);
-        mutex_unlock(&wiphy_to_dev(wdev->wiphy)->devlist_mtx);
 }
 
 void cfg80211_sme_rx_auth(struct net_device *dev,
@@ -924,9 +923,12 @@ int cfg80211_connect(struct cfg80211_registered_device *rdev,
         int err;
 
         mutex_lock(&rdev->devlist_mtx);
+        /* might request scan - scan_mtx -> wdev_mtx dependency */
+        mutex_lock(&rdev->sched_scan_mtx);
         wdev_lock(dev->ieee80211_ptr);
         err = __cfg80211_connect(rdev, dev, connect, connkeys, NULL);
         wdev_unlock(dev->ieee80211_ptr);
+        mutex_unlock(&rdev->sched_scan_mtx);
         mutex_unlock(&rdev->devlist_mtx);
 
         return err;
diff --git a/net/wireless/trace.h b/net/wireless/trace.h
index b7a531380e19..7586de77a2f8 100644
--- a/net/wireless/trace.h
+++ b/net/wireless/trace.h
@@ -27,7 +27,8 @@
 #define WIPHY_PR_ARG    __entry->wiphy_name
 
 #define WDEV_ENTRY      __field(u32, id)
-#define WDEV_ASSIGN     (__entry->id) = (wdev ? wdev->identifier : 0)
+#define WDEV_ASSIGN     (__entry->id) = (!IS_ERR_OR_NULL(wdev)  \
+                                         ? wdev->identifier : 0)
 #define WDEV_PR_FMT     "wdev(%u)"
 #define WDEV_PR_ARG     (__entry->id)
 
@@ -1778,7 +1779,7 @@ TRACE_EVENT(rdev_set_mac_acl,
         ),
         TP_fast_assign(
                 WIPHY_ASSIGN;
-                WIPHY_ASSIGN;
+                NETDEV_ASSIGN;
                 __entry->acl_policy = params->acl_policy;
         ),
         TP_printk(WIPHY_PR_FMT ", " NETDEV_PR_FMT ", acl policy: %d",
diff --git a/net/wireless/wext-sme.c b/net/wireless/wext-sme.c
index fb9622f6d99c..e79cb5c0655a 100644
--- a/net/wireless/wext-sme.c
+++ b/net/wireless/wext-sme.c
@@ -89,6 +89,7 @@ int cfg80211_mgd_wext_siwfreq(struct net_device *dev,
 
         cfg80211_lock_rdev(rdev);
         mutex_lock(&rdev->devlist_mtx);
+        mutex_lock(&rdev->sched_scan_mtx);
         wdev_lock(wdev);
 
         if (wdev->sme_state != CFG80211_SME_IDLE) {
@@ -135,6 +136,7 @@ int cfg80211_mgd_wext_siwfreq(struct net_device *dev,
         err = cfg80211_mgd_wext_connect(rdev, wdev);
  out:
         wdev_unlock(wdev);
+        mutex_unlock(&rdev->sched_scan_mtx);
         mutex_unlock(&rdev->devlist_mtx);
         cfg80211_unlock_rdev(rdev);
         return err;
@@ -190,6 +192,7 @@ int cfg80211_mgd_wext_siwessid(struct net_device *dev,
 
         cfg80211_lock_rdev(rdev);
         mutex_lock(&rdev->devlist_mtx);
+        mutex_lock(&rdev->sched_scan_mtx);
         wdev_lock(wdev);
 
         err = 0;
@@ -223,6 +226,7 @@ int cfg80211_mgd_wext_siwessid(struct net_device *dev,
         err = cfg80211_mgd_wext_connect(rdev, wdev);
  out:
         wdev_unlock(wdev);
+        mutex_unlock(&rdev->sched_scan_mtx);
         mutex_unlock(&rdev->devlist_mtx);
         cfg80211_unlock_rdev(rdev);
         return err;
@@ -285,6 +289,7 @@ int cfg80211_mgd_wext_siwap(struct net_device *dev,
 
         cfg80211_lock_rdev(rdev);
         mutex_lock(&rdev->devlist_mtx);
+        mutex_lock(&rdev->sched_scan_mtx);
         wdev_lock(wdev);
 
         if (wdev->sme_state != CFG80211_SME_IDLE) {
@@ -313,6 +318,7 @@ int cfg80211_mgd_wext_siwap(struct net_device *dev,
         err = cfg80211_mgd_wext_connect(rdev, wdev);
  out:
         wdev_unlock(wdev);
+        mutex_unlock(&rdev->sched_scan_mtx);
         mutex_unlock(&rdev->devlist_mtx);
         cfg80211_unlock_rdev(rdev);
         return err;
diff --git a/net/xfrm/xfrm_replay.c b/net/xfrm/xfrm_replay.c
index 35754cc8a9e5..8dafe6d3c6e4 100644
--- a/net/xfrm/xfrm_replay.c
+++ b/net/xfrm/xfrm_replay.c
@@ -334,6 +334,70 @@ static void xfrm_replay_notify_bmp(struct xfrm_state *x, int event)
                 x->xflags &= ~XFRM_TIME_DEFER;
 }
 
+static void xfrm_replay_notify_esn(struct xfrm_state *x, int event)
+{
+        u32 seq_diff, oseq_diff;
+        struct km_event c;
+        struct xfrm_replay_state_esn *replay_esn = x->replay_esn;
+        struct xfrm_replay_state_esn *preplay_esn = x->preplay_esn;
+
+        /* we send notify messages in case
+         *  1. we updated on of the sequence numbers, and the seqno difference
+         *     is at least x->replay_maxdiff, in this case we also update the
+         *     timeout of our timer function
+         *  2. if x->replay_maxage has elapsed since last update,
+         *     and there were changes
+         *
+         *  The state structure must be locked!
+         */
+
+        switch (event) {
+        case XFRM_REPLAY_UPDATE:
+                if (!x->replay_maxdiff)
+                        break;
+
+                if (replay_esn->seq_hi == preplay_esn->seq_hi)
+                        seq_diff = replay_esn->seq - preplay_esn->seq;
+                else
+                        seq_diff = ~preplay_esn->seq + replay_esn->seq + 1;
+
+                if (replay_esn->oseq_hi == preplay_esn->oseq_hi)
+                        oseq_diff = replay_esn->oseq - preplay_esn->oseq;
+                else
+                        oseq_diff = ~preplay_esn->oseq + replay_esn->oseq + 1;
+
+                if (seq_diff < x->replay_maxdiff &&
+                    oseq_diff < x->replay_maxdiff) {
+
+                        if (x->xflags & XFRM_TIME_DEFER)
+                                event = XFRM_REPLAY_TIMEOUT;
+                        else
+                                return;
+                }
+
+                break;
+
+        case XFRM_REPLAY_TIMEOUT:
+                if (memcmp(x->replay_esn, x->preplay_esn,
+                           xfrm_replay_state_esn_len(replay_esn)) == 0) {
+                        x->xflags |= XFRM_TIME_DEFER;
+                        return;
+                }
+
+                break;
+        }
+
+        memcpy(x->preplay_esn, x->replay_esn,
+               xfrm_replay_state_esn_len(replay_esn));
+        c.event = XFRM_MSG_NEWAE;
+        c.data.aevent = event;
+        km_state_notify(x, &c);
+
+        if (x->replay_maxage &&
+            !mod_timer(&x->rtimer, jiffies + x->replay_maxage))
+                x->xflags &= ~XFRM_TIME_DEFER;
+}
+
 static int xfrm_replay_overflow_esn(struct xfrm_state *x, struct sk_buff *skb)
 {
         int err = 0;
@@ -510,7 +574,7 @@ static struct xfrm_replay xfrm_replay_esn = {
         .advance        = xfrm_replay_advance_esn,
         .check          = xfrm_replay_check_esn,
         .recheck        = xfrm_replay_recheck_esn,
-        .notify         = xfrm_replay_notify_bmp,
+        .notify         = xfrm_replay_notify_esn,
         .overflow       = xfrm_replay_overflow_esn,
 };
 
diff --git a/sound/pci/hda/hda_codec.c b/sound/pci/hda/hda_codec.c
index ecdf30eb5879..4aba7646dd9c 100644
--- a/sound/pci/hda/hda_codec.c
+++ b/sound/pci/hda/hda_codec.c
@@ -173,7 +173,7 @@ const char *snd_hda_get_jack_type(u32 cfg)
                 "Line Out", "Speaker", "HP Out", "CD",
                 "SPDIF Out", "Digital Out", "Modem Line", "Modem Hand",
                 "Line In", "Aux", "Mic", "Telephony",
-                "SPDIF In", "Digitial In", "Reserved", "Other"
+                "SPDIF In", "Digital In", "Reserved", "Other"
         };
 
         return jack_types[(cfg & AC_DEFCFG_DEVICE)
diff --git a/sound/pci/hda/hda_eld.c b/sound/pci/hda/hda_eld.c
index 7dd846380a50..d0d7ac1e99d2 100644
--- a/sound/pci/hda/hda_eld.c
+++ b/sound/pci/hda/hda_eld.c
@@ -320,7 +320,7 @@ int snd_hdmi_get_eld(struct hda_codec *codec, hda_nid_t nid,
                      unsigned char *buf, int *eld_size)
 {
         int i;
-        int ret;
+        int ret = 0;
         int size;
 
         /*
diff --git a/sound/pci/hda/hda_generic.c b/sound/pci/hda/hda_generic.c
index 43c2ea539561..2dbe767be16b 100644
--- a/sound/pci/hda/hda_generic.c
+++ b/sound/pci/hda/hda_generic.c
@@ -740,7 +740,7 @@ EXPORT_SYMBOL_HDA(snd_hda_activate_path);
 static void path_power_down_sync(struct hda_codec *codec, struct nid_path *path)
 {
         struct hda_gen_spec *spec = codec->spec;
-        bool changed;
+        bool changed = false;
         int i;
 
         if (!spec->power_down_unused || path->active)
diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index 418bfc0eb0a3..bcd40ee488e3 100644
--- a/sound/pci/hda/hda_intel.c
+++ b/sound/pci/hda/hda_intel.c
@@ -134,8 +134,8 @@ MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
  * this may give more power-saving, but will take longer time to
  * wake up.
  */
-static int power_save_controller = -1;
-module_param(power_save_controller, bint, 0644);
+static bool power_save_controller = 1;
+module_param(power_save_controller, bool, 0644);
 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 #endif /* CONFIG_PM */
 
@@ -2931,8 +2931,6 @@ static int azx_runtime_idle(struct device *dev)
         struct snd_card *card = dev_get_drvdata(dev);
         struct azx *chip = card->private_data;
 
-        if (power_save_controller > 0)
-                return 0;
         if (!power_save_controller ||
             !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
                 return -EBUSY;
diff --git a/sound/pci/hda/patch_hdmi.c b/sound/pci/hda/patch_hdmi.c
index 78e1827d0a95..de8ac5c07fd0 100644
--- a/sound/pci/hda/patch_hdmi.c
+++ b/sound/pci/hda/patch_hdmi.c
@@ -1196,7 +1196,7 @@ static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
 
         _snd_printd(SND_PR_VERBOSE,
                 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
-                codec->addr, pin_nid, eld->monitor_present, eld->eld_valid);
+                codec->addr, pin_nid, pin_eld->monitor_present, eld->eld_valid);
 
         if (eld->eld_valid) {
                 if (snd_hdmi_get_eld(codec, pin_nid, eld->eld_buffer,
diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c
index 563c24df4d6f..f15c36bde540 100644
--- a/sound/pci/hda/patch_realtek.c
+++ b/sound/pci/hda/patch_realtek.c
@@ -3440,7 +3440,8 @@ static int alc662_parse_auto_config(struct hda_codec *codec)
         const hda_nid_t *ssids;
 
         if (codec->vendor_id == 0x10ec0272 || codec->vendor_id == 0x10ec0663 ||
-            codec->vendor_id == 0x10ec0665 || codec->vendor_id == 0x10ec0670)
+            codec->vendor_id == 0x10ec0665 || codec->vendor_id == 0x10ec0670 ||
+            codec->vendor_id == 0x10ec0671)
                 ssids = alc663_ssids;
         else
                 ssids = alc662_ssids;
@@ -3894,6 +3895,7 @@ static const struct hda_codec_preset snd_hda_preset_realtek[] = {
         { .id = 0x10ec0665, .name = "ALC665", .patch = patch_alc662 },
         { .id = 0x10ec0668, .name = "ALC668", .patch = patch_alc662 },
         { .id = 0x10ec0670, .name = "ALC670", .patch = patch_alc662 },
+        { .id = 0x10ec0671, .name = "ALC671", .patch = patch_alc662 },
         { .id = 0x10ec0680, .name = "ALC680", .patch = patch_alc680 },
         { .id = 0x10ec0880, .name = "ALC880", .patch = patch_alc880 },
         { .id = 0x10ec0882, .name = "ALC882", .patch = patch_alc882 },
diff --git a/sound/soc/codecs/max98090.c b/sound/soc/codecs/max98090.c
index fc176044994d..fc176044994d 100755..100644
--- a/sound/soc/codecs/max98090.c
+++ b/sound/soc/codecs/max98090.c
diff --git a/sound/soc/codecs/max98090.h b/sound/soc/codecs/max98090.h
index 7e103f249053..7e103f249053 100755..100644
--- a/sound/soc/codecs/max98090.h
+++ b/sound/soc/codecs/max98090.h
diff --git a/sound/soc/codecs/si476x.c b/sound/soc/codecs/si476x.c
index f2d61a187830..566ea3256e2d 100644
--- a/sound/soc/codecs/si476x.c
+++ b/sound/soc/codecs/si476x.c
@@ -159,6 +159,7 @@ static int si476x_codec_hw_params(struct snd_pcm_substream *substream,
         switch (params_format(params)) {
         case SNDRV_PCM_FORMAT_S8:
                 width = SI476X_PCM_FORMAT_S8;
+                break;
         case SNDRV_PCM_FORMAT_S16_LE:
                 width = SI476X_PCM_FORMAT_S16_LE;
                 break;
diff --git a/sound/soc/codecs/wm_adsp.c b/sound/soc/codecs/wm_adsp.c
index f3f7e75f8628..9af1bddc4c62 100644
--- a/sound/soc/codecs/wm_adsp.c
+++ b/sound/soc/codecs/wm_adsp.c
@@ -828,7 +828,8 @@ static int wm_adsp_load_coeff(struct wm_adsp *dsp)
                                                 &buf_list);
                         if (!buf) {
                                 adsp_err(dsp, "Out of memory\n");
-                                return -ENOMEM;
+                                ret = -ENOMEM;
+                                goto out_fw;
                         }
 
                         adsp_dbg(dsp, "%s.%d: Writing %d bytes at %x\n",
@@ -865,7 +866,7 @@ out_fw:
         wm_adsp_buf_free(&buf_list);
 out:
         kfree(file);
-        return 0;
+        return ret;
 }
 
 int wm_adsp1_init(struct wm_adsp *adsp)
diff --git a/sound/soc/fsl/imx-ssi.c b/sound/soc/fsl/imx-ssi.c
index 55464a5b0706..810c7eeb7b03 100644
--- a/sound/soc/fsl/imx-ssi.c
+++ b/sound/soc/fsl/imx-ssi.c
@@ -496,6 +496,8 @@ static void imx_ssi_ac97_reset(struct snd_ac97 *ac97)
 
         if (imx_ssi->ac97_reset)
                 imx_ssi->ac97_reset(ac97);
+        /* First read sometimes fails, do a dummy read */
+        imx_ssi_ac97_read(ac97, 0);
 }
 
 static void imx_ssi_ac97_warm_reset(struct snd_ac97 *ac97)
@@ -504,6 +506,9 @@ static void imx_ssi_ac97_warm_reset(struct snd_ac97 *ac97)
 
         if (imx_ssi->ac97_warm_reset)
                 imx_ssi->ac97_warm_reset(ac97);
+
+        /* First read sometimes fails, do a dummy read */
+        imx_ssi_ac97_read(ac97, 0);
 }
 
 struct snd_ac97_bus_ops soc_ac97_ops = {
diff --git a/sound/soc/fsl/pcm030-audio-fabric.c b/sound/soc/fsl/pcm030-audio-fabric.c
index 8e52c1485df3..eb4373840bb6 100644
--- a/sound/soc/fsl/pcm030-audio-fabric.c
+++ b/sound/soc/fsl/pcm030-audio-fabric.c
@@ -51,7 +51,7 @@ static struct snd_soc_card pcm030_card = {
         .num_links = ARRAY_SIZE(pcm030_fabric_dai),
 };
 
-static int __init pcm030_fabric_probe(struct platform_device *op)
+static int pcm030_fabric_probe(struct platform_device *op)
 {
         struct device_node *np = op->dev.of_node;
         struct device_node *platform_np;
diff --git a/sound/soc/sh/dma-sh7760.c b/sound/soc/sh/dma-sh7760.c
index 19eff8fc4fdd..1a8b03e4b41b 100644
--- a/sound/soc/sh/dma-sh7760.c
+++ b/sound/soc/sh/dma-sh7760.c
@@ -342,8 +342,8 @@ static int camelot_pcm_new(struct snd_soc_pcm_runtime *rtd)
         return 0;
 }
 
-static struct snd_soc_platform sh7760_soc_platform = {
-        .pcm_ops        = &camelot_pcm_ops,
+static struct snd_soc_platform_driver sh7760_soc_platform = {
+        .ops            = &camelot_pcm_ops,
         .pcm_new        = camelot_pcm_new,
         .pcm_free       = camelot_pcm_free,
 };
diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c
index b7e84a7cd9ee..507d251916af 100644
--- a/sound/soc/soc-core.c
+++ b/sound/soc/soc-core.c
@@ -3140,7 +3140,7 @@ int snd_soc_bytes_put(struct snd_kcontrol *kcontrol,
         if (params->mask) {
                 ret = regmap_read(codec->control_data, params->base, &val);
                 if (ret != 0)
-                        return ret;
+                        goto out;
 
                 val &= params->mask;
 
@@ -3158,13 +3158,15 @@ int snd_soc_bytes_put(struct snd_kcontrol *kcontrol,
                         ((u32 *)data)[0] |= cpu_to_be32(val);
                         break;
                 default:
-                        return -EINVAL;
+                        ret = -EINVAL;
+                        goto out;
                 }
         }
 
         ret = regmap_raw_write(codec->control_data, params->base,
                                data, len);
 
+out:
         kfree(data);
 
         return ret;
@@ -4197,7 +4199,6 @@ int snd_soc_of_parse_audio_routing(struct snd_soc_card *card,
                         dev_err(card->dev,
                                 "ASoC: Property '%s' index %d could not be read: %d\n",
                                 propname, 2 * i, ret);
-                        kfree(routes);
                         return -EINVAL;
                 }
                 ret = of_property_read_string_index(np, propname,
@@ -4206,7 +4207,6 @@ int snd_soc_of_parse_audio_routing(struct snd_soc_card *card,
                         dev_err(card->dev,
                                 "ASoC: Property '%s' index %d could not be read: %d\n",
                                 propname, (2 * i) + 1, ret);
-                        kfree(routes);
                         return -EINVAL;
                 }
         }
diff --git a/sound/soc/soc-dapm.c b/sound/soc/soc-dapm.c
index 1d6a9b3ceb27..d6d9ba2e6916 100644
--- a/sound/soc/soc-dapm.c
+++ b/sound/soc/soc-dapm.c
@@ -831,6 +831,9 @@ static int is_connected_output_ep(struct snd_soc_dapm_widget *widget,
                 if (path->weak)
                         continue;
 
+                if (path->walking)
+                        return 1;
+
                 if (path->walked)
                         continue;
 
@@ -838,6 +841,7 @@ static int is_connected_output_ep(struct snd_soc_dapm_widget *widget,
 
                 if (path->sink && path->connect) {
                         path->walked = 1;
+                        path->walking = 1;
 
                         /* do we need to add this widget to the list ? */
                         if (list) {
@@ -847,11 +851,14 @@ static int is_connected_output_ep(struct snd_soc_dapm_widget *widget,
                                         dev_err(widget->dapm->dev,
                                                 "ASoC: could not add widget %s\n",
                                                 widget->name);
+                                        path->walking = 0;
                                         return con;
                                 }
                         }
 
                         con += is_connected_output_ep(path->sink, list);
+
+                        path->walking = 0;
                 }
         }
 
@@ -931,6 +938,9 @@ static int is_connected_input_ep(struct snd_soc_dapm_widget *widget,
                 if (path->weak)
                         continue;
 
+                if (path->walking)
+                        return 1;
+
                 if (path->walked)
                         continue;
 
@@ -938,6 +948,7 @@ static int is_connected_input_ep(struct snd_soc_dapm_widget *widget,
 
                 if (path->source && path->connect) {
                         path->walked = 1;
+                        path->walking = 1;
 
                         /* do we need to add this widget to the list ? */
                         if (list) {
@@ -947,11 +958,14 @@ static int is_connected_input_ep(struct snd_soc_dapm_widget *widget,
                                         dev_err(widget->dapm->dev,
                                                 "ASoC: could not add widget %s\n",
                                                 widget->name);
+                                        path->walking = 0;
                                         return con;
                                 }
                         }
 
                         con += is_connected_input_ep(path->source, list);
+
+                        path->walking = 0;
                 }
         }
 
diff --git a/sound/soc/spear/spear_pcm.c b/sound/soc/spear/spear_pcm.c
index 9b76cc5a1148..5e7aebe1e664 100644
--- a/sound/soc/spear/spear_pcm.c
+++ b/sound/soc/spear/spear_pcm.c
@@ -149,9 +149,9 @@ static void spear_pcm_free(struct snd_pcm *pcm)
 
 static u64 spear_pcm_dmamask = DMA_BIT_MASK(32);
 
-static int spear_pcm_new(struct snd_card *card,
-                struct snd_soc_dai *dai, struct snd_pcm *pcm)
+static int spear_pcm_new(struct snd_soc_pcm_runtime *rtd)
 {
+        struct snd_card *card = rtd->card->snd_card;
         int ret;
 
         if (!card->dev->dma_mask)
@@ -159,16 +159,16 @@ static int spear_pcm_new(struct snd_card *card,
         if (!card->dev->coherent_dma_mask)
                 card->dev->coherent_dma_mask = DMA_BIT_MASK(32);
 
-        if (dai->driver->playback.channels_min) {
-                ret = spear_pcm_preallocate_dma_buffer(pcm,
+        if (rtd->cpu_dai->driver->playback.channels_min) {
+                ret = spear_pcm_preallocate_dma_buffer(rtd->pcm,
                                 SNDRV_PCM_STREAM_PLAYBACK,
                                 spear_pcm_hardware.buffer_bytes_max);
                 if (ret)
                         return ret;
         }
 
-        if (dai->driver->capture.channels_min) {
-                ret = spear_pcm_preallocate_dma_buffer(pcm,
+        if (rtd->cpu_dai->driver->capture.channels_min) {
+                ret = spear_pcm_preallocate_dma_buffer(rtd->pcm,
                                 SNDRV_PCM_STREAM_CAPTURE,
                                 spear_pcm_hardware.buffer_bytes_max);
                 if (ret)
diff --git a/sound/usb/clock.c b/sound/usb/clock.c
index 5e634a2eb282..9e2703a25156 100644
--- a/sound/usb/clock.c
+++ b/sound/usb/clock.c
@@ -253,7 +253,7 @@ static int set_sample_rate_v2(struct snd_usb_audio *chip, int iface,
 {
         struct usb_device *dev = chip->dev;
         unsigned char data[4];
-        int err, crate;
+        int err, cur_rate, prev_rate;
         int clock = snd_usb_clock_find_source(chip, fmt->clock);
 
         if (clock < 0)
@@ -266,6 +266,19 @@ static int set_sample_rate_v2(struct snd_usb_audio *chip, int iface,
                 return -ENXIO;
         }
 
+        err = snd_usb_ctl_msg(dev, usb_rcvctrlpipe(dev, 0), UAC2_CS_CUR,
+                              USB_TYPE_CLASS | USB_RECIP_INTERFACE | USB_DIR_IN,
+                              UAC2_CS_CONTROL_SAM_FREQ << 8,
+                              snd_usb_ctrl_intf(chip) | (clock << 8),
+                              data, sizeof(data));
+        if (err < 0) {
+                snd_printk(KERN_WARNING "%d:%d:%d: cannot get freq (v2)\n",
+                           dev->devnum, iface, fmt->altsetting);
+                prev_rate = 0;
+        } else {
+                prev_rate = data[0] | (data[1] << 8) | (data[2] << 16) | (data[3] << 24);
+        }
+
         data[0] = rate;
         data[1] = rate >> 8;
         data[2] = rate >> 16;
@@ -280,19 +293,31 @@ static int set_sample_rate_v2(struct snd_usb_audio *chip, int iface,
                 return err;
         }
 
-        if ((err = snd_usb_ctl_msg(dev, usb_rcvctrlpipe(dev, 0), UAC2_CS_CUR,
-                                   USB_TYPE_CLASS | USB_RECIP_INTERFACE | USB_DIR_IN,
-                                   UAC2_CS_CONTROL_SAM_FREQ << 8,
-                                   snd_usb_ctrl_intf(chip) | (clock << 8),
-                                   data, sizeof(data))) < 0) {
+        err = snd_usb_ctl_msg(dev, usb_rcvctrlpipe(dev, 0), UAC2_CS_CUR,
+                              USB_TYPE_CLASS | USB_RECIP_INTERFACE | USB_DIR_IN,
+                              UAC2_CS_CONTROL_SAM_FREQ << 8,
+                              snd_usb_ctrl_intf(chip) | (clock << 8),
+                              data, sizeof(data));
+        if (err < 0) {
                 snd_printk(KERN_WARNING "%d:%d:%d: cannot get freq (v2)\n",
                            dev->devnum, iface, fmt->altsetting);
-                return err;
+                cur_rate = 0;
+        } else {
+                cur_rate = data[0] | (data[1] << 8) | (data[2] << 16) | (data[3] << 24);
         }
 
-        crate = data[0] | (data[1] << 8) | (data[2] << 16) | (data[3] << 24);
-        if (crate != rate)
-                snd_printd(KERN_WARNING "current rate %d is different from the runtime rate %d\n", crate, rate);
+        if (cur_rate != rate) {
+                snd_printd(KERN_WARNING
+                           "current rate %d is different from the runtime rate %d\n",
+                           cur_rate, rate);
+        }
+
+        /* Some devices doesn't respond to sample rate changes while the
+         * interface is active. */
+        if (rate != prev_rate) {
+                usb_set_interface(dev, iface, 0);
+                usb_set_interface(dev, iface, fmt->altsetting);
+        }
 
         return 0;
 }
diff --git a/virt/kvm/kvm_main.c b/virt/kvm/kvm_main.c
index adc68feb5c5a..f18013f09e68 100644
--- a/virt/kvm/kvm_main.c
+++ b/virt/kvm/kvm_main.c
@@ -1541,21 +1541,38 @@ int kvm_write_guest(struct kvm *kvm, gpa_t gpa, const void *data,
 }
 
 int kvm_gfn_to_hva_cache_init(struct kvm *kvm, struct gfn_to_hva_cache *ghc,
-                              gpa_t gpa)
+                              gpa_t gpa, unsigned long len)
 {
         struct kvm_memslots *slots = kvm_memslots(kvm);
         int offset = offset_in_page(gpa);
-        gfn_t gfn = gpa >> PAGE_SHIFT;
+        gfn_t start_gfn = gpa >> PAGE_SHIFT;
+        gfn_t end_gfn = (gpa + len - 1) >> PAGE_SHIFT;
+        gfn_t nr_pages_needed = end_gfn - start_gfn + 1;
+        gfn_t nr_pages_avail;
 
         ghc->gpa = gpa;
         ghc->generation = slots->generation;
-        ghc->memslot = gfn_to_memslot(kvm, gfn);
-        ghc->hva = gfn_to_hva_many(ghc->memslot, gfn, NULL);
-        if (!kvm_is_error_hva(ghc->hva))
+        ghc->len = len;
+        ghc->memslot = gfn_to_memslot(kvm, start_gfn);
+        ghc->hva = gfn_to_hva_many(ghc->memslot, start_gfn, &nr_pages_avail);
+        if (!kvm_is_error_hva(ghc->hva) && nr_pages_avail >= nr_pages_needed) {
                 ghc->hva += offset;
-        else
-                return -EFAULT;
-
+        } else {
+                /*
+                 * If the requested region crosses two memslots, we still
+                 * verify that the entire region is valid here.
+                 */
+                while (start_gfn <= end_gfn) {
+                        ghc->memslot = gfn_to_memslot(kvm, start_gfn);
+                        ghc->hva = gfn_to_hva_many(ghc->memslot, start_gfn,
+                                                   &nr_pages_avail);
+                        if (kvm_is_error_hva(ghc->hva))
+                                return -EFAULT;
+                        start_gfn += nr_pages_avail;
+                }
+                /* Use the slow path for cross page reads and writes. */
+                ghc->memslot = NULL;
+        }
         return 0;
 }
 EXPORT_SYMBOL_GPL(kvm_gfn_to_hva_cache_init);
@@ -1566,8 +1583,13 @@ int kvm_write_guest_cached(struct kvm *kvm, struct gfn_to_hva_cache *ghc,
         struct kvm_memslots *slots = kvm_memslots(kvm);
         int r;
 
+        BUG_ON(len > ghc->len);
+
         if (slots->generation != ghc->generation)
-                kvm_gfn_to_hva_cache_init(kvm, ghc, ghc->gpa);
+                kvm_gfn_to_hva_cache_init(kvm, ghc, ghc->gpa, ghc->len);
+
+        if (unlikely(!ghc->memslot))
+                return kvm_write_guest(kvm, ghc->gpa, data, len);
 
         if (kvm_is_error_hva(ghc->hva))
                 return -EFAULT;
@@ -1587,8 +1609,13 @@ int kvm_read_guest_cached(struct kvm *kvm, struct gfn_to_hva_cache *ghc,
         struct kvm_memslots *slots = kvm_memslots(kvm);
         int r;
 
+        BUG_ON(len > ghc->len);
+
         if (slots->generation != ghc->generation)
-                kvm_gfn_to_hva_cache_init(kvm, ghc, ghc->gpa);
+                kvm_gfn_to_hva_cache_init(kvm, ghc, ghc->gpa, ghc->len);
+
+        if (unlikely(!ghc->memslot))
+                return kvm_read_guest(kvm, ghc->gpa, data, len);
 
         if (kvm_is_error_hva(ghc->hva))
                 return -EFAULT;