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-rw-r--r--drivers/net/igb/e1000_82575.c64
-rw-r--r--drivers/net/igb/e1000_82575.h1
-rw-r--r--drivers/net/igb/e1000_mac.c82
-rw-r--r--drivers/net/igb/e1000_mac.h4
-rw-r--r--drivers/net/igb/e1000_regs.h3
5 files changed, 0 insertions, 154 deletions
diff --git a/drivers/net/igb/e1000_82575.c b/drivers/net/igb/e1000_82575.c
index 76f9f866f8c7..bb823acc7443 100644
--- a/drivers/net/igb/e1000_82575.c
+++ b/drivers/net/igb/e1000_82575.c
@@ -1238,70 +1238,6 @@ out:
1238} 1238}
1239 1239
1240/** 1240/**
1241 * igb_translate_register_82576 - Translate the proper register offset
1242 * @reg: e1000 register to be read
1243 *
1244 * Registers in 82576 are located in different offsets than other adapters
1245 * even though they function in the same manner. This function takes in
1246 * the name of the register to read and returns the correct offset for
1247 * 82576 silicon.
1248 **/
1249u32 igb_translate_register_82576(u32 reg)
1250{
1251 /*
1252 * Some of the 82576 registers are located at different
1253 * offsets than they are in older adapters.
1254 * Despite the difference in location, the registers
1255 * function in the same manner.
1256 */
1257 switch (reg) {
1258 case E1000_TDBAL(0):
1259 reg = 0x0E000;
1260 break;
1261 case E1000_TDBAH(0):
1262 reg = 0x0E004;
1263 break;
1264 case E1000_TDLEN(0):
1265 reg = 0x0E008;
1266 break;
1267 case E1000_TDH(0):
1268 reg = 0x0E010;
1269 break;
1270 case E1000_TDT(0):
1271 reg = 0x0E018;
1272 break;
1273 case E1000_TXDCTL(0):
1274 reg = 0x0E028;
1275 break;
1276 case E1000_RDBAL(0):
1277 reg = 0x0C000;
1278 break;
1279 case E1000_RDBAH(0):
1280 reg = 0x0C004;
1281 break;
1282 case E1000_RDLEN(0):
1283 reg = 0x0C008;
1284 break;
1285 case E1000_RDH(0):
1286 reg = 0x0C010;
1287 break;
1288 case E1000_RDT(0):
1289 reg = 0x0C018;
1290 break;
1291 case E1000_RXDCTL(0):
1292 reg = 0x0C028;
1293 break;
1294 case E1000_SRRCTL(0):
1295 reg = 0x0C00C;
1296 break;
1297 default:
1298 break;
1299 }
1300
1301 return reg;
1302}
1303
1304/**
1305 * igb_reset_init_script_82575 - Inits HW defaults after reset 1241 * igb_reset_init_script_82575 - Inits HW defaults after reset
1306 * @hw: pointer to the HW structure 1242 * @hw: pointer to the HW structure
1307 * 1243 *
diff --git a/drivers/net/igb/e1000_82575.h b/drivers/net/igb/e1000_82575.h
index 2f848e578a24..c1928b5efe1f 100644
--- a/drivers/net/igb/e1000_82575.h
+++ b/drivers/net/igb/e1000_82575.h
@@ -28,7 +28,6 @@
28#ifndef _E1000_82575_H_ 28#ifndef _E1000_82575_H_
29#define _E1000_82575_H_ 29#define _E1000_82575_H_
30 30
31u32 igb_translate_register_82576(u32 reg);
32void igb_update_mc_addr_list_82575(struct e1000_hw*, u8*, u32, u32, u32); 31void igb_update_mc_addr_list_82575(struct e1000_hw*, u8*, u32, u32, u32);
33extern void igb_shutdown_fiber_serdes_link_82575(struct e1000_hw *hw); 32extern void igb_shutdown_fiber_serdes_link_82575(struct e1000_hw *hw);
34extern void igb_rx_fifo_flush_82575(struct e1000_hw *hw); 33extern void igb_rx_fifo_flush_82575(struct e1000_hw *hw);
diff --git a/drivers/net/igb/e1000_mac.c b/drivers/net/igb/e1000_mac.c
index 9b0f0afdaeb8..e18747c70bec 100644
--- a/drivers/net/igb/e1000_mac.c
+++ b/drivers/net/igb/e1000_mac.c
@@ -144,34 +144,6 @@ void igb_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)
144} 144}
145 145
146/** 146/**
147 * igb_init_rx_addrs - Initialize receive address's
148 * @hw: pointer to the HW structure
149 * @rar_count: receive address registers
150 *
151 * Setups the receive address registers by setting the base receive address
152 * register to the devices MAC address and clearing all the other receive
153 * address registers to 0.
154 **/
155void igb_init_rx_addrs(struct e1000_hw *hw, u16 rar_count)
156{
157 u32 i;
158
159 /* Setup the receive address */
160 hw_dbg("Programming MAC Address into RAR[0]\n");
161
162 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
163
164 /* Zero out the other (rar_entry_count - 1) receive addresses */
165 hw_dbg("Clearing RAR[1-%u]\n", rar_count-1);
166 for (i = 1; i < rar_count; i++) {
167 array_wr32(E1000_RA, (i << 1), 0);
168 wrfl();
169 array_wr32(E1000_RA, ((i << 1) + 1), 0);
170 wrfl();
171 }
172}
173
174/**
175 * igb_check_alt_mac_addr - Check for alternate MAC addr 147 * igb_check_alt_mac_addr - Check for alternate MAC addr
176 * @hw: pointer to the HW structure 148 * @hw: pointer to the HW structure
177 * 149 *
@@ -297,60 +269,6 @@ void igb_mta_set(struct e1000_hw *hw, u32 hash_value)
297} 269}
298 270
299/** 271/**
300 * igb_update_mc_addr_list - Update Multicast addresses
301 * @hw: pointer to the HW structure
302 * @mc_addr_list: array of multicast addresses to program
303 * @mc_addr_count: number of multicast addresses to program
304 * @rar_used_count: the first RAR register free to program
305 * @rar_count: total number of supported Receive Address Registers
306 *
307 * Updates the Receive Address Registers and Multicast Table Array.
308 * The caller must have a packed mc_addr_list of multicast addresses.
309 * The parameter rar_count will usually be hw->mac.rar_entry_count
310 * unless there are workarounds that change this.
311 **/
312void igb_update_mc_addr_list(struct e1000_hw *hw,
313 u8 *mc_addr_list, u32 mc_addr_count,
314 u32 rar_used_count, u32 rar_count)
315{
316 u32 hash_value;
317 u32 i;
318
319 /*
320 * Load the first set of multicast addresses into the exact
321 * filters (RAR). If there are not enough to fill the RAR
322 * array, clear the filters.
323 */
324 for (i = rar_used_count; i < rar_count; i++) {
325 if (mc_addr_count) {
326 hw->mac.ops.rar_set(hw, mc_addr_list, i);
327 mc_addr_count--;
328 mc_addr_list += ETH_ALEN;
329 } else {
330 array_wr32(E1000_RA, i << 1, 0);
331 wrfl();
332 array_wr32(E1000_RA, (i << 1) + 1, 0);
333 wrfl();
334 }
335 }
336
337 /* Clear the old settings from the MTA */
338 hw_dbg("Clearing MTA\n");
339 for (i = 0; i < hw->mac.mta_reg_count; i++) {
340 array_wr32(E1000_MTA, i, 0);
341 wrfl();
342 }
343
344 /* Load any remaining multicast addresses into the hash table. */
345 for (; mc_addr_count > 0; mc_addr_count--) {
346 hash_value = igb_hash_mc_addr(hw, mc_addr_list);
347 hw_dbg("Hash value = 0x%03X\n", hash_value);
348 igb_mta_set(hw, hash_value);
349 mc_addr_list += ETH_ALEN;
350 }
351}
352
353/**
354 * igb_hash_mc_addr - Generate a multicast hash value 272 * igb_hash_mc_addr - Generate a multicast hash value
355 * @hw: pointer to the HW structure 273 * @hw: pointer to the HW structure
356 * @mc_addr: pointer to a multicast address 274 * @mc_addr: pointer to a multicast address
diff --git a/drivers/net/igb/e1000_mac.h b/drivers/net/igb/e1000_mac.h
index c2a9365ee040..cbee6af7d912 100644
--- a/drivers/net/igb/e1000_mac.h
+++ b/drivers/net/igb/e1000_mac.h
@@ -51,9 +51,6 @@ s32 igb_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed,
51 u16 *duplex); 51 u16 *duplex);
52s32 igb_id_led_init(struct e1000_hw *hw); 52s32 igb_id_led_init(struct e1000_hw *hw);
53s32 igb_led_off(struct e1000_hw *hw); 53s32 igb_led_off(struct e1000_hw *hw);
54void igb_update_mc_addr_list(struct e1000_hw *hw,
55 u8 *mc_addr_list, u32 mc_addr_count,
56 u32 rar_used_count, u32 rar_count);
57s32 igb_setup_link(struct e1000_hw *hw); 54s32 igb_setup_link(struct e1000_hw *hw);
58s32 igb_validate_mdi_setting(struct e1000_hw *hw); 55s32 igb_validate_mdi_setting(struct e1000_hw *hw);
59s32 igb_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg, 56s32 igb_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg,
@@ -62,7 +59,6 @@ s32 igb_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg,
62void igb_clear_hw_cntrs_base(struct e1000_hw *hw); 59void igb_clear_hw_cntrs_base(struct e1000_hw *hw);
63void igb_clear_vfta(struct e1000_hw *hw); 60void igb_clear_vfta(struct e1000_hw *hw);
64void igb_config_collision_dist(struct e1000_hw *hw); 61void igb_config_collision_dist(struct e1000_hw *hw);
65void igb_init_rx_addrs(struct e1000_hw *hw, u16 rar_count);
66void igb_mta_set(struct e1000_hw *hw, u32 hash_value); 62void igb_mta_set(struct e1000_hw *hw, u32 hash_value);
67void igb_put_hw_semaphore(struct e1000_hw *hw); 63void igb_put_hw_semaphore(struct e1000_hw *hw);
68void igb_rar_set(struct e1000_hw *hw, u8 *addr, u32 index); 64void igb_rar_set(struct e1000_hw *hw, u8 *addr, u32 index);
diff --git a/drivers/net/igb/e1000_regs.h b/drivers/net/igb/e1000_regs.h
index b95093d24c09..95523af26056 100644
--- a/drivers/net/igb/e1000_regs.h
+++ b/drivers/net/igb/e1000_regs.h
@@ -262,9 +262,6 @@
262#define E1000_RETA(_i) (0x05C00 + ((_i) * 4)) 262#define E1000_RETA(_i) (0x05C00 + ((_i) * 4))
263#define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW Array */ 263#define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW Array */
264 264
265#define E1000_REGISTER(a, reg) (((a)->mac.type < e1000_82576) \
266 ? reg : e1000_translate_register_82576(reg))
267
268#define wr32(reg, value) (writel(value, hw->hw_addr + reg)) 265#define wr32(reg, value) (writel(value, hw->hw_addr + reg))
269#define rd32(reg) (readl(hw->hw_addr + reg)) 266#define rd32(reg) (readl(hw->hw_addr + reg))
270#define wrfl() ((void)rd32(E1000_STATUS)) 267#define wrfl() ((void)rd32(E1000_STATUS))