diff options
-rw-r--r-- | drivers/net/sky2.c | 13 | ||||
-rw-r--r-- | drivers/net/sky2.h | 9 |
2 files changed, 13 insertions, 9 deletions
diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c index 79d62ae8d7cd..71722f53f2b4 100644 --- a/drivers/net/sky2.c +++ b/drivers/net/sky2.c | |||
@@ -677,17 +677,15 @@ static void sky2_mac_init(struct sky2_hw *hw, unsigned port) | |||
677 | /* Flush Rx MAC FIFO on any flow control or error */ | 677 | /* Flush Rx MAC FIFO on any flow control or error */ |
678 | sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR); | 678 | sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR); |
679 | 679 | ||
680 | /* Set threshold to 0xa (64 bytes) | 680 | /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */ |
681 | * ASF disabled so no need to do WA dev #4.30 | 681 | sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1); |
682 | */ | ||
683 | sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF); | ||
684 | 682 | ||
685 | /* Configure Tx MAC FIFO */ | 683 | /* Configure Tx MAC FIFO */ |
686 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR); | 684 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR); |
687 | sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); | 685 | sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); |
688 | 686 | ||
689 | if (hw->chip_id == CHIP_ID_YUKON_EC_U) { | 687 | if (hw->chip_id == CHIP_ID_YUKON_EC_U) { |
690 | sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 512/8); | 688 | sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8); |
691 | sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8); | 689 | sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8); |
692 | if (hw->dev[port]->mtu > ETH_DATA_LEN) { | 690 | if (hw->dev[port]->mtu > ETH_DATA_LEN) { |
693 | /* set Tx GMAC FIFO Almost Empty Threshold */ | 691 | /* set Tx GMAC FIFO Almost Empty Threshold */ |
@@ -1061,7 +1059,8 @@ static int sky2_rx_start(struct sky2_port *sky2) | |||
1061 | sky2->rx_put = sky2->rx_next = 0; | 1059 | sky2->rx_put = sky2->rx_next = 0; |
1062 | sky2_qset(hw, rxq); | 1060 | sky2_qset(hw, rxq); |
1063 | 1061 | ||
1064 | if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) { | 1062 | if (hw->chip_id == CHIP_ID_YUKON_EC_U && |
1063 | (hw->chip_rev == CHIP_REV_YU_EC_U_A1 || hw->chip_rev == CHIP_REV_YU_EC_U_B0)) { | ||
1065 | /* MAC Rx RAM Read is controlled by hardware */ | 1064 | /* MAC Rx RAM Read is controlled by hardware */ |
1066 | sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS); | 1065 | sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS); |
1067 | } | 1066 | } |
@@ -1510,7 +1509,7 @@ static int sky2_down(struct net_device *dev) | |||
1510 | 1509 | ||
1511 | /* WA for dev. #4.209 */ | 1510 | /* WA for dev. #4.209 */ |
1512 | if (hw->chip_id == CHIP_ID_YUKON_EC_U | 1511 | if (hw->chip_id == CHIP_ID_YUKON_EC_U |
1513 | && hw->chip_rev == CHIP_REV_YU_EC_U_A1) | 1512 | && (hw->chip_rev == CHIP_REV_YU_EC_U_A1 || hw->chip_rev == CHIP_REV_YU_EC_U_B0)) |
1514 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), | 1513 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), |
1515 | sky2->speed != SPEED_1000 ? | 1514 | sky2->speed != SPEED_1000 ? |
1516 | TX_STFW_ENA : TX_STFW_DIS); | 1515 | TX_STFW_ENA : TX_STFW_DIS); |
diff --git a/drivers/net/sky2.h b/drivers/net/sky2.h index 6d2a23f66c9a..c551ec32e63d 100644 --- a/drivers/net/sky2.h +++ b/drivers/net/sky2.h | |||
@@ -383,8 +383,13 @@ enum { | |||
383 | CHIP_REV_YU_EC_A2 = 1, /* Chip Rev. for Yukon-EC A2 */ | 383 | CHIP_REV_YU_EC_A2 = 1, /* Chip Rev. for Yukon-EC A2 */ |
384 | CHIP_REV_YU_EC_A3 = 2, /* Chip Rev. for Yukon-EC A3 */ | 384 | CHIP_REV_YU_EC_A3 = 2, /* Chip Rev. for Yukon-EC A3 */ |
385 | 385 | ||
386 | CHIP_REV_YU_EC_U_A0 = 0, | 386 | CHIP_REV_YU_EC_U_A0 = 1, |
387 | CHIP_REV_YU_EC_U_A1 = 1, | 387 | CHIP_REV_YU_EC_U_A1 = 2, |
388 | CHIP_REV_YU_EC_U_B0 = 3, | ||
389 | |||
390 | CHIP_REV_YU_FE_A1 = 1, | ||
391 | CHIP_REV_YU_FE_A2 = 2, | ||
392 | |||
388 | }; | 393 | }; |
389 | 394 | ||
390 | /* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */ | 395 | /* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */ |