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-rw-r--r--Documentation/arm/Samsung-S3C24XX/GPIO.txt10
-rw-r--r--arch/arm/common/Kconfig7
-rw-r--r--arch/arm/common/vic.c221
-rw-r--r--arch/arm/include/asm/hardware/pl080.h138
-rw-r--r--arch/arm/include/asm/hardware/vic.h2
-rw-r--r--arch/arm/mach-ep93xx/core.c4
-rw-r--r--arch/arm/mach-netx/generic.c2
-rw-r--r--arch/arm/mach-s3c2400/gpio.c6
-rw-r--r--arch/arm/mach-s3c2410/Kconfig8
-rw-r--r--arch/arm/mach-s3c2410/dma.c4
-rw-r--r--arch/arm/mach-s3c2410/gpio.c6
-rw-r--r--arch/arm/mach-s3c2410/h1940-bluetooth.c26
-rw-r--r--arch/arm/mach-s3c2410/include/mach/dma.h265
-rw-r--r--arch/arm/mach-s3c2410/include/mach/gpio-core.h2
-rw-r--r--arch/arm/mach-s3c2410/include/mach/gpio-fns.h103
-rw-r--r--arch/arm/mach-s3c2410/include/mach/gpio-nrs.h70
-rw-r--r--arch/arm/mach-s3c2410/include/mach/gpio.h1
-rw-r--r--arch/arm/mach-s3c2410/include/mach/hardware.h95
-rw-r--r--arch/arm/mach-s3c2410/include/mach/map.h2
-rw-r--r--arch/arm/mach-s3c2410/include/mach/regs-gpio.h333
-rw-r--r--arch/arm/mach-s3c2410/include/mach/system-reset.h36
-rw-r--r--arch/arm/mach-s3c2410/mach-amlm5900.c5
-rw-r--r--arch/arm/mach-s3c2410/mach-bast.c10
-rw-r--r--arch/arm/mach-s3c2410/mach-h1940.c2
-rw-r--r--arch/arm/mach-s3c2410/mach-n30.c51
-rw-r--r--arch/arm/mach-s3c2410/mach-qt2410.c19
-rw-r--r--arch/arm/mach-s3c2410/mach-vr1000.c11
-rw-r--r--arch/arm/mach-s3c2410/pm.c5
-rw-r--r--arch/arm/mach-s3c2410/usb-simtec.c32
-rw-r--r--arch/arm/mach-s3c2412/Kconfig3
-rw-r--r--arch/arm/mach-s3c2412/dma.c3
-rw-r--r--arch/arm/mach-s3c2412/mach-jive.c43
-rw-r--r--arch/arm/mach-s3c2412/mach-smdk2413.c9
-rw-r--r--arch/arm/mach-s3c2440/Kconfig5
-rw-r--r--arch/arm/mach-s3c2440/dma.c4
-rw-r--r--arch/arm/mach-s3c2440/mach-anubis.c3
-rw-r--r--arch/arm/mach-s3c2440/mach-at2440evb.c2
-rw-r--r--arch/arm/mach-s3c2440/mach-nexcoder.c17
-rw-r--r--arch/arm/mach-s3c2440/mach-osiris.c9
-rw-r--r--arch/arm/mach-s3c2443/dma.c3
-rw-r--r--arch/arm/mach-s3c6400/Kconfig25
-rw-r--r--arch/arm/mach-s3c6400/Makefile10
-rw-r--r--arch/arm/mach-s3c6400/include/mach/dma.h59
-rw-r--r--arch/arm/mach-s3c6400/include/mach/map.h6
-rw-r--r--arch/arm/mach-s3c6400/include/mach/regs-clock.h16
-rw-r--r--arch/arm/mach-s3c6400/include/mach/system.h8
-rw-r--r--arch/arm/mach-s3c6400/mach-smdk6400.c96
-rw-r--r--arch/arm/mach-s3c6400/s3c6400.c89
-rw-r--r--arch/arm/mach-s3c6400/setup-sdhci.c63
-rw-r--r--arch/arm/mach-s3c6410/Kconfig37
-rw-r--r--arch/arm/mach-s3c6410/Makefile4
-rw-r--r--arch/arm/mach-s3c6410/cpu.c3
-rw-r--r--arch/arm/mach-s3c6410/mach-anw6410.c245
-rw-r--r--arch/arm/mach-s3c6410/mach-ncp.c107
-rw-r--r--arch/arm/mach-s3c6410/mach-smdk6410.c198
-rw-r--r--arch/arm/mach-s3c6410/setup-sdhci.c34
-rw-r--r--arch/arm/mach-versatile/core.c2
-rw-r--r--arch/arm/plat-s3c/Kconfig26
-rw-r--r--arch/arm/plat-s3c/Makefile7
-rw-r--r--arch/arm/plat-s3c/dev-usb-hsotg.c41
-rw-r--r--arch/arm/plat-s3c/dev-usb.c50
-rw-r--r--arch/arm/plat-s3c/dma.c86
-rw-r--r--arch/arm/plat-s3c/gpio.c11
-rw-r--r--arch/arm/plat-s3c/include/plat/adc.h10
-rw-r--r--arch/arm/plat-s3c/include/plat/clock.h1
-rw-r--r--arch/arm/plat-s3c/include/plat/cpu.h3
-rw-r--r--arch/arm/plat-s3c/include/plat/devs.h1
-rw-r--r--arch/arm/plat-s3c/include/plat/dma-core.h22
-rw-r--r--arch/arm/plat-s3c/include/plat/dma.h127
-rw-r--r--arch/arm/plat-s3c/include/plat/gpio-core.h30
-rw-r--r--arch/arm/plat-s3c/include/plat/pm.h15
-rw-r--r--arch/arm/plat-s3c/include/plat/regs-serial.h5
-rw-r--r--arch/arm/plat-s3c/include/plat/sdhci.h50
-rw-r--r--arch/arm/plat-s3c/include/plat/udc-hs.h29
-rw-r--r--arch/arm/plat-s3c/include/plat/watchdog-reset.h49
-rw-r--r--arch/arm/plat-s3c/pm-gpio.c380
-rw-r--r--arch/arm/plat-s3c/pm.c19
-rw-r--r--arch/arm/plat-s3c24xx/Kconfig1
-rw-r--r--arch/arm/plat-s3c24xx/adc.c11
-rw-r--r--arch/arm/plat-s3c24xx/common-smdk.c25
-rw-r--r--arch/arm/plat-s3c24xx/devs.c30
-rw-r--r--arch/arm/plat-s3c24xx/dma.c151
-rw-r--r--arch/arm/plat-s3c24xx/gpio.c34
-rw-r--r--arch/arm/plat-s3c24xx/gpiolib.c50
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/dma-plat.h (renamed from arch/arm/plat-s3c24xx/include/plat/dma.h)12
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/map.h1
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/pm-core.h5
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/regs-dma.h145
-rw-r--r--arch/arm/plat-s3c24xx/pm.c222
-rw-r--r--arch/arm/plat-s3c24xx/setup-i2c.c5
-rw-r--r--arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c20
-rw-r--r--arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c20
-rw-r--r--arch/arm/plat-s3c64xx/Kconfig10
-rw-r--r--arch/arm/plat-s3c64xx/Makefile11
-rw-r--r--arch/arm/plat-s3c64xx/clock.c19
-rw-r--r--arch/arm/plat-s3c64xx/cpu.c32
-rw-r--r--arch/arm/plat-s3c64xx/dma.c722
-rw-r--r--arch/arm/plat-s3c64xx/gpiolib.c10
-rw-r--r--arch/arm/plat-s3c64xx/include/plat/dma-plat.h70
-rw-r--r--arch/arm/plat-s3c64xx/include/plat/irqs.h1
-rw-r--r--arch/arm/plat-s3c64xx/include/plat/pm-core.h98
-rw-r--r--arch/arm/plat-s3c64xx/include/plat/regs-clock.h1
-rw-r--r--arch/arm/plat-s3c64xx/include/plat/s3c6400.h3
-rw-r--r--arch/arm/plat-s3c64xx/irq-eint.c3
-rw-r--r--arch/arm/plat-s3c64xx/irq-pm.c111
-rw-r--r--arch/arm/plat-s3c64xx/irq.c9
-rw-r--r--arch/arm/plat-s3c64xx/pm.c175
-rw-r--r--arch/arm/plat-s3c64xx/s3c6400-clock.c106
-rw-r--r--arch/arm/plat-s3c64xx/setup-sdhci-gpio.c55
-rw-r--r--arch/arm/plat-s3c64xx/sleep.S144
-rw-r--r--drivers/leds/leds-h1940.c2
-rw-r--r--drivers/leds/leds-s3c24xx.c1
-rw-r--r--drivers/mmc/host/s3cmci.c5
-rw-r--r--drivers/spi/spi_s3c24xx_gpio.c1
-rw-r--r--sound/soc/s3c24xx/s3c2412-i2s.c1
-rw-r--r--sound/soc/s3c24xx/s3c2443-ac97.c1
-rw-r--r--sound/soc/s3c24xx/s3c24xx-i2s.c2
-rw-r--r--sound/soc/s3c24xx/s3c24xx-pcm.c21
118 files changed, 4529 insertions, 1358 deletions
diff --git a/Documentation/arm/Samsung-S3C24XX/GPIO.txt b/Documentation/arm/Samsung-S3C24XX/GPIO.txt
index ea7ccfc4b274..948c8718d967 100644
--- a/Documentation/arm/Samsung-S3C24XX/GPIO.txt
+++ b/Documentation/arm/Samsung-S3C24XX/GPIO.txt
@@ -51,7 +51,7 @@ PIN Numbers
51----------- 51-----------
52 52
53 Each pin has an unique number associated with it in regs-gpio.h, 53 Each pin has an unique number associated with it in regs-gpio.h,
54 eg S3C2410_GPA0 or S3C2410_GPF1. These defines are used to tell 54 eg S3C2410_GPA(0) or S3C2410_GPF(1). These defines are used to tell
55 the GPIO functions which pin is to be used. 55 the GPIO functions which pin is to be used.
56 56
57 57
@@ -65,11 +65,11 @@ Configuring a pin
65 65
66 Eg: 66 Eg:
67 67
68 s3c2410_gpio_cfgpin(S3C2410_GPA0, S3C2410_GPA0_ADDR0); 68 s3c2410_gpio_cfgpin(S3C2410_GPA(0), S3C2410_GPA0_ADDR0);
69 s3c2410_gpio_cfgpin(S3C2410_GPE8, S3C2410_GPE8_SDDAT1); 69 s3c2410_gpio_cfgpin(S3C2410_GPE(8), S3C2410_GPE8_SDDAT1);
70 70
71 which would turn GPA0 into the lowest Address line A0, and set 71 which would turn GPA(0) into the lowest Address line A0, and set
72 GPE8 to be connected to the SDIO/MMC controller's SDDAT1 line. 72 GPE(8) to be connected to the SDIO/MMC controller's SDDAT1 line.
73 73
74 74
75Reading the current configuration 75Reading the current configuration
diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
index a2cd9beaf37d..38518d450bc0 100644
--- a/arch/arm/common/Kconfig
+++ b/arch/arm/common/Kconfig
@@ -4,6 +4,13 @@ config ARM_GIC
4config ARM_VIC 4config ARM_VIC
5 bool 5 bool
6 6
7config ARM_VIC_NR
8 int
9 default 2
10 help
11 The maximum number of VICs available in the system, for
12 power management.
13
7config ICST525 14config ICST525
8 bool 15 bool
9 16
diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c
index b2a781d9ce05..887c6eb3a18a 100644
--- a/arch/arm/common/vic.c
+++ b/arch/arm/common/vic.c
@@ -21,6 +21,7 @@
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/list.h> 22#include <linux/list.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/sysdev.h>
24 25
25#include <asm/mach/irq.h> 26#include <asm/mach/irq.h>
26#include <asm/hardware/vic.h> 27#include <asm/hardware/vic.h>
@@ -39,11 +40,219 @@ static void vic_unmask_irq(unsigned int irq)
39 writel(1 << irq, base + VIC_INT_ENABLE); 40 writel(1 << irq, base + VIC_INT_ENABLE);
40} 41}
41 42
43/**
44 * vic_init2 - common initialisation code
45 * @base: Base of the VIC.
46 *
47 * Common initialisation code for registeration
48 * and resume.
49*/
50static void vic_init2(void __iomem *base)
51{
52 int i;
53
54 for (i = 0; i < 16; i++) {
55 void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
56 writel(VIC_VECT_CNTL_ENABLE | i, reg);
57 }
58
59 writel(32, base + VIC_PL190_DEF_VECT_ADDR);
60}
61
62#if defined(CONFIG_PM)
63/**
64 * struct vic_device - VIC PM device
65 * @sysdev: The system device which is registered.
66 * @irq: The IRQ number for the base of the VIC.
67 * @base: The register base for the VIC.
68 * @resume_sources: A bitmask of interrupts for resume.
69 * @resume_irqs: The IRQs enabled for resume.
70 * @int_select: Save for VIC_INT_SELECT.
71 * @int_enable: Save for VIC_INT_ENABLE.
72 * @soft_int: Save for VIC_INT_SOFT.
73 * @protect: Save for VIC_PROTECT.
74 */
75struct vic_device {
76 struct sys_device sysdev;
77
78 void __iomem *base;
79 int irq;
80 u32 resume_sources;
81 u32 resume_irqs;
82 u32 int_select;
83 u32 int_enable;
84 u32 soft_int;
85 u32 protect;
86};
87
88/* we cannot allocate memory when VICs are initially registered */
89static struct vic_device vic_devices[CONFIG_ARM_VIC_NR];
90
91static inline struct vic_device *to_vic(struct sys_device *sys)
92{
93 return container_of(sys, struct vic_device, sysdev);
94}
95
96static int vic_id;
97
98static int vic_class_resume(struct sys_device *dev)
99{
100 struct vic_device *vic = to_vic(dev);
101 void __iomem *base = vic->base;
102
103 printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base);
104
105 /* re-initialise static settings */
106 vic_init2(base);
107
108 writel(vic->int_select, base + VIC_INT_SELECT);
109 writel(vic->protect, base + VIC_PROTECT);
110
111 /* set the enabled ints and then clear the non-enabled */
112 writel(vic->int_enable, base + VIC_INT_ENABLE);
113 writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR);
114
115 /* and the same for the soft-int register */
116
117 writel(vic->soft_int, base + VIC_INT_SOFT);
118 writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR);
119
120 return 0;
121}
122
123static int vic_class_suspend(struct sys_device *dev, pm_message_t state)
124{
125 struct vic_device *vic = to_vic(dev);
126 void __iomem *base = vic->base;
127
128 printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base);
129
130 vic->int_select = readl(base + VIC_INT_SELECT);
131 vic->int_enable = readl(base + VIC_INT_ENABLE);
132 vic->soft_int = readl(base + VIC_INT_SOFT);
133 vic->protect = readl(base + VIC_PROTECT);
134
135 /* set the interrupts (if any) that are used for
136 * resuming the system */
137
138 writel(vic->resume_irqs, base + VIC_INT_ENABLE);
139 writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR);
140
141 return 0;
142}
143
144struct sysdev_class vic_class = {
145 .name = "vic",
146 .suspend = vic_class_suspend,
147 .resume = vic_class_resume,
148};
149
150/**
151 * vic_pm_register - Register a VIC for later power management control
152 * @base: The base address of the VIC.
153 * @irq: The base IRQ for the VIC.
154 * @resume_sources: bitmask of interrupts allowed for resume sources.
155 *
156 * Register the VIC with the system device tree so that it can be notified
157 * of suspend and resume requests and ensure that the correct actions are
158 * taken to re-instate the settings on resume.
159 */
160static void __init vic_pm_register(void __iomem *base, unsigned int irq, u32 resume_sources)
161{
162 struct vic_device *v;
163
164 if (vic_id >= ARRAY_SIZE(vic_devices))
165 printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
166 else {
167 v = &vic_devices[vic_id];
168 v->base = base;
169 v->resume_sources = resume_sources;
170 v->irq = irq;
171 vic_id++;
172 }
173}
174
175/**
176 * vic_pm_init - initicall to register VIC pm
177 *
178 * This is called via late_initcall() to register
179 * the resources for the VICs due to the early
180 * nature of the VIC's registration.
181*/
182static int __init vic_pm_init(void)
183{
184 struct vic_device *dev = vic_devices;
185 int err;
186 int id;
187
188 if (vic_id == 0)
189 return 0;
190
191 err = sysdev_class_register(&vic_class);
192 if (err) {
193 printk(KERN_ERR "%s: cannot register class\n", __func__);
194 return err;
195 }
196
197 for (id = 0; id < vic_id; id++, dev++) {
198 dev->sysdev.id = id;
199 dev->sysdev.cls = &vic_class;
200
201 err = sysdev_register(&dev->sysdev);
202 if (err) {
203 printk(KERN_ERR "%s: failed to register device\n",
204 __func__);
205 return err;
206 }
207 }
208
209 return 0;
210}
211
212late_initcall(vic_pm_init);
213
214static struct vic_device *vic_from_irq(unsigned int irq)
215{
216 struct vic_device *v = vic_devices;
217 unsigned int base_irq = irq & ~31;
218 int id;
219
220 for (id = 0; id < vic_id; id++, v++) {
221 if (v->irq == base_irq)
222 return v;
223 }
224
225 return NULL;
226}
227
228static int vic_set_wake(unsigned int irq, unsigned int on)
229{
230 struct vic_device *v = vic_from_irq(irq);
231 unsigned int off = irq & 31;
232
233 if (!v)
234 return -EINVAL;
235
236 if (on)
237 v->resume_irqs |= 1 << off;
238 else
239 v->resume_irqs &= ~(1 << off);
240
241 return 0;
242}
243
244#else
245static inline void vic_pm_register(void __iomem *base, unsigned int irq, u32 arg1) { }
246
247#define vic_set_wake NULL
248#endif /* CONFIG_PM */
249
42static struct irq_chip vic_chip = { 250static struct irq_chip vic_chip = {
43 .name = "VIC", 251 .name = "VIC",
44 .ack = vic_mask_irq, 252 .ack = vic_mask_irq,
45 .mask = vic_mask_irq, 253 .mask = vic_mask_irq,
46 .unmask = vic_unmask_irq, 254 .unmask = vic_unmask_irq,
255 .set_wake = vic_set_wake,
47}; 256};
48 257
49/** 258/**
@@ -51,9 +260,10 @@ static struct irq_chip vic_chip = {
51 * @base: iomem base address 260 * @base: iomem base address
52 * @irq_start: starting interrupt number, must be muliple of 32 261 * @irq_start: starting interrupt number, must be muliple of 32
53 * @vic_sources: bitmask of interrupt sources to allow 262 * @vic_sources: bitmask of interrupt sources to allow
263 * @resume_sources: bitmask of interrupt sources to allow for resume
54 */ 264 */
55void __init vic_init(void __iomem *base, unsigned int irq_start, 265void __init vic_init(void __iomem *base, unsigned int irq_start,
56 u32 vic_sources) 266 u32 vic_sources, u32 resume_sources)
57{ 267{
58 unsigned int i; 268 unsigned int i;
59 269
@@ -77,12 +287,7 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
77 writel(value, base + VIC_PL190_VECT_ADDR); 287 writel(value, base + VIC_PL190_VECT_ADDR);
78 } 288 }
79 289
80 for (i = 0; i < 16; i++) { 290 vic_init2(base);
81 void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
82 writel(VIC_VECT_CNTL_ENABLE | i, reg);
83 }
84
85 writel(32, base + VIC_PL190_DEF_VECT_ADDR);
86 291
87 for (i = 0; i < 32; i++) { 292 for (i = 0; i < 32; i++) {
88 if (vic_sources & (1 << i)) { 293 if (vic_sources & (1 << i)) {
@@ -94,4 +299,6 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
94 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 299 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
95 } 300 }
96 } 301 }
302
303 vic_pm_register(base, irq_start, resume_sources);
97} 304}
diff --git a/arch/arm/include/asm/hardware/pl080.h b/arch/arm/include/asm/hardware/pl080.h
new file mode 100644
index 000000000000..6a6c66be7f65
--- /dev/null
+++ b/arch/arm/include/asm/hardware/pl080.h
@@ -0,0 +1,138 @@
1/* arch/arm/include/asm/hardware/pl080.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * ARM PrimeCell PL080 DMA controller
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15/* Note, there are some Samsung updates to this controller block which
16 * make it not entierly compatible with the PL080 specification from
17 * ARM. When in doubt, check the Samsung documentation first.
18 *
19 * The Samsung defines are PL080S, and add an extra controll register,
20 * the ability to move more than 2^11 counts of data and some extra
21 * OneNAND features.
22*/
23
24#define PL080_INT_STATUS (0x00)
25#define PL080_TC_STATUS (0x04)
26#define PL080_TC_CLEAR (0x08)
27#define PL080_ERR_STATUS (0x0C)
28#define PL080_ERR_CLEAR (0x10)
29#define PL080_RAW_TC_STATUS (0x14)
30#define PL080_RAW_ERR_STATUS (0x18)
31#define PL080_EN_CHAN (0x1c)
32#define PL080_SOFT_BREQ (0x20)
33#define PL080_SOFT_SREQ (0x24)
34#define PL080_SOFT_LBREQ (0x28)
35#define PL080_SOFT_LSREQ (0x2C)
36
37#define PL080_CONFIG (0x30)
38#define PL080_CONFIG_M2_BE (1 << 2)
39#define PL080_CONFIG_M1_BE (1 << 1)
40#define PL080_CONFIG_ENABLE (1 << 0)
41
42#define PL080_SYNC (0x34)
43
44/* Per channel configuration registers */
45
46#define PL008_Cx_STRIDE (0x20)
47#define PL080_Cx_BASE(x) ((0x100 + (x * 0x20)))
48#define PL080_Cx_SRC_ADDR(x) ((0x100 + (x * 0x20)))
49#define PL080_Cx_DST_ADDR(x) ((0x104 + (x * 0x20)))
50#define PL080_Cx_LLI(x) ((0x108 + (x * 0x20)))
51#define PL080_Cx_CONTROL(x) ((0x10C + (x * 0x20)))
52#define PL080_Cx_CONFIG(x) ((0x110 + (x * 0x20)))
53#define PL080S_Cx_CONTROL2(x) ((0x110 + (x * 0x20)))
54#define PL080S_Cx_CONFIG(x) ((0x114 + (x * 0x20)))
55
56#define PL080_CH_SRC_ADDR (0x00)
57#define PL080_CH_DST_ADDR (0x04)
58#define PL080_CH_LLI (0x08)
59#define PL080_CH_CONTROL (0x0C)
60#define PL080_CH_CONFIG (0x10)
61#define PL080S_CH_CONTROL2 (0x10)
62#define PL080S_CH_CONFIG (0x14)
63
64#define PL080_LLI_ADDR_MASK (0x3fffffff << 2)
65#define PL080_LLI_ADDR_SHIFT (2)
66#define PL080_LLI_LM_AHB2 (1 << 0)
67
68#define PL080_CONTROL_TC_IRQ_EN (1 << 31)
69#define PL080_CONTROL_PROT_MASK (0x7 << 28)
70#define PL080_CONTROL_PROT_SHIFT (28)
71#define PL080_CONTROL_PROT_SYS (1 << 28)
72#define PL080_CONTROL_DST_INCR (1 << 27)
73#define PL080_CONTROL_SRC_INCR (1 << 26)
74#define PL080_CONTROL_DST_AHB2 (1 << 25)
75#define PL080_CONTROL_SRC_AHB2 (1 << 24)
76#define PL080_CONTROL_DWIDTH_MASK (0x7 << 21)
77#define PL080_CONTROL_DWIDTH_SHIFT (21)
78#define PL080_CONTROL_SWIDTH_MASK (0x7 << 18)
79#define PL080_CONTROL_SWIDTH_SHIFT (18)
80#define PL080_CONTROL_DB_SIZE_MASK (0x7 << 15)
81#define PL080_CONTROL_DB_SIZE_SHIFT (15)
82#define PL080_CONTROL_SB_SIZE_MASK (0x7 << 12)
83#define PL080_CONTROL_SB_SIZE_SHIFT (12)
84#define PL080_CONTROL_TRANSFER_SIZE_MASK (0xfff << 0)
85#define PL080_CONTROL_TRANSFER_SIZE_SHIFT (0)
86
87#define PL080_BSIZE_1 (0x0)
88#define PL080_BSIZE_4 (0x1)
89#define PL080_BSIZE_8 (0x2)
90#define PL080_BSIZE_16 (0x3)
91#define PL080_BSIZE_32 (0x4)
92#define PL080_BSIZE_64 (0x5)
93#define PL080_BSIZE_128 (0x6)
94#define PL080_BSIZE_256 (0x7)
95
96#define PL080_WIDTH_8BIT (0x0)
97#define PL080_WIDTH_16BIT (0x1)
98#define PL080_WIDTH_32BIT (0x2)
99
100#define PL080_CONFIG_HALT (1 << 18)
101#define PL080_CONFIG_ACTIVE (1 << 17) /* RO */
102#define PL080_CONFIG_LOCK (1 << 16)
103#define PL080_CONFIG_TC_IRQ_MASK (1 << 15)
104#define PL080_CONFIG_ERR_IRQ_MASK (1 << 14)
105#define PL080_CONFIG_FLOW_CONTROL_MASK (0x7 << 11)
106#define PL080_CONFIG_FLOW_CONTROL_SHIFT (11)
107#define PL080_CONFIG_DST_SEL_MASK (0xf << 6)
108#define PL080_CONFIG_DST_SEL_SHIFT (6)
109#define PL080_CONFIG_SRC_SEL_MASK (0xf << 1)
110#define PL080_CONFIG_SRC_SEL_SHIFT (1)
111#define PL080_CONFIG_ENABLE (1 << 0)
112
113#define PL080_FLOW_MEM2MEM (0x0)
114#define PL080_FLOW_MEM2PER (0x1)
115#define PL080_FLOW_PER2MEM (0x2)
116#define PL080_FLOW_SRC2DST (0x3)
117#define PL080_FLOW_SRC2DST_DST (0x4)
118#define PL080_FLOW_MEM2PER_PER (0x5)
119#define PL080_FLOW_PER2MEM_PER (0x6)
120#define PL080_FLOW_SRC2DST_SRC (0x7)
121
122/* DMA linked list chain structure */
123
124struct pl080_lli {
125 u32 src_addr;
126 u32 dst_addr;
127 u32 next_lli;
128 u32 control0;
129};
130
131struct pl080s_lli {
132 u32 src_addr;
133 u32 dst_addr;
134 u32 next_lli;
135 u32 control0;
136 u32 control1;
137};
138
diff --git a/arch/arm/include/asm/hardware/vic.h b/arch/arm/include/asm/hardware/vic.h
index f87328d4a180..5d72550a8097 100644
--- a/arch/arm/include/asm/hardware/vic.h
+++ b/arch/arm/include/asm/hardware/vic.h
@@ -41,7 +41,7 @@
41#define VIC_PL192_VECT_ADDR 0xF00 41#define VIC_PL192_VECT_ADDR 0xF00
42 42
43#ifndef __ASSEMBLY__ 43#ifndef __ASSEMBLY__
44void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources); 44void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources, u32 resume_sources);
45#endif 45#endif
46 46
47#endif 47#endif
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index f477df0e5e4c..204dc5cbd0b8 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -362,8 +362,8 @@ void __init ep93xx_init_irq(void)
362{ 362{
363 int gpio_irq; 363 int gpio_irq;
364 364
365 vic_init((void *)EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK); 365 vic_init((void *)EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0);
366 vic_init((void *)EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK); 366 vic_init((void *)EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0);
367 367
368 for (gpio_irq = gpio_to_irq(0); 368 for (gpio_irq = gpio_to_irq(0);
369 gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) { 369 gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
diff --git a/arch/arm/mach-netx/generic.c b/arch/arm/mach-netx/generic.c
index 79df60c20e70..43da8bb4926b 100644
--- a/arch/arm/mach-netx/generic.c
+++ b/arch/arm/mach-netx/generic.c
@@ -168,7 +168,7 @@ void __init netx_init_irq(void)
168{ 168{
169 int irq; 169 int irq;
170 170
171 vic_init(__io(io_p2v(NETX_PA_VIC)), 0, ~0); 171 vic_init(__io(io_p2v(NETX_PA_VIC)), 0, ~0, 0);
172 172
173 for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) { 173 for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) {
174 set_irq_chip(irq, &netx_hif_chip); 174 set_irq_chip(irq, &netx_hif_chip);
diff --git a/arch/arm/mach-s3c2400/gpio.c b/arch/arm/mach-s3c2400/gpio.c
index 7a7ed4174c8c..6c68e78f3595 100644
--- a/arch/arm/mach-s3c2400/gpio.c
+++ b/arch/arm/mach-s3c2400/gpio.c
@@ -33,10 +33,10 @@
33 33
34int s3c2400_gpio_getirq(unsigned int pin) 34int s3c2400_gpio_getirq(unsigned int pin)
35{ 35{
36 if (pin < S3C2410_GPE0 || pin > S3C2400_GPE7_EINT7) 36 if (pin < S3C2410_GPE(0) || pin > S3C2400_GPE(7))
37 return -1; /* not valid interrupts */ 37 return -EINVAL; /* not valid interrupts */
38 38
39 return (pin - S3C2410_GPE0) + IRQ_EINT0; 39 return (pin - S3C2410_GPE(0)) + IRQ_EINT0;
40} 40}
41 41
42EXPORT_SYMBOL(s3c2400_gpio_getirq); 42EXPORT_SYMBOL(s3c2400_gpio_getirq);
diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig
index 63a30d1dd425..41bb65d5b91f 100644
--- a/arch/arm/mach-s3c2410/Kconfig
+++ b/arch/arm/mach-s3c2410/Kconfig
@@ -59,6 +59,7 @@ config ARCH_H1940
59 bool "IPAQ H1940" 59 bool "IPAQ H1940"
60 select CPU_S3C2410 60 select CPU_S3C2410
61 select PM_H1940 if PM 61 select PM_H1940 if PM
62 select S3C_DEV_USB_HOST
62 help 63 help
63 Say Y here if you are using the HP IPAQ H1940 64 Say Y here if you are using the HP IPAQ H1940
64 65
@@ -70,6 +71,7 @@ config PM_H1940
70config MACH_N30 71config MACH_N30
71 bool "Acer N30 family" 72 bool "Acer N30 family"
72 select CPU_S3C2410 73 select CPU_S3C2410
74 select S3C_DEV_USB_HOST
73 help 75 help
74 Say Y here if you want suppt for the Acer N30, Acer N35, 76 Say Y here if you want suppt for the Acer N30, Acer N35,
75 Navman PiN570, Yakumo AlphaX or Airis NC05 PDAs. 77 Navman PiN570, Yakumo AlphaX or Airis NC05 PDAs.
@@ -82,6 +84,7 @@ config ARCH_BAST
82 select MACH_BAST_IDE 84 select MACH_BAST_IDE
83 select S3C24XX_DCLK 85 select S3C24XX_DCLK
84 select ISA 86 select ISA
87 select S3C_DEV_USB_HOST
85 help 88 help
86 Say Y here if you are using the Simtec Electronics EB2410ITX 89 Say Y here if you are using the Simtec Electronics EB2410ITX
87 development board (also known as BAST) 90 development board (also known as BAST)
@@ -89,6 +92,7 @@ config ARCH_BAST
89config MACH_OTOM 92config MACH_OTOM
90 bool "NexVision OTOM Board" 93 bool "NexVision OTOM Board"
91 select CPU_S3C2410 94 select CPU_S3C2410
95 select S3C_DEV_USB_HOST
92 help 96 help
93 Say Y here if you are using the Nex Vision OTOM board 97 Say Y here if you are using the Nex Vision OTOM board
94 98
@@ -96,6 +100,7 @@ config MACH_AML_M5900
96 bool "AML M5900 Series" 100 bool "AML M5900 Series"
97 select CPU_S3C2410 101 select CPU_S3C2410
98 select PM_SIMTEC if PM 102 select PM_SIMTEC if PM
103 select S3C_DEV_USB_HOST
99 help 104 help
100 Say Y here if you are using the American Microsystems M5900 Series 105 Say Y here if you are using the American Microsystems M5900 Series
101 <http://www.amltd.com> 106 <http://www.amltd.com>
@@ -111,6 +116,7 @@ config BAST_PC104_IRQ
111config MACH_TCT_HAMMER 116config MACH_TCT_HAMMER
112 bool "TCT Hammer Board" 117 bool "TCT Hammer Board"
113 select CPU_S3C2410 118 select CPU_S3C2410
119 select S3C_DEV_USB_HOST
114 help 120 help
115 Say Y here if you are using the TinCanTools Hammer Board 121 Say Y here if you are using the TinCanTools Hammer Board
116 <http://www.tincantools.com> 122 <http://www.tincantools.com>
@@ -122,12 +128,14 @@ config MACH_VR1000
122 select SIMTEC_NOR 128 select SIMTEC_NOR
123 select MACH_BAST_IDE 129 select MACH_BAST_IDE
124 select CPU_S3C2410 130 select CPU_S3C2410
131 select S3C_DEV_USB_HOST
125 help 132 help
126 Say Y here if you are using the Thorcom VR1000 board. 133 Say Y here if you are using the Thorcom VR1000 board.
127 134
128config MACH_QT2410 135config MACH_QT2410
129 bool "QT2410" 136 bool "QT2410"
130 select CPU_S3C2410 137 select CPU_S3C2410
138 select S3C_DEV_USB_HOST
131 help 139 help
132 Say Y here if you are using the Armzone QT2410 140 Say Y here if you are using the Armzone QT2410
133 141
diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c
index 440c014e24b3..dbf96e60d992 100644
--- a/arch/arm/mach-s3c2410/dma.c
+++ b/arch/arm/mach-s3c2410/dma.c
@@ -17,14 +17,16 @@
17#include <linux/sysdev.h> 17#include <linux/sysdev.h>
18#include <linux/serial_core.h> 18#include <linux/serial_core.h>
19 19
20#include <mach/map.h>
20#include <mach/dma.h> 21#include <mach/dma.h>
21 22
22#include <plat/cpu.h> 23#include <plat/cpu.h>
23#include <plat/dma.h> 24#include <plat/dma-plat.h>
24 25
25#include <plat/regs-serial.h> 26#include <plat/regs-serial.h>
26#include <mach/regs-gpio.h> 27#include <mach/regs-gpio.h>
27#include <plat/regs-ac97.h> 28#include <plat/regs-ac97.h>
29#include <plat/regs-dma.h>
28#include <mach/regs-mem.h> 30#include <mach/regs-mem.h>
29#include <mach/regs-lcd.h> 31#include <mach/regs-lcd.h>
30#include <mach/regs-sdi.h> 32#include <mach/regs-sdi.h>
diff --git a/arch/arm/mach-s3c2410/gpio.c b/arch/arm/mach-s3c2410/gpio.c
index 36a3132f39e7..7974afca297c 100644
--- a/arch/arm/mach-s3c2410/gpio.c
+++ b/arch/arm/mach-s3c2410/gpio.c
@@ -39,12 +39,12 @@ int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
39 unsigned long flags; 39 unsigned long flags;
40 unsigned long val; 40 unsigned long val;
41 41
42 if (pin < S3C2410_GPG8 || pin > S3C2410_GPG15) 42 if (pin < S3C2410_GPG(8) || pin > S3C2410_GPG(15))
43 return -1; 43 return -EINVAL;
44 44
45 config &= 0xff; 45 config &= 0xff;
46 46
47 pin -= S3C2410_GPG8; 47 pin -= S3C2410_GPG(8);
48 reg += pin & ~3; 48 reg += pin & ~3;
49 49
50 local_irq_save(flags); 50 local_irq_save(flags);
diff --git a/arch/arm/mach-s3c2410/h1940-bluetooth.c b/arch/arm/mach-s3c2410/h1940-bluetooth.c
index 5a6bc56f186b..5aabf117cbb0 100644
--- a/arch/arm/mach-s3c2410/h1940-bluetooth.c
+++ b/arch/arm/mach-s3c2410/h1940-bluetooth.c
@@ -16,6 +16,8 @@
16#include <linux/string.h> 16#include <linux/string.h>
17#include <linux/ctype.h> 17#include <linux/ctype.h>
18#include <linux/leds.h> 18#include <linux/leds.h>
19#include <linux/gpio.h>
20
19#include <mach/regs-gpio.h> 21#include <mach/regs-gpio.h>
20#include <mach/hardware.h> 22#include <mach/hardware.h>
21#include <mach/h1940-latch.h> 23#include <mach/h1940-latch.h>
@@ -41,9 +43,9 @@ static void h1940bt_enable(int on)
41 h1940_latch_control(0, H1940_LATCH_BLUETOOTH_POWER); 43 h1940_latch_control(0, H1940_LATCH_BLUETOOTH_POWER);
42 /* Reset the chip */ 44 /* Reset the chip */
43 mdelay(10); 45 mdelay(10);
44 s3c2410_gpio_setpin(S3C2410_GPH1, 1); 46 s3c2410_gpio_setpin(S3C2410_GPH(1), 1);
45 mdelay(10); 47 mdelay(10);
46 s3c2410_gpio_setpin(S3C2410_GPH1, 0); 48 s3c2410_gpio_setpin(S3C2410_GPH(1), 0);
47 49
48 state = 1; 50 state = 1;
49 } 51 }
@@ -52,9 +54,9 @@ static void h1940bt_enable(int on)
52 led_trigger_event(bt_led_trigger, 0); 54 led_trigger_event(bt_led_trigger, 0);
53#endif 55#endif
54 56
55 s3c2410_gpio_setpin(S3C2410_GPH1, 1); 57 s3c2410_gpio_setpin(S3C2410_GPH(1), 1);
56 mdelay(10); 58 mdelay(10);
57 s3c2410_gpio_setpin(S3C2410_GPH1, 0); 59 s3c2410_gpio_setpin(S3C2410_GPH(1), 0);
58 mdelay(10); 60 mdelay(10);
59 h1940_latch_control(H1940_LATCH_BLUETOOTH_POWER, 0); 61 h1940_latch_control(H1940_LATCH_BLUETOOTH_POWER, 0);
60 62
@@ -87,14 +89,14 @@ static DEVICE_ATTR(enable, 0644,
87static int __init h1940bt_probe(struct platform_device *pdev) 89static int __init h1940bt_probe(struct platform_device *pdev)
88{ 90{
89 /* Configures BT serial port GPIOs */ 91 /* Configures BT serial port GPIOs */
90 s3c2410_gpio_cfgpin(S3C2410_GPH0, S3C2410_GPH0_nCTS0); 92 s3c2410_gpio_cfgpin(S3C2410_GPH(0), S3C2410_GPH0_nCTS0);
91 s3c2410_gpio_pullup(S3C2410_GPH0, 1); 93 s3c2410_gpio_pullup(S3C2410_GPH(0), 1);
92 s3c2410_gpio_cfgpin(S3C2410_GPH1, S3C2410_GPH1_OUTP); 94 s3c2410_gpio_cfgpin(S3C2410_GPH(1), S3C2410_GPIO_OUTPUT);
93 s3c2410_gpio_pullup(S3C2410_GPH1, 1); 95 s3c2410_gpio_pullup(S3C2410_GPH(1), 1);
94 s3c2410_gpio_cfgpin(S3C2410_GPH2, S3C2410_GPH2_TXD0); 96 s3c2410_gpio_cfgpin(S3C2410_GPH(2), S3C2410_GPH2_TXD0);
95 s3c2410_gpio_pullup(S3C2410_GPH2, 1); 97 s3c2410_gpio_pullup(S3C2410_GPH(2), 1);
96 s3c2410_gpio_cfgpin(S3C2410_GPH3, S3C2410_GPH3_RXD0); 98 s3c2410_gpio_cfgpin(S3C2410_GPH(3), S3C2410_GPH3_RXD0);
97 s3c2410_gpio_pullup(S3C2410_GPH3, 1); 99 s3c2410_gpio_pullup(S3C2410_GPH(3), 1);
98 100
99#ifdef CONFIG_LEDS_H1940 101#ifdef CONFIG_LEDS_H1940
100 led_trigger_register_simple("h1940-bluetooth", &bt_led_trigger); 102 led_trigger_register_simple("h1940-bluetooth", &bt_led_trigger);
diff --git a/arch/arm/mach-s3c2410/include/mach/dma.h b/arch/arm/mach-s3c2410/include/mach/dma.h
index 13358ce2128c..c3a2629e0ded 100644
--- a/arch/arm/mach-s3c2410/include/mach/dma.h
+++ b/arch/arm/mach-s3c2410/include/mach/dma.h
@@ -3,7 +3,7 @@
3 * Copyright (C) 2003,2004,2006 Simtec Electronics 3 * Copyright (C) 2003,2004,2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk> 4 * Ben Dooks <ben@simtec.co.uk>
5 * 5 *
6 * Samsung S3C241XX DMA support 6 * Samsung S3C24XX DMA support
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
@@ -13,8 +13,8 @@
13#ifndef __ASM_ARCH_DMA_H 13#ifndef __ASM_ARCH_DMA_H
14#define __ASM_ARCH_DMA_H __FILE__ 14#define __ASM_ARCH_DMA_H __FILE__
15 15
16#include <plat/dma.h>
16#include <linux/sysdev.h> 17#include <linux/sysdev.h>
17#include <mach/hardware.h>
18 18
19#define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */ 19#define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */
20 20
@@ -55,9 +55,9 @@ enum dma_ch {
55 55
56/* we have 4 dma channels */ 56/* we have 4 dma channels */
57#ifndef CONFIG_CPU_S3C2443 57#ifndef CONFIG_CPU_S3C2443
58#define S3C2410_DMA_CHANNELS (4) 58#define S3C_DMA_CHANNELS (4)
59#else 59#else
60#define S3C2410_DMA_CHANNELS (6) 60#define S3C_DMA_CHANNELS (6)
61#endif 61#endif
62 62
63/* types */ 63/* types */
@@ -68,7 +68,6 @@ enum s3c2410_dma_state {
68 S3C2410_DMA_PAUSED 68 S3C2410_DMA_PAUSED
69}; 69};
70 70
71
72/* enum s3c2410_dma_loadst 71/* enum s3c2410_dma_loadst
73 * 72 *
74 * This represents the state of the DMA engine, wrt to the loaded / running 73 * This represents the state of the DMA engine, wrt to the loaded / running
@@ -104,32 +103,6 @@ enum s3c2410_dma_loadst {
104 S3C2410_DMALOAD_1LOADED_1RUNNING, 103 S3C2410_DMALOAD_1LOADED_1RUNNING,
105}; 104};
106 105
107enum s3c2410_dma_buffresult {
108 S3C2410_RES_OK,
109 S3C2410_RES_ERR,
110 S3C2410_RES_ABORT
111};
112
113enum s3c2410_dmasrc {
114 S3C2410_DMASRC_HW, /* source is memory */
115 S3C2410_DMASRC_MEM /* source is hardware */
116};
117
118/* enum s3c2410_chan_op
119 *
120 * operation codes passed to the DMA code by the user, and also used
121 * to inform the current channel owner of any changes to the system state
122*/
123
124enum s3c2410_chan_op {
125 S3C2410_DMAOP_START,
126 S3C2410_DMAOP_STOP,
127 S3C2410_DMAOP_PAUSE,
128 S3C2410_DMAOP_RESUME,
129 S3C2410_DMAOP_FLUSH,
130 S3C2410_DMAOP_TIMEOUT, /* internal signal to handler */
131 S3C2410_DMAOP_STARTED, /* indicate channel started */
132};
133 106
134/* flags */ 107/* flags */
135 108
@@ -139,17 +112,14 @@ enum s3c2410_chan_op {
139 112
140/* dma buffer */ 113/* dma buffer */
141 114
142struct s3c2410_dma_client { 115struct s3c2410_dma_buf;
143 char *name;
144};
145 116
146/* s3c2410_dma_buf_s 117/* s3c2410_dma_buf
147 * 118 *
148 * internally used buffer structure to describe a queued or running 119 * internally used buffer structure to describe a queued or running
149 * buffer. 120 * buffer.
150*/ 121*/
151 122
152struct s3c2410_dma_buf;
153struct s3c2410_dma_buf { 123struct s3c2410_dma_buf {
154 struct s3c2410_dma_buf *next; 124 struct s3c2410_dma_buf *next;
155 int magic; /* magic */ 125 int magic; /* magic */
@@ -161,20 +131,6 @@ struct s3c2410_dma_buf {
161 131
162/* [1] is this updated for both recv/send modes? */ 132/* [1] is this updated for both recv/send modes? */
163 133
164struct s3c2410_dma_chan;
165
166/* s3c2410_dma_cbfn_t
167 *
168 * buffer callback routine type
169*/
170
171typedef void (*s3c2410_dma_cbfn_t)(struct s3c2410_dma_chan *,
172 void *buf, int size,
173 enum s3c2410_dma_buffresult result);
174
175typedef int (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *,
176 enum s3c2410_chan_op );
177
178struct s3c2410_dma_stats { 134struct s3c2410_dma_stats {
179 unsigned long loads; 135 unsigned long loads;
180 unsigned long timeout_longest; 136 unsigned long timeout_longest;
@@ -206,10 +162,10 @@ struct s3c2410_dma_chan {
206 162
207 /* channel configuration */ 163 /* channel configuration */
208 enum s3c2410_dmasrc source; 164 enum s3c2410_dmasrc source;
165 enum dma_ch req_ch;
209 unsigned long dev_addr; 166 unsigned long dev_addr;
210 unsigned long load_timeout; 167 unsigned long load_timeout;
211 unsigned int flags; /* channel flags */ 168 unsigned int flags; /* channel flags */
212 unsigned int hw_cfg; /* last hw config */
213 169
214 struct s3c24xx_dma_map *map; /* channel hw maps */ 170 struct s3c24xx_dma_map *map; /* channel hw maps */
215 171
@@ -236,213 +192,6 @@ struct s3c2410_dma_chan {
236 struct sys_device dev; 192 struct sys_device dev;
237}; 193};
238 194
239/* the currently allocated channel information */
240extern struct s3c2410_dma_chan s3c2410_chans[];
241
242/* note, we don't really use dma_device_t at the moment */
243typedef unsigned long dma_device_t; 195typedef unsigned long dma_device_t;
244 196
245/* functions --------------------------------------------------------------- */
246
247/* s3c2410_dma_request
248 *
249 * request a dma channel exclusivley
250*/
251
252extern int s3c2410_dma_request(unsigned int channel,
253 struct s3c2410_dma_client *, void *dev);
254
255
256/* s3c2410_dma_ctrl
257 *
258 * change the state of the dma channel
259*/
260
261extern int s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op);
262
263/* s3c2410_dma_setflags
264 *
265 * set the channel's flags to a given state
266*/
267
268extern int s3c2410_dma_setflags(unsigned int channel,
269 unsigned int flags);
270
271/* s3c2410_dma_free
272 *
273 * free the dma channel (will also abort any outstanding operations)
274*/
275
276extern int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *);
277
278/* s3c2410_dma_enqueue
279 *
280 * place the given buffer onto the queue of operations for the channel.
281 * The buffer must be allocated from dma coherent memory, or the Dcache/WB
282 * drained before the buffer is given to the DMA system.
283*/
284
285extern int s3c2410_dma_enqueue(unsigned int channel, void *id,
286 dma_addr_t data, int size);
287
288/* s3c2410_dma_config
289 *
290 * configure the dma channel
291*/
292
293extern int s3c2410_dma_config(unsigned int channel, int xferunit, int dcon);
294
295/* s3c2410_dma_devconfig
296 *
297 * configure the device we're talking to
298*/
299
300extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source,
301 int hwcfg, unsigned long devaddr);
302
303/* s3c2410_dma_getposition
304 *
305 * get the position that the dma transfer is currently at
306*/
307
308extern int s3c2410_dma_getposition(unsigned int channel,
309 dma_addr_t *src, dma_addr_t *dest);
310
311extern int s3c2410_dma_set_opfn(unsigned int, s3c2410_dma_opfn_t rtn);
312extern int s3c2410_dma_set_buffdone_fn(unsigned int, s3c2410_dma_cbfn_t rtn);
313
314/* DMA Register definitions */
315
316#define S3C2410_DMA_DISRC (0x00)
317#define S3C2410_DMA_DISRCC (0x04)
318#define S3C2410_DMA_DIDST (0x08)
319#define S3C2410_DMA_DIDSTC (0x0C)
320#define S3C2410_DMA_DCON (0x10)
321#define S3C2410_DMA_DSTAT (0x14)
322#define S3C2410_DMA_DCSRC (0x18)
323#define S3C2410_DMA_DCDST (0x1C)
324#define S3C2410_DMA_DMASKTRIG (0x20)
325#define S3C2412_DMA_DMAREQSEL (0x24)
326#define S3C2443_DMA_DMAREQSEL (0x24)
327
328#define S3C2410_DISRCC_INC (1<<0)
329#define S3C2410_DISRCC_APB (1<<1)
330
331#define S3C2410_DMASKTRIG_STOP (1<<2)
332#define S3C2410_DMASKTRIG_ON (1<<1)
333#define S3C2410_DMASKTRIG_SWTRIG (1<<0)
334
335#define S3C2410_DCON_DEMAND (0<<31)
336#define S3C2410_DCON_HANDSHAKE (1<<31)
337#define S3C2410_DCON_SYNC_PCLK (0<<30)
338#define S3C2410_DCON_SYNC_HCLK (1<<30)
339
340#define S3C2410_DCON_INTREQ (1<<29)
341
342#define S3C2410_DCON_CH0_XDREQ0 (0<<24)
343#define S3C2410_DCON_CH0_UART0 (1<<24)
344#define S3C2410_DCON_CH0_SDI (2<<24)
345#define S3C2410_DCON_CH0_TIMER (3<<24)
346#define S3C2410_DCON_CH0_USBEP1 (4<<24)
347
348#define S3C2410_DCON_CH1_XDREQ1 (0<<24)
349#define S3C2410_DCON_CH1_UART1 (1<<24)
350#define S3C2410_DCON_CH1_I2SSDI (2<<24)
351#define S3C2410_DCON_CH1_SPI (3<<24)
352#define S3C2410_DCON_CH1_USBEP2 (4<<24)
353
354#define S3C2410_DCON_CH2_I2SSDO (0<<24)
355#define S3C2410_DCON_CH2_I2SSDI (1<<24)
356#define S3C2410_DCON_CH2_SDI (2<<24)
357#define S3C2410_DCON_CH2_TIMER (3<<24)
358#define S3C2410_DCON_CH2_USBEP3 (4<<24)
359
360#define S3C2410_DCON_CH3_UART2 (0<<24)
361#define S3C2410_DCON_CH3_SDI (1<<24)
362#define S3C2410_DCON_CH3_SPI (2<<24)
363#define S3C2410_DCON_CH3_TIMER (3<<24)
364#define S3C2410_DCON_CH3_USBEP4 (4<<24)
365
366#define S3C2410_DCON_SRCSHIFT (24)
367#define S3C2410_DCON_SRCMASK (7<<24)
368
369#define S3C2410_DCON_BYTE (0<<20)
370#define S3C2410_DCON_HALFWORD (1<<20)
371#define S3C2410_DCON_WORD (2<<20)
372
373#define S3C2410_DCON_AUTORELOAD (0<<22)
374#define S3C2410_DCON_NORELOAD (1<<22)
375#define S3C2410_DCON_HWTRIG (1<<23)
376
377#ifdef CONFIG_CPU_S3C2440
378#define S3C2440_DIDSTC_CHKINT (1<<2)
379
380#define S3C2440_DCON_CH0_I2SSDO (5<<24)
381#define S3C2440_DCON_CH0_PCMIN (6<<24)
382
383#define S3C2440_DCON_CH1_PCMOUT (5<<24)
384#define S3C2440_DCON_CH1_SDI (6<<24)
385
386#define S3C2440_DCON_CH2_PCMIN (5<<24)
387#define S3C2440_DCON_CH2_MICIN (6<<24)
388
389#define S3C2440_DCON_CH3_MICIN (5<<24)
390#define S3C2440_DCON_CH3_PCMOUT (6<<24)
391#endif
392
393#ifdef CONFIG_CPU_S3C2412
394
395#define S3C2412_DMAREQSEL_SRC(x) ((x)<<1)
396
397#define S3C2412_DMAREQSEL_HW (1)
398
399#define S3C2412_DMAREQSEL_SPI0TX S3C2412_DMAREQSEL_SRC(0)
400#define S3C2412_DMAREQSEL_SPI0RX S3C2412_DMAREQSEL_SRC(1)
401#define S3C2412_DMAREQSEL_SPI1TX S3C2412_DMAREQSEL_SRC(2)
402#define S3C2412_DMAREQSEL_SPI1RX S3C2412_DMAREQSEL_SRC(3)
403#define S3C2412_DMAREQSEL_I2STX S3C2412_DMAREQSEL_SRC(4)
404#define S3C2412_DMAREQSEL_I2SRX S3C2412_DMAREQSEL_SRC(5)
405#define S3C2412_DMAREQSEL_TIMER S3C2412_DMAREQSEL_SRC(9)
406#define S3C2412_DMAREQSEL_SDI S3C2412_DMAREQSEL_SRC(10)
407#define S3C2412_DMAREQSEL_USBEP1 S3C2412_DMAREQSEL_SRC(13)
408#define S3C2412_DMAREQSEL_USBEP2 S3C2412_DMAREQSEL_SRC(14)
409#define S3C2412_DMAREQSEL_USBEP3 S3C2412_DMAREQSEL_SRC(15)
410#define S3C2412_DMAREQSEL_USBEP4 S3C2412_DMAREQSEL_SRC(16)
411#define S3C2412_DMAREQSEL_XDREQ0 S3C2412_DMAREQSEL_SRC(17)
412#define S3C2412_DMAREQSEL_XDREQ1 S3C2412_DMAREQSEL_SRC(18)
413#define S3C2412_DMAREQSEL_UART0_0 S3C2412_DMAREQSEL_SRC(19)
414#define S3C2412_DMAREQSEL_UART0_1 S3C2412_DMAREQSEL_SRC(20)
415#define S3C2412_DMAREQSEL_UART1_0 S3C2412_DMAREQSEL_SRC(21)
416#define S3C2412_DMAREQSEL_UART1_1 S3C2412_DMAREQSEL_SRC(22)
417#define S3C2412_DMAREQSEL_UART2_0 S3C2412_DMAREQSEL_SRC(23)
418#define S3C2412_DMAREQSEL_UART2_1 S3C2412_DMAREQSEL_SRC(24)
419
420#endif
421
422#define S3C2443_DMAREQSEL_SRC(x) ((x)<<1)
423
424#define S3C2443_DMAREQSEL_HW (1)
425
426#define S3C2443_DMAREQSEL_SPI0TX S3C2443_DMAREQSEL_SRC(0)
427#define S3C2443_DMAREQSEL_SPI0RX S3C2443_DMAREQSEL_SRC(1)
428#define S3C2443_DMAREQSEL_SPI1TX S3C2443_DMAREQSEL_SRC(2)
429#define S3C2443_DMAREQSEL_SPI1RX S3C2443_DMAREQSEL_SRC(3)
430#define S3C2443_DMAREQSEL_I2STX S3C2443_DMAREQSEL_SRC(4)
431#define S3C2443_DMAREQSEL_I2SRX S3C2443_DMAREQSEL_SRC(5)
432#define S3C2443_DMAREQSEL_TIMER S3C2443_DMAREQSEL_SRC(9)
433#define S3C2443_DMAREQSEL_SDI S3C2443_DMAREQSEL_SRC(10)
434#define S3C2443_DMAREQSEL_XDREQ0 S3C2443_DMAREQSEL_SRC(17)
435#define S3C2443_DMAREQSEL_XDREQ1 S3C2443_DMAREQSEL_SRC(18)
436#define S3C2443_DMAREQSEL_UART0_0 S3C2443_DMAREQSEL_SRC(19)
437#define S3C2443_DMAREQSEL_UART0_1 S3C2443_DMAREQSEL_SRC(20)
438#define S3C2443_DMAREQSEL_UART1_0 S3C2443_DMAREQSEL_SRC(21)
439#define S3C2443_DMAREQSEL_UART1_1 S3C2443_DMAREQSEL_SRC(22)
440#define S3C2443_DMAREQSEL_UART2_0 S3C2443_DMAREQSEL_SRC(23)
441#define S3C2443_DMAREQSEL_UART2_1 S3C2443_DMAREQSEL_SRC(24)
442#define S3C2443_DMAREQSEL_UART3_0 S3C2443_DMAREQSEL_SRC(25)
443#define S3C2443_DMAREQSEL_UART3_1 S3C2443_DMAREQSEL_SRC(26)
444#define S3C2443_DMAREQSEL_PCMOUT S3C2443_DMAREQSEL_SRC(27)
445#define S3C2443_DMAREQSEL_PCMIN S3C2443_DMAREQSEL_SRC(28)
446#define S3C2443_DMAREQSEL_MICIN S3C2443_DMAREQSEL_SRC(29)
447
448#endif /* __ASM_ARCH_DMA_H */ 197#endif /* __ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-core.h b/arch/arm/mach-s3c2410/include/mach/gpio-core.h
index 6c9fbb99ef14..8fe192081d3a 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio-core.h
+++ b/arch/arm/mach-s3c2410/include/mach/gpio-core.h
@@ -24,7 +24,7 @@ static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int pin)
24{ 24{
25 struct s3c_gpio_chip *chip; 25 struct s3c_gpio_chip *chip;
26 26
27 if (pin > S3C2410_GPG10) 27 if (pin > S3C2410_GPG(10))
28 return NULL; 28 return NULL;
29 29
30 chip = &s3c24xx_gpios[pin/32]; 30 chip = &s3c24xx_gpios[pin/32];
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h b/arch/arm/mach-s3c2410/include/mach/gpio-fns.h
new file mode 100644
index 000000000000..801dff13858d
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/gpio-fns.h
@@ -0,0 +1,103 @@
1/* arch/arm/mach-s3c2410/include/mach/gpio-fns.h
2 *
3 * Copyright (c) 2003,2009 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 - hardware
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* These functions are in the to-be-removed category and it is strongly
14 * encouraged not to use these in new code. They will be marked deprecated
15 * very soon.
16 *
17 * Most of the functionality can be either replaced by the gpiocfg calls
18 * for the s3c platform or by the generic GPIOlib API.
19*/
20
21/* external functions for GPIO support
22 *
23 * These allow various different clients to access the same GPIO
24 * registers without conflicting. If your driver only owns the entire
25 * GPIO register, then it is safe to ioremap/__raw_{read|write} to it.
26*/
27
28/* s3c2410_gpio_cfgpin
29 *
30 * set the configuration of the given pin to the value passed.
31 *
32 * eg:
33 * s3c2410_gpio_cfgpin(S3C2410_GPA(0), S3C2410_GPA0_ADDR0);
34 * s3c2410_gpio_cfgpin(S3C2410_GPE(8), S3C2410_GPE8_SDDAT1);
35*/
36
37extern void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function);
38
39extern unsigned int s3c2410_gpio_getcfg(unsigned int pin);
40
41/* s3c2410_gpio_getirq
42 *
43 * turn the given pin number into the corresponding IRQ number
44 *
45 * returns:
46 * < 0 = no interrupt for this pin
47 * >=0 = interrupt number for the pin
48*/
49
50extern int s3c2410_gpio_getirq(unsigned int pin);
51
52#ifdef CONFIG_CPU_S3C2400
53
54extern int s3c2400_gpio_getirq(unsigned int pin);
55
56#endif /* CONFIG_CPU_S3C2400 */
57
58/* s3c2410_gpio_irqfilter
59 *
60 * set the irq filtering on the given pin
61 *
62 * on = 0 => disable filtering
63 * 1 => enable filtering
64 *
65 * config = S3C2410_EINTFLT_PCLK or S3C2410_EINTFLT_EXTCLK orred with
66 * width of filter (0 through 63)
67 *
68 *
69*/
70
71extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
72 unsigned int config);
73
74/* s3c2410_gpio_pullup
75 *
76 * configure the pull-up control on the given pin
77 *
78 * to = 1 => disable the pull-up
79 * 0 => enable the pull-up
80 *
81 * eg;
82 *
83 * s3c2410_gpio_pullup(S3C2410_GPB(0), 0);
84 * s3c2410_gpio_pullup(S3C2410_GPE(8), 0);
85*/
86
87extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to);
88
89/* s3c2410_gpio_getpull
90 *
91 * Read the state of the pull-up on a given pin
92 *
93 * return:
94 * < 0 => error code
95 * 0 => enabled
96 * 1 => disabled
97*/
98
99extern int s3c2410_gpio_getpull(unsigned int pin);
100
101extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to);
102
103extern unsigned int s3c2410_gpio_getpin(unsigned int pin);
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h b/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
index ce1ec69806a1..2edbb9c88ab3 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
+++ b/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
@@ -11,6 +11,9 @@
11 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
12*/ 12*/
13 13
14#ifndef __MACH_GPIONRS_H
15#define __MACH_GPIONRS_H
16
14#define S3C2410_GPIONO(bank,offset) ((bank) + (offset)) 17#define S3C2410_GPIONO(bank,offset) ((bank) + (offset))
15 18
16#define S3C2410_GPIO_BANKA (32*0) 19#define S3C2410_GPIO_BANKA (32*0)
@@ -21,3 +24,70 @@
21#define S3C2410_GPIO_BANKF (32*5) 24#define S3C2410_GPIO_BANKF (32*5)
22#define S3C2410_GPIO_BANKG (32*6) 25#define S3C2410_GPIO_BANKG (32*6)
23#define S3C2410_GPIO_BANKH (32*7) 26#define S3C2410_GPIO_BANKH (32*7)
27
28/* GPIO bank sizes */
29#define S3C2410_GPIO_A_NR (32)
30#define S3C2410_GPIO_B_NR (32)
31#define S3C2410_GPIO_C_NR (32)
32#define S3C2410_GPIO_D_NR (32)
33#define S3C2410_GPIO_E_NR (32)
34#define S3C2410_GPIO_F_NR (32)
35#define S3C2410_GPIO_G_NR (32)
36#define S3C2410_GPIO_H_NR (32)
37
38#if CONFIG_S3C_GPIO_SPACE != 0
39#error CONFIG_S3C_GPIO_SPACE cannot be zero at the moment
40#endif
41
42#define S3C2410_GPIO_NEXT(__gpio) \
43 ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 0)
44
45#ifndef __ASSEMBLY__
46
47enum s3c_gpio_number {
48 S3C2410_GPIO_A_START = 0,
49 S3C2410_GPIO_B_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_A),
50 S3C2410_GPIO_C_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_B),
51 S3C2410_GPIO_D_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_C),
52 S3C2410_GPIO_E_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_D),
53 S3C2410_GPIO_F_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_E),
54 S3C2410_GPIO_G_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_F),
55 S3C2410_GPIO_H_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_G),
56};
57
58#endif /* __ASSEMBLY__ */
59
60/* S3C2410 GPIO number definitions. */
61
62#define S3C2410_GPA(_nr) (S3C2410_GPIO_A_START + (_nr))
63#define S3C2410_GPB(_nr) (S3C2410_GPIO_B_START + (_nr))
64#define S3C2410_GPC(_nr) (S3C2410_GPIO_C_START + (_nr))
65#define S3C2410_GPD(_nr) (S3C2410_GPIO_D_START + (_nr))
66#define S3C2410_GPE(_nr) (S3C2410_GPIO_E_START + (_nr))
67#define S3C2410_GPF(_nr) (S3C2410_GPIO_F_START + (_nr))
68#define S3C2410_GPG(_nr) (S3C2410_GPIO_G_START + (_nr))
69#define S3C2410_GPH(_nr) (S3C2410_GPIO_H_START + (_nr))
70
71/* compatibility until drivers can be modified */
72
73#define S3C2410_GPA0 S3C2410_GPA(0)
74#define S3C2410_GPA1 S3C2410_GPA(1)
75#define S3C2410_GPA3 S3C2410_GPA(3)
76#define S3C2410_GPA7 S3C2410_GPA(7)
77
78#define S3C2410_GPE0 S3C2410_GPE(0)
79#define S3C2410_GPE1 S3C2410_GPE(1)
80#define S3C2410_GPE2 S3C2410_GPE(2)
81#define S3C2410_GPE3 S3C2410_GPE(3)
82#define S3C2410_GPE4 S3C2410_GPE(4)
83#define S3C2410_GPE5 S3C2410_GPE(5)
84#define S3C2410_GPE6 S3C2410_GPE(6)
85#define S3C2410_GPE7 S3C2410_GPE(7)
86#define S3C2410_GPE8 S3C2410_GPE(8)
87#define S3C2410_GPE9 S3C2410_GPE(9)
88#define S3C2410_GPE10 S3C2410_GPE(10)
89
90#define S3C2410_GPH10 S3C2410_GPH(10)
91
92#endif /* __MACH_GPIONRS_H */
93
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio.h b/arch/arm/mach-s3c2410/include/mach/gpio.h
index 51a88cf9526b..15f0b3e7ce69 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio.h
+++ b/arch/arm/mach-s3c2410/include/mach/gpio.h
@@ -24,5 +24,6 @@
24 24
25#include <asm-generic/gpio.h> 25#include <asm-generic/gpio.h>
26#include <mach/gpio-nrs.h> 26#include <mach/gpio-nrs.h>
27#include <mach/gpio-fns.h>
27 28
28#define S3C_GPIO_END (S3C2410_GPIO_BANKH + 32) 29#define S3C_GPIO_END (S3C2410_GPIO_BANKH + 32)
diff --git a/arch/arm/mach-s3c2410/include/mach/hardware.h b/arch/arm/mach-s3c2410/include/mach/hardware.h
index 74d5a1a4024c..aef5631eac58 100644
--- a/arch/arm/mach-s3c2410/include/mach/hardware.h
+++ b/arch/arm/mach-s3c2410/include/mach/hardware.h
@@ -15,101 +15,6 @@
15 15
16#ifndef __ASSEMBLY__ 16#ifndef __ASSEMBLY__
17 17
18/* external functions for GPIO support
19 *
20 * These allow various different clients to access the same GPIO
21 * registers without conflicting. If your driver only owns the entire
22 * GPIO register, then it is safe to ioremap/__raw_{read|write} to it.
23*/
24
25/* s3c2410_gpio_cfgpin
26 *
27 * set the configuration of the given pin to the value passed.
28 *
29 * eg:
30 * s3c2410_gpio_cfgpin(S3C2410_GPA0, S3C2410_GPA0_ADDR0);
31 * s3c2410_gpio_cfgpin(S3C2410_GPE8, S3C2410_GPE8_SDDAT1);
32*/
33
34extern void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function);
35
36extern unsigned int s3c2410_gpio_getcfg(unsigned int pin);
37
38/* s3c2410_gpio_getirq
39 *
40 * turn the given pin number into the corresponding IRQ number
41 *
42 * returns:
43 * < 0 = no interrupt for this pin
44 * >=0 = interrupt number for the pin
45*/
46
47extern int s3c2410_gpio_getirq(unsigned int pin);
48
49/* s3c2410_gpio_irq2pin
50 *
51 * turn the given irq number into the corresponding GPIO number
52 *
53 * returns:
54 * < 0 = no pin
55 * >=0 = gpio pin number
56*/
57
58extern int s3c2410_gpio_irq2pin(unsigned int irq);
59
60#ifdef CONFIG_CPU_S3C2400
61
62extern int s3c2400_gpio_getirq(unsigned int pin);
63
64#endif /* CONFIG_CPU_S3C2400 */
65
66/* s3c2410_gpio_irqfilter
67 *
68 * set the irq filtering on the given pin
69 *
70 * on = 0 => disable filtering
71 * 1 => enable filtering
72 *
73 * config = S3C2410_EINTFLT_PCLK or S3C2410_EINTFLT_EXTCLK orred with
74 * width of filter (0 through 63)
75 *
76 *
77*/
78
79extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
80 unsigned int config);
81
82/* s3c2410_gpio_pullup
83 *
84 * configure the pull-up control on the given pin
85 *
86 * to = 1 => disable the pull-up
87 * 0 => enable the pull-up
88 *
89 * eg;
90 *
91 * s3c2410_gpio_pullup(S3C2410_GPB0, 0);
92 * s3c2410_gpio_pullup(S3C2410_GPE8, 0);
93*/
94
95extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to);
96
97/* s3c2410_gpio_getpull
98 *
99 * Read the state of the pull-up on a given pin
100 *
101 * return:
102 * < 0 => error code
103 * 0 => enabled
104 * 1 => disabled
105*/
106
107extern int s3c2410_gpio_getpull(unsigned int pin);
108
109extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to);
110
111extern unsigned int s3c2410_gpio_getpin(unsigned int pin);
112
113extern unsigned int s3c2410_modify_misccr(unsigned int clr, unsigned int chg); 18extern unsigned int s3c2410_modify_misccr(unsigned int clr, unsigned int chg);
114 19
115#ifdef CONFIG_CPU_S3C2440 20#ifdef CONFIG_CPU_S3C2440
diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c2410/include/mach/map.h
index 255fdfeaf957..e99b212cb1ca 100644
--- a/arch/arm/mach-s3c2410/include/mach/map.h
+++ b/arch/arm/mach-s3c2410/include/mach/map.h
@@ -84,7 +84,6 @@
84 84
85#define S3C24XX_PA_IRQ S3C2410_PA_IRQ 85#define S3C24XX_PA_IRQ S3C2410_PA_IRQ
86#define S3C24XX_PA_MEMCTRL S3C2410_PA_MEMCTRL 86#define S3C24XX_PA_MEMCTRL S3C2410_PA_MEMCTRL
87#define S3C24XX_PA_USBHOST S3C2410_PA_USBHOST
88#define S3C24XX_PA_DMA S3C2410_PA_DMA 87#define S3C24XX_PA_DMA S3C2410_PA_DMA
89#define S3C24XX_PA_CLKPWR S3C2410_PA_CLKPWR 88#define S3C24XX_PA_CLKPWR S3C2410_PA_CLKPWR
90#define S3C24XX_PA_LCD S3C2410_PA_LCD 89#define S3C24XX_PA_LCD S3C2410_PA_LCD
@@ -102,6 +101,7 @@
102 101
103#define S3C_PA_IIC S3C2410_PA_IIC 102#define S3C_PA_IIC S3C2410_PA_IIC
104#define S3C_PA_UART S3C24XX_PA_UART 103#define S3C_PA_UART S3C24XX_PA_UART
104#define S3C_PA_USBHOST S3C2410_PA_USBHOST
105#define S3C_PA_HSMMC0 S3C2443_PA_HSMMC 105#define S3C_PA_HSMMC0 S3C2443_PA_HSMMC
106 106
107#endif /* __ASM_ARCH_MAP_H */ 107#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
index 35a03df473fc..b278d0c45ccf 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
@@ -69,104 +69,58 @@
69#define S3C2400_GPACON S3C2410_GPIOREG(0x00) 69#define S3C2400_GPACON S3C2410_GPIOREG(0x00)
70#define S3C2400_GPADAT S3C2410_GPIOREG(0x04) 70#define S3C2400_GPADAT S3C2410_GPIOREG(0x04)
71 71
72#define S3C2410_GPA0 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 0)
73#define S3C2410_GPA0_OUT (0<<0)
74#define S3C2410_GPA0_ADDR0 (1<<0) 72#define S3C2410_GPA0_ADDR0 (1<<0)
75 73
76#define S3C2410_GPA1 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 1)
77#define S3C2410_GPA1_OUT (0<<1)
78#define S3C2410_GPA1_ADDR16 (1<<1) 74#define S3C2410_GPA1_ADDR16 (1<<1)
79 75
80#define S3C2410_GPA2 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 2)
81#define S3C2410_GPA2_OUT (0<<2)
82#define S3C2410_GPA2_ADDR17 (1<<2) 76#define S3C2410_GPA2_ADDR17 (1<<2)
83 77
84#define S3C2410_GPA3 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 3)
85#define S3C2410_GPA3_OUT (0<<3)
86#define S3C2410_GPA3_ADDR18 (1<<3) 78#define S3C2410_GPA3_ADDR18 (1<<3)
87 79
88#define S3C2410_GPA4 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 4)
89#define S3C2410_GPA4_OUT (0<<4)
90#define S3C2410_GPA4_ADDR19 (1<<4) 80#define S3C2410_GPA4_ADDR19 (1<<4)
91 81
92#define S3C2410_GPA5 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 5)
93#define S3C2410_GPA5_OUT (0<<5)
94#define S3C2410_GPA5_ADDR20 (1<<5) 82#define S3C2410_GPA5_ADDR20 (1<<5)
95 83
96#define S3C2410_GPA6 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 6)
97#define S3C2410_GPA6_OUT (0<<6)
98#define S3C2410_GPA6_ADDR21 (1<<6) 84#define S3C2410_GPA6_ADDR21 (1<<6)
99 85
100#define S3C2410_GPA7 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 7)
101#define S3C2410_GPA7_OUT (0<<7)
102#define S3C2410_GPA7_ADDR22 (1<<7) 86#define S3C2410_GPA7_ADDR22 (1<<7)
103 87
104#define S3C2410_GPA8 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 8)
105#define S3C2410_GPA8_OUT (0<<8)
106#define S3C2410_GPA8_ADDR23 (1<<8) 88#define S3C2410_GPA8_ADDR23 (1<<8)
107 89
108#define S3C2410_GPA9 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 9)
109#define S3C2410_GPA9_OUT (0<<9)
110#define S3C2410_GPA9_ADDR24 (1<<9) 90#define S3C2410_GPA9_ADDR24 (1<<9)
111 91
112#define S3C2410_GPA10 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 10)
113#define S3C2410_GPA10_OUT (0<<10)
114#define S3C2410_GPA10_ADDR25 (1<<10) 92#define S3C2410_GPA10_ADDR25 (1<<10)
115#define S3C2400_GPA10_SCKE (1<<10) 93#define S3C2400_GPA10_SCKE (1<<10)
116 94
117#define S3C2410_GPA11 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 11)
118#define S3C2410_GPA11_OUT (0<<11)
119#define S3C2410_GPA11_ADDR26 (1<<11) 95#define S3C2410_GPA11_ADDR26 (1<<11)
120#define S3C2400_GPA11_nCAS0 (1<<11) 96#define S3C2400_GPA11_nCAS0 (1<<11)
121 97
122#define S3C2410_GPA12 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 12)
123#define S3C2410_GPA12_OUT (0<<12)
124#define S3C2410_GPA12_nGCS1 (1<<12) 98#define S3C2410_GPA12_nGCS1 (1<<12)
125#define S3C2400_GPA12_nCAS1 (1<<12) 99#define S3C2400_GPA12_nCAS1 (1<<12)
126 100
127#define S3C2410_GPA13 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 13)
128#define S3C2410_GPA13_OUT (0<<13)
129#define S3C2410_GPA13_nGCS2 (1<<13) 101#define S3C2410_GPA13_nGCS2 (1<<13)
130#define S3C2400_GPA13_nGCS1 (1<<13) 102#define S3C2400_GPA13_nGCS1 (1<<13)
131 103
132#define S3C2410_GPA14 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 14)
133#define S3C2410_GPA14_OUT (0<<14)
134#define S3C2410_GPA14_nGCS3 (1<<14) 104#define S3C2410_GPA14_nGCS3 (1<<14)
135#define S3C2400_GPA14_nGCS2 (1<<14) 105#define S3C2400_GPA14_nGCS2 (1<<14)
136 106
137#define S3C2410_GPA15 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 15)
138#define S3C2410_GPA15_OUT (0<<15)
139#define S3C2410_GPA15_nGCS4 (1<<15) 107#define S3C2410_GPA15_nGCS4 (1<<15)
140#define S3C2400_GPA15_nGCS3 (1<<15) 108#define S3C2400_GPA15_nGCS3 (1<<15)
141 109
142#define S3C2410_GPA16 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 16)
143#define S3C2410_GPA16_OUT (0<<16)
144#define S3C2410_GPA16_nGCS5 (1<<16) 110#define S3C2410_GPA16_nGCS5 (1<<16)
145#define S3C2400_GPA16_nGCS4 (1<<16) 111#define S3C2400_GPA16_nGCS4 (1<<16)
146 112
147#define S3C2410_GPA17 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 17)
148#define S3C2410_GPA17_OUT (0<<17)
149#define S3C2410_GPA17_CLE (1<<17) 113#define S3C2410_GPA17_CLE (1<<17)
150#define S3C2400_GPA17_nGCS5 (1<<17) 114#define S3C2400_GPA17_nGCS5 (1<<17)
151 115
152#define S3C2410_GPA18 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 18)
153#define S3C2410_GPA18_OUT (0<<18)
154#define S3C2410_GPA18_ALE (1<<18) 116#define S3C2410_GPA18_ALE (1<<18)
155 117
156#define S3C2410_GPA19 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 19)
157#define S3C2410_GPA19_OUT (0<<19)
158#define S3C2410_GPA19_nFWE (1<<19) 118#define S3C2410_GPA19_nFWE (1<<19)
159 119
160#define S3C2410_GPA20 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 20)
161#define S3C2410_GPA20_OUT (0<<20)
162#define S3C2410_GPA20_nFRE (1<<20) 120#define S3C2410_GPA20_nFRE (1<<20)
163 121
164#define S3C2410_GPA21 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 21)
165#define S3C2410_GPA21_OUT (0<<21)
166#define S3C2410_GPA21_nRSTOUT (1<<21) 122#define S3C2410_GPA21_nRSTOUT (1<<21)
167 123
168#define S3C2410_GPA22 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 22)
169#define S3C2410_GPA22_OUT (0<<22)
170#define S3C2410_GPA22_nFCE (1<<22) 124#define S3C2410_GPA22_nFCE (1<<22)
171 125
172/* 0x08 and 0x0c are reserved on S3C2410 */ 126/* 0x08 and 0x0c are reserved on S3C2410 */
@@ -194,107 +148,69 @@
194 148
195/* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */ 149/* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */
196 150
197#define S3C2410_GPB0 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 0)
198#define S3C2410_GPB0_INP (0x00 << 0)
199#define S3C2410_GPB0_OUTP (0x01 << 0)
200#define S3C2410_GPB0_TOUT0 (0x02 << 0) 151#define S3C2410_GPB0_TOUT0 (0x02 << 0)
201#define S3C2400_GPB0_DATA16 (0x02 << 0) 152#define S3C2400_GPB0_DATA16 (0x02 << 0)
202 153
203#define S3C2410_GPB1 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 1)
204#define S3C2410_GPB1_INP (0x00 << 2)
205#define S3C2410_GPB1_OUTP (0x01 << 2)
206#define S3C2410_GPB1_TOUT1 (0x02 << 2) 154#define S3C2410_GPB1_TOUT1 (0x02 << 2)
207#define S3C2400_GPB1_DATA17 (0x02 << 2) 155#define S3C2400_GPB1_DATA17 (0x02 << 2)
208 156
209#define S3C2410_GPB2 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 2)
210#define S3C2410_GPB2_INP (0x00 << 4)
211#define S3C2410_GPB2_OUTP (0x01 << 4)
212#define S3C2410_GPB2_TOUT2 (0x02 << 4) 157#define S3C2410_GPB2_TOUT2 (0x02 << 4)
213#define S3C2400_GPB2_DATA18 (0x02 << 4) 158#define S3C2400_GPB2_DATA18 (0x02 << 4)
214#define S3C2400_GPB2_TCLK1 (0x03 << 4) 159#define S3C2400_GPB2_TCLK1 (0x03 << 4)
215 160
216#define S3C2410_GPB3 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 3)
217#define S3C2410_GPB3_INP (0x00 << 6)
218#define S3C2410_GPB3_OUTP (0x01 << 6)
219#define S3C2410_GPB3_TOUT3 (0x02 << 6) 161#define S3C2410_GPB3_TOUT3 (0x02 << 6)
220#define S3C2400_GPB3_DATA19 (0x02 << 6) 162#define S3C2400_GPB3_DATA19 (0x02 << 6)
221#define S3C2400_GPB3_TXD1 (0x03 << 6) 163#define S3C2400_GPB3_TXD1 (0x03 << 6)
222 164
223#define S3C2410_GPB4 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 4)
224#define S3C2410_GPB4_INP (0x00 << 8)
225#define S3C2410_GPB4_OUTP (0x01 << 8)
226#define S3C2410_GPB4_TCLK0 (0x02 << 8) 165#define S3C2410_GPB4_TCLK0 (0x02 << 8)
227#define S3C2400_GPB4_DATA20 (0x02 << 8) 166#define S3C2400_GPB4_DATA20 (0x02 << 8)
228#define S3C2410_GPB4_MASK (0x03 << 8) 167#define S3C2410_GPB4_MASK (0x03 << 8)
229#define S3C2400_GPB4_RXD1 (0x03 << 8) 168#define S3C2400_GPB4_RXD1 (0x03 << 8)
230#define S3C2400_GPB4_MASK (0x03 << 8) 169#define S3C2400_GPB4_MASK (0x03 << 8)
231 170
232#define S3C2410_GPB5 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 5)
233#define S3C2410_GPB5_INP (0x00 << 10)
234#define S3C2410_GPB5_OUTP (0x01 << 10)
235#define S3C2410_GPB5_nXBACK (0x02 << 10) 171#define S3C2410_GPB5_nXBACK (0x02 << 10)
236#define S3C2443_GPB5_XBACK (0x03 << 10) 172#define S3C2443_GPB5_XBACK (0x03 << 10)
237#define S3C2400_GPB5_DATA21 (0x02 << 10) 173#define S3C2400_GPB5_DATA21 (0x02 << 10)
238#define S3C2400_GPB5_nCTS1 (0x03 << 10) 174#define S3C2400_GPB5_nCTS1 (0x03 << 10)
239 175
240#define S3C2410_GPB6 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 6)
241#define S3C2410_GPB6_INP (0x00 << 12)
242#define S3C2410_GPB6_OUTP (0x01 << 12)
243#define S3C2410_GPB6_nXBREQ (0x02 << 12) 176#define S3C2410_GPB6_nXBREQ (0x02 << 12)
244#define S3C2443_GPB6_XBREQ (0x03 << 12) 177#define S3C2443_GPB6_XBREQ (0x03 << 12)
245#define S3C2400_GPB6_DATA22 (0x02 << 12) 178#define S3C2400_GPB6_DATA22 (0x02 << 12)
246#define S3C2400_GPB6_nRTS1 (0x03 << 12) 179#define S3C2400_GPB6_nRTS1 (0x03 << 12)
247 180
248#define S3C2410_GPB7 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 7)
249#define S3C2410_GPB7_INP (0x00 << 14)
250#define S3C2410_GPB7_OUTP (0x01 << 14)
251#define S3C2410_GPB7_nXDACK1 (0x02 << 14) 181#define S3C2410_GPB7_nXDACK1 (0x02 << 14)
252#define S3C2443_GPB7_XDACK1 (0x03 << 14) 182#define S3C2443_GPB7_XDACK1 (0x03 << 14)
253#define S3C2400_GPB7_DATA23 (0x02 << 14) 183#define S3C2400_GPB7_DATA23 (0x02 << 14)
254 184
255#define S3C2410_GPB8 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 8)
256#define S3C2410_GPB8_INP (0x00 << 16)
257#define S3C2410_GPB8_OUTP (0x01 << 16)
258#define S3C2410_GPB8_nXDREQ1 (0x02 << 16) 185#define S3C2410_GPB8_nXDREQ1 (0x02 << 16)
259#define S3C2400_GPB8_DATA24 (0x02 << 16) 186#define S3C2400_GPB8_DATA24 (0x02 << 16)
260 187
261#define S3C2410_GPB9 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 9)
262#define S3C2410_GPB9_INP (0x00 << 18)
263#define S3C2410_GPB9_OUTP (0x01 << 18)
264#define S3C2410_GPB9_nXDACK0 (0x02 << 18) 188#define S3C2410_GPB9_nXDACK0 (0x02 << 18)
265#define S3C2443_GPB9_XDACK0 (0x03 << 18) 189#define S3C2443_GPB9_XDACK0 (0x03 << 18)
266#define S3C2400_GPB9_DATA25 (0x02 << 18) 190#define S3C2400_GPB9_DATA25 (0x02 << 18)
267#define S3C2400_GPB9_I2SSDI (0x03 << 18) 191#define S3C2400_GPB9_I2SSDI (0x03 << 18)
268 192
269#define S3C2410_GPB10 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 10)
270#define S3C2410_GPB10_INP (0x00 << 20)
271#define S3C2410_GPB10_OUTP (0x01 << 20)
272#define S3C2410_GPB10_nXDRE0 (0x02 << 20) 193#define S3C2410_GPB10_nXDRE0 (0x02 << 20)
273#define S3C2443_GPB10_XDREQ0 (0x03 << 20) 194#define S3C2443_GPB10_XDREQ0 (0x03 << 20)
274#define S3C2400_GPB10_DATA26 (0x02 << 20) 195#define S3C2400_GPB10_DATA26 (0x02 << 20)
275#define S3C2400_GPB10_nSS (0x03 << 20) 196#define S3C2400_GPB10_nSS (0x03 << 20)
276 197
277#define S3C2400_GPB11 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 11)
278#define S3C2400_GPB11_INP (0x00 << 22) 198#define S3C2400_GPB11_INP (0x00 << 22)
279#define S3C2400_GPB11_OUTP (0x01 << 22) 199#define S3C2400_GPB11_OUTP (0x01 << 22)
280#define S3C2400_GPB11_DATA27 (0x02 << 22) 200#define S3C2400_GPB11_DATA27 (0x02 << 22)
281 201
282#define S3C2400_GPB12 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 12)
283#define S3C2400_GPB12_INP (0x00 << 24) 202#define S3C2400_GPB12_INP (0x00 << 24)
284#define S3C2400_GPB12_OUTP (0x01 << 24) 203#define S3C2400_GPB12_OUTP (0x01 << 24)
285#define S3C2400_GPB12_DATA28 (0x02 << 24) 204#define S3C2400_GPB12_DATA28 (0x02 << 24)
286 205
287#define S3C2400_GPB13 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 13)
288#define S3C2400_GPB13_INP (0x00 << 26) 206#define S3C2400_GPB13_INP (0x00 << 26)
289#define S3C2400_GPB13_OUTP (0x01 << 26) 207#define S3C2400_GPB13_OUTP (0x01 << 26)
290#define S3C2400_GPB13_DATA29 (0x02 << 26) 208#define S3C2400_GPB13_DATA29 (0x02 << 26)
291 209
292#define S3C2400_GPB14 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 14)
293#define S3C2400_GPB14_INP (0x00 << 28) 210#define S3C2400_GPB14_INP (0x00 << 28)
294#define S3C2400_GPB14_OUTP (0x01 << 28) 211#define S3C2400_GPB14_OUTP (0x01 << 28)
295#define S3C2400_GPB14_DATA30 (0x02 << 28) 212#define S3C2400_GPB14_DATA30 (0x02 << 28)
296 213
297#define S3C2400_GPB15 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 15)
298#define S3C2400_GPB15_INP (0x00 << 30) 214#define S3C2400_GPB15_INP (0x00 << 30)
299#define S3C2400_GPB15_OUTP (0x01 << 30) 215#define S3C2400_GPB15_OUTP (0x01 << 30)
300#define S3C2400_GPB15_DATA31 (0x02 << 30) 216#define S3C2400_GPB15_DATA31 (0x02 << 30)
@@ -315,99 +231,51 @@
315#define S3C2400_GPCDAT S3C2410_GPIOREG(0x18) 231#define S3C2400_GPCDAT S3C2410_GPIOREG(0x18)
316#define S3C2400_GPCUP S3C2410_GPIOREG(0x1C) 232#define S3C2400_GPCUP S3C2410_GPIOREG(0x1C)
317 233
318#define S3C2410_GPC0 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 0)
319#define S3C2410_GPC0_INP (0x00 << 0)
320#define S3C2410_GPC0_OUTP (0x01 << 0)
321#define S3C2410_GPC0_LEND (0x02 << 0) 234#define S3C2410_GPC0_LEND (0x02 << 0)
322#define S3C2400_GPC0_VD0 (0x02 << 0) 235#define S3C2400_GPC0_VD0 (0x02 << 0)
323 236
324#define S3C2410_GPC1 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 1)
325#define S3C2410_GPC1_INP (0x00 << 2)
326#define S3C2410_GPC1_OUTP (0x01 << 2)
327#define S3C2410_GPC1_VCLK (0x02 << 2) 237#define S3C2410_GPC1_VCLK (0x02 << 2)
328#define S3C2400_GPC1_VD1 (0x02 << 2) 238#define S3C2400_GPC1_VD1 (0x02 << 2)
329 239
330#define S3C2410_GPC2 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 2)
331#define S3C2410_GPC2_INP (0x00 << 4)
332#define S3C2410_GPC2_OUTP (0x01 << 4)
333#define S3C2410_GPC2_VLINE (0x02 << 4) 240#define S3C2410_GPC2_VLINE (0x02 << 4)
334#define S3C2400_GPC2_VD2 (0x02 << 4) 241#define S3C2400_GPC2_VD2 (0x02 << 4)
335 242
336#define S3C2410_GPC3 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 3)
337#define S3C2410_GPC3_INP (0x00 << 6)
338#define S3C2410_GPC3_OUTP (0x01 << 6)
339#define S3C2410_GPC3_VFRAME (0x02 << 6) 243#define S3C2410_GPC3_VFRAME (0x02 << 6)
340#define S3C2400_GPC3_VD3 (0x02 << 6) 244#define S3C2400_GPC3_VD3 (0x02 << 6)
341 245
342#define S3C2410_GPC4 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 4)
343#define S3C2410_GPC4_INP (0x00 << 8)
344#define S3C2410_GPC4_OUTP (0x01 << 8)
345#define S3C2410_GPC4_VM (0x02 << 8) 246#define S3C2410_GPC4_VM (0x02 << 8)
346#define S3C2400_GPC4_VD4 (0x02 << 8) 247#define S3C2400_GPC4_VD4 (0x02 << 8)
347 248
348#define S3C2410_GPC5 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 5)
349#define S3C2410_GPC5_INP (0x00 << 10)
350#define S3C2410_GPC5_OUTP (0x01 << 10)
351#define S3C2410_GPC5_LCDVF0 (0x02 << 10) 249#define S3C2410_GPC5_LCDVF0 (0x02 << 10)
352#define S3C2400_GPC5_VD5 (0x02 << 10) 250#define S3C2400_GPC5_VD5 (0x02 << 10)
353 251
354#define S3C2410_GPC6 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 6)
355#define S3C2410_GPC6_INP (0x00 << 12)
356#define S3C2410_GPC6_OUTP (0x01 << 12)
357#define S3C2410_GPC6_LCDVF1 (0x02 << 12) 252#define S3C2410_GPC6_LCDVF1 (0x02 << 12)
358#define S3C2400_GPC6_VD6 (0x02 << 12) 253#define S3C2400_GPC6_VD6 (0x02 << 12)
359 254
360#define S3C2410_GPC7 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 7)
361#define S3C2410_GPC7_INP (0x00 << 14)
362#define S3C2410_GPC7_OUTP (0x01 << 14)
363#define S3C2410_GPC7_LCDVF2 (0x02 << 14) 255#define S3C2410_GPC7_LCDVF2 (0x02 << 14)
364#define S3C2400_GPC7_VD7 (0x02 << 14) 256#define S3C2400_GPC7_VD7 (0x02 << 14)
365 257
366#define S3C2410_GPC8 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 8)
367#define S3C2410_GPC8_INP (0x00 << 16)
368#define S3C2410_GPC8_OUTP (0x01 << 16)
369#define S3C2410_GPC8_VD0 (0x02 << 16) 258#define S3C2410_GPC8_VD0 (0x02 << 16)
370#define S3C2400_GPC8_VD8 (0x02 << 16) 259#define S3C2400_GPC8_VD8 (0x02 << 16)
371 260
372#define S3C2410_GPC9 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 9)
373#define S3C2410_GPC9_INP (0x00 << 18)
374#define S3C2410_GPC9_OUTP (0x01 << 18)
375#define S3C2410_GPC9_VD1 (0x02 << 18) 261#define S3C2410_GPC9_VD1 (0x02 << 18)
376#define S3C2400_GPC9_VD9 (0x02 << 18) 262#define S3C2400_GPC9_VD9 (0x02 << 18)
377 263
378#define S3C2410_GPC10 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 10)
379#define S3C2410_GPC10_INP (0x00 << 20)
380#define S3C2410_GPC10_OUTP (0x01 << 20)
381#define S3C2410_GPC10_VD2 (0x02 << 20) 264#define S3C2410_GPC10_VD2 (0x02 << 20)
382#define S3C2400_GPC10_VD10 (0x02 << 20) 265#define S3C2400_GPC10_VD10 (0x02 << 20)
383 266
384#define S3C2410_GPC11 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 11)
385#define S3C2410_GPC11_INP (0x00 << 22)
386#define S3C2410_GPC11_OUTP (0x01 << 22)
387#define S3C2410_GPC11_VD3 (0x02 << 22) 267#define S3C2410_GPC11_VD3 (0x02 << 22)
388#define S3C2400_GPC11_VD11 (0x02 << 22) 268#define S3C2400_GPC11_VD11 (0x02 << 22)
389 269
390#define S3C2410_GPC12 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 12)
391#define S3C2410_GPC12_INP (0x00 << 24)
392#define S3C2410_GPC12_OUTP (0x01 << 24)
393#define S3C2410_GPC12_VD4 (0x02 << 24) 270#define S3C2410_GPC12_VD4 (0x02 << 24)
394#define S3C2400_GPC12_VD12 (0x02 << 24) 271#define S3C2400_GPC12_VD12 (0x02 << 24)
395 272
396#define S3C2410_GPC13 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 13)
397#define S3C2410_GPC13_INP (0x00 << 26)
398#define S3C2410_GPC13_OUTP (0x01 << 26)
399#define S3C2410_GPC13_VD5 (0x02 << 26) 273#define S3C2410_GPC13_VD5 (0x02 << 26)
400#define S3C2400_GPC13_VD13 (0x02 << 26) 274#define S3C2400_GPC13_VD13 (0x02 << 26)
401 275
402#define S3C2410_GPC14 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 14)
403#define S3C2410_GPC14_INP (0x00 << 28)
404#define S3C2410_GPC14_OUTP (0x01 << 28)
405#define S3C2410_GPC14_VD6 (0x02 << 28) 276#define S3C2410_GPC14_VD6 (0x02 << 28)
406#define S3C2400_GPC14_VD14 (0x02 << 28) 277#define S3C2400_GPC14_VD14 (0x02 << 28)
407 278
408#define S3C2410_GPC15 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 15)
409#define S3C2410_GPC15_INP (0x00 << 30)
410#define S3C2410_GPC15_OUTP (0x01 << 30)
411#define S3C2410_GPC15_VD7 (0x02 << 30) 279#define S3C2410_GPC15_VD7 (0x02 << 30)
412#define S3C2400_GPC15_VD15 (0x02 << 30) 280#define S3C2400_GPC15_VD15 (0x02 << 30)
413 281
@@ -432,99 +300,51 @@
432#define S3C2400_GPDDAT S3C2410_GPIOREG(0x24) 300#define S3C2400_GPDDAT S3C2410_GPIOREG(0x24)
433#define S3C2400_GPDUP S3C2410_GPIOREG(0x28) 301#define S3C2400_GPDUP S3C2410_GPIOREG(0x28)
434 302
435#define S3C2410_GPD0 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 0)
436#define S3C2410_GPD0_INP (0x00 << 0)
437#define S3C2410_GPD0_OUTP (0x01 << 0)
438#define S3C2410_GPD0_VD8 (0x02 << 0) 303#define S3C2410_GPD0_VD8 (0x02 << 0)
439#define S3C2400_GPD0_VFRAME (0x02 << 0) 304#define S3C2400_GPD0_VFRAME (0x02 << 0)
440#define S3C2442_GPD0_nSPICS1 (0x03 << 0) 305#define S3C2442_GPD0_nSPICS1 (0x03 << 0)
441 306
442#define S3C2410_GPD1 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 1)
443#define S3C2410_GPD1_INP (0x00 << 2)
444#define S3C2410_GPD1_OUTP (0x01 << 2)
445#define S3C2410_GPD1_VD9 (0x02 << 2) 307#define S3C2410_GPD1_VD9 (0x02 << 2)
446#define S3C2400_GPD1_VM (0x02 << 2) 308#define S3C2400_GPD1_VM (0x02 << 2)
447#define S3C2442_GPD1_SPICLK1 (0x03 << 2) 309#define S3C2442_GPD1_SPICLK1 (0x03 << 2)
448 310
449#define S3C2410_GPD2 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 2)
450#define S3C2410_GPD2_INP (0x00 << 4)
451#define S3C2410_GPD2_OUTP (0x01 << 4)
452#define S3C2410_GPD2_VD10 (0x02 << 4) 311#define S3C2410_GPD2_VD10 (0x02 << 4)
453#define S3C2400_GPD2_VLINE (0x02 << 4) 312#define S3C2400_GPD2_VLINE (0x02 << 4)
454 313
455#define S3C2410_GPD3 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 3)
456#define S3C2410_GPD3_INP (0x00 << 6)
457#define S3C2410_GPD3_OUTP (0x01 << 6)
458#define S3C2410_GPD3_VD11 (0x02 << 6) 314#define S3C2410_GPD3_VD11 (0x02 << 6)
459#define S3C2400_GPD3_VCLK (0x02 << 6) 315#define S3C2400_GPD3_VCLK (0x02 << 6)
460 316
461#define S3C2410_GPD4 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 4)
462#define S3C2410_GPD4_INP (0x00 << 8)
463#define S3C2410_GPD4_OUTP (0x01 << 8)
464#define S3C2410_GPD4_VD12 (0x02 << 8) 317#define S3C2410_GPD4_VD12 (0x02 << 8)
465#define S3C2400_GPD4_LEND (0x02 << 8) 318#define S3C2400_GPD4_LEND (0x02 << 8)
466 319
467#define S3C2410_GPD5 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 5)
468#define S3C2410_GPD5_INP (0x00 << 10)
469#define S3C2410_GPD5_OUTP (0x01 << 10)
470#define S3C2410_GPD5_VD13 (0x02 << 10) 320#define S3C2410_GPD5_VD13 (0x02 << 10)
471#define S3C2400_GPD5_TOUT0 (0x02 << 10) 321#define S3C2400_GPD5_TOUT0 (0x02 << 10)
472 322
473#define S3C2410_GPD6 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 6)
474#define S3C2410_GPD6_INP (0x00 << 12)
475#define S3C2410_GPD6_OUTP (0x01 << 12)
476#define S3C2410_GPD6_VD14 (0x02 << 12) 323#define S3C2410_GPD6_VD14 (0x02 << 12)
477#define S3C2400_GPD6_TOUT1 (0x02 << 12) 324#define S3C2400_GPD6_TOUT1 (0x02 << 12)
478 325
479#define S3C2410_GPD7 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 7)
480#define S3C2410_GPD7_INP (0x00 << 14)
481#define S3C2410_GPD7_OUTP (0x01 << 14)
482#define S3C2410_GPD7_VD15 (0x02 << 14) 326#define S3C2410_GPD7_VD15 (0x02 << 14)
483#define S3C2400_GPD7_TOUT2 (0x02 << 14) 327#define S3C2400_GPD7_TOUT2 (0x02 << 14)
484 328
485#define S3C2410_GPD8 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 8)
486#define S3C2410_GPD8_INP (0x00 << 16)
487#define S3C2410_GPD8_OUTP (0x01 << 16)
488#define S3C2410_GPD8_VD16 (0x02 << 16) 329#define S3C2410_GPD8_VD16 (0x02 << 16)
489#define S3C2400_GPD8_TOUT3 (0x02 << 16) 330#define S3C2400_GPD8_TOUT3 (0x02 << 16)
490 331
491#define S3C2410_GPD9 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 9)
492#define S3C2410_GPD9_INP (0x00 << 18)
493#define S3C2410_GPD9_OUTP (0x01 << 18)
494#define S3C2410_GPD9_VD17 (0x02 << 18) 332#define S3C2410_GPD9_VD17 (0x02 << 18)
495#define S3C2400_GPD9_TCLK0 (0x02 << 18) 333#define S3C2400_GPD9_TCLK0 (0x02 << 18)
496#define S3C2410_GPD9_MASK (0x03 << 18) 334#define S3C2410_GPD9_MASK (0x03 << 18)
497 335
498#define S3C2410_GPD10 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 10)
499#define S3C2410_GPD10_INP (0x00 << 20)
500#define S3C2410_GPD10_OUTP (0x01 << 20)
501#define S3C2410_GPD10_VD18 (0x02 << 20) 336#define S3C2410_GPD10_VD18 (0x02 << 20)
502#define S3C2400_GPD10_nWAIT (0x02 << 20) 337#define S3C2400_GPD10_nWAIT (0x02 << 20)
503 338
504#define S3C2410_GPD11 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 11)
505#define S3C2410_GPD11_INP (0x00 << 22)
506#define S3C2410_GPD11_OUTP (0x01 << 22)
507#define S3C2410_GPD11_VD19 (0x02 << 22) 339#define S3C2410_GPD11_VD19 (0x02 << 22)
508 340
509#define S3C2410_GPD12 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 12)
510#define S3C2410_GPD12_INP (0x00 << 24)
511#define S3C2410_GPD12_OUTP (0x01 << 24)
512#define S3C2410_GPD12_VD20 (0x02 << 24) 341#define S3C2410_GPD12_VD20 (0x02 << 24)
513 342
514#define S3C2410_GPD13 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 13)
515#define S3C2410_GPD13_INP (0x00 << 26)
516#define S3C2410_GPD13_OUTP (0x01 << 26)
517#define S3C2410_GPD13_VD21 (0x02 << 26) 343#define S3C2410_GPD13_VD21 (0x02 << 26)
518 344
519#define S3C2410_GPD14 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 14)
520#define S3C2410_GPD14_INP (0x00 << 28)
521#define S3C2410_GPD14_OUTP (0x01 << 28)
522#define S3C2410_GPD14_VD22 (0x02 << 28) 345#define S3C2410_GPD14_VD22 (0x02 << 28)
523#define S3C2410_GPD14_nSS1 (0x03 << 28) 346#define S3C2410_GPD14_nSS1 (0x03 << 28)
524 347
525#define S3C2410_GPD15 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 15)
526#define S3C2410_GPD15_INP (0x00 << 30)
527#define S3C2410_GPD15_OUTP (0x01 << 30)
528#define S3C2410_GPD15_VD23 (0x02 << 30) 348#define S3C2410_GPD15_VD23 (0x02 << 30)
529#define S3C2410_GPD15_nSS0 (0x03 << 30) 349#define S3C2410_GPD15_nSS0 (0x03 << 30)
530 350
@@ -550,34 +370,22 @@
550#define S3C2400_GPEDAT S3C2410_GPIOREG(0x30) 370#define S3C2400_GPEDAT S3C2410_GPIOREG(0x30)
551#define S3C2400_GPEUP S3C2410_GPIOREG(0x34) 371#define S3C2400_GPEUP S3C2410_GPIOREG(0x34)
552 372
553#define S3C2410_GPE0 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 0)
554#define S3C2410_GPE0_INP (0x00 << 0)
555#define S3C2410_GPE0_OUTP (0x01 << 0)
556#define S3C2410_GPE0_I2SLRCK (0x02 << 0) 373#define S3C2410_GPE0_I2SLRCK (0x02 << 0)
557#define S3C2443_GPE0_AC_nRESET (0x03 << 0) 374#define S3C2443_GPE0_AC_nRESET (0x03 << 0)
558#define S3C2400_GPE0_EINT0 (0x02 << 0) 375#define S3C2400_GPE0_EINT0 (0x02 << 0)
559#define S3C2410_GPE0_MASK (0x03 << 0) 376#define S3C2410_GPE0_MASK (0x03 << 0)
560 377
561#define S3C2410_GPE1 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 1)
562#define S3C2410_GPE1_INP (0x00 << 2)
563#define S3C2410_GPE1_OUTP (0x01 << 2)
564#define S3C2410_GPE1_I2SSCLK (0x02 << 2) 378#define S3C2410_GPE1_I2SSCLK (0x02 << 2)
565#define S3C2443_GPE1_AC_SYNC (0x03 << 2) 379#define S3C2443_GPE1_AC_SYNC (0x03 << 2)
566#define S3C2400_GPE1_EINT1 (0x02 << 2) 380#define S3C2400_GPE1_EINT1 (0x02 << 2)
567#define S3C2400_GPE1_nSS (0x03 << 2) 381#define S3C2400_GPE1_nSS (0x03 << 2)
568#define S3C2410_GPE1_MASK (0x03 << 2) 382#define S3C2410_GPE1_MASK (0x03 << 2)
569 383
570#define S3C2410_GPE2 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 2)
571#define S3C2410_GPE2_INP (0x00 << 4)
572#define S3C2410_GPE2_OUTP (0x01 << 4)
573#define S3C2410_GPE2_CDCLK (0x02 << 4) 384#define S3C2410_GPE2_CDCLK (0x02 << 4)
574#define S3C2443_GPE2_AC_BITCLK (0x03 << 4) 385#define S3C2443_GPE2_AC_BITCLK (0x03 << 4)
575#define S3C2400_GPE2_EINT2 (0x02 << 4) 386#define S3C2400_GPE2_EINT2 (0x02 << 4)
576#define S3C2400_GPE2_I2SSDI (0x03 << 4) 387#define S3C2400_GPE2_I2SSDI (0x03 << 4)
577 388
578#define S3C2410_GPE3 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 3)
579#define S3C2410_GPE3_INP (0x00 << 6)
580#define S3C2410_GPE3_OUTP (0x01 << 6)
581#define S3C2410_GPE3_I2SSDI (0x02 << 6) 389#define S3C2410_GPE3_I2SSDI (0x02 << 6)
582#define S3C2443_GPE3_AC_SDI (0x03 << 6) 390#define S3C2443_GPE3_AC_SDI (0x03 << 6)
583#define S3C2400_GPE3_EINT3 (0x02 << 6) 391#define S3C2400_GPE3_EINT3 (0x02 << 6)
@@ -585,9 +393,6 @@
585#define S3C2410_GPE3_nSS0 (0x03 << 6) 393#define S3C2410_GPE3_nSS0 (0x03 << 6)
586#define S3C2410_GPE3_MASK (0x03 << 6) 394#define S3C2410_GPE3_MASK (0x03 << 6)
587 395
588#define S3C2410_GPE4 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 4)
589#define S3C2410_GPE4_INP (0x00 << 8)
590#define S3C2410_GPE4_OUTP (0x01 << 8)
591#define S3C2410_GPE4_I2SSDO (0x02 << 8) 396#define S3C2410_GPE4_I2SSDO (0x02 << 8)
592#define S3C2443_GPE4_AC_SDO (0x03 << 8) 397#define S3C2443_GPE4_AC_SDO (0x03 << 8)
593#define S3C2400_GPE4_EINT4 (0x02 << 8) 398#define S3C2400_GPE4_EINT4 (0x02 << 8)
@@ -595,81 +400,48 @@
595#define S3C2410_GPE4_I2SSDI (0x03 << 8) 400#define S3C2410_GPE4_I2SSDI (0x03 << 8)
596#define S3C2410_GPE4_MASK (0x03 << 8) 401#define S3C2410_GPE4_MASK (0x03 << 8)
597 402
598#define S3C2410_GPE5 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 5)
599#define S3C2410_GPE5_INP (0x00 << 10)
600#define S3C2410_GPE5_OUTP (0x01 << 10)
601#define S3C2410_GPE5_SDCLK (0x02 << 10) 403#define S3C2410_GPE5_SDCLK (0x02 << 10)
602#define S3C2443_GPE5_SD1_CLK (0x02 << 10) 404#define S3C2443_GPE5_SD1_CLK (0x02 << 10)
603#define S3C2400_GPE5_EINT5 (0x02 << 10) 405#define S3C2400_GPE5_EINT5 (0x02 << 10)
604#define S3C2400_GPE5_TCLK1 (0x03 << 10) 406#define S3C2400_GPE5_TCLK1 (0x03 << 10)
605 407
606#define S3C2410_GPE6 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 6)
607#define S3C2410_GPE6_INP (0x00 << 12)
608#define S3C2410_GPE6_OUTP (0x01 << 12)
609#define S3C2410_GPE6_SDCMD (0x02 << 12) 408#define S3C2410_GPE6_SDCMD (0x02 << 12)
610#define S3C2443_GPE6_SD1_CMD (0x02 << 12) 409#define S3C2443_GPE6_SD1_CMD (0x02 << 12)
611#define S3C2443_GPE6_AC_BITCLK (0x03 << 12) 410#define S3C2443_GPE6_AC_BITCLK (0x03 << 12)
612#define S3C2400_GPE6_EINT6 (0x02 << 12) 411#define S3C2400_GPE6_EINT6 (0x02 << 12)
613 412
614#define S3C2410_GPE7 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 7)
615#define S3C2410_GPE7_INP (0x00 << 14)
616#define S3C2410_GPE7_OUTP (0x01 << 14)
617#define S3C2410_GPE7_SDDAT0 (0x02 << 14) 413#define S3C2410_GPE7_SDDAT0 (0x02 << 14)
618#define S3C2443_GPE5_SD1_DAT0 (0x02 << 14) 414#define S3C2443_GPE5_SD1_DAT0 (0x02 << 14)
619#define S3C2443_GPE7_AC_SDI (0x03 << 14) 415#define S3C2443_GPE7_AC_SDI (0x03 << 14)
620#define S3C2400_GPE7_EINT7 (0x02 << 14) 416#define S3C2400_GPE7_EINT7 (0x02 << 14)
621 417
622#define S3C2410_GPE8 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 8)
623#define S3C2410_GPE8_INP (0x00 << 16)
624#define S3C2410_GPE8_OUTP (0x01 << 16)
625#define S3C2410_GPE8_SDDAT1 (0x02 << 16) 418#define S3C2410_GPE8_SDDAT1 (0x02 << 16)
626#define S3C2443_GPE8_SD1_DAT1 (0x02 << 16) 419#define S3C2443_GPE8_SD1_DAT1 (0x02 << 16)
627#define S3C2443_GPE8_AC_SDO (0x03 << 16) 420#define S3C2443_GPE8_AC_SDO (0x03 << 16)
628#define S3C2400_GPE8_nXDACK0 (0x02 << 16) 421#define S3C2400_GPE8_nXDACK0 (0x02 << 16)
629 422
630#define S3C2410_GPE9 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 9)
631#define S3C2410_GPE9_INP (0x00 << 18)
632#define S3C2410_GPE9_OUTP (0x01 << 18)
633#define S3C2410_GPE9_SDDAT2 (0x02 << 18) 423#define S3C2410_GPE9_SDDAT2 (0x02 << 18)
634#define S3C2443_GPE9_SD1_DAT2 (0x02 << 18) 424#define S3C2443_GPE9_SD1_DAT2 (0x02 << 18)
635#define S3C2443_GPE9_AC_SYNC (0x03 << 18) 425#define S3C2443_GPE9_AC_SYNC (0x03 << 18)
636#define S3C2400_GPE9_nXDACK1 (0x02 << 18) 426#define S3C2400_GPE9_nXDACK1 (0x02 << 18)
637#define S3C2400_GPE9_nXBACK (0x03 << 18) 427#define S3C2400_GPE9_nXBACK (0x03 << 18)
638 428
639#define S3C2410_GPE10 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 10)
640#define S3C2410_GPE10_INP (0x00 << 20)
641#define S3C2410_GPE10_OUTP (0x01 << 20)
642#define S3C2410_GPE10_SDDAT3 (0x02 << 20) 429#define S3C2410_GPE10_SDDAT3 (0x02 << 20)
643#define S3C2443_GPE10_SD1_DAT3 (0x02 << 20) 430#define S3C2443_GPE10_SD1_DAT3 (0x02 << 20)
644#define S3C2443_GPE10_AC_nRESET (0x03 << 20) 431#define S3C2443_GPE10_AC_nRESET (0x03 << 20)
645#define S3C2400_GPE10_nXDREQ0 (0x02 << 20) 432#define S3C2400_GPE10_nXDREQ0 (0x02 << 20)
646 433
647#define S3C2410_GPE11 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 11)
648#define S3C2410_GPE11_INP (0x00 << 22)
649#define S3C2410_GPE11_OUTP (0x01 << 22)
650#define S3C2410_GPE11_SPIMISO0 (0x02 << 22) 434#define S3C2410_GPE11_SPIMISO0 (0x02 << 22)
651#define S3C2400_GPE11_nXDREQ1 (0x02 << 22) 435#define S3C2400_GPE11_nXDREQ1 (0x02 << 22)
652#define S3C2400_GPE11_nXBREQ (0x03 << 22) 436#define S3C2400_GPE11_nXBREQ (0x03 << 22)
653 437
654#define S3C2410_GPE12 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 12)
655#define S3C2410_GPE12_INP (0x00 << 24)
656#define S3C2410_GPE12_OUTP (0x01 << 24)
657#define S3C2410_GPE12_SPIMOSI0 (0x02 << 24) 438#define S3C2410_GPE12_SPIMOSI0 (0x02 << 24)
658 439
659#define S3C2410_GPE13 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 13)
660#define S3C2410_GPE13_INP (0x00 << 26)
661#define S3C2410_GPE13_OUTP (0x01 << 26)
662#define S3C2410_GPE13_SPICLK0 (0x02 << 26) 440#define S3C2410_GPE13_SPICLK0 (0x02 << 26)
663 441
664#define S3C2410_GPE14 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 14)
665#define S3C2410_GPE14_INP (0x00 << 28)
666#define S3C2410_GPE14_OUTP (0x01 << 28)
667#define S3C2410_GPE14_IICSCL (0x02 << 28) 442#define S3C2410_GPE14_IICSCL (0x02 << 28)
668#define S3C2410_GPE14_MASK (0x03 << 28) 443#define S3C2410_GPE14_MASK (0x03 << 28)
669 444
670#define S3C2410_GPE15 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 15)
671#define S3C2410_GPE15_INP (0x00 << 30)
672#define S3C2410_GPE15_OUTP (0x01 << 30)
673#define S3C2410_GPE15_IICSDA (0x02 << 30) 445#define S3C2410_GPE15_IICSDA (0x02 << 30)
674#define S3C2410_GPE15_MASK (0x03 << 30) 446#define S3C2410_GPE15_MASK (0x03 << 30)
675 447
@@ -705,55 +477,31 @@
705#define S3C2400_GPFDAT S3C2410_GPIOREG(0x3C) 477#define S3C2400_GPFDAT S3C2410_GPIOREG(0x3C)
706#define S3C2400_GPFUP S3C2410_GPIOREG(0x40) 478#define S3C2400_GPFUP S3C2410_GPIOREG(0x40)
707 479
708#define S3C2410_GPF0 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 0)
709#define S3C2410_GPF0_INP (0x00 << 0)
710#define S3C2410_GPF0_OUTP (0x01 << 0)
711#define S3C2410_GPF0_EINT0 (0x02 << 0) 480#define S3C2410_GPF0_EINT0 (0x02 << 0)
712#define S3C2400_GPF0_RXD0 (0x02 << 0) 481#define S3C2400_GPF0_RXD0 (0x02 << 0)
713 482
714#define S3C2410_GPF1 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 1)
715#define S3C2410_GPF1_INP (0x00 << 2)
716#define S3C2410_GPF1_OUTP (0x01 << 2)
717#define S3C2410_GPF1_EINT1 (0x02 << 2) 483#define S3C2410_GPF1_EINT1 (0x02 << 2)
718#define S3C2400_GPF1_RXD1 (0x02 << 2) 484#define S3C2400_GPF1_RXD1 (0x02 << 2)
719#define S3C2400_GPF1_IICSDA (0x03 << 2) 485#define S3C2400_GPF1_IICSDA (0x03 << 2)
720 486
721#define S3C2410_GPF2 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 2)
722#define S3C2410_GPF2_INP (0x00 << 4)
723#define S3C2410_GPF2_OUTP (0x01 << 4)
724#define S3C2410_GPF2_EINT2 (0x02 << 4) 487#define S3C2410_GPF2_EINT2 (0x02 << 4)
725#define S3C2400_GPF2_TXD0 (0x02 << 4) 488#define S3C2400_GPF2_TXD0 (0x02 << 4)
726 489
727#define S3C2410_GPF3 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 3)
728#define S3C2410_GPF3_INP (0x00 << 6)
729#define S3C2410_GPF3_OUTP (0x01 << 6)
730#define S3C2410_GPF3_EINT3 (0x02 << 6) 490#define S3C2410_GPF3_EINT3 (0x02 << 6)
731#define S3C2400_GPF3_TXD1 (0x02 << 6) 491#define S3C2400_GPF3_TXD1 (0x02 << 6)
732#define S3C2400_GPF3_IICSCL (0x03 << 6) 492#define S3C2400_GPF3_IICSCL (0x03 << 6)
733 493
734#define S3C2410_GPF4 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 4)
735#define S3C2410_GPF4_INP (0x00 << 8)
736#define S3C2410_GPF4_OUTP (0x01 << 8)
737#define S3C2410_GPF4_EINT4 (0x02 << 8) 494#define S3C2410_GPF4_EINT4 (0x02 << 8)
738#define S3C2400_GPF4_nRTS0 (0x02 << 8) 495#define S3C2400_GPF4_nRTS0 (0x02 << 8)
739#define S3C2400_GPF4_nXBACK (0x03 << 8) 496#define S3C2400_GPF4_nXBACK (0x03 << 8)
740 497
741#define S3C2410_GPF5 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 5)
742#define S3C2410_GPF5_INP (0x00 << 10)
743#define S3C2410_GPF5_OUTP (0x01 << 10)
744#define S3C2410_GPF5_EINT5 (0x02 << 10) 498#define S3C2410_GPF5_EINT5 (0x02 << 10)
745#define S3C2400_GPF5_nCTS0 (0x02 << 10) 499#define S3C2400_GPF5_nCTS0 (0x02 << 10)
746#define S3C2400_GPF5_nXBREQ (0x03 << 10) 500#define S3C2400_GPF5_nXBREQ (0x03 << 10)
747 501
748#define S3C2410_GPF6 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 6)
749#define S3C2410_GPF6_INP (0x00 << 12)
750#define S3C2410_GPF6_OUTP (0x01 << 12)
751#define S3C2410_GPF6_EINT6 (0x02 << 12) 502#define S3C2410_GPF6_EINT6 (0x02 << 12)
752#define S3C2400_GPF6_CLKOUT (0x02 << 12) 503#define S3C2400_GPF6_CLKOUT (0x02 << 12)
753 504
754#define S3C2410_GPF7 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 7)
755#define S3C2410_GPF7_INP (0x00 << 14)
756#define S3C2410_GPF7_OUTP (0x01 << 14)
757#define S3C2410_GPF7_EINT7 (0x02 << 14) 505#define S3C2410_GPF7_EINT7 (0x02 << 14)
758 506
759#define S3C2410_GPF_PUPDIS(x) (1<<(x)) 507#define S3C2410_GPF_PUPDIS(x) (1<<(x))
@@ -778,117 +526,69 @@
778#define S3C2400_GPGDAT S3C2410_GPIOREG(0x48) 526#define S3C2400_GPGDAT S3C2410_GPIOREG(0x48)
779#define S3C2400_GPGUP S3C2410_GPIOREG(0x4C) 527#define S3C2400_GPGUP S3C2410_GPIOREG(0x4C)
780 528
781#define S3C2410_GPG0 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 0)
782#define S3C2410_GPG0_INP (0x00 << 0)
783#define S3C2410_GPG0_OUTP (0x01 << 0)
784#define S3C2410_GPG0_EINT8 (0x02 << 0) 529#define S3C2410_GPG0_EINT8 (0x02 << 0)
785#define S3C2400_GPG0_I2SLRCK (0x02 << 0) 530#define S3C2400_GPG0_I2SLRCK (0x02 << 0)
786 531
787#define S3C2410_GPG1 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 1)
788#define S3C2410_GPG1_INP (0x00 << 2)
789#define S3C2410_GPG1_OUTP (0x01 << 2)
790#define S3C2410_GPG1_EINT9 (0x02 << 2) 532#define S3C2410_GPG1_EINT9 (0x02 << 2)
791#define S3C2400_GPG1_I2SSCLK (0x02 << 2) 533#define S3C2400_GPG1_I2SSCLK (0x02 << 2)
792 534
793#define S3C2410_GPG2 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 2)
794#define S3C2410_GPG2_INP (0x00 << 4)
795#define S3C2410_GPG2_OUTP (0x01 << 4)
796#define S3C2410_GPG2_EINT10 (0x02 << 4) 535#define S3C2410_GPG2_EINT10 (0x02 << 4)
797#define S3C2410_GPG2_nSS0 (0x03 << 4) 536#define S3C2410_GPG2_nSS0 (0x03 << 4)
798#define S3C2400_GPG2_CDCLK (0x02 << 4) 537#define S3C2400_GPG2_CDCLK (0x02 << 4)
799 538
800#define S3C2410_GPG3 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 3)
801#define S3C2410_GPG3_INP (0x00 << 6)
802#define S3C2410_GPG3_OUTP (0x01 << 6)
803#define S3C2410_GPG3_EINT11 (0x02 << 6) 539#define S3C2410_GPG3_EINT11 (0x02 << 6)
804#define S3C2410_GPG3_nSS1 (0x03 << 6) 540#define S3C2410_GPG3_nSS1 (0x03 << 6)
805#define S3C2400_GPG3_I2SSDO (0x02 << 6) 541#define S3C2400_GPG3_I2SSDO (0x02 << 6)
806#define S3C2400_GPG3_I2SSDI (0x03 << 6) 542#define S3C2400_GPG3_I2SSDI (0x03 << 6)
807 543
808#define S3C2410_GPG4 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 4)
809#define S3C2410_GPG4_INP (0x00 << 8)
810#define S3C2410_GPG4_OUTP (0x01 << 8)
811#define S3C2410_GPG4_EINT12 (0x02 << 8) 544#define S3C2410_GPG4_EINT12 (0x02 << 8)
812#define S3C2400_GPG4_MMCCLK (0x02 << 8) 545#define S3C2400_GPG4_MMCCLK (0x02 << 8)
813#define S3C2400_GPG4_I2SSDI (0x03 << 8) 546#define S3C2400_GPG4_I2SSDI (0x03 << 8)
814#define S3C2410_GPG4_LCDPWREN (0x03 << 8) 547#define S3C2410_GPG4_LCDPWREN (0x03 << 8)
815#define S3C2443_GPG4_LCDPWRDN (0x03 << 8) 548#define S3C2443_GPG4_LCDPWRDN (0x03 << 8)
816 549
817#define S3C2410_GPG5 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 5)
818#define S3C2410_GPG5_INP (0x00 << 10)
819#define S3C2410_GPG5_OUTP (0x01 << 10)
820#define S3C2410_GPG5_EINT13 (0x02 << 10) 550#define S3C2410_GPG5_EINT13 (0x02 << 10)
821#define S3C2400_GPG5_MMCCMD (0x02 << 10) 551#define S3C2400_GPG5_MMCCMD (0x02 << 10)
822#define S3C2400_GPG5_IICSDA (0x03 << 10) 552#define S3C2400_GPG5_IICSDA (0x03 << 10)
823#define S3C2410_GPG5_SPIMISO1 (0x03 << 10) /* not s3c2443 */ 553#define S3C2410_GPG5_SPIMISO1 (0x03 << 10) /* not s3c2443 */
824 554
825#define S3C2410_GPG6 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 6)
826#define S3C2410_GPG6_INP (0x00 << 12)
827#define S3C2410_GPG6_OUTP (0x01 << 12)
828#define S3C2410_GPG6_EINT14 (0x02 << 12) 555#define S3C2410_GPG6_EINT14 (0x02 << 12)
829#define S3C2400_GPG6_MMCDAT (0x02 << 12) 556#define S3C2400_GPG6_MMCDAT (0x02 << 12)
830#define S3C2400_GPG6_IICSCL (0x03 << 12) 557#define S3C2400_GPG6_IICSCL (0x03 << 12)
831#define S3C2410_GPG6_SPIMOSI1 (0x03 << 12) 558#define S3C2410_GPG6_SPIMOSI1 (0x03 << 12)
832 559
833#define S3C2410_GPG7 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 7)
834#define S3C2410_GPG7_INP (0x00 << 14)
835#define S3C2410_GPG7_OUTP (0x01 << 14)
836#define S3C2410_GPG7_EINT15 (0x02 << 14) 560#define S3C2410_GPG7_EINT15 (0x02 << 14)
837#define S3C2410_GPG7_SPICLK1 (0x03 << 14) 561#define S3C2410_GPG7_SPICLK1 (0x03 << 14)
838#define S3C2400_GPG7_SPIMISO (0x02 << 14) 562#define S3C2400_GPG7_SPIMISO (0x02 << 14)
839#define S3C2400_GPG7_IICSDA (0x03 << 14) 563#define S3C2400_GPG7_IICSDA (0x03 << 14)
840 564
841#define S3C2410_GPG8 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 8)
842#define S3C2410_GPG8_INP (0x00 << 16)
843#define S3C2410_GPG8_OUTP (0x01 << 16)
844#define S3C2410_GPG8_EINT16 (0x02 << 16) 565#define S3C2410_GPG8_EINT16 (0x02 << 16)
845#define S3C2400_GPG8_SPIMOSI (0x02 << 16) 566#define S3C2400_GPG8_SPIMOSI (0x02 << 16)
846#define S3C2400_GPG8_IICSCL (0x03 << 16) 567#define S3C2400_GPG8_IICSCL (0x03 << 16)
847 568
848#define S3C2410_GPG9 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 9)
849#define S3C2410_GPG9_INP (0x00 << 18)
850#define S3C2410_GPG9_OUTP (0x01 << 18)
851#define S3C2410_GPG9_EINT17 (0x02 << 18) 569#define S3C2410_GPG9_EINT17 (0x02 << 18)
852#define S3C2400_GPG9_SPICLK (0x02 << 18) 570#define S3C2400_GPG9_SPICLK (0x02 << 18)
853#define S3C2400_GPG9_MMCCLK (0x03 << 18) 571#define S3C2400_GPG9_MMCCLK (0x03 << 18)
854 572
855#define S3C2410_GPG10 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10)
856#define S3C2410_GPG10_INP (0x00 << 20)
857#define S3C2410_GPG10_OUTP (0x01 << 20)
858#define S3C2410_GPG10_EINT18 (0x02 << 20) 573#define S3C2410_GPG10_EINT18 (0x02 << 20)
859 574
860#define S3C2410_GPG11 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 11)
861#define S3C2410_GPG11_INP (0x00 << 22)
862#define S3C2410_GPG11_OUTP (0x01 << 22)
863#define S3C2410_GPG11_EINT19 (0x02 << 22) 575#define S3C2410_GPG11_EINT19 (0x02 << 22)
864#define S3C2410_GPG11_TCLK1 (0x03 << 22) 576#define S3C2410_GPG11_TCLK1 (0x03 << 22)
865#define S3C2443_GPG11_CF_nIREQ (0x03 << 22) 577#define S3C2443_GPG11_CF_nIREQ (0x03 << 22)
866 578
867#define S3C2410_GPG12 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 12)
868#define S3C2410_GPG12_INP (0x00 << 24)
869#define S3C2410_GPG12_OUTP (0x01 << 24)
870#define S3C2410_GPG12_EINT20 (0x02 << 24) 579#define S3C2410_GPG12_EINT20 (0x02 << 24)
871#define S3C2410_GPG12_XMON (0x03 << 24) 580#define S3C2410_GPG12_XMON (0x03 << 24)
872#define S3C2442_GPG12_nSPICS0 (0x03 << 24) 581#define S3C2442_GPG12_nSPICS0 (0x03 << 24)
873#define S3C2443_GPG12_nINPACK (0x03 << 24) 582#define S3C2443_GPG12_nINPACK (0x03 << 24)
874 583
875#define S3C2410_GPG13 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 13)
876#define S3C2410_GPG13_INP (0x00 << 26)
877#define S3C2410_GPG13_OUTP (0x01 << 26)
878#define S3C2410_GPG13_EINT21 (0x02 << 26) 584#define S3C2410_GPG13_EINT21 (0x02 << 26)
879#define S3C2410_GPG13_nXPON (0x03 << 26) 585#define S3C2410_GPG13_nXPON (0x03 << 26)
880#define S3C2443_GPG13_CF_nREG (0x03 << 26) 586#define S3C2443_GPG13_CF_nREG (0x03 << 26)
881 587
882#define S3C2410_GPG14 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 14)
883#define S3C2410_GPG14_INP (0x00 << 28)
884#define S3C2410_GPG14_OUTP (0x01 << 28)
885#define S3C2410_GPG14_EINT22 (0x02 << 28) 588#define S3C2410_GPG14_EINT22 (0x02 << 28)
886#define S3C2410_GPG14_YMON (0x03 << 28) 589#define S3C2410_GPG14_YMON (0x03 << 28)
887#define S3C2443_GPG14_CF_RESET (0x03 << 28) 590#define S3C2443_GPG14_CF_RESET (0x03 << 28)
888 591
889#define S3C2410_GPG15 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 15)
890#define S3C2410_GPG15_INP (0x00 << 30)
891#define S3C2410_GPG15_OUTP (0x01 << 30)
892#define S3C2410_GPG15_EINT23 (0x02 << 30) 592#define S3C2410_GPG15_EINT23 (0x02 << 30)
893#define S3C2410_GPG15_nYPON (0x03 << 30) 593#define S3C2410_GPG15_nYPON (0x03 << 30)
894#define S3C2443_GPG15_CF_PWR (0x03 << 30) 594#define S3C2443_GPG15_CF_PWR (0x03 << 30)
@@ -907,62 +607,29 @@
907#define S3C2410_GPHDAT S3C2410_GPIOREG(0x74) 607#define S3C2410_GPHDAT S3C2410_GPIOREG(0x74)
908#define S3C2410_GPHUP S3C2410_GPIOREG(0x78) 608#define S3C2410_GPHUP S3C2410_GPIOREG(0x78)
909 609
910#define S3C2410_GPH0 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 0)
911#define S3C2410_GPH0_INP (0x00 << 0)
912#define S3C2410_GPH0_OUTP (0x01 << 0)
913#define S3C2410_GPH0_nCTS0 (0x02 << 0) 610#define S3C2410_GPH0_nCTS0 (0x02 << 0)
914 611
915#define S3C2410_GPH1 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 1)
916#define S3C2410_GPH1_INP (0x00 << 2)
917#define S3C2410_GPH1_OUTP (0x01 << 2)
918#define S3C2410_GPH1_nRTS0 (0x02 << 2) 612#define S3C2410_GPH1_nRTS0 (0x02 << 2)
919 613
920#define S3C2410_GPH2 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 2)
921#define S3C2410_GPH2_INP (0x00 << 4)
922#define S3C2410_GPH2_OUTP (0x01 << 4)
923#define S3C2410_GPH2_TXD0 (0x02 << 4) 614#define S3C2410_GPH2_TXD0 (0x02 << 4)
924 615
925#define S3C2410_GPH3 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 3)
926#define S3C2410_GPH3_INP (0x00 << 6)
927#define S3C2410_GPH3_OUTP (0x01 << 6)
928#define S3C2410_GPH3_RXD0 (0x02 << 6) 616#define S3C2410_GPH3_RXD0 (0x02 << 6)
929 617
930#define S3C2410_GPH4 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 4)
931#define S3C2410_GPH4_INP (0x00 << 8)
932#define S3C2410_GPH4_OUTP (0x01 << 8)
933#define S3C2410_GPH4_TXD1 (0x02 << 8) 618#define S3C2410_GPH4_TXD1 (0x02 << 8)
934 619
935#define S3C2410_GPH5 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 5)
936#define S3C2410_GPH5_INP (0x00 << 10)
937#define S3C2410_GPH5_OUTP (0x01 << 10)
938#define S3C2410_GPH5_RXD1 (0x02 << 10) 620#define S3C2410_GPH5_RXD1 (0x02 << 10)
939 621
940#define S3C2410_GPH6 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 6)
941#define S3C2410_GPH6_INP (0x00 << 12)
942#define S3C2410_GPH6_OUTP (0x01 << 12)
943#define S3C2410_GPH6_TXD2 (0x02 << 12) 622#define S3C2410_GPH6_TXD2 (0x02 << 12)
944#define S3C2410_GPH6_nRTS1 (0x03 << 12) 623#define S3C2410_GPH6_nRTS1 (0x03 << 12)
945 624
946#define S3C2410_GPH7 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 7)
947#define S3C2410_GPH7_INP (0x00 << 14)
948#define S3C2410_GPH7_OUTP (0x01 << 14)
949#define S3C2410_GPH7_RXD2 (0x02 << 14) 625#define S3C2410_GPH7_RXD2 (0x02 << 14)
950#define S3C2410_GPH7_nCTS1 (0x03 << 14) 626#define S3C2410_GPH7_nCTS1 (0x03 << 14)
951 627
952#define S3C2410_GPH8 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 8)
953#define S3C2410_GPH8_INP (0x00 << 16)
954#define S3C2410_GPH8_OUTP (0x01 << 16)
955#define S3C2410_GPH8_UCLK (0x02 << 16) 628#define S3C2410_GPH8_UCLK (0x02 << 16)
956 629
957#define S3C2410_GPH9 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 9)
958#define S3C2410_GPH9_INP (0x00 << 18)
959#define S3C2410_GPH9_OUTP (0x01 << 18)
960#define S3C2410_GPH9_CLKOUT0 (0x02 << 18) 630#define S3C2410_GPH9_CLKOUT0 (0x02 << 18)
961#define S3C2442_GPH9_nSPICS0 (0x03 << 18) 631#define S3C2442_GPH9_nSPICS0 (0x03 << 18)
962 632
963#define S3C2410_GPH10 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 10)
964#define S3C2410_GPH10_INP (0x00 << 20)
965#define S3C2410_GPH10_OUTP (0x01 << 20)
966#define S3C2410_GPH10_CLKOUT1 (0x02 << 20) 633#define S3C2410_GPH10_CLKOUT1 (0x02 << 20)
967 634
968/* The S3C2412 and S3C2413 move the GPJ register set to after 635/* The S3C2412 and S3C2413 move the GPJ register set to after
diff --git a/arch/arm/mach-s3c2410/include/mach/system-reset.h b/arch/arm/mach-s3c2410/include/mach/system-reset.h
index b8687f71c304..6faadcee7729 100644
--- a/arch/arm/mach-s3c2410/include/mach/system-reset.h
+++ b/arch/arm/mach-s3c2410/include/mach/system-reset.h
@@ -11,21 +11,13 @@
11*/ 11*/
12 12
13#include <mach/hardware.h> 13#include <mach/hardware.h>
14#include <linux/io.h> 14#include <plat/watchdog-reset.h>
15
16#include <plat/regs-watchdog.h>
17#include <mach/regs-clock.h>
18
19#include <linux/clk.h>
20#include <linux/err.h>
21 15
22extern void (*s3c24xx_reset_hook)(void); 16extern void (*s3c24xx_reset_hook)(void);
23 17
24static void 18static void
25arch_reset(char mode, const char *cmd) 19arch_reset(char mode, const char *cmd)
26{ 20{
27 struct clk *wdtclk;
28
29 if (mode == 's') { 21 if (mode == 's') {
30 cpu_reset(0); 22 cpu_reset(0);
31 } 23 }
@@ -33,31 +25,7 @@ arch_reset(char mode, const char *cmd)
33 if (s3c24xx_reset_hook) 25 if (s3c24xx_reset_hook)
34 s3c24xx_reset_hook(); 26 s3c24xx_reset_hook();
35 27
36 printk("arch_reset: attempting watchdog reset\n"); 28 arch_wdt_reset();
37
38 __raw_writel(0, S3C2410_WTCON); /* disable watchdog, to be safe */
39
40 wdtclk = clk_get(NULL, "watchdog");
41 if (!IS_ERR(wdtclk)) {
42 clk_enable(wdtclk);
43 } else
44 printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__);
45
46 /* put initial values into count and data */
47 __raw_writel(0x80, S3C2410_WTCNT);
48 __raw_writel(0x80, S3C2410_WTDAT);
49
50 /* set the watchdog to go and reset... */
51 __raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN |
52 S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON);
53
54 /* wait for reset to assert... */
55 mdelay(500);
56
57 printk(KERN_ERR "Watchdog reset failed to assert reset\n");
58
59 /* delay to allow the serial port to show the message */
60 mdelay(50);
61 29
62 /* we'll take a jump through zero as a poor second */ 30 /* we'll take a jump through zero as a poor second */
63 cpu_reset(0); 31 cpu_reset(0);
diff --git a/arch/arm/mach-s3c2410/mach-amlm5900.c b/arch/arm/mach-s3c2410/mach-amlm5900.c
index 6d6995afeb43..06a84adfb13f 100644
--- a/arch/arm/mach-s3c2410/mach-amlm5900.c
+++ b/arch/arm/mach-s3c2410/mach-amlm5900.c
@@ -32,6 +32,7 @@
32#include <linux/list.h> 32#include <linux/list.h>
33#include <linux/timer.h> 33#include <linux/timer.h>
34#include <linux/init.h> 34#include <linux/init.h>
35#include <linux/gpio.h>
35#include <linux/device.h> 36#include <linux/device.h>
36#include <linux/platform_device.h> 37#include <linux/platform_device.h>
37#include <linux/proc_fs.h> 38#include <linux/proc_fs.h>
@@ -224,8 +225,8 @@ static void amlm5900_init_pm(void)
224 } else { 225 } else {
225 enable_irq_wake(IRQ_EINT9); 226 enable_irq_wake(IRQ_EINT9);
226 /* configure the suspend/resume status pin */ 227 /* configure the suspend/resume status pin */
227 s3c2410_gpio_cfgpin(S3C2410_GPF2, S3C2410_GPF2_OUTP); 228 s3c2410_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT);
228 s3c2410_gpio_pullup(S3C2410_GPF2, 0); 229 s3c2410_gpio_pullup(S3C2410_GPF(2), 0);
229 } 230 }
230} 231}
231static void __init amlm5900_init(void) 232static void __init amlm5900_init(void)
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index 8637dea5e150..ce3baba2cd7f 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -16,6 +16,7 @@
16#include <linux/list.h> 16#include <linux/list.h>
17#include <linux/timer.h> 17#include <linux/timer.h>
18#include <linux/init.h> 18#include <linux/init.h>
19#include <linux/gpio.h>
19#include <linux/sysdev.h> 20#include <linux/sysdev.h>
20#include <linux/serial_core.h> 21#include <linux/serial_core.h>
21#include <linux/platform_device.h> 22#include <linux/platform_device.h>
@@ -212,15 +213,15 @@ static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
212static int bast_pm_suspend(struct sys_device *sd, pm_message_t state) 213static int bast_pm_suspend(struct sys_device *sd, pm_message_t state)
213{ 214{
214 /* ensure that an nRESET is not generated on resume. */ 215 /* ensure that an nRESET is not generated on resume. */
215 s3c2410_gpio_setpin(S3C2410_GPA21, 1); 216 s3c2410_gpio_setpin(S3C2410_GPA(21), 1);
216 s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_OUT); 217 s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);
217 218
218 return 0; 219 return 0;
219} 220}
220 221
221static int bast_pm_resume(struct sys_device *sd) 222static int bast_pm_resume(struct sys_device *sd)
222{ 223{
223 s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_nRSTOUT); 224 s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
224 return 0; 225 return 0;
225} 226}
226 227
@@ -591,8 +592,6 @@ static void __init bast_map_io(void)
591 s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc)); 592 s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
592 s3c24xx_init_clocks(0); 593 s3c24xx_init_clocks(0);
593 s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs)); 594 s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
594
595 usb_simtec_init();
596} 595}
597 596
598static void __init bast_init(void) 597static void __init bast_init(void)
@@ -607,6 +606,7 @@ static void __init bast_init(void)
607 i2c_register_board_info(0, bast_i2c_devs, 606 i2c_register_board_info(0, bast_i2c_devs,
608 ARRAY_SIZE(bast_i2c_devs)); 607 ARRAY_SIZE(bast_i2c_devs));
609 608
609 usb_simtec_init();
610 nor_simtec_init(); 610 nor_simtec_init();
611} 611}
612 612
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
index 7a7c4da4c256..d9cd5ddecf4a 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -127,7 +127,7 @@ static void h1940_udc_pullup(enum s3c2410_udc_cmd_e cmd)
127 127
128static struct s3c2410_udc_mach_info h1940_udc_cfg __initdata = { 128static struct s3c2410_udc_mach_info h1940_udc_cfg __initdata = {
129 .udc_command = h1940_udc_pullup, 129 .udc_command = h1940_udc_pullup,
130 .vbus_pin = S3C2410_GPG5, 130 .vbus_pin = S3C2410_GPG(5),
131 .vbus_pin_inverted = 1, 131 .vbus_pin_inverted = 1,
132}; 132};
133 133
diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c
index 2b83f8707710..0f6ed61af415 100644
--- a/arch/arm/mach-s3c2410/mach-n30.c
+++ b/arch/arm/mach-s3c2410/mach-n30.c
@@ -19,6 +19,7 @@
19 19
20#include <linux/gpio_keys.h> 20#include <linux/gpio_keys.h>
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/gpio.h>
22#include <linux/input.h> 23#include <linux/input.h>
23#include <linux/interrupt.h> 24#include <linux/interrupt.h>
24#include <linux/platform_device.h> 25#include <linux/platform_device.h>
@@ -85,10 +86,10 @@ static void n30_udc_pullup(enum s3c2410_udc_cmd_e cmd)
85{ 86{
86 switch (cmd) { 87 switch (cmd) {
87 case S3C2410_UDC_P_ENABLE : 88 case S3C2410_UDC_P_ENABLE :
88 s3c2410_gpio_setpin(S3C2410_GPB3, 1); 89 s3c2410_gpio_setpin(S3C2410_GPB(3), 1);
89 break; 90 break;
90 case S3C2410_UDC_P_DISABLE : 91 case S3C2410_UDC_P_DISABLE :
91 s3c2410_gpio_setpin(S3C2410_GPB3, 0); 92 s3c2410_gpio_setpin(S3C2410_GPB(3), 0);
92 break; 93 break;
93 case S3C2410_UDC_P_RESET : 94 case S3C2410_UDC_P_RESET :
94 break; 95 break;
@@ -99,55 +100,55 @@ static void n30_udc_pullup(enum s3c2410_udc_cmd_e cmd)
99 100
100static struct s3c2410_udc_mach_info n30_udc_cfg __initdata = { 101static struct s3c2410_udc_mach_info n30_udc_cfg __initdata = {
101 .udc_command = n30_udc_pullup, 102 .udc_command = n30_udc_pullup,
102 .vbus_pin = S3C2410_GPG1, 103 .vbus_pin = S3C2410_GPG(1),
103 .vbus_pin_inverted = 0, 104 .vbus_pin_inverted = 0,
104}; 105};
105 106
106static struct gpio_keys_button n30_buttons[] = { 107static struct gpio_keys_button n30_buttons[] = {
107 { 108 {
108 .gpio = S3C2410_GPF0, 109 .gpio = S3C2410_GPF(0),
109 .code = KEY_POWER, 110 .code = KEY_POWER,
110 .desc = "Power", 111 .desc = "Power",
111 .active_low = 0, 112 .active_low = 0,
112 }, 113 },
113 { 114 {
114 .gpio = S3C2410_GPG9, 115 .gpio = S3C2410_GPG(9),
115 .code = KEY_UP, 116 .code = KEY_UP,
116 .desc = "Thumbwheel Up", 117 .desc = "Thumbwheel Up",
117 .active_low = 0, 118 .active_low = 0,
118 }, 119 },
119 { 120 {
120 .gpio = S3C2410_GPG8, 121 .gpio = S3C2410_GPG(8),
121 .code = KEY_DOWN, 122 .code = KEY_DOWN,
122 .desc = "Thumbwheel Down", 123 .desc = "Thumbwheel Down",
123 .active_low = 0, 124 .active_low = 0,
124 }, 125 },
125 { 126 {
126 .gpio = S3C2410_GPG7, 127 .gpio = S3C2410_GPG(7),
127 .code = KEY_ENTER, 128 .code = KEY_ENTER,
128 .desc = "Thumbwheel Press", 129 .desc = "Thumbwheel Press",
129 .active_low = 0, 130 .active_low = 0,
130 }, 131 },
131 { 132 {
132 .gpio = S3C2410_GPF7, 133 .gpio = S3C2410_GPF(7),
133 .code = KEY_HOMEPAGE, 134 .code = KEY_HOMEPAGE,
134 .desc = "Home", 135 .desc = "Home",
135 .active_low = 0, 136 .active_low = 0,
136 }, 137 },
137 { 138 {
138 .gpio = S3C2410_GPF6, 139 .gpio = S3C2410_GPF(6),
139 .code = KEY_CALENDAR, 140 .code = KEY_CALENDAR,
140 .desc = "Calendar", 141 .desc = "Calendar",
141 .active_low = 0, 142 .active_low = 0,
142 }, 143 },
143 { 144 {
144 .gpio = S3C2410_GPF5, 145 .gpio = S3C2410_GPF(5),
145 .code = KEY_ADDRESSBOOK, 146 .code = KEY_ADDRESSBOOK,
146 .desc = "Contacts", 147 .desc = "Contacts",
147 .active_low = 0, 148 .active_low = 0,
148 }, 149 },
149 { 150 {
150 .gpio = S3C2410_GPF4, 151 .gpio = S3C2410_GPF(4),
151 .code = KEY_MAIL, 152 .code = KEY_MAIL,
152 .desc = "Mail", 153 .desc = "Mail",
153 .active_low = 0, 154 .active_low = 0,
@@ -169,73 +170,73 @@ static struct platform_device n30_button_device = {
169 170
170static struct gpio_keys_button n35_buttons[] = { 171static struct gpio_keys_button n35_buttons[] = {
171 { 172 {
172 .gpio = S3C2410_GPF0, 173 .gpio = S3C2410_GPF(0),
173 .code = KEY_POWER, 174 .code = KEY_POWER,
174 .desc = "Power", 175 .desc = "Power",
175 .active_low = 0, 176 .active_low = 0,
176 }, 177 },
177 { 178 {
178 .gpio = S3C2410_GPG9, 179 .gpio = S3C2410_GPG(9),
179 .code = KEY_UP, 180 .code = KEY_UP,
180 .desc = "Joystick Up", 181 .desc = "Joystick Up",
181 .active_low = 0, 182 .active_low = 0,
182 }, 183 },
183 { 184 {
184 .gpio = S3C2410_GPG8, 185 .gpio = S3C2410_GPG(8),
185 .code = KEY_DOWN, 186 .code = KEY_DOWN,
186 .desc = "Joystick Down", 187 .desc = "Joystick Down",
187 .active_low = 0, 188 .active_low = 0,
188 }, 189 },
189 { 190 {
190 .gpio = S3C2410_GPG6, 191 .gpio = S3C2410_GPG(6),
191 .code = KEY_DOWN, 192 .code = KEY_DOWN,
192 .desc = "Joystick Left", 193 .desc = "Joystick Left",
193 .active_low = 0, 194 .active_low = 0,
194 }, 195 },
195 { 196 {
196 .gpio = S3C2410_GPG5, 197 .gpio = S3C2410_GPG(5),
197 .code = KEY_DOWN, 198 .code = KEY_DOWN,
198 .desc = "Joystick Right", 199 .desc = "Joystick Right",
199 .active_low = 0, 200 .active_low = 0,
200 }, 201 },
201 { 202 {
202 .gpio = S3C2410_GPG7, 203 .gpio = S3C2410_GPG(7),
203 .code = KEY_ENTER, 204 .code = KEY_ENTER,
204 .desc = "Joystick Press", 205 .desc = "Joystick Press",
205 .active_low = 0, 206 .active_low = 0,
206 }, 207 },
207 { 208 {
208 .gpio = S3C2410_GPF7, 209 .gpio = S3C2410_GPF(7),
209 .code = KEY_HOMEPAGE, 210 .code = KEY_HOMEPAGE,
210 .desc = "Home", 211 .desc = "Home",
211 .active_low = 0, 212 .active_low = 0,
212 }, 213 },
213 { 214 {
214 .gpio = S3C2410_GPF6, 215 .gpio = S3C2410_GPF(6),
215 .code = KEY_CALENDAR, 216 .code = KEY_CALENDAR,
216 .desc = "Calendar", 217 .desc = "Calendar",
217 .active_low = 0, 218 .active_low = 0,
218 }, 219 },
219 { 220 {
220 .gpio = S3C2410_GPF5, 221 .gpio = S3C2410_GPF(5),
221 .code = KEY_ADDRESSBOOK, 222 .code = KEY_ADDRESSBOOK,
222 .desc = "Contacts", 223 .desc = "Contacts",
223 .active_low = 0, 224 .active_low = 0,
224 }, 225 },
225 { 226 {
226 .gpio = S3C2410_GPF4, 227 .gpio = S3C2410_GPF(4),
227 .code = KEY_MAIL, 228 .code = KEY_MAIL,
228 .desc = "Mail", 229 .desc = "Mail",
229 .active_low = 0, 230 .active_low = 0,
230 }, 231 },
231 { 232 {
232 .gpio = S3C2410_GPF3, 233 .gpio = S3C2410_GPF(3),
233 .code = SW_RADIO, 234 .code = SW_RADIO,
234 .desc = "GPS Antenna", 235 .desc = "GPS Antenna",
235 .active_low = 0, 236 .active_low = 0,
236 }, 237 },
237 { 238 {
238 .gpio = S3C2410_GPG2, 239 .gpio = S3C2410_GPG(2),
239 .code = SW_HEADPHONE_INSERT, 240 .code = SW_HEADPHONE_INSERT,
240 .desc = "Headphone", 241 .desc = "Headphone",
241 .active_low = 0, 242 .active_low = 0,
@@ -259,7 +260,7 @@ static struct platform_device n35_button_device = {
259/* This is the bluetooth LED on the device. */ 260/* This is the bluetooth LED on the device. */
260static struct s3c24xx_led_platdata n30_blue_led_pdata = { 261static struct s3c24xx_led_platdata n30_blue_led_pdata = {
261 .name = "blue_led", 262 .name = "blue_led",
262 .gpio = S3C2410_GPG6, 263 .gpio = S3C2410_GPG(6),
263 .def_trigger = "", 264 .def_trigger = "",
264}; 265};
265 266
@@ -270,7 +271,7 @@ static struct s3c24xx_led_platdata n30_blue_led_pdata = {
270static struct s3c24xx_led_platdata n30_warning_led_pdata = { 271static struct s3c24xx_led_platdata n30_warning_led_pdata = {
271 .name = "warning_led", 272 .name = "warning_led",
272 .flags = S3C24XX_LEDF_ACTLOW, 273 .flags = S3C24XX_LEDF_ACTLOW,
273 .gpio = S3C2410_GPD9, 274 .gpio = S3C2410_GPD(9),
274 .def_trigger = "", 275 .def_trigger = "",
275}; 276};
276 277
diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c
index 9f1ba9b63f70..2cc9849eb448 100644
--- a/arch/arm/mach-s3c2410/mach-qt2410.c
+++ b/arch/arm/mach-s3c2410/mach-qt2410.c
@@ -27,6 +27,7 @@
27#include <linux/list.h> 27#include <linux/list.h>
28#include <linux/timer.h> 28#include <linux/timer.h>
29#include <linux/init.h> 29#include <linux/init.h>
30#include <linux/gpio.h>
30#include <linux/sysdev.h> 31#include <linux/sysdev.h>
31#include <linux/platform_device.h> 32#include <linux/platform_device.h>
32#include <linux/serial_core.h> 33#include <linux/serial_core.h>
@@ -198,7 +199,7 @@ static struct platform_device qt2410_cs89x0 = {
198/* LED */ 199/* LED */
199 200
200static struct s3c24xx_led_platdata qt2410_pdata_led = { 201static struct s3c24xx_led_platdata qt2410_pdata_led = {
201 .gpio = S3C2410_GPB0, 202 .gpio = S3C2410_GPB(0),
202 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, 203 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
203 .name = "led", 204 .name = "led",
204 .def_trigger = "timer", 205 .def_trigger = "timer",
@@ -218,18 +219,18 @@ static void spi_gpio_cs(struct s3c2410_spigpio_info *spi, int cs)
218{ 219{
219 switch (cs) { 220 switch (cs) {
220 case BITBANG_CS_ACTIVE: 221 case BITBANG_CS_ACTIVE:
221 s3c2410_gpio_setpin(S3C2410_GPB5, 0); 222 s3c2410_gpio_setpin(S3C2410_GPB(5), 0);
222 break; 223 break;
223 case BITBANG_CS_INACTIVE: 224 case BITBANG_CS_INACTIVE:
224 s3c2410_gpio_setpin(S3C2410_GPB5, 1); 225 s3c2410_gpio_setpin(S3C2410_GPB(5), 1);
225 break; 226 break;
226 } 227 }
227} 228}
228 229
229static struct s3c2410_spigpio_info spi_gpio_cfg = { 230static struct s3c2410_spigpio_info spi_gpio_cfg = {
230 .pin_clk = S3C2410_GPG7, 231 .pin_clk = S3C2410_GPG(7),
231 .pin_mosi = S3C2410_GPG6, 232 .pin_mosi = S3C2410_GPG(6),
232 .pin_miso = S3C2410_GPG5, 233 .pin_miso = S3C2410_GPG(5),
233 .chip_select = &spi_gpio_cs, 234 .chip_select = &spi_gpio_cs,
234}; 235};
235 236
@@ -346,13 +347,13 @@ static void __init qt2410_machine_init(void)
346 } 347 }
347 s3c24xx_fb_set_platdata(&qt2410_fb_info); 348 s3c24xx_fb_set_platdata(&qt2410_fb_info);
348 349
349 s3c2410_gpio_cfgpin(S3C2410_GPB0, S3C2410_GPIO_OUTPUT); 350 s3c2410_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPIO_OUTPUT);
350 s3c2410_gpio_setpin(S3C2410_GPB0, 1); 351 s3c2410_gpio_setpin(S3C2410_GPB(0), 1);
351 352
352 s3c24xx_udc_set_platdata(&qt2410_udc_cfg); 353 s3c24xx_udc_set_platdata(&qt2410_udc_cfg);
353 s3c_i2c0_set_platdata(NULL); 354 s3c_i2c0_set_platdata(NULL);
354 355
355 s3c2410_gpio_cfgpin(S3C2410_GPB5, S3C2410_GPIO_OUTPUT); 356 s3c2410_gpio_cfgpin(S3C2410_GPB(5), S3C2410_GPIO_OUTPUT);
356 357
357 platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices)); 358 platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices));
358 s3c_pm_init(); 359 s3c_pm_init();
diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c
index 61a1ea9c5c5c..1628cc773a2c 100644
--- a/arch/arm/mach-s3c2410/mach-vr1000.c
+++ b/arch/arm/mach-s3c2410/mach-vr1000.c
@@ -18,6 +18,7 @@
18#include <linux/list.h> 18#include <linux/list.h>
19#include <linux/timer.h> 19#include <linux/timer.h>
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/gpio.h>
21#include <linux/dm9000.h> 22#include <linux/dm9000.h>
22#include <linux/i2c.h> 23#include <linux/i2c.h>
23 24
@@ -277,19 +278,19 @@ static struct platform_device vr1000_dm9k1 = {
277 278
278static struct s3c24xx_led_platdata vr1000_led1_pdata = { 279static struct s3c24xx_led_platdata vr1000_led1_pdata = {
279 .name = "led1", 280 .name = "led1",
280 .gpio = S3C2410_GPB0, 281 .gpio = S3C2410_GPB(0),
281 .def_trigger = "", 282 .def_trigger = "",
282}; 283};
283 284
284static struct s3c24xx_led_platdata vr1000_led2_pdata = { 285static struct s3c24xx_led_platdata vr1000_led2_pdata = {
285 .name = "led2", 286 .name = "led2",
286 .gpio = S3C2410_GPB1, 287 .gpio = S3C2410_GPB(1),
287 .def_trigger = "", 288 .def_trigger = "",
288}; 289};
289 290
290static struct s3c24xx_led_platdata vr1000_led3_pdata = { 291static struct s3c24xx_led_platdata vr1000_led3_pdata = {
291 .name = "led3", 292 .name = "led3",
292 .gpio = S3C2410_GPB2, 293 .gpio = S3C2410_GPB(2),
293 .def_trigger = "", 294 .def_trigger = "",
294}; 295};
295 296
@@ -355,8 +356,8 @@ static struct clk *vr1000_clocks[] __initdata = {
355 356
356static void vr1000_power_off(void) 357static void vr1000_power_off(void)
357{ 358{
358 s3c2410_gpio_cfgpin(S3C2410_GPB9, S3C2410_GPB9_OUTP); 359 s3c2410_gpio_cfgpin(S3C2410_GPB(9), S3C2410_GPIO_OUTPUT);
359 s3c2410_gpio_setpin(S3C2410_GPB9, 1); 360 s3c2410_gpio_setpin(S3C2410_GPB(9), 1);
360} 361}
361 362
362static void __init vr1000_map_io(void) 363static void __init vr1000_map_io(void)
diff --git a/arch/arm/mach-s3c2410/pm.c b/arch/arm/mach-s3c2410/pm.c
index 87fc481d92d4..143e08a599d4 100644
--- a/arch/arm/mach-s3c2410/pm.c
+++ b/arch/arm/mach-s3c2410/pm.c
@@ -25,6 +25,7 @@
25#include <linux/errno.h> 25#include <linux/errno.h>
26#include <linux/time.h> 26#include <linux/time.h>
27#include <linux/sysdev.h> 27#include <linux/sysdev.h>
28#include <linux/gpio.h>
28#include <linux/io.h> 29#include <linux/io.h>
29 30
30#include <mach/hardware.h> 31#include <mach/hardware.h>
@@ -76,7 +77,7 @@ static void s3c2410_pm_prepare(void)
76 } 77 }
77 78
78 if ( machine_is_aml_m5900() ) 79 if ( machine_is_aml_m5900() )
79 s3c2410_gpio_setpin(S3C2410_GPF2, 1); 80 s3c2410_gpio_setpin(S3C2410_GPF(2), 1);
80 81
81} 82}
82 83
@@ -91,7 +92,7 @@ static int s3c2410_pm_resume(struct sys_device *dev)
91 __raw_writel(tmp, S3C2410_GSTATUS2); 92 __raw_writel(tmp, S3C2410_GSTATUS2);
92 93
93 if ( machine_is_aml_m5900() ) 94 if ( machine_is_aml_m5900() )
94 s3c2410_gpio_setpin(S3C2410_GPF2, 0); 95 s3c2410_gpio_setpin(S3C2410_GPF(2), 0);
95 96
96 return 0; 97 return 0;
97} 98}
diff --git a/arch/arm/mach-s3c2410/usb-simtec.c b/arch/arm/mach-s3c2410/usb-simtec.c
index 8331e8d97e20..6cd9377ddb82 100644
--- a/arch/arm/mach-s3c2410/usb-simtec.c
+++ b/arch/arm/mach-s3c2410/usb-simtec.c
@@ -18,9 +18,11 @@
18#include <linux/types.h> 18#include <linux/types.h>
19#include <linux/interrupt.h> 19#include <linux/interrupt.h>
20#include <linux/list.h> 20#include <linux/list.h>
21#include <linux/gpio.h>
21#include <linux/timer.h> 22#include <linux/timer.h>
22#include <linux/init.h> 23#include <linux/init.h>
23#include <linux/device.h> 24#include <linux/device.h>
25#include <linux/gpio.h>
24#include <linux/io.h> 26#include <linux/io.h>
25 27
26#include <asm/mach/arch.h> 28#include <asm/mach/arch.h>
@@ -29,7 +31,6 @@
29 31
30#include <mach/bast-map.h> 32#include <mach/bast-map.h>
31#include <mach/bast-irq.h> 33#include <mach/bast-irq.h>
32#include <mach/regs-gpio.h>
33 34
34#include <mach/hardware.h> 35#include <mach/hardware.h>
35#include <asm/irq.h> 36#include <asm/irq.h>
@@ -53,9 +54,9 @@ usb_simtec_powercontrol(int port, int to)
53 power_state[port] = to; 54 power_state[port] = to;
54 55
55 if (power_state[0] && power_state[1]) 56 if (power_state[0] && power_state[1])
56 s3c2410_gpio_setpin(S3C2410_GPB4, 0); 57 gpio_set_value(S3C2410_GPB(4), 0);
57 else 58 else
58 s3c2410_gpio_setpin(S3C2410_GPB4, 1); 59 gpio_set_value(S3C2410_GPB(4), 1);
59} 60}
60 61
61static irqreturn_t 62static irqreturn_t
@@ -63,7 +64,7 @@ usb_simtec_ocirq(int irq, void *pw)
63{ 64{
64 struct s3c2410_hcd_info *info = pw; 65 struct s3c2410_hcd_info *info = pw;
65 66
66 if (s3c2410_gpio_getpin(S3C2410_GPG10) == 0) { 67 if (gpio_get_value(S3C2410_GPG(10)) == 0) {
67 pr_debug("usb_simtec: over-current irq (oc detected)\n"); 68 pr_debug("usb_simtec: over-current irq (oc detected)\n");
68 s3c2410_usb_report_oc(info, 3); 69 s3c2410_usb_report_oc(info, 3);
69 } else { 70 } else {
@@ -106,10 +107,27 @@ static struct s3c2410_hcd_info usb_simtec_info = {
106 107
107int usb_simtec_init(void) 108int usb_simtec_init(void)
108{ 109{
110 int ret;
111
109 printk("USB Power Control, (c) 2004 Simtec Electronics\n"); 112 printk("USB Power Control, (c) 2004 Simtec Electronics\n");
110 s3c_device_usb.dev.platform_data = &usb_simtec_info;
111 113
112 s3c2410_gpio_cfgpin(S3C2410_GPB4, S3C2410_GPB4_OUTP); 114 ret = gpio_request(S3C2410_GPB(4), "USB power control");
113 s3c2410_gpio_setpin(S3C2410_GPB4, 1); 115 if (ret < 0) {
116 pr_err("%s: failed to get GPB4\n", __func__);
117 return ret;
118 }
119
120 ret = gpio_request(S3C2410_GPG(10), "USB overcurrent");
121 if (ret < 0) {
122 pr_err("%s: failed to get GPG10\n", __func__);
123 gpio_free(S3C2410_GPB(4));
124 return ret;
125 }
126
127 /* turn power on */
128 gpio_direction_output(S3C2410_GPB(4), 1);
129 gpio_direction_input(S3C2410_GPG(10));
130
131 s3c_device_usb.dev.platform_data = &usb_simtec_info;
114 return 0; 132 return 0;
115} 133}
diff --git a/arch/arm/mach-s3c2412/Kconfig b/arch/arm/mach-s3c2412/Kconfig
index ca99564ae4b5..63586ffd0ae7 100644
--- a/arch/arm/mach-s3c2412/Kconfig
+++ b/arch/arm/mach-s3c2412/Kconfig
@@ -38,6 +38,7 @@ menu "S3C2412 Machines"
38config MACH_JIVE 38config MACH_JIVE
39 bool "Logitech Jive" 39 bool "Logitech Jive"
40 select CPU_S3C2412 40 select CPU_S3C2412
41 select S3C_DEV_USB_HOST
41 help 42 help
42 Say Y here if you are using the Logitech Jive. 43 Say Y here if you are using the Logitech Jive.
43 44
@@ -50,6 +51,7 @@ config MACH_SMDK2413
50 select CPU_S3C2412 51 select CPU_S3C2412
51 select MACH_S3C2413 52 select MACH_S3C2413
52 select MACH_SMDK 53 select MACH_SMDK
54 select S3C_DEV_USB_HOST
53 help 55 help
54 Say Y here if you are using an SMDK2413 56 Say Y here if you are using an SMDK2413
55 57
@@ -72,6 +74,7 @@ config MACH_SMDK2412
72config MACH_VSTMS 74config MACH_VSTMS
73 bool "VMSTMS" 75 bool "VMSTMS"
74 select CPU_S3C2412 76 select CPU_S3C2412
77 select S3C_DEV_USB_HOST
75 help 78 help
76 Say Y here if you are using an VSTMS board 79 Say Y here if you are using an VSTMS board
77 80
diff --git a/arch/arm/mach-s3c2412/dma.c b/arch/arm/mach-s3c2412/dma.c
index 9e3478506c6f..f8d16fc10bc6 100644
--- a/arch/arm/mach-s3c2412/dma.c
+++ b/arch/arm/mach-s3c2412/dma.c
@@ -20,12 +20,13 @@
20 20
21#include <mach/dma.h> 21#include <mach/dma.h>
22 22
23#include <plat/dma.h> 23#include <plat/dma-plat.h>
24#include <plat/cpu.h> 24#include <plat/cpu.h>
25 25
26#include <plat/regs-serial.h> 26#include <plat/regs-serial.h>
27#include <mach/regs-gpio.h> 27#include <mach/regs-gpio.h>
28#include <plat/regs-ac97.h> 28#include <plat/regs-ac97.h>
29#include <plat/regs-dma.h>
29#include <mach/regs-mem.h> 30#include <mach/regs-mem.h>
30#include <mach/regs-lcd.h> 31#include <mach/regs-lcd.h>
31#include <mach/regs-sdi.h> 32#include <mach/regs-sdi.h>
diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c2412/mach-jive.c
index 8f0d37d43b43..8df506eac903 100644
--- a/arch/arm/mach-s3c2412/mach-jive.c
+++ b/arch/arm/mach-s3c2412/mach-jive.c
@@ -16,6 +16,7 @@
16#include <linux/list.h> 16#include <linux/list.h>
17#include <linux/timer.h> 17#include <linux/timer.h>
18#include <linux/init.h> 18#include <linux/init.h>
19#include <linux/gpio.h>
19#include <linux/sysdev.h> 20#include <linux/sysdev.h>
20#include <linux/serial_core.h> 21#include <linux/serial_core.h>
21#include <linux/platform_device.h> 22#include <linux/platform_device.h>
@@ -356,8 +357,8 @@ static void jive_lcm_reset(unsigned int set)
356{ 357{
357 printk(KERN_DEBUG "%s(%d)\n", __func__, set); 358 printk(KERN_DEBUG "%s(%d)\n", __func__, set);
358 359
359 s3c2410_gpio_setpin(S3C2410_GPG13, set); 360 s3c2410_gpio_setpin(S3C2410_GPG(13), set);
360 s3c2410_gpio_cfgpin(S3C2410_GPG13, S3C2410_GPIO_OUTPUT); 361 s3c2410_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPIO_OUTPUT);
361} 362}
362 363
363#undef LCD_UPPER_MARGIN 364#undef LCD_UPPER_MARGIN
@@ -390,13 +391,13 @@ static struct ili9320_platdata jive_lcm_config = {
390 391
391static void jive_lcd_spi_chipselect(struct s3c2410_spigpio_info *spi, int cs) 392static void jive_lcd_spi_chipselect(struct s3c2410_spigpio_info *spi, int cs)
392{ 393{
393 s3c2410_gpio_setpin(S3C2410_GPB7, cs ? 0 : 1); 394 s3c2410_gpio_setpin(S3C2410_GPB(7), cs ? 0 : 1);
394} 395}
395 396
396static struct s3c2410_spigpio_info jive_lcd_spi = { 397static struct s3c2410_spigpio_info jive_lcd_spi = {
397 .bus_num = 1, 398 .bus_num = 1,
398 .pin_clk = S3C2410_GPG8, 399 .pin_clk = S3C2410_GPG(8),
399 .pin_mosi = S3C2410_GPB8, 400 .pin_mosi = S3C2410_GPB(8),
400 .num_chipselect = 1, 401 .num_chipselect = 1,
401 .chip_select = jive_lcd_spi_chipselect, 402 .chip_select = jive_lcd_spi_chipselect,
402}; 403};
@@ -412,13 +413,13 @@ static struct platform_device jive_device_lcdspi = {
412 413
413static void jive_wm8750_chipselect(struct s3c2410_spigpio_info *spi, int cs) 414static void jive_wm8750_chipselect(struct s3c2410_spigpio_info *spi, int cs)
414{ 415{
415 s3c2410_gpio_setpin(S3C2410_GPH10, cs ? 0 : 1); 416 s3c2410_gpio_setpin(S3C2410_GPH(10), cs ? 0 : 1);
416} 417}
417 418
418static struct s3c2410_spigpio_info jive_wm8750_spi = { 419static struct s3c2410_spigpio_info jive_wm8750_spi = {
419 .bus_num = 2, 420 .bus_num = 2,
420 .pin_clk = S3C2410_GPB4, 421 .pin_clk = S3C2410_GPB(4),
421 .pin_mosi = S3C2410_GPB9, 422 .pin_mosi = S3C2410_GPB(9),
422 .num_chipselect = 1, 423 .num_chipselect = 1,
423 .chip_select = jive_wm8750_chipselect, 424 .chip_select = jive_wm8750_chipselect,
424}; 425};
@@ -479,7 +480,7 @@ static struct platform_device *jive_devices[] __initdata = {
479}; 480};
480 481
481static struct s3c2410_udc_mach_info jive_udc_cfg __initdata = { 482static struct s3c2410_udc_mach_info jive_udc_cfg __initdata = {
482 .vbus_pin = S3C2410_GPG1, /* detect is on GPG1 */ 483 .vbus_pin = S3C2410_GPG(1), /* detect is on GPG1 */
483}; 484};
484 485
485/* Jive power management device */ 486/* Jive power management device */
@@ -529,8 +530,8 @@ static void jive_power_off(void)
529{ 530{
530 printk(KERN_INFO "powering system down...\n"); 531 printk(KERN_INFO "powering system down...\n");
531 532
532 s3c2410_gpio_setpin(S3C2410_GPC5, 1); 533 s3c2410_gpio_setpin(S3C2410_GPC(5), 1);
533 s3c2410_gpio_cfgpin(S3C2410_GPC5, S3C2410_GPIO_OUTPUT); 534 s3c2410_gpio_cfgpin(S3C2410_GPC(5), S3C2410_GPIO_OUTPUT);
534} 535}
535 536
536static void __init jive_machine_init(void) 537static void __init jive_machine_init(void)
@@ -634,22 +635,22 @@ static void __init jive_machine_init(void)
634 635
635 /* initialise the spi */ 636 /* initialise the spi */
636 637
637 s3c2410_gpio_setpin(S3C2410_GPG13, 0); 638 s3c2410_gpio_setpin(S3C2410_GPG(13), 0);
638 s3c2410_gpio_cfgpin(S3C2410_GPG13, S3C2410_GPIO_OUTPUT); 639 s3c2410_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPIO_OUTPUT);
639 640
640 s3c2410_gpio_setpin(S3C2410_GPB7, 1); 641 s3c2410_gpio_setpin(S3C2410_GPB(7), 1);
641 s3c2410_gpio_cfgpin(S3C2410_GPB7, S3C2410_GPIO_OUTPUT); 642 s3c2410_gpio_cfgpin(S3C2410_GPB(7), S3C2410_GPIO_OUTPUT);
642 643
643 s3c2410_gpio_setpin(S3C2410_GPB6, 0); 644 s3c2410_gpio_setpin(S3C2410_GPB(6), 0);
644 s3c2410_gpio_cfgpin(S3C2410_GPB6, S3C2410_GPIO_OUTPUT); 645 s3c2410_gpio_cfgpin(S3C2410_GPB(6), S3C2410_GPIO_OUTPUT);
645 646
646 s3c2410_gpio_setpin(S3C2410_GPG8, 1); 647 s3c2410_gpio_setpin(S3C2410_GPG(8), 1);
647 s3c2410_gpio_cfgpin(S3C2410_GPG8, S3C2410_GPIO_OUTPUT); 648 s3c2410_gpio_cfgpin(S3C2410_GPG(8), S3C2410_GPIO_OUTPUT);
648 649
649 /* initialise the WM8750 spi */ 650 /* initialise the WM8750 spi */
650 651
651 s3c2410_gpio_setpin(S3C2410_GPH10, 1); 652 s3c2410_gpio_setpin(S3C2410_GPH(10), 1);
652 s3c2410_gpio_cfgpin(S3C2410_GPH10, S3C2410_GPIO_OUTPUT); 653 s3c2410_gpio_cfgpin(S3C2410_GPH(10), S3C2410_GPIO_OUTPUT);
653 654
654 /* Turn off suspend on both USB ports, and switch the 655 /* Turn off suspend on both USB ports, and switch the
655 * selectable USB port to USB device mode. */ 656 * selectable USB port to USB device mode. */
diff --git a/arch/arm/mach-s3c2412/mach-smdk2413.c b/arch/arm/mach-s3c2412/mach-smdk2413.c
index eba66aa6bd20..9a5e43419722 100644
--- a/arch/arm/mach-s3c2412/mach-smdk2413.c
+++ b/arch/arm/mach-s3c2412/mach-smdk2413.c
@@ -17,6 +17,7 @@
17#include <linux/list.h> 17#include <linux/list.h>
18#include <linux/timer.h> 18#include <linux/timer.h>
19#include <linux/init.h> 19#include <linux/init.h>
20#include <linux/gpio.h>
20#include <linux/serial_core.h> 21#include <linux/serial_core.h>
21#include <linux/platform_device.h> 22#include <linux/platform_device.h>
22#include <linux/io.h> 23#include <linux/io.h>
@@ -84,10 +85,10 @@ static void smdk2413_udc_pullup(enum s3c2410_udc_cmd_e cmd)
84 switch (cmd) 85 switch (cmd)
85 { 86 {
86 case S3C2410_UDC_P_ENABLE : 87 case S3C2410_UDC_P_ENABLE :
87 s3c2410_gpio_setpin(S3C2410_GPF2, 1); 88 s3c2410_gpio_setpin(S3C2410_GPF(2), 1);
88 break; 89 break;
89 case S3C2410_UDC_P_DISABLE : 90 case S3C2410_UDC_P_DISABLE :
90 s3c2410_gpio_setpin(S3C2410_GPF2, 0); 91 s3c2410_gpio_setpin(S3C2410_GPF(2), 0);
91 break; 92 break;
92 case S3C2410_UDC_P_RESET : 93 case S3C2410_UDC_P_RESET :
93 break; 94 break;
@@ -134,8 +135,8 @@ static void __init smdk2413_machine_init(void)
134{ /* Turn off suspend on both USB ports, and switch the 135{ /* Turn off suspend on both USB ports, and switch the
135 * selectable USB port to USB device mode. */ 136 * selectable USB port to USB device mode. */
136 137
137 s3c2410_gpio_setpin(S3C2410_GPF2, 0); 138 s3c2410_gpio_setpin(S3C2410_GPF(2), 0);
138 s3c2410_gpio_cfgpin(S3C2410_GPF2, S3C2410_GPIO_OUTPUT); 139 s3c2410_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT);
139 140
140 s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST | 141 s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
141 S3C2410_MISCCR_USBSUSPND0 | 142 S3C2410_MISCCR_USBSUSPND0 |
diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig
index cde5ae9a4340..5df73cbf2b40 100644
--- a/arch/arm/mach-s3c2440/Kconfig
+++ b/arch/arm/mach-s3c2440/Kconfig
@@ -33,6 +33,7 @@ config MACH_ANUBIS
33 select PM_SIMTEC if PM 33 select PM_SIMTEC if PM
34 select HAVE_PATA_PLATFORM 34 select HAVE_PATA_PLATFORM
35 select S3C24XX_GPIO_EXTRA64 35 select S3C24XX_GPIO_EXTRA64
36 select S3C_DEV_USB_HOST
36 help 37 help
37 Say Y here if you are using the Simtec Electronics ANUBIS 38 Say Y here if you are using the Simtec Electronics ANUBIS
38 development system 39 development system
@@ -43,6 +44,7 @@ config MACH_OSIRIS
43 select S3C24XX_DCLK 44 select S3C24XX_DCLK
44 select PM_SIMTEC if PM 45 select PM_SIMTEC if PM
45 select S3C24XX_GPIO_EXTRA128 46 select S3C24XX_GPIO_EXTRA128
47 select S3C_DEV_USB_HOST
46 help 48 help
47 Say Y here if you are using the Simtec IM2440D20 module, also 49 Say Y here if you are using the Simtec IM2440D20 module, also
48 known as the Osiris. 50 known as the Osiris.
@@ -58,12 +60,14 @@ config ARCH_S3C2440
58 bool "SMDK2440" 60 bool "SMDK2440"
59 select CPU_S3C2440 61 select CPU_S3C2440
60 select MACH_SMDK 62 select MACH_SMDK
63 select S3C_DEV_USB_HOST
61 help 64 help
62 Say Y here if you are using the SMDK2440. 65 Say Y here if you are using the SMDK2440.
63 66
64config MACH_NEXCODER_2440 67config MACH_NEXCODER_2440
65 bool "NexVision NEXCODER 2440 Light Board" 68 bool "NexVision NEXCODER 2440 Light Board"
66 select CPU_S3C2440 69 select CPU_S3C2440
70 select S3C_DEV_USB_HOST
67 help 71 help
68 Say Y here if you are using the Nex Vision NEXCODER 2440 Light Board 72 Say Y here if you are using the Nex Vision NEXCODER 2440 Light Board
69 73
@@ -76,6 +80,7 @@ config SMDK2440_CPU2440
76config MACH_AT2440EVB 80config MACH_AT2440EVB
77 bool "Avantech AT2440EVB development board" 81 bool "Avantech AT2440EVB development board"
78 select CPU_S3C2440 82 select CPU_S3C2440
83 select S3C_DEV_USB_HOST
79 help 84 help
80 Say Y here if you are using the AT2440EVB development board 85 Say Y here if you are using the AT2440EVB development board
81 86
diff --git a/arch/arm/mach-s3c2440/dma.c b/arch/arm/mach-s3c2440/dma.c
index 69b6cf34df47..e08e081430f0 100644
--- a/arch/arm/mach-s3c2440/dma.c
+++ b/arch/arm/mach-s3c2440/dma.c
@@ -17,14 +17,16 @@
17#include <linux/sysdev.h> 17#include <linux/sysdev.h>
18#include <linux/serial_core.h> 18#include <linux/serial_core.h>
19 19
20#include <mach/map.h>
20#include <mach/dma.h> 21#include <mach/dma.h>
21 22
22#include <plat/dma.h> 23#include <plat/dma-plat.h>
23#include <plat/cpu.h> 24#include <plat/cpu.h>
24 25
25#include <plat/regs-serial.h> 26#include <plat/regs-serial.h>
26#include <mach/regs-gpio.h> 27#include <mach/regs-gpio.h>
27#include <plat/regs-ac97.h> 28#include <plat/regs-ac97.h>
29#include <plat/regs-dma.h>
28#include <mach/regs-mem.h> 30#include <mach/regs-mem.h>
29#include <mach/regs-lcd.h> 31#include <mach/regs-lcd.h>
30#include <mach/regs-sdi.h> 32#include <mach/regs-sdi.h>
diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c2440/mach-anubis.c
index 9c6abf9fb540..68f3870991bf 100644
--- a/arch/arm/mach-s3c2440/mach-anubis.c
+++ b/arch/arm/mach-s3c2440/mach-anubis.c
@@ -15,6 +15,7 @@
15#include <linux/list.h> 15#include <linux/list.h>
16#include <linux/timer.h> 16#include <linux/timer.h>
17#include <linux/init.h> 17#include <linux/init.h>
18#include <linux/gpio.h>
18#include <linux/serial_core.h> 19#include <linux/serial_core.h>
19#include <linux/platform_device.h> 20#include <linux/platform_device.h>
20#include <linux/ata_platform.h> 21#include <linux/ata_platform.h>
@@ -468,7 +469,7 @@ static void __init anubis_map_io(void)
468 anubis_nand_sets[0].nr_partitions = ARRAY_SIZE(anubis_default_nand_part_large); 469 anubis_nand_sets[0].nr_partitions = ARRAY_SIZE(anubis_default_nand_part_large);
469 } else { 470 } else {
470 /* ensure that the GPIO is setup */ 471 /* ensure that the GPIO is setup */
471 s3c2410_gpio_setpin(S3C2410_GPA0, 1); 472 s3c2410_gpio_setpin(S3C2410_GPA(0), 1);
472 } 473 }
473} 474}
474 475
diff --git a/arch/arm/mach-s3c2440/mach-at2440evb.c b/arch/arm/mach-s3c2440/mach-at2440evb.c
index 315c42e31278..dfc7010935da 100644
--- a/arch/arm/mach-s3c2440/mach-at2440evb.c
+++ b/arch/arm/mach-s3c2440/mach-at2440evb.c
@@ -166,7 +166,7 @@ static struct platform_device at2440evb_device_eth = {
166}; 166};
167 167
168static struct s3c24xx_mci_pdata at2440evb_mci_pdata = { 168static struct s3c24xx_mci_pdata at2440evb_mci_pdata = {
169 .gpio_detect = S3C2410_GPG10, 169 .gpio_detect = S3C2410_GPG(10),
170}; 170};
171 171
172/* 7" LCD panel */ 172/* 7" LCD panel */
diff --git a/arch/arm/mach-s3c2440/mach-nexcoder.c b/arch/arm/mach-s3c2440/mach-nexcoder.c
index 7aeaa972d7f5..d43edede590e 100644
--- a/arch/arm/mach-s3c2440/mach-nexcoder.c
+++ b/arch/arm/mach-s3c2440/mach-nexcoder.c
@@ -18,6 +18,7 @@
18#include <linux/list.h> 18#include <linux/list.h>
19#include <linux/timer.h> 19#include <linux/timer.h>
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/gpio.h>
21#include <linux/string.h> 22#include <linux/string.h>
22#include <linux/serial_core.h> 23#include <linux/serial_core.h>
23#include <linux/platform_device.h> 24#include <linux/platform_device.h>
@@ -120,16 +121,16 @@ static struct platform_device *nexcoder_devices[] __initdata = {
120static void __init nexcoder_sensorboard_init(void) 121static void __init nexcoder_sensorboard_init(void)
121{ 122{
122 // Initialize SCCB bus 123 // Initialize SCCB bus
123 s3c2410_gpio_setpin(S3C2410_GPE14, 1); // IICSCL 124 s3c2410_gpio_setpin(S3C2410_GPE(14), 1); // IICSCL
124 s3c2410_gpio_cfgpin(S3C2410_GPE14, S3C2410_GPE14_OUTP); 125 s3c2410_gpio_cfgpin(S3C2410_GPE(14), S3C2410_GPIO_OUTPUT);
125 s3c2410_gpio_setpin(S3C2410_GPE15, 1); // IICSDA 126 s3c2410_gpio_setpin(S3C2410_GPE(15), 1); // IICSDA
126 s3c2410_gpio_cfgpin(S3C2410_GPE15, S3C2410_GPE15_OUTP); 127 s3c2410_gpio_cfgpin(S3C2410_GPE(15), S3C2410_GPIO_OUTPUT);
127 128
128 // Power up the sensor board 129 // Power up the sensor board
129 s3c2410_gpio_setpin(S3C2410_GPF1, 1); 130 s3c2410_gpio_setpin(S3C2410_GPF(1), 1);
130 s3c2410_gpio_cfgpin(S3C2410_GPF1, S3C2410_GPF1_OUTP); // CAM_GPIO7 => nLDO_PWRDN 131 s3c2410_gpio_cfgpin(S3C2410_GPF(1), S3C2410_GPIO_OUTPUT); // CAM_GPIO7 => nLDO_PWRDN
131 s3c2410_gpio_setpin(S3C2410_GPF2, 0); 132 s3c2410_gpio_setpin(S3C2410_GPF(2), 0);
132 s3c2410_gpio_cfgpin(S3C2410_GPF2, S3C2410_GPF2_OUTP); // CAM_GPIO6 => CAM_PWRDN 133 s3c2410_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT); // CAM_GPIO6 => CAM_PWRDN
133} 134}
134 135
135static void __init nexcoder_map_io(void) 136static void __init nexcoder_map_io(void)
diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c
index c8a46685ce38..cba064b49a64 100644
--- a/arch/arm/mach-s3c2440/mach-osiris.c
+++ b/arch/arm/mach-s3c2440/mach-osiris.c
@@ -15,6 +15,7 @@
15#include <linux/list.h> 15#include <linux/list.h>
16#include <linux/timer.h> 16#include <linux/timer.h>
17#include <linux/init.h> 17#include <linux/init.h>
18#include <linux/gpio.h>
18#include <linux/device.h> 19#include <linux/device.h>
19#include <linux/sysdev.h> 20#include <linux/sysdev.h>
20#include <linux/serial_core.h> 21#include <linux/serial_core.h>
@@ -291,8 +292,8 @@ static int osiris_pm_suspend(struct sys_device *sd, pm_message_t state)
291 __raw_writeb(tmp, OSIRIS_VA_CTRL0); 292 __raw_writeb(tmp, OSIRIS_VA_CTRL0);
292 293
293 /* ensure that an nRESET is not generated on resume. */ 294 /* ensure that an nRESET is not generated on resume. */
294 s3c2410_gpio_setpin(S3C2410_GPA21, 1); 295 s3c2410_gpio_setpin(S3C2410_GPA(21), 1);
295 s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_OUT); 296 s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);
296 297
297 return 0; 298 return 0;
298} 299}
@@ -304,7 +305,7 @@ static int osiris_pm_resume(struct sys_device *sd)
304 305
305 __raw_writeb(pm_osiris_ctrl0, OSIRIS_VA_CTRL0); 306 __raw_writeb(pm_osiris_ctrl0, OSIRIS_VA_CTRL0);
306 307
307 s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_nRSTOUT); 308 s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
308 309
309 return 0; 310 return 0;
310} 311}
@@ -384,7 +385,7 @@ static void __init osiris_map_io(void)
384 osiris_nand_sets[0].nr_partitions = ARRAY_SIZE(osiris_default_nand_part_large); 385 osiris_nand_sets[0].nr_partitions = ARRAY_SIZE(osiris_default_nand_part_large);
385 } else { 386 } else {
386 /* write-protect line to the NAND */ 387 /* write-protect line to the NAND */
387 s3c2410_gpio_setpin(S3C2410_GPA0, 1); 388 s3c2410_gpio_setpin(S3C2410_GPA(0), 1);
388 } 389 }
389 390
390 /* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */ 391 /* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */
diff --git a/arch/arm/mach-s3c2443/dma.c b/arch/arm/mach-s3c2443/dma.c
index 8430e5829186..397f3b5c0b47 100644
--- a/arch/arm/mach-s3c2443/dma.c
+++ b/arch/arm/mach-s3c2443/dma.c
@@ -20,12 +20,13 @@
20 20
21#include <mach/dma.h> 21#include <mach/dma.h>
22 22
23#include <plat/dma.h> 23#include <plat/dma-plat.h>
24#include <plat/cpu.h> 24#include <plat/cpu.h>
25 25
26#include <plat/regs-serial.h> 26#include <plat/regs-serial.h>
27#include <mach/regs-gpio.h> 27#include <mach/regs-gpio.h>
28#include <plat/regs-ac97.h> 28#include <plat/regs-ac97.h>
29#include <plat/regs-dma.h>
29#include <mach/regs-mem.h> 30#include <mach/regs-mem.h>
30#include <mach/regs-lcd.h> 31#include <mach/regs-lcd.h>
31#include <mach/regs-sdi.h> 32#include <mach/regs-sdi.h>
diff --git a/arch/arm/mach-s3c6400/Kconfig b/arch/arm/mach-s3c6400/Kconfig
index 6da82b5c09ba..f5af212066c3 100644
--- a/arch/arm/mach-s3c6400/Kconfig
+++ b/arch/arm/mach-s3c6400/Kconfig
@@ -5,4 +5,27 @@
5# 5#
6# Licensed under GPLv2 6# Licensed under GPLv2
7 7
8# Currently nothing here, this will be added later 8# Configuration options for the S3C6410 CPU
9
10config CPU_S3C6400
11 bool
12 select CPU_S3C6400_INIT
13 select CPU_S3C6400_CLOCK
14 help
15 Enable S3C6400 CPU support
16
17config S3C6400_SETUP_SDHCI
18 bool
19 help
20 Internal configuration for default SDHCI
21 setup for S3C6400.
22
23# S36400 Macchine support
24
25config MACH_SMDK6400
26 bool "SMDK6400"
27 select CPU_S3C6400
28 select S3C_DEV_HSMMC
29 select S3C6400_SETUP_SDHCI
30 help
31 Machine support for the Samsung SMDK6400
diff --git a/arch/arm/mach-s3c6400/Makefile b/arch/arm/mach-s3c6400/Makefile
index 8f397db25b87..df1ce4aa03e5 100644
--- a/arch/arm/mach-s3c6400/Makefile
+++ b/arch/arm/mach-s3c6400/Makefile
@@ -12,4 +12,12 @@ obj- :=
12 12
13# Core support for S3C6400 system 13# Core support for S3C6400 system
14 14
15obj-n += blank.o 15obj-$(CONFIG_CPU_S3C6400) += s3c6400.o
16
17# setup support
18
19obj-$(CONFIG_S3C6400_SETUP_SDHCI) += setup-sdhci.o
20
21# Machine support
22
23obj-$(CONFIG_MACH_SMDK6400) += mach-smdk6400.o
diff --git a/arch/arm/mach-s3c6400/include/mach/dma.h b/arch/arm/mach-s3c6400/include/mach/dma.h
index 9771ac2cb07e..1067619f0ba0 100644
--- a/arch/arm/mach-s3c6400/include/mach/dma.h
+++ b/arch/arm/mach-s3c6400/include/mach/dma.h
@@ -11,6 +11,63 @@
11#ifndef __ASM_ARCH_DMA_H 11#ifndef __ASM_ARCH_DMA_H
12#define __ASM_ARCH_DMA_H __FILE__ 12#define __ASM_ARCH_DMA_H __FILE__
13 13
14/* currently nothing here, placeholder */ 14#define S3C_DMA_CHANNELS (16)
15
16/* see mach-s3c2410/dma.h for notes on dma channel numbers */
17
18/* Note, for the S3C64XX architecture we keep the DMACH_
19 * defines in the order they are allocated to [S]DMA0/[S]DMA1
20 * so that is easy to do DHACH_ -> DMA controller conversion
21 */
22enum dma_ch {
23 /* DMA0/SDMA0 */
24 DMACH_UART0 = 0,
25 DMACH_UART0_SRC2,
26 DMACH_UART1,
27 DMACH_UART1_SRC2,
28 DMACH_UART2,
29 DMACH_UART2_SRC2,
30 DMACH_UART3,
31 DMACH_UART3_SRC2,
32 DMACH_PCM0_TX,
33 DMACH_PCM0_RX,
34 DMACH_I2S0_OUT,
35 DMACH_I2S0_IN,
36 DMACH_SPI0_TX,
37 DMACH_SPI0_RX,
38 DMACH_HSI_I2SV40_TX,
39 DMACH_HSI_I2SV40_RX,
40
41 /* DMA1/SDMA1 */
42 DMACH_PCM1_TX = 16,
43 DMACH_PCM1_RX,
44 DMACH_I2S1_OUT,
45 DMACH_I2S1_IN,
46 DMACH_SPI1_TX,
47 DMACH_SPI1_RX,
48 DMACH_AC97_PCMOUT,
49 DMACH_AC97_PCMIN,
50 DMACH_AC97_MICIN,
51 DMACH_PWM,
52 DMACH_IRDA,
53 DMACH_EXTERNAL,
54 DMACH_RES1,
55 DMACH_RES2,
56 DMACH_SECURITY_RX, /* SDMA1 only */
57 DMACH_SECURITY_TX, /* SDMA1 only */
58 DMACH_MAX /* the end */
59};
60
61static __inline__ int s3c_dma_has_circular(void)
62{
63 /* we will be supporting ciruclar buffers as soon as we have DMA
64 * engine support.
65 */
66 return 1;
67}
68
69#define S3C2410_DMAF_CIRCULAR (1 << 0)
70
71#include <plat/dma.h>
15 72
16#endif /* __ASM_ARCH_IRQ_H */ 73#endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s3c6400/include/mach/map.h b/arch/arm/mach-s3c6400/include/mach/map.h
index 8199972ed5bd..5057d9948d35 100644
--- a/arch/arm/mach-s3c6400/include/mach/map.h
+++ b/arch/arm/mach-s3c6400/include/mach/map.h
@@ -39,6 +39,8 @@
39#define S3C_VA_UART3 S3C_VA_UARTx(3) 39#define S3C_VA_UART3 S3C_VA_UARTx(3)
40 40
41#define S3C64XX_PA_FB (0x77100000) 41#define S3C64XX_PA_FB (0x77100000)
42#define S3C64XX_PA_USB_HSOTG (0x7C000000)
43#define S3C64XX_PA_WATCHDOG (0x7E004000)
42#define S3C64XX_PA_SYSCON (0x7E00F000) 44#define S3C64XX_PA_SYSCON (0x7E00F000)
43#define S3C64XX_PA_IIS0 (0x7F002000) 45#define S3C64XX_PA_IIS0 (0x7F002000)
44#define S3C64XX_PA_IIS1 (0x7F003000) 46#define S3C64XX_PA_IIS1 (0x7F003000)
@@ -57,6 +59,8 @@
57#define S3C64XX_PA_MODEM (0x74108000) 59#define S3C64XX_PA_MODEM (0x74108000)
58#define S3C64XX_VA_MODEM S3C_ADDR(0x00600000) 60#define S3C64XX_VA_MODEM S3C_ADDR(0x00600000)
59 61
62#define S3C64XX_PA_USBHOST (0x74300000)
63
60/* place VICs close together */ 64/* place VICs close together */
61#define S3C_VA_VIC0 (S3C_VA_IRQ + 0x00) 65#define S3C_VA_VIC0 (S3C_VA_IRQ + 0x00)
62#define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000) 66#define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000)
@@ -69,5 +73,7 @@
69#define S3C_PA_IIC S3C64XX_PA_IIC0 73#define S3C_PA_IIC S3C64XX_PA_IIC0
70#define S3C_PA_IIC1 S3C64XX_PA_IIC1 74#define S3C_PA_IIC1 S3C64XX_PA_IIC1
71#define S3C_PA_FB S3C64XX_PA_FB 75#define S3C_PA_FB S3C64XX_PA_FB
76#define S3C_PA_USBHOST S3C64XX_PA_USBHOST
77#define S3C_PA_USB_HSOTG S3C64XX_PA_USB_HSOTG
72 78
73#endif /* __ASM_ARCH_6400_MAP_H */ 79#endif /* __ASM_ARCH_6400_MAP_H */
diff --git a/arch/arm/mach-s3c6400/include/mach/regs-clock.h b/arch/arm/mach-s3c6400/include/mach/regs-clock.h
new file mode 100644
index 000000000000..a6c7f4eb3a1b
--- /dev/null
+++ b/arch/arm/mach-s3c6400/include/mach/regs-clock.h
@@ -0,0 +1,16 @@
1/* linux/arch/arm/mach-s3c6400/include/mach/regs-clock.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C64XX - clock register compatibility with s3c24xx
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <plat/regs-clock.h>
16
diff --git a/arch/arm/mach-s3c6400/include/mach/system.h b/arch/arm/mach-s3c6400/include/mach/system.h
index 090cfd969bc7..2e58cb7a7147 100644
--- a/arch/arm/mach-s3c6400/include/mach/system.h
+++ b/arch/arm/mach-s3c6400/include/mach/system.h
@@ -11,6 +11,8 @@
11#ifndef __ASM_ARCH_SYSTEM_H 11#ifndef __ASM_ARCH_SYSTEM_H
12#define __ASM_ARCH_SYSTEM_H __FILE__ 12#define __ASM_ARCH_SYSTEM_H __FILE__
13 13
14#include <plat/watchdog-reset.h>
15
14static void arch_idle(void) 16static void arch_idle(void)
15{ 17{
16 /* nothing here yet */ 18 /* nothing here yet */
@@ -18,7 +20,11 @@ static void arch_idle(void)
18 20
19static void arch_reset(char mode, const char *cmd) 21static void arch_reset(char mode, const char *cmd)
20{ 22{
21 /* nothing here yet */ 23 if (mode != 's')
24 arch_wdt_reset();
25
26 /* if all else fails, or mode was for soft, jump to 0 */
27 cpu_reset(0);
22} 28}
23 29
24#endif /* __ASM_ARCH_IRQ_H */ 30#endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s3c6400/mach-smdk6400.c b/arch/arm/mach-s3c6400/mach-smdk6400.c
new file mode 100644
index 000000000000..ab19285389a7
--- /dev/null
+++ b/arch/arm/mach-s3c6400/mach-smdk6400.c
@@ -0,0 +1,96 @@
1/* linux/arch/arm/mach-s3c6400/mach-smdk6400.c
2 *
3 * Copyright 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/interrupt.h>
15#include <linux/list.h>
16#include <linux/timer.h>
17#include <linux/init.h>
18#include <linux/serial_core.h>
19#include <linux/platform_device.h>
20#include <linux/i2c.h>
21#include <linux/io.h>
22
23#include <asm/mach-types.h>
24
25#include <asm/mach/arch.h>
26#include <asm/mach/map.h>
27#include <asm/mach/irq.h>
28
29#include <mach/hardware.h>
30#include <mach/map.h>
31
32#include <plat/regs-serial.h>
33
34#include <plat/s3c6400.h>
35#include <plat/clock.h>
36#include <plat/devs.h>
37#include <plat/cpu.h>
38#include <plat/iic.h>
39
40#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
41#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
42#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
43
44static struct s3c2410_uartcfg smdk6400_uartcfgs[] __initdata = {
45 [0] = {
46 .hwport = 0,
47 .flags = 0,
48 .ucon = 0x3c5,
49 .ulcon = 0x03,
50 .ufcon = 0x51,
51 },
52 [1] = {
53 .hwport = 1,
54 .flags = 0,
55 .ucon = 0x3c5,
56 .ulcon = 0x03,
57 .ufcon = 0x51,
58 },
59};
60
61static struct map_desc smdk6400_iodesc[] = {};
62
63static void __init smdk6400_map_io(void)
64{
65 s3c64xx_init_io(smdk6400_iodesc, ARRAY_SIZE(smdk6400_iodesc));
66 s3c24xx_init_clocks(12000000);
67 s3c24xx_init_uarts(smdk6400_uartcfgs, ARRAY_SIZE(smdk6400_uartcfgs));
68}
69
70static struct platform_device *smdk6400_devices[] __initdata = {
71 &s3c_device_hsmmc1,
72 &s3c_device_i2c0,
73};
74
75static struct i2c_board_info i2c_devs[] __initdata = {
76 { I2C_BOARD_INFO("wm8753", 0x1A), },
77 { I2C_BOARD_INFO("24c08", 0x50), },
78};
79
80static void __init smdk6400_machine_init(void)
81{
82 i2c_register_board_info(0, i2c_devs, ARRAY_SIZE(i2c_devs));
83 platform_add_devices(smdk6400_devices, ARRAY_SIZE(smdk6400_devices));
84}
85
86MACHINE_START(SMDK6400, "SMDK6400")
87 /* Maintainer: Ben Dooks <ben@fluff.org> */
88 .phys_io = S3C_PA_UART & 0xfff00000,
89 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
90 .boot_params = S3C64XX_PA_SDRAM + 0x100,
91
92 .init_irq = s3c6400_init_irq,
93 .map_io = smdk6400_map_io,
94 .init_machine = smdk6400_machine_init,
95 .timer = &s3c24xx_timer,
96MACHINE_END
diff --git a/arch/arm/mach-s3c6400/s3c6400.c b/arch/arm/mach-s3c6400/s3c6400.c
new file mode 100644
index 000000000000..1ece887d90bb
--- /dev/null
+++ b/arch/arm/mach-s3c6400/s3c6400.c
@@ -0,0 +1,89 @@
1/* linux/arch/arm/mach-s3c6410/cpu.c
2 *
3 * Copyright 2009 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/interrupt.h>
15#include <linux/list.h>
16#include <linux/timer.h>
17#include <linux/init.h>
18#include <linux/clk.h>
19#include <linux/io.h>
20#include <linux/sysdev.h>
21#include <linux/serial_core.h>
22#include <linux/platform_device.h>
23
24#include <asm/mach/arch.h>
25#include <asm/mach/map.h>
26#include <asm/mach/irq.h>
27
28#include <mach/hardware.h>
29#include <asm/irq.h>
30
31#include <plat/cpu-freq.h>
32#include <plat/regs-serial.h>
33#include <plat/regs-clock.h>
34
35#include <plat/cpu.h>
36#include <plat/devs.h>
37#include <plat/clock.h>
38#include <plat/sdhci.h>
39#include <plat/iic-core.h>
40#include <plat/s3c6400.h>
41
42void __init s3c6400_map_io(void)
43{
44 /* setup SDHCI */
45
46 s3c6400_default_sdhci0();
47 s3c6400_default_sdhci1();
48
49 /* the i2c devices are directly compatible with s3c2440 */
50 s3c_i2c0_setname("s3c2440-i2c");
51}
52
53void __init s3c6400_init_clocks(int xtal)
54{
55 printk(KERN_DEBUG "%s: initialising clocks\n", __func__);
56 s3c24xx_register_baseclocks(xtal);
57 s3c64xx_register_clocks();
58 s3c6400_register_clocks(S3C6400_CLKDIV0_ARM_MASK);
59 s3c6400_setup_clocks();
60}
61
62void __init s3c6400_init_irq(void)
63{
64 /* VIC0 does not have IRQS 5..7,
65 * VIC1 is fully populated. */
66 s3c64xx_init_irq(~0 & ~(0xf << 5), ~0);
67}
68
69struct sysdev_class s3c6400_sysclass = {
70 .name = "s3c6400-core",
71};
72
73static struct sys_device s3c6400_sysdev = {
74 .cls = &s3c6400_sysclass,
75};
76
77static int __init s3c6400_core_init(void)
78{
79 return sysdev_class_register(&s3c6400_sysclass);
80}
81
82core_initcall(s3c6400_core_init);
83
84int __init s3c6400_init(void)
85{
86 printk("S3C6400: Initialising architecture\n");
87
88 return sysdev_register(&s3c6400_sysdev);
89}
diff --git a/arch/arm/mach-s3c6400/setup-sdhci.c b/arch/arm/mach-s3c6400/setup-sdhci.c
new file mode 100644
index 000000000000..b93dafbee1f4
--- /dev/null
+++ b/arch/arm/mach-s3c6400/setup-sdhci.c
@@ -0,0 +1,63 @@
1/* linux/arch/arm/mach-s3c6410/setup-sdhci.c
2 *
3 * Copyright 2008 Simtec Electronics
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C6410 - Helper functions for settign up SDHCI device(s) (HSMMC)
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/interrupt.h>
18#include <linux/platform_device.h>
19#include <linux/io.h>
20
21#include <linux/mmc/card.h>
22#include <linux/mmc/host.h>
23
24#include <plat/regs-sdhci.h>
25#include <plat/sdhci.h>
26
27/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
28
29char *s3c6400_hsmmc_clksrcs[4] = {
30 [0] = "hsmmc",
31 [1] = "hsmmc",
32 [2] = "mmc_bus",
33 /* [3] = "48m", - note not succesfully used yet */
34};
35
36void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev,
37 void __iomem *r,
38 struct mmc_ios *ios,
39 struct mmc_card *card)
40{
41 u32 ctrl2, ctrl3;
42
43 ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
44 ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
45 ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
46 S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
47 S3C_SDHCI_CTRL2_ENFBCLKRX |
48 S3C_SDHCI_CTRL2_DFCNT_NONE |
49 S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
50
51 if (ios->clock < 25 * 1000000)
52 ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
53 S3C_SDHCI_CTRL3_FCSEL2 |
54 S3C_SDHCI_CTRL3_FCSEL1 |
55 S3C_SDHCI_CTRL3_FCSEL0);
56 else
57 ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
58
59 printk(KERN_INFO "%s: CTRL 2=%08x, 3=%08x\n", __func__, ctrl2, ctrl3);
60 writel(ctrl2, r + S3C_SDHCI_CONTROL2);
61 writel(ctrl3, r + S3C_SDHCI_CONTROL3);
62}
63
diff --git a/arch/arm/mach-s3c6410/Kconfig b/arch/arm/mach-s3c6410/Kconfig
index 1d5010070027..e63aac7f4e5a 100644
--- a/arch/arm/mach-s3c6410/Kconfig
+++ b/arch/arm/mach-s3c6410/Kconfig
@@ -16,9 +16,18 @@ config CPU_S3C6410
16 16
17config S3C6410_SETUP_SDHCI 17config S3C6410_SETUP_SDHCI
18 bool 18 bool
19 select S3C64XX_SETUP_SDHCI_GPIO
19 help 20 help
20 Internal helper functions for S3C6410 based SDHCI systems 21 Internal helper functions for S3C6410 based SDHCI systems
21 22
23config MACH_ANW6410
24 bool "A&W6410"
25 select CPU_S3C6410
26 select S3C_DEV_FB
27 select S3C64XX_SETUP_FB_24BPP
28 help
29 Machine support for the A&W6410
30
22config MACH_SMDK6410 31config MACH_SMDK6410
23 bool "SMDK6410" 32 bool "SMDK6410"
24 select CPU_S3C6410 33 select CPU_S3C6410
@@ -26,6 +35,8 @@ config MACH_SMDK6410
26 select S3C_DEV_HSMMC1 35 select S3C_DEV_HSMMC1
27 select S3C_DEV_I2C1 36 select S3C_DEV_I2C1
28 select S3C_DEV_FB 37 select S3C_DEV_FB
38 select S3C_DEV_USB_HOST
39 select S3C_DEV_USB_HSOTG
29 select S3C6410_SETUP_SDHCI 40 select S3C6410_SETUP_SDHCI
30 select S3C64XX_SETUP_I2C1 41 select S3C64XX_SETUP_I2C1
31 select S3C64XX_SETUP_FB_24BPP 42 select S3C64XX_SETUP_FB_24BPP
@@ -60,3 +71,29 @@ config SMDK6410_SD_CH1
60 channels 0 and 1 are the same. 71 channels 0 and 1 are the same.
61 72
62endchoice 73endchoice
74
75config SMDK6410_WM1190_EV1
76 bool "Support Wolfson Microelectronics 1190-EV1 PMIC card"
77 depends on MACH_SMDK6410
78 select REGULATOR
79 select REGULATOR_WM8350
80 select MFD_WM8350_I2C
81 select MFD_WM8350_CONFIG_MODE_0
82 select MFD_WM8350_CONFIG_MODE_3
83 select MFD_WM8352_CONFIG_MODE_0
84 help
85 The Wolfson Microelectronics 1190-EV1 is a WM835x based PMIC
86 and audio daughtercard for the Samsung SMDK6410 reference
87 platform. Enabling this option will build support for this
88 module into the kernel. The presence of the module will be
89 detected at runtime so the the resulting kernel can be used
90 with or without the 1190-EV1 fitted.
91
92config MACH_NCP
93 bool "NCP"
94 select CPU_S3C6410
95 select S3C_DEV_I2C1
96 select S3C_DEV_HSMMC1
97 select S3C64XX_SETUP_I2C1
98 help
99 Machine support for the Samsung NCP
diff --git a/arch/arm/mach-s3c6410/Makefile b/arch/arm/mach-s3c6410/Makefile
index 2cd4f189036b..6f9deac88612 100644
--- a/arch/arm/mach-s3c6410/Makefile
+++ b/arch/arm/mach-s3c6410/Makefile
@@ -20,4 +20,8 @@ obj-$(CONFIG_S3C6410_SETUP_SDHCI) += setup-sdhci.o
20 20
21# machine support 21# machine support
22 22
23obj-$(CONFIG_MACH_ANW6410) += mach-anw6410.o
23obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o 24obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o
25obj-$(CONFIG_MACH_NCP) += mach-ncp.o
26
27
diff --git a/arch/arm/mach-s3c6410/cpu.c b/arch/arm/mach-s3c6410/cpu.c
index 6a73ca6b7a3a..ade904de8895 100644
--- a/arch/arm/mach-s3c6410/cpu.c
+++ b/arch/arm/mach-s3c6410/cpu.c
@@ -31,6 +31,7 @@
31 31
32#include <plat/cpu-freq.h> 32#include <plat/cpu-freq.h>
33#include <plat/regs-serial.h> 33#include <plat/regs-serial.h>
34#include <plat/regs-clock.h>
34 35
35#include <plat/cpu.h> 36#include <plat/cpu.h>
36#include <plat/devs.h> 37#include <plat/devs.h>
@@ -68,7 +69,7 @@ void __init s3c6410_init_clocks(int xtal)
68 printk(KERN_DEBUG "%s: initialising clocks\n", __func__); 69 printk(KERN_DEBUG "%s: initialising clocks\n", __func__);
69 s3c24xx_register_baseclocks(xtal); 70 s3c24xx_register_baseclocks(xtal);
70 s3c64xx_register_clocks(); 71 s3c64xx_register_clocks();
71 s3c6400_register_clocks(); 72 s3c6400_register_clocks(S3C6410_CLKDIV0_ARM_MASK);
72 s3c6400_setup_clocks(); 73 s3c6400_setup_clocks();
73} 74}
74 75
diff --git a/arch/arm/mach-s3c6410/mach-anw6410.c b/arch/arm/mach-s3c6410/mach-anw6410.c
new file mode 100644
index 000000000000..661cca63de25
--- /dev/null
+++ b/arch/arm/mach-s3c6410/mach-anw6410.c
@@ -0,0 +1,245 @@
1/* linux/arch/arm/mach-s3c6410/mach-anw6410.c
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 * Copyright 2009 Kwangwoo Lee
8 * Kwangwoo Lee <kwangwoo.lee@gmail.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14*/
15
16#include <linux/kernel.h>
17#include <linux/types.h>
18#include <linux/interrupt.h>
19#include <linux/list.h>
20#include <linux/timer.h>
21#include <linux/init.h>
22#include <linux/serial_core.h>
23#include <linux/platform_device.h>
24#include <linux/io.h>
25#include <linux/i2c.h>
26#include <linux/fb.h>
27#include <linux/gpio.h>
28#include <linux/delay.h>
29#include <linux/dm9000.h>
30
31#include <video/platform_lcd.h>
32
33#include <asm/mach/arch.h>
34#include <asm/mach/map.h>
35#include <asm/mach/irq.h>
36
37#include <mach/hardware.h>
38#include <mach/regs-fb.h>
39#include <mach/map.h>
40
41#include <asm/irq.h>
42#include <asm/mach-types.h>
43
44#include <plat/regs-serial.h>
45#include <plat/iic.h>
46#include <plat/fb.h>
47
48#include <plat/s3c6410.h>
49#include <plat/clock.h>
50#include <plat/devs.h>
51#include <plat/cpu.h>
52#include <plat/regs-gpio.h>
53#include <plat/regs-modem.h>
54
55/* DM9000 */
56#define ANW6410_PA_DM9000 (0x18000000)
57
58/* A hardware buffer to control external devices is mapped at 0x30000000.
59 * It can not be read. So current status must be kept in anw6410_extdev_status.
60 */
61#define ANW6410_VA_EXTDEV S3C_ADDR(0x02000000)
62#define ANW6410_PA_EXTDEV (0x30000000)
63
64#define ANW6410_EN_DM9000 (1<<11)
65#define ANW6410_EN_LCD (1<<14)
66
67static __u32 anw6410_extdev_status;
68
69static struct s3c2410_uartcfg anw6410_uartcfgs[] __initdata = {
70 [0] = {
71 .hwport = 0,
72 .flags = 0,
73 .ucon = 0x3c5,
74 .ulcon = 0x03,
75 .ufcon = 0x51,
76 },
77 [1] = {
78 .hwport = 1,
79 .flags = 0,
80 .ucon = 0x3c5,
81 .ulcon = 0x03,
82 .ufcon = 0x51,
83 },
84};
85
86/* framebuffer and LCD setup. */
87static void __init anw6410_lcd_mode_set(void)
88{
89 u32 tmp;
90
91 /* set the LCD type */
92 tmp = __raw_readl(S3C64XX_SPCON);
93 tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
94 tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
95 __raw_writel(tmp, S3C64XX_SPCON);
96
97 /* remove the LCD bypass */
98 tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
99 tmp &= ~MIFPCON_LCD_BYPASS;
100 __raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
101}
102
103/* GPF1 = LCD panel power
104 * GPF4 = LCD backlight control
105 */
106static void anw6410_lcd_power_set(struct plat_lcd_data *pd,
107 unsigned int power)
108{
109 if (power) {
110 anw6410_extdev_status |= (ANW6410_EN_LCD << 16);
111 __raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
112
113 gpio_direction_output(S3C64XX_GPF(1), 1);
114 gpio_direction_output(S3C64XX_GPF(4), 1);
115 } else {
116 anw6410_extdev_status &= ~(ANW6410_EN_LCD << 16);
117 __raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
118
119 gpio_direction_output(S3C64XX_GPF(1), 0);
120 gpio_direction_output(S3C64XX_GPF(4), 0);
121 }
122}
123
124static struct plat_lcd_data anw6410_lcd_power_data = {
125 .set_power = anw6410_lcd_power_set,
126};
127
128static struct platform_device anw6410_lcd_powerdev = {
129 .name = "platform-lcd",
130 .dev.parent = &s3c_device_fb.dev,
131 .dev.platform_data = &anw6410_lcd_power_data,
132};
133
134static struct s3c_fb_pd_win anw6410_fb_win0 = {
135 /* this is to ensure we use win0 */
136 .win_mode = {
137 .pixclock = 41094,
138 .left_margin = 8,
139 .right_margin = 13,
140 .upper_margin = 7,
141 .lower_margin = 5,
142 .hsync_len = 3,
143 .vsync_len = 1,
144 .xres = 800,
145 .yres = 480,
146 },
147 .max_bpp = 32,
148 .default_bpp = 16,
149};
150
151/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
152static struct s3c_fb_platdata anw6410_lcd_pdata __initdata = {
153 .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
154 .win[0] = &anw6410_fb_win0,
155 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
156 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
157};
158
159/* DM9000AEP 10/100 ethernet controller */
160static void __init anw6410_dm9000_enable(void)
161{
162 anw6410_extdev_status |= (ANW6410_EN_DM9000 << 16);
163 __raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
164}
165
166static struct resource anw6410_dm9000_resource[] = {
167 [0] = {
168 .start = ANW6410_PA_DM9000,
169 .end = ANW6410_PA_DM9000 + 3,
170 .flags = IORESOURCE_MEM,
171 },
172 [1] = {
173 .start = ANW6410_PA_DM9000 + 4,
174 .end = ANW6410_PA_DM9000 + 4 + 500,
175 .flags = IORESOURCE_MEM,
176 },
177 [2] = {
178 .start = IRQ_EINT(15),
179 .end = IRQ_EINT(15),
180 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
181 },
182};
183
184static struct dm9000_plat_data anw6410_dm9000_pdata = {
185 .flags = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
186 /* dev_addr can be set to provide hwaddr. */
187};
188
189static struct platform_device anw6410_device_eth = {
190 .name = "dm9000",
191 .id = -1,
192 .num_resources = ARRAY_SIZE(anw6410_dm9000_resource),
193 .resource = anw6410_dm9000_resource,
194 .dev = {
195 .platform_data = &anw6410_dm9000_pdata,
196 },
197};
198
199static struct map_desc anw6410_iodesc[] __initdata = {
200 {
201 .virtual = (unsigned long)ANW6410_VA_EXTDEV,
202 .pfn = __phys_to_pfn(ANW6410_PA_EXTDEV),
203 .length = SZ_64K,
204 .type = MT_DEVICE,
205 },
206};
207
208static struct platform_device *anw6410_devices[] __initdata = {
209 &s3c_device_fb,
210 &anw6410_lcd_powerdev,
211 &anw6410_device_eth,
212};
213
214static void __init anw6410_map_io(void)
215{
216 s3c64xx_init_io(anw6410_iodesc, ARRAY_SIZE(anw6410_iodesc));
217 s3c24xx_init_clocks(12000000);
218 s3c24xx_init_uarts(anw6410_uartcfgs, ARRAY_SIZE(anw6410_uartcfgs));
219
220 anw6410_lcd_mode_set();
221}
222
223static void __init anw6410_machine_init(void)
224{
225 s3c_fb_set_platdata(&anw6410_lcd_pdata);
226
227 gpio_request(S3C64XX_GPF(1), "panel power");
228 gpio_request(S3C64XX_GPF(4), "LCD backlight");
229
230 anw6410_dm9000_enable();
231
232 platform_add_devices(anw6410_devices, ARRAY_SIZE(anw6410_devices));
233}
234
235MACHINE_START(ANW6410, "A&W6410")
236 /* Maintainer: Kwangwoo Lee <kwangwoo.lee@gmail.com> */
237 .phys_io = S3C_PA_UART & 0xfff00000,
238 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
239 .boot_params = S3C64XX_PA_SDRAM + 0x100,
240
241 .init_irq = s3c6410_init_irq,
242 .map_io = anw6410_map_io,
243 .init_machine = anw6410_machine_init,
244 .timer = &s3c24xx_timer,
245MACHINE_END
diff --git a/arch/arm/mach-s3c6410/mach-ncp.c b/arch/arm/mach-s3c6410/mach-ncp.c
new file mode 100644
index 000000000000..6030636f8548
--- /dev/null
+++ b/arch/arm/mach-s3c6410/mach-ncp.c
@@ -0,0 +1,107 @@
1/*
2 * linux/arch/arm/mach-s3c6410/mach-ncp.c
3 *
4 * Copyright (C) 2008-2009 Samsung Electronics
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/interrupt.h>
15#include <linux/list.h>
16#include <linux/timer.h>
17#include <linux/init.h>
18#include <linux/serial_core.h>
19#include <linux/platform_device.h>
20#include <linux/io.h>
21#include <linux/i2c.h>
22#include <linux/fb.h>
23#include <linux/gpio.h>
24#include <linux/delay.h>
25
26#include <video/platform_lcd.h>
27
28#include <asm/mach/arch.h>
29#include <asm/mach/map.h>
30#include <asm/mach/irq.h>
31
32#include <mach/hardware.h>
33#include <mach/regs-fb.h>
34#include <mach/map.h>
35
36#include <asm/irq.h>
37#include <asm/mach-types.h>
38
39#include <plat/regs-serial.h>
40#include <plat/iic.h>
41#include <plat/fb.h>
42
43#include <plat/s3c6410.h>
44#include <plat/clock.h>
45#include <plat/devs.h>
46#include <plat/cpu.h>
47
48#define UCON S3C2410_UCON_DEFAULT
49#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE
50#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
51
52static struct s3c2410_uartcfg ncp_uartcfgs[] __initdata = {
53 /* REVISIT: NCP uses only serial 1, 2 */
54 [0] = {
55 .hwport = 0,
56 .flags = 0,
57 .ucon = UCON,
58 .ulcon = ULCON,
59 .ufcon = UFCON,
60 },
61 [1] = {
62 .hwport = 1,
63 .flags = 0,
64 .ucon = UCON,
65 .ulcon = ULCON,
66 .ufcon = UFCON,
67 },
68 [2] = {
69 .hwport = 2,
70 .flags = 0,
71 .ucon = UCON,
72 .ulcon = ULCON,
73 .ufcon = UFCON,
74 },
75};
76
77static struct platform_device *ncp_devices[] __initdata = {
78 &s3c_device_hsmmc1,
79 &s3c_device_i2c0,
80};
81
82struct map_desc ncp_iodesc[] = {};
83
84static void __init ncp_map_io(void)
85{
86 s3c64xx_init_io(ncp_iodesc, ARRAY_SIZE(ncp_iodesc));
87 s3c24xx_init_clocks(12000000);
88 s3c24xx_init_uarts(ncp_uartcfgs, ARRAY_SIZE(ncp_uartcfgs));
89}
90
91static void __init ncp_machine_init(void)
92{
93 s3c_i2c0_set_platdata(NULL);
94
95 platform_add_devices(ncp_devices, ARRAY_SIZE(ncp_devices));
96}
97
98MACHINE_START(NCP, "NCP")
99 /* Maintainer: Samsung Electronics */
100 .phys_io = S3C_PA_UART & 0xfff00000,
101 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
102 .boot_params = S3C64XX_PA_SDRAM + 0x100,
103 .init_irq = s3c6410_init_irq,
104 .map_io = ncp_map_io,
105 .init_machine = ncp_machine_init,
106 .timer = &s3c24xx_timer,
107MACHINE_END
diff --git a/arch/arm/mach-s3c6410/mach-smdk6410.c b/arch/arm/mach-s3c6410/mach-smdk6410.c
index 7f473e47e4f1..bc9a7dea567f 100644
--- a/arch/arm/mach-s3c6410/mach-smdk6410.c
+++ b/arch/arm/mach-s3c6410/mach-smdk6410.c
@@ -24,6 +24,12 @@
24#include <linux/fb.h> 24#include <linux/fb.h>
25#include <linux/gpio.h> 25#include <linux/gpio.h>
26#include <linux/delay.h> 26#include <linux/delay.h>
27#include <linux/smsc911x.h>
28
29#ifdef CONFIG_SMDK6410_WM1190_EV1
30#include <linux/mfd/wm8350/core.h>
31#include <linux/mfd/wm8350/pmic.h>
32#endif
27 33
28#include <video/platform_lcd.h> 34#include <video/platform_lcd.h>
29 35
@@ -39,8 +45,12 @@
39#include <asm/mach-types.h> 45#include <asm/mach-types.h>
40 46
41#include <plat/regs-serial.h> 47#include <plat/regs-serial.h>
48#include <plat/regs-modem.h>
49#include <plat/regs-gpio.h>
50#include <plat/regs-sys.h>
42#include <plat/iic.h> 51#include <plat/iic.h>
43#include <plat/fb.h> 52#include <plat/fb.h>
53#include <plat/gpio-cfg.h>
44 54
45#include <plat/s3c6410.h> 55#include <plat/s3c6410.h>
46#include <plat/clock.h> 56#include <plat/clock.h>
@@ -129,6 +139,37 @@ static struct s3c_fb_platdata smdk6410_lcd_pdata __initdata = {
129 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, 139 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
130}; 140};
131 141
142static struct resource smdk6410_smsc911x_resources[] = {
143 [0] = {
144 .start = 0x18000000,
145 .end = 0x18000000 + SZ_64K - 1,
146 .flags = IORESOURCE_MEM,
147 },
148 [1] = {
149 .start = S3C_EINT(10),
150 .end = S3C_EINT(10),
151 .flags = IORESOURCE_IRQ | IRQ_TYPE_LEVEL_LOW,
152 },
153};
154
155static struct smsc911x_platform_config smdk6410_smsc911x_pdata = {
156 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
157 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
158 .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY,
159 .phy_interface = PHY_INTERFACE_MODE_MII,
160};
161
162
163static struct platform_device smdk6410_smsc911x = {
164 .name = "smsc911x",
165 .id = -1,
166 .num_resources = ARRAY_SIZE(smdk6410_smsc911x_resources),
167 .resource = &smdk6410_smsc911x_resources[0],
168 .dev = {
169 .platform_data = &smdk6410_smsc911x_pdata,
170 },
171};
172
132static struct map_desc smdk6410_iodesc[] = {}; 173static struct map_desc smdk6410_iodesc[] = {};
133 174
134static struct platform_device *smdk6410_devices[] __initdata = { 175static struct platform_device *smdk6410_devices[] __initdata = {
@@ -141,12 +182,155 @@ static struct platform_device *smdk6410_devices[] __initdata = {
141 &s3c_device_i2c0, 182 &s3c_device_i2c0,
142 &s3c_device_i2c1, 183 &s3c_device_i2c1,
143 &s3c_device_fb, 184 &s3c_device_fb,
185 &s3c_device_usb,
186 &s3c_device_usb_hsotg,
144 &smdk6410_lcd_powerdev, 187 &smdk6410_lcd_powerdev,
188
189 &smdk6410_smsc911x,
190};
191
192#ifdef CONFIG_SMDK6410_WM1190_EV1
193/* S3C64xx internal logic & PLL */
194static struct regulator_init_data wm8350_dcdc1_data = {
195 .constraints = {
196 .name = "PVDD_INT/PVDD_PLL",
197 .min_uV = 1200000,
198 .max_uV = 1200000,
199 .always_on = 1,
200 .apply_uV = 1,
201 },
202};
203
204/* Memory */
205static struct regulator_init_data wm8350_dcdc3_data = {
206 .constraints = {
207 .name = "PVDD_MEM",
208 .min_uV = 1800000,
209 .max_uV = 1800000,
210 .always_on = 1,
211 .state_mem = {
212 .uV = 1800000,
213 .mode = REGULATOR_MODE_NORMAL,
214 .enabled = 1,
215 },
216 .initial_state = PM_SUSPEND_MEM,
217 },
218};
219
220/* USB, EXT, PCM, ADC/DAC, USB, MMC */
221static struct regulator_init_data wm8350_dcdc4_data = {
222 .constraints = {
223 .name = "PVDD_HI/PVDD_EXT/PVDD_SYS/PVCCM2MTV",
224 .min_uV = 3000000,
225 .max_uV = 3000000,
226 .always_on = 1,
227 },
228};
229
230/* ARM core */
231static struct regulator_consumer_supply dcdc6_consumers[] = {
232 {
233 .supply = "vddarm",
234 }
235};
236
237static struct regulator_init_data wm8350_dcdc6_data = {
238 .constraints = {
239 .name = "PVDD_ARM",
240 .min_uV = 1000000,
241 .max_uV = 1300000,
242 .always_on = 1,
243 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
244 },
245 .num_consumer_supplies = ARRAY_SIZE(dcdc6_consumers),
246 .consumer_supplies = dcdc6_consumers,
145}; 247};
146 248
249/* Alive */
250static struct regulator_init_data wm8350_ldo1_data = {
251 .constraints = {
252 .name = "PVDD_ALIVE",
253 .min_uV = 1200000,
254 .max_uV = 1200000,
255 .always_on = 1,
256 .apply_uV = 1,
257 },
258};
259
260/* OTG */
261static struct regulator_init_data wm8350_ldo2_data = {
262 .constraints = {
263 .name = "PVDD_OTG",
264 .min_uV = 3300000,
265 .max_uV = 3300000,
266 .always_on = 1,
267 },
268};
269
270/* LCD */
271static struct regulator_init_data wm8350_ldo3_data = {
272 .constraints = {
273 .name = "PVDD_LCD",
274 .min_uV = 3000000,
275 .max_uV = 3000000,
276 .always_on = 1,
277 },
278};
279
280/* OTGi/1190-EV1 HPVDD & AVDD */
281static struct regulator_init_data wm8350_ldo4_data = {
282 .constraints = {
283 .name = "PVDD_OTGI/HPVDD/AVDD",
284 .min_uV = 1200000,
285 .max_uV = 1200000,
286 .apply_uV = 1,
287 .always_on = 1,
288 },
289};
290
291static struct {
292 int regulator;
293 struct regulator_init_data *initdata;
294} wm1190_regulators[] = {
295 { WM8350_DCDC_1, &wm8350_dcdc1_data },
296 { WM8350_DCDC_3, &wm8350_dcdc3_data },
297 { WM8350_DCDC_4, &wm8350_dcdc4_data },
298 { WM8350_DCDC_6, &wm8350_dcdc6_data },
299 { WM8350_LDO_1, &wm8350_ldo1_data },
300 { WM8350_LDO_2, &wm8350_ldo2_data },
301 { WM8350_LDO_3, &wm8350_ldo3_data },
302 { WM8350_LDO_4, &wm8350_ldo4_data },
303};
304
305static int __init smdk6410_wm8350_init(struct wm8350 *wm8350)
306{
307 int i;
308
309 /* Instantiate the regulators */
310 for (i = 0; i < ARRAY_SIZE(wm1190_regulators); i++)
311 wm8350_register_regulator(wm8350,
312 wm1190_regulators[i].regulator,
313 wm1190_regulators[i].initdata);
314
315 return 0;
316}
317
318static struct wm8350_platform_data __initdata smdk6410_wm8350_pdata = {
319 .init = smdk6410_wm8350_init,
320 .irq_high = 1,
321};
322#endif
323
147static struct i2c_board_info i2c_devs0[] __initdata = { 324static struct i2c_board_info i2c_devs0[] __initdata = {
148 { I2C_BOARD_INFO("24c08", 0x50), }, 325 { I2C_BOARD_INFO("24c08", 0x50), },
149 { I2C_BOARD_INFO("wm8580", 0x1b), }, 326 { I2C_BOARD_INFO("wm8580", 0x1b), },
327
328#ifdef CONFIG_SMDK6410_WM1190_EV1
329 { I2C_BOARD_INFO("wm8350", 0x1a),
330 .platform_data = &smdk6410_wm8350_pdata,
331 .irq = S3C_EINT(12),
332 },
333#endif
150}; 334};
151 335
152static struct i2c_board_info i2c_devs1[] __initdata = { 336static struct i2c_board_info i2c_devs1[] __initdata = {
@@ -155,9 +339,23 @@ static struct i2c_board_info i2c_devs1[] __initdata = {
155 339
156static void __init smdk6410_map_io(void) 340static void __init smdk6410_map_io(void)
157{ 341{
342 u32 tmp;
343
158 s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc)); 344 s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc));
159 s3c24xx_init_clocks(12000000); 345 s3c24xx_init_clocks(12000000);
160 s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs)); 346 s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs));
347
348 /* set the LCD type */
349
350 tmp = __raw_readl(S3C64XX_SPCON);
351 tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
352 tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
353 __raw_writel(tmp, S3C64XX_SPCON);
354
355 /* remove the lcd bypass */
356 tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
357 tmp &= ~MIFPCON_LCD_BYPASS;
358 __raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
161} 359}
162 360
163static void __init smdk6410_machine_init(void) 361static void __init smdk6410_machine_init(void)
diff --git a/arch/arm/mach-s3c6410/setup-sdhci.c b/arch/arm/mach-s3c6410/setup-sdhci.c
index 0b5788bd5985..20666f3bd478 100644
--- a/arch/arm/mach-s3c6410/setup-sdhci.c
+++ b/arch/arm/mach-s3c6410/setup-sdhci.c
@@ -21,8 +21,6 @@
21#include <linux/mmc/card.h> 21#include <linux/mmc/card.h>
22#include <linux/mmc/host.h> 22#include <linux/mmc/host.h>
23 23
24#include <mach/gpio.h>
25#include <plat/gpio-cfg.h>
26#include <plat/regs-sdhci.h> 24#include <plat/regs-sdhci.h>
27#include <plat/sdhci.h> 25#include <plat/sdhci.h>
28 26
@@ -35,22 +33,6 @@ char *s3c6410_hsmmc_clksrcs[4] = {
35 /* [3] = "48m", - note not succesfully used yet */ 33 /* [3] = "48m", - note not succesfully used yet */
36}; 34};
37 35
38void s3c6410_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
39{
40 unsigned int gpio;
41 unsigned int end;
42
43 end = S3C64XX_GPG(2 + width);
44
45 /* Set all the necessary GPG pins to special-function 0 */
46 for (gpio = S3C64XX_GPG(0); gpio < end; gpio++) {
47 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
48 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
49 }
50
51 s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
52 s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(2));
53}
54 36
55void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev, 37void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev,
56 void __iomem *r, 38 void __iomem *r,
@@ -84,19 +66,3 @@ void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev,
84 writel(ctrl3, r + S3C_SDHCI_CONTROL3); 66 writel(ctrl3, r + S3C_SDHCI_CONTROL3);
85} 67}
86 68
87void s3c6410_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
88{
89 unsigned int gpio;
90 unsigned int end;
91
92 end = S3C64XX_GPH(2 + width);
93
94 /* Set all the necessary GPG pins to special-function 0 */
95 for (gpio = S3C64XX_GPH(0); gpio < end; gpio++) {
96 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
97 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
98 }
99
100 s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
101 s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(3));
102}
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index b3bebcc5623b..69214fc8bd19 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -116,7 +116,7 @@ void __init versatile_init_irq(void)
116{ 116{
117 unsigned int i; 117 unsigned int i;
118 118
119 vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0); 119 vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0, 0);
120 120
121 set_irq_chained_handler(IRQ_VICSOURCE31, sic_handle_irq); 121 set_irq_chained_handler(IRQ_VICSOURCE31, sic_handle_irq);
122 122
diff --git a/arch/arm/plat-s3c/Kconfig b/arch/arm/plat-s3c/Kconfig
index de9383814e5e..935c7558469b 100644
--- a/arch/arm/plat-s3c/Kconfig
+++ b/arch/arm/plat-s3c/Kconfig
@@ -71,6 +71,15 @@ config S3C2410_PM_DEBUG
71 Resume code. See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt> 71 Resume code. See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt>
72 for more information. 72 for more information.
73 73
74config S3C_PM_DEBUG_LED_SMDK
75 bool "SMDK LED suspend/resume debugging"
76 depends on PM && (MACH_SMDK6410)
77 help
78 Say Y here to enable the use of the SMDK LEDs on the baseboard
79 for debugging of the state of the suspend and resume process.
80
81 Note, this currently only works for S3C64XX based SMDK boards.
82
74config S3C2410_PM_CHECK 83config S3C2410_PM_CHECK
75 bool "S3C2410 PM Suspend Memory CRC" 84 bool "S3C2410 PM Suspend Memory CRC"
76 depends on PM && CRC32 85 depends on PM && CRC32
@@ -150,6 +159,13 @@ config S3C_GPIO_CFG_S3C64XX
150 Internal configuration to enable S3C64XX style GPIO configuration 159 Internal configuration to enable S3C64XX style GPIO configuration
151 functions. 160 functions.
152 161
162# DMA
163
164config S3C_DMA
165 bool
166 help
167 Internal configuration for S3C DMA core
168
153# device definitions to compile in 169# device definitions to compile in
154 170
155config S3C_DEV_HSMMC 171config S3C_DEV_HSMMC
@@ -172,4 +188,14 @@ config S3C_DEV_FB
172 help 188 help
173 Compile in platform device definition for framebuffer 189 Compile in platform device definition for framebuffer
174 190
191config S3C_DEV_USB_HOST
192 bool
193 help
194 Compile in platform device definition for USB host.
195
196config S3C_DEV_USB_HSOTG
197 bool
198 help
199 Compile in platform device definition for USB high-speed OtG
200
175endif 201endif
diff --git a/arch/arm/plat-s3c/Makefile b/arch/arm/plat-s3c/Makefile
index 8d7815d25a51..610651455a78 100644
--- a/arch/arm/plat-s3c/Makefile
+++ b/arch/arm/plat-s3c/Makefile
@@ -18,9 +18,14 @@ obj-y += pwm-clock.o
18obj-y += gpio.o 18obj-y += gpio.o
19obj-y += gpio-config.o 19obj-y += gpio-config.o
20 20
21# DMA support
22
23obj-$(CONFIG_S3C_DMA) += dma.o
24
21# PM support 25# PM support
22 26
23obj-$(CONFIG_PM) += pm.o 27obj-$(CONFIG_PM) += pm.o
28obj-$(CONFIG_PM) += pm-gpio.o
24obj-$(CONFIG_S3C2410_PM_CHECK) += pm-check.o 29obj-$(CONFIG_S3C2410_PM_CHECK) += pm-check.o
25 30
26# devices 31# devices
@@ -30,3 +35,5 @@ obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmmc1.o
30obj-y += dev-i2c0.o 35obj-y += dev-i2c0.o
31obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o 36obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o
32obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o 37obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o
38obj-$(CONFIG_S3C_DEV_USB_HOST) += dev-usb.o
39obj-$(CONFIG_S3C_DEV_USB_HSOTG) += dev-usb-hsotg.o
diff --git a/arch/arm/plat-s3c/dev-usb-hsotg.c b/arch/arm/plat-s3c/dev-usb-hsotg.c
new file mode 100644
index 000000000000..e2f604b51c86
--- /dev/null
+++ b/arch/arm/plat-s3c/dev-usb-hsotg.c
@@ -0,0 +1,41 @@
1/* linux/arch/arm/plat-s3c/dev-usb-hsotg.c
2 *
3 * Copyright 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * S3C series device definition for USB high-speed UDC/OtG block
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/kernel.h>
15#include <linux/string.h>
16#include <linux/platform_device.h>
17
18#include <mach/irqs.h>
19#include <mach/map.h>
20
21#include <plat/devs.h>
22
23static struct resource s3c_usb_hsotg_resources[] = {
24 [0] = {
25 .start = S3C_PA_USB_HSOTG,
26 .end = S3C_PA_USB_HSOTG + 0x10000 - 1,
27 .flags = IORESOURCE_MEM,
28 },
29 [1] = {
30 .start = IRQ_OTG,
31 .end = IRQ_OTG,
32 .flags = IORESOURCE_IRQ,
33 },
34};
35
36struct platform_device s3c_device_usb_hsotg = {
37 .name = "s3c-hsotg",
38 .id = -1,
39 .num_resources = ARRAY_SIZE(s3c_usb_hsotg_resources),
40 .resource = s3c_usb_hsotg_resources,
41};
diff --git a/arch/arm/plat-s3c/dev-usb.c b/arch/arm/plat-s3c/dev-usb.c
new file mode 100644
index 000000000000..2ee85abed6d9
--- /dev/null
+++ b/arch/arm/plat-s3c/dev-usb.c
@@ -0,0 +1,50 @@
1/* linux/arch/arm/plat-s3c/dev-usb.c
2 *
3 * Copyright 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * S3C series device definition for USB host
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/kernel.h>
15#include <linux/string.h>
16#include <linux/platform_device.h>
17
18#include <mach/irqs.h>
19#include <mach/map.h>
20
21#include <plat/devs.h>
22
23
24static struct resource s3c_usb_resource[] = {
25 [0] = {
26 .start = S3C_PA_USBHOST,
27 .end = S3C_PA_USBHOST + 0x100 - 1,
28 .flags = IORESOURCE_MEM,
29 },
30 [1] = {
31 .start = IRQ_USBH,
32 .end = IRQ_USBH,
33 .flags = IORESOURCE_IRQ,
34 }
35};
36
37static u64 s3c_device_usb_dmamask = 0xffffffffUL;
38
39struct platform_device s3c_device_usb = {
40 .name = "s3c2410-ohci",
41 .id = -1,
42 .num_resources = ARRAY_SIZE(s3c_usb_resource),
43 .resource = s3c_usb_resource,
44 .dev = {
45 .dma_mask = &s3c_device_usb_dmamask,
46 .coherent_dma_mask = 0xffffffffUL
47 }
48};
49
50EXPORT_SYMBOL(s3c_device_usb);
diff --git a/arch/arm/plat-s3c/dma.c b/arch/arm/plat-s3c/dma.c
new file mode 100644
index 000000000000..c9db75c06af5
--- /dev/null
+++ b/arch/arm/plat-s3c/dma.c
@@ -0,0 +1,86 @@
1/* linux/arch/arm/plat-s3c/dma.c
2 *
3 * Copyright (c) 2003-2005,2006,2009 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * S3C DMA core
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14struct s3c2410_dma_buf;
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/errno.h>
19
20#include <mach/dma.h>
21#include <mach/irqs.h>
22
23#include <plat/dma-plat.h>
24
25/* dma channel state information */
26struct s3c2410_dma_chan s3c2410_chans[S3C_DMA_CHANNELS];
27struct s3c2410_dma_chan *s3c_dma_chan_map[DMACH_MAX];
28
29/* s3c_dma_lookup_channel
30 *
31 * change the dma channel number given into a real dma channel id
32*/
33
34struct s3c2410_dma_chan *s3c_dma_lookup_channel(unsigned int channel)
35{
36 if (channel & DMACH_LOW_LEVEL)
37 return &s3c2410_chans[channel & ~DMACH_LOW_LEVEL];
38 else
39 return s3c_dma_chan_map[channel];
40}
41
42/* do we need to protect the settings of the fields from
43 * irq?
44*/
45
46int s3c2410_dma_set_opfn(unsigned int channel, s3c2410_dma_opfn_t rtn)
47{
48 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
49
50 if (chan == NULL)
51 return -EINVAL;
52
53 pr_debug("%s: chan=%p, op rtn=%p\n", __func__, chan, rtn);
54
55 chan->op_fn = rtn;
56
57 return 0;
58}
59EXPORT_SYMBOL(s3c2410_dma_set_opfn);
60
61int s3c2410_dma_set_buffdone_fn(unsigned int channel, s3c2410_dma_cbfn_t rtn)
62{
63 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
64
65 if (chan == NULL)
66 return -EINVAL;
67
68 pr_debug("%s: chan=%p, callback rtn=%p\n", __func__, chan, rtn);
69
70 chan->callback_fn = rtn;
71
72 return 0;
73}
74EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn);
75
76int s3c2410_dma_setflags(unsigned int channel, unsigned int flags)
77{
78 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
79
80 if (chan == NULL)
81 return -EINVAL;
82
83 chan->flags = flags;
84 return 0;
85}
86EXPORT_SYMBOL(s3c2410_dma_setflags);
diff --git a/arch/arm/plat-s3c/gpio.c b/arch/arm/plat-s3c/gpio.c
index d71dd6d9ce5c..260fdc6ad685 100644
--- a/arch/arm/plat-s3c/gpio.c
+++ b/arch/arm/plat-s3c/gpio.c
@@ -16,7 +16,7 @@
16#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/gpio.h> 17#include <linux/gpio.h>
18 18
19#include <plat/gpio-core.h> 19#include <mach/gpio-core.h>
20 20
21#ifdef CONFIG_S3C_GPIO_TRACK 21#ifdef CONFIG_S3C_GPIO_TRACK
22struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END]; 22struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END];
@@ -140,6 +140,15 @@ __init void s3c_gpiolib_add(struct s3c_gpio_chip *chip)
140 if (!gc->get) 140 if (!gc->get)
141 gc->get = s3c_gpiolib_get; 141 gc->get = s3c_gpiolib_get;
142 142
143#ifdef CONFIG_PM
144 if (chip->pm != NULL) {
145 if (!chip->pm->save || !chip->pm->resume)
146 printk(KERN_ERR "gpio: %s has missing PM functions\n",
147 gc->label);
148 } else
149 printk(KERN_ERR "gpio: %s has no PM function\n", gc->label);
150#endif
151
143 /* gpiochip_add() prints own failure message on error. */ 152 /* gpiochip_add() prints own failure message on error. */
144 ret = gpiochip_add(gc); 153 ret = gpiochip_add(gc);
145 if (ret >= 0) 154 if (ret >= 0)
diff --git a/arch/arm/plat-s3c/include/plat/adc.h b/arch/arm/plat-s3c/include/plat/adc.h
index 43df2a404b0b..d847bd476b6c 100644
--- a/arch/arm/plat-s3c/include/plat/adc.h
+++ b/arch/arm/plat-s3c/include/plat/adc.h
@@ -19,10 +19,12 @@ struct s3c_adc_client;
19extern int s3c_adc_start(struct s3c_adc_client *client, 19extern int s3c_adc_start(struct s3c_adc_client *client,
20 unsigned int channel, unsigned int nr_samples); 20 unsigned int channel, unsigned int nr_samples);
21 21
22extern struct s3c_adc_client *s3c_adc_register(struct platform_device *pdev, 22extern struct s3c_adc_client *
23 void (*select)(unsigned selected), 23 s3c_adc_register(struct platform_device *pdev,
24 void (*conv)(unsigned d0, unsigned d1), 24 void (*select)(unsigned selected),
25 unsigned int is_ts); 25 void (*conv)(unsigned d0, unsigned d1,
26 unsigned *samples_left),
27 unsigned int is_ts);
26 28
27extern void s3c_adc_release(struct s3c_adc_client *client); 29extern void s3c_adc_release(struct s3c_adc_client *client);
28 30
diff --git a/arch/arm/plat-s3c/include/plat/clock.h b/arch/arm/plat-s3c/include/plat/clock.h
index a10622eed43a..d86af84b5b8c 100644
--- a/arch/arm/plat-s3c/include/plat/clock.h
+++ b/arch/arm/plat-s3c/include/plat/clock.h
@@ -50,6 +50,7 @@ extern struct clk clk_xtal;
50extern struct clk clk_ext; 50extern struct clk clk_ext;
51 51
52/* S3C64XX specific clocks */ 52/* S3C64XX specific clocks */
53extern struct clk clk_h2;
53extern struct clk clk_27m; 54extern struct clk clk_27m;
54extern struct clk clk_48m; 55extern struct clk clk_48m;
55 56
diff --git a/arch/arm/plat-s3c/include/plat/cpu.h b/arch/arm/plat-s3c/include/plat/cpu.h
index e62ae0fcfe56..be541cbba070 100644
--- a/arch/arm/plat-s3c/include/plat/cpu.h
+++ b/arch/arm/plat-s3c/include/plat/cpu.h
@@ -69,3 +69,6 @@ extern struct sysdev_class s3c2412_sysclass;
69extern struct sysdev_class s3c2440_sysclass; 69extern struct sysdev_class s3c2440_sysclass;
70extern struct sysdev_class s3c2442_sysclass; 70extern struct sysdev_class s3c2442_sysclass;
71extern struct sysdev_class s3c2443_sysclass; 71extern struct sysdev_class s3c2443_sysclass;
72extern struct sysdev_class s3c6410_sysclass;
73extern struct sysdev_class s3c64xx_sysclass;
74
diff --git a/arch/arm/plat-s3c/include/plat/devs.h b/arch/arm/plat-s3c/include/plat/devs.h
index 26f0cec3ac04..a0b6768fddcf 100644
--- a/arch/arm/plat-s3c/include/plat/devs.h
+++ b/arch/arm/plat-s3c/include/plat/devs.h
@@ -45,6 +45,7 @@ extern struct platform_device s3c_device_spi1;
45extern struct platform_device s3c_device_nand; 45extern struct platform_device s3c_device_nand;
46 46
47extern struct platform_device s3c_device_usbgadget; 47extern struct platform_device s3c_device_usbgadget;
48extern struct platform_device s3c_device_usb_hsotg;
48 49
49/* s3c2440 specific devices */ 50/* s3c2440 specific devices */
50 51
diff --git a/arch/arm/plat-s3c/include/plat/dma-core.h b/arch/arm/plat-s3c/include/plat/dma-core.h
new file mode 100644
index 000000000000..32ff2a92cb3c
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/dma-core.h
@@ -0,0 +1,22 @@
1/* arch/arm/plat-s3c/include/plat/dma.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * Samsung S3C DMA core support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15extern struct s3c2410_dma_chan *s3c_dma_lookup_channel(unsigned int channel);
16
17extern struct s3c2410_dma_chan *s3c_dma_chan_map[];
18
19/* the currently allocated channel information */
20extern struct s3c2410_dma_chan s3c2410_chans[];
21
22
diff --git a/arch/arm/plat-s3c/include/plat/dma.h b/arch/arm/plat-s3c/include/plat/dma.h
new file mode 100644
index 000000000000..34dba98f08e1
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/dma.h
@@ -0,0 +1,127 @@
1/* arch/arm/plat-s3c/include/plat/dma.h
2 *
3 * Copyright (C) 2003,2004,2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Samsung S3C DMA support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13enum s3c2410_dma_buffresult {
14 S3C2410_RES_OK,
15 S3C2410_RES_ERR,
16 S3C2410_RES_ABORT
17};
18
19enum s3c2410_dmasrc {
20 S3C2410_DMASRC_HW, /* source is memory */
21 S3C2410_DMASRC_MEM /* source is hardware */
22};
23
24/* enum s3c2410_chan_op
25 *
26 * operation codes passed to the DMA code by the user, and also used
27 * to inform the current channel owner of any changes to the system state
28*/
29
30enum s3c2410_chan_op {
31 S3C2410_DMAOP_START,
32 S3C2410_DMAOP_STOP,
33 S3C2410_DMAOP_PAUSE,
34 S3C2410_DMAOP_RESUME,
35 S3C2410_DMAOP_FLUSH,
36 S3C2410_DMAOP_TIMEOUT, /* internal signal to handler */
37 S3C2410_DMAOP_STARTED, /* indicate channel started */
38};
39
40struct s3c2410_dma_client {
41 char *name;
42};
43
44struct s3c2410_dma_chan;
45
46/* s3c2410_dma_cbfn_t
47 *
48 * buffer callback routine type
49*/
50
51typedef void (*s3c2410_dma_cbfn_t)(struct s3c2410_dma_chan *,
52 void *buf, int size,
53 enum s3c2410_dma_buffresult result);
54
55typedef int (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *,
56 enum s3c2410_chan_op );
57
58
59
60/* s3c2410_dma_request
61 *
62 * request a dma channel exclusivley
63*/
64
65extern int s3c2410_dma_request(unsigned int channel,
66 struct s3c2410_dma_client *, void *dev);
67
68
69/* s3c2410_dma_ctrl
70 *
71 * change the state of the dma channel
72*/
73
74extern int s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op);
75
76/* s3c2410_dma_setflags
77 *
78 * set the channel's flags to a given state
79*/
80
81extern int s3c2410_dma_setflags(unsigned int channel,
82 unsigned int flags);
83
84/* s3c2410_dma_free
85 *
86 * free the dma channel (will also abort any outstanding operations)
87*/
88
89extern int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *);
90
91/* s3c2410_dma_enqueue
92 *
93 * place the given buffer onto the queue of operations for the channel.
94 * The buffer must be allocated from dma coherent memory, or the Dcache/WB
95 * drained before the buffer is given to the DMA system.
96*/
97
98extern int s3c2410_dma_enqueue(unsigned int channel, void *id,
99 dma_addr_t data, int size);
100
101/* s3c2410_dma_config
102 *
103 * configure the dma channel
104*/
105
106extern int s3c2410_dma_config(unsigned int channel, int xferunit);
107
108/* s3c2410_dma_devconfig
109 *
110 * configure the device we're talking to
111*/
112
113extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source,
114 unsigned long devaddr);
115
116/* s3c2410_dma_getposition
117 *
118 * get the position that the dma transfer is currently at
119*/
120
121extern int s3c2410_dma_getposition(unsigned int channel,
122 dma_addr_t *src, dma_addr_t *dest);
123
124extern int s3c2410_dma_set_opfn(unsigned int, s3c2410_dma_opfn_t rtn);
125extern int s3c2410_dma_set_buffdone_fn(unsigned int, s3c2410_dma_cbfn_t rtn);
126
127
diff --git a/arch/arm/plat-s3c/include/plat/gpio-core.h b/arch/arm/plat-s3c/include/plat/gpio-core.h
index 2fc60a580ac8..32af612767aa 100644
--- a/arch/arm/plat-s3c/include/plat/gpio-core.h
+++ b/arch/arm/plat-s3c/include/plat/gpio-core.h
@@ -20,6 +20,18 @@
20 * specific code. 20 * specific code.
21*/ 21*/
22 22
23struct s3c_gpio_chip;
24
25/**
26 * struct s3c_gpio_pm - power management (suspend/resume) information
27 * @save: Routine to save the state of the GPIO block
28 * @resume: Routine to resume the GPIO block.
29 */
30struct s3c_gpio_pm {
31 void (*save)(struct s3c_gpio_chip *chip);
32 void (*resume)(struct s3c_gpio_chip *chip);
33};
34
23struct s3c_gpio_cfg; 35struct s3c_gpio_cfg;
24 36
25/** 37/**
@@ -27,6 +39,7 @@ struct s3c_gpio_cfg;
27 * @chip: The chip structure to be exported via gpiolib. 39 * @chip: The chip structure to be exported via gpiolib.
28 * @base: The base pointer to the gpio configuration registers. 40 * @base: The base pointer to the gpio configuration registers.
29 * @config: special function and pull-resistor control information. 41 * @config: special function and pull-resistor control information.
42 * @pm_save: Save information for suspend/resume support.
30 * 43 *
31 * This wrapper provides the necessary information for the Samsung 44 * This wrapper provides the necessary information for the Samsung
32 * specific gpios being registered with gpiolib. 45 * specific gpios being registered with gpiolib.
@@ -34,7 +47,11 @@ struct s3c_gpio_cfg;
34struct s3c_gpio_chip { 47struct s3c_gpio_chip {
35 struct gpio_chip chip; 48 struct gpio_chip chip;
36 struct s3c_gpio_cfg *config; 49 struct s3c_gpio_cfg *config;
50 struct s3c_gpio_pm *pm;
37 void __iomem *base; 51 void __iomem *base;
52#ifdef CONFIG_PM
53 u32 pm_save[4];
54#endif
38}; 55};
39 56
40static inline struct s3c_gpio_chip *to_s3c_gpio(struct gpio_chip *gpc) 57static inline struct s3c_gpio_chip *to_s3c_gpio(struct gpio_chip *gpc)
@@ -75,3 +92,16 @@ static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int chip)
75 92
76static inline void s3c_gpiolib_track(struct s3c_gpio_chip *chip) { } 93static inline void s3c_gpiolib_track(struct s3c_gpio_chip *chip) { }
77#endif 94#endif
95
96#ifdef CONFIG_PM
97extern struct s3c_gpio_pm s3c_gpio_pm_1bit;
98extern struct s3c_gpio_pm s3c_gpio_pm_2bit;
99extern struct s3c_gpio_pm s3c_gpio_pm_4bit;
100#define __gpio_pm(x) x
101#else
102#define s3c_gpio_pm_1bit NULL
103#define s3c_gpio_pm_2bit NULL
104#define s3c_gpio_pm_4bit NULL
105#define __gpio_pm(x) NULL
106
107#endif /* CONFIG_PM */
diff --git a/arch/arm/plat-s3c/include/plat/pm.h b/arch/arm/plat-s3c/include/plat/pm.h
index 3779775133a9..7a797192fcf3 100644
--- a/arch/arm/plat-s3c/include/plat/pm.h
+++ b/arch/arm/plat-s3c/include/plat/pm.h
@@ -44,6 +44,8 @@ extern void (*pm_cpu_sleep)(void);
44 44
45extern unsigned long s3c_pm_flags; 45extern unsigned long s3c_pm_flags;
46 46
47extern unsigned char pm_uart_udivslot; /* true to save UART UDIVSLOT */
48
47/* from sleep.S */ 49/* from sleep.S */
48 50
49extern int s3c_cpu_save(unsigned long *saveblk); 51extern int s3c_cpu_save(unsigned long *saveblk);
@@ -88,6 +90,7 @@ struct pm_uart_save {
88 u32 ufcon; 90 u32 ufcon;
89 u32 umcon; 91 u32 umcon;
90 u32 ubrdiv; 92 u32 ubrdiv;
93 u32 udivslot;
91}; 94};
92 95
93/* helper functions to save/restore lists of registers. */ 96/* helper functions to save/restore lists of registers. */
@@ -124,6 +127,18 @@ extern void s3c_pm_dbg(const char *msg, ...);
124#define S3C_PMDBG(fmt...) printk(KERN_DEBUG fmt) 127#define S3C_PMDBG(fmt...) printk(KERN_DEBUG fmt)
125#endif 128#endif
126 129
130#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
131/**
132 * s3c_pm_debug_smdkled() - Debug PM suspend/resume via SMDK Board LEDs
133 * @set: set bits for the state of the LEDs
134 * @clear: clear bits for the state of the LEDs.
135 */
136extern void s3c_pm_debug_smdkled(u32 set, u32 clear);
137
138#else
139static inline void s3c_pm_debug_smdkled(u32 set, u32 clear) { }
140#endif /* CONFIG_S3C_PM_DEBUG_LED_SMDK */
141
127/* suspend memory checking */ 142/* suspend memory checking */
128 143
129#ifdef CONFIG_S3C2410_PM_CHECK 144#ifdef CONFIG_S3C2410_PM_CHECK
diff --git a/arch/arm/plat-s3c/include/plat/regs-serial.h b/arch/arm/plat-s3c/include/plat/regs-serial.h
index 487d7d2a7e1d..66af75a5cdd1 100644
--- a/arch/arm/plat-s3c/include/plat/regs-serial.h
+++ b/arch/arm/plat-s3c/include/plat/regs-serial.h
@@ -189,6 +189,11 @@
189 189
190#define S3C2443_DIVSLOT (0x2C) 190#define S3C2443_DIVSLOT (0x2C)
191 191
192/* S3C64XX interrupt registers. */
193#define S3C64XX_UINTP 0x30
194#define S3C64XX_UINTSP 0x34
195#define S3C64XX_UINTM 0x38
196
192#ifndef __ASSEMBLY__ 197#ifndef __ASSEMBLY__
193 198
194/* struct s3c24xx_uart_clksrc 199/* struct s3c24xx_uart_clksrc
diff --git a/arch/arm/plat-s3c/include/plat/sdhci.h b/arch/arm/plat-s3c/include/plat/sdhci.h
index c4ca3920ca4b..f615308ccdfb 100644
--- a/arch/arm/plat-s3c/include/plat/sdhci.h
+++ b/arch/arm/plat-s3c/include/plat/sdhci.h
@@ -67,12 +67,52 @@ extern struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata;
67 67
68/* Helper function availablity */ 68/* Helper function availablity */
69 69
70extern void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
71extern void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
72
73/* S3C6400 SDHCI setup */
74
75#ifdef CONFIG_S3C6400_SETUP_SDHCI
76extern char *s3c6400_hsmmc_clksrcs[4];
77
78#ifdef CONFIG_S3C_DEV_HSMMC
79extern void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev,
80 void __iomem *r,
81 struct mmc_ios *ios,
82 struct mmc_card *card);
83
84static inline void s3c6400_default_sdhci0(void)
85{
86 s3c_hsmmc0_def_platdata.clocks = s3c6400_hsmmc_clksrcs;
87 s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio;
88 s3c_hsmmc0_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card;
89}
90
91#else
92static inline void s3c6400_default_sdhci0(void) { }
93#endif /* CONFIG_S3C_DEV_HSMMC */
94
95#ifdef CONFIG_S3C_DEV_HSMMC1
96static inline void s3c6400_default_sdhci1(void)
97{
98 s3c_hsmmc1_def_platdata.clocks = s3c6400_hsmmc_clksrcs;
99 s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio;
100 s3c_hsmmc1_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card;
101}
102#else
103static inline void s3c6400_default_sdhci1(void) { }
104#endif /* CONFIG_S3C_DEV_HSMMC1 */
105
106#else
107static inline void s3c6400_default_sdhci0(void) { }
108static inline void s3c6400_default_sdhci1(void) { }
109#endif /* CONFIG_S3C6400_SETUP_SDHCI */
110
111/* S3C6410 SDHCI setup */
112
70#ifdef CONFIG_S3C6410_SETUP_SDHCI 113#ifdef CONFIG_S3C6410_SETUP_SDHCI
71extern char *s3c6410_hsmmc_clksrcs[4]; 114extern char *s3c6410_hsmmc_clksrcs[4];
72 115
73extern void s3c6410_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
74extern void s3c6410_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
75
76extern void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev, 116extern void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev,
77 void __iomem *r, 117 void __iomem *r,
78 struct mmc_ios *ios, 118 struct mmc_ios *ios,
@@ -82,7 +122,7 @@ extern void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev,
82static inline void s3c6410_default_sdhci0(void) 122static inline void s3c6410_default_sdhci0(void)
83{ 123{
84 s3c_hsmmc0_def_platdata.clocks = s3c6410_hsmmc_clksrcs; 124 s3c_hsmmc0_def_platdata.clocks = s3c6410_hsmmc_clksrcs;
85 s3c_hsmmc0_def_platdata.cfg_gpio = s3c6410_setup_sdhci0_cfg_gpio; 125 s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio;
86 s3c_hsmmc0_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card; 126 s3c_hsmmc0_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card;
87} 127}
88#else 128#else
@@ -93,7 +133,7 @@ static inline void s3c6410_default_sdhci0(void) { }
93static inline void s3c6410_default_sdhci1(void) 133static inline void s3c6410_default_sdhci1(void)
94{ 134{
95 s3c_hsmmc1_def_platdata.clocks = s3c6410_hsmmc_clksrcs; 135 s3c_hsmmc1_def_platdata.clocks = s3c6410_hsmmc_clksrcs;
96 s3c_hsmmc1_def_platdata.cfg_gpio = s3c6410_setup_sdhci1_cfg_gpio; 136 s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio;
97 s3c_hsmmc1_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card; 137 s3c_hsmmc1_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card;
98} 138}
99#else 139#else
diff --git a/arch/arm/plat-s3c/include/plat/udc-hs.h b/arch/arm/plat-s3c/include/plat/udc-hs.h
new file mode 100644
index 000000000000..dd04db043109
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/udc-hs.h
@@ -0,0 +1,29 @@
1/* arch/arm/plat-s3c/include/plat/udc-hs.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C USB2.0 High-speed / OtG platform information
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15enum s3c_hostg_dmamode {
16 S3C_HSOTG_DMA_NONE, /* do not use DMA at-all */
17 S3C_HSOTG_DMA_ONLY, /* always use DMA */
18 S3C_HSOTG_DMA_DRV, /* DMA is chosen by driver */
19};
20
21/**
22 * struct s3c_hsotg_plat - platform data for high-speed otg/udc
23 * @dma: Whether to use DMA or not.
24 * @is_osc: The clock source is an oscillator, not a crystal
25 */
26struct s3c_hsotg_plat {
27 enum s3c_hostg_dmamode dma;
28 unsigned int is_osc : 1;
29};
diff --git a/arch/arm/plat-s3c/include/plat/watchdog-reset.h b/arch/arm/plat-s3c/include/plat/watchdog-reset.h
new file mode 100644
index 000000000000..54b762acb5a0
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/watchdog-reset.h
@@ -0,0 +1,49 @@
1/* arch/arm/plat-s3c/include/plat/watchdog-reset.h
2 *
3 * Copyright (c) 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 - System define for arch_reset() function
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <plat/regs-watchdog.h>
14#include <mach/map.h>
15
16#include <linux/clk.h>
17#include <linux/err.h>
18#include <linux/io.h>
19
20static inline void arch_wdt_reset(void)
21{
22 struct clk *wdtclk;
23
24 printk("arch_reset: attempting watchdog reset\n");
25
26 __raw_writel(0, S3C2410_WTCON); /* disable watchdog, to be safe */
27
28 wdtclk = clk_get(NULL, "watchdog");
29 if (!IS_ERR(wdtclk)) {
30 clk_enable(wdtclk);
31 } else
32 printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__);
33
34 /* put initial values into count and data */
35 __raw_writel(0x80, S3C2410_WTCNT);
36 __raw_writel(0x80, S3C2410_WTDAT);
37
38 /* set the watchdog to go and reset... */
39 __raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN |
40 S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON);
41
42 /* wait for reset to assert... */
43 mdelay(500);
44
45 printk(KERN_ERR "Watchdog reset failed to assert reset\n");
46
47 /* delay to allow the serial port to show the message */
48 mdelay(50);
49}
diff --git a/arch/arm/plat-s3c/pm-gpio.c b/arch/arm/plat-s3c/pm-gpio.c
new file mode 100644
index 000000000000..cfd326a8b693
--- /dev/null
+++ b/arch/arm/plat-s3c/pm-gpio.c
@@ -0,0 +1,380 @@
1
2/* linux/arch/arm/plat-s3c/pm-gpio.c
3 *
4 * Copyright 2008 Openmoko, Inc.
5 * Copyright 2008 Simtec Electronics
6 * Ben Dooks <ben@simtec.co.uk>
7 * http://armlinux.simtec.co.uk/
8 *
9 * S3C series GPIO PM code
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14*/
15
16#include <linux/kernel.h>
17#include <linux/sysdev.h>
18#include <linux/init.h>
19#include <linux/io.h>
20#include <linux/gpio.h>
21
22#include <mach/gpio-core.h>
23#include <plat/pm.h>
24
25/* PM GPIO helpers */
26
27#define OFFS_CON (0x00)
28#define OFFS_DAT (0x04)
29#define OFFS_UP (0x08)
30
31static void s3c_gpio_pm_1bit_save(struct s3c_gpio_chip *chip)
32{
33 chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON);
34 chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT);
35}
36
37static void s3c_gpio_pm_1bit_resume(struct s3c_gpio_chip *chip)
38{
39 void __iomem *base = chip->base;
40 u32 old_gpcon = __raw_readl(base + OFFS_CON);
41 u32 old_gpdat = __raw_readl(base + OFFS_DAT);
42 u32 gps_gpcon = chip->pm_save[0];
43 u32 gps_gpdat = chip->pm_save[1];
44 u32 gpcon;
45
46 /* GPACON only has one bit per control / data and no PULLUPs.
47 * GPACON[x] = 0 => Output, 1 => SFN */
48
49 /* first set all SFN bits to SFN */
50
51 gpcon = old_gpcon | gps_gpcon;
52 __raw_writel(gpcon, base + OFFS_CON);
53
54 /* now set all the other bits */
55
56 __raw_writel(gps_gpdat, base + OFFS_DAT);
57 __raw_writel(gps_gpcon, base + OFFS_CON);
58
59 S3C_PMDBG("%s: CON %08x => %08x, DAT %08x => %08x\n",
60 chip->chip.label, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
61}
62
63struct s3c_gpio_pm s3c_gpio_pm_1bit = {
64 .save = s3c_gpio_pm_1bit_save,
65 .resume = s3c_gpio_pm_1bit_resume,
66};
67
68static void s3c_gpio_pm_2bit_save(struct s3c_gpio_chip *chip)
69{
70 chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON);
71 chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT);
72 chip->pm_save[2] = __raw_readl(chip->base + OFFS_UP);
73}
74
75/* Test whether the given masked+shifted bits of an GPIO configuration
76 * are one of the SFN (special function) modes. */
77
78static inline int is_sfn(unsigned long con)
79{
80 return con >= 2;
81}
82
83/* Test if the given masked+shifted GPIO configuration is an input */
84
85static inline int is_in(unsigned long con)
86{
87 return con == 0;
88}
89
90/* Test if the given masked+shifted GPIO configuration is an output */
91
92static inline int is_out(unsigned long con)
93{
94 return con == 1;
95}
96
97/**
98 * s3c_gpio_pm_2bit_resume() - restore the given GPIO bank
99 * @chip: The chip information to resume.
100 *
101 * Restore one of the GPIO banks that was saved during suspend. This is
102 * not as simple as once thought, due to the possibility of glitches
103 * from the order that the CON and DAT registers are set in.
104 *
105 * The three states the pin can be are {IN,OUT,SFN} which gives us 9
106 * combinations of changes to check. Three of these, if the pin stays
107 * in the same configuration can be discounted. This leaves us with
108 * the following:
109 *
110 * { IN => OUT } Change DAT first
111 * { IN => SFN } Change CON first
112 * { OUT => SFN } Change CON first, so new data will not glitch
113 * { OUT => IN } Change CON first, so new data will not glitch
114 * { SFN => IN } Change CON first
115 * { SFN => OUT } Change DAT first, so new data will not glitch [1]
116 *
117 * We do not currently deal with the UP registers as these control
118 * weak resistors, so a small delay in change should not need to bring
119 * these into the calculations.
120 *
121 * [1] this assumes that writing to a pin DAT whilst in SFN will set the
122 * state for when it is next output.
123 */
124static void s3c_gpio_pm_2bit_resume(struct s3c_gpio_chip *chip)
125{
126 void __iomem *base = chip->base;
127 u32 old_gpcon = __raw_readl(base + OFFS_CON);
128 u32 old_gpdat = __raw_readl(base + OFFS_DAT);
129 u32 gps_gpcon = chip->pm_save[0];
130 u32 gps_gpdat = chip->pm_save[1];
131 u32 gpcon, old, new, mask;
132 u32 change_mask = 0x0;
133 int nr;
134
135 /* restore GPIO pull-up settings */
136 __raw_writel(chip->pm_save[2], base + OFFS_UP);
137
138 /* Create a change_mask of all the items that need to have
139 * their CON value changed before their DAT value, so that
140 * we minimise the work between the two settings.
141 */
142
143 for (nr = 0, mask = 0x03; nr < 32; nr += 2, mask <<= 2) {
144 old = (old_gpcon & mask) >> nr;
145 new = (gps_gpcon & mask) >> nr;
146
147 /* If there is no change, then skip */
148
149 if (old == new)
150 continue;
151
152 /* If both are special function, then skip */
153
154 if (is_sfn(old) && is_sfn(new))
155 continue;
156
157 /* Change is IN => OUT, do not change now */
158
159 if (is_in(old) && is_out(new))
160 continue;
161
162 /* Change is SFN => OUT, do not change now */
163
164 if (is_sfn(old) && is_out(new))
165 continue;
166
167 /* We should now be at the case of IN=>SFN,
168 * OUT=>SFN, OUT=>IN, SFN=>IN. */
169
170 change_mask |= mask;
171 }
172
173
174 /* Write the new CON settings */
175
176 gpcon = old_gpcon & ~change_mask;
177 gpcon |= gps_gpcon & change_mask;
178
179 __raw_writel(gpcon, base + OFFS_CON);
180
181 /* Now change any items that require DAT,CON */
182
183 __raw_writel(gps_gpdat, base + OFFS_DAT);
184 __raw_writel(gps_gpcon, base + OFFS_CON);
185
186 S3C_PMDBG("%s: CON %08x => %08x, DAT %08x => %08x\n",
187 chip->chip.label, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
188}
189
190struct s3c_gpio_pm s3c_gpio_pm_2bit = {
191 .save = s3c_gpio_pm_2bit_save,
192 .resume = s3c_gpio_pm_2bit_resume,
193};
194
195#ifdef CONFIG_ARCH_S3C64XX
196static void s3c_gpio_pm_4bit_save(struct s3c_gpio_chip *chip)
197{
198 chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON);
199 chip->pm_save[2] = __raw_readl(chip->base + OFFS_DAT);
200 chip->pm_save[3] = __raw_readl(chip->base + OFFS_UP);
201
202 if (chip->chip.ngpio > 8)
203 chip->pm_save[0] = __raw_readl(chip->base - 4);
204}
205
206static u32 s3c_gpio_pm_4bit_mask(u32 old_gpcon, u32 gps_gpcon)
207{
208 u32 old, new, mask;
209 u32 change_mask = 0x0;
210 int nr;
211
212 for (nr = 0, mask = 0x0f; nr < 16; nr += 4, mask <<= 4) {
213 old = (old_gpcon & mask) >> nr;
214 new = (gps_gpcon & mask) >> nr;
215
216 /* If there is no change, then skip */
217
218 if (old == new)
219 continue;
220
221 /* If both are special function, then skip */
222
223 if (is_sfn(old) && is_sfn(new))
224 continue;
225
226 /* Change is IN => OUT, do not change now */
227
228 if (is_in(old) && is_out(new))
229 continue;
230
231 /* Change is SFN => OUT, do not change now */
232
233 if (is_sfn(old) && is_out(new))
234 continue;
235
236 /* We should now be at the case of IN=>SFN,
237 * OUT=>SFN, OUT=>IN, SFN=>IN. */
238
239 change_mask |= mask;
240 }
241
242 return change_mask;
243}
244
245static void s3c_gpio_pm_4bit_con(struct s3c_gpio_chip *chip, int index)
246{
247 void __iomem *con = chip->base + (index * 4);
248 u32 old_gpcon = __raw_readl(con);
249 u32 gps_gpcon = chip->pm_save[index + 1];
250 u32 gpcon, mask;
251
252 mask = s3c_gpio_pm_4bit_mask(old_gpcon, gps_gpcon);
253
254 gpcon = old_gpcon & ~mask;
255 gpcon |= gps_gpcon & mask;
256
257 __raw_writel(gpcon, con);
258}
259
260static void s3c_gpio_pm_4bit_resume(struct s3c_gpio_chip *chip)
261{
262 void __iomem *base = chip->base;
263 u32 old_gpcon[2];
264 u32 old_gpdat = __raw_readl(base + OFFS_DAT);
265 u32 gps_gpdat = chip->pm_save[2];
266
267 /* First, modify the CON settings */
268
269 old_gpcon[0] = 0;
270 old_gpcon[1] = __raw_readl(base + OFFS_CON);
271
272 s3c_gpio_pm_4bit_con(chip, 0);
273 if (chip->chip.ngpio > 8) {
274 old_gpcon[0] = __raw_readl(base - 4);
275 s3c_gpio_pm_4bit_con(chip, -1);
276 }
277
278 /* Now change the configurations that require DAT,CON */
279
280 __raw_writel(chip->pm_save[2], base + OFFS_DAT);
281 __raw_writel(chip->pm_save[1], base + OFFS_CON);
282 if (chip->chip.ngpio > 8)
283 __raw_writel(chip->pm_save[0], base - 4);
284
285 __raw_writel(chip->pm_save[2], base + OFFS_DAT);
286 __raw_writel(chip->pm_save[3], base + OFFS_UP);
287
288 if (chip->chip.ngpio > 8) {
289 S3C_PMDBG("%s: CON4 %08x,%08x => %08x,%08x, DAT %08x => %08x\n",
290 chip->chip.label, old_gpcon[0], old_gpcon[1],
291 __raw_readl(base - 4),
292 __raw_readl(base + OFFS_CON),
293 old_gpdat, gps_gpdat);
294 } else
295 S3C_PMDBG("%s: CON4 %08x => %08x, DAT %08x => %08x\n",
296 chip->chip.label, old_gpcon[1],
297 __raw_readl(base + OFFS_CON),
298 old_gpdat, gps_gpdat);
299}
300
301struct s3c_gpio_pm s3c_gpio_pm_4bit = {
302 .save = s3c_gpio_pm_4bit_save,
303 .resume = s3c_gpio_pm_4bit_resume,
304};
305#endif /* CONFIG_ARCH_S3C64XX */
306
307/**
308 * s3c_pm_save_gpio() - save gpio chip data for suspend
309 * @ourchip: The chip for suspend.
310 */
311static void s3c_pm_save_gpio(struct s3c_gpio_chip *ourchip)
312{
313 struct s3c_gpio_pm *pm = ourchip->pm;
314
315 if (pm == NULL || pm->save == NULL)
316 S3C_PMDBG("%s: no pm for %s\n", __func__, ourchip->chip.label);
317 else
318 pm->save(ourchip);
319}
320
321/**
322 * s3c_pm_save_gpios() - Save the state of the GPIO banks.
323 *
324 * For all the GPIO banks, save the state of each one ready for going
325 * into a suspend mode.
326 */
327void s3c_pm_save_gpios(void)
328{
329 struct s3c_gpio_chip *ourchip;
330 unsigned int gpio_nr;
331
332 for (gpio_nr = 0; gpio_nr < S3C_GPIO_END; gpio_nr++) {
333 ourchip = s3c_gpiolib_getchip(gpio_nr);
334 if (!ourchip)
335 continue;
336
337 s3c_pm_save_gpio(ourchip);
338
339 S3C_PMDBG("%s: save %08x,%08x,%08x,%08x\n",
340 ourchip->chip.label,
341 ourchip->pm_save[0],
342 ourchip->pm_save[1],
343 ourchip->pm_save[2],
344 ourchip->pm_save[3]);
345
346 gpio_nr += ourchip->chip.ngpio;
347 gpio_nr += CONFIG_S3C_GPIO_SPACE;
348 }
349}
350
351/**
352 * s3c_pm_resume_gpio() - restore gpio chip data after suspend
353 * @ourchip: The suspended chip.
354 */
355static void s3c_pm_resume_gpio(struct s3c_gpio_chip *ourchip)
356{
357 struct s3c_gpio_pm *pm = ourchip->pm;
358
359 if (pm == NULL || pm->resume == NULL)
360 S3C_PMDBG("%s: no pm for %s\n", __func__, ourchip->chip.label);
361 else
362 pm->resume(ourchip);
363}
364
365void s3c_pm_restore_gpios(void)
366{
367 struct s3c_gpio_chip *ourchip;
368 unsigned int gpio_nr;
369
370 for (gpio_nr = 0; gpio_nr < S3C_GPIO_END; gpio_nr++) {
371 ourchip = s3c_gpiolib_getchip(gpio_nr);
372 if (!ourchip)
373 continue;
374
375 s3c_pm_resume_gpio(ourchip);
376
377 gpio_nr += ourchip->chip.ngpio;
378 gpio_nr += CONFIG_S3C_GPIO_SPACE;
379 }
380}
diff --git a/arch/arm/plat-s3c/pm.c b/arch/arm/plat-s3c/pm.c
index 061182ca66e3..8d97db2c7a0d 100644
--- a/arch/arm/plat-s3c/pm.c
+++ b/arch/arm/plat-s3c/pm.c
@@ -21,11 +21,10 @@
21 21
22#include <asm/cacheflush.h> 22#include <asm/cacheflush.h>
23#include <mach/hardware.h> 23#include <mach/hardware.h>
24#include <mach/map.h>
24 25
25#include <plat/regs-serial.h> 26#include <plat/regs-serial.h>
26#include <mach/regs-clock.h> 27#include <mach/regs-clock.h>
27#include <mach/regs-gpio.h>
28#include <mach/regs-mem.h>
29#include <mach/regs-irq.h> 28#include <mach/regs-irq.h>
30#include <asm/irq.h> 29#include <asm/irq.h>
31 30
@@ -70,6 +69,8 @@ static inline void s3c_pm_debug_init(void)
70 69
71/* Save the UART configurations if we are configured for debug. */ 70/* Save the UART configurations if we are configured for debug. */
72 71
72unsigned char pm_uart_udivslot;
73
73#ifdef CONFIG_S3C2410_PM_DEBUG 74#ifdef CONFIG_S3C2410_PM_DEBUG
74 75
75struct pm_uart_save uart_save[CONFIG_SERIAL_SAMSUNG_UARTS]; 76struct pm_uart_save uart_save[CONFIG_SERIAL_SAMSUNG_UARTS];
@@ -83,6 +84,12 @@ static void s3c_pm_save_uart(unsigned int uart, struct pm_uart_save *save)
83 save->ufcon = __raw_readl(regs + S3C2410_UFCON); 84 save->ufcon = __raw_readl(regs + S3C2410_UFCON);
84 save->umcon = __raw_readl(regs + S3C2410_UMCON); 85 save->umcon = __raw_readl(regs + S3C2410_UMCON);
85 save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV); 86 save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV);
87
88 if (pm_uart_udivslot)
89 save->udivslot = __raw_readl(regs + S3C2443_DIVSLOT);
90
91 S3C_PMDBG("UART[%d]: ULCON=%04x, UCON=%04x, UFCON=%04x, UBRDIV=%04x\n",
92 uart, save->ulcon, save->ucon, save->ufcon, save->ubrdiv);
86} 93}
87 94
88static void s3c_pm_save_uarts(void) 95static void s3c_pm_save_uarts(void)
@@ -98,11 +105,16 @@ static void s3c_pm_restore_uart(unsigned int uart, struct pm_uart_save *save)
98{ 105{
99 void __iomem *regs = S3C_VA_UARTx(uart); 106 void __iomem *regs = S3C_VA_UARTx(uart);
100 107
108 s3c_pm_arch_update_uart(regs, save);
109
101 __raw_writel(save->ulcon, regs + S3C2410_ULCON); 110 __raw_writel(save->ulcon, regs + S3C2410_ULCON);
102 __raw_writel(save->ucon, regs + S3C2410_UCON); 111 __raw_writel(save->ucon, regs + S3C2410_UCON);
103 __raw_writel(save->ufcon, regs + S3C2410_UFCON); 112 __raw_writel(save->ufcon, regs + S3C2410_UFCON);
104 __raw_writel(save->umcon, regs + S3C2410_UMCON); 113 __raw_writel(save->umcon, regs + S3C2410_UMCON);
105 __raw_writel(save->ubrdiv, regs + S3C2410_UBRDIV); 114 __raw_writel(save->ubrdiv, regs + S3C2410_UBRDIV);
115
116 if (pm_uart_udivslot)
117 __raw_writel(save->udivslot, regs + S3C2443_DIVSLOT);
106} 118}
107 119
108static void s3c_pm_restore_uarts(void) 120static void s3c_pm_restore_uarts(void)
@@ -313,6 +325,9 @@ static int s3c_pm_enter(suspend_state_t state)
313 325
314 S3C_PMDBG("%s: post sleep, preparing to return\n", __func__); 326 S3C_PMDBG("%s: post sleep, preparing to return\n", __func__);
315 327
328 /* LEDs should now be 1110 */
329 s3c_pm_debug_smdkled(1 << 1, 0);
330
316 s3c_pm_check_restore(); 331 s3c_pm_check_restore();
317 332
318 /* ok, let's return from sleep */ 333 /* ok, let's return from sleep */
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig
index 2c8a2f5d75ff..5b0bc914f58e 100644
--- a/arch/arm/plat-s3c24xx/Kconfig
+++ b/arch/arm/plat-s3c24xx/Kconfig
@@ -71,6 +71,7 @@ config PM_SIMTEC
71config S3C2410_DMA 71config S3C2410_DMA
72 bool "S3C2410 DMA support" 72 bool "S3C2410 DMA support"
73 depends on ARCH_S3C2410 73 depends on ARCH_S3C2410
74 select S3C_DMA
74 help 75 help
75 S3C2410 DMA support. This is needed for drivers like sound which 76 S3C2410 DMA support. This is needed for drivers like sound which
76 use the S3C2410's DMA system to move data to and from the 77 use the S3C2410's DMA system to move data to and from the
diff --git a/arch/arm/plat-s3c24xx/adc.c b/arch/arm/plat-s3c24xx/adc.c
index 91adfa71c172..ee1baf11ad9e 100644
--- a/arch/arm/plat-s3c24xx/adc.c
+++ b/arch/arm/plat-s3c24xx/adc.c
@@ -45,7 +45,8 @@ struct s3c_adc_client {
45 unsigned char channel; 45 unsigned char channel;
46 46
47 void (*select_cb)(unsigned selected); 47 void (*select_cb)(unsigned selected);
48 void (*convert_cb)(unsigned val1, unsigned val2); 48 void (*convert_cb)(unsigned val1, unsigned val2,
49 unsigned *samples_left);
49}; 50};
50 51
51struct adc_device { 52struct adc_device {
@@ -158,7 +159,8 @@ static void s3c_adc_default_select(unsigned select)
158 159
159struct s3c_adc_client *s3c_adc_register(struct platform_device *pdev, 160struct s3c_adc_client *s3c_adc_register(struct platform_device *pdev,
160 void (*select)(unsigned int selected), 161 void (*select)(unsigned int selected),
161 void (*conv)(unsigned d0, unsigned d1), 162 void (*conv)(unsigned d0, unsigned d1,
163 unsigned *samples_left),
162 unsigned int is_ts) 164 unsigned int is_ts)
163{ 165{
164 struct s3c_adc_client *client; 166 struct s3c_adc_client *client;
@@ -227,9 +229,10 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw)
227 data1 = readl(adc->regs + S3C2410_ADCDAT1); 229 data1 = readl(adc->regs + S3C2410_ADCDAT1);
228 adc_dbg(adc, "read %d: 0x%04x, 0x%04x\n", client->nr_samples, data0, data1); 230 adc_dbg(adc, "read %d: 0x%04x, 0x%04x\n", client->nr_samples, data0, data1);
229 231
230 (client->convert_cb)(data0 & 0x3ff, data1 & 0x3ff); 232 client->nr_samples--;
233 (client->convert_cb)(data0 & 0x3ff, data1 & 0x3ff, &client->nr_samples);
231 234
232 if (--client->nr_samples > 0) { 235 if (client->nr_samples > 0) {
233 /* fire another conversion for this */ 236 /* fire another conversion for this */
234 237
235 client->select_cb(1); 238 client->select_cb(1);
diff --git a/arch/arm/plat-s3c24xx/common-smdk.c b/arch/arm/plat-s3c24xx/common-smdk.c
index 1a8347cec20a..aa119863c5ce 100644
--- a/arch/arm/plat-s3c24xx/common-smdk.c
+++ b/arch/arm/plat-s3c24xx/common-smdk.c
@@ -18,6 +18,7 @@
18#include <linux/list.h> 18#include <linux/list.h>
19#include <linux/timer.h> 19#include <linux/timer.h>
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/gpio.h>
21#include <linux/sysdev.h> 22#include <linux/sysdev.h>
22#include <linux/platform_device.h> 23#include <linux/platform_device.h>
23 24
@@ -47,27 +48,27 @@
47/* LED devices */ 48/* LED devices */
48 49
49static struct s3c24xx_led_platdata smdk_pdata_led4 = { 50static struct s3c24xx_led_platdata smdk_pdata_led4 = {
50 .gpio = S3C2410_GPF4, 51 .gpio = S3C2410_GPF(4),
51 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, 52 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
52 .name = "led4", 53 .name = "led4",
53 .def_trigger = "timer", 54 .def_trigger = "timer",
54}; 55};
55 56
56static struct s3c24xx_led_platdata smdk_pdata_led5 = { 57static struct s3c24xx_led_platdata smdk_pdata_led5 = {
57 .gpio = S3C2410_GPF5, 58 .gpio = S3C2410_GPF(5),
58 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, 59 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
59 .name = "led5", 60 .name = "led5",
60 .def_trigger = "nand-disk", 61 .def_trigger = "nand-disk",
61}; 62};
62 63
63static struct s3c24xx_led_platdata smdk_pdata_led6 = { 64static struct s3c24xx_led_platdata smdk_pdata_led6 = {
64 .gpio = S3C2410_GPF6, 65 .gpio = S3C2410_GPF(6),
65 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, 66 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
66 .name = "led6", 67 .name = "led6",
67}; 68};
68 69
69static struct s3c24xx_led_platdata smdk_pdata_led7 = { 70static struct s3c24xx_led_platdata smdk_pdata_led7 = {
70 .gpio = S3C2410_GPF7, 71 .gpio = S3C2410_GPF(7),
71 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, 72 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
72 .name = "led7", 73 .name = "led7",
73}; 74};
@@ -184,15 +185,15 @@ void __init smdk_machine_init(void)
184{ 185{
185 /* Configure the LEDs (even if we have no LED support)*/ 186 /* Configure the LEDs (even if we have no LED support)*/
186 187
187 s3c2410_gpio_cfgpin(S3C2410_GPF4, S3C2410_GPF4_OUTP); 188 s3c2410_gpio_cfgpin(S3C2410_GPF(4), S3C2410_GPIO_OUTPUT);
188 s3c2410_gpio_cfgpin(S3C2410_GPF5, S3C2410_GPF5_OUTP); 189 s3c2410_gpio_cfgpin(S3C2410_GPF(5), S3C2410_GPIO_OUTPUT);
189 s3c2410_gpio_cfgpin(S3C2410_GPF6, S3C2410_GPF6_OUTP); 190 s3c2410_gpio_cfgpin(S3C2410_GPF(6), S3C2410_GPIO_OUTPUT);
190 s3c2410_gpio_cfgpin(S3C2410_GPF7, S3C2410_GPF7_OUTP); 191 s3c2410_gpio_cfgpin(S3C2410_GPF(7), S3C2410_GPIO_OUTPUT);
191 192
192 s3c2410_gpio_setpin(S3C2410_GPF4, 1); 193 s3c2410_gpio_setpin(S3C2410_GPF(4), 1);
193 s3c2410_gpio_setpin(S3C2410_GPF5, 1); 194 s3c2410_gpio_setpin(S3C2410_GPF(5), 1);
194 s3c2410_gpio_setpin(S3C2410_GPF6, 1); 195 s3c2410_gpio_setpin(S3C2410_GPF(6), 1);
195 s3c2410_gpio_setpin(S3C2410_GPF7, 1); 196 s3c2410_gpio_setpin(S3C2410_GPF(7), 1);
196 197
197 if (machine_is_smdk2443()) 198 if (machine_is_smdk2443())
198 smdk_nand_info.twrph0 = 50; 199 smdk_nand_info.twrph0 = 50;
diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c
index 16ac01d9b8ab..4eb378c89a39 100644
--- a/arch/arm/plat-s3c24xx/devs.c
+++ b/arch/arm/plat-s3c24xx/devs.c
@@ -136,36 +136,6 @@ struct platform_device *s3c24xx_uart_src[4] = {
136struct platform_device *s3c24xx_uart_devs[4] = { 136struct platform_device *s3c24xx_uart_devs[4] = {
137}; 137};
138 138
139/* USB Host Controller */
140
141static struct resource s3c_usb_resource[] = {
142 [0] = {
143 .start = S3C24XX_PA_USBHOST,
144 .end = S3C24XX_PA_USBHOST + S3C24XX_SZ_USBHOST - 1,
145 .flags = IORESOURCE_MEM,
146 },
147 [1] = {
148 .start = IRQ_USBH,
149 .end = IRQ_USBH,
150 .flags = IORESOURCE_IRQ,
151 }
152};
153
154static u64 s3c_device_usb_dmamask = 0xffffffffUL;
155
156struct platform_device s3c_device_usb = {
157 .name = "s3c2410-ohci",
158 .id = -1,
159 .num_resources = ARRAY_SIZE(s3c_usb_resource),
160 .resource = s3c_usb_resource,
161 .dev = {
162 .dma_mask = &s3c_device_usb_dmamask,
163 .coherent_dma_mask = 0xffffffffUL
164 }
165};
166
167EXPORT_SYMBOL(s3c_device_usb);
168
169/* LCD Controller */ 139/* LCD Controller */
170 140
171static struct resource s3c_lcd_resource[] = { 141static struct resource s3c_lcd_resource[] = {
diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c
index 07326f632361..196b19123653 100644
--- a/arch/arm/plat-s3c24xx/dma.c
+++ b/arch/arm/plat-s3c24xx/dma.c
@@ -31,10 +31,10 @@
31#include <asm/irq.h> 31#include <asm/irq.h>
32#include <mach/hardware.h> 32#include <mach/hardware.h>
33#include <mach/dma.h> 33#include <mach/dma.h>
34
35#include <mach/map.h> 34#include <mach/map.h>
36 35
37#include <plat/dma.h> 36#include <plat/dma-plat.h>
37#include <plat/regs-dma.h>
38 38
39/* io map for dma */ 39/* io map for dma */
40static void __iomem *dma_base; 40static void __iomem *dma_base;
@@ -44,8 +44,6 @@ static int dma_channels;
44 44
45static struct s3c24xx_dma_selection dma_sel; 45static struct s3c24xx_dma_selection dma_sel;
46 46
47/* dma channel state information */
48struct s3c2410_dma_chan s3c2410_chans[S3C2410_DMA_CHANNELS];
49 47
50/* debugging functions */ 48/* debugging functions */
51 49
@@ -135,21 +133,6 @@ dmadbg_showregs(const char *fname, int line, struct s3c2410_dma_chan *chan)
135#define dbg_showchan(chan) do { } while(0) 133#define dbg_showchan(chan) do { } while(0)
136#endif /* CONFIG_S3C2410_DMA_DEBUG */ 134#endif /* CONFIG_S3C2410_DMA_DEBUG */
137 135
138static struct s3c2410_dma_chan *dma_chan_map[DMACH_MAX];
139
140/* lookup_dma_channel
141 *
142 * change the dma channel number given into a real dma channel id
143*/
144
145static struct s3c2410_dma_chan *lookup_dma_channel(unsigned int channel)
146{
147 if (channel & DMACH_LOW_LEVEL)
148 return &s3c2410_chans[channel & ~DMACH_LOW_LEVEL];
149 else
150 return dma_chan_map[channel];
151}
152
153/* s3c2410_dma_stats_timeout 136/* s3c2410_dma_stats_timeout
154 * 137 *
155 * Update DMA stats from timeout info 138 * Update DMA stats from timeout info
@@ -214,8 +197,6 @@ s3c2410_dma_waitforload(struct s3c2410_dma_chan *chan, int line)
214 return 0; 197 return 0;
215} 198}
216 199
217
218
219/* s3c2410_dma_loadbuffer 200/* s3c2410_dma_loadbuffer
220 * 201 *
221 * load a buffer, and update the channel state 202 * load a buffer, and update the channel state
@@ -453,7 +434,7 @@ s3c2410_dma_canload(struct s3c2410_dma_chan *chan)
453int s3c2410_dma_enqueue(unsigned int channel, void *id, 434int s3c2410_dma_enqueue(unsigned int channel, void *id,
454 dma_addr_t data, int size) 435 dma_addr_t data, int size)
455{ 436{
456 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); 437 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
457 struct s3c2410_dma_buf *buf; 438 struct s3c2410_dma_buf *buf;
458 unsigned long flags; 439 unsigned long flags;
459 440
@@ -804,7 +785,7 @@ EXPORT_SYMBOL(s3c2410_dma_request);
804 785
805int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *client) 786int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *client)
806{ 787{
807 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); 788 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
808 unsigned long flags; 789 unsigned long flags;
809 790
810 if (chan == NULL) 791 if (chan == NULL)
@@ -836,7 +817,7 @@ int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *client)
836 chan->irq_claimed = 0; 817 chan->irq_claimed = 0;
837 818
838 if (!(channel & DMACH_LOW_LEVEL)) 819 if (!(channel & DMACH_LOW_LEVEL))
839 dma_chan_map[channel] = NULL; 820 s3c_dma_chan_map[channel] = NULL;
840 821
841 local_irq_restore(flags); 822 local_irq_restore(flags);
842 823
@@ -995,7 +976,7 @@ static int s3c2410_dma_started(struct s3c2410_dma_chan *chan)
995int 976int
996s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op) 977s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op)
997{ 978{
998 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); 979 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
999 980
1000 if (chan == NULL) 981 if (chan == NULL)
1001 return -EINVAL; 982 return -EINVAL;
@@ -1038,14 +1019,13 @@ EXPORT_SYMBOL(s3c2410_dma_ctrl);
1038/* s3c2410_dma_config 1019/* s3c2410_dma_config
1039 * 1020 *
1040 * xfersize: size of unit in bytes (1,2,4) 1021 * xfersize: size of unit in bytes (1,2,4)
1041 * dcon: base value of the DCONx register
1042*/ 1022*/
1043 1023
1044int s3c2410_dma_config(unsigned int channel, 1024int s3c2410_dma_config(unsigned int channel,
1045 int xferunit, 1025 int xferunit)
1046 int dcon)
1047{ 1026{
1048 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); 1027 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
1028 unsigned int dcon;
1049 1029
1050 pr_debug("%s: chan=%d, xfer_unit=%d, dcon=%08x\n", 1030 pr_debug("%s: chan=%d, xfer_unit=%d, dcon=%08x\n",
1051 __func__, channel, xferunit, dcon); 1031 __func__, channel, xferunit, dcon);
@@ -1055,10 +1035,33 @@ int s3c2410_dma_config(unsigned int channel,
1055 1035
1056 pr_debug("%s: Initial dcon is %08x\n", __func__, dcon); 1036 pr_debug("%s: Initial dcon is %08x\n", __func__, dcon);
1057 1037
1058 dcon |= chan->dcon & dma_sel.dcon_mask; 1038 dcon = chan->dcon & dma_sel.dcon_mask;
1059 1039
1060 pr_debug("%s: New dcon is %08x\n", __func__, dcon); 1040 pr_debug("%s: New dcon is %08x\n", __func__, dcon);
1061 1041
1042 switch (chan->req_ch) {
1043 case DMACH_I2S_IN:
1044 case DMACH_I2S_OUT:
1045 case DMACH_PCM_IN:
1046 case DMACH_PCM_OUT:
1047 case DMACH_MIC_IN:
1048 default:
1049 dcon |= S3C2410_DCON_HANDSHAKE;
1050 dcon |= S3C2410_DCON_SYNC_PCLK;
1051 break;
1052
1053 case DMACH_SDI:
1054 /* note, ensure if need HANDSHAKE or not */
1055 dcon |= S3C2410_DCON_SYNC_PCLK;
1056 break;
1057
1058 case DMACH_XD0:
1059 case DMACH_XD1:
1060 dcon |= S3C2410_DCON_HANDSHAKE;
1061 dcon |= S3C2410_DCON_SYNC_HCLK;
1062 break;
1063 }
1064
1062 switch (xferunit) { 1065 switch (xferunit) {
1063 case 1: 1066 case 1:
1064 dcon |= S3C2410_DCON_BYTE; 1067 dcon |= S3C2410_DCON_BYTE;
@@ -1090,58 +1093,6 @@ int s3c2410_dma_config(unsigned int channel,
1090 1093
1091EXPORT_SYMBOL(s3c2410_dma_config); 1094EXPORT_SYMBOL(s3c2410_dma_config);
1092 1095
1093int s3c2410_dma_setflags(unsigned int channel, unsigned int flags)
1094{
1095 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1096
1097 if (chan == NULL)
1098 return -EINVAL;
1099
1100 pr_debug("%s: chan=%p, flags=%08x\n", __func__, chan, flags);
1101
1102 chan->flags = flags;
1103
1104 return 0;
1105}
1106
1107EXPORT_SYMBOL(s3c2410_dma_setflags);
1108
1109
1110/* do we need to protect the settings of the fields from
1111 * irq?
1112*/
1113
1114int s3c2410_dma_set_opfn(unsigned int channel, s3c2410_dma_opfn_t rtn)
1115{
1116 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1117
1118 if (chan == NULL)
1119 return -EINVAL;
1120
1121 pr_debug("%s: chan=%p, op rtn=%p\n", __func__, chan, rtn);
1122
1123 chan->op_fn = rtn;
1124
1125 return 0;
1126}
1127
1128EXPORT_SYMBOL(s3c2410_dma_set_opfn);
1129
1130int s3c2410_dma_set_buffdone_fn(unsigned int channel, s3c2410_dma_cbfn_t rtn)
1131{
1132 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1133
1134 if (chan == NULL)
1135 return -EINVAL;
1136
1137 pr_debug("%s: chan=%p, callback rtn=%p\n", __func__, chan, rtn);
1138
1139 chan->callback_fn = rtn;
1140
1141 return 0;
1142}
1143
1144EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn);
1145 1096
1146/* s3c2410_dma_devconfig 1097/* s3c2410_dma_devconfig
1147 * 1098 *
@@ -1150,29 +1101,38 @@ EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn);
1150 * source: S3C2410_DMASRC_HW: source is hardware 1101 * source: S3C2410_DMASRC_HW: source is hardware
1151 * S3C2410_DMASRC_MEM: source is memory 1102 * S3C2410_DMASRC_MEM: source is memory
1152 * 1103 *
1153 * hwcfg: the value for xxxSTCn register,
1154 * bit 0: 0=increment pointer, 1=leave pointer
1155 * bit 1: 0=source is AHB, 1=source is APB
1156 *
1157 * devaddr: physical address of the source 1104 * devaddr: physical address of the source
1158*/ 1105*/
1159 1106
1160int s3c2410_dma_devconfig(int channel, 1107int s3c2410_dma_devconfig(int channel,
1161 enum s3c2410_dmasrc source, 1108 enum s3c2410_dmasrc source,
1162 int hwcfg,
1163 unsigned long devaddr) 1109 unsigned long devaddr)
1164{ 1110{
1165 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); 1111 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
1112 unsigned int hwcfg;
1166 1113
1167 if (chan == NULL) 1114 if (chan == NULL)
1168 return -EINVAL; 1115 return -EINVAL;
1169 1116
1170 pr_debug("%s: source=%d, hwcfg=%08x, devaddr=%08lx\n", 1117 pr_debug("%s: source=%d, devaddr=%08lx\n",
1171 __func__, (int)source, hwcfg, devaddr); 1118 __func__, (int)source, devaddr);
1172 1119
1173 chan->source = source; 1120 chan->source = source;
1174 chan->dev_addr = devaddr; 1121 chan->dev_addr = devaddr;
1175 chan->hw_cfg = hwcfg; 1122
1123 switch (chan->req_ch) {
1124 case DMACH_XD0:
1125 case DMACH_XD1:
1126 hwcfg = 0; /* AHB */
1127 break;
1128
1129 default:
1130 hwcfg = S3C2410_DISRCC_APB;
1131 }
1132
1133 /* always assume our peripheral desintation is a fixed
1134 * address in memory. */
1135 hwcfg |= S3C2410_DISRCC_INC;
1176 1136
1177 switch (source) { 1137 switch (source) {
1178 case S3C2410_DMASRC_HW: 1138 case S3C2410_DMASRC_HW:
@@ -1219,7 +1179,7 @@ EXPORT_SYMBOL(s3c2410_dma_devconfig);
1219 1179
1220int s3c2410_dma_getposition(unsigned int channel, dma_addr_t *src, dma_addr_t *dst) 1180int s3c2410_dma_getposition(unsigned int channel, dma_addr_t *src, dma_addr_t *dst)
1221{ 1181{
1222 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); 1182 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
1223 1183
1224 if (chan == NULL) 1184 if (chan == NULL)
1225 return -EINVAL; 1185 return -EINVAL;
@@ -1278,8 +1238,8 @@ static int s3c2410_dma_resume(struct sys_device *dev)
1278 1238
1279 printk(KERN_INFO "dma%d: restoring configuration\n", cp->number); 1239 printk(KERN_INFO "dma%d: restoring configuration\n", cp->number);
1280 1240
1281 s3c2410_dma_config(no, cp->xfer_unit, cp->dcon); 1241 s3c2410_dma_config(no, cp->xfer_unit);
1282 s3c2410_dma_devconfig(no, cp->source, cp->hw_cfg, cp->dev_addr); 1242 s3c2410_dma_devconfig(no, cp->source, cp->dev_addr);
1283 1243
1284 /* re-select the dma source for this channel */ 1244 /* re-select the dma source for this channel */
1285 1245
@@ -1476,7 +1436,8 @@ static struct s3c2410_dma_chan *s3c2410_dma_map_channel(int channel)
1476 found: 1436 found:
1477 dmach = &s3c2410_chans[ch]; 1437 dmach = &s3c2410_chans[ch];
1478 dmach->map = ch_map; 1438 dmach->map = ch_map;
1479 dma_chan_map[channel] = dmach; 1439 dmach->req_ch = channel;
1440 s3c_dma_chan_map[channel] = dmach;
1480 1441
1481 /* select the channel */ 1442 /* select the channel */
1482 1443
diff --git a/arch/arm/plat-s3c24xx/gpio.c b/arch/arm/plat-s3c24xx/gpio.c
index 4a899c279eb5..95df059b5a1d 100644
--- a/arch/arm/plat-s3c24xx/gpio.c
+++ b/arch/arm/plat-s3c24xx/gpio.c
@@ -183,35 +183,19 @@ EXPORT_SYMBOL(s3c2410_modify_misccr);
183 183
184int s3c2410_gpio_getirq(unsigned int pin) 184int s3c2410_gpio_getirq(unsigned int pin)
185{ 185{
186 if (pin < S3C2410_GPF0 || pin > S3C2410_GPG15) 186 if (pin < S3C2410_GPF(0) || pin > S3C2410_GPG(15))
187 return -1; /* not valid interrupts */ 187 return -EINVAL; /* not valid interrupts */
188 188
189 if (pin < S3C2410_GPG0 && pin > S3C2410_GPF7) 189 if (pin < S3C2410_GPG(0) && pin > S3C2410_GPF(7))
190 return -1; /* not valid pin */ 190 return -EINVAL; /* not valid pin */
191 191
192 if (pin < S3C2410_GPF4) 192 if (pin < S3C2410_GPF(4))
193 return (pin - S3C2410_GPF0) + IRQ_EINT0; 193 return (pin - S3C2410_GPF(0)) + IRQ_EINT0;
194 194
195 if (pin < S3C2410_GPG0) 195 if (pin < S3C2410_GPG(0))
196 return (pin - S3C2410_GPF4) + IRQ_EINT4; 196 return (pin - S3C2410_GPF(4)) + IRQ_EINT4;
197 197
198 return (pin - S3C2410_GPG0) + IRQ_EINT8; 198 return (pin - S3C2410_GPG(0)) + IRQ_EINT8;
199} 199}
200 200
201EXPORT_SYMBOL(s3c2410_gpio_getirq); 201EXPORT_SYMBOL(s3c2410_gpio_getirq);
202
203int s3c2410_gpio_irq2pin(unsigned int irq)
204{
205 if (irq >= IRQ_EINT0 && irq <= IRQ_EINT3)
206 return S3C2410_GPF0 + (irq - IRQ_EINT0);
207
208 if (irq >= IRQ_EINT4 && irq <= IRQ_EINT7)
209 return S3C2410_GPF4 + (irq - IRQ_EINT4);
210
211 if (irq >= IRQ_EINT8 && irq <= IRQ_EINT23)
212 return S3C2410_GPG0 + (irq - IRQ_EINT8);
213
214 return -EINVAL;
215}
216
217EXPORT_SYMBOL(s3c2410_gpio_irq2pin);
diff --git a/arch/arm/plat-s3c24xx/gpiolib.c b/arch/arm/plat-s3c24xx/gpiolib.c
index 5c0491bf738b..6d7a961d3269 100644
--- a/arch/arm/plat-s3c24xx/gpiolib.c
+++ b/arch/arm/plat-s3c24xx/gpiolib.c
@@ -15,6 +15,7 @@
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/module.h> 16#include <linux/module.h>
17#include <linux/interrupt.h> 17#include <linux/interrupt.h>
18#include <linux/sysdev.h>
18#include <linux/ioport.h> 19#include <linux/ioport.h>
19#include <linux/io.h> 20#include <linux/io.h>
20#include <linux/gpio.h> 21#include <linux/gpio.h>
@@ -22,6 +23,7 @@
22#include <mach/gpio-core.h> 23#include <mach/gpio-core.h>
23#include <mach/hardware.h> 24#include <mach/hardware.h>
24#include <asm/irq.h> 25#include <asm/irq.h>
26#include <plat/pm.h>
25 27
26#include <mach/regs-gpio.h> 28#include <mach/regs-gpio.h>
27 29
@@ -77,9 +79,10 @@ static int s3c24xx_gpiolib_bankg_toirq(struct gpio_chip *chip, unsigned offset)
77 79
78struct s3c_gpio_chip s3c24xx_gpios[] = { 80struct s3c_gpio_chip s3c24xx_gpios[] = {
79 [0] = { 81 [0] = {
80 .base = S3C24XX_GPIO_BASE(S3C2410_GPA0), 82 .base = S3C2410_GPACON,
83 .pm = __gpio_pm(&s3c_gpio_pm_1bit),
81 .chip = { 84 .chip = {
82 .base = S3C2410_GPA0, 85 .base = S3C2410_GPA(0),
83 .owner = THIS_MODULE, 86 .owner = THIS_MODULE,
84 .label = "GPIOA", 87 .label = "GPIOA",
85 .ngpio = 24, 88 .ngpio = 24,
@@ -88,45 +91,50 @@ struct s3c_gpio_chip s3c24xx_gpios[] = {
88 }, 91 },
89 }, 92 },
90 [1] = { 93 [1] = {
91 .base = S3C24XX_GPIO_BASE(S3C2410_GPB0), 94 .base = S3C2410_GPBCON,
95 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
92 .chip = { 96 .chip = {
93 .base = S3C2410_GPB0, 97 .base = S3C2410_GPB(0),
94 .owner = THIS_MODULE, 98 .owner = THIS_MODULE,
95 .label = "GPIOB", 99 .label = "GPIOB",
96 .ngpio = 16, 100 .ngpio = 16,
97 }, 101 },
98 }, 102 },
99 [2] = { 103 [2] = {
100 .base = S3C24XX_GPIO_BASE(S3C2410_GPC0), 104 .base = S3C2410_GPCCON,
105 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
101 .chip = { 106 .chip = {
102 .base = S3C2410_GPC0, 107 .base = S3C2410_GPC(0),
103 .owner = THIS_MODULE, 108 .owner = THIS_MODULE,
104 .label = "GPIOC", 109 .label = "GPIOC",
105 .ngpio = 16, 110 .ngpio = 16,
106 }, 111 },
107 }, 112 },
108 [3] = { 113 [3] = {
109 .base = S3C24XX_GPIO_BASE(S3C2410_GPD0), 114 .base = S3C2410_GPDCON,
115 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
110 .chip = { 116 .chip = {
111 .base = S3C2410_GPD0, 117 .base = S3C2410_GPD(0),
112 .owner = THIS_MODULE, 118 .owner = THIS_MODULE,
113 .label = "GPIOD", 119 .label = "GPIOD",
114 .ngpio = 16, 120 .ngpio = 16,
115 }, 121 },
116 }, 122 },
117 [4] = { 123 [4] = {
118 .base = S3C24XX_GPIO_BASE(S3C2410_GPE0), 124 .base = S3C2410_GPECON,
125 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
119 .chip = { 126 .chip = {
120 .base = S3C2410_GPE0, 127 .base = S3C2410_GPE(0),
121 .label = "GPIOE", 128 .label = "GPIOE",
122 .owner = THIS_MODULE, 129 .owner = THIS_MODULE,
123 .ngpio = 16, 130 .ngpio = 16,
124 }, 131 },
125 }, 132 },
126 [5] = { 133 [5] = {
127 .base = S3C24XX_GPIO_BASE(S3C2410_GPF0), 134 .base = S3C2410_GPFCON,
135 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
128 .chip = { 136 .chip = {
129 .base = S3C2410_GPF0, 137 .base = S3C2410_GPF(0),
130 .owner = THIS_MODULE, 138 .owner = THIS_MODULE,
131 .label = "GPIOF", 139 .label = "GPIOF",
132 .ngpio = 8, 140 .ngpio = 8,
@@ -134,14 +142,24 @@ struct s3c_gpio_chip s3c24xx_gpios[] = {
134 }, 142 },
135 }, 143 },
136 [6] = { 144 [6] = {
137 .base = S3C24XX_GPIO_BASE(S3C2410_GPG0), 145 .base = S3C2410_GPGCON,
146 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
138 .chip = { 147 .chip = {
139 .base = S3C2410_GPG0, 148 .base = S3C2410_GPG(0),
140 .owner = THIS_MODULE, 149 .owner = THIS_MODULE,
141 .label = "GPIOG", 150 .label = "GPIOG",
142 .ngpio = 10, 151 .ngpio = 16,
143 .to_irq = s3c24xx_gpiolib_bankg_toirq, 152 .to_irq = s3c24xx_gpiolib_bankg_toirq,
144 }, 153 },
154 }, {
155 .base = S3C2410_GPHCON,
156 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
157 .chip = {
158 .base = S3C2410_GPH(0),
159 .owner = THIS_MODULE,
160 .label = "GPIOH",
161 .ngpio = 11,
162 },
145 }, 163 },
146}; 164};
147 165
@@ -156,4 +174,4 @@ static __init int s3c24xx_gpiolib_init(void)
156 return 0; 174 return 0;
157} 175}
158 176
159arch_initcall(s3c24xx_gpiolib_init); 177core_initcall(s3c24xx_gpiolib_init);
diff --git a/arch/arm/plat-s3c24xx/include/plat/dma.h b/arch/arm/plat-s3c24xx/include/plat/dma-plat.h
index c78efe316fc8..9565ead1bc9b 100644
--- a/arch/arm/plat-s3c24xx/include/plat/dma.h
+++ b/arch/arm/plat-s3c24xx/include/plat/dma-plat.h
@@ -1,4 +1,4 @@
1/* linux/include/asm-arm/plat-s3c24xx/dma.h 1/* linux/arch/arm/plat-s3c24xx/include/plat/dma-plat.h
2 * 2 *
3 * Copyright (C) 2006 Simtec Electronics 3 * Copyright (C) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk> 4 * Ben Dooks <ben@simtec.co.uk>
@@ -10,8 +10,10 @@
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11*/ 11*/
12 12
13#include <plat/dma-core.h>
14
13extern struct sysdev_class dma_sysclass; 15extern struct sysdev_class dma_sysclass;
14extern struct s3c2410_dma_chan s3c2410_chans[S3C2410_DMA_CHANNELS]; 16extern struct s3c2410_dma_chan s3c2410_chans[S3C_DMA_CHANNELS];
15 17
16#define DMA_CH_VALID (1<<31) 18#define DMA_CH_VALID (1<<31)
17#define DMA_CH_NEVER (1<<30) 19#define DMA_CH_NEVER (1<<30)
@@ -31,8 +33,8 @@ struct s3c24xx_dma_map {
31 const char *name; 33 const char *name;
32 struct s3c24xx_dma_addr hw_addr; 34 struct s3c24xx_dma_addr hw_addr;
33 35
34 unsigned long channels[S3C2410_DMA_CHANNELS]; 36 unsigned long channels[S3C_DMA_CHANNELS];
35 unsigned long channels_rx[S3C2410_DMA_CHANNELS]; 37 unsigned long channels_rx[S3C_DMA_CHANNELS];
36}; 38};
37 39
38struct s3c24xx_dma_selection { 40struct s3c24xx_dma_selection {
@@ -58,7 +60,7 @@ extern int s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel);
58*/ 60*/
59 61
60struct s3c24xx_dma_order_ch { 62struct s3c24xx_dma_order_ch {
61 unsigned int list[S3C2410_DMA_CHANNELS]; /* list of channels */ 63 unsigned int list[S3C_DMA_CHANNELS]; /* list of channels */
62 unsigned int flags; /* flags */ 64 unsigned int flags; /* flags */
63}; 65};
64 66
diff --git a/arch/arm/plat-s3c24xx/include/plat/map.h b/arch/arm/plat-s3c24xx/include/plat/map.h
index eed8f78e7593..c4d133436fc7 100644
--- a/arch/arm/plat-s3c24xx/include/plat/map.h
+++ b/arch/arm/plat-s3c24xx/include/plat/map.h
@@ -58,7 +58,6 @@
58#define S3C24XX_SZ_SPI SZ_1M 58#define S3C24XX_SZ_SPI SZ_1M
59#define S3C24XX_SZ_SDI SZ_1M 59#define S3C24XX_SZ_SDI SZ_1M
60#define S3C24XX_SZ_NAND SZ_1M 60#define S3C24XX_SZ_NAND SZ_1M
61#define S3C24XX_SZ_USBHOST SZ_1M
62 61
63/* GPIO ports */ 62/* GPIO ports */
64 63
diff --git a/arch/arm/plat-s3c24xx/include/plat/pm-core.h b/arch/arm/plat-s3c24xx/include/plat/pm-core.h
index c75882113e04..fb45dd9adca5 100644
--- a/arch/arm/plat-s3c24xx/include/plat/pm-core.h
+++ b/arch/arm/plat-s3c24xx/include/plat/pm-core.h
@@ -57,3 +57,8 @@ static inline void s3c_pm_arch_show_resume_irqs(void)
57 s3c_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND), 57 s3c_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND),
58 s3c_irqwake_eintmask); 58 s3c_irqwake_eintmask);
59} 59}
60
61static inline void s3c_pm_arch_update_uart(void __iomem *regs,
62 struct pm_uart_save *save)
63{
64}
diff --git a/arch/arm/plat-s3c24xx/include/plat/regs-dma.h b/arch/arm/plat-s3c24xx/include/plat/regs-dma.h
new file mode 100644
index 000000000000..3bc0a216df97
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/include/plat/regs-dma.h
@@ -0,0 +1,145 @@
1/* arch/arm/mach-s3c2410/include/mach/dma.h
2 *
3 * Copyright (C) 2003,2004,2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Samsung S3C24XX DMA support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* DMA Register definitions */
14
15#define S3C2410_DMA_DISRC (0x00)
16#define S3C2410_DMA_DISRCC (0x04)
17#define S3C2410_DMA_DIDST (0x08)
18#define S3C2410_DMA_DIDSTC (0x0C)
19#define S3C2410_DMA_DCON (0x10)
20#define S3C2410_DMA_DSTAT (0x14)
21#define S3C2410_DMA_DCSRC (0x18)
22#define S3C2410_DMA_DCDST (0x1C)
23#define S3C2410_DMA_DMASKTRIG (0x20)
24#define S3C2412_DMA_DMAREQSEL (0x24)
25#define S3C2443_DMA_DMAREQSEL (0x24)
26
27#define S3C2410_DISRCC_INC (1<<0)
28#define S3C2410_DISRCC_APB (1<<1)
29
30#define S3C2410_DMASKTRIG_STOP (1<<2)
31#define S3C2410_DMASKTRIG_ON (1<<1)
32#define S3C2410_DMASKTRIG_SWTRIG (1<<0)
33
34#define S3C2410_DCON_DEMAND (0<<31)
35#define S3C2410_DCON_HANDSHAKE (1<<31)
36#define S3C2410_DCON_SYNC_PCLK (0<<30)
37#define S3C2410_DCON_SYNC_HCLK (1<<30)
38
39#define S3C2410_DCON_INTREQ (1<<29)
40
41#define S3C2410_DCON_CH0_XDREQ0 (0<<24)
42#define S3C2410_DCON_CH0_UART0 (1<<24)
43#define S3C2410_DCON_CH0_SDI (2<<24)
44#define S3C2410_DCON_CH0_TIMER (3<<24)
45#define S3C2410_DCON_CH0_USBEP1 (4<<24)
46
47#define S3C2410_DCON_CH1_XDREQ1 (0<<24)
48#define S3C2410_DCON_CH1_UART1 (1<<24)
49#define S3C2410_DCON_CH1_I2SSDI (2<<24)
50#define S3C2410_DCON_CH1_SPI (3<<24)
51#define S3C2410_DCON_CH1_USBEP2 (4<<24)
52
53#define S3C2410_DCON_CH2_I2SSDO (0<<24)
54#define S3C2410_DCON_CH2_I2SSDI (1<<24)
55#define S3C2410_DCON_CH2_SDI (2<<24)
56#define S3C2410_DCON_CH2_TIMER (3<<24)
57#define S3C2410_DCON_CH2_USBEP3 (4<<24)
58
59#define S3C2410_DCON_CH3_UART2 (0<<24)
60#define S3C2410_DCON_CH3_SDI (1<<24)
61#define S3C2410_DCON_CH3_SPI (2<<24)
62#define S3C2410_DCON_CH3_TIMER (3<<24)
63#define S3C2410_DCON_CH3_USBEP4 (4<<24)
64
65#define S3C2410_DCON_SRCSHIFT (24)
66#define S3C2410_DCON_SRCMASK (7<<24)
67
68#define S3C2410_DCON_BYTE (0<<20)
69#define S3C2410_DCON_HALFWORD (1<<20)
70#define S3C2410_DCON_WORD (2<<20)
71
72#define S3C2410_DCON_AUTORELOAD (0<<22)
73#define S3C2410_DCON_NORELOAD (1<<22)
74#define S3C2410_DCON_HWTRIG (1<<23)
75
76#ifdef CONFIG_CPU_S3C2440
77#define S3C2440_DIDSTC_CHKINT (1<<2)
78
79#define S3C2440_DCON_CH0_I2SSDO (5<<24)
80#define S3C2440_DCON_CH0_PCMIN (6<<24)
81
82#define S3C2440_DCON_CH1_PCMOUT (5<<24)
83#define S3C2440_DCON_CH1_SDI (6<<24)
84
85#define S3C2440_DCON_CH2_PCMIN (5<<24)
86#define S3C2440_DCON_CH2_MICIN (6<<24)
87
88#define S3C2440_DCON_CH3_MICIN (5<<24)
89#define S3C2440_DCON_CH3_PCMOUT (6<<24)
90#endif
91
92#ifdef CONFIG_CPU_S3C2412
93
94#define S3C2412_DMAREQSEL_SRC(x) ((x)<<1)
95
96#define S3C2412_DMAREQSEL_HW (1)
97
98#define S3C2412_DMAREQSEL_SPI0TX S3C2412_DMAREQSEL_SRC(0)
99#define S3C2412_DMAREQSEL_SPI0RX S3C2412_DMAREQSEL_SRC(1)
100#define S3C2412_DMAREQSEL_SPI1TX S3C2412_DMAREQSEL_SRC(2)
101#define S3C2412_DMAREQSEL_SPI1RX S3C2412_DMAREQSEL_SRC(3)
102#define S3C2412_DMAREQSEL_I2STX S3C2412_DMAREQSEL_SRC(4)
103#define S3C2412_DMAREQSEL_I2SRX S3C2412_DMAREQSEL_SRC(5)
104#define S3C2412_DMAREQSEL_TIMER S3C2412_DMAREQSEL_SRC(9)
105#define S3C2412_DMAREQSEL_SDI S3C2412_DMAREQSEL_SRC(10)
106#define S3C2412_DMAREQSEL_USBEP1 S3C2412_DMAREQSEL_SRC(13)
107#define S3C2412_DMAREQSEL_USBEP2 S3C2412_DMAREQSEL_SRC(14)
108#define S3C2412_DMAREQSEL_USBEP3 S3C2412_DMAREQSEL_SRC(15)
109#define S3C2412_DMAREQSEL_USBEP4 S3C2412_DMAREQSEL_SRC(16)
110#define S3C2412_DMAREQSEL_XDREQ0 S3C2412_DMAREQSEL_SRC(17)
111#define S3C2412_DMAREQSEL_XDREQ1 S3C2412_DMAREQSEL_SRC(18)
112#define S3C2412_DMAREQSEL_UART0_0 S3C2412_DMAREQSEL_SRC(19)
113#define S3C2412_DMAREQSEL_UART0_1 S3C2412_DMAREQSEL_SRC(20)
114#define S3C2412_DMAREQSEL_UART1_0 S3C2412_DMAREQSEL_SRC(21)
115#define S3C2412_DMAREQSEL_UART1_1 S3C2412_DMAREQSEL_SRC(22)
116#define S3C2412_DMAREQSEL_UART2_0 S3C2412_DMAREQSEL_SRC(23)
117#define S3C2412_DMAREQSEL_UART2_1 S3C2412_DMAREQSEL_SRC(24)
118
119#endif
120
121#define S3C2443_DMAREQSEL_SRC(x) ((x)<<1)
122
123#define S3C2443_DMAREQSEL_HW (1)
124
125#define S3C2443_DMAREQSEL_SPI0TX S3C2443_DMAREQSEL_SRC(0)
126#define S3C2443_DMAREQSEL_SPI0RX S3C2443_DMAREQSEL_SRC(1)
127#define S3C2443_DMAREQSEL_SPI1TX S3C2443_DMAREQSEL_SRC(2)
128#define S3C2443_DMAREQSEL_SPI1RX S3C2443_DMAREQSEL_SRC(3)
129#define S3C2443_DMAREQSEL_I2STX S3C2443_DMAREQSEL_SRC(4)
130#define S3C2443_DMAREQSEL_I2SRX S3C2443_DMAREQSEL_SRC(5)
131#define S3C2443_DMAREQSEL_TIMER S3C2443_DMAREQSEL_SRC(9)
132#define S3C2443_DMAREQSEL_SDI S3C2443_DMAREQSEL_SRC(10)
133#define S3C2443_DMAREQSEL_XDREQ0 S3C2443_DMAREQSEL_SRC(17)
134#define S3C2443_DMAREQSEL_XDREQ1 S3C2443_DMAREQSEL_SRC(18)
135#define S3C2443_DMAREQSEL_UART0_0 S3C2443_DMAREQSEL_SRC(19)
136#define S3C2443_DMAREQSEL_UART0_1 S3C2443_DMAREQSEL_SRC(20)
137#define S3C2443_DMAREQSEL_UART1_0 S3C2443_DMAREQSEL_SRC(21)
138#define S3C2443_DMAREQSEL_UART1_1 S3C2443_DMAREQSEL_SRC(22)
139#define S3C2443_DMAREQSEL_UART2_0 S3C2443_DMAREQSEL_SRC(23)
140#define S3C2443_DMAREQSEL_UART2_1 S3C2443_DMAREQSEL_SRC(24)
141#define S3C2443_DMAREQSEL_UART3_0 S3C2443_DMAREQSEL_SRC(25)
142#define S3C2443_DMAREQSEL_UART3_1 S3C2443_DMAREQSEL_SRC(26)
143#define S3C2443_DMAREQSEL_PCMOUT S3C2443_DMAREQSEL_SRC(27)
144#define S3C2443_DMAREQSEL_PCMIN S3C2443_DMAREQSEL_SRC(28)
145#define S3C2443_DMAREQSEL_MICIN S3C2443_DMAREQSEL_SRC(29)
diff --git a/arch/arm/plat-s3c24xx/pm.c b/arch/arm/plat-s3c24xx/pm.c
index 062a29339a91..56e5253ca02c 100644
--- a/arch/arm/plat-s3c24xx/pm.c
+++ b/arch/arm/plat-s3c24xx/pm.c
@@ -30,6 +30,7 @@
30#include <linux/suspend.h> 30#include <linux/suspend.h>
31#include <linux/errno.h> 31#include <linux/errno.h>
32#include <linux/time.h> 32#include <linux/time.h>
33#include <linux/gpio.h>
33#include <linux/interrupt.h> 34#include <linux/interrupt.h>
34#include <linux/serial_core.h> 35#include <linux/serial_core.h>
35#include <linux/io.h> 36#include <linux/io.h>
@@ -75,43 +76,10 @@ static struct sleep_save core_save[] = {
75 SAVE_ITEM(S3C2410_CLKSLOW), 76 SAVE_ITEM(S3C2410_CLKSLOW),
76}; 77};
77 78
78static struct gpio_sleep {
79 void __iomem *base;
80 unsigned int gpcon;
81 unsigned int gpdat;
82 unsigned int gpup;
83} gpio_save[] = {
84 [0] = {
85 .base = S3C2410_GPACON,
86 },
87 [1] = {
88 .base = S3C2410_GPBCON,
89 },
90 [2] = {
91 .base = S3C2410_GPCCON,
92 },
93 [3] = {
94 .base = S3C2410_GPDCON,
95 },
96 [4] = {
97 .base = S3C2410_GPECON,
98 },
99 [5] = {
100 .base = S3C2410_GPFCON,
101 },
102 [6] = {
103 .base = S3C2410_GPGCON,
104 },
105 [7] = {
106 .base = S3C2410_GPHCON,
107 },
108};
109
110static struct sleep_save misc_save[] = { 79static struct sleep_save misc_save[] = {
111 SAVE_ITEM(S3C2410_DCLKCON), 80 SAVE_ITEM(S3C2410_DCLKCON),
112}; 81};
113 82
114
115/* s3c_pm_check_resume_pin 83/* s3c_pm_check_resume_pin
116 * 84 *
117 * check to see if the pin is configured correctly for sleep mode, and 85 * check to see if the pin is configured correctly for sleep mode, and
@@ -156,195 +124,15 @@ void s3c_pm_configure_extint(void)
156 * and then configure it as an input if it is not 124 * and then configure it as an input if it is not
157 */ 125 */
158 126
159 for (pin = S3C2410_GPF0; pin <= S3C2410_GPF7; pin++) { 127 for (pin = S3C2410_GPF(0); pin <= S3C2410_GPF(7); pin++) {
160 s3c_pm_check_resume_pin(pin, pin - S3C2410_GPF0); 128 s3c_pm_check_resume_pin(pin, pin - S3C2410_GPF(0));
161 }
162
163 for (pin = S3C2410_GPG0; pin <= S3C2410_GPG7; pin++) {
164 s3c_pm_check_resume_pin(pin, (pin - S3C2410_GPG0)+8);
165 } 129 }
166}
167
168/* offsets for CON/DAT/UP registers */
169
170#define OFFS_CON (S3C2410_GPACON - S3C2410_GPACON)
171#define OFFS_DAT (S3C2410_GPADAT - S3C2410_GPACON)
172#define OFFS_UP (S3C2410_GPBUP - S3C2410_GPBCON)
173
174/* s3c_pm_save_gpios()
175 *
176 * Save the state of the GPIOs
177 */
178
179void s3c_pm_save_gpios(void)
180{
181 struct gpio_sleep *gps = gpio_save;
182 unsigned int gpio;
183
184 for (gpio = 0; gpio < ARRAY_SIZE(gpio_save); gpio++, gps++) {
185 void __iomem *base = gps->base;
186
187 gps->gpcon = __raw_readl(base + OFFS_CON);
188 gps->gpdat = __raw_readl(base + OFFS_DAT);
189
190 if (gpio > 0)
191 gps->gpup = __raw_readl(base + OFFS_UP);
192 130
131 for (pin = S3C2410_GPG(0); pin <= S3C2410_GPG(7); pin++) {
132 s3c_pm_check_resume_pin(pin, (pin - S3C2410_GPG(0))+8);
193 } 133 }
194} 134}
195 135
196/* Test whether the given masked+shifted bits of an GPIO configuration
197 * are one of the SFN (special function) modes. */
198
199static inline int is_sfn(unsigned long con)
200{
201 return (con == 2 || con == 3);
202}
203
204/* Test if the given masked+shifted GPIO configuration is an input */
205
206static inline int is_in(unsigned long con)
207{
208 return con == 0;
209}
210
211/* Test if the given masked+shifted GPIO configuration is an output */
212
213static inline int is_out(unsigned long con)
214{
215 return con == 1;
216}
217
218/**
219 * s3c2410_pm_restore_gpio() - restore the given GPIO bank
220 * @index: The number of the GPIO bank being resumed.
221 * @gps: The sleep confgiuration for the bank.
222 *
223 * Restore one of the GPIO banks that was saved during suspend. This is
224 * not as simple as once thought, due to the possibility of glitches
225 * from the order that the CON and DAT registers are set in.
226 *
227 * The three states the pin can be are {IN,OUT,SFN} which gives us 9
228 * combinations of changes to check. Three of these, if the pin stays
229 * in the same configuration can be discounted. This leaves us with
230 * the following:
231 *
232 * { IN => OUT } Change DAT first
233 * { IN => SFN } Change CON first
234 * { OUT => SFN } Change CON first, so new data will not glitch
235 * { OUT => IN } Change CON first, so new data will not glitch
236 * { SFN => IN } Change CON first
237 * { SFN => OUT } Change DAT first, so new data will not glitch [1]
238 *
239 * We do not currently deal with the UP registers as these control
240 * weak resistors, so a small delay in change should not need to bring
241 * these into the calculations.
242 *
243 * [1] this assumes that writing to a pin DAT whilst in SFN will set the
244 * state for when it is next output.
245 */
246
247static void s3c2410_pm_restore_gpio(int index, struct gpio_sleep *gps)
248{
249 void __iomem *base = gps->base;
250 unsigned long gps_gpcon = gps->gpcon;
251 unsigned long gps_gpdat = gps->gpdat;
252 unsigned long old_gpcon;
253 unsigned long old_gpdat;
254 unsigned long old_gpup = 0x0;
255 unsigned long gpcon;
256 int nr;
257
258 old_gpcon = __raw_readl(base + OFFS_CON);
259 old_gpdat = __raw_readl(base + OFFS_DAT);
260
261 if (base == S3C2410_GPACON) {
262 /* GPACON only has one bit per control / data and no PULLUPs.
263 * GPACON[x] = 0 => Output, 1 => SFN */
264
265 /* first set all SFN bits to SFN */
266
267 gpcon = old_gpcon | gps->gpcon;
268 __raw_writel(gpcon, base + OFFS_CON);
269
270 /* now set all the other bits */
271
272 __raw_writel(gps_gpdat, base + OFFS_DAT);
273 __raw_writel(gps_gpcon, base + OFFS_CON);
274 } else {
275 unsigned long old, new, mask;
276 unsigned long change_mask = 0x0;
277
278 old_gpup = __raw_readl(base + OFFS_UP);
279
280 /* Create a change_mask of all the items that need to have
281 * their CON value changed before their DAT value, so that
282 * we minimise the work between the two settings.
283 */
284
285 for (nr = 0, mask = 0x03; nr < 32; nr += 2, mask <<= 2) {
286 old = (old_gpcon & mask) >> nr;
287 new = (gps_gpcon & mask) >> nr;
288
289 /* If there is no change, then skip */
290
291 if (old == new)
292 continue;
293
294 /* If both are special function, then skip */
295
296 if (is_sfn(old) && is_sfn(new))
297 continue;
298
299 /* Change is IN => OUT, do not change now */
300
301 if (is_in(old) && is_out(new))
302 continue;
303
304 /* Change is SFN => OUT, do not change now */
305
306 if (is_sfn(old) && is_out(new))
307 continue;
308
309 /* We should now be at the case of IN=>SFN,
310 * OUT=>SFN, OUT=>IN, SFN=>IN. */
311
312 change_mask |= mask;
313 }
314
315 /* Write the new CON settings */
316
317 gpcon = old_gpcon & ~change_mask;
318 gpcon |= gps_gpcon & change_mask;
319
320 __raw_writel(gpcon, base + OFFS_CON);
321
322 /* Now change any items that require DAT,CON */
323
324 __raw_writel(gps_gpdat, base + OFFS_DAT);
325 __raw_writel(gps_gpcon, base + OFFS_CON);
326 __raw_writel(gps->gpup, base + OFFS_UP);
327 }
328
329 S3C_PMDBG("GPIO[%d] CON %08lx => %08lx, DAT %08lx => %08lx\n",
330 index, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
331}
332
333
334/** s3c2410_pm_restore_gpios()
335 *
336 * Restore the state of the GPIOs
337 */
338
339void s3c_pm_restore_gpios(void)
340{
341 struct gpio_sleep *gps = gpio_save;
342 int gpio;
343
344 for (gpio = 0; gpio < ARRAY_SIZE(gpio_save); gpio++, gps++) {
345 s3c2410_pm_restore_gpio(gpio, gps);
346 }
347}
348 136
349void s3c_pm_restore_core(void) 137void s3c_pm_restore_core(void)
350{ 138{
diff --git a/arch/arm/plat-s3c24xx/setup-i2c.c b/arch/arm/plat-s3c24xx/setup-i2c.c
index d62b7e7fb355..71a6accf114e 100644
--- a/arch/arm/plat-s3c24xx/setup-i2c.c
+++ b/arch/arm/plat-s3c24xx/setup-i2c.c
@@ -11,6 +11,7 @@
11*/ 11*/
12 12
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/gpio.h>
14 15
15struct platform_device; 16struct platform_device;
16 17
@@ -20,6 +21,6 @@ struct platform_device;
20 21
21void s3c_i2c0_cfg_gpio(struct platform_device *dev) 22void s3c_i2c0_cfg_gpio(struct platform_device *dev)
22{ 23{
23 s3c2410_gpio_cfgpin(S3C2410_GPE15, S3C2410_GPE15_IICSDA); 24 s3c2410_gpio_cfgpin(S3C2410_GPE(15), S3C2410_GPE15_IICSDA);
24 s3c2410_gpio_cfgpin(S3C2410_GPE14, S3C2410_GPE14_IICSCL); 25 s3c2410_gpio_cfgpin(S3C2410_GPE(14), S3C2410_GPE14_IICSCL);
25} 26}
diff --git a/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c b/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
index 8b403cbb53d2..9edf7894eedd 100644
--- a/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
+++ b/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
@@ -22,16 +22,16 @@ void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi,
22 int enable) 22 int enable)
23{ 23{
24 if (enable) { 24 if (enable) {
25 s3c2410_gpio_cfgpin(S3C2410_GPE13, S3C2410_GPE13_SPICLK0); 25 s3c2410_gpio_cfgpin(S3C2410_GPE(13), S3C2410_GPE13_SPICLK0);
26 s3c2410_gpio_cfgpin(S3C2410_GPE12, S3C2410_GPE12_SPIMOSI0); 26 s3c2410_gpio_cfgpin(S3C2410_GPE(12), S3C2410_GPE12_SPIMOSI0);
27 s3c2410_gpio_cfgpin(S3C2410_GPE11, S3C2410_GPE11_SPIMISO0); 27 s3c2410_gpio_cfgpin(S3C2410_GPE(11), S3C2410_GPE11_SPIMISO0);
28 s3c2410_gpio_pullup(S3C2410_GPE11, 0); 28 s3c2410_gpio_pullup(S3C2410_GPE(11), 0);
29 s3c2410_gpio_pullup(S3C2410_GPE13, 0); 29 s3c2410_gpio_pullup(S3C2410_GPE(13), 0);
30 } else { 30 } else {
31 s3c2410_gpio_cfgpin(S3C2410_GPE13, S3C2410_GPIO_INPUT); 31 s3c2410_gpio_cfgpin(S3C2410_GPE(13), S3C2410_GPIO_INPUT);
32 s3c2410_gpio_cfgpin(S3C2410_GPE11, S3C2410_GPIO_INPUT); 32 s3c2410_gpio_cfgpin(S3C2410_GPE(11), S3C2410_GPIO_INPUT);
33 s3c2410_gpio_pullup(S3C2410_GPE11, 1); 33 s3c2410_gpio_pullup(S3C2410_GPE(11), 1);
34 s3c2410_gpio_pullup(S3C2410_GPE12, 1); 34 s3c2410_gpio_pullup(S3C2410_GPE(12), 1);
35 s3c2410_gpio_pullup(S3C2410_GPE13, 1); 35 s3c2410_gpio_pullup(S3C2410_GPE(13), 1);
36 } 36 }
37} 37}
diff --git a/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c b/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c
index 8fccd4e549f0..f34d0fc69ad8 100644
--- a/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c
+++ b/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c
@@ -22,16 +22,16 @@ void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi,
22 int enable) 22 int enable)
23{ 23{
24 if (enable) { 24 if (enable) {
25 s3c2410_gpio_cfgpin(S3C2410_GPG7, S3C2410_GPG7_SPICLK1); 25 s3c2410_gpio_cfgpin(S3C2410_GPG(7), S3C2410_GPG7_SPICLK1);
26 s3c2410_gpio_cfgpin(S3C2410_GPG6, S3C2410_GPG6_SPIMOSI1); 26 s3c2410_gpio_cfgpin(S3C2410_GPG(6), S3C2410_GPG6_SPIMOSI1);
27 s3c2410_gpio_cfgpin(S3C2410_GPG5, S3C2410_GPG5_SPIMISO1); 27 s3c2410_gpio_cfgpin(S3C2410_GPG(5), S3C2410_GPG5_SPIMISO1);
28 s3c2410_gpio_pullup(S3C2410_GPG5, 0); 28 s3c2410_gpio_pullup(S3C2410_GPG(5), 0);
29 s3c2410_gpio_pullup(S3C2410_GPG6, 0); 29 s3c2410_gpio_pullup(S3C2410_GPG(6), 0);
30 } else { 30 } else {
31 s3c2410_gpio_cfgpin(S3C2410_GPG7, S3C2410_GPIO_INPUT); 31 s3c2410_gpio_cfgpin(S3C2410_GPG(7), S3C2410_GPIO_INPUT);
32 s3c2410_gpio_cfgpin(S3C2410_GPG5, S3C2410_GPIO_INPUT); 32 s3c2410_gpio_cfgpin(S3C2410_GPG(5), S3C2410_GPIO_INPUT);
33 s3c2410_gpio_pullup(S3C2410_GPG5, 1); 33 s3c2410_gpio_pullup(S3C2410_GPG(5), 1);
34 s3c2410_gpio_pullup(S3C2410_GPG6, 1); 34 s3c2410_gpio_pullup(S3C2410_GPG(6), 1);
35 s3c2410_gpio_pullup(S3C2410_GPG7, 1); 35 s3c2410_gpio_pullup(S3C2410_GPG(7), 1);
36 } 36 }
37} 37}
diff --git a/arch/arm/plat-s3c64xx/Kconfig b/arch/arm/plat-s3c64xx/Kconfig
index 54375a00a7d2..5ebd8b425a54 100644
--- a/arch/arm/plat-s3c64xx/Kconfig
+++ b/arch/arm/plat-s3c64xx/Kconfig
@@ -19,6 +19,7 @@ config PLAT_S3C64XX
19 select S3C_GPIO_PULL_UPDOWN 19 select S3C_GPIO_PULL_UPDOWN
20 select S3C_GPIO_CFG_S3C24XX 20 select S3C_GPIO_CFG_S3C24XX
21 select S3C_GPIO_CFG_S3C64XX 21 select S3C_GPIO_CFG_S3C64XX
22 select USB_ARCH_HAS_OHCI
22 help 23 help
23 Base platform code for any Samsung S3C64XX device 24 Base platform code for any Samsung S3C64XX device
24 25
@@ -38,6 +39,10 @@ config CPU_S3C6400_CLOCK
38 Common clock support code for the S3C6400 that is shared 39 Common clock support code for the S3C6400 that is shared
39 by other CPUs in the series, such as the S3C6410. 40 by other CPUs in the series, such as the S3C6410.
40 41
42config S3C64XX_DMA
43 bool "S3C64XX DMA"
44 select S3C_DMA
45
41# platform specific device setup 46# platform specific device setup
42 47
43config S3C64XX_SETUP_I2C0 48config S3C64XX_SETUP_I2C0
@@ -59,4 +64,9 @@ config S3C64XX_SETUP_FB_24BPP
59 help 64 help
60 Common setup code for S3C64XX with an 24bpp RGB display helper. 65 Common setup code for S3C64XX with an 24bpp RGB display helper.
61 66
67config S3C64XX_SETUP_SDHCI_GPIO
68 bool
69 help
70 Common setup code for S3C64XX SDHCI GPIO configurations
71
62endif 72endif
diff --git a/arch/arm/plat-s3c64xx/Makefile b/arch/arm/plat-s3c64xx/Makefile
index 2e6d79bf8f33..2ed5df34f9ea 100644
--- a/arch/arm/plat-s3c64xx/Makefile
+++ b/arch/arm/plat-s3c64xx/Makefile
@@ -24,8 +24,19 @@ obj-y += gpiolib.o
24obj-$(CONFIG_CPU_S3C6400_INIT) += s3c6400-init.o 24obj-$(CONFIG_CPU_S3C6400_INIT) += s3c6400-init.o
25obj-$(CONFIG_CPU_S3C6400_CLOCK) += s3c6400-clock.o 25obj-$(CONFIG_CPU_S3C6400_CLOCK) += s3c6400-clock.o
26 26
27# PM support
28
29obj-$(CONFIG_PM) += pm.o
30obj-$(CONFIG_PM) += sleep.o
31obj-$(CONFIG_PM) += irq-pm.o
32
33# DMA support
34
35obj-$(CONFIG_S3C64XX_DMA) += dma.o
36
27# Device setup 37# Device setup
28 38
29obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o 39obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o
30obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o 40obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o
31obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o 41obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o
42obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o \ No newline at end of file
diff --git a/arch/arm/plat-s3c64xx/clock.c b/arch/arm/plat-s3c64xx/clock.c
index ad1b9682c9c3..0bc2fa1dfc40 100644
--- a/arch/arm/plat-s3c64xx/clock.c
+++ b/arch/arm/plat-s3c64xx/clock.c
@@ -27,6 +27,12 @@
27#include <plat/devs.h> 27#include <plat/devs.h>
28#include <plat/clock.h> 28#include <plat/clock.h>
29 29
30struct clk clk_h2 = {
31 .name = "hclk2",
32 .id = -1,
33 .rate = 0,
34};
35
30struct clk clk_27m = { 36struct clk clk_27m = {
31 .name = "clk_27m", 37 .name = "clk_27m",
32 .id = -1, 38 .id = -1,
@@ -152,6 +158,18 @@ static struct clk init_clocks_disable[] = {
152 .parent = &clk_48m, 158 .parent = &clk_48m,
153 .enable = s3c64xx_sclk_ctrl, 159 .enable = s3c64xx_sclk_ctrl,
154 .ctrlbit = S3C_CLKCON_SCLK_MMC2_48, 160 .ctrlbit = S3C_CLKCON_SCLK_MMC2_48,
161 }, {
162 .name = "dma0",
163 .id = -1,
164 .parent = &clk_h,
165 .enable = s3c64xx_hclk_ctrl,
166 .ctrlbit = S3C_CLKCON_HCLK_DMA0,
167 }, {
168 .name = "dma1",
169 .id = -1,
170 .parent = &clk_h,
171 .enable = s3c64xx_hclk_ctrl,
172 .ctrlbit = S3C_CLKCON_HCLK_DMA1,
155 }, 173 },
156}; 174};
157 175
@@ -246,6 +264,7 @@ static struct clk *clks[] __initdata = {
246 &clk_epll, 264 &clk_epll,
247 &clk_27m, 265 &clk_27m,
248 &clk_48m, 266 &clk_48m,
267 &clk_h2,
249}; 268};
250 269
251void __init s3c64xx_register_clocks(void) 270void __init s3c64xx_register_clocks(void)
diff --git a/arch/arm/plat-s3c64xx/cpu.c b/arch/arm/plat-s3c64xx/cpu.c
index 91f49a3a665d..b1fdd83940a6 100644
--- a/arch/arm/plat-s3c64xx/cpu.c
+++ b/arch/arm/plat-s3c64xx/cpu.c
@@ -16,6 +16,7 @@
16#include <linux/module.h> 16#include <linux/module.h>
17#include <linux/interrupt.h> 17#include <linux/interrupt.h>
18#include <linux/ioport.h> 18#include <linux/ioport.h>
19#include <linux/sysdev.h>
19#include <linux/serial_core.h> 20#include <linux/serial_core.h>
20#include <linux/platform_device.h> 21#include <linux/platform_device.h>
21#include <linux/io.h> 22#include <linux/io.h>
@@ -101,9 +102,24 @@ static struct map_desc s3c_iodesc[] __initdata = {
101 .pfn = __phys_to_pfn(S3C64XX_PA_MODEM), 102 .pfn = __phys_to_pfn(S3C64XX_PA_MODEM),
102 .length = SZ_4K, 103 .length = SZ_4K,
103 .type = MT_DEVICE, 104 .type = MT_DEVICE,
105 }, {
106 .virtual = (unsigned long)S3C_VA_WATCHDOG,
107 .pfn = __phys_to_pfn(S3C64XX_PA_WATCHDOG),
108 .length = SZ_4K,
109 .type = MT_DEVICE,
104 }, 110 },
105}; 111};
106 112
113
114struct sysdev_class s3c64xx_sysclass = {
115 .name = "s3c64xx-core",
116};
117
118static struct sys_device s3c64xx_sysdev = {
119 .cls = &s3c64xx_sysclass,
120};
121
122
107/* read cpu identification code */ 123/* read cpu identification code */
108 124
109void __init s3c64xx_init_io(struct map_desc *mach_desc, int size) 125void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
@@ -115,5 +131,21 @@ void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
115 iotable_init(mach_desc, size); 131 iotable_init(mach_desc, size);
116 132
117 idcode = __raw_readl(S3C_VA_SYS + 0x118); 133 idcode = __raw_readl(S3C_VA_SYS + 0x118);
134 if (!idcode) {
135 /* S3C6400 has the ID register in a different place,
136 * and needs a write before it can be read. */
137
138 __raw_writel(0x0, S3C_VA_SYS + 0xA1C);
139 idcode = __raw_readl(S3C_VA_SYS + 0xA1C);
140 }
141
118 s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids)); 142 s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids));
119} 143}
144
145static __init int s3c64xx_sysdev_init(void)
146{
147 sysdev_class_register(&s3c64xx_sysclass);
148 return sysdev_register(&s3c64xx_sysdev);
149}
150
151core_initcall(s3c64xx_sysdev_init);
diff --git a/arch/arm/plat-s3c64xx/dma.c b/arch/arm/plat-s3c64xx/dma.c
new file mode 100644
index 000000000000..67aa93dbb69e
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/dma.c
@@ -0,0 +1,722 @@
1/* linux/arch/arm/plat-s3c64xx/dma.c
2 *
3 * Copyright 2009 Openmoko, Inc.
4 * Copyright 2009 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64XX DMA core
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/interrupt.h>
18#include <linux/dmapool.h>
19#include <linux/sysdev.h>
20#include <linux/errno.h>
21#include <linux/delay.h>
22#include <linux/clk.h>
23#include <linux/err.h>
24#include <linux/io.h>
25
26#include <mach/dma.h>
27#include <mach/map.h>
28#include <mach/irqs.h>
29
30#include <plat/dma-plat.h>
31#include <plat/regs-sys.h>
32
33#include <asm/hardware/pl080.h>
34
35/* dma channel state information */
36
37struct s3c64xx_dmac {
38 struct sys_device sysdev;
39 struct clk *clk;
40 void __iomem *regs;
41 struct s3c2410_dma_chan *channels;
42 enum dma_ch chanbase;
43};
44
45/* pool to provide LLI buffers */
46static struct dma_pool *dma_pool;
47
48/* Debug configuration and code */
49
50static unsigned char debug_show_buffs = 0;
51
52static void dbg_showchan(struct s3c2410_dma_chan *chan)
53{
54 pr_debug("DMA%d: %08x->%08x L %08x C %08x,%08x S %08x\n",
55 chan->number,
56 readl(chan->regs + PL080_CH_SRC_ADDR),
57 readl(chan->regs + PL080_CH_DST_ADDR),
58 readl(chan->regs + PL080_CH_LLI),
59 readl(chan->regs + PL080_CH_CONTROL),
60 readl(chan->regs + PL080S_CH_CONTROL2),
61 readl(chan->regs + PL080S_CH_CONFIG));
62}
63
64static void show_lli(struct pl080s_lli *lli)
65{
66 pr_debug("LLI[%p] %08x->%08x, NL %08x C %08x,%08x\n",
67 lli, lli->src_addr, lli->dst_addr, lli->next_lli,
68 lli->control0, lli->control1);
69}
70
71static void dbg_showbuffs(struct s3c2410_dma_chan *chan)
72{
73 struct s3c64xx_dma_buff *ptr;
74 struct s3c64xx_dma_buff *end;
75
76 pr_debug("DMA%d: buffs next %p, curr %p, end %p\n",
77 chan->number, chan->next, chan->curr, chan->end);
78
79 ptr = chan->next;
80 end = chan->end;
81
82 if (debug_show_buffs) {
83 for (; ptr != NULL; ptr = ptr->next) {
84 pr_debug("DMA%d: %08x ",
85 chan->number, ptr->lli_dma);
86 show_lli(ptr->lli);
87 }
88 }
89}
90
91/* End of Debug */
92
93static struct s3c2410_dma_chan *s3c64xx_dma_map_channel(unsigned int channel)
94{
95 struct s3c2410_dma_chan *chan;
96 unsigned int start, offs;
97
98 start = 0;
99
100 if (channel >= DMACH_PCM1_TX)
101 start = 8;
102
103 for (offs = 0; offs < 8; offs++) {
104 chan = &s3c2410_chans[start + offs];
105 if (!chan->in_use)
106 goto found;
107 }
108
109 return NULL;
110
111found:
112 s3c_dma_chan_map[channel] = chan;
113 return chan;
114}
115
116int s3c2410_dma_config(unsigned int channel, int xferunit)
117{
118 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
119
120 if (chan == NULL)
121 return -EINVAL;
122
123 switch (xferunit) {
124 case 1:
125 chan->hw_width = 0;
126 break;
127 case 2:
128 chan->hw_width = 1;
129 break;
130 case 4:
131 chan->hw_width = 2;
132 break;
133 default:
134 printk(KERN_ERR "%s: illegal width %d\n", __func__, xferunit);
135 return -EINVAL;
136 }
137
138 return 0;
139}
140EXPORT_SYMBOL(s3c2410_dma_config);
141
142static void s3c64xx_dma_fill_lli(struct s3c2410_dma_chan *chan,
143 struct pl080s_lli *lli,
144 dma_addr_t data, int size)
145{
146 dma_addr_t src, dst;
147 u32 control0, control1;
148
149 switch (chan->source) {
150 case S3C2410_DMASRC_HW:
151 src = chan->dev_addr;
152 dst = data;
153 control0 = PL080_CONTROL_SRC_AHB2;
154 control0 |= (u32)chan->hw_width << PL080_CONTROL_SWIDTH_SHIFT;
155 control0 |= 2 << PL080_CONTROL_DWIDTH_SHIFT;
156 control0 |= PL080_CONTROL_DST_INCR;
157 break;
158
159 case S3C2410_DMASRC_MEM:
160 src = data;
161 dst = chan->dev_addr;
162 control0 = PL080_CONTROL_DST_AHB2;
163 control0 |= (u32)chan->hw_width << PL080_CONTROL_DWIDTH_SHIFT;
164 control0 |= 2 << PL080_CONTROL_SWIDTH_SHIFT;
165 control0 |= PL080_CONTROL_SRC_INCR;
166 break;
167 default:
168 BUG();
169 }
170
171 /* note, we do not currently setup any of the burst controls */
172
173 control1 = size >> chan->hw_width; /* size in no of xfers */
174 control0 |= PL080_CONTROL_PROT_SYS; /* always in priv. mode */
175 control0 |= PL080_CONTROL_TC_IRQ_EN; /* always fire IRQ */
176
177 lli->src_addr = src;
178 lli->dst_addr = dst;
179 lli->next_lli = 0;
180 lli->control0 = control0;
181 lli->control1 = control1;
182}
183
184static void s3c64xx_lli_to_regs(struct s3c2410_dma_chan *chan,
185 struct pl080s_lli *lli)
186{
187 void __iomem *regs = chan->regs;
188
189 pr_debug("%s: LLI %p => regs\n", __func__, lli);
190 show_lli(lli);
191
192 writel(lli->src_addr, regs + PL080_CH_SRC_ADDR);
193 writel(lli->dst_addr, regs + PL080_CH_DST_ADDR);
194 writel(lli->next_lli, regs + PL080_CH_LLI);
195 writel(lli->control0, regs + PL080_CH_CONTROL);
196 writel(lli->control1, regs + PL080S_CH_CONTROL2);
197}
198
199static int s3c64xx_dma_start(struct s3c2410_dma_chan *chan)
200{
201 struct s3c64xx_dmac *dmac = chan->dmac;
202 u32 config;
203 u32 bit = chan->bit;
204
205 dbg_showchan(chan);
206
207 pr_debug("%s: clearing interrupts\n", __func__);
208
209 /* clear interrupts */
210 writel(bit, dmac->regs + PL080_TC_CLEAR);
211 writel(bit, dmac->regs + PL080_ERR_CLEAR);
212
213 pr_debug("%s: starting channel\n", __func__);
214
215 config = readl(chan->regs + PL080S_CH_CONFIG);
216 config |= PL080_CONFIG_ENABLE;
217
218 pr_debug("%s: writing config %08x\n", __func__, config);
219 writel(config, chan->regs + PL080S_CH_CONFIG);
220
221 return 0;
222}
223
224static int s3c64xx_dma_stop(struct s3c2410_dma_chan *chan)
225{
226 u32 config;
227 int timeout;
228
229 pr_debug("%s: stopping channel\n", __func__);
230
231 dbg_showchan(chan);
232
233 config = readl(chan->regs + PL080S_CH_CONFIG);
234 config |= PL080_CONFIG_HALT;
235 writel(config, chan->regs + PL080S_CH_CONFIG);
236
237 timeout = 1000;
238 do {
239 config = readl(chan->regs + PL080S_CH_CONFIG);
240 pr_debug("%s: %d - config %08x\n", __func__, timeout, config);
241 if (config & PL080_CONFIG_ACTIVE)
242 udelay(10);
243 else
244 break;
245 } while (--timeout > 0);
246
247 if (config & PL080_CONFIG_ACTIVE) {
248 printk(KERN_ERR "%s: channel still active\n", __func__);
249 return -EFAULT;
250 }
251
252 config = readl(chan->regs + PL080S_CH_CONFIG);
253 config &= ~PL080_CONFIG_ENABLE;
254 writel(config, chan->regs + PL080S_CH_CONFIG);
255
256 return 0;
257}
258
259static inline void s3c64xx_dma_bufffdone(struct s3c2410_dma_chan *chan,
260 struct s3c64xx_dma_buff *buf,
261 enum s3c2410_dma_buffresult result)
262{
263 if (chan->callback_fn != NULL)
264 (chan->callback_fn)(chan, buf->pw, 0, result);
265}
266
267static void s3c64xx_dma_freebuff(struct s3c64xx_dma_buff *buff)
268{
269 dma_pool_free(dma_pool, buff->lli, buff->lli_dma);
270 kfree(buff);
271}
272
273static int s3c64xx_dma_flush(struct s3c2410_dma_chan *chan)
274{
275 struct s3c64xx_dma_buff *buff, *next;
276 u32 config;
277
278 dbg_showchan(chan);
279
280 pr_debug("%s: flushing channel\n", __func__);
281
282 config = readl(chan->regs + PL080S_CH_CONFIG);
283 config &= ~PL080_CONFIG_ENABLE;
284 writel(config, chan->regs + PL080S_CH_CONFIG);
285
286 /* dump all the buffers associated with this channel */
287
288 for (buff = chan->curr; buff != NULL; buff = next) {
289 next = buff->next;
290 pr_debug("%s: buff %p (next %p)\n", __func__, buff, buff->next);
291
292 s3c64xx_dma_bufffdone(chan, buff, S3C2410_RES_ABORT);
293 s3c64xx_dma_freebuff(buff);
294 }
295
296 chan->curr = chan->next = chan->end = NULL;
297
298 return 0;
299}
300
301int s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op)
302{
303 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
304
305 WARN_ON(!chan);
306 if (!chan)
307 return -EINVAL;
308
309 switch (op) {
310 case S3C2410_DMAOP_START:
311 return s3c64xx_dma_start(chan);
312
313 case S3C2410_DMAOP_STOP:
314 return s3c64xx_dma_stop(chan);
315
316 case S3C2410_DMAOP_FLUSH:
317 return s3c64xx_dma_flush(chan);
318
319 /* belive PAUSE/RESUME are no-ops */
320 case S3C2410_DMAOP_PAUSE:
321 case S3C2410_DMAOP_RESUME:
322 case S3C2410_DMAOP_STARTED:
323 case S3C2410_DMAOP_TIMEOUT:
324 return 0;
325 }
326
327 return -ENOENT;
328}
329EXPORT_SYMBOL(s3c2410_dma_ctrl);
330
331/* s3c2410_dma_enque
332 *
333 */
334
335int s3c2410_dma_enqueue(unsigned int channel, void *id,
336 dma_addr_t data, int size)
337{
338 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
339 struct s3c64xx_dma_buff *next;
340 struct s3c64xx_dma_buff *buff;
341 struct pl080s_lli *lli;
342 int ret;
343
344 WARN_ON(!chan);
345 if (!chan)
346 return -EINVAL;
347
348 buff = kzalloc(sizeof(struct s3c64xx_dma_buff), GFP_KERNEL);
349 if (!buff) {
350 printk(KERN_ERR "%s: no memory for buffer\n", __func__);
351 return -ENOMEM;
352 }
353
354 lli = dma_pool_alloc(dma_pool, GFP_KERNEL, &buff->lli_dma);
355 if (!lli) {
356 printk(KERN_ERR "%s: no memory for lli\n", __func__);
357 ret = -ENOMEM;
358 goto err_buff;
359 }
360
361 pr_debug("%s: buff %p, dp %08x lli (%p, %08x) %d\n",
362 __func__, buff, data, lli, (u32)buff->lli_dma, size);
363
364 buff->lli = lli;
365 buff->pw = id;
366
367 s3c64xx_dma_fill_lli(chan, lli, data, size);
368
369 if ((next = chan->next) != NULL) {
370 struct s3c64xx_dma_buff *end = chan->end;
371 struct pl080s_lli *endlli = end->lli;
372
373 pr_debug("enquing onto channel\n");
374
375 end->next = buff;
376 endlli->next_lli = buff->lli_dma;
377
378 if (chan->flags & S3C2410_DMAF_CIRCULAR) {
379 struct s3c64xx_dma_buff *curr = chan->curr;
380 lli->next_lli = curr->lli_dma;
381 }
382
383 if (next == chan->curr) {
384 writel(buff->lli_dma, chan->regs + PL080_CH_LLI);
385 chan->next = buff;
386 }
387
388 show_lli(endlli);
389 chan->end = buff;
390 } else {
391 pr_debug("enquing onto empty channel\n");
392
393 chan->curr = buff;
394 chan->next = buff;
395 chan->end = buff;
396
397 s3c64xx_lli_to_regs(chan, lli);
398 }
399
400 show_lli(lli);
401
402 dbg_showchan(chan);
403 dbg_showbuffs(chan);
404 return 0;
405
406err_buff:
407 kfree(buff);
408 return ret;
409}
410
411EXPORT_SYMBOL(s3c2410_dma_enqueue);
412
413
414int s3c2410_dma_devconfig(int channel,
415 enum s3c2410_dmasrc source,
416 unsigned long devaddr)
417{
418 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
419 u32 peripheral;
420 u32 config = 0;
421
422 pr_debug("%s: channel %d, source %d, dev %08lx, chan %p\n",
423 __func__, channel, source, devaddr, chan);
424
425 WARN_ON(!chan);
426 if (!chan)
427 return -EINVAL;
428
429 peripheral = (chan->peripheral & 0xf);
430 chan->source = source;
431 chan->dev_addr = devaddr;
432
433 pr_debug("%s: peripheral %d\n", __func__, peripheral);
434
435 switch (source) {
436 case S3C2410_DMASRC_HW:
437 config = 2 << PL080_CONFIG_FLOW_CONTROL_SHIFT;
438 config |= peripheral << PL080_CONFIG_SRC_SEL_SHIFT;
439 break;
440 case S3C2410_DMASRC_MEM:
441 config = 1 << PL080_CONFIG_FLOW_CONTROL_SHIFT;
442 config |= peripheral << PL080_CONFIG_DST_SEL_SHIFT;
443 break;
444 default:
445 printk(KERN_ERR "%s: bad source\n", __func__);
446 return -EINVAL;
447 }
448
449 /* allow TC and ERR interrupts */
450 config |= PL080_CONFIG_TC_IRQ_MASK;
451 config |= PL080_CONFIG_ERR_IRQ_MASK;
452
453 pr_debug("%s: config %08x\n", __func__, config);
454
455 writel(config, chan->regs + PL080S_CH_CONFIG);
456
457 return 0;
458}
459EXPORT_SYMBOL(s3c2410_dma_devconfig);
460
461
462int s3c2410_dma_getposition(unsigned int channel,
463 dma_addr_t *src, dma_addr_t *dst)
464{
465 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
466
467 WARN_ON(!chan);
468 if (!chan)
469 return -EINVAL;
470
471 if (src != NULL)
472 *src = readl(chan->regs + PL080_CH_SRC_ADDR);
473
474 if (dst != NULL)
475 *dst = readl(chan->regs + PL080_CH_DST_ADDR);
476
477 return 0;
478}
479EXPORT_SYMBOL(s3c2410_dma_getposition);
480
481/* s3c2410_request_dma
482 *
483 * get control of an dma channel
484*/
485
486int s3c2410_dma_request(unsigned int channel,
487 struct s3c2410_dma_client *client,
488 void *dev)
489{
490 struct s3c2410_dma_chan *chan;
491 unsigned long flags;
492
493 pr_debug("dma%d: s3c2410_request_dma: client=%s, dev=%p\n",
494 channel, client->name, dev);
495
496 local_irq_save(flags);
497
498 chan = s3c64xx_dma_map_channel(channel);
499 if (chan == NULL) {
500 local_irq_restore(flags);
501 return -EBUSY;
502 }
503
504 dbg_showchan(chan);
505
506 chan->client = client;
507 chan->in_use = 1;
508 chan->peripheral = channel;
509
510 local_irq_restore(flags);
511
512 /* need to setup */
513
514 pr_debug("%s: channel initialised, %p\n", __func__, chan);
515
516 return chan->number | DMACH_LOW_LEVEL;
517}
518
519EXPORT_SYMBOL(s3c2410_dma_request);
520
521/* s3c2410_dma_free
522 *
523 * release the given channel back to the system, will stop and flush
524 * any outstanding transfers, and ensure the channel is ready for the
525 * next claimant.
526 *
527 * Note, although a warning is currently printed if the freeing client
528 * info is not the same as the registrant's client info, the free is still
529 * allowed to go through.
530*/
531
532int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *client)
533{
534 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
535 unsigned long flags;
536
537 if (chan == NULL)
538 return -EINVAL;
539
540 local_irq_save(flags);
541
542 if (chan->client != client) {
543 printk(KERN_WARNING "dma%d: possible free from different client (channel %p, passed %p)\n",
544 channel, chan->client, client);
545 }
546
547 /* sort out stopping and freeing the channel */
548
549
550 chan->client = NULL;
551 chan->in_use = 0;
552
553 if (!(channel & DMACH_LOW_LEVEL))
554 s3c_dma_chan_map[channel] = NULL;
555
556 local_irq_restore(flags);
557
558 return 0;
559}
560
561EXPORT_SYMBOL(s3c2410_dma_free);
562
563
564static void s3c64xx_dma_tcirq(struct s3c64xx_dmac *dmac, int offs)
565{
566 struct s3c2410_dma_chan *chan = dmac->channels + offs;
567
568 /* note, we currently do not bother to work out which buffer
569 * or buffers have been completed since the last tc-irq. */
570
571 if (chan->callback_fn)
572 (chan->callback_fn)(chan, chan->curr->pw, 0, S3C2410_RES_OK);
573}
574
575static void s3c64xx_dma_errirq(struct s3c64xx_dmac *dmac, int offs)
576{
577 printk(KERN_DEBUG "%s: offs %d\n", __func__, offs);
578}
579
580static irqreturn_t s3c64xx_dma_irq(int irq, void *pw)
581{
582 struct s3c64xx_dmac *dmac = pw;
583 u32 tcstat, errstat;
584 u32 bit;
585 int offs;
586
587 tcstat = readl(dmac->regs + PL080_TC_STATUS);
588 errstat = readl(dmac->regs + PL080_ERR_STATUS);
589
590 for (offs = 0, bit = 1; offs < 8; offs++, bit <<= 1) {
591 if (tcstat & bit) {
592 writel(bit, dmac->regs + PL080_TC_CLEAR);
593 s3c64xx_dma_tcirq(dmac, offs);
594 }
595
596 if (errstat & bit) {
597 s3c64xx_dma_errirq(dmac, offs);
598 writel(bit, dmac->regs + PL080_ERR_CLEAR);
599 }
600 }
601
602 return IRQ_HANDLED;
603}
604
605static struct sysdev_class dma_sysclass = {
606 .name = "s3c64xx-dma",
607};
608
609static int s3c64xx_dma_init1(int chno, enum dma_ch chbase,
610 int irq, unsigned int base)
611{
612 struct s3c2410_dma_chan *chptr = &s3c2410_chans[chno];
613 struct s3c64xx_dmac *dmac;
614 char clkname[16];
615 void __iomem *regs;
616 void __iomem *regptr;
617 int err, ch;
618
619 dmac = kzalloc(sizeof(struct s3c64xx_dmac), GFP_KERNEL);
620 if (!dmac) {
621 printk(KERN_ERR "%s: failed to alloc mem\n", __func__);
622 return -ENOMEM;
623 }
624
625 dmac->sysdev.id = chno / 8;
626 dmac->sysdev.cls = &dma_sysclass;
627
628 err = sysdev_register(&dmac->sysdev);
629 if (err) {
630 printk(KERN_ERR "%s: failed to register sysdevice\n", __func__);
631 goto err_alloc;
632 }
633
634 regs = ioremap(base, 0x200);
635 if (!regs) {
636 printk(KERN_ERR "%s: failed to ioremap()\n", __func__);
637 err = -ENXIO;
638 goto err_dev;
639 }
640
641 snprintf(clkname, sizeof(clkname), "dma%d", dmac->sysdev.id);
642
643 dmac->clk = clk_get(NULL, clkname);
644 if (IS_ERR(dmac->clk)) {
645 printk(KERN_ERR "%s: failed to get clock %s\n", __func__, clkname);
646 err = PTR_ERR(dmac->clk);
647 goto err_map;
648 }
649
650 clk_enable(dmac->clk);
651
652 dmac->regs = regs;
653 dmac->chanbase = chbase;
654 dmac->channels = chptr;
655
656 err = request_irq(irq, s3c64xx_dma_irq, 0, "DMA", dmac);
657 if (err < 0) {
658 printk(KERN_ERR "%s: failed to get irq\n", __func__);
659 goto err_clk;
660 }
661
662 regptr = regs + PL080_Cx_BASE(0);
663
664 for (ch = 0; ch < 8; ch++, chno++, chptr++) {
665 printk(KERN_INFO "%s: registering DMA %d (%p)\n",
666 __func__, chno, regptr);
667
668 chptr->bit = 1 << ch;
669 chptr->number = chno;
670 chptr->dmac = dmac;
671 chptr->regs = regptr;
672 regptr += PL008_Cx_STRIDE;
673 }
674
675 /* for the moment, permanently enable the controller */
676 writel(PL080_CONFIG_ENABLE, regs + PL080_CONFIG);
677
678 printk(KERN_INFO "PL080: IRQ %d, at %p\n", irq, regs);
679
680 return 0;
681
682err_clk:
683 clk_disable(dmac->clk);
684 clk_put(dmac->clk);
685err_map:
686 iounmap(regs);
687err_dev:
688 sysdev_unregister(&dmac->sysdev);
689err_alloc:
690 kfree(dmac);
691 return err;
692}
693
694static int __init s3c64xx_dma_init(void)
695{
696 int ret;
697
698 printk(KERN_INFO "%s: Registering DMA channels\n", __func__);
699
700 dma_pool = dma_pool_create("DMA-LLI", NULL, 32, 16, 0);
701 if (!dma_pool) {
702 printk(KERN_ERR "%s: failed to create pool\n", __func__);
703 return -ENOMEM;
704 }
705
706 ret = sysdev_class_register(&dma_sysclass);
707 if (ret) {
708 printk(KERN_ERR "%s: failed to create sysclass\n", __func__);
709 return -ENOMEM;
710 }
711
712 /* Set all DMA configuration to be DMA, not SDMA */
713 writel(0xffffff, S3C_SYSREG(0x110));
714
715 /* Register standard DMA controlers */
716 s3c64xx_dma_init1(0, DMACH_UART0, IRQ_DMA0, 0x75000000);
717 s3c64xx_dma_init1(8, DMACH_PCM1_TX, IRQ_DMA1, 0x75100000);
718
719 return 0;
720}
721
722arch_initcall(s3c64xx_dma_init);
diff --git a/arch/arm/plat-s3c64xx/gpiolib.c b/arch/arm/plat-s3c64xx/gpiolib.c
index 78ee52cffc9e..da7b60ee5e67 100644
--- a/arch/arm/plat-s3c64xx/gpiolib.c
+++ b/arch/arm/plat-s3c64xx/gpiolib.c
@@ -385,12 +385,19 @@ static __init void s3c64xx_gpiolib_add_4bit(struct s3c_gpio_chip *chip)
385{ 385{
386 chip->chip.direction_input = s3c64xx_gpiolib_4bit_input; 386 chip->chip.direction_input = s3c64xx_gpiolib_4bit_input;
387 chip->chip.direction_output = s3c64xx_gpiolib_4bit_output; 387 chip->chip.direction_output = s3c64xx_gpiolib_4bit_output;
388 chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
388} 389}
389 390
390static __init void s3c64xx_gpiolib_add_4bit2(struct s3c_gpio_chip *chip) 391static __init void s3c64xx_gpiolib_add_4bit2(struct s3c_gpio_chip *chip)
391{ 392{
392 chip->chip.direction_input = s3c64xx_gpiolib_4bit2_input; 393 chip->chip.direction_input = s3c64xx_gpiolib_4bit2_input;
393 chip->chip.direction_output = s3c64xx_gpiolib_4bit2_output; 394 chip->chip.direction_output = s3c64xx_gpiolib_4bit2_output;
395 chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
396}
397
398static __init void s3c64xx_gpiolib_add_2bit(struct s3c_gpio_chip *chip)
399{
400 chip->pm = __gpio_pm(&s3c_gpio_pm_2bit);
394} 401}
395 402
396static __init void s3c64xx_gpiolib_add(struct s3c_gpio_chip *chips, 403static __init void s3c64xx_gpiolib_add(struct s3c_gpio_chip *chips,
@@ -412,7 +419,8 @@ static __init int s3c64xx_gpiolib_init(void)
412 s3c64xx_gpiolib_add(gpio_4bit2, ARRAY_SIZE(gpio_4bit2), 419 s3c64xx_gpiolib_add(gpio_4bit2, ARRAY_SIZE(gpio_4bit2),
413 s3c64xx_gpiolib_add_4bit2); 420 s3c64xx_gpiolib_add_4bit2);
414 421
415 s3c64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit), NULL); 422 s3c64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit),
423 s3c64xx_gpiolib_add_2bit);
416 424
417 return 0; 425 return 0;
418} 426}
diff --git a/arch/arm/plat-s3c64xx/include/plat/dma-plat.h b/arch/arm/plat-s3c64xx/include/plat/dma-plat.h
new file mode 100644
index 000000000000..0c30dd986725
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/dma-plat.h
@@ -0,0 +1,70 @@
1/* linux/arch/arm/plat-s3c64xx/include/plat/dma-plat.h
2 *
3 * Copyright 2009 Openmoko, Inc.
4 * Copyright 2009 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64XX DMA core
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */
16
17struct s3c64xx_dma_buff;
18
19/** s3c64xx_dma_buff - S3C64XX DMA buffer descriptor
20 * @next: Pointer to next buffer in queue or ring.
21 * @pw: Client provided identifier
22 * @lli: Pointer to hardware descriptor this buffer is associated with.
23 * @lli_dma: Hardare address of the descriptor.
24 */
25struct s3c64xx_dma_buff {
26 struct s3c64xx_dma_buff *next;
27
28 void *pw;
29 struct pl080_lli *lli;
30 dma_addr_t lli_dma;
31};
32
33struct s3c64xx_dmac;
34
35struct s3c2410_dma_chan {
36 unsigned char number; /* number of this dma channel */
37 unsigned char in_use; /* channel allocated */
38 unsigned char bit; /* bit for enable/disable/etc */
39 unsigned char hw_width;
40 unsigned char peripheral;
41
42 unsigned int flags;
43 enum s3c2410_dmasrc source;
44
45
46 dma_addr_t dev_addr;
47
48 struct s3c2410_dma_client *client;
49 struct s3c64xx_dmac *dmac; /* pointer to controller */
50
51 void __iomem *regs;
52
53 /* cdriver callbacks */
54 s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */
55 s3c2410_dma_opfn_t op_fn; /* channel op callback */
56
57 /* buffer list and information */
58 struct s3c64xx_dma_buff *curr; /* current dma buffer */
59 struct s3c64xx_dma_buff *next; /* next buffer to load */
60 struct s3c64xx_dma_buff *end; /* end of queue */
61
62 /* note, when channel is running in circular mode, curr is the
63 * first buffer enqueued, end is the last and curr is where the
64 * last buffer-done event is set-at. The buffers are not freed
65 * and the last buffer hardware descriptor points back to the
66 * first.
67 */
68};
69
70#include <plat/dma-core.h>
diff --git a/arch/arm/plat-s3c64xx/include/plat/irqs.h b/arch/arm/plat-s3c64xx/include/plat/irqs.h
index f865bf4d709e..743a70094d04 100644
--- a/arch/arm/plat-s3c64xx/include/plat/irqs.h
+++ b/arch/arm/plat-s3c64xx/include/plat/irqs.h
@@ -157,6 +157,7 @@
157 157
158#define S3C_EINT(x) ((x) + S3C_IRQ_EINT_BASE) 158#define S3C_EINT(x) ((x) + S3C_IRQ_EINT_BASE)
159#define IRQ_EINT(x) S3C_EINT(x) 159#define IRQ_EINT(x) S3C_EINT(x)
160#define IRQ_EINT_BIT(x) ((x) - S3C_EINT(0))
160 161
161/* Next the external interrupt groups. These are similar to the IRQ_EINT(x) 162/* Next the external interrupt groups. These are similar to the IRQ_EINT(x)
162 * that they are sourced from the GPIO pins but with a different scheme for 163 * that they are sourced from the GPIO pins but with a different scheme for
diff --git a/arch/arm/plat-s3c64xx/include/plat/pm-core.h b/arch/arm/plat-s3c64xx/include/plat/pm-core.h
new file mode 100644
index 000000000000..d347de3ba0dc
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/pm-core.h
@@ -0,0 +1,98 @@
1/* linux/arch/arm/plat-s3c64xx/include/plat/pm-core.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64XX - PM core support for arch/arm/plat-s3c/pm.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <plat/regs-gpio.h>
16
17static inline void s3c_pm_debug_init_uart(void)
18{
19 u32 tmp = __raw_readl(S3C_PCLK_GATE);
20
21 /* As a note, since the S3C64XX UARTs generally have multiple
22 * clock sources, we simply enable PCLK at the moment and hope
23 * that the resume settings for the UART are suitable for the
24 * use with PCLK.
25 */
26
27 tmp |= S3C_CLKCON_PCLK_UART0;
28 tmp |= S3C_CLKCON_PCLK_UART1;
29 tmp |= S3C_CLKCON_PCLK_UART2;
30 tmp |= S3C_CLKCON_PCLK_UART3;
31
32 __raw_writel(tmp, S3C_PCLK_GATE);
33 udelay(10);
34}
35
36static inline void s3c_pm_arch_prepare_irqs(void)
37{
38 /* VIC should have already been taken care of */
39
40 /* clear any pending EINT0 interrupts */
41 __raw_writel(__raw_readl(S3C64XX_EINT0PEND), S3C64XX_EINT0PEND);
42}
43
44static inline void s3c_pm_arch_stop_clocks(void)
45{
46}
47
48static inline void s3c_pm_arch_show_resume_irqs(void)
49{
50}
51
52/* make these defines, we currently do not have any need to change
53 * the IRQ wake controls depending on the CPU we are running on */
54
55#define s3c_irqwake_eintallow ((1 << 28) - 1)
56#define s3c_irqwake_intallow (0)
57
58static inline void s3c_pm_arch_update_uart(void __iomem *regs,
59 struct pm_uart_save *save)
60{
61 u32 ucon = __raw_readl(regs + S3C2410_UCON);
62 u32 ucon_clk = ucon & S3C6400_UCON_CLKMASK;
63 u32 save_clk = save->ucon & S3C6400_UCON_CLKMASK;
64 u32 new_ucon;
65 u32 delta;
66
67 /* S3C64XX UART blocks only support level interrupts, so ensure that
68 * when we restore unused UART blocks we force the level interrupt
69 * settigs. */
70 save->ucon |= S3C2410_UCON_TXILEVEL | S3C2410_UCON_RXILEVEL;
71
72 /* We have a constraint on changing the clock type of the UART
73 * between UCLKx and PCLK, so ensure that when we restore UCON
74 * that the CLK field is correctly modified if the bootloader
75 * has changed anything.
76 */
77 if (ucon_clk != save_clk) {
78 new_ucon = save->ucon;
79 delta = ucon_clk ^ save_clk;
80
81 /* change from UCLKx => wrong PCLK,
82 * either UCLK can be tested for by a bit-test
83 * with UCLK0 */
84 if (ucon_clk & S3C6400_UCON_UCLK0 &&
85 !(save_clk & S3C6400_UCON_UCLK0) &&
86 delta & S3C6400_UCON_PCLK2) {
87 new_ucon &= ~S3C6400_UCON_UCLK0;
88 } else if (delta == S3C6400_UCON_PCLK2) {
89 /* as an precaution, don't change from
90 * PCLK2 => PCLK or vice-versa */
91 new_ucon ^= S3C6400_UCON_PCLK2;
92 }
93
94 S3C_PMDBG("ucon change %04x => %04x (save=%04x)\n",
95 ucon, new_ucon, save->ucon);
96 save->ucon = new_ucon;
97 }
98}
diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h
index b1082c163247..52836d41e333 100644
--- a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h
+++ b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h
@@ -32,6 +32,7 @@
32#define S3C_HCLK_GATE S3C_CLKREG(0x30) 32#define S3C_HCLK_GATE S3C_CLKREG(0x30)
33#define S3C_PCLK_GATE S3C_CLKREG(0x34) 33#define S3C_PCLK_GATE S3C_CLKREG(0x34)
34#define S3C_SCLK_GATE S3C_CLKREG(0x38) 34#define S3C_SCLK_GATE S3C_CLKREG(0x38)
35#define S3C_MEM0_GATE S3C_CLKREG(0x3C)
35 36
36/* CLKDIV0 */ 37/* CLKDIV0 */
37#define S3C6400_CLKDIV0_MFC_MASK (0xf << 28) 38#define S3C6400_CLKDIV0_MFC_MASK (0xf << 28)
diff --git a/arch/arm/plat-s3c64xx/include/plat/s3c6400.h b/arch/arm/plat-s3c64xx/include/plat/s3c6400.h
index 571eaa2e54f1..11f2e1e119b0 100644
--- a/arch/arm/plat-s3c64xx/include/plat/s3c6400.h
+++ b/arch/arm/plat-s3c64xx/include/plat/s3c6400.h
@@ -15,12 +15,13 @@
15/* Common init code for S3C6400 related SoCs */ 15/* Common init code for S3C6400 related SoCs */
16 16
17extern void s3c6400_common_init_uarts(struct s3c2410_uartcfg *cfg, int no); 17extern void s3c6400_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
18extern void s3c6400_register_clocks(void); 18extern void s3c6400_register_clocks(unsigned armclk_divlimit);
19extern void s3c6400_setup_clocks(void); 19extern void s3c6400_setup_clocks(void);
20 20
21#ifdef CONFIG_CPU_S3C6400 21#ifdef CONFIG_CPU_S3C6400
22 22
23extern int s3c6400_init(void); 23extern int s3c6400_init(void);
24extern void s3c6400_init_irq(void);
24extern void s3c6400_map_io(void); 25extern void s3c6400_map_io(void);
25extern void s3c6400_init_clocks(int xtal); 26extern void s3c6400_init_clocks(int xtal);
26 27
diff --git a/arch/arm/plat-s3c64xx/irq-eint.c b/arch/arm/plat-s3c64xx/irq-eint.c
index 47e5155bb13e..f81b7b818ba0 100644
--- a/arch/arm/plat-s3c64xx/irq-eint.c
+++ b/arch/arm/plat-s3c64xx/irq-eint.c
@@ -14,6 +14,7 @@
14 14
15#include <linux/kernel.h> 15#include <linux/kernel.h>
16#include <linux/interrupt.h> 16#include <linux/interrupt.h>
17#include <linux/sysdev.h>
17#include <linux/gpio.h> 18#include <linux/gpio.h>
18#include <linux/irq.h> 19#include <linux/irq.h>
19#include <linux/io.h> 20#include <linux/io.h>
@@ -26,6 +27,7 @@
26 27
27#include <mach/map.h> 28#include <mach/map.h>
28#include <plat/cpu.h> 29#include <plat/cpu.h>
30#include <plat/pm.h>
29 31
30#define eint_offset(irq) ((irq) - IRQ_EINT(0)) 32#define eint_offset(irq) ((irq) - IRQ_EINT(0))
31#define eint_irq_to_bit(irq) (1 << eint_offset(irq)) 33#define eint_irq_to_bit(irq) (1 << eint_offset(irq))
@@ -134,6 +136,7 @@ static struct irq_chip s3c_irq_eint = {
134 .mask_ack = s3c_irq_eint_maskack, 136 .mask_ack = s3c_irq_eint_maskack,
135 .ack = s3c_irq_eint_ack, 137 .ack = s3c_irq_eint_ack,
136 .set_type = s3c_irq_eint_set_type, 138 .set_type = s3c_irq_eint_set_type,
139 .set_wake = s3c_irqext_wake,
137}; 140};
138 141
139/* s3c_irq_demux_eint 142/* s3c_irq_demux_eint
diff --git a/arch/arm/plat-s3c64xx/irq-pm.c b/arch/arm/plat-s3c64xx/irq-pm.c
new file mode 100644
index 000000000000..ca523b5d4c17
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/irq-pm.c
@@ -0,0 +1,111 @@
1/* arch/arm/plat-s3c64xx/irq-pm.c
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64XX - Interrupt handling Power Management
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include <linux/sysdev.h>
17#include <linux/interrupt.h>
18#include <linux/serial_core.h>
19#include <linux/irq.h>
20#include <linux/io.h>
21
22#include <mach/map.h>
23
24#include <plat/regs-serial.h>
25#include <plat/regs-timer.h>
26#include <plat/regs-gpio.h>
27#include <plat/cpu.h>
28#include <plat/pm.h>
29
30/* We handled all the IRQ types in this code, to save having to make several
31 * small files to handle each different type separately. Having the EINT_GRP
32 * code here shouldn't be as much bloat as the IRQ table space needed when
33 * they are enabled. The added benefit is we ensure that these registers are
34 * in the same state as we suspended.
35 */
36
37static struct sleep_save irq_save[] = {
38 SAVE_ITEM(S3C64XX_PRIORITY),
39 SAVE_ITEM(S3C64XX_EINT0CON0),
40 SAVE_ITEM(S3C64XX_EINT0CON1),
41 SAVE_ITEM(S3C64XX_EINT0FLTCON0),
42 SAVE_ITEM(S3C64XX_EINT0FLTCON1),
43 SAVE_ITEM(S3C64XX_EINT0FLTCON2),
44 SAVE_ITEM(S3C64XX_EINT0FLTCON3),
45 SAVE_ITEM(S3C64XX_EINT0MASK),
46 SAVE_ITEM(S3C64XX_TINT_CSTAT),
47};
48
49static struct irq_grp_save {
50 u32 fltcon;
51 u32 con;
52 u32 mask;
53} eint_grp_save[5];
54
55static u32 irq_uart_mask[CONFIG_SERIAL_SAMSUNG_UARTS];
56
57static int s3c64xx_irq_pm_suspend(struct sys_device *dev, pm_message_t state)
58{
59 struct irq_grp_save *grp = eint_grp_save;
60 int i;
61
62 S3C_PMDBG("%s: suspending IRQs\n", __func__);
63
64 s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
65
66 for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
67 irq_uart_mask[i] = __raw_readl(S3C_VA_UARTx(i) + S3C64XX_UINTM);
68
69 for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
70 grp->con = __raw_readl(S3C64XX_EINT12CON + (i * 4));
71 grp->mask = __raw_readl(S3C64XX_EINT12MASK + (i * 4));
72 grp->fltcon = __raw_readl(S3C64XX_EINT12FLTCON + (i * 4));
73 }
74
75 return 0;
76}
77
78static int s3c64xx_irq_pm_resume(struct sys_device *dev)
79{
80 struct irq_grp_save *grp = eint_grp_save;
81 int i;
82
83 S3C_PMDBG("%s: resuming IRQs\n", __func__);
84
85 s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
86
87 for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
88 __raw_writel(irq_uart_mask[i], S3C_VA_UARTx(i) + S3C64XX_UINTM);
89
90 for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
91 __raw_writel(grp->con, S3C64XX_EINT12CON + (i * 4));
92 __raw_writel(grp->mask, S3C64XX_EINT12MASK + (i * 4));
93 __raw_writel(grp->fltcon, S3C64XX_EINT12FLTCON + (i * 4));
94 }
95
96 S3C_PMDBG("%s: IRQ configuration restored\n", __func__);
97 return 0;
98}
99
100static struct sysdev_driver s3c64xx_irq_driver = {
101 .suspend = s3c64xx_irq_pm_suspend,
102 .resume = s3c64xx_irq_pm_resume,
103};
104
105static int __init s3c64xx_irq_pm_init(void)
106{
107 return sysdev_driver_register(&s3c64xx_sysclass, &s3c64xx_irq_driver);
108}
109
110arch_initcall(s3c64xx_irq_pm_init);
111
diff --git a/arch/arm/plat-s3c64xx/irq.c b/arch/arm/plat-s3c64xx/irq.c
index f22edf7c2d2d..8dc5b6da9789 100644
--- a/arch/arm/plat-s3c64xx/irq.c
+++ b/arch/arm/plat-s3c64xx/irq.c
@@ -14,12 +14,14 @@
14 14
15#include <linux/kernel.h> 15#include <linux/kernel.h>
16#include <linux/interrupt.h> 16#include <linux/interrupt.h>
17#include <linux/serial_core.h>
17#include <linux/irq.h> 18#include <linux/irq.h>
18#include <linux/io.h> 19#include <linux/io.h>
19 20
20#include <asm/hardware/vic.h> 21#include <asm/hardware/vic.h>
21 22
22#include <mach/map.h> 23#include <mach/map.h>
24#include <plat/regs-serial.h>
23#include <plat/regs-timer.h> 25#include <plat/regs-timer.h>
24#include <plat/cpu.h> 26#include <plat/cpu.h>
25 27
@@ -135,9 +137,6 @@ static inline unsigned int s3c_irq_uart_bit(unsigned int irq)
135} 137}
136 138
137/* UART interrupt registers, not worth adding to seperate include header */ 139/* UART interrupt registers, not worth adding to seperate include header */
138#define S3C64XX_UINTP 0x30
139#define S3C64XX_UINTSP 0x34
140#define S3C64XX_UINTM 0x38
141 140
142static void s3c_irq_uart_mask(unsigned int irq) 141static void s3c_irq_uart_mask(unsigned int irq)
143{ 142{
@@ -233,8 +232,8 @@ void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
233 printk(KERN_DEBUG "%s: initialising interrupts\n", __func__); 232 printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
234 233
235 /* initialise the pair of VICs */ 234 /* initialise the pair of VICs */
236 vic_init(S3C_VA_VIC0, S3C_VIC0_BASE, vic0_valid); 235 vic_init(S3C_VA_VIC0, S3C_VIC0_BASE, vic0_valid, 0);
237 vic_init(S3C_VA_VIC1, S3C_VIC1_BASE, vic1_valid); 236 vic_init(S3C_VA_VIC1, S3C_VIC1_BASE, vic1_valid, 0);
238 237
239 /* add the timer sub-irqs */ 238 /* add the timer sub-irqs */
240 239
diff --git a/arch/arm/plat-s3c64xx/pm.c b/arch/arm/plat-s3c64xx/pm.c
new file mode 100644
index 000000000000..07a6516a4f3c
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/pm.c
@@ -0,0 +1,175 @@
1/* linux/arch/arm/plat-s3c64xx/pm.c
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64XX CPU PM support.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/init.h>
16#include <linux/suspend.h>
17#include <linux/serial_core.h>
18#include <linux/io.h>
19
20#include <mach/map.h>
21
22#include <plat/pm.h>
23#include <plat/regs-sys.h>
24#include <plat/regs-gpio.h>
25#include <plat/regs-clock.h>
26#include <plat/regs-syscon-power.h>
27#include <plat/regs-gpio-memport.h>
28
29#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
30#include <plat/gpio-bank-n.h>
31
32void s3c_pm_debug_smdkled(u32 set, u32 clear)
33{
34 unsigned long flags;
35 u32 reg;
36
37 local_irq_save(flags);
38 reg = __raw_readl(S3C64XX_GPNCON);
39 reg &= ~(S3C64XX_GPN_CONMASK(12) | S3C64XX_GPN_CONMASK(13) |
40 S3C64XX_GPN_CONMASK(14) | S3C64XX_GPN_CONMASK(15));
41 reg |= S3C64XX_GPN_OUTPUT(12) | S3C64XX_GPN_OUTPUT(13) |
42 S3C64XX_GPN_OUTPUT(14) | S3C64XX_GPN_OUTPUT(15);
43 __raw_writel(reg, S3C64XX_GPNCON);
44
45 reg = __raw_readl(S3C64XX_GPNDAT);
46 reg &= ~(clear << 12);
47 reg |= set << 12;
48 __raw_writel(reg, S3C64XX_GPNDAT);
49
50 local_irq_restore(flags);
51}
52#endif
53
54static struct sleep_save core_save[] = {
55 SAVE_ITEM(S3C_APLL_LOCK),
56 SAVE_ITEM(S3C_MPLL_LOCK),
57 SAVE_ITEM(S3C_EPLL_LOCK),
58 SAVE_ITEM(S3C_CLK_SRC),
59 SAVE_ITEM(S3C_CLK_DIV0),
60 SAVE_ITEM(S3C_CLK_DIV1),
61 SAVE_ITEM(S3C_CLK_DIV2),
62 SAVE_ITEM(S3C_CLK_OUT),
63 SAVE_ITEM(S3C_HCLK_GATE),
64 SAVE_ITEM(S3C_PCLK_GATE),
65 SAVE_ITEM(S3C_SCLK_GATE),
66 SAVE_ITEM(S3C_MEM0_GATE),
67
68 SAVE_ITEM(S3C_EPLL_CON1),
69 SAVE_ITEM(S3C_EPLL_CON0),
70
71 SAVE_ITEM(S3C64XX_MEM0DRVCON),
72 SAVE_ITEM(S3C64XX_MEM1DRVCON),
73
74#ifndef CONFIG_CPU_FREQ
75 SAVE_ITEM(S3C_APLL_CON),
76 SAVE_ITEM(S3C_MPLL_CON),
77#endif
78};
79
80static struct sleep_save misc_save[] = {
81 SAVE_ITEM(S3C64XX_AHB_CON0),
82 SAVE_ITEM(S3C64XX_AHB_CON1),
83 SAVE_ITEM(S3C64XX_AHB_CON2),
84
85 SAVE_ITEM(S3C64XX_SPCON),
86
87 SAVE_ITEM(S3C64XX_MEM0CONSTOP),
88 SAVE_ITEM(S3C64XX_MEM1CONSTOP),
89 SAVE_ITEM(S3C64XX_MEM0CONSLP0),
90 SAVE_ITEM(S3C64XX_MEM0CONSLP1),
91 SAVE_ITEM(S3C64XX_MEM1CONSLP),
92};
93
94void s3c_pm_configure_extint(void)
95{
96 __raw_writel(s3c_irqwake_eintmask, S3C64XX_EINT_MASK);
97}
98
99void s3c_pm_restore_core(void)
100{
101 __raw_writel(0, S3C64XX_EINT_MASK);
102
103 s3c_pm_debug_smdkled(1 << 2, 0);
104
105 s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
106 s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save));
107}
108
109void s3c_pm_save_core(void)
110{
111 s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save));
112 s3c_pm_do_save(core_save, ARRAY_SIZE(core_save));
113}
114
115/* since both s3c6400 and s3c6410 share the same sleep pm calls, we
116 * put the per-cpu code in here until any new cpu comes along and changes
117 * this.
118 */
119
120#include <plat/regs-gpio.h>
121
122static void s3c64xx_cpu_suspend(void)
123{
124 unsigned long tmp;
125
126 /* set our standby method to sleep */
127
128 tmp = __raw_readl(S3C64XX_PWR_CFG);
129 tmp &= ~S3C64XX_PWRCFG_CFG_WFI_MASK;
130 tmp |= S3C64XX_PWRCFG_CFG_WFI_SLEEP;
131 __raw_writel(tmp, S3C64XX_PWR_CFG);
132
133 /* clear any old wakeup */
134
135 __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT),
136 S3C64XX_WAKEUP_STAT);
137
138 /* set the LED state to 0110 over sleep */
139 s3c_pm_debug_smdkled(3 << 1, 0xf);
140
141 /* issue the standby signal into the pm unit. Note, we
142 * issue a write-buffer drain just in case */
143
144 tmp = 0;
145
146 asm("b 1f\n\t"
147 ".align 5\n\t"
148 "1:\n\t"
149 "mcr p15, 0, %0, c7, c10, 5\n\t"
150 "mcr p15, 0, %0, c7, c10, 4\n\t"
151 "mcr p15, 0, %0, c7, c0, 4" :: "r" (tmp));
152
153 /* we should never get past here */
154
155 panic("sleep resumed to originator?");
156}
157
158static void s3c64xx_pm_prepare(void)
159{
160 /* store address of resume. */
161 __raw_writel(virt_to_phys(s3c_cpu_resume), S3C64XX_INFORM0);
162
163 /* ensure previous wakeup state is cleared before sleeping */
164 __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), S3C64XX_WAKEUP_STAT);
165}
166
167static int s3c64xx_pm_init(void)
168{
169 pm_cpu_prep = s3c64xx_pm_prepare;
170 pm_cpu_sleep = s3c64xx_cpu_suspend;
171 pm_uart_udivslot = 1;
172 return 0;
173}
174
175arch_initcall(s3c64xx_pm_init);
diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c
index 05b17528041e..1debc1f9f987 100644
--- a/arch/arm/plat-s3c64xx/s3c6400-clock.c
+++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c
@@ -133,6 +133,65 @@ static struct clksrc_clk clk_mout_mpll = {
133 .sources = &clk_src_mpll, 133 .sources = &clk_src_mpll,
134}; 134};
135 135
136static unsigned int armclk_mask;
137
138static unsigned long s3c64xx_clk_arm_get_rate(struct clk *clk)
139{
140 unsigned long rate = clk_get_rate(clk->parent);
141 u32 clkdiv;
142
143 /* divisor mask starts at bit0, so no need to shift */
144 clkdiv = __raw_readl(S3C_CLK_DIV0) & armclk_mask;
145
146 return rate / (clkdiv + 1);
147}
148
149static unsigned long s3c64xx_clk_arm_round_rate(struct clk *clk,
150 unsigned long rate)
151{
152 unsigned long parent = clk_get_rate(clk->parent);
153 u32 div;
154
155 if (parent < rate)
156 return rate;
157
158 div = (parent / rate) - 1;
159 if (div > armclk_mask)
160 div = armclk_mask;
161
162 return parent / (div + 1);
163}
164
165static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate)
166{
167 unsigned long parent = clk_get_rate(clk->parent);
168 u32 div;
169 u32 val;
170
171 if (rate < parent / (armclk_mask + 1))
172 return -EINVAL;
173
174 rate = clk_round_rate(clk, rate);
175 div = clk_get_rate(clk->parent) / rate;
176
177 val = __raw_readl(S3C_CLK_DIV0);
178 val &= armclk_mask;
179 val |= (div - 1);
180 __raw_writel(val, S3C_CLK_DIV0);
181
182 return 0;
183
184}
185
186static struct clk clk_arm = {
187 .name = "armclk",
188 .id = -1,
189 .parent = &clk_mout_apll.clk,
190 .get_rate = s3c64xx_clk_arm_get_rate,
191 .set_rate = s3c64xx_clk_arm_set_rate,
192 .round_rate = s3c64xx_clk_arm_round_rate,
193};
194
136static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk) 195static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk)
137{ 196{
138 unsigned long rate = clk_get_rate(clk->parent); 197 unsigned long rate = clk_get_rate(clk->parent);
@@ -520,6 +579,33 @@ static struct clksrc_clk clk_irda = {
520 .reg_divider = S3C_CLK_DIV2, 579 .reg_divider = S3C_CLK_DIV2,
521}; 580};
522 581
582static struct clk *clkset_camif_list[] = {
583 &clk_h2,
584};
585
586static struct clk_sources clkset_camif = {
587 .sources = clkset_camif_list,
588 .nr_sources = ARRAY_SIZE(clkset_camif_list),
589};
590
591static struct clksrc_clk clk_camif = {
592 .clk = {
593 .name = "camera",
594 .id = -1,
595 .ctrlbit = S3C_CLKCON_SCLK_CAM,
596 .enable = s3c64xx_sclk_ctrl,
597 .set_parent = s3c64xx_setparent_clksrc,
598 .get_rate = s3c64xx_getrate_clksrc,
599 .set_rate = s3c64xx_setrate_clksrc,
600 .round_rate = s3c64xx_roundrate_clksrc,
601 },
602 .shift = 0,
603 .mask = 0,
604 .sources = &clkset_camif,
605 .divider_shift = S3C6400_CLKDIV0_CAM_SHIFT,
606 .reg_divider = S3C_CLK_DIV0,
607};
608
523/* Clock initialisation code */ 609/* Clock initialisation code */
524 610
525static struct clksrc_clk *init_parents[] = { 611static struct clksrc_clk *init_parents[] = {
@@ -536,6 +622,7 @@ static struct clksrc_clk *init_parents[] = {
536 &clk_audio0, 622 &clk_audio0,
537 &clk_audio1, 623 &clk_audio1,
538 &clk_irda, 624 &clk_irda,
625 &clk_camif,
539}; 626};
540 627
541static void __init_or_cpufreq s3c6400_set_clksrc(struct clksrc_clk *clk) 628static void __init_or_cpufreq s3c6400_set_clksrc(struct clksrc_clk *clk)
@@ -608,6 +695,7 @@ void __init_or_cpufreq s3c6400_setup_clocks(void)
608 clk_fout_epll.rate = epll; 695 clk_fout_epll.rate = epll;
609 clk_fout_apll.rate = apll; 696 clk_fout_apll.rate = apll;
610 697
698 clk_h2.rate = hclk2;
611 clk_h.rate = hclk; 699 clk_h.rate = hclk;
612 clk_p.rate = pclk; 700 clk_p.rate = pclk;
613 clk_f.rate = fclk; 701 clk_f.rate = fclk;
@@ -635,14 +723,30 @@ static struct clk *clks[] __initdata = {
635 &clk_audio0.clk, 723 &clk_audio0.clk,
636 &clk_audio1.clk, 724 &clk_audio1.clk,
637 &clk_irda.clk, 725 &clk_irda.clk,
726 &clk_camif.clk,
727 &clk_arm,
638}; 728};
639 729
640void __init s3c6400_register_clocks(void) 730/**
731 * s3c6400_register_clocks - register clocks for s3c6400 and above
732 * @armclk_divlimit: Divisor mask for ARMCLK
733 *
734 * Register the clocks for the S3C6400 and above SoC range, such
735 * as ARMCLK and the clocks which have divider chains attached.
736 *
737 * This call does not setup the clocks, which is left to the
738 * s3c6400_setup_clocks() call which may be needed by the cpufreq
739 * or resume code to re-set the clocks if the bootloader has changed
740 * them.
741 */
742void __init s3c6400_register_clocks(unsigned armclk_divlimit)
641{ 743{
642 struct clk *clkp; 744 struct clk *clkp;
643 int ret; 745 int ret;
644 int ptr; 746 int ptr;
645 747
748 armclk_mask = armclk_divlimit;
749
646 for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) { 750 for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
647 clkp = clks[ptr]; 751 clkp = clks[ptr];
648 ret = s3c24xx_register_clock(clkp); 752 ret = s3c24xx_register_clock(clkp);
diff --git a/arch/arm/plat-s3c64xx/setup-sdhci-gpio.c b/arch/arm/plat-s3c64xx/setup-sdhci-gpio.c
new file mode 100644
index 000000000000..5417123b0ac1
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/setup-sdhci-gpio.c
@@ -0,0 +1,55 @@
1/* linux/arch/arm/plat-s3c64xx/setup-sdhci-gpio.c
2 *
3 * Copyright 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * S3C64XX - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/interrupt.h>
17#include <linux/platform_device.h>
18#include <linux/io.h>
19
20#include <mach/gpio.h>
21#include <plat/gpio-cfg.h>
22
23void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
24{
25 unsigned int gpio;
26 unsigned int end;
27
28 end = S3C64XX_GPG(2 + width);
29
30 /* Set all the necessary GPG pins to special-function 0 */
31 for (gpio = S3C64XX_GPG(0); gpio < end; gpio++) {
32 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
33 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
34 }
35
36 s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
37 s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(2));
38}
39
40void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
41{
42 unsigned int gpio;
43 unsigned int end;
44
45 end = S3C64XX_GPH(2 + width);
46
47 /* Set all the necessary GPG pins to special-function 0 */
48 for (gpio = S3C64XX_GPH(0); gpio < end; gpio++) {
49 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
50 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
51 }
52
53 s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
54 s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(3));
55}
diff --git a/arch/arm/plat-s3c64xx/sleep.S b/arch/arm/plat-s3c64xx/sleep.S
new file mode 100644
index 000000000000..8e71fe90a373
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/sleep.S
@@ -0,0 +1,144 @@
1/* linux/0arch/arm/plat-s3c64xx/sleep.S
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64XX CPU sleep code
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/linkage.h>
16#include <asm/assembler.h>
17#include <mach/map.h>
18
19#undef S3C64XX_VA_GPIO
20#define S3C64XX_VA_GPIO (0x0)
21
22#include <plat/regs-gpio.h>
23#include <plat/gpio-bank-n.h>
24
25#define LL_UART (S3C_PA_UART + (0x400 * CONFIG_S3C_LOWLEVEL_UART_PORT))
26
27 .text
28
29 /* s3c_cpu_save
30 *
31 * Save enough processor state to allow the restart of the pm.c
32 * code after resume.
33 *
34 * entry:
35 * r0 = pointer to the save block
36 */
37
38ENTRY(s3c_cpu_save)
39 stmfd sp!, { r4 - r12, lr }
40
41 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
42 mrc p15, 0, r5, c3, c0, 0 @ Domain ID
43 mrc p15, 0, r6, c2, c0, 0 @ Translation Table BASE0
44 mrc p15, 0, r7, c2, c0, 1 @ Translation Table BASE1
45 mrc p15, 0, r8, c2, c0, 2 @ Translation Table Control
46 mrc p15, 0, r9, c1, c0, 0 @ Control register
47 mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register
48 mrc p15, 0, r11, c1, c0, 2 @ Co-processor access controls
49
50 stmia r0, { r4 - r13 } @ Save CP registers and SP
51
52 @@ save our state to ram
53 bl s3c_pm_cb_flushcache
54
55 @@ call final suspend code
56 ldr r0, =pm_cpu_sleep
57 ldr pc, [r0]
58
59 @@ return to the caller, after the MMU is turned on.
60 @@ restore the last bits of the stack and return.
61resume_with_mmu:
62 ldmfd sp!, { r4 - r12, pc } @ return, from sp from s3c_cpu_save
63
64 .data
65
66 /* the next bit is code, but it requires easy access to the
67 * s3c_sleep_save_phys data before the MMU is switched on, so
68 * we store the code that needs this variable in the .data where
69 * the value can be written to (the .text segment is RO).
70 */
71
72 .global s3c_sleep_save_phys
73s3c_sleep_save_phys:
74 .word 0
75
76 /* Sleep magic, the word before the resume entry point so that the
77 * bootloader can check for a resumeable image. */
78
79 .word 0x2bedf00d
80
81 /* s3c_cpu_reusme
82 *
83 * This is the entry point, stored by whatever method the bootloader
84 * requires to get the kernel runnign again. This code expects to be
85 * entered with no caches live and the MMU disabled. It will then
86 * restore the MMU and other basic CP registers saved and restart
87 * the kernel C code to finish the resume code.
88 */
89
90ENTRY(s3c_cpu_resume)
91 msr cpsr_c, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
92 ldr r2, =LL_UART /* for debug */
93
94#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
95 /* Initialise the GPIO state if we are debugging via the SMDK LEDs,
96 * as the uboot version supplied resets these to inputs during the
97 * resume checks.
98 */
99
100 ldr r3, =S3C64XX_PA_GPIO
101 ldr r0, [ r3, #S3C64XX_GPNCON ]
102 bic r0, r0, #(S3C64XX_GPN_CONMASK(12) | S3C64XX_GPN_CONMASK(13) | \
103 S3C64XX_GPN_CONMASK(14) | S3C64XX_GPN_CONMASK(15))
104 orr r0, r0, #(S3C64XX_GPN_OUTPUT(12) | S3C64XX_GPN_OUTPUT(13) | \
105 S3C64XX_GPN_OUTPUT(14) | S3C64XX_GPN_OUTPUT(15))
106 str r0, [ r3, #S3C64XX_GPNCON ]
107
108 ldr r0, [ r3, #S3C64XX_GPNDAT ]
109 bic r0, r0, #0xf << 12 @ GPN12..15
110 orr r0, r0, #1 << 15 @ GPN15
111 str r0, [ r3, #S3C64XX_GPNDAT ]
112#endif
113
114 /* __v6_setup from arch/arm/mm/proc-v6.S, ensure that the caches
115 * are thoroughly cleaned just in case the bootloader didn't do it
116 * for us. */
117 mov r0, #0
118 mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache
119 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
120 mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
121 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
122 @@mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
123 @@mcr p15, 0, r0, c7, c7, 0 @ Invalidate I + D caches
124
125 ldr r0, s3c_sleep_save_phys
126 ldmia r0, { r4 - r13 }
127
128 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
129 mcr p15, 0, r5, c3, c0, 0 @ Domain ID
130 mcr p15, 0, r6, c2, c0, 0 @ Translation Table BASE0
131 mcr p15, 0, r7, c2, c0, 1 @ Translation Table BASE1
132 mcr p15, 0, r8, c2, c0, 2 @ Translation Table Control
133 mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register
134
135 mov r0, #0 @ restore copro access controls
136 mcr p15, 0, r11, c1, c0, 2 @ Co-processor access controls
137 mcr p15, 0, r0, c7, c5, 4
138
139 ldr r2, =resume_with_mmu
140 mcr p15, 0, r9, c1, c0, 0 /* turn mmu back on */
141 nop
142 mov pc, r2 /* jump back */
143
144 .end
diff --git a/drivers/leds/leds-h1940.c b/drivers/leds/leds-h1940.c
index 1aa46a390a0d..173d104d9ff2 100644
--- a/drivers/leds/leds-h1940.c
+++ b/drivers/leds/leds-h1940.c
@@ -16,6 +16,8 @@
16#include <linux/string.h> 16#include <linux/string.h>
17#include <linux/ctype.h> 17#include <linux/ctype.h>
18#include <linux/leds.h> 18#include <linux/leds.h>
19#include <linux/gpio.h>
20
19#include <mach/regs-gpio.h> 21#include <mach/regs-gpio.h>
20#include <mach/hardware.h> 22#include <mach/hardware.h>
21#include <mach/h1940-latch.h> 23#include <mach/h1940-latch.h>
diff --git a/drivers/leds/leds-s3c24xx.c b/drivers/leds/leds-s3c24xx.c
index aa2e7ae0cdae..aa7acf3b9224 100644
--- a/drivers/leds/leds-s3c24xx.c
+++ b/drivers/leds/leds-s3c24xx.c
@@ -15,6 +15,7 @@
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/platform_device.h> 16#include <linux/platform_device.h>
17#include <linux/leds.h> 17#include <linux/leds.h>
18#include <linux/gpio.h>
18 19
19#include <mach/hardware.h> 20#include <mach/hardware.h>
20#include <mach/regs-gpio.h> 21#include <mach/regs-gpio.h>
diff --git a/drivers/mmc/host/s3cmci.c b/drivers/mmc/host/s3cmci.c
index 2db166b7096f..4eb4f37544ab 100644
--- a/drivers/mmc/host/s3cmci.c
+++ b/drivers/mmc/host/s3cmci.c
@@ -17,6 +17,7 @@
17#include <linux/mmc/host.h> 17#include <linux/mmc/host.h>
18#include <linux/platform_device.h> 18#include <linux/platform_device.h>
19#include <linux/cpufreq.h> 19#include <linux/cpufreq.h>
20#include <linux/gpio.h>
20#include <linux/irq.h> 21#include <linux/irq.h>
21#include <linux/io.h> 22#include <linux/io.h>
22 23
@@ -789,7 +790,7 @@ static void s3cmci_dma_setup(struct s3cmci_host *host,
789 790
790 last_source = source; 791 last_source = source;
791 792
792 s3c2410_dma_devconfig(host->dma, source, 3, 793 s3c2410_dma_devconfig(host->dma, source,
793 host->mem->start + host->sdidata); 794 host->mem->start + host->sdidata);
794 795
795 if (!setup_ok) { 796 if (!setup_ok) {
@@ -1121,7 +1122,7 @@ static void s3cmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1121 case MMC_POWER_OFF: 1122 case MMC_POWER_OFF:
1122 default: 1123 default:
1123 s3c2410_gpio_setpin(S3C2410_GPE5, 0); 1124 s3c2410_gpio_setpin(S3C2410_GPE5, 0);
1124 s3c2410_gpio_cfgpin(S3C2410_GPE5, S3C2410_GPE5_OUTP); 1125 s3c2410_gpio_cfgpin(S3C2410_GPE5, S3C2410_GPIO_OUTPUT);
1125 1126
1126 if (host->is2440) 1127 if (host->is2440)
1127 mci_con |= S3C2440_SDICON_SDRESET; 1128 mci_con |= S3C2440_SDICON_SDRESET;
diff --git a/drivers/spi/spi_s3c24xx_gpio.c b/drivers/spi/spi_s3c24xx_gpio.c
index f2447a5476bb..bbf9371cd284 100644
--- a/drivers/spi/spi_s3c24xx_gpio.c
+++ b/drivers/spi/spi_s3c24xx_gpio.c
@@ -17,6 +17,7 @@
17#include <linux/spinlock.h> 17#include <linux/spinlock.h>
18#include <linux/workqueue.h> 18#include <linux/workqueue.h>
19#include <linux/platform_device.h> 19#include <linux/platform_device.h>
20#include <linux/gpio.h>
20 21
21#include <linux/spi/spi.h> 22#include <linux/spi/spi.h>
22#include <linux/spi/spi_bitbang.h> 23#include <linux/spi/spi_bitbang.h>
diff --git a/sound/soc/s3c24xx/s3c2412-i2s.c b/sound/soc/s3c24xx/s3c2412-i2s.c
index b7e0b3f0bfc8..c35b74b2d1da 100644
--- a/sound/soc/s3c24xx/s3c2412-i2s.c
+++ b/sound/soc/s3c24xx/s3c2412-i2s.c
@@ -20,6 +20,7 @@
20#include <linux/module.h> 20#include <linux/module.h>
21#include <linux/device.h> 21#include <linux/device.h>
22#include <linux/delay.h> 22#include <linux/delay.h>
23#include <linux/gpio.h>
23#include <linux/clk.h> 24#include <linux/clk.h>
24#include <linux/kernel.h> 25#include <linux/kernel.h>
25#include <linux/io.h> 26#include <linux/io.h>
diff --git a/sound/soc/s3c24xx/s3c2443-ac97.c b/sound/soc/s3c24xx/s3c2443-ac97.c
index 3698f707c44d..3f03d5ddfacd 100644
--- a/sound/soc/s3c24xx/s3c2443-ac97.c
+++ b/sound/soc/s3c24xx/s3c2443-ac97.c
@@ -19,6 +19,7 @@
19#include <linux/io.h> 19#include <linux/io.h>
20#include <linux/wait.h> 20#include <linux/wait.h>
21#include <linux/delay.h> 21#include <linux/delay.h>
22#include <linux/gpio.h>
22#include <linux/clk.h> 23#include <linux/clk.h>
23 24
24#include <sound/core.h> 25#include <sound/core.h>
diff --git a/sound/soc/s3c24xx/s3c24xx-i2s.c b/sound/soc/s3c24xx/s3c24xx-i2s.c
index cc066964dad6..556e35f0ab73 100644
--- a/sound/soc/s3c24xx/s3c24xx-i2s.c
+++ b/sound/soc/s3c24xx/s3c24xx-i2s.c
@@ -21,6 +21,8 @@
21#include <linux/clk.h> 21#include <linux/clk.h>
22#include <linux/jiffies.h> 22#include <linux/jiffies.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/gpio.h>
25
24#include <sound/core.h> 26#include <sound/core.h>
25#include <sound/pcm.h> 27#include <sound/pcm.h>
26#include <sound/pcm_params.h> 28#include <sound/pcm_params.h>
diff --git a/sound/soc/s3c24xx/s3c24xx-pcm.c b/sound/soc/s3c24xx/s3c24xx-pcm.c
index 169ddad31575..eecfa5eba06b 100644
--- a/sound/soc/s3c24xx/s3c24xx-pcm.c
+++ b/sound/soc/s3c24xx/s3c24xx-pcm.c
@@ -218,24 +218,17 @@ static int s3c24xx_pcm_prepare(struct snd_pcm_substream *substream)
218 * sync to pclk, half-word transfers to the IIS-FIFO. */ 218 * sync to pclk, half-word transfers to the IIS-FIFO. */
219 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 219 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
220 s3c2410_dma_devconfig(prtd->params->channel, 220 s3c2410_dma_devconfig(prtd->params->channel,
221 S3C2410_DMASRC_MEM, S3C2410_DISRCC_INC | 221 S3C2410_DMASRC_MEM,
222 S3C2410_DISRCC_APB, prtd->params->dma_addr); 222 prtd->params->dma_addr);
223
224 s3c2410_dma_config(prtd->params->channel,
225 prtd->params->dma_size,
226 S3C2410_DCON_SYNC_PCLK |
227 S3C2410_DCON_HANDSHAKE);
228 } else { 223 } else {
229 s3c2410_dma_config(prtd->params->channel,
230 prtd->params->dma_size,
231 S3C2410_DCON_HANDSHAKE |
232 S3C2410_DCON_SYNC_PCLK);
233
234 s3c2410_dma_devconfig(prtd->params->channel, 224 s3c2410_dma_devconfig(prtd->params->channel,
235 S3C2410_DMASRC_HW, 0x3, 225 S3C2410_DMASRC_HW,
236 prtd->params->dma_addr); 226 prtd->params->dma_addr);
237 } 227 }
238 228
229 s3c2410_dma_config(prtd->params->channel,
230 prtd->params->dma_size);
231
239 /* flush the DMA channel */ 232 /* flush the DMA channel */
240 s3c2410_dma_ctrl(prtd->params->channel, S3C2410_DMAOP_FLUSH); 233 s3c2410_dma_ctrl(prtd->params->channel, S3C2410_DMAOP_FLUSH);
241 prtd->dma_loaded = 0; 234 prtd->dma_loaded = 0;