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-rw-r--r--arch/sparc64/kernel/ebus.c3
-rw-r--r--arch/sparc64/kernel/pci.c2
-rw-r--r--arch/sparc64/kernel/pci_common.c2
-rw-r--r--arch/sparc64/kernel/pci_fire.c1
-rw-r--r--arch/sparc64/kernel/pci_impl.h113
-rw-r--r--arch/sparc64/kernel/pci_iommu.c4
-rw-r--r--arch/sparc64/kernel/pci_psycho.c2
-rw-r--r--arch/sparc64/kernel/pci_sabre.c2
-rw-r--r--arch/sparc64/kernel/pci_schizo.c3
-rw-r--r--arch/sparc64/kernel/pci_sun4v.c1
-rw-r--r--include/asm-sparc64/pbm.h132
11 files changed, 124 insertions, 141 deletions
diff --git a/arch/sparc64/kernel/ebus.c b/arch/sparc64/kernel/ebus.c
index 0ace17bafba4..ad55a9bb50dd 100644
--- a/arch/sparc64/kernel/ebus.c
+++ b/arch/sparc64/kernel/ebus.c
@@ -13,16 +13,17 @@
13#include <linux/string.h> 13#include <linux/string.h>
14#include <linux/interrupt.h> 14#include <linux/interrupt.h>
15#include <linux/delay.h> 15#include <linux/delay.h>
16#include <linux/pci.h>
16 17
17#include <asm/system.h> 18#include <asm/system.h>
18#include <asm/page.h> 19#include <asm/page.h>
19#include <asm/pbm.h>
20#include <asm/ebus.h> 20#include <asm/ebus.h>
21#include <asm/oplib.h> 21#include <asm/oplib.h>
22#include <asm/prom.h> 22#include <asm/prom.h>
23#include <asm/of_device.h> 23#include <asm/of_device.h>
24#include <asm/bpp.h> 24#include <asm/bpp.h>
25#include <asm/irq.h> 25#include <asm/irq.h>
26#include <asm/io.h>
26 27
27/* EBUS dma library. */ 28/* EBUS dma library. */
28 29
diff --git a/arch/sparc64/kernel/pci.c b/arch/sparc64/kernel/pci.c
index ca290d6de64d..d85e1ed7c3e4 100644
--- a/arch/sparc64/kernel/pci.c
+++ b/arch/sparc64/kernel/pci.c
@@ -14,12 +14,12 @@
14#include <linux/sched.h> 14#include <linux/sched.h>
15#include <linux/capability.h> 15#include <linux/capability.h>
16#include <linux/errno.h> 16#include <linux/errno.h>
17#include <linux/pci.h>
17#include <linux/msi.h> 18#include <linux/msi.h>
18#include <linux/irq.h> 19#include <linux/irq.h>
19#include <linux/init.h> 20#include <linux/init.h>
20 21
21#include <asm/uaccess.h> 22#include <asm/uaccess.h>
22#include <asm/pbm.h>
23#include <asm/pgtable.h> 23#include <asm/pgtable.h>
24#include <asm/irq.h> 24#include <asm/irq.h>
25#include <asm/ebus.h> 25#include <asm/ebus.h>
diff --git a/arch/sparc64/kernel/pci_common.c b/arch/sparc64/kernel/pci_common.c
index 8dcc7cc4ec71..76faaa8135dd 100644
--- a/arch/sparc64/kernel/pci_common.c
+++ b/arch/sparc64/kernel/pci_common.c
@@ -9,9 +9,9 @@
9#include <linux/pci.h> 9#include <linux/pci.h>
10#include <linux/device.h> 10#include <linux/device.h>
11 11
12#include <asm/pbm.h>
13#include <asm/prom.h> 12#include <asm/prom.h>
14#include <asm/of_device.h> 13#include <asm/of_device.h>
14#include <asm/oplib.h>
15 15
16#include "pci_impl.h" 16#include "pci_impl.h"
17 17
diff --git a/arch/sparc64/kernel/pci_fire.c b/arch/sparc64/kernel/pci_fire.c
index 5df31300b4d9..2e0eb4ee8f71 100644
--- a/arch/sparc64/kernel/pci_fire.c
+++ b/arch/sparc64/kernel/pci_fire.c
@@ -7,7 +7,6 @@
7#include <linux/slab.h> 7#include <linux/slab.h>
8#include <linux/init.h> 8#include <linux/init.h>
9 9
10#include <asm/pbm.h>
11#include <asm/oplib.h> 10#include <asm/oplib.h>
12#include <asm/prom.h> 11#include <asm/prom.h>
13 12
diff --git a/arch/sparc64/kernel/pci_impl.h b/arch/sparc64/kernel/pci_impl.h
index 61505c19fd1e..8e38023868aa 100644
--- a/arch/sparc64/kernel/pci_impl.h
+++ b/arch/sparc64/kernel/pci_impl.h
@@ -8,8 +8,119 @@
8 8
9#include <linux/types.h> 9#include <linux/types.h>
10#include <linux/spinlock.h> 10#include <linux/spinlock.h>
11#include <linux/pci.h>
12#include <linux/msi.h>
11#include <asm/io.h> 13#include <asm/io.h>
12#include <asm/prom.h> 14#include <asm/prom.h>
15#include <asm/iommu.h>
16
17/* The abstraction used here is that there are PCI controllers,
18 * each with one (Sabre) or two (PSYCHO/SCHIZO) PCI bus modules
19 * underneath. Each PCI bus module uses an IOMMU (shared by both
20 * PBMs of a controller, or per-PBM), and if a streaming buffer
21 * is present, each PCI bus module has it's own. (ie. the IOMMU
22 * might be shared between PBMs, the STC is never shared)
23 * Furthermore, each PCI bus module controls it's own autonomous
24 * PCI bus.
25 */
26
27#define PCI_STC_FLUSHFLAG_INIT(STC) \
28 (*((STC)->strbuf_flushflag) = 0UL)
29#define PCI_STC_FLUSHFLAG_SET(STC) \
30 (*((STC)->strbuf_flushflag) != 0UL)
31
32struct pci_controller_info;
33
34struct pci_pbm_info {
35 struct pci_pbm_info *next;
36 int index;
37
38 /* PCI controller we sit under. */
39 struct pci_controller_info *parent;
40
41 /* Physical address base of controller registers. */
42 unsigned long controller_regs;
43
44 /* Physical address base of PBM registers. */
45 unsigned long pbm_regs;
46
47 /* Physical address of DMA sync register, if any. */
48 unsigned long sync_reg;
49
50 /* Opaque 32-bit system bus Port ID. */
51 u32 portid;
52
53 /* Opaque 32-bit handle used for hypervisor calls. */
54 u32 devhandle;
55
56 /* Chipset version information. */
57 int chip_type;
58#define PBM_CHIP_TYPE_SABRE 1
59#define PBM_CHIP_TYPE_PSYCHO 2
60#define PBM_CHIP_TYPE_SCHIZO 3
61#define PBM_CHIP_TYPE_SCHIZO_PLUS 4
62#define PBM_CHIP_TYPE_TOMATILLO 5
63 int chip_version;
64 int chip_revision;
65
66 /* Name used for top-level resources. */
67 char *name;
68
69 /* OBP specific information. */
70 struct device_node *prom_node;
71 u64 ino_bitmap;
72
73 /* PBM I/O and Memory space resources. */
74 struct resource io_space;
75 struct resource mem_space;
76
77 /* Base of PCI Config space, can be per-PBM or shared. */
78 unsigned long config_space;
79
80 /* State of 66MHz capabilities on this PBM. */
81 int is_66mhz_capable;
82 int all_devs_66mhz;
83
84#ifdef CONFIG_PCI_MSI
85 /* MSI info. */
86 u32 msiq_num;
87 u32 msiq_ent_count;
88 u32 msiq_first;
89 u32 msiq_first_devino;
90 u32 msi_num;
91 u32 msi_first;
92 u32 msi_data_mask;
93 u32 msix_data_width;
94 u64 msi32_start;
95 u64 msi64_start;
96 u32 msi32_len;
97 u32 msi64_len;
98 void *msi_queues;
99 unsigned long *msi_bitmap;
100 int (*setup_msi_irq)(unsigned int *virt_irq_p, struct pci_dev *pdev,
101 struct msi_desc *entry);
102 void (*teardown_msi_irq)(unsigned int virt_irq, struct pci_dev *pdev);
103#endif /* !(CONFIG_PCI_MSI) */
104
105 /* This PBM's streaming buffer. */
106 struct strbuf stc;
107
108 /* IOMMU state, potentially shared by both PBM segments. */
109 struct iommu *iommu;
110
111 /* Now things for the actual PCI bus probes. */
112 unsigned int pci_first_busno;
113 unsigned int pci_last_busno;
114 struct pci_bus *pci_bus;
115 void (*scan_bus)(struct pci_pbm_info *);
116 struct pci_ops *pci_ops;
117};
118
119struct pci_controller_info {
120 /* The PCI bus modules controlled by us. */
121 struct pci_pbm_info pbm_A;
122 struct pci_pbm_info pbm_B;
123};
13 124
14extern struct pci_pbm_info *pci_pbm_root; 125extern struct pci_pbm_info *pci_pbm_root;
15extern unsigned long pci_memspace_mask; 126extern unsigned long pci_memspace_mask;
@@ -17,6 +128,8 @@ extern unsigned long pci_memspace_mask;
17extern int pci_num_pbms; 128extern int pci_num_pbms;
18 129
19/* PCI bus scanning and fixup support. */ 130/* PCI bus scanning and fixup support. */
131extern void pci_iommu_table_init(struct iommu *iommu, int tsbsize,
132 u32 dma_offset, u32 dma_addr_mask);
20extern void pci_get_pbm_props(struct pci_pbm_info *pbm); 133extern void pci_get_pbm_props(struct pci_pbm_info *pbm);
21extern struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm); 134extern struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm);
22extern void pci_determine_mem_io_space(struct pci_pbm_info *pbm); 135extern void pci_determine_mem_io_space(struct pci_pbm_info *pbm);
diff --git a/arch/sparc64/kernel/pci_iommu.c b/arch/sparc64/kernel/pci_iommu.c
index 9e405cbbcb0d..dfd6f9f4790b 100644
--- a/arch/sparc64/kernel/pci_iommu.c
+++ b/arch/sparc64/kernel/pci_iommu.c
@@ -8,10 +8,12 @@
8#include <linux/sched.h> 8#include <linux/sched.h>
9#include <linux/mm.h> 9#include <linux/mm.h>
10#include <linux/delay.h> 10#include <linux/delay.h>
11#include <linux/pci.h>
11 12
12#include <asm/pbm.h> 13#include <asm/oplib.h>
13 14
14#include "iommu_common.h" 15#include "iommu_common.h"
16#include "pci_impl.h"
15 17
16#define PCI_STC_CTXMATCH_ADDR(STC, CTX) \ 18#define PCI_STC_CTXMATCH_ADDR(STC, CTX) \
17 ((STC)->strbuf_ctxmatch_base + ((CTX) << 3)) 19 ((STC)->strbuf_ctxmatch_base + ((CTX) << 3))
diff --git a/arch/sparc64/kernel/pci_psycho.c b/arch/sparc64/kernel/pci_psycho.c
index 8ef808348993..401e5dfe9bd5 100644
--- a/arch/sparc64/kernel/pci_psycho.c
+++ b/arch/sparc64/kernel/pci_psycho.c
@@ -12,12 +12,12 @@
12#include <linux/slab.h> 12#include <linux/slab.h>
13#include <linux/interrupt.h> 13#include <linux/interrupt.h>
14 14
15#include <asm/pbm.h>
16#include <asm/iommu.h> 15#include <asm/iommu.h>
17#include <asm/irq.h> 16#include <asm/irq.h>
18#include <asm/starfire.h> 17#include <asm/starfire.h>
19#include <asm/prom.h> 18#include <asm/prom.h>
20#include <asm/of_device.h> 19#include <asm/of_device.h>
20#include <asm/oplib.h>
21 21
22#include "pci_impl.h" 22#include "pci_impl.h"
23#include "iommu_common.h" 23#include "iommu_common.h"
diff --git a/arch/sparc64/kernel/pci_sabre.c b/arch/sparc64/kernel/pci_sabre.c
index 733ab366a3d4..863308c8955d 100644
--- a/arch/sparc64/kernel/pci_sabre.c
+++ b/arch/sparc64/kernel/pci_sabre.c
@@ -13,12 +13,12 @@
13#include <linux/interrupt.h> 13#include <linux/interrupt.h>
14 14
15#include <asm/apb.h> 15#include <asm/apb.h>
16#include <asm/pbm.h>
17#include <asm/iommu.h> 16#include <asm/iommu.h>
18#include <asm/irq.h> 17#include <asm/irq.h>
19#include <asm/smp.h> 18#include <asm/smp.h>
20#include <asm/oplib.h> 19#include <asm/oplib.h>
21#include <asm/prom.h> 20#include <asm/prom.h>
21#include <asm/of_device.h>
22 22
23#include "pci_impl.h" 23#include "pci_impl.h"
24#include "iommu_common.h" 24#include "iommu_common.h"
diff --git a/arch/sparc64/kernel/pci_schizo.c b/arch/sparc64/kernel/pci_schizo.c
index 72743acecbc0..312f3e4f2ed4 100644
--- a/arch/sparc64/kernel/pci_schizo.c
+++ b/arch/sparc64/kernel/pci_schizo.c
@@ -10,12 +10,13 @@
10#include <linux/slab.h> 10#include <linux/slab.h>
11#include <linux/interrupt.h> 11#include <linux/interrupt.h>
12 12
13#include <asm/pbm.h>
14#include <asm/iommu.h> 13#include <asm/iommu.h>
15#include <asm/irq.h> 14#include <asm/irq.h>
16#include <asm/upa.h> 15#include <asm/upa.h>
17#include <asm/pstate.h> 16#include <asm/pstate.h>
18#include <asm/prom.h> 17#include <asm/prom.h>
18#include <asm/of_device.h>
19#include <asm/oplib.h>
19 20
20#include "pci_impl.h" 21#include "pci_impl.h"
21#include "iommu_common.h" 22#include "iommu_common.h"
diff --git a/arch/sparc64/kernel/pci_sun4v.c b/arch/sparc64/kernel/pci_sun4v.c
index ce46b0471693..0c76a8891a96 100644
--- a/arch/sparc64/kernel/pci_sun4v.c
+++ b/arch/sparc64/kernel/pci_sun4v.c
@@ -13,7 +13,6 @@
13#include <linux/irq.h> 13#include <linux/irq.h>
14#include <linux/msi.h> 14#include <linux/msi.h>
15 15
16#include <asm/pbm.h>
17#include <asm/iommu.h> 16#include <asm/iommu.h>
18#include <asm/irq.h> 17#include <asm/irq.h>
19#include <asm/upa.h> 18#include <asm/upa.h>
diff --git a/include/asm-sparc64/pbm.h b/include/asm-sparc64/pbm.h
deleted file mode 100644
index d99e0468c7e4..000000000000
--- a/include/asm-sparc64/pbm.h
+++ /dev/null
@@ -1,132 +0,0 @@
1/* pbm.h: UltraSparc PCI controller software state.
2 *
3 * Copyright (C) 1997, 1998, 1999, 2007 David S. Miller (davem@davemloft.net)
4 */
5
6#ifndef __SPARC64_PBM_H
7#define __SPARC64_PBM_H
8
9#include <linux/types.h>
10#include <linux/pci.h>
11#include <linux/ioport.h>
12#include <linux/spinlock.h>
13#include <linux/msi.h>
14
15#include <asm/io.h>
16#include <asm/page.h>
17#include <asm/oplib.h>
18#include <asm/prom.h>
19#include <asm/of_device.h>
20#include <asm/iommu.h>
21
22/* The abstraction used here is that there are PCI controllers,
23 * each with one (Sabre) or two (PSYCHO/SCHIZO) PCI bus modules
24 * underneath. Each PCI bus module uses an IOMMU (shared by both
25 * PBMs of a controller, or per-PBM), and if a streaming buffer
26 * is present, each PCI bus module has it's own. (ie. the IOMMU
27 * might be shared between PBMs, the STC is never shared)
28 * Furthermore, each PCI bus module controls it's own autonomous
29 * PCI bus.
30 */
31
32extern void pci_iommu_table_init(struct iommu *iommu, int tsbsize, u32 dma_offset, u32 dma_addr_mask);
33
34#define PCI_STC_FLUSHFLAG_INIT(STC) \
35 (*((STC)->strbuf_flushflag) = 0UL)
36#define PCI_STC_FLUSHFLAG_SET(STC) \
37 (*((STC)->strbuf_flushflag) != 0UL)
38
39struct pci_controller_info;
40
41struct pci_pbm_info {
42 struct pci_pbm_info *next;
43 int index;
44
45 /* PCI controller we sit under. */
46 struct pci_controller_info *parent;
47
48 /* Physical address base of controller registers. */
49 unsigned long controller_regs;
50
51 /* Physical address base of PBM registers. */
52 unsigned long pbm_regs;
53
54 /* Physical address of DMA sync register, if any. */
55 unsigned long sync_reg;
56
57 /* Opaque 32-bit system bus Port ID. */
58 u32 portid;
59
60 /* Opaque 32-bit handle used for hypervisor calls. */
61 u32 devhandle;
62
63 /* Chipset version information. */
64 int chip_type;
65#define PBM_CHIP_TYPE_SABRE 1
66#define PBM_CHIP_TYPE_PSYCHO 2
67#define PBM_CHIP_TYPE_SCHIZO 3
68#define PBM_CHIP_TYPE_SCHIZO_PLUS 4
69#define PBM_CHIP_TYPE_TOMATILLO 5
70 int chip_version;
71 int chip_revision;
72
73 /* Name used for top-level resources. */
74 char *name;
75
76 /* OBP specific information. */
77 struct device_node *prom_node;
78 u64 ino_bitmap;
79
80 /* PBM I/O and Memory space resources. */
81 struct resource io_space;
82 struct resource mem_space;
83
84 /* Base of PCI Config space, can be per-PBM or shared. */
85 unsigned long config_space;
86
87 /* State of 66MHz capabilities on this PBM. */
88 int is_66mhz_capable;
89 int all_devs_66mhz;
90
91#ifdef CONFIG_PCI_MSI
92 /* MSI info. */
93 u32 msiq_num;
94 u32 msiq_ent_count;
95 u32 msiq_first;
96 u32 msiq_first_devino;
97 u32 msi_num;
98 u32 msi_first;
99 u32 msi_data_mask;
100 u32 msix_data_width;
101 u64 msi32_start;
102 u64 msi64_start;
103 u32 msi32_len;
104 u32 msi64_len;
105 void *msi_queues;
106 unsigned long *msi_bitmap;
107 int (*setup_msi_irq)(unsigned int *virt_irq_p, struct pci_dev *pdev,
108 struct msi_desc *entry);
109 void (*teardown_msi_irq)(unsigned int virt_irq, struct pci_dev *pdev);
110#endif /* !(CONFIG_PCI_MSI) */
111
112 /* This PBM's streaming buffer. */
113 struct strbuf stc;
114
115 /* IOMMU state, potentially shared by both PBM segments. */
116 struct iommu *iommu;
117
118 /* Now things for the actual PCI bus probes. */
119 unsigned int pci_first_busno;
120 unsigned int pci_last_busno;
121 struct pci_bus *pci_bus;
122 void (*scan_bus)(struct pci_pbm_info *);
123 struct pci_ops *pci_ops;
124};
125
126struct pci_controller_info {
127 /* The PCI bus modules controlled by us. */
128 struct pci_pbm_info pbm_A;
129 struct pci_pbm_info pbm_B;
130};
131
132#endif /* !(__SPARC64_PBM_H) */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-27 07:56:45 -0500