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-rw-r--r--arch/x86_64/kernel/i8259.c40
-rw-r--r--arch/x86_64/kernel/io_apic.c32
-rw-r--r--include/asm-x86_64/hw_irq.h18
3 files changed, 53 insertions, 37 deletions
diff --git a/arch/x86_64/kernel/i8259.c b/arch/x86_64/kernel/i8259.c
index 103517d9f8e6..45d85630196a 100644
--- a/arch/x86_64/kernel/i8259.c
+++ b/arch/x86_64/kernel/i8259.c
@@ -299,7 +299,7 @@ void init_8259A(int auto_eoi)
299 * outb_p - this has to work on a wide range of PC hardware. 299 * outb_p - this has to work on a wide range of PC hardware.
300 */ 300 */
301 outb_p(0x11, 0x20); /* ICW1: select 8259A-1 init */ 301 outb_p(0x11, 0x20); /* ICW1: select 8259A-1 init */
302 outb_p(0x20 + 0, 0x21); /* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */ 302 outb_p(IRQ0_VECTOR, 0x21); /* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */
303 outb_p(0x04, 0x21); /* 8259A-1 (the master) has a slave on IR2 */ 303 outb_p(0x04, 0x21); /* 8259A-1 (the master) has a slave on IR2 */
304 if (auto_eoi) 304 if (auto_eoi)
305 outb_p(0x03, 0x21); /* master does Auto EOI */ 305 outb_p(0x03, 0x21); /* master does Auto EOI */
@@ -307,7 +307,7 @@ void init_8259A(int auto_eoi)
307 outb_p(0x01, 0x21); /* master expects normal EOI */ 307 outb_p(0x01, 0x21); /* master expects normal EOI */
308 308
309 outb_p(0x11, 0xA0); /* ICW1: select 8259A-2 init */ 309 outb_p(0x11, 0xA0); /* ICW1: select 8259A-2 init */
310 outb_p(0x20 + 8, 0xA1); /* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */ 310 outb_p(IRQ8_VECTOR, 0xA1); /* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */
311 outb_p(0x02, 0xA1); /* 8259A-2 is a slave on master's IR2 */ 311 outb_p(0x02, 0xA1); /* 8259A-2 is a slave on master's IR2 */
312 outb_p(0x01, 0xA1); /* (slave's support for AEOI in flat mode 312 outb_p(0x01, 0xA1); /* (slave's support for AEOI in flat mode
313 is to be investigated) */ 313 is to be investigated) */
@@ -398,24 +398,24 @@ device_initcall(i8259A_init_sysfs);
398 398
399static struct irqaction irq2 = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL}; 399static struct irqaction irq2 = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL};
400DEFINE_PER_CPU(vector_irq_t, vector_irq) = { 400DEFINE_PER_CPU(vector_irq_t, vector_irq) = {
401 [0 ... FIRST_EXTERNAL_VECTOR - 1] = -1, 401 [0 ... IRQ0_VECTOR - 1] = -1,
402 [FIRST_EXTERNAL_VECTOR + 0] = 0, 402 [IRQ0_VECTOR] = 0,
403 [FIRST_EXTERNAL_VECTOR + 1] = 1, 403 [IRQ1_VECTOR] = 1,
404 [FIRST_EXTERNAL_VECTOR + 2] = 2, 404 [IRQ2_VECTOR] = 2,
405 [FIRST_EXTERNAL_VECTOR + 3] = 3, 405 [IRQ3_VECTOR] = 3,
406 [FIRST_EXTERNAL_VECTOR + 4] = 4, 406 [IRQ4_VECTOR] = 4,
407 [FIRST_EXTERNAL_VECTOR + 5] = 5, 407 [IRQ5_VECTOR] = 5,
408 [FIRST_EXTERNAL_VECTOR + 6] = 6, 408 [IRQ6_VECTOR] = 6,
409 [FIRST_EXTERNAL_VECTOR + 7] = 7, 409 [IRQ7_VECTOR] = 7,
410 [FIRST_EXTERNAL_VECTOR + 8] = 8, 410 [IRQ8_VECTOR] = 8,
411 [FIRST_EXTERNAL_VECTOR + 9] = 9, 411 [IRQ9_VECTOR] = 9,
412 [FIRST_EXTERNAL_VECTOR + 10] = 10, 412 [IRQ10_VECTOR] = 10,
413 [FIRST_EXTERNAL_VECTOR + 11] = 11, 413 [IRQ11_VECTOR] = 11,
414 [FIRST_EXTERNAL_VECTOR + 12] = 12, 414 [IRQ12_VECTOR] = 12,
415 [FIRST_EXTERNAL_VECTOR + 13] = 13, 415 [IRQ13_VECTOR] = 13,
416 [FIRST_EXTERNAL_VECTOR + 14] = 14, 416 [IRQ14_VECTOR] = 14,
417 [FIRST_EXTERNAL_VECTOR + 15] = 15, 417 [IRQ15_VECTOR] = 15,
418 [FIRST_EXTERNAL_VECTOR + 16 ... NR_VECTORS - 1] = -1 418 [IRQ15_VECTOR + 1 ... NR_VECTORS - 1] = -1
419}; 419};
420 420
421void __init init_ISA_irqs (void) 421void __init init_ISA_irqs (void)
diff --git a/arch/x86_64/kernel/io_apic.c b/arch/x86_64/kernel/io_apic.c
index 79fa7b2bbee4..8dede0bd2267 100644
--- a/arch/x86_64/kernel/io_apic.c
+++ b/arch/x86_64/kernel/io_apic.c
@@ -54,22 +54,22 @@ struct irq_cfg {
54 54
55/* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ 55/* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
56struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = { 56struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
57 [0] = { .domain = CPU_MASK_ALL, .vector = FIRST_EXTERNAL_VECTOR + 0 }, 57 [0] = { .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
58 [1] = { .domain = CPU_MASK_ALL, .vector = FIRST_EXTERNAL_VECTOR + 1 }, 58 [1] = { .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
59 [2] = { .domain = CPU_MASK_ALL, .vector = FIRST_EXTERNAL_VECTOR + 2 }, 59 [2] = { .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
60 [3] = { .domain = CPU_MASK_ALL, .vector = FIRST_EXTERNAL_VECTOR + 3 }, 60 [3] = { .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
61 [4] = { .domain = CPU_MASK_ALL, .vector = FIRST_EXTERNAL_VECTOR + 4 }, 61 [4] = { .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
62 [5] = { .domain = CPU_MASK_ALL, .vector = FIRST_EXTERNAL_VECTOR + 5 }, 62 [5] = { .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
63 [6] = { .domain = CPU_MASK_ALL, .vector = FIRST_EXTERNAL_VECTOR + 6 }, 63 [6] = { .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
64 [7] = { .domain = CPU_MASK_ALL, .vector = FIRST_EXTERNAL_VECTOR + 7 }, 64 [7] = { .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
65 [8] = { .domain = CPU_MASK_ALL, .vector = FIRST_EXTERNAL_VECTOR + 8 }, 65 [8] = { .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
66 [9] = { .domain = CPU_MASK_ALL, .vector = FIRST_EXTERNAL_VECTOR + 9 }, 66 [9] = { .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
67 [10] = { .domain = CPU_MASK_ALL, .vector = FIRST_EXTERNAL_VECTOR + 10 }, 67 [10] = { .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
68 [11] = { .domain = CPU_MASK_ALL, .vector = FIRST_EXTERNAL_VECTOR + 11 }, 68 [11] = { .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
69 [12] = { .domain = CPU_MASK_ALL, .vector = FIRST_EXTERNAL_VECTOR + 12 }, 69 [12] = { .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
70 [13] = { .domain = CPU_MASK_ALL, .vector = FIRST_EXTERNAL_VECTOR + 13 }, 70 [13] = { .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
71 [14] = { .domain = CPU_MASK_ALL, .vector = FIRST_EXTERNAL_VECTOR + 14 }, 71 [14] = { .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
72 [15] = { .domain = CPU_MASK_ALL, .vector = FIRST_EXTERNAL_VECTOR + 15 }, 72 [15] = { .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
73}; 73};
74 74
75static int assign_irq_vector(int irq, cpumask_t mask); 75static int assign_irq_vector(int irq, cpumask_t mask);
diff --git a/include/asm-x86_64/hw_irq.h b/include/asm-x86_64/hw_irq.h
index 552df5f10a6d..dc395edc2f2a 100644
--- a/include/asm-x86_64/hw_irq.h
+++ b/include/asm-x86_64/hw_irq.h
@@ -35,6 +35,22 @@
35/* 35/*
36 * Vectors 0x20-0x2f are used for ISA interrupts. 36 * Vectors 0x20-0x2f are used for ISA interrupts.
37 */ 37 */
38#define IRQ0_VECTOR FIRST_EXTERNAL_VECTOR
39#define IRQ1_VECTOR IRQ0_VECTOR + 1
40#define IRQ2_VECTOR IRQ0_VECTOR + 2
41#define IRQ3_VECTOR IRQ0_VECTOR + 3
42#define IRQ4_VECTOR IRQ0_VECTOR + 4
43#define IRQ5_VECTOR IRQ0_VECTOR + 5
44#define IRQ6_VECTOR IRQ0_VECTOR + 6
45#define IRQ7_VECTOR IRQ0_VECTOR + 7
46#define IRQ8_VECTOR IRQ0_VECTOR + 8
47#define IRQ9_VECTOR IRQ0_VECTOR + 9
48#define IRQ10_VECTOR IRQ0_VECTOR + 10
49#define IRQ11_VECTOR IRQ0_VECTOR + 11
50#define IRQ12_VECTOR IRQ0_VECTOR + 12
51#define IRQ13_VECTOR IRQ0_VECTOR + 13
52#define IRQ14_VECTOR IRQ0_VECTOR + 14
53#define IRQ15_VECTOR IRQ0_VECTOR + 15
38 54
39/* 55/*
40 * Special IRQ vectors used by the SMP architecture, 0xf0-0xff 56 * Special IRQ vectors used by the SMP architecture, 0xf0-0xff
@@ -69,7 +85,7 @@
69 * we start at 0x31 to spread out vectors evenly between priority 85 * we start at 0x31 to spread out vectors evenly between priority
70 * levels. (0x80 is the syscall vector) 86 * levels. (0x80 is the syscall vector)
71 */ 87 */
72#define FIRST_DEVICE_VECTOR 0x31 88#define FIRST_DEVICE_VECTOR (IRQ15_VECTOR + 2)
73#define FIRST_SYSTEM_VECTOR 0xef /* duplicated in irq.h */ 89#define FIRST_SYSTEM_VECTOR 0xef /* duplicated in irq.h */
74 90
75 91