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-rw-r--r--arch/ia64/sn/kernel/sn2/ptc_deadlock.S1
-rw-r--r--include/asm-ia64/sn/shub_mmr.h346
2 files changed, 175 insertions, 172 deletions
diff --git a/arch/ia64/sn/kernel/sn2/ptc_deadlock.S b/arch/ia64/sn/kernel/sn2/ptc_deadlock.S
index 7947312801ec..96cb71d15682 100644
--- a/arch/ia64/sn/kernel/sn2/ptc_deadlock.S
+++ b/arch/ia64/sn/kernel/sn2/ptc_deadlock.S
@@ -6,6 +6,7 @@
6 * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved. 6 * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved.
7 */ 7 */
8 8
9#include <asm/types.h>
9#include <asm/sn/shub_mmr.h> 10#include <asm/sn/shub_mmr.h>
10 11
11#define DEADLOCKBIT SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_SHFT 12#define DEADLOCKBIT SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_SHFT
diff --git a/include/asm-ia64/sn/shub_mmr.h b/include/asm-ia64/sn/shub_mmr.h
index 323fa0cd8d83..7de1d1d4b71a 100644
--- a/include/asm-ia64/sn/shub_mmr.h
+++ b/include/asm-ia64/sn/shub_mmr.h
@@ -14,96 +14,98 @@
14/* Register "SH_IPI_INT" */ 14/* Register "SH_IPI_INT" */
15/* SHub Inter-Processor Interrupt Registers */ 15/* SHub Inter-Processor Interrupt Registers */
16/* ==================================================================== */ 16/* ==================================================================== */
17#define SH1_IPI_INT 0x0000000110000380 17#define SH1_IPI_INT __IA64_UL_CONST(0x0000000110000380)
18#define SH2_IPI_INT 0x0000000010000380 18#define SH2_IPI_INT __IA64_UL_CONST(0x0000000010000380)
19 19
20/* SH_IPI_INT_TYPE */ 20/* SH_IPI_INT_TYPE */
21/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ 21/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
22#define SH_IPI_INT_TYPE_SHFT 0 22#define SH_IPI_INT_TYPE_SHFT 0
23#define SH_IPI_INT_TYPE_MASK 0x0000000000000007 23#define SH_IPI_INT_TYPE_MASK __IA64_UL_CONST(0x0000000000000007)
24 24
25/* SH_IPI_INT_AGT */ 25/* SH_IPI_INT_AGT */
26/* Description: Agent, must be 0 for SHub */ 26/* Description: Agent, must be 0 for SHub */
27#define SH_IPI_INT_AGT_SHFT 3 27#define SH_IPI_INT_AGT_SHFT 3
28#define SH_IPI_INT_AGT_MASK 0x0000000000000008 28#define SH_IPI_INT_AGT_MASK __IA64_UL_CONST(0x0000000000000008)
29 29
30/* SH_IPI_INT_PID */ 30/* SH_IPI_INT_PID */
31/* Description: Processor ID, same setting as on targeted McKinley */ 31/* Description: Processor ID, same setting as on targeted McKinley */
32#define SH_IPI_INT_PID_SHFT 4 32#define SH_IPI_INT_PID_SHFT 4
33#define SH_IPI_INT_PID_MASK 0x00000000000ffff0 33#define SH_IPI_INT_PID_MASK __IA64_UL_CONST(0x00000000000ffff0)
34 34
35/* SH_IPI_INT_BASE */ 35/* SH_IPI_INT_BASE */
36/* Description: Optional interrupt vector area, 2MB aligned */ 36/* Description: Optional interrupt vector area, 2MB aligned */
37#define SH_IPI_INT_BASE_SHFT 21 37#define SH_IPI_INT_BASE_SHFT 21
38#define SH_IPI_INT_BASE_MASK 0x0003ffffffe00000 38#define SH_IPI_INT_BASE_MASK __IA64_UL_CONST(0x0003ffffffe00000)
39 39
40/* SH_IPI_INT_IDX */ 40/* SH_IPI_INT_IDX */
41/* Description: Targeted McKinley interrupt vector */ 41/* Description: Targeted McKinley interrupt vector */
42#define SH_IPI_INT_IDX_SHFT 52 42#define SH_IPI_INT_IDX_SHFT 52
43#define SH_IPI_INT_IDX_MASK 0x0ff0000000000000 43#define SH_IPI_INT_IDX_MASK __IA64_UL_CONST(0x0ff0000000000000)
44 44
45/* SH_IPI_INT_SEND */ 45/* SH_IPI_INT_SEND */
46/* Description: Send Interrupt Message to PI, This generates a puls */ 46/* Description: Send Interrupt Message to PI, This generates a puls */
47#define SH_IPI_INT_SEND_SHFT 63 47#define SH_IPI_INT_SEND_SHFT 63
48#define SH_IPI_INT_SEND_MASK 0x8000000000000000 48#define SH_IPI_INT_SEND_MASK __IA64_UL_CONST(0x8000000000000000)
49 49
50/* ==================================================================== */ 50/* ==================================================================== */
51/* Register "SH_EVENT_OCCURRED" */ 51/* Register "SH_EVENT_OCCURRED" */
52/* SHub Interrupt Event Occurred */ 52/* SHub Interrupt Event Occurred */
53/* ==================================================================== */ 53/* ==================================================================== */
54#define SH1_EVENT_OCCURRED 0x0000000110010000 54#define SH1_EVENT_OCCURRED __IA64_UL_CONST(0x0000000110010000)
55#define SH1_EVENT_OCCURRED_ALIAS 0x0000000110010008 55#define SH1_EVENT_OCCURRED_ALIAS __IA64_UL_CONST(0x0000000110010008)
56#define SH2_EVENT_OCCURRED 0x0000000010010000 56#define SH2_EVENT_OCCURRED __IA64_UL_CONST(0x0000000010010000)
57#define SH2_EVENT_OCCURRED_ALIAS 0x0000000010010008 57#define SH2_EVENT_OCCURRED_ALIAS __IA64_UL_CONST(0x0000000010010008)
58 58
59/* ==================================================================== */ 59/* ==================================================================== */
60/* Register "SH_PI_CAM_CONTROL" */ 60/* Register "SH_PI_CAM_CONTROL" */
61/* CRB CAM MMR Access Control */ 61/* CRB CAM MMR Access Control */
62/* ==================================================================== */ 62/* ==================================================================== */
63#define SH1_PI_CAM_CONTROL 0x0000000120050300 63#define SH1_PI_CAM_CONTROL __IA64_UL_CONST(0x0000000120050300)
64 64
65/* ==================================================================== */ 65/* ==================================================================== */
66/* Register "SH_SHUB_ID" */ 66/* Register "SH_SHUB_ID" */
67/* SHub ID Number */ 67/* SHub ID Number */
68/* ==================================================================== */ 68/* ==================================================================== */
69#define SH1_SHUB_ID 0x0000000110060580 69#define SH1_SHUB_ID __IA64_UL_CONST(0x0000000110060580)
70#define SH1_SHUB_ID_REVISION_SHFT 28 70#define SH1_SHUB_ID_REVISION_SHFT 28
71#define SH1_SHUB_ID_REVISION_MASK 0x00000000f0000000 71#define SH1_SHUB_ID_REVISION_MASK __IA64_UL_CONST(0x00000000f0000000)
72 72
73/* ==================================================================== */ 73/* ==================================================================== */
74/* Register "SH_RTC" */ 74/* Register "SH_RTC" */
75/* Real-time Clock */ 75/* Real-time Clock */
76/* ==================================================================== */ 76/* ==================================================================== */
77#define SH1_RTC 0x00000001101c0000 77#define SH1_RTC __IA64_UL_CONST(0x00000001101c0000)
78#define SH2_RTC 0x00000002101c0000 78#define SH2_RTC __IA64_UL_CONST(0x00000002101c0000)
79#define SH_RTC_MASK 0x007fffffffffffff 79#define SH_RTC_MASK __IA64_UL_CONST(0x007fffffffffffff)
80 80
81/* ==================================================================== */ 81/* ==================================================================== */
82/* Register "SH_PIO_WRITE_STATUS_0|1" */ 82/* Register "SH_PIO_WRITE_STATUS_0|1" */
83/* PIO Write Status for CPU 0 & 1 */ 83/* PIO Write Status for CPU 0 & 1 */
84/* ==================================================================== */ 84/* ==================================================================== */
85#define SH1_PIO_WRITE_STATUS_0 0x0000000120070200 85#define SH1_PIO_WRITE_STATUS_0 __IA64_UL_CONST(0x0000000120070200)
86#define SH1_PIO_WRITE_STATUS_1 0x0000000120070280 86#define SH1_PIO_WRITE_STATUS_1 __IA64_UL_CONST(0x0000000120070280)
87#define SH2_PIO_WRITE_STATUS_0 0x0000000020070200 87#define SH2_PIO_WRITE_STATUS_0 __IA64_UL_CONST(0x0000000020070200)
88#define SH2_PIO_WRITE_STATUS_1 0x0000000020070280 88#define SH2_PIO_WRITE_STATUS_1 __IA64_UL_CONST(0x0000000020070280)
89#define SH2_PIO_WRITE_STATUS_2 0x0000000020070300 89#define SH2_PIO_WRITE_STATUS_2 __IA64_UL_CONST(0x0000000020070300)
90#define SH2_PIO_WRITE_STATUS_3 0x0000000020070380 90#define SH2_PIO_WRITE_STATUS_3 __IA64_UL_CONST(0x0000000020070380)
91 91
92/* SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK */ 92/* SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK */
93/* Description: Deadlock response detected */ 93/* Description: Deadlock response detected */
94#define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_SHFT 1 94#define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_SHFT 1
95#define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_MASK 0x0000000000000002 95#define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_MASK \
96 __IA64_UL_CONST(0x0000000000000002)
96 97
97/* SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT */ 98/* SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT */
98/* Description: Count of currently pending PIO writes */ 99/* Description: Count of currently pending PIO writes */
99#define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_SHFT 56 100#define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_SHFT 56
100#define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK 0x3f00000000000000 101#define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK \
102 __IA64_UL_CONST(0x3f00000000000000)
101 103
102/* ==================================================================== */ 104/* ==================================================================== */
103/* Register "SH_PIO_WRITE_STATUS_0_ALIAS" */ 105/* Register "SH_PIO_WRITE_STATUS_0_ALIAS" */
104/* ==================================================================== */ 106/* ==================================================================== */
105#define SH1_PIO_WRITE_STATUS_0_ALIAS 0x0000000120070208 107#define SH1_PIO_WRITE_STATUS_0_ALIAS __IA64_UL_CONST(0x0000000120070208)
106#define SH2_PIO_WRITE_STATUS_0_ALIAS 0x0000000020070208 108#define SH2_PIO_WRITE_STATUS_0_ALIAS __IA64_UL_CONST(0x0000000020070208)
107 109
108/* ==================================================================== */ 110/* ==================================================================== */
109/* Register "SH_EVENT_OCCURRED" */ 111/* Register "SH_EVENT_OCCURRED" */
@@ -111,33 +113,33 @@
111/* ==================================================================== */ 113/* ==================================================================== */
112/* SH_EVENT_OCCURRED_UART_INT */ 114/* SH_EVENT_OCCURRED_UART_INT */
113/* Description: Pending Junk Bus UART Interrupt */ 115/* Description: Pending Junk Bus UART Interrupt */
114#define SH_EVENT_OCCURRED_UART_INT_SHFT 20 116#define SH_EVENT_OCCURRED_UART_INT_SHFT 20
115#define SH_EVENT_OCCURRED_UART_INT_MASK 0x0000000000100000 117#define SH_EVENT_OCCURRED_UART_INT_MASK __IA64_UL_CONST(0x0000000000100000)
116 118
117/* SH_EVENT_OCCURRED_IPI_INT */ 119/* SH_EVENT_OCCURRED_IPI_INT */
118/* Description: Pending IPI Interrupt */ 120/* Description: Pending IPI Interrupt */
119#define SH_EVENT_OCCURRED_IPI_INT_SHFT 28 121#define SH_EVENT_OCCURRED_IPI_INT_SHFT 28
120#define SH_EVENT_OCCURRED_IPI_INT_MASK 0x0000000010000000 122#define SH_EVENT_OCCURRED_IPI_INT_MASK __IA64_UL_CONST(0x0000000010000000)
121 123
122/* SH_EVENT_OCCURRED_II_INT0 */ 124/* SH_EVENT_OCCURRED_II_INT0 */
123/* Description: Pending II 0 Interrupt */ 125/* Description: Pending II 0 Interrupt */
124#define SH_EVENT_OCCURRED_II_INT0_SHFT 29 126#define SH_EVENT_OCCURRED_II_INT0_SHFT 29
125#define SH_EVENT_OCCURRED_II_INT0_MASK 0x0000000020000000 127#define SH_EVENT_OCCURRED_II_INT0_MASK __IA64_UL_CONST(0x0000000020000000)
126 128
127/* SH_EVENT_OCCURRED_II_INT1 */ 129/* SH_EVENT_OCCURRED_II_INT1 */
128/* Description: Pending II 1 Interrupt */ 130/* Description: Pending II 1 Interrupt */
129#define SH_EVENT_OCCURRED_II_INT1_SHFT 30 131#define SH_EVENT_OCCURRED_II_INT1_SHFT 30
130#define SH_EVENT_OCCURRED_II_INT1_MASK 0x0000000040000000 132#define SH_EVENT_OCCURRED_II_INT1_MASK __IA64_UL_CONST(0x0000000040000000)
131 133
132/* SH2_EVENT_OCCURRED_EXTIO_INT2 */ 134/* SH2_EVENT_OCCURRED_EXTIO_INT2 */
133/* Description: Pending SHUB 2 EXT IO INT2 */ 135/* Description: Pending SHUB 2 EXT IO INT2 */
134#define SH2_EVENT_OCCURRED_EXTIO_INT2_SHFT 33 136#define SH2_EVENT_OCCURRED_EXTIO_INT2_SHFT 33
135#define SH2_EVENT_OCCURRED_EXTIO_INT2_MASK 0x0000000200000000 137#define SH2_EVENT_OCCURRED_EXTIO_INT2_MASK __IA64_UL_CONST(0x0000000200000000)
136 138
137/* SH2_EVENT_OCCURRED_EXTIO_INT3 */ 139/* SH2_EVENT_OCCURRED_EXTIO_INT3 */
138/* Description: Pending SHUB 2 EXT IO INT3 */ 140/* Description: Pending SHUB 2 EXT IO INT3 */
139#define SH2_EVENT_OCCURRED_EXTIO_INT3_SHFT 34 141#define SH2_EVENT_OCCURRED_EXTIO_INT3_SHFT 34
140#define SH2_EVENT_OCCURRED_EXTIO_INT3_MASK 0x0000000400000000 142#define SH2_EVENT_OCCURRED_EXTIO_INT3_MASK __IA64_UL_CONST(0x0000000400000000)
141 143
142#define SH_ALL_INT_MASK \ 144#define SH_ALL_INT_MASK \
143 (SH_EVENT_OCCURRED_UART_INT_MASK | SH_EVENT_OCCURRED_IPI_INT_MASK | \ 145 (SH_EVENT_OCCURRED_UART_INT_MASK | SH_EVENT_OCCURRED_IPI_INT_MASK | \
@@ -149,310 +151,310 @@
149/* ==================================================================== */ 151/* ==================================================================== */
150/* LEDS */ 152/* LEDS */
151/* ==================================================================== */ 153/* ==================================================================== */
152#define SH1_REAL_JUNK_BUS_LED0 0x7fed00000UL 154#define SH1_REAL_JUNK_BUS_LED0 0x7fed00000UL
153#define SH1_REAL_JUNK_BUS_LED1 0x7fed10000UL 155#define SH1_REAL_JUNK_BUS_LED1 0x7fed10000UL
154#define SH1_REAL_JUNK_BUS_LED2 0x7fed20000UL 156#define SH1_REAL_JUNK_BUS_LED2 0x7fed20000UL
155#define SH1_REAL_JUNK_BUS_LED3 0x7fed30000UL 157#define SH1_REAL_JUNK_BUS_LED3 0x7fed30000UL
156 158
157#define SH2_REAL_JUNK_BUS_LED0 0xf0000000UL 159#define SH2_REAL_JUNK_BUS_LED0 0xf0000000UL
158#define SH2_REAL_JUNK_BUS_LED1 0xf0010000UL 160#define SH2_REAL_JUNK_BUS_LED1 0xf0010000UL
159#define SH2_REAL_JUNK_BUS_LED2 0xf0020000UL 161#define SH2_REAL_JUNK_BUS_LED2 0xf0020000UL
160#define SH2_REAL_JUNK_BUS_LED3 0xf0030000UL 162#define SH2_REAL_JUNK_BUS_LED3 0xf0030000UL
161 163
162/* ==================================================================== */ 164/* ==================================================================== */
163/* Register "SH1_PTC_0" */ 165/* Register "SH1_PTC_0" */
164/* Puge Translation Cache Message Configuration Information */ 166/* Puge Translation Cache Message Configuration Information */
165/* ==================================================================== */ 167/* ==================================================================== */
166#define SH1_PTC_0 0x00000001101a0000 168#define SH1_PTC_0 __IA64_UL_CONST(0x00000001101a0000)
167 169
168/* SH1_PTC_0_A */ 170/* SH1_PTC_0_A */
169/* Description: Type */ 171/* Description: Type */
170#define SH1_PTC_0_A_SHFT 0 172#define SH1_PTC_0_A_SHFT 0
171 173
172/* SH1_PTC_0_PS */ 174/* SH1_PTC_0_PS */
173/* Description: Page Size */ 175/* Description: Page Size */
174#define SH1_PTC_0_PS_SHFT 2 176#define SH1_PTC_0_PS_SHFT 2
175 177
176/* SH1_PTC_0_RID */ 178/* SH1_PTC_0_RID */
177/* Description: Region ID */ 179/* Description: Region ID */
178#define SH1_PTC_0_RID_SHFT 8 180#define SH1_PTC_0_RID_SHFT 8
179 181
180/* SH1_PTC_0_START */ 182/* SH1_PTC_0_START */
181/* Description: Start */ 183/* Description: Start */
182#define SH1_PTC_0_START_SHFT 63 184#define SH1_PTC_0_START_SHFT 63
183 185
184/* ==================================================================== */ 186/* ==================================================================== */
185/* Register "SH1_PTC_1" */ 187/* Register "SH1_PTC_1" */
186/* Puge Translation Cache Message Configuration Information */ 188/* Puge Translation Cache Message Configuration Information */
187/* ==================================================================== */ 189/* ==================================================================== */
188#define SH1_PTC_1 0x00000001101a0080 190#define SH1_PTC_1 __IA64_UL_CONST(0x00000001101a0080)
189 191
190/* SH1_PTC_1_START */ 192/* SH1_PTC_1_START */
191/* Description: PTC_1 Start */ 193/* Description: PTC_1 Start */
192#define SH1_PTC_1_START_SHFT 63 194#define SH1_PTC_1_START_SHFT 63
193
194 195
195/* ==================================================================== */ 196/* ==================================================================== */
196/* Register "SH2_PTC" */ 197/* Register "SH2_PTC" */
197/* Puge Translation Cache Message Configuration Information */ 198/* Puge Translation Cache Message Configuration Information */
198/* ==================================================================== */ 199/* ==================================================================== */
199#define SH2_PTC 0x0000000170000000 200#define SH2_PTC __IA64_UL_CONST(0x0000000170000000)
200 201
201/* SH2_PTC_A */ 202/* SH2_PTC_A */
202/* Description: Type */ 203/* Description: Type */
203#define SH2_PTC_A_SHFT 0 204#define SH2_PTC_A_SHFT 0
204 205
205/* SH2_PTC_PS */ 206/* SH2_PTC_PS */
206/* Description: Page Size */ 207/* Description: Page Size */
207#define SH2_PTC_PS_SHFT 2 208#define SH2_PTC_PS_SHFT 2
208 209
209/* SH2_PTC_RID */ 210/* SH2_PTC_RID */
210/* Description: Region ID */ 211/* Description: Region ID */
211#define SH2_PTC_RID_SHFT 4 212#define SH2_PTC_RID_SHFT 4
212 213
213/* SH2_PTC_START */ 214/* SH2_PTC_START */
214/* Description: Start */ 215/* Description: Start */
215#define SH2_PTC_START_SHFT 63 216#define SH2_PTC_START_SHFT 63
216 217
217/* SH2_PTC_ADDR_RID */ 218/* SH2_PTC_ADDR_RID */
218/* Description: Region ID */ 219/* Description: Region ID */
219#define SH2_PTC_ADDR_SHFT 4 220#define SH2_PTC_ADDR_SHFT 4
220#define SH2_PTC_ADDR_MASK 0x1ffffffffffff000 221#define SH2_PTC_ADDR_MASK __IA64_UL_CONST(0x1ffffffffffff000)
221 222
222/* ==================================================================== */ 223/* ==================================================================== */
223/* Register "SH_RTC1_INT_CONFIG" */ 224/* Register "SH_RTC1_INT_CONFIG" */
224/* SHub RTC 1 Interrupt Config Registers */ 225/* SHub RTC 1 Interrupt Config Registers */
225/* ==================================================================== */ 226/* ==================================================================== */
226 227
227#define SH1_RTC1_INT_CONFIG 0x0000000110001480 228#define SH1_RTC1_INT_CONFIG __IA64_UL_CONST(0x0000000110001480)
228#define SH2_RTC1_INT_CONFIG 0x0000000010001480 229#define SH2_RTC1_INT_CONFIG __IA64_UL_CONST(0x0000000010001480)
229#define SH_RTC1_INT_CONFIG_MASK 0x0ff3ffffffefffff 230#define SH_RTC1_INT_CONFIG_MASK __IA64_UL_CONST(0x0ff3ffffffefffff)
230#define SH_RTC1_INT_CONFIG_INIT 0x0000000000000000 231#define SH_RTC1_INT_CONFIG_INIT __IA64_UL_CONST(0x0000000000000000)
231 232
232/* SH_RTC1_INT_CONFIG_TYPE */ 233/* SH_RTC1_INT_CONFIG_TYPE */
233/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ 234/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
234#define SH_RTC1_INT_CONFIG_TYPE_SHFT 0 235#define SH_RTC1_INT_CONFIG_TYPE_SHFT 0
235#define SH_RTC1_INT_CONFIG_TYPE_MASK 0x0000000000000007 236#define SH_RTC1_INT_CONFIG_TYPE_MASK __IA64_UL_CONST(0x0000000000000007)
236 237
237/* SH_RTC1_INT_CONFIG_AGT */ 238/* SH_RTC1_INT_CONFIG_AGT */
238/* Description: Agent, must be 0 for SHub */ 239/* Description: Agent, must be 0 for SHub */
239#define SH_RTC1_INT_CONFIG_AGT_SHFT 3 240#define SH_RTC1_INT_CONFIG_AGT_SHFT 3
240#define SH_RTC1_INT_CONFIG_AGT_MASK 0x0000000000000008 241#define SH_RTC1_INT_CONFIG_AGT_MASK __IA64_UL_CONST(0x0000000000000008)
241 242
242/* SH_RTC1_INT_CONFIG_PID */ 243/* SH_RTC1_INT_CONFIG_PID */
243/* Description: Processor ID, same setting as on targeted McKinley */ 244/* Description: Processor ID, same setting as on targeted McKinley */
244#define SH_RTC1_INT_CONFIG_PID_SHFT 4 245#define SH_RTC1_INT_CONFIG_PID_SHFT 4
245#define SH_RTC1_INT_CONFIG_PID_MASK 0x00000000000ffff0 246#define SH_RTC1_INT_CONFIG_PID_MASK __IA64_UL_CONST(0x00000000000ffff0)
246 247
247/* SH_RTC1_INT_CONFIG_BASE */ 248/* SH_RTC1_INT_CONFIG_BASE */
248/* Description: Optional interrupt vector area, 2MB aligned */ 249/* Description: Optional interrupt vector area, 2MB aligned */
249#define SH_RTC1_INT_CONFIG_BASE_SHFT 21 250#define SH_RTC1_INT_CONFIG_BASE_SHFT 21
250#define SH_RTC1_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 251#define SH_RTC1_INT_CONFIG_BASE_MASK __IA64_UL_CONST(0x0003ffffffe00000)
251 252
252/* SH_RTC1_INT_CONFIG_IDX */ 253/* SH_RTC1_INT_CONFIG_IDX */
253/* Description: Targeted McKinley interrupt vector */ 254/* Description: Targeted McKinley interrupt vector */
254#define SH_RTC1_INT_CONFIG_IDX_SHFT 52 255#define SH_RTC1_INT_CONFIG_IDX_SHFT 52
255#define SH_RTC1_INT_CONFIG_IDX_MASK 0x0ff0000000000000 256#define SH_RTC1_INT_CONFIG_IDX_MASK __IA64_UL_CONST(0x0ff0000000000000)
256 257
257/* ==================================================================== */ 258/* ==================================================================== */
258/* Register "SH_RTC1_INT_ENABLE" */ 259/* Register "SH_RTC1_INT_ENABLE" */
259/* SHub RTC 1 Interrupt Enable Registers */ 260/* SHub RTC 1 Interrupt Enable Registers */
260/* ==================================================================== */ 261/* ==================================================================== */
261 262
262#define SH1_RTC1_INT_ENABLE 0x0000000110001500 263#define SH1_RTC1_INT_ENABLE __IA64_UL_CONST(0x0000000110001500)
263#define SH2_RTC1_INT_ENABLE 0x0000000010001500 264#define SH2_RTC1_INT_ENABLE __IA64_UL_CONST(0x0000000010001500)
264#define SH_RTC1_INT_ENABLE_MASK 0x0000000000000001 265#define SH_RTC1_INT_ENABLE_MASK __IA64_UL_CONST(0x0000000000000001)
265#define SH_RTC1_INT_ENABLE_INIT 0x0000000000000000 266#define SH_RTC1_INT_ENABLE_INIT __IA64_UL_CONST(0x0000000000000000)
266 267
267/* SH_RTC1_INT_ENABLE_RTC1_ENABLE */ 268/* SH_RTC1_INT_ENABLE_RTC1_ENABLE */
268/* Description: Enable RTC 1 Interrupt */ 269/* Description: Enable RTC 1 Interrupt */
269#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_SHFT 0 270#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_SHFT 0
270#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_MASK 0x0000000000000001 271#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_MASK \
272 __IA64_UL_CONST(0x0000000000000001)
271 273
272/* ==================================================================== */ 274/* ==================================================================== */
273/* Register "SH_RTC2_INT_CONFIG" */ 275/* Register "SH_RTC2_INT_CONFIG" */
274/* SHub RTC 2 Interrupt Config Registers */ 276/* SHub RTC 2 Interrupt Config Registers */
275/* ==================================================================== */ 277/* ==================================================================== */
276 278
277#define SH1_RTC2_INT_CONFIG 0x0000000110001580 279#define SH1_RTC2_INT_CONFIG __IA64_UL_CONST(0x0000000110001580)
278#define SH2_RTC2_INT_CONFIG 0x0000000010001580 280#define SH2_RTC2_INT_CONFIG __IA64_UL_CONST(0x0000000010001580)
279#define SH_RTC2_INT_CONFIG_MASK 0x0ff3ffffffefffff 281#define SH_RTC2_INT_CONFIG_MASK __IA64_UL_CONST(0x0ff3ffffffefffff)
280#define SH_RTC2_INT_CONFIG_INIT 0x0000000000000000 282#define SH_RTC2_INT_CONFIG_INIT __IA64_UL_CONST(0x0000000000000000)
281 283
282/* SH_RTC2_INT_CONFIG_TYPE */ 284/* SH_RTC2_INT_CONFIG_TYPE */
283/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ 285/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
284#define SH_RTC2_INT_CONFIG_TYPE_SHFT 0 286#define SH_RTC2_INT_CONFIG_TYPE_SHFT 0
285#define SH_RTC2_INT_CONFIG_TYPE_MASK 0x0000000000000007 287#define SH_RTC2_INT_CONFIG_TYPE_MASK __IA64_UL_CONST(0x0000000000000007)
286 288
287/* SH_RTC2_INT_CONFIG_AGT */ 289/* SH_RTC2_INT_CONFIG_AGT */
288/* Description: Agent, must be 0 for SHub */ 290/* Description: Agent, must be 0 for SHub */
289#define SH_RTC2_INT_CONFIG_AGT_SHFT 3 291#define SH_RTC2_INT_CONFIG_AGT_SHFT 3
290#define SH_RTC2_INT_CONFIG_AGT_MASK 0x0000000000000008 292#define SH_RTC2_INT_CONFIG_AGT_MASK __IA64_UL_CONST(0x0000000000000008)
291 293
292/* SH_RTC2_INT_CONFIG_PID */ 294/* SH_RTC2_INT_CONFIG_PID */
293/* Description: Processor ID, same setting as on targeted McKinley */ 295/* Description: Processor ID, same setting as on targeted McKinley */
294#define SH_RTC2_INT_CONFIG_PID_SHFT 4 296#define SH_RTC2_INT_CONFIG_PID_SHFT 4
295#define SH_RTC2_INT_CONFIG_PID_MASK 0x00000000000ffff0 297#define SH_RTC2_INT_CONFIG_PID_MASK __IA64_UL_CONST(0x00000000000ffff0)
296 298
297/* SH_RTC2_INT_CONFIG_BASE */ 299/* SH_RTC2_INT_CONFIG_BASE */
298/* Description: Optional interrupt vector area, 2MB aligned */ 300/* Description: Optional interrupt vector area, 2MB aligned */
299#define SH_RTC2_INT_CONFIG_BASE_SHFT 21 301#define SH_RTC2_INT_CONFIG_BASE_SHFT 21
300#define SH_RTC2_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 302#define SH_RTC2_INT_CONFIG_BASE_MASK __IA64_UL_CONST(0x0003ffffffe00000)
301 303
302/* SH_RTC2_INT_CONFIG_IDX */ 304/* SH_RTC2_INT_CONFIG_IDX */
303/* Description: Targeted McKinley interrupt vector */ 305/* Description: Targeted McKinley interrupt vector */
304#define SH_RTC2_INT_CONFIG_IDX_SHFT 52 306#define SH_RTC2_INT_CONFIG_IDX_SHFT 52
305#define SH_RTC2_INT_CONFIG_IDX_MASK 0x0ff0000000000000 307#define SH_RTC2_INT_CONFIG_IDX_MASK __IA64_UL_CONST(0x0ff0000000000000)
306 308
307/* ==================================================================== */ 309/* ==================================================================== */
308/* Register "SH_RTC2_INT_ENABLE" */ 310/* Register "SH_RTC2_INT_ENABLE" */
309/* SHub RTC 2 Interrupt Enable Registers */ 311/* SHub RTC 2 Interrupt Enable Registers */
310/* ==================================================================== */ 312/* ==================================================================== */
311 313
312#define SH1_RTC2_INT_ENABLE 0x0000000110001600 314#define SH1_RTC2_INT_ENABLE __IA64_UL_CONST(0x0000000110001600)
313#define SH2_RTC2_INT_ENABLE 0x0000000010001600 315#define SH2_RTC2_INT_ENABLE __IA64_UL_CONST(0x0000000010001600)
314#define SH_RTC2_INT_ENABLE_MASK 0x0000000000000001 316#define SH_RTC2_INT_ENABLE_MASK __IA64_UL_CONST(0x0000000000000001)
315#define SH_RTC2_INT_ENABLE_INIT 0x0000000000000000 317#define SH_RTC2_INT_ENABLE_INIT __IA64_UL_CONST(0x0000000000000000)
316 318
317/* SH_RTC2_INT_ENABLE_RTC2_ENABLE */ 319/* SH_RTC2_INT_ENABLE_RTC2_ENABLE */
318/* Description: Enable RTC 2 Interrupt */ 320/* Description: Enable RTC 2 Interrupt */
319#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_SHFT 0 321#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_SHFT 0
320#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_MASK 0x0000000000000001 322#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_MASK \
323 __IA64_UL_CONST(0x0000000000000001)
321 324
322/* ==================================================================== */ 325/* ==================================================================== */
323/* Register "SH_RTC3_INT_CONFIG" */ 326/* Register "SH_RTC3_INT_CONFIG" */
324/* SHub RTC 3 Interrupt Config Registers */ 327/* SHub RTC 3 Interrupt Config Registers */
325/* ==================================================================== */ 328/* ==================================================================== */
326 329
327#define SH1_RTC3_INT_CONFIG 0x0000000110001680 330#define SH1_RTC3_INT_CONFIG __IA64_UL_CONST(0x0000000110001680)
328#define SH2_RTC3_INT_CONFIG 0x0000000010001680 331#define SH2_RTC3_INT_CONFIG __IA64_UL_CONST(0x0000000010001680)
329#define SH_RTC3_INT_CONFIG_MASK 0x0ff3ffffffefffff 332#define SH_RTC3_INT_CONFIG_MASK __IA64_UL_CONST(0x0ff3ffffffefffff)
330#define SH_RTC3_INT_CONFIG_INIT 0x0000000000000000 333#define SH_RTC3_INT_CONFIG_INIT __IA64_UL_CONST(0x0000000000000000)
331 334
332/* SH_RTC3_INT_CONFIG_TYPE */ 335/* SH_RTC3_INT_CONFIG_TYPE */
333/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ 336/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
334#define SH_RTC3_INT_CONFIG_TYPE_SHFT 0 337#define SH_RTC3_INT_CONFIG_TYPE_SHFT 0
335#define SH_RTC3_INT_CONFIG_TYPE_MASK 0x0000000000000007 338#define SH_RTC3_INT_CONFIG_TYPE_MASK __IA64_UL_CONST(0x0000000000000007)
336 339
337/* SH_RTC3_INT_CONFIG_AGT */ 340/* SH_RTC3_INT_CONFIG_AGT */
338/* Description: Agent, must be 0 for SHub */ 341/* Description: Agent, must be 0 for SHub */
339#define SH_RTC3_INT_CONFIG_AGT_SHFT 3 342#define SH_RTC3_INT_CONFIG_AGT_SHFT 3
340#define SH_RTC3_INT_CONFIG_AGT_MASK 0x0000000000000008 343#define SH_RTC3_INT_CONFIG_AGT_MASK __IA64_UL_CONST(0x0000000000000008)
341 344
342/* SH_RTC3_INT_CONFIG_PID */ 345/* SH_RTC3_INT_CONFIG_PID */
343/* Description: Processor ID, same setting as on targeted McKinley */ 346/* Description: Processor ID, same setting as on targeted McKinley */
344#define SH_RTC3_INT_CONFIG_PID_SHFT 4 347#define SH_RTC3_INT_CONFIG_PID_SHFT 4
345#define SH_RTC3_INT_CONFIG_PID_MASK 0x00000000000ffff0 348#define SH_RTC3_INT_CONFIG_PID_MASK __IA64_UL_CONST(0x00000000000ffff0)
346 349
347/* SH_RTC3_INT_CONFIG_BASE */ 350/* SH_RTC3_INT_CONFIG_BASE */
348/* Description: Optional interrupt vector area, 2MB aligned */ 351/* Description: Optional interrupt vector area, 2MB aligned */
349#define SH_RTC3_INT_CONFIG_BASE_SHFT 21 352#define SH_RTC3_INT_CONFIG_BASE_SHFT 21
350#define SH_RTC3_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 353#define SH_RTC3_INT_CONFIG_BASE_MASK __IA64_UL_CONST(0x0003ffffffe00000)
351 354
352/* SH_RTC3_INT_CONFIG_IDX */ 355/* SH_RTC3_INT_CONFIG_IDX */
353/* Description: Targeted McKinley interrupt vector */ 356/* Description: Targeted McKinley interrupt vector */
354#define SH_RTC3_INT_CONFIG_IDX_SHFT 52 357#define SH_RTC3_INT_CONFIG_IDX_SHFT 52
355#define SH_RTC3_INT_CONFIG_IDX_MASK 0x0ff0000000000000 358#define SH_RTC3_INT_CONFIG_IDX_MASK __IA64_UL_CONST(0x0ff0000000000000)
356 359
357/* ==================================================================== */ 360/* ==================================================================== */
358/* Register "SH_RTC3_INT_ENABLE" */ 361/* Register "SH_RTC3_INT_ENABLE" */
359/* SHub RTC 3 Interrupt Enable Registers */ 362/* SHub RTC 3 Interrupt Enable Registers */
360/* ==================================================================== */ 363/* ==================================================================== */
361 364
362#define SH1_RTC3_INT_ENABLE 0x0000000110001700 365#define SH1_RTC3_INT_ENABLE __IA64_UL_CONST(0x0000000110001700)
363#define SH2_RTC3_INT_ENABLE 0x0000000010001700 366#define SH2_RTC3_INT_ENABLE __IA64_UL_CONST(0x0000000010001700)
364#define SH_RTC3_INT_ENABLE_MASK 0x0000000000000001 367#define SH_RTC3_INT_ENABLE_MASK __IA64_UL_CONST(0x0000000000000001)
365#define SH_RTC3_INT_ENABLE_INIT 0x0000000000000000 368#define SH_RTC3_INT_ENABLE_INIT __IA64_UL_CONST(0x0000000000000000)
366 369
367/* SH_RTC3_INT_ENABLE_RTC3_ENABLE */ 370/* SH_RTC3_INT_ENABLE_RTC3_ENABLE */
368/* Description: Enable RTC 3 Interrupt */ 371/* Description: Enable RTC 3 Interrupt */
369#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_SHFT 0 372#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_SHFT 0
370#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_MASK 0x0000000000000001 373#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_MASK \
374 __IA64_UL_CONST(0x0000000000000001)
371 375
372/* SH_EVENT_OCCURRED_RTC1_INT */ 376/* SH_EVENT_OCCURRED_RTC1_INT */
373/* Description: Pending RTC 1 Interrupt */ 377/* Description: Pending RTC 1 Interrupt */
374#define SH_EVENT_OCCURRED_RTC1_INT_SHFT 24 378#define SH_EVENT_OCCURRED_RTC1_INT_SHFT 24
375#define SH_EVENT_OCCURRED_RTC1_INT_MASK 0x0000000001000000 379#define SH_EVENT_OCCURRED_RTC1_INT_MASK __IA64_UL_CONST(0x0000000001000000)
376 380
377/* SH_EVENT_OCCURRED_RTC2_INT */ 381/* SH_EVENT_OCCURRED_RTC2_INT */
378/* Description: Pending RTC 2 Interrupt */ 382/* Description: Pending RTC 2 Interrupt */
379#define SH_EVENT_OCCURRED_RTC2_INT_SHFT 25 383#define SH_EVENT_OCCURRED_RTC2_INT_SHFT 25
380#define SH_EVENT_OCCURRED_RTC2_INT_MASK 0x0000000002000000 384#define SH_EVENT_OCCURRED_RTC2_INT_MASK __IA64_UL_CONST(0x0000000002000000)
381 385
382/* SH_EVENT_OCCURRED_RTC3_INT */ 386/* SH_EVENT_OCCURRED_RTC3_INT */
383/* Description: Pending RTC 3 Interrupt */ 387/* Description: Pending RTC 3 Interrupt */
384#define SH_EVENT_OCCURRED_RTC3_INT_SHFT 26 388#define SH_EVENT_OCCURRED_RTC3_INT_SHFT 26
385#define SH_EVENT_OCCURRED_RTC3_INT_MASK 0x0000000004000000 389#define SH_EVENT_OCCURRED_RTC3_INT_MASK __IA64_UL_CONST(0x0000000004000000)
386 390
387/* ==================================================================== */ 391/* ==================================================================== */
388/* Register "SH_IPI_ACCESS" */ 392/* Register "SH_IPI_ACCESS" */
389/* CPU interrupt Access Permission Bits */ 393/* CPU interrupt Access Permission Bits */
390/* ==================================================================== */ 394/* ==================================================================== */
391 395
392#define SH1_IPI_ACCESS 0x0000000110060480 396#define SH1_IPI_ACCESS __IA64_UL_CONST(0x0000000110060480)
393#define SH2_IPI_ACCESS0 0x0000000010060c00 397#define SH2_IPI_ACCESS0 __IA64_UL_CONST(0x0000000010060c00)
394#define SH2_IPI_ACCESS1 0x0000000010060c80 398#define SH2_IPI_ACCESS1 __IA64_UL_CONST(0x0000000010060c80)
395#define SH2_IPI_ACCESS2 0x0000000010060d00 399#define SH2_IPI_ACCESS2 __IA64_UL_CONST(0x0000000010060d00)
396#define SH2_IPI_ACCESS3 0x0000000010060d80 400#define SH2_IPI_ACCESS3 __IA64_UL_CONST(0x0000000010060d80)
397 401
398/* ==================================================================== */ 402/* ==================================================================== */
399/* Register "SH_INT_CMPB" */ 403/* Register "SH_INT_CMPB" */
400/* RTC Compare Value for Processor B */ 404/* RTC Compare Value for Processor B */
401/* ==================================================================== */ 405/* ==================================================================== */
402 406
403#define SH1_INT_CMPB 0x00000001101b0080 407#define SH1_INT_CMPB __IA64_UL_CONST(0x00000001101b0080)
404#define SH2_INT_CMPB 0x00000000101b0080 408#define SH2_INT_CMPB __IA64_UL_CONST(0x00000000101b0080)
405#define SH_INT_CMPB_MASK 0x007fffffffffffff 409#define SH_INT_CMPB_MASK __IA64_UL_CONST(0x007fffffffffffff)
406#define SH_INT_CMPB_INIT 0x0000000000000000 410#define SH_INT_CMPB_INIT __IA64_UL_CONST(0x0000000000000000)
407 411
408/* SH_INT_CMPB_REAL_TIME_CMPB */ 412/* SH_INT_CMPB_REAL_TIME_CMPB */
409/* Description: Real Time Clock Compare */ 413/* Description: Real Time Clock Compare */
410#define SH_INT_CMPB_REAL_TIME_CMPB_SHFT 0 414#define SH_INT_CMPB_REAL_TIME_CMPB_SHFT 0
411#define SH_INT_CMPB_REAL_TIME_CMPB_MASK 0x007fffffffffffff 415#define SH_INT_CMPB_REAL_TIME_CMPB_MASK __IA64_UL_CONST(0x007fffffffffffff)
412 416
413/* ==================================================================== */ 417/* ==================================================================== */
414/* Register "SH_INT_CMPC" */ 418/* Register "SH_INT_CMPC" */
415/* RTC Compare Value for Processor C */ 419/* RTC Compare Value for Processor C */
416/* ==================================================================== */ 420/* ==================================================================== */
417 421
418#define SH1_INT_CMPC 0x00000001101b0100 422#define SH1_INT_CMPC __IA64_UL_CONST(0x00000001101b0100)
419#define SH2_INT_CMPC 0x00000000101b0100 423#define SH2_INT_CMPC __IA64_UL_CONST(0x00000000101b0100)
420#define SH_INT_CMPC_MASK 0x007fffffffffffff 424#define SH_INT_CMPC_MASK __IA64_UL_CONST(0x007fffffffffffff)
421#define SH_INT_CMPC_INIT 0x0000000000000000 425#define SH_INT_CMPC_INIT __IA64_UL_CONST(0x0000000000000000)
422 426
423/* SH_INT_CMPC_REAL_TIME_CMPC */ 427/* SH_INT_CMPC_REAL_TIME_CMPC */
424/* Description: Real Time Clock Compare */ 428/* Description: Real Time Clock Compare */
425#define SH_INT_CMPC_REAL_TIME_CMPC_SHFT 0 429#define SH_INT_CMPC_REAL_TIME_CMPC_SHFT 0
426#define SH_INT_CMPC_REAL_TIME_CMPC_MASK 0x007fffffffffffff 430#define SH_INT_CMPC_REAL_TIME_CMPC_MASK __IA64_UL_CONST(0x007fffffffffffff)
427 431
428/* ==================================================================== */ 432/* ==================================================================== */
429/* Register "SH_INT_CMPD" */ 433/* Register "SH_INT_CMPD" */
430/* RTC Compare Value for Processor D */ 434/* RTC Compare Value for Processor D */
431/* ==================================================================== */ 435/* ==================================================================== */
432 436
433#define SH1_INT_CMPD 0x00000001101b0180 437#define SH1_INT_CMPD __IA64_UL_CONST(0x00000001101b0180)
434#define SH2_INT_CMPD 0x00000000101b0180 438#define SH2_INT_CMPD __IA64_UL_CONST(0x00000000101b0180)
435#define SH_INT_CMPD_MASK 0x007fffffffffffff 439#define SH_INT_CMPD_MASK __IA64_UL_CONST(0x007fffffffffffff)
436#define SH_INT_CMPD_INIT 0x0000000000000000 440#define SH_INT_CMPD_INIT __IA64_UL_CONST(0x0000000000000000)
437 441
438/* SH_INT_CMPD_REAL_TIME_CMPD */ 442/* SH_INT_CMPD_REAL_TIME_CMPD */
439/* Description: Real Time Clock Compare */ 443/* Description: Real Time Clock Compare */
440#define SH_INT_CMPD_REAL_TIME_CMPD_SHFT 0 444#define SH_INT_CMPD_REAL_TIME_CMPD_SHFT 0
441#define SH_INT_CMPD_REAL_TIME_CMPD_MASK 0x007fffffffffffff 445#define SH_INT_CMPD_REAL_TIME_CMPD_MASK __IA64_UL_CONST(0x007fffffffffffff)
442 446
443/* ==================================================================== */ 447/* ==================================================================== */
444/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC0" */ 448/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC0" */
445/* privilege vector for acc=0 */ 449/* privilege vector for acc=0 */
446/* ==================================================================== */ 450/* ==================================================================== */
447 451#define SH1_MD_DQLP_MMR_DIR_PRIVEC0 __IA64_UL_CONST(0x0000000100030300)
448#define SH1_MD_DQLP_MMR_DIR_PRIVEC0 0x0000000100030300
449 452
450/* ==================================================================== */ 453/* ==================================================================== */
451/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC0" */ 454/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC0" */
452/* privilege vector for acc=0 */ 455/* privilege vector for acc=0 */
453/* ==================================================================== */ 456/* ==================================================================== */
454 457#define SH1_MD_DQRP_MMR_DIR_PRIVEC0 __IA64_UL_CONST(0x0000000100050300)
455#define SH1_MD_DQRP_MMR_DIR_PRIVEC0 0x0000000100050300
456 458
457/* ==================================================================== */ 459/* ==================================================================== */
458/* Some MMRs are functionally identical (or close enough) on both SHUB1 */ 460/* Some MMRs are functionally identical (or close enough) on both SHUB1 */
@@ -484,17 +486,17 @@
484/* Engine 0 Control and Status Register */ 486/* Engine 0 Control and Status Register */
485/* ========================================================================== */ 487/* ========================================================================== */
486 488
487#define SH2_BT_ENG_CSR_0 0x0000000030040000 489#define SH2_BT_ENG_CSR_0 __IA64_UL_CONST(0x0000000030040000)
488#define SH2_BT_ENG_SRC_ADDR_0 0x0000000030040080 490#define SH2_BT_ENG_SRC_ADDR_0 __IA64_UL_CONST(0x0000000030040080)
489#define SH2_BT_ENG_DEST_ADDR_0 0x0000000030040100 491#define SH2_BT_ENG_DEST_ADDR_0 __IA64_UL_CONST(0x0000000030040100)
490#define SH2_BT_ENG_NOTIF_ADDR_0 0x0000000030040180 492#define SH2_BT_ENG_NOTIF_ADDR_0 __IA64_UL_CONST(0x0000000030040180)
491 493
492/* ========================================================================== */ 494/* ========================================================================== */
493/* BTE interfaces 1-3 */ 495/* BTE interfaces 1-3 */
494/* ========================================================================== */ 496/* ========================================================================== */
495 497
496#define SH2_BT_ENG_CSR_1 0x0000000030050000 498#define SH2_BT_ENG_CSR_1 __IA64_UL_CONST(0x0000000030050000)
497#define SH2_BT_ENG_CSR_2 0x0000000030060000 499#define SH2_BT_ENG_CSR_2 __IA64_UL_CONST(0x0000000030060000)
498#define SH2_BT_ENG_CSR_3 0x0000000030070000 500#define SH2_BT_ENG_CSR_3 __IA64_UL_CONST(0x0000000030070000)
499 501
500#endif /* _ASM_IA64_SN_SHUB_MMR_H */ 502#endif /* _ASM_IA64_SN_SHUB_MMR_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-25 23:26:33 -0400