2 files changed, 67 insertions, 0 deletions

diff --git a/arch/sh/kernel/process.c b/arch/sh/kernel/process.c
index 0b1d5dd7a93b..91516dca4a85 100644
--- a/arch/sh/kernel/process.c
+++ b/arch/sh/kernel/process.c
@@ -5,6 +5,7 @@
  *  Copyright (C) 1995  Linus Torvalds
  *
  *  SuperH version:  Copyright (C) 1999, 2000  Niibe Yutaka & Kaz Kojima
+ *                   Copyright (C) 2006 Lineo Solutions Inc. support SH4A UBC
  */
 
 /*
@@ -290,6 +291,24 @@ int copy_thread(int nr, unsigned long clone_flags, unsigned long usp,
 static void
 ubc_set_tracing(int asid, unsigned long pc)
 {
+#if defined(CONFIG_CPU_SH4A)
+        unsigned long val;
+
+        val = (UBC_CBR_ID_INST | UBC_CBR_RW_READ | UBC_CBR_CE);
+        val |= (UBC_CBR_AIE | UBC_CBR_AIV_SET(asid));
+
+        ctrl_outl(val, UBC_CBR0);
+        ctrl_outl(pc,  UBC_CAR0);
+        ctrl_outl(0x0, UBC_CAMR0);
+        ctrl_outl(0x0, UBC_CBCR);
+
+        val = (UBC_CRR_RES | UBC_CRR_PCB | UBC_CRR_BIE);
+        ctrl_outl(val, UBC_CRR0);
+
+        /* Read UBC register that we writed last. For chekking UBC Register changed */
+        val = ctrl_inl(UBC_CRR0);
+
+#else   /* CONFIG_CPU_SH4A */
         ctrl_outl(pc, UBC_BARA);
 
 #ifdef CONFIG_MMU
@@ -307,6 +326,7 @@ ubc_set_tracing(int asid, unsigned long pc)
                 ctrl_outw(BBR_INST | BBR_READ, UBC_BBRA);
                 ctrl_outw(BRCR_PCBA, UBC_BRCR);
         }
+#endif  /* CONFIG_CPU_SH4A */
 }
 
 /*
@@ -359,8 +379,13 @@ struct task_struct *__switch_to(struct task_struct *prev, struct task_struct *ne
 #endif
                 ubc_set_tracing(asid, next->thread.ubc_pc);
         } else {
+#if defined(CONFIG_CPU_SH4A)
+                ctrl_outl(UBC_CBR_INIT, UBC_CBR0);
+                ctrl_outl(UBC_CRR_INIT, UBC_CRR0);
+#else
                 ctrl_outw(0, UBC_BBRA);
                 ctrl_outw(0, UBC_BBRB);
+#endif
         }
 
         return prev;
@@ -460,8 +485,13 @@ asmlinkage void break_point_trap(unsigned long r4, unsigned long r5,
                                  struct pt_regs regs)
 {
         /* Clear tracing.  */
+#if defined(CONFIG_CPU_SH4A)
+        ctrl_outl(UBC_CBR_INIT, UBC_CBR0);
+        ctrl_outl(UBC_CRR_INIT, UBC_CRR0);
+#else
         ctrl_outw(0, UBC_BBRA);
         ctrl_outw(0, UBC_BBRB);
+#endif
         current->thread.ubc_pc = 0;
         ubc_usercnt -= 1;
 
diff --git a/include/asm-sh/cpu-sh4/ubc.h b/include/asm-sh/cpu-sh4/ubc.h
index 3d0943167659..c86e17050935 100644
--- a/include/asm-sh/cpu-sh4/ubc.h
+++ b/include/asm-sh/cpu-sh4/ubc.h
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 1999 Niibe Yutaka
  * Copyright (C) 2003 Paul Mundt
+ * Copyright (C) 2006 Lineo Solutions Inc. support SH4A UBC
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -11,6 +12,41 @@
 #ifndef __ASM_CPU_SH4_UBC_H
 #define __ASM_CPU_SH4_UBC_H
 
+#if defined(CONFIG_CPU_SH4A)
+#define UBC_CBR0                0xff200000
+#define UBC_CRR0                0xff200004
+#define UBC_CAR0                0xff200008
+#define UBC_CAMR0               0xff20000c
+#define UBC_CBR1                0xff200020
+#define UBC_CRR1                0xff200024
+#define UBC_CAR1                0xff200028
+#define UBC_CAMR1               0xff20002c
+#define UBC_CDR1                0xff200030
+#define UBC_CDMR1               0xff200034
+#define UBC_CETR1               0xff200038
+#define UBC_CCMFR               0xff200600
+#define UBC_CBCR                0xff200620
+
+/* CBR  */
+#define UBC_CBR_AIE             (0x01<<30)
+#define UBC_CBR_ID_INST         (0x01<<4)
+#define UBC_CBR_RW_READ         (0x01<<1)
+#define UBC_CBR_CE              (0x01)
+
+#define UBC_CBR_AIV_MASK        (0x00FF0000)
+#define UBC_CBR_AIV_SHIFT       (16)
+#define UBC_CBR_AIV_SET(asid)   (((asid)<<UBC_CBR_AIV_SHIFT) & UBC_CBR_AIV_MASK)
+
+#define UBC_CBR_INIT            0x20000000
+
+/* CRR  */
+#define UBC_CRR_RES             (0x01<<13)
+#define UBC_CRR_PCB             (0x01<<1)
+#define UBC_CRR_BIE             (0x01)
+
+#define UBC_CRR_INIT            0x00002000
+
+#else   /* CONFIG_CPU_SH4 */
 #define UBC_BARA                0xff200000
 #define UBC_BAMRA               0xff200004
 #define UBC_BBRA                0xff200008
@@ -22,6 +58,7 @@
 #define UBC_BDRB                0xff200018
 #define UBC_BDMRB               0xff20001c
 #define UBC_BRCR                0xff200020
+#endif  /* CONFIG_CPU_SH4 */
 
 #endif /* __ASM_CPU_SH4_UBC_H */