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-rw-r--r--include/asm-m68knommu/m520xsim.h54
1 files changed, 54 insertions, 0 deletions
diff --git a/include/asm-m68knommu/m520xsim.h b/include/asm-m68knommu/m520xsim.h
new file mode 100644
index 000000000000..6dc62869e62b
--- /dev/null
+++ b/include/asm-m68knommu/m520xsim.h
@@ -0,0 +1,54 @@
1/****************************************************************************/
2
3/*
4 * m520xsim.h -- ColdFire 5207/5208 System Integration Module support.
5 *
6 * (C) Copyright 2005, Intec Automation (mike@steroidmicros.com)
7 */
8
9/****************************************************************************/
10#ifndef m520xsim_h
11#define m520xsim_h
12/****************************************************************************/
13
14#include <linux/config.h>
15
16/*
17 * Define the 5282 SIM register set addresses.
18 */
19#define MCFICM_INTC0 0x48000 /* Base for Interrupt Ctrl 0 */
20#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
21#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
22#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
23#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
24#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
25#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
26#define MCFINTC_ICR0 0x40 /* Base ICR register */
27
28#define MCFINT_VECBASE 64
29#define MCFINT_UART0 26 /* Interrupt number for UART0 */
30#define MCFINT_UART1 27 /* Interrupt number for UART1 */
31#define MCFINT_UART2 28 /* Interrupt number for UART2 */
32#define MCFINT_QSPI 31 /* Interrupt number for QSPI */
33#define MCFINT_PIT1 4 /* Interrupt number for PIT1 (PIT0 in processor) */
34
35
36#define MCF_GPIO_PAR_UART (0xA4036)
37#define MCF_GPIO_PAR_FECI2C (0xA4033)
38#define MCF_GPIO_PAR_FEC (0xA4038)
39
40#define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0001)
41#define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0002)
42
43#define MCF_GPIO_PAR_UART_PAR_URXD1 (0x0040)
44#define MCF_GPIO_PAR_UART_PAR_UTXD1 (0x0080)
45
46#define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02)
47#define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04)
48
49#define ICR_INTRCONF 0x05
50#define MCFPIT_IMR MCFINTC_IMRL
51#define MCFPIT_IMR_IBIT (1 << MCFINT_PIT1)
52
53/****************************************************************************/
54#endif /* m520xsim_h */