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-rw-r--r--arch/mips/Kconfig26
-rw-r--r--arch/mips/Makefile4
-rw-r--r--arch/mips/kernel/Makefile4
-rw-r--r--arch/mips/kernel/r4k_switch.S2
-rw-r--r--arch/mips/kernel/traps.c2
-rw-r--r--arch/mips/lib-32/Makefile4
-rw-r--r--arch/mips/lib-64/Makefile4
-rw-r--r--arch/mips/mm/Makefile4
-rw-r--r--arch/mips/mm/cache.c4
-rw-r--r--arch/mips/mm/tlb-r4k.c2
-rw-r--r--arch/mips/mm/tlb-sb1.c2
-rw-r--r--arch/mips/oprofile/Makefile4
-rw-r--r--include/asm-mips/addrspace.h2
-rw-r--r--include/asm-mips/mach-mips/cpu-feature-overrides.h4
-rw-r--r--include/asm-mips/page.h2
-rw-r--r--include/asm-mips/pgtable-32.h6
-rw-r--r--include/asm-mips/pgtable-bits.h6
-rw-r--r--include/asm-mips/pgtable.h6
18 files changed, 51 insertions, 37 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 0ca63e7ce0a7..a4c62c72aa89 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1050,14 +1050,28 @@ choice
1050 prompt "CPU type" 1050 prompt "CPU type"
1051 default CPU_R4X00 1051 default CPU_R4X00
1052 1052
1053config CPU_MIPS32 1053config CPU_MIPS32_R1
1054 bool "MIPS32" 1054 bool "MIPS32 Release 1"
1055 select CPU_SUPPORTS_32BIT_KERNEL 1055 select CPU_SUPPORTS_32BIT_KERNEL
1056 select CPU_HAS_PREFETCH
1057 help
1058 Choose this option to build a kernel for release 1 or later of the
1059 MIPS32 architecture. Most modern embedded systems with a 32-bit
1060 MIPS processor are based on a MIPS32 processor. If you know the
1061 specific type of processor in your system, choose those that one
1062 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
1056 1063
1057config CPU_MIPS64 1064config CPU_MIPS64_R1
1058 bool "MIPS64" 1065 bool "MIPS64 Release 1"
1059 select CPU_SUPPORTS_32BIT_KERNEL 1066 select CPU_SUPPORTS_32BIT_KERNEL
1060 select CPU_SUPPORTS_64BIT_KERNEL 1067 select CPU_SUPPORTS_64BIT_KERNEL
1068 select CPU_HAS_PREFETCH
1069 help
1070 Choose this option to build a kernel for release 1 or later of the
1071 MIPS64 architecture. Many modern embedded systems with a 64-bit
1072 MIPS processor are based on a MIPS64 processor. If you know the
1073 specific type of processor in your system, choose those that one
1074 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
1061 1075
1062config CPU_R3000 1076config CPU_R3000
1063 bool "R3000" 1077 bool "R3000"
@@ -1253,7 +1267,7 @@ config SB1_PASS_2_1_WORKAROUNDS
1253 1267
1254config 64BIT_PHYS_ADDR 1268config 64BIT_PHYS_ADDR
1255 bool "Support for 64-bit physical address space" 1269 bool "Support for 64-bit physical address space"
1256 depends on (CPU_R4X00 || CPU_R5000 || CPU_RM7000 || CPU_RM9000 || CPU_R10000 || CPU_SB1 || CPU_MIPS32 || CPU_MIPS64) && 32BIT 1270 depends on (CPU_R4X00 || CPU_R5000 || CPU_RM7000 || CPU_RM9000 || CPU_R10000 || CPU_SB1 || CPU_MIPS32_R1 || CPU_MIPS64_R1) && 32BIT
1257 1271
1258config CPU_ADVANCED 1272config CPU_ADVANCED
1259 bool "Override CPU Options" 1273 bool "Override CPU Options"
@@ -1276,7 +1290,7 @@ config CPU_HAS_LLSC
1276 1290
1277config CPU_HAS_LLDSCD 1291config CPU_HAS_LLDSCD
1278 bool "lld/scd Instructions available" if CPU_ADVANCED 1292 bool "lld/scd Instructions available" if CPU_ADVANCED
1279 default y if !CPU_ADVANCED && !CPU_R3000 && !CPU_VR41XX && !CPU_TX39XX && !CPU_MIPS32 1293 default y if !CPU_ADVANCED && !CPU_R3000 && !CPU_VR41XX && !CPU_TX39XX && !CPU_MIPS32_R1
1280 help 1294 help
1281 Say Y here if your CPU has the lld and scd instructions, the 64-bit 1295 Say Y here if your CPU has the lld and scd instructions, the 64-bit
1282 equivalents of ll and sc. Say Y here for better performance, N if 1296 equivalents of ll and sc. Say Y here for better performance, N if
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index bbf902796390..56e1d42a5796 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -182,11 +182,11 @@ cflags-$(CONFIG_CPU_TX49XX) += \
182 $(call set_gccflags,r4600,mips3,r4600,mips3,mips2) \ 182 $(call set_gccflags,r4600,mips3,r4600,mips3,mips2) \
183 -Wa,--trap 183 -Wa,--trap
184 184
185cflags-$(CONFIG_CPU_MIPS32) += \ 185cflags-$(CONFIG_CPU_MIPS32_R1) += \
186 $(call set_gccflags,mips32,mips32,r4600,mips3,mips2) \ 186 $(call set_gccflags,mips32,mips32,r4600,mips3,mips2) \
187 -Wa,--trap 187 -Wa,--trap
188 188
189cflags-$(CONFIG_CPU_MIPS64) += \ 189cflags-$(CONFIG_CPU_MIPS64_R1) += \
190 $(call set_gccflags,mips64,mips64,r4600,mips3,mips2) \ 190 $(call set_gccflags,mips64,mips64,r4600,mips3,mips2) \
191 -Wa,--trap 191 -Wa,--trap
192 192
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index d54964d52c83..0867417032f2 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -28,8 +28,8 @@ obj-$(CONFIG_CPU_RM9000) += r4k_fpu.o r4k_switch.o
28obj-$(CONFIG_CPU_NEVADA) += r4k_fpu.o r4k_switch.o 28obj-$(CONFIG_CPU_NEVADA) += r4k_fpu.o r4k_switch.o
29obj-$(CONFIG_CPU_R10000) += r4k_fpu.o r4k_switch.o 29obj-$(CONFIG_CPU_R10000) += r4k_fpu.o r4k_switch.o
30obj-$(CONFIG_CPU_SB1) += r4k_fpu.o r4k_switch.o 30obj-$(CONFIG_CPU_SB1) += r4k_fpu.o r4k_switch.o
31obj-$(CONFIG_CPU_MIPS32) += r4k_fpu.o r4k_switch.o 31obj-$(CONFIG_CPU_MIPS32_R1) += r4k_fpu.o r4k_switch.o
32obj-$(CONFIG_CPU_MIPS64) += r4k_fpu.o r4k_switch.o 32obj-$(CONFIG_CPU_MIPS64_R1) += r4k_fpu.o r4k_switch.o
33obj-$(CONFIG_CPU_R6000) += r6000_fpu.o r4k_switch.o 33obj-$(CONFIG_CPU_R6000) += r6000_fpu.o r4k_switch.o
34 34
35obj-$(CONFIG_SMP) += smp.o 35obj-$(CONFIG_SMP) += smp.o
diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S
index d2afbd19a9c8..27361f44defe 100644
--- a/arch/mips/kernel/r4k_switch.S
+++ b/arch/mips/kernel/r4k_switch.S
@@ -165,7 +165,7 @@ LEAF(_init_fpu)
1651: 1651:
166#endif 166#endif
167 167
168#ifdef CONFIG_CPU_MIPS32 168#ifdef CONFIG_CPU_MIPS32_R1
169 mtc1 t1, $f0 169 mtc1 t1, $f0
170 mtc1 t1, $f1 170 mtc1 t1, $f1
171 mtc1 t1, $f2 171 mtc1 t1, $f2
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 46636a2fe982..b2fa607eeeb8 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -864,7 +864,7 @@ asmlinkage void cache_parity_error(void)
864 reg_val & (1<<22) ? "E0 " : ""); 864 reg_val & (1<<22) ? "E0 " : "");
865 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); 865 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
866 866
867#if defined(CONFIG_CPU_MIPS32) || defined (CONFIG_CPU_MIPS64) 867#if defined(CONFIG_CPU_MIPS32_R1) || defined(CONFIG_CPU_MIPS64_R1)
868 if (reg_val & (1<<22)) 868 if (reg_val & (1<<22))
869 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); 869 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
870 870
diff --git a/arch/mips/lib-32/Makefile b/arch/mips/lib-32/Makefile
index ad285786e74b..8119996736ae 100644
--- a/arch/mips/lib-32/Makefile
+++ b/arch/mips/lib-32/Makefile
@@ -4,8 +4,8 @@
4 4
5lib-y += csum_partial.o memset.o watch.o 5lib-y += csum_partial.o memset.o watch.o
6 6
7obj-$(CONFIG_CPU_MIPS32) += dump_tlb.o 7obj-$(CONFIG_CPU_MIPS32_R1) += dump_tlb.o
8obj-$(CONFIG_CPU_MIPS64) += dump_tlb.o 8obj-$(CONFIG_CPU_MIPS64_R1) += dump_tlb.o
9obj-$(CONFIG_CPU_NEVADA) += dump_tlb.o 9obj-$(CONFIG_CPU_NEVADA) += dump_tlb.o
10obj-$(CONFIG_CPU_R10000) += dump_tlb.o 10obj-$(CONFIG_CPU_R10000) += dump_tlb.o
11obj-$(CONFIG_CPU_R3000) += r3k_dump_tlb.o 11obj-$(CONFIG_CPU_R3000) += r3k_dump_tlb.o
diff --git a/arch/mips/lib-64/Makefile b/arch/mips/lib-64/Makefile
index ad285786e74b..8119996736ae 100644
--- a/arch/mips/lib-64/Makefile
+++ b/arch/mips/lib-64/Makefile
@@ -4,8 +4,8 @@
4 4
5lib-y += csum_partial.o memset.o watch.o 5lib-y += csum_partial.o memset.o watch.o
6 6
7obj-$(CONFIG_CPU_MIPS32) += dump_tlb.o 7obj-$(CONFIG_CPU_MIPS32_R1) += dump_tlb.o
8obj-$(CONFIG_CPU_MIPS64) += dump_tlb.o 8obj-$(CONFIG_CPU_MIPS64_R1) += dump_tlb.o
9obj-$(CONFIG_CPU_NEVADA) += dump_tlb.o 9obj-$(CONFIG_CPU_NEVADA) += dump_tlb.o
10obj-$(CONFIG_CPU_R10000) += dump_tlb.o 10obj-$(CONFIG_CPU_R10000) += dump_tlb.o
11obj-$(CONFIG_CPU_R3000) += r3k_dump_tlb.o 11obj-$(CONFIG_CPU_R3000) += r3k_dump_tlb.o
diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile
index b56a0abdc3d4..74fea868af33 100644
--- a/arch/mips/mm/Makefile
+++ b/arch/mips/mm/Makefile
@@ -9,8 +9,8 @@ obj-$(CONFIG_32BIT) += ioremap.o pgtable-32.o
9obj-$(CONFIG_64BIT) += pgtable-64.o 9obj-$(CONFIG_64BIT) += pgtable-64.o
10obj-$(CONFIG_HIGHMEM) += highmem.o 10obj-$(CONFIG_HIGHMEM) += highmem.o
11 11
12obj-$(CONFIG_CPU_MIPS32) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o 12obj-$(CONFIG_CPU_MIPS32_R1) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
13obj-$(CONFIG_CPU_MIPS64) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o 13obj-$(CONFIG_CPU_MIPS64_R1) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
14obj-$(CONFIG_CPU_NEVADA) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o 14obj-$(CONFIG_CPU_NEVADA) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
15obj-$(CONFIG_CPU_R10000) += c-r4k.o cex-gen.o pg-r4k.o tlb-andes.o 15obj-$(CONFIG_CPU_R10000) += c-r4k.o cex-gen.o pg-r4k.o tlb-andes.o
16obj-$(CONFIG_CPU_R3000) += c-r3k.o tlb-r3k.o pg-r4k.o 16obj-$(CONFIG_CPU_R3000) += c-r3k.o tlb-r3k.o pg-r4k.o
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index eaecb8631973..172293b58390 100644
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -118,8 +118,8 @@ void __init cpu_cache_init(void)
118#if defined(CONFIG_CPU_R4X00) || defined(CONFIG_CPU_VR41XX) || \ 118#if defined(CONFIG_CPU_R4X00) || defined(CONFIG_CPU_VR41XX) || \
119 defined(CONFIG_CPU_R4300) || defined(CONFIG_CPU_R5000) || \ 119 defined(CONFIG_CPU_R4300) || defined(CONFIG_CPU_R5000) || \
120 defined(CONFIG_CPU_NEVADA) || defined(CONFIG_CPU_R5432) || \ 120 defined(CONFIG_CPU_NEVADA) || defined(CONFIG_CPU_R5432) || \
121 defined(CONFIG_CPU_R5500) || defined(CONFIG_CPU_MIPS32) || \ 121 defined(CONFIG_CPU_R5500) || defined(CONFIG_CPU_MIPS32_R1) || \
122 defined(CONFIG_CPU_MIPS64) || defined(CONFIG_CPU_TX49XX) || \ 122 defined(CONFIG_CPU_MIPS64_R1) || defined(CONFIG_CPU_TX49XX) || \
123 defined(CONFIG_CPU_RM7000) || defined(CONFIG_CPU_RM9000) 123 defined(CONFIG_CPU_RM7000) || defined(CONFIG_CPU_RM9000)
124 ld_mmu_r4xx0(); 124 ld_mmu_r4xx0();
125#endif 125#endif
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index 316c8a3d6b53..8297970f0bb1 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -263,7 +263,7 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
263 idx = read_c0_index(); 263 idx = read_c0_index();
264 ptep = pte_offset_map(pmdp, address); 264 ptep = pte_offset_map(pmdp, address);
265 265
266#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) 266#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
267 write_c0_entrylo0(ptep->pte_high); 267 write_c0_entrylo0(ptep->pte_high);
268 ptep++; 268 ptep++;
269 write_c0_entrylo1(ptep->pte_high); 269 write_c0_entrylo1(ptep->pte_high);
diff --git a/arch/mips/mm/tlb-sb1.c b/arch/mips/mm/tlb-sb1.c
index bba7130e7547..f55fbbe473a5 100644
--- a/arch/mips/mm/tlb-sb1.c
+++ b/arch/mips/mm/tlb-sb1.c
@@ -320,7 +320,7 @@ void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
320 idx = read_c0_index(); 320 idx = read_c0_index();
321 ptep = pte_offset_map(pmdp, address); 321 ptep = pte_offset_map(pmdp, address);
322 322
323#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) 323#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
324 write_c0_entrylo0(ptep->pte_high); 324 write_c0_entrylo0(ptep->pte_high);
325 ptep++; 325 ptep++;
326 write_c0_entrylo1(ptep->pte_high); 326 write_c0_entrylo1(ptep->pte_high);
diff --git a/arch/mips/oprofile/Makefile b/arch/mips/oprofile/Makefile
index 354261d37d62..17b411b22063 100644
--- a/arch/mips/oprofile/Makefile
+++ b/arch/mips/oprofile/Makefile
@@ -10,6 +10,6 @@ DRIVER_OBJS = $(addprefix ../../../drivers/oprofile/, \
10 10
11oprofile-y := $(DRIVER_OBJS) common.o 11oprofile-y := $(DRIVER_OBJS) common.o
12 12
13oprofile-$(CONFIG_CPU_MIPS32) += op_model_mipsxx.o 13oprofile-$(CONFIG_CPU_MIPS32_R1) += op_model_mipsxx.o
14oprofile-$(CONFIG_CPU_MIPS64) += op_model_mipsxx.o 14oprofile-$(CONFIG_CPU_MIPS64_R1) += op_model_mipsxx.o
15oprofile-$(CONFIG_CPU_RM9000) += op_model_rm9000.o 15oprofile-$(CONFIG_CPU_RM9000) += op_model_rm9000.o
diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h
index c806eef41e7f..a54cdd417956 100644
--- a/include/asm-mips/addrspace.h
+++ b/include/asm-mips/addrspace.h
@@ -131,7 +131,7 @@
131 || defined (CONFIG_CPU_R5000) \ 131 || defined (CONFIG_CPU_R5000) \
132 || defined (CONFIG_CPU_NEVADA) \ 132 || defined (CONFIG_CPU_NEVADA) \
133 || defined (CONFIG_CPU_TX49XX) \ 133 || defined (CONFIG_CPU_TX49XX) \
134 || defined (CONFIG_CPU_MIPS64) 134 || defined (CONFIG_CPU_MIPS64_R1)
135#define KUSIZE _LLCONST_(0x0000010000000000) /* 2^^40 */ 135#define KUSIZE _LLCONST_(0x0000010000000000) /* 2^^40 */
136#define KUSIZE_64 _LLCONST_(0x0000010000000000) /* 2^^40 */ 136#define KUSIZE_64 _LLCONST_(0x0000010000000000) /* 2^^40 */
137#define K0SIZE _LLCONST_(0x0000001000000000) /* 2^^36 */ 137#define K0SIZE _LLCONST_(0x0000001000000000) /* 2^^36 */
diff --git a/include/asm-mips/mach-mips/cpu-feature-overrides.h b/include/asm-mips/mach-mips/cpu-feature-overrides.h
index 6f51be571bf0..7a1189fdf1aa 100644
--- a/include/asm-mips/mach-mips/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-mips/cpu-feature-overrides.h
@@ -14,7 +14,7 @@
14/* 14/*
15 * CPU feature overrides for MIPS boards 15 * CPU feature overrides for MIPS boards
16 */ 16 */
17#ifdef CONFIG_CPU_MIPS32 17#ifdef CONFIG_CPU_MIPS32_R1
18#define cpu_has_tlb 1 18#define cpu_has_tlb 1
19#define cpu_has_4kex 1 19#define cpu_has_4kex 1
20#define cpu_has_4ktlb 1 20#define cpu_has_4ktlb 1
@@ -39,7 +39,7 @@
39/* #define cpu_has_subset_pcaches ? */ 39/* #define cpu_has_subset_pcaches ? */
40#endif 40#endif
41 41
42#ifdef CONFIG_CPU_MIPS64 42#ifdef CONFIG_CPU_MIPS64_R1
43#define cpu_has_tlb 1 43#define cpu_has_tlb 1
44#define cpu_has_4kex 1 44#define cpu_has_4kex 1
45#define cpu_has_4ktlb 1 45#define cpu_has_4ktlb 1
diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h
index ee25a779bf49..0076a537cf0c 100644
--- a/include/asm-mips/page.h
+++ b/include/asm-mips/page.h
@@ -76,7 +76,7 @@ static inline void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
76 * These are used to make use of C type-checking.. 76 * These are used to make use of C type-checking..
77 */ 77 */
78#ifdef CONFIG_64BIT_PHYS_ADDR 78#ifdef CONFIG_64BIT_PHYS_ADDR
79 #ifdef CONFIG_CPU_MIPS32 79 #ifdef CONFIG_CPU_MIPS32_R1
80 typedef struct { unsigned long pte_low, pte_high; } pte_t; 80 typedef struct { unsigned long pte_low, pte_high; } pte_t;
81 #define pte_val(x) ((x).pte_low | ((unsigned long long)(x).pte_high << 32)) 81 #define pte_val(x) ((x).pte_low | ((unsigned long long)(x).pte_high << 32))
82 #else 82 #else
diff --git a/include/asm-mips/pgtable-32.h b/include/asm-mips/pgtable-32.h
index 9b4d39d9f2f0..217afc375a84 100644
--- a/include/asm-mips/pgtable-32.h
+++ b/include/asm-mips/pgtable-32.h
@@ -116,7 +116,7 @@ static inline void pmd_clear(pmd_t *pmdp)
116 pmd_val(*pmdp) = ((unsigned long) invalid_pte_table); 116 pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
117} 117}
118 118
119#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) 119#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
120#define pte_page(x) pfn_to_page(pte_pfn(x)) 120#define pte_page(x) pfn_to_page(pte_pfn(x))
121#define pte_pfn(x) ((unsigned long)((x).pte_high >> 6)) 121#define pte_pfn(x) ((unsigned long)((x).pte_high >> 6))
122static inline pte_t 122static inline pte_t
@@ -139,7 +139,7 @@ pfn_pte(unsigned long pfn, pgprot_t prot)
139#define pte_pfn(x) ((unsigned long)((x).pte >> PAGE_SHIFT)) 139#define pte_pfn(x) ((unsigned long)((x).pte >> PAGE_SHIFT))
140#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) 140#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
141#endif 141#endif
142#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */ 142#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) */
143 143
144#define __pgd_offset(address) pgd_index(address) 144#define __pgd_offset(address) pgd_index(address)
145#define __pud_offset(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) 145#define __pud_offset(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
@@ -202,7 +202,7 @@ pfn_pte(unsigned long pfn, pgprot_t prot)
202 */ 202 */
203#define PTE_FILE_MAX_BITS 27 203#define PTE_FILE_MAX_BITS 27
204 204
205#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) 205#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
206 /* fixme */ 206 /* fixme */
207#define pte_to_pgoff(_pte) (((_pte).pte_high >> 6) + ((_pte).pte_high & 0x3f)) 207#define pte_to_pgoff(_pte) (((_pte).pte_high >> 6) + ((_pte).pte_high & 0x3f))
208#define pgoff_to_pte(off) \ 208#define pgoff_to_pte(off) \
diff --git a/include/asm-mips/pgtable-bits.h b/include/asm-mips/pgtable-bits.h
index 3aad751ccd5f..01e76e932e3f 100644
--- a/include/asm-mips/pgtable-bits.h
+++ b/include/asm-mips/pgtable-bits.h
@@ -33,7 +33,7 @@
33 * unpredictable things. The code (when it is written) to deal with 33 * unpredictable things. The code (when it is written) to deal with
34 * this problem will be in the update_mmu_cache() code for the r4k. 34 * this problem will be in the update_mmu_cache() code for the r4k.
35 */ 35 */
36#if defined(CONFIG_CPU_MIPS32) && defined(CONFIG_64BIT_PHYS_ADDR) 36#if defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR)
37 37
38#define _PAGE_PRESENT (1<<6) /* implemented in software */ 38#define _PAGE_PRESENT (1<<6) /* implemented in software */
39#define _PAGE_READ (1<<7) /* implemented in software */ 39#define _PAGE_READ (1<<7) /* implemented in software */
@@ -123,7 +123,7 @@
123 123
124#endif 124#endif
125#endif 125#endif
126#endif /* defined(CONFIG_CPU_MIPS32) && defined(CONFIG_64BIT_PHYS_ADDR) */ 126#endif /* defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR) */
127 127
128#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED) 128#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
129#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) 129#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
@@ -140,7 +140,7 @@
140#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_COW 140#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_COW
141#endif 141#endif
142 142
143#if defined(CONFIG_CPU_MIPS32) && defined(CONFIG_64BIT_PHYS_ADDR) 143#if defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR)
144#define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 3) 144#define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 3)
145#else 145#else
146#define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 9) 146#define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 9)
diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h
index 754ec6c5a8f7..9f75baf11e25 100644
--- a/include/asm-mips/pgtable.h
+++ b/include/asm-mips/pgtable.h
@@ -82,7 +82,7 @@ extern void paging_init(void);
82#define pte_none(pte) (!(pte_val(pte) & ~_PAGE_GLOBAL)) 82#define pte_none(pte) (!(pte_val(pte) & ~_PAGE_GLOBAL))
83#define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT) 83#define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
84 84
85#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) 85#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
86static inline void set_pte(pte_t *ptep, pte_t pte) 86static inline void set_pte(pte_t *ptep, pte_t pte)
87{ 87{
88 ptep->pte_high = pte.pte_high; 88 ptep->pte_high = pte.pte_high;
@@ -170,7 +170,7 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
170 * Undefined behaviour if not.. 170 * Undefined behaviour if not..
171 */ 171 */
172static inline int pte_user(pte_t pte) { BUG(); return 0; } 172static inline int pte_user(pte_t pte) { BUG(); return 0; }
173#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) 173#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
174static inline int pte_read(pte_t pte) { return (pte).pte_low & _PAGE_READ; } 174static inline int pte_read(pte_t pte) { return (pte).pte_low & _PAGE_READ; }
175static inline int pte_write(pte_t pte) { return (pte).pte_low & _PAGE_WRITE; } 175static inline int pte_write(pte_t pte) { return (pte).pte_low & _PAGE_WRITE; }
176static inline int pte_dirty(pte_t pte) { return (pte).pte_low & _PAGE_MODIFIED; } 176static inline int pte_dirty(pte_t pte) { return (pte).pte_low & _PAGE_MODIFIED; }
@@ -329,7 +329,7 @@ static inline pgprot_t pgprot_noncached(pgprot_t _prot)
329 */ 329 */
330#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) 330#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
331 331
332#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) 332#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
333static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 333static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
334{ 334{
335 pte.pte_low &= _PAGE_CHG_MASK; 335 pte.pte_low &= _PAGE_CHG_MASK;