4 files changed, 64 insertions, 0 deletions

diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts
index 5fdcb69554f2..4f2c3af2e052 100644
--- a/arch/powerpc/boot/dts/mpc8541cds.dts
+++ b/arch/powerpc/boot/dts/mpc8541cds.dts
@@ -48,6 +48,22 @@
                 reg = <e0000000 00100000>;      // CCSRBAR 1M
                 bus-frequency = <0>;
 
+                memory-controller@2000 {
+                        compatible = "fsl,8541-memory-controller";
+                        reg = <2000 1000>;
+                        interrupt-parent = <&mpic>;
+                        interrupts = <2 2>;
+                };
+
+                l2-cache-controller@20000 {
+                        compatible = "fsl,8541-l2-cache-controller";
+                        reg = <20000 1000>;
+                        cache-line-size = <20>; // 32 bytes
+                        cache-size = <40000>;   // L2, 256K
+                        interrupt-parent = <&mpic>;
+                        interrupts = <0 2>;
+                };
+
                 i2c@3000 {
                         device_type = "i2c";
                         compatible = "fsl-i2c";
diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts
index 6b084605bb4b..3033599e74e8 100644
--- a/arch/powerpc/boot/dts/mpc8544ds.dts
+++ b/arch/powerpc/boot/dts/mpc8544ds.dts
@@ -48,6 +48,22 @@
                 reg = <e0000000 00100000>;      // CCSRBAR 1M
                 bus-frequency = <0>;            // Filled out by uboot.
 
+                memory-controller@2000 {
+                        compatible = "fsl,8544-memory-controller";
+                        reg = <2000 1000>;
+                        interrupt-parent = <&mpic>;
+                        interrupts = <2 2>;
+                };
+
+                l2-cache-controller@20000 {
+                        compatible = "fsl,8544-l2-cache-controller";
+                        reg = <20000 1000>;
+                        cache-line-size = <20>; // 32 bytes
+                        cache-size = <40000>;   // L2, 256K
+                        interrupt-parent = <&mpic>;
+                        interrupts = <0 2>;
+                };
+
                 i2c@3000 {
                         device_type = "i2c";
                         compatible = "fsl-i2c";
diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts
index 68a4795720dc..951ed92f1154 100644
--- a/arch/powerpc/boot/dts/mpc8555cds.dts
+++ b/arch/powerpc/boot/dts/mpc8555cds.dts
@@ -48,6 +48,22 @@
                 reg = <e0000000 00100000>;      // CCSRBAR 1M
                 bus-frequency = <0>;
 
+                memory-controller@2000 {
+                        compatible = "fsl,8555-memory-controller";
+                        reg = <2000 1000>;
+                        interrupt-parent = <&mpic>;
+                        interrupts = <2 2>;
+                };
+
+                l2-cache-controller@20000 {
+                        compatible = "fsl,8555-l2-cache-controller";
+                        reg = <20000 1000>;
+                        cache-line-size = <20>; // 32 bytes
+                        cache-size = <40000>;   // L2, 256K
+                        interrupt-parent = <&mpic>;
+                        interrupts = <0 2>;
+                };
+
                 i2c@3000 {
                         device_type = "i2c";
                         compatible = "fsl-i2c";
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index 948a3b61bd4a..a123ec9456bc 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -57,6 +57,22 @@
                 reg = <e0000000 00100000>;
                 bus-frequency = <0>;
 
+                memory-controller@2000 {
+                        compatible = "fsl,8568-memory-controller";
+                        reg = <2000 1000>;
+                        interrupt-parent = <&mpic>;
+                        interrupts = <2 2>;
+                };
+
+                l2-cache-controller@20000 {
+                        compatible = "fsl,8568-l2-cache-controller";
+                        reg = <20000 1000>;
+                        cache-line-size = <20>; // 32 bytes
+                        cache-size = <80000>;   // L2, 512K
+                        interrupt-parent = <&mpic>;
+                        interrupts = <0 2>;
+                };
+
                 i2c@3000 {
                         device_type = "i2c";
                         compatible = "fsl-i2c";