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-rw-r--r--arch/mips/Kconfig22
-rw-r--r--arch/mips/Makefile7
-rw-r--r--arch/mips/cobalt/setup.c4
-rw-r--r--arch/mips/configs/rb532_defconfig1314
-rw-r--r--arch/mips/kernel/linux32.c17
-rw-r--r--arch/mips/kernel/scall32-o32.S2
-rw-r--r--arch/mips/kernel/scall64-64.S2
-rw-r--r--arch/mips/kernel/scall64-n32.S2
-rw-r--r--arch/mips/kernel/scall64-o32.S2
-rw-r--r--arch/mips/kernel/syscall.c9
-rw-r--r--arch/mips/math-emu/kernel_linkage.c1
-rw-r--r--arch/mips/pci/Makefile1
-rw-r--r--arch/mips/pci/fixup-rc32434.c69
-rw-r--r--arch/mips/pci/ops-rc32434.c207
-rw-r--r--arch/mips/pci/pci-rc32434.c221
-rw-r--r--arch/mips/pci/pci.c2
-rw-r--r--arch/mips/rb532/Makefile7
-rw-r--r--arch/mips/rb532/devices.c331
-rw-r--r--arch/mips/rb532/gpio.c220
-rw-r--r--arch/mips/rb532/irq.c209
-rw-r--r--arch/mips/rb532/prom.c158
-rw-r--r--arch/mips/rb532/serial.c53
-rw-r--r--arch/mips/rb532/setup.c79
-rw-r--r--arch/mips/rb532/time.c67
-rw-r--r--arch/mips/sgi-ip22/ip22-platform.c3
-rw-r--r--arch/mips/sgi-ip22/ip28-berr.c4
-rw-r--r--arch/mips/sgi-ip32/ip32-platform.c13
-rw-r--r--arch/mips/txx9/Kconfig2
-rw-r--r--arch/mips/txx9/generic/Makefile4
-rw-r--r--arch/mips/txx9/generic/irq_tx4927.c2
-rw-r--r--arch/mips/txx9/generic/irq_tx4938.c2
-rw-r--r--arch/mips/txx9/generic/mem_tx4927.c94
-rw-r--r--arch/mips/txx9/generic/mem_tx4938.c124
-rw-r--r--arch/mips/txx9/generic/setup.c38
-rw-r--r--arch/mips/txx9/generic/setup_tx4927.c194
-rw-r--r--arch/mips/txx9/generic/setup_tx4938.c259
-rw-r--r--arch/mips/txx9/jmr3927/setup.c8
-rw-r--r--arch/mips/txx9/rbtx4927/irq.c12
-rw-r--r--arch/mips/txx9/rbtx4927/prom.c6
-rw-r--r--arch/mips/txx9/rbtx4927/setup.c89
-rw-r--r--arch/mips/txx9/rbtx4938/prom.c6
-rw-r--r--arch/mips/txx9/rbtx4938/setup.c231
-rw-r--r--include/asm-mips/bitops.h6
-rw-r--r--include/asm-mips/bootinfo.h6
-rw-r--r--include/asm-mips/fpu.h2
-rw-r--r--include/asm-mips/mach-rc32434/cpu-feature-overrides.h81
-rw-r--r--include/asm-mips/mach-rc32434/ddr.h141
-rw-r--r--include/asm-mips/mach-rc32434/dma.h103
-rw-r--r--include/asm-mips/mach-rc32434/dma_v.h52
-rw-r--r--include/asm-mips/mach-rc32434/eth.h220
-rw-r--r--include/asm-mips/mach-rc32434/gpio.h126
-rw-r--r--include/asm-mips/mach-rc32434/integ.h59
-rw-r--r--include/asm-mips/mach-rc32434/irq.h8
-rw-r--r--include/asm-mips/mach-rc32434/pci.h481
-rw-r--r--include/asm-mips/mach-rc32434/prom.h44
-rw-r--r--include/asm-mips/mach-rc32434/rb.h81
-rw-r--r--include/asm-mips/mach-rc32434/rc32434.h61
-rw-r--r--include/asm-mips/mach-rc32434/timer.h65
-rw-r--r--include/asm-mips/mach-rc32434/war.h25
-rw-r--r--include/asm-mips/mips-boards/atlas.h80
-rw-r--r--include/asm-mips/mips-boards/atlasint.h109
-rw-r--r--include/asm-mips/mips-boards/maltasmp.h36
-rw-r--r--include/asm-mips/mips-boards/saa9730_uart.h69
-rw-r--r--include/asm-mips/mips-boards/sead.h36
-rw-r--r--include/asm-mips/mips-boards/seadint.h28
-rw-r--r--include/asm-mips/page.h3
-rw-r--r--include/asm-mips/pci.h1
-rw-r--r--include/asm-mips/setup.h2
-rw-r--r--include/asm-mips/txx9/generic.h7
-rw-r--r--include/asm-mips/txx9/rbtx4927.h26
-rw-r--r--include/asm-mips/txx9/rbtx4938.h52
-rw-r--r--include/asm-mips/txx9/tx3927.h19
-rw-r--r--include/asm-mips/txx9/tx4927.h63
-rw-r--r--include/asm-mips/txx9/tx4938.h243
74 files changed, 5240 insertions, 1192 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index d21df5f1b1f3..b9c754f4070c 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -330,6 +330,7 @@ config SGI_IP22
330 select SGI_HAS_DS1286 330 select SGI_HAS_DS1286
331 select SGI_HAS_I8042 331 select SGI_HAS_I8042
332 select SGI_HAS_INDYDOG 332 select SGI_HAS_INDYDOG
333 select SGI_HAS_HAL2
333 select SGI_HAS_SEEQ 334 select SGI_HAS_SEEQ
334 select SGI_HAS_WD93 335 select SGI_HAS_WD93
335 select SGI_HAS_ZILOG 336 select SGI_HAS_ZILOG
@@ -386,7 +387,6 @@ config SGI_IP28
386 select SGI_HAS_I8042 387 select SGI_HAS_I8042
387 select SGI_HAS_INDYDOG 388 select SGI_HAS_INDYDOG
388 select SGI_HAS_HAL2 389 select SGI_HAS_HAL2
389 select SGI_HAS_HAL2
390 select SGI_HAS_SEEQ 390 select SGI_HAS_SEEQ
391 select SGI_HAS_WD93 391 select SGI_HAS_WD93
392 select SGI_HAS_ZILOG 392 select SGI_HAS_ZILOG
@@ -558,6 +558,24 @@ config MACH_TX39XX
558config MACH_TX49XX 558config MACH_TX49XX
559 bool "Toshiba TX49 series based machines" 559 bool "Toshiba TX49 series based machines"
560 560
561config MIKROTIK_RB532
562 bool "Mikrotik RB532 boards"
563 select CEVT_R4K
564 select CSRC_R4K
565 select DMA_NONCOHERENT
566 select GENERIC_HARDIRQS_NO__DO_IRQ
567 select HW_HAS_PCI
568 select IRQ_CPU
569 select SYS_HAS_CPU_MIPS32_R1
570 select SYS_SUPPORTS_32BIT_KERNEL
571 select SYS_SUPPORTS_LITTLE_ENDIAN
572 select SWAP_IO_SPACE
573 select BOOT_RAW
574 select GENERIC_GPIO
575 help
576 Support the Mikrotik(tm) RouterBoard 532 series,
577 based on the IDT RC32434 SoC.
578
561config WR_PPMC 579config WR_PPMC
562 bool "Wind River PPMC board" 580 bool "Wind River PPMC board"
563 select CEVT_R4K 581 select CEVT_R4K
@@ -899,7 +917,7 @@ config BOOT_ELF32
899 917
900config MIPS_L1_CACHE_SHIFT 918config MIPS_L1_CACHE_SHIFT
901 int 919 int
902 default "4" if MACH_DECSTATION 920 default "4" if MACH_DECSTATION || MIKROTIK_RB532
903 default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM 921 default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM
904 default "4" if PMC_MSP4200_EVAL 922 default "4" if PMC_MSP4200_EVAL
905 default "5" 923 default "5"
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 356453322b49..9aab51caf16a 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -560,6 +560,13 @@ load-$(CONFIG_MACH_TX49XX) += 0xffffffff80100000
560core-$(CONFIG_TOSHIBA_JMR3927) += arch/mips/txx9/jmr3927/ 560core-$(CONFIG_TOSHIBA_JMR3927) += arch/mips/txx9/jmr3927/
561 561
562# 562#
563# Routerboard 532 board
564#
565core-$(CONFIG_MIKROTIK_RB532) += arch/mips/rb532/
566cflags-$(CONFIG_MIKROTIK_RB532) += -Iinclude/asm-mips/mach-rc32434
567load-$(CONFIG_MIKROTIK_RB532) += 0xffffffff80101000
568
569#
563# Toshiba RBTX4927 board or 570# Toshiba RBTX4927 board or
564# Toshiba RBTX4937 board 571# Toshiba RBTX4937 board
565# 572#
diff --git a/arch/mips/cobalt/setup.c b/arch/mips/cobalt/setup.c
index dd23beb8604f..b51644227241 100644
--- a/arch/mips/cobalt/setup.c
+++ b/arch/mips/cobalt/setup.c
@@ -81,8 +81,8 @@ void __init plat_mem_setup(void)
81 81
82 set_io_port_base(CKSEG1ADDR(GT_DEF_PCI0_IO_BASE)); 82 set_io_port_base(CKSEG1ADDR(GT_DEF_PCI0_IO_BASE));
83 83
84 /* I/O port resource must include LCD/buttons */ 84 /* I/O port resource */
85 ioport_resource.end = 0x0fffffff; 85 ioport_resource.end = 0x01ffffff;
86 86
87 /* These resources have been reserved by VIA SuperI/O chip. */ 87 /* These resources have been reserved by VIA SuperI/O chip. */
88 for (i = 0; i < ARRAY_SIZE(cobalt_reserved_resources); i++) 88 for (i = 0; i < ARRAY_SIZE(cobalt_reserved_resources); i++)
diff --git a/arch/mips/configs/rb532_defconfig b/arch/mips/configs/rb532_defconfig
new file mode 100644
index 000000000000..f28dc32974e5
--- /dev/null
+++ b/arch/mips/configs/rb532_defconfig
@@ -0,0 +1,1314 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.25
4# Mon Apr 28 12:24:17 2008
5#
6CONFIG_MIPS=y
7
8#
9# Machine selection
10#
11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_BCM47XX is not set
14# CONFIG_MIPS_COBALT is not set
15# CONFIG_MACH_DECSTATION is not set
16# CONFIG_MACH_JAZZ is not set
17# CONFIG_LASAT is not set
18# CONFIG_LEMOTE_FULONG is not set
19# CONFIG_MIPS_ATLAS is not set
20# CONFIG_MIPS_MALTA is not set
21# CONFIG_MIPS_SEAD is not set
22# CONFIG_MIPS_SIM is not set
23# CONFIG_MARKEINS is not set
24# CONFIG_MACH_VR41XX is not set
25# CONFIG_PNX8550_JBS is not set
26# CONFIG_PNX8550_STB810 is not set
27# CONFIG_PMC_MSP is not set
28# CONFIG_PMC_YOSEMITE is not set
29# CONFIG_SGI_IP22 is not set
30# CONFIG_SGI_IP27 is not set
31# CONFIG_SGI_IP28 is not set
32# CONFIG_SGI_IP32 is not set
33# CONFIG_SIBYTE_CRHINE is not set
34# CONFIG_SIBYTE_CARMEL is not set
35# CONFIG_SIBYTE_CRHONE is not set
36# CONFIG_SIBYTE_RHONE is not set
37# CONFIG_SIBYTE_SWARM is not set
38# CONFIG_SIBYTE_LITTLESUR is not set
39# CONFIG_SIBYTE_SENTOSA is not set
40# CONFIG_SIBYTE_BIGSUR is not set
41# CONFIG_SNI_RM is not set
42# CONFIG_TOSHIBA_JMR3927 is not set
43CONFIG_MIKROTIK_RB532=y
44# CONFIG_TOSHIBA_RBTX4927 is not set
45# CONFIG_TOSHIBA_RBTX4938 is not set
46# CONFIG_WR_PPMC is not set
47CONFIG_RWSEM_GENERIC_SPINLOCK=y
48# CONFIG_ARCH_HAS_ILOG2_U32 is not set
49# CONFIG_ARCH_HAS_ILOG2_U64 is not set
50CONFIG_ARCH_SUPPORTS_OPROFILE=y
51CONFIG_GENERIC_FIND_NEXT_BIT=y
52CONFIG_GENERIC_HWEIGHT=y
53CONFIG_GENERIC_CALIBRATE_DELAY=y
54CONFIG_GENERIC_CLOCKEVENTS=y
55CONFIG_GENERIC_TIME=y
56CONFIG_GENERIC_CMOS_UPDATE=y
57CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
58CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
59CONFIG_BOOT_RAW=y
60CONFIG_CEVT_R4K=y
61CONFIG_CSRC_R4K=y
62CONFIG_DMA_NONCOHERENT=y
63CONFIG_DMA_NEED_PCI_MAP_STATE=y
64# CONFIG_HOTPLUG_CPU is not set
65# CONFIG_NO_IOPORT is not set
66CONFIG_GENERIC_GPIO=y
67# CONFIG_CPU_BIG_ENDIAN is not set
68CONFIG_CPU_LITTLE_ENDIAN=y
69CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
70CONFIG_IRQ_CPU=y
71CONFIG_SWAP_IO_SPACE=y
72CONFIG_MIPS_L1_CACHE_SHIFT=4
73
74#
75# CPU selection
76#
77# CONFIG_CPU_LOONGSON2 is not set
78CONFIG_CPU_MIPS32_R1=y
79# CONFIG_CPU_MIPS32_R2 is not set
80# CONFIG_CPU_MIPS64_R1 is not set
81# CONFIG_CPU_MIPS64_R2 is not set
82# CONFIG_CPU_R3000 is not set
83# CONFIG_CPU_TX39XX is not set
84# CONFIG_CPU_VR41XX is not set
85# CONFIG_CPU_R4300 is not set
86# CONFIG_CPU_R4X00 is not set
87# CONFIG_CPU_TX49XX is not set
88# CONFIG_CPU_R5000 is not set
89# CONFIG_CPU_R5432 is not set
90# CONFIG_CPU_R6000 is not set
91# CONFIG_CPU_NEVADA is not set
92# CONFIG_CPU_R8000 is not set
93# CONFIG_CPU_R10000 is not set
94# CONFIG_CPU_RM7000 is not set
95# CONFIG_CPU_RM9000 is not set
96# CONFIG_CPU_SB1 is not set
97CONFIG_SYS_HAS_CPU_MIPS32_R1=y
98CONFIG_CPU_MIPS32=y
99CONFIG_CPU_MIPSR1=y
100CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
101CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
102
103#
104# Kernel type
105#
106CONFIG_32BIT=y
107# CONFIG_64BIT is not set
108CONFIG_PAGE_SIZE_4KB=y
109# CONFIG_PAGE_SIZE_8KB is not set
110# CONFIG_PAGE_SIZE_16KB is not set
111# CONFIG_PAGE_SIZE_64KB is not set
112CONFIG_CPU_HAS_PREFETCH=y
113CONFIG_MIPS_MT_DISABLED=y
114# CONFIG_MIPS_MT_SMP is not set
115# CONFIG_MIPS_MT_SMTC is not set
116CONFIG_CPU_HAS_LLSC=y
117CONFIG_CPU_HAS_SYNC=y
118CONFIG_GENERIC_HARDIRQS=y
119CONFIG_GENERIC_IRQ_PROBE=y
120CONFIG_CPU_SUPPORTS_HIGHMEM=y
121CONFIG_ARCH_FLATMEM_ENABLE=y
122CONFIG_ARCH_POPULATES_NODE_MAP=y
123CONFIG_SELECT_MEMORY_MODEL=y
124CONFIG_FLATMEM_MANUAL=y
125# CONFIG_DISCONTIGMEM_MANUAL is not set
126# CONFIG_SPARSEMEM_MANUAL is not set
127CONFIG_FLATMEM=y
128CONFIG_FLAT_NODE_MEM_MAP=y
129# CONFIG_SPARSEMEM_STATIC is not set
130# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
131CONFIG_SPLIT_PTLOCK_CPUS=4
132# CONFIG_RESOURCES_64BIT is not set
133CONFIG_ZONE_DMA_FLAG=0
134CONFIG_VIRT_TO_BUS=y
135CONFIG_TICK_ONESHOT=y
136CONFIG_NO_HZ=y
137CONFIG_HIGH_RES_TIMERS=y
138CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
139# CONFIG_HZ_48 is not set
140CONFIG_HZ_100=y
141# CONFIG_HZ_128 is not set
142# CONFIG_HZ_250 is not set
143# CONFIG_HZ_256 is not set
144# CONFIG_HZ_1000 is not set
145# CONFIG_HZ_1024 is not set
146CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
147CONFIG_HZ=100
148CONFIG_PREEMPT_NONE=y
149# CONFIG_PREEMPT_VOLUNTARY is not set
150# CONFIG_PREEMPT is not set
151# CONFIG_KEXEC is not set
152# CONFIG_SECCOMP is not set
153CONFIG_LOCKDEP_SUPPORT=y
154CONFIG_STACKTRACE_SUPPORT=y
155CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
156
157#
158# General setup
159#
160CONFIG_EXPERIMENTAL=y
161CONFIG_BROKEN_ON_SMP=y
162CONFIG_INIT_ENV_ARG_LIMIT=32
163CONFIG_LOCALVERSION=""
164# CONFIG_LOCALVERSION_AUTO is not set
165CONFIG_SWAP=y
166CONFIG_SYSVIPC=y
167CONFIG_SYSVIPC_SYSCTL=y
168# CONFIG_POSIX_MQUEUE is not set
169CONFIG_BSD_PROCESS_ACCT=y
170# CONFIG_BSD_PROCESS_ACCT_V3 is not set
171# CONFIG_TASKSTATS is not set
172# CONFIG_AUDIT is not set
173CONFIG_IKCONFIG=y
174CONFIG_IKCONFIG_PROC=y
175CONFIG_LOG_BUF_SHIFT=14
176# CONFIG_CGROUPS is not set
177CONFIG_GROUP_SCHED=y
178CONFIG_FAIR_GROUP_SCHED=y
179# CONFIG_RT_GROUP_SCHED is not set
180CONFIG_USER_SCHED=y
181# CONFIG_CGROUP_SCHED is not set
182CONFIG_SYSFS_DEPRECATED=y
183CONFIG_SYSFS_DEPRECATED_V2=y
184# CONFIG_RELAY is not set
185# CONFIG_NAMESPACES is not set
186CONFIG_BLK_DEV_INITRD=y
187CONFIG_INITRAMFS_SOURCE=""
188CONFIG_CC_OPTIMIZE_FOR_SIZE=y
189CONFIG_SYSCTL=y
190CONFIG_EMBEDDED=y
191CONFIG_SYSCTL_SYSCALL=y
192# CONFIG_KALLSYMS is not set
193CONFIG_HOTPLUG=y
194CONFIG_PRINTK=y
195CONFIG_BUG=y
196# CONFIG_ELF_CORE is not set
197CONFIG_COMPAT_BRK=y
198CONFIG_BASE_FULL=y
199CONFIG_FUTEX=y
200CONFIG_ANON_INODES=y
201CONFIG_EPOLL=y
202CONFIG_SIGNALFD=y
203CONFIG_TIMERFD=y
204CONFIG_EVENTFD=y
205CONFIG_SHMEM=y
206# CONFIG_VM_EVENT_COUNTERS is not set
207CONFIG_SLAB=y
208# CONFIG_SLUB is not set
209# CONFIG_SLOB is not set
210# CONFIG_PROFILING is not set
211# CONFIG_MARKERS is not set
212CONFIG_HAVE_OPROFILE=y
213# CONFIG_HAVE_KPROBES is not set
214# CONFIG_HAVE_KRETPROBES is not set
215CONFIG_PROC_PAGE_MONITOR=y
216CONFIG_SLABINFO=y
217CONFIG_RT_MUTEXES=y
218# CONFIG_TINY_SHMEM is not set
219CONFIG_BASE_SMALL=0
220CONFIG_MODULES=y
221CONFIG_MODULE_UNLOAD=y
222# CONFIG_MODULE_FORCE_UNLOAD is not set
223# CONFIG_MODVERSIONS is not set
224# CONFIG_MODULE_SRCVERSION_ALL is not set
225# CONFIG_KMOD is not set
226CONFIG_BLOCK=y
227# CONFIG_LBD is not set
228# CONFIG_BLK_DEV_IO_TRACE is not set
229# CONFIG_LSF is not set
230# CONFIG_BLK_DEV_BSG is not set
231
232#
233# IO Schedulers
234#
235CONFIG_IOSCHED_NOOP=y
236# CONFIG_IOSCHED_AS is not set
237CONFIG_IOSCHED_DEADLINE=y
238# CONFIG_IOSCHED_CFQ is not set
239# CONFIG_DEFAULT_AS is not set
240CONFIG_DEFAULT_DEADLINE=y
241# CONFIG_DEFAULT_CFQ is not set
242# CONFIG_DEFAULT_NOOP is not set
243CONFIG_DEFAULT_IOSCHED="deadline"
244CONFIG_CLASSIC_RCU=y
245
246#
247# Bus options (PCI, PCMCIA, EISA, ISA, TC)
248#
249CONFIG_HW_HAS_PCI=y
250CONFIG_PCI=y
251CONFIG_PCI_DOMAINS=y
252# CONFIG_ARCH_SUPPORTS_MSI is not set
253CONFIG_PCI_LEGACY=y
254CONFIG_MMU=y
255# CONFIG_PCCARD is not set
256# CONFIG_HOTPLUG_PCI is not set
257
258#
259# Executable file formats
260#
261CONFIG_BINFMT_ELF=y
262# CONFIG_BINFMT_MISC is not set
263CONFIG_TRAD_SIGNALS=y
264
265#
266# Power management options
267#
268CONFIG_ARCH_SUSPEND_POSSIBLE=y
269# CONFIG_PM is not set
270
271#
272# Networking
273#
274CONFIG_NET=y
275
276#
277# Networking options
278#
279CONFIG_PACKET=y
280CONFIG_PACKET_MMAP=y
281CONFIG_UNIX=y
282# CONFIG_NET_KEY is not set
283CONFIG_INET=y
284CONFIG_IP_MULTICAST=y
285CONFIG_IP_ADVANCED_ROUTER=y
286CONFIG_ASK_IP_FIB_HASH=y
287# CONFIG_IP_FIB_TRIE is not set
288CONFIG_IP_FIB_HASH=y
289CONFIG_IP_MULTIPLE_TABLES=y
290CONFIG_IP_ROUTE_MULTIPATH=y
291CONFIG_IP_ROUTE_VERBOSE=y
292# CONFIG_IP_PNP is not set
293# CONFIG_NET_IPIP is not set
294# CONFIG_NET_IPGRE is not set
295# CONFIG_IP_MROUTE is not set
296CONFIG_ARPD=y
297CONFIG_SYN_COOKIES=y
298# CONFIG_INET_AH is not set
299# CONFIG_INET_ESP is not set
300# CONFIG_INET_IPCOMP is not set
301# CONFIG_INET_XFRM_TUNNEL is not set
302# CONFIG_INET_TUNNEL is not set
303# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
304# CONFIG_INET_XFRM_MODE_TUNNEL is not set
305# CONFIG_INET_XFRM_MODE_BEET is not set
306# CONFIG_INET_LRO is not set
307CONFIG_INET_DIAG=m
308CONFIG_INET_TCP_DIAG=m
309CONFIG_TCP_CONG_ADVANCED=y
310CONFIG_TCP_CONG_BIC=m
311CONFIG_TCP_CONG_CUBIC=m
312CONFIG_TCP_CONG_WESTWOOD=m
313CONFIG_TCP_CONG_HTCP=m
314CONFIG_TCP_CONG_HSTCP=m
315CONFIG_TCP_CONG_HYBLA=m
316CONFIG_TCP_CONG_VEGAS=y
317CONFIG_TCP_CONG_SCALABLE=m
318CONFIG_TCP_CONG_LP=m
319CONFIG_TCP_CONG_VENO=m
320CONFIG_TCP_CONG_YEAH=m
321CONFIG_TCP_CONG_ILLINOIS=m
322# CONFIG_DEFAULT_BIC is not set
323# CONFIG_DEFAULT_CUBIC is not set
324# CONFIG_DEFAULT_HTCP is not set
325CONFIG_DEFAULT_VEGAS=y
326# CONFIG_DEFAULT_WESTWOOD is not set
327# CONFIG_DEFAULT_RENO is not set
328CONFIG_DEFAULT_TCP_CONG="vegas"
329# CONFIG_TCP_MD5SIG is not set
330# CONFIG_IP_VS is not set
331# CONFIG_IPV6 is not set
332# CONFIG_NETWORK_SECMARK is not set
333CONFIG_NETFILTER=y
334# CONFIG_NETFILTER_DEBUG is not set
335CONFIG_NETFILTER_ADVANCED=y
336# CONFIG_BRIDGE_NETFILTER is not set
337
338#
339# Core Netfilter Configuration
340#
341# CONFIG_NETFILTER_NETLINK_QUEUE is not set
342# CONFIG_NETFILTER_NETLINK_LOG is not set
343CONFIG_NF_CONNTRACK=y
344CONFIG_NF_CT_ACCT=y
345CONFIG_NF_CONNTRACK_MARK=y
346# CONFIG_NF_CONNTRACK_EVENTS is not set
347# CONFIG_NF_CT_PROTO_DCCP is not set
348# CONFIG_NF_CT_PROTO_SCTP is not set
349# CONFIG_NF_CT_PROTO_UDPLITE is not set
350# CONFIG_NF_CONNTRACK_AMANDA is not set
351CONFIG_NF_CONNTRACK_FTP=m
352# CONFIG_NF_CONNTRACK_H323 is not set
353CONFIG_NF_CONNTRACK_IRC=m
354# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set
355# CONFIG_NF_CONNTRACK_PPTP is not set
356# CONFIG_NF_CONNTRACK_SANE is not set
357# CONFIG_NF_CONNTRACK_SIP is not set
358CONFIG_NF_CONNTRACK_TFTP=m
359# CONFIG_NF_CT_NETLINK is not set
360CONFIG_NETFILTER_XTABLES=y
361# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set
362# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set
363# CONFIG_NETFILTER_XT_TARGET_DSCP is not set
364# CONFIG_NETFILTER_XT_TARGET_MARK is not set
365CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
366CONFIG_NETFILTER_XT_TARGET_NFLOG=m
367# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set
368# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
369CONFIG_NETFILTER_XT_TARGET_TRACE=m
370# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
371# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set
372CONFIG_NETFILTER_XT_MATCH_COMMENT=m
373# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set
374CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
375# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set
376# CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set
377CONFIG_NETFILTER_XT_MATCH_DCCP=m
378# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
379# CONFIG_NETFILTER_XT_MATCH_ESP is not set
380# CONFIG_NETFILTER_XT_MATCH_HELPER is not set
381# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
382# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set
383CONFIG_NETFILTER_XT_MATCH_LIMIT=y
384# CONFIG_NETFILTER_XT_MATCH_MAC is not set
385# CONFIG_NETFILTER_XT_MATCH_MARK is not set
386# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
387CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
388# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set
389# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set
390# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
391CONFIG_NETFILTER_XT_MATCH_REALM=m
392CONFIG_NETFILTER_XT_MATCH_SCTP=m
393CONFIG_NETFILTER_XT_MATCH_STATE=y
394# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
395# CONFIG_NETFILTER_XT_MATCH_STRING is not set
396# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set
397# CONFIG_NETFILTER_XT_MATCH_TIME is not set
398CONFIG_NETFILTER_XT_MATCH_U32=m
399CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
400
401#
402# IP: Netfilter Configuration
403#
404CONFIG_NF_CONNTRACK_IPV4=y
405CONFIG_NF_CONNTRACK_PROC_COMPAT=y
406# CONFIG_IP_NF_QUEUE is not set
407CONFIG_IP_NF_IPTABLES=y
408# CONFIG_IP_NF_MATCH_RECENT is not set
409# CONFIG_IP_NF_MATCH_ECN is not set
410# CONFIG_IP_NF_MATCH_AH is not set
411# CONFIG_IP_NF_MATCH_TTL is not set
412CONFIG_IP_NF_MATCH_ADDRTYPE=m
413CONFIG_IP_NF_FILTER=y
414CONFIG_IP_NF_TARGET_REJECT=y
415# CONFIG_IP_NF_TARGET_LOG is not set
416# CONFIG_IP_NF_TARGET_ULOG is not set
417CONFIG_NF_NAT=y
418CONFIG_NF_NAT_NEEDED=y
419CONFIG_IP_NF_TARGET_MASQUERADE=y
420# CONFIG_IP_NF_TARGET_REDIRECT is not set
421# CONFIG_IP_NF_TARGET_NETMAP is not set
422# CONFIG_NF_NAT_SNMP_BASIC is not set
423CONFIG_NF_NAT_FTP=m
424CONFIG_NF_NAT_IRC=m
425CONFIG_NF_NAT_TFTP=m
426# CONFIG_NF_NAT_AMANDA is not set
427# CONFIG_NF_NAT_PPTP is not set
428# CONFIG_NF_NAT_H323 is not set
429# CONFIG_NF_NAT_SIP is not set
430CONFIG_IP_NF_MANGLE=y
431# CONFIG_IP_NF_TARGET_ECN is not set
432# CONFIG_IP_NF_TARGET_TTL is not set
433# CONFIG_IP_NF_TARGET_CLUSTERIP is not set
434CONFIG_IP_NF_RAW=m
435# CONFIG_IP_NF_ARPTABLES is not set
436# CONFIG_IP_DCCP is not set
437# CONFIG_IP_SCTP is not set
438# CONFIG_TIPC is not set
439# CONFIG_ATM is not set
440CONFIG_BRIDGE=y
441CONFIG_VLAN_8021Q=y
442# CONFIG_DECNET is not set
443CONFIG_LLC=y
444CONFIG_LLC2=m
445# CONFIG_IPX is not set
446# CONFIG_ATALK is not set
447# CONFIG_X25 is not set
448# CONFIG_LAPB is not set
449# CONFIG_ECONET is not set
450# CONFIG_WAN_ROUTER is not set
451CONFIG_NET_SCHED=y
452
453#
454# Queueing/Scheduling
455#
456CONFIG_NET_SCH_CBQ=m
457# CONFIG_NET_SCH_HTB is not set
458# CONFIG_NET_SCH_HFSC is not set
459CONFIG_NET_SCH_PRIO=m
460CONFIG_NET_SCH_RR=m
461# CONFIG_NET_SCH_RED is not set
462# CONFIG_NET_SCH_SFQ is not set
463# CONFIG_NET_SCH_TEQL is not set
464# CONFIG_NET_SCH_TBF is not set
465# CONFIG_NET_SCH_GRED is not set
466# CONFIG_NET_SCH_DSMARK is not set
467CONFIG_NET_SCH_NETEM=m
468# CONFIG_NET_SCH_INGRESS is not set
469
470#
471# Classification
472#
473CONFIG_NET_CLS=y
474CONFIG_NET_CLS_BASIC=m
475CONFIG_NET_CLS_TCINDEX=m
476CONFIG_NET_CLS_ROUTE4=m
477CONFIG_NET_CLS_ROUTE=y
478CONFIG_NET_CLS_FW=m
479CONFIG_NET_CLS_U32=m
480CONFIG_CLS_U32_PERF=y
481CONFIG_CLS_U32_MARK=y
482CONFIG_NET_CLS_RSVP=m
483CONFIG_NET_CLS_RSVP6=m
484# CONFIG_NET_CLS_FLOW is not set
485CONFIG_NET_EMATCH=y
486CONFIG_NET_EMATCH_STACK=32
487CONFIG_NET_EMATCH_CMP=m
488CONFIG_NET_EMATCH_NBYTE=m
489CONFIG_NET_EMATCH_U32=m
490CONFIG_NET_EMATCH_META=m
491CONFIG_NET_EMATCH_TEXT=m
492CONFIG_NET_CLS_ACT=y
493CONFIG_NET_ACT_POLICE=y
494CONFIG_NET_ACT_GACT=m
495CONFIG_GACT_PROB=y
496CONFIG_NET_ACT_MIRRED=m
497CONFIG_NET_ACT_IPT=m
498# CONFIG_NET_ACT_NAT is not set
499CONFIG_NET_ACT_PEDIT=m
500# CONFIG_NET_ACT_SIMP is not set
501CONFIG_NET_CLS_IND=y
502CONFIG_NET_SCH_FIFO=y
503
504#
505# Network testing
506#
507# CONFIG_NET_PKTGEN is not set
508CONFIG_HAMRADIO=y
509
510#
511# Packet Radio protocols
512#
513# CONFIG_AX25 is not set
514# CONFIG_CAN is not set
515# CONFIG_IRDA is not set
516# CONFIG_BT is not set
517# CONFIG_AF_RXRPC is not set
518CONFIG_FIB_RULES=y
519
520#
521# Wireless
522#
523# CONFIG_CFG80211 is not set
524CONFIG_WIRELESS_EXT=y
525# CONFIG_MAC80211 is not set
526# CONFIG_IEEE80211 is not set
527# CONFIG_RFKILL is not set
528# CONFIG_NET_9P is not set
529
530#
531# Device Drivers
532#
533
534#
535# Generic Driver Options
536#
537CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
538CONFIG_STANDALONE=y
539CONFIG_PREVENT_FIRMWARE_BUILD=y
540CONFIG_FW_LOADER=y
541# CONFIG_SYS_HYPERVISOR is not set
542# CONFIG_CONNECTOR is not set
543CONFIG_MTD=y
544# CONFIG_MTD_DEBUG is not set
545# CONFIG_MTD_CONCAT is not set
546CONFIG_MTD_PARTITIONS=y
547# CONFIG_MTD_REDBOOT_PARTS is not set
548# CONFIG_MTD_CMDLINE_PARTS is not set
549# CONFIG_MTD_AR7_PARTS is not set
550
551#
552# User Modules And Translation Layers
553#
554CONFIG_MTD_CHAR=y
555CONFIG_MTD_BLKDEVS=y
556CONFIG_MTD_BLOCK=y
557# CONFIG_FTL is not set
558# CONFIG_NFTL is not set
559# CONFIG_INFTL is not set
560# CONFIG_RFD_FTL is not set
561# CONFIG_SSFDC is not set
562# CONFIG_MTD_OOPS is not set
563
564#
565# RAM/ROM/Flash chip drivers
566#
567# CONFIG_MTD_CFI is not set
568# CONFIG_MTD_JEDECPROBE is not set
569CONFIG_MTD_MAP_BANK_WIDTH_1=y
570CONFIG_MTD_MAP_BANK_WIDTH_2=y
571CONFIG_MTD_MAP_BANK_WIDTH_4=y
572# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
573# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
574# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
575CONFIG_MTD_CFI_I1=y
576CONFIG_MTD_CFI_I2=y
577# CONFIG_MTD_CFI_I4 is not set
578# CONFIG_MTD_CFI_I8 is not set
579# CONFIG_MTD_RAM is not set
580# CONFIG_MTD_ROM is not set
581# CONFIG_MTD_ABSENT is not set
582
583#
584# Mapping drivers for chip access
585#
586# CONFIG_MTD_COMPLEX_MAPPINGS is not set
587# CONFIG_MTD_INTEL_VR_NOR is not set
588# CONFIG_MTD_PLATRAM is not set
589
590#
591# Self-contained MTD device drivers
592#
593# CONFIG_MTD_PMC551 is not set
594# CONFIG_MTD_SLRAM is not set
595# CONFIG_MTD_PHRAM is not set
596# CONFIG_MTD_MTDRAM is not set
597CONFIG_MTD_BLOCK2MTD=y
598
599#
600# Disk-On-Chip Device Drivers
601#
602# CONFIG_MTD_DOC2000 is not set
603# CONFIG_MTD_DOC2001 is not set
604# CONFIG_MTD_DOC2001PLUS is not set
605CONFIG_MTD_NAND=y
606CONFIG_MTD_NAND_VERIFY_WRITE=y
607# CONFIG_MTD_NAND_ECC_SMC is not set
608# CONFIG_MTD_NAND_MUSEUM_IDS is not set
609CONFIG_MTD_NAND_IDS=y
610# CONFIG_MTD_NAND_DISKONCHIP is not set
611# CONFIG_MTD_NAND_CAFE is not set
612# CONFIG_MTD_NAND_NANDSIM is not set
613CONFIG_MTD_NAND_PLATFORM=y
614# CONFIG_MTD_ONENAND is not set
615
616#
617# UBI - Unsorted block images
618#
619# CONFIG_MTD_UBI is not set
620# CONFIG_PARPORT is not set
621CONFIG_BLK_DEV=y
622# CONFIG_BLK_CPQ_DA is not set
623# CONFIG_BLK_CPQ_CISS_DA is not set
624# CONFIG_BLK_DEV_DAC960 is not set
625# CONFIG_BLK_DEV_UMEM is not set
626# CONFIG_BLK_DEV_COW_COMMON is not set
627# CONFIG_BLK_DEV_LOOP is not set
628# CONFIG_BLK_DEV_NBD is not set
629# CONFIG_BLK_DEV_SX8 is not set
630# CONFIG_BLK_DEV_RAM is not set
631# CONFIG_CDROM_PKTCDVD is not set
632# CONFIG_ATA_OVER_ETH is not set
633CONFIG_MISC_DEVICES=y
634# CONFIG_PHANTOM is not set
635# CONFIG_EEPROM_93CX6 is not set
636# CONFIG_SGI_IOC4 is not set
637# CONFIG_TIFM_CORE is not set
638# CONFIG_ENCLOSURE_SERVICES is not set
639CONFIG_HAVE_IDE=y
640# CONFIG_IDE is not set
641
642#
643# SCSI device support
644#
645# CONFIG_RAID_ATTRS is not set
646CONFIG_SCSI=y
647CONFIG_SCSI_DMA=y
648# CONFIG_SCSI_TGT is not set
649# CONFIG_SCSI_NETLINK is not set
650CONFIG_SCSI_PROC_FS=y
651
652#
653# SCSI support type (disk, tape, CD-ROM)
654#
655# CONFIG_BLK_DEV_SD is not set
656# CONFIG_CHR_DEV_ST is not set
657# CONFIG_CHR_DEV_OSST is not set
658# CONFIG_BLK_DEV_SR is not set
659# CONFIG_CHR_DEV_SG is not set
660# CONFIG_CHR_DEV_SCH is not set
661
662#
663# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
664#
665# CONFIG_SCSI_MULTI_LUN is not set
666# CONFIG_SCSI_CONSTANTS is not set
667# CONFIG_SCSI_LOGGING is not set
668# CONFIG_SCSI_SCAN_ASYNC is not set
669CONFIG_SCSI_WAIT_SCAN=m
670
671#
672# SCSI Transports
673#
674# CONFIG_SCSI_SPI_ATTRS is not set
675# CONFIG_SCSI_FC_ATTRS is not set
676# CONFIG_SCSI_ISCSI_ATTRS is not set
677# CONFIG_SCSI_SAS_LIBSAS is not set
678# CONFIG_SCSI_SRP_ATTRS is not set
679CONFIG_SCSI_LOWLEVEL=y
680# CONFIG_ISCSI_TCP is not set
681# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
682# CONFIG_SCSI_3W_9XXX is not set
683# CONFIG_SCSI_ACARD is not set
684# CONFIG_SCSI_AACRAID is not set
685# CONFIG_SCSI_AIC7XXX is not set
686# CONFIG_SCSI_AIC7XXX_OLD is not set
687# CONFIG_SCSI_AIC79XX is not set
688# CONFIG_SCSI_AIC94XX is not set
689# CONFIG_SCSI_DPT_I2O is not set
690# CONFIG_SCSI_ADVANSYS is not set
691# CONFIG_SCSI_ARCMSR is not set
692# CONFIG_MEGARAID_NEWGEN is not set
693# CONFIG_MEGARAID_LEGACY is not set
694# CONFIG_MEGARAID_SAS is not set
695# CONFIG_SCSI_HPTIOP is not set
696# CONFIG_SCSI_DMX3191D is not set
697# CONFIG_SCSI_FUTURE_DOMAIN is not set
698# CONFIG_SCSI_IPS is not set
699# CONFIG_SCSI_INITIO is not set
700# CONFIG_SCSI_INIA100 is not set
701# CONFIG_SCSI_MVSAS is not set
702# CONFIG_SCSI_STEX is not set
703# CONFIG_SCSI_SYM53C8XX_2 is not set
704# CONFIG_SCSI_IPR is not set
705# CONFIG_SCSI_QLOGIC_1280 is not set
706# CONFIG_SCSI_QLA_FC is not set
707# CONFIG_SCSI_QLA_ISCSI is not set
708# CONFIG_SCSI_LPFC is not set
709# CONFIG_SCSI_DC395x is not set
710# CONFIG_SCSI_DC390T is not set
711# CONFIG_SCSI_NSP32 is not set
712# CONFIG_SCSI_DEBUG is not set
713# CONFIG_SCSI_SRP is not set
714CONFIG_ATA=y
715# CONFIG_ATA_NONSTANDARD is not set
716# CONFIG_SATA_PMP is not set
717# CONFIG_SATA_AHCI is not set
718# CONFIG_SATA_SIL24 is not set
719CONFIG_ATA_SFF=y
720# CONFIG_SATA_SVW is not set
721# CONFIG_ATA_PIIX is not set
722# CONFIG_SATA_MV is not set
723# CONFIG_SATA_NV is not set
724# CONFIG_PDC_ADMA is not set
725# CONFIG_SATA_QSTOR is not set
726# CONFIG_SATA_PROMISE is not set
727# CONFIG_SATA_SX4 is not set
728# CONFIG_SATA_SIL is not set
729# CONFIG_SATA_SIS is not set
730# CONFIG_SATA_ULI is not set
731# CONFIG_SATA_VIA is not set
732# CONFIG_SATA_VITESSE is not set
733# CONFIG_SATA_INIC162X is not set
734# CONFIG_PATA_ALI is not set
735# CONFIG_PATA_AMD is not set
736# CONFIG_PATA_ARTOP is not set
737# CONFIG_PATA_ATIIXP is not set
738# CONFIG_PATA_CMD640_PCI is not set
739# CONFIG_PATA_CMD64X is not set
740# CONFIG_PATA_CS5520 is not set
741# CONFIG_PATA_CS5530 is not set
742# CONFIG_PATA_CYPRESS is not set
743# CONFIG_PATA_EFAR is not set
744# CONFIG_ATA_GENERIC is not set
745# CONFIG_PATA_HPT366 is not set
746# CONFIG_PATA_HPT37X is not set
747# CONFIG_PATA_HPT3X2N is not set
748# CONFIG_PATA_HPT3X3 is not set
749# CONFIG_PATA_IT821X is not set
750# CONFIG_PATA_IT8213 is not set
751# CONFIG_PATA_JMICRON is not set
752# CONFIG_PATA_TRIFLEX is not set
753# CONFIG_PATA_MARVELL is not set
754# CONFIG_PATA_MPIIX is not set
755# CONFIG_PATA_OLDPIIX is not set
756# CONFIG_PATA_NETCELL is not set
757# CONFIG_PATA_NINJA32 is not set
758# CONFIG_PATA_NS87410 is not set
759# CONFIG_PATA_NS87415 is not set
760# CONFIG_PATA_OPTI is not set
761# CONFIG_PATA_OPTIDMA is not set
762# CONFIG_PATA_PDC_OLD is not set
763# CONFIG_PATA_RADISYS is not set
764CONFIG_PATA_RB532=y
765# CONFIG_PATA_RZ1000 is not set
766# CONFIG_PATA_SC1200 is not set
767# CONFIG_PATA_SERVERWORKS is not set
768# CONFIG_PATA_PDC2027X is not set
769# CONFIG_PATA_SIL680 is not set
770# CONFIG_PATA_SIS is not set
771# CONFIG_PATA_VIA is not set
772# CONFIG_PATA_WINBOND is not set
773# CONFIG_PATA_PLATFORM is not set
774# CONFIG_MD is not set
775# CONFIG_FUSION is not set
776
777#
778# IEEE 1394 (FireWire) support
779#
780# CONFIG_FIREWIRE is not set
781# CONFIG_IEEE1394 is not set
782# CONFIG_I2O is not set
783CONFIG_NETDEVICES=y
784# CONFIG_NETDEVICES_MULTIQUEUE is not set
785CONFIG_IFB=m
786# CONFIG_DUMMY is not set
787# CONFIG_BONDING is not set
788# CONFIG_MACVLAN is not set
789# CONFIG_EQUALIZER is not set
790# CONFIG_TUN is not set
791# CONFIG_VETH is not set
792# CONFIG_ARCNET is not set
793# CONFIG_PHYLIB is not set
794CONFIG_NET_ETHERNET=y
795CONFIG_MII=y
796# CONFIG_AX88796 is not set
797CONFIG_KORINA=y
798# CONFIG_HAPPYMEAL is not set
799# CONFIG_SUNGEM is not set
800# CONFIG_CASSINI is not set
801# CONFIG_NET_VENDOR_3COM is not set
802# CONFIG_DM9000 is not set
803# CONFIG_NET_TULIP is not set
804# CONFIG_HP100 is not set
805# CONFIG_IBM_NEW_EMAC_ZMII is not set
806# CONFIG_IBM_NEW_EMAC_RGMII is not set
807# CONFIG_IBM_NEW_EMAC_TAH is not set
808# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
809CONFIG_NET_PCI=y
810# CONFIG_PCNET32 is not set
811# CONFIG_AMD8111_ETH is not set
812# CONFIG_ADAPTEC_STARFIRE is not set
813# CONFIG_B44 is not set
814# CONFIG_FORCEDETH is not set
815# CONFIG_TC35815 is not set
816# CONFIG_EEPRO100 is not set
817# CONFIG_E100 is not set
818# CONFIG_FEALNX is not set
819# CONFIG_NATSEMI is not set
820# CONFIG_NE2K_PCI is not set
821# CONFIG_8139CP is not set
822# CONFIG_8139TOO is not set
823# CONFIG_R6040 is not set
824# CONFIG_SIS900 is not set
825# CONFIG_EPIC100 is not set
826# CONFIG_SUNDANCE is not set
827# CONFIG_TLAN is not set
828CONFIG_VIA_RHINE=y
829# CONFIG_VIA_RHINE_MMIO is not set
830CONFIG_VIA_RHINE_NAPI=y
831# CONFIG_SC92031 is not set
832# CONFIG_NETDEV_1000 is not set
833# CONFIG_NETDEV_10000 is not set
834# CONFIG_TR is not set
835
836#
837# Wireless LAN
838#
839# CONFIG_WLAN_PRE80211 is not set
840CONFIG_WLAN_80211=y
841# CONFIG_IPW2100 is not set
842# CONFIG_IPW2200 is not set
843# CONFIG_LIBERTAS is not set
844# CONFIG_HERMES is not set
845CONFIG_ATMEL=m
846# CONFIG_PCI_ATMEL is not set
847# CONFIG_PRISM54 is not set
848# CONFIG_IWLWIFI_LEDS is not set
849# CONFIG_HOSTAP is not set
850# CONFIG_WAN is not set
851# CONFIG_FDDI is not set
852# CONFIG_HIPPI is not set
853CONFIG_PPP=m
854CONFIG_PPP_MULTILINK=y
855CONFIG_PPP_FILTER=y
856CONFIG_PPP_ASYNC=m
857# CONFIG_PPP_SYNC_TTY is not set
858CONFIG_PPP_DEFLATE=m
859CONFIG_PPP_BSDCOMP=m
860# CONFIG_PPP_MPPE is not set
861CONFIG_PPPOE=m
862CONFIG_PPPOL2TP=m
863# CONFIG_SLIP is not set
864CONFIG_SLHC=m
865# CONFIG_NET_FC is not set
866# CONFIG_NETCONSOLE is not set
867# CONFIG_NETPOLL is not set
868# CONFIG_NET_POLL_CONTROLLER is not set
869# CONFIG_ISDN is not set
870# CONFIG_PHONE is not set
871
872#
873# Input device support
874#
875CONFIG_INPUT=y
876# CONFIG_INPUT_FF_MEMLESS is not set
877# CONFIG_INPUT_POLLDEV is not set
878
879#
880# Userland interfaces
881#
882# CONFIG_INPUT_MOUSEDEV is not set
883# CONFIG_INPUT_JOYDEV is not set
884# CONFIG_INPUT_EVDEV is not set
885# CONFIG_INPUT_EVBUG is not set
886
887#
888# Input Device Drivers
889#
890CONFIG_INPUT_KEYBOARD=y
891# CONFIG_KEYBOARD_ATKBD is not set
892# CONFIG_KEYBOARD_SUNKBD is not set
893# CONFIG_KEYBOARD_LKKBD is not set
894# CONFIG_KEYBOARD_XTKBD is not set
895# CONFIG_KEYBOARD_NEWTON is not set
896# CONFIG_KEYBOARD_STOWAWAY is not set
897# CONFIG_KEYBOARD_GPIO is not set
898# CONFIG_INPUT_MOUSE is not set
899# CONFIG_INPUT_JOYSTICK is not set
900# CONFIG_INPUT_TABLET is not set
901# CONFIG_INPUT_TOUCHSCREEN is not set
902# CONFIG_INPUT_MISC is not set
903
904#
905# Hardware I/O ports
906#
907# CONFIG_SERIO is not set
908# CONFIG_GAMEPORT is not set
909
910#
911# Character devices
912#
913# CONFIG_VT is not set
914# CONFIG_SERIAL_NONSTANDARD is not set
915# CONFIG_NOZOMI is not set
916
917#
918# Serial drivers
919#
920CONFIG_SERIAL_8250=y
921CONFIG_SERIAL_8250_CONSOLE=y
922# CONFIG_SERIAL_8250_PCI is not set
923CONFIG_SERIAL_8250_NR_UARTS=2
924CONFIG_SERIAL_8250_RUNTIME_UARTS=2
925# CONFIG_SERIAL_8250_EXTENDED is not set
926
927#
928# Non-8250 serial port support
929#
930CONFIG_SERIAL_CORE=y
931CONFIG_SERIAL_CORE_CONSOLE=y
932# CONFIG_SERIAL_JSM is not set
933CONFIG_UNIX98_PTYS=y
934# CONFIG_LEGACY_PTYS is not set
935# CONFIG_IPMI_HANDLER is not set
936CONFIG_HW_RANDOM=y
937# CONFIG_RTC is not set
938# CONFIG_R3964 is not set
939# CONFIG_APPLICOM is not set
940# CONFIG_RAW_DRIVER is not set
941# CONFIG_TCG_TPM is not set
942CONFIG_DEVPORT=y
943# CONFIG_I2C is not set
944
945#
946# SPI support
947#
948# CONFIG_SPI is not set
949# CONFIG_SPI_MASTER is not set
950# CONFIG_W1 is not set
951# CONFIG_POWER_SUPPLY is not set
952# CONFIG_HWMON is not set
953# CONFIG_THERMAL is not set
954CONFIG_WATCHDOG=y
955# CONFIG_WATCHDOG_NOWAYOUT is not set
956
957#
958# Watchdog Device Drivers
959#
960# CONFIG_SOFT_WATCHDOG is not set
961
962#
963# PCI-based Watchdog Cards
964#
965# CONFIG_PCIPCWATCHDOG is not set
966# CONFIG_WDTPCI is not set
967
968#
969# Sonics Silicon Backplane
970#
971CONFIG_SSB_POSSIBLE=y
972# CONFIG_SSB is not set
973
974#
975# Multifunction device drivers
976#
977# CONFIG_MFD_SM501 is not set
978# CONFIG_HTC_PASIC3 is not set
979
980#
981# Multimedia devices
982#
983CONFIG_VIDEO_DEV=m
984CONFIG_VIDEO_V4L2_COMMON=m
985CONFIG_VIDEO_ALLOW_V4L1=y
986CONFIG_VIDEO_V4L1_COMPAT=y
987CONFIG_VIDEO_V4L2=m
988CONFIG_VIDEO_V4L1=m
989CONFIG_VIDEO_CAPTURE_DRIVERS=y
990# CONFIG_VIDEO_ADV_DEBUG is not set
991# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
992
993#
994# Encoders/decoders and other helper chips
995#
996
997#
998# Audio decoders
999#
1000
1001#
1002# Video decoders
1003#
1004
1005#
1006# Video and audio decoders
1007#
1008
1009#
1010# MPEG video encoders
1011#
1012# CONFIG_VIDEO_CX2341X is not set
1013
1014#
1015# Video encoders
1016#
1017
1018#
1019# Video improvement chips
1020#
1021# CONFIG_VIDEO_VIVI is not set
1022# CONFIG_VIDEO_CPIA is not set
1023# CONFIG_VIDEO_STRADIS is not set
1024# CONFIG_SOC_CAMERA is not set
1025# CONFIG_RADIO_ADAPTERS is not set
1026# CONFIG_DVB_CORE is not set
1027# CONFIG_DAB is not set
1028
1029#
1030# Graphics support
1031#
1032# CONFIG_DRM is not set
1033# CONFIG_VGASTATE is not set
1034# CONFIG_VIDEO_OUTPUT_CONTROL is not set
1035# CONFIG_FB is not set
1036# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
1037
1038#
1039# Display device support
1040#
1041# CONFIG_DISPLAY_SUPPORT is not set
1042
1043#
1044# Sound
1045#
1046# CONFIG_SOUND is not set
1047CONFIG_HID_SUPPORT=y
1048# CONFIG_HID is not set
1049CONFIG_USB_SUPPORT=y
1050CONFIG_USB_ARCH_HAS_HCD=y
1051CONFIG_USB_ARCH_HAS_OHCI=y
1052CONFIG_USB_ARCH_HAS_EHCI=y
1053# CONFIG_USB is not set
1054# CONFIG_USB_OTG_WHITELIST is not set
1055# CONFIG_USB_OTG_BLACKLIST_HUB is not set
1056
1057#
1058# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
1059#
1060# CONFIG_USB_GADGET is not set
1061# CONFIG_MMC is not set
1062# CONFIG_MEMSTICK is not set
1063CONFIG_NEW_LEDS=y
1064CONFIG_LEDS_CLASS=y
1065
1066#
1067# LED drivers
1068#
1069# CONFIG_LEDS_GPIO is not set
1070
1071#
1072# LED Triggers
1073#
1074CONFIG_LEDS_TRIGGERS=y
1075CONFIG_LEDS_TRIGGER_TIMER=y
1076CONFIG_LEDS_TRIGGER_HEARTBEAT=y
1077# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
1078# CONFIG_INFINIBAND is not set
1079CONFIG_RTC_LIB=y
1080# CONFIG_RTC_CLASS is not set
1081# CONFIG_UIO is not set
1082
1083#
1084# File systems
1085#
1086CONFIG_EXT2_FS=y
1087# CONFIG_EXT2_FS_XATTR is not set
1088# CONFIG_EXT2_FS_XIP is not set
1089# CONFIG_EXT3_FS is not set
1090# CONFIG_EXT4DEV_FS is not set
1091# CONFIG_REISERFS_FS is not set
1092# CONFIG_JFS_FS is not set
1093# CONFIG_FS_POSIX_ACL is not set
1094# CONFIG_XFS_FS is not set
1095# CONFIG_OCFS2_FS is not set
1096# CONFIG_DNOTIFY is not set
1097# CONFIG_INOTIFY is not set
1098# CONFIG_QUOTA is not set
1099# CONFIG_AUTOFS_FS is not set
1100# CONFIG_AUTOFS4_FS is not set
1101# CONFIG_FUSE_FS is not set
1102
1103#
1104# CD-ROM/DVD Filesystems
1105#
1106# CONFIG_ISO9660_FS is not set
1107# CONFIG_UDF_FS is not set
1108
1109#
1110# DOS/FAT/NT Filesystems
1111#
1112# CONFIG_MSDOS_FS is not set
1113# CONFIG_VFAT_FS is not set
1114# CONFIG_NTFS_FS is not set
1115
1116#
1117# Pseudo filesystems
1118#
1119CONFIG_PROC_FS=y
1120CONFIG_PROC_KCORE=y
1121CONFIG_PROC_SYSCTL=y
1122CONFIG_SYSFS=y
1123CONFIG_TMPFS=y
1124# CONFIG_TMPFS_POSIX_ACL is not set
1125# CONFIG_HUGETLB_PAGE is not set
1126CONFIG_CONFIGFS_FS=y
1127
1128#
1129# Miscellaneous filesystems
1130#
1131# CONFIG_ADFS_FS is not set
1132# CONFIG_AFFS_FS is not set
1133# CONFIG_HFS_FS is not set
1134# CONFIG_HFSPLUS_FS is not set
1135# CONFIG_BEFS_FS is not set
1136# CONFIG_BFS_FS is not set
1137# CONFIG_EFS_FS is not set
1138CONFIG_JFFS2_FS=y
1139CONFIG_JFFS2_FS_DEBUG=0
1140CONFIG_JFFS2_FS_WRITEBUFFER=y
1141# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
1142CONFIG_JFFS2_SUMMARY=y
1143# CONFIG_JFFS2_FS_XATTR is not set
1144CONFIG_JFFS2_COMPRESSION_OPTIONS=y
1145CONFIG_JFFS2_ZLIB=y
1146# CONFIG_JFFS2_LZO is not set
1147CONFIG_JFFS2_RTIME=y
1148# CONFIG_JFFS2_RUBIN is not set
1149# CONFIG_JFFS2_CMODE_NONE is not set
1150CONFIG_JFFS2_CMODE_PRIORITY=y
1151# CONFIG_JFFS2_CMODE_SIZE is not set
1152# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
1153# CONFIG_CRAMFS is not set
1154# CONFIG_VXFS_FS is not set
1155# CONFIG_MINIX_FS is not set
1156# CONFIG_HPFS_FS is not set
1157# CONFIG_QNX4FS_FS is not set
1158# CONFIG_ROMFS_FS is not set
1159# CONFIG_SYSV_FS is not set
1160# CONFIG_UFS_FS is not set
1161CONFIG_NETWORK_FILESYSTEMS=y
1162# CONFIG_NFS_FS is not set
1163# CONFIG_NFSD is not set
1164# CONFIG_SMB_FS is not set
1165# CONFIG_CIFS is not set
1166# CONFIG_NCP_FS is not set
1167# CONFIG_CODA_FS is not set
1168# CONFIG_AFS_FS is not set
1169
1170#
1171# Partition Types
1172#
1173CONFIG_PARTITION_ADVANCED=y
1174# CONFIG_ACORN_PARTITION is not set
1175# CONFIG_OSF_PARTITION is not set
1176# CONFIG_AMIGA_PARTITION is not set
1177# CONFIG_ATARI_PARTITION is not set
1178CONFIG_MAC_PARTITION=y
1179CONFIG_MSDOS_PARTITION=y
1180CONFIG_BSD_DISKLABEL=y
1181# CONFIG_MINIX_SUBPARTITION is not set
1182# CONFIG_SOLARIS_X86_PARTITION is not set
1183# CONFIG_UNIXWARE_DISKLABEL is not set
1184# CONFIG_LDM_PARTITION is not set
1185# CONFIG_SGI_PARTITION is not set
1186# CONFIG_ULTRIX_PARTITION is not set
1187# CONFIG_SUN_PARTITION is not set
1188# CONFIG_KARMA_PARTITION is not set
1189# CONFIG_EFI_PARTITION is not set
1190# CONFIG_SYSV68_PARTITION is not set
1191# CONFIG_NLS is not set
1192# CONFIG_DLM is not set
1193
1194#
1195# Kernel hacking
1196#
1197CONFIG_TRACE_IRQFLAGS_SUPPORT=y
1198# CONFIG_PRINTK_TIME is not set
1199CONFIG_ENABLE_WARN_DEPRECATED=y
1200# CONFIG_ENABLE_MUST_CHECK is not set
1201CONFIG_FRAME_WARN=1024
1202# CONFIG_MAGIC_SYSRQ is not set
1203# CONFIG_UNUSED_SYMBOLS is not set
1204# CONFIG_DEBUG_FS is not set
1205# CONFIG_HEADERS_CHECK is not set
1206# CONFIG_DEBUG_KERNEL is not set
1207# CONFIG_SAMPLES is not set
1208CONFIG_CMDLINE=""
1209
1210#
1211# Security options
1212#
1213# CONFIG_KEYS is not set
1214# CONFIG_SECURITY is not set
1215# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1216CONFIG_CRYPTO=y
1217
1218#
1219# Crypto core or helper
1220#
1221CONFIG_CRYPTO_ALGAPI=m
1222CONFIG_CRYPTO_AEAD=m
1223CONFIG_CRYPTO_BLKCIPHER=m
1224# CONFIG_CRYPTO_MANAGER is not set
1225# CONFIG_CRYPTO_GF128MUL is not set
1226# CONFIG_CRYPTO_NULL is not set
1227# CONFIG_CRYPTO_CRYPTD is not set
1228# CONFIG_CRYPTO_AUTHENC is not set
1229CONFIG_CRYPTO_TEST=m
1230
1231#
1232# Authenticated Encryption with Associated Data
1233#
1234# CONFIG_CRYPTO_CCM is not set
1235# CONFIG_CRYPTO_GCM is not set
1236# CONFIG_CRYPTO_SEQIV is not set
1237
1238#
1239# Block modes
1240#
1241# CONFIG_CRYPTO_CBC is not set
1242# CONFIG_CRYPTO_CTR is not set
1243# CONFIG_CRYPTO_CTS is not set
1244# CONFIG_CRYPTO_ECB is not set
1245# CONFIG_CRYPTO_LRW is not set
1246# CONFIG_CRYPTO_PCBC is not set
1247# CONFIG_CRYPTO_XTS is not set
1248
1249#
1250# Hash modes
1251#
1252# CONFIG_CRYPTO_HMAC is not set
1253# CONFIG_CRYPTO_XCBC is not set
1254
1255#
1256# Digest
1257#
1258# CONFIG_CRYPTO_CRC32C is not set
1259# CONFIG_CRYPTO_MD4 is not set
1260# CONFIG_CRYPTO_MD5 is not set
1261# CONFIG_CRYPTO_MICHAEL_MIC is not set
1262# CONFIG_CRYPTO_SHA1 is not set
1263# CONFIG_CRYPTO_SHA256 is not set
1264# CONFIG_CRYPTO_SHA512 is not set
1265# CONFIG_CRYPTO_TGR192 is not set
1266# CONFIG_CRYPTO_WP512 is not set
1267
1268#
1269# Ciphers
1270#
1271# CONFIG_CRYPTO_AES is not set
1272# CONFIG_CRYPTO_ANUBIS is not set
1273# CONFIG_CRYPTO_ARC4 is not set
1274# CONFIG_CRYPTO_BLOWFISH is not set
1275# CONFIG_CRYPTO_CAMELLIA is not set
1276# CONFIG_CRYPTO_CAST5 is not set
1277# CONFIG_CRYPTO_CAST6 is not set
1278# CONFIG_CRYPTO_DES is not set
1279# CONFIG_CRYPTO_FCRYPT is not set
1280# CONFIG_CRYPTO_KHAZAD is not set
1281# CONFIG_CRYPTO_SALSA20 is not set
1282# CONFIG_CRYPTO_SEED is not set
1283# CONFIG_CRYPTO_SERPENT is not set
1284# CONFIG_CRYPTO_TEA is not set
1285# CONFIG_CRYPTO_TWOFISH is not set
1286
1287#
1288# Compression
1289#
1290# CONFIG_CRYPTO_DEFLATE is not set
1291# CONFIG_CRYPTO_LZO is not set
1292# CONFIG_CRYPTO_HW is not set
1293
1294#
1295# Library routines
1296#
1297CONFIG_BITREVERSE=y
1298# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1299CONFIG_CRC_CCITT=m
1300CONFIG_CRC16=m
1301# CONFIG_CRC_ITU_T is not set
1302CONFIG_CRC32=y
1303# CONFIG_CRC7 is not set
1304CONFIG_LIBCRC32C=m
1305CONFIG_ZLIB_INFLATE=y
1306CONFIG_ZLIB_DEFLATE=y
1307CONFIG_TEXTSEARCH=y
1308CONFIG_TEXTSEARCH_KMP=m
1309CONFIG_TEXTSEARCH_BM=m
1310CONFIG_TEXTSEARCH_FSM=m
1311CONFIG_PLIST=y
1312CONFIG_HAS_IOMEM=y
1313CONFIG_HAS_IOPORT=y
1314CONFIG_HAS_DMA=y
diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c
index 65af3cc90abb..c266211ed653 100644
--- a/arch/mips/kernel/linux32.c
+++ b/arch/mips/kernel/linux32.c
@@ -129,23 +129,6 @@ out:
129 return error; 129 return error;
130} 130}
131 131
132
133asmlinkage int sys_truncate64(const char __user *path, unsigned int high,
134 unsigned int low)
135{
136 if ((int)high < 0)
137 return -EINVAL;
138 return sys_truncate(path, ((long) high << 32) | low);
139}
140
141asmlinkage int sys_ftruncate64(unsigned int fd, unsigned int high,
142 unsigned int low)
143{
144 if ((int)high < 0)
145 return -EINVAL;
146 return sys_ftruncate(fd, ((long) high << 32) | low);
147}
148
149/* 132/*
150 * sys_execve() executes a new program. 133 * sys_execve() executes a new program.
151 */ 134 */
diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S
index c058c0b61a2a..fc4fd4d705e2 100644
--- a/arch/mips/kernel/scall32-o32.S
+++ b/arch/mips/kernel/scall32-o32.S
@@ -354,7 +354,7 @@ einval: li v0, -EINVAL
354 sys sys_mkdir 2 354 sys sys_mkdir 2
355 sys sys_rmdir 1 /* 4040 */ 355 sys sys_rmdir 1 /* 4040 */
356 sys sys_dup 1 356 sys sys_dup 1
357 sys sys_pipe 0 357 sys sysm_pipe 0
358 sys sys_times 1 358 sys sys_times 1
359 sys sys_ni_syscall 0 359 sys sys_ni_syscall 0
360 sys sys_brk 1 /* 4045 */ 360 sys sys_brk 1 /* 4045 */
diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S
index dc597b600c68..2b73fd1e4528 100644
--- a/arch/mips/kernel/scall64-64.S
+++ b/arch/mips/kernel/scall64-64.S
@@ -219,7 +219,7 @@ sys_call_table:
219 PTR sys_readv 219 PTR sys_readv
220 PTR sys_writev 220 PTR sys_writev
221 PTR sys_access /* 5020 */ 221 PTR sys_access /* 5020 */
222 PTR sys_pipe 222 PTR sysm_pipe
223 PTR sys_select 223 PTR sys_select
224 PTR sys_sched_yield 224 PTR sys_sched_yield
225 PTR sys_mremap 225 PTR sys_mremap
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index 12940eca7893..2654e75d2fef 100644
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -141,7 +141,7 @@ EXPORT(sysn32_call_table)
141 PTR compat_sys_readv 141 PTR compat_sys_readv
142 PTR compat_sys_writev 142 PTR compat_sys_writev
143 PTR sys_access /* 6020 */ 143 PTR sys_access /* 6020 */
144 PTR sys_pipe 144 PTR sysm_pipe
145 PTR compat_sys_select 145 PTR compat_sys_select
146 PTR sys_sched_yield 146 PTR sys_sched_yield
147 PTR sys_mremap 147 PTR sys_mremap
diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S
index 9a275efb4f04..76167bea5a70 100644
--- a/arch/mips/kernel/scall64-o32.S
+++ b/arch/mips/kernel/scall64-o32.S
@@ -247,7 +247,7 @@ sys_call_table:
247 PTR sys_mkdir 247 PTR sys_mkdir
248 PTR sys_rmdir /* 4040 */ 248 PTR sys_rmdir /* 4040 */
249 PTR sys_dup 249 PTR sys_dup
250 PTR sys_pipe 250 PTR sysm_pipe
251 PTR compat_sys_times 251 PTR compat_sys_times
252 PTR sys_ni_syscall 252 PTR sys_ni_syscall
253 PTR sys_brk /* 4045 */ 253 PTR sys_brk /* 4045 */
diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c
index af1bdc897488..3523c8d12eda 100644
--- a/arch/mips/kernel/syscall.c
+++ b/arch/mips/kernel/syscall.c
@@ -40,7 +40,14 @@
40#include <asm/sysmips.h> 40#include <asm/sysmips.h>
41#include <asm/uaccess.h> 41#include <asm/uaccess.h>
42 42
43asmlinkage int sys_pipe(nabi_no_regargs volatile struct pt_regs regs) 43/*
44 * For historic reasons the pipe(2) syscall on MIPS has an unusual calling
45 * convention. It returns results in registers $v0 / $v1 which means there
46 * is no need for it to do verify the validity of a userspace pointer
47 * argument. Historically that used to be expensive in Linux. These days
48 * the performance advantage is negligible.
49 */
50asmlinkage int sysm_pipe(nabi_no_regargs volatile struct pt_regs regs)
44{ 51{
45 int fd[2]; 52 int fd[2];
46 int error, res; 53 int error, res;
diff --git a/arch/mips/math-emu/kernel_linkage.c b/arch/mips/math-emu/kernel_linkage.c
index ed49ef01ac53..52e6c58c8de1 100644
--- a/arch/mips/math-emu/kernel_linkage.c
+++ b/arch/mips/math-emu/kernel_linkage.c
@@ -24,6 +24,7 @@
24#include <asm/signal.h> 24#include <asm/signal.h>
25#include <asm/uaccess.h> 25#include <asm/uaccess.h>
26 26
27#include <asm/fpu.h>
27#include <asm/fpu_emulator.h> 28#include <asm/fpu_emulator.h>
28 29
29#define SIGNALLING_NAN 0x7ff800007ff80000LL 30#define SIGNALLING_NAN 0x7ff800007ff80000LL
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 57e34cafa497..15e01aec37fd 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -49,3 +49,4 @@ obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-rbtx4938.o
49obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o 49obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
50obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o 50obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
51obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o 51obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
52obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o
diff --git a/arch/mips/pci/fixup-rc32434.c b/arch/mips/pci/fixup-rc32434.c
new file mode 100644
index 000000000000..75b90dcb7a09
--- /dev/null
+++ b/arch/mips/pci/fixup-rc32434.c
@@ -0,0 +1,69 @@
1/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc.
4 * stevel@mvista.com or source@mvista.com
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27#include <linux/types.h>
28#include <linux/pci.h>
29#include <linux/kernel.h>
30#include <linux/init.h>
31
32#include <asm/mach-rc32434/rc32434.h>
33
34static int __devinitdata irq_map[2][12] = {
35 {0, 0, 2, 3, 2, 3, 0, 0, 0, 0, 0, 1},
36 {0, 0, 1, 3, 0, 2, 1, 3, 0, 2, 1, 3}
37};
38
39int __devinit pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
40{
41 int irq = 0;
42
43 if (dev->bus->number < 2 && PCI_SLOT(dev->devfn) < 12)
44 irq = irq_map[dev->bus->number][PCI_SLOT(dev->devfn)];
45
46 return irq + GROUP4_IRQ_BASE + 4;
47}
48
49static void rc32434_pci_early_fixup(struct pci_dev *dev)
50{
51 if (PCI_SLOT(dev->devfn) == 6 && dev->bus->number == 0) {
52 /* disable prefetched memory range */
53 pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, 0);
54 pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, 0x10);
55
56 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 4);
57 }
58}
59
60/*
61 * The fixup applies to both the IDT and VIA devices present on the board
62 */
63DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, rc32434_pci_early_fixup);
64
65/* Do platform specific device initialization at pci_enable_device() time */
66int pcibios_plat_dev_init(struct pci_dev *dev)
67{
68 return 0;
69}
diff --git a/arch/mips/pci/ops-rc32434.c b/arch/mips/pci/ops-rc32434.c
new file mode 100644
index 000000000000..d1f8fa210ca1
--- /dev/null
+++ b/arch/mips/pci/ops-rc32434.c
@@ -0,0 +1,207 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * pci_ops for IDT EB434 board
4 *
5 * Copyright 2004 IDT Inc. (rischelp@idt.com)
6 * Copyright 2006 Felix Fietkau <nbd@openwrt.org>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28#include <linux/delay.h>
29#include <linux/init.h>
30#include <linux/io.h>
31#include <linux/pci.h>
32#include <linux/types.h>
33
34#include <asm/cpu.h>
35#include <asm/mach-rc32434/rc32434.h>
36#include <asm/mach-rc32434/pci.h>
37
38#define PCI_ACCESS_READ 0
39#define PCI_ACCESS_WRITE 1
40
41
42#define PCI_CFG_SET(bus, slot, func, off) \
43 (rc32434_pci->pcicfga = (0x80000000 | \
44 ((bus) << 16) | ((slot)<<11) | \
45 ((func)<<8) | (off)))
46
47static inline int config_access(unsigned char access_type,
48 struct pci_bus *bus, unsigned int devfn,
49 unsigned char where, u32 *data)
50{
51 unsigned int slot = PCI_SLOT(devfn);
52 u8 func = PCI_FUNC(devfn);
53
54 /* Setup address */
55 PCI_CFG_SET(bus->number, slot, func, where);
56 rc32434_sync();
57
58 if (access_type == PCI_ACCESS_WRITE)
59 rc32434_pci->pcicfgd = *data;
60 else
61 *data = rc32434_pci->pcicfgd;
62
63 rc32434_sync();
64
65 return 0;
66}
67
68
69/*
70 * We can't address 8 and 16 bit words directly. Instead we have to
71 * read/write a 32bit word and mask/modify the data we actually want.
72 */
73static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
74 int where, u8 *val)
75{
76 u32 data;
77 int ret;
78
79 ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
80 *val = (data >> ((where & 3) << 3)) & 0xff;
81 return ret;
82}
83
84static int read_config_word(struct pci_bus *bus, unsigned int devfn,
85 int where, u16 *val)
86{
87 u32 data;
88 int ret;
89
90 ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
91 *val = (data >> ((where & 3) << 3)) & 0xffff;
92 return ret;
93}
94
95static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
96 int where, u32 *val)
97{
98 int ret;
99 int delay = 1;
100
101 /*
102 * Don't scan too far, else there will be errors with plugged in
103 * daughterboard (rb564).
104 */
105 if (bus->number == 0 && PCI_SLOT(devfn) > 21)
106 return 0;
107
108retry:
109 ret = config_access(PCI_ACCESS_READ, bus, devfn, where, val);
110
111 /*
112 * Certain devices react delayed at device scan time, this
113 * gives them time to settle
114 */
115 if (where == PCI_VENDOR_ID) {
116 if (ret == 0xffffffff || ret == 0x00000000 ||
117 ret == 0x0000ffff || ret == 0xffff0000) {
118 if (delay > 4)
119 return 0;
120 delay *= 2;
121 msleep(delay);
122 goto retry;
123 }
124 }
125
126 return ret;
127}
128
129static int
130write_config_byte(struct pci_bus *bus, unsigned int devfn, int where,
131 u8 val)
132{
133 u32 data = 0;
134
135 if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
136 return -1;
137
138 data = (data & ~(0xff << ((where & 3) << 3))) |
139 (val << ((where & 3) << 3));
140
141 if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
142 return -1;
143
144 return PCIBIOS_SUCCESSFUL;
145}
146
147
148static int
149write_config_word(struct pci_bus *bus, unsigned int devfn, int where,
150 u16 val)
151{
152 u32 data = 0;
153
154 if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
155 return -1;
156
157 data = (data & ~(0xffff << ((where & 3) << 3))) |
158 (val << ((where & 3) << 3));
159
160 if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
161 return -1;
162
163
164 return PCIBIOS_SUCCESSFUL;
165}
166
167
168static int
169write_config_dword(struct pci_bus *bus, unsigned int devfn, int where,
170 u32 val)
171{
172 if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val))
173 return -1;
174
175 return PCIBIOS_SUCCESSFUL;
176}
177
178static int pci_config_read(struct pci_bus *bus, unsigned int devfn,
179 int where, int size, u32 *val)
180{
181 switch (size) {
182 case 1:
183 return read_config_byte(bus, devfn, where, (u8 *) val);
184 case 2:
185 return read_config_word(bus, devfn, where, (u16 *) val);
186 default:
187 return read_config_dword(bus, devfn, where, val);
188 }
189}
190
191static int pci_config_write(struct pci_bus *bus, unsigned int devfn,
192 int where, int size, u32 val)
193{
194 switch (size) {
195 case 1:
196 return write_config_byte(bus, devfn, where, (u8) val);
197 case 2:
198 return write_config_word(bus, devfn, where, (u16) val);
199 default:
200 return write_config_dword(bus, devfn, where, val);
201 }
202}
203
204struct pci_ops rc32434_pci_ops = {
205 .read = pci_config_read,
206 .write = pci_config_write,
207};
diff --git a/arch/mips/pci/pci-rc32434.c b/arch/mips/pci/pci-rc32434.c
new file mode 100644
index 000000000000..1c2821e2f494
--- /dev/null
+++ b/arch/mips/pci/pci-rc32434.c
@@ -0,0 +1,221 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * PCI initialization for IDT EB434 board
4 *
5 * Copyright 2004 IDT Inc. (rischelp@idt.com)
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#include <linux/types.h>
29#include <linux/pci.h>
30#include <linux/kernel.h>
31#include <linux/init.h>
32
33#include <asm/mach-rc32434/rc32434.h>
34#include <asm/mach-rc32434/pci.h>
35
36#define PCI_ACCESS_READ 0
37#define PCI_ACCESS_WRITE 1
38
39/* define an unsigned array for the PCI registers */
40static unsigned int korina_cnfg_regs[25] = {
41 KORINA_CNFG1, KORINA_CNFG2, KORINA_CNFG3, KORINA_CNFG4,
42 KORINA_CNFG5, KORINA_CNFG6, KORINA_CNFG7, KORINA_CNFG8,
43 KORINA_CNFG9, KORINA_CNFG10, KORINA_CNFG11, KORINA_CNFG12,
44 KORINA_CNFG13, KORINA_CNFG14, KORINA_CNFG15, KORINA_CNFG16,
45 KORINA_CNFG17, KORINA_CNFG18, KORINA_CNFG19, KORINA_CNFG20,
46 KORINA_CNFG21, KORINA_CNFG22, KORINA_CNFG23, KORINA_CNFG24
47};
48static struct resource rc32434_res_pci_mem1;
49static struct resource rc32434_res_pci_mem2;
50
51static struct resource rc32434_res_pci_mem1 = {
52 .name = "PCI MEM1",
53 .start = 0x50000000,
54 .end = 0x5FFFFFFF,
55 .flags = IORESOURCE_MEM,
56 .parent = &rc32434_res_pci_mem1,
57 .sibling = NULL,
58 .child = &rc32434_res_pci_mem2
59};
60
61static struct resource rc32434_res_pci_mem2 = {
62 .name = "PCI Mem2",
63 .start = 0x60000000,
64 .end = 0x6FFFFFFF,
65 .flags = IORESOURCE_MEM,
66 .parent = &rc32434_res_pci_mem1,
67 .sibling = NULL,
68 .child = NULL
69};
70
71static struct resource rc32434_res_pci_io1 = {
72 .name = "PCI I/O1",
73 .start = 0x18800000,
74 .end = 0x188FFFFF,
75 .flags = IORESOURCE_IO,
76};
77
78extern struct pci_ops rc32434_pci_ops;
79
80#define PCI_MEM1_START PCI_ADDR_START
81#define PCI_MEM1_END (PCI_ADDR_START + CPUTOPCI_MEM_WIN - 1)
82#define PCI_MEM2_START (PCI_ADDR_START + CPUTOPCI_MEM_WIN)
83#define PCI_MEM2_END (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) - 1)
84#define PCI_IO1_START (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN))
85#define PCI_IO1_END \
86 (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN - 1)
87#define PCI_IO2_START \
88 (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN)
89#define PCI_IO2_END \
90 (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + (2 * CPUTOPCI_IO_WIN) - 1)
91
92struct pci_controller rc32434_controller2;
93
94struct pci_controller rc32434_controller = {
95 .pci_ops = &rc32434_pci_ops,
96 .mem_resource = &rc32434_res_pci_mem1,
97 .io_resource = &rc32434_res_pci_io1,
98 .mem_offset = 0,
99 .io_offset = 0,
100
101};
102
103#ifdef __MIPSEB__
104#define PCI_ENDIAN_FLAG PCILBAC_sb_m
105#else
106#define PCI_ENDIAN_FLAG 0
107#endif
108
109static int __init rc32434_pcibridge_init(void)
110{
111 unsigned int pcicvalue, pcicdata = 0;
112 unsigned int dummyread, pcicntlval;
113 int loopCount;
114 unsigned int pci_config_addr;
115
116 pcicvalue = rc32434_pci->pcic;
117 pcicvalue = (pcicvalue >> PCIM_SHFT) & PCIM_BIT_LEN;
118 if (!((pcicvalue == PCIM_H_EA) ||
119 (pcicvalue == PCIM_H_IA_FIX) ||
120 (pcicvalue == PCIM_H_IA_RR))) {
121 pr_err(KERN_ERR "PCI init error!!!\n");
122 /* Not in Host Mode, return ERROR */
123 return -1;
124 }
125 /* Enables the Idle Grant mode, Arbiter Parking */
126 pcicdata |= (PCI_CTL_IGM | PCI_CTL_EAP | PCI_CTL_EN);
127 rc32434_pci->pcic = pcicdata; /* Enable the PCI bus Interface */
128 /* Zero out the PCI status & PCI Status Mask */
129 for (;;) {
130 pcicdata = rc32434_pci->pcis;
131 if (!(pcicdata & PCI_STAT_RIP))
132 break;
133 }
134
135 rc32434_pci->pcis = 0;
136 rc32434_pci->pcism = 0xFFFFFFFF;
137 /* Zero out the PCI decoupled registers */
138 rc32434_pci->pcidac = 0; /*
139 * disable PCI decoupled accesses at
140 * initialization
141 */
142 rc32434_pci->pcidas = 0; /* clear the status */
143 rc32434_pci->pcidasm = 0x0000007F; /* Mask all the interrupts */
144 /* Mask PCI Messaging Interrupts */
145 rc32434_pci_msg->pciiic = 0;
146 rc32434_pci_msg->pciiim = 0xFFFFFFFF;
147 rc32434_pci_msg->pciioic = 0;
148 rc32434_pci_msg->pciioim = 0;
149
150
151 /* Setup PCILB0 as Memory Window */
152 rc32434_pci->pcilba[0].address = (unsigned int) (PCI_ADDR_START);
153
154 /* setup the PCI map address as same as the local address */
155
156 rc32434_pci->pcilba[0].mapping = (unsigned int) (PCI_ADDR_START);
157
158
159 /* Setup PCILBA1 as MEM */
160 rc32434_pci->pcilba[0].control =
161 (((SIZE_256MB & 0x1f) << PCI_LBAC_SIZE_BIT) | PCI_ENDIAN_FLAG);
162 dummyread = rc32434_pci->pcilba[0].control; /* flush the CPU write Buffers */
163 rc32434_pci->pcilba[1].address = 0x60000000;
164 rc32434_pci->pcilba[1].mapping = 0x60000000;
165
166 /* setup PCILBA2 as IO Window */
167 rc32434_pci->pcilba[1].control =
168 (((SIZE_256MB & 0x1f) << PCI_LBAC_SIZE_BIT) | PCI_ENDIAN_FLAG);
169 dummyread = rc32434_pci->pcilba[1].control; /* flush the CPU write Buffers */
170 rc32434_pci->pcilba[2].address = 0x18C00000;
171 rc32434_pci->pcilba[2].mapping = 0x18FFFFFF;
172
173 /* setup PCILBA2 as IO Window */
174 rc32434_pci->pcilba[2].control =
175 (((SIZE_4MB & 0x1f) << PCI_LBAC_SIZE_BIT) | PCI_ENDIAN_FLAG);
176 dummyread = rc32434_pci->pcilba[2].control; /* flush the CPU write Buffers */
177
178 /* Setup PCILBA3 as IO Window */
179 rc32434_pci->pcilba[3].address = 0x18800000;
180 rc32434_pci->pcilba[3].mapping = 0x18800000;
181 rc32434_pci->pcilba[3].control =
182 ((((SIZE_1MB & 0x1ff) << PCI_LBAC_SIZE_BIT) | PCI_LBAC_MSI) |
183 PCI_ENDIAN_FLAG);
184 dummyread = rc32434_pci->pcilba[3].control; /* flush the CPU write Buffers */
185
186 pci_config_addr = (unsigned int) (0x80000004);
187 for (loopCount = 0; loopCount < 24; loopCount++) {
188 rc32434_pci->pcicfga = pci_config_addr;
189 dummyread = rc32434_pci->pcicfga;
190 rc32434_pci->pcicfgd = korina_cnfg_regs[loopCount];
191 dummyread = rc32434_pci->pcicfgd;
192 pci_config_addr += 4;
193 }
194 rc32434_pci->pcitc =
195 (unsigned int) ((PCITC_RTIMER_VAL & 0xff) << PCI_TC_RTIMER_BIT) |
196 ((PCITC_DTIMER_VAL & 0xff) << PCI_TC_DTIMER_BIT);
197
198 pcicntlval = rc32434_pci->pcic;
199 pcicntlval &= ~PCI_CTL_TNR;
200 rc32434_pci->pcic = pcicntlval;
201 pcicntlval = rc32434_pci->pcic;
202
203 return 0;
204}
205
206static int __init rc32434_pci_init(void)
207{
208 pr_info("PCI: Initializing PCI\n");
209
210 ioport_resource.start = rc32434_res_pci_io1.start;
211 ioport_resource.end = rc32434_res_pci_io1.end;
212
213 rc32434_pcibridge_init();
214
215 register_pci_controller(&rc32434_controller);
216 rc32434_sync();
217
218 return 0;
219}
220
221arch_initcall(rc32434_pci_init);
diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index d7d6cb063d26..77bd5b68dc43 100644
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -204,7 +204,7 @@ static int pcibios_enable_resources(struct pci_dev *dev, int mask)
204 * If we set up a device for bus mastering, we need to check the latency 204 * If we set up a device for bus mastering, we need to check the latency
205 * timer as certain crappy BIOSes forget to set it properly. 205 * timer as certain crappy BIOSes forget to set it properly.
206 */ 206 */
207unsigned int pcibios_max_latency = 255; 207static unsigned int pcibios_max_latency = 255;
208 208
209void pcibios_set_master(struct pci_dev *dev) 209void pcibios_set_master(struct pci_dev *dev)
210{ 210{
diff --git a/arch/mips/rb532/Makefile b/arch/mips/rb532/Makefile
new file mode 100644
index 000000000000..8f0b6b6a1625
--- /dev/null
+++ b/arch/mips/rb532/Makefile
@@ -0,0 +1,7 @@
1#
2# Makefile for the RB532 board specific parts of the kernel
3#
4
5obj-y += irq.o time.o setup.o serial.o prom.o gpio.o devices.o
6
7EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/rb532/devices.c b/arch/mips/rb532/devices.c
new file mode 100644
index 000000000000..44fb0a62877f
--- /dev/null
+++ b/arch/mips/rb532/devices.c
@@ -0,0 +1,331 @@
1/*
2 * RouterBoard 500 Platform devices
3 *
4 * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2007 Florian Fainelli <florian@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/ctype.h>
20#include <linux/string.h>
21#include <linux/platform_device.h>
22#include <linux/mtd/nand.h>
23#include <linux/mtd/mtd.h>
24#include <linux/mtd/partitions.h>
25#include <linux/gpio_keys.h>
26#include <linux/input.h>
27
28#include <asm/bootinfo.h>
29
30#include <asm/mach-rc32434/rc32434.h>
31#include <asm/mach-rc32434/dma.h>
32#include <asm/mach-rc32434/dma_v.h>
33#include <asm/mach-rc32434/eth.h>
34#include <asm/mach-rc32434/rb.h>
35#include <asm/mach-rc32434/integ.h>
36#include <asm/mach-rc32434/gpio.h>
37
38#define ETH0_DMA_RX_IRQ (GROUP1_IRQ_BASE + 0)
39#define ETH0_DMA_TX_IRQ (GROUP1_IRQ_BASE + 1)
40#define ETH0_RX_OVR_IRQ (GROUP3_IRQ_BASE + 9)
41#define ETH0_TX_UND_IRQ (GROUP3_IRQ_BASE + 10)
42
43#define ETH0_RX_DMA_ADDR (DMA0_BASE_ADDR + 0 * DMA_CHAN_OFFSET)
44#define ETH0_TX_DMA_ADDR (DMA0_BASE_ADDR + 1 * DMA_CHAN_OFFSET)
45
46/* NAND definitions */
47#define GPIO_RDY (1 << 0x08)
48#define GPIO_WPX (1 << 0x09)
49#define GPIO_ALE (1 << 0x0a)
50#define GPIO_CLE (1 << 0x0b)
51
52extern char *board_type;
53
54static struct resource korina_dev0_res[] = {
55 {
56 .name = "korina_regs",
57 .start = ETH0_BASE_ADDR,
58 .end = ETH0_BASE_ADDR + sizeof(struct eth_regs),
59 .flags = IORESOURCE_MEM,
60 }, {
61 .name = "korina_rx",
62 .start = ETH0_DMA_RX_IRQ,
63 .end = ETH0_DMA_RX_IRQ,
64 .flags = IORESOURCE_IRQ
65 }, {
66 .name = "korina_tx",
67 .start = ETH0_DMA_TX_IRQ,
68 .end = ETH0_DMA_TX_IRQ,
69 .flags = IORESOURCE_IRQ
70 }, {
71 .name = "korina_ovr",
72 .start = ETH0_RX_OVR_IRQ,
73 .end = ETH0_RX_OVR_IRQ,
74 .flags = IORESOURCE_IRQ
75 }, {
76 .name = "korina_und",
77 .start = ETH0_TX_UND_IRQ,
78 .end = ETH0_TX_UND_IRQ,
79 .flags = IORESOURCE_IRQ
80 }, {
81 .name = "korina_dma_rx",
82 .start = ETH0_RX_DMA_ADDR,
83 .end = ETH0_RX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
84 .flags = IORESOURCE_MEM,
85 }, {
86 .name = "korina_dma_tx",
87 .start = ETH0_TX_DMA_ADDR,
88 .end = ETH0_TX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
89 .flags = IORESOURCE_MEM,
90 }
91};
92
93static struct korina_device korina_dev0_data = {
94 .name = "korina0",
95 .mac = {0xde, 0xca, 0xff, 0xc0, 0xff, 0xee}
96};
97
98static struct platform_device korina_dev0 = {
99 .id = 0,
100 .name = "korina",
101 .dev.platform_data = &korina_dev0_data,
102 .resource = korina_dev0_res,
103 .num_resources = ARRAY_SIZE(korina_dev0_res),
104};
105
106#define CF_GPIO_NUM 13
107
108static struct resource cf_slot0_res[] = {
109 {
110 .name = "cf_membase",
111 .flags = IORESOURCE_MEM
112 }, {
113 .name = "cf_irq",
114 .start = (8 + 4 * 32 + CF_GPIO_NUM), /* 149 */
115 .end = (8 + 4 * 32 + CF_GPIO_NUM),
116 .flags = IORESOURCE_IRQ
117 }
118};
119
120static struct cf_device cf_slot0_data = {
121 .gpio_pin = 13
122};
123
124static struct platform_device cf_slot0 = {
125 .id = 0,
126 .name = "pata-rb532-cf",
127 .dev.platform_data = &cf_slot0_data,
128 .resource = cf_slot0_res,
129 .num_resources = ARRAY_SIZE(cf_slot0_res),
130};
131
132/* Resources and device for NAND */
133static int rb532_dev_ready(struct mtd_info *mtd)
134{
135 return readl(IDT434_REG_BASE + GPIOD) & GPIO_RDY;
136}
137
138static void rb532_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
139{
140 struct nand_chip *chip = mtd->priv;
141 unsigned char orbits, nandbits;
142
143 if (ctrl & NAND_CTRL_CHANGE) {
144 orbits = (ctrl & NAND_CLE) << 1;
145 orbits |= (ctrl & NAND_ALE) >> 1;
146
147 nandbits = (~ctrl & NAND_CLE) << 1;
148 nandbits |= (~ctrl & NAND_ALE) >> 1;
149
150 set_latch_u5(orbits, nandbits);
151 }
152 if (cmd != NAND_CMD_NONE)
153 writeb(cmd, chip->IO_ADDR_W);
154}
155
156static struct resource nand_slot0_res[] = {
157 [0] = {
158 .name = "nand_membase",
159 .flags = IORESOURCE_MEM
160 }
161};
162
163static struct platform_nand_data rb532_nand_data = {
164 .ctrl.dev_ready = rb532_dev_ready,
165 .ctrl.cmd_ctrl = rb532_cmd_ctrl,
166};
167
168static struct platform_device nand_slot0 = {
169 .name = "gen_nand",
170 .id = -1,
171 .resource = nand_slot0_res,
172 .num_resources = ARRAY_SIZE(nand_slot0_res),
173 .dev.platform_data = &rb532_nand_data,
174};
175
176static struct mtd_partition rb532_partition_info[] = {
177 {
178 .name = "Routerboard NAND boot",
179 .offset = 0,
180 .size = 4 * 1024 * 1024,
181 }, {
182 .name = "rootfs",
183 .offset = MTDPART_OFS_NXTBLK,
184 .size = MTDPART_SIZ_FULL,
185 }
186};
187
188static struct platform_device rb532_led = {
189 .name = "rb532-led",
190 .id = 0,
191};
192
193static struct gpio_keys_button rb532_gpio_btn[] = {
194 {
195 .gpio = 1,
196 .code = BTN_0,
197 .desc = "S1",
198 .active_low = 1,
199 }
200};
201
202static struct gpio_keys_platform_data rb532_gpio_btn_data = {
203 .buttons = rb532_gpio_btn,
204 .nbuttons = ARRAY_SIZE(rb532_gpio_btn),
205};
206
207static struct platform_device rb532_button = {
208 .name = "gpio-keys",
209 .id = -1,
210 .dev = {
211 .platform_data = &rb532_gpio_btn_data,
212 }
213};
214
215static struct resource rb532_wdt_res[] = {
216 {
217 .name = "rb532_wdt_res",
218 .start = INTEG0_BASE_ADDR,
219 .end = INTEG0_BASE_ADDR + sizeof(struct integ),
220 .flags = IORESOURCE_MEM,
221 }
222};
223
224static struct platform_device rb532_wdt = {
225 .name = "rc32434_wdt",
226 .id = -1,
227 .resource = rb532_wdt_res,
228 .num_resources = ARRAY_SIZE(rb532_wdt_res),
229};
230
231static struct platform_device *rb532_devs[] = {
232 &korina_dev0,
233 &nand_slot0,
234 &cf_slot0,
235 &rb532_led,
236 &rb532_button,
237 &rb532_wdt
238};
239
240static void __init parse_mac_addr(char *macstr)
241{
242 int i, j;
243 unsigned char result, value;
244
245 for (i = 0; i < 6; i++) {
246 result = 0;
247
248 if (i != 5 && *(macstr + 2) != ':')
249 return;
250
251 for (j = 0; j < 2; j++) {
252 if (isxdigit(*macstr)
253 && (value =
254 isdigit(*macstr) ? *macstr -
255 '0' : toupper(*macstr) - 'A' + 10) < 16) {
256 result = result * 16 + value;
257 macstr++;
258 } else
259 return;
260 }
261
262 macstr++;
263 korina_dev0_data.mac[i] = result;
264 }
265}
266
267
268/* DEVICE CONTROLLER 1 */
269#define CFG_DC_DEV1 ((void *)0xb8010010)
270#define CFG_DC_DEV2 ((void *)0xb8010020)
271#define CFG_DC_DEVBASE 0x0
272#define CFG_DC_DEVMASK 0x4
273#define CFG_DC_DEVC 0x8
274#define CFG_DC_DEVTC 0xC
275
276/* NAND definitions */
277#define NAND_CHIP_DELAY 25
278
279static void __init rb532_nand_setup(void)
280{
281 switch (mips_machtype) {
282 case MACH_MIKROTIK_RB532A:
283 set_latch_u5(LO_FOFF | LO_CEX,
284 LO_ULED | LO_ALE | LO_CLE | LO_WPX);
285 break;
286 default:
287 set_latch_u5(LO_WPX | LO_FOFF | LO_CEX,
288 LO_ULED | LO_ALE | LO_CLE);
289 break;
290 }
291
292 /* Setup NAND specific settings */
293 rb532_nand_data.chip.nr_chips = 1;
294 rb532_nand_data.chip.nr_partitions = ARRAY_SIZE(rb532_partition_info);
295 rb532_nand_data.chip.partitions = rb532_partition_info;
296 rb532_nand_data.chip.chip_delay = NAND_CHIP_DELAY;
297 rb532_nand_data.chip.options = NAND_NO_AUTOINCR;
298}
299
300
301static int __init plat_setup_devices(void)
302{
303 /* Look for the CF card reader */
304 if (!readl(CFG_DC_DEV1 + CFG_DC_DEVMASK))
305 rb532_devs[1] = NULL;
306 else {
307 cf_slot0_res[0].start =
308 readl(CFG_DC_DEV1 + CFG_DC_DEVBASE);
309 cf_slot0_res[0].end = cf_slot0_res[0].start + 0x1000;
310 }
311
312 /* Read the NAND resources from the device controller */
313 nand_slot0_res[0].start = readl(CFG_DC_DEV2 + CFG_DC_DEVBASE);
314 nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000;
315
316 /* Initialise the NAND device */
317 rb532_nand_setup();
318
319 return platform_add_devices(rb532_devs, ARRAY_SIZE(rb532_devs));
320}
321
322static int __init setup_kmac(char *s)
323{
324 printk(KERN_INFO "korina mac = %s\n", s);
325 parse_mac_addr(s);
326 return 0;
327}
328
329__setup("kmac=", setup_kmac);
330
331arch_initcall(plat_setup_devices);
diff --git a/arch/mips/rb532/gpio.c b/arch/mips/rb532/gpio.c
new file mode 100644
index 000000000000..b2fe82dba0a5
--- /dev/null
+++ b/arch/mips/rb532/gpio.c
@@ -0,0 +1,220 @@
1/*
2 * Miscellaneous functions for IDT EB434 board
3 *
4 * Copyright 2004 IDT Inc. (rischelp@idt.com)
5 * Copyright 2006 Phil Sutter <n0-1@freewrt.org>
6 * Copyright 2007 Florian Fainelli <florian@openwrt.org>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#include <linux/kernel.h>
30#include <linux/gpio.h>
31#include <linux/init.h>
32#include <linux/types.h>
33#include <linux/pci.h>
34#include <linux/spinlock.h>
35#include <linux/io.h>
36#include <linux/platform_device.h>
37
38#include <asm/addrspace.h>
39
40#include <asm/mach-rc32434/rb.h>
41
42struct rb532_gpio_reg __iomem *rb532_gpio_reg0;
43EXPORT_SYMBOL(rb532_gpio_reg0);
44
45struct mpmc_device dev3;
46
47static struct resource rb532_gpio_reg0_res[] = {
48 {
49 .name = "gpio_reg0",
50 .start = (u32)(IDT434_REG_BASE + GPIOBASE),
51 .end = (u32)(IDT434_REG_BASE + GPIOBASE + sizeof(struct rb532_gpio_reg)),
52 .flags = IORESOURCE_MEM,
53 }
54};
55
56static struct resource rb532_dev3_ctl_res[] = {
57 {
58 .name = "dev3_ctl",
59 .start = (u32)(IDT434_REG_BASE + DEV3BASE),
60 .end = (u32)(IDT434_REG_BASE + DEV3BASE + sizeof(struct dev_reg)),
61 .flags = IORESOURCE_MEM,
62 }
63};
64
65void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val)
66{
67 unsigned flags, data;
68 unsigned i = 0;
69
70 spin_lock_irqsave(&dev3.lock, flags);
71
72 data = *(volatile unsigned *) (IDT434_REG_BASE + reg_offs);
73 for (i = 0; i != len; ++i) {
74 if (val & (1 << i))
75 data |= (1 << (i + bit));
76 else
77 data &= ~(1 << (i + bit));
78 }
79 writel(data, (IDT434_REG_BASE + reg_offs));
80
81 spin_unlock_irqrestore(&dev3.lock, flags);
82}
83EXPORT_SYMBOL(set_434_reg);
84
85unsigned get_434_reg(unsigned reg_offs)
86{
87 return readl(IDT434_REG_BASE + reg_offs);
88}
89EXPORT_SYMBOL(get_434_reg);
90
91void set_latch_u5(unsigned char or_mask, unsigned char nand_mask)
92{
93 unsigned flags;
94
95 spin_lock_irqsave(&dev3.lock, flags);
96
97 dev3.state = (dev3.state | or_mask) & ~nand_mask;
98 writel(dev3.state, &dev3.base);
99
100 spin_unlock_irqrestore(&dev3.lock, flags);
101}
102EXPORT_SYMBOL(set_latch_u5);
103
104unsigned char get_latch_u5(void)
105{
106 return dev3.state;
107}
108EXPORT_SYMBOL(get_latch_u5);
109
110int rb532_gpio_get_value(unsigned gpio)
111{
112 return readl(&rb532_gpio_reg0->gpiod) & (1 << gpio);
113}
114EXPORT_SYMBOL(rb532_gpio_get_value);
115
116void rb532_gpio_set_value(unsigned gpio, int value)
117{
118 unsigned tmp;
119
120 tmp = readl(&rb532_gpio_reg0->gpiod) & ~(1 << gpio);
121 if (value)
122 tmp |= 1 << gpio;
123
124 writel(tmp, (void *)&rb532_gpio_reg0->gpiod);
125}
126EXPORT_SYMBOL(rb532_gpio_set_value);
127
128int rb532_gpio_direction_input(unsigned gpio)
129{
130 writel(readl(&rb532_gpio_reg0->gpiocfg) & ~(1 << gpio),
131 (void *)&rb532_gpio_reg0->gpiocfg);
132
133 return 0;
134}
135EXPORT_SYMBOL(rb532_gpio_direction_input);
136
137int rb532_gpio_direction_output(unsigned gpio, int value)
138{
139 gpio_set_value(gpio, value);
140 writel(readl(&rb532_gpio_reg0->gpiocfg) | (1 << gpio),
141 (void *)&rb532_gpio_reg0->gpiocfg);
142
143 return 0;
144}
145EXPORT_SYMBOL(rb532_gpio_direction_output);
146
147void rb532_gpio_set_int_level(unsigned gpio, int value)
148{
149 unsigned tmp;
150
151 tmp = readl(&rb532_gpio_reg0->gpioilevel) & ~(1 << gpio);
152 if (value)
153 tmp |= 1 << gpio;
154 writel(tmp, (void *)&rb532_gpio_reg0->gpioilevel);
155}
156EXPORT_SYMBOL(rb532_gpio_set_int_level);
157
158int rb532_gpio_get_int_level(unsigned gpio)
159{
160 return readl(&rb532_gpio_reg0->gpioilevel) & (1 << gpio);
161}
162EXPORT_SYMBOL(rb532_gpio_get_int_level);
163
164void rb532_gpio_set_int_status(unsigned gpio, int value)
165{
166 unsigned tmp;
167
168 tmp = readl(&rb532_gpio_reg0->gpioistat);
169 if (value)
170 tmp |= 1 << gpio;
171 writel(tmp, (void *)&rb532_gpio_reg0->gpioistat);
172}
173EXPORT_SYMBOL(rb532_gpio_set_int_status);
174
175int rb532_gpio_get_int_status(unsigned gpio)
176{
177 return readl(&rb532_gpio_reg0->gpioistat) & (1 << gpio);
178}
179EXPORT_SYMBOL(rb532_gpio_get_int_status);
180
181void rb532_gpio_set_func(unsigned gpio, int value)
182{
183 unsigned tmp;
184
185 tmp = readl(&rb532_gpio_reg0->gpiofunc);
186 if (value)
187 tmp |= 1 << gpio;
188 writel(tmp, (void *)&rb532_gpio_reg0->gpiofunc);
189}
190EXPORT_SYMBOL(rb532_gpio_set_func);
191
192int rb532_gpio_get_func(unsigned gpio)
193{
194 return readl(&rb532_gpio_reg0->gpiofunc) & (1 << gpio);
195}
196EXPORT_SYMBOL(rb532_gpio_get_func);
197
198int __init rb532_gpio_init(void)
199{
200 rb532_gpio_reg0 = ioremap_nocache(rb532_gpio_reg0_res[0].start,
201 rb532_gpio_reg0_res[0].end -
202 rb532_gpio_reg0_res[0].start);
203
204 if (!rb532_gpio_reg0) {
205 printk(KERN_ERR "rb532: cannot remap GPIO register 0\n");
206 return -ENXIO;
207 }
208
209 dev3.base = ioremap_nocache(rb532_dev3_ctl_res[0].start,
210 rb532_dev3_ctl_res[0].end -
211 rb532_dev3_ctl_res[0].start);
212
213 if (!dev3.base) {
214 printk(KERN_ERR "rb532: cannot remap device controller 3\n");
215 return -ENXIO;
216 }
217
218 return 0;
219}
220arch_initcall(rb532_gpio_init);
diff --git a/arch/mips/rb532/irq.c b/arch/mips/rb532/irq.c
new file mode 100644
index 000000000000..c0d0f950caf2
--- /dev/null
+++ b/arch/mips/rb532/irq.c
@@ -0,0 +1,209 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
10 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
12 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
13 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
14 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
15 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
16 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 * Copyright 2002 MontaVista Software Inc.
23 * Author: MontaVista Software, Inc.
24 * stevel@mvista.com or source@mvista.com
25 */
26
27#include <linux/bitops.h>
28#include <linux/errno.h>
29#include <linux/init.h>
30#include <linux/io.h>
31#include <linux/kernel_stat.h>
32#include <linux/module.h>
33#include <linux/signal.h>
34#include <linux/sched.h>
35#include <linux/types.h>
36#include <linux/interrupt.h>
37#include <linux/ioport.h>
38#include <linux/timex.h>
39#include <linux/slab.h>
40#include <linux/random.h>
41#include <linux/delay.h>
42
43#include <asm/bootinfo.h>
44#include <asm/time.h>
45#include <asm/mipsregs.h>
46#include <asm/system.h>
47
48#include <asm/mach-rc32434/rc32434.h>
49
50struct intr_group {
51 u32 mask; /* mask of valid bits in pending/mask registers */
52 volatile u32 *base_addr;
53};
54
55#define RC32434_NR_IRQS (GROUP4_IRQ_BASE + 32)
56
57#if (NR_IRQS < RC32434_NR_IRQS)
58#error Too little irqs defined. Did you override <asm/irq.h> ?
59#endif
60
61static const struct intr_group intr_group[NUM_INTR_GROUPS] = {
62 {
63 .mask = 0x0000efff,
64 .base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 0 * IC_GROUP_OFFSET)},
65 {
66 .mask = 0x00001fff,
67 .base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 1 * IC_GROUP_OFFSET)},
68 {
69 .mask = 0x00000007,
70 .base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 2 * IC_GROUP_OFFSET)},
71 {
72 .mask = 0x0003ffff,
73 .base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 3 * IC_GROUP_OFFSET)},
74 {
75 .mask = 0xffffffff,
76 .base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 4 * IC_GROUP_OFFSET)}
77};
78
79#define READ_PEND(base) (*(base))
80#define READ_MASK(base) (*(base + 2))
81#define WRITE_MASK(base, val) (*(base + 2) = (val))
82
83static inline int irq_to_group(unsigned int irq_nr)
84{
85 return (irq_nr - GROUP0_IRQ_BASE) >> 5;
86}
87
88static inline int group_to_ip(unsigned int group)
89{
90 return group + 2;
91}
92
93static inline void enable_local_irq(unsigned int ip)
94{
95 int ipnum = 0x100 << ip;
96
97 set_c0_status(ipnum);
98}
99
100static inline void disable_local_irq(unsigned int ip)
101{
102 int ipnum = 0x100 << ip;
103
104 clear_c0_status(ipnum);
105}
106
107static inline void ack_local_irq(unsigned int ip)
108{
109 int ipnum = 0x100 << ip;
110
111 clear_c0_cause(ipnum);
112}
113
114static void rb532_enable_irq(unsigned int irq_nr)
115{
116 int ip = irq_nr - GROUP0_IRQ_BASE;
117 unsigned int group, intr_bit;
118 volatile unsigned int *addr;
119
120 if (ip < 0)
121 enable_local_irq(irq_nr);
122 else {
123 group = ip >> 5;
124
125 ip &= (1 << 5) - 1;
126 intr_bit = 1 << ip;
127
128 enable_local_irq(group_to_ip(group));
129
130 addr = intr_group[group].base_addr;
131 WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);
132 }
133}
134
135static void rb532_disable_irq(unsigned int irq_nr)
136{
137 int ip = irq_nr - GROUP0_IRQ_BASE;
138 unsigned int group, intr_bit, mask;
139 volatile unsigned int *addr;
140
141 if (ip < 0) {
142 disable_local_irq(irq_nr);
143 } else {
144 group = ip >> 5;
145
146 ip &= (1 << 5) - 1;
147 intr_bit = 1 << ip;
148 addr = intr_group[group].base_addr;
149 mask = READ_MASK(addr);
150 mask |= intr_bit;
151 WRITE_MASK(addr, mask);
152
153 /*
154 * if there are no more interrupts enabled in this
155 * group, disable corresponding IP
156 */
157 if (mask == intr_group[group].mask)
158 disable_local_irq(group_to_ip(group));
159 }
160}
161
162static void rb532_mask_and_ack_irq(unsigned int irq_nr)
163{
164 rb532_disable_irq(irq_nr);
165 ack_local_irq(group_to_ip(irq_to_group(irq_nr)));
166}
167
168static struct irq_chip rc32434_irq_type = {
169 .name = "RB532",
170 .ack = rb532_disable_irq,
171 .mask = rb532_disable_irq,
172 .mask_ack = rb532_mask_and_ack_irq,
173 .unmask = rb532_enable_irq,
174};
175
176void __init arch_init_irq(void)
177{
178 int i;
179
180 pr_info("Initializing IRQ's: %d out of %d\n", RC32434_NR_IRQS, NR_IRQS);
181
182 for (i = 0; i < RC32434_NR_IRQS; i++)
183 set_irq_chip_and_handler(i, &rc32434_irq_type,
184 handle_level_irq);
185}
186
187/* Main Interrupt dispatcher */
188asmlinkage void plat_irq_dispatch(void)
189{
190 unsigned int ip, pend, group;
191 volatile unsigned int *addr;
192 unsigned int cp0_cause = read_c0_cause() & read_c0_status();
193
194 if (cp0_cause & CAUSEF_IP7) {
195 do_IRQ(7);
196 } else {
197 ip = (cp0_cause & 0x7c00);
198 if (ip) {
199 group = 21 + (fls(ip) - 32);
200
201 addr = intr_group[group].base_addr;
202
203 pend = READ_PEND(addr);
204 pend &= ~READ_MASK(addr); /* only unmasked interrupts */
205 pend = 39 + (fls(pend) - 32);
206 do_IRQ((group << 5) + pend);
207 }
208 }
209}
diff --git a/arch/mips/rb532/prom.c b/arch/mips/rb532/prom.c
new file mode 100644
index 000000000000..1bc0af8febf4
--- /dev/null
+++ b/arch/mips/rb532/prom.c
@@ -0,0 +1,158 @@
1/*
2 * RouterBoard 500 specific prom routines
3 *
4 * Copyright (C) 2003, Peter Sadik <peter.sadik@idt.com>
5 * Copyright (C) 2005-2006, P.Christeas <p_christ@hol.gr>
6 * Copyright (C) 2007, Gabor Juhos <juhosg@openwrt.org>
7 * Felix Fietkau <nbd@openwrt.org>
8 * Florian Fainelli <florian@openwrt.org>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the
22 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
23 * Boston, MA 02110-1301, USA.
24 *
25 */
26
27#include <linux/init.h>
28#include <linux/mm.h>
29#include <linux/module.h>
30#include <linux/string.h>
31#include <linux/console.h>
32#include <linux/bootmem.h>
33#include <linux/ioport.h>
34#include <linux/blkdev.h>
35
36#include <asm/bootinfo.h>
37#include <asm/mach-rc32434/ddr.h>
38#include <asm/mach-rc32434/prom.h>
39
40extern void __init setup_serial_port(void);
41
42unsigned int idt_cpu_freq = 132000000;
43EXPORT_SYMBOL(idt_cpu_freq);
44unsigned int gpio_bootup_state;
45EXPORT_SYMBOL(gpio_bootup_state);
46
47static struct resource ddr_reg[] = {
48 {
49 .name = "ddr-reg",
50 .start = DDR0_PHYS_ADDR,
51 .end = DDR0_PHYS_ADDR + sizeof(struct ddr_ram),
52 .flags = IORESOURCE_MEM,
53 }
54};
55
56void __init prom_free_prom_memory(void)
57{
58 /* No prom memory to free */
59}
60
61static inline int match_tag(char *arg, const char *tag)
62{
63 return strncmp(arg, tag, strlen(tag)) == 0;
64}
65
66static inline unsigned long tag2ul(char *arg, const char *tag)
67{
68 char *num;
69
70 num = arg + strlen(tag);
71 return simple_strtoul(num, 0, 10);
72}
73
74void __init prom_setup_cmdline(void)
75{
76 char cmd_line[CL_SIZE];
77 char *cp, *board;
78 int prom_argc;
79 char **prom_argv, **prom_envp;
80 int i;
81
82 prom_argc = fw_arg0;
83 prom_argv = (char **) fw_arg1;
84 prom_envp = (char **) fw_arg2;
85
86 cp = cmd_line;
87 /* Note: it is common that parameters start
88 * at argv[1] and not argv[0],
89 * however, our elf loader starts at [0] */
90 for (i = 0; i < prom_argc; i++) {
91 if (match_tag(prom_argv[i], FREQ_TAG)) {
92 idt_cpu_freq = tag2ul(prom_argv[i], FREQ_TAG);
93 continue;
94 }
95#ifdef IGNORE_CMDLINE_MEM
96 /* parses out the "mem=xx" arg */
97 if (match_tag(prom_argv[i], MEM_TAG))
98 continue;
99#endif
100 if (i > 0)
101 *(cp++) = ' ';
102 if (match_tag(prom_argv[i], BOARD_TAG)) {
103 board = prom_argv[i] + strlen(BOARD_TAG);
104
105 if (match_tag(board, BOARD_RB532A))
106 mips_machtype = MACH_MIKROTIK_RB532A;
107 else
108 mips_machtype = MACH_MIKROTIK_RB532;
109 }
110
111 if (match_tag(prom_argv[i], GPIO_TAG))
112 gpio_bootup_state = tag2ul(prom_argv[i], GPIO_TAG);
113
114 strcpy(cp, prom_argv[i]);
115 cp += strlen(prom_argv[i]);
116 }
117 *(cp++) = ' ';
118
119 i = strlen(arcs_cmdline);
120 if (i > 0) {
121 *(cp++) = ' ';
122 strcpy(cp, arcs_cmdline);
123 cp += strlen(arcs_cmdline);
124 }
125 if (gpio_bootup_state & 0x02)
126 strcpy(cp, GPIO_INIT_NOBUTTON);
127 else
128 strcpy(cp, GPIO_INIT_BUTTON);
129
130 cmd_line[CL_SIZE-1] = '\0';
131
132 strcpy(arcs_cmdline, cmd_line);
133}
134
135void __init prom_init(void)
136{
137 struct ddr_ram __iomem *ddr;
138 phys_t memsize;
139 phys_t ddrbase;
140
141 ddr = ioremap_nocache(ddr_reg[0].start,
142 ddr_reg[0].end - ddr_reg[0].start);
143
144 if (!ddr) {
145 printk(KERN_ERR "Unable to remap DDR register\n");
146 return;
147 }
148
149 ddrbase = (phys_t)&ddr->ddrbase;
150 memsize = (phys_t)&ddr->ddrmask;
151 memsize = 0 - memsize;
152
153 prom_setup_cmdline();
154
155 /* give all RAM to boot allocator,
156 * except for the first 0x400 and the last 0x200 bytes */
157 add_memory_region(ddrbase + 0x400, memsize - 0x600, BOOT_MEM_RAM);
158}
diff --git a/arch/mips/rb532/serial.c b/arch/mips/rb532/serial.c
new file mode 100644
index 000000000000..1a05b5ddee09
--- /dev/null
+++ b/arch/mips/rb532/serial.c
@@ -0,0 +1,53 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Serial port initialisation.
4 *
5 * Copyright 2004 IDT Inc. (rischelp@idt.com)
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#include <linux/init.h>
29#include <linux/tty.h>
30#include <linux/serial_core.h>
31#include <linux/serial_8250.h>
32
33#include <asm/serial.h>
34#include <asm/mach-rc32434/rc32434.h>
35
36extern unsigned int idt_cpu_freq;
37
38static struct uart_port rb532_uart = {
39 .type = PORT_16550A,
40 .line = 0,
41 .irq = RC32434_UART0_IRQ,
42 .iotype = UPIO_MEM,
43 .membase = (char *)KSEG1ADDR(RC32434_UART0_BASE),
44 .regshift = 2
45};
46
47int __init setup_serial_port(void)
48{
49 rb532_uart.uartclk = idt_cpu_freq;
50
51 return early_serial_setup(&rb532_uart);
52}
53arch_initcall(setup_serial_port);
diff --git a/arch/mips/rb532/setup.c b/arch/mips/rb532/setup.c
new file mode 100644
index 000000000000..7aafa95ac20b
--- /dev/null
+++ b/arch/mips/rb532/setup.c
@@ -0,0 +1,79 @@
1/*
2 * setup.c - boot time setup code
3 */
4
5#include <linux/init.h>
6
7#include <asm/bootinfo.h>
8#include <asm/reboot.h>
9#include <asm/time.h>
10#include <linux/ioport.h>
11
12#include <asm/mach-rc32434/rc32434.h>
13#include <asm/mach-rc32434/pci.h>
14
15struct pci_reg __iomem *pci_reg;
16EXPORT_SYMBOL(pci_reg);
17
18static struct resource pci0_res[] = {
19 {
20 .name = "pci_reg0",
21 .start = PCI0_BASE_ADDR,
22 .end = PCI0_BASE_ADDR + sizeof(struct pci_reg),
23 .flags = IORESOURCE_MEM,
24 }
25};
26
27static void rb_machine_restart(char *command)
28{
29 /* just jump to the reset vector */
30 writel(0x80000001, (void *)KSEG1ADDR(RC32434_REG_BASE + RC32434_RST));
31 ((void (*)(void)) KSEG1ADDR(0x1FC00000u))();
32}
33
34static void rb_machine_halt(void)
35{
36 for (;;)
37 continue;
38}
39
40void __init plat_mem_setup(void)
41{
42 u32 val;
43
44 _machine_restart = rb_machine_restart;
45 _machine_halt = rb_machine_halt;
46 pm_power_off = rb_machine_halt;
47
48 set_io_port_base(KSEG1);
49
50 pci_reg = ioremap_nocache(pci0_res[0].start,
51 pci0_res[0].end - pci0_res[0].start);
52 if (!pci_reg) {
53 printk(KERN_ERR "Could not remap PCI registers\n");
54 return;
55 }
56
57 val = __raw_readl(&pci_reg->pcic);
58 val &= 0xFFFFFF7;
59 __raw_writel(val, (void *)&pci_reg->pcic);
60
61#ifdef CONFIG_PCI
62 /* Enable PCI interrupts in EPLD Mask register */
63 *epld_mask = 0x0;
64 *(epld_mask + 1) = 0x0;
65#endif
66 write_c0_wired(0);
67}
68
69const char *get_system_type(void)
70{
71 switch (mips_machtype) {
72 case MACH_MIKROTIK_RB532A:
73 return "Mikrotik RB532A";
74 break;
75 default:
76 return "Mikrotik RB532";
77 break;
78 }
79}
diff --git a/arch/mips/rb532/time.c b/arch/mips/rb532/time.c
new file mode 100644
index 000000000000..db74edf8cefb
--- /dev/null
+++ b/arch/mips/rb532/time.c
@@ -0,0 +1,67 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * Setting up the clock on the MIPS boards.
19 */
20
21#include <linux/init.h>
22#include <linux/kernel_stat.h>
23#include <linux/ptrace.h>
24#include <linux/sched.h>
25#include <linux/spinlock.h>
26#include <linux/mc146818rtc.h>
27#include <linux/irq.h>
28#include <linux/timex.h>
29
30#include <asm/mipsregs.h>
31#include <asm/debug.h>
32#include <asm/time.h>
33#include <asm/mach-rc32434/rc32434.h>
34
35extern unsigned int idt_cpu_freq;
36
37/*
38 * Figure out the r4k offset, the amount to increment the compare
39 * register for each time tick. There is no RTC available.
40 *
41 * The RC32434 counts at half the CPU *core* speed.
42 */
43static unsigned long __init cal_r4koff(void)
44{
45 mips_hpt_frequency = idt_cpu_freq * IDT_CLOCK_MULT / 2;
46
47 return mips_hpt_frequency / HZ;
48}
49
50void __init plat_time_init(void)
51{
52 unsigned int est_freq, flags;
53 unsigned long r4k_offset;
54
55 local_irq_save(flags);
56
57 printk(KERN_INFO "calculating r4koff... ");
58 r4k_offset = cal_r4koff();
59 printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
60
61 est_freq = 2 * r4k_offset * HZ;
62 est_freq += 5000; /* round */
63 est_freq -= est_freq % 10000;
64 printk(KERN_INFO "CPU frequency %d.%02d MHz\n", est_freq / 1000000,
65 (est_freq % 1000000) * 100 / 1000000);
66 local_irq_restore(flags);
67}
diff --git a/arch/mips/sgi-ip22/ip22-platform.c b/arch/mips/sgi-ip22/ip22-platform.c
index fc6df96305ed..60141235ec40 100644
--- a/arch/mips/sgi-ip22/ip22-platform.c
+++ b/arch/mips/sgi-ip22/ip22-platform.c
@@ -188,8 +188,7 @@ static int __init sgi_button_devinit(void)
188 if (ip22_is_fullhouse()) 188 if (ip22_is_fullhouse())
189 return 0; /* full house has no volume buttons */ 189 return 0; /* full house has no volume buttons */
190 190
191 return IS_ERR(platform_device_register_simple("sgiindybtns", 191 return IS_ERR(platform_device_register_simple("sgibtns", -1, NULL, 0));
192 -1, NULL, 0));
193} 192}
194 193
195device_initcall(sgi_button_devinit); 194device_initcall(sgi_button_devinit);
diff --git a/arch/mips/sgi-ip22/ip28-berr.c b/arch/mips/sgi-ip22/ip28-berr.c
index fee7a2e0e538..30e12e2ec4b5 100644
--- a/arch/mips/sgi-ip22/ip28-berr.c
+++ b/arch/mips/sgi-ip22/ip28-berr.c
@@ -412,7 +412,7 @@ static int ip28_be_interrupt(const struct pt_regs *regs)
412 * Now we have an asynchronous bus error, speculatively or DMA caused. 412 * Now we have an asynchronous bus error, speculatively or DMA caused.
413 * Need to search all DMA descriptors for the error address. 413 * Need to search all DMA descriptors for the error address.
414 */ 414 */
415 for (i = 0; i < ARRAY_SIZE(hpc3); ++i) { 415 for (i = 0; i < sizeof(hpc3)/sizeof(struct hpc3_stat); ++i) {
416 struct hpc3_stat *hp = (struct hpc3_stat *)&hpc3 + i; 416 struct hpc3_stat *hp = (struct hpc3_stat *)&hpc3 + i;
417 if ((cpu_err_stat & CPU_ERRMASK) && 417 if ((cpu_err_stat & CPU_ERRMASK) &&
418 (cpu_err_addr == hp->ndptr || cpu_err_addr == hp->cbp)) 418 (cpu_err_addr == hp->ndptr || cpu_err_addr == hp->cbp))
@@ -421,7 +421,7 @@ static int ip28_be_interrupt(const struct pt_regs *regs)
421 (gio_err_addr == hp->ndptr || gio_err_addr == hp->cbp)) 421 (gio_err_addr == hp->ndptr || gio_err_addr == hp->cbp))
422 break; 422 break;
423 } 423 }
424 if (i < ARRAY_SIZE(hpc3)) { 424 if (i < sizeof(hpc3)/sizeof(struct hpc3_stat)) {
425 struct hpc3_stat *hp = (struct hpc3_stat *)&hpc3 + i; 425 struct hpc3_stat *hp = (struct hpc3_stat *)&hpc3 + i;
426 printk(KERN_ERR "at DMA addresses: HPC3 @ %08lx:" 426 printk(KERN_ERR "at DMA addresses: HPC3 @ %08lx:"
427 " ctl %08x, ndp %08x, cbp %08x\n", 427 " ctl %08x, ndp %08x, cbp %08x\n",
diff --git a/arch/mips/sgi-ip32/ip32-platform.c b/arch/mips/sgi-ip32/ip32-platform.c
index 2ee401ba0b25..3d63721e0e80 100644
--- a/arch/mips/sgi-ip32/ip32-platform.c
+++ b/arch/mips/sgi-ip32/ip32-platform.c
@@ -85,18 +85,7 @@ device_initcall(sgio2audio_devinit);
85 85
86static __init int sgio2btns_devinit(void) 86static __init int sgio2btns_devinit(void)
87{ 87{
88 struct platform_device *pd; 88 return IS_ERR(platform_device_register_simple("sgibtns", -1, NULL, 0));
89 int ret;
90
91 pd = platform_device_alloc("sgio2btns", -1);
92 if (!pd)
93 return -ENOMEM;
94
95 ret = platform_device_add(pd);
96 if (ret)
97 platform_device_put(pd);
98
99 return ret;
100} 89}
101 90
102device_initcall(sgio2btns_devinit); 91device_initcall(sgio2btns_devinit);
diff --git a/arch/mips/txx9/Kconfig b/arch/mips/txx9/Kconfig
index b92a134ef124..6de4c5aa92be 100644
--- a/arch/mips/txx9/Kconfig
+++ b/arch/mips/txx9/Kconfig
@@ -7,6 +7,8 @@ config TOSHIBA_RBTX4927
7 bool "Toshiba RBTX49[23]7 board" 7 bool "Toshiba RBTX49[23]7 board"
8 depends on MACH_TX49XX 8 depends on MACH_TX49XX
9 select SOC_TX4927 9 select SOC_TX4927
10 # TX4937 is subset of TX4938
11 select SOC_TX4938
10 help 12 help
11 This Toshiba board is based on the TX4927 processor. Say Y here to 13 This Toshiba board is based on the TX4927 processor. Say Y here to
12 support this machine type 14 support this machine type
diff --git a/arch/mips/txx9/generic/Makefile b/arch/mips/txx9/generic/Makefile
index 668fdaad6448..9c120771e65f 100644
--- a/arch/mips/txx9/generic/Makefile
+++ b/arch/mips/txx9/generic/Makefile
@@ -4,8 +4,8 @@
4 4
5obj-y += setup.o 5obj-y += setup.o
6obj-$(CONFIG_PCI) += pci.o 6obj-$(CONFIG_PCI) += pci.o
7obj-$(CONFIG_SOC_TX4927) += mem_tx4927.o irq_tx4927.o 7obj-$(CONFIG_SOC_TX4927) += mem_tx4927.o setup_tx4927.o irq_tx4927.o
8obj-$(CONFIG_SOC_TX4938) += mem_tx4938.o irq_tx4938.o 8obj-$(CONFIG_SOC_TX4938) += mem_tx4927.o setup_tx4938.o irq_tx4938.o
9obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o 9obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o
10obj-$(CONFIG_KGDB) += dbgio.o 10obj-$(CONFIG_KGDB) += dbgio.o
11 11
diff --git a/arch/mips/txx9/generic/irq_tx4927.c b/arch/mips/txx9/generic/irq_tx4927.c
index 6377bd8a9050..cbea1fdde82b 100644
--- a/arch/mips/txx9/generic/irq_tx4927.c
+++ b/arch/mips/txx9/generic/irq_tx4927.c
@@ -31,7 +31,7 @@
31void __init tx4927_irq_init(void) 31void __init tx4927_irq_init(void)
32{ 32{
33 mips_cpu_irq_init(); 33 mips_cpu_irq_init();
34 txx9_irq_init(TX4927_IRC_REG); 34 txx9_irq_init(TX4927_IRC_REG & 0xfffffffffULL);
35 set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4927_IRC_INT, 35 set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4927_IRC_INT,
36 handle_simple_irq); 36 handle_simple_irq);
37} 37}
diff --git a/arch/mips/txx9/generic/irq_tx4938.c b/arch/mips/txx9/generic/irq_tx4938.c
index 5fc86c9c9d2f..6eac684bf190 100644
--- a/arch/mips/txx9/generic/irq_tx4938.c
+++ b/arch/mips/txx9/generic/irq_tx4938.c
@@ -19,7 +19,7 @@
19void __init tx4938_irq_init(void) 19void __init tx4938_irq_init(void)
20{ 20{
21 mips_cpu_irq_init(); 21 mips_cpu_irq_init();
22 txx9_irq_init(TX4938_IRC_REG); 22 txx9_irq_init(TX4938_IRC_REG & 0xfffffffffULL);
23 set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4938_IRC_INT, 23 set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4938_IRC_INT,
24 handle_simple_irq); 24 handle_simple_irq);
25} 25}
diff --git a/arch/mips/txx9/generic/mem_tx4927.c b/arch/mips/txx9/generic/mem_tx4927.c
index 12dfc377bf2f..ef6ea6e97873 100644
--- a/arch/mips/txx9/generic/mem_tx4927.c
+++ b/arch/mips/txx9/generic/mem_tx4927.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/arch/mips/tx4927/common/tx4927_prom.c 2 * linux/arch/mips/txx9/generic/mem_tx4927.c
3 * 3 *
4 * common tx4927 memory interface 4 * common tx4927 memory interface
5 * 5 *
@@ -32,8 +32,9 @@
32#include <linux/init.h> 32#include <linux/init.h>
33#include <linux/types.h> 33#include <linux/types.h>
34#include <linux/io.h> 34#include <linux/io.h>
35#include <asm/txx9/tx4927.h>
35 36
36static unsigned int __init tx4927_process_sdccr(unsigned long addr) 37static unsigned int __init tx4927_process_sdccr(u64 __iomem *addr)
37{ 38{
38 u64 val; 39 u64 val;
39 unsigned int sdccr_ce; 40 unsigned int sdccr_ce;
@@ -45,97 +46,32 @@ static unsigned int __init tx4927_process_sdccr(unsigned long addr)
45 unsigned int rs = 0; 46 unsigned int rs = 0;
46 unsigned int cs = 0; 47 unsigned int cs = 0;
47 unsigned int mw = 0; 48 unsigned int mw = 0;
48 unsigned int msize = 0;
49 49
50 val = __raw_readq((void __iomem *)addr); 50 val = __raw_readq(addr);
51 51
52 /* MVMCP -- need #defs for these bits masks */ 52 /* MVMCP -- need #defs for these bits masks */
53 sdccr_ce = ((val & (1 << 10)) >> 10); 53 sdccr_ce = ((val & (1 << 10)) >> 10);
54 sdccr_bs = ((val & (1 << 8)) >> 8); 54 sdccr_bs = ((val & (1 << 8)) >> 8);
55 sdccr_rs = ((val & (3 << 5)) >> 5); 55 sdccr_rs = ((val & (3 << 5)) >> 5);
56 sdccr_cs = ((val & (3 << 2)) >> 2); 56 sdccr_cs = ((val & (7 << 2)) >> 2);
57 sdccr_mw = ((val & (1 << 0)) >> 0); 57 sdccr_mw = ((val & (1 << 0)) >> 0);
58 58
59 if (sdccr_ce) { 59 if (sdccr_ce) {
60 switch (sdccr_bs) { 60 bs = 2 << sdccr_bs;
61 case 0:{ 61 rs = 2048 << sdccr_rs;
62 bs = 2; 62 cs = 256 << sdccr_cs;
63 break; 63 mw = 8 >> sdccr_mw;
64 }
65 case 1:{
66 bs = 4;
67 break;
68 }
69 }
70 switch (sdccr_rs) {
71 case 0:{
72 rs = 2048;
73 break;
74 }
75 case 1:{
76 rs = 4096;
77 break;
78 }
79 case 2:{
80 rs = 8192;
81 break;
82 }
83 case 3:{
84 rs = 0;
85 break;
86 }
87 }
88 switch (sdccr_cs) {
89 case 0:{
90 cs = 256;
91 break;
92 }
93 case 1:{
94 cs = 512;
95 break;
96 }
97 case 2:{
98 cs = 1024;
99 break;
100 }
101 case 3:{
102 cs = 2048;
103 break;
104 }
105 }
106 switch (sdccr_mw) {
107 case 0:{
108 mw = 8;
109 break;
110 } /* 8 bytes = 64 bits */
111 case 1:{
112 mw = 4;
113 break;
114 } /* 4 bytes = 32 bits */
115 }
116 } 64 }
117 65
118 /* bytes per chip MB per chip num chips */ 66 return rs * cs * mw * bs;
119 msize = (((rs * cs * mw) / (1024 * 1024)) * bs);
120
121 return (msize);
122} 67}
123 68
124
125unsigned int __init tx4927_get_mem_size(void) 69unsigned int __init tx4927_get_mem_size(void)
126{ 70{
127 unsigned int c0; 71 unsigned int total = 0;
128 unsigned int c1; 72 int i;
129 unsigned int c2;
130 unsigned int c3;
131 unsigned int total;
132
133 /* MVMCP -- need #defs for these registers */
134 c0 = tx4927_process_sdccr(0xff1f8000);
135 c1 = tx4927_process_sdccr(0xff1f8008);
136 c2 = tx4927_process_sdccr(0xff1f8010);
137 c3 = tx4927_process_sdccr(0xff1f8018);
138 total = c0 + c1 + c2 + c3;
139 73
140 return (total); 74 for (i = 0; i < ARRAY_SIZE(tx4927_sdramcptr->cr); i++)
75 total += tx4927_process_sdccr(&tx4927_sdramcptr->cr[i]);
76 return total;
141} 77}
diff --git a/arch/mips/txx9/generic/mem_tx4938.c b/arch/mips/txx9/generic/mem_tx4938.c
deleted file mode 100644
index 20baeaeba4cd..000000000000
--- a/arch/mips/txx9/generic/mem_tx4938.c
+++ /dev/null
@@ -1,124 +0,0 @@
1/*
2 * linux/arch/mips/tx4938/common/prom.c
3 *
4 * common tx4938 memory interface
5 * Copyright (C) 2000-2001 Toshiba Corporation
6 *
7 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 *
12 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
13 */
14
15#include <linux/init.h>
16#include <linux/types.h>
17#include <linux/io.h>
18
19static unsigned int __init
20tx4938_process_sdccr(u64 * addr)
21{
22 u64 val;
23 unsigned int sdccr_ce;
24 unsigned int sdccr_rs;
25 unsigned int sdccr_cs;
26 unsigned int sdccr_mw;
27 unsigned int rs = 0;
28 unsigned int cs = 0;
29 unsigned int mw = 0;
30 unsigned int bc = 4;
31 unsigned int msize = 0;
32
33 val = ____raw_readq((void __iomem *)addr);
34
35 /* MVMCP -- need #defs for these bits masks */
36 sdccr_ce = ((val & (1 << 10)) >> 10);
37 sdccr_rs = ((val & (3 << 5)) >> 5);
38 sdccr_cs = ((val & (7 << 2)) >> 2);
39 sdccr_mw = ((val & (1 << 0)) >> 0);
40
41 if (sdccr_ce) {
42 switch (sdccr_rs) {
43 case 0:{
44 rs = 2048;
45 break;
46 }
47 case 1:{
48 rs = 4096;
49 break;
50 }
51 case 2:{
52 rs = 8192;
53 break;
54 }
55 default:{
56 rs = 0;
57 break;
58 }
59 }
60 switch (sdccr_cs) {
61 case 0:{
62 cs = 256;
63 break;
64 }
65 case 1:{
66 cs = 512;
67 break;
68 }
69 case 2:{
70 cs = 1024;
71 break;
72 }
73 case 3:{
74 cs = 2048;
75 break;
76 }
77 case 4:{
78 cs = 4096;
79 break;
80 }
81 default:{
82 cs = 0;
83 break;
84 }
85 }
86 switch (sdccr_mw) {
87 case 0:{
88 mw = 8;
89 break;
90 } /* 8 bytes = 64 bits */
91 case 1:{
92 mw = 4;
93 break;
94 } /* 4 bytes = 32 bits */
95 }
96 }
97
98 /* bytes per chip MB per chip bank count */
99 msize = (((rs * cs * mw) / (1024 * 1024)) * (bc));
100
101 /* MVMCP -- bc hard coded to 4 from table 9.3.1 */
102 /* boad supports bc=2 but no way to detect */
103
104 return (msize);
105}
106
107unsigned int __init
108tx4938_get_mem_size(void)
109{
110 unsigned int c0;
111 unsigned int c1;
112 unsigned int c2;
113 unsigned int c3;
114 unsigned int total;
115
116 /* MVMCP -- need #defs for these registers */
117 c0 = tx4938_process_sdccr((u64 *) 0xff1f8000);
118 c1 = tx4938_process_sdccr((u64 *) 0xff1f8008);
119 c2 = tx4938_process_sdccr((u64 *) 0xff1f8010);
120 c3 = tx4938_process_sdccr((u64 *) 0xff1f8018);
121 total = c0 + c1 + c2 + c3;
122
123 return (total);
124}
diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c
index 5afc5d5cab03..8c60c78b9a9e 100644
--- a/arch/mips/txx9/generic/setup.c
+++ b/arch/mips/txx9/generic/setup.c
@@ -19,7 +19,9 @@
19#include <linux/module.h> 19#include <linux/module.h>
20#include <linux/clk.h> 20#include <linux/clk.h>
21#include <linux/err.h> 21#include <linux/err.h>
22#include <linux/gpio.h>
22#include <asm/bootinfo.h> 23#include <asm/bootinfo.h>
24#include <asm/time.h>
23#include <asm/txx9/generic.h> 25#include <asm/txx9/generic.h>
24#ifdef CONFIG_CPU_TX49XX 26#ifdef CONFIG_CPU_TX49XX
25#include <asm/txx9/tx4938.h> 27#include <asm/txx9/tx4938.h>
@@ -30,6 +32,7 @@ struct resource txx9_ce_res[8];
30static char txx9_ce_res_name[8][4]; /* "CEn" */ 32static char txx9_ce_res_name[8][4]; /* "CEn" */
31 33
32/* pcode, internal register */ 34/* pcode, internal register */
35unsigned int txx9_pcode;
33char txx9_pcode_str[8]; 36char txx9_pcode_str[8];
34static struct resource txx9_reg_res = { 37static struct resource txx9_reg_res = {
35 .name = txx9_pcode_str, 38 .name = txx9_pcode_str,
@@ -59,15 +62,16 @@ unsigned int txx9_master_clock;
59unsigned int txx9_cpu_clock; 62unsigned int txx9_cpu_clock;
60unsigned int txx9_gbus_clock; 63unsigned int txx9_gbus_clock;
61 64
65int txx9_ccfg_toeon __initdata = 1;
62 66
63/* Minimum CLK support */ 67/* Minimum CLK support */
64 68
65struct clk *clk_get(struct device *dev, const char *id) 69struct clk *clk_get(struct device *dev, const char *id)
66{ 70{
67 if (!strcmp(id, "spi-baseclk")) 71 if (!strcmp(id, "spi-baseclk"))
68 return (struct clk *)(txx9_gbus_clock / 2 / 4); 72 return (struct clk *)((unsigned long)txx9_gbus_clock / 2 / 4);
69 if (!strcmp(id, "imbus_clk")) 73 if (!strcmp(id, "imbus_clk"))
70 return (struct clk *)(txx9_gbus_clock / 2); 74 return (struct clk *)((unsigned long)txx9_gbus_clock / 2);
71 return ERR_PTR(-ENOENT); 75 return ERR_PTR(-ENOENT);
72} 76}
73EXPORT_SYMBOL(clk_get); 77EXPORT_SYMBOL(clk_get);
@@ -94,6 +98,22 @@ void clk_put(struct clk *clk)
94} 98}
95EXPORT_SYMBOL(clk_put); 99EXPORT_SYMBOL(clk_put);
96 100
101/* GPIO support */
102
103#ifdef CONFIG_GENERIC_GPIO
104int gpio_to_irq(unsigned gpio)
105{
106 return -EINVAL;
107}
108EXPORT_SYMBOL(gpio_to_irq);
109
110int irq_to_gpio(unsigned irq)
111{
112 return -EINVAL;
113}
114EXPORT_SYMBOL(irq_to_gpio);
115#endif
116
97extern struct txx9_board_vec jmr3927_vec; 117extern struct txx9_board_vec jmr3927_vec;
98extern struct txx9_board_vec rbtx4927_vec; 118extern struct txx9_board_vec rbtx4927_vec;
99extern struct txx9_board_vec rbtx4937_vec; 119extern struct txx9_board_vec rbtx4937_vec;
@@ -107,6 +127,12 @@ void __init prom_init_cmdline(void)
107 int argc = (int)fw_arg0; 127 int argc = (int)fw_arg0;
108 char **argv = (char **)fw_arg1; 128 char **argv = (char **)fw_arg1;
109 int i; /* Always ignore the "-c" at argv[0] */ 129 int i; /* Always ignore the "-c" at argv[0] */
130#ifdef CONFIG_64BIT
131 char *fixed_argv[32];
132 for (i = 0; i < argc; i++)
133 fixed_argv[i] = (char *)(long)(*((__s32 *)argv + i));
134 argv = fixed_argv;
135#endif
110 136
111 /* ignore all built-in args if any f/w args given */ 137 /* ignore all built-in args if any f/w args given */
112 if (argc > 1) 138 if (argc > 1)
@@ -126,15 +152,19 @@ void __init prom_init(void)
126#endif 152#endif
127#ifdef CONFIG_CPU_TX49XX 153#ifdef CONFIG_CPU_TX49XX
128 switch (TX4938_REV_PCODE()) { 154 switch (TX4938_REV_PCODE()) {
155#ifdef CONFIG_TOSHIBA_RBTX4927
129 case 0x4927: 156 case 0x4927:
130 txx9_board_vec = &rbtx4927_vec; 157 txx9_board_vec = &rbtx4927_vec;
131 break; 158 break;
132 case 0x4937: 159 case 0x4937:
133 txx9_board_vec = &rbtx4937_vec; 160 txx9_board_vec = &rbtx4937_vec;
134 break; 161 break;
162#endif
163#ifdef CONFIG_TOSHIBA_RBTX4938
135 case 0x4938: 164 case 0x4938:
136 txx9_board_vec = &rbtx4938_vec; 165 txx9_board_vec = &rbtx4938_vec;
137 break; 166 break;
167#endif
138 } 168 }
139#endif 169#endif
140 170
@@ -160,6 +190,10 @@ char * __init prom_getcmdline(void)
160/* wrappers */ 190/* wrappers */
161void __init plat_mem_setup(void) 191void __init plat_mem_setup(void)
162{ 192{
193 ioport_resource.start = 0;
194 ioport_resource.end = ~0UL; /* no limit */
195 iomem_resource.start = 0;
196 iomem_resource.end = ~0UL; /* no limit */
163 txx9_board_vec->mem_setup(); 197 txx9_board_vec->mem_setup();
164} 198}
165 199
diff --git a/arch/mips/txx9/generic/setup_tx4927.c b/arch/mips/txx9/generic/setup_tx4927.c
new file mode 100644
index 000000000000..89d6e28add93
--- /dev/null
+++ b/arch/mips/txx9/generic/setup_tx4927.c
@@ -0,0 +1,194 @@
1/*
2 * TX4927 setup routines
3 * Based on linux/arch/mips/txx9/rbtx4938/setup.c,
4 * and RBTX49xx patch from CELF patch archive.
5 *
6 * 2003-2005 (c) MontaVista Software, Inc.
7 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13#include <linux/init.h>
14#include <linux/ioport.h>
15#include <linux/delay.h>
16#include <linux/serial_core.h>
17#include <linux/param.h>
18#include <asm/txx9irq.h>
19#include <asm/txx9tmr.h>
20#include <asm/txx9pio.h>
21#include <asm/txx9/generic.h>
22#include <asm/txx9/tx4927.h>
23
24void __init tx4927_wdr_init(void)
25{
26 /* clear WatchDogReset (W1C) */
27 tx4927_ccfg_set(TX4927_CCFG_WDRST);
28 /* do reset on watchdog */
29 tx4927_ccfg_set(TX4927_CCFG_WR);
30}
31
32static struct resource tx4927_sdram_resource[4];
33
34void __init tx4927_setup(void)
35{
36 int i;
37 __u32 divmode;
38 int cpuclk = 0;
39 u64 ccfg;
40
41 txx9_reg_res_init(TX4927_REV_PCODE(), TX4927_REG_BASE,
42 TX4927_REG_SIZE);
43
44 /* SDRAMC,EBUSC are configured by PROM */
45 for (i = 0; i < 8; i++) {
46 if (!(TX4927_EBUSC_CR(i) & 0x8))
47 continue; /* disabled */
48 txx9_ce_res[i].start = (unsigned long)TX4927_EBUSC_BA(i);
49 txx9_ce_res[i].end =
50 txx9_ce_res[i].start + TX4927_EBUSC_SIZE(i) - 1;
51 request_resource(&iomem_resource, &txx9_ce_res[i]);
52 }
53
54 /* clocks */
55 ccfg = ____raw_readq(&tx4927_ccfgptr->ccfg);
56 if (txx9_master_clock) {
57 /* calculate gbus_clock and cpu_clock from master_clock */
58 divmode = (__u32)ccfg & TX4927_CCFG_DIVMODE_MASK;
59 switch (divmode) {
60 case TX4927_CCFG_DIVMODE_8:
61 case TX4927_CCFG_DIVMODE_10:
62 case TX4927_CCFG_DIVMODE_12:
63 case TX4927_CCFG_DIVMODE_16:
64 txx9_gbus_clock = txx9_master_clock * 4; break;
65 default:
66 txx9_gbus_clock = txx9_master_clock;
67 }
68 switch (divmode) {
69 case TX4927_CCFG_DIVMODE_2:
70 case TX4927_CCFG_DIVMODE_8:
71 cpuclk = txx9_gbus_clock * 2; break;
72 case TX4927_CCFG_DIVMODE_2_5:
73 case TX4927_CCFG_DIVMODE_10:
74 cpuclk = txx9_gbus_clock * 5 / 2; break;
75 case TX4927_CCFG_DIVMODE_3:
76 case TX4927_CCFG_DIVMODE_12:
77 cpuclk = txx9_gbus_clock * 3; break;
78 case TX4927_CCFG_DIVMODE_4:
79 case TX4927_CCFG_DIVMODE_16:
80 cpuclk = txx9_gbus_clock * 4; break;
81 }
82 txx9_cpu_clock = cpuclk;
83 } else {
84 if (txx9_cpu_clock == 0)
85 txx9_cpu_clock = 200000000; /* 200MHz */
86 /* calculate gbus_clock and master_clock from cpu_clock */
87 cpuclk = txx9_cpu_clock;
88 divmode = (__u32)ccfg & TX4927_CCFG_DIVMODE_MASK;
89 switch (divmode) {
90 case TX4927_CCFG_DIVMODE_2:
91 case TX4927_CCFG_DIVMODE_8:
92 txx9_gbus_clock = cpuclk / 2; break;
93 case TX4927_CCFG_DIVMODE_2_5:
94 case TX4927_CCFG_DIVMODE_10:
95 txx9_gbus_clock = cpuclk * 2 / 5; break;
96 case TX4927_CCFG_DIVMODE_3:
97 case TX4927_CCFG_DIVMODE_12:
98 txx9_gbus_clock = cpuclk / 3; break;
99 case TX4927_CCFG_DIVMODE_4:
100 case TX4927_CCFG_DIVMODE_16:
101 txx9_gbus_clock = cpuclk / 4; break;
102 }
103 switch (divmode) {
104 case TX4927_CCFG_DIVMODE_8:
105 case TX4927_CCFG_DIVMODE_10:
106 case TX4927_CCFG_DIVMODE_12:
107 case TX4927_CCFG_DIVMODE_16:
108 txx9_master_clock = txx9_gbus_clock / 4; break;
109 default:
110 txx9_master_clock = txx9_gbus_clock;
111 }
112 }
113 /* change default value to udelay/mdelay take reasonable time */
114 loops_per_jiffy = txx9_cpu_clock / HZ / 2;
115
116 /* CCFG */
117 tx4927_wdr_init();
118 /* clear BusErrorOnWrite flag (W1C) */
119 tx4927_ccfg_set(TX4927_CCFG_BEOW);
120 /* enable Timeout BusError */
121 if (txx9_ccfg_toeon)
122 tx4927_ccfg_set(TX4927_CCFG_TOE);
123
124 /* DMA selection */
125 txx9_clear64(&tx4927_ccfgptr->pcfg, TX4927_PCFG_DMASEL_ALL);
126
127 /* Use external clock for external arbiter */
128 if (!(____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCIARB))
129 txx9_clear64(&tx4927_ccfgptr->pcfg, TX4927_PCFG_PCICLKEN_ALL);
130
131 printk(KERN_INFO "%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
132 txx9_pcode_str,
133 (cpuclk + 500000) / 1000000,
134 (txx9_master_clock + 500000) / 1000000,
135 (__u32)____raw_readq(&tx4927_ccfgptr->crir),
136 (unsigned long long)____raw_readq(&tx4927_ccfgptr->ccfg),
137 (unsigned long long)____raw_readq(&tx4927_ccfgptr->pcfg));
138
139 printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str);
140 for (i = 0; i < 4; i++) {
141 __u64 cr = TX4927_SDRAMC_CR(i);
142 unsigned long base, size;
143 if (!((__u32)cr & 0x00000400))
144 continue; /* disabled */
145 base = (unsigned long)(cr >> 49) << 21;
146 size = (((unsigned long)(cr >> 33) & 0x7fff) + 1) << 21;
147 printk(" CR%d:%016llx", i, (unsigned long long)cr);
148 tx4927_sdram_resource[i].name = "SDRAM";
149 tx4927_sdram_resource[i].start = base;
150 tx4927_sdram_resource[i].end = base + size - 1;
151 tx4927_sdram_resource[i].flags = IORESOURCE_MEM;
152 request_resource(&iomem_resource, &tx4927_sdram_resource[i]);
153 }
154 printk(" TR:%09llx\n",
155 (unsigned long long)____raw_readq(&tx4927_sdramcptr->tr));
156
157 /* TMR */
158 /* disable all timers */
159 for (i = 0; i < TX4927_NR_TMR; i++)
160 txx9_tmr_init(TX4927_TMR_REG(i) & 0xfffffffffULL);
161
162 /* PIO */
163 txx9_gpio_init(TX4927_PIO_REG & 0xfffffffffULL, 0, TX4927_NUM_PIO);
164 __raw_writel(0, &tx4927_pioptr->maskcpu);
165 __raw_writel(0, &tx4927_pioptr->maskext);
166}
167
168void __init tx4927_time_init(unsigned int tmrnr)
169{
170 if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_TINTDIS)
171 txx9_clockevent_init(TX4927_TMR_REG(tmrnr) & 0xfffffffffULL,
172 TXX9_IRQ_BASE + TX4927_IR_TMR(tmrnr),
173 TXX9_IMCLK);
174}
175
176void __init tx4927_setup_serial(void)
177{
178#ifdef CONFIG_SERIAL_TXX9
179 int i;
180 struct uart_port req;
181
182 for (i = 0; i < 2; i++) {
183 memset(&req, 0, sizeof(req));
184 req.line = i;
185 req.iotype = UPIO_MEM;
186 req.membase = (unsigned char __iomem *)TX4927_SIO_REG(i);
187 req.mapbase = TX4927_SIO_REG(i) & 0xfffffffffULL;
188 req.irq = TXX9_IRQ_BASE + TX4927_IR_SIO(i);
189 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
190 req.uartclk = TXX9_IMCLK;
191 early_serial_txx9_setup(&req);
192 }
193#endif /* CONFIG_SERIAL_TXX9 */
194}
diff --git a/arch/mips/txx9/generic/setup_tx4938.c b/arch/mips/txx9/generic/setup_tx4938.c
new file mode 100644
index 000000000000..317378d8579d
--- /dev/null
+++ b/arch/mips/txx9/generic/setup_tx4938.c
@@ -0,0 +1,259 @@
1/*
2 * TX4938/4937 setup routines
3 * Based on linux/arch/mips/txx9/rbtx4938/setup.c,
4 * and RBTX49xx patch from CELF patch archive.
5 *
6 * 2003-2005 (c) MontaVista Software, Inc.
7 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13#include <linux/init.h>
14#include <linux/ioport.h>
15#include <linux/delay.h>
16#include <linux/serial_core.h>
17#include <linux/param.h>
18#include <asm/txx9irq.h>
19#include <asm/txx9tmr.h>
20#include <asm/txx9pio.h>
21#include <asm/txx9/generic.h>
22#include <asm/txx9/tx4938.h>
23
24void __init tx4938_wdr_init(void)
25{
26 /* clear WatchDogReset (W1C) */
27 tx4938_ccfg_set(TX4938_CCFG_WDRST);
28 /* do reset on watchdog */
29 tx4938_ccfg_set(TX4938_CCFG_WR);
30}
31
32static struct resource tx4938_sdram_resource[4];
33static struct resource tx4938_sram_resource;
34
35#define TX4938_SRAM_SIZE 0x800
36
37void __init tx4938_setup(void)
38{
39 int i;
40 __u32 divmode;
41 int cpuclk = 0;
42 u64 ccfg;
43
44 txx9_reg_res_init(TX4938_REV_PCODE(), TX4938_REG_BASE,
45 TX4938_REG_SIZE);
46
47 /* SDRAMC,EBUSC are configured by PROM */
48 for (i = 0; i < 8; i++) {
49 if (!(TX4938_EBUSC_CR(i) & 0x8))
50 continue; /* disabled */
51 txx9_ce_res[i].start = (unsigned long)TX4938_EBUSC_BA(i);
52 txx9_ce_res[i].end =
53 txx9_ce_res[i].start + TX4938_EBUSC_SIZE(i) - 1;
54 request_resource(&iomem_resource, &txx9_ce_res[i]);
55 }
56
57 /* clocks */
58 ccfg = ____raw_readq(&tx4938_ccfgptr->ccfg);
59 if (txx9_master_clock) {
60 /* calculate gbus_clock and cpu_clock from master_clock */
61 divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK;
62 switch (divmode) {
63 case TX4938_CCFG_DIVMODE_8:
64 case TX4938_CCFG_DIVMODE_10:
65 case TX4938_CCFG_DIVMODE_12:
66 case TX4938_CCFG_DIVMODE_16:
67 case TX4938_CCFG_DIVMODE_18:
68 txx9_gbus_clock = txx9_master_clock * 4; break;
69 default:
70 txx9_gbus_clock = txx9_master_clock;
71 }
72 switch (divmode) {
73 case TX4938_CCFG_DIVMODE_2:
74 case TX4938_CCFG_DIVMODE_8:
75 cpuclk = txx9_gbus_clock * 2; break;
76 case TX4938_CCFG_DIVMODE_2_5:
77 case TX4938_CCFG_DIVMODE_10:
78 cpuclk = txx9_gbus_clock * 5 / 2; break;
79 case TX4938_CCFG_DIVMODE_3:
80 case TX4938_CCFG_DIVMODE_12:
81 cpuclk = txx9_gbus_clock * 3; break;
82 case TX4938_CCFG_DIVMODE_4:
83 case TX4938_CCFG_DIVMODE_16:
84 cpuclk = txx9_gbus_clock * 4; break;
85 case TX4938_CCFG_DIVMODE_4_5:
86 case TX4938_CCFG_DIVMODE_18:
87 cpuclk = txx9_gbus_clock * 9 / 2; break;
88 }
89 txx9_cpu_clock = cpuclk;
90 } else {
91 if (txx9_cpu_clock == 0)
92 txx9_cpu_clock = 300000000; /* 300MHz */
93 /* calculate gbus_clock and master_clock from cpu_clock */
94 cpuclk = txx9_cpu_clock;
95 divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK;
96 switch (divmode) {
97 case TX4938_CCFG_DIVMODE_2:
98 case TX4938_CCFG_DIVMODE_8:
99 txx9_gbus_clock = cpuclk / 2; break;
100 case TX4938_CCFG_DIVMODE_2_5:
101 case TX4938_CCFG_DIVMODE_10:
102 txx9_gbus_clock = cpuclk * 2 / 5; break;
103 case TX4938_CCFG_DIVMODE_3:
104 case TX4938_CCFG_DIVMODE_12:
105 txx9_gbus_clock = cpuclk / 3; break;
106 case TX4938_CCFG_DIVMODE_4:
107 case TX4938_CCFG_DIVMODE_16:
108 txx9_gbus_clock = cpuclk / 4; break;
109 case TX4938_CCFG_DIVMODE_4_5:
110 case TX4938_CCFG_DIVMODE_18:
111 txx9_gbus_clock = cpuclk * 2 / 9; break;
112 }
113 switch (divmode) {
114 case TX4938_CCFG_DIVMODE_8:
115 case TX4938_CCFG_DIVMODE_10:
116 case TX4938_CCFG_DIVMODE_12:
117 case TX4938_CCFG_DIVMODE_16:
118 case TX4938_CCFG_DIVMODE_18:
119 txx9_master_clock = txx9_gbus_clock / 4; break;
120 default:
121 txx9_master_clock = txx9_gbus_clock;
122 }
123 }
124 /* change default value to udelay/mdelay take reasonable time */
125 loops_per_jiffy = txx9_cpu_clock / HZ / 2;
126
127 /* CCFG */
128 tx4938_wdr_init();
129 /* clear BusErrorOnWrite flag (W1C) */
130 tx4938_ccfg_set(TX4938_CCFG_BEOW);
131 /* enable Timeout BusError */
132 if (txx9_ccfg_toeon)
133 tx4938_ccfg_set(TX4938_CCFG_TOE);
134
135 /* DMA selection */
136 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_DMASEL_ALL);
137
138 /* Use external clock for external arbiter */
139 if (!(____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB))
140 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_PCICLKEN_ALL);
141
142 printk(KERN_INFO "%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
143 txx9_pcode_str,
144 (cpuclk + 500000) / 1000000,
145 (txx9_master_clock + 500000) / 1000000,
146 (__u32)____raw_readq(&tx4938_ccfgptr->crir),
147 (unsigned long long)____raw_readq(&tx4938_ccfgptr->ccfg),
148 (unsigned long long)____raw_readq(&tx4938_ccfgptr->pcfg));
149
150 printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str);
151 for (i = 0; i < 4; i++) {
152 __u64 cr = TX4938_SDRAMC_CR(i);
153 unsigned long base, size;
154 if (!((__u32)cr & 0x00000400))
155 continue; /* disabled */
156 base = (unsigned long)(cr >> 49) << 21;
157 size = (((unsigned long)(cr >> 33) & 0x7fff) + 1) << 21;
158 printk(" CR%d:%016llx", i, (unsigned long long)cr);
159 tx4938_sdram_resource[i].name = "SDRAM";
160 tx4938_sdram_resource[i].start = base;
161 tx4938_sdram_resource[i].end = base + size - 1;
162 tx4938_sdram_resource[i].flags = IORESOURCE_MEM;
163 request_resource(&iomem_resource, &tx4938_sdram_resource[i]);
164 }
165 printk(" TR:%09llx\n",
166 (unsigned long long)____raw_readq(&tx4938_sdramcptr->tr));
167
168 /* SRAM */
169 if (txx9_pcode == 0x4938 && ____raw_readq(&tx4938_sramcptr->cr) & 1) {
170 unsigned int size = TX4938_SRAM_SIZE;
171 tx4938_sram_resource.name = "SRAM";
172 tx4938_sram_resource.start =
173 (____raw_readq(&tx4938_sramcptr->cr) >> (39-11))
174 & ~(size - 1);
175 tx4938_sram_resource.end =
176 tx4938_sram_resource.start + TX4938_SRAM_SIZE - 1;
177 tx4938_sram_resource.flags = IORESOURCE_MEM;
178 request_resource(&iomem_resource, &tx4938_sram_resource);
179 }
180
181 /* TMR */
182 /* disable all timers */
183 for (i = 0; i < TX4938_NR_TMR; i++)
184 txx9_tmr_init(TX4938_TMR_REG(i) & 0xfffffffffULL);
185
186 /* DMA */
187 for (i = 0; i < 2; i++)
188 ____raw_writeq(TX4938_DMA_MCR_MSTEN,
189 (void __iomem *)(TX4938_DMA_REG(i) + 0x50));
190
191 /* PIO */
192 txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, TX4938_NUM_PIO);
193 __raw_writel(0, &tx4938_pioptr->maskcpu);
194 __raw_writel(0, &tx4938_pioptr->maskext);
195
196 if (txx9_pcode == 0x4938) {
197 __u64 pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg);
198 /* set PCIC1 reset */
199 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
200 if (pcfg & (TX4938_PCFG_ETH0_SEL | TX4938_PCFG_ETH1_SEL)) {
201 mdelay(1); /* at least 128 cpu clock */
202 /* clear PCIC1 reset */
203 txx9_clear64(&tx4938_ccfgptr->clkctr,
204 TX4938_CLKCTR_PCIC1RST);
205 } else {
206 printk(KERN_INFO "%s: stop PCIC1\n", txx9_pcode_str);
207 /* stop PCIC1 */
208 txx9_set64(&tx4938_ccfgptr->clkctr,
209 TX4938_CLKCTR_PCIC1CKD);
210 }
211 if (!(pcfg & TX4938_PCFG_ETH0_SEL)) {
212 printk(KERN_INFO "%s: stop ETH0\n", txx9_pcode_str);
213 txx9_set64(&tx4938_ccfgptr->clkctr,
214 TX4938_CLKCTR_ETH0RST);
215 txx9_set64(&tx4938_ccfgptr->clkctr,
216 TX4938_CLKCTR_ETH0CKD);
217 }
218 if (!(pcfg & TX4938_PCFG_ETH1_SEL)) {
219 printk(KERN_INFO "%s: stop ETH1\n", txx9_pcode_str);
220 txx9_set64(&tx4938_ccfgptr->clkctr,
221 TX4938_CLKCTR_ETH1RST);
222 txx9_set64(&tx4938_ccfgptr->clkctr,
223 TX4938_CLKCTR_ETH1CKD);
224 }
225 }
226}
227
228void __init tx4938_time_init(unsigned int tmrnr)
229{
230 if (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_TINTDIS)
231 txx9_clockevent_init(TX4938_TMR_REG(tmrnr) & 0xfffffffffULL,
232 TXX9_IRQ_BASE + TX4938_IR_TMR(tmrnr),
233 TXX9_IMCLK);
234}
235
236void __init tx4938_setup_serial(void)
237{
238#ifdef CONFIG_SERIAL_TXX9
239 int i;
240 struct uart_port req;
241 unsigned int ch_mask = 0;
242
243 if (__raw_readq(&tx4938_ccfgptr->pcfg) & TX4938_PCFG_ETH0_SEL)
244 ch_mask |= 1 << 1; /* disable SIO1 by PCFG setting */
245 for (i = 0; i < 2; i++) {
246 if ((1 << i) & ch_mask)
247 continue;
248 memset(&req, 0, sizeof(req));
249 req.line = i;
250 req.iotype = UPIO_MEM;
251 req.membase = (unsigned char __iomem *)TX4938_SIO_REG(i);
252 req.mapbase = TX4938_SIO_REG(i) & 0xfffffffffULL;
253 req.irq = TXX9_IRQ_BASE + TX4938_IR_SIO(i);
254 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
255 req.uartclk = TXX9_IMCLK;
256 early_serial_txx9_setup(&req);
257 }
258#endif /* CONFIG_SERIAL_TXX9 */
259}
diff --git a/arch/mips/txx9/jmr3927/setup.c b/arch/mips/txx9/jmr3927/setup.c
index 5e35ef73c5a5..03647ebe4130 100644
--- a/arch/mips/txx9/jmr3927/setup.c
+++ b/arch/mips/txx9/jmr3927/setup.c
@@ -105,14 +105,6 @@ static void __init jmr3927_mem_setup(void)
105 _machine_halt = jmr3927_machine_halt; 105 _machine_halt = jmr3927_machine_halt;
106 pm_power_off = jmr3927_machine_power_off; 106 pm_power_off = jmr3927_machine_power_off;
107 107
108 /*
109 * IO/MEM resources.
110 */
111 ioport_resource.start = 0;
112 ioport_resource.end = 0xffffffff;
113 iomem_resource.start = 0;
114 iomem_resource.end = 0xffffffff;
115
116 /* Reboot on panic */ 108 /* Reboot on panic */
117 panic_timeout = 180; 109 panic_timeout = 180;
118 110
diff --git a/arch/mips/txx9/rbtx4927/irq.c b/arch/mips/txx9/rbtx4927/irq.c
index 70f13211bc2a..cd748a930328 100644
--- a/arch/mips/txx9/rbtx4927/irq.c
+++ b/arch/mips/txx9/rbtx4927/irq.c
@@ -126,14 +126,12 @@ static struct irq_chip toshiba_rbtx4927_irq_ioc_type = {
126 .mask_ack = toshiba_rbtx4927_irq_ioc_disable, 126 .mask_ack = toshiba_rbtx4927_irq_ioc_disable,
127 .unmask = toshiba_rbtx4927_irq_ioc_enable, 127 .unmask = toshiba_rbtx4927_irq_ioc_enable,
128}; 128};
129#define TOSHIBA_RBTX4927_IOC_INTR_ENAB (void __iomem *)0xbc002000UL
130#define TOSHIBA_RBTX4927_IOC_INTR_STAT (void __iomem *)0xbc002006UL
131 129
132static int toshiba_rbtx4927_irq_nested(int sw_irq) 130static int toshiba_rbtx4927_irq_nested(int sw_irq)
133{ 131{
134 u8 level3; 132 u8 level3;
135 133
136 level3 = readb(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f; 134 level3 = readb(rbtx4927_imstat_addr) & 0x1f;
137 if (level3) 135 if (level3)
138 sw_irq = RBTX4927_IRQ_IOC + fls(level3) - 1; 136 sw_irq = RBTX4927_IRQ_IOC + fls(level3) - 1;
139 return (sw_irq); 137 return (sw_irq);
@@ -154,18 +152,18 @@ static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq)
154{ 152{
155 unsigned char v; 153 unsigned char v;
156 154
157 v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB); 155 v = readb(rbtx4927_imask_addr);
158 v |= (1 << (irq - RBTX4927_IRQ_IOC)); 156 v |= (1 << (irq - RBTX4927_IRQ_IOC));
159 writeb(v, TOSHIBA_RBTX4927_IOC_INTR_ENAB); 157 writeb(v, rbtx4927_imask_addr);
160} 158}
161 159
162static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq) 160static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq)
163{ 161{
164 unsigned char v; 162 unsigned char v;
165 163
166 v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB); 164 v = readb(rbtx4927_imask_addr);
167 v &= ~(1 << (irq - RBTX4927_IRQ_IOC)); 165 v &= ~(1 << (irq - RBTX4927_IRQ_IOC));
168 writeb(v, TOSHIBA_RBTX4927_IOC_INTR_ENAB); 166 writeb(v, rbtx4927_imask_addr);
169 mmiowb(); 167 mmiowb();
170} 168}
171 169
diff --git a/arch/mips/txx9/rbtx4927/prom.c b/arch/mips/txx9/rbtx4927/prom.c
index 942e627d2dc1..5c0de54ebdd2 100644
--- a/arch/mips/txx9/rbtx4927/prom.c
+++ b/arch/mips/txx9/rbtx4927/prom.c
@@ -36,10 +36,6 @@
36 36
37void __init rbtx4927_prom_init(void) 37void __init rbtx4927_prom_init(void)
38{ 38{
39 extern int tx4927_get_mem_size(void);
40 int msize;
41
42 prom_init_cmdline(); 39 prom_init_cmdline();
43 msize = tx4927_get_mem_size(); 40 add_memory_region(0, tx4927_get_mem_size(), BOOT_MEM_RAM);
44 add_memory_region(0, msize << 20, BOOT_MEM_RAM);
45} 41}
diff --git a/arch/mips/txx9/rbtx4927/setup.c b/arch/mips/txx9/rbtx4927/setup.c
index 1657fd935da8..3da20ea3e55c 100644
--- a/arch/mips/txx9/rbtx4927/setup.c
+++ b/arch/mips/txx9/rbtx4927/setup.c
@@ -53,17 +53,10 @@
53#include <asm/io.h> 53#include <asm/io.h>
54#include <asm/processor.h> 54#include <asm/processor.h>
55#include <asm/reboot.h> 55#include <asm/reboot.h>
56#include <asm/time.h>
57#include <asm/txx9tmr.h>
58#include <asm/txx9/generic.h> 56#include <asm/txx9/generic.h>
59#include <asm/txx9/pci.h> 57#include <asm/txx9/pci.h>
60#include <asm/txx9/rbtx4927.h> 58#include <asm/txx9/rbtx4927.h>
61#include <asm/txx9/tx4938.h> /* for TX4937 */ 59#include <asm/txx9/tx4938.h> /* for TX4937 */
62#ifdef CONFIG_SERIAL_TXX9
63#include <linux/serial_core.h>
64#endif
65
66static int tx4927_ccfg_toeon = 1;
67 60
68#ifdef CONFIG_PCI 61#ifdef CONFIG_PCI
69static void __init tx4927_pci_setup(void) 62static void __init tx4927_pci_setup(void)
@@ -184,14 +177,14 @@ static void toshiba_rbtx4927_restart(char *command)
184 printk(KERN_NOTICE "System Rebooting...\n"); 177 printk(KERN_NOTICE "System Rebooting...\n");
185 178
186 /* enable the s/w reset register */ 179 /* enable the s/w reset register */
187 writeb(RBTX4927_SW_RESET_ENABLE_SET, RBTX4927_SW_RESET_ENABLE); 180 writeb(1, rbtx4927_softresetlock_addr);
188 181
189 /* wait for enable to be seen */ 182 /* wait for enable to be seen */
190 while ((readb(RBTX4927_SW_RESET_ENABLE) & 183 while (!(readb(rbtx4927_softresetlock_addr) & 1))
191 RBTX4927_SW_RESET_ENABLE_SET) == 0x00); 184 ;
192 185
193 /* do a s/w reset */ 186 /* do a s/w reset */
194 writeb(RBTX4927_SW_RESET_DO_SET, RBTX4927_SW_RESET_DO); 187 writeb(1, rbtx4927_softreset_addr);
195 188
196 /* do something passive while waiting for reset */ 189 /* do something passive while waiting for reset */
197 local_irq_disable(); 190 local_irq_disable();
@@ -213,9 +206,11 @@ static void toshiba_rbtx4927_power_off(void)
213 /* no return */ 206 /* no return */
214} 207}
215 208
209static void __init rbtx4927_clock_init(void);
210static void __init rbtx4937_clock_init(void);
211
216static void __init rbtx4927_mem_setup(void) 212static void __init rbtx4927_mem_setup(void)
217{ 213{
218 int i;
219 u32 cp0_config; 214 u32 cp0_config;
220 char *argptr; 215 char *argptr;
221 216
@@ -227,16 +222,18 @@ static void __init rbtx4927_mem_setup(void)
227 cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC); 222 cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC);
228 write_c0_config(cp0_config); 223 write_c0_config(cp0_config);
229 224
230 ioport_resource.end = 0xffffffff; 225 if (TX4927_REV_PCODE() == 0x4927) {
231 iomem_resource.end = 0xffffffff; 226 rbtx4927_clock_init();
227 tx4927_setup();
228 } else {
229 rbtx4937_clock_init();
230 tx4938_setup();
231 }
232 232
233 _machine_restart = toshiba_rbtx4927_restart; 233 _machine_restart = toshiba_rbtx4927_restart;
234 _machine_halt = toshiba_rbtx4927_halt; 234 _machine_halt = toshiba_rbtx4927_halt;
235 pm_power_off = toshiba_rbtx4927_power_off; 235 pm_power_off = toshiba_rbtx4927_power_off;
236 236
237 for (i = 0; i < TX4927_NR_TMR; i++)
238 txx9_tmr_init(TX4927_TMR_REG(0) & 0xfffffffffULL);
239
240#ifdef CONFIG_PCI 237#ifdef CONFIG_PCI
241 txx9_alloc_pci_controller(&txx9_primary_pcic, 238 txx9_alloc_pci_controller(&txx9_primary_pcic,
242 RBTX4927_PCIMEM, RBTX4927_PCIMEM_SIZE, 239 RBTX4927_PCIMEM, RBTX4927_PCIMEM_SIZE,
@@ -245,36 +242,13 @@ static void __init rbtx4927_mem_setup(void)
245 set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET); 242 set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET);
246#endif 243#endif
247 244
248 /* CCFG */ 245 tx4927_setup_serial();
249 /* do reset on watchdog */
250 tx4927_ccfg_set(TX4927_CCFG_WR);
251 /* enable Timeout BusError */
252 if (tx4927_ccfg_toeon)
253 tx4927_ccfg_set(TX4927_CCFG_TOE);
254
255#ifdef CONFIG_SERIAL_TXX9
256 {
257 extern int early_serial_txx9_setup(struct uart_port *port);
258 struct uart_port req;
259 for(i = 0; i < 2; i++) {
260 memset(&req, 0, sizeof(req));
261 req.line = i;
262 req.iotype = UPIO_MEM;
263 req.membase = (char *)(0xff1ff300 + i * 0x100);
264 req.mapbase = 0xff1ff300 + i * 0x100;
265 req.irq = TXX9_IRQ_BASE + TX4927_IR_SIO(i);
266 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
267 req.uartclk = 50000000;
268 early_serial_txx9_setup(&req);
269 }
270 }
271#ifdef CONFIG_SERIAL_TXX9_CONSOLE 246#ifdef CONFIG_SERIAL_TXX9_CONSOLE
272 argptr = prom_getcmdline(); 247 argptr = prom_getcmdline();
273 if (strstr(argptr, "console=") == NULL) { 248 if (strstr(argptr, "console=") == NULL) {
274 strcat(argptr, " console=ttyS0,38400"); 249 strcat(argptr, " console=ttyS0,38400");
275 } 250 }
276#endif 251#endif
277#endif
278 252
279#ifdef CONFIG_ROOT_NFS 253#ifdef CONFIG_ROOT_NFS
280 argptr = prom_getcmdline(); 254 argptr = prom_getcmdline();
@@ -291,19 +265,7 @@ static void __init rbtx4927_mem_setup(void)
291#endif 265#endif
292} 266}
293 267
294static void __init rbtx49x7_common_time_init(void) 268static void __init rbtx4927_clock_init(void)
295{
296 /* change default value to udelay/mdelay take reasonable time */
297 loops_per_jiffy = txx9_cpu_clock / HZ / 2;
298
299 mips_hpt_frequency = txx9_cpu_clock / 2;
300 if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_TINTDIS)
301 txx9_clockevent_init(TX4927_TMR_REG(0) & 0xfffffffffULL,
302 TXX9_IRQ_BASE + 17,
303 50000000);
304}
305
306static void __init rbtx4927_time_init(void)
307{ 269{
308 /* 270 /*
309 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz. 271 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
@@ -325,11 +287,9 @@ static void __init rbtx4927_time_init(void)
325 default: 287 default:
326 txx9_cpu_clock = 200000000; /* 200MHz */ 288 txx9_cpu_clock = 200000000; /* 200MHz */
327 } 289 }
328
329 rbtx49x7_common_time_init();
330} 290}
331 291
332static void __init rbtx4937_time_init(void) 292static void __init rbtx4937_clock_init(void)
333{ 293{
334 /* 294 /*
335 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz. 295 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
@@ -357,15 +317,18 @@ static void __init rbtx4937_time_init(void)
357 default: 317 default:
358 txx9_cpu_clock = 333333333; /* 333MHz */ 318 txx9_cpu_clock = 333333333; /* 333MHz */
359 } 319 }
320}
360 321
361 rbtx49x7_common_time_init(); 322static void __init rbtx4927_time_init(void)
323{
324 tx4927_time_init(0);
362} 325}
363 326
364static int __init toshiba_rbtx4927_rtc_init(void) 327static int __init toshiba_rbtx4927_rtc_init(void)
365{ 328{
366 static struct resource __initdata res = { 329 struct resource res = {
367 .start = 0x1c010000, 330 .start = RBTX4927_BRAMRTC_BASE - IO_BASE,
368 .end = 0x1c010000 + 0x800 - 1, 331 .end = RBTX4927_BRAMRTC_BASE - IO_BASE + 0x800 - 1,
369 .flags = IORESOURCE_MEM, 332 .flags = IORESOURCE_MEM,
370 }; 333 };
371 struct platform_device *dev = 334 struct platform_device *dev =
@@ -375,7 +338,7 @@ static int __init toshiba_rbtx4927_rtc_init(void)
375 338
376static int __init rbtx4927_ne_init(void) 339static int __init rbtx4927_ne_init(void)
377{ 340{
378 static struct resource __initdata res[] = { 341 struct resource res[] = {
379 { 342 {
380 .start = RBTX4927_RTL_8019_BASE, 343 .start = RBTX4927_RTL_8019_BASE,
381 .end = RBTX4927_RTL_8019_BASE + 0x20 - 1, 344 .end = RBTX4927_RTL_8019_BASE + 0x20 - 1,
@@ -434,7 +397,7 @@ struct txx9_board_vec rbtx4937_vec __initdata = {
434 .prom_init = rbtx4927_prom_init, 397 .prom_init = rbtx4927_prom_init,
435 .mem_setup = rbtx4927_mem_setup, 398 .mem_setup = rbtx4927_mem_setup,
436 .irq_setup = rbtx4927_irq_setup, 399 .irq_setup = rbtx4927_irq_setup,
437 .time_init = rbtx4937_time_init, 400 .time_init = rbtx4927_time_init,
438 .device_init = rbtx4927_device_init, 401 .device_init = rbtx4927_device_init,
439 .arch_init = rbtx4937_arch_init, 402 .arch_init = rbtx4937_arch_init,
440#ifdef CONFIG_PCI 403#ifdef CONFIG_PCI
diff --git a/arch/mips/txx9/rbtx4938/prom.c b/arch/mips/txx9/rbtx4938/prom.c
index fbb37458ddb2..ee189519ce5a 100644
--- a/arch/mips/txx9/rbtx4938/prom.c
+++ b/arch/mips/txx9/rbtx4938/prom.c
@@ -18,12 +18,8 @@
18 18
19void __init rbtx4938_prom_init(void) 19void __init rbtx4938_prom_init(void)
20{ 20{
21 extern int tx4938_get_mem_size(void);
22 int msize;
23#ifndef CONFIG_TX4938_NAND_BOOT 21#ifndef CONFIG_TX4938_NAND_BOOT
24 prom_init_cmdline(); 22 prom_init_cmdline();
25#endif 23#endif
26 24 add_memory_region(0, tx4938_get_mem_size(), BOOT_MEM_RAM);
27 msize = tx4938_get_mem_size();
28 add_memory_region(0, msize << 20, BOOT_MEM_RAM);
29} 25}
diff --git a/arch/mips/txx9/rbtx4938/setup.c b/arch/mips/txx9/rbtx4938/setup.c
index aaa987ae0f83..6c2b99bb8af6 100644
--- a/arch/mips/txx9/rbtx4938/setup.c
+++ b/arch/mips/txx9/rbtx4938/setup.c
@@ -20,21 +20,14 @@
20#include <linux/gpio.h> 20#include <linux/gpio.h>
21 21
22#include <asm/reboot.h> 22#include <asm/reboot.h>
23#include <asm/time.h>
24#include <asm/txx9tmr.h>
25#include <asm/io.h> 23#include <asm/io.h>
26#include <asm/txx9/generic.h> 24#include <asm/txx9/generic.h>
27#include <asm/txx9/pci.h> 25#include <asm/txx9/pci.h>
28#include <asm/txx9/rbtx4938.h> 26#include <asm/txx9/rbtx4938.h>
29#ifdef CONFIG_SERIAL_TXX9
30#include <linux/serial_core.h>
31#endif
32#include <linux/spi/spi.h> 27#include <linux/spi/spi.h>
33#include <asm/txx9/spi.h> 28#include <asm/txx9/spi.h>
34#include <asm/txx9pio.h> 29#include <asm/txx9pio.h>
35 30
36static int tx4938_ccfg_toeon = 1;
37
38static void rbtx4938_machine_halt(void) 31static void rbtx4938_machine_halt(void)
39{ 32{
40 printk(KERN_NOTICE "System Halted\n"); 33 printk(KERN_NOTICE "System Halted\n");
@@ -182,188 +175,10 @@ static void __init rbtx4938_spi_setup(void)
182} 175}
183 176
184static struct resource rbtx4938_fpga_resource; 177static struct resource rbtx4938_fpga_resource;
185static struct resource tx4938_sdram_resource[4];
186static struct resource tx4938_sram_resource;
187
188void __init tx4938_board_setup(void)
189{
190 int i;
191 unsigned long divmode;
192 int cpuclk = 0;
193 unsigned long pcode = TX4938_REV_PCODE();
194
195 ioport_resource.start = 0;
196 ioport_resource.end = 0xffffffff;
197 iomem_resource.start = 0;
198 iomem_resource.end = 0xffffffff; /* expand to 4GB */
199
200 txx9_reg_res_init(pcode, TX4938_REG_BASE,
201 TX4938_REG_SIZE);
202 /* SDRAMC,EBUSC are configured by PROM */
203 for (i = 0; i < 8; i++) {
204 if (!(TX4938_EBUSC_CR(i) & 0x8))
205 continue; /* disabled */
206 txx9_ce_res[i].start = (unsigned long)TX4938_EBUSC_BA(i);
207 txx9_ce_res[i].end =
208 txx9_ce_res[i].start + TX4938_EBUSC_SIZE(i) - 1;
209 request_resource(&iomem_resource, &txx9_ce_res[i]);
210 }
211
212 /* clocks */
213 if (txx9_master_clock) {
214 u64 ccfg = ____raw_readq(&tx4938_ccfgptr->ccfg);
215 /* calculate gbus_clock and cpu_clock_freq from master_clock */
216 divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK;
217 switch (divmode) {
218 case TX4938_CCFG_DIVMODE_8:
219 case TX4938_CCFG_DIVMODE_10:
220 case TX4938_CCFG_DIVMODE_12:
221 case TX4938_CCFG_DIVMODE_16:
222 case TX4938_CCFG_DIVMODE_18:
223 txx9_gbus_clock = txx9_master_clock * 4; break;
224 default:
225 txx9_gbus_clock = txx9_master_clock;
226 }
227 switch (divmode) {
228 case TX4938_CCFG_DIVMODE_2:
229 case TX4938_CCFG_DIVMODE_8:
230 cpuclk = txx9_gbus_clock * 2; break;
231 case TX4938_CCFG_DIVMODE_2_5:
232 case TX4938_CCFG_DIVMODE_10:
233 cpuclk = txx9_gbus_clock * 5 / 2; break;
234 case TX4938_CCFG_DIVMODE_3:
235 case TX4938_CCFG_DIVMODE_12:
236 cpuclk = txx9_gbus_clock * 3; break;
237 case TX4938_CCFG_DIVMODE_4:
238 case TX4938_CCFG_DIVMODE_16:
239 cpuclk = txx9_gbus_clock * 4; break;
240 case TX4938_CCFG_DIVMODE_4_5:
241 case TX4938_CCFG_DIVMODE_18:
242 cpuclk = txx9_gbus_clock * 9 / 2; break;
243 }
244 txx9_cpu_clock = cpuclk;
245 } else {
246 u64 ccfg = ____raw_readq(&tx4938_ccfgptr->ccfg);
247 if (txx9_cpu_clock == 0) {
248 txx9_cpu_clock = 300000000; /* 300MHz */
249 }
250 /* calculate gbus_clock and master_clock from cpu_clock_freq */
251 cpuclk = txx9_cpu_clock;
252 divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK;
253 switch (divmode) {
254 case TX4938_CCFG_DIVMODE_2:
255 case TX4938_CCFG_DIVMODE_8:
256 txx9_gbus_clock = cpuclk / 2; break;
257 case TX4938_CCFG_DIVMODE_2_5:
258 case TX4938_CCFG_DIVMODE_10:
259 txx9_gbus_clock = cpuclk * 2 / 5; break;
260 case TX4938_CCFG_DIVMODE_3:
261 case TX4938_CCFG_DIVMODE_12:
262 txx9_gbus_clock = cpuclk / 3; break;
263 case TX4938_CCFG_DIVMODE_4:
264 case TX4938_CCFG_DIVMODE_16:
265 txx9_gbus_clock = cpuclk / 4; break;
266 case TX4938_CCFG_DIVMODE_4_5:
267 case TX4938_CCFG_DIVMODE_18:
268 txx9_gbus_clock = cpuclk * 2 / 9; break;
269 }
270 switch (divmode) {
271 case TX4938_CCFG_DIVMODE_8:
272 case TX4938_CCFG_DIVMODE_10:
273 case TX4938_CCFG_DIVMODE_12:
274 case TX4938_CCFG_DIVMODE_16:
275 case TX4938_CCFG_DIVMODE_18:
276 txx9_master_clock = txx9_gbus_clock / 4; break;
277 default:
278 txx9_master_clock = txx9_gbus_clock;
279 }
280 }
281 /* change default value to udelay/mdelay take reasonable time */
282 loops_per_jiffy = txx9_cpu_clock / HZ / 2;
283
284 /* CCFG */
285 /* clear WatchDogReset,BusErrorOnWrite flag (W1C) */
286 tx4938_ccfg_set(TX4938_CCFG_WDRST | TX4938_CCFG_BEOW);
287 /* do reset on watchdog */
288 tx4938_ccfg_set(TX4938_CCFG_WR);
289 /* clear PCIC1 reset */
290 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
291
292 /* enable Timeout BusError */
293 if (tx4938_ccfg_toeon)
294 tx4938_ccfg_set(TX4938_CCFG_TOE);
295
296 /* DMA selection */
297 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_DMASEL_ALL);
298
299 /* Use external clock for external arbiter */
300 if (!(____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB))
301 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_PCICLKEN_ALL);
302
303 printk(KERN_INFO "%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
304 txx9_pcode_str,
305 (cpuclk + 500000) / 1000000,
306 (txx9_master_clock + 500000) / 1000000,
307 (__u32)____raw_readq(&tx4938_ccfgptr->crir),
308 (unsigned long long)____raw_readq(&tx4938_ccfgptr->ccfg),
309 (unsigned long long)____raw_readq(&tx4938_ccfgptr->pcfg));
310
311 printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str);
312 for (i = 0; i < 4; i++) {
313 unsigned long long cr = tx4938_sdramcptr->cr[i];
314 unsigned long ram_base, ram_size;
315 if (!((unsigned long)cr & 0x00000400))
316 continue; /* disabled */
317 ram_base = (unsigned long)(cr >> 49) << 21;
318 ram_size = ((unsigned long)(cr >> 33) + 1) << 21;
319 if (ram_base >= 0x20000000)
320 continue; /* high memory (ignore) */
321 printk(" CR%d:%016Lx", i, cr);
322 tx4938_sdram_resource[i].name = "SDRAM";
323 tx4938_sdram_resource[i].start = ram_base;
324 tx4938_sdram_resource[i].end = ram_base + ram_size - 1;
325 tx4938_sdram_resource[i].flags = IORESOURCE_MEM;
326 request_resource(&iomem_resource, &tx4938_sdram_resource[i]);
327 }
328 printk(" TR:%09Lx\n", tx4938_sdramcptr->tr);
329
330 /* SRAM */
331 if (tx4938_sramcptr->cr & 1) {
332 unsigned int size = 0x800;
333 unsigned long base =
334 (tx4938_sramcptr->cr >> (39-11)) & ~(size - 1);
335 tx4938_sram_resource.name = "SRAM";
336 tx4938_sram_resource.start = base;
337 tx4938_sram_resource.end = base + size - 1;
338 tx4938_sram_resource.flags = IORESOURCE_MEM;
339 request_resource(&iomem_resource, &tx4938_sram_resource);
340 }
341
342 /* TMR */
343 for (i = 0; i < TX4938_NR_TMR; i++)
344 txx9_tmr_init(TX4938_TMR_REG(i) & 0xfffffffffULL);
345
346 /* enable DMA */
347 for (i = 0; i < 2; i++)
348 ____raw_writeq(TX4938_DMA_MCR_MSTEN,
349 (void __iomem *)(TX4938_DMA_REG(i) + 0x50));
350
351 /* PIO */
352 __raw_writel(0, &tx4938_pioptr->maskcpu);
353 __raw_writel(0, &tx4938_pioptr->maskext);
354
355#ifdef CONFIG_PCI
356 txx9_alloc_pci_controller(&txx9_primary_pcic, 0, 0, 0, 0);
357#endif
358}
359 178
360static void __init rbtx4938_time_init(void) 179static void __init rbtx4938_time_init(void)
361{ 180{
362 mips_hpt_frequency = txx9_cpu_clock / 2; 181 tx4938_time_init(0);
363 if (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_TINTDIS)
364 txx9_clockevent_init(TX4938_TMR_REG(0) & 0xfffffffffULL,
365 TXX9_IRQ_BASE + TX4938_IR_TMR(0),
366 txx9_gbus_clock / 2);
367} 182}
368 183
369static void __init rbtx4938_mem_setup(void) 184static void __init rbtx4938_mem_setup(void)
@@ -371,39 +186,24 @@ static void __init rbtx4938_mem_setup(void)
371 unsigned long long pcfg; 186 unsigned long long pcfg;
372 char *argptr; 187 char *argptr;
373 188
374 iomem_resource.end = 0xffffffff; /* 4GB */
375
376 if (txx9_master_clock == 0) 189 if (txx9_master_clock == 0)
377 txx9_master_clock = 25000000; /* 25MHz */ 190 txx9_master_clock = 25000000; /* 25MHz */
378 tx4938_board_setup(); 191
379#ifndef CONFIG_PCI 192 tx4938_setup();
193
194#ifdef CONFIG_PCI
195 txx9_alloc_pci_controller(&txx9_primary_pcic, 0, 0, 0, 0);
196#else
380 set_io_port_base(RBTX4938_ETHER_BASE); 197 set_io_port_base(RBTX4938_ETHER_BASE);
381#endif 198#endif
382 199
383#ifdef CONFIG_SERIAL_TXX9 200 tx4938_setup_serial();
384 {
385 extern int early_serial_txx9_setup(struct uart_port *port);
386 int i;
387 struct uart_port req;
388 for(i = 0; i < 2; i++) {
389 memset(&req, 0, sizeof(req));
390 req.line = i;
391 req.iotype = UPIO_MEM;
392 req.membase = (char *)(0xff1ff300 + i * 0x100);
393 req.mapbase = 0xff1ff300 + i * 0x100;
394 req.irq = RBTX4938_IRQ_IRC_SIO(i);
395 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
396 req.uartclk = 50000000;
397 early_serial_txx9_setup(&req);
398 }
399 }
400#ifdef CONFIG_SERIAL_TXX9_CONSOLE 201#ifdef CONFIG_SERIAL_TXX9_CONSOLE
401 argptr = prom_getcmdline(); 202 argptr = prom_getcmdline();
402 if (strstr(argptr, "console=") == NULL) { 203 if (strstr(argptr, "console=") == NULL) {
403 strcat(argptr, " console=ttyS0,38400"); 204 strcat(argptr, " console=ttyS0,38400");
404 } 205 }
405#endif 206#endif
406#endif
407 207
408#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61 208#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61
409 printk("PIOSEL: disabling both ata and nand selection\n"); 209 printk("PIOSEL: disabling both ata and nand selection\n");
@@ -457,7 +257,7 @@ static void __init rbtx4938_mem_setup(void)
457 rbtx4938_fpga_resource.start = CPHYSADDR(RBTX4938_FPGA_REG_ADDR); 257 rbtx4938_fpga_resource.start = CPHYSADDR(RBTX4938_FPGA_REG_ADDR);
458 rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff; 258 rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff;
459 rbtx4938_fpga_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY; 259 rbtx4938_fpga_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
460 if (request_resource(&iomem_resource, &rbtx4938_fpga_resource)) 260 if (request_resource(&txx9_ce_res[2], &rbtx4938_fpga_resource))
461 printk("request resource for fpga failed\n"); 261 printk("request resource for fpga failed\n");
462 262
463 _machine_restart = rbtx4938_machine_restart; 263 _machine_restart = rbtx4938_machine_restart;
@@ -488,18 +288,6 @@ static int __init rbtx4938_ne_init(void)
488 return IS_ERR(dev) ? PTR_ERR(dev) : 0; 288 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
489} 289}
490 290
491/* GPIO support */
492
493int gpio_to_irq(unsigned gpio)
494{
495 return -EINVAL;
496}
497
498int irq_to_gpio(unsigned irq)
499{
500 return -EINVAL;
501}
502
503static DEFINE_SPINLOCK(rbtx4938_spi_gpio_lock); 291static DEFINE_SPINLOCK(rbtx4938_spi_gpio_lock);
504 292
505static void rbtx4938_spi_gpio_set(struct gpio_chip *chip, unsigned int offset, 293static void rbtx4938_spi_gpio_set(struct gpio_chip *chip, unsigned int offset,
@@ -579,7 +367,6 @@ static int __init rbtx4938_spi_init(void)
579 367
580static void __init rbtx4938_arch_init(void) 368static void __init rbtx4938_arch_init(void)
581{ 369{
582 txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, 16);
583 gpiochip_add(&rbtx4938_spi_gpio_chip); 370 gpiochip_add(&rbtx4938_spi_gpio_chip);
584 rbtx4938_pci_setup(); 371 rbtx4938_pci_setup();
585 rbtx4938_spi_init(); 372 rbtx4938_spi_init();
diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h
index 9a7274ba6a0b..49df8c4c9d25 100644
--- a/include/asm-mips/bitops.h
+++ b/include/asm-mips/bitops.h
@@ -82,7 +82,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
82 "2: b 1b \n" 82 "2: b 1b \n"
83 " .previous \n" 83 " .previous \n"
84 : "=&r" (temp), "=m" (*m) 84 : "=&r" (temp), "=m" (*m)
85 : "i" (bit), "m" (*m), "r" (~0)); 85 : "ir" (bit), "m" (*m), "r" (~0));
86#endif /* CONFIG_CPU_MIPSR2 */ 86#endif /* CONFIG_CPU_MIPSR2 */
87 } else if (cpu_has_llsc) { 87 } else if (cpu_has_llsc) {
88 __asm__ __volatile__( 88 __asm__ __volatile__(
@@ -147,7 +147,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
147 "2: b 1b \n" 147 "2: b 1b \n"
148 " .previous \n" 148 " .previous \n"
149 : "=&r" (temp), "=m" (*m) 149 : "=&r" (temp), "=m" (*m)
150 : "i" (bit), "m" (*m)); 150 : "ir" (bit), "m" (*m));
151#endif /* CONFIG_CPU_MIPSR2 */ 151#endif /* CONFIG_CPU_MIPSR2 */
152 } else if (cpu_has_llsc) { 152 } else if (cpu_has_llsc) {
153 __asm__ __volatile__( 153 __asm__ __volatile__(
@@ -428,7 +428,7 @@ static inline int test_and_clear_bit(unsigned long nr,
428 "2: b 1b \n" 428 "2: b 1b \n"
429 " .previous \n" 429 " .previous \n"
430 : "=&r" (temp), "=m" (*m), "=&r" (res) 430 : "=&r" (temp), "=m" (*m), "=&r" (res)
431 : "i" (bit), "m" (*m) 431 : "ir" (bit), "m" (*m)
432 : "memory"); 432 : "memory");
433#endif 433#endif
434 } else if (cpu_has_llsc) { 434 } else if (cpu_has_llsc) {
diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h
index d39e143b4a3c..610fe3af7a03 100644
--- a/include/asm-mips/bootinfo.h
+++ b/include/asm-mips/bootinfo.h
@@ -51,6 +51,12 @@
51#define MACH_MSP7120_FPGA 5 /* PMC-Sierra MSP7120 Emulation */ 51#define MACH_MSP7120_FPGA 5 /* PMC-Sierra MSP7120 Emulation */
52#define MACH_MSP_OTHER 255 /* PMC-Sierra unknown board type */ 52#define MACH_MSP_OTHER 255 /* PMC-Sierra unknown board type */
53 53
54/*
55 * Valid machtype for group Mikrotik
56 */
57#define MACH_MIKROTIK_RB532 0 /* Mikrotik RouterBoard 532 */
58#define MACH_MIKROTIK_RB532A 1 /* Mikrotik RouterBoard 532A */
59
54#define CL_SIZE COMMAND_LINE_SIZE 60#define CL_SIZE COMMAND_LINE_SIZE
55 61
56extern char *system_type; 62extern char *system_type;
diff --git a/include/asm-mips/fpu.h b/include/asm-mips/fpu.h
index e59d4c039661..8a3ef247659a 100644
--- a/include/asm-mips/fpu.h
+++ b/include/asm-mips/fpu.h
@@ -35,6 +35,8 @@ extern asmlinkage int (*save_fp_context32)(struct sigcontext32 __user *sc);
35extern asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user *sc); 35extern asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user *sc);
36 36
37extern void fpu_emulator_init_fpu(void); 37extern void fpu_emulator_init_fpu(void);
38extern int fpu_emulator_save_context(struct sigcontext __user *sc);
39extern int fpu_emulator_restore_context(struct sigcontext __user *sc);
38extern void _init_fpu(void); 40extern void _init_fpu(void);
39extern void _save_fp(struct task_struct *); 41extern void _save_fp(struct task_struct *);
40extern void _restore_fp(struct task_struct *); 42extern void _restore_fp(struct task_struct *);
diff --git a/include/asm-mips/mach-rc32434/cpu-feature-overrides.h b/include/asm-mips/mach-rc32434/cpu-feature-overrides.h
new file mode 100644
index 000000000000..f3bc7efa2608
--- /dev/null
+++ b/include/asm-mips/mach-rc32434/cpu-feature-overrides.h
@@ -0,0 +1,81 @@
1/*
2 * IDT RC32434 specific CPU feature overrides
3 *
4 * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
5 *
6 * This file was derived from: include/asm-mips/cpu-features.h
7 * Copyright (C) 2003, 2004 Ralf Baechle
8 * Copyright (C) 2004 Maciej W. Rozycki
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the
22 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
23 * Boston, MA 02110-1301, USA.
24 */
25#ifndef __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H
26#define __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H
27
28/*
29 * The IDT RC32434 SOC has a built-in MIPS 4Kc core.
30 */
31#define cpu_has_tlb 1
32#define cpu_has_4kex 1
33#define cpu_has_3k_cache 0
34#define cpu_has_4k_cache 1
35#define cpu_has_tx39_cache 0
36#define cpu_has_sb1_cache 0
37#define cpu_has_fpu 0
38#define cpu_has_32fpr 0
39#define cpu_has_counter 1
40#define cpu_has_watch 1
41#define cpu_has_divec 1
42#define cpu_has_vce 0
43#define cpu_has_cache_cdex_p 0
44#define cpu_has_cache_cdex_s 0
45#define cpu_has_prefetch 1
46#define cpu_has_mcheck 1
47#define cpu_has_ejtag 1
48#define cpu_has_llsc 1
49
50#define cpu_has_mips16 0
51#define cpu_has_mdmx 0
52#define cpu_has_mips3d 0
53#define cpu_has_smartmips 0
54
55#define cpu_has_vtag_icache 0
56/* #define cpu_has_dc_aliases ? */
57/* #define cpu_has_ic_fills_f_dc ? */
58/* #define cpu_has_pindexed_dcache ? */
59
60/* #define cpu_icache_snoops_remote_store ? */
61
62#define cpu_has_mips32r1 1
63#define cpu_has_mips32r2 0
64#define cpu_has_mips64r1 0
65#define cpu_has_mips64r2 0
66
67#define cpu_has_dsp 0
68#define cpu_has_mipsmt 0
69
70/* #define cpu_has_nofpuex ? */
71#define cpu_has_64bits 0
72#define cpu_has_64bit_zero_reg 0
73#define cpu_has_64bit_gp_regs 0
74#define cpu_has_64bit_addresses 0
75
76#define cpu_has_inclusive_pcaches 0
77
78#define cpu_dcache_line_size() 16
79#define cpu_icache_line_size() 16
80
81#endif /* __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-rc32434/ddr.h b/include/asm-mips/mach-rc32434/ddr.h
new file mode 100644
index 000000000000..291e2cf9dde0
--- /dev/null
+++ b/include/asm-mips/mach-rc32434/ddr.h
@@ -0,0 +1,141 @@
1/*
2 * Definitions for the DDR registers
3 *
4 * Copyright 2002 Ryan Holm <ryan.holmQVist@idt.com>
5 * Copyright 2008 Florian Fainelli <florian@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 *
27 */
28
29#ifndef _ASM_RC32434_DDR_H_
30#define _ASM_RC32434_DDR_H_
31
32#include <asm/mach-rc32434/rb.h>
33
34/* DDR register structure */
35struct ddr_ram {
36 u32 ddrbase;
37 u32 ddrmask;
38 u32 res1;
39 u32 res2;
40 u32 ddrc;
41 u32 ddrabase;
42 u32 ddramask;
43 u32 ddramap;
44 u32 ddrcust;
45 u32 ddrrdc;
46 u32 ddrspare;
47};
48
49#define DDR0_PHYS_ADDR 0x18018000
50
51/* DDR banks masks */
52#define DDR_MASK 0xffff0000
53#define DDR0_BASE_MSK DDR_MASK
54#define DDR1_BASE_MSK DDR_MASK
55
56/* DDR bank0 registers */
57#define RC32434_DDR0_ATA_BIT 5
58#define RC32434_DDR0_ATA_MSK 0x000000E0
59#define RC32434_DDR0_DBW_BIT 8
60#define RC32434_DDR0_DBW_MSK 0x00000100
61#define RC32434_DDR0_WR_BIT 9
62#define RC32434_DDR0_WR_MSK 0x00000600
63#define RC32434_DDR0_PS_BIT 11
64#define RC32434_DDR0_PS_MSK 0x00001800
65#define RC32434_DDR0_DTYPE_BIT 13
66#define RC32434_DDR0_DTYPE_MSK 0x0000e000
67#define RC32434_DDR0_RFC_BIT 16
68#define RC32434_DDR0_RFC_MSK 0x000f0000
69#define RC32434_DDR0_RP_BIT 20
70#define RC32434_DDR0_RP_MSK 0x00300000
71#define RC32434_DDR0_AP_BIT 22
72#define RC32434_DDR0_AP_MSK 0x00400000
73#define RC32434_DDR0_RCD_BIT 23
74#define RC32434_DDR0_RCD_MSK 0x01800000
75#define RC32434_DDR0_CL_BIT 25
76#define RC32434_DDR0_CL_MSK 0x06000000
77#define RC32434_DDR0_DBM_BIT 27
78#define RC32434_DDR0_DBM_MSK 0x08000000
79#define RC32434_DDR0_SDS_BIT 28
80#define RC32434_DDR0_SDS_MSK 0x10000000
81#define RC32434_DDR0_ATP_BIT 29
82#define RC32434_DDR0_ATP_MSK 0x60000000
83#define RC32434_DDR0_RE_BIT 31
84#define RC32434_DDR0_RE_MSK 0x80000000
85
86/* DDR bank C registers */
87#define RC32434_DDRC_MSK(x) BIT_TO_MASK(x)
88#define RC32434_DDRC_CES_BIT 0
89#define RC32434_DDRC_ACE_BIT 1
90
91/* Custom DDR bank registers */
92#define RC32434_DCST_MSK(x) BIT_TO_MASK(x)
93#define RC32434_DCST_CS_BIT 0
94#define RC32434_DCST_CS_MSK 0x00000003
95#define RC32434_DCST_WE_BIT 2
96#define RC32434_DCST_RAS_BIT 3
97#define RC32434_DCST_CAS_BIT 4
98#define RC32434_DSCT_CKE_BIT 5
99#define RC32434_DSCT_BA_BIT 6
100#define RC32434_DSCT_BA_MSK 0x000000c0
101
102/* DDR QSC registers */
103#define RC32434_QSC_DM_BIT 0
104#define RC32434_QSC_DM_MSK 0x00000003
105#define RC32434_QSC_DQSBS_BIT 2
106#define RC32434_QSC_DQSBS_MSK 0x000000fc
107#define RC32434_QSC_DB_BIT 8
108#define RC32434_QSC_DB_MSK 0x00000100
109#define RC32434_QSC_DBSP_BIT 9
110#define RC32434_QSC_DBSP_MSK 0x01fffe00
111#define RC32434_QSC_BDP_BIT 25
112#define RC32434_QSC_BDP_MSK 0x7e000000
113
114/* DDR LLC registers */
115#define RC32434_LLC_EAO_BIT 0
116#define RC32434_LLC_EAO_MSK 0x00000001
117#define RC32434_LLC_EO_BIT 1
118#define RC32434_LLC_EO_MSK 0x0000003e
119#define RC32434_LLC_FS_BIT 6
120#define RC32434_LLC_FS_MSK 0x000000c0
121#define RC32434_LLC_AS_BIT 8
122#define RC32434_LLC_AS_MSK 0x00000700
123#define RC32434_LLC_SP_BIT 11
124#define RC32434_LLC_SP_MSK 0x001ff800
125
126/* DDR LLFC registers */
127#define RC32434_LLFC_MSK(x) BIT_TO_MASK(x)
128#define RC32434_LLFC_MEN_BIT 0
129#define RC32434_LLFC_EAN_BIT 1
130#define RC32434_LLFC_FF_BIT 2
131
132/* DDR DLLTA registers */
133#define RC32434_DLLTA_ADDR_BIT 2
134#define RC32434_DLLTA_ADDR_MSK 0xfffffffc
135
136/* DDR DLLED registers */
137#define RC32434_DLLED_MSK(x) BIT_TO_MASK(x)
138#define RC32434_DLLED_DBE_BIT 0
139#define RC32434_DLLED_DTE_BIT 1
140
141#endif /* _ASM_RC32434_DDR_H_ */
diff --git a/include/asm-mips/mach-rc32434/dma.h b/include/asm-mips/mach-rc32434/dma.h
new file mode 100644
index 000000000000..5f898b5873f7
--- /dev/null
+++ b/include/asm-mips/mach-rc32434/dma.h
@@ -0,0 +1,103 @@
1/*
2 * Copyright 2002 Integrated Device Technology, Inc.
3 * All rights reserved.
4 *
5 * DMA register definition.
6 *
7 * Author : ryan.holmQVist@idt.com
8 * Date : 20011005
9 */
10
11#ifndef __ASM_RC32434_DMA_H
12#define __ASM_RC32434_DMA_H
13
14#include <asm/mach-rc32434/rb.h>
15
16#define DMA0_BASE_ADDR 0x18040000
17
18/*
19 * DMA descriptor (in physical memory).
20 */
21
22struct dma_desc {
23 u32 control; /* Control. use DMAD_* */
24 u32 ca; /* Current Address. */
25 u32 devcs; /* Device control and status. */
26 u32 link; /* Next descriptor in chain. */
27};
28
29#define DMA_DESC_SIZ sizeof(struct dma_desc)
30#define DMA_DESC_COUNT_BIT 0
31#define DMA_DESC_COUNT_MSK 0x0003ffff
32#define DMA_DESC_DS_BIT 20
33#define DMA_DESC_DS_MSK 0x00300000
34
35#define DMA_DESC_DEV_CMD_BIT 22
36#define DMA_DESC_DEV_CMD_MSK 0x01c00000
37
38/* DMA command sizes */
39#define DMA_DESC_DEV_CMD_BYTE 0
40#define DMA_DESC_DEV_CMD_HLF_WD 1
41#define DMA_DESC_DEV_CMD_WORD 2
42#define DMA_DESC_DEV_CMD_2WORDS 3
43#define DMA_DESC_DEV_CMD_4WORDS 4
44#define DMA_DESC_DEV_CMD_6WORDS 5
45#define DMA_DESC_DEV_CMD_8WORDS 6
46#define DMA_DESC_DEV_CMD_16WORDS 7
47
48/* DMA descriptors interrupts */
49#define DMA_DESC_COF (1 << 25) /* Chain on finished */
50#define DMA_DESC_COD (1 << 26) /* Chain on done */
51#define DMA_DESC_IOF (1 << 27) /* Interrupt on finished */
52#define DMA_DESC_IOD (1 << 28) /* Interrupt on done */
53#define DMA_DESC_TERM (1 << 29) /* Terminated */
54#define DMA_DESC_DONE (1 << 30) /* Done */
55#define DMA_DESC_FINI (1 << 31) /* Finished */
56
57/*
58 * DMA register (within Internal Register Map).
59 */
60
61struct dma_reg {
62 u32 dmac; /* Control. */
63 u32 dmas; /* Status. */
64 u32 dmasm; /* Mask. */
65 u32 dmadptr; /* Descriptor pointer. */
66 u32 dmandptr; /* Next descriptor pointer. */
67};
68
69/* DMA channels specific registers */
70#define DMA_CHAN_RUN_BIT (1 << 0)
71#define DMA_CHAN_DONE_BIT (1 << 1)
72#define DMA_CHAN_MODE_BIT (1 << 2)
73#define DMA_CHAN_MODE_MSK 0x0000000c
74#define DMA_CHAN_MODE_AUTO 0
75#define DMA_CHAN_MODE_BURST 1
76#define DMA_CHAN_MODE_XFRT 2
77#define DMA_CHAN_MODE_RSVD 3
78#define DMA_CHAN_ACT_BIT (1 << 4)
79
80/* DMA status registers */
81#define DMA_STAT_FINI (1 << 0)
82#define DMA_STAT_DONE (1 << 1)
83#define DMA_STAT_CHAIN (1 << 2)
84#define DMA_STAT_ERR (1 << 3)
85#define DMA_STAT_HALT (1 << 4)
86
87/*
88 * DMA channel definitions
89 */
90
91#define DMA_CHAN_ETH_RCV 0
92#define DMA_CHAN_ETH_XMT 1
93#define DMA_CHAN_MEM_TO_FIFO 2
94#define DMA_CHAN_FIFO_TO_MEM 3
95#define DMA_CHAN_PCI_TO_MEM 4
96#define DMA_CHAN_MEM_TO_PCI 5
97#define DMA_CHAN_COUNT 6
98
99struct dma_channel {
100 struct dma_reg ch[DMA_CHAN_COUNT];
101};
102
103#endif /* __ASM_RC32434_DMA_H */
diff --git a/include/asm-mips/mach-rc32434/dma_v.h b/include/asm-mips/mach-rc32434/dma_v.h
new file mode 100644
index 000000000000..173a9f9146cd
--- /dev/null
+++ b/include/asm-mips/mach-rc32434/dma_v.h
@@ -0,0 +1,52 @@
1/*
2 * Copyright 2002 Integrated Device Technology, Inc.
3 * All rights reserved.
4 *
5 * DMA register definition.
6 *
7 * Author : ryan.holmQVist@idt.com
8 * Date : 20011005
9 */
10
11#ifndef _ASM_RC32434_DMA_V_H_
12#define _ASM_RC32434_DMA_V_H_
13
14#include <asm/mach-rc32434/dma.h>
15#include <asm/mach-rc32434/rc32434.h>
16
17#define DMA_CHAN_OFFSET 0x14
18#define IS_DMA_USED(X) (((X) & \
19 (DMA_DESC_FINI | DMA_DESC_DONE | DMA_DESC_TERM)) \
20 != 0)
21#define DMA_COUNT(count) ((count) & DMA_DESC_COUNT_MSK)
22
23#define DMA_HALT_TIMEOUT 500
24
25static inline int rc32434_halt_dma(struct dma_reg *ch)
26{
27 int timeout = 1;
28 if (__raw_readl(&ch->dmac) & DMA_CHAN_RUN_BIT) {
29 __raw_writel(0, &ch->dmac);
30 for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
31 if (__raw_readl(&ch->dmas) & DMA_STAT_HALT) {
32 __raw_writel(0, &ch->dmas);
33 break;
34 }
35 }
36 }
37
38 return timeout ? 0 : 1;
39}
40
41static inline void rc32434_start_dma(struct dma_reg *ch, u32 dma_addr)
42{
43 __raw_writel(0, &ch->dmandptr);
44 __raw_writel(dma_addr, &ch->dmadptr);
45}
46
47static inline void rc32434_chain_dma(struct dma_reg *ch, u32 dma_addr)
48{
49 __raw_writel(dma_addr, &ch->dmandptr);
50}
51
52#endif /* _ASM_RC32434_DMA_V_H_ */
diff --git a/include/asm-mips/mach-rc32434/eth.h b/include/asm-mips/mach-rc32434/eth.h
new file mode 100644
index 000000000000..a25cbc56173d
--- /dev/null
+++ b/include/asm-mips/mach-rc32434/eth.h
@@ -0,0 +1,220 @@
1/*
2 * Definitions for the Ethernet registers
3 *
4 * Copyright 2002 Allend Stichter <allen.stichter@idt.com>
5 * Copyright 2008 Florian Fainelli <florian@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 *
27 */
28
29#ifndef __ASM_RC32434_ETH_H
30#define __ASM_RC32434_ETH_H
31
32
33#define ETH0_BASE_ADDR 0x18060000
34
35struct eth_regs {
36 u32 ethintfc;
37 u32 ethfifott;
38 u32 etharc;
39 u32 ethhash0;
40 u32 ethhash1;
41 u32 ethu0[4]; /* Reserved. */
42 u32 ethpfs;
43 u32 ethmcp;
44 u32 eth_u1[10]; /* Reserved. */
45 u32 ethspare;
46 u32 eth_u2[42]; /* Reserved. */
47 u32 ethsal0;
48 u32 ethsah0;
49 u32 ethsal1;
50 u32 ethsah1;
51 u32 ethsal2;
52 u32 ethsah2;
53 u32 ethsal3;
54 u32 ethsah3;
55 u32 ethrbc;
56 u32 ethrpc;
57 u32 ethrupc;
58 u32 ethrfc;
59 u32 ethtbc;
60 u32 ethgpf;
61 u32 eth_u9[50]; /* Reserved. */
62 u32 ethmac1;
63 u32 ethmac2;
64 u32 ethipgt;
65 u32 ethipgr;
66 u32 ethclrt;
67 u32 ethmaxf;
68 u32 eth_u10; /* Reserved. */
69 u32 ethmtest;
70 u32 miimcfg;
71 u32 miimcmd;
72 u32 miimaddr;
73 u32 miimwtd;
74 u32 miimrdd;
75 u32 miimind;
76 u32 eth_u11; /* Reserved. */
77 u32 eth_u12; /* Reserved. */
78 u32 ethcfsa0;
79 u32 ethcfsa1;
80 u32 ethcfsa2;
81};
82
83/* Ethernet interrupt registers */
84#define ETH_INT_FC_EN (1 << 0)
85#define ETH_INT_FC_ITS (1 << 1)
86#define ETH_INT_FC_RIP (1 << 2)
87#define ETH_INT_FC_JAM (1 << 3)
88#define ETH_INT_FC_OVR (1 << 4)
89#define ETH_INT_FC_UND (1 << 5)
90#define ETH_INT_FC_IOC 0x000000c0
91
92/* Ethernet FIFO registers */
93#define ETH_FIFI_TT_TTH_BIT 0
94#define ETH_FIFO_TT_TTH 0x0000007f
95
96/* Ethernet ARC/multicast registers */
97#define ETH_ARC_PRO (1 << 0)
98#define ETH_ARC_AM (1 << 1)
99#define ETH_ARC_AFM (1 << 2)
100#define ETH_ARC_AB (1 << 3)
101
102/* Ethernet SAL registers */
103#define ETH_SAL_BYTE_5 0x000000ff
104#define ETH_SAL_BYTE_4 0x0000ff00
105#define ETH_SAL_BYTE_3 0x00ff0000
106#define ETH_SAL_BYTE_2 0xff000000
107
108/* Ethernet SAH registers */
109#define ETH_SAH_BYTE1 0x000000ff
110#define ETH_SAH_BYTE0 0x0000ff00
111
112/* Ethernet GPF register */
113#define ETH_GPF_PTV 0x0000ffff
114
115/* Ethernet PFG register */
116#define ETH_PFS_PFD (1 << 0)
117
118/* Ethernet CFSA[0-3] registers */
119#define ETH_CFSA0_CFSA4 0x000000ff
120#define ETH_CFSA0_CFSA5 0x0000ff00
121#define ETH_CFSA1_CFSA2 0x000000ff
122#define ETH_CFSA1_CFSA3 0x0000ff00
123#define ETH_CFSA1_CFSA0 0x000000ff
124#define ETH_CFSA1_CFSA1 0x0000ff00
125
126/* Ethernet MAC1 registers */
127#define ETH_MAC1_RE (1 << 0)
128#define ETH_MAC1_PAF (1 << 1)
129#define ETH_MAC1_RFC (1 << 2)
130#define ETH_MAC1_TFC (1 << 3)
131#define ETH_MAC1_LB (1 << 4)
132#define ETH_MAC1_MR (1 << 31)
133
134/* Ethernet MAC2 registers */
135#define ETH_MAC2_FD (1 << 0)
136#define ETH_MAC2_FLC (1 << 1)
137#define ETH_MAC2_HFE (1 << 2)
138#define ETH_MAC2_DC (1 << 3)
139#define ETH_MAC2_CEN (1 << 4)
140#define ETH_MAC2_PE (1 << 5)
141#define ETH_MAC2_VPE (1 << 6)
142#define ETH_MAC2_APE (1 << 7)
143#define ETH_MAC2_PPE (1 << 8)
144#define ETH_MAC2_LPE (1 << 9)
145#define ETH_MAC2_NB (1 << 12)
146#define ETH_MAC2_BP (1 << 13)
147#define ETH_MAC2_ED (1 << 14)
148
149/* Ethernet IPGT register */
150#define ETH_IPGT 0x0000007f
151
152/* Ethernet IPGR registers */
153#define ETH_IPGR_IPGR2 0x0000007f
154#define ETH_IPGR_IPGR1 0x00007f00
155
156/* Ethernet CLRT registers */
157#define ETH_CLRT_MAX_RET 0x0000000f
158#define ETH_CLRT_COL_WIN 0x00003f00
159
160/* Ethernet MAXF register */
161#define ETH_MAXF 0x0000ffff
162
163/* Ethernet test registers */
164#define ETH_TEST_REG (1 << 2)
165#define ETH_MCP_DIV 0x000000ff
166
167/* MII registers */
168#define ETH_MII_CFG_RSVD 0x0000000c
169#define ETH_MII_CMD_RD (1 << 0)
170#define ETH_MII_CMD_SCN (1 << 1)
171#define ETH_MII_REG_ADDR 0x0000001f
172#define ETH_MII_PHY_ADDR 0x00001f00
173#define ETH_MII_WTD_DATA 0x0000ffff
174#define ETH_MII_RDD_DATA 0x0000ffff
175#define ETH_MII_IND_BSY (1 << 0)
176#define ETH_MII_IND_SCN (1 << 1)
177#define ETH_MII_IND_NV (1 << 2)
178
179/*
180 * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
181 */
182
183#define ETH_RX_FD (1 << 0)
184#define ETH_RX_LD (1 << 1)
185#define ETH_RX_ROK (1 << 2)
186#define ETH_RX_FM (1 << 3)
187#define ETH_RX_MP (1 << 4)
188#define ETH_RX_BP (1 << 5)
189#define ETH_RX_VLT (1 << 6)
190#define ETH_RX_CF (1 << 7)
191#define ETH_RX_OVR (1 << 8)
192#define ETH_RX_CRC (1 << 9)
193#define ETH_RX_CV (1 << 10)
194#define ETH_RX_DB (1 << 11)
195#define ETH_RX_LE (1 << 12)
196#define ETH_RX_LOR (1 << 13)
197#define ETH_RX_CES (1 << 14)
198#define ETH_RX_LEN_BIT 16
199#define ETH_RX_LEN 0xffff0000
200
201#define ETH_TX_FD (1 << 0)
202#define ETH_TX_LD (1 << 1)
203#define ETH_TX_OEN (1 << 2)
204#define ETH_TX_PEN (1 << 3)
205#define ETH_TX_CEN (1 << 4)
206#define ETH_TX_HEN (1 << 5)
207#define ETH_TX_TOK (1 << 6)
208#define ETH_TX_MP (1 << 7)
209#define ETH_TX_BP (1 << 8)
210#define ETH_TX_UND (1 << 9)
211#define ETH_TX_OF (1 << 10)
212#define ETH_TX_ED (1 << 11)
213#define ETH_TX_EC (1 << 12)
214#define ETH_TX_LC (1 << 13)
215#define ETH_TX_TD (1 << 14)
216#define ETH_TX_CRC (1 << 15)
217#define ETH_TX_LE (1 << 16)
218#define ETH_TX_CC 0x001E0000
219
220#endif /* __ASM_RC32434_ETH_H */
diff --git a/include/asm-mips/mach-rc32434/gpio.h b/include/asm-mips/mach-rc32434/gpio.h
new file mode 100644
index 000000000000..f946f5f45bbb
--- /dev/null
+++ b/include/asm-mips/mach-rc32434/gpio.h
@@ -0,0 +1,126 @@
1/*
2 * Copyright 2002 Integrated Device Technology, Inc.
3 * All rights reserved.
4 *
5 * GPIO register definition.
6 *
7 * Author : ryan.holmQVist@idt.com
8 * Date : 20011005
9 * Copyright (C) 2001, 2002 Ryan Holm <ryan.holmQVist@idt.com>
10 * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
11 */
12
13#ifndef _RC32434_GPIO_H_
14#define _RC32434_GPIO_H_
15
16#include <linux/types.h>
17
18struct rb532_gpio_reg {
19 u32 gpiofunc; /* GPIO Function Register
20 * gpiofunc[x]==0 bit = gpio
21 * func[x]==1 bit = altfunc
22 */
23 u32 gpiocfg; /* GPIO Configuration Register
24 * gpiocfg[x]==0 bit = input
25 * gpiocfg[x]==1 bit = output
26 */
27 u32 gpiod; /* GPIO Data Register
28 * gpiod[x] read/write gpio pinX status
29 */
30 u32 gpioilevel; /* GPIO Interrupt Status Register
31 * interrupt level (see gpioistat)
32 */
33 u32 gpioistat; /* Gpio Interrupt Status Register
34 * istat[x] = (gpiod[x] == level[x])
35 * cleared in ISR (STICKY bits)
36 */
37 u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
38};
39
40/* UART GPIO signals */
41#define RC32434_UART0_SOUT (1 << 0)
42#define RC32434_UART0_SIN (1 << 1)
43#define RC32434_UART0_RTS (1 << 2)
44#define RC32434_UART0_CTS (1 << 3)
45
46/* M & P bus GPIO signals */
47#define RC32434_MP_BIT_22 (1 << 4)
48#define RC32434_MP_BIT_23 (1 << 5)
49#define RC32434_MP_BIT_24 (1 << 6)
50#define RC32434_MP_BIT_25 (1 << 7)
51
52/* CPU GPIO signals */
53#define RC32434_CPU_GPIO (1 << 8)
54
55/* Reserved GPIO signals */
56#define RC32434_AF_SPARE_6 (1 << 9)
57#define RC32434_AF_SPARE_4 (1 << 10)
58#define RC32434_AF_SPARE_3 (1 << 11)
59#define RC32434_AF_SPARE_2 (1 << 12)
60
61/* PCI messaging unit */
62#define RC32434_PCI_MSU_GPIO (1 << 13)
63
64
65extern void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val);
66extern unsigned get_434_reg(unsigned reg_offs);
67extern void set_latch_u5(unsigned char or_mask, unsigned char nand_mask);
68extern unsigned char get_latch_u5(void);
69
70extern int rb532_gpio_get_value(unsigned gpio);
71extern void rb532_gpio_set_value(unsigned gpio, int value);
72extern int rb532_gpio_direction_input(unsigned gpio);
73extern int rb532_gpio_direction_output(unsigned gpio, int value);
74extern void rb532_gpio_set_int_level(unsigned gpio, int value);
75extern int rb532_gpio_get_int_level(unsigned gpio);
76extern void rb532_gpio_set_int_status(unsigned gpio, int value);
77extern int rb532_gpio_get_int_status(unsigned gpio);
78
79
80/* Wrappers for the arch-neutral GPIO API */
81
82static inline int gpio_request(unsigned gpio, const char *label)
83{
84 /* Not yet implemented */
85 return 0;
86}
87
88static inline void gpio_free(unsigned gpio)
89{
90 /* Not yet implemented */
91}
92
93static inline int gpio_direction_input(unsigned gpio)
94{
95 return rb532_gpio_direction_input(gpio);
96}
97
98static inline int gpio_direction_output(unsigned gpio, int value)
99{
100 return rb532_gpio_direction_output(gpio, value);
101}
102
103static inline int gpio_get_value(unsigned gpio)
104{
105 return rb532_gpio_get_value(gpio);
106}
107
108static inline void gpio_set_value(unsigned gpio, int value)
109{
110 rb532_gpio_set_value(gpio, value);
111}
112
113static inline int gpio_to_irq(unsigned gpio)
114{
115 return gpio;
116}
117
118static inline int irq_to_gpio(unsigned irq)
119{
120 return irq;
121}
122
123/* For cansleep */
124#include <asm-generic/gpio.h>
125
126#endif /* _RC32434_GPIO_H_ */
diff --git a/include/asm-mips/mach-rc32434/integ.h b/include/asm-mips/mach-rc32434/integ.h
new file mode 100644
index 000000000000..fa65bc3d8807
--- /dev/null
+++ b/include/asm-mips/mach-rc32434/integ.h
@@ -0,0 +1,59 @@
1/*
2 * Definitions for the Watchdog registers
3 *
4 * Copyright 2002 Ryan Holm <ryan.holmQVist@idt.com>
5 * Copyright 2008 Florian Fainelli <florian@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 *
27 */
28
29#ifndef __RC32434_INTEG_H__
30#define __RC32434_INTEG_H__
31
32#include <asm/mach-rc32434/rb.h>
33
34#define INTEG0_BASE_ADDR 0x18030030
35
36struct integ {
37 u32 errcs; /* sticky use ERRCS_ */
38 u32 wtcount; /* Watchdog timer count reg. */
39 u32 wtcompare; /* Watchdog timer timeout value. */
40 u32 wtc; /* Watchdog timer control. use WTC_ */
41};
42
43/* Error counters */
44#define RC32434_ERR_WTO 0
45#define RC32434_ERR_WNE 1
46#define RC32434_ERR_UCW 2
47#define RC32434_ERR_UCR 3
48#define RC32434_ERR_UPW 4
49#define RC32434_ERR_UPR 5
50#define RC32434_ERR_UDW 6
51#define RC32434_ERR_UDR 7
52#define RC32434_ERR_SAE 8
53#define RC32434_ERR_WRE 9
54
55/* Watchdog control bits */
56#define RC32434_WTC_EN 0
57#define RC32434_WTC_TO 1
58
59#endif /* __RC32434_INTEG_H__ */
diff --git a/include/asm-mips/mach-rc32434/irq.h b/include/asm-mips/mach-rc32434/irq.h
new file mode 100644
index 000000000000..cb9e4725f5dc
--- /dev/null
+++ b/include/asm-mips/mach-rc32434/irq.h
@@ -0,0 +1,8 @@
1#ifndef __ASM_RC32434_IRQ_H
2#define __ASM_RC32434_IRQ_H
3
4#define NR_IRQS 256
5
6#include <asm/mach-generic/irq.h>
7
8#endif /* __ASM_RC32434_IRQ_H */
diff --git a/include/asm-mips/mach-rc32434/pci.h b/include/asm-mips/mach-rc32434/pci.h
new file mode 100644
index 000000000000..410638f2af74
--- /dev/null
+++ b/include/asm-mips/mach-rc32434/pci.h
@@ -0,0 +1,481 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
10 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
12 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
13 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
14 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
15 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
16 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 * Copyright 2004 IDT Inc. (rischelp@idt.com)
23 *
24 * Initial Release
25 */
26
27#ifndef _ASM_RC32434_PCI_H_
28#define _ASM_RC32434_PCI_H_
29
30#define epld_mask ((volatile unsigned char *)0xB900000d)
31
32#define PCI0_BASE_ADDR 0x18080000
33#define PCI_LBA_COUNT 4
34
35struct pci_map {
36 u32 address; /* Address. */
37 u32 control; /* Control. */
38 u32 mapping; /* mapping. */
39};
40
41struct pci_reg {
42 u32 pcic;
43 u32 pcis;
44 u32 pcism;
45 u32 pcicfga;
46 u32 pcicfgd;
47 volatile struct pci_map pcilba[PCI_LBA_COUNT];
48 u32 pcidac;
49 u32 pcidas;
50 u32 pcidasm;
51 u32 pcidad;
52 u32 pcidma8c;
53 u32 pcidma9c;
54 u32 pcitc;
55};
56
57#define PCI_MSU_COUNT 2
58
59struct pci_msu {
60 u32 pciim[PCI_MSU_COUNT];
61 u32 pciom[PCI_MSU_COUNT];
62 u32 pciid;
63 u32 pciiic;
64 u32 pciiim;
65 u32 pciiod;
66 u32 pciioic;
67 u32 pciioim;
68};
69
70/*
71 * PCI Control Register
72 */
73
74#define PCI_CTL_EN (1 << 0)
75#define PCI_CTL_TNR (1 << 1)
76#define PCI_CTL_SCE (1 << 2)
77#define PCI_CTL_IEN (1 << 3)
78#define PCI_CTL_AAA (1 << 4)
79#define PCI_CTL_EAP (1 << 5)
80#define PCI_CTL_PCIM_BIT 6
81#define PCI_CTL_PCIM 0x000001c0
82
83#define PCI_CTL_PCIM_DIS 0
84#define PCI_CTL_PCIM_TNR 1 /* Satellite - target not ready */
85#define PCI_CTL_PCIM_SUS 2 /* Satellite - suspended CPU. */
86#define PCI_CTL_PCIM_EXT 3 /* Host - external arbiter. */
87#define PCI_CTL PCIM_PRIO 4 /* Host - fixed priority arb. */
88#define PCI_CTL_PCIM_RR 5 /* Host - round robin priority. */
89#define PCI_CTL_PCIM_RSVD6 6
90#define PCI_CTL_PCIM_RSVD7 7
91
92#define PCI_CTL_IGM (1 << 9)
93
94/*
95 * PCI Status Register
96 */
97
98#define PCI_STAT_EED (1 << 0)
99#define PCI_STAT_WR (1 << 1)
100#define PCI_STAT_NMI (1 << 2)
101#define PCI_STAT_II (1 << 3)
102#define PCI_STAT_CWE (1 << 4)
103#define PCI_STAT_CRE (1 << 5)
104#define PCI_STAT_MDPE (1 << 6)
105#define PCI_STAT_STA (1 << 7)
106#define PCI_STAT_RTA (1 << 8)
107#define PCI_STAT_RMA (1 << 9)
108#define PCI_STAT_SSE (1 << 10)
109#define PCI_STAT_OSE (1 << 11)
110#define PCI_STAT_PE (1 << 12)
111#define PCI_STAT_TAE (1 << 13)
112#define PCI_STAT_RLE (1 << 14)
113#define PCI_STAT_BME (1 << 15)
114#define PCI_STAT_PRD (1 << 16)
115#define PCI_STAT_RIP (1 << 17)
116
117/*
118 * PCI Status Mask Register
119 */
120
121#define PCI_STATM_EED PCI_STAT_EED
122#define PCI_STATM_WR PCI_STAT_WR
123#define PCI_STATM_NMI PCI_STAT_NMI
124#define PCI_STATM_II PCI_STAT_II
125#define PCI_STATM_CWE PCI_STAT_CWE
126#define PCI_STATM_CRE PCI_STAT_CRE
127#define PCI_STATM_MDPE PCI_STAT_MDPE
128#define PCI_STATM_STA PCI_STAT_STA
129#define PCI_STATM_RTA PCI_STAT_RTA
130#define PCI_STATM_RMA PCI_STAT_RMA
131#define PCI_STATM_SSE PCI_STAT_SSE
132#define PCI_STATM_OSE PCI_STAT_OSE
133#define PCI_STATM_PE PCI_STAT_PE
134#define PCI_STATM_TAE PCI_STAT_TAE
135#define PCI_STATM_RLE PCI_STAT_RLE
136#define PCI_STATM_BME PCI_STAT_BME
137#define PCI_STATM_PRD PCI_STAT_PRD
138#define PCI_STATM_RIP PCI_STAT_RIP
139
140/*
141 * PCI Configuration Address Register
142 */
143#define PCI_CFGA_REG_BIT 2
144#define PCI_CFGA_REG 0x000000fc
145#define PCI_CFGA_REG_ID (0x00 >> 2) /* use PCFGID */
146#define PCI_CFGA_REG_04 (0x04 >> 2) /* use PCFG04_ */
147#define PCI_CFGA_REG_08 (0x08 >> 2) /* use PCFG08_ */
148#define PCI_CFGA_REG_0C (0x0C >> 2) /* use PCFG0C_ */
149#define PCI_CFGA_REG_PBA0 (0x10 >> 2) /* use PCIPBA_ */
150#define PCI_CFGA_REG_PBA1 (0x14 >> 2) /* use PCIPBA_ */
151#define PCI_CFGA_REG_PBA2 (0x18 >> 2) /* use PCIPBA_ */
152#define PCI_CFGA_REG_PBA3 (0x1c >> 2) /* use PCIPBA_ */
153#define PCI_CFGA_REG_SUBSYS (0x2c >> 2) /* use PCFGSS_ */
154#define PCI_CFGA_REG_3C (0x3C >> 2) /* use PCFG3C_ */
155#define PCI_CFGA_REG_PBBA0C (0x44 >> 2) /* use PCIPBAC_ */
156#define PCI_CFGA_REG_PBA0M (0x48 >> 2)
157#define PCI_CFGA_REG_PBA1C (0x4c >> 2) /* use PCIPBAC_ */
158#define PCI_CFGA_REG_PBA1M (0x50 >> 2)
159#define PCI_CFGA_REG_PBA2C (0x54 >> 2) /* use PCIPBAC_ */
160#define PCI_CFGA_REG_PBA2M (0x58 >> 2)
161#define PCI_CFGA_REG_PBA3C (0x5c >> 2) /* use PCIPBAC_ */
162#define PCI_CFGA_REG_PBA3M (0x60 >> 2)
163#define PCI_CFGA_REG_PMGT (0x64 >> 2)
164#define PCI_CFGA_FUNC_BIT 8
165#define PCI_CFGA_FUNC 0x00000700
166#define PCI_CFGA_DEV_BIT 11
167#define PCI_CFGA_DEV 0x0000f800
168#define PCI_CFGA_DEV_INTERN 0
169#define PCI_CFGA_BUS_BIT 16
170#define PCI CFGA_BUS 0x00ff0000
171#define PCI_CFGA_BUS_TYPE0 0
172#define PCI_CFGA_EN (1 << 31)
173
174/* PCI CFG04 commands */
175#define PCI_CFG04_CMD_IO_ENA (1 << 0)
176#define PCI_CFG04_CMD_MEM_ENA (1 << 1)
177#define PCI_CFG04_CMD_BM_ENA (1 << 2)
178#define PCI_CFG04_CMD_MW_INV (1 << 4)
179#define PCI_CFG04_CMD_PAR_ENA (1 << 6)
180#define PCI_CFG04_CMD_SER_ENA (1 << 8)
181#define PCI_CFG04_CMD_FAST_ENA (1 << 9)
182
183/* PCI CFG04 status fields */
184#define PCI_CFG04_STAT_BIT 16
185#define PCI_CFG04_STAT 0xffff0000
186#define PCI_CFG04_STAT_66_MHZ (1 << 21)
187#define PCI_CFG04_STAT_FBB (1 << 23)
188#define PCI_CFG04_STAT_MDPE (1 << 24)
189#define PCI_CFG04_STAT_DST (1 << 25)
190#define PCI_CFG04_STAT_STA (1 << 27)
191#define PCI_CFG04_STAT_RTA (1 << 28)
192#define PCI_CFG04_STAT_RMA (1 << 29)
193#define PCI_CFG04_STAT_SSE (1 << 30)
194#define PCI_CFG04_STAT_PE (1 << 31)
195
196#define PCI_PBA_MSI (1 << 0)
197#define PCI_PBA_P (1 << 2)
198
199/* PCI PBAC registers */
200#define PCI_PBAC_MSI (1 << 0)
201#define PCI_PBAC_P (1 << 1)
202#define PCI_PBAC_SIZE_BIT 2
203#define PCI_PBAC_SIZE 0x0000007c
204#define PCI_PBAC_SB (1 << 7)
205#define PCI_PBAC_PP (1 << 8)
206#define PCI_PBAC_MR_BIT 9
207#define PCI_PBAC_MR 0x00000600
208#define PCI_PBAC_MR_RD 0
209#define PCI_PBAC_MR_RD_LINE 1
210#define PCI_PBAC_MR_RD_MULT 2
211#define PCI_PBAC_MRL (1 << 11)
212#define PCI_PBAC_MRM (1 << 12)
213#define PCI_PBAC_TRP (1 << 13)
214
215#define PCI_CFG40_TRDY_TIM 0x000000ff
216#define PCI_CFG40_RET_LIM 0x0000ff00
217
218/*
219 * PCI Local Base Address [0|1|2|3] Register
220 */
221
222#define PCI_LBA_BADDR_BIT 0
223#define PCI_LBA_BADDR 0xffffff00
224
225/*
226 * PCI Local Base Address Control Register
227 */
228
229#define PCI_LBAC_MSI (1 << 0)
230#define PCI_LBAC_MSI_MEM 0
231#define PCI_LBAC_MSI_IO 1
232#define PCI_LBAC_SIZE_BIT 2
233#define PCI_LBAC_SIZE 0x0000007c
234#define PCI_LBAC_SB (1 << 7)
235#define PCI_LBAC_RT (1 << 8)
236#define PCI_LBAC_RT_NO_PREF 0
237#define PCI_LBAC_RT_PREF 1
238
239/*
240 * PCI Local Base Address [0|1|2|3] Mapping Register
241 */
242#define PCI_LBAM_MADDR_BIT 8
243#define PCI_LBAM_MADDR 0xffffff00
244
245/*
246 * PCI Decoupled Access Control Register
247 */
248#define PCI_DAC_DEN (1 << 0)
249
250/*
251 * PCI Decoupled Access Status Register
252 */
253#define PCI_DAS_D (1 << 0)
254#define PCI_DAS_B (1 << 1)
255#define PCI_DAS_E (1 << 2)
256#define PCI_DAS_OFE (1 << 3)
257#define PCI_DAS_OFF (1 << 4)
258#define PCI_DAS_IFE (1 << 5)
259#define PCI_DAS_IFF (1 << 6)
260
261/*
262 * PCI DMA Channel 8 Configuration Register
263 */
264#define PCI_DMA8C_MBS_BIT 0
265#define PCI_DMA8C_MBS 0x00000fff /* Maximum Burst Size. */
266#define PCI_DMA8C_OUR (1 << 12)
267
268/*
269 * PCI DMA Channel 9 Configuration Register
270 */
271#define PCI_DMA9C_MBS_BIT 0 /* Maximum Burst Size. */
272#define PCI_DMA9C_MBS 0x00000fff
273
274/*
275 * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
276 */
277
278#define PCI_DMAD_PT_BIT 22 /* in DEVCMD field (descriptor) */
279#define PCI_DMAD_PT 0x00c00000 /* preferred transaction field */
280/* These are for reads (DMA channel 8) */
281#define PCI_DMAD_DEVCMD_MR 0 /* memory read */
282#define PCI_DMAD_DEVCMD_MRL 1 /* memory read line */
283#define PCI_DMAD_DEVCMD_MRM 2 /* memory read multiple */
284#define PCI_DMAD_DEVCMD_IOR 3 /* I/O read */
285/* These are for writes (DMA channel 9) */
286#define PCI_DMAD_DEVCMD_MW 0 /* memory write */
287#define PCI_DMAD_DEVCMD_MWI 1 /* memory write invalidate */
288#define PCI_DMAD_DEVCMD_IOW 3 /* I/O write */
289
290/* Swap byte field applies to both DMA channel 8 and 9 */
291#define PCI_DMAD_SB (1 << 24) /* swap byte field */
292
293
294/*
295 * PCI Target Control Register
296 */
297
298#define PCI_TC_RTIMER_BIT 0
299#define PCI_TC_RTIMER 0x000000ff
300#define PCI_TC_DTIMER_BIT 8
301#define PCI_TC_DTIMER 0x0000ff00
302#define PCI_TC_RDR (1 << 18)
303#define PCI_TC_DDT (1 << 19)
304
305/*
306 * PCI messaging unit [applies to both inbound and outbound registers ]
307 */
308#define PCI_MSU_M0 (1 << 0)
309#define PCI_MSU_M1 (1 << 1)
310#define PCI_MSU_DB (1 << 2)
311
312#define PCI_MSG_ADDR 0xB8088010
313#define PCI0_ADDR 0xB8080000
314#define rc32434_pci ((struct pci_reg *) PCI0_ADDR)
315#define rc32434_pci_msg ((struct pci_msu *) PCI_MSG_ADDR)
316
317#define PCIM_SHFT 0x6
318#define PCIM_BIT_LEN 0x7
319#define PCIM_H_EA 0x3
320#define PCIM_H_IA_FIX 0x4
321#define PCIM_H_IA_RR 0x5
322#if 0
323#define PCI_ADDR_START 0x13000000
324#endif
325
326#define PCI_ADDR_START 0x50000000
327
328#define CPUTOPCI_MEM_WIN 0x02000000
329#define CPUTOPCI_IO_WIN 0x00100000
330#define PCILBA_SIZE_SHFT 2
331#define PCILBA_SIZE_MASK 0x1F
332#define SIZE_256MB 0x1C
333#define SIZE_128MB 0x1B
334#define SIZE_64MB 0x1A
335#define SIZE_32MB 0x19
336#define SIZE_16MB 0x18
337#define SIZE_4MB 0x16
338#define SIZE_2MB 0x15
339#define SIZE_1MB 0x14
340#define KORINA_CONFIG0_ADDR 0x80000000
341#define KORINA_CONFIG1_ADDR 0x80000004
342#define KORINA_CONFIG2_ADDR 0x80000008
343#define KORINA_CONFIG3_ADDR 0x8000000C
344#define KORINA_CONFIG4_ADDR 0x80000010
345#define KORINA_CONFIG5_ADDR 0x80000014
346#define KORINA_CONFIG6_ADDR 0x80000018
347#define KORINA_CONFIG7_ADDR 0x8000001C
348#define KORINA_CONFIG8_ADDR 0x80000020
349#define KORINA_CONFIG9_ADDR 0x80000024
350#define KORINA_CONFIG10_ADDR 0x80000028
351#define KORINA_CONFIG11_ADDR 0x8000002C
352#define KORINA_CONFIG12_ADDR 0x80000030
353#define KORINA_CONFIG13_ADDR 0x80000034
354#define KORINA_CONFIG14_ADDR 0x80000038
355#define KORINA_CONFIG15_ADDR 0x8000003C
356#define KORINA_CONFIG16_ADDR 0x80000040
357#define KORINA_CONFIG17_ADDR 0x80000044
358#define KORINA_CONFIG18_ADDR 0x80000048
359#define KORINA_CONFIG19_ADDR 0x8000004C
360#define KORINA_CONFIG20_ADDR 0x80000050
361#define KORINA_CONFIG21_ADDR 0x80000054
362#define KORINA_CONFIG22_ADDR 0x80000058
363#define KORINA_CONFIG23_ADDR 0x8000005C
364#define KORINA_CONFIG24_ADDR 0x80000060
365#define KORINA_CONFIG25_ADDR 0x80000064
366#define KORINA_CMD (PCI_CFG04_CMD_IO_ENA | \
367 PCI_CFG04_CMD_MEM_ENA | \
368 PCI_CFG04_CMD_BM_ENA | \
369 PCI_CFG04_CMD_MW_INV | \
370 PCI_CFG04_CMD_PAR_ENA | \
371 PCI_CFG04_CMD_SER_ENA)
372
373#define KORINA_STAT (PCI_CFG04_STAT_MDPE | \
374 PCI_CFG04_STAT_STA | \
375 PCI_CFG04_STAT_RTA | \
376 PCI_CFG04_STAT_RMA | \
377 PCI_CFG04_STAT_SSE | \
378 PCI_CFG04_STAT_PE)
379
380#define KORINA_CNFG1 ((KORINA_STAT<<16)|KORINA_CMD)
381
382#define KORINA_REVID 0
383#define KORINA_CLASS_CODE 0
384#define KORINA_CNFG2 ((KORINA_CLASS_CODE<<8) | \
385 KORINA_REVID)
386
387#define KORINA_CACHE_LINE_SIZE 4
388#define KORINA_MASTER_LAT 0x3c
389#define KORINA_HEADER_TYPE 0
390#define KORINA_BIST 0
391
392#define KORINA_CNFG3 ((KORINA_BIST << 24) | \
393 (KORINA_HEADER_TYPE<<16) | \
394 (KORINA_MASTER_LAT<<8) | \
395 KORINA_CACHE_LINE_SIZE)
396
397#define KORINA_BAR0 0x00000008 /* 128 MB Memory */
398#define KORINA_BAR1 0x18800001 /* 1 MB IO */
399#define KORINA_BAR2 0x18000001 /* 2 MB IO window for Korina
400 internal Registers */
401#define KORINA_BAR3 0x48000008 /* Spare 128 MB Memory */
402
403#define KORINA_CNFG4 KORINA_BAR0
404#define KORINA_CNFG5 KORINA_BAR1
405#define KORINA_CNFG6 KORINA_BAR2
406#define KORINA_CNFG7 KORINA_BAR3
407
408#define KORINA_SUBSYS_VENDOR_ID 0x011d
409#define KORINA_SUBSYSTEM_ID 0x0214
410#define KORINA_CNFG8 0
411#define KORINA_CNFG9 0
412#define KORINA_CNFG10 0
413#define KORINA_CNFG11 ((KORINA_SUBSYS_VENDOR_ID<<16) | \
414 KORINA_SUBSYSTEM_ID)
415#define KORINA_INT_LINE 1
416#define KORINA_INT_PIN 1
417#define KORINA_MIN_GNT 8
418#define KORINA_MAX_LAT 0x38
419#define KORINA_CNFG12 0
420#define KORINA_CNFG13 0
421#define KORINA_CNFG14 0
422#define KORINA_CNFG15 ((KORINA_MAX_LAT<<24) | \
423 (KORINA_MIN_GNT<<16) | \
424 (KORINA_INT_PIN<<8) | \
425 KORINA_INT_LINE)
426#define KORINA_RETRY_LIMIT 0x80
427#define KORINA_TRDY_LIMIT 0x80
428#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \
429 KORINA_TRDY_LIMIT)
430#define PCI_PBAxC_R 0x0
431#define PCI_PBAxC_RL 0x1
432#define PCI_PBAxC_RM 0x2
433#define SIZE_SHFT 2
434
435#if defined(__MIPSEB__)
436#define KORINA_PBA0C (PCI_PBAC_MRL | PCI_PBAC_SB | \
437 ((PCI_PBAxC_RM & 0x3) << PCI_PBAC_MR_BIT) | \
438 PCI_PBAC_PP | \
439 (SIZE_128MB<<SIZE_SHFT) | \
440 PCI_PBAC_P)
441#else
442#define KORINA_PBA0C (PCI_PBAC_MRL | \
443 ((PCI_PBAxC_RM & 0x3) << PCI_PBAC_MR_BIT) | \
444 PCI_PBAC_PP | \
445 (SIZE_128MB<<SIZE_SHFT) | \
446 PCI_PBAC_P)
447#endif
448#define KORINA_CNFG17 KORINA_PBA0C
449#define KORINA_PBA0M 0x0
450#define KORINA_CNFG18 KORINA_PBA0M
451
452#if defined(__MIPSEB__)
453#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | PCI_PBAC_SB | \
454 PCI_PBAC_MSI)
455#else
456#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | \
457 PCI_PBAC_MSI)
458#endif
459#define KORINA_CNFG19 KORINA_PBA1C
460#define KORINA_PBA1M 0x0
461#define KORINA_CNFG20 KORINA_PBA1M
462
463#if defined(__MIPSEB__)
464#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | PCI_PBAC_SB | \
465 PCI_PBAC_MSI)
466#else
467#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | \
468 PCI_PBAC_MSI)
469#endif
470#define KORINA_CNFG21 KORINA_PBA2C
471#define KORINA_PBA2M 0x18000000
472#define KORINA_CNFG22 KORINA_PBA2M
473#define KORINA_PBA3C 0
474#define KORINA_CNFG23 KORINA_PBA3C
475#define KORINA_PBA3M 0
476#define KORINA_CNFG24 KORINA_PBA3M
477
478#define PCITC_DTIMER_VAL 8
479#define PCITC_RTIMER_VAL 0x10
480
481#endif /* __ASM_RC32434_PCI_H */
diff --git a/include/asm-mips/mach-rc32434/prom.h b/include/asm-mips/mach-rc32434/prom.h
new file mode 100644
index 000000000000..1d66ddcda89a
--- /dev/null
+++ b/include/asm-mips/mach-rc32434/prom.h
@@ -0,0 +1,44 @@
1/*
2 * Definitions for the PROM
3 *
4 * Copyright 2002 Ryan Holm <ryan.holmQVist@idt.com>
5 * Copyright 2008 Florian Fainelli <florian@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 *
27 */
28
29#define PROM_ENTRY(x) (0xbfc00000 + ((x) * 8))
30
31#define GPIO_INIT_NOBUTTON ""
32#define GPIO_INIT_BUTTON " 2"
33
34#define SR_NMI 0x00180000
35#define SERIAL_SPEED_ENTRY 0x00000001
36
37#define FREQ_TAG "HZ="
38#define GPIO_TAG "gpio="
39#define KMAC_TAG "kmac="
40#define MEM_TAG "mem="
41#define BOARD_TAG "board="
42
43#define BOARD_RB532 "500"
44#define BOARD_RB532A "500r5"
diff --git a/include/asm-mips/mach-rc32434/rb.h b/include/asm-mips/mach-rc32434/rb.h
new file mode 100644
index 000000000000..e0a76e3ffea8
--- /dev/null
+++ b/include/asm-mips/mach-rc32434/rb.h
@@ -0,0 +1,81 @@
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * Copyright (C) 2004 IDT Inc.
13 * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
14 */
15#ifndef __ASM_RC32434_RB_H
16#define __ASM_RC32434_RB_H
17
18#include <linux/genhd.h>
19
20#define IDT434_REG_BASE ((volatile void *) KSEG1ADDR(0x18000000))
21#define DEV0BASE 0x010000
22#define DEV0MASK 0x010004
23#define DEV0C 0x010008
24#define DEV0T 0x01000C
25#define DEV1BASE 0x010010
26#define DEV1MASK 0x010014
27#define DEV1C 0x010018
28#define DEV1TC 0x01001C
29#define DEV2BASE 0x010020
30#define DEV2MASK 0x010024
31#define DEV2C 0x010028
32#define DEV2TC 0x01002C
33#define DEV3BASE 0x010030
34#define DEV3MASK 0x010034
35#define DEV3C 0x010038
36#define DEV3TC 0x01003C
37#define BTCS 0x010040
38#define BTCOMPARE 0x010044
39#define GPIOBASE 0x050000
40#define GPIOCFG 0x050004
41#define GPIOD 0x050008
42#define GPIOILEVEL 0x05000C
43#define GPIOISTAT 0x050010
44#define GPIONMIEN 0x050014
45#define IMASK6 0x038038
46#define LO_WPX (1 << 0)
47#define LO_ALE (1 << 1)
48#define LO_CLE (1 << 2)
49#define LO_CEX (1 << 3)
50#define LO_FOFF (1 << 5)
51#define LO_SPICS (1 << 6)
52#define LO_ULED (1 << 7)
53
54#define BIT_TO_MASK(x) (1 << x)
55
56struct dev_reg {
57 u32 base;
58 u32 mask;
59 u32 ctl;
60 u32 timing;
61};
62
63struct korina_device {
64 char *name;
65 unsigned char mac[6];
66 struct net_device *dev;
67};
68
69struct cf_device {
70 int gpio_pin;
71 void *dev;
72 struct gendisk *gd;
73};
74
75struct mpmc_device {
76 unsigned char state;
77 spinlock_t lock;
78 void __iomem *base;
79};
80
81#endif /* __ASM_RC32434_RB_H */
diff --git a/include/asm-mips/mach-rc32434/rc32434.h b/include/asm-mips/mach-rc32434/rc32434.h
new file mode 100644
index 000000000000..c4a02145104e
--- /dev/null
+++ b/include/asm-mips/mach-rc32434/rc32434.h
@@ -0,0 +1,61 @@
1/*
2 * Definitions for IDT RC323434 CPU.
3 */
4
5#ifndef _ASM_RC32434_RC32434_H_
6#define _ASM_RC32434_RC32434_H_
7
8#include <linux/delay.h>
9#include <linux/io.h>
10
11#define RC32434_REG_BASE 0x18000000
12#define RC32434_RST (1 << 15)
13
14#define IDT_CLOCK_MULT 2
15#define MIPS_CPU_TIMER_IRQ 7
16
17/* Interrupt Controller */
18#define IC_GROUP0_PEND (RC32434_REG_BASE + 0x38000)
19#define IC_GROUP0_MASK (RC32434_REG_BASE + 0x38008)
20#define IC_GROUP_OFFSET 0x0C
21
22#define NUM_INTR_GROUPS 5
23
24/* 16550 UARTs */
25#define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */
26 /* GRP3 IRQ numbers start here */
27#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32)
28 /* GRP4 IRQ numbers start here */
29#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32)
30 /* GRP5 IRQ numbers start here */
31#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32)
32#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
33
34
35#ifdef __MIPSEB__
36#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58003)
37#else
38#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58000)
39#endif
40
41#define RC32434_UART0_IRQ (GROUP3_IRQ_BASE + 0)
42
43/* cpu pipeline flush */
44static inline void rc32434_sync(void)
45{
46 __asm__ volatile ("sync");
47}
48
49static inline void rc32434_sync_udelay(int us)
50{
51 __asm__ volatile ("sync");
52 udelay(us);
53}
54
55static inline void rc32434_sync_delay(int ms)
56{
57 __asm__ volatile ("sync");
58 mdelay(ms);
59}
60
61#endif /* _ASM_RC32434_RC32434_H_ */
diff --git a/include/asm-mips/mach-rc32434/timer.h b/include/asm-mips/mach-rc32434/timer.h
new file mode 100644
index 000000000000..e49b1d57a017
--- /dev/null
+++ b/include/asm-mips/mach-rc32434/timer.h
@@ -0,0 +1,65 @@
1/*
2 * Definitions for timer registers
3 *
4 * Copyright 2004 Philip Rischel <rischelp@idt.com>
5 * Copyright 2008 Florian Fainelli <florian@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 *
27 */
28
29#ifndef __ASM_RC32434_TIMER_H
30#define __ASM_RC32434_TIMER_H
31
32#include <asm/mach-rc32434/rb.h>
33
34#define TIMER0_BASE_ADDR 0x18028000
35#define TIMER_COUNT 3
36
37struct timer_counter {
38 u32 count;
39 u32 compare;
40 u32 ctc; /*use CTC_ */
41};
42
43struct timer {
44 struct timer_counter tim[TIMER_COUNT];
45 u32 rcount; /* use RCOUNT_ */
46 u32 rcompare; /* use RCOMPARE_ */
47 u32 rtc; /* use RTC_ */
48};
49
50#define RC32434_CTC_EN_BIT 0
51#define RC32434_CTC_TO_BIT 1
52
53/* Real time clock registers */
54#define RC32434_RTC_MSK(x) BIT_TO_MASK(x)
55#define RC32434_RTC_CE_BIT 0
56#define RC32434_RTC_TO_BIT 1
57#define RC32434_RTC_RQE_BIT 2
58
59/* Counter registers */
60#define RC32434_RCOUNT_BIT 0
61#define RC32434_RCOUNT_MSK 0x0000ffff
62#define RC32434_RCOMP_BIT 0
63#define RC32434_RCOMP_MSK 0x0000ffff
64
65#endif /* __ASM_RC32434_TIMER_H */
diff --git a/include/asm-mips/mach-rc32434/war.h b/include/asm-mips/mach-rc32434/war.h
new file mode 100644
index 000000000000..3ddf187e98a6
--- /dev/null
+++ b/include/asm-mips/mach-rc32434/war.h
@@ -0,0 +1,25 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
9#define __ASM_MIPS_MACH_MIPS_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 1
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */
diff --git a/include/asm-mips/mips-boards/atlas.h b/include/asm-mips/mips-boards/atlas.h
deleted file mode 100644
index a8ae12d120ee..000000000000
--- a/include/asm-mips/mips-boards/atlas.h
+++ /dev/null
@@ -1,80 +0,0 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * ########################################################################
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 *
20 * ########################################################################
21 *
22 * Defines of the Atlas board specific address-MAP, registers, etc.
23 *
24 */
25#ifndef _MIPS_ATLAS_H
26#define _MIPS_ATLAS_H
27
28#include <asm/addrspace.h>
29
30/*
31 * Atlas RTC-device indirect register access.
32 */
33#define ATLAS_RTC_ADR_REG 0x1f000800
34#define ATLAS_RTC_DAT_REG 0x1f000808
35
36/*
37 * Atlas interrupt controller register base.
38 */
39#define ATLAS_ICTRL_REGS_BASE 0x1f000000
40
41/*
42 * Atlas registers are memory mapped on 64-bit aligned boundaries and
43 * only word access are allowed.
44 */
45struct atlas_ictrl_regs {
46 volatile unsigned int intraw;
47 int dummy1;
48 volatile unsigned int intseten;
49 int dummy2;
50 volatile unsigned int intrsten;
51 int dummy3;
52 volatile unsigned int intenable;
53 int dummy4;
54 volatile unsigned int intstatus;
55 int dummy5;
56};
57
58/*
59 * Atlas UART register base.
60 */
61#define ATLAS_UART_REGS_BASE 0x1f000900
62#define ATLAS_BASE_BAUD ( 3686400 / 16 )
63
64/*
65 * Atlas PSU standby register.
66 */
67#define ATLAS_PSUSTBY_REG 0x1f000600
68#define ATLAS_GOSTBY 0x4d
69
70/*
71 * We make a universal assumption about the way the bootloader (YAMON)
72 * have located the Philips SAA9730 chip.
73 * This is not ideal, but is needed for setting up remote debugging as
74 * soon as possible.
75 */
76#define ATLAS_SAA9730_REG 0x10800000
77
78#define ATLAS_SAA9730_BAUDCLOCK 3692300
79
80#endif /* !(_MIPS_ATLAS_H) */
diff --git a/include/asm-mips/mips-boards/atlasint.h b/include/asm-mips/mips-boards/atlasint.h
deleted file mode 100644
index 93ba1c1b2a4f..000000000000
--- a/include/asm-mips/mips-boards/atlasint.h
+++ /dev/null
@@ -1,109 +0,0 @@
1/*
2 * Copyright (C) 1999, 2006 MIPS Technologies, Inc. All rights reserved.
3 * Authors: Carsten Langgaard <carstenl@mips.com>
4 * Maciej W. Rozycki <macro@mips.com>
5 *
6 * ########################################################################
7 *
8 * This program is free software; you can distribute it and/or modify it
9 * under the terms of the GNU General Public License (Version 2) as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 *
21 * ########################################################################
22 *
23 * Defines for the Atlas interrupt controller.
24 *
25 */
26#ifndef _MIPS_ATLASINT_H
27#define _MIPS_ATLASINT_H
28
29#include <irq.h>
30
31/* CPU interrupt offsets */
32#define MIPSCPU_INT_SW0 0
33#define MIPSCPU_INT_SW1 1
34#define MIPSCPU_INT_MB0 2
35#define MIPSCPU_INT_ATLAS MIPSCPU_INT_MB0
36#define MIPSCPU_INT_MB1 3
37#define MIPSCPU_INT_MB2 4
38#define MIPSCPU_INT_MB3 5
39#define MIPSCPU_INT_MB4 6
40
41/*
42 * Interrupts 8..39 are used for Atlas interrupt controller interrupts
43 */
44#define ATLAS_INT_BASE 8
45#define ATLAS_INT_UART (ATLAS_INT_BASE + 0)
46#define ATLAS_INT_TIM0 (ATLAS_INT_BASE + 1)
47#define ATLAS_INT_RES2 (ATLAS_INT_BASE + 2)
48#define ATLAS_INT_RES3 (ATLAS_INT_BASE + 3)
49#define ATLAS_INT_RTC (ATLAS_INT_BASE + 4)
50#define ATLAS_INT_COREHI (ATLAS_INT_BASE + 5)
51#define ATLAS_INT_CORELO (ATLAS_INT_BASE + 6)
52#define ATLAS_INT_RES7 (ATLAS_INT_BASE + 7)
53#define ATLAS_INT_PCIA (ATLAS_INT_BASE + 8)
54#define ATLAS_INT_PCIB (ATLAS_INT_BASE + 9)
55#define ATLAS_INT_PCIC (ATLAS_INT_BASE + 10)
56#define ATLAS_INT_PCID (ATLAS_INT_BASE + 11)
57#define ATLAS_INT_ENUM (ATLAS_INT_BASE + 12)
58#define ATLAS_INT_DEG (ATLAS_INT_BASE + 13)
59#define ATLAS_INT_ATXFAIL (ATLAS_INT_BASE + 14)
60#define ATLAS_INT_INTA (ATLAS_INT_BASE + 15)
61#define ATLAS_INT_INTB (ATLAS_INT_BASE + 16)
62#define ATLAS_INT_ETH ATLAS_INT_INTB
63#define ATLAS_INT_INTC (ATLAS_INT_BASE + 17)
64#define ATLAS_INT_SCSI ATLAS_INT_INTC
65#define ATLAS_INT_INTD (ATLAS_INT_BASE + 18)
66#define ATLAS_INT_SERR (ATLAS_INT_BASE + 19)
67#define ATLAS_INT_RES20 (ATLAS_INT_BASE + 20)
68#define ATLAS_INT_RES21 (ATLAS_INT_BASE + 21)
69#define ATLAS_INT_RES22 (ATLAS_INT_BASE + 22)
70#define ATLAS_INT_RES23 (ATLAS_INT_BASE + 23)
71#define ATLAS_INT_RES24 (ATLAS_INT_BASE + 24)
72#define ATLAS_INT_RES25 (ATLAS_INT_BASE + 25)
73#define ATLAS_INT_RES26 (ATLAS_INT_BASE + 26)
74#define ATLAS_INT_RES27 (ATLAS_INT_BASE + 27)
75#define ATLAS_INT_RES28 (ATLAS_INT_BASE + 28)
76#define ATLAS_INT_RES29 (ATLAS_INT_BASE + 29)
77#define ATLAS_INT_RES30 (ATLAS_INT_BASE + 30)
78#define ATLAS_INT_RES31 (ATLAS_INT_BASE + 31)
79#define ATLAS_INT_END (ATLAS_INT_BASE + 31)
80
81/*
82 * Interrupts 64..127 are used for Soc-it Classic interrupts
83 */
84#define MSC01C_INT_BASE 64
85
86/* SOC-it Classic interrupt offsets */
87#define MSC01C_INT_TMR 0
88#define MSC01C_INT_PCI 1
89
90/*
91 * Interrupts 64..127 are used for Soc-it EIC interrupts
92 */
93#define MSC01E_INT_BASE 64
94
95/* SOC-it EIC interrupt offsets */
96#define MSC01E_INT_SW0 1
97#define MSC01E_INT_SW1 2
98#define MSC01E_INT_MB0 3
99#define MSC01E_INT_ATLAS MSC01E_INT_MB0
100#define MSC01E_INT_MB1 4
101#define MSC01E_INT_MB2 5
102#define MSC01E_INT_MB3 6
103#define MSC01E_INT_MB4 7
104#define MSC01E_INT_TMR 8
105#define MSC01E_INT_PCI 9
106#define MSC01E_INT_PERFCTR 10
107#define MSC01E_INT_CPUCTR 11
108
109#endif /* !(_MIPS_ATLASINT_H) */
diff --git a/include/asm-mips/mips-boards/maltasmp.h b/include/asm-mips/mips-boards/maltasmp.h
deleted file mode 100644
index 8d7e955d506e..000000000000
--- a/include/asm-mips/mips-boards/maltasmp.h
+++ /dev/null
@@ -1,36 +0,0 @@
1/*
2 * There are several SMP models supported
3 * SMTC is mutually exclusive to other options (atm)
4 */
5#if defined(CONFIG_MIPS_MT_SMTC)
6#define malta_smtc 1
7#define malta_cmp 0
8#define malta_smvp 0
9#else
10#define malta_smtc 0
11#if defined(CONFIG_MIPS_CMP)
12extern int gcmp_present;
13#define malta_cmp gcmp_present
14#else
15#define malta_cmp 0
16#endif
17/* FIXME: should become COMFIG_MIPS_MT_SMVP */
18#if defined(CONFIG_MIPS_MT_SMP)
19#define malta_smvp 1
20#else
21#define malta_smvp 0
22#endif
23#endif
24
25#include <asm/mipsregs.h>
26#include <asm/mipsmtregs.h>
27
28/* malta_smtc */
29#include <asm/smtc.h>
30#include <asm/smtc_ipi.h>
31
32/* malta_cmp */
33#include <asm/cmp.h>
34
35/* malta_smvp */
36#include <asm/smvp.h>
diff --git a/include/asm-mips/mips-boards/saa9730_uart.h b/include/asm-mips/mips-boards/saa9730_uart.h
deleted file mode 100644
index c913143d58ec..000000000000
--- a/include/asm-mips/mips-boards/saa9730_uart.h
+++ /dev/null
@@ -1,69 +0,0 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * ########################################################################
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 *
20 * ########################################################################
21 *
22 * Register definitions for the UART part of the Philips SAA9730 chip.
23 *
24 */
25
26#ifndef SAA9730_UART_H
27#define SAA9730_UART_H
28
29/* The SAA9730 UART register map, as seen via the PCI bus */
30
31#define SAA9730_UART_REGS_ADDR 0x21800
32
33struct uart_saa9730_regmap {
34 volatile unsigned char Thr_Rbr;
35 volatile unsigned char Ier;
36 volatile unsigned char Iir_Fcr;
37 volatile unsigned char Lcr;
38 volatile unsigned char Mcr;
39 volatile unsigned char Lsr;
40 volatile unsigned char Msr;
41 volatile unsigned char Scr;
42 volatile unsigned char BaudDivLsb;
43 volatile unsigned char BaudDivMsb;
44 volatile unsigned char Junk0;
45 volatile unsigned char Junk1;
46 volatile unsigned int Config; /* 0x2180c */
47 volatile unsigned int TxStart; /* 0x21810 */
48 volatile unsigned int TxLength; /* 0x21814 */
49 volatile unsigned int TxCounter; /* 0x21818 */
50 volatile unsigned int RxStart; /* 0x2181c */
51 volatile unsigned int RxLength; /* 0x21820 */
52 volatile unsigned int RxCounter; /* 0x21824 */
53};
54typedef volatile struct uart_saa9730_regmap t_uart_saa9730_regmap;
55
56/*
57 * Only a subset of the UART control bits are defined here,
58 * enough to make the serial debug port work.
59 */
60
61#define SAA9730_LCR_DATA8 0x03
62
63#define SAA9730_MCR_DTR 0x01
64#define SAA9730_MCR_RTS 0x02
65
66#define SAA9730_LSR_DR 0x01
67#define SAA9730_LSR_THRE 0x20
68
69#endif /* !(SAA9730_UART_H) */
diff --git a/include/asm-mips/mips-boards/sead.h b/include/asm-mips/mips-boards/sead.h
deleted file mode 100644
index 68c69de0b66f..000000000000
--- a/include/asm-mips/mips-boards/sead.h
+++ /dev/null
@@ -1,36 +0,0 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved.
4 *
5 * ########################################################################
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 *
20 * ########################################################################
21 *
22 * Defines of the SEAD board specific address-MAP, registers, etc.
23 *
24 */
25#ifndef _MIPS_SEAD_H
26#define _MIPS_SEAD_H
27
28#include <asm/addrspace.h>
29
30/*
31 * SEAD UART register base.
32 */
33#define SEAD_UART0_REGS_BASE (0x1f000800)
34#define SEAD_BASE_BAUD ( 3686400 / 16 )
35
36#endif /* !(_MIPS_SEAD_H) */
diff --git a/include/asm-mips/mips-boards/seadint.h b/include/asm-mips/mips-boards/seadint.h
deleted file mode 100644
index e710bae07340..000000000000
--- a/include/asm-mips/mips-boards/seadint.h
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved.
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * Defines for the SEAD interrupt controller.
19 */
20#ifndef _MIPS_SEADINT_H
21#define _MIPS_SEADINT_H
22
23#include <irq.h>
24
25#define MIPSCPU_INT_UART0 2
26#define MIPSCPU_INT_UART1 3
27
28#endif /* !(_MIPS_SEADINT_H) */
diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h
index 8735aa0b8963..494f00ba9541 100644
--- a/include/asm-mips/page.h
+++ b/include/asm-mips/page.h
@@ -34,6 +34,9 @@
34#include <linux/pfn.h> 34#include <linux/pfn.h>
35#include <asm/io.h> 35#include <asm/io.h>
36 36
37extern void build_clear_page(void);
38extern void build_copy_page(void);
39
37/* 40/*
38 * It's normally defined only for FLATMEM config but it's 41 * It's normally defined only for FLATMEM config but it's
39 * used in our early mem init code for all memory models. 42 * used in our early mem init code for all memory models.
diff --git a/include/asm-mips/pci.h b/include/asm-mips/pci.h
index d3be83436070..c205875d7f31 100644
--- a/include/asm-mips/pci.h
+++ b/include/asm-mips/pci.h
@@ -173,6 +173,5 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
173} 173}
174 174
175extern int pci_probe_only; 175extern int pci_probe_only;
176extern unsigned int pcibios_max_latency;
177 176
178#endif /* _ASM_PCI_H */ 177#endif /* _ASM_PCI_H */
diff --git a/include/asm-mips/setup.h b/include/asm-mips/setup.h
index 883f59bfa097..e600cedda976 100644
--- a/include/asm-mips/setup.h
+++ b/include/asm-mips/setup.h
@@ -3,6 +3,8 @@
3 3
4#define COMMAND_LINE_SIZE 256 4#define COMMAND_LINE_SIZE 256
5 5
6#ifdef __KERNEL__
6extern void setup_early_printk(void); 7extern void setup_early_printk(void);
8#endif /* __KERNEL__ */
7 9
8#endif /* __SETUP_H */ 10#endif /* __SETUP_H */
diff --git a/include/asm-mips/txx9/generic.h b/include/asm-mips/txx9/generic.h
index d8756660523d..cbae37ec3d88 100644
--- a/include/asm-mips/txx9/generic.h
+++ b/include/asm-mips/txx9/generic.h
@@ -12,6 +12,8 @@
12#include <linux/ioport.h> /* for struct resource */ 12#include <linux/ioport.h> /* for struct resource */
13 13
14extern struct resource txx9_ce_res[]; 14extern struct resource txx9_ce_res[];
15#define TXX9_CE(n) (unsigned long)(txx9_ce_res[(n)].start)
16extern unsigned int txx9_pcode;
15extern char txx9_pcode_str[8]; 17extern char txx9_pcode_str[8];
16void txx9_reg_res_init(unsigned int pcode, unsigned long base, 18void txx9_reg_res_init(unsigned int pcode, unsigned long base,
17 unsigned long size); 19 unsigned long size);
@@ -19,6 +21,11 @@ void txx9_reg_res_init(unsigned int pcode, unsigned long base,
19extern unsigned int txx9_master_clock; 21extern unsigned int txx9_master_clock;
20extern unsigned int txx9_cpu_clock; 22extern unsigned int txx9_cpu_clock;
21extern unsigned int txx9_gbus_clock; 23extern unsigned int txx9_gbus_clock;
24#define TXX9_IMCLK (txx9_gbus_clock / 2)
25
26extern int txx9_ccfg_toeon;
27struct uart_port;
28int early_serial_txx9_setup(struct uart_port *port);
22 29
23struct pci_dev; 30struct pci_dev;
24struct txx9_board_vec { 31struct txx9_board_vec {
diff --git a/include/asm-mips/txx9/rbtx4927.h b/include/asm-mips/txx9/rbtx4927.h
index bf194589216f..6fcec912c143 100644
--- a/include/asm-mips/txx9/rbtx4927.h
+++ b/include/asm-mips/txx9/rbtx4927.h
@@ -34,7 +34,23 @@
34#define RBTX4927_PCIIO 0x16000000 34#define RBTX4927_PCIIO 0x16000000
35#define RBTX4927_PCIIO_SIZE 0x01000000 35#define RBTX4927_PCIIO_SIZE 0x01000000
36 36
37#define rbtx4927_pcireset_addr ((__u8 __iomem *)0xbc00f006UL) 37#define RBTX4927_IMASK_ADDR (IO_BASE + TXX9_CE(2) + 0x00002000)
38#define RBTX4927_IMSTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x00002006)
39#define RBTX4927_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f000)
40#define RBTX4927_SOFTRESETLOCK_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f002)
41#define RBTX4927_PCIRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f006)
42#define RBTX4927_BRAMRTC_BASE (IO_BASE + TXX9_CE(2) + 0x00010000)
43#define RBTX4927_ETHER_BASE (IO_BASE + TXX9_CE(2) + 0x00020000)
44
45/* Ethernet port address */
46#define RBTX4927_ETHER_ADDR (RBTX4927_ETHER_BASE + 0x280)
47
48#define rbtx4927_imask_addr ((__u8 __iomem *)RBTX4927_IMASK_ADDR)
49#define rbtx4927_imstat_addr ((__u8 __iomem *)RBTX4927_IMSTAT_ADDR)
50#define rbtx4927_softreset_addr ((__u8 __iomem *)RBTX4927_SOFTRESET_ADDR)
51#define rbtx4927_softresetlock_addr \
52 ((__u8 __iomem *)RBTX4927_SOFTRESETLOCK_ADDR)
53#define rbtx4927_pcireset_addr ((__u8 __iomem *)RBTX4927_PCIRESET_ADDR)
38 54
39/* bits for ISTAT/IMASK/IMSTAT */ 55/* bits for ISTAT/IMASK/IMSTAT */
40#define RBTX4927_INTB_PCID 0 56#define RBTX4927_INTB_PCID 0
@@ -62,13 +78,7 @@
62#define RBTX4927_ISA_IO_OFFSET 0 78#define RBTX4927_ISA_IO_OFFSET 0
63#endif 79#endif
64 80
65#define RBTX4927_SW_RESET_DO (void __iomem *)0xbc00f000UL 81#define RBTX4927_RTL_8019_BASE (RBTX4927_ETHER_ADDR - mips_io_port_base)
66#define RBTX4927_SW_RESET_DO_SET 0x01
67
68#define RBTX4927_SW_RESET_ENABLE (void __iomem *)0xbc00f002UL
69#define RBTX4927_SW_RESET_ENABLE_SET 0x01
70
71#define RBTX4927_RTL_8019_BASE (0x1c020280 - RBTX4927_ISA_IO_OFFSET)
72#define RBTX4927_RTL_8019_IRQ (TXX9_IRQ_BASE + TX4927_IR_INT(3)) 82#define RBTX4927_RTL_8019_IRQ (TXX9_IRQ_BASE + TX4927_IR_INT(3))
73 83
74void rbtx4927_prom_init(void); 84void rbtx4927_prom_init(void);
diff --git a/include/asm-mips/txx9/rbtx4938.h b/include/asm-mips/txx9/rbtx4938.h
index 2f5d5e705a41..9f0441a28126 100644
--- a/include/asm-mips/txx9/rbtx4938.h
+++ b/include/asm-mips/txx9/rbtx4938.h
@@ -15,35 +15,31 @@
15#include <asm/txx9irq.h> 15#include <asm/txx9irq.h>
16#include <asm/txx9/tx4938.h> 16#include <asm/txx9/tx4938.h>
17 17
18/* CS */
19#define RBTX4938_CE0 0x1c000000 /* 64M */
20#define RBTX4938_CE2 0x17f00000 /* 1M */
21
22/* Address map */ 18/* Address map */
23#define RBTX4938_FPGA_REG_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000000) 19#define RBTX4938_FPGA_REG_ADDR (IO_BASE + TXX9_CE(2) + 0x00000000)
24#define RBTX4938_FPGA_REV_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000002) 20#define RBTX4938_FPGA_REV_ADDR (IO_BASE + TXX9_CE(2) + 0x00000002)
25#define RBTX4938_CONFIG1_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000004) 21#define RBTX4938_CONFIG1_ADDR (IO_BASE + TXX9_CE(2) + 0x00000004)
26#define RBTX4938_CONFIG2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000006) 22#define RBTX4938_CONFIG2_ADDR (IO_BASE + TXX9_CE(2) + 0x00000006)
27#define RBTX4938_CONFIG3_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000008) 23#define RBTX4938_CONFIG3_ADDR (IO_BASE + TXX9_CE(2) + 0x00000008)
28#define RBTX4938_LED_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001000) 24#define RBTX4938_LED_ADDR (IO_BASE + TXX9_CE(2) + 0x00001000)
29#define RBTX4938_DIPSW_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001002) 25#define RBTX4938_DIPSW_ADDR (IO_BASE + TXX9_CE(2) + 0x00001002)
30#define RBTX4938_BDIPSW_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001004) 26#define RBTX4938_BDIPSW_ADDR (IO_BASE + TXX9_CE(2) + 0x00001004)
31#define RBTX4938_IMASK_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002000) 27#define RBTX4938_IMASK_ADDR (IO_BASE + TXX9_CE(2) + 0x00002000)
32#define RBTX4938_IMASK2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002002) 28#define RBTX4938_IMASK2_ADDR (IO_BASE + TXX9_CE(2) + 0x00002002)
33#define RBTX4938_INTPOL_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002004) 29#define RBTX4938_INTPOL_ADDR (IO_BASE + TXX9_CE(2) + 0x00002004)
34#define RBTX4938_ISTAT_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002006) 30#define RBTX4938_ISTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x00002006)
35#define RBTX4938_ISTAT2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002008) 31#define RBTX4938_ISTAT2_ADDR (IO_BASE + TXX9_CE(2) + 0x00002008)
36#define RBTX4938_IMSTAT_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000200a) 32#define RBTX4938_IMSTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x0000200a)
37#define RBTX4938_IMSTAT2_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000200c) 33#define RBTX4938_IMSTAT2_ADDR (IO_BASE + TXX9_CE(2) + 0x0000200c)
38#define RBTX4938_SOFTINT_ADDR (KSEG1 + RBTX4938_CE2 + 0x00003000) 34#define RBTX4938_SOFTINT_ADDR (IO_BASE + TXX9_CE(2) + 0x00003000)
39#define RBTX4938_PIOSEL_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005000) 35#define RBTX4938_PIOSEL_ADDR (IO_BASE + TXX9_CE(2) + 0x00005000)
40#define RBTX4938_SPICS_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005002) 36#define RBTX4938_SPICS_ADDR (IO_BASE + TXX9_CE(2) + 0x00005002)
41#define RBTX4938_SFPWR_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005008) 37#define RBTX4938_SFPWR_ADDR (IO_BASE + TXX9_CE(2) + 0x00005008)
42#define RBTX4938_SFVOL_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000500a) 38#define RBTX4938_SFVOL_ADDR (IO_BASE + TXX9_CE(2) + 0x0000500a)
43#define RBTX4938_SOFTRESET_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007000) 39#define RBTX4938_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x00007000)
44#define RBTX4938_SOFTRESETLOCK_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007002) 40#define RBTX4938_SOFTRESETLOCK_ADDR (IO_BASE + TXX9_CE(2) + 0x00007002)
45#define RBTX4938_PCIRESET_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007004) 41#define RBTX4938_PCIRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x00007004)
46#define RBTX4938_ETHER_BASE (KSEG1 + RBTX4938_CE2 + 0x00020000) 42#define RBTX4938_ETHER_BASE (IO_BASE + TXX9_CE(2) + 0x00020000)
47 43
48/* Ethernet port address (Jumperless Mode (W12:Open)) */ 44/* Ethernet port address (Jumperless Mode (W12:Open)) */
49#define RBTX4938_ETHER_ADDR (RBTX4938_ETHER_BASE + 0x280) 45#define RBTX4938_ETHER_ADDR (RBTX4938_ETHER_BASE + 0x280)
diff --git a/include/asm-mips/txx9/tx3927.h b/include/asm-mips/txx9/tx3927.h
index ca414c7624e1..ea79e1b16e71 100644
--- a/include/asm-mips/txx9/tx3927.h
+++ b/include/asm-mips/txx9/tx3927.h
@@ -10,17 +10,18 @@
10 10
11#include <asm/txx9/txx927.h> 11#include <asm/txx9/txx927.h>
12 12
13#define TX3927_SDRAMC_REG 0xfffe8000 13#define TX3927_REG_BASE 0xfffe0000UL
14#define TX3927_ROMC_REG 0xfffe9000 14#define TX3927_SDRAMC_REG (TX3927_REG_BASE + 0x8000)
15#define TX3927_DMA_REG 0xfffeb000 15#define TX3927_ROMC_REG (TX3927_REG_BASE + 0x9000)
16#define TX3927_IRC_REG 0xfffec000 16#define TX3927_DMA_REG (TX3927_REG_BASE + 0xb000)
17#define TX3927_PCIC_REG 0xfffed000 17#define TX3927_IRC_REG (TX3927_REG_BASE + 0xc000)
18#define TX3927_CCFG_REG 0xfffee000 18#define TX3927_PCIC_REG (TX3927_REG_BASE + 0xd000)
19#define TX3927_CCFG_REG (TX3927_REG_BASE + 0xe000)
19#define TX3927_NR_TMR 3 20#define TX3927_NR_TMR 3
20#define TX3927_TMR_REG(ch) (0xfffef000 + (ch) * 0x100) 21#define TX3927_TMR_REG(ch) (TX3927_REG_BASE + 0xf000 + (ch) * 0x100)
21#define TX3927_NR_SIO 2 22#define TX3927_NR_SIO 2
22#define TX3927_SIO_REG(ch) (0xfffef300 + (ch) * 0x100) 23#define TX3927_SIO_REG(ch) (TX3927_REG_BASE + 0xf300 + (ch) * 0x100)
23#define TX3927_PIO_REG 0xfffef500 24#define TX3927_PIO_REG (TX3927_REG_BASE + 0xf500)
24 25
25struct tx3927_sdramc_reg { 26struct tx3927_sdramc_reg {
26 volatile unsigned long cr[8]; 27 volatile unsigned long cr[8];
diff --git a/include/asm-mips/txx9/tx4927.h b/include/asm-mips/txx9/tx4927.h
index 46d60afc038b..ceb4b79ff4e3 100644
--- a/include/asm-mips/txx9/tx4927.h
+++ b/include/asm-mips/txx9/tx4927.h
@@ -32,32 +32,46 @@
32#include <asm/txx9irq.h> 32#include <asm/txx9irq.h>
33#include <asm/txx9/tx4927pcic.h> 33#include <asm/txx9/tx4927pcic.h>
34 34
35#define TX4927_SDRAMC_REG 0xff1f8000 35#ifdef CONFIG_64BIT
36#define TX4927_EBUSC_REG 0xff1f9000 36#define TX4927_REG_BASE 0xffffffffff1f0000UL
37#define TX4927_PCIC_REG 0xff1fd000 37#else
38#define TX4927_CCFG_REG 0xff1fe000 38#define TX4927_REG_BASE 0xff1f0000UL
39#define TX4927_IRC_REG 0xff1ff600 39#endif
40#define TX4927_REG_SIZE 0x00010000
41
42#define TX4927_SDRAMC_REG (TX4927_REG_BASE + 0x8000)
43#define TX4927_EBUSC_REG (TX4927_REG_BASE + 0x9000)
44#define TX4927_PCIC_REG (TX4927_REG_BASE + 0xd000)
45#define TX4927_CCFG_REG (TX4927_REG_BASE + 0xe000)
46#define TX4927_IRC_REG (TX4927_REG_BASE + 0xf600)
40#define TX4927_NR_TMR 3 47#define TX4927_NR_TMR 3
41#define TX4927_TMR_REG(ch) (0xff1ff000 + (ch) * 0x100) 48#define TX4927_TMR_REG(ch) (TX4927_REG_BASE + 0xf000 + (ch) * 0x100)
49#define TX4927_NR_SIO 2
50#define TX4927_SIO_REG(ch) (TX4927_REG_BASE + 0xf300 + (ch) * 0x100)
51#define TX4927_PIO_REG (TX4927_REG_BASE + 0xf500)
42 52
43#define TX4927_IR_INT(n) (2 + (n)) 53#define TX4927_IR_INT(n) (2 + (n))
44#define TX4927_IR_SIO(n) (8 + (n)) 54#define TX4927_IR_SIO(n) (8 + (n))
45#define TX4927_IR_PCIC 16 55#define TX4927_IR_PCIC 16
56#define TX4927_NUM_IR_TMR 3
57#define TX4927_IR_TMR(n) (17 + (n))
46#define TX4927_IR_PCIERR 22 58#define TX4927_IR_PCIERR 22
47#define TX4927_NUM_IR 32 59#define TX4927_NUM_IR 32
48 60
49#define TX4927_IRC_INT 2 /* IP[2] in Status register */ 61#define TX4927_IRC_INT 2 /* IP[2] in Status register */
50 62
63#define TX4927_NUM_PIO 16
64
51struct tx4927_sdramc_reg { 65struct tx4927_sdramc_reg {
52 volatile unsigned long long cr[4]; 66 u64 cr[4];
53 volatile unsigned long long unused0[4]; 67 u64 unused0[4];
54 volatile unsigned long long tr; 68 u64 tr;
55 volatile unsigned long long unused1[2]; 69 u64 unused1[2];
56 volatile unsigned long long cmd; 70 u64 cmd;
57}; 71};
58 72
59struct tx4927_ebusc_reg { 73struct tx4927_ebusc_reg {
60 volatile unsigned long long cr[8]; 74 u64 cr[8];
61}; 75};
62 76
63struct tx4927_ccfg_reg { 77struct tx4927_ccfg_reg {
@@ -160,12 +174,28 @@ struct tx4927_ccfg_reg {
160#define TX4927_CLKCTR_SIO0RST 0x00000002 174#define TX4927_CLKCTR_SIO0RST 0x00000002
161#define TX4927_CLKCTR_SIO1RST 0x00000001 175#define TX4927_CLKCTR_SIO1RST 0x00000001
162 176
163#define tx4927_sdramcptr ((struct tx4927_sdramc_reg *)TX4927_SDRAMC_REG) 177#define tx4927_sdramcptr \
178 ((struct tx4927_sdramc_reg __iomem *)TX4927_SDRAMC_REG)
164#define tx4927_pcicptr \ 179#define tx4927_pcicptr \
165 ((struct tx4927_pcic_reg __iomem *)TX4927_PCIC_REG) 180 ((struct tx4927_pcic_reg __iomem *)TX4927_PCIC_REG)
166#define tx4927_ccfgptr \ 181#define tx4927_ccfgptr \
167 ((struct tx4927_ccfg_reg __iomem *)TX4927_CCFG_REG) 182 ((struct tx4927_ccfg_reg __iomem *)TX4927_CCFG_REG)
168#define tx4927_ebuscptr ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG) 183#define tx4927_ebuscptr \
184 ((struct tx4927_ebusc_reg __iomem *)TX4927_EBUSC_REG)
185#define tx4927_pioptr ((struct txx9_pio_reg __iomem *)TX4927_PIO_REG)
186
187#define TX4927_REV_PCODE() \
188 ((__u32)__raw_readq(&tx4927_ccfgptr->crir) >> 16)
189
190#define TX4927_SDRAMC_CR(ch) __raw_readq(&tx4927_sdramcptr->cr[(ch)])
191#define TX4927_SDRAMC_BA(ch) ((TX4927_SDRAMC_CR(ch) >> 49) << 21)
192#define TX4927_SDRAMC_SIZE(ch) \
193 ((((TX4927_SDRAMC_CR(ch) >> 33) & 0x7fff) + 1) << 21)
194
195#define TX4927_EBUSC_CR(ch) __raw_readq(&tx4927_ebuscptr->cr[(ch)])
196#define TX4927_EBUSC_BA(ch) ((TX4927_EBUSC_CR(ch) >> 48) << 20)
197#define TX4927_EBUSC_SIZE(ch) \
198 (0x00100000 << ((unsigned long)(TX4927_EBUSC_CR(ch) >> 8) & 0xf))
169 199
170/* utilities */ 200/* utilities */
171static inline void txx9_clear64(__u64 __iomem *adr, __u64 bits) 201static inline void txx9_clear64(__u64 __iomem *adr, __u64 bits)
@@ -212,6 +242,11 @@ static inline void tx4927_ccfg_change(__u64 change, __u64 new)
212 &tx4927_ccfgptr->ccfg); 242 &tx4927_ccfgptr->ccfg);
213} 243}
214 244
245unsigned int tx4927_get_mem_size(void);
246void tx4927_wdr_init(void);
247void tx4927_setup(void);
248void tx4927_time_init(unsigned int tmrnr);
249void tx4927_setup_serial(void);
215int tx4927_report_pciclk(void); 250int tx4927_report_pciclk(void);
216int tx4927_pciclk66_setup(void); 251int tx4927_pciclk66_setup(void);
217void tx4927_irq_init(void); 252void tx4927_irq_init(void);
diff --git a/include/asm-mips/txx9/tx4938.h b/include/asm-mips/txx9/tx4938.h
index 12de68a4c10a..1ed969d381d6 100644
--- a/include/asm-mips/txx9/tx4938.h
+++ b/include/asm-mips/txx9/tx4938.h
@@ -15,20 +15,11 @@
15/* some controllers are compatible with 4927 */ 15/* some controllers are compatible with 4927 */
16#include <asm/txx9/tx4927.h> 16#include <asm/txx9/tx4927.h>
17 17
18#define tx4938_read_nfmc(addr) (*(volatile unsigned int *)(addr)) 18#ifdef CONFIG_64BIT
19#define tx4938_write_nfmc(b, addr) (*(volatile unsigned int *)(addr)) = (b) 19#define TX4938_REG_BASE 0xffffffffff1f0000UL /* == TX4937_REG_BASE */
20 20#else
21#define TX4938_PCIIO_0 0x10000000 21#define TX4938_REG_BASE 0xff1f0000UL /* == TX4937_REG_BASE */
22#define TX4938_PCIIO_1 0x01010000 22#endif
23#define TX4938_PCIMEM_0 0x08000000
24#define TX4938_PCIMEM_1 0x11000000
25
26#define TX4938_PCIIO_SIZE_0 0x01000000
27#define TX4938_PCIIO_SIZE_1 0x00010000
28#define TX4938_PCIMEM_SIZE_0 0x08000000
29#define TX4938_PCIMEM_SIZE_1 0x00010000
30
31#define TX4938_REG_BASE 0xff1f0000 /* == TX4937_REG_BASE */
32#define TX4938_REG_SIZE 0x00010000 /* == TX4937_REG_SIZE */ 23#define TX4938_REG_SIZE 0x00010000 /* == TX4937_REG_SIZE */
33 24
34/* NDFMC, SRAMC, PCIC1, SPIC: TX4938 only */ 25/* NDFMC, SRAMC, PCIC1, SPIC: TX4938 only */
@@ -49,149 +40,8 @@
49#define TX4938_ACLC_REG (TX4938_REG_BASE + 0xf700) 40#define TX4938_ACLC_REG (TX4938_REG_BASE + 0xf700)
50#define TX4938_SPI_REG (TX4938_REG_BASE + 0xf800) 41#define TX4938_SPI_REG (TX4938_REG_BASE + 0xf800)
51 42
52#define _CONST64(c) c##ull
53
54#include <asm/byteorder.h>
55
56#ifdef __BIG_ENDIAN
57#define endian_def_l2(e1, e2) \
58 volatile unsigned long e1, e2
59#define endian_def_s2(e1, e2) \
60 volatile unsigned short e1, e2
61#define endian_def_sb2(e1, e2, e3) \
62 volatile unsigned short e1;volatile unsigned char e2, e3
63#define endian_def_b2s(e1, e2, e3) \
64 volatile unsigned char e1, e2;volatile unsigned short e3
65#define endian_def_b4(e1, e2, e3, e4) \
66 volatile unsigned char e1, e2, e3, e4
67#else
68#define endian_def_l2(e1, e2) \
69 volatile unsigned long e2, e1
70#define endian_def_s2(e1, e2) \
71 volatile unsigned short e2, e1
72#define endian_def_sb2(e1, e2, e3) \
73 volatile unsigned char e3, e2;volatile unsigned short e1
74#define endian_def_b2s(e1, e2, e3) \
75 volatile unsigned short e3;volatile unsigned char e2, e1
76#define endian_def_b4(e1, e2, e3, e4) \
77 volatile unsigned char e4, e3, e2, e1
78#endif
79
80
81struct tx4938_sdramc_reg {
82 volatile unsigned long long cr[4];
83 volatile unsigned long long unused0[4];
84 volatile unsigned long long tr;
85 volatile unsigned long long unused1[2];
86 volatile unsigned long long cmd;
87 volatile unsigned long long sfcmd;
88};
89
90struct tx4938_ebusc_reg {
91 volatile unsigned long long cr[8];
92};
93
94struct tx4938_dma_reg {
95 struct tx4938_dma_ch_reg {
96 volatile unsigned long long cha;
97 volatile unsigned long long sar;
98 volatile unsigned long long dar;
99 endian_def_l2(unused0, cntr);
100 endian_def_l2(unused1, sair);
101 endian_def_l2(unused2, dair);
102 endian_def_l2(unused3, ccr);
103 endian_def_l2(unused4, csr);
104 } ch[4];
105 volatile unsigned long long dbr[8];
106 volatile unsigned long long tdhr;
107 volatile unsigned long long midr;
108 endian_def_l2(unused0, mcr);
109};
110
111struct tx4938_aclc_reg {
112 volatile unsigned long acctlen;
113 volatile unsigned long acctldis;
114 volatile unsigned long acregacc;
115 volatile unsigned long unused0;
116 volatile unsigned long acintsts;
117 volatile unsigned long acintmsts;
118 volatile unsigned long acinten;
119 volatile unsigned long acintdis;
120 volatile unsigned long acsemaph;
121 volatile unsigned long unused1[7];
122 volatile unsigned long acgpidat;
123 volatile unsigned long acgpodat;
124 volatile unsigned long acslten;
125 volatile unsigned long acsltdis;
126 volatile unsigned long acfifosts;
127 volatile unsigned long unused2[11];
128 volatile unsigned long acdmasts;
129 volatile unsigned long acdmasel;
130 volatile unsigned long unused3[6];
131 volatile unsigned long acaudodat;
132 volatile unsigned long acsurrdat;
133 volatile unsigned long accentdat;
134 volatile unsigned long aclfedat;
135 volatile unsigned long acaudiat;
136 volatile unsigned long unused4;
137 volatile unsigned long acmodoat;
138 volatile unsigned long acmodidat;
139 volatile unsigned long unused5[15];
140 volatile unsigned long acrevid;
141};
142
143
144struct tx4938_tmr_reg {
145 volatile unsigned long tcr;
146 volatile unsigned long tisr;
147 volatile unsigned long cpra;
148 volatile unsigned long cprb;
149 volatile unsigned long itmr;
150 volatile unsigned long unused0[3];
151 volatile unsigned long ccdr;
152 volatile unsigned long unused1[3];
153 volatile unsigned long pgmr;
154 volatile unsigned long unused2[3];
155 volatile unsigned long wtmr;
156 volatile unsigned long unused3[43];
157 volatile unsigned long trr;
158};
159
160struct tx4938_sio_reg {
161 volatile unsigned long lcr;
162 volatile unsigned long dicr;
163 volatile unsigned long disr;
164 volatile unsigned long cisr;
165 volatile unsigned long fcr;
166 volatile unsigned long flcr;
167 volatile unsigned long bgr;
168 volatile unsigned long tfifo;
169 volatile unsigned long rfifo;
170};
171
172struct tx4938_ndfmc_reg {
173 endian_def_l2(unused0, dtr);
174 endian_def_l2(unused1, mcr);
175 endian_def_l2(unused2, sr);
176 endian_def_l2(unused3, isr);
177 endian_def_l2(unused4, imr);
178 endian_def_l2(unused5, spr);
179 endian_def_l2(unused6, rstr);
180};
181
182struct tx4938_spi_reg {
183 volatile unsigned long mcr;
184 volatile unsigned long cr0;
185 volatile unsigned long cr1;
186 volatile unsigned long fs;
187 volatile unsigned long unused1;
188 volatile unsigned long sr;
189 volatile unsigned long dr;
190 volatile unsigned long unused2;
191};
192
193struct tx4938_sramc_reg { 43struct tx4938_sramc_reg {
194 volatile unsigned long long cr; 44 u64 cr;
195}; 45};
196 46
197struct tx4938_ccfg_reg { 47struct tx4938_ccfg_reg {
@@ -209,34 +59,6 @@ struct tx4938_ccfg_reg {
209 u64 jmpadr; 59 u64 jmpadr;
210}; 60};
211 61
212#undef endian_def_l2
213#undef endian_def_s2
214#undef endian_def_sb2
215#undef endian_def_b2s
216#undef endian_def_b4
217
218/*
219 * NDFMC
220 */
221
222/* NDFMCR : NDFMC Mode Control */
223#define TX4938_NDFMCR_WE 0x80
224#define TX4938_NDFMCR_ECC_ALL 0x60
225#define TX4938_NDFMCR_ECC_RESET 0x60
226#define TX4938_NDFMCR_ECC_READ 0x40
227#define TX4938_NDFMCR_ECC_ON 0x20
228#define TX4938_NDFMCR_ECC_OFF 0x00
229#define TX4938_NDFMCR_CE 0x10
230#define TX4938_NDFMCR_BSPRT 0x04
231#define TX4938_NDFMCR_ALE 0x02
232#define TX4938_NDFMCR_CLE 0x01
233
234/* NDFMCR : NDFMC Status */
235#define TX4938_NDFSR_BUSY 0x80
236
237/* NDFMCR : NDFMC Reset */
238#define TX4938_NDFRSTR_RST 0x01
239
240/* 62/*
241 * IRC 63 * IRC
242 */ 64 */
@@ -268,13 +90,15 @@ struct tx4938_ccfg_reg {
268 90
269#define TX4938_IRC_INT 2 /* IP[2] in Status register */ 91#define TX4938_IRC_INT 2 /* IP[2] in Status register */
270 92
93#define TX4938_NUM_PIO 16
94
271/* 95/*
272 * CCFG 96 * CCFG
273 */ 97 */
274/* CCFG : Chip Configuration */ 98/* CCFG : Chip Configuration */
275#define TX4938_CCFG_WDRST _CONST64(0x0000020000000000) 99#define TX4938_CCFG_WDRST 0x0000020000000000ULL
276#define TX4938_CCFG_WDREXEN _CONST64(0x0000010000000000) 100#define TX4938_CCFG_WDREXEN 0x0000010000000000ULL
277#define TX4938_CCFG_BCFG_MASK _CONST64(0x000000ff00000000) 101#define TX4938_CCFG_BCFG_MASK 0x000000ff00000000ULL
278#define TX4938_CCFG_TINTDIS 0x01000000 102#define TX4938_CCFG_TINTDIS 0x01000000
279#define TX4938_CCFG_PCI66 0x00800000 103#define TX4938_CCFG_PCI66 0x00800000
280#define TX4938_CCFG_PCIMODE 0x00400000 104#define TX4938_CCFG_PCIMODE 0x00400000
@@ -310,12 +134,12 @@ struct tx4938_ccfg_reg {
310#define TX4938_CCFG_ACEHOLD 0x00000001 134#define TX4938_CCFG_ACEHOLD 0x00000001
311 135
312/* PCFG : Pin Configuration */ 136/* PCFG : Pin Configuration */
313#define TX4938_PCFG_ETH0_SEL _CONST64(0x8000000000000000) 137#define TX4938_PCFG_ETH0_SEL 0x8000000000000000ULL
314#define TX4938_PCFG_ETH1_SEL _CONST64(0x4000000000000000) 138#define TX4938_PCFG_ETH1_SEL 0x4000000000000000ULL
315#define TX4938_PCFG_ATA_SEL _CONST64(0x2000000000000000) 139#define TX4938_PCFG_ATA_SEL 0x2000000000000000ULL
316#define TX4938_PCFG_ISA_SEL _CONST64(0x1000000000000000) 140#define TX4938_PCFG_ISA_SEL 0x1000000000000000ULL
317#define TX4938_PCFG_SPI_SEL _CONST64(0x0800000000000000) 141#define TX4938_PCFG_SPI_SEL 0x0800000000000000ULL
318#define TX4938_PCFG_NDF_SEL _CONST64(0x0400000000000000) 142#define TX4938_PCFG_NDF_SEL 0x0400000000000000ULL
319#define TX4938_PCFG_SDCLKDLY_MASK 0x30000000 143#define TX4938_PCFG_SDCLKDLY_MASK 0x30000000
320#define TX4938_PCFG_SDCLKDLY(d) ((d)<<28) 144#define TX4938_PCFG_SDCLKDLY(d) ((d)<<28)
321#define TX4938_PCFG_SYSCLKEN 0x08000000 145#define TX4938_PCFG_SYSCLKEN 0x08000000
@@ -336,8 +160,8 @@ struct tx4938_ccfg_reg {
336#define TX4938_PCFG_DMASEL3_SIO0 0x00000008 160#define TX4938_PCFG_DMASEL3_SIO0 0x00000008
337 161
338/* CLKCTR : Clock Control */ 162/* CLKCTR : Clock Control */
339#define TX4938_CLKCTR_NDFCKD _CONST64(0x0001000000000000) 163#define TX4938_CLKCTR_NDFCKD 0x0001000000000000ULL
340#define TX4938_CLKCTR_NDFRST _CONST64(0x0000000100000000) 164#define TX4938_CLKCTR_NDFRST 0x0000000100000000ULL
341#define TX4938_CLKCTR_ETH1CKD 0x80000000 165#define TX4938_CLKCTR_ETH1CKD 0x80000000
342#define TX4938_CLKCTR_ETH0CKD 0x40000000 166#define TX4938_CLKCTR_ETH0CKD 0x40000000
343#define TX4938_CLKCTR_SPICKD 0x20000000 167#define TX4938_CLKCTR_SPICKD 0x20000000
@@ -424,20 +248,16 @@ struct tx4938_ccfg_reg {
424#define TX4938_DMA_CSR_DESERR 0x00000002 248#define TX4938_DMA_CSR_DESERR 0x00000002
425#define TX4938_DMA_CSR_SORERR 0x00000001 249#define TX4938_DMA_CSR_SORERR 0x00000001
426 250
427#define tx4938_sdramcptr ((struct tx4938_sdramc_reg *)TX4938_SDRAMC_REG) 251#define tx4938_sdramcptr tx4927_sdramcptr
428#define tx4938_ebuscptr ((struct tx4938_ebusc_reg *)TX4938_EBUSC_REG) 252#define tx4938_ebuscptr tx4927_ebuscptr
429#define tx4938_dmaptr(ch) ((struct tx4938_dma_reg *)TX4938_DMA_REG(ch))
430#define tx4938_ndfmcptr ((struct tx4938_ndfmc_reg *)TX4938_NDFMC_REG)
431#define tx4938_pcicptr tx4927_pcicptr 253#define tx4938_pcicptr tx4927_pcicptr
432#define tx4938_pcic1ptr \ 254#define tx4938_pcic1ptr \
433 ((struct tx4927_pcic_reg __iomem *)TX4938_PCIC1_REG) 255 ((struct tx4927_pcic_reg __iomem *)TX4938_PCIC1_REG)
434#define tx4938_ccfgptr \ 256#define tx4938_ccfgptr \
435 ((struct tx4938_ccfg_reg __iomem *)TX4938_CCFG_REG) 257 ((struct tx4938_ccfg_reg __iomem *)TX4938_CCFG_REG)
436#define tx4938_sioptr(ch) ((struct tx4938_sio_reg *)TX4938_SIO_REG(ch))
437#define tx4938_pioptr ((struct txx9_pio_reg __iomem *)TX4938_PIO_REG) 258#define tx4938_pioptr ((struct txx9_pio_reg __iomem *)TX4938_PIO_REG)
438#define tx4938_aclcptr ((struct tx4938_aclc_reg *)TX4938_ACLC_REG) 259#define tx4938_sramcptr \
439#define tx4938_spiptr ((struct tx4938_spi_reg *)TX4938_SPI_REG) 260 ((struct tx4938_sramc_reg __iomem *)TX4938_SRAMC_REG)
440#define tx4938_sramcptr ((struct tx4938_sramc_reg *)TX4938_SRAMC_REG)
441 261
442 262
443#define TX4938_REV_PCODE() \ 263#define TX4938_REV_PCODE() \
@@ -447,14 +267,19 @@ struct tx4938_ccfg_reg {
447#define tx4938_ccfg_set(bits) tx4927_ccfg_set(bits) 267#define tx4938_ccfg_set(bits) tx4927_ccfg_set(bits)
448#define tx4938_ccfg_change(change, new) tx4927_ccfg_change(change, new) 268#define tx4938_ccfg_change(change, new) tx4927_ccfg_change(change, new)
449 269
450#define TX4938_SDRAMC_BA(ch) ((tx4938_sdramcptr->cr[ch] >> 49) << 21) 270#define TX4938_SDRAMC_CR(ch) TX4927_SDRAMC_CR(ch)
451#define TX4938_SDRAMC_SIZE(ch) (((tx4938_sdramcptr->cr[ch] >> 33) + 1) << 21) 271#define TX4938_SDRAMC_BA(ch) TX4927_SDRAMC_BA(ch)
272#define TX4938_SDRAMC_SIZE(ch) TX4927_SDRAMC_SIZE(ch)
452 273
453#define TX4938_EBUSC_CR(ch) __raw_readq(&tx4938_ebuscptr->cr[(ch)]) 274#define TX4938_EBUSC_CR(ch) TX4927_EBUSC_CR(ch)
454#define TX4938_EBUSC_BA(ch) ((tx4938_ebuscptr->cr[ch] >> 48) << 20) 275#define TX4938_EBUSC_BA(ch) TX4927_EBUSC_BA(ch)
455#define TX4938_EBUSC_SIZE(ch) \ 276#define TX4938_EBUSC_SIZE(ch) TX4927_EBUSC_SIZE(ch)
456 (0x00100000 << ((unsigned long)(tx4938_ebuscptr->cr[ch] >> 8) & 0xf))
457 277
278#define tx4938_get_mem_size() tx4927_get_mem_size()
279void tx4938_wdr_init(void);
280void tx4938_setup(void);
281void tx4938_time_init(unsigned int tmrnr);
282void tx4938_setup_serial(void);
458int tx4938_report_pciclk(void); 283int tx4938_report_pciclk(void);
459void tx4938_report_pci1clk(void); 284void tx4938_report_pci1clk(void);
460int tx4938_pciclk66_setup(void); 285int tx4938_pciclk66_setup(void);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-17 12:25:21 -0500