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-rw-r--r--MAINTAINERS3
-rw-r--r--arch/arm/mach-shmobile/board-ap4evb.c106
-rw-r--r--arch/arm/mach-shmobile/board-g4evm.c127
-rw-r--r--arch/arm/mach-shmobile/include/mach/irqs.h6
-rw-r--r--arch/arm/mach-shmobile/intc-sh7367.c178
-rw-r--r--arch/arm/mach-shmobile/intc-sh7372.c12
-rw-r--r--arch/arm/mach-shmobile/intc-sh7377.c300
-rw-r--r--arch/arm/mach-shmobile/setup-sh7372.c47
-rw-r--r--drivers/dma/Kconfig2
-rw-r--r--drivers/dma/shdma.c8
-rw-r--r--drivers/i2c/busses/Kconfig2
-rw-r--r--drivers/i2c/busses/i2c-sh_mobile.c121
-rw-r--r--include/linux/serial_sci.h2
13 files changed, 851 insertions, 63 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index 8e019486b006..552e0b692f25 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -955,8 +955,9 @@ ARM/SHMOBILE ARM ARCHITECTURE
955M: Paul Mundt <lethal@linux-sh.org> 955M: Paul Mundt <lethal@linux-sh.org>
956M: Magnus Damm <magnus.damm@gmail.com> 956M: Magnus Damm <magnus.damm@gmail.com>
957L: linux-sh@vger.kernel.org 957L: linux-sh@vger.kernel.org
958T: git git://git.kernel.org/pub/scm/linux/kernel/git/lethal/genesis-2.6.git
959W: http://oss.renesas.com 958W: http://oss.renesas.com
959Q: http://patchwork.kernel.org/project/linux-sh/list/
960T: git git://git.kernel.org/pub/scm/linux/kernel/git/lethal/genesis-2.6.git
960S: Supported 961S: Supported
961F: arch/arm/mach-shmobile/ 962F: arch/arm/mach-shmobile/
962F: drivers/sh/ 963F: drivers/sh/
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index 1c2ec96ce261..d3b8ca5d4041 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -26,11 +26,14 @@
26#include <linux/mtd/mtd.h> 26#include <linux/mtd/mtd.h>
27#include <linux/mtd/partitions.h> 27#include <linux/mtd/partitions.h>
28#include <linux/mtd/physmap.h> 28#include <linux/mtd/physmap.h>
29#include <linux/i2c.h>
30#include <linux/i2c/tsc2007.h>
29#include <linux/io.h> 31#include <linux/io.h>
30#include <linux/smsc911x.h> 32#include <linux/smsc911x.h>
31#include <linux/gpio.h> 33#include <linux/gpio.h>
32#include <linux/input.h> 34#include <linux/input.h>
33#include <linux/input/sh_keysc.h> 35#include <linux/input/sh_keysc.h>
36#include <linux/usb/r8a66597.h>
34#include <mach/common.h> 37#include <mach/common.h>
35#include <mach/sh7372.h> 38#include <mach/sh7372.h>
36#include <asm/mach-types.h> 39#include <asm/mach-types.h>
@@ -80,12 +83,25 @@
80 */ 83 */
81 84
82/* 85/*
83 * KEYSC 86 * LCD / IRQ / KEYSC / IrDA
84 * 87 *
85 * SW43 KEYSC 88 * IRQ = IRQ26 (TS), IRQ27 (VIO), IRQ28 (TouchScreen)
86 * ------------------------- 89 * LCD = 2nd LCDC
87 * ON enable 90 *
88 * OFF disable 91 * | SW43 |
92 * SW3 | ON | OFF |
93 * -------------+-----------------------+---------------+
94 * ON | KEY / IrDA | LCD |
95 * OFF | KEY / IrDA / IRQ | IRQ |
96 */
97
98/*
99 * USB
100 *
101 * J7 : 1-2 MAX3355E VBUS
102 * 2-3 DC 5.0V
103 *
104 * S39: bit2: off
89 */ 105 */
90 106
91/* MTD */ 107/* MTD */
@@ -227,11 +243,73 @@ static struct platform_device sdhi0_device = {
227 .id = 0, 243 .id = 0,
228}; 244};
229 245
246/* USB1 */
247void usb1_host_port_power(int port, int power)
248{
249 if (!power) /* only power-on supported for now */
250 return;
251
252 /* set VBOUT/PWEN and EXTLP1 in DVSTCTR */
253 __raw_writew(__raw_readw(0xE68B0008) | 0x600, 0xE68B0008);
254}
255
256static struct r8a66597_platdata usb1_host_data = {
257 .on_chip = 1,
258 .port_power = usb1_host_port_power,
259};
260
261static struct resource usb1_host_resources[] = {
262 [0] = {
263 .name = "USBHS",
264 .start = 0xE68B0000,
265 .end = 0xE68B00E6 - 1,
266 .flags = IORESOURCE_MEM,
267 },
268 [1] = {
269 .start = 215,
270 .end = 215,
271 .flags = IORESOURCE_IRQ,
272 },
273};
274
275static struct platform_device usb1_host_device = {
276 .name = "r8a66597_hcd",
277 .id = 1,
278 .dev = {
279 .dma_mask = NULL, /* not use dma */
280 .coherent_dma_mask = 0xffffffff,
281 .platform_data = &usb1_host_data,
282 },
283 .num_resources = ARRAY_SIZE(usb1_host_resources),
284 .resource = usb1_host_resources,
285};
286
230static struct platform_device *ap4evb_devices[] __initdata = { 287static struct platform_device *ap4evb_devices[] __initdata = {
231 &nor_flash_device, 288 &nor_flash_device,
232 &smc911x_device, 289 &smc911x_device,
233 &keysc_device, 290 &keysc_device,
234 &sdhi0_device, 291 &sdhi0_device,
292 &usb1_host_device,
293};
294
295/* TouchScreen (Needs SW3 set to OFF) */
296#define IRQ28 396
297struct tsc2007_platform_data tsc2007_info = {
298 .model = 2007,
299 .x_plate_ohms = 180,
300};
301
302/* I2C */
303static struct i2c_board_info i2c1_devices[] = {
304 {
305 I2C_BOARD_INFO("r2025sd", 0x32),
306 },
307 {
308 I2C_BOARD_INFO("tsc2007", 0x48),
309 .type = "tsc2007",
310 .platform_data = &tsc2007_info,
311 .irq = IRQ28,
312 },
235}; 313};
236 314
237static struct map_desc ap4evb_io_desc[] __initdata = { 315static struct map_desc ap4evb_io_desc[] __initdata = {
@@ -318,6 +396,24 @@ static void __init ap4evb_init(void)
318 gpio_request(GPIO_FN_SDHID0_1, NULL); 396 gpio_request(GPIO_FN_SDHID0_1, NULL);
319 gpio_request(GPIO_FN_SDHID0_0, NULL); 397 gpio_request(GPIO_FN_SDHID0_0, NULL);
320 398
399 /* enable TouchScreen */
400 gpio_request(GPIO_FN_IRQ28_123, NULL);
401 set_irq_type(IRQ28, IRQ_TYPE_LEVEL_LOW);
402
403 i2c_register_board_info(1, i2c1_devices,
404 ARRAY_SIZE(i2c1_devices));
405
406 /* USB enable */
407 gpio_request(GPIO_FN_VBUS0_1, NULL);
408 gpio_request(GPIO_FN_IDIN_1_18, NULL);
409 gpio_request(GPIO_FN_PWEN_1_115, NULL);
410 gpio_request(GPIO_FN_OVCN_1_114, NULL);
411 gpio_request(GPIO_FN_EXTLP_1, NULL);
412 gpio_request(GPIO_FN_OVCN2_1, NULL);
413
414 /* setup USB phy */
415 __raw_writew(0x8a0a, 0xE6058130); /* USBCR2 */
416
321 sh7372_add_standard_devices(); 417 sh7372_add_standard_devices();
322 418
323 platform_add_devices(ap4evb_devices, ARRAY_SIZE(ap4evb_devices)); 419 platform_add_devices(ap4evb_devices, ARRAY_SIZE(ap4evb_devices));
diff --git a/arch/arm/mach-shmobile/board-g4evm.c b/arch/arm/mach-shmobile/board-g4evm.c
index 10673a90be52..33441d58cfa6 100644
--- a/arch/arm/mach-shmobile/board-g4evm.c
+++ b/arch/arm/mach-shmobile/board-g4evm.c
@@ -30,6 +30,7 @@
30#include <linux/io.h> 30#include <linux/io.h>
31#include <linux/input.h> 31#include <linux/input.h>
32#include <linux/input/sh_keysc.h> 32#include <linux/input/sh_keysc.h>
33#include <linux/mfd/sh_mobile_sdhi.h>
33#include <linux/gpio.h> 34#include <linux/gpio.h>
34#include <mach/sh7377.h> 35#include <mach/sh7377.h>
35#include <mach/common.h> 36#include <mach/common.h>
@@ -37,6 +38,31 @@
37#include <asm/mach/arch.h> 38#include <asm/mach/arch.h>
38#include <asm/mach/map.h> 39#include <asm/mach/map.h>
39 40
41/*
42 * SDHI
43 *
44 * SDHI0 : card detection is possible
45 * SDHI1 : card detection is impossible
46 *
47 * [G4-MAIN-BOARD]
48 * JP74 : short # DBG_2V8A for SDHI0
49 * JP75 : NC # DBG_3V3A for SDHI0
50 * JP76 : NC # DBG_3V3A_SD for SDHI0
51 * JP77 : NC # 3V3A_SDIO for SDHI1
52 * JP78 : short # DBG_2V8A for SDHI1
53 * JP79 : NC # DBG_3V3A for SDHI1
54 * JP80 : NC # DBG_3V3A_SD for SDHI1
55 *
56 * [G4-CORE-BOARD]
57 * S32 : all off # to dissever from G3-CORE_DBG board
58 * S33 : all off # to dissever from G3-CORE_DBG board
59 *
60 * [G3-CORE_DBG-BOARD]
61 * S1 : all off # to dissever from G3-CORE_DBG board
62 * S3 : all off # to dissever from G3-CORE_DBG board
63 * S4 : all off # to dissever from G3-CORE_DBG board
64 */
65
40static struct mtd_partition nor_flash_partitions[] = { 66static struct mtd_partition nor_flash_partitions[] = {
41 { 67 {
42 .name = "loader", 68 .name = "loader",
@@ -169,10 +195,53 @@ static struct platform_device keysc_device = {
169 }, 195 },
170}; 196};
171 197
198/* SDHI */
199static struct resource sdhi0_resources[] = {
200 [0] = {
201 .name = "SDHI0",
202 .start = 0xe6d50000,
203 .end = 0xe6d501ff,
204 .flags = IORESOURCE_MEM,
205 },
206 [1] = {
207 .start = 96,
208 .flags = IORESOURCE_IRQ,
209 },
210};
211
212static struct platform_device sdhi0_device = {
213 .name = "sh_mobile_sdhi",
214 .num_resources = ARRAY_SIZE(sdhi0_resources),
215 .resource = sdhi0_resources,
216 .id = 0,
217};
218
219static struct resource sdhi1_resources[] = {
220 [0] = {
221 .name = "SDHI1",
222 .start = 0xe6d60000,
223 .end = 0xe6d601ff,
224 .flags = IORESOURCE_MEM,
225 },
226 [1] = {
227 .start = 100,
228 .flags = IORESOURCE_IRQ,
229 },
230};
231
232static struct platform_device sdhi1_device = {
233 .name = "sh_mobile_sdhi",
234 .num_resources = ARRAY_SIZE(sdhi1_resources),
235 .resource = sdhi1_resources,
236 .id = 1,
237};
238
172static struct platform_device *g4evm_devices[] __initdata = { 239static struct platform_device *g4evm_devices[] __initdata = {
173 &nor_flash_device, 240 &nor_flash_device,
174 &usb_host_device, 241 &usb_host_device,
175 &keysc_device, 242 &keysc_device,
243 &sdhi0_device,
244 &sdhi1_device,
176}; 245};
177 246
178static struct map_desc g4evm_io_desc[] __initdata = { 247static struct map_desc g4evm_io_desc[] __initdata = {
@@ -197,6 +266,36 @@ static void __init g4evm_map_io(void)
197 shmobile_setup_console(); 266 shmobile_setup_console();
198} 267}
199 268
269#define GPIO_SDHID0_D0 0xe60520fc
270#define GPIO_SDHID0_D1 0xe60520fd
271#define GPIO_SDHID0_D2 0xe60520fe
272#define GPIO_SDHID0_D3 0xe60520ff
273#define GPIO_SDHICMD0 0xe6052100
274
275#define GPIO_SDHID1_D0 0xe6052103
276#define GPIO_SDHID1_D1 0xe6052104
277#define GPIO_SDHID1_D2 0xe6052105
278#define GPIO_SDHID1_D3 0xe6052106
279#define GPIO_SDHICMD1 0xe6052107
280
281/*
282 * FIXME !!
283 *
284 * gpio_pull_up is quick_hack.
285 *
286 * current gpio frame work doesn't have
287 * the method to control only pull up/down/free.
288 * this function should be replaced by correct gpio function
289 */
290static void __init gpio_pull_up(u32 addr)
291{
292 u8 data = __raw_readb(addr);
293
294 data &= 0x0F;
295 data |= 0xC0;
296 __raw_writeb(data, addr);
297}
298
200static void __init g4evm_init(void) 299static void __init g4evm_init(void)
201{ 300{
202 sh7377_pinmux_init(); 301 sh7377_pinmux_init();
@@ -253,6 +352,34 @@ static void __init g4evm_init(void)
253 gpio_request(GPIO_FN_PORT71_KEYIN5_PU, NULL); 352 gpio_request(GPIO_FN_PORT71_KEYIN5_PU, NULL);
254 gpio_request(GPIO_FN_PORT72_KEYIN6_PU, NULL); 353 gpio_request(GPIO_FN_PORT72_KEYIN6_PU, NULL);
255 354
355 /* SDHI0 */
356 gpio_request(GPIO_FN_SDHICLK0, NULL);
357 gpio_request(GPIO_FN_SDHICD0, NULL);
358 gpio_request(GPIO_FN_SDHID0_0, NULL);
359 gpio_request(GPIO_FN_SDHID0_1, NULL);
360 gpio_request(GPIO_FN_SDHID0_2, NULL);
361 gpio_request(GPIO_FN_SDHID0_3, NULL);
362 gpio_request(GPIO_FN_SDHICMD0, NULL);
363 gpio_request(GPIO_FN_SDHIWP0, NULL);
364 gpio_pull_up(GPIO_SDHID0_D0);
365 gpio_pull_up(GPIO_SDHID0_D1);
366 gpio_pull_up(GPIO_SDHID0_D2);
367 gpio_pull_up(GPIO_SDHID0_D3);
368 gpio_pull_up(GPIO_SDHICMD0);
369
370 /* SDHI1 */
371 gpio_request(GPIO_FN_SDHICLK1, NULL);
372 gpio_request(GPIO_FN_SDHID1_0, NULL);
373 gpio_request(GPIO_FN_SDHID1_1, NULL);
374 gpio_request(GPIO_FN_SDHID1_2, NULL);
375 gpio_request(GPIO_FN_SDHID1_3, NULL);
376 gpio_request(GPIO_FN_SDHICMD1, NULL);
377 gpio_pull_up(GPIO_SDHID1_D0);
378 gpio_pull_up(GPIO_SDHID1_D1);
379 gpio_pull_up(GPIO_SDHID1_D2);
380 gpio_pull_up(GPIO_SDHID1_D3);
381 gpio_pull_up(GPIO_SDHICMD1);
382
256 sh7377_add_standard_devices(); 383 sh7377_add_standard_devices();
257 384
258 platform_add_devices(g4evm_devices, ARRAY_SIZE(g4evm_devices)); 385 platform_add_devices(g4evm_devices, ARRAY_SIZE(g4evm_devices));
diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h
index 5179b72e1ee3..51b4a6ab6c60 100644
--- a/arch/arm/mach-shmobile/include/mach/irqs.h
+++ b/arch/arm/mach-shmobile/include/mach/irqs.h
@@ -4,7 +4,13 @@
4#define NR_IRQS 512 4#define NR_IRQS 512
5#define NR_IRQS_LEGACY 8 5#define NR_IRQS_LEGACY 8
6 6
7/* INTCA */
7#define evt2irq(evt) (((evt) >> 5) - 16) 8#define evt2irq(evt) (((evt) >> 5) - 16)
8#define irq2evt(irq) (((irq) + 16) << 5) 9#define irq2evt(irq) (((irq) + 16) << 5)
9 10
11/* INTCS */
12#define INTCS_VECT_BASE 0x3400
13#define INTCS_VECT(n, vect) INTC_VECT((n), INTCS_VECT_BASE + (vect))
14#define intcs_evt2irq(evt) evt2irq(INTCS_VECT_BASE + (evt))
15
10#endif /* __ASM_MACH_IRQS_H */ 16#endif /* __ASM_MACH_IRQS_H */
diff --git a/arch/arm/mach-shmobile/intc-sh7367.c b/arch/arm/mach-shmobile/intc-sh7367.c
index 5ff70cadfc32..1a20c489b20d 100644
--- a/arch/arm/mach-shmobile/intc-sh7367.c
+++ b/arch/arm/mach-shmobile/intc-sh7367.c
@@ -75,7 +75,7 @@ enum {
75 ETM11, ARM11, USBHS, FLCTL, IIC1 75 ETM11, ARM11, USBHS, FLCTL, IIC1
76}; 76};
77 77
78static struct intc_vect intca_vectors[] = { 78static struct intc_vect intca_vectors[] __initdata = {
79 INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220), 79 INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220),
80 INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260), 80 INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260),
81 INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0), 81 INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0),
@@ -162,7 +162,7 @@ static struct intc_group intca_groups[] __initdata = {
162 INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1), 162 INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1),
163}; 163};
164 164
165static struct intc_mask_reg intca_mask_registers[] = { 165static struct intc_mask_reg intca_mask_registers[] __initdata = {
166 { 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */ 166 { 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */
167 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, 167 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
168 { 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */ 168 { 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */
@@ -211,7 +211,7 @@ static struct intc_mask_reg intca_mask_registers[] = {
211 MISTY, CMT3, RWDT1, RWDT0 } }, 211 MISTY, CMT3, RWDT1, RWDT0 } },
212}; 212};
213 213
214static struct intc_prio_reg intca_prio_registers[] = { 214static struct intc_prio_reg intca_prio_registers[] __initdata = {
215 { 0xe6900010, 0, 32, 4, /* INTPRI00A */ 215 { 0xe6900010, 0, 32, 4, /* INTPRI00A */
216 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, 216 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
217 { 0xe6900014, 0, 32, 4, /* INTPRI10A */ 217 { 0xe6900014, 0, 32, 4, /* INTPRI10A */
@@ -263,8 +263,178 @@ static struct intc_desc intca_desc __initdata = {
263 intca_sense_registers, intca_ack_registers), 263 intca_sense_registers, intca_ack_registers),
264}; 264};
265 265
266enum {
267 UNUSED_INTCS = 0,
268
269 INTCS,
270
271 /* interrupt sources INTCS */
272 VIO2_VEU0, VIO2_VEU1, VIO2_VEU2, VIO2_VEU3,
273 VIO3_VOU,
274 RTDMAC_1_DEI0, RTDMAC_1_DEI1, RTDMAC_1_DEI2, RTDMAC_1_DEI3,
275 VIO1_CEU, VIO1_BEU0, VIO1_BEU1, VIO1_BEU2,
276 VPU,
277 SGX530,
278 _2DDMAC_2DDM0, _2DDMAC_2DDM1, _2DDMAC_2DDM2, _2DDMAC_2DDM3,
279 IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2,
280 IPMMU_IPMMUB, IPMMU_IPMMUS,
281 RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR,
282 MSIOF,
283 IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0,
284 TMU_TUNI0, TMU_TUNI1, TMU_TUNI2,
285 CMT,
286 TSIF,
287 IPMMUI,
288 MVI3,
289 ICB,
290 PEP,
291 ASA,
292 BEM,
293 VE2HO,
294 HQE,
295 JPEG,
296 LCDC,
297
298 /* interrupt groups INTCS */
299 _2DDMAC, RTDMAC_1, RTDMAC_2, VEU, BEU, IIC0, IPMMU, IIC2,
300};
301
302static struct intc_vect intcs_vectors[] = {
303 INTCS_VECT(VIO2_VEU0, 0x700), INTCS_VECT(VIO2_VEU1, 0x720),
304 INTCS_VECT(VIO2_VEU2, 0x740), INTCS_VECT(VIO2_VEU3, 0x760),
305 INTCS_VECT(VIO3_VOU, 0x780),
306 INTCS_VECT(RTDMAC_1_DEI0, 0x800), INTCS_VECT(RTDMAC_1_DEI1, 0x820),
307 INTCS_VECT(RTDMAC_1_DEI2, 0x840), INTCS_VECT(RTDMAC_1_DEI3, 0x860),
308 INTCS_VECT(VIO1_CEU, 0x880), INTCS_VECT(VIO1_BEU0, 0x8a0),
309 INTCS_VECT(VIO1_BEU1, 0x8c0), INTCS_VECT(VIO1_BEU2, 0x8e0),
310 INTCS_VECT(VPU, 0x980),
311 INTCS_VECT(SGX530, 0x9e0),
312 INTCS_VECT(_2DDMAC_2DDM0, 0xa00), INTCS_VECT(_2DDMAC_2DDM1, 0xa20),
313 INTCS_VECT(_2DDMAC_2DDM2, 0xa40), INTCS_VECT(_2DDMAC_2DDM3, 0xa60),
314 INTCS_VECT(IIC2_ALI2, 0xa80), INTCS_VECT(IIC2_TACKI2, 0xaa0),
315 INTCS_VECT(IIC2_WAITI2, 0xac0), INTCS_VECT(IIC2_DTEI2, 0xae0),
316 INTCS_VECT(IPMMU_IPMMUB, 0xb20), INTCS_VECT(IPMMU_IPMMUS, 0xb60),
317 INTCS_VECT(RTDMAC_2_DEI4, 0xb80), INTCS_VECT(RTDMAC_2_DEI5, 0xba0),
318 INTCS_VECT(RTDMAC_2_DADERR, 0xbc0),
319 INTCS_VECT(MSIOF, 0xd20),
320 INTCS_VECT(IIC0_ALI0, 0xe00), INTCS_VECT(IIC0_TACKI0, 0xe20),
321 INTCS_VECT(IIC0_WAITI0, 0xe40), INTCS_VECT(IIC0_DTEI0, 0xe60),
322 INTCS_VECT(TMU_TUNI0, 0xe80), INTCS_VECT(TMU_TUNI1, 0xea0),
323 INTCS_VECT(TMU_TUNI2, 0xec0),
324 INTCS_VECT(CMT, 0xf00),
325 INTCS_VECT(TSIF, 0xf20),
326 INTCS_VECT(IPMMUI, 0xf60),
327 INTCS_VECT(MVI3, 0x420),
328 INTCS_VECT(ICB, 0x480),
329 INTCS_VECT(PEP, 0x4a0),
330 INTCS_VECT(ASA, 0x4c0),
331 INTCS_VECT(BEM, 0x4e0),
332 INTCS_VECT(VE2HO, 0x520),
333 INTCS_VECT(HQE, 0x540),
334 INTCS_VECT(JPEG, 0x560),
335 INTCS_VECT(LCDC, 0x580),
336
337 INTC_VECT(INTCS, 0xf80),
338};
339
340static struct intc_group intcs_groups[] __initdata = {
341 INTC_GROUP(_2DDMAC, _2DDMAC_2DDM0, _2DDMAC_2DDM1,
342 _2DDMAC_2DDM2, _2DDMAC_2DDM3),
343 INTC_GROUP(RTDMAC_1, RTDMAC_1_DEI0, RTDMAC_1_DEI1,
344 RTDMAC_1_DEI2, RTDMAC_1_DEI3),
345 INTC_GROUP(RTDMAC_2, RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR),
346 INTC_GROUP(VEU, VIO2_VEU0, VIO2_VEU1, VIO2_VEU2, VIO2_VEU3),
347 INTC_GROUP(BEU, VIO1_BEU0, VIO1_BEU1, VIO1_BEU2),
348 INTC_GROUP(IIC0, IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0),
349 INTC_GROUP(IPMMU, IPMMU_IPMMUS, IPMMU_IPMMUB),
350 INTC_GROUP(IIC2, IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2),
351};
352
353static struct intc_mask_reg intcs_mask_registers[] = {
354 { 0xffd20184, 0xffd201c4, 8, /* IMR1SA / IMCR1SA */
355 { VIO1_BEU2, VIO1_BEU1, VIO1_BEU0, VIO1_CEU,
356 VIO2_VEU3, VIO2_VEU2, VIO2_VEU1, VIO2_VEU0 } },
357 { 0xffd20188, 0xffd201c8, 8, /* IMR2SA / IMCR2SA */
358 { VIO3_VOU, 0, VE2HO, VPU,
359 0, 0, 0, 0 } },
360 { 0xffd2018c, 0xffd201cc, 8, /* IMR3SA / IMCR3SA */
361 { _2DDMAC_2DDM3, _2DDMAC_2DDM2, _2DDMAC_2DDM1, _2DDMAC_2DDM0,
362 BEM, ASA, PEP, ICB } },
363 { 0xffd20190, 0xffd201d0, 8, /* IMR4SA / IMCR4SA */
364 { 0, 0, MVI3, 0,
365 JPEG, HQE, 0, LCDC } },
366 { 0xffd20194, 0xffd201d4, 8, /* IMR5SA / IMCR5SA */
367 { 0, RTDMAC_2_DADERR, RTDMAC_2_DEI5, RTDMAC_2_DEI4,
368 RTDMAC_1_DEI3, RTDMAC_1_DEI2, RTDMAC_1_DEI1, RTDMAC_1_DEI0 } },
369 { 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */
370 { 0, 0, MSIOF, 0,
371 SGX530, 0, 0, 0 } },
372 { 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */
373 { 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0,
374 0, 0, 0, 0 } },
375 { 0xffd201a4, 0xffd201e4, 8, /* IMR9SA / IMCR9SA */
376 { 0, 0, 0, CMT,
377 IIC2_DTEI2, IIC2_WAITI2, IIC2_TACKI2, IIC2_ALI2 } },
378 { 0xffd201a8, 0xffd201e8, 8, /* IMR10SA / IMCR10SA */
379 { IPMMU_IPMMUS, 0, IPMMU_IPMMUB, 0,
380 0, 0, 0, 0 } },
381 { 0xffd201ac, 0xffd201ec, 8, /* IMR11SA / IMCR11SA */
382 { IIC0_DTEI0, IIC0_WAITI0, IIC0_TACKI0, IIC0_ALI0,
383 0, 0, IPMMUI, TSIF } },
384 { 0xffd20104, 0, 16, /* INTAMASK */
385 { 0, 0, 0, 0, 0, 0, 0, 0,
386 0, 0, 0, 0, 0, 0, 0, INTCS } },
387};
388
389/* Priority is needed for INTCA to receive the INTCS interrupt */
390static struct intc_prio_reg intcs_prio_registers[] = {
391 { 0xffd20000, 0, 16, 4, /* IPRAS */ { 0, MVI3, _2DDMAC, ICB } },
392 { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPEG, LCDC, 0, 0 } },
393 { 0xffd20008, 0, 16, 4, /* IPRCS */ { BBIF2, 0, 0, 0 } },
394 { 0xffd20010, 0, 16, 4, /* IPRES */ { RTDMAC_1, VIO1_CEU, 0, VPU } },
395 { 0xffd20014, 0, 16, 4, /* IPRFS */ { 0, RTDMAC_2, 0, CMT } },
396 { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU_TUNI0, TMU_TUNI1,
397 TMU_TUNI2, 0 } },
398 { 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, VIO3_VOU, VEU, BEU } },
399 { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF, IIC0 } },
400 { 0xffd20024, 0, 16, 4, /* IPRJS */ { 0, SGX530, 0, 0 } },
401 { 0xffd20028, 0, 16, 4, /* IPRKS */ { BEM, ASA, IPMMUI, PEP } },
402 { 0xffd2002c, 0, 16, 4, /* IPRLS */ { IPMMU, 0, VE2HO, HQE } },
403 { 0xffd20030, 0, 16, 4, /* IPRMS */ { IIC2, 0, 0, 0 } },
404};
405
406static struct resource intcs_resources[] __initdata = {
407 [0] = {
408 .start = 0xffd20000,
409 .end = 0xffd2ffff,
410 .flags = IORESOURCE_MEM,
411 }
412};
413
414static struct intc_desc intcs_desc __initdata = {
415 .name = "sh7367-intcs",
416 .resource = intcs_resources,
417 .num_resources = ARRAY_SIZE(intcs_resources),
418 .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
419 intcs_prio_registers, NULL, NULL),
420};
421
422static void intcs_demux(unsigned int irq, struct irq_desc *desc)
423{
424 void __iomem *reg = (void *)get_irq_data(irq);
425 unsigned int evtcodeas = ioread32(reg);
426
427 generic_handle_irq(intcs_evt2irq(evtcodeas));
428}
429
266void __init sh7367_init_irq(void) 430void __init sh7367_init_irq(void)
267{ 431{
268 /* INTCA */ 432 void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
433
269 register_intc_controller(&intca_desc); 434 register_intc_controller(&intca_desc);
435 register_intc_controller(&intcs_desc);
436
437 /* demux using INTEVTSA */
438 set_irq_data(evt2irq(0xf80), (void *)intevtsa);
439 set_irq_chained_handler(evt2irq(0xf80), intcs_demux);
270} 440}
diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c
index 3ce9d9bd5899..cfba59f057ec 100644
--- a/arch/arm/mach-shmobile/intc-sh7372.c
+++ b/arch/arm/mach-shmobile/intc-sh7372.c
@@ -319,17 +319,17 @@ static struct intc_prio_reg intca_prio_registers[] __initdata = {
319 { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } }, 319 { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } },
320 { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S, 320 { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S,
321 CMT14, CMT15 } }, 321 CMT14, CMT15 } },
322 { 0xe694003c, 0, 16, 4, /* IPRPA3 */ { 0, 0, 322 { 0xe695003c, 0, 16, 4, /* IPRPA3 */ { 0, 0,
323 MMC_MMC_ERR, MMC_MMC_NOR } }, 323 MMC_MMC_ERR, MMC_MMC_NOR } },
324 { 0xe6940040, 0, 16, 4, /* IPRQA3 */ { IIC4_ALI4, IIC4_TACKI4, 324 { 0xe6950040, 0, 16, 4, /* IPRQA3 */ { IIC4_ALI4, IIC4_TACKI4,
325 IIC4_WAITI4, IIC4_DTEI4 } }, 325 IIC4_WAITI4, IIC4_DTEI4 } },
326 { 0xe6940044, 0, 16, 4, /* IPRRA3 */ { IIC3_ALI3, IIC3_TACKI3, 326 { 0xe6950044, 0, 16, 4, /* IPRRA3 */ { IIC3_ALI3, IIC3_TACKI3,
327 IIC3_WAITI3, IIC3_DTEI3 } }, 327 IIC3_WAITI3, IIC3_DTEI3 } },
328 { 0xe6940048, 0, 16, 4, /* IPRSA3 */ { 0/*ERI*/, 0/*RXI*/, 328 { 0xe6950048, 0, 16, 4, /* IPRSA3 */ { 0/*ERI*/, 0/*RXI*/,
329 0/*TXI*/, 0/*TEI*/} }, 329 0/*TXI*/, 0/*TEI*/} },
330 { 0xe694004c, 0, 16, 4, /* IPRTA3 */ { USB0_USB0I1, USB0_USB0I0, 330 { 0xe695004c, 0, 16, 4, /* IPRTA3 */ { USB0_USB0I1, USB0_USB0I0,
331 USB1_USB1I1, USB1_USB1I0 } }, 331 USB1_USB1I1, USB1_USB1I0 } },
332 { 0xe6940050, 0, 16, 4, /* IPRUA3 */ { USBHSDMAC1_USHDMI, 0, 0, 0 } }, 332 { 0xe6950050, 0, 16, 4, /* IPRUA3 */ { USBHSDMAC1_USHDMI, 0, 0, 0 } },
333}; 333};
334 334
335static struct intc_sense_reg intca_sense_registers[] __initdata = { 335static struct intc_sense_reg intca_sense_registers[] __initdata = {
diff --git a/arch/arm/mach-shmobile/intc-sh7377.c b/arch/arm/mach-shmobile/intc-sh7377.c
index 5c781e2d1897..2cdeb8ccd821 100644
--- a/arch/arm/mach-shmobile/intc-sh7377.c
+++ b/arch/arm/mach-shmobile/intc-sh7377.c
@@ -90,7 +90,7 @@ enum {
90 ICUSB, ICUDMC 90 ICUSB, ICUDMC
91}; 91};
92 92
93static struct intc_vect intca_vectors[] = { 93static struct intc_vect intca_vectors[] __initdata = {
94 INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220), 94 INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220),
95 INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260), 95 INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260),
96 INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0), 96 INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0),
@@ -202,7 +202,7 @@ static struct intc_group intca_groups[] __initdata = {
202 INTC_GROUP(ICUDMC, ICUDMC_ICUDMC1, ICUDMC_ICUDMC2), 202 INTC_GROUP(ICUDMC, ICUDMC_ICUDMC1, ICUDMC_ICUDMC2),
203}; 203};
204 204
205static struct intc_mask_reg intca_mask_registers[] = { 205static struct intc_mask_reg intca_mask_registers[] __initdata = {
206 { 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */ 206 { 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */
207 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, 207 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
208 { 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */ 208 { 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */
@@ -272,7 +272,7 @@ static struct intc_mask_reg intca_mask_registers[] = {
272 SCIFA6, 0, 0, 0 } }, 272 SCIFA6, 0, 0, 0 } },
273}; 273};
274 274
275static struct intc_prio_reg intca_prio_registers[] = { 275static struct intc_prio_reg intca_prio_registers[] __initdata = {
276 { 0xe6900010, 0, 32, 4, /* INTPRI00A */ 276 { 0xe6900010, 0, 32, 4, /* INTPRI00A */
277 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, 277 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
278 { 0xe6900014, 0, 32, 4, /* INTPRI10A */ 278 { 0xe6900014, 0, 32, 4, /* INTPRI10A */
@@ -346,7 +346,301 @@ static struct intc_desc intca_desc __initdata = {
346 intca_sense_registers, intca_ack_registers), 346 intca_sense_registers, intca_ack_registers),
347}; 347};
348 348
349/* this macro ignore entry which is also in INTCA */
350#define __IGNORE(a...)
351#define __IGNORE0(a...) 0
352
353enum {
354 UNUSED_INTCS = 0,
355
356 INTCS,
357
358 /* interrupt sources INTCS */
359 VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3,
360 RTDMAC1_1_DEI0, RTDMAC1_1_DEI1, RTDMAC1_1_DEI2, RTDMAC1_1_DEI3,
361 CEU,
362 BEU_BEU0, BEU_BEU1, BEU_BEU2,
363 __IGNORE(MFI)
364 __IGNORE(BBIF2)
365 VPU,
366 TSIF1,
367 __IGNORE(SGX540)
368 _2DDMAC,
369 IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2,
370 IPMMU_IPMMUR, IPMMU_IPMMUR2,
371 RTDMAC1_2_DEI4, RTDMAC1_2_DEI5, RTDMAC1_2_DADERR,
372 __IGNORE(KEYSC)
373 __IGNORE(TTI20)
374 __IGNORE(MSIOF)
375 IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0,
376 TMU_TUNI0, TMU_TUNI1, TMU_TUNI2,
377 CMT0,
378 TSIF0,
379 __IGNORE(CMT2)
380 LMB,
381 __IGNORE(MSUG)
382 __IGNORE(MSU_MSU, MSU_MSU2)
383 __IGNORE(CTI)
384 MVI3,
385 __IGNORE(RWDT0)
386 __IGNORE(RWDT1)
387 ICB,
388 PEP,
389 ASA,
390 __IGNORE(_2DG)
391 HQE,
392 JPU,
393 LCDC0,
394 __IGNORE(LCRC)
395 RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, RTDMAC2_1_DEI2, RTDMAC2_1_DEI3,
396 RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR,
397 FRC,
398 LCDC1,
399 CSIRX,
400 DSITX_DSITX0, DSITX_DSITX1,
401 __IGNORE(SPU2_SPU0, SPU2_SPU1)
402 __IGNORE(FSI)
403 __IGNORE(FMSI)
404 __IGNORE(SCUV)
405 TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12,
406 TSIF2,
407 CMT4,
408 __IGNORE(MFIS2)
409 CPORTS2R,
410
411 /* interrupt groups INTCS */
412 RTDMAC1_1, RTDMAC1_2, VEU, BEU, IIC0, __IGNORE(MSU) IPMMU,
413 IIC2, RTDMAC2_1, RTDMAC2_2, DSITX, __IGNORE(SPU2) TMU1,
414};
415
416#define INTCS_INTVECT 0x0F80
417static struct intc_vect intcs_vectors[] __initdata = {
418 INTCS_VECT(VEU_VEU0, 0x0700), INTCS_VECT(VEU_VEU1, 0x0720),
419 INTCS_VECT(VEU_VEU2, 0x0740), INTCS_VECT(VEU_VEU3, 0x0760),
420 INTCS_VECT(RTDMAC1_1_DEI0, 0x0800), INTCS_VECT(RTDMAC1_1_DEI1, 0x0820),
421 INTCS_VECT(RTDMAC1_1_DEI2, 0x0840), INTCS_VECT(RTDMAC1_1_DEI3, 0x0860),
422 INTCS_VECT(CEU, 0x0880),
423 INTCS_VECT(BEU_BEU0, 0x08A0),
424 INTCS_VECT(BEU_BEU1, 0x08C0),
425 INTCS_VECT(BEU_BEU2, 0x08E0),
426 __IGNORE(INTCS_VECT(MFI, 0x0900))
427 __IGNORE(INTCS_VECT(BBIF2, 0x0960))
428 INTCS_VECT(VPU, 0x0980),
429 INTCS_VECT(TSIF1, 0x09A0),
430 __IGNORE(INTCS_VECT(SGX540, 0x09E0))
431 INTCS_VECT(_2DDMAC, 0x0A00),
432 INTCS_VECT(IIC2_ALI2, 0x0A80), INTCS_VECT(IIC2_TACKI2, 0x0AA0),
433 INTCS_VECT(IIC2_WAITI2, 0x0AC0), INTCS_VECT(IIC2_DTEI2, 0x0AE0),
434 INTCS_VECT(IPMMU_IPMMUR, 0x0B00), INTCS_VECT(IPMMU_IPMMUR2, 0x0B20),
435 INTCS_VECT(RTDMAC1_2_DEI4, 0x0B80),
436 INTCS_VECT(RTDMAC1_2_DEI5, 0x0BA0),
437 INTCS_VECT(RTDMAC1_2_DADERR, 0x0BC0),
438 __IGNORE(INTCS_VECT(KEYSC 0x0BE0))
439 __IGNORE(INTCS_VECT(TTI20, 0x0C80))
440 __IGNORE(INTCS_VECT(MSIOF, 0x0D20))
441 INTCS_VECT(IIC0_ALI0, 0x0E00), INTCS_VECT(IIC0_TACKI0, 0x0E20),
442 INTCS_VECT(IIC0_WAITI0, 0x0E40), INTCS_VECT(IIC0_DTEI0, 0x0E60),
443 INTCS_VECT(TMU_TUNI0, 0x0E80),
444 INTCS_VECT(TMU_TUNI1, 0x0EA0),
445 INTCS_VECT(TMU_TUNI2, 0x0EC0),
446 INTCS_VECT(CMT0, 0x0F00),
447 INTCS_VECT(TSIF0, 0x0F20),
448 __IGNORE(INTCS_VECT(CMT2, 0x0F40))
449 INTCS_VECT(LMB, 0x0F60),
450 __IGNORE(INTCS_VECT(MSUG, 0x0F80))
451 __IGNORE(INTCS_VECT(MSU_MSU, 0x0FA0))
452 __IGNORE(INTCS_VECT(MSU_MSU2, 0x0FC0))
453 __IGNORE(INTCS_VECT(CTI, 0x0400))
454 INTCS_VECT(MVI3, 0x0420),
455 __IGNORE(INTCS_VECT(RWDT0, 0x0440))
456 __IGNORE(INTCS_VECT(RWDT1, 0x0460))
457 INTCS_VECT(ICB, 0x0480),
458 INTCS_VECT(PEP, 0x04A0),
459 INTCS_VECT(ASA, 0x04C0),
460 __IGNORE(INTCS_VECT(_2DG, 0x04E0))
461 INTCS_VECT(HQE, 0x0540),
462 INTCS_VECT(JPU, 0x0560),
463 INTCS_VECT(LCDC0, 0x0580),
464 __IGNORE(INTCS_VECT(LCRC, 0x05A0))
465 INTCS_VECT(RTDMAC2_1_DEI0, 0x1300), INTCS_VECT(RTDMAC2_1_DEI1, 0x1320),
466 INTCS_VECT(RTDMAC2_1_DEI2, 0x1340), INTCS_VECT(RTDMAC2_1_DEI3, 0x1360),
467 INTCS_VECT(RTDMAC2_2_DEI4, 0x1380), INTCS_VECT(RTDMAC2_2_DEI5, 0x13A0),
468 INTCS_VECT(RTDMAC2_2_DADERR, 0x13C0),
469 INTCS_VECT(FRC, 0x1700),
470 INTCS_VECT(LCDC1, 0x1780),
471 INTCS_VECT(CSIRX, 0x17A0),
472 INTCS_VECT(DSITX_DSITX0, 0x17C0), INTCS_VECT(DSITX_DSITX1, 0x17E0),
473 __IGNORE(INTCS_VECT(SPU2_SPU0, 0x1800))
474 __IGNORE(INTCS_VECT(SPU2_SPU1, 0x1820))
475 __IGNORE(INTCS_VECT(FSI, 0x1840))
476 __IGNORE(INTCS_VECT(FMSI, 0x1860))
477 __IGNORE(INTCS_VECT(SCUV, 0x1880))
478 INTCS_VECT(TMU1_TUNI10, 0x1900), INTCS_VECT(TMU1_TUNI11, 0x1920),
479 INTCS_VECT(TMU1_TUNI12, 0x1940),
480 INTCS_VECT(TSIF2, 0x1960),
481 INTCS_VECT(CMT4, 0x1980),
482 __IGNORE(INTCS_VECT(MFIS2, 0x1A00))
483 INTCS_VECT(CPORTS2R, 0x1A20),
484
485 INTC_VECT(INTCS, INTCS_INTVECT),
486};
487
488static struct intc_group intcs_groups[] __initdata = {
489 INTC_GROUP(RTDMAC1_1,
490 RTDMAC1_1_DEI0, RTDMAC1_1_DEI1,
491 RTDMAC1_1_DEI2, RTDMAC1_1_DEI3),
492 INTC_GROUP(RTDMAC1_2,
493 RTDMAC1_2_DEI4, RTDMAC1_2_DEI5, RTDMAC1_2_DADERR),
494 INTC_GROUP(VEU, VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3),
495 INTC_GROUP(BEU, BEU_BEU0, BEU_BEU1, BEU_BEU2),
496 INTC_GROUP(IIC0, IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0),
497 __IGNORE(INTC_GROUP(MSU, MSU_MSU, MSU_MSU2))
498 INTC_GROUP(IPMMU, IPMMU_IPMMUR, IPMMU_IPMMUR2),
499 INTC_GROUP(IIC2, IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2),
500 INTC_GROUP(RTDMAC2_1,
501 RTDMAC2_1_DEI0, RTDMAC2_1_DEI1,
502 RTDMAC2_1_DEI2, RTDMAC2_1_DEI3),
503 INTC_GROUP(RTDMAC2_2, RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR),
504 INTC_GROUP(DSITX, DSITX_DSITX0, DSITX_DSITX1),
505 __IGNORE(INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1))
506 INTC_GROUP(TMU1, TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12),
507};
508
509static struct intc_mask_reg intcs_mask_registers[] __initdata = {
510 { 0xE6940184, 0xE69401C4, 8, /* IMR1AS / IMCR1AS */
511 { BEU_BEU2, BEU_BEU1, BEU_BEU0, CEU,
512 VEU_VEU3, VEU_VEU2, VEU_VEU1, VEU_VEU0 } },
513 { 0xE6940188, 0xE69401C8, 8, /* IMR2AS / IMCR2AS */
514 { 0, 0, 0, VPU,
515 __IGNORE0(BBIF2), 0, 0, __IGNORE0(MFI) } },
516 { 0xE694018C, 0xE69401CC, 8, /* IMR3AS / IMCR3AS */
517 { 0, 0, 0, _2DDMAC,
518 __IGNORE0(_2DG), ASA, PEP, ICB } },
519 { 0xE6940190, 0xE69401D0, 8, /* IMR4AS / IMCR4AS */
520 { 0, 0, MVI3, __IGNORE0(CTI),
521 JPU, HQE, __IGNORE0(LCRC), LCDC0 } },
522 { 0xE6940194, 0xE69401D4, 8, /* IMR5AS / IMCR5AS */
523 { __IGNORE0(KEYSC), RTDMAC1_2_DADERR, RTDMAC1_2_DEI5, RTDMAC1_2_DEI4,
524 RTDMAC1_1_DEI3, RTDMAC1_1_DEI2, RTDMAC1_1_DEI1, RTDMAC1_1_DEI0 } },
525 __IGNORE({ 0xE6940198, 0xE69401D8, 8, /* IMR6AS / IMCR6AS */
526 { 0, 0, MSIOF, 0,
527 SGX540, 0, TTI20, 0 } })
528 { 0xE694019C, 0xE69401DC, 8, /* IMR7AS / IMCR7AS */
529 { 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0,
530 0, 0, 0, 0 } },
531 __IGNORE({ 0xE69401A0, 0xE69401E0, 8, /* IMR8AS / IMCR8AS */
532 { 0, 0, 0, 0,
533 0, MSU_MSU, MSU_MSU2, MSUG } })
534 { 0xE69401A4, 0xE69401E4, 8, /* IMR9AS / IMCR9AS */
535 { __IGNORE0(RWDT1), __IGNORE0(RWDT0), __IGNORE0(CMT2), CMT0,
536 IIC2_DTEI2, IIC2_WAITI2, IIC2_TACKI2, IIC2_ALI2 } },
537 { 0xE69401A8, 0xE69401E8, 8, /* IMR10AS / IMCR10AS */
538 { 0, 0, IPMMU_IPMMUR, IPMMU_IPMMUR2,
539 0, 0, 0, 0 } },
540 { 0xE69401AC, 0xE69401EC, 8, /* IMR11AS / IMCR11AS */
541 { IIC0_DTEI0, IIC0_WAITI0, IIC0_TACKI0, IIC0_ALI0,
542 0, TSIF1, LMB, TSIF0 } },
543 { 0xE6950180, 0xE69501C0, 8, /* IMR0AS3 / IMCR0AS3 */
544 { RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, RTDMAC2_1_DEI2, RTDMAC2_1_DEI3,
545 RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR, 0 } },
546 { 0xE6950190, 0xE69501D0, 8, /* IMR4AS3 / IMCR4AS3 */
547 { FRC, 0, 0, 0,
548 LCDC1, CSIRX, DSITX_DSITX0, DSITX_DSITX1 } },
549 __IGNORE({ 0xE6950194, 0xE69501D4, 8, /* IMR5AS3 / IMCR5AS3 */
550 {SPU2_SPU0, SPU2_SPU1, FSI, FMSI,
551 SCUV, 0, 0, 0 } })
552 { 0xE6950198, 0xE69501D8, 8, /* IMR6AS3 / IMCR6AS3 */
553 { TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12, TSIF2,
554 CMT4, 0, 0, 0 } },
555 { 0xE695019C, 0xE69501DC, 8, /* IMR7AS3 / IMCR7AS3 */
556 { __IGNORE0(MFIS2), CPORTS2R, 0, 0,
557 0, 0, 0, 0 } },
558 { 0xFFD20104, 0, 16, /* INTAMASK */
559 { 0, 0, 0, 0, 0, 0, 0, 0,
560 0, 0, 0, 0, 0, 0, 0, INTCS } }
561};
562
563static struct intc_prio_reg intcs_prio_registers[] __initdata = {
564 /* IPRAS */
565 { 0xFFD20000, 0, 16, 4, { __IGNORE0(CTI), MVI3, _2DDMAC, ICB } },
566 /* IPRBS */
567 { 0xFFD20004, 0, 16, 4, { JPU, LCDC0, 0, __IGNORE0(LCRC) } },
568 /* IPRCS */
569 __IGNORE({ 0xFFD20008, 0, 16, 4, { BBIF2, 0, 0, 0 } })
570 /* IPRES */
571 { 0xFFD20010, 0, 16, 4, { RTDMAC1_1, CEU, __IGNORE0(MFI), VPU } },
572 /* IPRFS */
573 { 0xFFD20014, 0, 16, 4,
574 { __IGNORE0(KEYSC), RTDMAC1_2, __IGNORE0(CMT2), CMT0 } },
575 /* IPRGS */
576 { 0xFFD20018, 0, 16, 4, { TMU_TUNI0, TMU_TUNI1, TMU_TUNI2, TSIF1 } },
577 /* IPRHS */
578 { 0xFFD2001C, 0, 16, 4, { __IGNORE0(TTI20), 0, VEU, BEU } },
579 /* IPRIS */
580 { 0xFFD20020, 0, 16, 4, { 0, __IGNORE0(MSIOF), TSIF0, IIC0 } },
581 /* IPRJS */
582 __IGNORE({ 0xFFD20024, 0, 16, 4, { 0, SGX540, MSUG, MSU } })
583 /* IPRKS */
584 { 0xFFD20028, 0, 16, 4, { __IGNORE0(_2DG), ASA, LMB, PEP } },
585 /* IPRLS */
586 { 0xFFD2002C, 0, 16, 4, { IPMMU, 0, 0, HQE } },
587 /* IPRMS */
588 { 0xFFD20030, 0, 16, 4,
589 { IIC2, 0, __IGNORE0(RWDT1), __IGNORE0(RWDT0) } },
590 /* IPRAS3 */
591 { 0xFFD50000, 0, 16, 4, { RTDMAC2_1, 0, 0, 0 } },
592 /* IPRBS3 */
593 { 0xFFD50004, 0, 16, 4, { RTDMAC2_2, 0, 0, 0 } },
594 /* IPRIS3 */
595 { 0xFFD50020, 0, 16, 4, { FRC, 0, 0, 0 } },
596 /* IPRJS3 */
597 { 0xFFD50024, 0, 16, 4, { LCDC1, CSIRX, DSITX, 0 } },
598 /* IPRKS3 */
599 __IGNORE({ 0xFFD50028, 0, 16, 4, { SPU2, 0, FSI, FMSI } })
600 /* IPRLS3 */
601 __IGNORE({ 0xFFD5002C, 0, 16, 4, { SCUV, 0, 0, 0 } })
602 /* IPRMS3 */
603 { 0xFFD50030, 0, 16, 4, { TMU1, 0, 0, TSIF2 } },
604 /* IPRNS3 */
605 { 0xFFD50034, 0, 16, 4, { CMT4, 0, 0, 0 } },
606 /* IPROS3 */
607 { 0xFFD50038, 0, 16, 4, { __IGNORE0(MFIS2), CPORTS2R, 0, 0 } },
608};
609
610static struct resource intcs_resources[] __initdata = {
611 [0] = {
612 .start = 0xffd20000,
613 .end = 0xffd500ff,
614 .flags = IORESOURCE_MEM,
615 }
616};
617
618static struct intc_desc intcs_desc __initdata = {
619 .name = "sh7377-intcs",
620 .resource = intcs_resources,
621 .num_resources = ARRAY_SIZE(intcs_resources),
622 .hw = INTC_HW_DESC(intcs_vectors, intcs_groups,
623 intcs_mask_registers, intcs_prio_registers,
624 NULL, NULL),
625};
626
627static void intcs_demux(unsigned int irq, struct irq_desc *desc)
628{
629 void __iomem *reg = (void *)get_irq_data(irq);
630 unsigned int evtcodeas = ioread32(reg);
631
632 generic_handle_irq(intcs_evt2irq(evtcodeas));
633}
634
635#define INTEVTSA 0xFFD20100
349void __init sh7377_init_irq(void) 636void __init sh7377_init_irq(void)
350{ 637{
638 void __iomem *intevtsa = ioremap_nocache(INTEVTSA, PAGE_SIZE);
639
351 register_intc_controller(&intca_desc); 640 register_intc_controller(&intca_desc);
641 register_intc_controller(&intcs_desc);
642
643 /* demux using INTEVTSA */
644 set_irq_data(evt2irq(INTCS_INTVECT), (void *)intevtsa);
645 set_irq_chained_handler(evt2irq(INTCS_INTVECT), intcs_demux);
352} 646}
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index 1d1153290f59..b7c5d896e01c 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -32,6 +32,7 @@
32#include <asm/mach-types.h> 32#include <asm/mach-types.h>
33#include <asm/mach/arch.h> 33#include <asm/mach/arch.h>
34 34
35/* SCIF */
35static struct plat_sci_port scif0_platform_data = { 36static struct plat_sci_port scif0_platform_data = {
36 .mapbase = 0xe6c40000, 37 .mapbase = 0xe6c40000,
37 .flags = UPF_BOOT_AUTOCONF, 38 .flags = UPF_BOOT_AUTOCONF,
@@ -137,6 +138,7 @@ static struct platform_device scif6_device = {
137 }, 138 },
138}; 139};
139 140
141/* CMT */
140static struct sh_timer_config cmt10_platform_data = { 142static struct sh_timer_config cmt10_platform_data = {
141 .name = "CMT10", 143 .name = "CMT10",
142 .channel_offset = 0x10, 144 .channel_offset = 0x10,
@@ -169,6 +171,49 @@ static struct platform_device cmt10_device = {
169 .num_resources = ARRAY_SIZE(cmt10_resources), 171 .num_resources = ARRAY_SIZE(cmt10_resources),
170}; 172};
171 173
174/* I2C */
175static struct resource iic0_resources[] = {
176 [0] = {
177 .name = "IIC0",
178 .start = 0xFFF20000,
179 .end = 0xFFF20425 - 1,
180 .flags = IORESOURCE_MEM,
181 },
182 [1] = {
183 .start = intcs_evt2irq(0xe00),
184 .end = intcs_evt2irq(0xe60),
185 .flags = IORESOURCE_IRQ,
186 },
187};
188
189static struct platform_device iic0_device = {
190 .name = "i2c-sh_mobile",
191 .id = 0, /* "i2c0" clock */
192 .num_resources = ARRAY_SIZE(iic0_resources),
193 .resource = iic0_resources,
194};
195
196static struct resource iic1_resources[] = {
197 [0] = {
198 .name = "IIC1",
199 .start = 0xE6C20000,
200 .end = 0xE6C20425 - 1,
201 .flags = IORESOURCE_MEM,
202 },
203 [1] = {
204 .start = 44,
205 .end = 47,
206 .flags = IORESOURCE_IRQ,
207 },
208};
209
210static struct platform_device iic1_device = {
211 .name = "i2c-sh_mobile",
212 .id = 1, /* "i2c1" clock */
213 .num_resources = ARRAY_SIZE(iic1_resources),
214 .resource = iic1_resources,
215};
216
172static struct platform_device *sh7372_early_devices[] __initdata = { 217static struct platform_device *sh7372_early_devices[] __initdata = {
173 &scif0_device, 218 &scif0_device,
174 &scif1_device, 219 &scif1_device,
@@ -178,6 +223,8 @@ static struct platform_device *sh7372_early_devices[] __initdata = {
178 &scif5_device, 223 &scif5_device,
179 &scif6_device, 224 &scif6_device,
180 &cmt10_device, 225 &cmt10_device,
226 &iic0_device,
227 &iic1_device,
181}; 228};
182 229
183void __init sh7372_add_standard_devices(void) 230void __init sh7372_add_standard_devices(void)
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index c27f80e5d531..9d8ca990dde6 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -128,7 +128,7 @@ config TXX9_DMAC
128 128
129config SH_DMAE 129config SH_DMAE
130 tristate "Renesas SuperH DMAC support" 130 tristate "Renesas SuperH DMAC support"
131 depends on SUPERH && SH_DMA 131 depends on (SUPERH && SH_DMA) || (ARM && ARCH_SHMOBILE)
132 depends on !SH_DMA_API 132 depends on !SH_DMA_API
133 select DMA_ENGINE 133 select DMA_ENGINE
134 help 134 help
diff --git a/drivers/dma/shdma.c b/drivers/dma/shdma.c
index 323afef77802..c2b0172a7589 100644
--- a/drivers/dma/shdma.c
+++ b/drivers/dma/shdma.c
@@ -811,7 +811,7 @@ static irqreturn_t sh_dmae_interrupt(int irq, void *data)
811 return ret; 811 return ret;
812} 812}
813 813
814#if defined(CONFIG_CPU_SH4) 814#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
815static irqreturn_t sh_dmae_err(int irq, void *data) 815static irqreturn_t sh_dmae_err(int irq, void *data)
816{ 816{
817 struct sh_dmae_device *shdev = (struct sh_dmae_device *)data; 817 struct sh_dmae_device *shdev = (struct sh_dmae_device *)data;
@@ -1052,7 +1052,7 @@ static int __init sh_dmae_probe(struct platform_device *pdev)
1052 /* Default transfer size of 32 bytes requires 32-byte alignment */ 1052 /* Default transfer size of 32 bytes requires 32-byte alignment */
1053 shdev->common.copy_align = LOG2_DEFAULT_XFER_SIZE; 1053 shdev->common.copy_align = LOG2_DEFAULT_XFER_SIZE;
1054 1054
1055#if defined(CONFIG_CPU_SH4) 1055#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
1056 chanirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1); 1056 chanirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
1057 1057
1058 if (!chanirq_res) 1058 if (!chanirq_res)
@@ -1077,7 +1077,7 @@ static int __init sh_dmae_probe(struct platform_device *pdev)
1077 1077
1078#else 1078#else
1079 chanirq_res = errirq_res; 1079 chanirq_res = errirq_res;
1080#endif /* CONFIG_CPU_SH4 */ 1080#endif /* CONFIG_CPU_SH4 || CONFIG_ARCH_SHMOBILE */
1081 1081
1082 if (chanirq_res->start == chanirq_res->end && 1082 if (chanirq_res->start == chanirq_res->end &&
1083 !platform_get_resource(pdev, IORESOURCE_IRQ, 1)) { 1083 !platform_get_resource(pdev, IORESOURCE_IRQ, 1)) {
@@ -1124,7 +1124,7 @@ static int __init sh_dmae_probe(struct platform_device *pdev)
1124chan_probe_err: 1124chan_probe_err:
1125 sh_dmae_chan_remove(shdev); 1125 sh_dmae_chan_remove(shdev);
1126eirqres: 1126eirqres:
1127#if defined(CONFIG_CPU_SH4) 1127#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
1128 free_irq(errirq, shdev); 1128 free_irq(errirq, shdev);
1129eirq_err: 1129eirq_err:
1130#endif 1130#endif
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 87ab0568bb0e..dec387d3f04d 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -529,7 +529,7 @@ config I2C_SH7760
529 529
530config I2C_SH_MOBILE 530config I2C_SH_MOBILE
531 tristate "SuperH Mobile I2C Controller" 531 tristate "SuperH Mobile I2C Controller"
532 depends on SUPERH 532 depends on SUPERH || ARCH_SHMOBILE
533 help 533 help
534 If you say yes to this option, support will be included for the 534 If you say yes to this option, support will be included for the
535 built-in I2C interface on the Renesas SH-Mobile processor. 535 built-in I2C interface on the Renesas SH-Mobile processor.
diff --git a/drivers/i2c/busses/i2c-sh_mobile.c b/drivers/i2c/busses/i2c-sh_mobile.c
index ffb405d7c6f2..598c49acaeb5 100644
--- a/drivers/i2c/busses/i2c-sh_mobile.c
+++ b/drivers/i2c/busses/i2c-sh_mobile.c
@@ -119,8 +119,10 @@ struct sh_mobile_i2c_data {
119 struct i2c_adapter adap; 119 struct i2c_adapter adap;
120 120
121 struct clk *clk; 121 struct clk *clk;
122 u_int8_t icic;
122 u_int8_t iccl; 123 u_int8_t iccl;
123 u_int8_t icch; 124 u_int8_t icch;
125 u_int8_t flags;
124 126
125 spinlock_t lock; 127 spinlock_t lock;
126 wait_queue_head_t wait; 128 wait_queue_head_t wait;
@@ -129,15 +131,17 @@ struct sh_mobile_i2c_data {
129 int sr; 131 int sr;
130}; 132};
131 133
134#define IIC_FLAG_HAS_ICIC67 (1 << 0)
135
132#define NORMAL_SPEED 100000 /* FAST_SPEED 400000 */ 136#define NORMAL_SPEED 100000 /* FAST_SPEED 400000 */
133 137
134/* Register offsets */ 138/* Register offsets */
135#define ICDR(pd) (pd->reg + 0x00) 139#define ICDR 0x00
136#define ICCR(pd) (pd->reg + 0x04) 140#define ICCR 0x04
137#define ICSR(pd) (pd->reg + 0x08) 141#define ICSR 0x08
138#define ICIC(pd) (pd->reg + 0x0c) 142#define ICIC 0x0c
139#define ICCL(pd) (pd->reg + 0x10) 143#define ICCL 0x10
140#define ICCH(pd) (pd->reg + 0x14) 144#define ICCH 0x14
141 145
142/* Register bits */ 146/* Register bits */
143#define ICCR_ICE 0x80 147#define ICCR_ICE 0x80
@@ -155,11 +159,32 @@ struct sh_mobile_i2c_data {
155#define ICSR_WAIT 0x02 159#define ICSR_WAIT 0x02
156#define ICSR_DTE 0x01 160#define ICSR_DTE 0x01
157 161
162#define ICIC_ICCLB8 0x80
163#define ICIC_ICCHB8 0x40
158#define ICIC_ALE 0x08 164#define ICIC_ALE 0x08
159#define ICIC_TACKE 0x04 165#define ICIC_TACKE 0x04
160#define ICIC_WAITE 0x02 166#define ICIC_WAITE 0x02
161#define ICIC_DTEE 0x01 167#define ICIC_DTEE 0x01
162 168
169static void iic_wr(struct sh_mobile_i2c_data *pd, int offs, unsigned char data)
170{
171 if (offs == ICIC)
172 data |= pd->icic;
173
174 iowrite8(data, pd->reg + offs);
175}
176
177static unsigned char iic_rd(struct sh_mobile_i2c_data *pd, int offs)
178{
179 return ioread8(pd->reg + offs);
180}
181
182static void iic_set_clr(struct sh_mobile_i2c_data *pd, int offs,
183 unsigned char set, unsigned char clr)
184{
185 iic_wr(pd, offs, (iic_rd(pd, offs) | set) & ~clr);
186}
187
163static void activate_ch(struct sh_mobile_i2c_data *pd) 188static void activate_ch(struct sh_mobile_i2c_data *pd)
164{ 189{
165 unsigned long i2c_clk; 190 unsigned long i2c_clk;
@@ -187,6 +212,14 @@ static void activate_ch(struct sh_mobile_i2c_data *pd)
187 else 212 else
188 pd->iccl = (u_int8_t)(num/denom); 213 pd->iccl = (u_int8_t)(num/denom);
189 214
215 /* one more bit of ICCL in ICIC */
216 if (pd->flags & IIC_FLAG_HAS_ICIC67) {
217 if ((num/denom) > 0xff)
218 pd->icic |= ICIC_ICCLB8;
219 else
220 pd->icic &= ~ICIC_ICCLB8;
221 }
222
190 /* Calculate the value for icch. From the data sheet: 223 /* Calculate the value for icch. From the data sheet:
191 icch = (p clock / transfer rate) * (H / (L + H)) */ 224 icch = (p clock / transfer rate) * (H / (L + H)) */
192 num = i2c_clk * 4; 225 num = i2c_clk * 4;
@@ -196,25 +229,33 @@ static void activate_ch(struct sh_mobile_i2c_data *pd)
196 else 229 else
197 pd->icch = (u_int8_t)(num/denom); 230 pd->icch = (u_int8_t)(num/denom);
198 231
232 /* one more bit of ICCH in ICIC */
233 if (pd->flags & IIC_FLAG_HAS_ICIC67) {
234 if ((num/denom) > 0xff)
235 pd->icic |= ICIC_ICCHB8;
236 else
237 pd->icic &= ~ICIC_ICCHB8;
238 }
239
199 /* Enable channel and configure rx ack */ 240 /* Enable channel and configure rx ack */
200 iowrite8(ioread8(ICCR(pd)) | ICCR_ICE, ICCR(pd)); 241 iic_set_clr(pd, ICCR, ICCR_ICE, 0);
201 242
202 /* Mask all interrupts */ 243 /* Mask all interrupts */
203 iowrite8(0, ICIC(pd)); 244 iic_wr(pd, ICIC, 0);
204 245
205 /* Set the clock */ 246 /* Set the clock */
206 iowrite8(pd->iccl, ICCL(pd)); 247 iic_wr(pd, ICCL, pd->iccl);
207 iowrite8(pd->icch, ICCH(pd)); 248 iic_wr(pd, ICCH, pd->icch);
208} 249}
209 250
210static void deactivate_ch(struct sh_mobile_i2c_data *pd) 251static void deactivate_ch(struct sh_mobile_i2c_data *pd)
211{ 252{
212 /* Clear/disable interrupts */ 253 /* Clear/disable interrupts */
213 iowrite8(0, ICSR(pd)); 254 iic_wr(pd, ICSR, 0);
214 iowrite8(0, ICIC(pd)); 255 iic_wr(pd, ICIC, 0);
215 256
216 /* Disable channel */ 257 /* Disable channel */
217 iowrite8(ioread8(ICCR(pd)) & ~ICCR_ICE, ICCR(pd)); 258 iic_set_clr(pd, ICCR, 0, ICCR_ICE);
218 259
219 /* Disable clock and mark device as idle */ 260 /* Disable clock and mark device as idle */
220 clk_disable(pd->clk); 261 clk_disable(pd->clk);
@@ -233,35 +274,35 @@ static unsigned char i2c_op(struct sh_mobile_i2c_data *pd,
233 274
234 switch (op) { 275 switch (op) {
235 case OP_START: /* issue start and trigger DTE interrupt */ 276 case OP_START: /* issue start and trigger DTE interrupt */
236 iowrite8(0x94, ICCR(pd)); 277 iic_wr(pd, ICCR, 0x94);
237 break; 278 break;
238 case OP_TX_FIRST: /* disable DTE interrupt and write data */ 279 case OP_TX_FIRST: /* disable DTE interrupt and write data */
239 iowrite8(ICIC_WAITE | ICIC_ALE | ICIC_TACKE, ICIC(pd)); 280 iic_wr(pd, ICIC, ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
240 iowrite8(data, ICDR(pd)); 281 iic_wr(pd, ICDR, data);
241 break; 282 break;
242 case OP_TX: /* write data */ 283 case OP_TX: /* write data */
243 iowrite8(data, ICDR(pd)); 284 iic_wr(pd, ICDR, data);
244 break; 285 break;
245 case OP_TX_STOP: /* write data and issue a stop afterwards */ 286 case OP_TX_STOP: /* write data and issue a stop afterwards */
246 iowrite8(data, ICDR(pd)); 287 iic_wr(pd, ICDR, data);
247 iowrite8(0x90, ICCR(pd)); 288 iic_wr(pd, ICCR, 0x90);
248 break; 289 break;
249 case OP_TX_TO_RX: /* select read mode */ 290 case OP_TX_TO_RX: /* select read mode */
250 iowrite8(0x81, ICCR(pd)); 291 iic_wr(pd, ICCR, 0x81);
251 break; 292 break;
252 case OP_RX: /* just read data */ 293 case OP_RX: /* just read data */
253 ret = ioread8(ICDR(pd)); 294 ret = iic_rd(pd, ICDR);
254 break; 295 break;
255 case OP_RX_STOP: /* enable DTE interrupt, issue stop */ 296 case OP_RX_STOP: /* enable DTE interrupt, issue stop */
256 iowrite8(ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE, 297 iic_wr(pd, ICIC,
257 ICIC(pd)); 298 ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
258 iowrite8(0xc0, ICCR(pd)); 299 iic_wr(pd, ICCR, 0xc0);
259 break; 300 break;
260 case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */ 301 case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */
261 iowrite8(ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE, 302 iic_wr(pd, ICIC,
262 ICIC(pd)); 303 ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
263 ret = ioread8(ICDR(pd)); 304 ret = iic_rd(pd, ICDR);
264 iowrite8(0xc0, ICCR(pd)); 305 iic_wr(pd, ICCR, 0xc0);
265 break; 306 break;
266 } 307 }
267 308
@@ -367,7 +408,7 @@ static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
367 unsigned char sr; 408 unsigned char sr;
368 int wakeup; 409 int wakeup;
369 410
370 sr = ioread8(ICSR(pd)); 411 sr = iic_rd(pd, ICSR);
371 pd->sr |= sr; /* remember state */ 412 pd->sr |= sr; /* remember state */
372 413
373 dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr, 414 dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr,
@@ -376,7 +417,7 @@ static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
376 417
377 if (sr & (ICSR_AL | ICSR_TACK)) { 418 if (sr & (ICSR_AL | ICSR_TACK)) {
378 /* don't interrupt transaction - continue to issue stop */ 419 /* don't interrupt transaction - continue to issue stop */
379 iowrite8(sr & ~(ICSR_AL | ICSR_TACK), ICSR(pd)); 420 iic_wr(pd, ICSR, sr & ~(ICSR_AL | ICSR_TACK));
380 wakeup = 0; 421 wakeup = 0;
381 } else if (pd->msg->flags & I2C_M_RD) 422 } else if (pd->msg->flags & I2C_M_RD)
382 wakeup = sh_mobile_i2c_isr_rx(pd); 423 wakeup = sh_mobile_i2c_isr_rx(pd);
@@ -384,7 +425,7 @@ static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
384 wakeup = sh_mobile_i2c_isr_tx(pd); 425 wakeup = sh_mobile_i2c_isr_tx(pd);
385 426
386 if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */ 427 if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */
387 iowrite8(sr & ~ICSR_WAIT, ICSR(pd)); 428 iic_wr(pd, ICSR, sr & ~ICSR_WAIT);
388 429
389 if (wakeup) { 430 if (wakeup) {
390 pd->sr |= SW_DONE; 431 pd->sr |= SW_DONE;
@@ -402,21 +443,21 @@ static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg)
402 } 443 }
403 444
404 /* Initialize channel registers */ 445 /* Initialize channel registers */
405 iowrite8(ioread8(ICCR(pd)) & ~ICCR_ICE, ICCR(pd)); 446 iic_set_clr(pd, ICCR, 0, ICCR_ICE);
406 447
407 /* Enable channel and configure rx ack */ 448 /* Enable channel and configure rx ack */
408 iowrite8(ioread8(ICCR(pd)) | ICCR_ICE, ICCR(pd)); 449 iic_set_clr(pd, ICCR, ICCR_ICE, 0);
409 450
410 /* Set the clock */ 451 /* Set the clock */
411 iowrite8(pd->iccl, ICCL(pd)); 452 iic_wr(pd, ICCL, pd->iccl);
412 iowrite8(pd->icch, ICCH(pd)); 453 iic_wr(pd, ICCH, pd->icch);
413 454
414 pd->msg = usr_msg; 455 pd->msg = usr_msg;
415 pd->pos = -1; 456 pd->pos = -1;
416 pd->sr = 0; 457 pd->sr = 0;
417 458
418 /* Enable all interrupts to begin with */ 459 /* Enable all interrupts to begin with */
419 iowrite8(ICIC_WAITE | ICIC_ALE | ICIC_TACKE | ICIC_DTEE, ICIC(pd)); 460 iic_wr(pd, ICIC, ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
420 return 0; 461 return 0;
421} 462}
422 463
@@ -451,7 +492,7 @@ static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
451 492
452 retry_count = 1000; 493 retry_count = 1000;
453again: 494again:
454 val = ioread8(ICSR(pd)); 495 val = iic_rd(pd, ICSR);
455 496
456 dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr); 497 dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr);
457 498
@@ -576,6 +617,12 @@ static int sh_mobile_i2c_probe(struct platform_device *dev)
576 goto err_irq; 617 goto err_irq;
577 } 618 }
578 619
620 /* The IIC blocks on SH-Mobile ARM processors
621 * come with two new bits in ICIC.
622 */
623 if (size > 0x17)
624 pd->flags |= IIC_FLAG_HAS_ICIC67;
625
579 /* Enable Runtime PM for this device. 626 /* Enable Runtime PM for this device.
580 * 627 *
581 * Also tell the Runtime PM core to ignore children 628 * Also tell the Runtime PM core to ignore children
diff --git a/include/linux/serial_sci.h b/include/linux/serial_sci.h
index f5364a1de68b..837efa4e63c2 100644
--- a/include/linux/serial_sci.h
+++ b/include/linux/serial_sci.h
@@ -3,7 +3,7 @@
3 3
4#include <linux/serial_core.h> 4#include <linux/serial_core.h>
5#ifdef CONFIG_SERIAL_SH_SCI_DMA 5#ifdef CONFIG_SERIAL_SH_SCI_DMA
6#include <asm/dmaengine.h> 6#include <linux/sh_dma.h>
7#endif 7#endif
8 8
9/* 9/*
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-06 19:12:22 -0500