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-rw-r--r--arch/arm/mach-msm/include/mach/sirc.h115
-rw-r--r--arch/arm/mach-msm/sirc.c177
2 files changed, 292 insertions, 0 deletions
diff --git a/arch/arm/mach-msm/include/mach/sirc.h b/arch/arm/mach-msm/include/mach/sirc.h
new file mode 100644
index 000000000000..7281337ee28d
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/sirc.h
@@ -0,0 +1,115 @@
1/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of Code Aurora Forum, Inc. nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 */
29
30#ifndef __ASM_ARCH_MSM_SIRC_H
31#define __ASM_ARCH_MSM_SIRC_H
32
33struct sirc_regs_t {
34 void *int_enable;
35 void *int_enable_clear;
36 void *int_enable_set;
37 void *int_type;
38 void *int_polarity;
39 void *int_clear;
40};
41
42struct sirc_cascade_regs {
43 void *int_status;
44 unsigned int cascade_irq;
45};
46
47void msm_init_sirc(void);
48void msm_sirc_enter_sleep(void);
49void msm_sirc_exit_sleep(void);
50
51#if defined(CONFIG_ARCH_MSM_SCORPION)
52
53#include <mach/msm_iomap.h>
54
55/*
56 * Secondary interrupt controller interrupts
57 */
58
59#define FIRST_SIRC_IRQ (NR_MSM_IRQS + NR_GPIO_IRQS)
60
61#define INT_UART1 (FIRST_SIRC_IRQ + 0)
62#define INT_UART2 (FIRST_SIRC_IRQ + 1)
63#define INT_UART3 (FIRST_SIRC_IRQ + 2)
64#define INT_UART1_RX (FIRST_SIRC_IRQ + 3)
65#define INT_UART2_RX (FIRST_SIRC_IRQ + 4)
66#define INT_UART3_RX (FIRST_SIRC_IRQ + 5)
67#define INT_SPI_INPUT (FIRST_SIRC_IRQ + 6)
68#define INT_SPI_OUTPUT (FIRST_SIRC_IRQ + 7)
69#define INT_SPI_ERROR (FIRST_SIRC_IRQ + 8)
70#define INT_GPIO_GROUP1 (FIRST_SIRC_IRQ + 9)
71#define INT_GPIO_GROUP2 (FIRST_SIRC_IRQ + 10)
72#define INT_GPIO_GROUP1_SECURE (FIRST_SIRC_IRQ + 11)
73#define INT_GPIO_GROUP2_SECURE (FIRST_SIRC_IRQ + 12)
74#define INT_AVS_SVIC (FIRST_SIRC_IRQ + 13)
75#define INT_AVS_REQ_UP (FIRST_SIRC_IRQ + 14)
76#define INT_AVS_REQ_DOWN (FIRST_SIRC_IRQ + 15)
77#define INT_PBUS_ERR (FIRST_SIRC_IRQ + 16)
78#define INT_AXI_ERR (FIRST_SIRC_IRQ + 17)
79#define INT_SMI_ERR (FIRST_SIRC_IRQ + 18)
80#define INT_EBI1_ERR (FIRST_SIRC_IRQ + 19)
81#define INT_IMEM_ERR (FIRST_SIRC_IRQ + 20)
82#define INT_TEMP_SENSOR (FIRST_SIRC_IRQ + 21)
83#define INT_TV_ENC (FIRST_SIRC_IRQ + 22)
84#define INT_GRP2D (FIRST_SIRC_IRQ + 23)
85#define INT_GSBI_QUP (FIRST_SIRC_IRQ + 24)
86#define INT_SC_ACG (FIRST_SIRC_IRQ + 25)
87#define INT_WDT0 (FIRST_SIRC_IRQ + 26)
88#define INT_WDT1 (FIRST_SIRC_IRQ + 27)
89
90#if defined(CONFIG_MSM_SOC_REV_A)
91#define NR_SIRC_IRQS 28
92#define SIRC_MASK 0x0FFFFFFF
93#else
94#define NR_SIRC_IRQS 23
95#define SIRC_MASK 0x007FFFFF
96#endif
97
98#define LAST_SIRC_IRQ (FIRST_SIRC_IRQ + NR_SIRC_IRQS - 1)
99
100#define SPSS_SIRC_INT_SELECT (MSM_SIRC_BASE + 0x00)
101#define SPSS_SIRC_INT_ENABLE (MSM_SIRC_BASE + 0x04)
102#define SPSS_SIRC_INT_ENABLE_CLEAR (MSM_SIRC_BASE + 0x08)
103#define SPSS_SIRC_INT_ENABLE_SET (MSM_SIRC_BASE + 0x0C)
104#define SPSS_SIRC_INT_TYPE (MSM_SIRC_BASE + 0x10)
105#define SPSS_SIRC_INT_POLARITY (MSM_SIRC_BASE + 0x14)
106#define SPSS_SIRC_SECURITY (MSM_SIRC_BASE + 0x18)
107#define SPSS_SIRC_IRQ_STATUS (MSM_SIRC_BASE + 0x1C)
108#define SPSS_SIRC_IRQ1_STATUS (MSM_SIRC_BASE + 0x20)
109#define SPSS_SIRC_RAW_STATUS (MSM_SIRC_BASE + 0x24)
110#define SPSS_SIRC_INT_CLEAR (MSM_SIRC_BASE + 0x28)
111#define SPSS_SIRC_SOFT_INT (MSM_SIRC_BASE + 0x2C)
112
113#endif
114
115#endif
diff --git a/arch/arm/mach-msm/sirc.c b/arch/arm/mach-msm/sirc.c
new file mode 100644
index 000000000000..b0794524ba6e
--- /dev/null
+++ b/arch/arm/mach-msm/sirc.c
@@ -0,0 +1,177 @@
1/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 *
17 */
18
19#include <linux/io.h>
20#include <linux/irq.h>
21#include <linux/interrupt.h>
22#include <asm/irq.h>
23
24static unsigned int int_enable;
25static unsigned int wake_enable;
26
27static struct sirc_regs_t sirc_regs = {
28 .int_enable = SPSS_SIRC_INT_ENABLE,
29 .int_enable_clear = SPSS_SIRC_INT_ENABLE_CLEAR,
30 .int_enable_set = SPSS_SIRC_INT_ENABLE_SET,
31 .int_type = SPSS_SIRC_INT_TYPE,
32 .int_polarity = SPSS_SIRC_INT_POLARITY,
33 .int_clear = SPSS_SIRC_INT_CLEAR,
34};
35
36static struct sirc_cascade_regs sirc_reg_table[] = {
37 {
38 .int_status = SPSS_SIRC_IRQ_STATUS,
39 .cascade_irq = INT_SIRC_0,
40 }
41};
42
43static unsigned int save_type;
44static unsigned int save_polarity;
45
46/* Mask off the given interrupt. Keep the int_enable mask in sync with
47 the enable reg, so it can be restored after power collapse. */
48static void sirc_irq_mask(unsigned int irq)
49{
50 unsigned int mask;
51
52
53 mask = 1 << (irq - FIRST_SIRC_IRQ);
54 writel(mask, sirc_regs.int_enable_clear);
55 int_enable &= ~mask;
56 return;
57}
58
59/* Unmask the given interrupt. Keep the int_enable mask in sync with
60 the enable reg, so it can be restored after power collapse. */
61static void sirc_irq_unmask(unsigned int irq)
62{
63 unsigned int mask;
64
65 mask = 1 << (irq - FIRST_SIRC_IRQ);
66 writel(mask, sirc_regs.int_enable_set);
67 int_enable |= mask;
68 return;
69}
70
71static void sirc_irq_ack(unsigned int irq)
72{
73 unsigned int mask;
74
75 mask = 1 << (irq - FIRST_SIRC_IRQ);
76 writel(mask, sirc_regs.int_clear);
77 return;
78}
79
80static int sirc_irq_set_wake(unsigned int irq, unsigned int on)
81{
82 unsigned int mask;
83
84 /* Used to set the interrupt enable mask during power collapse. */
85 mask = 1 << (irq - FIRST_SIRC_IRQ);
86 if (on)
87 wake_enable |= mask;
88 else
89 wake_enable &= ~mask;
90
91 return 0;
92}
93
94static int sirc_irq_set_type(unsigned int irq, unsigned int flow_type)
95{
96 unsigned int mask;
97 unsigned int val;
98
99 mask = 1 << (irq - FIRST_SIRC_IRQ);
100 val = readl(sirc_regs.int_polarity);
101
102 if (flow_type & (IRQF_TRIGGER_LOW | IRQF_TRIGGER_FALLING))
103 val |= mask;
104 else
105 val &= ~mask;
106
107 writel(val, sirc_regs.int_polarity);
108
109 val = readl(sirc_regs.int_type);
110 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
111 val |= mask;
112 irq_desc[irq].handle_irq = handle_edge_irq;
113 } else {
114 val &= ~mask;
115 irq_desc[irq].handle_irq = handle_level_irq;
116 }
117
118 writel(val, sirc_regs.int_type);
119
120 return 0;
121}
122
123/* Finds the pending interrupt on the passed cascade irq and redrives it */
124static void sirc_irq_handler(unsigned int irq, struct irq_desc *desc)
125{
126 unsigned int reg = 0;
127 unsigned int sirq;
128 unsigned int status;
129
130 while ((reg < ARRAY_SIZE(sirc_reg_table)) &&
131 (sirc_reg_table[reg].cascade_irq != irq))
132 reg++;
133
134 status = readl(sirc_reg_table[reg].int_status);
135 status &= SIRC_MASK;
136 if (status == 0)
137 return;
138
139 for (sirq = 0;
140 (sirq < NR_SIRC_IRQS) && ((status & (1U << sirq)) == 0);
141 sirq++)
142 ;
143 generic_handle_irq(sirq+FIRST_SIRC_IRQ);
144
145 desc->chip->ack(irq);
146}
147
148static struct irq_chip sirc_irq_chip = {
149 .name = "sirc",
150 .ack = sirc_irq_ack,
151 .mask = sirc_irq_mask,
152 .unmask = sirc_irq_unmask,
153 .set_wake = sirc_irq_set_wake,
154 .set_type = sirc_irq_set_type,
155};
156
157void __init msm_init_sirc(void)
158{
159 int i;
160
161 int_enable = 0;
162 wake_enable = 0;
163
164 for (i = FIRST_SIRC_IRQ; i < LAST_SIRC_IRQ; i++) {
165 set_irq_chip(i, &sirc_irq_chip);
166 set_irq_handler(i, handle_edge_irq);
167 set_irq_flags(i, IRQF_VALID);
168 }
169
170 for (i = 0; i < ARRAY_SIZE(sirc_reg_table); i++) {
171 set_irq_chained_handler(sirc_reg_table[i].cascade_irq,
172 sirc_irq_handler);
173 set_irq_wake(sirc_reg_table[i].cascade_irq, 1);
174 }
175 return;
176}
177
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-06 06:44:08 -0500