diff options
-rw-r--r-- | arch/arm/mach-exynos/common.c | 42 |
1 files changed, 31 insertions, 11 deletions
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index c59e18871006..9ff38aa08fd0 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c | |||
@@ -26,10 +26,12 @@ | |||
26 | #include <asm/hardware/gic.h> | 26 | #include <asm/hardware/gic.h> |
27 | #include <asm/mach/map.h> | 27 | #include <asm/mach/map.h> |
28 | #include <asm/mach/irq.h> | 28 | #include <asm/mach/irq.h> |
29 | #include <asm/cacheflush.h> | ||
29 | 30 | ||
30 | #include <mach/regs-irq.h> | 31 | #include <mach/regs-irq.h> |
31 | #include <mach/regs-pmu.h> | 32 | #include <mach/regs-pmu.h> |
32 | #include <mach/regs-gpio.h> | 33 | #include <mach/regs-gpio.h> |
34 | #include <mach/pmu.h> | ||
33 | 35 | ||
34 | #include <plat/cpu.h> | 36 | #include <plat/cpu.h> |
35 | #include <plat/clock.h> | 37 | #include <plat/clock.h> |
@@ -441,20 +443,38 @@ core_initcall(exynos4_core_init); | |||
441 | #ifdef CONFIG_CACHE_L2X0 | 443 | #ifdef CONFIG_CACHE_L2X0 |
442 | static int __init exynos4_l2x0_cache_init(void) | 444 | static int __init exynos4_l2x0_cache_init(void) |
443 | { | 445 | { |
444 | /* TAG, Data Latency Control: 2cycle */ | 446 | if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) { |
445 | __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL); | 447 | l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC; |
448 | /* TAG, Data Latency Control: 2 cycles */ | ||
449 | l2x0_saved_regs.tag_latency = 0x110; | ||
446 | 450 | ||
447 | if (soc_is_exynos4210()) | 451 | if (soc_is_exynos4212() || soc_is_exynos4412()) |
448 | __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); | 452 | l2x0_saved_regs.data_latency = 0x120; |
449 | else if (soc_is_exynos4212() || soc_is_exynos4412()) | 453 | else |
450 | __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); | 454 | l2x0_saved_regs.data_latency = 0x110; |
455 | |||
456 | l2x0_saved_regs.prefetch_ctrl = 0x30000007; | ||
457 | l2x0_saved_regs.pwr_ctrl = | ||
458 | (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN); | ||
459 | |||
460 | l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs); | ||
451 | 461 | ||
452 | /* L2X0 Prefetch Control */ | 462 | __raw_writel(l2x0_saved_regs.tag_latency, |
453 | __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL); | 463 | S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL); |
464 | __raw_writel(l2x0_saved_regs.data_latency, | ||
465 | S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); | ||
454 | 466 | ||
455 | /* L2X0 Power Control */ | 467 | /* L2X0 Prefetch Control */ |
456 | __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN, | 468 | __raw_writel(l2x0_saved_regs.prefetch_ctrl, |
457 | S5P_VA_L2CC + L2X0_POWER_CTRL); | 469 | S5P_VA_L2CC + L2X0_PREFETCH_CTRL); |
470 | |||
471 | /* L2X0 Power Control */ | ||
472 | __raw_writel(l2x0_saved_regs.pwr_ctrl, | ||
473 | S5P_VA_L2CC + L2X0_POWER_CTRL); | ||
474 | |||
475 | clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long)); | ||
476 | clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs)); | ||
477 | } | ||
458 | 478 | ||
459 | l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff); | 479 | l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff); |
460 | 480 | ||