diff options
-rw-r--r-- | arch/arm/kernel/hw_breakpoint.c | 25 |
1 files changed, 5 insertions, 20 deletions
diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c index 76a650a1a1d7..c87ea68d64ae 100644 --- a/arch/arm/kernel/hw_breakpoint.c +++ b/arch/arm/kernel/hw_breakpoint.c | |||
@@ -235,13 +235,6 @@ static int enable_monitor_mode(void) | |||
235 | 235 | ||
236 | ARM_DBG_READ(c1, 0, dscr); | 236 | ARM_DBG_READ(c1, 0, dscr); |
237 | 237 | ||
238 | /* Ensure that halting mode is disabled. */ | ||
239 | if (WARN_ONCE(dscr & ARM_DSCR_HDBGEN, | ||
240 | "halting debug mode enabled. Unable to access hardware resources.\n")) { | ||
241 | ret = -EPERM; | ||
242 | goto out; | ||
243 | } | ||
244 | |||
245 | /* If monitor mode is already enabled, just return. */ | 238 | /* If monitor mode is already enabled, just return. */ |
246 | if (dscr & ARM_DSCR_MDBGEN) | 239 | if (dscr & ARM_DSCR_MDBGEN) |
247 | goto out; | 240 | goto out; |
@@ -255,6 +248,7 @@ static int enable_monitor_mode(void) | |||
255 | case ARM_DEBUG_ARCH_V7_ECP14: | 248 | case ARM_DEBUG_ARCH_V7_ECP14: |
256 | case ARM_DEBUG_ARCH_V7_1: | 249 | case ARM_DEBUG_ARCH_V7_1: |
257 | ARM_DBG_WRITE(c2, 2, (dscr | ARM_DSCR_MDBGEN)); | 250 | ARM_DBG_WRITE(c2, 2, (dscr | ARM_DSCR_MDBGEN)); |
251 | isb(); | ||
258 | break; | 252 | break; |
259 | default: | 253 | default: |
260 | ret = -ENODEV; | 254 | ret = -ENODEV; |
@@ -1000,8 +994,6 @@ static struct notifier_block __cpuinitdata dbg_reset_nb = { | |||
1000 | 994 | ||
1001 | static int __init arch_hw_breakpoint_init(void) | 995 | static int __init arch_hw_breakpoint_init(void) |
1002 | { | 996 | { |
1003 | u32 dscr; | ||
1004 | |||
1005 | debug_arch = get_debug_arch(); | 997 | debug_arch = get_debug_arch(); |
1006 | 998 | ||
1007 | if (!debug_arch_supported()) { | 999 | if (!debug_arch_supported()) { |
@@ -1036,17 +1028,10 @@ static int __init arch_hw_breakpoint_init(void) | |||
1036 | core_num_brps, core_has_mismatch_brps() ? "(+1 reserved) " : | 1028 | core_num_brps, core_has_mismatch_brps() ? "(+1 reserved) " : |
1037 | "", core_num_wrps); | 1029 | "", core_num_wrps); |
1038 | 1030 | ||
1039 | ARM_DBG_READ(c1, 0, dscr); | 1031 | /* Work out the maximum supported watchpoint length. */ |
1040 | if (dscr & ARM_DSCR_HDBGEN) { | 1032 | max_watchpoint_len = get_max_wp_len(); |
1041 | max_watchpoint_len = 4; | 1033 | pr_info("maximum watchpoint size is %u bytes.\n", |
1042 | pr_warning("halting debug mode enabled. Assuming maximum watchpoint size of %u bytes.\n", | 1034 | max_watchpoint_len); |
1043 | max_watchpoint_len); | ||
1044 | } else { | ||
1045 | /* Work out the maximum supported watchpoint length. */ | ||
1046 | max_watchpoint_len = get_max_wp_len(); | ||
1047 | pr_info("maximum watchpoint size is %u bytes.\n", | ||
1048 | max_watchpoint_len); | ||
1049 | } | ||
1050 | 1035 | ||
1051 | /* Register debug fault handler. */ | 1036 | /* Register debug fault handler. */ |
1052 | hook_fault_code(FAULT_CODE_DEBUG, hw_breakpoint_pending, SIGTRAP, | 1037 | hook_fault_code(FAULT_CODE_DEBUG, hw_breakpoint_pending, SIGTRAP, |