2 files changed, 20 insertions, 17 deletions

diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/generic.c
index fa72a39e5d46..3982357de5b0 100644
--- a/arch/x86/kernel/cpu/mtrr/generic.c
+++ b/arch/x86/kernel/cpu/mtrr/generic.c
@@ -510,8 +510,9 @@ generic_get_free_region(unsigned long base, unsigned long size, int replace_reg)
 static void generic_get_mtrr(unsigned int reg, unsigned long *base,
                              unsigned long *size, mtrr_type *type)
 {
-        unsigned int mask_lo, mask_hi, base_lo, base_hi;
-        unsigned int tmp, hi;
+        u32 mask_lo, mask_hi, base_lo, base_hi;
+        unsigned int hi;
+        u64 tmp, mask;
 
         /*
          * get_mtrr doesn't need to update mtrr_state, also it could be called
@@ -532,18 +533,18 @@ static void generic_get_mtrr(unsigned int reg, unsigned long *base,
         rdmsr(MTRRphysBase_MSR(reg), base_lo, base_hi);
 
         /* Work out the shifted address mask: */
-        tmp = mask_hi << (32 - PAGE_SHIFT) | mask_lo >> PAGE_SHIFT;
-        mask_lo = size_or_mask | tmp;
+        tmp = (u64)mask_hi << (32 - PAGE_SHIFT) | mask_lo >> PAGE_SHIFT;
+        mask = size_or_mask | tmp;
 
         /* Expand tmp with high bits to all 1s: */
-        hi = fls(tmp);
+        hi = fls64(tmp);
         if (hi > 0) {
-                tmp |= ~((1<<(hi - 1)) - 1);
+                tmp |= ~((1ULL<<(hi - 1)) - 1);
 
-                if (tmp != mask_lo) {
+                if (tmp != mask) {
                         printk(KERN_WARNING "mtrr: your BIOS has configured an incorrect mask, fixing it.\n");
                         add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
-                        mask_lo = tmp;
+                        mask = tmp;
                 }
         }
 
@@ -551,8 +552,8 @@ static void generic_get_mtrr(unsigned int reg, unsigned long *base,
          * This works correctly if size is a power of two, i.e. a
          * contiguous range:
          */
-        *size = -mask_lo;
-        *base = base_hi << (32 - PAGE_SHIFT) | base_lo >> PAGE_SHIFT;
+        *size = -mask;
+        *base = (u64)base_hi << (32 - PAGE_SHIFT) | base_lo >> PAGE_SHIFT;
         *type = base_lo & 0xff;
 
 out_put_cpu:
diff --git a/arch/x86/kernel/cpu/mtrr/main.c b/arch/x86/kernel/cpu/mtrr/main.c
index 726bf963c227..ca22b73aaa25 100644
--- a/arch/x86/kernel/cpu/mtrr/main.c
+++ b/arch/x86/kernel/cpu/mtrr/main.c
@@ -305,7 +305,8 @@ int mtrr_add_page(unsigned long base, unsigned long size,
                 return -EINVAL;
         }
 
-        if (base & size_or_mask || size & size_or_mask) {
+        if ((base | (base + size - 1)) >>
+            (boot_cpu_data.x86_phys_bits - PAGE_SHIFT)) {
                 pr_warning("mtrr: base or size exceeds the MTRR width\n");
                 return -EINVAL;
         }
@@ -583,6 +584,7 @@ static struct syscore_ops mtrr_syscore_ops = {
 
 int __initdata changed_by_mtrr_cleanup;
 
+#define SIZE_OR_MASK_BITS(n)  (~((1ULL << ((n) - PAGE_SHIFT)) - 1))
 /**
  * mtrr_bp_init - initialize mtrrs on the boot CPU
  *
@@ -600,7 +602,7 @@ void __init mtrr_bp_init(void)
 
         if (cpu_has_mtrr) {
                 mtrr_if = &generic_mtrr_ops;
-                size_or_mask = 0xff000000;                      /* 36 bits */
+                size_or_mask = SIZE_OR_MASK_BITS(36);
                 size_and_mask = 0x00f00000;
                 phys_addr = 36;
 
@@ -619,7 +621,7 @@ void __init mtrr_bp_init(void)
                              boot_cpu_data.x86_mask == 0x4))
                                 phys_addr = 36;
 
-                        size_or_mask = ~((1ULL << (phys_addr - PAGE_SHIFT)) - 1);
+                        size_or_mask = SIZE_OR_MASK_BITS(phys_addr);
                         size_and_mask = ~size_or_mask & 0xfffff00000ULL;
                 } else if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR &&
                            boot_cpu_data.x86 == 6) {
@@ -627,7 +629,7 @@ void __init mtrr_bp_init(void)
                          * VIA C* family have Intel style MTRRs,
                          * but don't support PAE
                          */
-                        size_or_mask = 0xfff00000;              /* 32 bits */
+                        size_or_mask = SIZE_OR_MASK_BITS(32);
                         size_and_mask = 0;
                         phys_addr = 32;
                 }
@@ -637,21 +639,21 @@ void __init mtrr_bp_init(void)
                         if (cpu_has_k6_mtrr) {
                                 /* Pre-Athlon (K6) AMD CPU MTRRs */
                                 mtrr_if = mtrr_ops[X86_VENDOR_AMD];
-                                size_or_mask = 0xfff00000;      /* 32 bits */
+                                size_or_mask = SIZE_OR_MASK_BITS(32);
                                 size_and_mask = 0;
                         }
                         break;
                 case X86_VENDOR_CENTAUR:
                         if (cpu_has_centaur_mcr) {
                                 mtrr_if = mtrr_ops[X86_VENDOR_CENTAUR];
-                                size_or_mask = 0xfff00000;      /* 32 bits */
+                                size_or_mask = SIZE_OR_MASK_BITS(32);
                                 size_and_mask = 0;
                         }
                         break;
                 case X86_VENDOR_CYRIX:
                         if (cpu_has_cyrix_arr) {
                                 mtrr_if = mtrr_ops[X86_VENDOR_CYRIX];
-                                size_or_mask = 0xfff00000;      /* 32 bits */
+                                size_or_mask = SIZE_OR_MASK_BITS(32);
                                 size_and_mask = 0;
                         }
                         break;