diff options
-rw-r--r-- | arch/arm/mm/cache-l2x0.c | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index a8d02c048a1f..2a8e380501e8 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c | |||
@@ -81,10 +81,13 @@ static inline void l2x0_inv_line(unsigned long addr) | |||
81 | } | 81 | } |
82 | 82 | ||
83 | #if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915) | 83 | #if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915) |
84 | static inline void debug_writel(unsigned long val) | ||
85 | { | ||
86 | if (outer_cache.set_debug) | ||
87 | outer_cache.set_debug(val); | ||
88 | } | ||
84 | 89 | ||
85 | #define debug_writel(val) outer_cache.set_debug(val) | 90 | static void pl310_set_debug(unsigned long val) |
86 | |||
87 | static void l2x0_set_debug(unsigned long val) | ||
88 | { | 91 | { |
89 | writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL); | 92 | writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL); |
90 | } | 93 | } |
@@ -94,7 +97,7 @@ static inline void debug_writel(unsigned long val) | |||
94 | { | 97 | { |
95 | } | 98 | } |
96 | 99 | ||
97 | #define l2x0_set_debug NULL | 100 | #define pl310_set_debug NULL |
98 | #endif | 101 | #endif |
99 | 102 | ||
100 | #ifdef CONFIG_PL310_ERRATA_588369 | 103 | #ifdef CONFIG_PL310_ERRATA_588369 |
@@ -331,6 +334,7 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) | |||
331 | /* Unmapped register. */ | 334 | /* Unmapped register. */ |
332 | sync_reg_offset = L2X0_DUMMY_REG; | 335 | sync_reg_offset = L2X0_DUMMY_REG; |
333 | #endif | 336 | #endif |
337 | outer_cache.set_debug = pl310_set_debug; | ||
334 | break; | 338 | break; |
335 | case L2X0_CACHE_ID_PART_L210: | 339 | case L2X0_CACHE_ID_PART_L210: |
336 | ways = (aux >> 13) & 0xf; | 340 | ways = (aux >> 13) & 0xf; |
@@ -379,7 +383,6 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) | |||
379 | outer_cache.flush_all = l2x0_flush_all; | 383 | outer_cache.flush_all = l2x0_flush_all; |
380 | outer_cache.inv_all = l2x0_inv_all; | 384 | outer_cache.inv_all = l2x0_inv_all; |
381 | outer_cache.disable = l2x0_disable; | 385 | outer_cache.disable = l2x0_disable; |
382 | outer_cache.set_debug = l2x0_set_debug; | ||
383 | 386 | ||
384 | printk(KERN_INFO "%s cache controller enabled\n", type); | 387 | printk(KERN_INFO "%s cache controller enabled\n", type); |
385 | printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n", | 388 | printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n", |