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-rw-r--r--arch/blackfin/Kconfig.debug2
-rw-r--r--arch/blackfin/kernel/Makefile2
-rw-r--r--arch/blackfin/kernel/debug-mmrs.c1860
3 files changed, 1863 insertions, 1 deletions
diff --git a/arch/blackfin/Kconfig.debug b/arch/blackfin/Kconfig.debug
index 2641731f24cd..825d59e8ae45 100644
--- a/arch/blackfin/Kconfig.debug
+++ b/arch/blackfin/Kconfig.debug
@@ -32,7 +32,7 @@ config DEBUG_VERBOSE
32 Most people should say N here. 32 Most people should say N here.
33 33
34config DEBUG_MMRS 34config DEBUG_MMRS
35 bool "Generate Blackfin MMR tree" 35 tristate "Generate Blackfin MMR tree"
36 select DEBUG_FS 36 select DEBUG_FS
37 help 37 help
38 Create a tree of Blackfin MMRs via the debugfs tree. If 38 Create a tree of Blackfin MMRs via the debugfs tree. If
diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile
index ca5ccc777772..18ba6abd66db 100644
--- a/arch/blackfin/kernel/Makefile
+++ b/arch/blackfin/kernel/Makefile
@@ -37,3 +37,5 @@ obj-$(CONFIG_BFIN_PSEUDODBG_INSNS) += pseudodbg.o
37# the kgdb test puts code into L2 and without linker 37# the kgdb test puts code into L2 and without linker
38# relaxation, we need to force long calls to/from it 38# relaxation, we need to force long calls to/from it
39CFLAGS_kgdb_test.o := -mlong-calls -O0 39CFLAGS_kgdb_test.o := -mlong-calls -O0
40
41obj-$(CONFIG_DEBUG_MMRS) += debug-mmrs.o
diff --git a/arch/blackfin/kernel/debug-mmrs.c b/arch/blackfin/kernel/debug-mmrs.c
new file mode 100644
index 000000000000..94b1d8a0256a
--- /dev/null
+++ b/arch/blackfin/kernel/debug-mmrs.c
@@ -0,0 +1,1860 @@
1/*
2 * debugfs interface to core/system MMRs
3 *
4 * Copyright 2007-2011 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later
7 */
8
9#include <linux/debugfs.h>
10#include <linux/fs.h>
11#include <linux/kernel.h>
12#include <linux/module.h>
13
14#include <asm/blackfin.h>
15#include <asm/gpio.h>
16#include <asm/bfin_can.h>
17#include <asm/bfin_dma.h>
18#include <asm/bfin_ppi.h>
19#include <asm/bfin_serial.h>
20#include <asm/bfin5xx_spi.h>
21#include <asm/bfin_twi.h>
22
23/* Common code defines PORT_MUX on us, so redirect the MMR back locally */
24#ifdef BFIN_PORT_MUX
25#undef PORT_MUX
26#define PORT_MUX BFIN_PORT_MUX
27#endif
28
29#define _d(name, bits, addr, perms) debugfs_create_x##bits(name, perms, parent, (u##bits *)addr)
30#define d(name, bits, addr) _d(name, bits, addr, S_IRUSR|S_IWUSR)
31#define d_RO(name, bits, addr) _d(name, bits, addr, S_IRUSR)
32#define d_WO(name, bits, addr) _d(name, bits, addr, S_IWUSR)
33
34#define D_RO(name, bits) d_RO(#name, bits, name)
35#define D_WO(name, bits) d_WO(#name, bits, name)
36#define D32(name) d(#name, 32, name)
37#define D16(name) d(#name, 16, name)
38
39#define REGS_OFF(peri, mmr) offsetof(struct bfin_##peri##_regs, mmr)
40#define __REGS(peri, sname, rname) \
41 do { \
42 struct bfin_##peri##_regs r; \
43 void *addr = (void *)(base + REGS_OFF(peri, rname)); \
44 strcpy(_buf, sname); \
45 if (sizeof(r.rname) == 2) \
46 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, parent, addr); \
47 else \
48 debugfs_create_x32(buf, S_IRUSR|S_IWUSR, parent, addr); \
49 } while (0)
50#define REGS_STR_PFX(buf, pfx, num) \
51 ({ \
52 buf + (num >= 0 ? \
53 sprintf(buf, #pfx "%i_", num) : \
54 sprintf(buf, #pfx "_")); \
55 })
56#define REGS_STR_PFX_C(buf, pfx, num) \
57 ({ \
58 buf + (num >= 0 ? \
59 sprintf(buf, #pfx "%c_", 'A' + num) : \
60 sprintf(buf, #pfx "_")); \
61 })
62
63/*
64 * Core registers (not memory mapped)
65 */
66extern u32 last_seqstat;
67
68static int debug_cclk_get(void *data, u64 *val)
69{
70 *val = get_cclk();
71 return 0;
72}
73DEFINE_SIMPLE_ATTRIBUTE(fops_debug_cclk, debug_cclk_get, NULL, "0x%08llx\n");
74
75static int debug_sclk_get(void *data, u64 *val)
76{
77 *val = get_sclk();
78 return 0;
79}
80DEFINE_SIMPLE_ATTRIBUTE(fops_debug_sclk, debug_sclk_get, NULL, "0x%08llx\n");
81
82#define DEFINE_SYSREG(sr, pre, post) \
83static int sysreg_##sr##_get(void *data, u64 *val) \
84{ \
85 unsigned long tmp; \
86 pre; \
87 __asm__ __volatile__("%0 = " #sr ";" : "=d"(tmp)); \
88 *val = tmp; \
89 return 0; \
90} \
91static int sysreg_##sr##_set(void *data, u64 val) \
92{ \
93 unsigned long tmp = val; \
94 __asm__ __volatile__(#sr " = %0;" : : "d"(tmp)); \
95 post; \
96 return 0; \
97} \
98DEFINE_SIMPLE_ATTRIBUTE(fops_sysreg_##sr, sysreg_##sr##_get, sysreg_##sr##_set, "0x%08llx\n")
99
100DEFINE_SYSREG(cycles, , );
101DEFINE_SYSREG(cycles2, __asm__ __volatile__("%0 = cycles;" : "=d"(tmp)), );
102DEFINE_SYSREG(emudat, , );
103DEFINE_SYSREG(seqstat, , );
104DEFINE_SYSREG(syscfg, , CSYNC());
105#define D_SYSREG(sr) debugfs_create_file(#sr, S_IRUSR|S_IWUSR, parent, NULL, &fops_sysreg_##sr)
106
107/*
108 * CAN
109 */
110#define CAN_OFF(mmr) REGS_OFF(can, mmr)
111#define __CAN(uname, lname) __REGS(can, #uname, lname)
112static void __init __maybe_unused
113bfin_debug_mmrs_can(struct dentry *parent, unsigned long base, int num)
114{
115 static struct dentry *am, *mb;
116 int i, j;
117 char buf[32], *_buf = REGS_STR_PFX(buf, CAN, num);
118
119 if (!am) {
120 am = debugfs_create_dir("am", parent);
121 mb = debugfs_create_dir("mb", parent);
122 }
123
124 __CAN(MC1, mc1);
125 __CAN(MD1, md1);
126 __CAN(TRS1, trs1);
127 __CAN(TRR1, trr1);
128 __CAN(TA1, ta1);
129 __CAN(AA1, aa1);
130 __CAN(RMP1, rmp1);
131 __CAN(RML1, rml1);
132 __CAN(MBTIF1, mbtif1);
133 __CAN(MBRIF1, mbrif1);
134 __CAN(MBIM1, mbim1);
135 __CAN(RFH1, rfh1);
136 __CAN(OPSS1, opss1);
137
138 __CAN(MC2, mc2);
139 __CAN(MD2, md2);
140 __CAN(TRS2, trs2);
141 __CAN(TRR2, trr2);
142 __CAN(TA2, ta2);
143 __CAN(AA2, aa2);
144 __CAN(RMP2, rmp2);
145 __CAN(RML2, rml2);
146 __CAN(MBTIF2, mbtif2);
147 __CAN(MBRIF2, mbrif2);
148 __CAN(MBIM2, mbim2);
149 __CAN(RFH2, rfh2);
150 __CAN(OPSS2, opss2);
151
152 __CAN(CLOCK, clock);
153 __CAN(TIMING, timing);
154 __CAN(DEBUG, debug);
155 __CAN(STATUS, status);
156 __CAN(CEC, cec);
157 __CAN(GIS, gis);
158 __CAN(GIM, gim);
159 __CAN(GIF, gif);
160 __CAN(CONTROL, control);
161 __CAN(INTR, intr);
162 __CAN(VERSION, version);
163 __CAN(MBTD, mbtd);
164 __CAN(EWR, ewr);
165 __CAN(ESR, esr);
166 /*__CAN(UCREG, ucreg); no longer exists */
167 __CAN(UCCNT, uccnt);
168 __CAN(UCRC, ucrc);
169 __CAN(UCCNF, uccnf);
170 __CAN(VERSION2, version2);
171
172 for (i = 0; i < 32; ++i) {
173 sprintf(_buf, "AM%02iL", i);
174 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, am,
175 (u16 *)(base + CAN_OFF(msk[i].aml)));
176 sprintf(_buf, "AM%02iH", i);
177 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, am,
178 (u16 *)(base + CAN_OFF(msk[i].amh)));
179
180 for (j = 0; j < 3; ++j) {
181 sprintf(_buf, "MB%02i_DATA%i", i, j);
182 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
183 (u16 *)(base + CAN_OFF(chl[i].data[j*2])));
184 }
185 sprintf(_buf, "MB%02i_LENGTH", i);
186 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
187 (u16 *)(base + CAN_OFF(chl[i].dlc)));
188 sprintf(_buf, "MB%02i_TIMESTAMP", i);
189 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
190 (u16 *)(base + CAN_OFF(chl[i].tsv)));
191 sprintf(_buf, "MB%02i_ID0", i);
192 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
193 (u16 *)(base + CAN_OFF(chl[i].id0)));
194 sprintf(_buf, "MB%02i_ID1", i);
195 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
196 (u16 *)(base + CAN_OFF(chl[i].id1)));
197 }
198}
199#define CAN(num) bfin_debug_mmrs_can(parent, CAN##num##_MC1, num)
200
201/*
202 * DMA
203 */
204#define __DMA(uname, lname) __REGS(dma, #uname, lname)
205static void __init __maybe_unused
206bfin_debug_mmrs_dma(struct dentry *parent, unsigned long base, int num, char mdma, const char *pfx)
207{
208 char buf[32], *_buf;
209
210 if (mdma)
211 _buf = buf + sprintf(buf, "%s_%c%i_", pfx, mdma, num);
212 else
213 _buf = buf + sprintf(buf, "%s%i_", pfx, num);
214
215 __DMA(NEXT_DESC_PTR, next_desc_ptr);
216 __DMA(START_ADDR, start_addr);
217 __DMA(CONFIG, config);
218 __DMA(X_COUNT, x_count);
219 __DMA(X_MODIFY, x_modify);
220 __DMA(Y_COUNT, y_count);
221 __DMA(Y_MODIFY, y_modify);
222 __DMA(CURR_DESC_PTR, curr_desc_ptr);
223 __DMA(CURR_ADDR, curr_addr);
224 __DMA(IRQ_STATUS, irq_status);
225 __DMA(PERIPHERAL_MAP, peripheral_map);
226 __DMA(CURR_X_COUNT, curr_x_count);
227 __DMA(CURR_Y_COUNT, curr_y_count);
228}
229#define _DMA(num, base, mdma, pfx) bfin_debug_mmrs_dma(parent, base, num, mdma, pfx "DMA")
230#define DMA(num) _DMA(num, DMA##num##_NEXT_DESC_PTR, 0, "")
231#define _MDMA(num, x) \
232 do { \
233 _DMA(num, x##DMA_D##num##_CONFIG, 'D', #x); \
234 _DMA(num, x##DMA_S##num##_CONFIG, 'S', #x); \
235 } while (0)
236#define MDMA(num) _MDMA(num, M)
237#define IMDMA(num) _MDMA(num, IM)
238
239/*
240 * EPPI
241 */
242#define __EPPI(uname, lname) __REGS(eppi, #uname, lname)
243static void __init __maybe_unused
244bfin_debug_mmrs_eppi(struct dentry *parent, unsigned long base, int num)
245{
246 char buf[32], *_buf = REGS_STR_PFX(buf, EPPI, num);
247 __EPPI(STATUS, status);
248 __EPPI(HCOUNT, hcount);
249 __EPPI(HDELAY, hdelay);
250 __EPPI(VCOUNT, vcount);
251 __EPPI(VDELAY, vdelay);
252 __EPPI(FRAME, frame);
253 __EPPI(LINE, line);
254 __EPPI(CLKDIV, clkdiv);
255 __EPPI(CONTROL, control);
256 __EPPI(FS1W_HBL, fs1w_hbl);
257 __EPPI(FS1P_AVPL, fs1p_avpl);
258 __EPPI(FS2W_LVB, fs2w_lvb);
259 __EPPI(FS2P_LAVF, fs2p_lavf);
260 __EPPI(CLIP, clip);
261}
262#define EPPI(num) bfin_debug_mmrs_eppi(parent, EPPI##num##_STATUS, num)
263
264/*
265 * General Purpose Timers
266 */
267#define GPTIMER_OFF(mmr) (TIMER0_##mmr - TIMER0_CONFIG)
268#define __GPTIMER(name) \
269 do { \
270 strcpy(_buf, #name); \
271 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, parent, (u16 *)(base + GPTIMER_OFF(name))); \
272 } while (0)
273static void __init __maybe_unused
274bfin_debug_mmrs_gptimer(struct dentry *parent, unsigned long base, int num)
275{
276 char buf[32], *_buf = REGS_STR_PFX(buf, TIMER, num);
277 __GPTIMER(CONFIG);
278 __GPTIMER(COUNTER);
279 __GPTIMER(PERIOD);
280 __GPTIMER(WIDTH);
281}
282#define GPTIMER(num) bfin_debug_mmrs_gptimer(parent, TIMER##num##_CONFIG, num)
283
284/*
285 * Handshake MDMA
286 */
287#define __HMDMA(uname, lname) __REGS(hmdma, #uname, lname)
288static void __init __maybe_unused
289bfin_debug_mmrs_hmdma(struct dentry *parent, unsigned long base, int num)
290{
291 char buf[32], *_buf = REGS_STR_PFX(buf, HMDMA, num);
292 __HMDMA(CONTROL, control);
293 __HMDMA(ECINIT, ecinit);
294 __HMDMA(BCINIT, bcinit);
295 __HMDMA(ECURGENT, ecurgent);
296 __HMDMA(ECOVERFLOW, ecoverflow);
297 __HMDMA(ECOUNT, ecount);
298 __HMDMA(BCOUNT, bcount);
299}
300#define HMDMA(num) bfin_debug_mmrs_hmdma(parent, HMDMA##num##_CONTROL, num)
301
302/*
303 * Port/GPIO
304 */
305#define bfin_gpio_regs gpio_port_t
306#define __PORT(uname, lname) __REGS(gpio, #uname, lname)
307static void __init __maybe_unused
308bfin_debug_mmrs_port(struct dentry *parent, unsigned long base, int num)
309{
310 char buf[32], *_buf;
311#ifdef __ADSPBF54x__
312 _buf = REGS_STR_PFX_C(buf, PORT, num);
313 __PORT(FER, port_fer);
314 __PORT(SET, data_set);
315 __PORT(CLEAR, data_clear);
316 __PORT(DIR_SET, dir_set);
317 __PORT(DIR_CLEAR, dir_clear);
318 __PORT(INEN, inen);
319 __PORT(MUX, port_mux);
320#else
321 _buf = buf + sprintf(buf, "PORT%cIO_", num);
322 __PORT(CLEAR, data_clear);
323 __PORT(SET, data_set);
324 __PORT(TOGGLE, toggle);
325 __PORT(MASKA, maska);
326 __PORT(MASKA_CLEAR, maska_clear);
327 __PORT(MASKA_SET, maska_set);
328 __PORT(MASKA_TOGGLE, maska_toggle);
329 __PORT(MASKB, maskb);
330 __PORT(MASKB_CLEAR, maskb_clear);
331 __PORT(MASKB_SET, maskb_set);
332 __PORT(MASKB_TOGGLE, maskb_toggle);
333 __PORT(DIR, dir);
334 __PORT(POLAR, polar);
335 __PORT(EDGE, edge);
336 __PORT(BOTH, both);
337 __PORT(INEN, inen);
338#endif
339 _buf[-1] = '\0';
340 d(buf, 16, base + REGS_OFF(gpio, data));
341}
342#define PORT(base, num) bfin_debug_mmrs_port(parent, base, num)
343
344/*
345 * PPI
346 */
347#define __PPI(uname, lname) __REGS(ppi, #uname, lname)
348static void __init __maybe_unused
349bfin_debug_mmrs_ppi(struct dentry *parent, unsigned long base, int num)
350{
351 char buf[32], *_buf = REGS_STR_PFX(buf, PPI, num);
352 __PPI(CONTROL, control);
353 __PPI(STATUS, status);
354 __PPI(COUNT, count);
355 __PPI(DELAY, delay);
356 __PPI(FRAME, frame);
357}
358#define PPI(num) bfin_debug_mmrs_ppi(parent, PPI##num##_STATUS, num)
359
360/*
361 * SPI
362 */
363#define __SPI(uname, lname) __REGS(spi, #uname, lname)
364static void __init __maybe_unused
365bfin_debug_mmrs_spi(struct dentry *parent, unsigned long base, int num)
366{
367 char buf[32], *_buf = REGS_STR_PFX(buf, SPI, num);
368 __SPI(CTL, ctl);
369 __SPI(FLG, flg);
370 __SPI(STAT, stat);
371 __SPI(TDBR, tdbr);
372 __SPI(RDBR, rdbr);
373 __SPI(BAUD, baud);
374 __SPI(SHADOW, shadow);
375}
376#define SPI(num) bfin_debug_mmrs_spi(parent, SPI##num##_REGBASE, num)
377
378/*
379 * SPORT
380 */
381static inline int sport_width(void *mmr)
382{
383 unsigned long lmmr = (unsigned long)mmr;
384 if ((lmmr & 0xff) == 0x10)
385 /* SPORT#_TX has 0x10 offset -> SPORT#_TCR2 has 0x04 offset */
386 lmmr -= 0xc;
387 else
388 /* SPORT#_RX has 0x18 offset -> SPORT#_RCR2 has 0x24 offset */
389 lmmr += 0xc;
390 /* extract SLEN field from control register 2 and add 1 */
391 return (bfin_read16(lmmr) & 0x1f) + 1;
392}
393static int sport_set(void *mmr, u64 val)
394{
395 unsigned long flags;
396 local_irq_save(flags);
397 if (sport_width(mmr) <= 16)
398 bfin_write16(mmr, val);
399 else
400 bfin_write32(mmr, val);
401 local_irq_restore(flags);
402 return 0;
403}
404static int sport_get(void *mmr, u64 *val)
405{
406 unsigned long flags;
407 local_irq_save(flags);
408 if (sport_width(mmr) <= 16)
409 *val = bfin_read16(mmr);
410 else
411 *val = bfin_read32(mmr);
412 local_irq_restore(flags);
413 return 0;
414}
415DEFINE_SIMPLE_ATTRIBUTE(fops_sport, sport_get, sport_set, "0x%08llx\n");
416/*DEFINE_SIMPLE_ATTRIBUTE(fops_sport_ro, sport_get, NULL, "0x%08llx\n");*/
417DEFINE_SIMPLE_ATTRIBUTE(fops_sport_wo, NULL, sport_set, "0x%08llx\n");
418#define SPORT_OFF(mmr) (SPORT0_##mmr - SPORT0_TCR1)
419#define _D_SPORT(name, perms, fops) \
420 do { \
421 strcpy(_buf, #name); \
422 debugfs_create_file(buf, perms, parent, (void *)(base + SPORT_OFF(name)), fops); \
423 } while (0)
424#define __SPORT_RW(name) _D_SPORT(name, S_IRUSR|S_IWUSR, &fops_sport)
425#define __SPORT_RO(name) _D_SPORT(name, S_IRUSR, &fops_sport_ro)
426#define __SPORT_WO(name) _D_SPORT(name, S_IWUSR, &fops_sport_wo)
427#define __SPORT(name, bits) \
428 do { \
429 strcpy(_buf, #name); \
430 debugfs_create_x##bits(buf, S_IRUSR|S_IWUSR, parent, (u##bits *)(base + SPORT_OFF(name))); \
431 } while (0)
432static void __init __maybe_unused
433bfin_debug_mmrs_sport(struct dentry *parent, unsigned long base, int num)
434{
435 char buf[32], *_buf = REGS_STR_PFX(buf, SPORT, num);
436 __SPORT(CHNL, 16);
437 __SPORT(MCMC1, 16);
438 __SPORT(MCMC2, 16);
439 __SPORT(MRCS0, 32);
440 __SPORT(MRCS1, 32);
441 __SPORT(MRCS2, 32);
442 __SPORT(MRCS3, 32);
443 __SPORT(MTCS0, 32);
444 __SPORT(MTCS1, 32);
445 __SPORT(MTCS2, 32);
446 __SPORT(MTCS3, 32);
447 __SPORT(RCLKDIV, 16);
448 __SPORT(RCR1, 16);
449 __SPORT(RCR2, 16);
450 __SPORT(RFSDIV, 16);
451 __SPORT_RW(RX);
452 __SPORT(STAT, 16);
453 __SPORT(TCLKDIV, 16);
454 __SPORT(TCR1, 16);
455 __SPORT(TCR2, 16);
456 __SPORT(TFSDIV, 16);
457 __SPORT_WO(TX);
458}
459#define SPORT(num) bfin_debug_mmrs_sport(parent, SPORT##num##_TCR1, num)
460
461/*
462 * TWI
463 */
464#define __TWI(uname, lname) __REGS(twi, #uname, lname)
465static void __init __maybe_unused
466bfin_debug_mmrs_twi(struct dentry *parent, unsigned long base, int num)
467{
468 char buf[32], *_buf = REGS_STR_PFX(buf, TWI, num);
469 __TWI(CLKDIV, clkdiv);
470 __TWI(CONTROL, control);
471 __TWI(SLAVE_CTL, slave_ctl);
472 __TWI(SLAVE_STAT, slave_stat);
473 __TWI(SLAVE_ADDR, slave_addr);
474 __TWI(MASTER_CTL, master_ctl);
475 __TWI(MASTER_STAT, master_stat);
476 __TWI(MASTER_ADDR, master_addr);
477 __TWI(INT_STAT, int_stat);
478 __TWI(INT_MASK, int_mask);
479 __TWI(FIFO_CTL, fifo_ctl);
480 __TWI(FIFO_STAT, fifo_stat);
481 __TWI(XMT_DATA8, xmt_data8);
482 __TWI(XMT_DATA16, xmt_data16);
483 __TWI(RCV_DATA8, rcv_data8);
484 __TWI(RCV_DATA16, rcv_data16);
485}
486#define TWI(num) bfin_debug_mmrs_twi(parent, TWI##num##_CLKDIV, num)
487
488/*
489 * UART
490 */
491#define __UART(uname, lname) __REGS(uart, #uname, lname)
492static void __init __maybe_unused
493bfin_debug_mmrs_uart(struct dentry *parent, unsigned long base, int num)
494{
495 char buf[32], *_buf = REGS_STR_PFX(buf, UART, num);
496#ifdef BFIN_UART_BF54X_STYLE
497 __UART(DLL, dll);
498 __UART(DLH, dlh);
499 __UART(GCTL, gctl);
500 __UART(LCR, lcr);
501 __UART(MCR, mcr);
502 __UART(LSR, lsr);
503 __UART(MSR, msr);
504 __UART(SCR, scr);
505 __UART(IER_SET, ier_set);
506 __UART(IER_CLEAR, ier_clear);
507 __UART(THR, thr);
508 __UART(RBR, rbr);
509#else
510 __UART(DLL, dll);
511 __UART(THR, thr);
512 __UART(RBR, rbr);
513 __UART(DLH, dlh);
514 __UART(IER, ier);
515 __UART(IIR, iir);
516 __UART(LCR, lcr);
517 __UART(MCR, mcr);
518 __UART(LSR, lsr);
519 __UART(MSR, msr);
520 __UART(SCR, scr);
521 __UART(GCTL, gctl);
522#endif
523}
524#define UART(num) bfin_debug_mmrs_uart(parent, UART##num##_DLL, num)
525
526/*
527 * The actual debugfs generation
528 */
529static struct dentry *debug_mmrs_dentry;
530
531static int __init bfin_debug_mmrs_init(void)
532{
533 struct dentry *top, *parent;
534
535 pr_info("debug-mmrs: setting up Blackfin MMR debugfs\n");
536
537 top = debugfs_create_dir("blackfin", NULL);
538 if (top == NULL)
539 return -1;
540
541 parent = debugfs_create_dir("core_regs", top);
542 debugfs_create_file("cclk", S_IRUSR, parent, NULL, &fops_debug_cclk);
543 debugfs_create_file("sclk", S_IRUSR, parent, NULL, &fops_debug_sclk);
544 debugfs_create_x32("last_seqstat", S_IRUSR, parent, &last_seqstat);
545 D_SYSREG(cycles);
546 D_SYSREG(cycles2);
547 D_SYSREG(emudat);
548 D_SYSREG(seqstat);
549 D_SYSREG(syscfg);
550
551 /* Core MMRs */
552 parent = debugfs_create_dir("ctimer", top);
553 D32(TCNTL);
554 D32(TCOUNT);
555 D32(TPERIOD);
556 D32(TSCALE);
557
558 parent = debugfs_create_dir("cec", top);
559 D32(EVT0);
560 D32(EVT1);
561 D32(EVT2);
562 D32(EVT3);
563 D32(EVT4);
564 D32(EVT5);
565 D32(EVT6);
566 D32(EVT7);
567 D32(EVT8);
568 D32(EVT9);
569 D32(EVT10);
570 D32(EVT11);
571 D32(EVT12);
572 D32(EVT13);
573 D32(EVT14);
574 D32(EVT15);
575 D32(EVT_OVERRIDE);
576 D32(IMASK);
577 D32(IPEND);
578 D32(ILAT);
579 D32(IPRIO);
580
581 parent = debugfs_create_dir("debug", top);
582 D32(DBGSTAT);
583 D32(DSPID);
584
585 parent = debugfs_create_dir("mmu", top);
586 D32(SRAM_BASE_ADDRESS);
587 D32(DCPLB_ADDR0);
588 D32(DCPLB_ADDR10);
589 D32(DCPLB_ADDR11);
590 D32(DCPLB_ADDR12);
591 D32(DCPLB_ADDR13);
592 D32(DCPLB_ADDR14);
593 D32(DCPLB_ADDR15);
594 D32(DCPLB_ADDR1);
595 D32(DCPLB_ADDR2);
596 D32(DCPLB_ADDR3);
597 D32(DCPLB_ADDR4);
598 D32(DCPLB_ADDR5);
599 D32(DCPLB_ADDR6);
600 D32(DCPLB_ADDR7);
601 D32(DCPLB_ADDR8);
602 D32(DCPLB_ADDR9);
603 D32(DCPLB_DATA0);
604 D32(DCPLB_DATA10);
605 D32(DCPLB_DATA11);
606 D32(DCPLB_DATA12);
607 D32(DCPLB_DATA13);
608 D32(DCPLB_DATA14);
609 D32(DCPLB_DATA15);
610 D32(DCPLB_DATA1);
611 D32(DCPLB_DATA2);
612 D32(DCPLB_DATA3);
613 D32(DCPLB_DATA4);
614 D32(DCPLB_DATA5);
615 D32(DCPLB_DATA6);
616 D32(DCPLB_DATA7);
617 D32(DCPLB_DATA8);
618 D32(DCPLB_DATA9);
619 D32(DCPLB_FAULT_ADDR);
620 D32(DCPLB_STATUS);
621 D32(DMEM_CONTROL);
622 D32(DTEST_COMMAND);
623 D32(DTEST_DATA0);
624 D32(DTEST_DATA1);
625
626 D32(ICPLB_ADDR0);
627 D32(ICPLB_ADDR1);
628 D32(ICPLB_ADDR2);
629 D32(ICPLB_ADDR3);
630 D32(ICPLB_ADDR4);
631 D32(ICPLB_ADDR5);
632 D32(ICPLB_ADDR6);
633 D32(ICPLB_ADDR7);
634 D32(ICPLB_ADDR8);
635 D32(ICPLB_ADDR9);
636 D32(ICPLB_ADDR10);
637 D32(ICPLB_ADDR11);
638 D32(ICPLB_ADDR12);
639 D32(ICPLB_ADDR13);
640 D32(ICPLB_ADDR14);
641 D32(ICPLB_ADDR15);
642 D32(ICPLB_DATA0);
643 D32(ICPLB_DATA1);
644 D32(ICPLB_DATA2);
645 D32(ICPLB_DATA3);
646 D32(ICPLB_DATA4);
647 D32(ICPLB_DATA5);
648 D32(ICPLB_DATA6);
649 D32(ICPLB_DATA7);
650 D32(ICPLB_DATA8);
651 D32(ICPLB_DATA9);
652 D32(ICPLB_DATA10);
653 D32(ICPLB_DATA11);
654 D32(ICPLB_DATA12);
655 D32(ICPLB_DATA13);
656 D32(ICPLB_DATA14);
657 D32(ICPLB_DATA15);
658 D32(ICPLB_FAULT_ADDR);
659 D32(ICPLB_STATUS);
660 D32(IMEM_CONTROL);
661 if (!ANOMALY_05000481) {
662 D32(ITEST_COMMAND);
663 D32(ITEST_DATA0);
664 D32(ITEST_DATA1);
665 }
666
667 parent = debugfs_create_dir("perf", top);
668 D32(PFCNTR0);
669 D32(PFCNTR1);
670 D32(PFCTL);
671
672 parent = debugfs_create_dir("trace", top);
673 D32(TBUF);
674 D32(TBUFCTL);
675 D32(TBUFSTAT);
676
677 parent = debugfs_create_dir("watchpoint", top);
678 D32(WPIACTL);
679 D32(WPIA0);
680 D32(WPIA1);
681 D32(WPIA2);
682 D32(WPIA3);
683 D32(WPIA4);
684 D32(WPIA5);
685 D32(WPIACNT0);
686 D32(WPIACNT1);
687 D32(WPIACNT2);
688 D32(WPIACNT3);
689 D32(WPIACNT4);
690 D32(WPIACNT5);
691 D32(WPDACTL);
692 D32(WPDA0);
693 D32(WPDA1);
694 D32(WPDACNT0);
695 D32(WPDACNT1);
696 D32(WPSTAT);
697
698 /* System MMRs */
699#ifdef ATAPI_CONTROL
700 parent = debugfs_create_dir("atapi", top);
701 D16(ATAPI_CONTROL);
702 D16(ATAPI_DEV_ADDR);
703 D16(ATAPI_DEV_RXBUF);
704 D16(ATAPI_DEV_TXBUF);
705 D16(ATAPI_DMA_TFRCNT);
706 D16(ATAPI_INT_MASK);
707 D16(ATAPI_INT_STATUS);
708 D16(ATAPI_LINE_STATUS);
709 D16(ATAPI_MULTI_TIM_0);
710 D16(ATAPI_MULTI_TIM_1);
711 D16(ATAPI_MULTI_TIM_2);
712 D16(ATAPI_PIO_TFRCNT);
713 D16(ATAPI_PIO_TIM_0);
714 D16(ATAPI_PIO_TIM_1);
715 D16(ATAPI_REG_TIM_0);
716 D16(ATAPI_SM_STATE);
717 D16(ATAPI_STATUS);
718 D16(ATAPI_TERMINATE);
719 D16(ATAPI_UDMAOUT_TFRCNT);
720 D16(ATAPI_ULTRA_TIM_0);
721 D16(ATAPI_ULTRA_TIM_1);
722 D16(ATAPI_ULTRA_TIM_2);
723 D16(ATAPI_ULTRA_TIM_3);
724 D16(ATAPI_UMAIN_TFRCNT);
725 D16(ATAPI_XFER_LEN);
726#endif
727
728#if defined(CAN_MC1) || defined(CAN0_MC1) || defined(CAN1_MC1)
729 parent = debugfs_create_dir("can", top);
730# ifdef CAN_MC1
731 bfin_debug_mmrs_can(parent, CAN_MC1, -1);
732# endif
733# ifdef CAN0_MC1
734 CAN(0);
735# endif
736# ifdef CAN1_MC1
737 CAN(1);
738# endif
739#endif
740
741#ifdef CNT_COMMAND
742 parent = debugfs_create_dir("counter", top);
743 D16(CNT_COMMAND);
744 D16(CNT_CONFIG);
745 D32(CNT_COUNTER);
746 D16(CNT_DEBOUNCE);
747 D16(CNT_IMASK);
748 D32(CNT_MAX);
749 D32(CNT_MIN);
750 D16(CNT_STATUS);
751#endif
752
753 parent = debugfs_create_dir("dmac", top);
754#ifdef DMA_TC_CNT
755 D16(DMAC_TC_CNT);
756 D16(DMAC_TC_PER);
757#endif
758#ifdef DMAC0_TC_CNT
759 D16(DMAC0_TC_CNT);
760 D16(DMAC0_TC_PER);
761#endif
762#ifdef DMAC1_TC_CNT
763 D16(DMAC1_TC_CNT);
764 D16(DMAC1_TC_PER);
765#endif
766#ifdef DMAC1_PERIMUX
767 D16(DMAC1_PERIMUX);
768#endif
769
770#ifdef __ADSPBF561__
771 /* XXX: should rewrite the MMR map */
772# define DMA0_NEXT_DESC_PTR DMA2_0_NEXT_DESC_PTR
773# define DMA1_NEXT_DESC_PTR DMA2_1_NEXT_DESC_PTR
774# define DMA2_NEXT_DESC_PTR DMA2_2_NEXT_DESC_PTR
775# define DMA3_NEXT_DESC_PTR DMA2_3_NEXT_DESC_PTR
776# define DMA4_NEXT_DESC_PTR DMA2_4_NEXT_DESC_PTR
777# define DMA5_NEXT_DESC_PTR DMA2_5_NEXT_DESC_PTR
778# define DMA6_NEXT_DESC_PTR DMA2_6_NEXT_DESC_PTR
779# define DMA7_NEXT_DESC_PTR DMA2_7_NEXT_DESC_PTR
780# define DMA8_NEXT_DESC_PTR DMA2_8_NEXT_DESC_PTR
781# define DMA9_NEXT_DESC_PTR DMA2_9_NEXT_DESC_PTR
782# define DMA10_NEXT_DESC_PTR DMA2_10_NEXT_DESC_PTR
783# define DMA11_NEXT_DESC_PTR DMA2_11_NEXT_DESC_PTR
784# define DMA12_NEXT_DESC_PTR DMA1_0_NEXT_DESC_PTR
785# define DMA13_NEXT_DESC_PTR DMA1_1_NEXT_DESC_PTR
786# define DMA14_NEXT_DESC_PTR DMA1_2_NEXT_DESC_PTR
787# define DMA15_NEXT_DESC_PTR DMA1_3_NEXT_DESC_PTR
788# define DMA16_NEXT_DESC_PTR DMA1_4_NEXT_DESC_PTR
789# define DMA17_NEXT_DESC_PTR DMA1_5_NEXT_DESC_PTR
790# define DMA18_NEXT_DESC_PTR DMA1_6_NEXT_DESC_PTR
791# define DMA19_NEXT_DESC_PTR DMA1_7_NEXT_DESC_PTR
792# define DMA20_NEXT_DESC_PTR DMA1_8_NEXT_DESC_PTR
793# define DMA21_NEXT_DESC_PTR DMA1_9_NEXT_DESC_PTR
794# define DMA22_NEXT_DESC_PTR DMA1_10_NEXT_DESC_PTR
795# define DMA23_NEXT_DESC_PTR DMA1_11_NEXT_DESC_PTR
796#endif
797 parent = debugfs_create_dir("dma", top);
798 DMA(0);
799 DMA(1);
800 DMA(1);
801 DMA(2);
802 DMA(3);
803 DMA(4);
804 DMA(5);
805 DMA(6);
806 DMA(7);
807#ifdef DMA8_NEXT_DESC_PTR
808 DMA(8);
809 DMA(9);
810 DMA(10);
811 DMA(11);
812#endif
813#ifdef DMA12_NEXT_DESC_PTR
814 DMA(12);
815 DMA(13);
816 DMA(14);
817 DMA(15);
818 DMA(16);
819 DMA(17);
820 DMA(18);
821 DMA(19);
822#endif
823#ifdef DMA20_NEXT_DESC_PTR
824 DMA(20);
825 DMA(21);
826 DMA(22);
827 DMA(23);
828#endif
829
830 parent = debugfs_create_dir("ebiu_amc", top);
831 D32(EBIU_AMBCTL0);
832 D32(EBIU_AMBCTL1);
833 D16(EBIU_AMGCTL);
834#ifdef EBIU_MBSCTL
835 D16(EBIU_MBSCTL);
836 D32(EBIU_ARBSTAT);
837 D32(EBIU_MODE);
838 D16(EBIU_FCTL);
839#endif
840
841#ifdef EBIU_SDGCTL
842 parent = debugfs_create_dir("ebiu_sdram", top);
843# ifdef __ADSPBF561__
844 D32(EBIU_SDBCTL);
845# else
846 D16(EBIU_SDBCTL);
847# endif
848 D32(EBIU_SDGCTL);
849 D16(EBIU_SDRRC);
850 D16(EBIU_SDSTAT);
851#endif
852
853#ifdef EBIU_DDRACCT
854 parent = debugfs_create_dir("ebiu_ddr", top);
855 D32(EBIU_DDRACCT);
856 D32(EBIU_DDRARCT);
857 D32(EBIU_DDRBRC0);
858 D32(EBIU_DDRBRC1);
859 D32(EBIU_DDRBRC2);
860 D32(EBIU_DDRBRC3);
861 D32(EBIU_DDRBRC4);
862 D32(EBIU_DDRBRC5);
863 D32(EBIU_DDRBRC6);
864 D32(EBIU_DDRBRC7);
865 D32(EBIU_DDRBWC0);
866 D32(EBIU_DDRBWC1);
867 D32(EBIU_DDRBWC2);
868 D32(EBIU_DDRBWC3);
869 D32(EBIU_DDRBWC4);
870 D32(EBIU_DDRBWC5);
871 D32(EBIU_DDRBWC6);
872 D32(EBIU_DDRBWC7);
873 D32(EBIU_DDRCTL0);
874 D32(EBIU_DDRCTL1);
875 D32(EBIU_DDRCTL2);
876 D32(EBIU_DDRCTL3);
877 D32(EBIU_DDRGC0);
878 D32(EBIU_DDRGC1);
879 D32(EBIU_DDRGC2);
880 D32(EBIU_DDRGC3);
881 D32(EBIU_DDRMCCL);
882 D32(EBIU_DDRMCEN);
883 D32(EBIU_DDRQUE);
884 D32(EBIU_DDRTACT);
885 D32(EBIU_ERRADD);
886 D16(EBIU_ERRMST);
887 D16(EBIU_RSTCTL);
888#endif
889
890#ifdef EMAC_ADDRHI
891 parent = debugfs_create_dir("emac", top);
892 D32(EMAC_ADDRHI);
893 D32(EMAC_ADDRLO);
894 D32(EMAC_FLC);
895 D32(EMAC_HASHHI);
896 D32(EMAC_HASHLO);
897 D32(EMAC_MMC_CTL);
898 D32(EMAC_MMC_RIRQE);
899 D32(EMAC_MMC_RIRQS);
900 D32(EMAC_MMC_TIRQE);
901 D32(EMAC_MMC_TIRQS);
902 D32(EMAC_OPMODE);
903 D32(EMAC_RXC_ALIGN);
904 D32(EMAC_RXC_ALLFRM);
905 D32(EMAC_RXC_ALLOCT);
906 D32(EMAC_RXC_BROAD);
907 D32(EMAC_RXC_DMAOVF);
908 D32(EMAC_RXC_EQ64);
909 D32(EMAC_RXC_FCS);
910 D32(EMAC_RXC_GE1024);
911 D32(EMAC_RXC_LNERRI);
912 D32(EMAC_RXC_LNERRO);
913 D32(EMAC_RXC_LONG);
914 D32(EMAC_RXC_LT1024);
915 D32(EMAC_RXC_LT128);
916 D32(EMAC_RXC_LT256);
917 D32(EMAC_RXC_LT512);
918 D32(EMAC_RXC_MACCTL);
919 D32(EMAC_RXC_MULTI);
920 D32(EMAC_RXC_OCTET);
921 D32(EMAC_RXC_OK);
922 D32(EMAC_RXC_OPCODE);
923 D32(EMAC_RXC_PAUSE);
924 D32(EMAC_RXC_SHORT);
925 D32(EMAC_RXC_TYPED);
926 D32(EMAC_RXC_UNICST);
927 D32(EMAC_RX_IRQE);
928 D32(EMAC_RX_STAT);
929 D32(EMAC_RX_STKY);
930 D32(EMAC_STAADD);
931 D32(EMAC_STADAT);
932 D32(EMAC_SYSCTL);
933 D32(EMAC_SYSTAT);
934 D32(EMAC_TXC_1COL);
935 D32(EMAC_TXC_ABORT);
936 D32(EMAC_TXC_ALLFRM);
937 D32(EMAC_TXC_ALLOCT);
938 D32(EMAC_TXC_BROAD);
939 D32(EMAC_TXC_CRSERR);
940 D32(EMAC_TXC_DEFER);
941 D32(EMAC_TXC_DMAUND);
942 D32(EMAC_TXC_EQ64);
943 D32(EMAC_TXC_GE1024);
944 D32(EMAC_TXC_GT1COL);
945 D32(EMAC_TXC_LATECL);
946 D32(EMAC_TXC_LT1024);
947 D32(EMAC_TXC_LT128);
948 D32(EMAC_TXC_LT256);
949 D32(EMAC_TXC_LT512);
950 D32(EMAC_TXC_MACCTL);
951 D32(EMAC_TXC_MULTI);
952 D32(EMAC_TXC_OCTET);
953 D32(EMAC_TXC_OK);
954 D32(EMAC_TXC_UNICST);
955 D32(EMAC_TXC_XS_COL);
956 D32(EMAC_TXC_XS_DFR);
957 D32(EMAC_TX_IRQE);
958 D32(EMAC_TX_STAT);
959 D32(EMAC_TX_STKY);
960 D32(EMAC_VLAN1);
961 D32(EMAC_VLAN2);
962 D32(EMAC_WKUP_CTL);
963 D32(EMAC_WKUP_FFCMD);
964 D32(EMAC_WKUP_FFCRC0);
965 D32(EMAC_WKUP_FFCRC1);
966 D32(EMAC_WKUP_FFMSK0);
967 D32(EMAC_WKUP_FFMSK1);
968 D32(EMAC_WKUP_FFMSK2);
969 D32(EMAC_WKUP_FFMSK3);
970 D32(EMAC_WKUP_FFOFF);
971# ifdef EMAC_PTP_ACCR
972 D32(EMAC_PTP_ACCR);
973 D32(EMAC_PTP_ADDEND);
974 D32(EMAC_PTP_ALARMHI);
975 D32(EMAC_PTP_ALARMLO);
976 D16(EMAC_PTP_CTL);
977 D32(EMAC_PTP_FOFF);
978 D32(EMAC_PTP_FV1);
979 D32(EMAC_PTP_FV2);
980 D32(EMAC_PTP_FV3);
981 D16(EMAC_PTP_ID_OFF);
982 D32(EMAC_PTP_ID_SNAP);
983 D16(EMAC_PTP_IE);
984 D16(EMAC_PTP_ISTAT);
985 D32(EMAC_PTP_OFFSET);
986 D32(EMAC_PTP_PPS_PERIOD);
987 D32(EMAC_PTP_PPS_STARTHI);
988 D32(EMAC_PTP_PPS_STARTLO);
989 D32(EMAC_PTP_RXSNAPHI);
990 D32(EMAC_PTP_RXSNAPLO);
991 D32(EMAC_PTP_TIMEHI);
992 D32(EMAC_PTP_TIMELO);
993 D32(EMAC_PTP_TXSNAPHI);
994 D32(EMAC_PTP_TXSNAPLO);
995# endif
996#endif
997
998#if defined(EPPI0_STATUS) || defined(EPPI1_STATUS) || defined(EPPI2_STATUS)
999 parent = debugfs_create_dir("eppi", top);
1000# ifdef EPPI0_STATUS
1001 EPPI(0);
1002# endif
1003# ifdef EPPI1_STATUS
1004 EPPI(1);
1005# endif
1006# ifdef EPPI2_STATUS
1007 EPPI(2);
1008# endif
1009#endif
1010
1011 parent = debugfs_create_dir("gptimer", top);
1012#ifdef TIMER_DISABLE
1013 D16(TIMER_DISABLE);
1014 D16(TIMER_ENABLE);
1015 D32(TIMER_STATUS);
1016#endif
1017#ifdef TIMER_DISABLE0
1018 D16(TIMER_DISABLE0);
1019 D16(TIMER_ENABLE0);
1020 D32(TIMER_STATUS0);
1021#endif
1022#ifdef TIMER_DISABLE1
1023 D16(TIMER_DISABLE1);
1024 D16(TIMER_ENABLE1);
1025 D32(TIMER_STATUS1);
1026#endif
1027 /* XXX: Should convert BF561 MMR names */
1028#ifdef TMRS4_DISABLE
1029 D16(TMRS4_DISABLE);
1030 D16(TMRS4_ENABLE);
1031 D32(TMRS4_STATUS);
1032 D16(TMRS8_DISABLE);
1033 D16(TMRS8_ENABLE);
1034 D32(TMRS8_STATUS);
1035#endif
1036 GPTIMER(0);
1037 GPTIMER(1);
1038 GPTIMER(2);
1039#ifdef TIMER3_CONFIG
1040 GPTIMER(3);
1041 GPTIMER(4);
1042 GPTIMER(5);
1043 GPTIMER(6);
1044 GPTIMER(7);
1045#endif
1046#ifdef TIMER8_CONFIG
1047 GPTIMER(8);
1048 GPTIMER(9);
1049 GPTIMER(10);
1050#endif
1051#ifdef TIMER11_CONFIG
1052 GPTIMER(11);
1053#endif
1054
1055#ifdef HMDMA0_CONTROL
1056 parent = debugfs_create_dir("hmdma", top);
1057 HMDMA(0);
1058 HMDMA(1);
1059#endif
1060
1061#ifdef HOST_CONTROL
1062 parent = debugfs_create_dir("hostdp", top);
1063 D16(HOST_CONTROL);
1064 D16(HOST_STATUS);
1065 D16(HOST_TIMEOUT);
1066#endif
1067
1068#ifdef IMDMA_S0_CONFIG
1069 parent = debugfs_create_dir("imdma", top);
1070 IMDMA(0);
1071 IMDMA(1);
1072#endif
1073
1074#ifdef KPAD_CTL
1075 parent = debugfs_create_dir("keypad", top);
1076 D16(KPAD_CTL);
1077 D16(KPAD_PRESCALE);
1078 D16(KPAD_MSEL);
1079 D16(KPAD_ROWCOL);
1080 D16(KPAD_STAT);
1081 D16(KPAD_SOFTEVAL);
1082#endif
1083
1084 parent = debugfs_create_dir("mdma", top);
1085 MDMA(0);
1086 MDMA(1);
1087#ifdef MDMA_D2_CONFIG
1088 MDMA(2);
1089 MDMA(3);
1090#endif
1091
1092#ifdef MXVR_CONFIG
1093 parent = debugfs_create_dir("mxvr", top);
1094 D16(MXVR_CONFIG);
1095# ifdef MXVR_PLL_CTL_0
1096 D32(MXVR_PLL_CTL_0);
1097# endif
1098 D32(MXVR_STATE_0);
1099 D32(MXVR_STATE_1);
1100 D32(MXVR_INT_STAT_0);
1101 D32(MXVR_INT_STAT_1);
1102 D32(MXVR_INT_EN_0);
1103 D32(MXVR_INT_EN_1);
1104 D16(MXVR_POSITION);
1105 D16(MXVR_MAX_POSITION);
1106 D16(MXVR_DELAY);
1107 D16(MXVR_MAX_DELAY);
1108 D32(MXVR_LADDR);
1109 D16(MXVR_GADDR);
1110 D32(MXVR_AADDR);
1111 D32(MXVR_ALLOC_0);
1112 D32(MXVR_ALLOC_1);
1113 D32(MXVR_ALLOC_2);
1114 D32(MXVR_ALLOC_3);
1115 D32(MXVR_ALLOC_4);
1116 D32(MXVR_ALLOC_5);
1117 D32(MXVR_ALLOC_6);
1118 D32(MXVR_ALLOC_7);
1119 D32(MXVR_ALLOC_8);
1120 D32(MXVR_ALLOC_9);
1121 D32(MXVR_ALLOC_10);
1122 D32(MXVR_ALLOC_11);
1123 D32(MXVR_ALLOC_12);
1124 D32(MXVR_ALLOC_13);
1125 D32(MXVR_ALLOC_14);
1126 D32(MXVR_SYNC_LCHAN_0);
1127 D32(MXVR_SYNC_LCHAN_1);
1128 D32(MXVR_SYNC_LCHAN_2);
1129 D32(MXVR_SYNC_LCHAN_3);
1130 D32(MXVR_SYNC_LCHAN_4);
1131 D32(MXVR_SYNC_LCHAN_5);
1132 D32(MXVR_SYNC_LCHAN_6);
1133 D32(MXVR_SYNC_LCHAN_7);
1134 D32(MXVR_DMA0_CONFIG);
1135 D32(MXVR_DMA0_START_ADDR);
1136 D16(MXVR_DMA0_COUNT);
1137 D32(MXVR_DMA0_CURR_ADDR);
1138 D16(MXVR_DMA0_CURR_COUNT);
1139 D32(MXVR_DMA1_CONFIG);
1140 D32(MXVR_DMA1_START_ADDR);
1141 D16(MXVR_DMA1_COUNT);
1142 D32(MXVR_DMA1_CURR_ADDR);
1143 D16(MXVR_DMA1_CURR_COUNT);
1144 D32(MXVR_DMA2_CONFIG);
1145 D32(MXVR_DMA2_START_ADDR);
1146 D16(MXVR_DMA2_COUNT);
1147 D32(MXVR_DMA2_CURR_ADDR);
1148 D16(MXVR_DMA2_CURR_COUNT);
1149 D32(MXVR_DMA3_CONFIG);
1150 D32(MXVR_DMA3_START_ADDR);
1151 D16(MXVR_DMA3_COUNT);
1152 D32(MXVR_DMA3_CURR_ADDR);
1153 D16(MXVR_DMA3_CURR_COUNT);
1154 D32(MXVR_DMA4_CONFIG);
1155 D32(MXVR_DMA4_START_ADDR);
1156 D16(MXVR_DMA4_COUNT);
1157 D32(MXVR_DMA4_CURR_ADDR);
1158 D16(MXVR_DMA4_CURR_COUNT);
1159 D32(MXVR_DMA5_CONFIG);
1160 D32(MXVR_DMA5_START_ADDR);
1161 D16(MXVR_DMA5_COUNT);
1162 D32(MXVR_DMA5_CURR_ADDR);
1163 D16(MXVR_DMA5_CURR_COUNT);
1164 D32(MXVR_DMA6_CONFIG);
1165 D32(MXVR_DMA6_START_ADDR);
1166 D16(MXVR_DMA6_COUNT);
1167 D32(MXVR_DMA6_CURR_ADDR);
1168 D16(MXVR_DMA6_CURR_COUNT);
1169 D32(MXVR_DMA7_CONFIG);
1170 D32(MXVR_DMA7_START_ADDR);
1171 D16(MXVR_DMA7_COUNT);
1172 D32(MXVR_DMA7_CURR_ADDR);
1173 D16(MXVR_DMA7_CURR_COUNT);
1174 D16(MXVR_AP_CTL);
1175 D32(MXVR_APRB_START_ADDR);
1176 D32(MXVR_APRB_CURR_ADDR);
1177 D32(MXVR_APTB_START_ADDR);
1178 D32(MXVR_APTB_CURR_ADDR);
1179 D32(MXVR_CM_CTL);
1180 D32(MXVR_CMRB_START_ADDR);
1181 D32(MXVR_CMRB_CURR_ADDR);
1182 D32(MXVR_CMTB_START_ADDR);
1183 D32(MXVR_CMTB_CURR_ADDR);
1184 D32(MXVR_RRDB_START_ADDR);
1185 D32(MXVR_RRDB_CURR_ADDR);
1186 D32(MXVR_PAT_DATA_0);
1187 D32(MXVR_PAT_EN_0);
1188 D32(MXVR_PAT_DATA_1);
1189 D32(MXVR_PAT_EN_1);
1190 D16(MXVR_FRAME_CNT_0);
1191 D16(MXVR_FRAME_CNT_1);
1192 D32(MXVR_ROUTING_0);
1193 D32(MXVR_ROUTING_1);
1194 D32(MXVR_ROUTING_2);
1195 D32(MXVR_ROUTING_3);
1196 D32(MXVR_ROUTING_4);
1197 D32(MXVR_ROUTING_5);
1198 D32(MXVR_ROUTING_6);
1199 D32(MXVR_ROUTING_7);
1200 D32(MXVR_ROUTING_8);
1201 D32(MXVR_ROUTING_9);
1202 D32(MXVR_ROUTING_10);
1203 D32(MXVR_ROUTING_11);
1204 D32(MXVR_ROUTING_12);
1205 D32(MXVR_ROUTING_13);
1206 D32(MXVR_ROUTING_14);
1207# ifdef MXVR_PLL_CTL_1
1208 D32(MXVR_PLL_CTL_1);
1209# endif
1210 D16(MXVR_BLOCK_CNT);
1211# ifdef MXVR_CLK_CTL
1212 D32(MXVR_CLK_CTL);
1213# endif
1214# ifdef MXVR_CDRPLL_CTL
1215 D32(MXVR_CDRPLL_CTL);
1216# endif
1217# ifdef MXVR_FMPLL_CTL
1218 D32(MXVR_FMPLL_CTL);
1219# endif
1220# ifdef MXVR_PIN_CTL
1221 D16(MXVR_PIN_CTL);
1222# endif
1223# ifdef MXVR_SCLK_CNT
1224 D16(MXVR_SCLK_CNT);
1225# endif
1226#endif
1227
1228#ifdef NFC_ADDR
1229 parent = debugfs_create_dir("nfc", top);
1230 D_WO(NFC_ADDR, 16);
1231 D_WO(NFC_CMD, 16);
1232 D_RO(NFC_COUNT, 16);
1233 D16(NFC_CTL);
1234 D_WO(NFC_DATA_RD, 16);
1235 D_WO(NFC_DATA_WR, 16);
1236 D_RO(NFC_ECC0, 16);
1237 D_RO(NFC_ECC1, 16);
1238 D_RO(NFC_ECC2, 16);
1239 D_RO(NFC_ECC3, 16);
1240 D16(NFC_IRQMASK);
1241 D16(NFC_IRQSTAT);
1242 D_WO(NFC_PGCTL, 16);
1243 D_RO(NFC_READ, 16);
1244 D16(NFC_RST);
1245 D_RO(NFC_STAT, 16);
1246#endif
1247
1248#ifdef OTP_CONTROL
1249 parent = debugfs_create_dir("otp", top);
1250 D16(OTP_CONTROL);
1251 D16(OTP_BEN);
1252 D16(OTP_STATUS);
1253 D32(OTP_TIMING);
1254 D32(OTP_DATA0);
1255 D32(OTP_DATA1);
1256 D32(OTP_DATA2);
1257 D32(OTP_DATA3);
1258#endif
1259
1260#ifdef PIXC_CTL
1261 parent = debugfs_create_dir("pixc", top);
1262 D16(PIXC_CTL);
1263 D16(PIXC_PPL);
1264 D16(PIXC_LPF);
1265 D16(PIXC_AHSTART);
1266 D16(PIXC_AHEND);
1267 D16(PIXC_AVSTART);
1268 D16(PIXC_AVEND);
1269 D16(PIXC_ATRANSP);
1270 D16(PIXC_BHSTART);
1271 D16(PIXC_BHEND);
1272 D16(PIXC_BVSTART);
1273 D16(PIXC_BVEND);
1274 D16(PIXC_BTRANSP);
1275 D16(PIXC_INTRSTAT);
1276 D32(PIXC_RYCON);
1277 D32(PIXC_GUCON);
1278 D32(PIXC_BVCON);
1279 D32(PIXC_CCBIAS);
1280 D32(PIXC_TC);
1281#endif
1282
1283 parent = debugfs_create_dir("pll", top);
1284 D16(PLL_CTL);
1285 D16(PLL_DIV);
1286 D16(PLL_LOCKCNT);
1287 D16(PLL_STAT);
1288 D16(VR_CTL);
1289 D32(CHIPID); /* it's part of this hardware block */
1290
1291#if defined(PPI_STATUS) || defined(PPI0_STATUS) || defined(PPI1_STATUS)
1292 parent = debugfs_create_dir("ppi", top);
1293# ifdef PPI_STATUS
1294 bfin_debug_mmrs_ppi(parent, PPI_STATUS, -1);
1295# endif
1296# ifdef PPI0_STATUS
1297 PPI(0);
1298# endif
1299# ifdef PPI1_STATUS
1300 PPI(1);
1301# endif
1302#endif
1303
1304#ifdef PWM_CTRL
1305 parent = debugfs_create_dir("pwm", top);
1306 D16(PWM_CTRL);
1307 D16(PWM_STAT);
1308 D16(PWM_TM);
1309 D16(PWM_DT);
1310 D16(PWM_GATE);
1311 D16(PWM_CHA);
1312 D16(PWM_CHB);
1313 D16(PWM_CHC);
1314 D16(PWM_SEG);
1315 D16(PWM_SYNCWT);
1316 D16(PWM_CHAL);
1317 D16(PWM_CHBL);
1318 D16(PWM_CHCL);
1319 D16(PWM_LSI);
1320 D16(PWM_STAT2);
1321#endif
1322
1323#ifdef RSI_CONFIG
1324 parent = debugfs_create_dir("rsi", top);
1325 D32(RSI_ARGUMENT);
1326 D16(RSI_CEATA_CONTROL);
1327 D16(RSI_CLK_CONTROL);
1328 D16(RSI_COMMAND);
1329 D16(RSI_CONFIG);
1330 D16(RSI_DATA_CNT);
1331 D16(RSI_DATA_CONTROL);
1332 D16(RSI_DATA_LGTH);
1333 D32(RSI_DATA_TIMER);
1334 D16(RSI_EMASK);
1335 D16(RSI_ESTAT);
1336 D32(RSI_FIFO);
1337 D16(RSI_FIFO_CNT);
1338 D32(RSI_MASK0);
1339 D32(RSI_MASK1);
1340 D16(RSI_PID0);
1341 D16(RSI_PID1);
1342 D16(RSI_PID2);
1343 D16(RSI_PID3);
1344 D16(RSI_PWR_CONTROL);
1345 D16(RSI_RD_WAIT_EN);
1346 D32(RSI_RESPONSE0);
1347 D32(RSI_RESPONSE1);
1348 D32(RSI_RESPONSE2);
1349 D32(RSI_RESPONSE3);
1350 D16(RSI_RESP_CMD);
1351 D32(RSI_STATUS);
1352 D_WO(RSI_STATUSCL, 16);
1353#endif
1354
1355#ifdef RTC_ALARM
1356 parent = debugfs_create_dir("rtc", top);
1357 D32(RTC_ALARM);
1358 D16(RTC_ICTL);
1359 D16(RTC_ISTAT);
1360 D16(RTC_PREN);
1361 D32(RTC_STAT);
1362 D16(RTC_SWCNT);
1363#endif
1364
1365#ifdef SDH_CFG
1366 parent = debugfs_create_dir("sdh", top);
1367 D32(SDH_ARGUMENT);
1368 D16(SDH_CFG);
1369 D16(SDH_CLK_CTL);
1370 D16(SDH_COMMAND);
1371 D_RO(SDH_DATA_CNT, 16);
1372 D16(SDH_DATA_CTL);
1373 D16(SDH_DATA_LGTH);
1374 D32(SDH_DATA_TIMER);
1375 D16(SDH_E_MASK);
1376 D16(SDH_E_STATUS);
1377 D32(SDH_FIFO);
1378 D_RO(SDH_FIFO_CNT, 16);
1379 D32(SDH_MASK0);
1380 D32(SDH_MASK1);
1381 D_RO(SDH_PID0, 16);
1382 D_RO(SDH_PID1, 16);
1383 D_RO(SDH_PID2, 16);
1384 D_RO(SDH_PID3, 16);
1385 D_RO(SDH_PID4, 16);
1386 D_RO(SDH_PID5, 16);
1387 D_RO(SDH_PID6, 16);
1388 D_RO(SDH_PID7, 16);
1389 D16(SDH_PWR_CTL);
1390 D16(SDH_RD_WAIT_EN);
1391 D_RO(SDH_RESPONSE0, 32);
1392 D_RO(SDH_RESPONSE1, 32);
1393 D_RO(SDH_RESPONSE2, 32);
1394 D_RO(SDH_RESPONSE3, 32);
1395 D_RO(SDH_RESP_CMD, 16);
1396 D_RO(SDH_STATUS, 32);
1397 D_WO(SDH_STATUS_CLR, 16);
1398#endif
1399
1400#ifdef SECURE_CONTROL
1401 parent = debugfs_create_dir("security", top);
1402 D16(SECURE_CONTROL);
1403 D16(SECURE_STATUS);
1404 D32(SECURE_SYSSWT);
1405#endif
1406
1407 parent = debugfs_create_dir("sic", top);
1408 D16(SWRST);
1409 D16(SYSCR);
1410 D16(SIC_RVECT);
1411 D32(SIC_IAR0);
1412 D32(SIC_IAR1);
1413 D32(SIC_IAR2);
1414#ifdef SIC_IAR3
1415 D32(SIC_IAR3);
1416#endif
1417#ifdef SIC_IAR4
1418 D32(SIC_IAR4);
1419 D32(SIC_IAR5);
1420 D32(SIC_IAR6);
1421#endif
1422#ifdef SIC_IAR7
1423 D32(SIC_IAR7);
1424#endif
1425#ifdef SIC_IAR8
1426 D32(SIC_IAR8);
1427 D32(SIC_IAR9);
1428 D32(SIC_IAR10);
1429 D32(SIC_IAR11);
1430#endif
1431#ifdef SIC_IMASK
1432 D32(SIC_IMASK);
1433 D32(SIC_ISR);
1434 D32(SIC_IWR);
1435#endif
1436#ifdef SIC_IMASK0
1437 D32(SIC_IMASK0);
1438 D32(SIC_IMASK1);
1439 D32(SIC_ISR0);
1440 D32(SIC_ISR1);
1441 D32(SIC_IWR0);
1442 D32(SIC_IWR1);
1443#endif
1444#ifdef SIC_IMASK2
1445 D32(SIC_IMASK2);
1446 D32(SIC_ISR2);
1447 D32(SIC_IWR2);
1448#endif
1449#ifdef SICB_RVECT
1450 D16(SICB_SWRST);
1451 D16(SICB_SYSCR);
1452 D16(SICB_RVECT);
1453 D32(SICB_IAR0);
1454 D32(SICB_IAR1);
1455 D32(SICB_IAR2);
1456 D32(SICB_IAR3);
1457 D32(SICB_IAR4);
1458 D32(SICB_IAR5);
1459 D32(SICB_IAR6);
1460 D32(SICB_IAR7);
1461 D32(SICB_IMASK0);
1462 D32(SICB_IMASK1);
1463 D32(SICB_ISR0);
1464 D32(SICB_ISR1);
1465 D32(SICB_IWR0);
1466 D32(SICB_IWR1);
1467#endif
1468
1469 parent = debugfs_create_dir("spi", top);
1470#ifdef SPI0_REGBASE
1471 SPI(0);
1472#endif
1473#ifdef SPI1_REGBASE
1474 SPI(1);
1475#endif
1476#ifdef SPI2_REGBASE
1477 SPI(2);
1478#endif
1479
1480 parent = debugfs_create_dir("sport", top);
1481#ifdef SPORT0_STAT
1482 SPORT(0);
1483#endif
1484#ifdef SPORT1_STAT
1485 SPORT(1);
1486#endif
1487#ifdef SPORT2_STAT
1488 SPORT(2);
1489#endif
1490#ifdef SPORT3_STAT
1491 SPORT(3);
1492#endif
1493
1494#if defined(TWI_CLKDIV) || defined(TWI0_CLKDIV) || defined(TWI1_CLKDIV)
1495 parent = debugfs_create_dir("twi", top);
1496# ifdef TWI_CLKDIV
1497 bfin_debug_mmrs_twi(parent, TWI_CLKDIV, -1);
1498# endif
1499# ifdef TWI0_CLKDIV
1500 TWI(0);
1501# endif
1502# ifdef TWI1_CLKDIV
1503 TWI(1);
1504# endif
1505#endif
1506
1507 parent = debugfs_create_dir("uart", top);
1508#ifdef BFIN_UART_DLL
1509 bfin_debug_mmrs_uart(parent, BFIN_UART_DLL, -1);
1510#endif
1511#ifdef UART0_DLL
1512 UART(0);
1513#endif
1514#ifdef UART1_DLL
1515 UART(1);
1516#endif
1517#ifdef UART2_DLL
1518 UART(2);
1519#endif
1520#ifdef UART3_DLL
1521 UART(3);
1522#endif
1523
1524#ifdef USB_FADDR
1525 parent = debugfs_create_dir("usb", top);
1526 D16(USB_FADDR);
1527 D16(USB_POWER);
1528 D16(USB_INTRTX);
1529 D16(USB_INTRRX);
1530 D16(USB_INTRTXE);
1531 D16(USB_INTRRXE);
1532 D16(USB_INTRUSB);
1533 D16(USB_INTRUSBE);
1534 D16(USB_FRAME);
1535 D16(USB_INDEX);
1536 D16(USB_TESTMODE);
1537 D16(USB_GLOBINTR);
1538 D16(USB_GLOBAL_CTL);
1539 D16(USB_TX_MAX_PACKET);
1540 D16(USB_CSR0);
1541 D16(USB_TXCSR);
1542 D16(USB_RX_MAX_PACKET);
1543 D16(USB_RXCSR);
1544 D16(USB_COUNT0);
1545 D16(USB_RXCOUNT);
1546 D16(USB_TXTYPE);
1547 D16(USB_NAKLIMIT0);
1548 D16(USB_TXINTERVAL);
1549 D16(USB_RXTYPE);
1550 D16(USB_RXINTERVAL);
1551 D16(USB_TXCOUNT);
1552 D16(USB_EP0_FIFO);
1553 D16(USB_EP1_FIFO);
1554 D16(USB_EP2_FIFO);
1555 D16(USB_EP3_FIFO);
1556 D16(USB_EP4_FIFO);
1557 D16(USB_EP5_FIFO);
1558 D16(USB_EP6_FIFO);
1559 D16(USB_EP7_FIFO);
1560 D16(USB_OTG_DEV_CTL);
1561 D16(USB_OTG_VBUS_IRQ);
1562 D16(USB_OTG_VBUS_MASK);
1563 D16(USB_LINKINFO);
1564 D16(USB_VPLEN);
1565 D16(USB_HS_EOF1);
1566 D16(USB_FS_EOF1);
1567 D16(USB_LS_EOF1);
1568 D16(USB_APHY_CNTRL);
1569 D16(USB_APHY_CALIB);
1570 D16(USB_APHY_CNTRL2);
1571 D16(USB_PHY_TEST);
1572 D16(USB_PLLOSC_CTRL);
1573 D16(USB_SRP_CLKDIV);
1574 D16(USB_EP_NI0_TXMAXP);
1575 D16(USB_EP_NI0_TXCSR);
1576 D16(USB_EP_NI0_RXMAXP);
1577 D16(USB_EP_NI0_RXCSR);
1578 D16(USB_EP_NI0_RXCOUNT);
1579 D16(USB_EP_NI0_TXTYPE);
1580 D16(USB_EP_NI0_TXINTERVAL);
1581 D16(USB_EP_NI0_RXTYPE);
1582 D16(USB_EP_NI0_RXINTERVAL);
1583 D16(USB_EP_NI0_TXCOUNT);
1584 D16(USB_EP_NI1_TXMAXP);
1585 D16(USB_EP_NI1_TXCSR);
1586 D16(USB_EP_NI1_RXMAXP);
1587 D16(USB_EP_NI1_RXCSR);
1588 D16(USB_EP_NI1_RXCOUNT);
1589 D16(USB_EP_NI1_TXTYPE);
1590 D16(USB_EP_NI1_TXINTERVAL);
1591 D16(USB_EP_NI1_RXTYPE);
1592 D16(USB_EP_NI1_RXINTERVAL);
1593 D16(USB_EP_NI1_TXCOUNT);
1594 D16(USB_EP_NI2_TXMAXP);
1595 D16(USB_EP_NI2_TXCSR);
1596 D16(USB_EP_NI2_RXMAXP);
1597 D16(USB_EP_NI2_RXCSR);
1598 D16(USB_EP_NI2_RXCOUNT);
1599 D16(USB_EP_NI2_TXTYPE);
1600 D16(USB_EP_NI2_TXINTERVAL);
1601 D16(USB_EP_NI2_RXTYPE);
1602 D16(USB_EP_NI2_RXINTERVAL);
1603 D16(USB_EP_NI2_TXCOUNT);
1604 D16(USB_EP_NI3_TXMAXP);
1605 D16(USB_EP_NI3_TXCSR);
1606 D16(USB_EP_NI3_RXMAXP);
1607 D16(USB_EP_NI3_RXCSR);
1608 D16(USB_EP_NI3_RXCOUNT);
1609 D16(USB_EP_NI3_TXTYPE);
1610 D16(USB_EP_NI3_TXINTERVAL);
1611 D16(USB_EP_NI3_RXTYPE);
1612 D16(USB_EP_NI3_RXINTERVAL);
1613 D16(USB_EP_NI3_TXCOUNT);
1614 D16(USB_EP_NI4_TXMAXP);
1615 D16(USB_EP_NI4_TXCSR);
1616 D16(USB_EP_NI4_RXMAXP);
1617 D16(USB_EP_NI4_RXCSR);
1618 D16(USB_EP_NI4_RXCOUNT);
1619 D16(USB_EP_NI4_TXTYPE);
1620 D16(USB_EP_NI4_TXINTERVAL);
1621 D16(USB_EP_NI4_RXTYPE);
1622 D16(USB_EP_NI4_RXINTERVAL);
1623 D16(USB_EP_NI4_TXCOUNT);
1624 D16(USB_EP_NI5_TXMAXP);
1625 D16(USB_EP_NI5_TXCSR);
1626 D16(USB_EP_NI5_RXMAXP);
1627 D16(USB_EP_NI5_RXCSR);
1628 D16(USB_EP_NI5_RXCOUNT);
1629 D16(USB_EP_NI5_TXTYPE);
1630 D16(USB_EP_NI5_TXINTERVAL);
1631 D16(USB_EP_NI5_RXTYPE);
1632 D16(USB_EP_NI5_RXINTERVAL);
1633 D16(USB_EP_NI5_TXCOUNT);
1634 D16(USB_EP_NI6_TXMAXP);
1635 D16(USB_EP_NI6_TXCSR);
1636 D16(USB_EP_NI6_RXMAXP);
1637 D16(USB_EP_NI6_RXCSR);
1638 D16(USB_EP_NI6_RXCOUNT);
1639 D16(USB_EP_NI6_TXTYPE);
1640 D16(USB_EP_NI6_TXINTERVAL);
1641 D16(USB_EP_NI6_RXTYPE);
1642 D16(USB_EP_NI6_RXINTERVAL);
1643 D16(USB_EP_NI6_TXCOUNT);
1644 D16(USB_EP_NI7_TXMAXP);
1645 D16(USB_EP_NI7_TXCSR);
1646 D16(USB_EP_NI7_RXMAXP);
1647 D16(USB_EP_NI7_RXCSR);
1648 D16(USB_EP_NI7_RXCOUNT);
1649 D16(USB_EP_NI7_TXTYPE);
1650 D16(USB_EP_NI7_TXINTERVAL);
1651 D16(USB_EP_NI7_RXTYPE);
1652 D16(USB_EP_NI7_RXINTERVAL);
1653 D16(USB_EP_NI7_TXCOUNT);
1654 D16(USB_DMA_INTERRUPT);
1655 D16(USB_DMA0CONTROL);
1656 D16(USB_DMA0ADDRLOW);
1657 D16(USB_DMA0ADDRHIGH);
1658 D16(USB_DMA0COUNTLOW);
1659 D16(USB_DMA0COUNTHIGH);
1660 D16(USB_DMA1CONTROL);
1661 D16(USB_DMA1ADDRLOW);
1662 D16(USB_DMA1ADDRHIGH);
1663 D16(USB_DMA1COUNTLOW);
1664 D16(USB_DMA1COUNTHIGH);
1665 D16(USB_DMA2CONTROL);
1666 D16(USB_DMA2ADDRLOW);
1667 D16(USB_DMA2ADDRHIGH);
1668 D16(USB_DMA2COUNTLOW);
1669 D16(USB_DMA2COUNTHIGH);
1670 D16(USB_DMA3CONTROL);
1671 D16(USB_DMA3ADDRLOW);
1672 D16(USB_DMA3ADDRHIGH);
1673 D16(USB_DMA3COUNTLOW);
1674 D16(USB_DMA3COUNTHIGH);
1675 D16(USB_DMA4CONTROL);
1676 D16(USB_DMA4ADDRLOW);
1677 D16(USB_DMA4ADDRHIGH);
1678 D16(USB_DMA4COUNTLOW);
1679 D16(USB_DMA4COUNTHIGH);
1680 D16(USB_DMA5CONTROL);
1681 D16(USB_DMA5ADDRLOW);
1682 D16(USB_DMA5ADDRHIGH);
1683 D16(USB_DMA5COUNTLOW);
1684 D16(USB_DMA5COUNTHIGH);
1685 D16(USB_DMA6CONTROL);
1686 D16(USB_DMA6ADDRLOW);
1687 D16(USB_DMA6ADDRHIGH);
1688 D16(USB_DMA6COUNTLOW);
1689 D16(USB_DMA6COUNTHIGH);
1690 D16(USB_DMA7CONTROL);
1691 D16(USB_DMA7ADDRLOW);
1692 D16(USB_DMA7ADDRHIGH);
1693 D16(USB_DMA7COUNTLOW);
1694 D16(USB_DMA7COUNTHIGH);
1695#endif
1696
1697#ifdef WDOG_CNT
1698 parent = debugfs_create_dir("watchdog", top);
1699 D32(WDOG_CNT);
1700 D16(WDOG_CTL);
1701 D32(WDOG_STAT);
1702#endif
1703#ifdef WDOGA_CNT
1704 parent = debugfs_create_dir("watchdog", top);
1705 D32(WDOGA_CNT);
1706 D16(WDOGA_CTL);
1707 D32(WDOGA_STAT);
1708 D32(WDOGB_CNT);
1709 D16(WDOGB_CTL);
1710 D32(WDOGB_STAT);
1711#endif
1712
1713 /* BF533 glue */
1714#ifdef FIO_FLAG_D
1715#define PORTFIO FIO_FLAG_D
1716#endif
1717 /* BF561 glue */
1718#ifdef FIO0_FLAG_D
1719#define PORTFIO FIO0_FLAG_D
1720#endif
1721#ifdef FIO1_FLAG_D
1722#define PORTGIO FIO1_FLAG_D
1723#endif
1724#ifdef FIO2_FLAG_D
1725#define PORTHIO FIO2_FLAG_D
1726#endif
1727 parent = debugfs_create_dir("port", top);
1728#ifdef PORTFIO
1729 PORT(PORTFIO, 'F');
1730#endif
1731#ifdef PORTGIO
1732 PORT(PORTGIO, 'G');
1733#endif
1734#ifdef PORTHIO
1735 PORT(PORTHIO, 'H');
1736#endif
1737
1738#ifdef __ADSPBF51x__
1739 D16(PORTF_FER);
1740 D16(PORTF_DRIVE);
1741 D16(PORTF_HYSTERESIS);
1742 D16(PORTF_MUX);
1743
1744 D16(PORTG_FER);
1745 D16(PORTG_DRIVE);
1746 D16(PORTG_HYSTERESIS);
1747 D16(PORTG_MUX);
1748
1749 D16(PORTH_FER);
1750 D16(PORTH_DRIVE);
1751 D16(PORTH_HYSTERESIS);
1752 D16(PORTH_MUX);
1753
1754 D16(MISCPORT_DRIVE);
1755 D16(MISCPORT_HYSTERESIS);
1756#endif /* BF51x */
1757
1758#ifdef __ADSPBF52x__
1759 D16(PORTF_FER);
1760 D16(PORTF_DRIVE);
1761 D16(PORTF_HYSTERESIS);
1762 D16(PORTF_MUX);
1763 D16(PORTF_SLEW);
1764
1765 D16(PORTG_FER);
1766 D16(PORTG_DRIVE);
1767 D16(PORTG_HYSTERESIS);
1768 D16(PORTG_MUX);
1769 D16(PORTG_SLEW);
1770
1771 D16(PORTH_FER);
1772 D16(PORTH_DRIVE);
1773 D16(PORTH_HYSTERESIS);
1774 D16(PORTH_MUX);
1775 D16(PORTH_SLEW);
1776
1777 D16(MISCPORT_DRIVE);
1778 D16(MISCPORT_HYSTERESIS);
1779 D16(MISCPORT_SLEW);
1780#endif /* BF52x */
1781
1782#ifdef BF537_FAMILY
1783 D16(PORTF_FER);
1784 D16(PORTG_FER);
1785 D16(PORTH_FER);
1786 D16(PORT_MUX);
1787#endif /* BF534 BF536 BF537 */
1788
1789#ifdef BF538_FAMILY
1790 D16(PORTCIO_FER);
1791 D16(PORTCIO);
1792 D16(PORTCIO_CLEAR);
1793 D16(PORTCIO_SET);
1794 D16(PORTCIO_TOGGLE);
1795 D16(PORTCIO_DIR);
1796 D16(PORTCIO_INEN);
1797
1798 D16(PORTDIO);
1799 D16(PORTDIO_CLEAR);
1800 D16(PORTDIO_DIR);
1801 D16(PORTDIO_FER);
1802 D16(PORTDIO_INEN);
1803 D16(PORTDIO_SET);
1804 D16(PORTDIO_TOGGLE);
1805
1806 D16(PORTEIO);
1807 D16(PORTEIO_CLEAR);
1808 D16(PORTEIO_DIR);
1809 D16(PORTEIO_FER);
1810 D16(PORTEIO_INEN);
1811 D16(PORTEIO_SET);
1812 D16(PORTEIO_TOGGLE);
1813#endif /* BF538 BF539 */
1814
1815#ifdef __ADSPBF54x__
1816 {
1817 int num;
1818 unsigned long base;
1819 char *_buf, buf[32];
1820
1821 base = PORTA_FER;
1822 for (num = 0; num < 10; ++num) {
1823 PORT(base, num);
1824 base += sizeof(struct bfin_gpio_regs);
1825 }
1826
1827#define __PINT(uname, lname) __REGS(pint, #uname, lname)
1828 parent = debugfs_create_dir("pint", top);
1829 base = PINT0_MASK_SET;
1830 for (num = 0; num < 4; ++num) {
1831 _buf = REGS_STR_PFX(buf, PINT, num);
1832 __PINT(MASK_SET, mask_set);
1833 __PINT(MASK_CLEAR, mask_clear);
1834 __PINT(IRQ, irq);
1835 __PINT(ASSIGN, assign);
1836 __PINT(EDGE_SET, edge_set);
1837 __PINT(EDGE_CLEAR, edge_clear);
1838 __PINT(INVERT_SET, invert_set);
1839 __PINT(INVERT_CLEAR, invert_clear);
1840 __PINT(PINSTATE, pinstate);
1841 __PINT(LATCH, latch);
1842 base += sizeof(struct bfin_pint_regs);
1843 }
1844
1845 }
1846#endif /* BF54x */
1847
1848 debug_mmrs_dentry = top;
1849
1850 return 0;
1851}
1852module_init(bfin_debug_mmrs_init);
1853
1854static void __exit bfin_debug_mmrs_exit(void)
1855{
1856 debugfs_remove_recursive(debug_mmrs_dentry);
1857}
1858module_exit(bfin_debug_mmrs_exit);
1859
1860MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-06 09:25:16 -0500