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-rw-r--r--include/asm-arm/arch-s3c2410/dma.h90
1 files changed, 41 insertions, 49 deletions
diff --git a/include/asm-arm/arch-s3c2410/dma.h b/include/asm-arm/arch-s3c2410/dma.h
index 46e65409fcc5..3661e465b0a5 100644
--- a/include/asm-arm/arch-s3c2410/dma.h
+++ b/include/asm-arm/arch-s3c2410/dma.h
@@ -1,18 +1,13 @@
1/* linux/include/asm-arm/arch-bast/dma.h 1/* linux/include/asm-arm/arch-s3c2410/dma.h
2 * 2 *
3 * Copyright (C) 2003,2004 Simtec Electronics 3 * Copyright (C) 2003,2004,2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk> 4 * Ben Dooks <ben@simtec.co.uk>
5 * 5 *
6 * Samsung S3C2410X DMA support 6 * Samsung S3C241XX DMA support
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11 *
12 * Changelog:
13 * ??-May-2003 BJD Created file
14 * ??-Jun-2003 BJD Added more dma functionality to go with arch
15 * 10-Nov-2004 BJD Added sys_device support
16*/ 11*/
17 12
18#ifndef __ASM_ARCH_DMA_H 13#ifndef __ASM_ARCH_DMA_H
@@ -21,15 +16,13 @@
21#include <linux/sysdev.h> 16#include <linux/sysdev.h>
22#include "hardware.h" 17#include "hardware.h"
23 18
24
25/* 19/*
26 * This is the maximum DMA address(physical address) that can be DMAd to. 20 * This is the maximum DMA address(physical address) that can be DMAd to.
27 * 21 *
28 */ 22 */
29#define MAX_DMA_ADDRESS 0x20000000 23#define MAX_DMA_ADDRESS 0x40000000
30#define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */ 24#define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */
31 25
32
33/* we have 4 dma channels */ 26/* we have 4 dma channels */
34#define S3C2410_DMA_CHANNELS (4) 27#define S3C2410_DMA_CHANNELS (4)
35 28
@@ -83,10 +76,9 @@ enum s3c2410_dma_buffresult {
83 S3C2410_RES_ABORT 76 S3C2410_RES_ABORT
84}; 77};
85 78
86
87enum s3c2410_dmasrc { 79enum s3c2410_dmasrc {
88 S3C2410_DMASRC_HW, /* source is memory */ 80 S3C2410_DMASRC_HW, /* source is memory */
89 S3C2410_DMASRC_MEM /* source is hardware */ 81 S3C2410_DMASRC_MEM /* source is hardware */
90}; 82};
91 83
92/* enum s3c2410_chan_op 84/* enum s3c2410_chan_op
@@ -101,7 +93,7 @@ enum s3c2410_chan_op {
101 S3C2410_DMAOP_PAUSE, 93 S3C2410_DMAOP_PAUSE,
102 S3C2410_DMAOP_RESUME, 94 S3C2410_DMAOP_RESUME,
103 S3C2410_DMAOP_FLUSH, 95 S3C2410_DMAOP_FLUSH,
104 S3C2410_DMAOP_TIMEOUT, /* internal signal to handler */ 96 S3C2410_DMAOP_TIMEOUT, /* internal signal to handler */
105 S3C2410_DMAOP_STARTED, /* indicate channel started */ 97 S3C2410_DMAOP_STARTED, /* indicate channel started */
106}; 98};
107 99
@@ -125,12 +117,12 @@ struct s3c2410_dma_client {
125 117
126struct s3c2410_dma_buf; 118struct s3c2410_dma_buf;
127struct s3c2410_dma_buf { 119struct s3c2410_dma_buf {
128 struct s3c2410_dma_buf *next; 120 struct s3c2410_dma_buf *next;
129 int magic; /* magic */ 121 int magic; /* magic */
130 int size; /* buffer size in bytes */ 122 int size; /* buffer size in bytes */
131 dma_addr_t data; /* start of DMA data */ 123 dma_addr_t data; /* start of DMA data */
132 dma_addr_t ptr; /* where the DMA got to [1] */ 124 dma_addr_t ptr; /* where the DMA got to [1] */
133 void *id; /* client's id */ 125 void *id; /* client's id */
134}; 126};
135 127
136/* [1] is this updated for both recv/send modes? */ 128/* [1] is this updated for both recv/send modes? */
@@ -150,11 +142,11 @@ typedef int (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *,
150 enum s3c2410_chan_op ); 142 enum s3c2410_chan_op );
151 143
152struct s3c2410_dma_stats { 144struct s3c2410_dma_stats {
153 unsigned long loads; 145 unsigned long loads;
154 unsigned long timeout_longest; 146 unsigned long timeout_longest;
155 unsigned long timeout_shortest; 147 unsigned long timeout_shortest;
156 unsigned long timeout_avg; 148 unsigned long timeout_avg;
157 unsigned long timeout_failed; 149 unsigned long timeout_failed;
158}; 150};
159 151
160/* struct s3c2410_dma_chan 152/* struct s3c2410_dma_chan
@@ -164,42 +156,42 @@ struct s3c2410_dma_stats {
164 156
165struct s3c2410_dma_chan { 157struct s3c2410_dma_chan {
166 /* channel state flags and information */ 158 /* channel state flags and information */
167 unsigned char number; /* number of this dma channel */ 159 unsigned char number; /* number of this dma channel */
168 unsigned char in_use; /* channel allocated */ 160 unsigned char in_use; /* channel allocated */
169 unsigned char irq_claimed; /* irq claimed for channel */ 161 unsigned char irq_claimed; /* irq claimed for channel */
170 unsigned char irq_enabled; /* irq enabled for channel */ 162 unsigned char irq_enabled; /* irq enabled for channel */
171 unsigned char xfer_unit; /* size of an transfer */ 163 unsigned char xfer_unit; /* size of an transfer */
172 164
173 /* channel state */ 165 /* channel state */
174 166
175 enum s3c2410_dma_state state; 167 enum s3c2410_dma_state state;
176 enum s3c2410_dma_loadst load_state; 168 enum s3c2410_dma_loadst load_state;
177 struct s3c2410_dma_client *client; 169 struct s3c2410_dma_client *client;
178 170
179 /* channel configuration */ 171 /* channel configuration */
180 enum s3c2410_dmasrc source; 172 enum s3c2410_dmasrc source;
181 unsigned long dev_addr; 173 unsigned long dev_addr;
182 unsigned long load_timeout; 174 unsigned long load_timeout;
183 unsigned int flags; /* channel flags */ 175 unsigned int flags; /* channel flags */
184 176
185 /* channel's hardware position and configuration */ 177 /* channel's hardware position and configuration */
186 void __iomem *regs; /* channels registers */ 178 void __iomem *regs; /* channels registers */
187 void __iomem *addr_reg; /* data address register */ 179 void __iomem *addr_reg; /* data address register */
188 unsigned int irq; /* channel irq */ 180 unsigned int irq; /* channel irq */
189 unsigned long dcon; /* default value of DCON */ 181 unsigned long dcon; /* default value of DCON */
190 182
191 /* driver handles */ 183 /* driver handles */
192 s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */ 184 s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */
193 s3c2410_dma_opfn_t op_fn; /* channel operation callback */ 185 s3c2410_dma_opfn_t op_fn; /* channel op callback */
194 186
195 /* stats gathering */ 187 /* stats gathering */
196 struct s3c2410_dma_stats *stats; 188 struct s3c2410_dma_stats *stats;
197 struct s3c2410_dma_stats stats_store; 189 struct s3c2410_dma_stats stats_store;
198 190
199 /* buffer list and information */ 191 /* buffer list and information */
200 struct s3c2410_dma_buf *curr; /* current dma buffer */ 192 struct s3c2410_dma_buf *curr; /* current dma buffer */
201 struct s3c2410_dma_buf *next; /* next buffer to load */ 193 struct s3c2410_dma_buf *next; /* next buffer to load */
202 struct s3c2410_dma_buf *end; /* end of queue */ 194 struct s3c2410_dma_buf *end; /* end of queue */
203 195
204 /* system device */ 196 /* system device */
205 struct sys_device dev; 197 struct sys_device dev;