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-rw-r--r--arch/arm/Kconfig20
-rw-r--r--arch/arm/common/gic.c16
-rw-r--r--arch/arm/common/pl330.c12
-rw-r--r--arch/arm/include/asm/pmu.h10
-rw-r--r--arch/arm/include/asm/topology.h2
-rw-r--r--arch/arm/kernel/entry-armv.S2
-rw-r--r--arch/arm/kernel/kprobes-arm.c4
-rw-r--r--arch/arm/kernel/kprobes-test-arm.c27
-rw-r--r--arch/arm/kernel/kprobes-test-thumb.c16
-rw-r--r--arch/arm/kernel/kprobes-test.h100
-rw-r--r--arch/arm/kernel/perf_event.c11
-rw-r--r--arch/arm/kernel/pmu.c1
-rw-r--r--arch/arm/kernel/process.c3
-rw-r--r--arch/arm/kernel/topology.c2
-rw-r--r--arch/arm/lib/bitops.h26
-rw-r--r--arch/arm/lib/changebit.S4
-rw-r--r--arch/arm/lib/clearbit.S4
-rw-r--r--arch/arm/lib/setbit.S4
-rw-r--r--arch/arm/lib/testchangebit.S4
-rw-r--r--arch/arm/lib/testclearbit.S4
-rw-r--r--arch/arm/lib/testsetbit.S4
-rw-r--r--arch/arm/mm/cache-l2x0.c2
-rw-r--r--arch/arm/mm/dma-mapping.c11
-rw-r--r--arch/arm/mm/mmap.c23
-rw-r--r--drivers/i2c/busses/i2c-nuc900.c2
-rw-r--r--drivers/spi/spi-nuc900.c2
-rw-r--r--sound/soc/nuc900/nuc900-ac97.c3
27 files changed, 199 insertions, 120 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 44789eff983f..e084b7e981e8 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1231,7 +1231,7 @@ config ARM_ERRATA_742231
1231 capabilities of the processor. 1231 capabilities of the processor.
1232 1232
1233config PL310_ERRATA_588369 1233config PL310_ERRATA_588369
1234 bool "Clean & Invalidate maintenance operations do not invalidate clean lines" 1234 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1235 depends on CACHE_L2X0 1235 depends on CACHE_L2X0
1236 help 1236 help
1237 The PL310 L2 cache controller implements three types of Clean & 1237 The PL310 L2 cache controller implements three types of Clean &
@@ -1256,7 +1256,7 @@ config ARM_ERRATA_720789
1256 entries regardless of the ASID. 1256 entries regardless of the ASID.
1257 1257
1258config PL310_ERRATA_727915 1258config PL310_ERRATA_727915
1259 bool "Background Clean & Invalidate by Way operation can cause data corruption" 1259 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1260 depends on CACHE_L2X0 1260 depends on CACHE_L2X0
1261 help 1261 help
1262 PL310 implements the Clean & Invalidate by Way L2 cache maintenance 1262 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
@@ -1289,8 +1289,8 @@ config ARM_ERRATA_751472
1289 operation is received by a CPU before the ICIALLUIS has completed, 1289 operation is received by a CPU before the ICIALLUIS has completed,
1290 potentially leading to corrupted entries in the cache or TLB. 1290 potentially leading to corrupted entries in the cache or TLB.
1291 1291
1292config ARM_ERRATA_753970 1292config PL310_ERRATA_753970
1293 bool "ARM errata: cache sync operation may be faulty" 1293 bool "PL310 errata: cache sync operation may be faulty"
1294 depends on CACHE_PL310 1294 depends on CACHE_PL310
1295 help 1295 help
1296 This option enables the workaround for the 753970 PL310 (r3p0) erratum. 1296 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
@@ -1352,6 +1352,18 @@ config ARM_ERRATA_764369
1352 relevant cache maintenance functions and sets a specific bit 1352 relevant cache maintenance functions and sets a specific bit
1353 in the diagnostic control register of the SCU. 1353 in the diagnostic control register of the SCU.
1354 1354
1355config PL310_ERRATA_769419
1356 bool "PL310 errata: no automatic Store Buffer drain"
1357 depends on CACHE_L2X0
1358 help
1359 On revisions of the PL310 prior to r3p2, the Store Buffer does
1360 not automatically drain. This can cause normal, non-cacheable
1361 writes to be retained when the memory system is idle, leading
1362 to suboptimal I/O performance for drivers using coherent DMA.
1363 This option adds a write barrier to the cpu_idle loop so that,
1364 on systems with an outer cache, the store buffer is drained
1365 explicitly.
1366
1355endmenu 1367endmenu
1356 1368
1357source "arch/arm/common/Kconfig" 1369source "arch/arm/common/Kconfig"
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 0e6ae470c94f..410a546060a2 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -526,7 +526,8 @@ static void __init gic_pm_init(struct gic_chip_data *gic)
526 sizeof(u32)); 526 sizeof(u32));
527 BUG_ON(!gic->saved_ppi_conf); 527 BUG_ON(!gic->saved_ppi_conf);
528 528
529 cpu_pm_register_notifier(&gic_notifier_block); 529 if (gic == &gic_data[0])
530 cpu_pm_register_notifier(&gic_notifier_block);
530} 531}
531#else 532#else
532static void __init gic_pm_init(struct gic_chip_data *gic) 533static void __init gic_pm_init(struct gic_chip_data *gic)
@@ -581,13 +582,16 @@ void __init gic_init(unsigned int gic_nr, int irq_start,
581 * For primary GICs, skip over SGIs. 582 * For primary GICs, skip over SGIs.
582 * For secondary GICs, skip over PPIs, too. 583 * For secondary GICs, skip over PPIs, too.
583 */ 584 */
585 domain->hwirq_base = 32;
584 if (gic_nr == 0) { 586 if (gic_nr == 0) {
585 gic_cpu_base_addr = cpu_base; 587 gic_cpu_base_addr = cpu_base;
586 domain->hwirq_base = 16; 588
587 if (irq_start > 0) 589 if ((irq_start & 31) > 0) {
588 irq_start = (irq_start & ~31) + 16; 590 domain->hwirq_base = 16;
589 } else 591 if (irq_start != -1)
590 domain->hwirq_base = 32; 592 irq_start = (irq_start & ~31) + 16;
593 }
594 }
591 595
592 /* 596 /*
593 * Find out how many interrupts are supported. 597 * Find out how many interrupts are supported.
diff --git a/arch/arm/common/pl330.c b/arch/arm/common/pl330.c
index 7129cfbdacd6..f407a6b35d3d 100644
--- a/arch/arm/common/pl330.c
+++ b/arch/arm/common/pl330.c
@@ -1211,8 +1211,8 @@ static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc)
1211 ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT); 1211 ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT);
1212 ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT); 1212 ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT);
1213 1213
1214 ccr |= (rqc->dcctl << CC_SRCCCTRL_SHFT); 1214 ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT);
1215 ccr |= (rqc->scctl << CC_DSTCCTRL_SHFT); 1215 ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT);
1216 1216
1217 ccr |= (rqc->swap << CC_SWAP_SHFT); 1217 ccr |= (rqc->swap << CC_SWAP_SHFT);
1218 1218
@@ -1623,6 +1623,11 @@ static inline int _alloc_event(struct pl330_thread *thrd)
1623 return -1; 1623 return -1;
1624} 1624}
1625 1625
1626static bool _chan_ns(const struct pl330_info *pi, int i)
1627{
1628 return pi->pcfg.irq_ns & (1 << i);
1629}
1630
1626/* Upon success, returns IdentityToken for the 1631/* Upon success, returns IdentityToken for the
1627 * allocated channel, NULL otherwise. 1632 * allocated channel, NULL otherwise.
1628 */ 1633 */
@@ -1647,7 +1652,8 @@ void *pl330_request_channel(const struct pl330_info *pi)
1647 1652
1648 for (i = 0; i < chans; i++) { 1653 for (i = 0; i < chans; i++) {
1649 thrd = &pl330->channels[i]; 1654 thrd = &pl330->channels[i];
1650 if (thrd->free) { 1655 if ((thrd->free) && (!_manager_ns(thrd) ||
1656 _chan_ns(pi, i))) {
1651 thrd->ev = _alloc_event(thrd); 1657 thrd->ev = _alloc_event(thrd);
1652 if (thrd->ev >= 0) { 1658 if (thrd->ev >= 0) {
1653 thrd->free = false; 1659 thrd->free = false;
diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h
index 71d99b83cdb9..0bda22c094a6 100644
--- a/arch/arm/include/asm/pmu.h
+++ b/arch/arm/include/asm/pmu.h
@@ -55,16 +55,6 @@ reserve_pmu(enum arm_pmu_type type);
55extern void 55extern void
56release_pmu(enum arm_pmu_type type); 56release_pmu(enum arm_pmu_type type);
57 57
58/**
59 * init_pmu() - Initialise the PMU.
60 *
61 * Initialise the system ready for PMU enabling. This should typically set the
62 * IRQ affinity and nothing else. The users (oprofile/perf events etc) will do
63 * the actual hardware initialisation.
64 */
65extern int
66init_pmu(enum arm_pmu_type type);
67
68#else /* CONFIG_CPU_HAS_PMU */ 58#else /* CONFIG_CPU_HAS_PMU */
69 59
70#include <linux/err.h> 60#include <linux/err.h>
diff --git a/arch/arm/include/asm/topology.h b/arch/arm/include/asm/topology.h
index a7e457ed27c3..58b8b84adcd2 100644
--- a/arch/arm/include/asm/topology.h
+++ b/arch/arm/include/asm/topology.h
@@ -25,7 +25,7 @@ extern struct cputopo_arm cpu_topology[NR_CPUS];
25 25
26void init_cpu_topology(void); 26void init_cpu_topology(void);
27void store_cpu_topology(unsigned int cpuid); 27void store_cpu_topology(unsigned int cpuid);
28const struct cpumask *cpu_coregroup_mask(unsigned int cpu); 28const struct cpumask *cpu_coregroup_mask(int cpu);
29 29
30#else 30#else
31 31
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 9ad50c4208ae..b145f16c91bc 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -497,7 +497,7 @@ ENDPROC(__und_usr)
497 .popsection 497 .popsection
498 .pushsection __ex_table,"a" 498 .pushsection __ex_table,"a"
499 .long 1b, 4b 499 .long 1b, 4b
500#if __LINUX_ARM_ARCH__ >= 7 500#if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7
501 .long 2b, 4b 501 .long 2b, 4b
502 .long 3b, 4b 502 .long 3b, 4b
503#endif 503#endif
diff --git a/arch/arm/kernel/kprobes-arm.c b/arch/arm/kernel/kprobes-arm.c
index 9fe8910308af..8a30c89da70e 100644
--- a/arch/arm/kernel/kprobes-arm.c
+++ b/arch/arm/kernel/kprobes-arm.c
@@ -519,10 +519,12 @@ static const union decode_item arm_cccc_0000_____1001_table[] = {
519static const union decode_item arm_cccc_0001_____1001_table[] = { 519static const union decode_item arm_cccc_0001_____1001_table[] = {
520 /* Synchronization primitives */ 520 /* Synchronization primitives */
521 521
522#if __LINUX_ARM_ARCH__ < 6
523 /* Deprecated on ARMv6 and may be UNDEFINED on v7 */
522 /* SMP/SWPB cccc 0001 0x00 xxxx xxxx xxxx 1001 xxxx */ 524 /* SMP/SWPB cccc 0001 0x00 xxxx xxxx xxxx 1001 xxxx */
523 DECODE_EMULATEX (0x0fb000f0, 0x01000090, emulate_rd12rn16rm0_rwflags_nopc, 525 DECODE_EMULATEX (0x0fb000f0, 0x01000090, emulate_rd12rn16rm0_rwflags_nopc,
524 REGS(NOPC, NOPC, 0, 0, NOPC)), 526 REGS(NOPC, NOPC, 0, 0, NOPC)),
525 527#endif
526 /* LDREX/STREX{,D,B,H} cccc 0001 1xxx xxxx xxxx xxxx 1001 xxxx */ 528 /* LDREX/STREX{,D,B,H} cccc 0001 1xxx xxxx xxxx xxxx 1001 xxxx */
527 /* And unallocated instructions... */ 529 /* And unallocated instructions... */
528 DECODE_END 530 DECODE_END
diff --git a/arch/arm/kernel/kprobes-test-arm.c b/arch/arm/kernel/kprobes-test-arm.c
index fc82de8bdcce..ba32b393b3f0 100644
--- a/arch/arm/kernel/kprobes-test-arm.c
+++ b/arch/arm/kernel/kprobes-test-arm.c
@@ -427,18 +427,25 @@ void kprobe_arm_test_cases(void)
427 427
428 TEST_GROUP("Synchronization primitives") 428 TEST_GROUP("Synchronization primitives")
429 429
430 /* 430#if __LINUX_ARM_ARCH__ < 6
431 * Use hard coded constants for SWP instructions to avoid warnings 431 TEST_RP("swp lr, r",7,VAL2,", [r",8,0,"]")
432 * about deprecated instructions. 432 TEST_R( "swpvs r0, r",1,VAL1,", [sp]")
433 */ 433 TEST_RP("swp sp, r",14,VAL2,", [r",12,13*4,"]")
434 TEST_RP( ".word 0xe108e097 @ swp lr, r",7,VAL2,", [r",8,0,"]") 434#else
435 TEST_R( ".word 0x610d0091 @ swpvs r0, r",1,VAL1,", [sp]") 435 TEST_UNSUPPORTED(".word 0xe108e097 @ swp lr, r7, [r8]")
436 TEST_RP( ".word 0xe10cd09e @ swp sp, r",14,VAL2,", [r",12,13*4,"]") 436 TEST_UNSUPPORTED(".word 0x610d0091 @ swpvs r0, r1, [sp]")
437 TEST_UNSUPPORTED(".word 0xe10cd09e @ swp sp, r14 [r12]")
438#endif
437 TEST_UNSUPPORTED(".word 0xe102f091 @ swp pc, r1, [r2]") 439 TEST_UNSUPPORTED(".word 0xe102f091 @ swp pc, r1, [r2]")
438 TEST_UNSUPPORTED(".word 0xe102009f @ swp r0, pc, [r2]") 440 TEST_UNSUPPORTED(".word 0xe102009f @ swp r0, pc, [r2]")
439 TEST_UNSUPPORTED(".word 0xe10f0091 @ swp r0, r1, [pc]") 441 TEST_UNSUPPORTED(".word 0xe10f0091 @ swp r0, r1, [pc]")
440 TEST_RP( ".word 0xe148e097 @ swpb lr, r",7,VAL2,", [r",8,0,"]") 442#if __LINUX_ARM_ARCH__ < 6
441 TEST_R( ".word 0x614d0091 @ swpvsb r0, r",1,VAL1,", [sp]") 443 TEST_RP("swpb lr, r",7,VAL2,", [r",8,0,"]")
444 TEST_R( "swpvsb r0, r",1,VAL1,", [sp]")
445#else
446 TEST_UNSUPPORTED(".word 0xe148e097 @ swpb lr, r7, [r8]")
447 TEST_UNSUPPORTED(".word 0x614d0091 @ swpvsb r0, r1, [sp]")
448#endif
442 TEST_UNSUPPORTED(".word 0xe142f091 @ swpb pc, r1, [r2]") 449 TEST_UNSUPPORTED(".word 0xe142f091 @ swpb pc, r1, [r2]")
443 450
444 TEST_UNSUPPORTED(".word 0xe1100090") /* Unallocated space */ 451 TEST_UNSUPPORTED(".word 0xe1100090") /* Unallocated space */
@@ -550,7 +557,7 @@ void kprobe_arm_test_cases(void)
550 TEST_RPR( "strccd r",8, VAL2,", [r",13,0, ", r",12,48,"]") 557 TEST_RPR( "strccd r",8, VAL2,", [r",13,0, ", r",12,48,"]")
551 TEST_RPR( "strd r",4, VAL1,", [r",2, 24,", r",3, 48,"]!") 558 TEST_RPR( "strd r",4, VAL1,", [r",2, 24,", r",3, 48,"]!")
552 TEST_RPR( "strcsd r",12,VAL2,", [r",11,48,", -r",10,24,"]!") 559 TEST_RPR( "strcsd r",12,VAL2,", [r",11,48,", -r",10,24,"]!")
553 TEST_RPR( "strd r",2, VAL1,", [r",3, 24,"], r",4,48,"") 560 TEST_RPR( "strd r",2, VAL1,", [r",5, 24,"], r",4,48,"")
554 TEST_RPR( "strd r",10,VAL2,", [r",9, 48,"], -r",7,24,"") 561 TEST_RPR( "strd r",10,VAL2,", [r",9, 48,"], -r",7,24,"")
555 TEST_UNSUPPORTED(".word 0xe1afc0fa @ strd r12, [pc, r10]!") 562 TEST_UNSUPPORTED(".word 0xe1afc0fa @ strd r12, [pc, r10]!")
556 563
diff --git a/arch/arm/kernel/kprobes-test-thumb.c b/arch/arm/kernel/kprobes-test-thumb.c
index 5e726c31c45a..5d8b85792222 100644
--- a/arch/arm/kernel/kprobes-test-thumb.c
+++ b/arch/arm/kernel/kprobes-test-thumb.c
@@ -222,8 +222,8 @@ void kprobe_thumb16_test_cases(void)
222DONT_TEST_IN_ITBLOCK( 222DONT_TEST_IN_ITBLOCK(
223 TEST_BF_R( "cbnz r",0,0, ", 2f") 223 TEST_BF_R( "cbnz r",0,0, ", 2f")
224 TEST_BF_R( "cbz r",2,-1,", 2f") 224 TEST_BF_R( "cbz r",2,-1,", 2f")
225 TEST_BF_RX( "cbnz r",4,1, ", 2f",0x20) 225 TEST_BF_RX( "cbnz r",4,1, ", 2f", SPACE_0x20)
226 TEST_BF_RX( "cbz r",7,0, ", 2f",0x40) 226 TEST_BF_RX( "cbz r",7,0, ", 2f", SPACE_0x40)
227) 227)
228 TEST_R("sxth r0, r",7, HH1,"") 228 TEST_R("sxth r0, r",7, HH1,"")
229 TEST_R("sxth r7, r",0, HH2,"") 229 TEST_R("sxth r7, r",0, HH2,"")
@@ -246,7 +246,7 @@ DONT_TEST_IN_ITBLOCK(
246 TESTCASE_START(code) \ 246 TESTCASE_START(code) \
247 TEST_ARG_PTR(13, offset) \ 247 TEST_ARG_PTR(13, offset) \
248 TEST_ARG_END("") \ 248 TEST_ARG_END("") \
249 TEST_BRANCH_F(code,0) \ 249 TEST_BRANCH_F(code) \
250 TESTCASE_END 250 TESTCASE_END
251 251
252 TEST("push {r0}") 252 TEST("push {r0}")
@@ -319,8 +319,8 @@ CONDITION_INSTRUCTIONS(8,
319 319
320 TEST_BF( "b 2f") 320 TEST_BF( "b 2f")
321 TEST_BB( "b 2b") 321 TEST_BB( "b 2b")
322 TEST_BF_X("b 2f", 0x400) 322 TEST_BF_X("b 2f", SPACE_0x400)
323 TEST_BB_X("b 2b", 0x400) 323 TEST_BB_X("b 2b", SPACE_0x400)
324 324
325 TEST_GROUP("Testing instructions in IT blocks") 325 TEST_GROUP("Testing instructions in IT blocks")
326 326
@@ -746,7 +746,7 @@ CONDITION_INSTRUCTIONS(22,
746 TEST_BB("bne.w 2b") 746 TEST_BB("bne.w 2b")
747 TEST_BF("bgt.w 2f") 747 TEST_BF("bgt.w 2f")
748 TEST_BB("blt.w 2b") 748 TEST_BB("blt.w 2b")
749 TEST_BF_X("bpl.w 2f",0x1000) 749 TEST_BF_X("bpl.w 2f", SPACE_0x1000)
750) 750)
751 751
752 TEST_UNSUPPORTED("msr cpsr, r0") 752 TEST_UNSUPPORTED("msr cpsr, r0")
@@ -786,11 +786,11 @@ CONDITION_INSTRUCTIONS(22,
786 786
787 TEST_BF( "b.w 2f") 787 TEST_BF( "b.w 2f")
788 TEST_BB( "b.w 2b") 788 TEST_BB( "b.w 2b")
789 TEST_BF_X("b.w 2f", 0x1000) 789 TEST_BF_X("b.w 2f", SPACE_0x1000)
790 790
791 TEST_BF( "bl.w 2f") 791 TEST_BF( "bl.w 2f")
792 TEST_BB( "bl.w 2b") 792 TEST_BB( "bl.w 2b")
793 TEST_BB_X("bl.w 2b", 0x1000) 793 TEST_BB_X("bl.w 2b", SPACE_0x1000)
794 794
795 TEST_X( "blx __dummy_arm_subroutine", 795 TEST_X( "blx __dummy_arm_subroutine",
796 ".arm \n\t" 796 ".arm \n\t"
diff --git a/arch/arm/kernel/kprobes-test.h b/arch/arm/kernel/kprobes-test.h
index 0dc5d77b9356..e28a869b1ae4 100644
--- a/arch/arm/kernel/kprobes-test.h
+++ b/arch/arm/kernel/kprobes-test.h
@@ -149,23 +149,31 @@ struct test_arg_end {
149 "1: "instruction" \n\t" \ 149 "1: "instruction" \n\t" \
150 " nop \n\t" 150 " nop \n\t"
151 151
152#define TEST_BRANCH_F(instruction, xtra_dist) \ 152#define TEST_BRANCH_F(instruction) \
153 TEST_INSTRUCTION(instruction) \ 153 TEST_INSTRUCTION(instruction) \
154 ".if "#xtra_dist" \n\t" \
155 " b 99f \n\t" \ 154 " b 99f \n\t" \
156 ".space "#xtra_dist" \n\t" \ 155 "2: nop \n\t"
157 ".endif \n\t" \ 156
157#define TEST_BRANCH_B(instruction) \
158 " b 50f \n\t" \
159 " b 99f \n\t" \
160 "2: nop \n\t" \
161 " b 99f \n\t" \
162 TEST_INSTRUCTION(instruction)
163
164#define TEST_BRANCH_FX(instruction, codex) \
165 TEST_INSTRUCTION(instruction) \
166 " b 99f \n\t" \
167 codex" \n\t" \
158 " b 99f \n\t" \ 168 " b 99f \n\t" \
159 "2: nop \n\t" 169 "2: nop \n\t"
160 170
161#define TEST_BRANCH_B(instruction, xtra_dist) \ 171#define TEST_BRANCH_BX(instruction, codex) \
162 " b 50f \n\t" \ 172 " b 50f \n\t" \
163 " b 99f \n\t" \ 173 " b 99f \n\t" \
164 "2: nop \n\t" \ 174 "2: nop \n\t" \
165 " b 99f \n\t" \ 175 " b 99f \n\t" \
166 ".if "#xtra_dist" \n\t" \ 176 codex" \n\t" \
167 ".space "#xtra_dist" \n\t" \
168 ".endif \n\t" \
169 TEST_INSTRUCTION(instruction) 177 TEST_INSTRUCTION(instruction)
170 178
171#define TESTCASE_END \ 179#define TESTCASE_END \
@@ -301,47 +309,60 @@ struct test_arg_end {
301 TESTCASE_START(code1 #reg1 code2) \ 309 TESTCASE_START(code1 #reg1 code2) \
302 TEST_ARG_PTR(reg1, val1) \ 310 TEST_ARG_PTR(reg1, val1) \
303 TEST_ARG_END("") \ 311 TEST_ARG_END("") \
304 TEST_BRANCH_F(code1 #reg1 code2, 0) \ 312 TEST_BRANCH_F(code1 #reg1 code2) \
305 TESTCASE_END 313 TESTCASE_END
306 314
307#define TEST_BF_X(code, xtra_dist) \ 315#define TEST_BF(code) \
308 TESTCASE_START(code) \ 316 TESTCASE_START(code) \
309 TEST_ARG_END("") \ 317 TEST_ARG_END("") \
310 TEST_BRANCH_F(code, xtra_dist) \ 318 TEST_BRANCH_F(code) \
311 TESTCASE_END 319 TESTCASE_END
312 320
313#define TEST_BB_X(code, xtra_dist) \ 321#define TEST_BB(code) \
314 TESTCASE_START(code) \ 322 TESTCASE_START(code) \
315 TEST_ARG_END("") \ 323 TEST_ARG_END("") \
316 TEST_BRANCH_B(code, xtra_dist) \ 324 TEST_BRANCH_B(code) \
317 TESTCASE_END 325 TESTCASE_END
318 326
319#define TEST_BF_RX(code1, reg, val, code2, xtra_dist) \ 327#define TEST_BF_R(code1, reg, val, code2) \
320 TESTCASE_START(code1 #reg code2) \ 328 TESTCASE_START(code1 #reg code2) \
321 TEST_ARG_REG(reg, val) \ 329 TEST_ARG_REG(reg, val) \
322 TEST_ARG_END("") \ 330 TEST_ARG_END("") \
323 TEST_BRANCH_F(code1 #reg code2, xtra_dist) \ 331 TEST_BRANCH_F(code1 #reg code2) \
324 TESTCASE_END 332 TESTCASE_END
325 333
326#define TEST_BB_RX(code1, reg, val, code2, xtra_dist) \ 334#define TEST_BB_R(code1, reg, val, code2) \
327 TESTCASE_START(code1 #reg code2) \ 335 TESTCASE_START(code1 #reg code2) \
328 TEST_ARG_REG(reg, val) \ 336 TEST_ARG_REG(reg, val) \
329 TEST_ARG_END("") \ 337 TEST_ARG_END("") \
330 TEST_BRANCH_B(code1 #reg code2, xtra_dist) \ 338 TEST_BRANCH_B(code1 #reg code2) \
331 TESTCASE_END 339 TESTCASE_END
332 340
333#define TEST_BF(code) TEST_BF_X(code, 0)
334#define TEST_BB(code) TEST_BB_X(code, 0)
335
336#define TEST_BF_R(code1, reg, val, code2) TEST_BF_RX(code1, reg, val, code2, 0)
337#define TEST_BB_R(code1, reg, val, code2) TEST_BB_RX(code1, reg, val, code2, 0)
338
339#define TEST_BF_RR(code1, reg1, val1, code2, reg2, val2, code3) \ 341#define TEST_BF_RR(code1, reg1, val1, code2, reg2, val2, code3) \
340 TESTCASE_START(code1 #reg1 code2 #reg2 code3) \ 342 TESTCASE_START(code1 #reg1 code2 #reg2 code3) \
341 TEST_ARG_REG(reg1, val1) \ 343 TEST_ARG_REG(reg1, val1) \
342 TEST_ARG_REG(reg2, val2) \ 344 TEST_ARG_REG(reg2, val2) \
343 TEST_ARG_END("") \ 345 TEST_ARG_END("") \
344 TEST_BRANCH_F(code1 #reg1 code2 #reg2 code3, 0) \ 346 TEST_BRANCH_F(code1 #reg1 code2 #reg2 code3) \
347 TESTCASE_END
348
349#define TEST_BF_X(code, codex) \
350 TESTCASE_START(code) \
351 TEST_ARG_END("") \
352 TEST_BRANCH_FX(code, codex) \
353 TESTCASE_END
354
355#define TEST_BB_X(code, codex) \
356 TESTCASE_START(code) \
357 TEST_ARG_END("") \
358 TEST_BRANCH_BX(code, codex) \
359 TESTCASE_END
360
361#define TEST_BF_RX(code1, reg, val, code2, codex) \
362 TESTCASE_START(code1 #reg code2) \
363 TEST_ARG_REG(reg, val) \
364 TEST_ARG_END("") \
365 TEST_BRANCH_FX(code1 #reg code2, codex) \
345 TESTCASE_END 366 TESTCASE_END
346 367
347#define TEST_X(code, codex) \ 368#define TEST_X(code, codex) \
@@ -372,6 +393,25 @@ struct test_arg_end {
372 TESTCASE_END 393 TESTCASE_END
373 394
374 395
396/*
397 * Macros for defining space directives spread over multiple lines.
398 * These are required so the compiler guesses better the length of inline asm
399 * code and will spill the literal pool early enough to avoid generating PC
400 * relative loads with out of range offsets.
401 */
402#define TWICE(x) x x
403#define SPACE_0x8 TWICE(".space 4\n\t")
404#define SPACE_0x10 TWICE(SPACE_0x8)
405#define SPACE_0x20 TWICE(SPACE_0x10)
406#define SPACE_0x40 TWICE(SPACE_0x20)
407#define SPACE_0x80 TWICE(SPACE_0x40)
408#define SPACE_0x100 TWICE(SPACE_0x80)
409#define SPACE_0x200 TWICE(SPACE_0x100)
410#define SPACE_0x400 TWICE(SPACE_0x200)
411#define SPACE_0x800 TWICE(SPACE_0x400)
412#define SPACE_0x1000 TWICE(SPACE_0x800)
413
414
375/* Various values used in test cases... */ 415/* Various values used in test cases... */
376#define N(val) (val ^ 0xffffffff) 416#define N(val) (val ^ 0xffffffff)
377#define VAL1 0x12345678 417#define VAL1 0x12345678
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index 24e2347be6b1..c475379199b1 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -343,8 +343,14 @@ validate_group(struct perf_event *event)
343{ 343{
344 struct perf_event *sibling, *leader = event->group_leader; 344 struct perf_event *sibling, *leader = event->group_leader;
345 struct pmu_hw_events fake_pmu; 345 struct pmu_hw_events fake_pmu;
346 DECLARE_BITMAP(fake_used_mask, ARMPMU_MAX_HWEVENTS);
346 347
347 memset(&fake_pmu, 0, sizeof(fake_pmu)); 348 /*
349 * Initialise the fake PMU. We only need to populate the
350 * used_mask for the purposes of validation.
351 */
352 memset(fake_used_mask, 0, sizeof(fake_used_mask));
353 fake_pmu.used_mask = fake_used_mask;
348 354
349 if (!validate_event(&fake_pmu, leader)) 355 if (!validate_event(&fake_pmu, leader))
350 return -ENOSPC; 356 return -ENOSPC;
@@ -396,6 +402,9 @@ armpmu_reserve_hardware(struct arm_pmu *armpmu)
396 int i, err, irq, irqs; 402 int i, err, irq, irqs;
397 struct platform_device *pmu_device = armpmu->plat_device; 403 struct platform_device *pmu_device = armpmu->plat_device;
398 404
405 if (!pmu_device)
406 return -ENODEV;
407
399 err = reserve_pmu(armpmu->type); 408 err = reserve_pmu(armpmu->type);
400 if (err) { 409 if (err) {
401 pr_warning("unable to reserve pmu\n"); 410 pr_warning("unable to reserve pmu\n");
diff --git a/arch/arm/kernel/pmu.c b/arch/arm/kernel/pmu.c
index 2c3407ee8576..2334bf8a650a 100644
--- a/arch/arm/kernel/pmu.c
+++ b/arch/arm/kernel/pmu.c
@@ -33,3 +33,4 @@ release_pmu(enum arm_pmu_type type)
33{ 33{
34 clear_bit_unlock(type, pmu_lock); 34 clear_bit_unlock(type, pmu_lock);
35} 35}
36EXPORT_SYMBOL_GPL(release_pmu);
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 75316f0dd02a..3d0c6fb74ae4 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -192,6 +192,9 @@ void cpu_idle(void)
192#endif 192#endif
193 193
194 local_irq_disable(); 194 local_irq_disable();
195#ifdef CONFIG_PL310_ERRATA_769419
196 wmb();
197#endif
195 if (hlt_counter) { 198 if (hlt_counter) {
196 local_irq_enable(); 199 local_irq_enable();
197 cpu_relax(); 200 cpu_relax();
diff --git a/arch/arm/kernel/topology.c b/arch/arm/kernel/topology.c
index 1040c00405d0..8200deaa14f6 100644
--- a/arch/arm/kernel/topology.c
+++ b/arch/arm/kernel/topology.c
@@ -43,7 +43,7 @@
43 43
44struct cputopo_arm cpu_topology[NR_CPUS]; 44struct cputopo_arm cpu_topology[NR_CPUS];
45 45
46const struct cpumask *cpu_coregroup_mask(unsigned int cpu) 46const struct cpumask *cpu_coregroup_mask(int cpu)
47{ 47{
48 return &cpu_topology[cpu].core_sibling; 48 return &cpu_topology[cpu].core_sibling;
49} 49}
diff --git a/arch/arm/lib/bitops.h b/arch/arm/lib/bitops.h
index 10d868a5a481..d6408d1ee543 100644
--- a/arch/arm/lib/bitops.h
+++ b/arch/arm/lib/bitops.h
@@ -1,5 +1,9 @@
1#include <asm/unwind.h>
2
1#if __LINUX_ARM_ARCH__ >= 6 3#if __LINUX_ARM_ARCH__ >= 6
2 .macro bitop, instr 4 .macro bitop, name, instr
5ENTRY( \name )
6UNWIND( .fnstart )
3 ands ip, r1, #3 7 ands ip, r1, #3
4 strneb r1, [ip] @ assert word-aligned 8 strneb r1, [ip] @ assert word-aligned
5 mov r2, #1 9 mov r2, #1
@@ -13,9 +17,13 @@
13 cmp r0, #0 17 cmp r0, #0
14 bne 1b 18 bne 1b
15 bx lr 19 bx lr
20UNWIND( .fnend )
21ENDPROC(\name )
16 .endm 22 .endm
17 23
18 .macro testop, instr, store 24 .macro testop, name, instr, store
25ENTRY( \name )
26UNWIND( .fnstart )
19 ands ip, r1, #3 27 ands ip, r1, #3
20 strneb r1, [ip] @ assert word-aligned 28 strneb r1, [ip] @ assert word-aligned
21 mov r2, #1 29 mov r2, #1
@@ -34,9 +42,13 @@
34 cmp r0, #0 42 cmp r0, #0
35 movne r0, #1 43 movne r0, #1
362: bx lr 442: bx lr
45UNWIND( .fnend )
46ENDPROC(\name )
37 .endm 47 .endm
38#else 48#else
39 .macro bitop, instr 49 .macro bitop, name, instr
50ENTRY( \name )
51UNWIND( .fnstart )
40 ands ip, r1, #3 52 ands ip, r1, #3
41 strneb r1, [ip] @ assert word-aligned 53 strneb r1, [ip] @ assert word-aligned
42 and r2, r0, #31 54 and r2, r0, #31
@@ -49,6 +61,8 @@
49 str r2, [r1, r0, lsl #2] 61 str r2, [r1, r0, lsl #2]
50 restore_irqs ip 62 restore_irqs ip
51 mov pc, lr 63 mov pc, lr
64UNWIND( .fnend )
65ENDPROC(\name )
52 .endm 66 .endm
53 67
54/** 68/**
@@ -59,7 +73,9 @@
59 * Note: we can trivially conditionalise the store instruction 73 * Note: we can trivially conditionalise the store instruction
60 * to avoid dirtying the data cache. 74 * to avoid dirtying the data cache.
61 */ 75 */
62 .macro testop, instr, store 76 .macro testop, name, instr, store
77ENTRY( \name )
78UNWIND( .fnstart )
63 ands ip, r1, #3 79 ands ip, r1, #3
64 strneb r1, [ip] @ assert word-aligned 80 strneb r1, [ip] @ assert word-aligned
65 and r3, r0, #31 81 and r3, r0, #31
@@ -73,5 +89,7 @@
73 moveq r0, #0 89 moveq r0, #0
74 restore_irqs ip 90 restore_irqs ip
75 mov pc, lr 91 mov pc, lr
92UNWIND( .fnend )
93ENDPROC(\name )
76 .endm 94 .endm
77#endif 95#endif
diff --git a/arch/arm/lib/changebit.S b/arch/arm/lib/changebit.S
index 68ed5b62e839..f4027862172f 100644
--- a/arch/arm/lib/changebit.S
+++ b/arch/arm/lib/changebit.S
@@ -12,6 +12,4 @@
12#include "bitops.h" 12#include "bitops.h"
13 .text 13 .text
14 14
15ENTRY(_change_bit) 15bitop _change_bit, eor
16 bitop eor
17ENDPROC(_change_bit)
diff --git a/arch/arm/lib/clearbit.S b/arch/arm/lib/clearbit.S
index 4c04c3b51eeb..f6b75fb64d30 100644
--- a/arch/arm/lib/clearbit.S
+++ b/arch/arm/lib/clearbit.S
@@ -12,6 +12,4 @@
12#include "bitops.h" 12#include "bitops.h"
13 .text 13 .text
14 14
15ENTRY(_clear_bit) 15bitop _clear_bit, bic
16 bitop bic
17ENDPROC(_clear_bit)
diff --git a/arch/arm/lib/setbit.S b/arch/arm/lib/setbit.S
index bbee5c66a23e..618fedae4b37 100644
--- a/arch/arm/lib/setbit.S
+++ b/arch/arm/lib/setbit.S
@@ -12,6 +12,4 @@
12#include "bitops.h" 12#include "bitops.h"
13 .text 13 .text
14 14
15ENTRY(_set_bit) 15bitop _set_bit, orr
16 bitop orr
17ENDPROC(_set_bit)
diff --git a/arch/arm/lib/testchangebit.S b/arch/arm/lib/testchangebit.S
index 15a4d431f229..4becdc3a59cb 100644
--- a/arch/arm/lib/testchangebit.S
+++ b/arch/arm/lib/testchangebit.S
@@ -12,6 +12,4 @@
12#include "bitops.h" 12#include "bitops.h"
13 .text 13 .text
14 14
15ENTRY(_test_and_change_bit) 15testop _test_and_change_bit, eor, str
16 testop eor, str
17ENDPROC(_test_and_change_bit)
diff --git a/arch/arm/lib/testclearbit.S b/arch/arm/lib/testclearbit.S
index 521b66b5b95d..918841dcce7a 100644
--- a/arch/arm/lib/testclearbit.S
+++ b/arch/arm/lib/testclearbit.S
@@ -12,6 +12,4 @@
12#include "bitops.h" 12#include "bitops.h"
13 .text 13 .text
14 14
15ENTRY(_test_and_clear_bit) 15testop _test_and_clear_bit, bicne, strne
16 testop bicne, strne
17ENDPROC(_test_and_clear_bit)
diff --git a/arch/arm/lib/testsetbit.S b/arch/arm/lib/testsetbit.S
index 1c98cc2185bb..8d1b2fe9e487 100644
--- a/arch/arm/lib/testsetbit.S
+++ b/arch/arm/lib/testsetbit.S
@@ -12,6 +12,4 @@
12#include "bitops.h" 12#include "bitops.h"
13 .text 13 .text
14 14
15ENTRY(_test_and_set_bit) 15testop _test_and_set_bit, orreq, streq
16 testop orreq, streq
17ENDPROC(_test_and_set_bit)
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 8ac9e9f84790..b1e192ba8c24 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -61,7 +61,7 @@ static inline void cache_sync(void)
61{ 61{
62 void __iomem *base = l2x0_base; 62 void __iomem *base = l2x0_base;
63 63
64#ifdef CONFIG_ARM_ERRATA_753970 64#ifdef CONFIG_PL310_ERRATA_753970
65 /* write to an unmmapped register */ 65 /* write to an unmmapped register */
66 writel_relaxed(0, base + L2X0_DUMMY_REG); 66 writel_relaxed(0, base + L2X0_DUMMY_REG);
67#else 67#else
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index e4e7f6cba1ab..1aa664a1999f 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -168,7 +168,7 @@ static int __init consistent_init(void)
168 pte_t *pte; 168 pte_t *pte;
169 int i = 0; 169 int i = 0;
170 unsigned long base = consistent_base; 170 unsigned long base = consistent_base;
171 unsigned long num_ptes = (CONSISTENT_END - base) >> PGDIR_SHIFT; 171 unsigned long num_ptes = (CONSISTENT_END - base) >> PMD_SHIFT;
172 172
173 consistent_pte = kmalloc(num_ptes * sizeof(pte_t), GFP_KERNEL); 173 consistent_pte = kmalloc(num_ptes * sizeof(pte_t), GFP_KERNEL);
174 if (!consistent_pte) { 174 if (!consistent_pte) {
@@ -332,6 +332,15 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp,
332 struct page *page; 332 struct page *page;
333 void *addr; 333 void *addr;
334 334
335 /*
336 * Following is a work-around (a.k.a. hack) to prevent pages
337 * with __GFP_COMP being passed to split_page() which cannot
338 * handle them. The real problem is that this flag probably
339 * should be 0 on ARM as it is not supported on this
340 * platform; see CONFIG_HUGETLBFS.
341 */
342 gfp &= ~(__GFP_COMP);
343
335 *handle = ~0; 344 *handle = ~0;
336 size = PAGE_ALIGN(size); 345 size = PAGE_ALIGN(size);
337 346
diff --git a/arch/arm/mm/mmap.c b/arch/arm/mm/mmap.c
index 74be05f3e03a..44b628e4d6ea 100644
--- a/arch/arm/mm/mmap.c
+++ b/arch/arm/mm/mmap.c
@@ -9,8 +9,7 @@
9#include <linux/io.h> 9#include <linux/io.h>
10#include <linux/personality.h> 10#include <linux/personality.h>
11#include <linux/random.h> 11#include <linux/random.h>
12#include <asm/cputype.h> 12#include <asm/cachetype.h>
13#include <asm/system.h>
14 13
15#define COLOUR_ALIGN(addr,pgoff) \ 14#define COLOUR_ALIGN(addr,pgoff) \
16 ((((addr)+SHMLBA-1)&~(SHMLBA-1)) + \ 15 ((((addr)+SHMLBA-1)&~(SHMLBA-1)) + \
@@ -32,25 +31,15 @@ arch_get_unmapped_area(struct file *filp, unsigned long addr,
32 struct mm_struct *mm = current->mm; 31 struct mm_struct *mm = current->mm;
33 struct vm_area_struct *vma; 32 struct vm_area_struct *vma;
34 unsigned long start_addr; 33 unsigned long start_addr;
35#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) 34 int do_align = 0;
36 unsigned int cache_type; 35 int aliasing = cache_is_vipt_aliasing();
37 int do_align = 0, aliasing = 0;
38 36
39 /* 37 /*
40 * We only need to do colour alignment if either the I or D 38 * We only need to do colour alignment if either the I or D
41 * caches alias. This is indicated by bits 9 and 21 of the 39 * caches alias.
42 * cache type register.
43 */ 40 */
44 cache_type = read_cpuid_cachetype(); 41 if (aliasing)
45 if (cache_type != read_cpuid_id()) { 42 do_align = filp || (flags & MAP_SHARED);
46 aliasing = (cache_type | cache_type >> 12) & (1 << 11);
47 if (aliasing)
48 do_align = filp || flags & MAP_SHARED;
49 }
50#else
51#define do_align 0
52#define aliasing 0
53#endif
54 43
55 /* 44 /*
56 * We enforce the MAP_FIXED case. 45 * We enforce the MAP_FIXED case.
diff --git a/drivers/i2c/busses/i2c-nuc900.c b/drivers/i2c/busses/i2c-nuc900.c
index 835e47b39bc2..03b615778887 100644
--- a/drivers/i2c/busses/i2c-nuc900.c
+++ b/drivers/i2c/busses/i2c-nuc900.c
@@ -593,7 +593,7 @@ static int __devinit nuc900_i2c_probe(struct platform_device *pdev)
593 i2c->adap.algo_data = i2c; 593 i2c->adap.algo_data = i2c;
594 i2c->adap.dev.parent = &pdev->dev; 594 i2c->adap.dev.parent = &pdev->dev;
595 595
596 mfp_set_groupg(&pdev->dev); 596 mfp_set_groupg(&pdev->dev, NULL);
597 597
598 clk_get_rate(i2c->clk); 598 clk_get_rate(i2c->clk);
599 599
diff --git a/drivers/spi/spi-nuc900.c b/drivers/spi/spi-nuc900.c
index e763254741c2..21c70b2b8311 100644
--- a/drivers/spi/spi-nuc900.c
+++ b/drivers/spi/spi-nuc900.c
@@ -426,7 +426,7 @@ static int __devinit nuc900_spi_probe(struct platform_device *pdev)
426 goto err_clk; 426 goto err_clk;
427 } 427 }
428 428
429 mfp_set_groupg(&pdev->dev); 429 mfp_set_groupg(&pdev->dev, NULL);
430 nuc900_init_spi(hw); 430 nuc900_init_spi(hw);
431 431
432 err = spi_bitbang_start(&hw->bitbang); 432 err = spi_bitbang_start(&hw->bitbang);
diff --git a/sound/soc/nuc900/nuc900-ac97.c b/sound/soc/nuc900/nuc900-ac97.c
index 9c0edad90d8b..a4e3237956e2 100644
--- a/sound/soc/nuc900/nuc900-ac97.c
+++ b/sound/soc/nuc900/nuc900-ac97.c
@@ -365,7 +365,8 @@ static int __devinit nuc900_ac97_drvprobe(struct platform_device *pdev)
365 if (ret) 365 if (ret)
366 goto out3; 366 goto out3;
367 367
368 mfp_set_groupg(nuc900_audio->dev); /* enbale ac97 multifunction pin*/ 368 /* enbale ac97 multifunction pin */
369 mfp_set_groupg(nuc900_audio->dev, "nuc900-audio");
369 370
370 return 0; 371 return 0;
371 372
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 02:14:41 -0500