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-rw-r--r--Documentation/arm/SPEAr/overview.txt32
-rw-r--r--Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt52
-rw-r--r--Documentation/devicetree/bindings/arm/spear.txt14
-rw-r--r--Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt47
-rw-r--r--MAINTAINERS13
-rw-r--r--arch/arm/Makefile2
-rw-r--r--arch/arm/boot/dts/exynos5250-smdk5250.dts48
-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi60
-rw-r--r--arch/arm/boot/dts/spear1310-evb.dts292
-rw-r--r--arch/arm/boot/dts/spear1310.dtsi184
-rw-r--r--arch/arm/boot/dts/spear1340-evb.dts308
-rw-r--r--arch/arm/boot/dts/spear1340.dtsi56
-rw-r--r--arch/arm/boot/dts/spear13xx.dtsi262
-rw-r--r--arch/arm/configs/spear13xx_defconfig95
-rw-r--r--arch/arm/mach-exynos/Kconfig14
-rw-r--r--arch/arm/mach-exynos/Makefile7
-rw-r--r--arch/arm/mach-exynos/Makefile.boot3
-rw-r--r--arch/arm/mach-exynos/clock-exynos4212.c10
-rw-r--r--arch/arm/mach-exynos/clock-exynos5.c51
-rw-r--r--arch/arm/mach-exynos/common.c182
-rw-r--r--arch/arm/mach-exynos/dev-drm.c29
-rw-r--r--arch/arm/mach-exynos/dma.c141
-rw-r--r--arch/arm/mach-exynos/include/mach/gpio.h9
-rw-r--r--arch/arm/mach-exynos/include/mach/irqs.h40
-rw-r--r--arch/arm/mach-exynos/include/mach/map.h7
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-clock.h2
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-pmu.h10
-rw-r--r--arch/arm/mach-exynos/include/mach/spi-clocks.h2
-rw-r--r--arch/arm/mach-exynos/mach-exynos5-dt.c4
-rw-r--r--arch/arm/mach-exynos/mct.c17
-rw-r--r--arch/arm/mach-exynos/pm.c4
-rw-r--r--arch/arm/mach-exynos/pmu.c24
-rw-r--r--arch/arm/mach-s3c24xx/Kconfig5
-rw-r--r--arch/arm/mach-s3c24xx/Makefile1
-rw-r--r--arch/arm/mach-s3c24xx/clock-s3c2416.c1
-rw-r--r--arch/arm/mach-s3c24xx/clock-s3c2443.c6
-rw-r--r--arch/arm/mach-s3c24xx/common-s3c2443.c15
-rw-r--r--arch/arm/mach-s3c24xx/dma-s3c2443.c16
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/dma.h4
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/map.h5
-rw-r--r--arch/arm/mach-s3c24xx/setup-spi.c39
-rw-r--r--arch/arm/mach-spear13xx/Kconfig20
-rw-r--r--arch/arm/mach-spear13xx/Makefile10
-rw-r--r--arch/arm/mach-spear13xx/Makefile.boot6
-rw-r--r--arch/arm/mach-spear13xx/headsmp.S47
-rw-r--r--arch/arm/mach-spear13xx/hotplug.c119
-rw-r--r--arch/arm/mach-spear13xx/include/mach/debug-macro.S14
-rw-r--r--arch/arm/mach-spear13xx/include/mach/dma.h128
-rw-r--r--arch/arm/mach-spear13xx/include/mach/generic.h49
-rw-r--r--arch/arm/mach-spear13xx/include/mach/gpio.h19
-rw-r--r--arch/arm/mach-spear13xx/include/mach/hardware.h1
-rw-r--r--arch/arm/mach-spear13xx/include/mach/irqs.h20
-rw-r--r--arch/arm/mach-spear13xx/include/mach/spear.h62
-rw-r--r--arch/arm/mach-spear13xx/include/mach/spear1310_misc_regs.h0
-rw-r--r--arch/arm/mach-spear13xx/include/mach/spear1340_misc_regs.h0
-rw-r--r--arch/arm/mach-spear13xx/include/mach/timex.h19
-rw-r--r--arch/arm/mach-spear13xx/include/mach/uncompress.h19
-rw-r--r--arch/arm/mach-spear13xx/platsmp.c127
-rw-r--r--arch/arm/mach-spear13xx/spear1310.c88
-rw-r--r--arch/arm/mach-spear13xx/spear1340.c192
-rw-r--r--arch/arm/mach-spear13xx/spear13xx.c197
-rw-r--r--arch/arm/plat-samsung/Kconfig2
-rw-r--r--arch/arm/plat-samsung/include/plat/cpu.h2
-rw-r--r--arch/arm/plat-samsung/include/plat/devs.h2
-rw-r--r--arch/arm/plat-samsung/include/plat/dma-pl330.h1
-rw-r--r--arch/arm/plat-samsung/include/plat/s5p-clock.h4
-rw-r--r--arch/arm/plat-samsung/s5p-clock.c30
-rw-r--r--arch/arm/plat-spear/Kconfig12
-rw-r--r--arch/arm/plat-spear/Makefile5
-rw-r--r--arch/arm/plat-spear/restart.c5
-rw-r--r--drivers/clk/spear/Makefile2
-rw-r--r--drivers/clk/spear/spear1310_clock.c1106
-rw-r--r--drivers/clk/spear/spear1340_clock.c964
-rw-r--r--drivers/gpio/gpio-samsung.c11
-rw-r--r--drivers/pinctrl/spear/Kconfig10
-rw-r--r--drivers/pinctrl/spear/Makefile2
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear.h251
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear1310.c2198
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear1340.c1989
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear3xx.c103
-rw-r--r--drivers/spi/Kconfig2
81 files changed, 9648 insertions, 303 deletions
diff --git a/Documentation/arm/SPEAr/overview.txt b/Documentation/arm/SPEAr/overview.txt
index 28a9af953b9d..57aae7765c74 100644
--- a/Documentation/arm/SPEAr/overview.txt
+++ b/Documentation/arm/SPEAr/overview.txt
@@ -8,9 +8,8 @@ Introduction
8 weblink : http://www.st.com/spear 8 weblink : http://www.st.com/spear
9 9
10 The ST Microelectronics SPEAr range of ARM9/CortexA9 System-on-Chip CPUs are 10 The ST Microelectronics SPEAr range of ARM9/CortexA9 System-on-Chip CPUs are
11 supported by the 'spear' platform of ARM Linux. Currently SPEAr300, 11 supported by the 'spear' platform of ARM Linux. Currently SPEAr1310,
12 SPEAr310, SPEAr320 and SPEAr600 SOCs are supported. Support for the SPEAr13XX 12 SPEAr1340, SPEAr300, SPEAr310, SPEAr320 and SPEAr600 SOCs are supported.
13 series is in progress.
14 13
15 Hierarchy in SPEAr is as follows: 14 Hierarchy in SPEAr is as follows:
16 15
@@ -26,33 +25,36 @@ Introduction
26 - SPEAr600 (SOC) 25 - SPEAr600 (SOC)
27 - SPEAr600 Evaluation Board 26 - SPEAr600 Evaluation Board
28 - SPEAr13XX (13XX SOC series, based on ARM CORTEXA9) 27 - SPEAr13XX (13XX SOC series, based on ARM CORTEXA9)
29 - SPEAr1300 (SOC) 28 - SPEAr1310 (SOC)
29 - SPEAr1310 Evaluation Board
30 - SPEAr1340 (SOC)
31 - SPEAr1340 Evaluation Board
30 32
31 Configuration 33 Configuration
32 ------------- 34 -------------
33 35
34 A generic configuration is provided for each machine, and can be used as the 36 A generic configuration is provided for each machine, and can be used as the
35 default by 37 default by
36 make spear600_defconfig 38 make spear13xx_defconfig
37 make spear300_defconfig 39 make spear3xx_defconfig
38 make spear310_defconfig 40 make spear6xx_defconfig
39 make spear320_defconfig
40 41
41 Layout 42 Layout
42 ------ 43 ------
43 44
44 The common files for multiple machine families (SPEAr3XX, SPEAr6XX and 45 The common files for multiple machine families (SPEAr3xx, SPEAr6xx and
45 SPEAr13XX) are located in the platform code contained in arch/arm/plat-spear 46 SPEAr13xx) are located in the platform code contained in arch/arm/plat-spear
46 with headers in plat/. 47 with headers in plat/.
47 48
48 Each machine series have a directory with name arch/arm/mach-spear followed by 49 Each machine series have a directory with name arch/arm/mach-spear followed by
49 series name. Like mach-spear3xx, mach-spear6xx and mach-spear13xx. 50 series name. Like mach-spear3xx, mach-spear6xx and mach-spear13xx.
50 51
51 Common file for machines of spear3xx family is mach-spear3xx/spear3xx.c and for 52 Common file for machines of spear3xx family is mach-spear3xx/spear3xx.c, for
52 spear6xx is mach-spear6xx/spear6xx.c. mach-spear* also contain soc/machine 53 spear6xx is mach-spear6xx/spear6xx.c and for spear13xx family is
53 specific files, like spear300.c, spear310.c, spear320.c and spear600.c. 54 mach-spear13xx/spear13xx.c. mach-spear* also contain soc/machine specific
54 mach-spear* doesn't contains board specific files as they fully support 55 files, like spear1310.c, spear1340.c spear300.c, spear310.c, spear320.c and
55 Flattened Device Tree. 56 spear600.c. mach-spear* doesn't contains board specific files as they fully
57 support Flattened Device Tree.
56 58
57 59
58 Document Author 60 Document Author
diff --git a/Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt b/Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt
new file mode 100644
index 000000000000..f2f2171e530e
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt
@@ -0,0 +1,52 @@
1* Samsung Exynos Interrupt Combiner Controller
2
3Samsung's Exynos4 architecture includes a interrupt combiner controller which
4can combine interrupt sources as a group and provide a single interrupt request
5for the group. The interrupt request from each group are connected to a parent
6interrupt controller, such as GIC in case of Exynos4210.
7
8The interrupt combiner controller consists of multiple combiners. Upto eight
9interrupt sources can be connected to a combiner. The combiner outputs one
10combined interrupt for its eight interrupt sources. The combined interrupt
11is usually connected to a parent interrupt controller.
12
13A single node in the device tree is used to describe the interrupt combiner
14controller module (which includes multiple combiners). A combiner in the
15interrupt controller module shares config/control registers with other
16combiners. For example, a 32-bit interrupt enable/disable config register
17can accommodate upto 4 interrupt combiners (with each combiner supporting
18upto 8 interrupt sources).
19
20Required properties:
21- compatible: should be "samsung,exynos4210-combiner".
22- interrupt-controller: Identifies the node as an interrupt controller.
23- #interrupt-cells: should be <2>. The meaning of the cells are
24 * First Cell: Combiner Group Number.
25 * Second Cell: Interrupt number within the group.
26- reg: Base address and size of interrupt combiner registers.
27- interrupts: The list of interrupts generated by the combiners which are then
28 connected to a parent interrupt controller. The format of the interrupt
29 specifier depends in the interrupt parent controller.
30
31Optional properties:
32- samsung,combiner-nr: The number of interrupt combiners supported. If this
33 property is not specified, the default number of combiners is assumed
34 to be 16.
35- interrupt-parent: pHandle of the parent interrupt controller, if not
36 inherited from the parent node.
37
38
39Example:
40
41 The following is a an example from the Exynos4210 SoC dtsi file.
42
43 combiner:interrupt-controller@10440000 {
44 compatible = "samsung,exynos4210-combiner";
45 interrupt-controller;
46 #interrupt-cells = <2>;
47 reg = <0x10440000 0x1000>;
48 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
49 <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
50 <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
51 <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
52 };
diff --git a/Documentation/devicetree/bindings/arm/spear.txt b/Documentation/devicetree/bindings/arm/spear.txt
index aa5f355cc947..0d42949df6c2 100644
--- a/Documentation/devicetree/bindings/arm/spear.txt
+++ b/Documentation/devicetree/bindings/arm/spear.txt
@@ -2,25 +2,25 @@ ST SPEAr Platforms Device Tree Bindings
2--------------------------------------- 2---------------------------------------
3 3
4Boards with the ST SPEAr600 SoC shall have the following properties: 4Boards with the ST SPEAr600 SoC shall have the following properties:
5
6Required root node property: 5Required root node property:
7
8compatible = "st,spear600"; 6compatible = "st,spear600";
9 7
10Boards with the ST SPEAr300 SoC shall have the following properties: 8Boards with the ST SPEAr300 SoC shall have the following properties:
11
12Required root node property: 9Required root node property:
13
14compatible = "st,spear300"; 10compatible = "st,spear300";
15 11
16Boards with the ST SPEAr310 SoC shall have the following properties: 12Boards with the ST SPEAr310 SoC shall have the following properties:
17
18Required root node property: 13Required root node property:
19
20compatible = "st,spear310"; 14compatible = "st,spear310";
21 15
22Boards with the ST SPEAr320 SoC shall have the following properties: 16Boards with the ST SPEAr320 SoC shall have the following properties:
17Required root node property:
18compatible = "st,spear320";
23 19
20Boards with the ST SPEAr1310 SoC shall have the following properties:
24Required root node property: 21Required root node property:
22compatible = "st,spear1310";
25 23
26compatible = "st,spear320"; 24Boards with the ST SPEAr1340 SoC shall have the following properties:
25Required root node property:
26compatible = "st,spear1340";
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt
index 3664d37e6799..b4480d5c3aca 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt
@@ -4,6 +4,8 @@ Required properties:
4- compatible : "st,spear300-pinmux" 4- compatible : "st,spear300-pinmux"
5 : "st,spear310-pinmux" 5 : "st,spear310-pinmux"
6 : "st,spear320-pinmux" 6 : "st,spear320-pinmux"
7 : "st,spear1310-pinmux"
8 : "st,spear1340-pinmux"
7- reg : Address range of the pinctrl registers 9- reg : Address range of the pinctrl registers
8- st,pinmux-mode: Mandatory for SPEAr300 and SPEAr320 and invalid for others. 10- st,pinmux-mode: Mandatory for SPEAr300 and SPEAr320 and invalid for others.
9 - Its values for SPEAr300: 11 - Its values for SPEAr300:
@@ -89,6 +91,37 @@ For SPEAr320 machines:
89 "rmii0_1_grp", "i2c1_8_9_grp", "i2c1_98_99_grp", "i2c2_0_1_grp", 91 "rmii0_1_grp", "i2c1_8_9_grp", "i2c1_98_99_grp", "i2c2_0_1_grp",
90 "i2c2_2_3_grp", "i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp" 92 "i2c2_2_3_grp", "i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp"
91 93
94For SPEAr1310 machines:
95 "i2c0_grp", "ssp0_grp", "ssp0_cs0_grp", "ssp0_cs1_2_grp", "i2s0_grp",
96 "i2s1_grp", "clcd_grp", "clcd_high_res_grp", "arm_gpio_grp",
97 "smi_2_chips_grp", "smi_4_chips_grp", "gmii_grp", "rgmii_grp",
98 "smii_0_1_2_grp", "ras_mii_txclk_grp", "nand_8bit_grp",
99 "nand_16bit_grp", "nand_4_chips_grp", "keyboard_6x6_grp",
100 "keyboard_rowcol6_8_grp", "uart0_grp", "uart0_modem_grp",
101 "gpt0_tmr0_grp", "gpt0_tmr1_grp", "gpt1_tmr0_grp", "gpt1_tmr1_grp",
102 "sdhci_grp", "cf_grp", "xd_grp", "touch_xy_grp",
103 "uart1_disable_i2c_grp", "uart1_disable_sd_grp", "uart2_3_grp",
104 "uart4_grp", "uart5_grp", "rs485_0_1_tdm_0_1_grp", "i2c_1_2_grp",
105 "i2c3_dis_smi_clcd_grp", "i2c3_dis_sd_i2s0_grp", "i2c_4_5_dis_smi_grp",
106 "i2c4_dis_sd_grp", "i2c5_dis_sd_grp", "i2c_6_7_dis_kbd_grp",
107 "i2c6_dis_sd_grp", "i2c7_dis_sd_grp", "can0_dis_nor_grp",
108 "can0_dis_sd_grp", "can1_dis_sd_grp", "can1_dis_kbd_grp", "pcie0_grp",
109 "pcie1_grp", "pcie2_grp", "sata0_grp", "sata1_grp", "sata2_grp",
110 "ssp1_dis_kbd_grp", "ssp1_dis_sd_grp", "gpt64_grp"
111
112For SPEAr1340 machines:
113 "pads_as_gpio_grp", "fsmc_8bit_grp", "fsmc_16bit_grp", "fsmc_pnor_grp",
114 "keyboard_row_col_grp", "keyboard_col5_grp", "spdif_in_grp",
115 "spdif_out_grp", "gpt_0_1_grp", "pwm0_grp", "pwm1_grp", "pwm2_grp",
116 "pwm3_grp", "vip_mux_grp", "vip_mux_cam0_grp", "vip_mux_cam1_grp",
117 "vip_mux_cam2_grp", "vip_mux_cam3_grp", "cam0_grp", "cam1_grp",
118 "cam2_grp", "cam3_grp", "smi_grp", "ssp0_grp", "ssp0_cs1_grp",
119 "ssp0_cs2_grp", "ssp0_cs3_grp", "uart0_grp", "uart0_enh_grp",
120 "uart1_grp", "i2s_in_grp", "i2s_out_grp", "gmii_grp", "rgmii_grp",
121 "rmii_grp", "sgmii_grp", "i2c0_grp", "i2c1_grp", "cec0_grp", "cec1_grp",
122 "sdhci_grp", "cf_grp", "xd_grp", "clcd_grp", "arm_trace_grp",
123 "miphy_dbg_grp", "pcie_grp", "sata_grp"
124
92Valid values for function names are: 125Valid values for function names are:
93For All SPEAr3xx machines: 126For All SPEAr3xx machines:
94 "firda", "i2c0", "ssp_cs", "ssp0", "mii0", "gpio0", "uart0_ext", 127 "firda", "i2c0", "ssp_cs", "ssp0", "mii0", "gpio0", "uart0_ext",
@@ -106,3 +139,17 @@ For SPEAr320 machines:
106 "uart2", "uart3", "uart4", "uart5", "uart6", "rs485", "touchscreen", 139 "uart2", "uart3", "uart4", "uart5", "uart6", "rs485", "touchscreen",
107 "can0", "can1", "pwm0_1", "pwm2", "pwm3", "ssp1", "ssp2", "mii2", 140 "can0", "can1", "pwm0_1", "pwm2", "pwm3", "ssp1", "ssp2", "mii2",
108 "mii0_1", "i2c1", "i2c2" 141 "mii0_1", "i2c1", "i2c2"
142
143
144For SPEAr1310 machines:
145 "i2c0", "ssp0", "i2s0", "i2s1", "clcd", "arm_gpio", "smi", "gmii",
146 "rgmii", "smii_0_1_2", "ras_mii_txclk", "nand", "keyboard", "uart0",
147 "gpt0", "gpt1", "sdhci", "cf", "xd", "touchscreen", "uart1", "uart2_3",
148 "uart4", "uart5", "rs485_0_1_tdm_0_1", "i2c_1_2", "i2c3_i2s1",
149 "i2c_4_5", "i2c_6_7", "can0", "can1", "pci", "sata", "ssp1", "gpt64"
150
151For SPEAr1340 machines:
152 "pads_as_gpio", "fsmc", "keyboard", "spdif_in", "spdif_out", "gpt_0_1",
153 "pwm", "vip", "cam0", "cam1", "cam2", "cam3", "smi", "ssp0", "uart0",
154 "uart1", "i2s", "gmac", "i2c0", "i2c1", "cec0", "cec1", "sdhci", "cf",
155 "xd", "clcd", "arm_trace", "miphy_dbg", "pcie", "sata"
diff --git a/MAINTAINERS b/MAINTAINERS
index 64ec55559d73..daa31999b2a1 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6350,14 +6350,25 @@ F: include/linux/compiler.h
6350 6350
6351SPEAR PLATFORM SUPPORT 6351SPEAR PLATFORM SUPPORT
6352M: Viresh Kumar <viresh.kumar@st.com> 6352M: Viresh Kumar <viresh.kumar@st.com>
6353M: Shiraz Hashim <shiraz.hashim@st.com>
6353L: spear-devel@list.st.com 6354L: spear-devel@list.st.com
6354L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 6355L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
6355W: http://www.st.com/spear 6356W: http://www.st.com/spear
6356S: Maintained 6357S: Maintained
6357F: arch/arm/plat-spear/ 6358F: arch/arm/plat-spear/
6358 6359
6360SPEAR13XX MACHINE SUPPORT
6361M: Viresh Kumar <viresh.kumar@st.com>
6362M: Shiraz Hashim <shiraz.hashim@st.com>
6363L: spear-devel@list.st.com
6364L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
6365W: http://www.st.com/spear
6366S: Maintained
6367F: arch/arm/mach-spear13xx/
6368
6359SPEAR3XX MACHINE SUPPORT 6369SPEAR3XX MACHINE SUPPORT
6360M: Viresh Kumar <viresh.kumar@st.com> 6370M: Viresh Kumar <viresh.kumar@st.com>
6371M: Shiraz Hashim <shiraz.hashim@st.com>
6361L: spear-devel@list.st.com 6372L: spear-devel@list.st.com
6362L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 6373L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
6363W: http://www.st.com/spear 6374W: http://www.st.com/spear
@@ -6366,6 +6377,8 @@ F: arch/arm/mach-spear3xx/
6366 6377
6367SPEAR6XX MACHINE SUPPORT 6378SPEAR6XX MACHINE SUPPORT
6368M: Rajeev Kumar <rajeev-dlh.kumar@st.com> 6379M: Rajeev Kumar <rajeev-dlh.kumar@st.com>
6380M: Shiraz Hashim <shiraz.hashim@st.com>
6381M: Viresh Kumar <viresh.kumar@st.com>
6369L: spear-devel@list.st.com 6382L: spear-devel@list.st.com
6370L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 6383L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
6371W: http://www.st.com/spear 6384W: http://www.st.com/spear
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 18194acab493..0298b00fe241 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -186,6 +186,8 @@ machine-$(CONFIG_ARCH_VEXPRESS) := vexpress
186machine-$(CONFIG_ARCH_VT8500) := vt8500 186machine-$(CONFIG_ARCH_VT8500) := vt8500
187machine-$(CONFIG_ARCH_W90X900) := w90x900 187machine-$(CONFIG_ARCH_W90X900) := w90x900
188machine-$(CONFIG_FOOTBRIDGE) := footbridge 188machine-$(CONFIG_FOOTBRIDGE) := footbridge
189machine-$(CONFIG_MACH_SPEAR1310) := spear13xx
190machine-$(CONFIG_MACH_SPEAR1340) := spear13xx
189machine-$(CONFIG_MACH_SPEAR300) := spear3xx 191machine-$(CONFIG_MACH_SPEAR300) := spear3xx
190machine-$(CONFIG_MACH_SPEAR310) := spear3xx 192machine-$(CONFIG_MACH_SPEAR310) := spear3xx
191machine-$(CONFIG_MACH_SPEAR320) := spear3xx 193machine-$(CONFIG_MACH_SPEAR320) := spear3xx
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 399d17b231d2..49945cc1bc7d 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -23,4 +23,52 @@
23 chosen { 23 chosen {
24 bootargs = "root=/dev/ram0 rw ramdisk=8192 console=ttySAC1,115200"; 24 bootargs = "root=/dev/ram0 rw ramdisk=8192 console=ttySAC1,115200";
25 }; 25 };
26
27 i2c@12C60000 {
28 samsung,i2c-sda-delay = <100>;
29 samsung,i2c-max-bus-freq = <20000>;
30 gpios = <&gpb3 0 2 3 0>,
31 <&gpb3 1 2 3 0>;
32
33 eeprom@50 {
34 compatible = "samsung,s524ad0xd1";
35 reg = <0x50>;
36 };
37 };
38
39 i2c@12C70000 {
40 samsung,i2c-sda-delay = <100>;
41 samsung,i2c-max-bus-freq = <20000>;
42 gpios = <&gpb3 2 2 3 0>,
43 <&gpb3 3 2 3 0>;
44
45 eeprom@51 {
46 compatible = "samsung,s524ad0xd1";
47 reg = <0x51>;
48 };
49 };
50
51 i2c@12C80000 {
52 status = "disabled";
53 };
54
55 i2c@12C90000 {
56 status = "disabled";
57 };
58
59 i2c@12CA0000 {
60 status = "disabled";
61 };
62
63 i2c@12CB0000 {
64 status = "disabled";
65 };
66
67 i2c@12CC0000 {
68 status = "disabled";
69 };
70
71 i2c@12CD0000 {
72 status = "disabled";
73 };
26}; 74};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index dfc433599436..5ca0cdb76413 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -23,11 +23,11 @@
23 compatible = "samsung,exynos5250"; 23 compatible = "samsung,exynos5250";
24 interrupt-parent = <&gic>; 24 interrupt-parent = <&gic>;
25 25
26 gic:interrupt-controller@10490000 { 26 gic:interrupt-controller@10481000 {
27 compatible = "arm,cortex-a9-gic"; 27 compatible = "arm,cortex-a9-gic";
28 #interrupt-cells = <3>; 28 #interrupt-cells = <3>;
29 interrupt-controller; 29 interrupt-controller;
30 reg = <0x10490000 0x1000>, <0x10480000 0x100>; 30 reg = <0x10481000 0x1000>, <0x10482000 0x2000>;
31 }; 31 };
32 32
33 watchdog { 33 watchdog {
@@ -42,30 +42,6 @@
42 interrupts = <0 43 0>, <0 44 0>; 42 interrupts = <0 43 0>, <0 44 0>;
43 }; 43 };
44 44
45 sdhci@12200000 {
46 compatible = "samsung,exynos4210-sdhci";
47 reg = <0x12200000 0x100>;
48 interrupts = <0 75 0>;
49 };
50
51 sdhci@12210000 {
52 compatible = "samsung,exynos4210-sdhci";
53 reg = <0x12210000 0x100>;
54 interrupts = <0 76 0>;
55 };
56
57 sdhci@12220000 {
58 compatible = "samsung,exynos4210-sdhci";
59 reg = <0x12220000 0x100>;
60 interrupts = <0 77 0>;
61 };
62
63 sdhci@12230000 {
64 compatible = "samsung,exynos4210-sdhci";
65 reg = <0x12230000 0x100>;
66 interrupts = <0 78 0>;
67 };
68
69 serial@12C00000 { 45 serial@12C00000 {
70 compatible = "samsung,exynos4210-uart"; 46 compatible = "samsung,exynos4210-uart";
71 reg = <0x12C00000 0x100>; 47 reg = <0x12C00000 0x100>;
@@ -94,48 +70,64 @@
94 compatible = "samsung,s3c2440-i2c"; 70 compatible = "samsung,s3c2440-i2c";
95 reg = <0x12C60000 0x100>; 71 reg = <0x12C60000 0x100>;
96 interrupts = <0 56 0>; 72 interrupts = <0 56 0>;
73 #address-cells = <1>;
74 #size-cells = <0>;
97 }; 75 };
98 76
99 i2c@12C70000 { 77 i2c@12C70000 {
100 compatible = "samsung,s3c2440-i2c"; 78 compatible = "samsung,s3c2440-i2c";
101 reg = <0x12C70000 0x100>; 79 reg = <0x12C70000 0x100>;
102 interrupts = <0 57 0>; 80 interrupts = <0 57 0>;
81 #address-cells = <1>;
82 #size-cells = <0>;
103 }; 83 };
104 84
105 i2c@12C80000 { 85 i2c@12C80000 {
106 compatible = "samsung,s3c2440-i2c"; 86 compatible = "samsung,s3c2440-i2c";
107 reg = <0x12C80000 0x100>; 87 reg = <0x12C80000 0x100>;
108 interrupts = <0 58 0>; 88 interrupts = <0 58 0>;
89 #address-cells = <1>;
90 #size-cells = <0>;
109 }; 91 };
110 92
111 i2c@12C90000 { 93 i2c@12C90000 {
112 compatible = "samsung,s3c2440-i2c"; 94 compatible = "samsung,s3c2440-i2c";
113 reg = <0x12C90000 0x100>; 95 reg = <0x12C90000 0x100>;
114 interrupts = <0 59 0>; 96 interrupts = <0 59 0>;
97 #address-cells = <1>;
98 #size-cells = <0>;
115 }; 99 };
116 100
117 i2c@12CA0000 { 101 i2c@12CA0000 {
118 compatible = "samsung,s3c2440-i2c"; 102 compatible = "samsung,s3c2440-i2c";
119 reg = <0x12CA0000 0x100>; 103 reg = <0x12CA0000 0x100>;
120 interrupts = <0 60 0>; 104 interrupts = <0 60 0>;
105 #address-cells = <1>;
106 #size-cells = <0>;
121 }; 107 };
122 108
123 i2c@12CB0000 { 109 i2c@12CB0000 {
124 compatible = "samsung,s3c2440-i2c"; 110 compatible = "samsung,s3c2440-i2c";
125 reg = <0x12CB0000 0x100>; 111 reg = <0x12CB0000 0x100>;
126 interrupts = <0 61 0>; 112 interrupts = <0 61 0>;
113 #address-cells = <1>;
114 #size-cells = <0>;
127 }; 115 };
128 116
129 i2c@12CC0000 { 117 i2c@12CC0000 {
130 compatible = "samsung,s3c2440-i2c"; 118 compatible = "samsung,s3c2440-i2c";
131 reg = <0x12CC0000 0x100>; 119 reg = <0x12CC0000 0x100>;
132 interrupts = <0 62 0>; 120 interrupts = <0 62 0>;
121 #address-cells = <1>;
122 #size-cells = <0>;
133 }; 123 };
134 124
135 i2c@12CD0000 { 125 i2c@12CD0000 {
136 compatible = "samsung,s3c2440-i2c"; 126 compatible = "samsung,s3c2440-i2c";
137 reg = <0x12CD0000 0x100>; 127 reg = <0x12CD0000 0x100>;
138 interrupts = <0 63 0>; 128 interrupts = <0 63 0>;
129 #address-cells = <1>;
130 #size-cells = <0>;
139 }; 131 };
140 132
141 amba { 133 amba {
@@ -157,13 +149,13 @@
157 interrupts = <0 35 0>; 149 interrupts = <0 35 0>;
158 }; 150 };
159 151
160 mdma0: pdma@10800000 { 152 mdma0: mdma@10800000 {
161 compatible = "arm,pl330", "arm,primecell"; 153 compatible = "arm,pl330", "arm,primecell";
162 reg = <0x10800000 0x1000>; 154 reg = <0x10800000 0x1000>;
163 interrupts = <0 33 0>; 155 interrupts = <0 33 0>;
164 }; 156 };
165 157
166 mdma1: pdma@11C10000 { 158 mdma1: mdma@11C10000 {
167 compatible = "arm,pl330", "arm,primecell"; 159 compatible = "arm,pl330", "arm,primecell";
168 reg = <0x11C10000 0x1000>; 160 reg = <0x11C10000 0x1000>;
169 interrupts = <0 124 0>; 161 interrupts = <0 124 0>;
@@ -242,6 +234,12 @@
242 #gpio-cells = <4>; 234 #gpio-cells = <4>;
243 }; 235 };
244 236
237 gpc4: gpio-controller@114002E0 {
238 compatible = "samsung,exynos4-gpio";
239 reg = <0x114002E0 0x20>;
240 #gpio-cells = <4>;
241 };
242
245 gpd0: gpio-controller@11400160 { 243 gpd0: gpio-controller@11400160 {
246 compatible = "samsung,exynos4-gpio"; 244 compatible = "samsung,exynos4-gpio";
247 reg = <0x11400160 0x20>; 245 reg = <0x11400160 0x20>;
@@ -388,19 +386,19 @@
388 386
389 gpv2: gpio-controller@10D10040 { 387 gpv2: gpio-controller@10D10040 {
390 compatible = "samsung,exynos4-gpio"; 388 compatible = "samsung,exynos4-gpio";
391 reg = <0x10D10040 0x20>; 389 reg = <0x10D10060 0x20>;
392 #gpio-cells = <4>; 390 #gpio-cells = <4>;
393 }; 391 };
394 392
395 gpv3: gpio-controller@10D10060 { 393 gpv3: gpio-controller@10D10060 {
396 compatible = "samsung,exynos4-gpio"; 394 compatible = "samsung,exynos4-gpio";
397 reg = <0x10D10060 0x20>; 395 reg = <0x10D10080 0x20>;
398 #gpio-cells = <4>; 396 #gpio-cells = <4>;
399 }; 397 };
400 398
401 gpv4: gpio-controller@10D10080 { 399 gpv4: gpio-controller@10D10080 {
402 compatible = "samsung,exynos4-gpio"; 400 compatible = "samsung,exynos4-gpio";
403 reg = <0x10D10080 0x20>; 401 reg = <0x10D100C0 0x20>;
404 #gpio-cells = <4>; 402 #gpio-cells = <4>;
405 }; 403 };
406 404
diff --git a/arch/arm/boot/dts/spear1310-evb.dts b/arch/arm/boot/dts/spear1310-evb.dts
new file mode 100644
index 000000000000..8314e4171884
--- /dev/null
+++ b/arch/arm/boot/dts/spear1310-evb.dts
@@ -0,0 +1,292 @@
1/*
2 * DTS file for SPEAr1310 Evaluation Baord
3 *
4 * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15/include/ "spear1310.dtsi"
16
17/ {
18 model = "ST SPEAr1310 Evaluation Board";
19 compatible = "st,spear1310-evb", "st,spear1310";
20 #address-cells = <1>;
21 #size-cells = <1>;
22
23 memory {
24 reg = <0 0x40000000>;
25 };
26
27 ahb {
28 pinmux@e0700000 {
29 pinctrl-names = "default";
30 pinctrl-0 = <&state_default>;
31
32 state_default: pinmux {
33 i2c0-pmx {
34 st,pins = "i2c0_grp";
35 st,function = "i2c0";
36 };
37 i2s1 {
38 st,pins = "i2s1_grp";
39 st,function = "i2s1";
40 };
41 gpio {
42 st,pins = "arm_gpio_grp";
43 st,function = "arm_gpio";
44 };
45 eth {
46 st,pins = "gmii_grp";
47 st,function = "gmii";
48 };
49 ssp0 {
50 st,pins = "ssp0_grp";
51 st,function = "ssp0";
52 };
53 kbd {
54 st,pins = "keyboard_6x6_grp";
55 st,function = "keyboard";
56 };
57 sdhci {
58 st,pins = "sdhci_grp";
59 st,function = "sdhci";
60 };
61 smi-pmx {
62 st,pins = "smi_2_chips_grp";
63 st,function = "smi";
64 };
65 uart0 {
66 st,pins = "uart0_grp";
67 st,function = "uart0";
68 };
69 rs485 {
70 st,pins = "rs485_0_1_tdm_0_1_grp";
71 st,function = "rs485_0_1_tdm_0_1";
72 };
73 i2c1_2 {
74 st,pins = "i2c_1_2_grp";
75 st,function = "i2c_1_2";
76 };
77 pci {
78 st,pins = "pcie0_grp","pcie1_grp",
79 "pcie2_grp";
80 st,function = "pci";
81 };
82 smii {
83 st,pins = "smii_0_1_2_grp";
84 st,function = "smii_0_1_2";
85 };
86 nand {
87 st,pins = "nand_8bit_grp",
88 "nand_16bit_grp";
89 st,function = "nand";
90 };
91 };
92 };
93
94 ahci@b1000000 {
95 status = "okay";
96 };
97
98 cf@b2800000 {
99 status = "okay";
100 };
101
102 dma@ea800000 {
103 status = "okay";
104 };
105
106 dma@eb000000 {
107 status = "okay";
108 };
109
110 fsmc: flash@b0000000 {
111 status = "okay";
112 };
113
114 gmac0: eth@e2000000 {
115 status = "okay";
116 };
117
118 sdhci@b3000000 {
119 status = "okay";
120 };
121
122 smi: flash@ea000000 {
123 status = "okay";
124 clock-rate=<50000000>;
125
126 flash@e6000000 {
127 #address-cells = <1>;
128 #size-cells = <1>;
129 reg = <0xe6000000 0x800000>;
130 st,smi-fast-mode;
131
132 partition@0 {
133 label = "xloader";
134 reg = <0x0 0x10000>;
135 };
136 partition@10000 {
137 label = "u-boot";
138 reg = <0x10000 0x40000>;
139 };
140 partition@50000 {
141 label = "linux";
142 reg = <0x50000 0x2c0000>;
143 };
144 partition@310000 {
145 label = "rootfs";
146 reg = <0x310000 0x4f0000>;
147 };
148 };
149 };
150
151 spi0: spi@e0100000 {
152 status = "okay";
153 };
154
155 ehci@e4800000 {
156 status = "okay";
157 };
158
159 ehci@e5800000 {
160 status = "okay";
161 };
162
163 ohci@e4000000 {
164 status = "okay";
165 };
166
167 ohci@e5000000 {
168 status = "okay";
169 };
170
171 apb {
172 adc@e0080000 {
173 status = "okay";
174 };
175
176 gpio0: gpio@e0600000 {
177 status = "okay";
178 };
179
180 gpio1: gpio@e0680000 {
181 status = "okay";
182 };
183
184 i2c0: i2c@e0280000 {
185 status = "okay";
186 };
187
188 i2c1: i2c@5cd00000 {
189 status = "okay";
190 };
191
192 kbd@e0300000 {
193 linux,keymap = < 0x00000001
194 0x00010002
195 0x00020003
196 0x00030004
197 0x00040005
198 0x00050006
199 0x00060007
200 0x00070008
201 0x00080009
202 0x0100000a
203 0x0101000c
204 0x0102000d
205 0x0103000e
206 0x0104000f
207 0x01050010
208 0x01060011
209 0x01070012
210 0x01080013
211 0x02000014
212 0x02010015
213 0x02020016
214 0x02030017
215 0x02040018
216 0x02050019
217 0x0206001a
218 0x0207001b
219 0x0208001c
220 0x0300001d
221 0x0301001e
222 0x0302001f
223 0x03030020
224 0x03040021
225 0x03050022
226 0x03060023
227 0x03070024
228 0x03080025
229 0x04000026
230 0x04010027
231 0x04020028
232 0x04030029
233 0x0404002a
234 0x0405002b
235 0x0406002c
236 0x0407002d
237 0x0408002e
238 0x0500002f
239 0x05010030
240 0x05020031
241 0x05030032
242 0x05040033
243 0x05050034
244 0x05060035
245 0x05070036
246 0x05080037
247 0x06000038
248 0x06010039
249 0x0602003a
250 0x0603003b
251 0x0604003c
252 0x0605003d
253 0x0606003e
254 0x0607003f
255 0x06080040
256 0x07000041
257 0x07010042
258 0x07020043
259 0x07030044
260 0x07040045
261 0x07050046
262 0x07060047
263 0x07070048
264 0x07080049
265 0x0800004a
266 0x0801004b
267 0x0802004c
268 0x0803004d
269 0x0804004e
270 0x0805004f
271 0x08060050
272 0x08070051
273 0x08080052 >;
274 autorepeat;
275 st,mode = <0>;
276 status = "okay";
277 };
278
279 rtc@e0580000 {
280 status = "okay";
281 };
282
283 serial@e0000000 {
284 status = "okay";
285 };
286
287 wdt@ec800620 {
288 status = "okay";
289 };
290 };
291 };
292};
diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi
new file mode 100644
index 000000000000..9e61da404d57
--- /dev/null
+++ b/arch/arm/boot/dts/spear1310.dtsi
@@ -0,0 +1,184 @@
1/*
2 * DTS file for all SPEAr1310 SoCs
3 *
4 * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "spear13xx.dtsi"
15
16/ {
17 compatible = "st,spear1310";
18
19 ahb {
20 ahci@b1000000 {
21 compatible = "snps,spear-ahci";
22 reg = <0xb1000000 0x10000>;
23 interrupts = <0 68 0x4>;
24 status = "disabled";
25 };
26
27 ahci@b1800000 {
28 compatible = "snps,spear-ahci";
29 reg = <0xb1800000 0x10000>;
30 interrupts = <0 69 0x4>;
31 status = "disabled";
32 };
33
34 ahci@b4000000 {
35 compatible = "snps,spear-ahci";
36 reg = <0xb4000000 0x10000>;
37 interrupts = <0 70 0x4>;
38 status = "disabled";
39 };
40
41 gmac1: eth@5c400000 {
42 compatible = "st,spear600-gmac";
43 reg = <0x5c400000 0x8000>;
44 interrupts = <0 95 0x4>;
45 interrupt-names = "macirq";
46 status = "disabled";
47 };
48
49 gmac2: eth@5c500000 {
50 compatible = "st,spear600-gmac";
51 reg = <0x5c500000 0x8000>;
52 interrupts = <0 96 0x4>;
53 interrupt-names = "macirq";
54 status = "disabled";
55 };
56
57 gmac3: eth@5c600000 {
58 compatible = "st,spear600-gmac";
59 reg = <0x5c600000 0x8000>;
60 interrupts = <0 97 0x4>;
61 interrupt-names = "macirq";
62 status = "disabled";
63 };
64
65 gmac4: eth@5c700000 {
66 compatible = "st,spear600-gmac";
67 reg = <0x5c700000 0x8000>;
68 interrupts = <0 98 0x4>;
69 interrupt-names = "macirq";
70 status = "disabled";
71 };
72
73 spi1: spi@5d400000 {
74 compatible = "arm,pl022", "arm,primecell";
75 reg = <0x5d400000 0x1000>;
76 interrupts = <0 99 0x4>;
77 status = "disabled";
78 };
79
80 apb {
81 i2c1: i2c@5cd00000 {
82 #address-cells = <1>;
83 #size-cells = <0>;
84 compatible = "snps,designware-i2c";
85 reg = <0x5cd00000 0x1000>;
86 interrupts = <0 87 0x4>;
87 status = "disabled";
88 };
89
90 i2c2: i2c@5ce00000 {
91 #address-cells = <1>;
92 #size-cells = <0>;
93 compatible = "snps,designware-i2c";
94 reg = <0x5ce00000 0x1000>;
95 interrupts = <0 88 0x4>;
96 status = "disabled";
97 };
98
99 i2c3: i2c@5cf00000 {
100 #address-cells = <1>;
101 #size-cells = <0>;
102 compatible = "snps,designware-i2c";
103 reg = <0x5cf00000 0x1000>;
104 interrupts = <0 89 0x4>;
105 status = "disabled";
106 };
107
108 i2c4: i2c@5d000000 {
109 #address-cells = <1>;
110 #size-cells = <0>;
111 compatible = "snps,designware-i2c";
112 reg = <0x5d000000 0x1000>;
113 interrupts = <0 90 0x4>;
114 status = "disabled";
115 };
116
117 i2c5: i2c@5d100000 {
118 #address-cells = <1>;
119 #size-cells = <0>;
120 compatible = "snps,designware-i2c";
121 reg = <0x5d100000 0x1000>;
122 interrupts = <0 91 0x4>;
123 status = "disabled";
124 };
125
126 i2c6: i2c@5d200000 {
127 #address-cells = <1>;
128 #size-cells = <0>;
129 compatible = "snps,designware-i2c";
130 reg = <0x5d200000 0x1000>;
131 interrupts = <0 92 0x4>;
132 status = "disabled";
133 };
134
135 i2c7: i2c@5d300000 {
136 #address-cells = <1>;
137 #size-cells = <0>;
138 compatible = "snps,designware-i2c";
139 reg = <0x5d300000 0x1000>;
140 interrupts = <0 93 0x4>;
141 status = "disabled";
142 };
143
144 serial@5c800000 {
145 compatible = "arm,pl011", "arm,primecell";
146 reg = <0x5c800000 0x1000>;
147 interrupts = <0 82 0x4>;
148 status = "disabled";
149 };
150
151 serial@5c900000 {
152 compatible = "arm,pl011", "arm,primecell";
153 reg = <0x5c900000 0x1000>;
154 interrupts = <0 83 0x4>;
155 status = "disabled";
156 };
157
158 serial@5ca00000 {
159 compatible = "arm,pl011", "arm,primecell";
160 reg = <0x5ca00000 0x1000>;
161 interrupts = <0 84 0x4>;
162 status = "disabled";
163 };
164
165 serial@5cb00000 {
166 compatible = "arm,pl011", "arm,primecell";
167 reg = <0x5cb00000 0x1000>;
168 interrupts = <0 85 0x4>;
169 status = "disabled";
170 };
171
172 serial@5cc00000 {
173 compatible = "arm,pl011", "arm,primecell";
174 reg = <0x5cc00000 0x1000>;
175 interrupts = <0 86 0x4>;
176 status = "disabled";
177 };
178
179 thermal@e07008c4 {
180 st,thermal-flags = <0x7000>;
181 };
182 };
183 };
184};
diff --git a/arch/arm/boot/dts/spear1340-evb.dts b/arch/arm/boot/dts/spear1340-evb.dts
new file mode 100644
index 000000000000..0d8472e5ab9f
--- /dev/null
+++ b/arch/arm/boot/dts/spear1340-evb.dts
@@ -0,0 +1,308 @@
1/*
2 * DTS file for SPEAr1340 Evaluation Baord
3 *
4 * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15/include/ "spear1340.dtsi"
16
17/ {
18 model = "ST SPEAr1340 Evaluation Board";
19 compatible = "st,spear1340-evb", "st,spear1340";
20 #address-cells = <1>;
21 #size-cells = <1>;
22
23 memory {
24 reg = <0 0x40000000>;
25 };
26
27 ahb {
28 pinmux@e0700000 {
29 pinctrl-names = "default";
30 pinctrl-0 = <&state_default>;
31
32 state_default: pinmux {
33 pads_as_gpio {
34 st,pins = "pads_as_gpio_grp";
35 st,function = "pads_as_gpio";
36 };
37 fsmc {
38 st,pins = "fsmc_8bit_grp";
39 st,function = "fsmc";
40 };
41 kbd {
42 st,pins = "keyboard_row_col_grp",
43 "keyboard_col5_grp";
44 st,function = "keyboard";
45 };
46 uart0 {
47 st,pins = "uart0_grp", "uart0_enh_grp";
48 st,function = "uart0";
49 };
50 i2c0-pmx {
51 st,pins = "i2c0_grp";
52 st,function = "i2c0";
53 };
54 i2c1-pmx {
55 st,pins = "i2c1_grp";
56 st,function = "i2c1";
57 };
58 spdif-in {
59 st,pins = "spdif_in_grp";
60 st,function = "spdif_in";
61 };
62 spdif-out {
63 st,pins = "spdif_out_grp";
64 st,function = "spdif_out";
65 };
66 ssp0 {
67 st,pins = "ssp0_grp", "ssp0_cs1_grp",
68 "ssp0_cs3_grp";
69 st,function = "ssp0";
70 };
71 pwm {
72 st,pins = "pwm2_grp", "pwm3_grp";
73 st,function = "pwm";
74 };
75 smi-pmx {
76 st,pins = "smi_grp";
77 st,function = "smi";
78 };
79 i2s {
80 st,pins = "i2s_in_grp", "i2s_out_grp";
81 st,function = "i2s";
82 };
83 gmac {
84 st,pins = "gmii_grp", "rgmii_grp";
85 st,function = "gmac";
86 };
87 cam3 {
88 st,pins = "cam3_grp";
89 st,function = "cam3";
90 };
91 cec0 {
92 st,pins = "cec0_grp";
93 st,function = "cec0";
94 };
95 cec1 {
96 st,pins = "cec1_grp";
97 st,function = "cec1";
98 };
99 sdhci {
100 st,pins = "sdhci_grp";
101 st,function = "sdhci";
102 };
103 clcd {
104 st,pins = "clcd_grp";
105 st,function = "clcd";
106 };
107 sata {
108 st,pins = "sata_grp";
109 st,function = "sata";
110 };
111 };
112 };
113
114 dma@ea800000 {
115 status = "okay";
116 };
117
118 dma@eb000000 {
119 status = "okay";
120 };
121
122 fsmc: flash@b0000000 {
123 status = "okay";
124 };
125
126 gmac0: eth@e2000000 {
127 status = "okay";
128 };
129
130 sdhci@b3000000 {
131 status = "okay";
132 };
133
134 smi: flash@ea000000 {
135 status = "okay";
136 clock-rate=<50000000>;
137
138 flash@e6000000 {
139 #address-cells = <1>;
140 #size-cells = <1>;
141 reg = <0xe6000000 0x800000>;
142 st,smi-fast-mode;
143
144 partition@0 {
145 label = "xloader";
146 reg = <0x0 0x10000>;
147 };
148 partition@10000 {
149 label = "u-boot";
150 reg = <0x10000 0x40000>;
151 };
152 partition@50000 {
153 label = "linux";
154 reg = <0x50000 0x2c0000>;
155 };
156 partition@310000 {
157 label = "rootfs";
158 reg = <0x310000 0x4f0000>;
159 };
160 };
161 };
162
163 spi0: spi@e0100000 {
164 status = "okay";
165 };
166
167 ehci@e4800000 {
168 status = "okay";
169 };
170
171 ehci@e5800000 {
172 status = "okay";
173 };
174
175 ohci@e4000000 {
176 status = "okay";
177 };
178
179 ohci@e5000000 {
180 status = "okay";
181 };
182
183 apb {
184 adc@e0080000 {
185 status = "okay";
186 };
187
188 gpio0: gpio@e0600000 {
189 status = "okay";
190 };
191
192 gpio1: gpio@e0680000 {
193 status = "okay";
194 };
195
196 i2c0: i2c@e0280000 {
197 status = "okay";
198 };
199
200 i2c1: i2c@b4000000 {
201 status = "okay";
202 };
203
204 kbd@e0300000 {
205 linux,keymap = < 0x00000001
206 0x00010002
207 0x00020003
208 0x00030004
209 0x00040005
210 0x00050006
211 0x00060007
212 0x00070008
213 0x00080009
214 0x0100000a
215 0x0101000c
216 0x0102000d
217 0x0103000e
218 0x0104000f
219 0x01050010
220 0x01060011
221 0x01070012
222 0x01080013
223 0x02000014
224 0x02010015
225 0x02020016
226 0x02030017
227 0x02040018
228 0x02050019
229 0x0206001a
230 0x0207001b
231 0x0208001c
232 0x0300001d
233 0x0301001e
234 0x0302001f
235 0x03030020
236 0x03040021
237 0x03050022
238 0x03060023
239 0x03070024
240 0x03080025
241 0x04000026
242 0x04010027
243 0x04020028
244 0x04030029
245 0x0404002a
246 0x0405002b
247 0x0406002c
248 0x0407002d
249 0x0408002e
250 0x0500002f
251 0x05010030
252 0x05020031
253 0x05030032
254 0x05040033
255 0x05050034
256 0x05060035
257 0x05070036
258 0x05080037
259 0x06000038
260 0x06010039
261 0x0602003a
262 0x0603003b
263 0x0604003c
264 0x0605003d
265 0x0606003e
266 0x0607003f
267 0x06080040
268 0x07000041
269 0x07010042
270 0x07020043
271 0x07030044
272 0x07040045
273 0x07050046
274 0x07060047
275 0x07070048
276 0x07080049
277 0x0800004a
278 0x0801004b
279 0x0802004c
280 0x0803004d
281 0x0804004e
282 0x0805004f
283 0x08060050
284 0x08070051
285 0x08080052 >;
286 autorepeat;
287 st,mode = <0>;
288 status = "okay";
289 };
290
291 rtc@e0580000 {
292 status = "okay";
293 };
294
295 serial@e0000000 {
296 status = "okay";
297 };
298
299 serial@b4100000 {
300 status = "okay";
301 };
302
303 wdt@ec800620 {
304 status = "okay";
305 };
306 };
307 };
308};
diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi
new file mode 100644
index 000000000000..a26fc47a55e8
--- /dev/null
+++ b/arch/arm/boot/dts/spear1340.dtsi
@@ -0,0 +1,56 @@
1/*
2 * DTS file for all SPEAr1340 SoCs
3 *
4 * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "spear13xx.dtsi"
15
16/ {
17 compatible = "st,spear1340";
18
19 ahb {
20 ahci@b1000000 {
21 compatible = "snps,spear-ahci";
22 reg = <0xb1000000 0x10000>;
23 interrupts = <0 72 0x4>;
24 status = "disabled";
25 };
26
27 spi1: spi@5d400000 {
28 compatible = "arm,pl022", "arm,primecell";
29 reg = <0x5d400000 0x1000>;
30 interrupts = <0 99 0x4>;
31 status = "disabled";
32 };
33
34 apb {
35 i2c1: i2c@b4000000 {
36 #address-cells = <1>;
37 #size-cells = <0>;
38 compatible = "snps,designware-i2c";
39 reg = <0xb4000000 0x1000>;
40 interrupts = <0 104 0x4>;
41 status = "disabled";
42 };
43
44 serial@b4100000 {
45 compatible = "arm,pl011", "arm,primecell";
46 reg = <0xb4100000 0x1000>;
47 interrupts = <0 105 0x4>;
48 status = "disabled";
49 };
50
51 thermal@e07008c4 {
52 st,thermal-flags = <0x2a00>;
53 };
54 };
55 };
56};
diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
new file mode 100644
index 000000000000..1f8e1e1481df
--- /dev/null
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -0,0 +1,262 @@
1/*
2 * DTS file for all SPEAr13xx SoCs
3 *
4 * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "skeleton.dtsi"
15
16/ {
17 interrupt-parent = <&gic>;
18
19 cpus {
20 #address-cells = <1>;
21 #size-cells = <0>;
22
23 cpu@0 {
24 compatible = "arm,cortex-a9";
25 reg = <0>;
26 next-level-cache = <&L2>;
27 };
28
29 cpu@1 {
30 compatible = "arm,cortex-a9";
31 reg = <1>;
32 next-level-cache = <&L2>;
33 };
34 };
35
36 gic: interrupt-controller@ec801000 {
37 compatible = "arm,cortex-a9-gic";
38 interrupt-controller;
39 #interrupt-cells = <3>;
40 reg = < 0xec801000 0x1000 >,
41 < 0xec800100 0x0100 >;
42 };
43
44 pmu {
45 compatible = "arm,cortex-a9-pmu";
46 interrupts = <0 8 0x04
47 0 9 0x04>;
48 };
49
50 L2: l2-cache {
51 compatible = "arm,pl310-cache";
52 reg = <0xed000000 0x1000>;
53 cache-unified;
54 cache-level = <2>;
55 };
56
57 memory {
58 name = "memory";
59 device_type = "memory";
60 reg = <0 0x40000000>;
61 };
62
63 chosen {
64 bootargs = "console=ttyAMA0,115200";
65 };
66
67 ahb {
68 #address-cells = <1>;
69 #size-cells = <1>;
70 compatible = "simple-bus";
71 ranges = <0x50000000 0x50000000 0x10000000
72 0xb0000000 0xb0000000 0x10000000
73 0xe0000000 0xe0000000 0x10000000>;
74
75 sdhci@b3000000 {
76 compatible = "st,sdhci-spear";
77 reg = <0xb3000000 0x100>;
78 interrupts = <0 28 0x4>;
79 status = "disabled";
80 };
81
82 cf@b2800000 {
83 compatible = "arasan,cf-spear1340";
84 reg = <0xb2800000 0x100>;
85 interrupts = <0 29 0x4>;
86 status = "disabled";
87 };
88
89 dma@ea800000 {
90 compatible = "snps,dma-spear1340";
91 reg = <0xea800000 0x1000>;
92 interrupts = <0 19 0x4>;
93 status = "disabled";
94 };
95
96 dma@eb000000 {
97 compatible = "snps,dma-spear1340";
98 reg = <0xeb000000 0x1000>;
99 interrupts = <0 59 0x4>;
100 status = "disabled";
101 };
102
103 fsmc: flash@b0000000 {
104 compatible = "st,spear600-fsmc-nand";
105 #address-cells = <1>;
106 #size-cells = <1>;
107 reg = <0xb0000000 0x1000 /* FSMC Register */
108 0xb0800000 0x0010>; /* NAND Base */
109 reg-names = "fsmc_regs", "nand_data";
110 interrupts = <0 20 0x4
111 0 21 0x4
112 0 22 0x4
113 0 23 0x4>;
114 st,ale-off = <0x20000>;
115 st,cle-off = <0x10000>;
116 status = "disabled";
117 };
118
119 gmac0: eth@e2000000 {
120 compatible = "st,spear600-gmac";
121 reg = <0xe2000000 0x8000>;
122 interrupts = <0 23 0x4
123 0 24 0x4>;
124 interrupt-names = "macirq", "eth_wake_irq";
125 status = "disabled";
126 };
127
128 smi: flash@ea000000 {
129 compatible = "st,spear600-smi";
130 #address-cells = <1>;
131 #size-cells = <1>;
132 reg = <0xea000000 0x1000>;
133 interrupts = <0 30 0x4>;
134 status = "disabled";
135 };
136
137 spi0: spi@e0100000 {
138 compatible = "arm,pl022", "arm,primecell";
139 reg = <0xe0100000 0x1000>;
140 interrupts = <0 31 0x4>;
141 status = "disabled";
142 };
143
144 ehci@e4800000 {
145 compatible = "st,spear600-ehci", "usb-ehci";
146 reg = <0xe4800000 0x1000>;
147 interrupts = <0 64 0x4>;
148 status = "disabled";
149 };
150
151 ehci@e5800000 {
152 compatible = "st,spear600-ehci", "usb-ehci";
153 reg = <0xe5800000 0x1000>;
154 interrupts = <0 66 0x4>;
155 status = "disabled";
156 };
157
158 ohci@e4000000 {
159 compatible = "st,spear600-ohci", "usb-ohci";
160 reg = <0xe4000000 0x1000>;
161 interrupts = <0 65 0x4>;
162 status = "disabled";
163 };
164
165 ohci@e5000000 {
166 compatible = "st,spear600-ohci", "usb-ohci";
167 reg = <0xe5000000 0x1000>;
168 interrupts = <0 67 0x4>;
169 status = "disabled";
170 };
171
172 apb {
173 #address-cells = <1>;
174 #size-cells = <1>;
175 compatible = "simple-bus";
176 ranges = <0x50000000 0x50000000 0x10000000
177 0xb0000000 0xb0000000 0x10000000
178 0xe0000000 0xe0000000 0x10000000>;
179
180 gpio0: gpio@e0600000 {
181 compatible = "arm,pl061", "arm,primecell";
182 reg = <0xe0600000 0x1000>;
183 interrupts = <0 24 0x4>;
184 gpio-controller;
185 #gpio-cells = <2>;
186 interrupt-controller;
187 #interrupt-cells = <2>;
188 status = "disabled";
189 };
190
191 gpio1: gpio@e0680000 {
192 compatible = "arm,pl061", "arm,primecell";
193 reg = <0xe0680000 0x1000>;
194 interrupts = <0 25 0x4>;
195 gpio-controller;
196 #gpio-cells = <2>;
197 interrupt-controller;
198 #interrupt-cells = <2>;
199 status = "disabled";
200 };
201
202 kbd@e0300000 {
203 compatible = "st,spear300-kbd";
204 reg = <0xe0300000 0x1000>;
205 status = "disabled";
206 };
207
208 i2c0: i2c@e0280000 {
209 #address-cells = <1>;
210 #size-cells = <0>;
211 compatible = "snps,designware-i2c";
212 reg = <0xe0280000 0x1000>;
213 interrupts = <0 41 0x4>;
214 status = "disabled";
215 };
216
217 rtc@e0580000 {
218 compatible = "st,spear-rtc";
219 reg = <0xe0580000 0x1000>;
220 interrupts = <0 36 0x4>;
221 status = "disabled";
222 };
223
224 serial@e0000000 {
225 compatible = "arm,pl011", "arm,primecell";
226 reg = <0xe0000000 0x1000>;
227 interrupts = <0 36 0x4>;
228 status = "disabled";
229 };
230
231 adc@e0080000 {
232 compatible = "st,spear600-adc";
233 reg = <0xe0080000 0x1000>;
234 interrupts = <0 44 0x4>;
235 status = "disabled";
236 };
237
238 timer@e0380000 {
239 compatible = "st,spear-timer";
240 reg = <0xe0380000 0x400>;
241 interrupts = <0 37 0x4>;
242 };
243
244 timer@ec800600 {
245 compatible = "arm,cortex-a9-twd-timer";
246 reg = <0xec800600 0x20>;
247 interrupts = <1 13 0x301>;
248 };
249
250 wdt@ec800620 {
251 compatible = "arm,cortex-a9-twd-wdt";
252 reg = <0xec800620 0x20>;
253 status = "disabled";
254 };
255
256 thermal@e07008c4 {
257 compatible = "st,thermal-spear1340";
258 reg = <0xe07008c4 0x4>;
259 };
260 };
261 };
262};
diff --git a/arch/arm/configs/spear13xx_defconfig b/arch/arm/configs/spear13xx_defconfig
new file mode 100644
index 000000000000..1fdb82694ca2
--- /dev/null
+++ b/arch/arm/configs/spear13xx_defconfig
@@ -0,0 +1,95 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_SYSVIPC=y
3CONFIG_BSD_PROCESS_ACCT=y
4CONFIG_BLK_DEV_INITRD=y
5CONFIG_MODULES=y
6CONFIG_MODULE_UNLOAD=y
7CONFIG_MODVERSIONS=y
8CONFIG_PARTITION_ADVANCED=y
9CONFIG_PLAT_SPEAR=y
10CONFIG_ARCH_SPEAR13XX=y
11CONFIG_MACH_SPEAR1310=y
12CONFIG_MACH_SPEAR1340=y
13# CONFIG_SWP_EMULATE is not set
14CONFIG_SMP=y
15# CONFIG_SMP_ON_UP is not set
16# CONFIG_ARM_CPU_TOPOLOGY is not set
17CONFIG_ARM_APPENDED_DTB=y
18CONFIG_ARM_ATAG_DTB_COMPAT=y
19CONFIG_BINFMT_MISC=y
20CONFIG_NET=y
21CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
22CONFIG_MTD=y
23CONFIG_MTD_OF_PARTS=y
24CONFIG_MTD_CHAR=y
25CONFIG_MTD_BLOCK=y
26CONFIG_MTD_NAND=y
27CONFIG_MTD_NAND_FSMC=y
28CONFIG_BLK_DEV_RAM=y
29CONFIG_BLK_DEV_RAM_SIZE=16384
30CONFIG_ATA=y
31# CONFIG_SATA_PMP is not set
32CONFIG_SATA_AHCI_PLATFORM=y
33CONFIG_PATA_ARASAN_CF=y
34CONFIG_NETDEVICES=y
35# CONFIG_NET_VENDOR_BROADCOM is not set
36# CONFIG_NET_VENDOR_CIRRUS is not set
37# CONFIG_NET_VENDOR_FARADAY is not set
38# CONFIG_NET_VENDOR_INTEL is not set
39# CONFIG_NET_VENDOR_MICREL is not set
40# CONFIG_NET_VENDOR_NATSEMI is not set
41# CONFIG_NET_VENDOR_SEEQ is not set
42# CONFIG_NET_VENDOR_SMSC is not set
43CONFIG_STMMAC_ETH=y
44# CONFIG_WLAN is not set
45CONFIG_INPUT_FF_MEMLESS=y
46# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
47# CONFIG_KEYBOARD_ATKBD is not set
48CONFIG_KEYBOARD_SPEAR=y
49# CONFIG_INPUT_MOUSE is not set
50# CONFIG_LEGACY_PTYS is not set
51CONFIG_SERIAL_AMBA_PL011=y
52CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
53# CONFIG_HW_RANDOM is not set
54CONFIG_RAW_DRIVER=y
55CONFIG_MAX_RAW_DEVS=8192
56CONFIG_I2C=y
57CONFIG_I2C_DESIGNWARE_PLATFORM=y
58CONFIG_SPI=y
59CONFIG_SPI_PL022=y
60CONFIG_GPIO_SYSFS=y
61CONFIG_GPIO_PL061=y
62# CONFIG_HWMON is not set
63CONFIG_WATCHDOG=y
64CONFIG_MPCORE_WATCHDOG=y
65# CONFIG_HID_SUPPORT is not set
66CONFIG_USB=y
67# CONFIG_USB_DEVICE_CLASS is not set
68CONFIG_USB_EHCI_HCD=y
69CONFIG_USB_OHCI_HCD=y
70CONFIG_MMC=y
71CONFIG_MMC_SDHCI=y
72CONFIG_MMC_SDHCI_SPEAR=y
73CONFIG_RTC_CLASS=y
74CONFIG_DMADEVICES=y
75CONFIG_DW_DMAC=y
76CONFIG_DMATEST=m
77CONFIG_EXT2_FS=y
78CONFIG_EXT2_FS_XATTR=y
79CONFIG_EXT2_FS_SECURITY=y
80CONFIG_EXT3_FS=y
81CONFIG_EXT3_FS_SECURITY=y
82CONFIG_AUTOFS4_FS=m
83CONFIG_MSDOS_FS=m
84CONFIG_VFAT_FS=m
85CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
86CONFIG_TMPFS=y
87CONFIG_JFFS2_FS=y
88CONFIG_NLS_DEFAULT="utf8"
89CONFIG_NLS_CODEPAGE_437=y
90CONFIG_NLS_ASCII=m
91CONFIG_MAGIC_SYSRQ=y
92CONFIG_DEBUG_FS=y
93CONFIG_DEBUG_KERNEL=y
94CONFIG_DEBUG_SPINLOCK=y
95CONFIG_DEBUG_INFO=y
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index e3cfd5fd7dd5..43ebe9094411 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -61,6 +61,7 @@ config SOC_EXYNOS5250
61 bool "SAMSUNG EXYNOS5250" 61 bool "SAMSUNG EXYNOS5250"
62 default y 62 default y
63 depends on ARCH_EXYNOS5 63 depends on ARCH_EXYNOS5
64 select SAMSUNG_DMADEV
64 help 65 help
65 Enable EXYNOS5250 SoC support 66 Enable EXYNOS5250 SoC support
66 67
@@ -70,7 +71,7 @@ config EXYNOS4_MCT
70 help 71 help
71 Use MCT (Multi Core Timer) as kernel timers 72 Use MCT (Multi Core Timer) as kernel timers
72 73
73config EXYNOS4_DEV_DMA 74config EXYNOS_DEV_DMA
74 bool 75 bool
75 help 76 help
76 Compile in amba device definitions for DMA controller 77 Compile in amba device definitions for DMA controller
@@ -80,6 +81,11 @@ config EXYNOS4_DEV_AHCI
80 help 81 help
81 Compile in platform device definitions for AHCI 82 Compile in platform device definitions for AHCI
82 83
84config EXYNOS_DEV_DRM
85 bool
86 help
87 Compile in platform device definitions for core DRM device
88
83config EXYNOS4_SETUP_FIMD0 89config EXYNOS4_SETUP_FIMD0
84 bool 90 bool
85 help 91 help
@@ -161,7 +167,7 @@ config EXYNOS4_SETUP_USB_PHY
161 help 167 help
162 Common setup code for USB PHY controller 168 Common setup code for USB PHY controller
163 169
164config EXYNOS4_SETUP_SPI 170config EXYNOS_SETUP_SPI
165 bool 171 bool
166 help 172 help
167 Common setup code for SPI GPIO configurations. 173 Common setup code for SPI GPIO configurations.
@@ -224,7 +230,7 @@ config MACH_ARMLEX4210
224 select S3C_DEV_HSMMC2 230 select S3C_DEV_HSMMC2
225 select S3C_DEV_HSMMC3 231 select S3C_DEV_HSMMC3
226 select EXYNOS4_DEV_AHCI 232 select EXYNOS4_DEV_AHCI
227 select EXYNOS4_DEV_DMA 233 select EXYNOS_DEV_DMA
228 select EXYNOS4_SETUP_SDHCI 234 select EXYNOS4_SETUP_SDHCI
229 help 235 help
230 Machine support for Samsung ARMLEX4210 based on EXYNOS4210 236 Machine support for Samsung ARMLEX4210 based on EXYNOS4210
@@ -362,7 +368,7 @@ config MACH_SMDK4212
362 select SAMSUNG_DEV_KEYPAD 368 select SAMSUNG_DEV_KEYPAD
363 select SAMSUNG_DEV_PWM 369 select SAMSUNG_DEV_PWM
364 select EXYNOS_DEV_SYSMMU 370 select EXYNOS_DEV_SYSMMU
365 select EXYNOS4_DEV_DMA 371 select EXYNOS_DEV_DMA
366 select EXYNOS4_SETUP_I2C1 372 select EXYNOS4_SETUP_I2C1
367 select EXYNOS4_SETUP_I2C3 373 select EXYNOS4_SETUP_I2C3
368 select EXYNOS4_SETUP_I2C7 374 select EXYNOS4_SETUP_I2C7
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 272625231c73..440a637c76f1 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -50,10 +50,11 @@ obj-$(CONFIG_MACH_EXYNOS5_DT) += mach-exynos5-dt.o
50obj-y += dev-uart.o 50obj-y += dev-uart.o
51obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o 51obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o
52obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o 52obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o
53obj-$(CONFIG_EXYNOS_DEV_SYSMMU) += dev-sysmmu.o
54obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o 53obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o
55obj-$(CONFIG_EXYNOS4_DEV_DMA) += dma.o 54obj-$(CONFIG_EXYNOS_DEV_DMA) += dma.o
56obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI) += dev-ohci.o 55obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI) += dev-ohci.o
56obj-$(CONFIG_EXYNOS_DEV_DRM) += dev-drm.o
57obj-$(CONFIG_EXYNOS_DEV_SYSMMU) += dev-sysmmu.o
57 58
58obj-$(CONFIG_ARCH_EXYNOS) += setup-i2c0.o 59obj-$(CONFIG_ARCH_EXYNOS) += setup-i2c0.o
59obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o 60obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o
@@ -68,4 +69,4 @@ obj-$(CONFIG_EXYNOS4_SETUP_I2C7) += setup-i2c7.o
68obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o 69obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o
69obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o 70obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
70obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY) += setup-usb-phy.o 71obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY) += setup-usb-phy.o
71obj-$(CONFIG_EXYNOS4_SETUP_SPI) += setup-spi.o 72obj-$(CONFIG_EXYNOS_SETUP_SPI) += setup-spi.o
diff --git a/arch/arm/mach-exynos/Makefile.boot b/arch/arm/mach-exynos/Makefile.boot
index b9862e22bf10..31bd181b0514 100644
--- a/arch/arm/mach-exynos/Makefile.boot
+++ b/arch/arm/mach-exynos/Makefile.boot
@@ -1,2 +1,5 @@
1 zreladdr-y += 0x40008000 1 zreladdr-y += 0x40008000
2params_phys-y := 0x40000100 2params_phys-y := 0x40000100
3
4dtb-$(CONFIG_MACH_EXYNOS4_DT) += exynos4210-origen.dtb exynos4210-smdkv310.dtb
5dtb-$(CONFIG_MACH_EXYNOS5_DT) += exynos5250-smdk5250.dtb
diff --git a/arch/arm/mach-exynos/clock-exynos4212.c b/arch/arm/mach-exynos/clock-exynos4212.c
index 98823120570e..da397d21bbcf 100644
--- a/arch/arm/mach-exynos/clock-exynos4212.c
+++ b/arch/arm/mach-exynos/clock-exynos4212.c
@@ -92,6 +92,16 @@ static struct clk init_clocks_off[] = {
92 .devname = SYSMMU_CLOCK_DEVNAME(isp, 9), 92 .devname = SYSMMU_CLOCK_DEVNAME(isp, 9),
93 .enable = exynos4212_clk_ip_isp1_ctrl, 93 .enable = exynos4212_clk_ip_isp1_ctrl,
94 .ctrlbit = (1 << 4), 94 .ctrlbit = (1 << 4),
95 }, {
96 .name = "flite",
97 .devname = "exynos-fimc-lite.0",
98 .enable = exynos4212_clk_ip_isp0_ctrl,
99 .ctrlbit = (1 << 4),
100 }, {
101 .name = "flite",
102 .devname = "exynos-fimc-lite.1",
103 .enable = exynos4212_clk_ip_isp0_ctrl,
104 .ctrlbit = (1 << 3),
95 } 105 }
96}; 106};
97 107
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index 9f87a07b0bf8..5aa460b01fdf 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -165,11 +165,29 @@ static struct clksrc_clk exynos5_clk_sclk_apll = {
165 .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 }, 165 .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
166}; 166};
167 167
168static struct clksrc_clk exynos5_clk_mout_bpll_fout = {
169 .clk = {
170 .name = "mout_bpll_fout",
171 },
172 .sources = &clk_src_bpll_fout,
173 .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 0, .size = 1 },
174};
175
176static struct clk *exynos5_clk_src_bpll_list[] = {
177 [0] = &clk_fin_bpll,
178 [1] = &exynos5_clk_mout_bpll_fout.clk,
179};
180
181static struct clksrc_sources exynos5_clk_src_bpll = {
182 .sources = exynos5_clk_src_bpll_list,
183 .nr_sources = ARRAY_SIZE(exynos5_clk_src_bpll_list),
184};
185
168static struct clksrc_clk exynos5_clk_mout_bpll = { 186static struct clksrc_clk exynos5_clk_mout_bpll = {
169 .clk = { 187 .clk = {
170 .name = "mout_bpll", 188 .name = "mout_bpll",
171 }, 189 },
172 .sources = &clk_src_bpll, 190 .sources = &exynos5_clk_src_bpll,
173 .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 }, 191 .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 },
174}; 192};
175 193
@@ -207,11 +225,29 @@ static struct clksrc_clk exynos5_clk_mout_epll = {
207 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 }, 225 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },
208}; 226};
209 227
228static struct clksrc_clk exynos5_clk_mout_mpll_fout = {
229 .clk = {
230 .name = "mout_mpll_fout",
231 },
232 .sources = &clk_src_mpll_fout,
233 .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 4, .size = 1 },
234};
235
236static struct clk *exynos5_clk_src_mpll_list[] = {
237 [0] = &clk_fin_mpll,
238 [1] = &exynos5_clk_mout_mpll_fout.clk,
239};
240
241static struct clksrc_sources exynos5_clk_src_mpll = {
242 .sources = exynos5_clk_src_mpll_list,
243 .nr_sources = ARRAY_SIZE(exynos5_clk_src_mpll_list),
244};
245
210struct clksrc_clk exynos5_clk_mout_mpll = { 246struct clksrc_clk exynos5_clk_mout_mpll = {
211 .clk = { 247 .clk = {
212 .name = "mout_mpll", 248 .name = "mout_mpll",
213 }, 249 },
214 .sources = &clk_src_mpll, 250 .sources = &exynos5_clk_src_mpll,
215 .reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 }, 251 .reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
216}; 252};
217 253
@@ -474,6 +510,11 @@ static struct clk exynos5_init_clocks_off[] = {
474 .enable = exynos5_clk_ip_peris_ctrl, 510 .enable = exynos5_clk_ip_peris_ctrl,
475 .ctrlbit = (1 << 20), 511 .ctrlbit = (1 << 20),
476 }, { 512 }, {
513 .name = "watchdog",
514 .parent = &exynos5_clk_aclk_66.clk,
515 .enable = exynos5_clk_ip_peris_ctrl,
516 .ctrlbit = (1 << 19),
517 }, {
477 .name = "hsmmc", 518 .name = "hsmmc",
478 .devname = "exynos4-sdhci.0", 519 .devname = "exynos4-sdhci.0",
479 .parent = &exynos5_clk_aclk_200.clk, 520 .parent = &exynos5_clk_aclk_200.clk,
@@ -1031,10 +1072,12 @@ static struct clksrc_clk *exynos5_sysclks[] = {
1031 &exynos5_clk_mout_apll, 1072 &exynos5_clk_mout_apll,
1032 &exynos5_clk_sclk_apll, 1073 &exynos5_clk_sclk_apll,
1033 &exynos5_clk_mout_bpll, 1074 &exynos5_clk_mout_bpll,
1075 &exynos5_clk_mout_bpll_fout,
1034 &exynos5_clk_mout_bpll_user, 1076 &exynos5_clk_mout_bpll_user,
1035 &exynos5_clk_mout_cpll, 1077 &exynos5_clk_mout_cpll,
1036 &exynos5_clk_mout_epll, 1078 &exynos5_clk_mout_epll,
1037 &exynos5_clk_mout_mpll, 1079 &exynos5_clk_mout_mpll,
1080 &exynos5_clk_mout_mpll_fout,
1038 &exynos5_clk_mout_mpll_user, 1081 &exynos5_clk_mout_mpll_user,
1039 &exynos5_clk_vpllsrc, 1082 &exynos5_clk_vpllsrc,
1040 &exynos5_clk_sclk_vpll, 1083 &exynos5_clk_sclk_vpll,
@@ -1098,7 +1141,9 @@ static struct clk *exynos5_clks[] __initdata = {
1098 &exynos5_clk_sclk_hdmi27m, 1141 &exynos5_clk_sclk_hdmi27m,
1099 &exynos5_clk_sclk_hdmiphy, 1142 &exynos5_clk_sclk_hdmiphy,
1100 &clk_fout_bpll, 1143 &clk_fout_bpll,
1144 &clk_fout_bpll_div2,
1101 &clk_fout_cpll, 1145 &clk_fout_cpll,
1146 &clk_fout_mpll_div2,
1102 &exynos5_clk_armclk, 1147 &exynos5_clk_armclk,
1103}; 1148};
1104 1149
@@ -1263,8 +1308,10 @@ void __init_or_cpufreq exynos5_setup_clocks(void)
1263 1308
1264 clk_fout_apll.ops = &exynos5_fout_apll_ops; 1309 clk_fout_apll.ops = &exynos5_fout_apll_ops;
1265 clk_fout_bpll.rate = bpll; 1310 clk_fout_bpll.rate = bpll;
1311 clk_fout_bpll_div2.rate = bpll >> 1;
1266 clk_fout_cpll.rate = cpll; 1312 clk_fout_cpll.rate = cpll;
1267 clk_fout_mpll.rate = mpll; 1313 clk_fout_mpll.rate = mpll;
1314 clk_fout_mpll_div2.rate = mpll >> 1;
1268 clk_fout_epll.rate = epll; 1315 clk_fout_epll.rate = epll;
1269 clk_fout_vpll.rate = vpll; 1316 clk_fout_vpll.rate = vpll;
1270 1317
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 5ccd6e80a607..49134711f4c6 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -19,6 +19,9 @@
19#include <linux/serial_core.h> 19#include <linux/serial_core.h>
20#include <linux/of.h> 20#include <linux/of.h>
21#include <linux/of_irq.h> 21#include <linux/of_irq.h>
22#include <linux/export.h>
23#include <linux/irqdomain.h>
24#include <linux/of_address.h>
22 25
23#include <asm/proc-fns.h> 26#include <asm/proc-fns.h>
24#include <asm/exception.h> 27#include <asm/exception.h>
@@ -265,12 +268,12 @@ static struct map_desc exynos5_iodesc[] __initdata = {
265 }, { 268 }, {
266 .virtual = (unsigned long)S5P_VA_GIC_CPU, 269 .virtual = (unsigned long)S5P_VA_GIC_CPU,
267 .pfn = __phys_to_pfn(EXYNOS5_PA_GIC_CPU), 270 .pfn = __phys_to_pfn(EXYNOS5_PA_GIC_CPU),
268 .length = SZ_64K, 271 .length = SZ_8K,
269 .type = MT_DEVICE, 272 .type = MT_DEVICE,
270 }, { 273 }, {
271 .virtual = (unsigned long)S5P_VA_GIC_DIST, 274 .virtual = (unsigned long)S5P_VA_GIC_DIST,
272 .pfn = __phys_to_pfn(EXYNOS5_PA_GIC_DIST), 275 .pfn = __phys_to_pfn(EXYNOS5_PA_GIC_DIST),
273 .length = SZ_64K, 276 .length = SZ_4K,
274 .type = MT_DEVICE, 277 .type = MT_DEVICE,
275 }, 278 },
276}; 279};
@@ -399,6 +402,7 @@ struct combiner_chip_data {
399 void __iomem *base; 402 void __iomem *base;
400}; 403};
401 404
405static struct irq_domain *combiner_irq_domain;
402static struct combiner_chip_data combiner_data[MAX_COMBINER_NR]; 406static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
403 407
404static inline void __iomem *combiner_base(struct irq_data *data) 408static inline void __iomem *combiner_base(struct irq_data *data)
@@ -411,14 +415,14 @@ static inline void __iomem *combiner_base(struct irq_data *data)
411 415
412static void combiner_mask_irq(struct irq_data *data) 416static void combiner_mask_irq(struct irq_data *data)
413{ 417{
414 u32 mask = 1 << (data->irq % 32); 418 u32 mask = 1 << (data->hwirq % 32);
415 419
416 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR); 420 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
417} 421}
418 422
419static void combiner_unmask_irq(struct irq_data *data) 423static void combiner_unmask_irq(struct irq_data *data)
420{ 424{
421 u32 mask = 1 << (data->irq % 32); 425 u32 mask = 1 << (data->hwirq % 32);
422 426
423 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET); 427 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
424} 428}
@@ -474,49 +478,131 @@ static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int i
474 irq_set_chained_handler(irq, combiner_handle_cascade_irq); 478 irq_set_chained_handler(irq, combiner_handle_cascade_irq);
475} 479}
476 480
477static void __init combiner_init(unsigned int combiner_nr, void __iomem *base, 481static void __init combiner_init_one(unsigned int combiner_nr,
478 unsigned int irq_start) 482 void __iomem *base)
479{ 483{
480 unsigned int i;
481 unsigned int max_nr;
482
483 if (soc_is_exynos5250())
484 max_nr = EXYNOS5_MAX_COMBINER_NR;
485 else
486 max_nr = EXYNOS4_MAX_COMBINER_NR;
487
488 if (combiner_nr >= max_nr)
489 BUG();
490
491 combiner_data[combiner_nr].base = base; 484 combiner_data[combiner_nr].base = base;
492 combiner_data[combiner_nr].irq_offset = irq_start; 485 combiner_data[combiner_nr].irq_offset = irq_find_mapping(
486 combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER);
493 combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3); 487 combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
494 488
495 /* Disable all interrupts */ 489 /* Disable all interrupts */
496
497 __raw_writel(combiner_data[combiner_nr].irq_mask, 490 __raw_writel(combiner_data[combiner_nr].irq_mask,
498 base + COMBINER_ENABLE_CLEAR); 491 base + COMBINER_ENABLE_CLEAR);
492}
493
494#ifdef CONFIG_OF
495static int combiner_irq_domain_xlate(struct irq_domain *d,
496 struct device_node *controller,
497 const u32 *intspec, unsigned int intsize,
498 unsigned long *out_hwirq,
499 unsigned int *out_type)
500{
501 if (d->of_node != controller)
502 return -EINVAL;
503
504 if (intsize < 2)
505 return -EINVAL;
506
507 *out_hwirq = intspec[0] * MAX_IRQ_IN_COMBINER + intspec[1];
508 *out_type = 0;
509
510 return 0;
511}
512#else
513static int combiner_irq_domain_xlate(struct irq_domain *d,
514 struct device_node *controller,
515 const u32 *intspec, unsigned int intsize,
516 unsigned long *out_hwirq,
517 unsigned int *out_type)
518{
519 return -EINVAL;
520}
521#endif
522
523static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq,
524 irq_hw_number_t hw)
525{
526 irq_set_chip_and_handler(irq, &combiner_chip, handle_level_irq);
527 irq_set_chip_data(irq, &combiner_data[hw >> 3]);
528 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
499 529
500 /* Setup the Linux IRQ subsystem */ 530 return 0;
531}
532
533static struct irq_domain_ops combiner_irq_domain_ops = {
534 .xlate = combiner_irq_domain_xlate,
535 .map = combiner_irq_domain_map,
536};
501 537
502 for (i = irq_start; i < combiner_data[combiner_nr].irq_offset 538void __init combiner_init(void __iomem *combiner_base, struct device_node *np)
503 + MAX_IRQ_IN_COMBINER; i++) { 539{
504 irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq); 540 int i, irq, irq_base;
505 irq_set_chip_data(i, &combiner_data[combiner_nr]); 541 unsigned int max_nr, nr_irq;
506 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 542
543 if (np) {
544 if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) {
545 pr_warning("%s: number of combiners not specified, "
546 "setting default as %d.\n",
547 __func__, EXYNOS4_MAX_COMBINER_NR);
548 max_nr = EXYNOS4_MAX_COMBINER_NR;
549 }
550 } else {
551 max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
552 EXYNOS4_MAX_COMBINER_NR;
553 }
554 nr_irq = max_nr * MAX_IRQ_IN_COMBINER;
555
556 irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
557 if (IS_ERR_VALUE(irq_base)) {
558 irq_base = COMBINER_IRQ(0, 0);
559 pr_warning("%s: irq desc alloc failed. Continuing with %d as linux irq base\n", __func__, irq_base);
560 }
561
562 combiner_irq_domain = irq_domain_add_legacy(np, nr_irq, irq_base, 0,
563 &combiner_irq_domain_ops, &combiner_data);
564 if (WARN_ON(!combiner_irq_domain)) {
565 pr_warning("%s: irq domain init failed\n", __func__);
566 return;
567 }
568
569 for (i = 0; i < max_nr; i++) {
570 combiner_init_one(i, combiner_base + (i >> 2) * 0x10);
571 irq = IRQ_SPI(i);
572#ifdef CONFIG_OF
573 if (np)
574 irq = irq_of_parse_and_map(np, i);
575#endif
576 combiner_cascade_irq(i, irq);
507 } 577 }
508} 578}
509 579
510#ifdef CONFIG_OF 580#ifdef CONFIG_OF
581int __init combiner_of_init(struct device_node *np, struct device_node *parent)
582{
583 void __iomem *combiner_base;
584
585 combiner_base = of_iomap(np, 0);
586 if (!combiner_base) {
587 pr_err("%s: failed to map combiner registers\n", __func__);
588 return -ENXIO;
589 }
590
591 combiner_init(combiner_base, np);
592
593 return 0;
594}
595
511static const struct of_device_id exynos4_dt_irq_match[] = { 596static const struct of_device_id exynos4_dt_irq_match[] = {
512 { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, }, 597 { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
598 { .compatible = "samsung,exynos4210-combiner",
599 .data = combiner_of_init, },
513 {}, 600 {},
514}; 601};
515#endif 602#endif
516 603
517void __init exynos4_init_irq(void) 604void __init exynos4_init_irq(void)
518{ 605{
519 int irq;
520 unsigned int gic_bank_offset; 606 unsigned int gic_bank_offset;
521 607
522 gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000; 608 gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
@@ -528,12 +614,8 @@ void __init exynos4_init_irq(void)
528 of_irq_init(exynos4_dt_irq_match); 614 of_irq_init(exynos4_dt_irq_match);
529#endif 615#endif
530 616
531 for (irq = 0; irq < EXYNOS4_MAX_COMBINER_NR; irq++) { 617 if (!of_have_populated_dt())
532 618 combiner_init(S5P_VA_COMBINER_BASE, NULL);
533 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
534 COMBINER_IRQ(irq, 0));
535 combiner_cascade_irq(irq, IRQ_SPI(irq));
536 }
537 619
538 /* 620 /*
539 * The parameters of s5p_init_irq() are for VIC init. 621 * The parameters of s5p_init_irq() are for VIC init.
@@ -545,18 +627,9 @@ void __init exynos4_init_irq(void)
545 627
546void __init exynos5_init_irq(void) 628void __init exynos5_init_irq(void)
547{ 629{
548 int irq;
549
550#ifdef CONFIG_OF 630#ifdef CONFIG_OF
551 of_irq_init(exynos4_dt_irq_match); 631 of_irq_init(exynos4_dt_irq_match);
552#endif 632#endif
553
554 for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) {
555 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
556 COMBINER_IRQ(irq, 0));
557 combiner_cascade_irq(irq, IRQ_SPI(irq));
558 }
559
560 /* 633 /*
561 * The parameters of s5p_init_irq() are for VIC init. 634 * The parameters of s5p_init_irq() are for VIC init.
562 * Theses parameters should be NULL and 0 because EXYNOS4 635 * Theses parameters should be NULL and 0 because EXYNOS4
@@ -565,30 +638,18 @@ void __init exynos5_init_irq(void)
565 s5p_init_irq(NULL, 0); 638 s5p_init_irq(NULL, 0);
566} 639}
567 640
568struct bus_type exynos4_subsys = { 641struct bus_type exynos_subsys = {
569 .name = "exynos4-core", 642 .name = "exynos-core",
570 .dev_name = "exynos4-core", 643 .dev_name = "exynos-core",
571};
572
573struct bus_type exynos5_subsys = {
574 .name = "exynos5-core",
575 .dev_name = "exynos5-core",
576}; 644};
577 645
578static struct device exynos4_dev = { 646static struct device exynos4_dev = {
579 .bus = &exynos4_subsys, 647 .bus = &exynos_subsys,
580};
581
582static struct device exynos5_dev = {
583 .bus = &exynos5_subsys,
584}; 648};
585 649
586static int __init exynos_core_init(void) 650static int __init exynos_core_init(void)
587{ 651{
588 if (soc_is_exynos5250()) 652 return subsys_system_register(&exynos_subsys, NULL);
589 return subsys_system_register(&exynos5_subsys, NULL);
590 else
591 return subsys_system_register(&exynos4_subsys, NULL);
592} 653}
593core_initcall(exynos_core_init); 654core_initcall(exynos_core_init);
594 655
@@ -675,10 +736,7 @@ static int __init exynos_init(void)
675{ 736{
676 printk(KERN_INFO "EXYNOS: Initializing architecture\n"); 737 printk(KERN_INFO "EXYNOS: Initializing architecture\n");
677 738
678 if (soc_is_exynos5250()) 739 return device_register(&exynos4_dev);
679 return device_register(&exynos5_dev);
680 else
681 return device_register(&exynos4_dev);
682} 740}
683 741
684/* uart registration process */ 742/* uart registration process */
diff --git a/arch/arm/mach-exynos/dev-drm.c b/arch/arm/mach-exynos/dev-drm.c
new file mode 100644
index 000000000000..17c9c6ecc2e0
--- /dev/null
+++ b/arch/arm/mach-exynos/dev-drm.c
@@ -0,0 +1,29 @@
1/*
2 * linux/arch/arm/mach-exynos/dev-drm.c
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * EXYNOS - core DRM device
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#include <linux/kernel.h>
16#include <linux/dma-mapping.h>
17#include <linux/platform_device.h>
18
19#include <plat/devs.h>
20
21static u64 exynos_drm_dma_mask = DMA_BIT_MASK(32);
22
23struct platform_device exynos_device_drm = {
24 .name = "exynos-drm",
25 .dev = {
26 .dma_mask = &exynos_drm_dma_mask,
27 .coherent_dma_mask = DMA_BIT_MASK(32),
28 }
29};
diff --git a/arch/arm/mach-exynos/dma.c b/arch/arm/mach-exynos/dma.c
index 69aaa4503205..f60b66dbcf84 100644
--- a/arch/arm/mach-exynos/dma.c
+++ b/arch/arm/mach-exynos/dma.c
@@ -103,10 +103,45 @@ static u8 exynos4212_pdma0_peri[] = {
103 DMACH_MIPI_HSI5, 103 DMACH_MIPI_HSI5,
104}; 104};
105 105
106struct dma_pl330_platdata exynos4_pdma0_pdata; 106static u8 exynos5250_pdma0_peri[] = {
107 DMACH_PCM0_RX,
108 DMACH_PCM0_TX,
109 DMACH_PCM2_RX,
110 DMACH_PCM2_TX,
111 DMACH_SPI0_RX,
112 DMACH_SPI0_TX,
113 DMACH_SPI2_RX,
114 DMACH_SPI2_TX,
115 DMACH_I2S0S_TX,
116 DMACH_I2S0_RX,
117 DMACH_I2S0_TX,
118 DMACH_I2S2_RX,
119 DMACH_I2S2_TX,
120 DMACH_UART0_RX,
121 DMACH_UART0_TX,
122 DMACH_UART2_RX,
123 DMACH_UART2_TX,
124 DMACH_UART4_RX,
125 DMACH_UART4_TX,
126 DMACH_SLIMBUS0_RX,
127 DMACH_SLIMBUS0_TX,
128 DMACH_SLIMBUS2_RX,
129 DMACH_SLIMBUS2_TX,
130 DMACH_SLIMBUS4_RX,
131 DMACH_SLIMBUS4_TX,
132 DMACH_AC97_MICIN,
133 DMACH_AC97_PCMIN,
134 DMACH_AC97_PCMOUT,
135 DMACH_MIPI_HSI0,
136 DMACH_MIPI_HSI2,
137 DMACH_MIPI_HSI4,
138 DMACH_MIPI_HSI6,
139};
140
141static struct dma_pl330_platdata exynos_pdma0_pdata;
107 142
108static AMBA_AHB_DEVICE(exynos4_pdma0, "dma-pl330.0", 0x00041330, 143static AMBA_AHB_DEVICE(exynos_pdma0, "dma-pl330.0", 0x00041330,
109 EXYNOS4_PA_PDMA0, {EXYNOS4_IRQ_PDMA0}, &exynos4_pdma0_pdata); 144 EXYNOS4_PA_PDMA0, {EXYNOS4_IRQ_PDMA0}, &exynos_pdma0_pdata);
110 145
111static u8 exynos4210_pdma1_peri[] = { 146static u8 exynos4210_pdma1_peri[] = {
112 DMACH_PCM0_RX, 147 DMACH_PCM0_RX,
@@ -169,10 +204,45 @@ static u8 exynos4212_pdma1_peri[] = {
169 DMACH_MIPI_HSI7, 204 DMACH_MIPI_HSI7,
170}; 205};
171 206
172static struct dma_pl330_platdata exynos4_pdma1_pdata; 207static u8 exynos5250_pdma1_peri[] = {
208 DMACH_PCM0_RX,
209 DMACH_PCM0_TX,
210 DMACH_PCM1_RX,
211 DMACH_PCM1_TX,
212 DMACH_SPI1_RX,
213 DMACH_SPI1_TX,
214 DMACH_PWM,
215 DMACH_SPDIF,
216 DMACH_I2S0S_TX,
217 DMACH_I2S0_RX,
218 DMACH_I2S0_TX,
219 DMACH_I2S1_RX,
220 DMACH_I2S1_TX,
221 DMACH_UART0_RX,
222 DMACH_UART0_TX,
223 DMACH_UART1_RX,
224 DMACH_UART1_TX,
225 DMACH_UART3_RX,
226 DMACH_UART3_TX,
227 DMACH_SLIMBUS1_RX,
228 DMACH_SLIMBUS1_TX,
229 DMACH_SLIMBUS3_RX,
230 DMACH_SLIMBUS3_TX,
231 DMACH_SLIMBUS5_RX,
232 DMACH_SLIMBUS5_TX,
233 DMACH_SLIMBUS0AUX_RX,
234 DMACH_SLIMBUS0AUX_TX,
235 DMACH_DISP1,
236 DMACH_MIPI_HSI1,
237 DMACH_MIPI_HSI3,
238 DMACH_MIPI_HSI5,
239 DMACH_MIPI_HSI7,
240};
173 241
174static AMBA_AHB_DEVICE(exynos4_pdma1, "dma-pl330.1", 0x00041330, 242static struct dma_pl330_platdata exynos_pdma1_pdata;
175 EXYNOS4_PA_PDMA1, {EXYNOS4_IRQ_PDMA1}, &exynos4_pdma1_pdata); 243
244static AMBA_AHB_DEVICE(exynos_pdma1, "dma-pl330.1", 0x00041330,
245 EXYNOS4_PA_PDMA1, {EXYNOS4_IRQ_PDMA1}, &exynos_pdma1_pdata);
176 246
177static u8 mdma_peri[] = { 247static u8 mdma_peri[] = {
178 DMACH_MTOM_0, 248 DMACH_MTOM_0,
@@ -185,46 +255,63 @@ static u8 mdma_peri[] = {
185 DMACH_MTOM_7, 255 DMACH_MTOM_7,
186}; 256};
187 257
188static struct dma_pl330_platdata exynos4_mdma1_pdata = { 258static struct dma_pl330_platdata exynos_mdma1_pdata = {
189 .nr_valid_peri = ARRAY_SIZE(mdma_peri), 259 .nr_valid_peri = ARRAY_SIZE(mdma_peri),
190 .peri_id = mdma_peri, 260 .peri_id = mdma_peri,
191}; 261};
192 262
193static AMBA_AHB_DEVICE(exynos4_mdma1, "dma-pl330.2", 0x00041330, 263static AMBA_AHB_DEVICE(exynos_mdma1, "dma-pl330.2", 0x00041330,
194 EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1}, &exynos4_mdma1_pdata); 264 EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1}, &exynos_mdma1_pdata);
195 265
196static int __init exynos4_dma_init(void) 266static int __init exynos_dma_init(void)
197{ 267{
198 if (of_have_populated_dt()) 268 if (of_have_populated_dt())
199 return 0; 269 return 0;
200 270
201 if (soc_is_exynos4210()) { 271 if (soc_is_exynos4210()) {
202 exynos4_pdma0_pdata.nr_valid_peri = 272 exynos_pdma0_pdata.nr_valid_peri =
203 ARRAY_SIZE(exynos4210_pdma0_peri); 273 ARRAY_SIZE(exynos4210_pdma0_peri);
204 exynos4_pdma0_pdata.peri_id = exynos4210_pdma0_peri; 274 exynos_pdma0_pdata.peri_id = exynos4210_pdma0_peri;
205 exynos4_pdma1_pdata.nr_valid_peri = 275 exynos_pdma1_pdata.nr_valid_peri =
206 ARRAY_SIZE(exynos4210_pdma1_peri); 276 ARRAY_SIZE(exynos4210_pdma1_peri);
207 exynos4_pdma1_pdata.peri_id = exynos4210_pdma1_peri; 277 exynos_pdma1_pdata.peri_id = exynos4210_pdma1_peri;
208 } else if (soc_is_exynos4212() || soc_is_exynos4412()) { 278 } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
209 exynos4_pdma0_pdata.nr_valid_peri = 279 exynos_pdma0_pdata.nr_valid_peri =
210 ARRAY_SIZE(exynos4212_pdma0_peri); 280 ARRAY_SIZE(exynos4212_pdma0_peri);
211 exynos4_pdma0_pdata.peri_id = exynos4212_pdma0_peri; 281 exynos_pdma0_pdata.peri_id = exynos4212_pdma0_peri;
212 exynos4_pdma1_pdata.nr_valid_peri = 282 exynos_pdma1_pdata.nr_valid_peri =
213 ARRAY_SIZE(exynos4212_pdma1_peri); 283 ARRAY_SIZE(exynos4212_pdma1_peri);
214 exynos4_pdma1_pdata.peri_id = exynos4212_pdma1_peri; 284 exynos_pdma1_pdata.peri_id = exynos4212_pdma1_peri;
285 } else if (soc_is_exynos5250()) {
286 exynos_pdma0_pdata.nr_valid_peri =
287 ARRAY_SIZE(exynos5250_pdma0_peri);
288 exynos_pdma0_pdata.peri_id = exynos5250_pdma0_peri;
289 exynos_pdma1_pdata.nr_valid_peri =
290 ARRAY_SIZE(exynos5250_pdma1_peri);
291 exynos_pdma1_pdata.peri_id = exynos5250_pdma1_peri;
292
293 exynos_pdma0_device.res.start = EXYNOS5_PA_PDMA0;
294 exynos_pdma0_device.res.end = EXYNOS5_PA_PDMA0 + SZ_4K;
295 exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_PDMA0;
296 exynos_pdma1_device.res.start = EXYNOS5_PA_PDMA1;
297 exynos_pdma1_device.res.end = EXYNOS5_PA_PDMA1 + SZ_4K;
298 exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_PDMA1;
299 exynos_mdma1_device.res.start = EXYNOS5_PA_MDMA1;
300 exynos_mdma1_device.res.end = EXYNOS5_PA_MDMA1 + SZ_4K;
301 exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_MDMA1;
215 } 302 }
216 303
217 dma_cap_set(DMA_SLAVE, exynos4_pdma0_pdata.cap_mask); 304 dma_cap_set(DMA_SLAVE, exynos_pdma0_pdata.cap_mask);
218 dma_cap_set(DMA_CYCLIC, exynos4_pdma0_pdata.cap_mask); 305 dma_cap_set(DMA_CYCLIC, exynos_pdma0_pdata.cap_mask);
219 amba_device_register(&exynos4_pdma0_device, &iomem_resource); 306 amba_device_register(&exynos_pdma0_device, &iomem_resource);
220 307
221 dma_cap_set(DMA_SLAVE, exynos4_pdma1_pdata.cap_mask); 308 dma_cap_set(DMA_SLAVE, exynos_pdma1_pdata.cap_mask);
222 dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask); 309 dma_cap_set(DMA_CYCLIC, exynos_pdma1_pdata.cap_mask);
223 amba_device_register(&exynos4_pdma1_device, &iomem_resource); 310 amba_device_register(&exynos_pdma1_device, &iomem_resource);
224 311
225 dma_cap_set(DMA_MEMCPY, exynos4_mdma1_pdata.cap_mask); 312 dma_cap_set(DMA_MEMCPY, exynos_mdma1_pdata.cap_mask);
226 amba_device_register(&exynos4_mdma1_device, &iomem_resource); 313 amba_device_register(&exynos_mdma1_device, &iomem_resource);
227 314
228 return 0; 315 return 0;
229} 316}
230arch_initcall(exynos4_dma_init); 317arch_initcall(exynos_dma_init);
diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h
index d7498afe036a..eb24f1eb8e3b 100644
--- a/arch/arm/mach-exynos/include/mach/gpio.h
+++ b/arch/arm/mach-exynos/include/mach/gpio.h
@@ -153,10 +153,11 @@ enum exynos4_gpio_number {
153#define EXYNOS5_GPIO_B2_NR (4) 153#define EXYNOS5_GPIO_B2_NR (4)
154#define EXYNOS5_GPIO_B3_NR (4) 154#define EXYNOS5_GPIO_B3_NR (4)
155#define EXYNOS5_GPIO_C0_NR (7) 155#define EXYNOS5_GPIO_C0_NR (7)
156#define EXYNOS5_GPIO_C1_NR (7) 156#define EXYNOS5_GPIO_C1_NR (4)
157#define EXYNOS5_GPIO_C2_NR (7) 157#define EXYNOS5_GPIO_C2_NR (7)
158#define EXYNOS5_GPIO_C3_NR (7) 158#define EXYNOS5_GPIO_C3_NR (7)
159#define EXYNOS5_GPIO_D0_NR (8) 159#define EXYNOS5_GPIO_C4_NR (7)
160#define EXYNOS5_GPIO_D0_NR (4)
160#define EXYNOS5_GPIO_D1_NR (8) 161#define EXYNOS5_GPIO_D1_NR (8)
161#define EXYNOS5_GPIO_Y0_NR (6) 162#define EXYNOS5_GPIO_Y0_NR (6)
162#define EXYNOS5_GPIO_Y1_NR (4) 163#define EXYNOS5_GPIO_Y1_NR (4)
@@ -199,7 +200,8 @@ enum exynos5_gpio_number {
199 EXYNOS5_GPIO_C1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C0), 200 EXYNOS5_GPIO_C1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C0),
200 EXYNOS5_GPIO_C2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C1), 201 EXYNOS5_GPIO_C2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C1),
201 EXYNOS5_GPIO_C3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C2), 202 EXYNOS5_GPIO_C3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C2),
202 EXYNOS5_GPIO_D0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3), 203 EXYNOS5_GPIO_C4_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3),
204 EXYNOS5_GPIO_D0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C4),
203 EXYNOS5_GPIO_D1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D0), 205 EXYNOS5_GPIO_D1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D0),
204 EXYNOS5_GPIO_Y0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D1), 206 EXYNOS5_GPIO_Y0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D1),
205 EXYNOS5_GPIO_Y1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y0), 207 EXYNOS5_GPIO_Y1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y0),
@@ -242,6 +244,7 @@ enum exynos5_gpio_number {
242#define EXYNOS5_GPC1(_nr) (EXYNOS5_GPIO_C1_START + (_nr)) 244#define EXYNOS5_GPC1(_nr) (EXYNOS5_GPIO_C1_START + (_nr))
243#define EXYNOS5_GPC2(_nr) (EXYNOS5_GPIO_C2_START + (_nr)) 245#define EXYNOS5_GPC2(_nr) (EXYNOS5_GPIO_C2_START + (_nr))
244#define EXYNOS5_GPC3(_nr) (EXYNOS5_GPIO_C3_START + (_nr)) 246#define EXYNOS5_GPC3(_nr) (EXYNOS5_GPIO_C3_START + (_nr))
247#define EXYNOS5_GPC4(_nr) (EXYNOS5_GPIO_C4_START + (_nr))
245#define EXYNOS5_GPD0(_nr) (EXYNOS5_GPIO_D0_START + (_nr)) 248#define EXYNOS5_GPD0(_nr) (EXYNOS5_GPIO_D0_START + (_nr))
246#define EXYNOS5_GPD1(_nr) (EXYNOS5_GPIO_D1_START + (_nr)) 249#define EXYNOS5_GPD1(_nr) (EXYNOS5_GPIO_D1_START + (_nr))
247#define EXYNOS5_GPY0(_nr) (EXYNOS5_GPIO_Y0_START + (_nr)) 250#define EXYNOS5_GPY0(_nr) (EXYNOS5_GPIO_Y0_START + (_nr))
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index ddde8f3a24d4..7a4b4789eb72 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -287,6 +287,7 @@
287#define EXYNOS5_IRQ_MIPICSI1 IRQ_SPI(80) 287#define EXYNOS5_IRQ_MIPICSI1 IRQ_SPI(80)
288#define EXYNOS5_IRQ_EFNFCON_DMA_ABORT IRQ_SPI(81) 288#define EXYNOS5_IRQ_EFNFCON_DMA_ABORT IRQ_SPI(81)
289#define EXYNOS5_IRQ_MIPIDSI0 IRQ_SPI(82) 289#define EXYNOS5_IRQ_MIPIDSI0 IRQ_SPI(82)
290#define EXYNOS5_IRQ_WDT_IOP IRQ_SPI(83)
290#define EXYNOS5_IRQ_ROTATOR IRQ_SPI(84) 291#define EXYNOS5_IRQ_ROTATOR IRQ_SPI(84)
291#define EXYNOS5_IRQ_GSC0 IRQ_SPI(85) 292#define EXYNOS5_IRQ_GSC0 IRQ_SPI(85)
292#define EXYNOS5_IRQ_GSC1 IRQ_SPI(86) 293#define EXYNOS5_IRQ_GSC1 IRQ_SPI(86)
@@ -295,8 +296,8 @@
295#define EXYNOS5_IRQ_JPEG IRQ_SPI(89) 296#define EXYNOS5_IRQ_JPEG IRQ_SPI(89)
296#define EXYNOS5_IRQ_EFNFCON_DMA IRQ_SPI(90) 297#define EXYNOS5_IRQ_EFNFCON_DMA IRQ_SPI(90)
297#define EXYNOS5_IRQ_2D IRQ_SPI(91) 298#define EXYNOS5_IRQ_2D IRQ_SPI(91)
298#define EXYNOS5_IRQ_SFMC0 IRQ_SPI(92) 299#define EXYNOS5_IRQ_EFNFCON_0 IRQ_SPI(92)
299#define EXYNOS5_IRQ_SFMC1 IRQ_SPI(93) 300#define EXYNOS5_IRQ_EFNFCON_1 IRQ_SPI(93)
300#define EXYNOS5_IRQ_MIXER IRQ_SPI(94) 301#define EXYNOS5_IRQ_MIXER IRQ_SPI(94)
301#define EXYNOS5_IRQ_HDMI IRQ_SPI(95) 302#define EXYNOS5_IRQ_HDMI IRQ_SPI(95)
302#define EXYNOS5_IRQ_MFC IRQ_SPI(96) 303#define EXYNOS5_IRQ_MFC IRQ_SPI(96)
@@ -310,7 +311,7 @@
310#define EXYNOS5_IRQ_PCM2 IRQ_SPI(104) 311#define EXYNOS5_IRQ_PCM2 IRQ_SPI(104)
311#define EXYNOS5_IRQ_SPDIF IRQ_SPI(105) 312#define EXYNOS5_IRQ_SPDIF IRQ_SPI(105)
312#define EXYNOS5_IRQ_ADC0 IRQ_SPI(106) 313#define EXYNOS5_IRQ_ADC0 IRQ_SPI(106)
313 314#define EXYNOS5_IRQ_ADC1 IRQ_SPI(107)
314#define EXYNOS5_IRQ_SATA_PHY IRQ_SPI(108) 315#define EXYNOS5_IRQ_SATA_PHY IRQ_SPI(108)
315#define EXYNOS5_IRQ_SATA_PMEMREQ IRQ_SPI(109) 316#define EXYNOS5_IRQ_SATA_PMEMREQ IRQ_SPI(109)
316#define EXYNOS5_IRQ_CAM_C IRQ_SPI(110) 317#define EXYNOS5_IRQ_CAM_C IRQ_SPI(110)
@@ -319,8 +320,9 @@
319#define EXYNOS5_IRQ_DP1_INTP1 IRQ_SPI(113) 320#define EXYNOS5_IRQ_DP1_INTP1 IRQ_SPI(113)
320#define EXYNOS5_IRQ_CEC IRQ_SPI(114) 321#define EXYNOS5_IRQ_CEC IRQ_SPI(114)
321#define EXYNOS5_IRQ_SATA IRQ_SPI(115) 322#define EXYNOS5_IRQ_SATA IRQ_SPI(115)
322#define EXYNOS5_IRQ_NFCON IRQ_SPI(116)
323 323
324#define EXYNOS5_IRQ_MCT_L0 IRQ_SPI(120)
325#define EXYNOS5_IRQ_MCT_L1 IRQ_SPI(121)
324#define EXYNOS5_IRQ_MMC44 IRQ_SPI(123) 326#define EXYNOS5_IRQ_MMC44 IRQ_SPI(123)
325#define EXYNOS5_IRQ_MDMA1 IRQ_SPI(124) 327#define EXYNOS5_IRQ_MDMA1 IRQ_SPI(124)
326#define EXYNOS5_IRQ_FIMC_LITE0 IRQ_SPI(125) 328#define EXYNOS5_IRQ_FIMC_LITE0 IRQ_SPI(125)
@@ -328,7 +330,6 @@
328#define EXYNOS5_IRQ_RP_TIMER IRQ_SPI(127) 330#define EXYNOS5_IRQ_RP_TIMER IRQ_SPI(127)
329 331
330#define EXYNOS5_IRQ_PMU COMBINER_IRQ(1, 2) 332#define EXYNOS5_IRQ_PMU COMBINER_IRQ(1, 2)
331#define EXYNOS5_IRQ_PMU_CPU1 COMBINER_IRQ(1, 6)
332 333
333#define EXYNOS5_IRQ_SYSMMU_GSC0_0 COMBINER_IRQ(2, 0) 334#define EXYNOS5_IRQ_SYSMMU_GSC0_0 COMBINER_IRQ(2, 0)
334#define EXYNOS5_IRQ_SYSMMU_GSC0_1 COMBINER_IRQ(2, 1) 335#define EXYNOS5_IRQ_SYSMMU_GSC0_1 COMBINER_IRQ(2, 1)
@@ -339,6 +340,8 @@
339#define EXYNOS5_IRQ_SYSMMU_GSC3_0 COMBINER_IRQ(2, 6) 340#define EXYNOS5_IRQ_SYSMMU_GSC3_0 COMBINER_IRQ(2, 6)
340#define EXYNOS5_IRQ_SYSMMU_GSC3_1 COMBINER_IRQ(2, 7) 341#define EXYNOS5_IRQ_SYSMMU_GSC3_1 COMBINER_IRQ(2, 7)
341 342
343#define EXYNOS5_IRQ_SYSMMU_LITE2_0 COMBINER_IRQ(3, 0)
344#define EXYNOS5_IRQ_SYSMMU_LITE2_1 COMBINER_IRQ(3, 1)
342#define EXYNOS5_IRQ_SYSMMU_FIMD1_0 COMBINER_IRQ(3, 2) 345#define EXYNOS5_IRQ_SYSMMU_FIMD1_0 COMBINER_IRQ(3, 2)
343#define EXYNOS5_IRQ_SYSMMU_FIMD1_1 COMBINER_IRQ(3, 3) 346#define EXYNOS5_IRQ_SYSMMU_FIMD1_1 COMBINER_IRQ(3, 3)
344#define EXYNOS5_IRQ_SYSMMU_LITE0_0 COMBINER_IRQ(3, 4) 347#define EXYNOS5_IRQ_SYSMMU_LITE0_0 COMBINER_IRQ(3, 4)
@@ -362,8 +365,8 @@
362 365
363#define EXYNOS5_IRQ_SYSMMU_ARM_0 COMBINER_IRQ(6, 0) 366#define EXYNOS5_IRQ_SYSMMU_ARM_0 COMBINER_IRQ(6, 0)
364#define EXYNOS5_IRQ_SYSMMU_ARM_1 COMBINER_IRQ(6, 1) 367#define EXYNOS5_IRQ_SYSMMU_ARM_1 COMBINER_IRQ(6, 1)
365#define EXYNOS5_IRQ_SYSMMU_MFC_L_0 COMBINER_IRQ(6, 2) 368#define EXYNOS5_IRQ_SYSMMU_MFC_R_0 COMBINER_IRQ(6, 2)
366#define EXYNOS5_IRQ_SYSMMU_MFC_L_1 COMBINER_IRQ(6, 3) 369#define EXYNOS5_IRQ_SYSMMU_MFC_R_1 COMBINER_IRQ(6, 3)
367#define EXYNOS5_IRQ_SYSMMU_RTIC_0 COMBINER_IRQ(6, 4) 370#define EXYNOS5_IRQ_SYSMMU_RTIC_0 COMBINER_IRQ(6, 4)
368#define EXYNOS5_IRQ_SYSMMU_RTIC_1 COMBINER_IRQ(6, 5) 371#define EXYNOS5_IRQ_SYSMMU_RTIC_1 COMBINER_IRQ(6, 5)
369#define EXYNOS5_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(6, 6) 372#define EXYNOS5_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(6, 6)
@@ -375,11 +378,9 @@
375#define EXYNOS5_IRQ_SYSMMU_MDMA1_1 COMBINER_IRQ(7, 3) 378#define EXYNOS5_IRQ_SYSMMU_MDMA1_1 COMBINER_IRQ(7, 3)
376#define EXYNOS5_IRQ_SYSMMU_TV_0 COMBINER_IRQ(7, 4) 379#define EXYNOS5_IRQ_SYSMMU_TV_0 COMBINER_IRQ(7, 4)
377#define EXYNOS5_IRQ_SYSMMU_TV_1 COMBINER_IRQ(7, 5) 380#define EXYNOS5_IRQ_SYSMMU_TV_1 COMBINER_IRQ(7, 5)
378#define EXYNOS5_IRQ_SYSMMU_GPSX_0 COMBINER_IRQ(7, 6)
379#define EXYNOS5_IRQ_SYSMMU_GPSX_1 COMBINER_IRQ(7, 7)
380 381
381#define EXYNOS5_IRQ_SYSMMU_MFC_R_0 COMBINER_IRQ(8, 5) 382#define EXYNOS5_IRQ_SYSMMU_MFC_L_0 COMBINER_IRQ(8, 5)
382#define EXYNOS5_IRQ_SYSMMU_MFC_R_1 COMBINER_IRQ(8, 6) 383#define EXYNOS5_IRQ_SYSMMU_MFC_L_1 COMBINER_IRQ(8, 6)
383 384
384#define EXYNOS5_IRQ_SYSMMU_DIS1_0 COMBINER_IRQ(9, 4) 385#define EXYNOS5_IRQ_SYSMMU_DIS1_0 COMBINER_IRQ(9, 4)
385#define EXYNOS5_IRQ_SYSMMU_DIS1_1 COMBINER_IRQ(9, 5) 386#define EXYNOS5_IRQ_SYSMMU_DIS1_1 COMBINER_IRQ(9, 5)
@@ -395,17 +396,24 @@
395#define EXYNOS5_IRQ_SYSMMU_DRC_0 COMBINER_IRQ(11, 6) 396#define EXYNOS5_IRQ_SYSMMU_DRC_0 COMBINER_IRQ(11, 6)
396#define EXYNOS5_IRQ_SYSMMU_DRC_1 COMBINER_IRQ(11, 7) 397#define EXYNOS5_IRQ_SYSMMU_DRC_1 COMBINER_IRQ(11, 7)
397 398
399#define EXYNOS5_IRQ_MDMA1_ABORT COMBINER_IRQ(13, 1)
400
401#define EXYNOS5_IRQ_MDMA0_ABORT COMBINER_IRQ(15, 3)
402
398#define EXYNOS5_IRQ_FIMD1_FIFO COMBINER_IRQ(18, 4) 403#define EXYNOS5_IRQ_FIMD1_FIFO COMBINER_IRQ(18, 4)
399#define EXYNOS5_IRQ_FIMD1_VSYNC COMBINER_IRQ(18, 5) 404#define EXYNOS5_IRQ_FIMD1_VSYNC COMBINER_IRQ(18, 5)
400#define EXYNOS5_IRQ_FIMD1_SYSTEM COMBINER_IRQ(18, 6) 405#define EXYNOS5_IRQ_FIMD1_SYSTEM COMBINER_IRQ(18, 6)
401 406
407#define EXYNOS5_IRQ_ARMIOP_GIC COMBINER_IRQ(19, 0)
408#define EXYNOS5_IRQ_ARMISP_GIC COMBINER_IRQ(19, 1)
409#define EXYNOS5_IRQ_IOP_GIC COMBINER_IRQ(19, 3)
410#define EXYNOS5_IRQ_ISP_GIC COMBINER_IRQ(19, 4)
411
412#define EXYNOS5_IRQ_PMU_CPU1 COMBINER_IRQ(22, 4)
413
402#define EXYNOS5_IRQ_EINT0 COMBINER_IRQ(23, 0) 414#define EXYNOS5_IRQ_EINT0 COMBINER_IRQ(23, 0)
403#define EXYNOS5_IRQ_MCT_L0 COMBINER_IRQ(23, 1)
404#define EXYNOS5_IRQ_MCT_L1 COMBINER_IRQ(23, 2)
405#define EXYNOS5_IRQ_MCT_G0 COMBINER_IRQ(23, 3) 415#define EXYNOS5_IRQ_MCT_G0 COMBINER_IRQ(23, 3)
406#define EXYNOS5_IRQ_MCT_G1 COMBINER_IRQ(23, 4) 416#define EXYNOS5_IRQ_MCT_G1 COMBINER_IRQ(23, 4)
407#define EXYNOS5_IRQ_MCT_G2 COMBINER_IRQ(23, 5)
408#define EXYNOS5_IRQ_MCT_G3 COMBINER_IRQ(23, 6)
409 417
410#define EXYNOS5_IRQ_EINT1 COMBINER_IRQ(24, 0) 418#define EXYNOS5_IRQ_EINT1 COMBINER_IRQ(24, 0)
411#define EXYNOS5_IRQ_SYSMMU_LITE1_0 COMBINER_IRQ(24, 1) 419#define EXYNOS5_IRQ_SYSMMU_LITE1_0 COMBINER_IRQ(24, 1)
@@ -436,7 +444,7 @@
436 444
437#define EXYNOS5_MAX_COMBINER_NR 32 445#define EXYNOS5_MAX_COMBINER_NR 32
438 446
439#define EXYNOS5_IRQ_GPIO1_NR_GROUPS 13 447#define EXYNOS5_IRQ_GPIO1_NR_GROUPS 14
440#define EXYNOS5_IRQ_GPIO2_NR_GROUPS 9 448#define EXYNOS5_IRQ_GPIO2_NR_GROUPS 9
441#define EXYNOS5_IRQ_GPIO3_NR_GROUPS 5 449#define EXYNOS5_IRQ_GPIO3_NR_GROUPS 5
442#define EXYNOS5_IRQ_GPIO4_NR_GROUPS 1 450#define EXYNOS5_IRQ_GPIO4_NR_GROUPS 1
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 2196af2d8218..ca4aa89aa46b 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -34,6 +34,9 @@
34 34
35#define EXYNOS4_PA_JPEG 0x11840000 35#define EXYNOS4_PA_JPEG 0x11840000
36 36
37/* x = 0...1 */
38#define EXYNOS4_PA_FIMC_LITE(x) (0x12390000 + ((x) * 0x10000))
39
37#define EXYNOS4_PA_G2D 0x12800000 40#define EXYNOS4_PA_G2D 0x12800000
38 41
39#define EXYNOS4_PA_I2S0 0x03830000 42#define EXYNOS4_PA_I2S0 0x03830000
@@ -78,8 +81,8 @@
78 81
79#define EXYNOS4_PA_GIC_CPU 0x10480000 82#define EXYNOS4_PA_GIC_CPU 0x10480000
80#define EXYNOS4_PA_GIC_DIST 0x10490000 83#define EXYNOS4_PA_GIC_DIST 0x10490000
81#define EXYNOS5_PA_GIC_CPU 0x10480000 84#define EXYNOS5_PA_GIC_CPU 0x10482000
82#define EXYNOS5_PA_GIC_DIST 0x10490000 85#define EXYNOS5_PA_GIC_DIST 0x10481000
83 86
84#define EXYNOS4_PA_COREPERI 0x10500000 87#define EXYNOS4_PA_COREPERI 0x10500000
85#define EXYNOS4_PA_TWD 0x10500600 88#define EXYNOS4_PA_TWD 0x10500600
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
index dba83e91f0fd..b78b5f3ad9c0 100644
--- a/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -322,6 +322,8 @@
322#define EXYNOS5_CLKSRC_CDREX EXYNOS_CLKREG(0x20200) 322#define EXYNOS5_CLKSRC_CDREX EXYNOS_CLKREG(0x20200)
323#define EXYNOS5_CLKDIV_CDREX EXYNOS_CLKREG(0x20500) 323#define EXYNOS5_CLKDIV_CDREX EXYNOS_CLKREG(0x20500)
324 324
325#define EXYNOS5_PLL_DIV2_SEL EXYNOS_CLKREG(0x20A24)
326
325#define EXYNOS5_EPLL_LOCK EXYNOS_CLKREG(0x10030) 327#define EXYNOS5_EPLL_LOCK EXYNOS_CLKREG(0x10030)
326 328
327#define EXYNOS5_EPLLCON0_LOCKED_SHIFT (29) 329#define EXYNOS5_EPLLCON0_LOCKED_SHIFT (29)
diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
index d457d052a420..4dbb8629b200 100644
--- a/arch/arm/mach-exynos/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
@@ -180,7 +180,7 @@
180 180
181#define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0) 181#define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0)
182 182
183/* Only for EXYNOS4212 */ 183/* Only for EXYNOS4x12 */
184#define S5P_ISP_ARM_LOWPWR S5P_PMUREG(0x1050) 184#define S5P_ISP_ARM_LOWPWR S5P_PMUREG(0x1050)
185#define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR S5P_PMUREG(0x1054) 185#define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR S5P_PMUREG(0x1054)
186#define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR S5P_PMUREG(0x1058) 186#define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR S5P_PMUREG(0x1058)
@@ -221,4 +221,12 @@
221#define S5P_SECSS_MEM_OPTION S5P_PMUREG(0x2EC8) 221#define S5P_SECSS_MEM_OPTION S5P_PMUREG(0x2EC8)
222#define S5P_ROTATOR_MEM_OPTION S5P_PMUREG(0x2F48) 222#define S5P_ROTATOR_MEM_OPTION S5P_PMUREG(0x2F48)
223 223
224/* Only for EXYNOS4412 */
225#define S5P_ARM_CORE2_LOWPWR S5P_PMUREG(0x1020)
226#define S5P_DIS_IRQ_CORE2 S5P_PMUREG(0x1024)
227#define S5P_DIS_IRQ_CENTRAL2 S5P_PMUREG(0x1028)
228#define S5P_ARM_CORE3_LOWPWR S5P_PMUREG(0x1030)
229#define S5P_DIS_IRQ_CORE3 S5P_PMUREG(0x1034)
230#define S5P_DIS_IRQ_CENTRAL3 S5P_PMUREG(0x1038)
231
224#endif /* __ASM_ARCH_REGS_PMU_H */ 232#endif /* __ASM_ARCH_REGS_PMU_H */
diff --git a/arch/arm/mach-exynos/include/mach/spi-clocks.h b/arch/arm/mach-exynos/include/mach/spi-clocks.h
index 576efdf6d091..c71a5fba6a84 100644
--- a/arch/arm/mach-exynos/include/mach/spi-clocks.h
+++ b/arch/arm/mach-exynos/include/mach/spi-clocks.h
@@ -11,6 +11,6 @@
11#define __ASM_ARCH_SPI_CLKS_H __FILE__ 11#define __ASM_ARCH_SPI_CLKS_H __FILE__
12 12
13/* Must source from SCLK_SPI */ 13/* Must source from SCLK_SPI */
14#define EXYNOS4_SPI_SRCCLK_SCLK 0 14#define EXYNOS_SPI_SRCCLK_SCLK 0
15 15
16#endif /* __ASM_ARCH_SPI_CLKS_H */ 16#endif /* __ASM_ARCH_SPI_CLKS_H */
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 4711c8920e37..cf5d2228e998 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -43,6 +43,10 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
43 "exynos4210-uart.2", NULL), 43 "exynos4210-uart.2", NULL),
44 OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART3, 44 OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART3,
45 "exynos4210-uart.3", NULL), 45 "exynos4210-uart.3", NULL),
46 OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(0),
47 "s3c2440-i2c.0", NULL),
48 OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
49 "s3c2440-i2c.1", NULL),
46 OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL), 50 OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
47 OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL), 51 OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
48 OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL), 52 OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
index 897d9a9cf226..b601fb8a408b 100644
--- a/arch/arm/mach-exynos/mct.c
+++ b/arch/arm/mach-exynos/mct.c
@@ -388,6 +388,7 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
388{ 388{
389 struct mct_clock_event_device *mevt; 389 struct mct_clock_event_device *mevt;
390 unsigned int cpu = smp_processor_id(); 390 unsigned int cpu = smp_processor_id();
391 int mct_lx_irq;
391 392
392 mevt = this_cpu_ptr(&percpu_mct_tick); 393 mevt = this_cpu_ptr(&percpu_mct_tick);
393 mevt->evt = evt; 394 mevt->evt = evt;
@@ -414,14 +415,18 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
414 415
415 if (mct_int_type == MCT_INT_SPI) { 416 if (mct_int_type == MCT_INT_SPI) {
416 if (cpu == 0) { 417 if (cpu == 0) {
418 mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L0 :
419 EXYNOS5_IRQ_MCT_L0;
417 mct_tick0_event_irq.dev_id = mevt; 420 mct_tick0_event_irq.dev_id = mevt;
418 evt->irq = EXYNOS4_IRQ_MCT_L0; 421 evt->irq = mct_lx_irq;
419 setup_irq(EXYNOS4_IRQ_MCT_L0, &mct_tick0_event_irq); 422 setup_irq(mct_lx_irq, &mct_tick0_event_irq);
420 } else { 423 } else {
424 mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L1 :
425 EXYNOS5_IRQ_MCT_L1;
421 mct_tick1_event_irq.dev_id = mevt; 426 mct_tick1_event_irq.dev_id = mevt;
422 evt->irq = EXYNOS4_IRQ_MCT_L1; 427 evt->irq = mct_lx_irq;
423 setup_irq(EXYNOS4_IRQ_MCT_L1, &mct_tick1_event_irq); 428 setup_irq(mct_lx_irq, &mct_tick1_event_irq);
424 irq_set_affinity(EXYNOS4_IRQ_MCT_L1, cpumask_of(1)); 429 irq_set_affinity(mct_lx_irq, cpumask_of(1));
425 } 430 }
426 } else { 431 } else {
427 enable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, 0); 432 enable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, 0);
@@ -473,7 +478,7 @@ static void __init exynos4_timer_resources(void)
473 478
474static void __init exynos4_timer_init(void) 479static void __init exynos4_timer_init(void)
475{ 480{
476 if (soc_is_exynos4210()) 481 if ((soc_is_exynos4210()) || (soc_is_exynos5250()))
477 mct_int_type = MCT_INT_SPI; 482 mct_int_type = MCT_INT_SPI;
478 else 483 else
479 mct_int_type = MCT_INT_PPI; 484 mct_int_type = MCT_INT_PPI;
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 428cfeb57724..563dea9a6dbb 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -275,7 +275,7 @@ static void exynos4_restore_pll(void)
275 275
276static struct subsys_interface exynos4_pm_interface = { 276static struct subsys_interface exynos4_pm_interface = {
277 .name = "exynos4_pm", 277 .name = "exynos4_pm",
278 .subsys = &exynos4_subsys, 278 .subsys = &exynos_subsys,
279 .add_dev = exynos4_pm_add, 279 .add_dev = exynos4_pm_add,
280}; 280};
281 281
@@ -313,7 +313,7 @@ static int exynos4_pm_suspend(void)
313 tmp &= ~S5P_CENTRAL_LOWPWR_CFG; 313 tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
314 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); 314 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
315 315
316 if (soc_is_exynos4212()) { 316 if (soc_is_exynos4212() || soc_is_exynos4412()) {
317 tmp = __raw_readl(S5P_CENTRAL_SEQ_OPTION); 317 tmp = __raw_readl(S5P_CENTRAL_SEQ_OPTION);
318 tmp &= ~(S5P_USE_STANDBYWFI_ISP_ARM | 318 tmp &= ~(S5P_USE_STANDBYWFI_ISP_ARM |
319 S5P_USE_STANDBYWFE_ISP_ARM); 319 S5P_USE_STANDBYWFE_ISP_ARM);
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index bba48f5c3e8f..77c6815eebee 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -94,7 +94,7 @@ static struct exynos4_pmu_conf exynos4210_pmu_config[] = {
94 { PMU_TABLE_END,}, 94 { PMU_TABLE_END,},
95}; 95};
96 96
97static struct exynos4_pmu_conf exynos4212_pmu_config[] = { 97static struct exynos4_pmu_conf exynos4x12_pmu_config[] = {
98 { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } }, 98 { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } },
99 { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } }, 99 { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } },
100 { S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } }, 100 { S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } },
@@ -202,6 +202,16 @@ static struct exynos4_pmu_conf exynos4212_pmu_config[] = {
202 { PMU_TABLE_END,}, 202 { PMU_TABLE_END,},
203}; 203};
204 204
205static struct exynos4_pmu_conf exynos4412_pmu_config[] = {
206 { S5P_ARM_CORE2_LOWPWR, { 0x0, 0x0, 0x2 } },
207 { S5P_DIS_IRQ_CORE2, { 0x0, 0x0, 0x0 } },
208 { S5P_DIS_IRQ_CENTRAL2, { 0x0, 0x0, 0x0 } },
209 { S5P_ARM_CORE3_LOWPWR, { 0x0, 0x0, 0x2 } },
210 { S5P_DIS_IRQ_CORE3, { 0x0, 0x0, 0x0 } },
211 { S5P_DIS_IRQ_CENTRAL3, { 0x0, 0x0, 0x0 } },
212 { PMU_TABLE_END,},
213};
214
205void exynos4_sys_powerdown_conf(enum sys_powerdown mode) 215void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
206{ 216{
207 unsigned int i; 217 unsigned int i;
@@ -209,6 +219,12 @@ void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
209 for (i = 0; (exynos4_pmu_config[i].reg != PMU_TABLE_END) ; i++) 219 for (i = 0; (exynos4_pmu_config[i].reg != PMU_TABLE_END) ; i++)
210 __raw_writel(exynos4_pmu_config[i].val[mode], 220 __raw_writel(exynos4_pmu_config[i].val[mode],
211 exynos4_pmu_config[i].reg); 221 exynos4_pmu_config[i].reg);
222
223 if (soc_is_exynos4412()) {
224 for (i = 0; exynos4412_pmu_config[i].reg != PMU_TABLE_END ; i++)
225 __raw_writel(exynos4412_pmu_config[i].val[mode],
226 exynos4412_pmu_config[i].reg);
227 }
212} 228}
213 229
214static int __init exynos4_pmu_init(void) 230static int __init exynos4_pmu_init(void)
@@ -218,9 +234,9 @@ static int __init exynos4_pmu_init(void)
218 if (soc_is_exynos4210()) { 234 if (soc_is_exynos4210()) {
219 exynos4_pmu_config = exynos4210_pmu_config; 235 exynos4_pmu_config = exynos4210_pmu_config;
220 pr_info("EXYNOS4210 PMU Initialize\n"); 236 pr_info("EXYNOS4210 PMU Initialize\n");
221 } else if (soc_is_exynos4212()) { 237 } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
222 exynos4_pmu_config = exynos4212_pmu_config; 238 exynos4_pmu_config = exynos4x12_pmu_config;
223 pr_info("EXYNOS4212 PMU Initialize\n"); 239 pr_info("EXYNOS4x12 PMU Initialize\n");
224 } else { 240 } else {
225 pr_info("EXYNOS4: PMU not supported\n"); 241 pr_info("EXYNOS4: PMU not supported\n");
226 } 242 }
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index b34287ab5afd..e24961109b70 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -518,6 +518,11 @@ config S3C2443_DMA
518 help 518 help
519 Internal config node for S3C2443 DMA support 519 Internal config node for S3C2443 DMA support
520 520
521config S3C2443_SETUP_SPI
522 bool
523 help
524 Common setup code for SPI GPIO configurations
525
521endif # CPU_S3C2443 || CPU_S3C2416 526endif # CPU_S3C2443 || CPU_S3C2416
522 527
523if CPU_S3C2443 528if CPU_S3C2443
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile
index 270a0b6f4f22..0ab6ab15da4c 100644
--- a/arch/arm/mach-s3c24xx/Makefile
+++ b/arch/arm/mach-s3c24xx/Makefile
@@ -97,5 +97,6 @@ obj-$(CONFIG_MACH_OSIRIS_DVS) += mach-osiris-dvs.o
97# device setup 97# device setup
98 98
99obj-$(CONFIG_S3C2416_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o 99obj-$(CONFIG_S3C2416_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
100obj-$(CONFIG_S3C2443_SETUP_SPI) += setup-spi.o
100obj-$(CONFIG_ARCH_S3C24XX) += setup-i2c.o 101obj-$(CONFIG_ARCH_S3C24XX) += setup-i2c.o
101obj-$(CONFIG_S3C24XX_SETUP_TS) += setup-ts.o 102obj-$(CONFIG_S3C24XX_SETUP_TS) += setup-ts.o
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2416.c b/arch/arm/mach-s3c24xx/clock-s3c2416.c
index dbc9ab4aaca2..8702ecfaab30 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2416.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2416.c
@@ -144,6 +144,7 @@ static struct clk_lookup s3c2416_clk_lookup[] = {
144 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk), 144 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk),
145 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk), 145 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk),
146 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk), 146 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk),
147 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &hsspi_mux.clk),
147}; 148};
148 149
149void __init s3c2416_init_clocks(int xtal) 150void __init s3c2416_init_clocks(int xtal)
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2443.c b/arch/arm/mach-s3c24xx/clock-s3c2443.c
index efb3ac359566..a4c5a520d994 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2443.c
@@ -179,6 +179,11 @@ static struct clk *clks[] __initdata = {
179 &clk_hsmmc, 179 &clk_hsmmc,
180}; 180};
181 181
182static struct clk_lookup s3c2443_clk_lookup[] = {
183 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_hsmmc),
184 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_hsspi.clk),
185};
186
182void __init s3c2443_init_clocks(int xtal) 187void __init s3c2443_init_clocks(int xtal)
183{ 188{
184 unsigned long epllcon = __raw_readl(S3C2443_EPLLCON); 189 unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
@@ -210,6 +215,7 @@ void __init s3c2443_init_clocks(int xtal)
210 215
211 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 216 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
212 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 217 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
218 clkdev_add_table(s3c2443_clk_lookup, ARRAY_SIZE(s3c2443_clk_lookup));
213 219
214 s3c_pwmclk_init(); 220 s3c_pwmclk_init();
215} 221}
diff --git a/arch/arm/mach-s3c24xx/common-s3c2443.c b/arch/arm/mach-s3c24xx/common-s3c2443.c
index 460431589f39..aeeb2be283fa 100644
--- a/arch/arm/mach-s3c24xx/common-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/common-s3c2443.c
@@ -424,11 +424,6 @@ static struct clk init_clocks_off[] = {
424 .enable = s3c2443_clkcon_enable_p, 424 .enable = s3c2443_clkcon_enable_p,
425 .ctrlbit = S3C2443_PCLKCON_IIS, 425 .ctrlbit = S3C2443_PCLKCON_IIS,
426 }, { 426 }, {
427 .name = "hsspi",
428 .parent = &clk_p,
429 .enable = s3c2443_clkcon_enable_p,
430 .ctrlbit = S3C2443_PCLKCON_HSSPI,
431 }, {
432 .name = "adc", 427 .name = "adc",
433 .parent = &clk_p, 428 .parent = &clk_p,
434 .enable = s3c2443_clkcon_enable_p, 429 .enable = s3c2443_clkcon_enable_p,
@@ -562,6 +557,14 @@ static struct clk hsmmc1_clk = {
562 .ctrlbit = S3C2443_HCLKCON_HSMMC, 557 .ctrlbit = S3C2443_HCLKCON_HSMMC,
563}; 558};
564 559
560static struct clk hsspi_clk = {
561 .name = "spi",
562 .devname = "s3c64xx-spi.0",
563 .parent = &clk_p,
564 .enable = s3c2443_clkcon_enable_p,
565 .ctrlbit = S3C2443_PCLKCON_HSSPI,
566};
567
565/* EPLLCON compatible enough to get on/off information */ 568/* EPLLCON compatible enough to get on/off information */
566 569
567void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll) 570void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll)
@@ -612,6 +615,7 @@ static struct clk *clks[] __initdata = {
612 &clk_usb_bus, 615 &clk_usb_bus,
613 &clk_armdiv, 616 &clk_armdiv,
614 &hsmmc1_clk, 617 &hsmmc1_clk,
618 &hsspi_clk,
615}; 619};
616 620
617static struct clksrc_clk *clksrcs[] __initdata = { 621static struct clksrc_clk *clksrcs[] __initdata = {
@@ -629,6 +633,7 @@ static struct clk_lookup s3c2443_clk_lookup[] = {
629 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p), 633 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
630 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk), 634 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk),
631 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk), 635 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk),
636 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &hsspi_clk),
632}; 637};
633 638
634void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, 639void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2443.c b/arch/arm/mach-s3c24xx/dma-s3c2443.c
index e227c472a40a..2d94228d2866 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2443.c
@@ -55,12 +55,20 @@ static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
55 .name = "sdi", 55 .name = "sdi",
56 .channels = MAP(S3C2443_DMAREQSEL_SDI), 56 .channels = MAP(S3C2443_DMAREQSEL_SDI),
57 }, 57 },
58 [DMACH_SPI0] = { 58 [DMACH_SPI0_RX] = {
59 .name = "spi0", 59 .name = "spi0-rx",
60 .channels = MAP(S3C2443_DMAREQSEL_SPI0RX),
61 },
62 [DMACH_SPI0_TX] = {
63 .name = "spi0-tx",
60 .channels = MAP(S3C2443_DMAREQSEL_SPI0TX), 64 .channels = MAP(S3C2443_DMAREQSEL_SPI0TX),
61 }, 65 },
62 [DMACH_SPI1] = { /* only on S3C2443/S3C2450 */ 66 [DMACH_SPI1_RX] = { /* only on S3C2443/S3C2450 */
63 .name = "spi1", 67 .name = "spi1-rx",
68 .channels = MAP(S3C2443_DMAREQSEL_SPI1RX),
69 },
70 [DMACH_SPI1_TX] = { /* only on S3C2443/S3C2450 */
71 .name = "spi1-tx",
64 .channels = MAP(S3C2443_DMAREQSEL_SPI1TX), 72 .channels = MAP(S3C2443_DMAREQSEL_SPI1TX),
65 }, 73 },
66 [DMACH_UART0] = { 74 [DMACH_UART0] = {
diff --git a/arch/arm/mach-s3c24xx/include/mach/dma.h b/arch/arm/mach-s3c24xx/include/mach/dma.h
index acbdfecd4186..454831b66037 100644
--- a/arch/arm/mach-s3c24xx/include/mach/dma.h
+++ b/arch/arm/mach-s3c24xx/include/mach/dma.h
@@ -47,6 +47,10 @@ enum dma_ch {
47 DMACH_UART2_SRC2, 47 DMACH_UART2_SRC2,
48 DMACH_UART3, /* s3c2443 has extra uart */ 48 DMACH_UART3, /* s3c2443 has extra uart */
49 DMACH_UART3_SRC2, 49 DMACH_UART3_SRC2,
50 DMACH_SPI0_TX, /* s3c2443/2416/2450 hsspi0 */
51 DMACH_SPI0_RX, /* s3c2443/2416/2450 hsspi0 */
52 DMACH_SPI1_TX, /* s3c2443/2450 hsspi1 */
53 DMACH_SPI1_RX, /* s3c2443/2450 hsspi1 */
50 DMACH_MAX, /* the end entry */ 54 DMACH_MAX, /* the end entry */
51}; 55};
52 56
diff --git a/arch/arm/mach-s3c24xx/include/mach/map.h b/arch/arm/mach-s3c24xx/include/mach/map.h
index 78ae807f1281..8ba381f2dbe1 100644
--- a/arch/arm/mach-s3c24xx/include/mach/map.h
+++ b/arch/arm/mach-s3c24xx/include/mach/map.h
@@ -98,6 +98,8 @@
98 98
99/* SPI */ 99/* SPI */
100#define S3C2410_PA_SPI (0x59000000) 100#define S3C2410_PA_SPI (0x59000000)
101#define S3C2443_PA_SPI0 (0x52000000)
102#define S3C2443_PA_SPI1 S3C2410_PA_SPI
101 103
102/* SDI */ 104/* SDI */
103#define S3C2410_PA_SDI (0x5A000000) 105#define S3C2410_PA_SDI (0x5A000000)
@@ -162,4 +164,7 @@
162#define S3C_PA_WDT S3C2410_PA_WATCHDOG 164#define S3C_PA_WDT S3C2410_PA_WATCHDOG
163#define S3C_PA_NAND S3C24XX_PA_NAND 165#define S3C_PA_NAND S3C24XX_PA_NAND
164 166
167#define S3C_PA_SPI0 S3C2443_PA_SPI0
168#define S3C_PA_SPI1 S3C2443_PA_SPI1
169
165#endif /* __ASM_ARCH_MAP_H */ 170#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s3c24xx/setup-spi.c b/arch/arm/mach-s3c24xx/setup-spi.c
new file mode 100644
index 000000000000..5712c85f39b1
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/setup-spi.c
@@ -0,0 +1,39 @@
1/*
2 * HS-SPI device setup for S3C2443/S3C2416
3 *
4 * Copyright (C) 2011 Samsung Electronics Ltd.
5 * http://www.samsung.com/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/gpio.h>
13#include <linux/platform_device.h>
14
15#include <plat/gpio-cfg.h>
16#include <plat/s3c64xx-spi.h>
17
18#include <mach/hardware.h>
19#include <mach/regs-gpio.h>
20
21#ifdef CONFIG_S3C64XX_DEV_SPI0
22struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
23 .fifo_lvl_mask = 0x7f,
24 .rx_lvl_offset = 13,
25 .tx_st_done = 21,
26 .high_speed = 1,
27};
28
29int s3c64xx_spi0_cfg_gpio(struct platform_device *pdev)
30{
31 /* enable hsspi bit in misccr */
32 s3c2410_modify_misccr(S3C2416_MISCCR_HSSPI_EN2, 1);
33
34 s3c_gpio_cfgall_range(S3C2410_GPE(11), 3,
35 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
36
37 return 0;
38}
39#endif
diff --git a/arch/arm/mach-spear13xx/Kconfig b/arch/arm/mach-spear13xx/Kconfig
new file mode 100644
index 000000000000..eaadc66d96b3
--- /dev/null
+++ b/arch/arm/mach-spear13xx/Kconfig
@@ -0,0 +1,20 @@
1#
2# SPEAr13XX Machine configuration file
3#
4
5if ARCH_SPEAR13XX
6
7menu "SPEAr13xx Implementations"
8config MACH_SPEAR1310
9 bool "SPEAr1310 Machine support with Device Tree"
10 select PINCTRL_SPEAR1310
11 help
12 Supports ST SPEAr1310 machine configured via the device-tree
13
14config MACH_SPEAR1340
15 bool "SPEAr1340 Machine support with Device Tree"
16 select PINCTRL_SPEAR1340
17 help
18 Supports ST SPEAr1340 machine configured via the device-tree
19endmenu
20endif #ARCH_SPEAR13XX
diff --git a/arch/arm/mach-spear13xx/Makefile b/arch/arm/mach-spear13xx/Makefile
new file mode 100644
index 000000000000..3435ea78c15d
--- /dev/null
+++ b/arch/arm/mach-spear13xx/Makefile
@@ -0,0 +1,10 @@
1#
2# Makefile for SPEAr13XX machine series
3#
4
5obj-$(CONFIG_SMP) += headsmp.o platsmp.o
6obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
7
8obj-$(CONFIG_ARCH_SPEAR13XX) += spear13xx.o
9obj-$(CONFIG_MACH_SPEAR1310) += spear1310.o
10obj-$(CONFIG_MACH_SPEAR1340) += spear1340.o
diff --git a/arch/arm/mach-spear13xx/Makefile.boot b/arch/arm/mach-spear13xx/Makefile.boot
new file mode 100644
index 000000000000..403efd7e6d27
--- /dev/null
+++ b/arch/arm/mach-spear13xx/Makefile.boot
@@ -0,0 +1,6 @@
1zreladdr-y += 0x00008000
2params_phys-y := 0x00000100
3initrd_phys-y := 0x00800000
4
5dtb-$(CONFIG_MACH_SPEAR1310) += spear1310-evb.dtb
6dtb-$(CONFIG_MACH_SPEAR1340) += spear1340-evb.dtb
diff --git a/arch/arm/mach-spear13xx/headsmp.S b/arch/arm/mach-spear13xx/headsmp.S
new file mode 100644
index 000000000000..ed85473a047f
--- /dev/null
+++ b/arch/arm/mach-spear13xx/headsmp.S
@@ -0,0 +1,47 @@
1/*
2 * arch/arm/mach-spear13XX/headsmp.S
3 *
4 * Picked from realview
5 * Copyright (c) 2012 ST Microelectronics Limited
6 * Shiraz Hashim <shiraz.hashim@st.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/linkage.h>
14#include <linux/init.h>
15
16 __INIT
17
18/*
19 * spear13xx specific entry point for secondary CPUs. This provides
20 * a "holding pen" into which all secondary cores are held until we're
21 * ready for them to initialise.
22 */
23ENTRY(spear13xx_secondary_startup)
24 mrc p15, 0, r0, c0, c0, 5
25 and r0, r0, #15
26 adr r4, 1f
27 ldmia r4, {r5, r6}
28 sub r4, r4, r5
29 add r6, r6, r4
30pen: ldr r7, [r6]
31 cmp r7, r0
32 bne pen
33
34 /* re-enable coherency */
35 mrc p15, 0, r0, c1, c0, 1
36 orr r0, r0, #(1 << 6) | (1 << 0)
37 mcr p15, 0, r0, c1, c0, 1
38 /*
39 * we've been released from the holding pen: secondary_stack
40 * should now contain the SVC stack for this core
41 */
42 b secondary_startup
43
44 .align
451: .long .
46 .long pen_release
47ENDPROC(spear13xx_secondary_startup)
diff --git a/arch/arm/mach-spear13xx/hotplug.c b/arch/arm/mach-spear13xx/hotplug.c
new file mode 100644
index 000000000000..5c6867b46d09
--- /dev/null
+++ b/arch/arm/mach-spear13xx/hotplug.c
@@ -0,0 +1,119 @@
1/*
2 * linux/arch/arm/mach-spear13xx/hotplug.c
3 *
4 * Copyright (C) 2012 ST Microelectronics Ltd.
5 * Deepak Sikri <deepak.sikri@st.com>
6 *
7 * based upon linux/arch/arm/mach-realview/hotplug.c
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#include <linux/kernel.h>
14#include <linux/errno.h>
15#include <linux/smp.h>
16#include <asm/cacheflush.h>
17#include <asm/cp15.h>
18#include <asm/smp_plat.h>
19
20extern volatile int pen_release;
21
22static inline void cpu_enter_lowpower(void)
23{
24 unsigned int v;
25
26 flush_cache_all();
27 asm volatile(
28 " mcr p15, 0, %1, c7, c5, 0\n"
29 " dsb\n"
30 /*
31 * Turn off coherency
32 */
33 " mrc p15, 0, %0, c1, c0, 1\n"
34 " bic %0, %0, #0x20\n"
35 " mcr p15, 0, %0, c1, c0, 1\n"
36 " mrc p15, 0, %0, c1, c0, 0\n"
37 " bic %0, %0, %2\n"
38 " mcr p15, 0, %0, c1, c0, 0\n"
39 : "=&r" (v)
40 : "r" (0), "Ir" (CR_C)
41 : "cc", "memory");
42}
43
44static inline void cpu_leave_lowpower(void)
45{
46 unsigned int v;
47
48 asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
49 " orr %0, %0, %1\n"
50 " mcr p15, 0, %0, c1, c0, 0\n"
51 " mrc p15, 0, %0, c1, c0, 1\n"
52 " orr %0, %0, #0x20\n"
53 " mcr p15, 0, %0, c1, c0, 1\n"
54 : "=&r" (v)
55 : "Ir" (CR_C)
56 : "cc");
57}
58
59static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
60{
61 for (;;) {
62 wfi();
63
64 if (pen_release == cpu) {
65 /*
66 * OK, proper wakeup, we're done
67 */
68 break;
69 }
70
71 /*
72 * Getting here, means that we have come out of WFI without
73 * having been woken up - this shouldn't happen
74 *
75 * Just note it happening - when we're woken, we can report
76 * its occurrence.
77 */
78 (*spurious)++;
79 }
80}
81
82int platform_cpu_kill(unsigned int cpu)
83{
84 return 1;
85}
86
87/*
88 * platform-specific code to shutdown a CPU
89 *
90 * Called with IRQs disabled
91 */
92void __cpuinit platform_cpu_die(unsigned int cpu)
93{
94 int spurious = 0;
95
96 /*
97 * we're ready for shutdown now, so do it
98 */
99 cpu_enter_lowpower();
100 platform_do_lowpower(cpu, &spurious);
101
102 /*
103 * bring this CPU back into the world of cache
104 * coherency, and then restore interrupts
105 */
106 cpu_leave_lowpower();
107
108 if (spurious)
109 pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
110}
111
112int platform_cpu_disable(unsigned int cpu)
113{
114 /*
115 * we don't allow CPU 0 to be shutdown (it is still too special
116 * e.g. clock tick interrupts)
117 */
118 return cpu == 0 ? -EPERM : 0;
119}
diff --git a/arch/arm/mach-spear13xx/include/mach/debug-macro.S b/arch/arm/mach-spear13xx/include/mach/debug-macro.S
new file mode 100644
index 000000000000..ea1564609bd4
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/debug-macro.S
@@ -0,0 +1,14 @@
1/*
2 * arch/arm/mach-spear13xx/include/mach/debug-macro.S
3 *
4 * Debugging macro include header spear13xx machine family
5 *
6 * Copyright (C) 2012 ST Microelectronics
7 * Viresh Kumar <viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-spear13xx/include/mach/dma.h b/arch/arm/mach-spear13xx/include/mach/dma.h
new file mode 100644
index 000000000000..383ab04dc6c9
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/dma.h
@@ -0,0 +1,128 @@
1/*
2 * arch/arm/mach-spear13xx/include/mach/dma.h
3 *
4 * DMA information for SPEAr13xx machine family
5 *
6 * Copyright (C) 2012 ST Microelectronics
7 * Viresh Kumar <viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __MACH_DMA_H
15#define __MACH_DMA_H
16
17/* request id of all the peripherals */
18enum dma_master_info {
19 /* Accessible from only one master */
20 DMA_MASTER_MCIF = 0,
21 DMA_MASTER_FSMC = 1,
22 /* Accessible from both 0 & 1 */
23 DMA_MASTER_MEMORY = 0,
24 DMA_MASTER_ADC = 0,
25 DMA_MASTER_UART0 = 0,
26 DMA_MASTER_SSP0 = 0,
27 DMA_MASTER_I2C0 = 0,
28
29#ifdef CONFIG_MACH_SPEAR1310
30 /* Accessible from only one master */
31 SPEAR1310_DMA_MASTER_JPEG = 1,
32
33 /* Accessible from both 0 & 1 */
34 SPEAR1310_DMA_MASTER_I2S = 0,
35 SPEAR1310_DMA_MASTER_UART1 = 0,
36 SPEAR1310_DMA_MASTER_UART2 = 0,
37 SPEAR1310_DMA_MASTER_UART3 = 0,
38 SPEAR1310_DMA_MASTER_UART4 = 0,
39 SPEAR1310_DMA_MASTER_UART5 = 0,
40 SPEAR1310_DMA_MASTER_I2C1 = 0,
41 SPEAR1310_DMA_MASTER_I2C2 = 0,
42 SPEAR1310_DMA_MASTER_I2C3 = 0,
43 SPEAR1310_DMA_MASTER_I2C4 = 0,
44 SPEAR1310_DMA_MASTER_I2C5 = 0,
45 SPEAR1310_DMA_MASTER_I2C6 = 0,
46 SPEAR1310_DMA_MASTER_I2C7 = 0,
47 SPEAR1310_DMA_MASTER_SSP1 = 0,
48#endif
49
50#ifdef CONFIG_MACH_SPEAR1340
51 /* Accessible from only one master */
52 SPEAR1340_DMA_MASTER_I2S_PLAY = 1,
53 SPEAR1340_DMA_MASTER_I2S_REC = 1,
54 SPEAR1340_DMA_MASTER_I2C1 = 1,
55 SPEAR1340_DMA_MASTER_UART1 = 1,
56
57 /* following are accessible from both master 0 & 1 */
58 SPEAR1340_DMA_MASTER_SPDIF = 0,
59 SPEAR1340_DMA_MASTER_CAM = 1,
60 SPEAR1340_DMA_MASTER_VIDEO_IN = 0,
61 SPEAR1340_DMA_MASTER_MALI = 0,
62#endif
63};
64
65enum request_id {
66 DMA_REQ_ADC = 0,
67 DMA_REQ_SSP0_TX = 4,
68 DMA_REQ_SSP0_RX = 5,
69 DMA_REQ_UART0_TX = 6,
70 DMA_REQ_UART0_RX = 7,
71 DMA_REQ_I2C0_TX = 8,
72 DMA_REQ_I2C0_RX = 9,
73
74#ifdef CONFIG_MACH_SPEAR1310
75 SPEAR1310_DMA_REQ_FROM_JPEG = 2,
76 SPEAR1310_DMA_REQ_TO_JPEG = 3,
77 SPEAR1310_DMA_REQ_I2S_TX = 10,
78 SPEAR1310_DMA_REQ_I2S_RX = 11,
79
80 SPEAR1310_DMA_REQ_I2C1_RX = 0,
81 SPEAR1310_DMA_REQ_I2C1_TX = 1,
82 SPEAR1310_DMA_REQ_I2C2_RX = 2,
83 SPEAR1310_DMA_REQ_I2C2_TX = 3,
84 SPEAR1310_DMA_REQ_I2C3_RX = 4,
85 SPEAR1310_DMA_REQ_I2C3_TX = 5,
86 SPEAR1310_DMA_REQ_I2C4_RX = 6,
87 SPEAR1310_DMA_REQ_I2C4_TX = 7,
88 SPEAR1310_DMA_REQ_I2C5_RX = 8,
89 SPEAR1310_DMA_REQ_I2C5_TX = 9,
90 SPEAR1310_DMA_REQ_I2C6_RX = 10,
91 SPEAR1310_DMA_REQ_I2C6_TX = 11,
92 SPEAR1310_DMA_REQ_UART1_RX = 12,
93 SPEAR1310_DMA_REQ_UART1_TX = 13,
94 SPEAR1310_DMA_REQ_UART2_RX = 14,
95 SPEAR1310_DMA_REQ_UART2_TX = 15,
96 SPEAR1310_DMA_REQ_UART5_RX = 16,
97 SPEAR1310_DMA_REQ_UART5_TX = 17,
98 SPEAR1310_DMA_REQ_SSP1_RX = 18,
99 SPEAR1310_DMA_REQ_SSP1_TX = 19,
100 SPEAR1310_DMA_REQ_I2C7_RX = 20,
101 SPEAR1310_DMA_REQ_I2C7_TX = 21,
102 SPEAR1310_DMA_REQ_UART3_RX = 28,
103 SPEAR1310_DMA_REQ_UART3_TX = 29,
104 SPEAR1310_DMA_REQ_UART4_RX = 30,
105 SPEAR1310_DMA_REQ_UART4_TX = 31,
106#endif
107
108#ifdef CONFIG_MACH_SPEAR1340
109 SPEAR1340_DMA_REQ_SPDIF_TX = 2,
110 SPEAR1340_DMA_REQ_SPDIF_RX = 3,
111 SPEAR1340_DMA_REQ_I2S_TX = 10,
112 SPEAR1340_DMA_REQ_I2S_RX = 11,
113 SPEAR1340_DMA_REQ_UART1_TX = 12,
114 SPEAR1340_DMA_REQ_UART1_RX = 13,
115 SPEAR1340_DMA_REQ_I2C1_TX = 14,
116 SPEAR1340_DMA_REQ_I2C1_RX = 15,
117 SPEAR1340_DMA_REQ_CAM0_EVEN = 0,
118 SPEAR1340_DMA_REQ_CAM0_ODD = 1,
119 SPEAR1340_DMA_REQ_CAM1_EVEN = 2,
120 SPEAR1340_DMA_REQ_CAM1_ODD = 3,
121 SPEAR1340_DMA_REQ_CAM2_EVEN = 4,
122 SPEAR1340_DMA_REQ_CAM2_ODD = 5,
123 SPEAR1340_DMA_REQ_CAM3_EVEN = 6,
124 SPEAR1340_DMA_REQ_CAM3_ODD = 7,
125#endif
126};
127
128#endif /* __MACH_DMA_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/generic.h b/arch/arm/mach-spear13xx/include/mach/generic.h
new file mode 100644
index 000000000000..6d8c45b9f298
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/generic.h
@@ -0,0 +1,49 @@
1/*
2 * arch/arm/mach-spear13xx/include/mach/generic.h
3 *
4 * spear13xx machine family generic header file
5 *
6 * Copyright (C) 2012 ST Microelectronics
7 * Viresh Kumar <viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __MACH_GENERIC_H
15#define __MACH_GENERIC_H
16
17#include <linux/dmaengine.h>
18#include <asm/mach/time.h>
19
20/* Add spear13xx structure declarations here */
21extern struct sys_timer spear13xx_timer;
22extern struct pl022_ssp_controller pl022_plat_data;
23extern struct dw_dma_platform_data dmac_plat_data;
24extern struct dw_dma_slave cf_dma_priv;
25extern struct dw_dma_slave nand_read_dma_priv;
26extern struct dw_dma_slave nand_write_dma_priv;
27
28/* Add spear13xx family function declarations here */
29void __init spear_setup_of_timer(void);
30void __init spear13xx_map_io(void);
31void __init spear13xx_dt_init_irq(void);
32void __init spear13xx_l2x0_init(void);
33bool dw_dma_filter(struct dma_chan *chan, void *slave);
34void spear_restart(char, const char *);
35void spear13xx_secondary_startup(void);
36
37#ifdef CONFIG_MACH_SPEAR1310
38void __init spear1310_clk_init(void);
39#else
40static inline void spear1310_clk_init(void) {}
41#endif
42
43#ifdef CONFIG_MACH_SPEAR1340
44void __init spear1340_clk_init(void);
45#else
46static inline void spear1340_clk_init(void) {}
47#endif
48
49#endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/gpio.h b/arch/arm/mach-spear13xx/include/mach/gpio.h
new file mode 100644
index 000000000000..cd6f4f86a56b
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/gpio.h
@@ -0,0 +1,19 @@
1/*
2 * arch/arm/mach-spear13xx/include/mach/gpio.h
3 *
4 * GPIO macros for SPEAr13xx machine family
5 *
6 * Copyright (C) 2012 ST Microelectronics
7 * Viresh Kumar <viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __MACH_GPIO_H
15#define __MACH_GPIO_H
16
17#include <plat/gpio.h>
18
19#endif /* __MACH_GPIO_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/hardware.h b/arch/arm/mach-spear13xx/include/mach/hardware.h
new file mode 100644
index 000000000000..40a8c178f10d
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/hardware.h
@@ -0,0 +1 @@
/* empty */
diff --git a/arch/arm/mach-spear13xx/include/mach/irqs.h b/arch/arm/mach-spear13xx/include/mach/irqs.h
new file mode 100644
index 000000000000..f542a24aa5f2
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/irqs.h
@@ -0,0 +1,20 @@
1/*
2 * arch/arm/mach-spear13xx/include/mach/irqs.h
3 *
4 * IRQ helper macros for spear13xx machine family
5 *
6 * Copyright (C) 2012 ST Microelectronics
7 * Viresh Kumar <viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __MACH_IRQS_H
15#define __MACH_IRQS_H
16
17#define IRQ_GIC_END 160
18#define NR_IRQS IRQ_GIC_END
19
20#endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/spear.h b/arch/arm/mach-spear13xx/include/mach/spear.h
new file mode 100644
index 000000000000..30c57ef72686
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/spear.h
@@ -0,0 +1,62 @@
1/*
2 * arch/arm/mach-spear13xx/include/mach/spear.h
3 *
4 * spear13xx Machine family specific definition
5 *
6 * Copyright (C) 2012 ST Microelectronics
7 * Viresh Kumar <viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __MACH_SPEAR13XX_H
15#define __MACH_SPEAR13XX_H
16
17#include <asm/memory.h>
18
19#define PERIP_GRP2_BASE UL(0xB3000000)
20#define VA_PERIP_GRP2_BASE UL(0xFE000000)
21#define MCIF_SDHCI_BASE UL(0xB3000000)
22#define SYSRAM0_BASE UL(0xB3800000)
23#define VA_SYSRAM0_BASE UL(0xFE800000)
24#define SYS_LOCATION (VA_SYSRAM0_BASE + 0x600)
25
26#define PERIP_GRP1_BASE UL(0xE0000000)
27#define VA_PERIP_GRP1_BASE UL(0xFD000000)
28#define UART_BASE UL(0xE0000000)
29#define VA_UART_BASE UL(0xFD000000)
30#define SSP_BASE UL(0xE0100000)
31#define MISC_BASE UL(0xE0700000)
32#define VA_MISC_BASE IOMEM(UL(0xFD700000))
33
34#define A9SM_AND_MPMC_BASE UL(0xEC000000)
35#define VA_A9SM_AND_MPMC_BASE UL(0xFC000000)
36
37/* A9SM peripheral offsets */
38#define A9SM_PERIP_BASE UL(0xEC800000)
39#define VA_A9SM_PERIP_BASE UL(0xFC800000)
40#define VA_SCU_BASE (VA_A9SM_PERIP_BASE + 0x00)
41
42#define L2CC_BASE UL(0xED000000)
43#define VA_L2CC_BASE IOMEM(UL(0xFB000000))
44
45/* others */
46#define DMAC0_BASE UL(0xEA800000)
47#define DMAC1_BASE UL(0xEB000000)
48#define MCIF_CF_BASE UL(0xB2800000)
49
50/* Devices present in SPEAr1310 */
51#ifdef CONFIG_MACH_SPEAR1310
52#define SPEAR1310_RAS_GRP1_BASE UL(0xD8000000)
53#define VA_SPEAR1310_RAS_GRP1_BASE UL(0xFA000000)
54#define SPEAR1310_RAS_BASE UL(0xD8400000)
55#define VA_SPEAR1310_RAS_BASE IOMEM(UL(0xFA400000))
56#endif /* CONFIG_MACH_SPEAR1310 */
57
58/* Debug uart for linux, will be used for debug and uncompress messages */
59#define SPEAR_DBG_UART_BASE UART_BASE
60#define VA_SPEAR_DBG_UART_BASE VA_UART_BASE
61
62#endif /* __MACH_SPEAR13XX_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/spear1310_misc_regs.h b/arch/arm/mach-spear13xx/include/mach/spear1310_misc_regs.h
new file mode 100644
index 000000000000..e69de29bb2d1
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/spear1310_misc_regs.h
diff --git a/arch/arm/mach-spear13xx/include/mach/spear1340_misc_regs.h b/arch/arm/mach-spear13xx/include/mach/spear1340_misc_regs.h
new file mode 100644
index 000000000000..e69de29bb2d1
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/spear1340_misc_regs.h
diff --git a/arch/arm/mach-spear13xx/include/mach/timex.h b/arch/arm/mach-spear13xx/include/mach/timex.h
new file mode 100644
index 000000000000..31af3e8d976e
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/timex.h
@@ -0,0 +1,19 @@
1/*
2 * arch/arm/mach-spear3xx/include/mach/timex.h
3 *
4 * SPEAr3XX machine family specific timex definitions
5 *
6 * Copyright (C) 2012 ST Microelectronics
7 * Viresh Kumar <viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __MACH_TIMEX_H
15#define __MACH_TIMEX_H
16
17#include <plat/timex.h>
18
19#endif /* __MACH_TIMEX_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/uncompress.h b/arch/arm/mach-spear13xx/include/mach/uncompress.h
new file mode 100644
index 000000000000..c7840896ae6e
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/uncompress.h
@@ -0,0 +1,19 @@
1/*
2 * arch/arm/mach-spear13xx/include/mach/uncompress.h
3 *
4 * Serial port stubs for kernel decompress status messages
5 *
6 * Copyright (C) 2012 ST Microelectronics
7 * Viresh Kumar <viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __MACH_UNCOMPRESS_H
15#define __MACH_UNCOMPRESS_H
16
17#include <plat/uncompress.h>
18
19#endif /* __MACH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-spear13xx/platsmp.c b/arch/arm/mach-spear13xx/platsmp.c
new file mode 100644
index 000000000000..f5d07f2663d7
--- /dev/null
+++ b/arch/arm/mach-spear13xx/platsmp.c
@@ -0,0 +1,127 @@
1/*
2 * arch/arm/mach-spear13xx/platsmp.c
3 *
4 * based upon linux/arch/arm/mach-realview/platsmp.c
5 *
6 * Copyright (C) 2012 ST Microelectronics Ltd.
7 * Shiraz Hashim <shiraz.hashim@st.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/delay.h>
15#include <linux/jiffies.h>
16#include <linux/io.h>
17#include <linux/smp.h>
18#include <asm/cacheflush.h>
19#include <asm/hardware/gic.h>
20#include <asm/smp_scu.h>
21#include <mach/spear.h>
22
23/*
24 * control for which core is the next to come out of the secondary
25 * boot "holding pen"
26 */
27volatile int __cpuinitdata pen_release = -1;
28static DEFINE_SPINLOCK(boot_lock);
29
30static void __iomem *scu_base = IOMEM(VA_SCU_BASE);
31extern void spear13xx_secondary_startup(void);
32
33void __cpuinit platform_secondary_init(unsigned int cpu)
34{
35 /*
36 * if any interrupts are already enabled for the primary
37 * core (e.g. timer irq), then they will not have been enabled
38 * for us: do so
39 */
40 gic_secondary_init(0);
41
42 /*
43 * let the primary processor know we're out of the
44 * pen, then head off into the C entry point
45 */
46 pen_release = -1;
47 smp_wmb();
48
49 /*
50 * Synchronise with the boot thread.
51 */
52 spin_lock(&boot_lock);
53 spin_unlock(&boot_lock);
54}
55
56int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
57{
58 unsigned long timeout;
59
60 /*
61 * set synchronisation state between this boot processor
62 * and the secondary one
63 */
64 spin_lock(&boot_lock);
65
66 /*
67 * The secondary processor is waiting to be released from
68 * the holding pen - release it, then wait for it to flag
69 * that it has been released by resetting pen_release.
70 *
71 * Note that "pen_release" is the hardware CPU ID, whereas
72 * "cpu" is Linux's internal ID.
73 */
74 pen_release = cpu;
75 flush_cache_all();
76 outer_flush_all();
77
78 timeout = jiffies + (1 * HZ);
79 while (time_before(jiffies, timeout)) {
80 smp_rmb();
81 if (pen_release == -1)
82 break;
83
84 udelay(10);
85 }
86
87 /*
88 * now the secondary core is starting up let it run its
89 * calibrations, then wait for it to finish
90 */
91 spin_unlock(&boot_lock);
92
93 return pen_release != -1 ? -ENOSYS : 0;
94}
95
96/*
97 * Initialise the CPU possible map early - this describes the CPUs
98 * which may be present or become present in the system.
99 */
100void __init smp_init_cpus(void)
101{
102 unsigned int i, ncores = scu_get_core_count(scu_base);
103
104 if (ncores > nr_cpu_ids) {
105 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
106 ncores, nr_cpu_ids);
107 ncores = nr_cpu_ids;
108 }
109
110 for (i = 0; i < ncores; i++)
111 set_cpu_possible(i, true);
112
113 set_smp_cross_call(gic_raise_softirq);
114}
115
116void __init platform_smp_prepare_cpus(unsigned int max_cpus)
117{
118
119 scu_enable(scu_base);
120
121 /*
122 * Write the address of secondary startup into the system-wide location
123 * (presently it is in SRAM). The BootMonitor waits until it receives a
124 * soft interrupt, and then the secondary CPU branches to this address.
125 */
126 __raw_writel(virt_to_phys(spear13xx_secondary_startup), SYS_LOCATION);
127}
diff --git a/arch/arm/mach-spear13xx/spear1310.c b/arch/arm/mach-spear13xx/spear1310.c
new file mode 100644
index 000000000000..fefd15b2f380
--- /dev/null
+++ b/arch/arm/mach-spear13xx/spear1310.c
@@ -0,0 +1,88 @@
1/*
2 * arch/arm/mach-spear13xx/spear1310.c
3 *
4 * SPEAr1310 machine source file
5 *
6 * Copyright (C) 2012 ST Microelectronics
7 * Viresh Kumar <viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#define pr_fmt(fmt) "SPEAr1310: " fmt
15
16#include <linux/amba/pl022.h>
17#include <linux/of_platform.h>
18#include <asm/hardware/gic.h>
19#include <asm/mach/arch.h>
20#include <asm/mach/map.h>
21#include <mach/generic.h>
22#include <mach/spear.h>
23
24/* Base addresses */
25#define SPEAR1310_SSP1_BASE UL(0x5D400000)
26#define SPEAR1310_SATA0_BASE UL(0xB1000000)
27#define SPEAR1310_SATA1_BASE UL(0xB1800000)
28#define SPEAR1310_SATA2_BASE UL(0xB4000000)
29
30/* ssp device registration */
31static struct pl022_ssp_controller ssp1_plat_data = {
32 .bus_id = 0,
33 .enable_dma = 0,
34 .num_chipselect = 3,
35};
36
37/* Add SPEAr1310 auxdata to pass platform data */
38static struct of_dev_auxdata spear1310_auxdata_lookup[] __initdata = {
39 OF_DEV_AUXDATA("arasan,cf-spear1340", MCIF_CF_BASE, NULL, &cf_dma_priv),
40 OF_DEV_AUXDATA("snps,dma-spear1340", DMAC0_BASE, NULL, &dmac_plat_data),
41 OF_DEV_AUXDATA("snps,dma-spear1340", DMAC1_BASE, NULL, &dmac_plat_data),
42 OF_DEV_AUXDATA("arm,pl022", SSP_BASE, NULL, &pl022_plat_data),
43
44 OF_DEV_AUXDATA("arm,pl022", SPEAR1310_SSP1_BASE, NULL, &ssp1_plat_data),
45 {}
46};
47
48static void __init spear1310_dt_init(void)
49{
50 of_platform_populate(NULL, of_default_bus_match_table,
51 spear1310_auxdata_lookup, NULL);
52}
53
54static const char * const spear1310_dt_board_compat[] = {
55 "st,spear1310",
56 "st,spear1310-evb",
57 NULL,
58};
59
60/*
61 * Following will create 16MB static virtual/physical mappings
62 * PHYSICAL VIRTUAL
63 * 0xD8000000 0xFA000000
64 */
65struct map_desc spear1310_io_desc[] __initdata = {
66 {
67 .virtual = VA_SPEAR1310_RAS_GRP1_BASE,
68 .pfn = __phys_to_pfn(SPEAR1310_RAS_GRP1_BASE),
69 .length = SZ_16M,
70 .type = MT_DEVICE
71 },
72};
73
74static void __init spear1310_map_io(void)
75{
76 iotable_init(spear1310_io_desc, ARRAY_SIZE(spear1310_io_desc));
77 spear13xx_map_io();
78}
79
80DT_MACHINE_START(SPEAR1310_DT, "ST SPEAr1310 SoC with Flattened Device Tree")
81 .map_io = spear1310_map_io,
82 .init_irq = spear13xx_dt_init_irq,
83 .handle_irq = gic_handle_irq,
84 .timer = &spear13xx_timer,
85 .init_machine = spear1310_dt_init,
86 .restart = spear_restart,
87 .dt_compat = spear1310_dt_board_compat,
88MACHINE_END
diff --git a/arch/arm/mach-spear13xx/spear1340.c b/arch/arm/mach-spear13xx/spear1340.c
new file mode 100644
index 000000000000..ee38cbc56869
--- /dev/null
+++ b/arch/arm/mach-spear13xx/spear1340.c
@@ -0,0 +1,192 @@
1/*
2 * arch/arm/mach-spear13xx/spear1340.c
3 *
4 * SPEAr1340 machine source file
5 *
6 * Copyright (C) 2012 ST Microelectronics
7 * Viresh Kumar <viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#define pr_fmt(fmt) "SPEAr1340: " fmt
15
16#include <linux/ahci_platform.h>
17#include <linux/amba/serial.h>
18#include <linux/delay.h>
19#include <linux/dw_dmac.h>
20#include <linux/of_platform.h>
21#include <asm/hardware/gic.h>
22#include <asm/mach/arch.h>
23#include <mach/dma.h>
24#include <mach/generic.h>
25#include <mach/spear.h>
26
27/* Base addresses */
28#define SPEAR1340_SATA_BASE UL(0xB1000000)
29#define SPEAR1340_UART1_BASE UL(0xB4100000)
30
31/* Power Management Registers */
32#define SPEAR1340_PCM_CFG (VA_MISC_BASE + 0x100)
33#define SPEAR1340_PCM_WKUP_CFG (VA_MISC_BASE + 0x104)
34#define SPEAR1340_SWITCH_CTR (VA_MISC_BASE + 0x108)
35
36#define SPEAR1340_PERIP1_SW_RST (VA_MISC_BASE + 0x318)
37#define SPEAR1340_PERIP2_SW_RST (VA_MISC_BASE + 0x31C)
38#define SPEAR1340_PERIP3_SW_RST (VA_MISC_BASE + 0x320)
39
40/* PCIE - SATA configuration registers */
41#define SPEAR1340_PCIE_SATA_CFG (VA_MISC_BASE + 0x424)
42 /* PCIE CFG MASks */
43 #define SPEAR1340_PCIE_CFG_DEVICE_PRESENT (1 << 11)
44 #define SPEAR1340_PCIE_CFG_POWERUP_RESET (1 << 10)
45 #define SPEAR1340_PCIE_CFG_CORE_CLK_EN (1 << 9)
46 #define SPEAR1340_PCIE_CFG_AUX_CLK_EN (1 << 8)
47 #define SPEAR1340_SATA_CFG_TX_CLK_EN (1 << 4)
48 #define SPEAR1340_SATA_CFG_RX_CLK_EN (1 << 3)
49 #define SPEAR1340_SATA_CFG_POWERUP_RESET (1 << 2)
50 #define SPEAR1340_SATA_CFG_PM_CLK_EN (1 << 1)
51 #define SPEAR1340_PCIE_SATA_SEL_PCIE (0)
52 #define SPEAR1340_PCIE_SATA_SEL_SATA (1)
53 #define SPEAR1340_SATA_PCIE_CFG_MASK 0xF1F
54 #define SPEAR1340_PCIE_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_PCIE | \
55 SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
56 SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
57 SPEAR1340_PCIE_CFG_POWERUP_RESET | \
58 SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
59 #define SPEAR1340_SATA_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_SATA | \
60 SPEAR1340_SATA_CFG_PM_CLK_EN | \
61 SPEAR1340_SATA_CFG_POWERUP_RESET | \
62 SPEAR1340_SATA_CFG_RX_CLK_EN | \
63 SPEAR1340_SATA_CFG_TX_CLK_EN)
64
65#define SPEAR1340_PCIE_MIPHY_CFG (VA_MISC_BASE + 0x428)
66 #define SPEAR1340_MIPHY_OSC_BYPASS_EXT (1 << 31)
67 #define SPEAR1340_MIPHY_CLK_REF_DIV2 (1 << 27)
68 #define SPEAR1340_MIPHY_CLK_REF_DIV4 (2 << 27)
69 #define SPEAR1340_MIPHY_CLK_REF_DIV8 (3 << 27)
70 #define SPEAR1340_MIPHY_PLL_RATIO_TOP(x) (x << 0)
71 #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
72 (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
73 SPEAR1340_MIPHY_CLK_REF_DIV2 | \
74 SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
75 #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
76 (SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
77 #define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
78 (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
79 SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
80
81static struct dw_dma_slave uart1_dma_param[] = {
82 {
83 /* Tx */
84 .cfg_hi = DWC_CFGH_DST_PER(SPEAR1340_DMA_REQ_UART1_TX),
85 .cfg_lo = 0,
86 .src_master = DMA_MASTER_MEMORY,
87 .dst_master = SPEAR1340_DMA_MASTER_UART1,
88 }, {
89 /* Rx */
90 .cfg_hi = DWC_CFGH_SRC_PER(SPEAR1340_DMA_REQ_UART1_RX),
91 .cfg_lo = 0,
92 .src_master = SPEAR1340_DMA_MASTER_UART1,
93 .dst_master = DMA_MASTER_MEMORY,
94 }
95};
96
97static struct amba_pl011_data uart1_data = {
98 .dma_filter = dw_dma_filter,
99 .dma_tx_param = &uart1_dma_param[0],
100 .dma_rx_param = &uart1_dma_param[1],
101};
102
103/* SATA device registration */
104static int sata_miphy_init(struct device *dev, void __iomem *addr)
105{
106 writel(SPEAR1340_SATA_CFG_VAL, SPEAR1340_PCIE_SATA_CFG);
107 writel(SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK,
108 SPEAR1340_PCIE_MIPHY_CFG);
109 /* Switch on sata power domain */
110 writel((readl(SPEAR1340_PCM_CFG) | (0x800)), SPEAR1340_PCM_CFG);
111 msleep(20);
112 /* Disable PCIE SATA Controller reset */
113 writel((readl(SPEAR1340_PERIP1_SW_RST) & (~0x1000)),
114 SPEAR1340_PERIP1_SW_RST);
115 msleep(20);
116
117 return 0;
118}
119
120void sata_miphy_exit(struct device *dev)
121{
122 writel(0, SPEAR1340_PCIE_SATA_CFG);
123 writel(0, SPEAR1340_PCIE_MIPHY_CFG);
124
125 /* Enable PCIE SATA Controller reset */
126 writel((readl(SPEAR1340_PERIP1_SW_RST) | (0x1000)),
127 SPEAR1340_PERIP1_SW_RST);
128 msleep(20);
129 /* Switch off sata power domain */
130 writel((readl(SPEAR1340_PCM_CFG) & (~0x800)), SPEAR1340_PCM_CFG);
131 msleep(20);
132}
133
134int sata_suspend(struct device *dev)
135{
136 if (dev->power.power_state.event == PM_EVENT_FREEZE)
137 return 0;
138
139 sata_miphy_exit(dev);
140
141 return 0;
142}
143
144int sata_resume(struct device *dev)
145{
146 if (dev->power.power_state.event == PM_EVENT_THAW)
147 return 0;
148
149 return sata_miphy_init(dev, NULL);
150}
151
152static struct ahci_platform_data sata_pdata = {
153 .init = sata_miphy_init,
154 .exit = sata_miphy_exit,
155 .suspend = sata_suspend,
156 .resume = sata_resume,
157};
158
159/* Add SPEAr1340 auxdata to pass platform data */
160static struct of_dev_auxdata spear1340_auxdata_lookup[] __initdata = {
161 OF_DEV_AUXDATA("arasan,cf-spear1340", MCIF_CF_BASE, NULL, &cf_dma_priv),
162 OF_DEV_AUXDATA("snps,dma-spear1340", DMAC0_BASE, NULL, &dmac_plat_data),
163 OF_DEV_AUXDATA("snps,dma-spear1340", DMAC1_BASE, NULL, &dmac_plat_data),
164 OF_DEV_AUXDATA("arm,pl022", SSP_BASE, NULL, &pl022_plat_data),
165
166 OF_DEV_AUXDATA("snps,spear-ahci", SPEAR1340_SATA_BASE, NULL,
167 &sata_pdata),
168 OF_DEV_AUXDATA("arm,pl011", SPEAR1340_UART1_BASE, NULL, &uart1_data),
169 {}
170};
171
172static void __init spear1340_dt_init(void)
173{
174 of_platform_populate(NULL, of_default_bus_match_table,
175 spear1340_auxdata_lookup, NULL);
176}
177
178static const char * const spear1340_dt_board_compat[] = {
179 "st,spear1340",
180 "st,spear1340-evb",
181 NULL,
182};
183
184DT_MACHINE_START(SPEAR1340_DT, "ST SPEAr1340 SoC with Flattened Device Tree")
185 .map_io = spear13xx_map_io,
186 .init_irq = spear13xx_dt_init_irq,
187 .handle_irq = gic_handle_irq,
188 .timer = &spear13xx_timer,
189 .init_machine = spear1340_dt_init,
190 .restart = spear_restart,
191 .dt_compat = spear1340_dt_board_compat,
192MACHINE_END
diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c
new file mode 100644
index 000000000000..50b349ae863d
--- /dev/null
+++ b/arch/arm/mach-spear13xx/spear13xx.c
@@ -0,0 +1,197 @@
1/*
2 * arch/arm/mach-spear13xx/spear13xx.c
3 *
4 * SPEAr13XX machines common source file
5 *
6 * Copyright (C) 2012 ST Microelectronics
7 * Viresh Kumar <viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#define pr_fmt(fmt) "SPEAr13xx: " fmt
15
16#include <linux/amba/pl022.h>
17#include <linux/clk.h>
18#include <linux/dw_dmac.h>
19#include <linux/err.h>
20#include <linux/of_irq.h>
21#include <asm/hardware/cache-l2x0.h>
22#include <asm/hardware/gic.h>
23#include <asm/mach/map.h>
24#include <asm/smp_twd.h>
25#include <mach/dma.h>
26#include <mach/generic.h>
27#include <mach/spear.h>
28
29/* common dw_dma filter routine to be used by peripherals */
30bool dw_dma_filter(struct dma_chan *chan, void *slave)
31{
32 struct dw_dma_slave *dws = (struct dw_dma_slave *)slave;
33
34 if (chan->device->dev == dws->dma_dev) {
35 chan->private = slave;
36 return true;
37 } else {
38 return false;
39 }
40}
41
42/* ssp device registration */
43static struct dw_dma_slave ssp_dma_param[] = {
44 {
45 /* Tx */
46 .cfg_hi = DWC_CFGH_DST_PER(DMA_REQ_SSP0_TX),
47 .cfg_lo = 0,
48 .src_master = DMA_MASTER_MEMORY,
49 .dst_master = DMA_MASTER_SSP0,
50 }, {
51 /* Rx */
52 .cfg_hi = DWC_CFGH_SRC_PER(DMA_REQ_SSP0_RX),
53 .cfg_lo = 0,
54 .src_master = DMA_MASTER_SSP0,
55 .dst_master = DMA_MASTER_MEMORY,
56 }
57};
58
59struct pl022_ssp_controller pl022_plat_data = {
60 .bus_id = 0,
61 .enable_dma = 1,
62 .dma_filter = dw_dma_filter,
63 .dma_rx_param = &ssp_dma_param[1],
64 .dma_tx_param = &ssp_dma_param[0],
65 .num_chipselect = 3,
66};
67
68/* CF device registration */
69struct dw_dma_slave cf_dma_priv = {
70 .cfg_hi = 0,
71 .cfg_lo = 0,
72 .src_master = 0,
73 .dst_master = 0,
74};
75
76/* dmac device registeration */
77struct dw_dma_platform_data dmac_plat_data = {
78 .nr_channels = 8,
79 .chan_allocation_order = CHAN_ALLOCATION_DESCENDING,
80 .chan_priority = CHAN_PRIORITY_DESCENDING,
81};
82
83void __init spear13xx_l2x0_init(void)
84{
85 /*
86 * 512KB (64KB/way), 8-way associativity, parity supported
87 *
88 * FIXME: 9th bit, of Auxillary Controller register must be set
89 * for some spear13xx devices for stable L2 operation.
90 *
91 * Enable Early BRESP, L2 prefetch for Instruction and Data,
92 * write alloc and 'Full line of zero' options
93 *
94 */
95
96 writel_relaxed(0x06, VA_L2CC_BASE + L2X0_PREFETCH_CTRL);
97
98 /*
99 * Program following latencies in order to make
100 * SPEAr1340 work at 600 MHz
101 */
102 writel_relaxed(0x221, VA_L2CC_BASE + L2X0_TAG_LATENCY_CTRL);
103 writel_relaxed(0x441, VA_L2CC_BASE + L2X0_DATA_LATENCY_CTRL);
104 l2x0_init(VA_L2CC_BASE, 0x70A60001, 0xfe00ffff);
105}
106
107/*
108 * Following will create 16MB static virtual/physical mappings
109 * PHYSICAL VIRTUAL
110 * 0xB3000000 0xFE000000
111 * 0xE0000000 0xFD000000
112 * 0xEC000000 0xFC000000
113 * 0xED000000 0xFB000000
114 */
115struct map_desc spear13xx_io_desc[] __initdata = {
116 {
117 .virtual = VA_PERIP_GRP2_BASE,
118 .pfn = __phys_to_pfn(PERIP_GRP2_BASE),
119 .length = SZ_16M,
120 .type = MT_DEVICE
121 }, {
122 .virtual = VA_PERIP_GRP1_BASE,
123 .pfn = __phys_to_pfn(PERIP_GRP1_BASE),
124 .length = SZ_16M,
125 .type = MT_DEVICE
126 }, {
127 .virtual = VA_A9SM_AND_MPMC_BASE,
128 .pfn = __phys_to_pfn(A9SM_AND_MPMC_BASE),
129 .length = SZ_16M,
130 .type = MT_DEVICE
131 }, {
132 .virtual = (unsigned long)VA_L2CC_BASE,
133 .pfn = __phys_to_pfn(L2CC_BASE),
134 .length = SZ_4K,
135 .type = MT_DEVICE
136 },
137};
138
139/* This will create static memory mapping for selected devices */
140void __init spear13xx_map_io(void)
141{
142 iotable_init(spear13xx_io_desc, ARRAY_SIZE(spear13xx_io_desc));
143}
144
145static void __init spear13xx_clk_init(void)
146{
147 if (of_machine_is_compatible("st,spear1310"))
148 spear1310_clk_init();
149 else if (of_machine_is_compatible("st,spear1340"))
150 spear1340_clk_init();
151 else
152 pr_err("%s: Unknown machine\n", __func__);
153}
154
155static void __init spear13xx_timer_init(void)
156{
157 char pclk_name[] = "osc_24m_clk";
158 struct clk *gpt_clk, *pclk;
159
160 spear13xx_clk_init();
161
162 /* get the system timer clock */
163 gpt_clk = clk_get_sys("gpt0", NULL);
164 if (IS_ERR(gpt_clk)) {
165 pr_err("%s:couldn't get clk for gpt\n", __func__);
166 BUG();
167 }
168
169 /* get the suitable parent clock for timer*/
170 pclk = clk_get(NULL, pclk_name);
171 if (IS_ERR(pclk)) {
172 pr_err("%s:couldn't get %s as parent for gpt\n", __func__,
173 pclk_name);
174 BUG();
175 }
176
177 clk_set_parent(gpt_clk, pclk);
178 clk_put(gpt_clk);
179 clk_put(pclk);
180
181 spear_setup_of_timer();
182 twd_local_timer_of_register();
183}
184
185struct sys_timer spear13xx_timer = {
186 .init = spear13xx_timer_init,
187};
188
189static const struct of_device_id gic_of_match[] __initconst = {
190 { .compatible = "arm,cortex-a9-gic", .data = gic_of_init },
191 { /* Sentinel */ }
192};
193
194void __init spear13xx_dt_init_irq(void)
195{
196 of_irq_init(gic_of_match);
197}
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index f8c571031da8..a2fae4ea0936 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -419,7 +419,7 @@ config S3C_DMA
419config SAMSUNG_DMADEV 419config SAMSUNG_DMADEV
420 bool 420 bool
421 select DMADEVICES 421 select DMADEVICES
422 select PL330_DMA if (CPU_EXYNOS4210 || CPU_S5PV210 || CPU_S5PC100 || \ 422 select PL330_DMA if (ARCH_EXYNOS5 || ARCH_EXYNOS4 || CPU_S5PV210 || CPU_S5PC100 || \
423 CPU_S5P6450 || CPU_S5P6440) 423 CPU_S5P6450 || CPU_S5P6440)
424 select ARM_AMBA 424 select ARM_AMBA
425 help 425 help
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 787ceaca0be8..0721293fad63 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -202,7 +202,7 @@ extern struct bus_type s3c2443_subsys;
202extern struct bus_type s3c6410_subsys; 202extern struct bus_type s3c6410_subsys;
203extern struct bus_type s5p64x0_subsys; 203extern struct bus_type s5p64x0_subsys;
204extern struct bus_type s5pv210_subsys; 204extern struct bus_type s5pv210_subsys;
205extern struct bus_type exynos4_subsys; 205extern struct bus_type exynos_subsys;
206 206
207extern void (*s5pc1xx_idle)(void); 207extern void (*s5pc1xx_idle)(void);
208 208
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index 4067d1dd7f1c..61ca2f356c52 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -134,6 +134,8 @@ extern struct platform_device exynos4_device_pcm2;
134extern struct platform_device exynos4_device_pd[]; 134extern struct platform_device exynos4_device_pd[];
135extern struct platform_device exynos4_device_spdif; 135extern struct platform_device exynos4_device_spdif;
136 136
137extern struct platform_device exynos_device_drm;
138
137extern struct platform_device samsung_asoc_dma; 139extern struct platform_device samsung_asoc_dma;
138extern struct platform_device samsung_asoc_idma; 140extern struct platform_device samsung_asoc_idma;
139extern struct platform_device samsung_device_keypad; 141extern struct platform_device samsung_device_keypad;
diff --git a/arch/arm/plat-samsung/include/plat/dma-pl330.h b/arch/arm/plat-samsung/include/plat/dma-pl330.h
index 0670f37aaaed..d384a8016b47 100644
--- a/arch/arm/plat-samsung/include/plat/dma-pl330.h
+++ b/arch/arm/plat-samsung/include/plat/dma-pl330.h
@@ -90,6 +90,7 @@ enum dma_ch {
90 DMACH_MIPI_HSI5, 90 DMACH_MIPI_HSI5,
91 DMACH_MIPI_HSI6, 91 DMACH_MIPI_HSI6,
92 DMACH_MIPI_HSI7, 92 DMACH_MIPI_HSI7,
93 DMACH_DISP1,
93 DMACH_MTOM_0, 94 DMACH_MTOM_0,
94 DMACH_MTOM_1, 95 DMACH_MTOM_1,
95 DMACH_MTOM_2, 96 DMACH_MTOM_2,
diff --git a/arch/arm/plat-samsung/include/plat/s5p-clock.h b/arch/arm/plat-samsung/include/plat/s5p-clock.h
index 1de4b32f98e9..8364b4bea8b8 100644
--- a/arch/arm/plat-samsung/include/plat/s5p-clock.h
+++ b/arch/arm/plat-samsung/include/plat/s5p-clock.h
@@ -32,8 +32,10 @@ extern struct clk clk_48m;
32extern struct clk s5p_clk_27m; 32extern struct clk s5p_clk_27m;
33extern struct clk clk_fout_apll; 33extern struct clk clk_fout_apll;
34extern struct clk clk_fout_bpll; 34extern struct clk clk_fout_bpll;
35extern struct clk clk_fout_bpll_div2;
35extern struct clk clk_fout_cpll; 36extern struct clk clk_fout_cpll;
36extern struct clk clk_fout_mpll; 37extern struct clk clk_fout_mpll;
38extern struct clk clk_fout_mpll_div2;
37extern struct clk clk_fout_epll; 39extern struct clk clk_fout_epll;
38extern struct clk clk_fout_dpll; 40extern struct clk clk_fout_dpll;
39extern struct clk clk_fout_vpll; 41extern struct clk clk_fout_vpll;
@@ -42,8 +44,10 @@ extern struct clk clk_vpll;
42 44
43extern struct clksrc_sources clk_src_apll; 45extern struct clksrc_sources clk_src_apll;
44extern struct clksrc_sources clk_src_bpll; 46extern struct clksrc_sources clk_src_bpll;
47extern struct clksrc_sources clk_src_bpll_fout;
45extern struct clksrc_sources clk_src_cpll; 48extern struct clksrc_sources clk_src_cpll;
46extern struct clksrc_sources clk_src_mpll; 49extern struct clksrc_sources clk_src_mpll;
50extern struct clksrc_sources clk_src_mpll_fout;
47extern struct clksrc_sources clk_src_epll; 51extern struct clksrc_sources clk_src_epll;
48extern struct clksrc_sources clk_src_dpll; 52extern struct clksrc_sources clk_src_dpll;
49 53
diff --git a/arch/arm/plat-samsung/s5p-clock.c b/arch/arm/plat-samsung/s5p-clock.c
index 41d3dfd5dddb..031a61899bef 100644
--- a/arch/arm/plat-samsung/s5p-clock.c
+++ b/arch/arm/plat-samsung/s5p-clock.c
@@ -67,6 +67,11 @@ struct clk clk_fout_bpll = {
67 .id = -1, 67 .id = -1,
68}; 68};
69 69
70struct clk clk_fout_bpll_div2 = {
71 .name = "fout_bpll_div2",
72 .id = -1,
73};
74
70/* CPLL clock output */ 75/* CPLL clock output */
71 76
72struct clk clk_fout_cpll = { 77struct clk clk_fout_cpll = {
@@ -82,6 +87,11 @@ struct clk clk_fout_mpll = {
82 .id = -1, 87 .id = -1,
83}; 88};
84 89
90struct clk clk_fout_mpll_div2 = {
91 .name = "fout_mpll_div2",
92 .id = -1,
93};
94
85/* EPLL clock output */ 95/* EPLL clock output */
86struct clk clk_fout_epll = { 96struct clk clk_fout_epll = {
87 .name = "fout_epll", 97 .name = "fout_epll",
@@ -125,6 +135,16 @@ struct clksrc_sources clk_src_bpll = {
125 .nr_sources = ARRAY_SIZE(clk_src_bpll_list), 135 .nr_sources = ARRAY_SIZE(clk_src_bpll_list),
126}; 136};
127 137
138static struct clk *clk_src_bpll_fout_list[] = {
139 [0] = &clk_fout_bpll_div2,
140 [1] = &clk_fout_bpll,
141};
142
143struct clksrc_sources clk_src_bpll_fout = {
144 .sources = clk_src_bpll_fout_list,
145 .nr_sources = ARRAY_SIZE(clk_src_bpll_fout_list),
146};
147
128/* Possible clock sources for CPLL Mux */ 148/* Possible clock sources for CPLL Mux */
129static struct clk *clk_src_cpll_list[] = { 149static struct clk *clk_src_cpll_list[] = {
130 [0] = &clk_fin_cpll, 150 [0] = &clk_fin_cpll,
@@ -147,6 +167,16 @@ struct clksrc_sources clk_src_mpll = {
147 .nr_sources = ARRAY_SIZE(clk_src_mpll_list), 167 .nr_sources = ARRAY_SIZE(clk_src_mpll_list),
148}; 168};
149 169
170static struct clk *clk_src_mpll_fout_list[] = {
171 [0] = &clk_fout_mpll_div2,
172 [1] = &clk_fout_mpll,
173};
174
175struct clksrc_sources clk_src_mpll_fout = {
176 .sources = clk_src_mpll_fout_list,
177 .nr_sources = ARRAY_SIZE(clk_src_mpll_fout_list),
178};
179
150/* Possible clock sources for EPLL Mux */ 180/* Possible clock sources for EPLL Mux */
151static struct clk *clk_src_epll_list[] = { 181static struct clk *clk_src_epll_list[] = {
152 [0] = &clk_fin_epll, 182 [0] = &clk_fin_epll,
diff --git a/arch/arm/plat-spear/Kconfig b/arch/arm/plat-spear/Kconfig
index 387655b5ce05..4404f82d5979 100644
--- a/arch/arm/plat-spear/Kconfig
+++ b/arch/arm/plat-spear/Kconfig
@@ -8,6 +8,17 @@ choice
8 prompt "ST SPEAr Family" 8 prompt "ST SPEAr Family"
9 default ARCH_SPEAR3XX 9 default ARCH_SPEAR3XX
10 10
11config ARCH_SPEAR13XX
12 bool "ST SPEAr13xx with Device Tree"
13 select ARM_GIC
14 select CPU_V7
15 select USE_OF
16 select HAVE_SMP
17 select MIGHT_HAVE_CACHE_L2X0
18 select PINCTRL
19 help
20 Supports for ARM's SPEAR13XX family
21
11config ARCH_SPEAR3XX 22config ARCH_SPEAR3XX
12 bool "ST SPEAr3xx with Device Tree" 23 bool "ST SPEAr3xx with Device Tree"
13 select ARM_VIC 24 select ARM_VIC
@@ -27,6 +38,7 @@ config ARCH_SPEAR6XX
27endchoice 38endchoice
28 39
29# Adding SPEAr machine specific configuration files 40# Adding SPEAr machine specific configuration files
41source "arch/arm/mach-spear13xx/Kconfig"
30source "arch/arm/mach-spear3xx/Kconfig" 42source "arch/arm/mach-spear3xx/Kconfig"
31source "arch/arm/mach-spear6xx/Kconfig" 43source "arch/arm/mach-spear6xx/Kconfig"
32 44
diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile
index 38f1235f4632..2607bd05c525 100644
--- a/arch/arm/plat-spear/Makefile
+++ b/arch/arm/plat-spear/Makefile
@@ -3,6 +3,7 @@
3# 3#
4 4
5# Common support 5# Common support
6obj-y := restart.o time.o pl080.o 6obj-y := restart.o time.o
7 7
8obj-$(CONFIG_ARCH_SPEAR3XX) += shirq.o 8obj-$(CONFIG_ARCH_SPEAR3XX) += pl080.o shirq.o
9obj-$(CONFIG_ARCH_SPEAR6XX) += pl080.o
diff --git a/arch/arm/plat-spear/restart.c b/arch/arm/plat-spear/restart.c
index 4471a232713a..ea0a61302b7e 100644
--- a/arch/arm/plat-spear/restart.c
+++ b/arch/arm/plat-spear/restart.c
@@ -16,6 +16,7 @@
16#include <mach/spear.h> 16#include <mach/spear.h>
17#include <mach/generic.h> 17#include <mach/generic.h>
18 18
19#define SPEAR13XX_SYS_SW_RES (VA_MISC_BASE + 0x204)
19void spear_restart(char mode, const char *cmd) 20void spear_restart(char mode, const char *cmd)
20{ 21{
21 if (mode == 's') { 22 if (mode == 's') {
@@ -23,6 +24,10 @@ void spear_restart(char mode, const char *cmd)
23 soft_restart(0); 24 soft_restart(0);
24 } else { 25 } else {
25 /* hardware reset, Use on-chip reset capability */ 26 /* hardware reset, Use on-chip reset capability */
27#ifdef CONFIG_ARCH_SPEAR13XX
28 writel_relaxed(0x01, SPEAR13XX_SYS_SW_RES);
29#else
26 sysctl_soft_reset((void __iomem *)VA_SPEAR_SYS_CTRL_BASE); 30 sysctl_soft_reset((void __iomem *)VA_SPEAR_SYS_CTRL_BASE);
31#endif
27 } 32 }
28} 33}
diff --git a/drivers/clk/spear/Makefile b/drivers/clk/spear/Makefile
index 335886049c83..cdb425d3b8ee 100644
--- a/drivers/clk/spear/Makefile
+++ b/drivers/clk/spear/Makefile
@@ -6,3 +6,5 @@ obj-y += clk.o clk-aux-synth.o clk-frac-synth.o clk-gpt-synth.o clk-vco-pll.o
6 6
7obj-$(CONFIG_ARCH_SPEAR3XX) += spear3xx_clock.o 7obj-$(CONFIG_ARCH_SPEAR3XX) += spear3xx_clock.o
8obj-$(CONFIG_ARCH_SPEAR6XX) += spear6xx_clock.o 8obj-$(CONFIG_ARCH_SPEAR6XX) += spear6xx_clock.o
9obj-$(CONFIG_MACH_SPEAR1310) += spear1310_clock.o
10obj-$(CONFIG_MACH_SPEAR1340) += spear1340_clock.o
diff --git a/drivers/clk/spear/spear1310_clock.c b/drivers/clk/spear/spear1310_clock.c
new file mode 100644
index 000000000000..42b68df9aeef
--- /dev/null
+++ b/drivers/clk/spear/spear1310_clock.c
@@ -0,0 +1,1106 @@
1/*
2 * arch/arm/mach-spear13xx/spear1310_clock.c
3 *
4 * SPEAr1310 machine clock framework source file
5 *
6 * Copyright (C) 2012 ST Microelectronics
7 * Viresh Kumar <viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/clk.h>
15#include <linux/clkdev.h>
16#include <linux/err.h>
17#include <linux/io.h>
18#include <linux/of_platform.h>
19#include <linux/spinlock_types.h>
20#include <mach/spear.h>
21#include "clk.h"
22
23/* PLL related registers and bit values */
24#define SPEAR1310_PLL_CFG (VA_MISC_BASE + 0x210)
25 /* PLL_CFG bit values */
26 #define SPEAR1310_CLCD_SYNT_CLK_MASK 1
27 #define SPEAR1310_CLCD_SYNT_CLK_SHIFT 31
28 #define SPEAR1310_RAS_SYNT2_3_CLK_MASK 2
29 #define SPEAR1310_RAS_SYNT2_3_CLK_SHIFT 29
30 #define SPEAR1310_RAS_SYNT_CLK_MASK 2
31 #define SPEAR1310_RAS_SYNT0_1_CLK_SHIFT 27
32 #define SPEAR1310_PLL_CLK_MASK 2
33 #define SPEAR1310_PLL3_CLK_SHIFT 24
34 #define SPEAR1310_PLL2_CLK_SHIFT 22
35 #define SPEAR1310_PLL1_CLK_SHIFT 20
36
37#define SPEAR1310_PLL1_CTR (VA_MISC_BASE + 0x214)
38#define SPEAR1310_PLL1_FRQ (VA_MISC_BASE + 0x218)
39#define SPEAR1310_PLL2_CTR (VA_MISC_BASE + 0x220)
40#define SPEAR1310_PLL2_FRQ (VA_MISC_BASE + 0x224)
41#define SPEAR1310_PLL3_CTR (VA_MISC_BASE + 0x22C)
42#define SPEAR1310_PLL3_FRQ (VA_MISC_BASE + 0x230)
43#define SPEAR1310_PLL4_CTR (VA_MISC_BASE + 0x238)
44#define SPEAR1310_PLL4_FRQ (VA_MISC_BASE + 0x23C)
45#define SPEAR1310_PERIP_CLK_CFG (VA_MISC_BASE + 0x244)
46 /* PERIP_CLK_CFG bit values */
47 #define SPEAR1310_GPT_OSC24_VAL 0
48 #define SPEAR1310_GPT_APB_VAL 1
49 #define SPEAR1310_GPT_CLK_MASK 1
50 #define SPEAR1310_GPT3_CLK_SHIFT 11
51 #define SPEAR1310_GPT2_CLK_SHIFT 10
52 #define SPEAR1310_GPT1_CLK_SHIFT 9
53 #define SPEAR1310_GPT0_CLK_SHIFT 8
54 #define SPEAR1310_UART_CLK_PLL5_VAL 0
55 #define SPEAR1310_UART_CLK_OSC24_VAL 1
56 #define SPEAR1310_UART_CLK_SYNT_VAL 2
57 #define SPEAR1310_UART_CLK_MASK 2
58 #define SPEAR1310_UART_CLK_SHIFT 4
59
60 #define SPEAR1310_AUX_CLK_PLL5_VAL 0
61 #define SPEAR1310_AUX_CLK_SYNT_VAL 1
62 #define SPEAR1310_CLCD_CLK_MASK 2
63 #define SPEAR1310_CLCD_CLK_SHIFT 2
64 #define SPEAR1310_C3_CLK_MASK 1
65 #define SPEAR1310_C3_CLK_SHIFT 1
66
67#define SPEAR1310_GMAC_CLK_CFG (VA_MISC_BASE + 0x248)
68 #define SPEAR1310_GMAC_PHY_IF_SEL_MASK 3
69 #define SPEAR1310_GMAC_PHY_IF_SEL_SHIFT 4
70 #define SPEAR1310_GMAC_PHY_CLK_MASK 1
71 #define SPEAR1310_GMAC_PHY_CLK_SHIFT 3
72 #define SPEAR1310_GMAC_PHY_INPUT_CLK_MASK 2
73 #define SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT 1
74
75#define SPEAR1310_I2S_CLK_CFG (VA_MISC_BASE + 0x24C)
76 /* I2S_CLK_CFG register mask */
77 #define SPEAR1310_I2S_SCLK_X_MASK 0x1F
78 #define SPEAR1310_I2S_SCLK_X_SHIFT 27
79 #define SPEAR1310_I2S_SCLK_Y_MASK 0x1F
80 #define SPEAR1310_I2S_SCLK_Y_SHIFT 22
81 #define SPEAR1310_I2S_SCLK_EQ_SEL_SHIFT 21
82 #define SPEAR1310_I2S_SCLK_SYNTH_ENB 20
83 #define SPEAR1310_I2S_PRS1_CLK_X_MASK 0xFF
84 #define SPEAR1310_I2S_PRS1_CLK_X_SHIFT 12
85 #define SPEAR1310_I2S_PRS1_CLK_Y_MASK 0xFF
86 #define SPEAR1310_I2S_PRS1_CLK_Y_SHIFT 4
87 #define SPEAR1310_I2S_PRS1_EQ_SEL_SHIFT 3
88 #define SPEAR1310_I2S_REF_SEL_MASK 1
89 #define SPEAR1310_I2S_REF_SHIFT 2
90 #define SPEAR1310_I2S_SRC_CLK_MASK 2
91 #define SPEAR1310_I2S_SRC_CLK_SHIFT 0
92
93#define SPEAR1310_C3_CLK_SYNT (VA_MISC_BASE + 0x250)
94#define SPEAR1310_UART_CLK_SYNT (VA_MISC_BASE + 0x254)
95#define SPEAR1310_GMAC_CLK_SYNT (VA_MISC_BASE + 0x258)
96#define SPEAR1310_SDHCI_CLK_SYNT (VA_MISC_BASE + 0x25C)
97#define SPEAR1310_CFXD_CLK_SYNT (VA_MISC_BASE + 0x260)
98#define SPEAR1310_ADC_CLK_SYNT (VA_MISC_BASE + 0x264)
99#define SPEAR1310_AMBA_CLK_SYNT (VA_MISC_BASE + 0x268)
100#define SPEAR1310_CLCD_CLK_SYNT (VA_MISC_BASE + 0x270)
101#define SPEAR1310_RAS_CLK_SYNT0 (VA_MISC_BASE + 0x280)
102#define SPEAR1310_RAS_CLK_SYNT1 (VA_MISC_BASE + 0x288)
103#define SPEAR1310_RAS_CLK_SYNT2 (VA_MISC_BASE + 0x290)
104#define SPEAR1310_RAS_CLK_SYNT3 (VA_MISC_BASE + 0x298)
105 /* Check Fractional synthesizer reg masks */
106
107#define SPEAR1310_PERIP1_CLK_ENB (VA_MISC_BASE + 0x300)
108 /* PERIP1_CLK_ENB register masks */
109 #define SPEAR1310_RTC_CLK_ENB 31
110 #define SPEAR1310_ADC_CLK_ENB 30
111 #define SPEAR1310_C3_CLK_ENB 29
112 #define SPEAR1310_JPEG_CLK_ENB 28
113 #define SPEAR1310_CLCD_CLK_ENB 27
114 #define SPEAR1310_DMA_CLK_ENB 25
115 #define SPEAR1310_GPIO1_CLK_ENB 24
116 #define SPEAR1310_GPIO0_CLK_ENB 23
117 #define SPEAR1310_GPT1_CLK_ENB 22
118 #define SPEAR1310_GPT0_CLK_ENB 21
119 #define SPEAR1310_I2S0_CLK_ENB 20
120 #define SPEAR1310_I2S1_CLK_ENB 19
121 #define SPEAR1310_I2C0_CLK_ENB 18
122 #define SPEAR1310_SSP_CLK_ENB 17
123 #define SPEAR1310_UART_CLK_ENB 15
124 #define SPEAR1310_PCIE_SATA_2_CLK_ENB 14
125 #define SPEAR1310_PCIE_SATA_1_CLK_ENB 13
126 #define SPEAR1310_PCIE_SATA_0_CLK_ENB 12
127 #define SPEAR1310_UOC_CLK_ENB 11
128 #define SPEAR1310_UHC1_CLK_ENB 10
129 #define SPEAR1310_UHC0_CLK_ENB 9
130 #define SPEAR1310_GMAC_CLK_ENB 8
131 #define SPEAR1310_CFXD_CLK_ENB 7
132 #define SPEAR1310_SDHCI_CLK_ENB 6
133 #define SPEAR1310_SMI_CLK_ENB 5
134 #define SPEAR1310_FSMC_CLK_ENB 4
135 #define SPEAR1310_SYSRAM0_CLK_ENB 3
136 #define SPEAR1310_SYSRAM1_CLK_ENB 2
137 #define SPEAR1310_SYSROM_CLK_ENB 1
138 #define SPEAR1310_BUS_CLK_ENB 0
139
140#define SPEAR1310_PERIP2_CLK_ENB (VA_MISC_BASE + 0x304)
141 /* PERIP2_CLK_ENB register masks */
142 #define SPEAR1310_THSENS_CLK_ENB 8
143 #define SPEAR1310_I2S_REF_PAD_CLK_ENB 7
144 #define SPEAR1310_ACP_CLK_ENB 6
145 #define SPEAR1310_GPT3_CLK_ENB 5
146 #define SPEAR1310_GPT2_CLK_ENB 4
147 #define SPEAR1310_KBD_CLK_ENB 3
148 #define SPEAR1310_CPU_DBG_CLK_ENB 2
149 #define SPEAR1310_DDR_CORE_CLK_ENB 1
150 #define SPEAR1310_DDR_CTRL_CLK_ENB 0
151
152#define SPEAR1310_RAS_CLK_ENB (VA_MISC_BASE + 0x310)
153 /* RAS_CLK_ENB register masks */
154 #define SPEAR1310_SYNT3_CLK_ENB 17
155 #define SPEAR1310_SYNT2_CLK_ENB 16
156 #define SPEAR1310_SYNT1_CLK_ENB 15
157 #define SPEAR1310_SYNT0_CLK_ENB 14
158 #define SPEAR1310_PCLK3_CLK_ENB 13
159 #define SPEAR1310_PCLK2_CLK_ENB 12
160 #define SPEAR1310_PCLK1_CLK_ENB 11
161 #define SPEAR1310_PCLK0_CLK_ENB 10
162 #define SPEAR1310_PLL3_CLK_ENB 9
163 #define SPEAR1310_PLL2_CLK_ENB 8
164 #define SPEAR1310_C125M_PAD_CLK_ENB 7
165 #define SPEAR1310_C30M_CLK_ENB 6
166 #define SPEAR1310_C48M_CLK_ENB 5
167 #define SPEAR1310_OSC_25M_CLK_ENB 4
168 #define SPEAR1310_OSC_32K_CLK_ENB 3
169 #define SPEAR1310_OSC_24M_CLK_ENB 2
170 #define SPEAR1310_PCLK_CLK_ENB 1
171 #define SPEAR1310_ACLK_CLK_ENB 0
172
173/* RAS Area Control Register */
174#define SPEAR1310_RAS_CTRL_REG0 (VA_SPEAR1310_RAS_BASE + 0x000)
175 #define SPEAR1310_SSP1_CLK_MASK 3
176 #define SPEAR1310_SSP1_CLK_SHIFT 26
177 #define SPEAR1310_TDM_CLK_MASK 1
178 #define SPEAR1310_TDM2_CLK_SHIFT 24
179 #define SPEAR1310_TDM1_CLK_SHIFT 23
180 #define SPEAR1310_I2C_CLK_MASK 1
181 #define SPEAR1310_I2C7_CLK_SHIFT 22
182 #define SPEAR1310_I2C6_CLK_SHIFT 21
183 #define SPEAR1310_I2C5_CLK_SHIFT 20
184 #define SPEAR1310_I2C4_CLK_SHIFT 19
185 #define SPEAR1310_I2C3_CLK_SHIFT 18
186 #define SPEAR1310_I2C2_CLK_SHIFT 17
187 #define SPEAR1310_I2C1_CLK_SHIFT 16
188 #define SPEAR1310_GPT64_CLK_MASK 1
189 #define SPEAR1310_GPT64_CLK_SHIFT 15
190 #define SPEAR1310_RAS_UART_CLK_MASK 1
191 #define SPEAR1310_UART5_CLK_SHIFT 14
192 #define SPEAR1310_UART4_CLK_SHIFT 13
193 #define SPEAR1310_UART3_CLK_SHIFT 12
194 #define SPEAR1310_UART2_CLK_SHIFT 11
195 #define SPEAR1310_UART1_CLK_SHIFT 10
196 #define SPEAR1310_PCI_CLK_MASK 1
197 #define SPEAR1310_PCI_CLK_SHIFT 0
198
199#define SPEAR1310_RAS_CTRL_REG1 (VA_SPEAR1310_RAS_BASE + 0x004)
200 #define SPEAR1310_PHY_CLK_MASK 0x3
201 #define SPEAR1310_RMII_PHY_CLK_SHIFT 0
202 #define SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT 2
203
204#define SPEAR1310_RAS_SW_CLK_CTRL (VA_SPEAR1310_RAS_BASE + 0x0148)
205 #define SPEAR1310_CAN1_CLK_ENB 25
206 #define SPEAR1310_CAN0_CLK_ENB 24
207 #define SPEAR1310_GPT64_CLK_ENB 23
208 #define SPEAR1310_SSP1_CLK_ENB 22
209 #define SPEAR1310_I2C7_CLK_ENB 21
210 #define SPEAR1310_I2C6_CLK_ENB 20
211 #define SPEAR1310_I2C5_CLK_ENB 19
212 #define SPEAR1310_I2C4_CLK_ENB 18
213 #define SPEAR1310_I2C3_CLK_ENB 17
214 #define SPEAR1310_I2C2_CLK_ENB 16
215 #define SPEAR1310_I2C1_CLK_ENB 15
216 #define SPEAR1310_UART5_CLK_ENB 14
217 #define SPEAR1310_UART4_CLK_ENB 13
218 #define SPEAR1310_UART3_CLK_ENB 12
219 #define SPEAR1310_UART2_CLK_ENB 11
220 #define SPEAR1310_UART1_CLK_ENB 10
221 #define SPEAR1310_RS485_1_CLK_ENB 9
222 #define SPEAR1310_RS485_0_CLK_ENB 8
223 #define SPEAR1310_TDM2_CLK_ENB 7
224 #define SPEAR1310_TDM1_CLK_ENB 6
225 #define SPEAR1310_PCI_CLK_ENB 5
226 #define SPEAR1310_GMII_CLK_ENB 4
227 #define SPEAR1310_MII2_CLK_ENB 3
228 #define SPEAR1310_MII1_CLK_ENB 2
229 #define SPEAR1310_MII0_CLK_ENB 1
230 #define SPEAR1310_ESRAM_CLK_ENB 0
231
232static DEFINE_SPINLOCK(_lock);
233
234/* pll rate configuration table, in ascending order of rates */
235static struct pll_rate_tbl pll_rtbl[] = {
236 /* PCLK 24MHz */
237 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
238 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
239 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
240 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
241 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
242 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
243 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
244};
245
246/* vco-pll4 rate configuration table, in ascending order of rates */
247static struct pll_rate_tbl pll4_rtbl[] = {
248 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
249 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
250 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x2}, /* vco 1600, pll 400 MHz */
251 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
252};
253
254/* aux rate configuration table, in ascending order of rates */
255static struct aux_rate_tbl aux_rtbl[] = {
256 /* For VCO1div2 = 500 MHz */
257 {.xscale = 10, .yscale = 204, .eq = 0}, /* 12.29 MHz */
258 {.xscale = 4, .yscale = 21, .eq = 0}, /* 48 MHz */
259 {.xscale = 2, .yscale = 6, .eq = 0}, /* 83 MHz */
260 {.xscale = 2, .yscale = 4, .eq = 0}, /* 125 MHz */
261 {.xscale = 1, .yscale = 3, .eq = 1}, /* 166 MHz */
262 {.xscale = 1, .yscale = 2, .eq = 1}, /* 250 MHz */
263};
264
265/* gmac rate configuration table, in ascending order of rates */
266static struct aux_rate_tbl gmac_rtbl[] = {
267 /* For gmac phy input clk */
268 {.xscale = 2, .yscale = 6, .eq = 0}, /* divided by 6 */
269 {.xscale = 2, .yscale = 4, .eq = 0}, /* divided by 4 */
270 {.xscale = 1, .yscale = 3, .eq = 1}, /* divided by 3 */
271 {.xscale = 1, .yscale = 2, .eq = 1}, /* divided by 2 */
272};
273
274/* clcd rate configuration table, in ascending order of rates */
275static struct frac_rate_tbl clcd_rtbl[] = {
276 {.div = 0x14000}, /* 25 Mhz , for vc01div4 = 250 MHz*/
277 {.div = 0x1284B}, /* 27 Mhz , for vc01div4 = 250 MHz*/
278 {.div = 0x0D8D3}, /* 58 Mhz , for vco1div4 = 393 MHz */
279 {.div = 0x0B72C}, /* 58 Mhz , for vco1div4 = 332 MHz */
280 {.div = 0x089EE}, /* 58 Mhz , for vc01div4 = 250 MHz*/
281 {.div = 0x06f1C}, /* 72 Mhz , for vc01div4 = 250 MHz*/
282 {.div = 0x06E58}, /* 58 Mhz , for vco1div4 = 200 MHz */
283 {.div = 0x06c1B}, /* 74 Mhz , for vc01div4 = 250 MHz*/
284 {.div = 0x04A12}, /* 108 Mhz , for vc01div4 = 250 MHz*/
285 {.div = 0x0378E}, /* 144 Mhz , for vc01div4 = 250 MHz*/
286};
287
288/* i2s prescaler1 masks */
289static struct aux_clk_masks i2s_prs1_masks = {
290 .eq_sel_mask = AUX_EQ_SEL_MASK,
291 .eq_sel_shift = SPEAR1310_I2S_PRS1_EQ_SEL_SHIFT,
292 .eq1_mask = AUX_EQ1_SEL,
293 .eq2_mask = AUX_EQ2_SEL,
294 .xscale_sel_mask = SPEAR1310_I2S_PRS1_CLK_X_MASK,
295 .xscale_sel_shift = SPEAR1310_I2S_PRS1_CLK_X_SHIFT,
296 .yscale_sel_mask = SPEAR1310_I2S_PRS1_CLK_Y_MASK,
297 .yscale_sel_shift = SPEAR1310_I2S_PRS1_CLK_Y_SHIFT,
298};
299
300/* i2s sclk (bit clock) syynthesizers masks */
301static struct aux_clk_masks i2s_sclk_masks = {
302 .eq_sel_mask = AUX_EQ_SEL_MASK,
303 .eq_sel_shift = SPEAR1310_I2S_SCLK_EQ_SEL_SHIFT,
304 .eq1_mask = AUX_EQ1_SEL,
305 .eq2_mask = AUX_EQ2_SEL,
306 .xscale_sel_mask = SPEAR1310_I2S_SCLK_X_MASK,
307 .xscale_sel_shift = SPEAR1310_I2S_SCLK_X_SHIFT,
308 .yscale_sel_mask = SPEAR1310_I2S_SCLK_Y_MASK,
309 .yscale_sel_shift = SPEAR1310_I2S_SCLK_Y_SHIFT,
310 .enable_bit = SPEAR1310_I2S_SCLK_SYNTH_ENB,
311};
312
313/* i2s prs1 aux rate configuration table, in ascending order of rates */
314static struct aux_rate_tbl i2s_prs1_rtbl[] = {
315 /* For parent clk = 49.152 MHz */
316 {.xscale = 1, .yscale = 2, .eq = 0}, /* 12.288 MHz */
317};
318
319/* i2s sclk aux rate configuration table, in ascending order of rates */
320static struct aux_rate_tbl i2s_sclk_rtbl[] = {
321 /* For i2s_ref_clk = 12.288MHz */
322 {.xscale = 1, .yscale = 4, .eq = 0}, /* 1.53 MHz */
323 {.xscale = 1, .yscale = 2, .eq = 0}, /* 3.07 Mhz */
324};
325
326/* adc rate configuration table, in ascending order of rates */
327/* possible adc range is 2.5 MHz to 20 MHz. */
328static struct aux_rate_tbl adc_rtbl[] = {
329 /* For ahb = 166.67 MHz */
330 {.xscale = 1, .yscale = 31, .eq = 0}, /* 2.68 MHz */
331 {.xscale = 2, .yscale = 21, .eq = 0}, /* 7.94 MHz */
332 {.xscale = 4, .yscale = 21, .eq = 0}, /* 15.87 MHz */
333 {.xscale = 10, .yscale = 42, .eq = 0}, /* 19.84 MHz */
334};
335
336/* General synth rate configuration table, in ascending order of rates */
337static struct frac_rate_tbl gen_rtbl[] = {
338 /* For vco1div4 = 250 MHz */
339 {.div = 0x14000}, /* 25 MHz */
340 {.div = 0x0A000}, /* 50 MHz */
341 {.div = 0x05000}, /* 100 MHz */
342 {.div = 0x02000}, /* 250 MHz */
343};
344
345/* clock parents */
346static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", };
347static const char *gpt_parents[] = { "osc_24m_clk", "apb_clk", };
348static const char *uart0_parents[] = { "pll5_clk", "uart_synth_gate_clk", };
349static const char *c3_parents[] = { "pll5_clk", "c3_synth_gate_clk", };
350static const char *gmac_phy_input_parents[] = { "gmii_125m_pad_clk", "pll2_clk",
351 "osc_25m_clk", };
352static const char *gmac_phy_parents[] = { "gmac_phy_input_mux_clk",
353 "gmac_phy_synth_gate_clk", };
354static const char *clcd_synth_parents[] = { "vco1div4_clk", "pll2_clk", };
355static const char *clcd_pixel_parents[] = { "pll5_clk", "clcd_synth_clk", };
356static const char *i2s_src_parents[] = { "vco1div2_clk", "none", "pll3_clk",
357 "i2s_src_pad_clk", };
358static const char *i2s_ref_parents[] = { "i2s_src_mux_clk", "i2s_prs1_clk", };
359static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk",
360 "pll3_clk", };
361static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco3div2_clk",
362 "pll2_clk", };
363static const char *rmii_phy_parents[] = { "ras_tx50_clk", "none",
364 "ras_pll2_clk", "ras_synth0_clk", };
365static const char *smii_rgmii_phy_parents[] = { "none", "ras_tx125_clk",
366 "ras_pll2_clk", "ras_synth0_clk", };
367static const char *uart_parents[] = { "ras_apb_clk", "gen_synth3_clk", };
368static const char *i2c_parents[] = { "ras_apb_clk", "gen_synth1_clk", };
369static const char *ssp1_parents[] = { "ras_apb_clk", "gen_synth1_clk",
370 "ras_plclk0_clk", };
371static const char *pci_parents[] = { "ras_pll3_clk", "gen_synth2_clk", };
372static const char *tdm_parents[] = { "ras_pll3_clk", "gen_synth1_clk", };
373
374void __init spear1310_clk_init(void)
375{
376 struct clk *clk, *clk1;
377
378 clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
379 clk_register_clkdev(clk, "apb_pclk", NULL);
380
381 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
382 32000);
383 clk_register_clkdev(clk, "osc_32k_clk", NULL);
384
385 clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT,
386 24000000);
387 clk_register_clkdev(clk, "osc_24m_clk", NULL);
388
389 clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, CLK_IS_ROOT,
390 25000000);
391 clk_register_clkdev(clk, "osc_25m_clk", NULL);
392
393 clk = clk_register_fixed_rate(NULL, "gmii_125m_pad_clk", NULL,
394 CLK_IS_ROOT, 125000000);
395 clk_register_clkdev(clk, "gmii_125m_pad_clk", NULL);
396
397 clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL,
398 CLK_IS_ROOT, 12288000);
399 clk_register_clkdev(clk, "i2s_src_pad_clk", NULL);
400
401 /* clock derived from 32 KHz osc clk */
402 clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0,
403 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_RTC_CLK_ENB, 0,
404 &_lock);
405 clk_register_clkdev(clk, NULL, "fc900000.rtc");
406
407 /* clock derived from 24 or 25 MHz osc clk */
408 /* vco-pll */
409 clk = clk_register_mux(NULL, "vco1_mux_clk", vco_parents,
410 ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG,
411 SPEAR1310_PLL1_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0,
412 &_lock);
413 clk_register_clkdev(clk, "vco1_mux_clk", NULL);
414 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mux_clk",
415 0, SPEAR1310_PLL1_CTR, SPEAR1310_PLL1_FRQ, pll_rtbl,
416 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
417 clk_register_clkdev(clk, "vco1_clk", NULL);
418 clk_register_clkdev(clk1, "pll1_clk", NULL);
419
420 clk = clk_register_mux(NULL, "vco2_mux_clk", vco_parents,
421 ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG,
422 SPEAR1310_PLL2_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0,
423 &_lock);
424 clk_register_clkdev(clk, "vco2_mux_clk", NULL);
425 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mux_clk",
426 0, SPEAR1310_PLL2_CTR, SPEAR1310_PLL2_FRQ, pll_rtbl,
427 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
428 clk_register_clkdev(clk, "vco2_clk", NULL);
429 clk_register_clkdev(clk1, "pll2_clk", NULL);
430
431 clk = clk_register_mux(NULL, "vco3_mux_clk", vco_parents,
432 ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG,
433 SPEAR1310_PLL3_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0,
434 &_lock);
435 clk_register_clkdev(clk, "vco3_mux_clk", NULL);
436 clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mux_clk",
437 0, SPEAR1310_PLL3_CTR, SPEAR1310_PLL3_FRQ, pll_rtbl,
438 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
439 clk_register_clkdev(clk, "vco3_clk", NULL);
440 clk_register_clkdev(clk1, "pll3_clk", NULL);
441
442 clk = clk_register_vco_pll("vco4_clk", "pll4_clk", NULL, "osc_24m_clk",
443 0, SPEAR1310_PLL4_CTR, SPEAR1310_PLL4_FRQ, pll4_rtbl,
444 ARRAY_SIZE(pll4_rtbl), &_lock, &clk1, NULL);
445 clk_register_clkdev(clk, "vco4_clk", NULL);
446 clk_register_clkdev(clk1, "pll4_clk", NULL);
447
448 clk = clk_register_fixed_rate(NULL, "pll5_clk", "osc_24m_clk", 0,
449 48000000);
450 clk_register_clkdev(clk, "pll5_clk", NULL);
451
452 clk = clk_register_fixed_rate(NULL, "pll6_clk", "osc_25m_clk", 0,
453 25000000);
454 clk_register_clkdev(clk, "pll6_clk", NULL);
455
456 /* vco div n clocks */
457 clk = clk_register_fixed_factor(NULL, "vco1div2_clk", "vco1_clk", 0, 1,
458 2);
459 clk_register_clkdev(clk, "vco1div2_clk", NULL);
460
461 clk = clk_register_fixed_factor(NULL, "vco1div4_clk", "vco1_clk", 0, 1,
462 4);
463 clk_register_clkdev(clk, "vco1div4_clk", NULL);
464
465 clk = clk_register_fixed_factor(NULL, "vco2div2_clk", "vco2_clk", 0, 1,
466 2);
467 clk_register_clkdev(clk, "vco2div2_clk", NULL);
468
469 clk = clk_register_fixed_factor(NULL, "vco3div2_clk", "vco3_clk", 0, 1,
470 2);
471 clk_register_clkdev(clk, "vco3div2_clk", NULL);
472
473 /* peripherals */
474 clk_register_fixed_factor(NULL, "thermal_clk", "osc_24m_clk", 0, 1,
475 128);
476 clk = clk_register_gate(NULL, "thermal_gate_clk", "thermal_clk", 0,
477 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_THSENS_CLK_ENB, 0,
478 &_lock);
479 clk_register_clkdev(clk, NULL, "spear_thermal");
480
481 /* clock derived from pll4 clk */
482 clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1,
483 1);
484 clk_register_clkdev(clk, "ddr_clk", NULL);
485
486 /* clock derived from pll1 clk */
487 clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", 0, 1, 2);
488 clk_register_clkdev(clk, "cpu_clk", NULL);
489
490 clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1,
491 2);
492 clk_register_clkdev(clk, NULL, "ec800620.wdt");
493
494 clk = clk_register_fixed_factor(NULL, "ahb_clk", "pll1_clk", 0, 1,
495 6);
496 clk_register_clkdev(clk, "ahb_clk", NULL);
497
498 clk = clk_register_fixed_factor(NULL, "apb_clk", "pll1_clk", 0, 1,
499 12);
500 clk_register_clkdev(clk, "apb_clk", NULL);
501
502 /* gpt clocks */
503 clk = clk_register_mux(NULL, "gpt0_mux_clk", gpt_parents,
504 ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
505 SPEAR1310_GPT0_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
506 &_lock);
507 clk_register_clkdev(clk, "gpt0_mux_clk", NULL);
508 clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mux_clk", 0,
509 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT0_CLK_ENB, 0,
510 &_lock);
511 clk_register_clkdev(clk, NULL, "gpt0");
512
513 clk = clk_register_mux(NULL, "gpt1_mux_clk", gpt_parents,
514 ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
515 SPEAR1310_GPT1_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
516 &_lock);
517 clk_register_clkdev(clk, "gpt1_mux_clk", NULL);
518 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mux_clk", 0,
519 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT1_CLK_ENB, 0,
520 &_lock);
521 clk_register_clkdev(clk, NULL, "gpt1");
522
523 clk = clk_register_mux(NULL, "gpt2_mux_clk", gpt_parents,
524 ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
525 SPEAR1310_GPT2_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
526 &_lock);
527 clk_register_clkdev(clk, "gpt2_mux_clk", NULL);
528 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mux_clk", 0,
529 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT2_CLK_ENB, 0,
530 &_lock);
531 clk_register_clkdev(clk, NULL, "gpt2");
532
533 clk = clk_register_mux(NULL, "gpt3_mux_clk", gpt_parents,
534 ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
535 SPEAR1310_GPT3_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
536 &_lock);
537 clk_register_clkdev(clk, "gpt3_mux_clk", NULL);
538 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mux_clk", 0,
539 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT3_CLK_ENB, 0,
540 &_lock);
541 clk_register_clkdev(clk, NULL, "gpt3");
542
543 /* others */
544 clk = clk_register_aux("uart_synth_clk", "uart_synth_gate_clk",
545 "vco1div2_clk", 0, SPEAR1310_UART_CLK_SYNT, NULL,
546 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
547 clk_register_clkdev(clk, "uart_synth_clk", NULL);
548 clk_register_clkdev(clk1, "uart_synth_gate_clk", NULL);
549
550 clk = clk_register_mux(NULL, "uart0_mux_clk", uart0_parents,
551 ARRAY_SIZE(uart0_parents), 0, SPEAR1310_PERIP_CLK_CFG,
552 SPEAR1310_UART_CLK_SHIFT, SPEAR1310_UART_CLK_MASK, 0,
553 &_lock);
554 clk_register_clkdev(clk, "uart0_mux_clk", NULL);
555
556 clk = clk_register_gate(NULL, "uart0_clk", "uart0_mux_clk", 0,
557 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UART_CLK_ENB, 0,
558 &_lock);
559 clk_register_clkdev(clk, NULL, "e0000000.serial");
560
561 clk = clk_register_aux("sdhci_synth_clk", "sdhci_synth_gate_clk",
562 "vco1div2_clk", 0, SPEAR1310_SDHCI_CLK_SYNT, NULL,
563 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
564 clk_register_clkdev(clk, "sdhci_synth_clk", NULL);
565 clk_register_clkdev(clk1, "sdhci_synth_gate_clk", NULL);
566
567 clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_synth_gate_clk", 0,
568 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SDHCI_CLK_ENB, 0,
569 &_lock);
570 clk_register_clkdev(clk, NULL, "b3000000.sdhci");
571
572 clk = clk_register_aux("cfxd_synth_clk", "cfxd_synth_gate_clk",
573 "vco1div2_clk", 0, SPEAR1310_CFXD_CLK_SYNT, NULL,
574 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
575 clk_register_clkdev(clk, "cfxd_synth_clk", NULL);
576 clk_register_clkdev(clk1, "cfxd_synth_gate_clk", NULL);
577
578 clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_synth_gate_clk", 0,
579 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_CFXD_CLK_ENB, 0,
580 &_lock);
581 clk_register_clkdev(clk, NULL, "b2800000.cf");
582 clk_register_clkdev(clk, NULL, "arasan_xd");
583
584 clk = clk_register_aux("c3_synth_clk", "c3_synth_gate_clk",
585 "vco1div2_clk", 0, SPEAR1310_C3_CLK_SYNT, NULL,
586 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
587 clk_register_clkdev(clk, "c3_synth_clk", NULL);
588 clk_register_clkdev(clk1, "c3_synth_gate_clk", NULL);
589
590 clk = clk_register_mux(NULL, "c3_mux_clk", c3_parents,
591 ARRAY_SIZE(c3_parents), 0, SPEAR1310_PERIP_CLK_CFG,
592 SPEAR1310_C3_CLK_SHIFT, SPEAR1310_C3_CLK_MASK, 0,
593 &_lock);
594 clk_register_clkdev(clk, "c3_mux_clk", NULL);
595
596 clk = clk_register_gate(NULL, "c3_clk", "c3_mux_clk", 0,
597 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_C3_CLK_ENB, 0,
598 &_lock);
599 clk_register_clkdev(clk, NULL, "c3");
600
601 /* gmac */
602 clk = clk_register_mux(NULL, "gmac_phy_input_mux_clk",
603 gmac_phy_input_parents,
604 ARRAY_SIZE(gmac_phy_input_parents), 0,
605 SPEAR1310_GMAC_CLK_CFG,
606 SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT,
607 SPEAR1310_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock);
608 clk_register_clkdev(clk, "gmac_phy_input_mux_clk", NULL);
609
610 clk = clk_register_aux("gmac_phy_synth_clk", "gmac_phy_synth_gate_clk",
611 "gmac_phy_input_mux_clk", 0, SPEAR1310_GMAC_CLK_SYNT,
612 NULL, gmac_rtbl, ARRAY_SIZE(gmac_rtbl), &_lock, &clk1);
613 clk_register_clkdev(clk, "gmac_phy_synth_clk", NULL);
614 clk_register_clkdev(clk1, "gmac_phy_synth_gate_clk", NULL);
615
616 clk = clk_register_mux(NULL, "gmac_phy_mux_clk", gmac_phy_parents,
617 ARRAY_SIZE(gmac_phy_parents), 0,
618 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GMAC_PHY_CLK_SHIFT,
619 SPEAR1310_GMAC_PHY_CLK_MASK, 0, &_lock);
620 clk_register_clkdev(clk, NULL, "stmmacphy.0");
621
622 /* clcd */
623 clk = clk_register_mux(NULL, "clcd_synth_mux_clk", clcd_synth_parents,
624 ARRAY_SIZE(clcd_synth_parents), 0,
625 SPEAR1310_CLCD_CLK_SYNT, SPEAR1310_CLCD_SYNT_CLK_SHIFT,
626 SPEAR1310_CLCD_SYNT_CLK_MASK, 0, &_lock);
627 clk_register_clkdev(clk, "clcd_synth_mux_clk", NULL);
628
629 clk = clk_register_frac("clcd_synth_clk", "clcd_synth_mux_clk", 0,
630 SPEAR1310_CLCD_CLK_SYNT, clcd_rtbl,
631 ARRAY_SIZE(clcd_rtbl), &_lock);
632 clk_register_clkdev(clk, "clcd_synth_clk", NULL);
633
634 clk = clk_register_mux(NULL, "clcd_pixel_mux_clk", clcd_pixel_parents,
635 ARRAY_SIZE(clcd_pixel_parents), 0,
636 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_CLCD_CLK_SHIFT,
637 SPEAR1310_CLCD_CLK_MASK, 0, &_lock);
638 clk_register_clkdev(clk, "clcd_pixel_clk", NULL);
639
640 clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mux_clk", 0,
641 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_CLCD_CLK_ENB, 0,
642 &_lock);
643 clk_register_clkdev(clk, "clcd_clk", NULL);
644
645 /* i2s */
646 clk = clk_register_mux(NULL, "i2s_src_mux_clk", i2s_src_parents,
647 ARRAY_SIZE(i2s_src_parents), 0, SPEAR1310_I2S_CLK_CFG,
648 SPEAR1310_I2S_SRC_CLK_SHIFT, SPEAR1310_I2S_SRC_CLK_MASK,
649 0, &_lock);
650 clk_register_clkdev(clk, "i2s_src_clk", NULL);
651
652 clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mux_clk", 0,
653 SPEAR1310_I2S_CLK_CFG, &i2s_prs1_masks, i2s_prs1_rtbl,
654 ARRAY_SIZE(i2s_prs1_rtbl), &_lock, NULL);
655 clk_register_clkdev(clk, "i2s_prs1_clk", NULL);
656
657 clk = clk_register_mux(NULL, "i2s_ref_mux_clk", i2s_ref_parents,
658 ARRAY_SIZE(i2s_ref_parents), 0, SPEAR1310_I2S_CLK_CFG,
659 SPEAR1310_I2S_REF_SHIFT, SPEAR1310_I2S_REF_SEL_MASK, 0,
660 &_lock);
661 clk_register_clkdev(clk, "i2s_ref_clk", NULL);
662
663 clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mux_clk", 0,
664 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_I2S_REF_PAD_CLK_ENB,
665 0, &_lock);
666 clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL);
667
668 clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gate_clk",
669 "i2s_ref_pad_clk", 0, SPEAR1310_I2S_CLK_CFG,
670 &i2s_sclk_masks, i2s_sclk_rtbl,
671 ARRAY_SIZE(i2s_sclk_rtbl), &_lock, &clk1);
672 clk_register_clkdev(clk, "i2s_sclk_clk", NULL);
673 clk_register_clkdev(clk1, "i2s_sclk_gate_clk", NULL);
674
675 /* clock derived from ahb clk */
676 clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0,
677 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2C0_CLK_ENB, 0,
678 &_lock);
679 clk_register_clkdev(clk, NULL, "e0280000.i2c");
680
681 clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0,
682 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_DMA_CLK_ENB, 0,
683 &_lock);
684 clk_register_clkdev(clk, NULL, "ea800000.dma");
685 clk_register_clkdev(clk, NULL, "eb000000.dma");
686
687 clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0,
688 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_JPEG_CLK_ENB, 0,
689 &_lock);
690 clk_register_clkdev(clk, NULL, "b2000000.jpeg");
691
692 clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0,
693 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GMAC_CLK_ENB, 0,
694 &_lock);
695 clk_register_clkdev(clk, NULL, "e2000000.eth");
696
697 clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0,
698 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_FSMC_CLK_ENB, 0,
699 &_lock);
700 clk_register_clkdev(clk, NULL, "b0000000.flash");
701
702 clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0,
703 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SMI_CLK_ENB, 0,
704 &_lock);
705 clk_register_clkdev(clk, NULL, "ea000000.flash");
706
707 clk = clk_register_gate(NULL, "usbh0_clk", "ahb_clk", 0,
708 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC0_CLK_ENB, 0,
709 &_lock);
710 clk_register_clkdev(clk, "usbh.0_clk", NULL);
711
712 clk = clk_register_gate(NULL, "usbh1_clk", "ahb_clk", 0,
713 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC1_CLK_ENB, 0,
714 &_lock);
715 clk_register_clkdev(clk, "usbh.1_clk", NULL);
716
717 clk = clk_register_gate(NULL, "uoc_clk", "ahb_clk", 0,
718 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UOC_CLK_ENB, 0,
719 &_lock);
720 clk_register_clkdev(clk, NULL, "uoc");
721
722 clk = clk_register_gate(NULL, "pcie_sata_0_clk", "ahb_clk", 0,
723 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_0_CLK_ENB,
724 0, &_lock);
725 clk_register_clkdev(clk, NULL, "dw_pcie.0");
726 clk_register_clkdev(clk, NULL, "ahci.0");
727
728 clk = clk_register_gate(NULL, "pcie_sata_1_clk", "ahb_clk", 0,
729 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_1_CLK_ENB,
730 0, &_lock);
731 clk_register_clkdev(clk, NULL, "dw_pcie.1");
732 clk_register_clkdev(clk, NULL, "ahci.1");
733
734 clk = clk_register_gate(NULL, "pcie_sata_2_clk", "ahb_clk", 0,
735 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_2_CLK_ENB,
736 0, &_lock);
737 clk_register_clkdev(clk, NULL, "dw_pcie.2");
738 clk_register_clkdev(clk, NULL, "ahci.2");
739
740 clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
741 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SYSRAM0_CLK_ENB, 0,
742 &_lock);
743 clk_register_clkdev(clk, "sysram0_clk", NULL);
744
745 clk = clk_register_gate(NULL, "sysram1_clk", "ahb_clk", 0,
746 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SYSRAM1_CLK_ENB, 0,
747 &_lock);
748 clk_register_clkdev(clk, "sysram1_clk", NULL);
749
750 clk = clk_register_aux("adc_synth_clk", "adc_synth_gate_clk", "ahb_clk",
751 0, SPEAR1310_ADC_CLK_SYNT, NULL, adc_rtbl,
752 ARRAY_SIZE(adc_rtbl), &_lock, &clk1);
753 clk_register_clkdev(clk, "adc_synth_clk", NULL);
754 clk_register_clkdev(clk1, "adc_synth_gate_clk", NULL);
755
756 clk = clk_register_gate(NULL, "adc_clk", "adc_synth_gate_clk", 0,
757 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_ADC_CLK_ENB, 0,
758 &_lock);
759 clk_register_clkdev(clk, NULL, "adc_clk");
760
761 /* clock derived from apb clk */
762 clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0,
763 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SSP_CLK_ENB, 0,
764 &_lock);
765 clk_register_clkdev(clk, NULL, "e0100000.spi");
766
767 clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0,
768 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPIO0_CLK_ENB, 0,
769 &_lock);
770 clk_register_clkdev(clk, NULL, "e0600000.gpio");
771
772 clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0,
773 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPIO1_CLK_ENB, 0,
774 &_lock);
775 clk_register_clkdev(clk, NULL, "e0680000.gpio");
776
777 clk = clk_register_gate(NULL, "i2s0_clk", "apb_clk", 0,
778 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2S0_CLK_ENB, 0,
779 &_lock);
780 clk_register_clkdev(clk, NULL, "e0180000.i2s");
781
782 clk = clk_register_gate(NULL, "i2s1_clk", "apb_clk", 0,
783 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2S1_CLK_ENB, 0,
784 &_lock);
785 clk_register_clkdev(clk, NULL, "e0200000.i2s");
786
787 clk = clk_register_gate(NULL, "kbd_clk", "apb_clk", 0,
788 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_KBD_CLK_ENB, 0,
789 &_lock);
790 clk_register_clkdev(clk, NULL, "e0300000.kbd");
791
792 /* RAS clks */
793 clk = clk_register_mux(NULL, "gen_synth0_1_mux_clk",
794 gen_synth0_1_parents, ARRAY_SIZE(gen_synth0_1_parents),
795 0, SPEAR1310_PLL_CFG, SPEAR1310_RAS_SYNT0_1_CLK_SHIFT,
796 SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock);
797 clk_register_clkdev(clk, "gen_synth0_1_clk", NULL);
798
799 clk = clk_register_mux(NULL, "gen_synth2_3_mux_clk",
800 gen_synth2_3_parents, ARRAY_SIZE(gen_synth2_3_parents),
801 0, SPEAR1310_PLL_CFG, SPEAR1310_RAS_SYNT2_3_CLK_SHIFT,
802 SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock);
803 clk_register_clkdev(clk, "gen_synth2_3_clk", NULL);
804
805 clk = clk_register_frac("gen_synth0_clk", "gen_synth0_1_clk", 0,
806 SPEAR1310_RAS_CLK_SYNT0, gen_rtbl, ARRAY_SIZE(gen_rtbl),
807 &_lock);
808 clk_register_clkdev(clk, "gen_synth0_clk", NULL);
809
810 clk = clk_register_frac("gen_synth1_clk", "gen_synth0_1_clk", 0,
811 SPEAR1310_RAS_CLK_SYNT1, gen_rtbl, ARRAY_SIZE(gen_rtbl),
812 &_lock);
813 clk_register_clkdev(clk, "gen_synth1_clk", NULL);
814
815 clk = clk_register_frac("gen_synth2_clk", "gen_synth2_3_clk", 0,
816 SPEAR1310_RAS_CLK_SYNT2, gen_rtbl, ARRAY_SIZE(gen_rtbl),
817 &_lock);
818 clk_register_clkdev(clk, "gen_synth2_clk", NULL);
819
820 clk = clk_register_frac("gen_synth3_clk", "gen_synth2_3_clk", 0,
821 SPEAR1310_RAS_CLK_SYNT3, gen_rtbl, ARRAY_SIZE(gen_rtbl),
822 &_lock);
823 clk_register_clkdev(clk, "gen_synth3_clk", NULL);
824
825 clk = clk_register_gate(NULL, "ras_osc_24m_clk", "osc_24m_clk", 0,
826 SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_24M_CLK_ENB, 0,
827 &_lock);
828 clk_register_clkdev(clk, "ras_osc_24m_clk", NULL);
829
830 clk = clk_register_gate(NULL, "ras_osc_25m_clk", "osc_25m_clk", 0,
831 SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_25M_CLK_ENB, 0,
832 &_lock);
833 clk_register_clkdev(clk, "ras_osc_25m_clk", NULL);
834
835 clk = clk_register_gate(NULL, "ras_osc_32k_clk", "osc_32k_clk", 0,
836 SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_32K_CLK_ENB, 0,
837 &_lock);
838 clk_register_clkdev(clk, "ras_osc_32k_clk", NULL);
839
840 clk = clk_register_gate(NULL, "ras_pll2_clk", "pll2_clk", 0,
841 SPEAR1310_RAS_CLK_ENB, SPEAR1310_PLL2_CLK_ENB, 0,
842 &_lock);
843 clk_register_clkdev(clk, "ras_pll2_clk", NULL);
844
845 clk = clk_register_gate(NULL, "ras_pll3_clk", "pll3_clk", 0,
846 SPEAR1310_RAS_CLK_ENB, SPEAR1310_PLL3_CLK_ENB, 0,
847 &_lock);
848 clk_register_clkdev(clk, "ras_pll3_clk", NULL);
849
850 clk = clk_register_gate(NULL, "ras_tx125_clk", "gmii_125m_pad_clk", 0,
851 SPEAR1310_RAS_CLK_ENB, SPEAR1310_C125M_PAD_CLK_ENB, 0,
852 &_lock);
853 clk_register_clkdev(clk, "ras_tx125_clk", NULL);
854
855 clk = clk_register_fixed_rate(NULL, "ras_30m_fixed_clk", "pll5_clk", 0,
856 30000000);
857 clk = clk_register_gate(NULL, "ras_30m_clk", "ras_30m_fixed_clk", 0,
858 SPEAR1310_RAS_CLK_ENB, SPEAR1310_C30M_CLK_ENB, 0,
859 &_lock);
860 clk_register_clkdev(clk, "ras_30m_clk", NULL);
861
862 clk = clk_register_fixed_rate(NULL, "ras_48m_fixed_clk", "pll5_clk", 0,
863 48000000);
864 clk = clk_register_gate(NULL, "ras_48m_clk", "ras_48m_fixed_clk", 0,
865 SPEAR1310_RAS_CLK_ENB, SPEAR1310_C48M_CLK_ENB, 0,
866 &_lock);
867 clk_register_clkdev(clk, "ras_48m_clk", NULL);
868
869 clk = clk_register_gate(NULL, "ras_ahb_clk", "ahb_clk", 0,
870 SPEAR1310_RAS_CLK_ENB, SPEAR1310_ACLK_CLK_ENB, 0,
871 &_lock);
872 clk_register_clkdev(clk, "ras_ahb_clk", NULL);
873
874 clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0,
875 SPEAR1310_RAS_CLK_ENB, SPEAR1310_PCLK_CLK_ENB, 0,
876 &_lock);
877 clk_register_clkdev(clk, "ras_apb_clk", NULL);
878
879 clk = clk_register_fixed_rate(NULL, "ras_plclk0_clk", NULL, CLK_IS_ROOT,
880 50000000);
881
882 clk = clk_register_fixed_rate(NULL, "ras_tx50_clk", NULL, CLK_IS_ROOT,
883 50000000);
884
885 clk = clk_register_gate(NULL, "can0_clk", "apb_clk", 0,
886 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_CAN0_CLK_ENB, 0,
887 &_lock);
888 clk_register_clkdev(clk, NULL, "c_can_platform.0");
889
890 clk = clk_register_gate(NULL, "can1_clk", "apb_clk", 0,
891 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_CAN1_CLK_ENB, 0,
892 &_lock);
893 clk_register_clkdev(clk, NULL, "c_can_platform.1");
894
895 clk = clk_register_gate(NULL, "ras_smii0_clk", "ras_ahb_clk", 0,
896 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII0_CLK_ENB, 0,
897 &_lock);
898 clk_register_clkdev(clk, NULL, "5c400000.eth");
899
900 clk = clk_register_gate(NULL, "ras_smii1_clk", "ras_ahb_clk", 0,
901 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII1_CLK_ENB, 0,
902 &_lock);
903 clk_register_clkdev(clk, NULL, "5c500000.eth");
904
905 clk = clk_register_gate(NULL, "ras_smii2_clk", "ras_ahb_clk", 0,
906 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII2_CLK_ENB, 0,
907 &_lock);
908 clk_register_clkdev(clk, NULL, "5c600000.eth");
909
910 clk = clk_register_gate(NULL, "ras_rgmii_clk", "ras_ahb_clk", 0,
911 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_GMII_CLK_ENB, 0,
912 &_lock);
913 clk_register_clkdev(clk, NULL, "5c700000.eth");
914
915 clk = clk_register_mux(NULL, "smii_rgmii_phy_mux_clk",
916 smii_rgmii_phy_parents,
917 ARRAY_SIZE(smii_rgmii_phy_parents), 0,
918 SPEAR1310_RAS_CTRL_REG1,
919 SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT,
920 SPEAR1310_PHY_CLK_MASK, 0, &_lock);
921 clk_register_clkdev(clk, NULL, "stmmacphy.1");
922 clk_register_clkdev(clk, NULL, "stmmacphy.2");
923 clk_register_clkdev(clk, NULL, "stmmacphy.4");
924
925 clk = clk_register_mux(NULL, "rmii_phy_mux_clk", rmii_phy_parents,
926 ARRAY_SIZE(rmii_phy_parents), 0,
927 SPEAR1310_RAS_CTRL_REG1, SPEAR1310_RMII_PHY_CLK_SHIFT,
928 SPEAR1310_PHY_CLK_MASK, 0, &_lock);
929 clk_register_clkdev(clk, NULL, "stmmacphy.3");
930
931 clk = clk_register_mux(NULL, "uart1_mux_clk", uart_parents,
932 ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
933 SPEAR1310_UART1_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
934 0, &_lock);
935 clk_register_clkdev(clk, "uart1_mux_clk", NULL);
936
937 clk = clk_register_gate(NULL, "uart1_clk", "uart1_mux_clk", 0,
938 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART1_CLK_ENB, 0,
939 &_lock);
940 clk_register_clkdev(clk, NULL, "5c800000.serial");
941
942 clk = clk_register_mux(NULL, "uart2_mux_clk", uart_parents,
943 ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
944 SPEAR1310_UART2_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
945 0, &_lock);
946 clk_register_clkdev(clk, "uart2_mux_clk", NULL);
947
948 clk = clk_register_gate(NULL, "uart2_clk", "uart2_mux_clk", 0,
949 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART2_CLK_ENB, 0,
950 &_lock);
951 clk_register_clkdev(clk, NULL, "5c900000.serial");
952
953 clk = clk_register_mux(NULL, "uart3_mux_clk", uart_parents,
954 ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
955 SPEAR1310_UART3_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
956 0, &_lock);
957 clk_register_clkdev(clk, "uart3_mux_clk", NULL);
958
959 clk = clk_register_gate(NULL, "uart3_clk", "uart3_mux_clk", 0,
960 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART3_CLK_ENB, 0,
961 &_lock);
962 clk_register_clkdev(clk, NULL, "5ca00000.serial");
963
964 clk = clk_register_mux(NULL, "uart4_mux_clk", uart_parents,
965 ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
966 SPEAR1310_UART4_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
967 0, &_lock);
968 clk_register_clkdev(clk, "uart4_mux_clk", NULL);
969
970 clk = clk_register_gate(NULL, "uart4_clk", "uart4_mux_clk", 0,
971 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART4_CLK_ENB, 0,
972 &_lock);
973 clk_register_clkdev(clk, NULL, "5cb00000.serial");
974
975 clk = clk_register_mux(NULL, "uart5_mux_clk", uart_parents,
976 ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
977 SPEAR1310_UART5_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
978 0, &_lock);
979 clk_register_clkdev(clk, "uart5_mux_clk", NULL);
980
981 clk = clk_register_gate(NULL, "uart5_clk", "uart5_mux_clk", 0,
982 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART5_CLK_ENB, 0,
983 &_lock);
984 clk_register_clkdev(clk, NULL, "5cc00000.serial");
985
986 clk = clk_register_mux(NULL, "i2c1_mux_clk", i2c_parents,
987 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
988 SPEAR1310_I2C1_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
989 &_lock);
990 clk_register_clkdev(clk, "i2c1_mux_clk", NULL);
991
992 clk = clk_register_gate(NULL, "i2c1_clk", "i2c1_mux_clk", 0,
993 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C1_CLK_ENB, 0,
994 &_lock);
995 clk_register_clkdev(clk, NULL, "5cd00000.i2c");
996
997 clk = clk_register_mux(NULL, "i2c2_mux_clk", i2c_parents,
998 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
999 SPEAR1310_I2C2_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1000 &_lock);
1001 clk_register_clkdev(clk, "i2c2_mux_clk", NULL);
1002
1003 clk = clk_register_gate(NULL, "i2c2_clk", "i2c2_mux_clk", 0,
1004 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C2_CLK_ENB, 0,
1005 &_lock);
1006 clk_register_clkdev(clk, NULL, "5ce00000.i2c");
1007
1008 clk = clk_register_mux(NULL, "i2c3_mux_clk", i2c_parents,
1009 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1010 SPEAR1310_I2C3_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1011 &_lock);
1012 clk_register_clkdev(clk, "i2c3_mux_clk", NULL);
1013
1014 clk = clk_register_gate(NULL, "i2c3_clk", "i2c3_mux_clk", 0,
1015 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C3_CLK_ENB, 0,
1016 &_lock);
1017 clk_register_clkdev(clk, NULL, "5cf00000.i2c");
1018
1019 clk = clk_register_mux(NULL, "i2c4_mux_clk", i2c_parents,
1020 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1021 SPEAR1310_I2C4_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1022 &_lock);
1023 clk_register_clkdev(clk, "i2c4_mux_clk", NULL);
1024
1025 clk = clk_register_gate(NULL, "i2c4_clk", "i2c4_mux_clk", 0,
1026 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C4_CLK_ENB, 0,
1027 &_lock);
1028 clk_register_clkdev(clk, NULL, "5d000000.i2c");
1029
1030 clk = clk_register_mux(NULL, "i2c5_mux_clk", i2c_parents,
1031 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1032 SPEAR1310_I2C5_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1033 &_lock);
1034 clk_register_clkdev(clk, "i2c5_mux_clk", NULL);
1035
1036 clk = clk_register_gate(NULL, "i2c5_clk", "i2c5_mux_clk", 0,
1037 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C5_CLK_ENB, 0,
1038 &_lock);
1039 clk_register_clkdev(clk, NULL, "5d100000.i2c");
1040
1041 clk = clk_register_mux(NULL, "i2c6_mux_clk", i2c_parents,
1042 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1043 SPEAR1310_I2C6_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1044 &_lock);
1045 clk_register_clkdev(clk, "i2c6_mux_clk", NULL);
1046
1047 clk = clk_register_gate(NULL, "i2c6_clk", "i2c6_mux_clk", 0,
1048 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C6_CLK_ENB, 0,
1049 &_lock);
1050 clk_register_clkdev(clk, NULL, "5d200000.i2c");
1051
1052 clk = clk_register_mux(NULL, "i2c7_mux_clk", i2c_parents,
1053 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1054 SPEAR1310_I2C7_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1055 &_lock);
1056 clk_register_clkdev(clk, "i2c7_mux_clk", NULL);
1057
1058 clk = clk_register_gate(NULL, "i2c7_clk", "i2c7_mux_clk", 0,
1059 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C7_CLK_ENB, 0,
1060 &_lock);
1061 clk_register_clkdev(clk, NULL, "5d300000.i2c");
1062
1063 clk = clk_register_mux(NULL, "ssp1_mux_clk", ssp1_parents,
1064 ARRAY_SIZE(ssp1_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1065 SPEAR1310_SSP1_CLK_SHIFT, SPEAR1310_SSP1_CLK_MASK, 0,
1066 &_lock);
1067 clk_register_clkdev(clk, "ssp1_mux_clk", NULL);
1068
1069 clk = clk_register_gate(NULL, "ssp1_clk", "ssp1_mux_clk", 0,
1070 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_SSP1_CLK_ENB, 0,
1071 &_lock);
1072 clk_register_clkdev(clk, NULL, "5d400000.spi");
1073
1074 clk = clk_register_mux(NULL, "pci_mux_clk", pci_parents,
1075 ARRAY_SIZE(pci_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1076 SPEAR1310_PCI_CLK_SHIFT, SPEAR1310_PCI_CLK_MASK, 0,
1077 &_lock);
1078 clk_register_clkdev(clk, "pci_mux_clk", NULL);
1079
1080 clk = clk_register_gate(NULL, "pci_clk", "pci_mux_clk", 0,
1081 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_PCI_CLK_ENB, 0,
1082 &_lock);
1083 clk_register_clkdev(clk, NULL, "pci");
1084
1085 clk = clk_register_mux(NULL, "tdm1_mux_clk", tdm_parents,
1086 ARRAY_SIZE(tdm_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1087 SPEAR1310_TDM1_CLK_SHIFT, SPEAR1310_TDM_CLK_MASK, 0,
1088 &_lock);
1089 clk_register_clkdev(clk, "tdm1_mux_clk", NULL);
1090
1091 clk = clk_register_gate(NULL, "tdm1_clk", "tdm1_mux_clk", 0,
1092 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_TDM1_CLK_ENB, 0,
1093 &_lock);
1094 clk_register_clkdev(clk, NULL, "tdm_hdlc.0");
1095
1096 clk = clk_register_mux(NULL, "tdm2_mux_clk", tdm_parents,
1097 ARRAY_SIZE(tdm_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1098 SPEAR1310_TDM2_CLK_SHIFT, SPEAR1310_TDM_CLK_MASK, 0,
1099 &_lock);
1100 clk_register_clkdev(clk, "tdm2_mux_clk", NULL);
1101
1102 clk = clk_register_gate(NULL, "tdm2_clk", "tdm2_mux_clk", 0,
1103 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_TDM2_CLK_ENB, 0,
1104 &_lock);
1105 clk_register_clkdev(clk, NULL, "tdm_hdlc.1");
1106}
diff --git a/drivers/clk/spear/spear1340_clock.c b/drivers/clk/spear/spear1340_clock.c
new file mode 100644
index 000000000000..f130919d5bf8
--- /dev/null
+++ b/drivers/clk/spear/spear1340_clock.c
@@ -0,0 +1,964 @@
1/*
2 * arch/arm/mach-spear13xx/spear1340_clock.c
3 *
4 * SPEAr1340 machine clock framework source file
5 *
6 * Copyright (C) 2012 ST Microelectronics
7 * Viresh Kumar <viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/clk.h>
15#include <linux/clkdev.h>
16#include <linux/err.h>
17#include <linux/io.h>
18#include <linux/of_platform.h>
19#include <linux/spinlock_types.h>
20#include <mach/spear.h>
21#include "clk.h"
22
23/* Clock Configuration Registers */
24#define SPEAR1340_SYS_CLK_CTRL (VA_MISC_BASE + 0x200)
25 #define SPEAR1340_HCLK_SRC_SEL_SHIFT 27
26 #define SPEAR1340_HCLK_SRC_SEL_MASK 1
27 #define SPEAR1340_SCLK_SRC_SEL_SHIFT 23
28 #define SPEAR1340_SCLK_SRC_SEL_MASK 3
29
30/* PLL related registers and bit values */
31#define SPEAR1340_PLL_CFG (VA_MISC_BASE + 0x210)
32 /* PLL_CFG bit values */
33 #define SPEAR1340_CLCD_SYNT_CLK_MASK 1
34 #define SPEAR1340_CLCD_SYNT_CLK_SHIFT 31
35 #define SPEAR1340_GEN_SYNT2_3_CLK_SHIFT 29
36 #define SPEAR1340_GEN_SYNT_CLK_MASK 2
37 #define SPEAR1340_GEN_SYNT0_1_CLK_SHIFT 27
38 #define SPEAR1340_PLL_CLK_MASK 2
39 #define SPEAR1340_PLL3_CLK_SHIFT 24
40 #define SPEAR1340_PLL2_CLK_SHIFT 22
41 #define SPEAR1340_PLL1_CLK_SHIFT 20
42
43#define SPEAR1340_PLL1_CTR (VA_MISC_BASE + 0x214)
44#define SPEAR1340_PLL1_FRQ (VA_MISC_BASE + 0x218)
45#define SPEAR1340_PLL2_CTR (VA_MISC_BASE + 0x220)
46#define SPEAR1340_PLL2_FRQ (VA_MISC_BASE + 0x224)
47#define SPEAR1340_PLL3_CTR (VA_MISC_BASE + 0x22C)
48#define SPEAR1340_PLL3_FRQ (VA_MISC_BASE + 0x230)
49#define SPEAR1340_PLL4_CTR (VA_MISC_BASE + 0x238)
50#define SPEAR1340_PLL4_FRQ (VA_MISC_BASE + 0x23C)
51#define SPEAR1340_PERIP_CLK_CFG (VA_MISC_BASE + 0x244)
52 /* PERIP_CLK_CFG bit values */
53 #define SPEAR1340_SPDIF_CLK_MASK 1
54 #define SPEAR1340_SPDIF_OUT_CLK_SHIFT 15
55 #define SPEAR1340_SPDIF_IN_CLK_SHIFT 14
56 #define SPEAR1340_GPT3_CLK_SHIFT 13
57 #define SPEAR1340_GPT2_CLK_SHIFT 12
58 #define SPEAR1340_GPT_CLK_MASK 1
59 #define SPEAR1340_GPT1_CLK_SHIFT 9
60 #define SPEAR1340_GPT0_CLK_SHIFT 8
61 #define SPEAR1340_UART_CLK_MASK 2
62 #define SPEAR1340_UART1_CLK_SHIFT 6
63 #define SPEAR1340_UART0_CLK_SHIFT 4
64 #define SPEAR1340_CLCD_CLK_MASK 2
65 #define SPEAR1340_CLCD_CLK_SHIFT 2
66 #define SPEAR1340_C3_CLK_MASK 1
67 #define SPEAR1340_C3_CLK_SHIFT 1
68
69#define SPEAR1340_GMAC_CLK_CFG (VA_MISC_BASE + 0x248)
70 #define SPEAR1340_GMAC_PHY_CLK_MASK 1
71 #define SPEAR1340_GMAC_PHY_CLK_SHIFT 2
72 #define SPEAR1340_GMAC_PHY_INPUT_CLK_MASK 2
73 #define SPEAR1340_GMAC_PHY_INPUT_CLK_SHIFT 0
74
75#define SPEAR1340_I2S_CLK_CFG (VA_MISC_BASE + 0x24C)
76 /* I2S_CLK_CFG register mask */
77 #define SPEAR1340_I2S_SCLK_X_MASK 0x1F
78 #define SPEAR1340_I2S_SCLK_X_SHIFT 27
79 #define SPEAR1340_I2S_SCLK_Y_MASK 0x1F
80 #define SPEAR1340_I2S_SCLK_Y_SHIFT 22
81 #define SPEAR1340_I2S_SCLK_EQ_SEL_SHIFT 21
82 #define SPEAR1340_I2S_SCLK_SYNTH_ENB 20
83 #define SPEAR1340_I2S_PRS1_CLK_X_MASK 0xFF
84 #define SPEAR1340_I2S_PRS1_CLK_X_SHIFT 12
85 #define SPEAR1340_I2S_PRS1_CLK_Y_MASK 0xFF
86 #define SPEAR1340_I2S_PRS1_CLK_Y_SHIFT 4
87 #define SPEAR1340_I2S_PRS1_EQ_SEL_SHIFT 3
88 #define SPEAR1340_I2S_REF_SEL_MASK 1
89 #define SPEAR1340_I2S_REF_SHIFT 2
90 #define SPEAR1340_I2S_SRC_CLK_MASK 2
91 #define SPEAR1340_I2S_SRC_CLK_SHIFT 0
92
93#define SPEAR1340_C3_CLK_SYNT (VA_MISC_BASE + 0x250)
94#define SPEAR1340_UART0_CLK_SYNT (VA_MISC_BASE + 0x254)
95#define SPEAR1340_UART1_CLK_SYNT (VA_MISC_BASE + 0x258)
96#define SPEAR1340_GMAC_CLK_SYNT (VA_MISC_BASE + 0x25C)
97#define SPEAR1340_SDHCI_CLK_SYNT (VA_MISC_BASE + 0x260)
98#define SPEAR1340_CFXD_CLK_SYNT (VA_MISC_BASE + 0x264)
99#define SPEAR1340_ADC_CLK_SYNT (VA_MISC_BASE + 0x270)
100#define SPEAR1340_AMBA_CLK_SYNT (VA_MISC_BASE + 0x274)
101#define SPEAR1340_CLCD_CLK_SYNT (VA_MISC_BASE + 0x27C)
102#define SPEAR1340_SYS_CLK_SYNT (VA_MISC_BASE + 0x284)
103#define SPEAR1340_GEN_CLK_SYNT0 (VA_MISC_BASE + 0x28C)
104#define SPEAR1340_GEN_CLK_SYNT1 (VA_MISC_BASE + 0x294)
105#define SPEAR1340_GEN_CLK_SYNT2 (VA_MISC_BASE + 0x29C)
106#define SPEAR1340_GEN_CLK_SYNT3 (VA_MISC_BASE + 0x304)
107#define SPEAR1340_PERIP1_CLK_ENB (VA_MISC_BASE + 0x30C)
108 #define SPEAR1340_RTC_CLK_ENB 31
109 #define SPEAR1340_ADC_CLK_ENB 30
110 #define SPEAR1340_C3_CLK_ENB 29
111 #define SPEAR1340_CLCD_CLK_ENB 27
112 #define SPEAR1340_DMA_CLK_ENB 25
113 #define SPEAR1340_GPIO1_CLK_ENB 24
114 #define SPEAR1340_GPIO0_CLK_ENB 23
115 #define SPEAR1340_GPT1_CLK_ENB 22
116 #define SPEAR1340_GPT0_CLK_ENB 21
117 #define SPEAR1340_I2S_PLAY_CLK_ENB 20
118 #define SPEAR1340_I2S_REC_CLK_ENB 19
119 #define SPEAR1340_I2C0_CLK_ENB 18
120 #define SPEAR1340_SSP_CLK_ENB 17
121 #define SPEAR1340_UART0_CLK_ENB 15
122 #define SPEAR1340_PCIE_SATA_CLK_ENB 12
123 #define SPEAR1340_UOC_CLK_ENB 11
124 #define SPEAR1340_UHC1_CLK_ENB 10
125 #define SPEAR1340_UHC0_CLK_ENB 9
126 #define SPEAR1340_GMAC_CLK_ENB 8
127 #define SPEAR1340_CFXD_CLK_ENB 7
128 #define SPEAR1340_SDHCI_CLK_ENB 6
129 #define SPEAR1340_SMI_CLK_ENB 5
130 #define SPEAR1340_FSMC_CLK_ENB 4
131 #define SPEAR1340_SYSRAM0_CLK_ENB 3
132 #define SPEAR1340_SYSRAM1_CLK_ENB 2
133 #define SPEAR1340_SYSROM_CLK_ENB 1
134 #define SPEAR1340_BUS_CLK_ENB 0
135
136#define SPEAR1340_PERIP2_CLK_ENB (VA_MISC_BASE + 0x310)
137 #define SPEAR1340_THSENS_CLK_ENB 8
138 #define SPEAR1340_I2S_REF_PAD_CLK_ENB 7
139 #define SPEAR1340_ACP_CLK_ENB 6
140 #define SPEAR1340_GPT3_CLK_ENB 5
141 #define SPEAR1340_GPT2_CLK_ENB 4
142 #define SPEAR1340_KBD_CLK_ENB 3
143 #define SPEAR1340_CPU_DBG_CLK_ENB 2
144 #define SPEAR1340_DDR_CORE_CLK_ENB 1
145 #define SPEAR1340_DDR_CTRL_CLK_ENB 0
146
147#define SPEAR1340_PERIP3_CLK_ENB (VA_MISC_BASE + 0x314)
148 #define SPEAR1340_PLGPIO_CLK_ENB 18
149 #define SPEAR1340_VIDEO_DEC_CLK_ENB 16
150 #define SPEAR1340_VIDEO_ENC_CLK_ENB 15
151 #define SPEAR1340_SPDIF_OUT_CLK_ENB 13
152 #define SPEAR1340_SPDIF_IN_CLK_ENB 12
153 #define SPEAR1340_VIDEO_IN_CLK_ENB 11
154 #define SPEAR1340_CAM0_CLK_ENB 10
155 #define SPEAR1340_CAM1_CLK_ENB 9
156 #define SPEAR1340_CAM2_CLK_ENB 8
157 #define SPEAR1340_CAM3_CLK_ENB 7
158 #define SPEAR1340_MALI_CLK_ENB 6
159 #define SPEAR1340_CEC0_CLK_ENB 5
160 #define SPEAR1340_CEC1_CLK_ENB 4
161 #define SPEAR1340_PWM_CLK_ENB 3
162 #define SPEAR1340_I2C1_CLK_ENB 2
163 #define SPEAR1340_UART1_CLK_ENB 1
164
165static DEFINE_SPINLOCK(_lock);
166
167/* pll rate configuration table, in ascending order of rates */
168static struct pll_rate_tbl pll_rtbl[] = {
169 /* PCLK 24MHz */
170 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
171 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
172 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
173 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
174 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
175 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
176 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
177 {.mode = 0, .m = 0x96, .n = 0x06, .p = 0x0}, /* vco 1200, pll 1200 MHz */
178};
179
180/* vco-pll4 rate configuration table, in ascending order of rates */
181static struct pll_rate_tbl pll4_rtbl[] = {
182 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
183 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
184 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x2}, /* vco 1600, pll 400 MHz */
185 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
186};
187
188/*
189 * All below entries generate 166 MHz for
190 * different values of vco1div2
191 */
192static struct frac_rate_tbl amba_synth_rtbl[] = {
193 {.div = 0x06062}, /* for vco1div2 = 500 MHz */
194 {.div = 0x04D1B}, /* for vco1div2 = 400 MHz */
195 {.div = 0x04000}, /* for vco1div2 = 332 MHz */
196 {.div = 0x03031}, /* for vco1div2 = 250 MHz */
197 {.div = 0x0268D}, /* for vco1div2 = 200 MHz */
198};
199
200/*
201 * Synthesizer Clock derived from vcodiv2. This clock is one of the
202 * possible clocks to feed cpu directly.
203 * We can program this synthesizer to make cpu run on different clock
204 * frequencies.
205 * Following table provides configuration values to let cpu run on 200,
206 * 250, 332, 400 or 500 MHz considering different possibilites of input
207 * (vco1div2) clock.
208 *
209 * --------------------------------------------------------------------
210 * vco1div2(Mhz) fout(Mhz) cpuclk = fout/2 div
211 * --------------------------------------------------------------------
212 * 400 200 100 0x04000
213 * 400 250 125 0x03333
214 * 400 332 166 0x0268D
215 * 400 400 200 0x02000
216 * --------------------------------------------------------------------
217 * 500 200 100 0x05000
218 * 500 250 125 0x04000
219 * 500 332 166 0x03031
220 * 500 400 200 0x02800
221 * 500 500 250 0x02000
222 * --------------------------------------------------------------------
223 * 664 200 100 0x06a38
224 * 664 250 125 0x054FD
225 * 664 332 166 0x04000
226 * 664 400 200 0x0351E
227 * 664 500 250 0x02A7E
228 * --------------------------------------------------------------------
229 * 800 200 100 0x08000
230 * 800 250 125 0x06666
231 * 800 332 166 0x04D18
232 * 800 400 200 0x04000
233 * 800 500 250 0x03333
234 * --------------------------------------------------------------------
235 * sys rate configuration table is in descending order of divisor.
236 */
237static struct frac_rate_tbl sys_synth_rtbl[] = {
238 {.div = 0x08000},
239 {.div = 0x06a38},
240 {.div = 0x06666},
241 {.div = 0x054FD},
242 {.div = 0x05000},
243 {.div = 0x04D18},
244 {.div = 0x04000},
245 {.div = 0x0351E},
246 {.div = 0x03333},
247 {.div = 0x03031},
248 {.div = 0x02A7E},
249 {.div = 0x02800},
250 {.div = 0x0268D},
251 {.div = 0x02000},
252};
253
254/* aux rate configuration table, in ascending order of rates */
255static struct aux_rate_tbl aux_rtbl[] = {
256 /* For VCO1div2 = 500 MHz */
257 {.xscale = 10, .yscale = 204, .eq = 0}, /* 12.29 MHz */
258 {.xscale = 4, .yscale = 21, .eq = 0}, /* 48 MHz */
259 {.xscale = 2, .yscale = 6, .eq = 0}, /* 83 MHz */
260 {.xscale = 2, .yscale = 4, .eq = 0}, /* 125 MHz */
261 {.xscale = 1, .yscale = 3, .eq = 1}, /* 166 MHz */
262 {.xscale = 1, .yscale = 2, .eq = 1}, /* 250 MHz */
263};
264
265/* gmac rate configuration table, in ascending order of rates */
266static struct aux_rate_tbl gmac_rtbl[] = {
267 /* For gmac phy input clk */
268 {.xscale = 2, .yscale = 6, .eq = 0}, /* divided by 6 */
269 {.xscale = 2, .yscale = 4, .eq = 0}, /* divided by 4 */
270 {.xscale = 1, .yscale = 3, .eq = 1}, /* divided by 3 */
271 {.xscale = 1, .yscale = 2, .eq = 1}, /* divided by 2 */
272};
273
274/* clcd rate configuration table, in ascending order of rates */
275static struct frac_rate_tbl clcd_rtbl[] = {
276 {.div = 0x14000}, /* 25 Mhz , for vc01div4 = 250 MHz*/
277 {.div = 0x1284B}, /* 27 Mhz , for vc01div4 = 250 MHz*/
278 {.div = 0x0D8D3}, /* 58 Mhz , for vco1div4 = 393 MHz */
279 {.div = 0x0B72C}, /* 58 Mhz , for vco1div4 = 332 MHz */
280 {.div = 0x089EE}, /* 58 Mhz , for vc01div4 = 250 MHz*/
281 {.div = 0x07BA0}, /* 65 Mhz , for vc01div4 = 250 MHz*/
282 {.div = 0x06f1C}, /* 72 Mhz , for vc01div4 = 250 MHz*/
283 {.div = 0x06E58}, /* 58 Mhz , for vco1div4 = 200 MHz */
284 {.div = 0x06c1B}, /* 74 Mhz , for vc01div4 = 250 MHz*/
285 {.div = 0x04A12}, /* 108 Mhz , for vc01div4 = 250 MHz*/
286 {.div = 0x0378E}, /* 144 Mhz , for vc01div4 = 250 MHz*/
287 {.div = 0x0360D}, /* 148 Mhz , for vc01div4 = 250 MHz*/
288 {.div = 0x035E0}, /* 148.5 MHz, for vc01div4 = 250 MHz*/
289};
290
291/* i2s prescaler1 masks */
292static struct aux_clk_masks i2s_prs1_masks = {
293 .eq_sel_mask = AUX_EQ_SEL_MASK,
294 .eq_sel_shift = SPEAR1340_I2S_PRS1_EQ_SEL_SHIFT,
295 .eq1_mask = AUX_EQ1_SEL,
296 .eq2_mask = AUX_EQ2_SEL,
297 .xscale_sel_mask = SPEAR1340_I2S_PRS1_CLK_X_MASK,
298 .xscale_sel_shift = SPEAR1340_I2S_PRS1_CLK_X_SHIFT,
299 .yscale_sel_mask = SPEAR1340_I2S_PRS1_CLK_Y_MASK,
300 .yscale_sel_shift = SPEAR1340_I2S_PRS1_CLK_Y_SHIFT,
301};
302
303/* i2s sclk (bit clock) syynthesizers masks */
304static struct aux_clk_masks i2s_sclk_masks = {
305 .eq_sel_mask = AUX_EQ_SEL_MASK,
306 .eq_sel_shift = SPEAR1340_I2S_SCLK_EQ_SEL_SHIFT,
307 .eq1_mask = AUX_EQ1_SEL,
308 .eq2_mask = AUX_EQ2_SEL,
309 .xscale_sel_mask = SPEAR1340_I2S_SCLK_X_MASK,
310 .xscale_sel_shift = SPEAR1340_I2S_SCLK_X_SHIFT,
311 .yscale_sel_mask = SPEAR1340_I2S_SCLK_Y_MASK,
312 .yscale_sel_shift = SPEAR1340_I2S_SCLK_Y_SHIFT,
313 .enable_bit = SPEAR1340_I2S_SCLK_SYNTH_ENB,
314};
315
316/* i2s prs1 aux rate configuration table, in ascending order of rates */
317static struct aux_rate_tbl i2s_prs1_rtbl[] = {
318 /* For parent clk = 49.152 MHz */
319 {.xscale = 1, .yscale = 12, .eq = 0}, /* 2.048 MHz, smp freq = 8Khz */
320 {.xscale = 11, .yscale = 96, .eq = 0}, /* 2.816 MHz, smp freq = 11Khz */
321 {.xscale = 1, .yscale = 6, .eq = 0}, /* 4.096 MHz, smp freq = 16Khz */
322 {.xscale = 11, .yscale = 48, .eq = 0}, /* 5.632 MHz, smp freq = 22Khz */
323
324 /*
325 * with parent clk = 49.152, freq gen is 8.192 MHz, smp freq = 32Khz
326 * with parent clk = 12.288, freq gen is 2.048 MHz, smp freq = 8Khz
327 */
328 {.xscale = 1, .yscale = 3, .eq = 0},
329
330 /* For parent clk = 49.152 MHz */
331 {.xscale = 17, .yscale = 37, .eq = 0}, /* 11.289 MHz, smp freq = 44Khz*/
332 {.xscale = 1, .yscale = 2, .eq = 0}, /* 12.288 MHz, smp freq = 48Khz*/
333};
334
335/* i2s sclk aux rate configuration table, in ascending order of rates */
336static struct aux_rate_tbl i2s_sclk_rtbl[] = {
337 /* For sclk = ref_clk * x/2/y */
338 {.xscale = 1, .yscale = 4, .eq = 0},
339 {.xscale = 1, .yscale = 2, .eq = 0},
340};
341
342/* adc rate configuration table, in ascending order of rates */
343/* possible adc range is 2.5 MHz to 20 MHz. */
344static struct aux_rate_tbl adc_rtbl[] = {
345 /* For ahb = 166.67 MHz */
346 {.xscale = 1, .yscale = 31, .eq = 0}, /* 2.68 MHz */
347 {.xscale = 2, .yscale = 21, .eq = 0}, /* 7.94 MHz */
348 {.xscale = 4, .yscale = 21, .eq = 0}, /* 15.87 MHz */
349 {.xscale = 10, .yscale = 42, .eq = 0}, /* 19.84 MHz */
350};
351
352/* General synth rate configuration table, in ascending order of rates */
353static struct frac_rate_tbl gen_rtbl[] = {
354 /* For vco1div4 = 250 MHz */
355 {.div = 0x1624E}, /* 22.5792 MHz */
356 {.div = 0x14585}, /* 24.576 MHz */
357 {.div = 0x14000}, /* 25 MHz */
358 {.div = 0x0B127}, /* 45.1584 MHz */
359 {.div = 0x0A000}, /* 50 MHz */
360 {.div = 0x061A8}, /* 81.92 MHz */
361 {.div = 0x05000}, /* 100 MHz */
362 {.div = 0x02800}, /* 200 MHz */
363 {.div = 0x02620}, /* 210 MHz */
364 {.div = 0x02460}, /* 220 MHz */
365 {.div = 0x022C0}, /* 230 MHz */
366 {.div = 0x02160}, /* 240 MHz */
367 {.div = 0x02000}, /* 250 MHz */
368};
369
370/* clock parents */
371static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", };
372static const char *sys_parents[] = { "none", "pll1_clk", "none", "none",
373 "sys_synth_clk", "none", "pll2_clk", "pll3_clk", };
374static const char *ahb_parents[] = { "cpu_div3_clk", "amba_synth_clk", };
375static const char *gpt_parents[] = { "osc_24m_clk", "apb_clk", };
376static const char *uart0_parents[] = { "pll5_clk", "osc_24m_clk",
377 "uart0_synth_gate_clk", };
378static const char *uart1_parents[] = { "pll5_clk", "osc_24m_clk",
379 "uart1_synth_gate_clk", };
380static const char *c3_parents[] = { "pll5_clk", "c3_synth_gate_clk", };
381static const char *gmac_phy_input_parents[] = { "gmii_125m_pad_clk", "pll2_clk",
382 "osc_25m_clk", };
383static const char *gmac_phy_parents[] = { "gmac_phy_input_mux_clk",
384 "gmac_phy_synth_gate_clk", };
385static const char *clcd_synth_parents[] = { "vco1div4_clk", "pll2_clk", };
386static const char *clcd_pixel_parents[] = { "pll5_clk", "clcd_synth_clk", };
387static const char *i2s_src_parents[] = { "vco1div2_clk", "pll2_clk", "pll3_clk",
388 "i2s_src_pad_clk", };
389static const char *i2s_ref_parents[] = { "i2s_src_mux_clk", "i2s_prs1_clk", };
390static const char *spdif_out_parents[] = { "i2s_src_pad_clk", "gen_synth2_clk",
391};
392static const char *spdif_in_parents[] = { "pll2_clk", "gen_synth3_clk", };
393
394static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk",
395 "pll3_clk", };
396static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco3div2_clk",
397 "pll2_clk", };
398
399void __init spear1340_clk_init(void)
400{
401 struct clk *clk, *clk1;
402
403 clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
404 clk_register_clkdev(clk, "apb_pclk", NULL);
405
406 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
407 32000);
408 clk_register_clkdev(clk, "osc_32k_clk", NULL);
409
410 clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT,
411 24000000);
412 clk_register_clkdev(clk, "osc_24m_clk", NULL);
413
414 clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, CLK_IS_ROOT,
415 25000000);
416 clk_register_clkdev(clk, "osc_25m_clk", NULL);
417
418 clk = clk_register_fixed_rate(NULL, "gmii_125m_pad_clk", NULL,
419 CLK_IS_ROOT, 125000000);
420 clk_register_clkdev(clk, "gmii_125m_pad_clk", NULL);
421
422 clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL,
423 CLK_IS_ROOT, 12288000);
424 clk_register_clkdev(clk, "i2s_src_pad_clk", NULL);
425
426 /* clock derived from 32 KHz osc clk */
427 clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0,
428 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_RTC_CLK_ENB, 0,
429 &_lock);
430 clk_register_clkdev(clk, NULL, "fc900000.rtc");
431
432 /* clock derived from 24 or 25 MHz osc clk */
433 /* vco-pll */
434 clk = clk_register_mux(NULL, "vco1_mux_clk", vco_parents,
435 ARRAY_SIZE(vco_parents), 0, SPEAR1340_PLL_CFG,
436 SPEAR1340_PLL1_CLK_SHIFT, SPEAR1340_PLL_CLK_MASK, 0,
437 &_lock);
438 clk_register_clkdev(clk, "vco1_mux_clk", NULL);
439 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mux_clk",
440 0, SPEAR1340_PLL1_CTR, SPEAR1340_PLL1_FRQ, pll_rtbl,
441 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
442 clk_register_clkdev(clk, "vco1_clk", NULL);
443 clk_register_clkdev(clk1, "pll1_clk", NULL);
444
445 clk = clk_register_mux(NULL, "vco2_mux_clk", vco_parents,
446 ARRAY_SIZE(vco_parents), 0, SPEAR1340_PLL_CFG,
447 SPEAR1340_PLL2_CLK_SHIFT, SPEAR1340_PLL_CLK_MASK, 0,
448 &_lock);
449 clk_register_clkdev(clk, "vco2_mux_clk", NULL);
450 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mux_clk",
451 0, SPEAR1340_PLL2_CTR, SPEAR1340_PLL2_FRQ, pll_rtbl,
452 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
453 clk_register_clkdev(clk, "vco2_clk", NULL);
454 clk_register_clkdev(clk1, "pll2_clk", NULL);
455
456 clk = clk_register_mux(NULL, "vco3_mux_clk", vco_parents,
457 ARRAY_SIZE(vco_parents), 0, SPEAR1340_PLL_CFG,
458 SPEAR1340_PLL3_CLK_SHIFT, SPEAR1340_PLL_CLK_MASK, 0,
459 &_lock);
460 clk_register_clkdev(clk, "vco3_mux_clk", NULL);
461 clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mux_clk",
462 0, SPEAR1340_PLL3_CTR, SPEAR1340_PLL3_FRQ, pll_rtbl,
463 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
464 clk_register_clkdev(clk, "vco3_clk", NULL);
465 clk_register_clkdev(clk1, "pll3_clk", NULL);
466
467 clk = clk_register_vco_pll("vco4_clk", "pll4_clk", NULL, "osc_24m_clk",
468 0, SPEAR1340_PLL4_CTR, SPEAR1340_PLL4_FRQ, pll4_rtbl,
469 ARRAY_SIZE(pll4_rtbl), &_lock, &clk1, NULL);
470 clk_register_clkdev(clk, "vco4_clk", NULL);
471 clk_register_clkdev(clk1, "pll4_clk", NULL);
472
473 clk = clk_register_fixed_rate(NULL, "pll5_clk", "osc_24m_clk", 0,
474 48000000);
475 clk_register_clkdev(clk, "pll5_clk", NULL);
476
477 clk = clk_register_fixed_rate(NULL, "pll6_clk", "osc_25m_clk", 0,
478 25000000);
479 clk_register_clkdev(clk, "pll6_clk", NULL);
480
481 /* vco div n clocks */
482 clk = clk_register_fixed_factor(NULL, "vco1div2_clk", "vco1_clk", 0, 1,
483 2);
484 clk_register_clkdev(clk, "vco1div2_clk", NULL);
485
486 clk = clk_register_fixed_factor(NULL, "vco1div4_clk", "vco1_clk", 0, 1,
487 4);
488 clk_register_clkdev(clk, "vco1div4_clk", NULL);
489
490 clk = clk_register_fixed_factor(NULL, "vco2div2_clk", "vco2_clk", 0, 1,
491 2);
492 clk_register_clkdev(clk, "vco2div2_clk", NULL);
493
494 clk = clk_register_fixed_factor(NULL, "vco3div2_clk", "vco3_clk", 0, 1,
495 2);
496 clk_register_clkdev(clk, "vco3div2_clk", NULL);
497
498 /* peripherals */
499 clk_register_fixed_factor(NULL, "thermal_clk", "osc_24m_clk", 0, 1,
500 128);
501 clk = clk_register_gate(NULL, "thermal_gate_clk", "thermal_clk", 0,
502 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_THSENS_CLK_ENB, 0,
503 &_lock);
504 clk_register_clkdev(clk, NULL, "spear_thermal");
505
506 /* clock derived from pll4 clk */
507 clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1,
508 1);
509 clk_register_clkdev(clk, "ddr_clk", NULL);
510
511 /* clock derived from pll1 clk */
512 clk = clk_register_frac("sys_synth_clk", "vco1div2_clk", 0,
513 SPEAR1340_SYS_CLK_SYNT, sys_synth_rtbl,
514 ARRAY_SIZE(sys_synth_rtbl), &_lock);
515 clk_register_clkdev(clk, "sys_synth_clk", NULL);
516
517 clk = clk_register_frac("amba_synth_clk", "vco1div2_clk", 0,
518 SPEAR1340_AMBA_CLK_SYNT, amba_synth_rtbl,
519 ARRAY_SIZE(amba_synth_rtbl), &_lock);
520 clk_register_clkdev(clk, "amba_synth_clk", NULL);
521
522 clk = clk_register_mux(NULL, "sys_mux_clk", sys_parents,
523 ARRAY_SIZE(sys_parents), 0, SPEAR1340_SYS_CLK_CTRL,
524 SPEAR1340_SCLK_SRC_SEL_SHIFT,
525 SPEAR1340_SCLK_SRC_SEL_MASK, 0, &_lock);
526 clk_register_clkdev(clk, "sys_clk", NULL);
527
528 clk = clk_register_fixed_factor(NULL, "cpu_clk", "sys_mux_clk", 0, 1,
529 2);
530 clk_register_clkdev(clk, "cpu_clk", NULL);
531
532 clk = clk_register_fixed_factor(NULL, "cpu_div3_clk", "cpu_clk", 0, 1,
533 3);
534 clk_register_clkdev(clk, "cpu_div3_clk", NULL);
535
536 clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1,
537 2);
538 clk_register_clkdev(clk, NULL, "ec800620.wdt");
539
540 clk = clk_register_mux(NULL, "ahb_clk", ahb_parents,
541 ARRAY_SIZE(ahb_parents), 0, SPEAR1340_SYS_CLK_CTRL,
542 SPEAR1340_HCLK_SRC_SEL_SHIFT,
543 SPEAR1340_HCLK_SRC_SEL_MASK, 0, &_lock);
544 clk_register_clkdev(clk, "ahb_clk", NULL);
545
546 clk = clk_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1,
547 2);
548 clk_register_clkdev(clk, "apb_clk", NULL);
549
550 /* gpt clocks */
551 clk = clk_register_mux(NULL, "gpt0_mux_clk", gpt_parents,
552 ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG,
553 SPEAR1340_GPT0_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0,
554 &_lock);
555 clk_register_clkdev(clk, "gpt0_mux_clk", NULL);
556 clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mux_clk", 0,
557 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPT0_CLK_ENB, 0,
558 &_lock);
559 clk_register_clkdev(clk, NULL, "gpt0");
560
561 clk = clk_register_mux(NULL, "gpt1_mux_clk", gpt_parents,
562 ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG,
563 SPEAR1340_GPT1_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0,
564 &_lock);
565 clk_register_clkdev(clk, "gpt1_mux_clk", NULL);
566 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mux_clk", 0,
567 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPT1_CLK_ENB, 0,
568 &_lock);
569 clk_register_clkdev(clk, NULL, "gpt1");
570
571 clk = clk_register_mux(NULL, "gpt2_mux_clk", gpt_parents,
572 ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG,
573 SPEAR1340_GPT2_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0,
574 &_lock);
575 clk_register_clkdev(clk, "gpt2_mux_clk", NULL);
576 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mux_clk", 0,
577 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_GPT2_CLK_ENB, 0,
578 &_lock);
579 clk_register_clkdev(clk, NULL, "gpt2");
580
581 clk = clk_register_mux(NULL, "gpt3_mux_clk", gpt_parents,
582 ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG,
583 SPEAR1340_GPT3_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0,
584 &_lock);
585 clk_register_clkdev(clk, "gpt3_mux_clk", NULL);
586 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mux_clk", 0,
587 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_GPT3_CLK_ENB, 0,
588 &_lock);
589 clk_register_clkdev(clk, NULL, "gpt3");
590
591 /* others */
592 clk = clk_register_aux("uart0_synth_clk", "uart0_synth_gate_clk",
593 "vco1div2_clk", 0, SPEAR1340_UART0_CLK_SYNT, NULL,
594 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
595 clk_register_clkdev(clk, "uart0_synth_clk", NULL);
596 clk_register_clkdev(clk1, "uart0_synth_gate_clk", NULL);
597
598 clk = clk_register_mux(NULL, "uart0_mux_clk", uart0_parents,
599 ARRAY_SIZE(uart0_parents), 0, SPEAR1340_PERIP_CLK_CFG,
600 SPEAR1340_UART0_CLK_SHIFT, SPEAR1340_UART_CLK_MASK, 0,
601 &_lock);
602 clk_register_clkdev(clk, "uart0_mux_clk", NULL);
603
604 clk = clk_register_gate(NULL, "uart0_clk", "uart0_mux_clk", 0,
605 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UART0_CLK_ENB, 0,
606 &_lock);
607 clk_register_clkdev(clk, NULL, "e0000000.serial");
608
609 clk = clk_register_aux("uart1_synth_clk", "uart1_synth_gate_clk",
610 "vco1div2_clk", 0, SPEAR1340_UART1_CLK_SYNT, NULL,
611 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
612 clk_register_clkdev(clk, "uart1_synth_clk", NULL);
613 clk_register_clkdev(clk1, "uart1_synth_gate_clk", NULL);
614
615 clk = clk_register_mux(NULL, "uart1_mux_clk", uart1_parents,
616 ARRAY_SIZE(uart1_parents), 0, SPEAR1340_PERIP_CLK_CFG,
617 SPEAR1340_UART1_CLK_SHIFT, SPEAR1340_UART_CLK_MASK, 0,
618 &_lock);
619 clk_register_clkdev(clk, "uart1_mux_clk", NULL);
620
621 clk = clk_register_gate(NULL, "uart1_clk", "uart1_mux_clk", 0,
622 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UART1_CLK_ENB, 0,
623 &_lock);
624 clk_register_clkdev(clk, NULL, "b4100000.serial");
625
626 clk = clk_register_aux("sdhci_synth_clk", "sdhci_synth_gate_clk",
627 "vco1div2_clk", 0, SPEAR1340_SDHCI_CLK_SYNT, NULL,
628 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
629 clk_register_clkdev(clk, "sdhci_synth_clk", NULL);
630 clk_register_clkdev(clk1, "sdhci_synth_gate_clk", NULL);
631
632 clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_synth_gate_clk", 0,
633 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SDHCI_CLK_ENB, 0,
634 &_lock);
635 clk_register_clkdev(clk, NULL, "b3000000.sdhci");
636
637 clk = clk_register_aux("cfxd_synth_clk", "cfxd_synth_gate_clk",
638 "vco1div2_clk", 0, SPEAR1340_CFXD_CLK_SYNT, NULL,
639 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
640 clk_register_clkdev(clk, "cfxd_synth_clk", NULL);
641 clk_register_clkdev(clk1, "cfxd_synth_gate_clk", NULL);
642
643 clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_synth_gate_clk", 0,
644 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_CFXD_CLK_ENB, 0,
645 &_lock);
646 clk_register_clkdev(clk, NULL, "b2800000.cf");
647 clk_register_clkdev(clk, NULL, "arasan_xd");
648
649 clk = clk_register_aux("c3_synth_clk", "c3_synth_gate_clk",
650 "vco1div2_clk", 0, SPEAR1340_C3_CLK_SYNT, NULL,
651 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
652 clk_register_clkdev(clk, "c3_synth_clk", NULL);
653 clk_register_clkdev(clk1, "c3_synth_gate_clk", NULL);
654
655 clk = clk_register_mux(NULL, "c3_mux_clk", c3_parents,
656 ARRAY_SIZE(c3_parents), 0, SPEAR1340_PERIP_CLK_CFG,
657 SPEAR1340_C3_CLK_SHIFT, SPEAR1340_C3_CLK_MASK, 0,
658 &_lock);
659 clk_register_clkdev(clk, "c3_mux_clk", NULL);
660
661 clk = clk_register_gate(NULL, "c3_clk", "c3_mux_clk", 0,
662 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_C3_CLK_ENB, 0,
663 &_lock);
664 clk_register_clkdev(clk, NULL, "c3");
665
666 /* gmac */
667 clk = clk_register_mux(NULL, "gmac_phy_input_mux_clk",
668 gmac_phy_input_parents,
669 ARRAY_SIZE(gmac_phy_input_parents), 0,
670 SPEAR1340_GMAC_CLK_CFG,
671 SPEAR1340_GMAC_PHY_INPUT_CLK_SHIFT,
672 SPEAR1340_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock);
673 clk_register_clkdev(clk, "gmac_phy_input_mux_clk", NULL);
674
675 clk = clk_register_aux("gmac_phy_synth_clk", "gmac_phy_synth_gate_clk",
676 "gmac_phy_input_mux_clk", 0, SPEAR1340_GMAC_CLK_SYNT,
677 NULL, gmac_rtbl, ARRAY_SIZE(gmac_rtbl), &_lock, &clk1);
678 clk_register_clkdev(clk, "gmac_phy_synth_clk", NULL);
679 clk_register_clkdev(clk1, "gmac_phy_synth_gate_clk", NULL);
680
681 clk = clk_register_mux(NULL, "gmac_phy_mux_clk", gmac_phy_parents,
682 ARRAY_SIZE(gmac_phy_parents), 0,
683 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GMAC_PHY_CLK_SHIFT,
684 SPEAR1340_GMAC_PHY_CLK_MASK, 0, &_lock);
685 clk_register_clkdev(clk, NULL, "stmmacphy.0");
686
687 /* clcd */
688 clk = clk_register_mux(NULL, "clcd_synth_mux_clk", clcd_synth_parents,
689 ARRAY_SIZE(clcd_synth_parents), 0,
690 SPEAR1340_CLCD_CLK_SYNT, SPEAR1340_CLCD_SYNT_CLK_SHIFT,
691 SPEAR1340_CLCD_SYNT_CLK_MASK, 0, &_lock);
692 clk_register_clkdev(clk, "clcd_synth_mux_clk", NULL);
693
694 clk = clk_register_frac("clcd_synth_clk", "clcd_synth_mux_clk", 0,
695 SPEAR1340_CLCD_CLK_SYNT, clcd_rtbl,
696 ARRAY_SIZE(clcd_rtbl), &_lock);
697 clk_register_clkdev(clk, "clcd_synth_clk", NULL);
698
699 clk = clk_register_mux(NULL, "clcd_pixel_mux_clk", clcd_pixel_parents,
700 ARRAY_SIZE(clcd_pixel_parents), 0,
701 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_CLCD_CLK_SHIFT,
702 SPEAR1340_CLCD_CLK_MASK, 0, &_lock);
703 clk_register_clkdev(clk, "clcd_pixel_clk", NULL);
704
705 clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mux_clk", 0,
706 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_CLCD_CLK_ENB, 0,
707 &_lock);
708 clk_register_clkdev(clk, "clcd_clk", NULL);
709
710 /* i2s */
711 clk = clk_register_mux(NULL, "i2s_src_mux_clk", i2s_src_parents,
712 ARRAY_SIZE(i2s_src_parents), 0, SPEAR1340_I2S_CLK_CFG,
713 SPEAR1340_I2S_SRC_CLK_SHIFT, SPEAR1340_I2S_SRC_CLK_MASK,
714 0, &_lock);
715 clk_register_clkdev(clk, "i2s_src_clk", NULL);
716
717 clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mux_clk", 0,
718 SPEAR1340_I2S_CLK_CFG, &i2s_prs1_masks, i2s_prs1_rtbl,
719 ARRAY_SIZE(i2s_prs1_rtbl), &_lock, NULL);
720 clk_register_clkdev(clk, "i2s_prs1_clk", NULL);
721
722 clk = clk_register_mux(NULL, "i2s_ref_mux_clk", i2s_ref_parents,
723 ARRAY_SIZE(i2s_ref_parents), 0, SPEAR1340_I2S_CLK_CFG,
724 SPEAR1340_I2S_REF_SHIFT, SPEAR1340_I2S_REF_SEL_MASK, 0,
725 &_lock);
726 clk_register_clkdev(clk, "i2s_ref_clk", NULL);
727
728 clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mux_clk", 0,
729 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_I2S_REF_PAD_CLK_ENB,
730 0, &_lock);
731 clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL);
732
733 clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gate_clk",
734 "i2s_ref_mux_clk", 0, SPEAR1340_I2S_CLK_CFG,
735 &i2s_sclk_masks, i2s_sclk_rtbl,
736 ARRAY_SIZE(i2s_sclk_rtbl), &_lock, &clk1);
737 clk_register_clkdev(clk, "i2s_sclk_clk", NULL);
738 clk_register_clkdev(clk1, "i2s_sclk_gate_clk", NULL);
739
740 /* clock derived from ahb clk */
741 clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0,
742 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2C0_CLK_ENB, 0,
743 &_lock);
744 clk_register_clkdev(clk, NULL, "e0280000.i2c");
745
746 clk = clk_register_gate(NULL, "i2c1_clk", "ahb_clk", 0,
747 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2C1_CLK_ENB, 0,
748 &_lock);
749 clk_register_clkdev(clk, NULL, "b4000000.i2c");
750
751 clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0,
752 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_DMA_CLK_ENB, 0,
753 &_lock);
754 clk_register_clkdev(clk, NULL, "ea800000.dma");
755 clk_register_clkdev(clk, NULL, "eb000000.dma");
756
757 clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0,
758 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GMAC_CLK_ENB, 0,
759 &_lock);
760 clk_register_clkdev(clk, NULL, "e2000000.eth");
761
762 clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0,
763 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_FSMC_CLK_ENB, 0,
764 &_lock);
765 clk_register_clkdev(clk, NULL, "b0000000.flash");
766
767 clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0,
768 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SMI_CLK_ENB, 0,
769 &_lock);
770 clk_register_clkdev(clk, NULL, "ea000000.flash");
771
772 clk = clk_register_gate(NULL, "usbh0_clk", "ahb_clk", 0,
773 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UHC0_CLK_ENB, 0,
774 &_lock);
775 clk_register_clkdev(clk, "usbh.0_clk", NULL);
776
777 clk = clk_register_gate(NULL, "usbh1_clk", "ahb_clk", 0,
778 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UHC1_CLK_ENB, 0,
779 &_lock);
780 clk_register_clkdev(clk, "usbh.1_clk", NULL);
781
782 clk = clk_register_gate(NULL, "uoc_clk", "ahb_clk", 0,
783 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UOC_CLK_ENB, 0,
784 &_lock);
785 clk_register_clkdev(clk, NULL, "uoc");
786
787 clk = clk_register_gate(NULL, "pcie_sata_clk", "ahb_clk", 0,
788 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_PCIE_SATA_CLK_ENB,
789 0, &_lock);
790 clk_register_clkdev(clk, NULL, "dw_pcie");
791 clk_register_clkdev(clk, NULL, "ahci");
792
793 clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
794 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SYSRAM0_CLK_ENB, 0,
795 &_lock);
796 clk_register_clkdev(clk, "sysram0_clk", NULL);
797
798 clk = clk_register_gate(NULL, "sysram1_clk", "ahb_clk", 0,
799 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SYSRAM1_CLK_ENB, 0,
800 &_lock);
801 clk_register_clkdev(clk, "sysram1_clk", NULL);
802
803 clk = clk_register_aux("adc_synth_clk", "adc_synth_gate_clk", "ahb_clk",
804 0, SPEAR1340_ADC_CLK_SYNT, NULL, adc_rtbl,
805 ARRAY_SIZE(adc_rtbl), &_lock, &clk1);
806 clk_register_clkdev(clk, "adc_synth_clk", NULL);
807 clk_register_clkdev(clk1, "adc_synth_gate_clk", NULL);
808
809 clk = clk_register_gate(NULL, "adc_clk", "adc_synth_gate_clk", 0,
810 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_ADC_CLK_ENB, 0,
811 &_lock);
812 clk_register_clkdev(clk, NULL, "adc_clk");
813
814 /* clock derived from apb clk */
815 clk = clk_register_gate(NULL, "ssp_clk", "apb_clk", 0,
816 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SSP_CLK_ENB, 0,
817 &_lock);
818 clk_register_clkdev(clk, NULL, "e0100000.spi");
819
820 clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0,
821 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPIO0_CLK_ENB, 0,
822 &_lock);
823 clk_register_clkdev(clk, NULL, "e0600000.gpio");
824
825 clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0,
826 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPIO1_CLK_ENB, 0,
827 &_lock);
828 clk_register_clkdev(clk, NULL, "e0680000.gpio");
829
830 clk = clk_register_gate(NULL, "i2s_play_clk", "apb_clk", 0,
831 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2S_PLAY_CLK_ENB, 0,
832 &_lock);
833 clk_register_clkdev(clk, NULL, "b2400000.i2s");
834
835 clk = clk_register_gate(NULL, "i2s_rec_clk", "apb_clk", 0,
836 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2S_REC_CLK_ENB, 0,
837 &_lock);
838 clk_register_clkdev(clk, NULL, "b2000000.i2s");
839
840 clk = clk_register_gate(NULL, "kbd_clk", "apb_clk", 0,
841 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_KBD_CLK_ENB, 0,
842 &_lock);
843 clk_register_clkdev(clk, NULL, "e0300000.kbd");
844
845 /* RAS clks */
846 clk = clk_register_mux(NULL, "gen_synth0_1_mux_clk",
847 gen_synth0_1_parents, ARRAY_SIZE(gen_synth0_1_parents),
848 0, SPEAR1340_PLL_CFG, SPEAR1340_GEN_SYNT0_1_CLK_SHIFT,
849 SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock);
850 clk_register_clkdev(clk, "gen_synth0_1_clk", NULL);
851
852 clk = clk_register_mux(NULL, "gen_synth2_3_mux_clk",
853 gen_synth2_3_parents, ARRAY_SIZE(gen_synth2_3_parents),
854 0, SPEAR1340_PLL_CFG, SPEAR1340_GEN_SYNT2_3_CLK_SHIFT,
855 SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock);
856 clk_register_clkdev(clk, "gen_synth2_3_clk", NULL);
857
858 clk = clk_register_frac("gen_synth0_clk", "gen_synth0_1_clk", 0,
859 SPEAR1340_GEN_CLK_SYNT0, gen_rtbl, ARRAY_SIZE(gen_rtbl),
860 &_lock);
861 clk_register_clkdev(clk, "gen_synth0_clk", NULL);
862
863 clk = clk_register_frac("gen_synth1_clk", "gen_synth0_1_clk", 0,
864 SPEAR1340_GEN_CLK_SYNT1, gen_rtbl, ARRAY_SIZE(gen_rtbl),
865 &_lock);
866 clk_register_clkdev(clk, "gen_synth1_clk", NULL);
867
868 clk = clk_register_frac("gen_synth2_clk", "gen_synth2_3_clk", 0,
869 SPEAR1340_GEN_CLK_SYNT2, gen_rtbl, ARRAY_SIZE(gen_rtbl),
870 &_lock);
871 clk_register_clkdev(clk, "gen_synth2_clk", NULL);
872
873 clk = clk_register_frac("gen_synth3_clk", "gen_synth2_3_clk", 0,
874 SPEAR1340_GEN_CLK_SYNT3, gen_rtbl, ARRAY_SIZE(gen_rtbl),
875 &_lock);
876 clk_register_clkdev(clk, "gen_synth3_clk", NULL);
877
878 clk = clk_register_gate(NULL, "mali_clk", "gen_synth3_clk", 0,
879 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_MALI_CLK_ENB, 0,
880 &_lock);
881 clk_register_clkdev(clk, NULL, "mali");
882
883 clk = clk_register_gate(NULL, "cec0_clk", "ahb_clk", 0,
884 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CEC0_CLK_ENB, 0,
885 &_lock);
886 clk_register_clkdev(clk, NULL, "spear_cec.0");
887
888 clk = clk_register_gate(NULL, "cec1_clk", "ahb_clk", 0,
889 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CEC1_CLK_ENB, 0,
890 &_lock);
891 clk_register_clkdev(clk, NULL, "spear_cec.1");
892
893 clk = clk_register_mux(NULL, "spdif_out_mux_clk", spdif_out_parents,
894 ARRAY_SIZE(spdif_out_parents), 0,
895 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_OUT_CLK_SHIFT,
896 SPEAR1340_SPDIF_CLK_MASK, 0, &_lock);
897 clk_register_clkdev(clk, "spdif_out_mux_clk", NULL);
898
899 clk = clk_register_gate(NULL, "spdif_out_clk", "spdif_out_mux_clk", 0,
900 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_SPDIF_OUT_CLK_ENB,
901 0, &_lock);
902 clk_register_clkdev(clk, NULL, "spdif-out");
903
904 clk = clk_register_mux(NULL, "spdif_in_mux_clk", spdif_in_parents,
905 ARRAY_SIZE(spdif_in_parents), 0,
906 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_IN_CLK_SHIFT,
907 SPEAR1340_SPDIF_CLK_MASK, 0, &_lock);
908 clk_register_clkdev(clk, "spdif_in_mux_clk", NULL);
909
910 clk = clk_register_gate(NULL, "spdif_in_clk", "spdif_in_mux_clk", 0,
911 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_SPDIF_IN_CLK_ENB, 0,
912 &_lock);
913 clk_register_clkdev(clk, NULL, "spdif-in");
914
915 clk = clk_register_gate(NULL, "acp_clk", "acp_mux_clk", 0,
916 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_ACP_CLK_ENB, 0,
917 &_lock);
918 clk_register_clkdev(clk, NULL, "acp_clk");
919
920 clk = clk_register_gate(NULL, "plgpio_clk", "plgpio_mux_clk", 0,
921 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PLGPIO_CLK_ENB, 0,
922 &_lock);
923 clk_register_clkdev(clk, NULL, "plgpio");
924
925 clk = clk_register_gate(NULL, "video_dec_clk", "video_dec_mux_clk", 0,
926 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_DEC_CLK_ENB,
927 0, &_lock);
928 clk_register_clkdev(clk, NULL, "video_dec");
929
930 clk = clk_register_gate(NULL, "video_enc_clk", "video_enc_mux_clk", 0,
931 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_ENC_CLK_ENB,
932 0, &_lock);
933 clk_register_clkdev(clk, NULL, "video_enc");
934
935 clk = clk_register_gate(NULL, "video_in_clk", "video_in_mux_clk", 0,
936 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_IN_CLK_ENB, 0,
937 &_lock);
938 clk_register_clkdev(clk, NULL, "spear_vip");
939
940 clk = clk_register_gate(NULL, "cam0_clk", "cam0_mux_clk", 0,
941 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM0_CLK_ENB, 0,
942 &_lock);
943 clk_register_clkdev(clk, NULL, "spear_camif.0");
944
945 clk = clk_register_gate(NULL, "cam1_clk", "cam1_mux_clk", 0,
946 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM1_CLK_ENB, 0,
947 &_lock);
948 clk_register_clkdev(clk, NULL, "spear_camif.1");
949
950 clk = clk_register_gate(NULL, "cam2_clk", "cam2_mux_clk", 0,
951 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM2_CLK_ENB, 0,
952 &_lock);
953 clk_register_clkdev(clk, NULL, "spear_camif.2");
954
955 clk = clk_register_gate(NULL, "cam3_clk", "cam3_mux_clk", 0,
956 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM3_CLK_ENB, 0,
957 &_lock);
958 clk_register_clkdev(clk, NULL, "spear_camif.3");
959
960 clk = clk_register_gate(NULL, "pwm_clk", "pwm_mux_clk", 0,
961 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PWM_CLK_ENB, 0,
962 &_lock);
963 clk_register_clkdev(clk, NULL, "pwm");
964}
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index 421f6af0f995..7bb00448e13d 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -2454,6 +2454,12 @@ static struct samsung_gpio_chip exynos5_gpios_1[] = {
2454 }, 2454 },
2455 }, { 2455 }, {
2456 .chip = { 2456 .chip = {
2457 .base = EXYNOS5_GPC4(0),
2458 .ngpio = EXYNOS5_GPIO_C4_NR,
2459 .label = "GPC4",
2460 },
2461 }, {
2462 .chip = {
2457 .base = EXYNOS5_GPD0(0), 2463 .base = EXYNOS5_GPD0(0),
2458 .ngpio = EXYNOS5_GPIO_D0_NR, 2464 .ngpio = EXYNOS5_GPIO_D0_NR,
2459 .label = "GPD0", 2465 .label = "GPD0",
@@ -2826,8 +2832,11 @@ static __init void exynos5_gpiolib_init(void)
2826 goto err_ioremap1; 2832 goto err_ioremap1;
2827 } 2833 }
2828 2834
2835 /* need to set base address for gpc4 */
2836 exonys5_gpios_1[11].base = gpio_base1 + 0x2E0;
2837
2829 /* need to set base address for gpx */ 2838 /* need to set base address for gpx */
2830 chip = &exynos5_gpios_1[20]; 2839 chip = &exynos5_gpios_1[21];
2831 gpx_base = gpio_base1 + 0xC00; 2840 gpx_base = gpio_base1 + 0xC00;
2832 for (i = 0; i < 4; i++, chip++, gpx_base += 0x20) 2841 for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
2833 chip->base = gpx_base; 2842 chip->base = gpx_base;
diff --git a/drivers/pinctrl/spear/Kconfig b/drivers/pinctrl/spear/Kconfig
index 6a2596b4f359..91558791e766 100644
--- a/drivers/pinctrl/spear/Kconfig
+++ b/drivers/pinctrl/spear/Kconfig
@@ -31,4 +31,14 @@ config PINCTRL_SPEAR320
31 depends on MACH_SPEAR320 31 depends on MACH_SPEAR320
32 select PINCTRL_SPEAR3XX 32 select PINCTRL_SPEAR3XX
33 33
34config PINCTRL_SPEAR1310
35 bool "ST Microelectronics SPEAr1310 SoC pin controller driver"
36 depends on MACH_SPEAR1310
37 select PINCTRL_SPEAR
38
39config PINCTRL_SPEAR1340
40 bool "ST Microelectronics SPEAr1340 SoC pin controller driver"
41 depends on MACH_SPEAR1340
42 select PINCTRL_SPEAR
43
34endif 44endif
diff --git a/drivers/pinctrl/spear/Makefile b/drivers/pinctrl/spear/Makefile
index 15dcb85da22d..b28a7ba22443 100644
--- a/drivers/pinctrl/spear/Makefile
+++ b/drivers/pinctrl/spear/Makefile
@@ -5,3 +5,5 @@ obj-$(CONFIG_PINCTRL_SPEAR3XX) += pinctrl-spear3xx.o
5obj-$(CONFIG_PINCTRL_SPEAR300) += pinctrl-spear300.o 5obj-$(CONFIG_PINCTRL_SPEAR300) += pinctrl-spear300.o
6obj-$(CONFIG_PINCTRL_SPEAR310) += pinctrl-spear310.o 6obj-$(CONFIG_PINCTRL_SPEAR310) += pinctrl-spear310.o
7obj-$(CONFIG_PINCTRL_SPEAR320) += pinctrl-spear320.o 7obj-$(CONFIG_PINCTRL_SPEAR320) += pinctrl-spear320.o
8obj-$(CONFIG_PINCTRL_SPEAR1310) += pinctrl-spear1310.o
9obj-$(CONFIG_PINCTRL_SPEAR1340) += pinctrl-spear1340.o
diff --git a/drivers/pinctrl/spear/pinctrl-spear.h b/drivers/pinctrl/spear/pinctrl-spear.h
index 47a6b5b72f90..9155783bb47f 100644
--- a/drivers/pinctrl/spear/pinctrl-spear.h
+++ b/drivers/pinctrl/spear/pinctrl-spear.h
@@ -139,4 +139,255 @@ void __devinit pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg);
139int __devinit spear_pinctrl_probe(struct platform_device *pdev, 139int __devinit spear_pinctrl_probe(struct platform_device *pdev,
140 struct spear_pinctrl_machdata *machdata); 140 struct spear_pinctrl_machdata *machdata);
141int __devexit spear_pinctrl_remove(struct platform_device *pdev); 141int __devexit spear_pinctrl_remove(struct platform_device *pdev);
142
143#define SPEAR_PIN_0_TO_101 \
144 PINCTRL_PIN(0, "PLGPIO0"), \
145 PINCTRL_PIN(1, "PLGPIO1"), \
146 PINCTRL_PIN(2, "PLGPIO2"), \
147 PINCTRL_PIN(3, "PLGPIO3"), \
148 PINCTRL_PIN(4, "PLGPIO4"), \
149 PINCTRL_PIN(5, "PLGPIO5"), \
150 PINCTRL_PIN(6, "PLGPIO6"), \
151 PINCTRL_PIN(7, "PLGPIO7"), \
152 PINCTRL_PIN(8, "PLGPIO8"), \
153 PINCTRL_PIN(9, "PLGPIO9"), \
154 PINCTRL_PIN(10, "PLGPIO10"), \
155 PINCTRL_PIN(11, "PLGPIO11"), \
156 PINCTRL_PIN(12, "PLGPIO12"), \
157 PINCTRL_PIN(13, "PLGPIO13"), \
158 PINCTRL_PIN(14, "PLGPIO14"), \
159 PINCTRL_PIN(15, "PLGPIO15"), \
160 PINCTRL_PIN(16, "PLGPIO16"), \
161 PINCTRL_PIN(17, "PLGPIO17"), \
162 PINCTRL_PIN(18, "PLGPIO18"), \
163 PINCTRL_PIN(19, "PLGPIO19"), \
164 PINCTRL_PIN(20, "PLGPIO20"), \
165 PINCTRL_PIN(21, "PLGPIO21"), \
166 PINCTRL_PIN(22, "PLGPIO22"), \
167 PINCTRL_PIN(23, "PLGPIO23"), \
168 PINCTRL_PIN(24, "PLGPIO24"), \
169 PINCTRL_PIN(25, "PLGPIO25"), \
170 PINCTRL_PIN(26, "PLGPIO26"), \
171 PINCTRL_PIN(27, "PLGPIO27"), \
172 PINCTRL_PIN(28, "PLGPIO28"), \
173 PINCTRL_PIN(29, "PLGPIO29"), \
174 PINCTRL_PIN(30, "PLGPIO30"), \
175 PINCTRL_PIN(31, "PLGPIO31"), \
176 PINCTRL_PIN(32, "PLGPIO32"), \
177 PINCTRL_PIN(33, "PLGPIO33"), \
178 PINCTRL_PIN(34, "PLGPIO34"), \
179 PINCTRL_PIN(35, "PLGPIO35"), \
180 PINCTRL_PIN(36, "PLGPIO36"), \
181 PINCTRL_PIN(37, "PLGPIO37"), \
182 PINCTRL_PIN(38, "PLGPIO38"), \
183 PINCTRL_PIN(39, "PLGPIO39"), \
184 PINCTRL_PIN(40, "PLGPIO40"), \
185 PINCTRL_PIN(41, "PLGPIO41"), \
186 PINCTRL_PIN(42, "PLGPIO42"), \
187 PINCTRL_PIN(43, "PLGPIO43"), \
188 PINCTRL_PIN(44, "PLGPIO44"), \
189 PINCTRL_PIN(45, "PLGPIO45"), \
190 PINCTRL_PIN(46, "PLGPIO46"), \
191 PINCTRL_PIN(47, "PLGPIO47"), \
192 PINCTRL_PIN(48, "PLGPIO48"), \
193 PINCTRL_PIN(49, "PLGPIO49"), \
194 PINCTRL_PIN(50, "PLGPIO50"), \
195 PINCTRL_PIN(51, "PLGPIO51"), \
196 PINCTRL_PIN(52, "PLGPIO52"), \
197 PINCTRL_PIN(53, "PLGPIO53"), \
198 PINCTRL_PIN(54, "PLGPIO54"), \
199 PINCTRL_PIN(55, "PLGPIO55"), \
200 PINCTRL_PIN(56, "PLGPIO56"), \
201 PINCTRL_PIN(57, "PLGPIO57"), \
202 PINCTRL_PIN(58, "PLGPIO58"), \
203 PINCTRL_PIN(59, "PLGPIO59"), \
204 PINCTRL_PIN(60, "PLGPIO60"), \
205 PINCTRL_PIN(61, "PLGPIO61"), \
206 PINCTRL_PIN(62, "PLGPIO62"), \
207 PINCTRL_PIN(63, "PLGPIO63"), \
208 PINCTRL_PIN(64, "PLGPIO64"), \
209 PINCTRL_PIN(65, "PLGPIO65"), \
210 PINCTRL_PIN(66, "PLGPIO66"), \
211 PINCTRL_PIN(67, "PLGPIO67"), \
212 PINCTRL_PIN(68, "PLGPIO68"), \
213 PINCTRL_PIN(69, "PLGPIO69"), \
214 PINCTRL_PIN(70, "PLGPIO70"), \
215 PINCTRL_PIN(71, "PLGPIO71"), \
216 PINCTRL_PIN(72, "PLGPIO72"), \
217 PINCTRL_PIN(73, "PLGPIO73"), \
218 PINCTRL_PIN(74, "PLGPIO74"), \
219 PINCTRL_PIN(75, "PLGPIO75"), \
220 PINCTRL_PIN(76, "PLGPIO76"), \
221 PINCTRL_PIN(77, "PLGPIO77"), \
222 PINCTRL_PIN(78, "PLGPIO78"), \
223 PINCTRL_PIN(79, "PLGPIO79"), \
224 PINCTRL_PIN(80, "PLGPIO80"), \
225 PINCTRL_PIN(81, "PLGPIO81"), \
226 PINCTRL_PIN(82, "PLGPIO82"), \
227 PINCTRL_PIN(83, "PLGPIO83"), \
228 PINCTRL_PIN(84, "PLGPIO84"), \
229 PINCTRL_PIN(85, "PLGPIO85"), \
230 PINCTRL_PIN(86, "PLGPIO86"), \
231 PINCTRL_PIN(87, "PLGPIO87"), \
232 PINCTRL_PIN(88, "PLGPIO88"), \
233 PINCTRL_PIN(89, "PLGPIO89"), \
234 PINCTRL_PIN(90, "PLGPIO90"), \
235 PINCTRL_PIN(91, "PLGPIO91"), \
236 PINCTRL_PIN(92, "PLGPIO92"), \
237 PINCTRL_PIN(93, "PLGPIO93"), \
238 PINCTRL_PIN(94, "PLGPIO94"), \
239 PINCTRL_PIN(95, "PLGPIO95"), \
240 PINCTRL_PIN(96, "PLGPIO96"), \
241 PINCTRL_PIN(97, "PLGPIO97"), \
242 PINCTRL_PIN(98, "PLGPIO98"), \
243 PINCTRL_PIN(99, "PLGPIO99"), \
244 PINCTRL_PIN(100, "PLGPIO100"), \
245 PINCTRL_PIN(101, "PLGPIO101")
246
247#define SPEAR_PIN_102_TO_245 \
248 PINCTRL_PIN(102, "PLGPIO102"), \
249 PINCTRL_PIN(103, "PLGPIO103"), \
250 PINCTRL_PIN(104, "PLGPIO104"), \
251 PINCTRL_PIN(105, "PLGPIO105"), \
252 PINCTRL_PIN(106, "PLGPIO106"), \
253 PINCTRL_PIN(107, "PLGPIO107"), \
254 PINCTRL_PIN(108, "PLGPIO108"), \
255 PINCTRL_PIN(109, "PLGPIO109"), \
256 PINCTRL_PIN(110, "PLGPIO110"), \
257 PINCTRL_PIN(111, "PLGPIO111"), \
258 PINCTRL_PIN(112, "PLGPIO112"), \
259 PINCTRL_PIN(113, "PLGPIO113"), \
260 PINCTRL_PIN(114, "PLGPIO114"), \
261 PINCTRL_PIN(115, "PLGPIO115"), \
262 PINCTRL_PIN(116, "PLGPIO116"), \
263 PINCTRL_PIN(117, "PLGPIO117"), \
264 PINCTRL_PIN(118, "PLGPIO118"), \
265 PINCTRL_PIN(119, "PLGPIO119"), \
266 PINCTRL_PIN(120, "PLGPIO120"), \
267 PINCTRL_PIN(121, "PLGPIO121"), \
268 PINCTRL_PIN(122, "PLGPIO122"), \
269 PINCTRL_PIN(123, "PLGPIO123"), \
270 PINCTRL_PIN(124, "PLGPIO124"), \
271 PINCTRL_PIN(125, "PLGPIO125"), \
272 PINCTRL_PIN(126, "PLGPIO126"), \
273 PINCTRL_PIN(127, "PLGPIO127"), \
274 PINCTRL_PIN(128, "PLGPIO128"), \
275 PINCTRL_PIN(129, "PLGPIO129"), \
276 PINCTRL_PIN(130, "PLGPIO130"), \
277 PINCTRL_PIN(131, "PLGPIO131"), \
278 PINCTRL_PIN(132, "PLGPIO132"), \
279 PINCTRL_PIN(133, "PLGPIO133"), \
280 PINCTRL_PIN(134, "PLGPIO134"), \
281 PINCTRL_PIN(135, "PLGPIO135"), \
282 PINCTRL_PIN(136, "PLGPIO136"), \
283 PINCTRL_PIN(137, "PLGPIO137"), \
284 PINCTRL_PIN(138, "PLGPIO138"), \
285 PINCTRL_PIN(139, "PLGPIO139"), \
286 PINCTRL_PIN(140, "PLGPIO140"), \
287 PINCTRL_PIN(141, "PLGPIO141"), \
288 PINCTRL_PIN(142, "PLGPIO142"), \
289 PINCTRL_PIN(143, "PLGPIO143"), \
290 PINCTRL_PIN(144, "PLGPIO144"), \
291 PINCTRL_PIN(145, "PLGPIO145"), \
292 PINCTRL_PIN(146, "PLGPIO146"), \
293 PINCTRL_PIN(147, "PLGPIO147"), \
294 PINCTRL_PIN(148, "PLGPIO148"), \
295 PINCTRL_PIN(149, "PLGPIO149"), \
296 PINCTRL_PIN(150, "PLGPIO150"), \
297 PINCTRL_PIN(151, "PLGPIO151"), \
298 PINCTRL_PIN(152, "PLGPIO152"), \
299 PINCTRL_PIN(153, "PLGPIO153"), \
300 PINCTRL_PIN(154, "PLGPIO154"), \
301 PINCTRL_PIN(155, "PLGPIO155"), \
302 PINCTRL_PIN(156, "PLGPIO156"), \
303 PINCTRL_PIN(157, "PLGPIO157"), \
304 PINCTRL_PIN(158, "PLGPIO158"), \
305 PINCTRL_PIN(159, "PLGPIO159"), \
306 PINCTRL_PIN(160, "PLGPIO160"), \
307 PINCTRL_PIN(161, "PLGPIO161"), \
308 PINCTRL_PIN(162, "PLGPIO162"), \
309 PINCTRL_PIN(163, "PLGPIO163"), \
310 PINCTRL_PIN(164, "PLGPIO164"), \
311 PINCTRL_PIN(165, "PLGPIO165"), \
312 PINCTRL_PIN(166, "PLGPIO166"), \
313 PINCTRL_PIN(167, "PLGPIO167"), \
314 PINCTRL_PIN(168, "PLGPIO168"), \
315 PINCTRL_PIN(169, "PLGPIO169"), \
316 PINCTRL_PIN(170, "PLGPIO170"), \
317 PINCTRL_PIN(171, "PLGPIO171"), \
318 PINCTRL_PIN(172, "PLGPIO172"), \
319 PINCTRL_PIN(173, "PLGPIO173"), \
320 PINCTRL_PIN(174, "PLGPIO174"), \
321 PINCTRL_PIN(175, "PLGPIO175"), \
322 PINCTRL_PIN(176, "PLGPIO176"), \
323 PINCTRL_PIN(177, "PLGPIO177"), \
324 PINCTRL_PIN(178, "PLGPIO178"), \
325 PINCTRL_PIN(179, "PLGPIO179"), \
326 PINCTRL_PIN(180, "PLGPIO180"), \
327 PINCTRL_PIN(181, "PLGPIO181"), \
328 PINCTRL_PIN(182, "PLGPIO182"), \
329 PINCTRL_PIN(183, "PLGPIO183"), \
330 PINCTRL_PIN(184, "PLGPIO184"), \
331 PINCTRL_PIN(185, "PLGPIO185"), \
332 PINCTRL_PIN(186, "PLGPIO186"), \
333 PINCTRL_PIN(187, "PLGPIO187"), \
334 PINCTRL_PIN(188, "PLGPIO188"), \
335 PINCTRL_PIN(189, "PLGPIO189"), \
336 PINCTRL_PIN(190, "PLGPIO190"), \
337 PINCTRL_PIN(191, "PLGPIO191"), \
338 PINCTRL_PIN(192, "PLGPIO192"), \
339 PINCTRL_PIN(193, "PLGPIO193"), \
340 PINCTRL_PIN(194, "PLGPIO194"), \
341 PINCTRL_PIN(195, "PLGPIO195"), \
342 PINCTRL_PIN(196, "PLGPIO196"), \
343 PINCTRL_PIN(197, "PLGPIO197"), \
344 PINCTRL_PIN(198, "PLGPIO198"), \
345 PINCTRL_PIN(199, "PLGPIO199"), \
346 PINCTRL_PIN(200, "PLGPIO200"), \
347 PINCTRL_PIN(201, "PLGPIO201"), \
348 PINCTRL_PIN(202, "PLGPIO202"), \
349 PINCTRL_PIN(203, "PLGPIO203"), \
350 PINCTRL_PIN(204, "PLGPIO204"), \
351 PINCTRL_PIN(205, "PLGPIO205"), \
352 PINCTRL_PIN(206, "PLGPIO206"), \
353 PINCTRL_PIN(207, "PLGPIO207"), \
354 PINCTRL_PIN(208, "PLGPIO208"), \
355 PINCTRL_PIN(209, "PLGPIO209"), \
356 PINCTRL_PIN(210, "PLGPIO210"), \
357 PINCTRL_PIN(211, "PLGPIO211"), \
358 PINCTRL_PIN(212, "PLGPIO212"), \
359 PINCTRL_PIN(213, "PLGPIO213"), \
360 PINCTRL_PIN(214, "PLGPIO214"), \
361 PINCTRL_PIN(215, "PLGPIO215"), \
362 PINCTRL_PIN(216, "PLGPIO216"), \
363 PINCTRL_PIN(217, "PLGPIO217"), \
364 PINCTRL_PIN(218, "PLGPIO218"), \
365 PINCTRL_PIN(219, "PLGPIO219"), \
366 PINCTRL_PIN(220, "PLGPIO220"), \
367 PINCTRL_PIN(221, "PLGPIO221"), \
368 PINCTRL_PIN(222, "PLGPIO222"), \
369 PINCTRL_PIN(223, "PLGPIO223"), \
370 PINCTRL_PIN(224, "PLGPIO224"), \
371 PINCTRL_PIN(225, "PLGPIO225"), \
372 PINCTRL_PIN(226, "PLGPIO226"), \
373 PINCTRL_PIN(227, "PLGPIO227"), \
374 PINCTRL_PIN(228, "PLGPIO228"), \
375 PINCTRL_PIN(229, "PLGPIO229"), \
376 PINCTRL_PIN(230, "PLGPIO230"), \
377 PINCTRL_PIN(231, "PLGPIO231"), \
378 PINCTRL_PIN(232, "PLGPIO232"), \
379 PINCTRL_PIN(233, "PLGPIO233"), \
380 PINCTRL_PIN(234, "PLGPIO234"), \
381 PINCTRL_PIN(235, "PLGPIO235"), \
382 PINCTRL_PIN(236, "PLGPIO236"), \
383 PINCTRL_PIN(237, "PLGPIO237"), \
384 PINCTRL_PIN(238, "PLGPIO238"), \
385 PINCTRL_PIN(239, "PLGPIO239"), \
386 PINCTRL_PIN(240, "PLGPIO240"), \
387 PINCTRL_PIN(241, "PLGPIO241"), \
388 PINCTRL_PIN(242, "PLGPIO242"), \
389 PINCTRL_PIN(243, "PLGPIO243"), \
390 PINCTRL_PIN(244, "PLGPIO244"), \
391 PINCTRL_PIN(245, "PLGPIO245")
392
142#endif /* __PINMUX_SPEAR_H__ */ 393#endif /* __PINMUX_SPEAR_H__ */
diff --git a/drivers/pinctrl/spear/pinctrl-spear1310.c b/drivers/pinctrl/spear/pinctrl-spear1310.c
new file mode 100644
index 000000000000..fff168be7f00
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear1310.c
@@ -0,0 +1,2198 @@
1/*
2 * Driver for the ST Microelectronics SPEAr1310 pinmux
3 *
4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.kumar@st.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/err.h>
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/of_device.h>
16#include <linux/platform_device.h>
17#include "pinctrl-spear.h"
18
19#define DRIVER_NAME "spear1310-pinmux"
20
21/* pins */
22static const struct pinctrl_pin_desc spear1310_pins[] = {
23 SPEAR_PIN_0_TO_101,
24 SPEAR_PIN_102_TO_245,
25};
26
27/* registers */
28#define PERIP_CFG 0x32C
29 #define MCIF_SEL_SHIFT 3
30 #define MCIF_SEL_SD (0x1 << MCIF_SEL_SHIFT)
31 #define MCIF_SEL_CF (0x2 << MCIF_SEL_SHIFT)
32 #define MCIF_SEL_XD (0x3 << MCIF_SEL_SHIFT)
33 #define MCIF_SEL_MASK (0x3 << MCIF_SEL_SHIFT)
34
35#define PCIE_SATA_CFG 0x3A4
36 #define PCIE_SATA2_SEL_PCIE (0 << 31)
37 #define PCIE_SATA1_SEL_PCIE (0 << 30)
38 #define PCIE_SATA0_SEL_PCIE (0 << 29)
39 #define PCIE_SATA2_SEL_SATA (1 << 31)
40 #define PCIE_SATA1_SEL_SATA (1 << 30)
41 #define PCIE_SATA0_SEL_SATA (1 << 29)
42 #define SATA2_CFG_TX_CLK_EN (1 << 27)
43 #define SATA2_CFG_RX_CLK_EN (1 << 26)
44 #define SATA2_CFG_POWERUP_RESET (1 << 25)
45 #define SATA2_CFG_PM_CLK_EN (1 << 24)
46 #define SATA1_CFG_TX_CLK_EN (1 << 23)
47 #define SATA1_CFG_RX_CLK_EN (1 << 22)
48 #define SATA1_CFG_POWERUP_RESET (1 << 21)
49 #define SATA1_CFG_PM_CLK_EN (1 << 20)
50 #define SATA0_CFG_TX_CLK_EN (1 << 19)
51 #define SATA0_CFG_RX_CLK_EN (1 << 18)
52 #define SATA0_CFG_POWERUP_RESET (1 << 17)
53 #define SATA0_CFG_PM_CLK_EN (1 << 16)
54 #define PCIE2_CFG_DEVICE_PRESENT (1 << 11)
55 #define PCIE2_CFG_POWERUP_RESET (1 << 10)
56 #define PCIE2_CFG_CORE_CLK_EN (1 << 9)
57 #define PCIE2_CFG_AUX_CLK_EN (1 << 8)
58 #define PCIE1_CFG_DEVICE_PRESENT (1 << 7)
59 #define PCIE1_CFG_POWERUP_RESET (1 << 6)
60 #define PCIE1_CFG_CORE_CLK_EN (1 << 5)
61 #define PCIE1_CFG_AUX_CLK_EN (1 << 4)
62 #define PCIE0_CFG_DEVICE_PRESENT (1 << 3)
63 #define PCIE0_CFG_POWERUP_RESET (1 << 2)
64 #define PCIE0_CFG_CORE_CLK_EN (1 << 1)
65 #define PCIE0_CFG_AUX_CLK_EN (1 << 0)
66
67#define PAD_FUNCTION_EN_0 0x650
68 #define PMX_UART0_MASK (1 << 1)
69 #define PMX_I2C0_MASK (1 << 2)
70 #define PMX_I2S0_MASK (1 << 3)
71 #define PMX_SSP0_MASK (1 << 4)
72 #define PMX_CLCD1_MASK (1 << 5)
73 #define PMX_EGPIO00_MASK (1 << 6)
74 #define PMX_EGPIO01_MASK (1 << 7)
75 #define PMX_EGPIO02_MASK (1 << 8)
76 #define PMX_EGPIO03_MASK (1 << 9)
77 #define PMX_EGPIO04_MASK (1 << 10)
78 #define PMX_EGPIO05_MASK (1 << 11)
79 #define PMX_EGPIO06_MASK (1 << 12)
80 #define PMX_EGPIO07_MASK (1 << 13)
81 #define PMX_EGPIO08_MASK (1 << 14)
82 #define PMX_EGPIO09_MASK (1 << 15)
83 #define PMX_SMI_MASK (1 << 16)
84 #define PMX_NAND8_MASK (1 << 17)
85 #define PMX_GMIICLK_MASK (1 << 18)
86 #define PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK (1 << 19)
87 #define PMX_RXCLK_RDV_TXEN_D03_MASK (1 << 20)
88 #define PMX_GMIID47_MASK (1 << 21)
89 #define PMX_MDC_MDIO_MASK (1 << 22)
90 #define PMX_MCI_DATA8_15_MASK (1 << 23)
91 #define PMX_NFAD23_MASK (1 << 24)
92 #define PMX_NFAD24_MASK (1 << 25)
93 #define PMX_NFAD25_MASK (1 << 26)
94 #define PMX_NFCE3_MASK (1 << 27)
95 #define PMX_NFWPRT3_MASK (1 << 28)
96 #define PMX_NFRSTPWDWN0_MASK (1 << 29)
97 #define PMX_NFRSTPWDWN1_MASK (1 << 30)
98 #define PMX_NFRSTPWDWN2_MASK (1 << 31)
99
100#define PAD_FUNCTION_EN_1 0x654
101 #define PMX_NFRSTPWDWN3_MASK (1 << 0)
102 #define PMX_SMINCS2_MASK (1 << 1)
103 #define PMX_SMINCS3_MASK (1 << 2)
104 #define PMX_CLCD2_MASK (1 << 3)
105 #define PMX_KBD_ROWCOL68_MASK (1 << 4)
106 #define PMX_EGPIO10_MASK (1 << 5)
107 #define PMX_EGPIO11_MASK (1 << 6)
108 #define PMX_EGPIO12_MASK (1 << 7)
109 #define PMX_EGPIO13_MASK (1 << 8)
110 #define PMX_EGPIO14_MASK (1 << 9)
111 #define PMX_EGPIO15_MASK (1 << 10)
112 #define PMX_UART0_MODEM_MASK (1 << 11)
113 #define PMX_GPT0_TMR0_MASK (1 << 12)
114 #define PMX_GPT0_TMR1_MASK (1 << 13)
115 #define PMX_GPT1_TMR0_MASK (1 << 14)
116 #define PMX_GPT1_TMR1_MASK (1 << 15)
117 #define PMX_I2S1_MASK (1 << 16)
118 #define PMX_KBD_ROWCOL25_MASK (1 << 17)
119 #define PMX_NFIO8_15_MASK (1 << 18)
120 #define PMX_KBD_COL1_MASK (1 << 19)
121 #define PMX_NFCE1_MASK (1 << 20)
122 #define PMX_KBD_COL0_MASK (1 << 21)
123 #define PMX_NFCE2_MASK (1 << 22)
124 #define PMX_KBD_ROW1_MASK (1 << 23)
125 #define PMX_NFWPRT1_MASK (1 << 24)
126 #define PMX_KBD_ROW0_MASK (1 << 25)
127 #define PMX_NFWPRT2_MASK (1 << 26)
128 #define PMX_MCIDATA0_MASK (1 << 27)
129 #define PMX_MCIDATA1_MASK (1 << 28)
130 #define PMX_MCIDATA2_MASK (1 << 29)
131 #define PMX_MCIDATA3_MASK (1 << 30)
132 #define PMX_MCIDATA4_MASK (1 << 31)
133
134#define PAD_FUNCTION_EN_2 0x658
135 #define PMX_MCIDATA5_MASK (1 << 0)
136 #define PMX_MCIDATA6_MASK (1 << 1)
137 #define PMX_MCIDATA7_MASK (1 << 2)
138 #define PMX_MCIDATA1SD_MASK (1 << 3)
139 #define PMX_MCIDATA2SD_MASK (1 << 4)
140 #define PMX_MCIDATA3SD_MASK (1 << 5)
141 #define PMX_MCIADDR0ALE_MASK (1 << 6)
142 #define PMX_MCIADDR1CLECLK_MASK (1 << 7)
143 #define PMX_MCIADDR2_MASK (1 << 8)
144 #define PMX_MCICECF_MASK (1 << 9)
145 #define PMX_MCICEXD_MASK (1 << 10)
146 #define PMX_MCICESDMMC_MASK (1 << 11)
147 #define PMX_MCICDCF1_MASK (1 << 12)
148 #define PMX_MCICDCF2_MASK (1 << 13)
149 #define PMX_MCICDXD_MASK (1 << 14)
150 #define PMX_MCICDSDMMC_MASK (1 << 15)
151 #define PMX_MCIDATADIR_MASK (1 << 16)
152 #define PMX_MCIDMARQWP_MASK (1 << 17)
153 #define PMX_MCIIORDRE_MASK (1 << 18)
154 #define PMX_MCIIOWRWE_MASK (1 << 19)
155 #define PMX_MCIRESETCF_MASK (1 << 20)
156 #define PMX_MCICS0CE_MASK (1 << 21)
157 #define PMX_MCICFINTR_MASK (1 << 22)
158 #define PMX_MCIIORDY_MASK (1 << 23)
159 #define PMX_MCICS1_MASK (1 << 24)
160 #define PMX_MCIDMAACK_MASK (1 << 25)
161 #define PMX_MCISDCMD_MASK (1 << 26)
162 #define PMX_MCILEDS_MASK (1 << 27)
163 #define PMX_TOUCH_XY_MASK (1 << 28)
164 #define PMX_SSP0_CS0_MASK (1 << 29)
165 #define PMX_SSP0_CS1_2_MASK (1 << 30)
166
167/* combined macros */
168#define PMX_GMII_MASK (PMX_GMIICLK_MASK | \
169 PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK | \
170 PMX_RXCLK_RDV_TXEN_D03_MASK | \
171 PMX_GMIID47_MASK | PMX_MDC_MDIO_MASK)
172
173#define PMX_EGPIO_0_GRP_MASK (PMX_EGPIO00_MASK | PMX_EGPIO01_MASK | \
174 PMX_EGPIO02_MASK | \
175 PMX_EGPIO03_MASK | PMX_EGPIO04_MASK | \
176 PMX_EGPIO05_MASK | PMX_EGPIO06_MASK | \
177 PMX_EGPIO07_MASK | PMX_EGPIO08_MASK | \
178 PMX_EGPIO09_MASK)
179#define PMX_EGPIO_1_GRP_MASK (PMX_EGPIO10_MASK | PMX_EGPIO11_MASK | \
180 PMX_EGPIO12_MASK | PMX_EGPIO13_MASK | \
181 PMX_EGPIO14_MASK | PMX_EGPIO15_MASK)
182
183#define PMX_KEYBOARD_6X6_MASK (PMX_KBD_ROW0_MASK | PMX_KBD_ROW1_MASK | \
184 PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL0_MASK | \
185 PMX_KBD_COL1_MASK)
186
187#define PMX_NAND8BIT_0_MASK (PMX_NAND8_MASK | PMX_NFAD23_MASK | \
188 PMX_NFAD24_MASK | PMX_NFAD25_MASK | \
189 PMX_NFWPRT3_MASK | PMX_NFRSTPWDWN0_MASK | \
190 PMX_NFRSTPWDWN1_MASK | PMX_NFRSTPWDWN2_MASK | \
191 PMX_NFCE3_MASK)
192#define PMX_NAND8BIT_1_MASK PMX_NFRSTPWDWN3_MASK
193
194#define PMX_NAND16BIT_1_MASK (PMX_KBD_ROWCOL25_MASK | PMX_NFIO8_15_MASK)
195#define PMX_NAND_4CHIPS_MASK (PMX_NFCE1_MASK | PMX_NFCE2_MASK | \
196 PMX_NFWPRT1_MASK | PMX_NFWPRT2_MASK | \
197 PMX_KBD_ROW0_MASK | PMX_KBD_ROW1_MASK | \
198 PMX_KBD_COL0_MASK | PMX_KBD_COL1_MASK)
199
200#define PMX_MCIFALL_1_MASK 0xF8000000
201#define PMX_MCIFALL_2_MASK 0x0FFFFFFF
202
203#define PMX_PCI_REG1_MASK (PMX_SMINCS2_MASK | PMX_SMINCS3_MASK | \
204 PMX_CLCD2_MASK | PMX_KBD_ROWCOL68_MASK | \
205 PMX_EGPIO_1_GRP_MASK | PMX_GPT0_TMR0_MASK | \
206 PMX_GPT0_TMR1_MASK | PMX_GPT1_TMR0_MASK | \
207 PMX_GPT1_TMR1_MASK | PMX_I2S1_MASK | \
208 PMX_NFCE2_MASK)
209#define PMX_PCI_REG2_MASK (PMX_TOUCH_XY_MASK | PMX_SSP0_CS0_MASK | \
210 PMX_SSP0_CS1_2_MASK)
211
212#define PMX_SMII_0_1_2_MASK (PMX_CLCD2_MASK | PMX_KBD_ROWCOL68_MASK)
213#define PMX_RGMII_REG0_MASK (PMX_MCI_DATA8_15_MASK | \
214 PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK | \
215 PMX_GMIID47_MASK)
216#define PMX_RGMII_REG1_MASK (PMX_KBD_ROWCOL68_MASK | PMX_EGPIO_1_GRP_MASK |\
217 PMX_KBD_ROW1_MASK | PMX_NFWPRT1_MASK | \
218 PMX_KBD_ROW0_MASK | PMX_NFWPRT2_MASK)
219#define PMX_RGMII_REG2_MASK (PMX_TOUCH_XY_MASK | PMX_SSP0_CS0_MASK | \
220 PMX_SSP0_CS1_2_MASK)
221
222#define PCIE_CFG_VAL(x) (PCIE_SATA##x##_SEL_PCIE | \
223 PCIE##x##_CFG_AUX_CLK_EN | \
224 PCIE##x##_CFG_CORE_CLK_EN | \
225 PCIE##x##_CFG_POWERUP_RESET | \
226 PCIE##x##_CFG_DEVICE_PRESENT)
227#define SATA_CFG_VAL(x) (PCIE_SATA##x##_SEL_SATA | \
228 SATA##x##_CFG_PM_CLK_EN | \
229 SATA##x##_CFG_POWERUP_RESET | \
230 SATA##x##_CFG_RX_CLK_EN | \
231 SATA##x##_CFG_TX_CLK_EN)
232
233/* Pad multiplexing for i2c0 device */
234static const unsigned i2c0_pins[] = { 102, 103 };
235static struct spear_muxreg i2c0_muxreg[] = {
236 {
237 .reg = PAD_FUNCTION_EN_0,
238 .mask = PMX_I2C0_MASK,
239 .val = PMX_I2C0_MASK,
240 },
241};
242
243static struct spear_modemux i2c0_modemux[] = {
244 {
245 .muxregs = i2c0_muxreg,
246 .nmuxregs = ARRAY_SIZE(i2c0_muxreg),
247 },
248};
249
250static struct spear_pingroup i2c0_pingroup = {
251 .name = "i2c0_grp",
252 .pins = i2c0_pins,
253 .npins = ARRAY_SIZE(i2c0_pins),
254 .modemuxs = i2c0_modemux,
255 .nmodemuxs = ARRAY_SIZE(i2c0_modemux),
256};
257
258static const char *const i2c0_grps[] = { "i2c0_grp" };
259static struct spear_function i2c0_function = {
260 .name = "i2c0",
261 .groups = i2c0_grps,
262 .ngroups = ARRAY_SIZE(i2c0_grps),
263};
264
265/* Pad multiplexing for ssp0 device */
266static const unsigned ssp0_pins[] = { 109, 110, 111, 112 };
267static struct spear_muxreg ssp0_muxreg[] = {
268 {
269 .reg = PAD_FUNCTION_EN_0,
270 .mask = PMX_SSP0_MASK,
271 .val = PMX_SSP0_MASK,
272 },
273};
274
275static struct spear_modemux ssp0_modemux[] = {
276 {
277 .muxregs = ssp0_muxreg,
278 .nmuxregs = ARRAY_SIZE(ssp0_muxreg),
279 },
280};
281
282static struct spear_pingroup ssp0_pingroup = {
283 .name = "ssp0_grp",
284 .pins = ssp0_pins,
285 .npins = ARRAY_SIZE(ssp0_pins),
286 .modemuxs = ssp0_modemux,
287 .nmodemuxs = ARRAY_SIZE(ssp0_modemux),
288};
289
290/* Pad multiplexing for ssp0_cs0 device */
291static const unsigned ssp0_cs0_pins[] = { 96 };
292static struct spear_muxreg ssp0_cs0_muxreg[] = {
293 {
294 .reg = PAD_FUNCTION_EN_2,
295 .mask = PMX_SSP0_CS0_MASK,
296 .val = PMX_SSP0_CS0_MASK,
297 },
298};
299
300static struct spear_modemux ssp0_cs0_modemux[] = {
301 {
302 .muxregs = ssp0_cs0_muxreg,
303 .nmuxregs = ARRAY_SIZE(ssp0_cs0_muxreg),
304 },
305};
306
307static struct spear_pingroup ssp0_cs0_pingroup = {
308 .name = "ssp0_cs0_grp",
309 .pins = ssp0_cs0_pins,
310 .npins = ARRAY_SIZE(ssp0_cs0_pins),
311 .modemuxs = ssp0_cs0_modemux,
312 .nmodemuxs = ARRAY_SIZE(ssp0_cs0_modemux),
313};
314
315/* ssp0_cs1_2 device */
316static const unsigned ssp0_cs1_2_pins[] = { 94, 95 };
317static struct spear_muxreg ssp0_cs1_2_muxreg[] = {
318 {
319 .reg = PAD_FUNCTION_EN_2,
320 .mask = PMX_SSP0_CS1_2_MASK,
321 .val = PMX_SSP0_CS1_2_MASK,
322 },
323};
324
325static struct spear_modemux ssp0_cs1_2_modemux[] = {
326 {
327 .muxregs = ssp0_cs1_2_muxreg,
328 .nmuxregs = ARRAY_SIZE(ssp0_cs1_2_muxreg),
329 },
330};
331
332static struct spear_pingroup ssp0_cs1_2_pingroup = {
333 .name = "ssp0_cs1_2_grp",
334 .pins = ssp0_cs1_2_pins,
335 .npins = ARRAY_SIZE(ssp0_cs1_2_pins),
336 .modemuxs = ssp0_cs1_2_modemux,
337 .nmodemuxs = ARRAY_SIZE(ssp0_cs1_2_modemux),
338};
339
340static const char *const ssp0_grps[] = { "ssp0_grp", "ssp0_cs0_grp",
341 "ssp0_cs1_2_grp" };
342static struct spear_function ssp0_function = {
343 .name = "ssp0",
344 .groups = ssp0_grps,
345 .ngroups = ARRAY_SIZE(ssp0_grps),
346};
347
348/* Pad multiplexing for i2s0 device */
349static const unsigned i2s0_pins[] = { 104, 105, 106, 107, 108 };
350static struct spear_muxreg i2s0_muxreg[] = {
351 {
352 .reg = PAD_FUNCTION_EN_0,
353 .mask = PMX_I2S0_MASK,
354 .val = PMX_I2S0_MASK,
355 },
356};
357
358static struct spear_modemux i2s0_modemux[] = {
359 {
360 .muxregs = i2s0_muxreg,
361 .nmuxregs = ARRAY_SIZE(i2s0_muxreg),
362 },
363};
364
365static struct spear_pingroup i2s0_pingroup = {
366 .name = "i2s0_grp",
367 .pins = i2s0_pins,
368 .npins = ARRAY_SIZE(i2s0_pins),
369 .modemuxs = i2s0_modemux,
370 .nmodemuxs = ARRAY_SIZE(i2s0_modemux),
371};
372
373static const char *const i2s0_grps[] = { "i2s0_grp" };
374static struct spear_function i2s0_function = {
375 .name = "i2s0",
376 .groups = i2s0_grps,
377 .ngroups = ARRAY_SIZE(i2s0_grps),
378};
379
380/* Pad multiplexing for i2s1 device */
381static const unsigned i2s1_pins[] = { 0, 1, 2, 3 };
382static struct spear_muxreg i2s1_muxreg[] = {
383 {
384 .reg = PAD_FUNCTION_EN_1,
385 .mask = PMX_I2S1_MASK,
386 .val = PMX_I2S1_MASK,
387 },
388};
389
390static struct spear_modemux i2s1_modemux[] = {
391 {
392 .muxregs = i2s1_muxreg,
393 .nmuxregs = ARRAY_SIZE(i2s1_muxreg),
394 },
395};
396
397static struct spear_pingroup i2s1_pingroup = {
398 .name = "i2s1_grp",
399 .pins = i2s1_pins,
400 .npins = ARRAY_SIZE(i2s1_pins),
401 .modemuxs = i2s1_modemux,
402 .nmodemuxs = ARRAY_SIZE(i2s1_modemux),
403};
404
405static const char *const i2s1_grps[] = { "i2s1_grp" };
406static struct spear_function i2s1_function = {
407 .name = "i2s1",
408 .groups = i2s1_grps,
409 .ngroups = ARRAY_SIZE(i2s1_grps),
410};
411
412/* Pad multiplexing for clcd device */
413static const unsigned clcd_pins[] = { 113, 114, 115, 116, 117, 118, 119, 120,
414 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134,
415 135, 136, 137, 138, 139, 140, 141, 142 };
416static struct spear_muxreg clcd_muxreg[] = {
417 {
418 .reg = PAD_FUNCTION_EN_0,
419 .mask = PMX_CLCD1_MASK,
420 .val = PMX_CLCD1_MASK,
421 },
422};
423
424static struct spear_modemux clcd_modemux[] = {
425 {
426 .muxregs = clcd_muxreg,
427 .nmuxregs = ARRAY_SIZE(clcd_muxreg),
428 },
429};
430
431static struct spear_pingroup clcd_pingroup = {
432 .name = "clcd_grp",
433 .pins = clcd_pins,
434 .npins = ARRAY_SIZE(clcd_pins),
435 .modemuxs = clcd_modemux,
436 .nmodemuxs = ARRAY_SIZE(clcd_modemux),
437};
438
439static const unsigned clcd_high_res_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37,
440 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53 };
441static struct spear_muxreg clcd_high_res_muxreg[] = {
442 {
443 .reg = PAD_FUNCTION_EN_1,
444 .mask = PMX_CLCD2_MASK,
445 .val = PMX_CLCD2_MASK,
446 },
447};
448
449static struct spear_modemux clcd_high_res_modemux[] = {
450 {
451 .muxregs = clcd_high_res_muxreg,
452 .nmuxregs = ARRAY_SIZE(clcd_high_res_muxreg),
453 },
454};
455
456static struct spear_pingroup clcd_high_res_pingroup = {
457 .name = "clcd_high_res_grp",
458 .pins = clcd_high_res_pins,
459 .npins = ARRAY_SIZE(clcd_high_res_pins),
460 .modemuxs = clcd_high_res_modemux,
461 .nmodemuxs = ARRAY_SIZE(clcd_high_res_modemux),
462};
463
464static const char *const clcd_grps[] = { "clcd_grp", "clcd_high_res" };
465static struct spear_function clcd_function = {
466 .name = "clcd",
467 .groups = clcd_grps,
468 .ngroups = ARRAY_SIZE(clcd_grps),
469};
470
471static const unsigned arm_gpio_pins[] = { 18, 19, 20, 21, 22, 23, 143, 144, 145,
472 146, 147, 148, 149, 150, 151, 152 };
473static struct spear_muxreg arm_gpio_muxreg[] = {
474 {
475 .reg = PAD_FUNCTION_EN_0,
476 .mask = PMX_EGPIO_0_GRP_MASK,
477 .val = PMX_EGPIO_0_GRP_MASK,
478 }, {
479 .reg = PAD_FUNCTION_EN_1,
480 .mask = PMX_EGPIO_1_GRP_MASK,
481 .val = PMX_EGPIO_1_GRP_MASK,
482 },
483};
484
485static struct spear_modemux arm_gpio_modemux[] = {
486 {
487 .muxregs = arm_gpio_muxreg,
488 .nmuxregs = ARRAY_SIZE(arm_gpio_muxreg),
489 },
490};
491
492static struct spear_pingroup arm_gpio_pingroup = {
493 .name = "arm_gpio_grp",
494 .pins = arm_gpio_pins,
495 .npins = ARRAY_SIZE(arm_gpio_pins),
496 .modemuxs = arm_gpio_modemux,
497 .nmodemuxs = ARRAY_SIZE(arm_gpio_modemux),
498};
499
500static const char *const arm_gpio_grps[] = { "arm_gpio_grp" };
501static struct spear_function arm_gpio_function = {
502 .name = "arm_gpio",
503 .groups = arm_gpio_grps,
504 .ngroups = ARRAY_SIZE(arm_gpio_grps),
505};
506
507/* Pad multiplexing for smi 2 chips device */
508static const unsigned smi_2_chips_pins[] = { 153, 154, 155, 156, 157 };
509static struct spear_muxreg smi_2_chips_muxreg[] = {
510 {
511 .reg = PAD_FUNCTION_EN_0,
512 .mask = PMX_SMI_MASK,
513 .val = PMX_SMI_MASK,
514 },
515};
516
517static struct spear_modemux smi_2_chips_modemux[] = {
518 {
519 .muxregs = smi_2_chips_muxreg,
520 .nmuxregs = ARRAY_SIZE(smi_2_chips_muxreg),
521 },
522};
523
524static struct spear_pingroup smi_2_chips_pingroup = {
525 .name = "smi_2_chips_grp",
526 .pins = smi_2_chips_pins,
527 .npins = ARRAY_SIZE(smi_2_chips_pins),
528 .modemuxs = smi_2_chips_modemux,
529 .nmodemuxs = ARRAY_SIZE(smi_2_chips_modemux),
530};
531
532static const unsigned smi_4_chips_pins[] = { 54, 55 };
533static struct spear_muxreg smi_4_chips_muxreg[] = {
534 {
535 .reg = PAD_FUNCTION_EN_0,
536 .mask = PMX_SMI_MASK,
537 .val = PMX_SMI_MASK,
538 }, {
539 .reg = PAD_FUNCTION_EN_1,
540 .mask = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
541 .val = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
542 },
543};
544
545static struct spear_modemux smi_4_chips_modemux[] = {
546 {
547 .muxregs = smi_4_chips_muxreg,
548 .nmuxregs = ARRAY_SIZE(smi_4_chips_muxreg),
549 },
550};
551
552static struct spear_pingroup smi_4_chips_pingroup = {
553 .name = "smi_4_chips_grp",
554 .pins = smi_4_chips_pins,
555 .npins = ARRAY_SIZE(smi_4_chips_pins),
556 .modemuxs = smi_4_chips_modemux,
557 .nmodemuxs = ARRAY_SIZE(smi_4_chips_modemux),
558};
559
560static const char *const smi_grps[] = { "smi_2_chips_grp", "smi_4_chips_grp" };
561static struct spear_function smi_function = {
562 .name = "smi",
563 .groups = smi_grps,
564 .ngroups = ARRAY_SIZE(smi_grps),
565};
566
567/* Pad multiplexing for gmii device */
568static const unsigned gmii_pins[] = { 173, 174, 175, 176, 177, 178, 179, 180,
569 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194,
570 195, 196, 197, 198, 199, 200 };
571static struct spear_muxreg gmii_muxreg[] = {
572 {
573 .reg = PAD_FUNCTION_EN_0,
574 .mask = PMX_GMII_MASK,
575 .val = PMX_GMII_MASK,
576 },
577};
578
579static struct spear_modemux gmii_modemux[] = {
580 {
581 .muxregs = gmii_muxreg,
582 .nmuxregs = ARRAY_SIZE(gmii_muxreg),
583 },
584};
585
586static struct spear_pingroup gmii_pingroup = {
587 .name = "gmii_grp",
588 .pins = gmii_pins,
589 .npins = ARRAY_SIZE(gmii_pins),
590 .modemuxs = gmii_modemux,
591 .nmodemuxs = ARRAY_SIZE(gmii_modemux),
592};
593
594static const char *const gmii_grps[] = { "gmii_grp" };
595static struct spear_function gmii_function = {
596 .name = "gmii",
597 .groups = gmii_grps,
598 .ngroups = ARRAY_SIZE(gmii_grps),
599};
600
601/* Pad multiplexing for rgmii device */
602static const unsigned rgmii_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,
603 28, 29, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 175,
604 180, 181, 182, 183, 185, 188, 193, 194, 195, 196, 197, 198, 211, 212 };
605static struct spear_muxreg rgmii_muxreg[] = {
606 {
607 .reg = PAD_FUNCTION_EN_0,
608 .mask = PMX_RGMII_REG0_MASK,
609 .val = 0,
610 }, {
611 .reg = PAD_FUNCTION_EN_1,
612 .mask = PMX_RGMII_REG1_MASK,
613 .val = 0,
614 }, {
615 .reg = PAD_FUNCTION_EN_2,
616 .mask = PMX_RGMII_REG2_MASK,
617 .val = 0,
618 },
619};
620
621static struct spear_modemux rgmii_modemux[] = {
622 {
623 .muxregs = rgmii_muxreg,
624 .nmuxregs = ARRAY_SIZE(rgmii_muxreg),
625 },
626};
627
628static struct spear_pingroup rgmii_pingroup = {
629 .name = "rgmii_grp",
630 .pins = rgmii_pins,
631 .npins = ARRAY_SIZE(rgmii_pins),
632 .modemuxs = rgmii_modemux,
633 .nmodemuxs = ARRAY_SIZE(rgmii_modemux),
634};
635
636static const char *const rgmii_grps[] = { "rgmii_grp" };
637static struct spear_function rgmii_function = {
638 .name = "rgmii",
639 .groups = rgmii_grps,
640 .ngroups = ARRAY_SIZE(rgmii_grps),
641};
642
643/* Pad multiplexing for smii_0_1_2 device */
644static const unsigned smii_0_1_2_pins[] = { 24, 25, 26, 27, 28, 29, 30, 31, 32,
645 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50,
646 51, 52, 53, 54, 55 };
647static struct spear_muxreg smii_0_1_2_muxreg[] = {
648 {
649 .reg = PAD_FUNCTION_EN_1,
650 .mask = PMX_SMII_0_1_2_MASK,
651 .val = 0,
652 },
653};
654
655static struct spear_modemux smii_0_1_2_modemux[] = {
656 {
657 .muxregs = smii_0_1_2_muxreg,
658 .nmuxregs = ARRAY_SIZE(smii_0_1_2_muxreg),
659 },
660};
661
662static struct spear_pingroup smii_0_1_2_pingroup = {
663 .name = "smii_0_1_2_grp",
664 .pins = smii_0_1_2_pins,
665 .npins = ARRAY_SIZE(smii_0_1_2_pins),
666 .modemuxs = smii_0_1_2_modemux,
667 .nmodemuxs = ARRAY_SIZE(smii_0_1_2_modemux),
668};
669
670static const char *const smii_0_1_2_grps[] = { "smii_0_1_2_grp" };
671static struct spear_function smii_0_1_2_function = {
672 .name = "smii_0_1_2",
673 .groups = smii_0_1_2_grps,
674 .ngroups = ARRAY_SIZE(smii_0_1_2_grps),
675};
676
677/* Pad multiplexing for ras_mii_txclk device */
678static const unsigned ras_mii_txclk_pins[] = { 98, 99 };
679static struct spear_muxreg ras_mii_txclk_muxreg[] = {
680 {
681 .reg = PAD_FUNCTION_EN_1,
682 .mask = PMX_NFCE2_MASK,
683 .val = 0,
684 },
685};
686
687static struct spear_modemux ras_mii_txclk_modemux[] = {
688 {
689 .muxregs = ras_mii_txclk_muxreg,
690 .nmuxregs = ARRAY_SIZE(ras_mii_txclk_muxreg),
691 },
692};
693
694static struct spear_pingroup ras_mii_txclk_pingroup = {
695 .name = "ras_mii_txclk_grp",
696 .pins = ras_mii_txclk_pins,
697 .npins = ARRAY_SIZE(ras_mii_txclk_pins),
698 .modemuxs = ras_mii_txclk_modemux,
699 .nmodemuxs = ARRAY_SIZE(ras_mii_txclk_modemux),
700};
701
702static const char *const ras_mii_txclk_grps[] = { "ras_mii_txclk_grp" };
703static struct spear_function ras_mii_txclk_function = {
704 .name = "ras_mii_txclk",
705 .groups = ras_mii_txclk_grps,
706 .ngroups = ARRAY_SIZE(ras_mii_txclk_grps),
707};
708
709/* Pad multiplexing for nand 8bit device (cs0 only) */
710static const unsigned nand_8bit_pins[] = { 56, 57, 58, 59, 60, 61, 62, 63, 64,
711 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82,
712 83, 84, 85, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169,
713 170, 171, 172, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211,
714 212 };
715static struct spear_muxreg nand_8bit_muxreg[] = {
716 {
717 .reg = PAD_FUNCTION_EN_0,
718 .mask = PMX_NAND8BIT_0_MASK,
719 .val = PMX_NAND8BIT_0_MASK,
720 }, {
721 .reg = PAD_FUNCTION_EN_1,
722 .mask = PMX_NAND8BIT_1_MASK,
723 .val = PMX_NAND8BIT_1_MASK,
724 },
725};
726
727static struct spear_modemux nand_8bit_modemux[] = {
728 {
729 .muxregs = nand_8bit_muxreg,
730 .nmuxregs = ARRAY_SIZE(nand_8bit_muxreg),
731 },
732};
733
734static struct spear_pingroup nand_8bit_pingroup = {
735 .name = "nand_8bit_grp",
736 .pins = nand_8bit_pins,
737 .npins = ARRAY_SIZE(nand_8bit_pins),
738 .modemuxs = nand_8bit_modemux,
739 .nmodemuxs = ARRAY_SIZE(nand_8bit_modemux),
740};
741
742/* Pad multiplexing for nand 16bit device */
743static const unsigned nand_16bit_pins[] = { 201, 202, 203, 204, 207, 208, 209,
744 210 };
745static struct spear_muxreg nand_16bit_muxreg[] = {
746 {
747 .reg = PAD_FUNCTION_EN_1,
748 .mask = PMX_NAND16BIT_1_MASK,
749 .val = PMX_NAND16BIT_1_MASK,
750 },
751};
752
753static struct spear_modemux nand_16bit_modemux[] = {
754 {
755 .muxregs = nand_16bit_muxreg,
756 .nmuxregs = ARRAY_SIZE(nand_16bit_muxreg),
757 },
758};
759
760static struct spear_pingroup nand_16bit_pingroup = {
761 .name = "nand_16bit_grp",
762 .pins = nand_16bit_pins,
763 .npins = ARRAY_SIZE(nand_16bit_pins),
764 .modemuxs = nand_16bit_modemux,
765 .nmodemuxs = ARRAY_SIZE(nand_16bit_modemux),
766};
767
768/* Pad multiplexing for nand 4 chips */
769static const unsigned nand_4_chips_pins[] = { 205, 206, 211, 212 };
770static struct spear_muxreg nand_4_chips_muxreg[] = {
771 {
772 .reg = PAD_FUNCTION_EN_1,
773 .mask = PMX_NAND_4CHIPS_MASK,
774 .val = PMX_NAND_4CHIPS_MASK,
775 },
776};
777
778static struct spear_modemux nand_4_chips_modemux[] = {
779 {
780 .muxregs = nand_4_chips_muxreg,
781 .nmuxregs = ARRAY_SIZE(nand_4_chips_muxreg),
782 },
783};
784
785static struct spear_pingroup nand_4_chips_pingroup = {
786 .name = "nand_4_chips_grp",
787 .pins = nand_4_chips_pins,
788 .npins = ARRAY_SIZE(nand_4_chips_pins),
789 .modemuxs = nand_4_chips_modemux,
790 .nmodemuxs = ARRAY_SIZE(nand_4_chips_modemux),
791};
792
793static const char *const nand_grps[] = { "nand_8bit_grp", "nand_16bit_grp",
794 "nand_4_chips_grp" };
795static struct spear_function nand_function = {
796 .name = "nand",
797 .groups = nand_grps,
798 .ngroups = ARRAY_SIZE(nand_grps),
799};
800
801/* Pad multiplexing for keyboard_6x6 device */
802static const unsigned keyboard_6x6_pins[] = { 201, 202, 203, 204, 205, 206, 207,
803 208, 209, 210, 211, 212 };
804static struct spear_muxreg keyboard_6x6_muxreg[] = {
805 {
806 .reg = PAD_FUNCTION_EN_1,
807 .mask = PMX_KEYBOARD_6X6_MASK | PMX_NFIO8_15_MASK |
808 PMX_NFCE1_MASK | PMX_NFCE2_MASK | PMX_NFWPRT1_MASK |
809 PMX_NFWPRT2_MASK,
810 .val = PMX_KEYBOARD_6X6_MASK,
811 },
812};
813
814static struct spear_modemux keyboard_6x6_modemux[] = {
815 {
816 .muxregs = keyboard_6x6_muxreg,
817 .nmuxregs = ARRAY_SIZE(keyboard_6x6_muxreg),
818 },
819};
820
821static struct spear_pingroup keyboard_6x6_pingroup = {
822 .name = "keyboard_6x6_grp",
823 .pins = keyboard_6x6_pins,
824 .npins = ARRAY_SIZE(keyboard_6x6_pins),
825 .modemuxs = keyboard_6x6_modemux,
826 .nmodemuxs = ARRAY_SIZE(keyboard_6x6_modemux),
827};
828
829/* Pad multiplexing for keyboard_rowcol6_8 device */
830static const unsigned keyboard_rowcol6_8_pins[] = { 24, 25, 26, 27, 28, 29 };
831static struct spear_muxreg keyboard_rowcol6_8_muxreg[] = {
832 {
833 .reg = PAD_FUNCTION_EN_1,
834 .mask = PMX_KBD_ROWCOL68_MASK,
835 .val = PMX_KBD_ROWCOL68_MASK,
836 },
837};
838
839static struct spear_modemux keyboard_rowcol6_8_modemux[] = {
840 {
841 .muxregs = keyboard_rowcol6_8_muxreg,
842 .nmuxregs = ARRAY_SIZE(keyboard_rowcol6_8_muxreg),
843 },
844};
845
846static struct spear_pingroup keyboard_rowcol6_8_pingroup = {
847 .name = "keyboard_rowcol6_8_grp",
848 .pins = keyboard_rowcol6_8_pins,
849 .npins = ARRAY_SIZE(keyboard_rowcol6_8_pins),
850 .modemuxs = keyboard_rowcol6_8_modemux,
851 .nmodemuxs = ARRAY_SIZE(keyboard_rowcol6_8_modemux),
852};
853
854static const char *const keyboard_grps[] = { "keyboard_6x6_grp",
855 "keyboard_rowcol6_8_grp" };
856static struct spear_function keyboard_function = {
857 .name = "keyboard",
858 .groups = keyboard_grps,
859 .ngroups = ARRAY_SIZE(keyboard_grps),
860};
861
862/* Pad multiplexing for uart0 device */
863static const unsigned uart0_pins[] = { 100, 101 };
864static struct spear_muxreg uart0_muxreg[] = {
865 {
866 .reg = PAD_FUNCTION_EN_0,
867 .mask = PMX_UART0_MASK,
868 .val = PMX_UART0_MASK,
869 },
870};
871
872static struct spear_modemux uart0_modemux[] = {
873 {
874 .muxregs = uart0_muxreg,
875 .nmuxregs = ARRAY_SIZE(uart0_muxreg),
876 },
877};
878
879static struct spear_pingroup uart0_pingroup = {
880 .name = "uart0_grp",
881 .pins = uart0_pins,
882 .npins = ARRAY_SIZE(uart0_pins),
883 .modemuxs = uart0_modemux,
884 .nmodemuxs = ARRAY_SIZE(uart0_modemux),
885};
886
887/* Pad multiplexing for uart0_modem device */
888static const unsigned uart0_modem_pins[] = { 12, 13, 14, 15, 16, 17 };
889static struct spear_muxreg uart0_modem_muxreg[] = {
890 {
891 .reg = PAD_FUNCTION_EN_1,
892 .mask = PMX_UART0_MODEM_MASK,
893 .val = PMX_UART0_MODEM_MASK,
894 },
895};
896
897static struct spear_modemux uart0_modem_modemux[] = {
898 {
899 .muxregs = uart0_modem_muxreg,
900 .nmuxregs = ARRAY_SIZE(uart0_modem_muxreg),
901 },
902};
903
904static struct spear_pingroup uart0_modem_pingroup = {
905 .name = "uart0_modem_grp",
906 .pins = uart0_modem_pins,
907 .npins = ARRAY_SIZE(uart0_modem_pins),
908 .modemuxs = uart0_modem_modemux,
909 .nmodemuxs = ARRAY_SIZE(uart0_modem_modemux),
910};
911
912static const char *const uart0_grps[] = { "uart0_grp", "uart0_modem_grp" };
913static struct spear_function uart0_function = {
914 .name = "uart0",
915 .groups = uart0_grps,
916 .ngroups = ARRAY_SIZE(uart0_grps),
917};
918
919/* Pad multiplexing for gpt0_tmr0 device */
920static const unsigned gpt0_tmr0_pins[] = { 10, 11 };
921static struct spear_muxreg gpt0_tmr0_muxreg[] = {
922 {
923 .reg = PAD_FUNCTION_EN_1,
924 .mask = PMX_GPT0_TMR0_MASK,
925 .val = PMX_GPT0_TMR0_MASK,
926 },
927};
928
929static struct spear_modemux gpt0_tmr0_modemux[] = {
930 {
931 .muxregs = gpt0_tmr0_muxreg,
932 .nmuxregs = ARRAY_SIZE(gpt0_tmr0_muxreg),
933 },
934};
935
936static struct spear_pingroup gpt0_tmr0_pingroup = {
937 .name = "gpt0_tmr0_grp",
938 .pins = gpt0_tmr0_pins,
939 .npins = ARRAY_SIZE(gpt0_tmr0_pins),
940 .modemuxs = gpt0_tmr0_modemux,
941 .nmodemuxs = ARRAY_SIZE(gpt0_tmr0_modemux),
942};
943
944/* Pad multiplexing for gpt0_tmr1 device */
945static const unsigned gpt0_tmr1_pins[] = { 8, 9 };
946static struct spear_muxreg gpt0_tmr1_muxreg[] = {
947 {
948 .reg = PAD_FUNCTION_EN_1,
949 .mask = PMX_GPT0_TMR1_MASK,
950 .val = PMX_GPT0_TMR1_MASK,
951 },
952};
953
954static struct spear_modemux gpt0_tmr1_modemux[] = {
955 {
956 .muxregs = gpt0_tmr1_muxreg,
957 .nmuxregs = ARRAY_SIZE(gpt0_tmr1_muxreg),
958 },
959};
960
961static struct spear_pingroup gpt0_tmr1_pingroup = {
962 .name = "gpt0_tmr1_grp",
963 .pins = gpt0_tmr1_pins,
964 .npins = ARRAY_SIZE(gpt0_tmr1_pins),
965 .modemuxs = gpt0_tmr1_modemux,
966 .nmodemuxs = ARRAY_SIZE(gpt0_tmr1_modemux),
967};
968
969static const char *const gpt0_grps[] = { "gpt0_tmr0_grp", "gpt0_tmr1_grp" };
970static struct spear_function gpt0_function = {
971 .name = "gpt0",
972 .groups = gpt0_grps,
973 .ngroups = ARRAY_SIZE(gpt0_grps),
974};
975
976/* Pad multiplexing for gpt1_tmr0 device */
977static const unsigned gpt1_tmr0_pins[] = { 6, 7 };
978static struct spear_muxreg gpt1_tmr0_muxreg[] = {
979 {
980 .reg = PAD_FUNCTION_EN_1,
981 .mask = PMX_GPT1_TMR0_MASK,
982 .val = PMX_GPT1_TMR0_MASK,
983 },
984};
985
986static struct spear_modemux gpt1_tmr0_modemux[] = {
987 {
988 .muxregs = gpt1_tmr0_muxreg,
989 .nmuxregs = ARRAY_SIZE(gpt1_tmr0_muxreg),
990 },
991};
992
993static struct spear_pingroup gpt1_tmr0_pingroup = {
994 .name = "gpt1_tmr0_grp",
995 .pins = gpt1_tmr0_pins,
996 .npins = ARRAY_SIZE(gpt1_tmr0_pins),
997 .modemuxs = gpt1_tmr0_modemux,
998 .nmodemuxs = ARRAY_SIZE(gpt1_tmr0_modemux),
999};
1000
1001/* Pad multiplexing for gpt1_tmr1 device */
1002static const unsigned gpt1_tmr1_pins[] = { 4, 5 };
1003static struct spear_muxreg gpt1_tmr1_muxreg[] = {
1004 {
1005 .reg = PAD_FUNCTION_EN_1,
1006 .mask = PMX_GPT1_TMR1_MASK,
1007 .val = PMX_GPT1_TMR1_MASK,
1008 },
1009};
1010
1011static struct spear_modemux gpt1_tmr1_modemux[] = {
1012 {
1013 .muxregs = gpt1_tmr1_muxreg,
1014 .nmuxregs = ARRAY_SIZE(gpt1_tmr1_muxreg),
1015 },
1016};
1017
1018static struct spear_pingroup gpt1_tmr1_pingroup = {
1019 .name = "gpt1_tmr1_grp",
1020 .pins = gpt1_tmr1_pins,
1021 .npins = ARRAY_SIZE(gpt1_tmr1_pins),
1022 .modemuxs = gpt1_tmr1_modemux,
1023 .nmodemuxs = ARRAY_SIZE(gpt1_tmr1_modemux),
1024};
1025
1026static const char *const gpt1_grps[] = { "gpt1_tmr1_grp", "gpt1_tmr0_grp" };
1027static struct spear_function gpt1_function = {
1028 .name = "gpt1",
1029 .groups = gpt1_grps,
1030 .ngroups = ARRAY_SIZE(gpt1_grps),
1031};
1032
1033/* Pad multiplexing for mcif device */
1034static const unsigned mcif_pins[] = { 86, 87, 88, 89, 90, 91, 92, 93, 213, 214,
1035 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228,
1036 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242,
1037 243, 244, 245 };
1038#define MCIF_MUXREG \
1039 { \
1040 .reg = PAD_FUNCTION_EN_0, \
1041 .mask = PMX_MCI_DATA8_15_MASK, \
1042 .val = PMX_MCI_DATA8_15_MASK, \
1043 }, { \
1044 .reg = PAD_FUNCTION_EN_1, \
1045 .mask = PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK | \
1046 PMX_NFWPRT2_MASK, \
1047 .val = PMX_MCIFALL_1_MASK, \
1048 }, { \
1049 .reg = PAD_FUNCTION_EN_2, \
1050 .mask = PMX_MCIFALL_2_MASK, \
1051 .val = PMX_MCIFALL_2_MASK, \
1052 }
1053
1054/* sdhci device */
1055static struct spear_muxreg sdhci_muxreg[] = {
1056 MCIF_MUXREG,
1057 {
1058 .reg = PERIP_CFG,
1059 .mask = MCIF_SEL_MASK,
1060 .val = MCIF_SEL_SD,
1061 },
1062};
1063
1064static struct spear_modemux sdhci_modemux[] = {
1065 {
1066 .muxregs = sdhci_muxreg,
1067 .nmuxregs = ARRAY_SIZE(sdhci_muxreg),
1068 },
1069};
1070
1071static struct spear_pingroup sdhci_pingroup = {
1072 .name = "sdhci_grp",
1073 .pins = mcif_pins,
1074 .npins = ARRAY_SIZE(mcif_pins),
1075 .modemuxs = sdhci_modemux,
1076 .nmodemuxs = ARRAY_SIZE(sdhci_modemux),
1077};
1078
1079static const char *const sdhci_grps[] = { "sdhci_grp" };
1080static struct spear_function sdhci_function = {
1081 .name = "sdhci",
1082 .groups = sdhci_grps,
1083 .ngroups = ARRAY_SIZE(sdhci_grps),
1084};
1085
1086/* cf device */
1087static struct spear_muxreg cf_muxreg[] = {
1088 MCIF_MUXREG,
1089 {
1090 .reg = PERIP_CFG,
1091 .mask = MCIF_SEL_MASK,
1092 .val = MCIF_SEL_CF,
1093 },
1094};
1095
1096static struct spear_modemux cf_modemux[] = {
1097 {
1098 .muxregs = cf_muxreg,
1099 .nmuxregs = ARRAY_SIZE(cf_muxreg),
1100 },
1101};
1102
1103static struct spear_pingroup cf_pingroup = {
1104 .name = "cf_grp",
1105 .pins = mcif_pins,
1106 .npins = ARRAY_SIZE(mcif_pins),
1107 .modemuxs = cf_modemux,
1108 .nmodemuxs = ARRAY_SIZE(cf_modemux),
1109};
1110
1111static const char *const cf_grps[] = { "cf_grp" };
1112static struct spear_function cf_function = {
1113 .name = "cf",
1114 .groups = cf_grps,
1115 .ngroups = ARRAY_SIZE(cf_grps),
1116};
1117
1118/* xd device */
1119static struct spear_muxreg xd_muxreg[] = {
1120 MCIF_MUXREG,
1121 {
1122 .reg = PERIP_CFG,
1123 .mask = MCIF_SEL_MASK,
1124 .val = MCIF_SEL_XD,
1125 },
1126};
1127
1128static struct spear_modemux xd_modemux[] = {
1129 {
1130 .muxregs = xd_muxreg,
1131 .nmuxregs = ARRAY_SIZE(xd_muxreg),
1132 },
1133};
1134
1135static struct spear_pingroup xd_pingroup = {
1136 .name = "xd_grp",
1137 .pins = mcif_pins,
1138 .npins = ARRAY_SIZE(mcif_pins),
1139 .modemuxs = xd_modemux,
1140 .nmodemuxs = ARRAY_SIZE(xd_modemux),
1141};
1142
1143static const char *const xd_grps[] = { "xd_grp" };
1144static struct spear_function xd_function = {
1145 .name = "xd",
1146 .groups = xd_grps,
1147 .ngroups = ARRAY_SIZE(xd_grps),
1148};
1149
1150/* Pad multiplexing for touch_xy device */
1151static const unsigned touch_xy_pins[] = { 97 };
1152static struct spear_muxreg touch_xy_muxreg[] = {
1153 {
1154 .reg = PAD_FUNCTION_EN_2,
1155 .mask = PMX_TOUCH_XY_MASK,
1156 .val = PMX_TOUCH_XY_MASK,
1157 },
1158};
1159
1160static struct spear_modemux touch_xy_modemux[] = {
1161 {
1162 .muxregs = touch_xy_muxreg,
1163 .nmuxregs = ARRAY_SIZE(touch_xy_muxreg),
1164 },
1165};
1166
1167static struct spear_pingroup touch_xy_pingroup = {
1168 .name = "touch_xy_grp",
1169 .pins = touch_xy_pins,
1170 .npins = ARRAY_SIZE(touch_xy_pins),
1171 .modemuxs = touch_xy_modemux,
1172 .nmodemuxs = ARRAY_SIZE(touch_xy_modemux),
1173};
1174
1175static const char *const touch_xy_grps[] = { "touch_xy_grp" };
1176static struct spear_function touch_xy_function = {
1177 .name = "touchscreen",
1178 .groups = touch_xy_grps,
1179 .ngroups = ARRAY_SIZE(touch_xy_grps),
1180};
1181
1182/* Pad multiplexing for uart1 device */
1183/* Muxed with I2C */
1184static const unsigned uart1_dis_i2c_pins[] = { 102, 103 };
1185static struct spear_muxreg uart1_dis_i2c_muxreg[] = {
1186 {
1187 .reg = PAD_FUNCTION_EN_0,
1188 .mask = PMX_I2C0_MASK,
1189 .val = 0,
1190 },
1191};
1192
1193static struct spear_modemux uart1_dis_i2c_modemux[] = {
1194 {
1195 .muxregs = uart1_dis_i2c_muxreg,
1196 .nmuxregs = ARRAY_SIZE(uart1_dis_i2c_muxreg),
1197 },
1198};
1199
1200static struct spear_pingroup uart_1_dis_i2c_pingroup = {
1201 .name = "uart1_disable_i2c_grp",
1202 .pins = uart1_dis_i2c_pins,
1203 .npins = ARRAY_SIZE(uart1_dis_i2c_pins),
1204 .modemuxs = uart1_dis_i2c_modemux,
1205 .nmodemuxs = ARRAY_SIZE(uart1_dis_i2c_modemux),
1206};
1207
1208/* Muxed with SD/MMC */
1209static const unsigned uart1_dis_sd_pins[] = { 214, 215 };
1210static struct spear_muxreg uart1_dis_sd_muxreg[] = {
1211 {
1212 .reg = PAD_FUNCTION_EN_1,
1213 .mask = PMX_MCIDATA1_MASK |
1214 PMX_MCIDATA2_MASK,
1215 .val = 0,
1216 },
1217};
1218
1219static struct spear_modemux uart1_dis_sd_modemux[] = {
1220 {
1221 .muxregs = uart1_dis_sd_muxreg,
1222 .nmuxregs = ARRAY_SIZE(uart1_dis_sd_muxreg),
1223 },
1224};
1225
1226static struct spear_pingroup uart_1_dis_sd_pingroup = {
1227 .name = "uart1_disable_sd_grp",
1228 .pins = uart1_dis_sd_pins,
1229 .npins = ARRAY_SIZE(uart1_dis_sd_pins),
1230 .modemuxs = uart1_dis_sd_modemux,
1231 .nmodemuxs = ARRAY_SIZE(uart1_dis_sd_modemux),
1232};
1233
1234static const char *const uart1_grps[] = { "uart1_disable_i2c_grp",
1235 "uart1_disable_sd_grp" };
1236static struct spear_function uart1_function = {
1237 .name = "uart1",
1238 .groups = uart1_grps,
1239 .ngroups = ARRAY_SIZE(uart1_grps),
1240};
1241
1242/* Pad multiplexing for uart2_3 device */
1243static const unsigned uart2_3_pins[] = { 104, 105, 106, 107 };
1244static struct spear_muxreg uart2_3_muxreg[] = {
1245 {
1246 .reg = PAD_FUNCTION_EN_0,
1247 .mask = PMX_I2S0_MASK,
1248 .val = 0,
1249 },
1250};
1251
1252static struct spear_modemux uart2_3_modemux[] = {
1253 {
1254 .muxregs = uart2_3_muxreg,
1255 .nmuxregs = ARRAY_SIZE(uart2_3_muxreg),
1256 },
1257};
1258
1259static struct spear_pingroup uart_2_3_pingroup = {
1260 .name = "uart2_3_grp",
1261 .pins = uart2_3_pins,
1262 .npins = ARRAY_SIZE(uart2_3_pins),
1263 .modemuxs = uart2_3_modemux,
1264 .nmodemuxs = ARRAY_SIZE(uart2_3_modemux),
1265};
1266
1267static const char *const uart2_3_grps[] = { "uart2_3_grp" };
1268static struct spear_function uart2_3_function = {
1269 .name = "uart2_3",
1270 .groups = uart2_3_grps,
1271 .ngroups = ARRAY_SIZE(uart2_3_grps),
1272};
1273
1274/* Pad multiplexing for uart4 device */
1275static const unsigned uart4_pins[] = { 108, 113 };
1276static struct spear_muxreg uart4_muxreg[] = {
1277 {
1278 .reg = PAD_FUNCTION_EN_0,
1279 .mask = PMX_I2S0_MASK | PMX_CLCD1_MASK,
1280 .val = 0,
1281 },
1282};
1283
1284static struct spear_modemux uart4_modemux[] = {
1285 {
1286 .muxregs = uart4_muxreg,
1287 .nmuxregs = ARRAY_SIZE(uart4_muxreg),
1288 },
1289};
1290
1291static struct spear_pingroup uart_4_pingroup = {
1292 .name = "uart4_grp",
1293 .pins = uart4_pins,
1294 .npins = ARRAY_SIZE(uart4_pins),
1295 .modemuxs = uart4_modemux,
1296 .nmodemuxs = ARRAY_SIZE(uart4_modemux),
1297};
1298
1299static const char *const uart4_grps[] = { "uart4_grp" };
1300static struct spear_function uart4_function = {
1301 .name = "uart4",
1302 .groups = uart4_grps,
1303 .ngroups = ARRAY_SIZE(uart4_grps),
1304};
1305
1306/* Pad multiplexing for uart5 device */
1307static const unsigned uart5_pins[] = { 114, 115 };
1308static struct spear_muxreg uart5_muxreg[] = {
1309 {
1310 .reg = PAD_FUNCTION_EN_0,
1311 .mask = PMX_CLCD1_MASK,
1312 .val = 0,
1313 },
1314};
1315
1316static struct spear_modemux uart5_modemux[] = {
1317 {
1318 .muxregs = uart5_muxreg,
1319 .nmuxregs = ARRAY_SIZE(uart5_muxreg),
1320 },
1321};
1322
1323static struct spear_pingroup uart_5_pingroup = {
1324 .name = "uart5_grp",
1325 .pins = uart5_pins,
1326 .npins = ARRAY_SIZE(uart5_pins),
1327 .modemuxs = uart5_modemux,
1328 .nmodemuxs = ARRAY_SIZE(uart5_modemux),
1329};
1330
1331static const char *const uart5_grps[] = { "uart5_grp" };
1332static struct spear_function uart5_function = {
1333 .name = "uart5",
1334 .groups = uart5_grps,
1335 .ngroups = ARRAY_SIZE(uart5_grps),
1336};
1337
1338/* Pad multiplexing for rs485_0_1_tdm_0_1 device */
1339static const unsigned rs485_0_1_tdm_0_1_pins[] = { 116, 117, 118, 119, 120, 121,
1340 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135,
1341 136, 137 };
1342static struct spear_muxreg rs485_0_1_tdm_0_1_muxreg[] = {
1343 {
1344 .reg = PAD_FUNCTION_EN_0,
1345 .mask = PMX_CLCD1_MASK,
1346 .val = 0,
1347 },
1348};
1349
1350static struct spear_modemux rs485_0_1_tdm_0_1_modemux[] = {
1351 {
1352 .muxregs = rs485_0_1_tdm_0_1_muxreg,
1353 .nmuxregs = ARRAY_SIZE(rs485_0_1_tdm_0_1_muxreg),
1354 },
1355};
1356
1357static struct spear_pingroup rs485_0_1_tdm_0_1_pingroup = {
1358 .name = "rs485_0_1_tdm_0_1_grp",
1359 .pins = rs485_0_1_tdm_0_1_pins,
1360 .npins = ARRAY_SIZE(rs485_0_1_tdm_0_1_pins),
1361 .modemuxs = rs485_0_1_tdm_0_1_modemux,
1362 .nmodemuxs = ARRAY_SIZE(rs485_0_1_tdm_0_1_modemux),
1363};
1364
1365static const char *const rs485_0_1_tdm_0_1_grps[] = { "rs485_0_1_tdm_0_1_grp" };
1366static struct spear_function rs485_0_1_tdm_0_1_function = {
1367 .name = "rs485_0_1_tdm_0_1",
1368 .groups = rs485_0_1_tdm_0_1_grps,
1369 .ngroups = ARRAY_SIZE(rs485_0_1_tdm_0_1_grps),
1370};
1371
1372/* Pad multiplexing for i2c_1_2 device */
1373static const unsigned i2c_1_2_pins[] = { 138, 139, 140, 141 };
1374static struct spear_muxreg i2c_1_2_muxreg[] = {
1375 {
1376 .reg = PAD_FUNCTION_EN_0,
1377 .mask = PMX_CLCD1_MASK,
1378 .val = 0,
1379 },
1380};
1381
1382static struct spear_modemux i2c_1_2_modemux[] = {
1383 {
1384 .muxregs = i2c_1_2_muxreg,
1385 .nmuxregs = ARRAY_SIZE(i2c_1_2_muxreg),
1386 },
1387};
1388
1389static struct spear_pingroup i2c_1_2_pingroup = {
1390 .name = "i2c_1_2_grp",
1391 .pins = i2c_1_2_pins,
1392 .npins = ARRAY_SIZE(i2c_1_2_pins),
1393 .modemuxs = i2c_1_2_modemux,
1394 .nmodemuxs = ARRAY_SIZE(i2c_1_2_modemux),
1395};
1396
1397static const char *const i2c_1_2_grps[] = { "i2c_1_2_grp" };
1398static struct spear_function i2c_1_2_function = {
1399 .name = "i2c_1_2",
1400 .groups = i2c_1_2_grps,
1401 .ngroups = ARRAY_SIZE(i2c_1_2_grps),
1402};
1403
1404/* Pad multiplexing for i2c3_dis_smi_clcd device */
1405/* Muxed with SMI & CLCD */
1406static const unsigned i2c3_dis_smi_clcd_pins[] = { 142, 153 };
1407static struct spear_muxreg i2c3_dis_smi_clcd_muxreg[] = {
1408 {
1409 .reg = PAD_FUNCTION_EN_0,
1410 .mask = PMX_CLCD1_MASK | PMX_SMI_MASK,
1411 .val = 0,
1412 },
1413};
1414
1415static struct spear_modemux i2c3_dis_smi_clcd_modemux[] = {
1416 {
1417 .muxregs = i2c3_dis_smi_clcd_muxreg,
1418 .nmuxregs = ARRAY_SIZE(i2c3_dis_smi_clcd_muxreg),
1419 },
1420};
1421
1422static struct spear_pingroup i2c3_dis_smi_clcd_pingroup = {
1423 .name = "i2c3_dis_smi_clcd_grp",
1424 .pins = i2c3_dis_smi_clcd_pins,
1425 .npins = ARRAY_SIZE(i2c3_dis_smi_clcd_pins),
1426 .modemuxs = i2c3_dis_smi_clcd_modemux,
1427 .nmodemuxs = ARRAY_SIZE(i2c3_dis_smi_clcd_modemux),
1428};
1429
1430/* Pad multiplexing for i2c3_dis_sd_i2s0 device */
1431/* Muxed with SD/MMC & I2S1 */
1432static const unsigned i2c3_dis_sd_i2s0_pins[] = { 0, 216 };
1433static struct spear_muxreg i2c3_dis_sd_i2s0_muxreg[] = {
1434 {
1435 .reg = PAD_FUNCTION_EN_1,
1436 .mask = PMX_I2S1_MASK | PMX_MCIDATA3_MASK,
1437 .val = 0,
1438 },
1439};
1440
1441static struct spear_modemux i2c3_dis_sd_i2s0_modemux[] = {
1442 {
1443 .muxregs = i2c3_dis_sd_i2s0_muxreg,
1444 .nmuxregs = ARRAY_SIZE(i2c3_dis_sd_i2s0_muxreg),
1445 },
1446};
1447
1448static struct spear_pingroup i2c3_dis_sd_i2s0_pingroup = {
1449 .name = "i2c3_dis_sd_i2s0_grp",
1450 .pins = i2c3_dis_sd_i2s0_pins,
1451 .npins = ARRAY_SIZE(i2c3_dis_sd_i2s0_pins),
1452 .modemuxs = i2c3_dis_sd_i2s0_modemux,
1453 .nmodemuxs = ARRAY_SIZE(i2c3_dis_sd_i2s0_modemux),
1454};
1455
1456static const char *const i2c3_grps[] = { "i2c3_dis_smi_clcd_grp",
1457 "i2c3_dis_sd_i2s0_grp" };
1458static struct spear_function i2c3_unction = {
1459 .name = "i2c3_i2s1",
1460 .groups = i2c3_grps,
1461 .ngroups = ARRAY_SIZE(i2c3_grps),
1462};
1463
1464/* Pad multiplexing for i2c_4_5_dis_smi device */
1465/* Muxed with SMI */
1466static const unsigned i2c_4_5_dis_smi_pins[] = { 154, 155, 156, 157 };
1467static struct spear_muxreg i2c_4_5_dis_smi_muxreg[] = {
1468 {
1469 .reg = PAD_FUNCTION_EN_0,
1470 .mask = PMX_SMI_MASK,
1471 .val = 0,
1472 },
1473};
1474
1475static struct spear_modemux i2c_4_5_dis_smi_modemux[] = {
1476 {
1477 .muxregs = i2c_4_5_dis_smi_muxreg,
1478 .nmuxregs = ARRAY_SIZE(i2c_4_5_dis_smi_muxreg),
1479 },
1480};
1481
1482static struct spear_pingroup i2c_4_5_dis_smi_pingroup = {
1483 .name = "i2c_4_5_dis_smi_grp",
1484 .pins = i2c_4_5_dis_smi_pins,
1485 .npins = ARRAY_SIZE(i2c_4_5_dis_smi_pins),
1486 .modemuxs = i2c_4_5_dis_smi_modemux,
1487 .nmodemuxs = ARRAY_SIZE(i2c_4_5_dis_smi_modemux),
1488};
1489
1490/* Pad multiplexing for i2c4_dis_sd device */
1491/* Muxed with SD/MMC */
1492static const unsigned i2c4_dis_sd_pins[] = { 217, 218 };
1493static struct spear_muxreg i2c4_dis_sd_muxreg[] = {
1494 {
1495 .reg = PAD_FUNCTION_EN_1,
1496 .mask = PMX_MCIDATA4_MASK,
1497 .val = 0,
1498 }, {
1499 .reg = PAD_FUNCTION_EN_2,
1500 .mask = PMX_MCIDATA5_MASK,
1501 .val = 0,
1502 },
1503};
1504
1505static struct spear_modemux i2c4_dis_sd_modemux[] = {
1506 {
1507 .muxregs = i2c4_dis_sd_muxreg,
1508 .nmuxregs = ARRAY_SIZE(i2c4_dis_sd_muxreg),
1509 },
1510};
1511
1512static struct spear_pingroup i2c4_dis_sd_pingroup = {
1513 .name = "i2c4_dis_sd_grp",
1514 .pins = i2c4_dis_sd_pins,
1515 .npins = ARRAY_SIZE(i2c4_dis_sd_pins),
1516 .modemuxs = i2c4_dis_sd_modemux,
1517 .nmodemuxs = ARRAY_SIZE(i2c4_dis_sd_modemux),
1518};
1519
1520/* Pad multiplexing for i2c5_dis_sd device */
1521/* Muxed with SD/MMC */
1522static const unsigned i2c5_dis_sd_pins[] = { 219, 220 };
1523static struct spear_muxreg i2c5_dis_sd_muxreg[] = {
1524 {
1525 .reg = PAD_FUNCTION_EN_2,
1526 .mask = PMX_MCIDATA6_MASK |
1527 PMX_MCIDATA7_MASK,
1528 .val = 0,
1529 },
1530};
1531
1532static struct spear_modemux i2c5_dis_sd_modemux[] = {
1533 {
1534 .muxregs = i2c5_dis_sd_muxreg,
1535 .nmuxregs = ARRAY_SIZE(i2c5_dis_sd_muxreg),
1536 },
1537};
1538
1539static struct spear_pingroup i2c5_dis_sd_pingroup = {
1540 .name = "i2c5_dis_sd_grp",
1541 .pins = i2c5_dis_sd_pins,
1542 .npins = ARRAY_SIZE(i2c5_dis_sd_pins),
1543 .modemuxs = i2c5_dis_sd_modemux,
1544 .nmodemuxs = ARRAY_SIZE(i2c5_dis_sd_modemux),
1545};
1546
1547static const char *const i2c_4_5_grps[] = { "i2c5_dis_sd_grp",
1548 "i2c4_dis_sd_grp", "i2c_4_5_dis_smi_grp" };
1549static struct spear_function i2c_4_5_function = {
1550 .name = "i2c_4_5",
1551 .groups = i2c_4_5_grps,
1552 .ngroups = ARRAY_SIZE(i2c_4_5_grps),
1553};
1554
1555/* Pad multiplexing for i2c_6_7_dis_kbd device */
1556/* Muxed with KBD */
1557static const unsigned i2c_6_7_dis_kbd_pins[] = { 207, 208, 209, 210 };
1558static struct spear_muxreg i2c_6_7_dis_kbd_muxreg[] = {
1559 {
1560 .reg = PAD_FUNCTION_EN_1,
1561 .mask = PMX_KBD_ROWCOL25_MASK,
1562 .val = 0,
1563 },
1564};
1565
1566static struct spear_modemux i2c_6_7_dis_kbd_modemux[] = {
1567 {
1568 .muxregs = i2c_6_7_dis_kbd_muxreg,
1569 .nmuxregs = ARRAY_SIZE(i2c_6_7_dis_kbd_muxreg),
1570 },
1571};
1572
1573static struct spear_pingroup i2c_6_7_dis_kbd_pingroup = {
1574 .name = "i2c_6_7_dis_kbd_grp",
1575 .pins = i2c_6_7_dis_kbd_pins,
1576 .npins = ARRAY_SIZE(i2c_6_7_dis_kbd_pins),
1577 .modemuxs = i2c_6_7_dis_kbd_modemux,
1578 .nmodemuxs = ARRAY_SIZE(i2c_6_7_dis_kbd_modemux),
1579};
1580
1581/* Pad multiplexing for i2c6_dis_sd device */
1582/* Muxed with SD/MMC */
1583static const unsigned i2c6_dis_sd_pins[] = { 236, 237 };
1584static struct spear_muxreg i2c6_dis_sd_muxreg[] = {
1585 {
1586 .reg = PAD_FUNCTION_EN_2,
1587 .mask = PMX_MCIIORDRE_MASK |
1588 PMX_MCIIOWRWE_MASK,
1589 .val = 0,
1590 },
1591};
1592
1593static struct spear_modemux i2c6_dis_sd_modemux[] = {
1594 {
1595 .muxregs = i2c6_dis_sd_muxreg,
1596 .nmuxregs = ARRAY_SIZE(i2c6_dis_sd_muxreg),
1597 },
1598};
1599
1600static struct spear_pingroup i2c6_dis_sd_pingroup = {
1601 .name = "i2c6_dis_sd_grp",
1602 .pins = i2c6_dis_sd_pins,
1603 .npins = ARRAY_SIZE(i2c6_dis_sd_pins),
1604 .modemuxs = i2c6_dis_sd_modemux,
1605 .nmodemuxs = ARRAY_SIZE(i2c6_dis_sd_modemux),
1606};
1607
1608/* Pad multiplexing for i2c7_dis_sd device */
1609static const unsigned i2c7_dis_sd_pins[] = { 238, 239 };
1610static struct spear_muxreg i2c7_dis_sd_muxreg[] = {
1611 {
1612 .reg = PAD_FUNCTION_EN_2,
1613 .mask = PMX_MCIRESETCF_MASK |
1614 PMX_MCICS0CE_MASK,
1615 .val = 0,
1616 },
1617};
1618
1619static struct spear_modemux i2c7_dis_sd_modemux[] = {
1620 {
1621 .muxregs = i2c7_dis_sd_muxreg,
1622 .nmuxregs = ARRAY_SIZE(i2c7_dis_sd_muxreg),
1623 },
1624};
1625
1626static struct spear_pingroup i2c7_dis_sd_pingroup = {
1627 .name = "i2c7_dis_sd_grp",
1628 .pins = i2c7_dis_sd_pins,
1629 .npins = ARRAY_SIZE(i2c7_dis_sd_pins),
1630 .modemuxs = i2c7_dis_sd_modemux,
1631 .nmodemuxs = ARRAY_SIZE(i2c7_dis_sd_modemux),
1632};
1633
1634static const char *const i2c_6_7_grps[] = { "i2c6_dis_sd_grp",
1635 "i2c7_dis_sd_grp", "i2c_6_7_dis_kbd_grp" };
1636static struct spear_function i2c_6_7_function = {
1637 .name = "i2c_6_7",
1638 .groups = i2c_6_7_grps,
1639 .ngroups = ARRAY_SIZE(i2c_6_7_grps),
1640};
1641
1642/* Pad multiplexing for can0_dis_nor device */
1643/* Muxed with NOR */
1644static const unsigned can0_dis_nor_pins[] = { 56, 57 };
1645static struct spear_muxreg can0_dis_nor_muxreg[] = {
1646 {
1647 .reg = PAD_FUNCTION_EN_0,
1648 .mask = PMX_NFRSTPWDWN2_MASK,
1649 .val = 0,
1650 }, {
1651 .reg = PAD_FUNCTION_EN_1,
1652 .mask = PMX_NFRSTPWDWN3_MASK,
1653 .val = 0,
1654 },
1655};
1656
1657static struct spear_modemux can0_dis_nor_modemux[] = {
1658 {
1659 .muxregs = can0_dis_nor_muxreg,
1660 .nmuxregs = ARRAY_SIZE(can0_dis_nor_muxreg),
1661 },
1662};
1663
1664static struct spear_pingroup can0_dis_nor_pingroup = {
1665 .name = "can0_dis_nor_grp",
1666 .pins = can0_dis_nor_pins,
1667 .npins = ARRAY_SIZE(can0_dis_nor_pins),
1668 .modemuxs = can0_dis_nor_modemux,
1669 .nmodemuxs = ARRAY_SIZE(can0_dis_nor_modemux),
1670};
1671
1672/* Pad multiplexing for can0_dis_sd device */
1673/* Muxed with SD/MMC */
1674static const unsigned can0_dis_sd_pins[] = { 240, 241 };
1675static struct spear_muxreg can0_dis_sd_muxreg[] = {
1676 {
1677 .reg = PAD_FUNCTION_EN_2,
1678 .mask = PMX_MCICFINTR_MASK | PMX_MCIIORDY_MASK,
1679 .val = 0,
1680 },
1681};
1682
1683static struct spear_modemux can0_dis_sd_modemux[] = {
1684 {
1685 .muxregs = can0_dis_sd_muxreg,
1686 .nmuxregs = ARRAY_SIZE(can0_dis_sd_muxreg),
1687 },
1688};
1689
1690static struct spear_pingroup can0_dis_sd_pingroup = {
1691 .name = "can0_dis_sd_grp",
1692 .pins = can0_dis_sd_pins,
1693 .npins = ARRAY_SIZE(can0_dis_sd_pins),
1694 .modemuxs = can0_dis_sd_modemux,
1695 .nmodemuxs = ARRAY_SIZE(can0_dis_sd_modemux),
1696};
1697
1698static const char *const can0_grps[] = { "can0_dis_nor_grp", "can0_dis_sd_grp"
1699};
1700static struct spear_function can0_function = {
1701 .name = "can0",
1702 .groups = can0_grps,
1703 .ngroups = ARRAY_SIZE(can0_grps),
1704};
1705
1706/* Pad multiplexing for can1_dis_sd device */
1707/* Muxed with SD/MMC */
1708static const unsigned can1_dis_sd_pins[] = { 242, 243 };
1709static struct spear_muxreg can1_dis_sd_muxreg[] = {
1710 {
1711 .reg = PAD_FUNCTION_EN_2,
1712 .mask = PMX_MCICS1_MASK | PMX_MCIDMAACK_MASK,
1713 .val = 0,
1714 },
1715};
1716
1717static struct spear_modemux can1_dis_sd_modemux[] = {
1718 {
1719 .muxregs = can1_dis_sd_muxreg,
1720 .nmuxregs = ARRAY_SIZE(can1_dis_sd_muxreg),
1721 },
1722};
1723
1724static struct spear_pingroup can1_dis_sd_pingroup = {
1725 .name = "can1_dis_sd_grp",
1726 .pins = can1_dis_sd_pins,
1727 .npins = ARRAY_SIZE(can1_dis_sd_pins),
1728 .modemuxs = can1_dis_sd_modemux,
1729 .nmodemuxs = ARRAY_SIZE(can1_dis_sd_modemux),
1730};
1731
1732/* Pad multiplexing for can1_dis_kbd device */
1733/* Muxed with KBD */
1734static const unsigned can1_dis_kbd_pins[] = { 201, 202 };
1735static struct spear_muxreg can1_dis_kbd_muxreg[] = {
1736 {
1737 .reg = PAD_FUNCTION_EN_1,
1738 .mask = PMX_KBD_ROWCOL25_MASK,
1739 .val = 0,
1740 },
1741};
1742
1743static struct spear_modemux can1_dis_kbd_modemux[] = {
1744 {
1745 .muxregs = can1_dis_kbd_muxreg,
1746 .nmuxregs = ARRAY_SIZE(can1_dis_kbd_muxreg),
1747 },
1748};
1749
1750static struct spear_pingroup can1_dis_kbd_pingroup = {
1751 .name = "can1_dis_kbd_grp",
1752 .pins = can1_dis_kbd_pins,
1753 .npins = ARRAY_SIZE(can1_dis_kbd_pins),
1754 .modemuxs = can1_dis_kbd_modemux,
1755 .nmodemuxs = ARRAY_SIZE(can1_dis_kbd_modemux),
1756};
1757
1758static const char *const can1_grps[] = { "can1_dis_sd_grp", "can1_dis_kbd_grp"
1759};
1760static struct spear_function can1_function = {
1761 .name = "can1",
1762 .groups = can1_grps,
1763 .ngroups = ARRAY_SIZE(can1_grps),
1764};
1765
1766/* Pad multiplexing for pci device */
1767static const unsigned pci_sata_pins[] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 18,
1768 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,
1769 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54,
1770 55, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99 };
1771#define PCI_SATA_MUXREG \
1772 { \
1773 .reg = PAD_FUNCTION_EN_0, \
1774 .mask = PMX_MCI_DATA8_15_MASK, \
1775 .val = 0, \
1776 }, { \
1777 .reg = PAD_FUNCTION_EN_1, \
1778 .mask = PMX_PCI_REG1_MASK, \
1779 .val = 0, \
1780 }, { \
1781 .reg = PAD_FUNCTION_EN_2, \
1782 .mask = PMX_PCI_REG2_MASK, \
1783 .val = 0, \
1784 }
1785
1786/* pad multiplexing for pcie0 device */
1787static struct spear_muxreg pcie0_muxreg[] = {
1788 PCI_SATA_MUXREG,
1789 {
1790 .reg = PCIE_SATA_CFG,
1791 .mask = PCIE_CFG_VAL(0),
1792 .val = PCIE_CFG_VAL(0),
1793 },
1794};
1795
1796static struct spear_modemux pcie0_modemux[] = {
1797 {
1798 .muxregs = pcie0_muxreg,
1799 .nmuxregs = ARRAY_SIZE(pcie0_muxreg),
1800 },
1801};
1802
1803static struct spear_pingroup pcie0_pingroup = {
1804 .name = "pcie0_grp",
1805 .pins = pci_sata_pins,
1806 .npins = ARRAY_SIZE(pci_sata_pins),
1807 .modemuxs = pcie0_modemux,
1808 .nmodemuxs = ARRAY_SIZE(pcie0_modemux),
1809};
1810
1811/* pad multiplexing for pcie1 device */
1812static struct spear_muxreg pcie1_muxreg[] = {
1813 PCI_SATA_MUXREG,
1814 {
1815 .reg = PCIE_SATA_CFG,
1816 .mask = PCIE_CFG_VAL(1),
1817 .val = PCIE_CFG_VAL(1),
1818 },
1819};
1820
1821static struct spear_modemux pcie1_modemux[] = {
1822 {
1823 .muxregs = pcie1_muxreg,
1824 .nmuxregs = ARRAY_SIZE(pcie1_muxreg),
1825 },
1826};
1827
1828static struct spear_pingroup pcie1_pingroup = {
1829 .name = "pcie1_grp",
1830 .pins = pci_sata_pins,
1831 .npins = ARRAY_SIZE(pci_sata_pins),
1832 .modemuxs = pcie1_modemux,
1833 .nmodemuxs = ARRAY_SIZE(pcie1_modemux),
1834};
1835
1836/* pad multiplexing for pcie2 device */
1837static struct spear_muxreg pcie2_muxreg[] = {
1838 PCI_SATA_MUXREG,
1839 {
1840 .reg = PCIE_SATA_CFG,
1841 .mask = PCIE_CFG_VAL(2),
1842 .val = PCIE_CFG_VAL(2),
1843 },
1844};
1845
1846static struct spear_modemux pcie2_modemux[] = {
1847 {
1848 .muxregs = pcie2_muxreg,
1849 .nmuxregs = ARRAY_SIZE(pcie2_muxreg),
1850 },
1851};
1852
1853static struct spear_pingroup pcie2_pingroup = {
1854 .name = "pcie2_grp",
1855 .pins = pci_sata_pins,
1856 .npins = ARRAY_SIZE(pci_sata_pins),
1857 .modemuxs = pcie2_modemux,
1858 .nmodemuxs = ARRAY_SIZE(pcie2_modemux),
1859};
1860
1861static const char *const pci_grps[] = { "pcie0_grp", "pcie1_grp", "pcie2_grp" };
1862static struct spear_function pci_function = {
1863 .name = "pci",
1864 .groups = pci_grps,
1865 .ngroups = ARRAY_SIZE(pci_grps),
1866};
1867
1868/* pad multiplexing for sata0 device */
1869static struct spear_muxreg sata0_muxreg[] = {
1870 PCI_SATA_MUXREG,
1871 {
1872 .reg = PCIE_SATA_CFG,
1873 .mask = SATA_CFG_VAL(0),
1874 .val = SATA_CFG_VAL(0),
1875 },
1876};
1877
1878static struct spear_modemux sata0_modemux[] = {
1879 {
1880 .muxregs = sata0_muxreg,
1881 .nmuxregs = ARRAY_SIZE(sata0_muxreg),
1882 },
1883};
1884
1885static struct spear_pingroup sata0_pingroup = {
1886 .name = "sata0_grp",
1887 .pins = pci_sata_pins,
1888 .npins = ARRAY_SIZE(pci_sata_pins),
1889 .modemuxs = sata0_modemux,
1890 .nmodemuxs = ARRAY_SIZE(sata0_modemux),
1891};
1892
1893/* pad multiplexing for sata1 device */
1894static struct spear_muxreg sata1_muxreg[] = {
1895 PCI_SATA_MUXREG,
1896 {
1897 .reg = PCIE_SATA_CFG,
1898 .mask = SATA_CFG_VAL(1),
1899 .val = SATA_CFG_VAL(1),
1900 },
1901};
1902
1903static struct spear_modemux sata1_modemux[] = {
1904 {
1905 .muxregs = sata1_muxreg,
1906 .nmuxregs = ARRAY_SIZE(sata1_muxreg),
1907 },
1908};
1909
1910static struct spear_pingroup sata1_pingroup = {
1911 .name = "sata1_grp",
1912 .pins = pci_sata_pins,
1913 .npins = ARRAY_SIZE(pci_sata_pins),
1914 .modemuxs = sata1_modemux,
1915 .nmodemuxs = ARRAY_SIZE(sata1_modemux),
1916};
1917
1918/* pad multiplexing for sata2 device */
1919static struct spear_muxreg sata2_muxreg[] = {
1920 PCI_SATA_MUXREG,
1921 {
1922 .reg = PCIE_SATA_CFG,
1923 .mask = SATA_CFG_VAL(2),
1924 .val = SATA_CFG_VAL(2),
1925 },
1926};
1927
1928static struct spear_modemux sata2_modemux[] = {
1929 {
1930 .muxregs = sata2_muxreg,
1931 .nmuxregs = ARRAY_SIZE(sata2_muxreg),
1932 },
1933};
1934
1935static struct spear_pingroup sata2_pingroup = {
1936 .name = "sata2_grp",
1937 .pins = pci_sata_pins,
1938 .npins = ARRAY_SIZE(pci_sata_pins),
1939 .modemuxs = sata2_modemux,
1940 .nmodemuxs = ARRAY_SIZE(sata2_modemux),
1941};
1942
1943static const char *const sata_grps[] = { "sata0_grp", "sata1_grp", "sata2_grp"
1944};
1945static struct spear_function sata_function = {
1946 .name = "sata",
1947 .groups = sata_grps,
1948 .ngroups = ARRAY_SIZE(sata_grps),
1949};
1950
1951/* Pad multiplexing for ssp1_dis_kbd device */
1952static const unsigned ssp1_dis_kbd_pins[] = { 203, 204, 205, 206 };
1953static struct spear_muxreg ssp1_dis_kbd_muxreg[] = {
1954 {
1955 .reg = PAD_FUNCTION_EN_1,
1956 .mask = PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK |
1957 PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK |
1958 PMX_NFCE2_MASK,
1959 .val = 0,
1960 },
1961};
1962
1963static struct spear_modemux ssp1_dis_kbd_modemux[] = {
1964 {
1965 .muxregs = ssp1_dis_kbd_muxreg,
1966 .nmuxregs = ARRAY_SIZE(ssp1_dis_kbd_muxreg),
1967 },
1968};
1969
1970static struct spear_pingroup ssp1_dis_kbd_pingroup = {
1971 .name = "ssp1_dis_kbd_grp",
1972 .pins = ssp1_dis_kbd_pins,
1973 .npins = ARRAY_SIZE(ssp1_dis_kbd_pins),
1974 .modemuxs = ssp1_dis_kbd_modemux,
1975 .nmodemuxs = ARRAY_SIZE(ssp1_dis_kbd_modemux),
1976};
1977
1978/* Pad multiplexing for ssp1_dis_sd device */
1979static const unsigned ssp1_dis_sd_pins[] = { 224, 226, 227, 228 };
1980static struct spear_muxreg ssp1_dis_sd_muxreg[] = {
1981 {
1982 .reg = PAD_FUNCTION_EN_2,
1983 .mask = PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK |
1984 PMX_MCICECF_MASK | PMX_MCICEXD_MASK,
1985 .val = 0,
1986 },
1987};
1988
1989static struct spear_modemux ssp1_dis_sd_modemux[] = {
1990 {
1991 .muxregs = ssp1_dis_sd_muxreg,
1992 .nmuxregs = ARRAY_SIZE(ssp1_dis_sd_muxreg),
1993 },
1994};
1995
1996static struct spear_pingroup ssp1_dis_sd_pingroup = {
1997 .name = "ssp1_dis_sd_grp",
1998 .pins = ssp1_dis_sd_pins,
1999 .npins = ARRAY_SIZE(ssp1_dis_sd_pins),
2000 .modemuxs = ssp1_dis_sd_modemux,
2001 .nmodemuxs = ARRAY_SIZE(ssp1_dis_sd_modemux),
2002};
2003
2004static const char *const ssp1_grps[] = { "ssp1_dis_kbd_grp",
2005 "ssp1_dis_sd_grp" };
2006static struct spear_function ssp1_function = {
2007 .name = "ssp1",
2008 .groups = ssp1_grps,
2009 .ngroups = ARRAY_SIZE(ssp1_grps),
2010};
2011
2012/* Pad multiplexing for gpt64 device */
2013static const unsigned gpt64_pins[] = { 230, 231, 232, 245 };
2014static struct spear_muxreg gpt64_muxreg[] = {
2015 {
2016 .reg = PAD_FUNCTION_EN_2,
2017 .mask = PMX_MCICDCF1_MASK | PMX_MCICDCF2_MASK | PMX_MCICDXD_MASK
2018 | PMX_MCILEDS_MASK,
2019 .val = 0,
2020 },
2021};
2022
2023static struct spear_modemux gpt64_modemux[] = {
2024 {
2025 .muxregs = gpt64_muxreg,
2026 .nmuxregs = ARRAY_SIZE(gpt64_muxreg),
2027 },
2028};
2029
2030static struct spear_pingroup gpt64_pingroup = {
2031 .name = "gpt64_grp",
2032 .pins = gpt64_pins,
2033 .npins = ARRAY_SIZE(gpt64_pins),
2034 .modemuxs = gpt64_modemux,
2035 .nmodemuxs = ARRAY_SIZE(gpt64_modemux),
2036};
2037
2038static const char *const gpt64_grps[] = { "gpt64_grp" };
2039static struct spear_function gpt64_function = {
2040 .name = "gpt64",
2041 .groups = gpt64_grps,
2042 .ngroups = ARRAY_SIZE(gpt64_grps),
2043};
2044
2045/* pingroups */
2046static struct spear_pingroup *spear1310_pingroups[] = {
2047 &i2c0_pingroup,
2048 &ssp0_pingroup,
2049 &i2s0_pingroup,
2050 &i2s1_pingroup,
2051 &clcd_pingroup,
2052 &clcd_high_res_pingroup,
2053 &arm_gpio_pingroup,
2054 &smi_2_chips_pingroup,
2055 &smi_4_chips_pingroup,
2056 &gmii_pingroup,
2057 &rgmii_pingroup,
2058 &smii_0_1_2_pingroup,
2059 &ras_mii_txclk_pingroup,
2060 &nand_8bit_pingroup,
2061 &nand_16bit_pingroup,
2062 &nand_4_chips_pingroup,
2063 &keyboard_6x6_pingroup,
2064 &keyboard_rowcol6_8_pingroup,
2065 &uart0_pingroup,
2066 &uart0_modem_pingroup,
2067 &gpt0_tmr0_pingroup,
2068 &gpt0_tmr1_pingroup,
2069 &gpt1_tmr0_pingroup,
2070 &gpt1_tmr1_pingroup,
2071 &sdhci_pingroup,
2072 &cf_pingroup,
2073 &xd_pingroup,
2074 &touch_xy_pingroup,
2075 &ssp0_cs0_pingroup,
2076 &ssp0_cs1_2_pingroup,
2077 &uart_1_dis_i2c_pingroup,
2078 &uart_1_dis_sd_pingroup,
2079 &uart_2_3_pingroup,
2080 &uart_4_pingroup,
2081 &uart_5_pingroup,
2082 &rs485_0_1_tdm_0_1_pingroup,
2083 &i2c_1_2_pingroup,
2084 &i2c3_dis_smi_clcd_pingroup,
2085 &i2c3_dis_sd_i2s0_pingroup,
2086 &i2c_4_5_dis_smi_pingroup,
2087 &i2c4_dis_sd_pingroup,
2088 &i2c5_dis_sd_pingroup,
2089 &i2c_6_7_dis_kbd_pingroup,
2090 &i2c6_dis_sd_pingroup,
2091 &i2c7_dis_sd_pingroup,
2092 &can0_dis_nor_pingroup,
2093 &can0_dis_sd_pingroup,
2094 &can1_dis_sd_pingroup,
2095 &can1_dis_kbd_pingroup,
2096 &pcie0_pingroup,
2097 &pcie1_pingroup,
2098 &pcie2_pingroup,
2099 &sata0_pingroup,
2100 &sata1_pingroup,
2101 &sata2_pingroup,
2102 &ssp1_dis_kbd_pingroup,
2103 &ssp1_dis_sd_pingroup,
2104 &gpt64_pingroup,
2105};
2106
2107/* functions */
2108static struct spear_function *spear1310_functions[] = {
2109 &i2c0_function,
2110 &ssp0_function,
2111 &i2s0_function,
2112 &i2s1_function,
2113 &clcd_function,
2114 &arm_gpio_function,
2115 &smi_function,
2116 &gmii_function,
2117 &rgmii_function,
2118 &smii_0_1_2_function,
2119 &ras_mii_txclk_function,
2120 &nand_function,
2121 &keyboard_function,
2122 &uart0_function,
2123 &gpt0_function,
2124 &gpt1_function,
2125 &sdhci_function,
2126 &cf_function,
2127 &xd_function,
2128 &touch_xy_function,
2129 &uart1_function,
2130 &uart2_3_function,
2131 &uart4_function,
2132 &uart5_function,
2133 &rs485_0_1_tdm_0_1_function,
2134 &i2c_1_2_function,
2135 &i2c3_unction,
2136 &i2c_4_5_function,
2137 &i2c_6_7_function,
2138 &can0_function,
2139 &can1_function,
2140 &pci_function,
2141 &sata_function,
2142 &ssp1_function,
2143 &gpt64_function,
2144};
2145
2146static struct spear_pinctrl_machdata spear1310_machdata = {
2147 .pins = spear1310_pins,
2148 .npins = ARRAY_SIZE(spear1310_pins),
2149 .groups = spear1310_pingroups,
2150 .ngroups = ARRAY_SIZE(spear1310_pingroups),
2151 .functions = spear1310_functions,
2152 .nfunctions = ARRAY_SIZE(spear1310_functions),
2153 .modes_supported = false,
2154};
2155
2156static struct of_device_id spear1310_pinctrl_of_match[] __devinitdata = {
2157 {
2158 .compatible = "st,spear1310-pinmux",
2159 },
2160 {},
2161};
2162
2163static int __devinit spear1310_pinctrl_probe(struct platform_device *pdev)
2164{
2165 return spear_pinctrl_probe(pdev, &spear1310_machdata);
2166}
2167
2168static int __devexit spear1310_pinctrl_remove(struct platform_device *pdev)
2169{
2170 return spear_pinctrl_remove(pdev);
2171}
2172
2173static struct platform_driver spear1310_pinctrl_driver = {
2174 .driver = {
2175 .name = DRIVER_NAME,
2176 .owner = THIS_MODULE,
2177 .of_match_table = spear1310_pinctrl_of_match,
2178 },
2179 .probe = spear1310_pinctrl_probe,
2180 .remove = __devexit_p(spear1310_pinctrl_remove),
2181};
2182
2183static int __init spear1310_pinctrl_init(void)
2184{
2185 return platform_driver_register(&spear1310_pinctrl_driver);
2186}
2187arch_initcall(spear1310_pinctrl_init);
2188
2189static void __exit spear1310_pinctrl_exit(void)
2190{
2191 platform_driver_unregister(&spear1310_pinctrl_driver);
2192}
2193module_exit(spear1310_pinctrl_exit);
2194
2195MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>");
2196MODULE_DESCRIPTION("ST Microelectronics SPEAr1310 pinctrl driver");
2197MODULE_LICENSE("GPL v2");
2198MODULE_DEVICE_TABLE(of, spear1310_pinctrl_of_match);
diff --git a/drivers/pinctrl/spear/pinctrl-spear1340.c b/drivers/pinctrl/spear/pinctrl-spear1340.c
new file mode 100644
index 000000000000..a8ab2a6f51bf
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear1340.c
@@ -0,0 +1,1989 @@
1/*
2 * Driver for the ST Microelectronics SPEAr1340 pinmux
3 *
4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.kumar@st.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/err.h>
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/of_device.h>
16#include <linux/platform_device.h>
17#include "pinctrl-spear.h"
18
19#define DRIVER_NAME "spear1340-pinmux"
20
21/* pins */
22static const struct pinctrl_pin_desc spear1340_pins[] = {
23 SPEAR_PIN_0_TO_101,
24 SPEAR_PIN_102_TO_245,
25 PINCTRL_PIN(246, "PLGPIO246"),
26 PINCTRL_PIN(247, "PLGPIO247"),
27 PINCTRL_PIN(248, "PLGPIO248"),
28 PINCTRL_PIN(249, "PLGPIO249"),
29 PINCTRL_PIN(250, "PLGPIO250"),
30 PINCTRL_PIN(251, "PLGPIO251"),
31};
32
33/* In SPEAr1340 there are two levels of pad muxing */
34/* - pads as gpio OR peripherals */
35#define PAD_FUNCTION_EN_1 0x668
36#define PAD_FUNCTION_EN_2 0x66C
37#define PAD_FUNCTION_EN_3 0x670
38#define PAD_FUNCTION_EN_4 0x674
39#define PAD_FUNCTION_EN_5 0x690
40#define PAD_FUNCTION_EN_6 0x694
41#define PAD_FUNCTION_EN_7 0x698
42#define PAD_FUNCTION_EN_8 0x69C
43
44/* - If peripherals, then primary OR alternate peripheral */
45#define PAD_SHARED_IP_EN_1 0x6A0
46#define PAD_SHARED_IP_EN_2 0x6A4
47
48/*
49 * Macro's for first level of pmx - pads as gpio OR peripherals. There are 8
50 * registers with 32 bits each for handling gpio pads, register 8 has only 26
51 * relevant bits.
52 */
53/* macro's for making pads as gpio's */
54#define PADS_AS_GPIO_REG0_MASK 0xFFFFFFFE
55#define PADS_AS_GPIO_REGS_MASK 0xFFFFFFFF
56#define PADS_AS_GPIO_REG7_MASK 0x07FFFFFF
57
58/* macro's for making pads as peripherals */
59#define FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK 0x00000FFE
60#define UART0_ENH_AND_GPT_REG0_MASK 0x0003F000
61#define PWM1_AND_KBD_COL5_REG0_MASK 0x00040000
62#define I2C1_REG0_MASK 0x01080000
63#define SPDIF_IN_REG0_MASK 0x00100000
64#define PWM2_AND_GPT0_TMR0_CPT_REG0_MASK 0x00400000
65#define PWM3_AND_GPT0_TMR1_CLK_REG0_MASK 0x00800000
66#define PWM0_AND_SSP0_CS1_REG0_MASK 0x02000000
67#define VIP_AND_CAM3_REG0_MASK 0xFC200000
68#define VIP_AND_CAM3_REG1_MASK 0x0000000F
69#define VIP_REG1_MASK 0x00001EF0
70#define VIP_AND_CAM2_REG1_MASK 0x007FE100
71#define VIP_AND_CAM1_REG1_MASK 0xFF800000
72#define VIP_AND_CAM1_REG2_MASK 0x00000003
73#define VIP_AND_CAM0_REG2_MASK 0x00001FFC
74#define SMI_REG2_MASK 0x0021E000
75#define SSP0_REG2_MASK 0x001E0000
76#define TS_AND_SSP0_CS2_REG2_MASK 0x00400000
77#define UART0_REG2_MASK 0x01800000
78#define UART1_REG2_MASK 0x06000000
79#define I2S_IN_REG2_MASK 0xF8000000
80#define DEVS_GRP_AND_MIPHY_DBG_REG3_MASK 0x000001FE
81#define I2S_OUT_REG3_MASK 0x000001EF
82#define I2S_IN_REG3_MASK 0x00000010
83#define GMAC_REG3_MASK 0xFFFFFE00
84#define GMAC_REG4_MASK 0x0000001F
85#define DEVS_GRP_AND_MIPHY_DBG_REG4_MASK 0x7FFFFF20
86#define SSP0_CS3_REG4_MASK 0x00000020
87#define I2C0_REG4_MASK 0x000000C0
88#define CEC0_REG4_MASK 0x00000100
89#define CEC1_REG4_MASK 0x00000200
90#define SPDIF_OUT_REG4_MASK 0x00000400
91#define CLCD_REG4_MASK 0x7FFFF800
92#define CLCD_AND_ARM_TRACE_REG4_MASK 0x80000000
93#define CLCD_AND_ARM_TRACE_REG5_MASK 0xFFFFFFFF
94#define CLCD_AND_ARM_TRACE_REG6_MASK 0x00000001
95#define FSMC_PNOR_AND_MCIF_REG6_MASK 0x073FFFFE
96#define MCIF_REG6_MASK 0xF8C00000
97#define MCIF_REG7_MASK 0x000043FF
98#define FSMC_8BIT_REG7_MASK 0x07FFBC00
99
100/* other registers */
101#define PERIP_CFG 0x42C
102 /* PERIP_CFG register masks */
103 #define SSP_CS_CTL_HW 0
104 #define SSP_CS_CTL_SW 1
105 #define SSP_CS_CTL_MASK 1
106 #define SSP_CS_CTL_SHIFT 21
107 #define SSP_CS_VAL_MASK 1
108 #define SSP_CS_VAL_SHIFT 20
109 #define SSP_CS_SEL_CS0 0
110 #define SSP_CS_SEL_CS1 1
111 #define SSP_CS_SEL_CS2 2
112 #define SSP_CS_SEL_MASK 3
113 #define SSP_CS_SEL_SHIFT 18
114
115 #define I2S_CHNL_2_0 (0)
116 #define I2S_CHNL_3_1 (1)
117 #define I2S_CHNL_5_1 (2)
118 #define I2S_CHNL_7_1 (3)
119 #define I2S_CHNL_PLAY_SHIFT (4)
120 #define I2S_CHNL_PLAY_MASK (3 << 4)
121 #define I2S_CHNL_REC_SHIFT (6)
122 #define I2S_CHNL_REC_MASK (3 << 6)
123
124 #define SPDIF_OUT_ENB_MASK (1 << 2)
125 #define SPDIF_OUT_ENB_SHIFT 2
126
127 #define MCIF_SEL_SD 1
128 #define MCIF_SEL_CF 2
129 #define MCIF_SEL_XD 3
130 #define MCIF_SEL_MASK 3
131 #define MCIF_SEL_SHIFT 0
132
133#define GMAC_CLK_CFG 0x248
134 #define GMAC_PHY_IF_GMII_VAL (0 << 3)
135 #define GMAC_PHY_IF_RGMII_VAL (1 << 3)
136 #define GMAC_PHY_IF_SGMII_VAL (2 << 3)
137 #define GMAC_PHY_IF_RMII_VAL (4 << 3)
138 #define GMAC_PHY_IF_SEL_MASK (7 << 3)
139 #define GMAC_PHY_INPUT_ENB_VAL 0
140 #define GMAC_PHY_SYNT_ENB_VAL 1
141 #define GMAC_PHY_CLK_MASK 1
142 #define GMAC_PHY_CLK_SHIFT 2
143 #define GMAC_PHY_125M_PAD_VAL 0
144 #define GMAC_PHY_PLL2_VAL 1
145 #define GMAC_PHY_OSC3_VAL 2
146 #define GMAC_PHY_INPUT_CLK_MASK 3
147 #define GMAC_PHY_INPUT_CLK_SHIFT 0
148
149#define PCIE_SATA_CFG 0x424
150 /* PCIE CFG MASks */
151 #define PCIE_CFG_DEVICE_PRESENT (1 << 11)
152 #define PCIE_CFG_POWERUP_RESET (1 << 10)
153 #define PCIE_CFG_CORE_CLK_EN (1 << 9)
154 #define PCIE_CFG_AUX_CLK_EN (1 << 8)
155 #define SATA_CFG_TX_CLK_EN (1 << 4)
156 #define SATA_CFG_RX_CLK_EN (1 << 3)
157 #define SATA_CFG_POWERUP_RESET (1 << 2)
158 #define SATA_CFG_PM_CLK_EN (1 << 1)
159 #define PCIE_SATA_SEL_PCIE (0)
160 #define PCIE_SATA_SEL_SATA (1)
161 #define SATA_PCIE_CFG_MASK 0xF1F
162 #define PCIE_CFG_VAL (PCIE_SATA_SEL_PCIE | PCIE_CFG_AUX_CLK_EN | \
163 PCIE_CFG_CORE_CLK_EN | PCIE_CFG_POWERUP_RESET |\
164 PCIE_CFG_DEVICE_PRESENT)
165 #define SATA_CFG_VAL (PCIE_SATA_SEL_SATA | SATA_CFG_PM_CLK_EN | \
166 SATA_CFG_POWERUP_RESET | SATA_CFG_RX_CLK_EN | \
167 SATA_CFG_TX_CLK_EN)
168
169/* Macro's for second level of pmx - pads as primary OR alternate peripheral */
170/* Write 0 to enable FSMC_16_BIT */
171#define KBD_ROW_COL_MASK (1 << 0)
172
173/* Write 0 to enable UART0_ENH */
174#define GPT_MASK (1 << 1) /* Only clk & cpt */
175
176/* Write 0 to enable PWM1 */
177#define KBD_COL5_MASK (1 << 2)
178
179/* Write 0 to enable PWM2 */
180#define GPT0_TMR0_CPT_MASK (1 << 3) /* Only clk & cpt */
181
182/* Write 0 to enable PWM3 */
183#define GPT0_TMR1_CLK_MASK (1 << 4) /* Only clk & cpt */
184
185/* Write 0 to enable PWM0 */
186#define SSP0_CS1_MASK (1 << 5)
187
188/* Write 0 to enable VIP */
189#define CAM3_MASK (1 << 6)
190
191/* Write 0 to enable VIP */
192#define CAM2_MASK (1 << 7)
193
194/* Write 0 to enable VIP */
195#define CAM1_MASK (1 << 8)
196
197/* Write 0 to enable VIP */
198#define CAM0_MASK (1 << 9)
199
200/* Write 0 to enable TS */
201#define SSP0_CS2_MASK (1 << 10)
202
203/* Write 0 to enable FSMC PNOR */
204#define MCIF_MASK (1 << 11)
205
206/* Write 0 to enable CLCD */
207#define ARM_TRACE_MASK (1 << 12)
208
209/* Write 0 to enable I2S, SSP0_CS2, CEC0, 1, SPDIF out, CLCD */
210#define MIPHY_DBG_MASK (1 << 13)
211
212/*
213 * Pad multiplexing for making all pads as gpio's. This is done to override the
214 * values passed from bootloader and start from scratch.
215 */
216static const unsigned pads_as_gpio_pins[] = { 251 };
217static struct spear_muxreg pads_as_gpio_muxreg[] = {
218 {
219 .reg = PAD_FUNCTION_EN_1,
220 .mask = PADS_AS_GPIO_REG0_MASK,
221 .val = 0x0,
222 }, {
223 .reg = PAD_FUNCTION_EN_2,
224 .mask = PADS_AS_GPIO_REGS_MASK,
225 .val = 0x0,
226 }, {
227 .reg = PAD_FUNCTION_EN_3,
228 .mask = PADS_AS_GPIO_REGS_MASK,
229 .val = 0x0,
230 }, {
231 .reg = PAD_FUNCTION_EN_4,
232 .mask = PADS_AS_GPIO_REGS_MASK,
233 .val = 0x0,
234 }, {
235 .reg = PAD_FUNCTION_EN_5,
236 .mask = PADS_AS_GPIO_REGS_MASK,
237 .val = 0x0,
238 }, {
239 .reg = PAD_FUNCTION_EN_6,
240 .mask = PADS_AS_GPIO_REGS_MASK,
241 .val = 0x0,
242 }, {
243 .reg = PAD_FUNCTION_EN_7,
244 .mask = PADS_AS_GPIO_REGS_MASK,
245 .val = 0x0,
246 }, {
247 .reg = PAD_FUNCTION_EN_8,
248 .mask = PADS_AS_GPIO_REG7_MASK,
249 .val = 0x0,
250 },
251};
252
253static struct spear_modemux pads_as_gpio_modemux[] = {
254 {
255 .muxregs = pads_as_gpio_muxreg,
256 .nmuxregs = ARRAY_SIZE(pads_as_gpio_muxreg),
257 },
258};
259
260static struct spear_pingroup pads_as_gpio_pingroup = {
261 .name = "pads_as_gpio_grp",
262 .pins = pads_as_gpio_pins,
263 .npins = ARRAY_SIZE(pads_as_gpio_pins),
264 .modemuxs = pads_as_gpio_modemux,
265 .nmodemuxs = ARRAY_SIZE(pads_as_gpio_modemux),
266};
267
268static const char *const pads_as_gpio_grps[] = { "pads_as_gpio_grp" };
269static struct spear_function pads_as_gpio_function = {
270 .name = "pads_as_gpio",
271 .groups = pads_as_gpio_grps,
272 .ngroups = ARRAY_SIZE(pads_as_gpio_grps),
273};
274
275/* Pad multiplexing for fsmc_8bit device */
276static const unsigned fsmc_8bit_pins[] = { 233, 234, 235, 236, 238, 239, 240,
277 241, 242, 243, 244, 245, 246, 247, 248, 249 };
278static struct spear_muxreg fsmc_8bit_muxreg[] = {
279 {
280 .reg = PAD_FUNCTION_EN_8,
281 .mask = FSMC_8BIT_REG7_MASK,
282 .val = FSMC_8BIT_REG7_MASK,
283 }
284};
285
286static struct spear_modemux fsmc_8bit_modemux[] = {
287 {
288 .muxregs = fsmc_8bit_muxreg,
289 .nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg),
290 },
291};
292
293static struct spear_pingroup fsmc_8bit_pingroup = {
294 .name = "fsmc_8bit_grp",
295 .pins = fsmc_8bit_pins,
296 .npins = ARRAY_SIZE(fsmc_8bit_pins),
297 .modemuxs = fsmc_8bit_modemux,
298 .nmodemuxs = ARRAY_SIZE(fsmc_8bit_modemux),
299};
300
301/* Pad multiplexing for fsmc_16bit device */
302static const unsigned fsmc_16bit_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 };
303static struct spear_muxreg fsmc_16bit_muxreg[] = {
304 {
305 .reg = PAD_SHARED_IP_EN_1,
306 .mask = KBD_ROW_COL_MASK,
307 .val = 0,
308 }, {
309 .reg = PAD_FUNCTION_EN_1,
310 .mask = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK,
311 .val = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK,
312 },
313};
314
315static struct spear_modemux fsmc_16bit_modemux[] = {
316 {
317 .muxregs = fsmc_16bit_muxreg,
318 .nmuxregs = ARRAY_SIZE(fsmc_16bit_muxreg),
319 },
320};
321
322static struct spear_pingroup fsmc_16bit_pingroup = {
323 .name = "fsmc_16bit_grp",
324 .pins = fsmc_16bit_pins,
325 .npins = ARRAY_SIZE(fsmc_16bit_pins),
326 .modemuxs = fsmc_16bit_modemux,
327 .nmodemuxs = ARRAY_SIZE(fsmc_16bit_modemux),
328};
329
330/* pad multiplexing for fsmc_pnor device */
331static const unsigned fsmc_pnor_pins[] = { 192, 193, 194, 195, 196, 197, 198,
332 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212,
333 215, 216, 217 };
334static struct spear_muxreg fsmc_pnor_muxreg[] = {
335 {
336 .reg = PAD_SHARED_IP_EN_1,
337 .mask = MCIF_MASK,
338 .val = 0,
339 }, {
340 .reg = PAD_FUNCTION_EN_7,
341 .mask = FSMC_PNOR_AND_MCIF_REG6_MASK,
342 .val = FSMC_PNOR_AND_MCIF_REG6_MASK,
343 },
344};
345
346static struct spear_modemux fsmc_pnor_modemux[] = {
347 {
348 .muxregs = fsmc_pnor_muxreg,
349 .nmuxregs = ARRAY_SIZE(fsmc_pnor_muxreg),
350 },
351};
352
353static struct spear_pingroup fsmc_pnor_pingroup = {
354 .name = "fsmc_pnor_grp",
355 .pins = fsmc_pnor_pins,
356 .npins = ARRAY_SIZE(fsmc_pnor_pins),
357 .modemuxs = fsmc_pnor_modemux,
358 .nmodemuxs = ARRAY_SIZE(fsmc_pnor_modemux),
359};
360
361static const char *const fsmc_grps[] = { "fsmc_8bit_grp", "fsmc_16bit_grp",
362 "fsmc_pnor_grp" };
363static struct spear_function fsmc_function = {
364 .name = "fsmc",
365 .groups = fsmc_grps,
366 .ngroups = ARRAY_SIZE(fsmc_grps),
367};
368
369/* pad multiplexing for keyboard rows-cols device */
370static const unsigned keyboard_row_col_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
371 10 };
372static struct spear_muxreg keyboard_row_col_muxreg[] = {
373 {
374 .reg = PAD_SHARED_IP_EN_1,
375 .mask = KBD_ROW_COL_MASK,
376 .val = KBD_ROW_COL_MASK,
377 }, {
378 .reg = PAD_FUNCTION_EN_1,
379 .mask = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK,
380 .val = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK,
381 },
382};
383
384static struct spear_modemux keyboard_row_col_modemux[] = {
385 {
386 .muxregs = keyboard_row_col_muxreg,
387 .nmuxregs = ARRAY_SIZE(keyboard_row_col_muxreg),
388 },
389};
390
391static struct spear_pingroup keyboard_row_col_pingroup = {
392 .name = "keyboard_row_col_grp",
393 .pins = keyboard_row_col_pins,
394 .npins = ARRAY_SIZE(keyboard_row_col_pins),
395 .modemuxs = keyboard_row_col_modemux,
396 .nmodemuxs = ARRAY_SIZE(keyboard_row_col_modemux),
397};
398
399/* pad multiplexing for keyboard col5 device */
400static const unsigned keyboard_col5_pins[] = { 17 };
401static struct spear_muxreg keyboard_col5_muxreg[] = {
402 {
403 .reg = PAD_SHARED_IP_EN_1,
404 .mask = KBD_COL5_MASK,
405 .val = KBD_COL5_MASK,
406 }, {
407 .reg = PAD_FUNCTION_EN_1,
408 .mask = PWM1_AND_KBD_COL5_REG0_MASK,
409 .val = PWM1_AND_KBD_COL5_REG0_MASK,
410 },
411};
412
413static struct spear_modemux keyboard_col5_modemux[] = {
414 {
415 .muxregs = keyboard_col5_muxreg,
416 .nmuxregs = ARRAY_SIZE(keyboard_col5_muxreg),
417 },
418};
419
420static struct spear_pingroup keyboard_col5_pingroup = {
421 .name = "keyboard_col5_grp",
422 .pins = keyboard_col5_pins,
423 .npins = ARRAY_SIZE(keyboard_col5_pins),
424 .modemuxs = keyboard_col5_modemux,
425 .nmodemuxs = ARRAY_SIZE(keyboard_col5_modemux),
426};
427
428static const char *const keyboard_grps[] = { "keyboard_row_col_grp",
429 "keyboard_col5_grp" };
430static struct spear_function keyboard_function = {
431 .name = "keyboard",
432 .groups = keyboard_grps,
433 .ngroups = ARRAY_SIZE(keyboard_grps),
434};
435
436/* pad multiplexing for spdif_in device */
437static const unsigned spdif_in_pins[] = { 19 };
438static struct spear_muxreg spdif_in_muxreg[] = {
439 {
440 .reg = PAD_FUNCTION_EN_1,
441 .mask = SPDIF_IN_REG0_MASK,
442 .val = SPDIF_IN_REG0_MASK,
443 },
444};
445
446static struct spear_modemux spdif_in_modemux[] = {
447 {
448 .muxregs = spdif_in_muxreg,
449 .nmuxregs = ARRAY_SIZE(spdif_in_muxreg),
450 },
451};
452
453static struct spear_pingroup spdif_in_pingroup = {
454 .name = "spdif_in_grp",
455 .pins = spdif_in_pins,
456 .npins = ARRAY_SIZE(spdif_in_pins),
457 .modemuxs = spdif_in_modemux,
458 .nmodemuxs = ARRAY_SIZE(spdif_in_modemux),
459};
460
461static const char *const spdif_in_grps[] = { "spdif_in_grp" };
462static struct spear_function spdif_in_function = {
463 .name = "spdif_in",
464 .groups = spdif_in_grps,
465 .ngroups = ARRAY_SIZE(spdif_in_grps),
466};
467
468/* pad multiplexing for spdif_out device */
469static const unsigned spdif_out_pins[] = { 137 };
470static struct spear_muxreg spdif_out_muxreg[] = {
471 {
472 .reg = PAD_FUNCTION_EN_5,
473 .mask = SPDIF_OUT_REG4_MASK,
474 .val = SPDIF_OUT_REG4_MASK,
475 }, {
476 .reg = PERIP_CFG,
477 .mask = SPDIF_OUT_ENB_MASK,
478 .val = SPDIF_OUT_ENB_MASK,
479 }
480};
481
482static struct spear_modemux spdif_out_modemux[] = {
483 {
484 .muxregs = spdif_out_muxreg,
485 .nmuxregs = ARRAY_SIZE(spdif_out_muxreg),
486 },
487};
488
489static struct spear_pingroup spdif_out_pingroup = {
490 .name = "spdif_out_grp",
491 .pins = spdif_out_pins,
492 .npins = ARRAY_SIZE(spdif_out_pins),
493 .modemuxs = spdif_out_modemux,
494 .nmodemuxs = ARRAY_SIZE(spdif_out_modemux),
495};
496
497static const char *const spdif_out_grps[] = { "spdif_out_grp" };
498static struct spear_function spdif_out_function = {
499 .name = "spdif_out",
500 .groups = spdif_out_grps,
501 .ngroups = ARRAY_SIZE(spdif_out_grps),
502};
503
504/* pad multiplexing for gpt_0_1 device */
505static const unsigned gpt_0_1_pins[] = { 11, 12, 13, 14, 15, 16, 21, 22 };
506static struct spear_muxreg gpt_0_1_muxreg[] = {
507 {
508 .reg = PAD_SHARED_IP_EN_1,
509 .mask = GPT_MASK | GPT0_TMR0_CPT_MASK | GPT0_TMR1_CLK_MASK,
510 .val = GPT_MASK | GPT0_TMR0_CPT_MASK | GPT0_TMR1_CLK_MASK,
511 }, {
512 .reg = PAD_FUNCTION_EN_1,
513 .mask = UART0_ENH_AND_GPT_REG0_MASK |
514 PWM2_AND_GPT0_TMR0_CPT_REG0_MASK |
515 PWM3_AND_GPT0_TMR1_CLK_REG0_MASK,
516 .val = UART0_ENH_AND_GPT_REG0_MASK |
517 PWM2_AND_GPT0_TMR0_CPT_REG0_MASK |
518 PWM3_AND_GPT0_TMR1_CLK_REG0_MASK,
519 },
520};
521
522static struct spear_modemux gpt_0_1_modemux[] = {
523 {
524 .muxregs = gpt_0_1_muxreg,
525 .nmuxregs = ARRAY_SIZE(gpt_0_1_muxreg),
526 },
527};
528
529static struct spear_pingroup gpt_0_1_pingroup = {
530 .name = "gpt_0_1_grp",
531 .pins = gpt_0_1_pins,
532 .npins = ARRAY_SIZE(gpt_0_1_pins),
533 .modemuxs = gpt_0_1_modemux,
534 .nmodemuxs = ARRAY_SIZE(gpt_0_1_modemux),
535};
536
537static const char *const gpt_0_1_grps[] = { "gpt_0_1_grp" };
538static struct spear_function gpt_0_1_function = {
539 .name = "gpt_0_1",
540 .groups = gpt_0_1_grps,
541 .ngroups = ARRAY_SIZE(gpt_0_1_grps),
542};
543
544/* pad multiplexing for pwm0 device */
545static const unsigned pwm0_pins[] = { 24 };
546static struct spear_muxreg pwm0_muxreg[] = {
547 {
548 .reg = PAD_SHARED_IP_EN_1,
549 .mask = SSP0_CS1_MASK,
550 .val = 0,
551 }, {
552 .reg = PAD_FUNCTION_EN_1,
553 .mask = PWM0_AND_SSP0_CS1_REG0_MASK,
554 .val = PWM0_AND_SSP0_CS1_REG0_MASK,
555 },
556};
557
558static struct spear_modemux pwm0_modemux[] = {
559 {
560 .muxregs = pwm0_muxreg,
561 .nmuxregs = ARRAY_SIZE(pwm0_muxreg),
562 },
563};
564
565static struct spear_pingroup pwm0_pingroup = {
566 .name = "pwm0_grp",
567 .pins = pwm0_pins,
568 .npins = ARRAY_SIZE(pwm0_pins),
569 .modemuxs = pwm0_modemux,
570 .nmodemuxs = ARRAY_SIZE(pwm0_modemux),
571};
572
573/* pad multiplexing for pwm1 device */
574static const unsigned pwm1_pins[] = { 17 };
575static struct spear_muxreg pwm1_muxreg[] = {
576 {
577 .reg = PAD_SHARED_IP_EN_1,
578 .mask = KBD_COL5_MASK,
579 .val = 0,
580 }, {
581 .reg = PAD_FUNCTION_EN_1,
582 .mask = PWM1_AND_KBD_COL5_REG0_MASK,
583 .val = PWM1_AND_KBD_COL5_REG0_MASK,
584 },
585};
586
587static struct spear_modemux pwm1_modemux[] = {
588 {
589 .muxregs = pwm1_muxreg,
590 .nmuxregs = ARRAY_SIZE(pwm1_muxreg),
591 },
592};
593
594static struct spear_pingroup pwm1_pingroup = {
595 .name = "pwm1_grp",
596 .pins = pwm1_pins,
597 .npins = ARRAY_SIZE(pwm1_pins),
598 .modemuxs = pwm1_modemux,
599 .nmodemuxs = ARRAY_SIZE(pwm1_modemux),
600};
601
602/* pad multiplexing for pwm2 device */
603static const unsigned pwm2_pins[] = { 21 };
604static struct spear_muxreg pwm2_muxreg[] = {
605 {
606 .reg = PAD_SHARED_IP_EN_1,
607 .mask = GPT0_TMR0_CPT_MASK,
608 .val = 0,
609 }, {
610 .reg = PAD_FUNCTION_EN_1,
611 .mask = PWM2_AND_GPT0_TMR0_CPT_REG0_MASK,
612 .val = PWM2_AND_GPT0_TMR0_CPT_REG0_MASK,
613 },
614};
615
616static struct spear_modemux pwm2_modemux[] = {
617 {
618 .muxregs = pwm2_muxreg,
619 .nmuxregs = ARRAY_SIZE(pwm2_muxreg),
620 },
621};
622
623static struct spear_pingroup pwm2_pingroup = {
624 .name = "pwm2_grp",
625 .pins = pwm2_pins,
626 .npins = ARRAY_SIZE(pwm2_pins),
627 .modemuxs = pwm2_modemux,
628 .nmodemuxs = ARRAY_SIZE(pwm2_modemux),
629};
630
631/* pad multiplexing for pwm3 device */
632static const unsigned pwm3_pins[] = { 22 };
633static struct spear_muxreg pwm3_muxreg[] = {
634 {
635 .reg = PAD_SHARED_IP_EN_1,
636 .mask = GPT0_TMR1_CLK_MASK,
637 .val = 0,
638 }, {
639 .reg = PAD_FUNCTION_EN_1,
640 .mask = PWM3_AND_GPT0_TMR1_CLK_REG0_MASK,
641 .val = PWM3_AND_GPT0_TMR1_CLK_REG0_MASK,
642 },
643};
644
645static struct spear_modemux pwm3_modemux[] = {
646 {
647 .muxregs = pwm3_muxreg,
648 .nmuxregs = ARRAY_SIZE(pwm3_muxreg),
649 },
650};
651
652static struct spear_pingroup pwm3_pingroup = {
653 .name = "pwm3_grp",
654 .pins = pwm3_pins,
655 .npins = ARRAY_SIZE(pwm3_pins),
656 .modemuxs = pwm3_modemux,
657 .nmodemuxs = ARRAY_SIZE(pwm3_modemux),
658};
659
660static const char *const pwm_grps[] = { "pwm0_grp", "pwm1_grp", "pwm2_grp",
661 "pwm3_grp" };
662static struct spear_function pwm_function = {
663 .name = "pwm",
664 .groups = pwm_grps,
665 .ngroups = ARRAY_SIZE(pwm_grps),
666};
667
668/* pad multiplexing for vip_mux device */
669static const unsigned vip_mux_pins[] = { 35, 36, 37, 38, 40, 41, 42, 43 };
670static struct spear_muxreg vip_mux_muxreg[] = {
671 {
672 .reg = PAD_FUNCTION_EN_2,
673 .mask = VIP_REG1_MASK,
674 .val = VIP_REG1_MASK,
675 },
676};
677
678static struct spear_modemux vip_mux_modemux[] = {
679 {
680 .muxregs = vip_mux_muxreg,
681 .nmuxregs = ARRAY_SIZE(vip_mux_muxreg),
682 },
683};
684
685static struct spear_pingroup vip_mux_pingroup = {
686 .name = "vip_mux_grp",
687 .pins = vip_mux_pins,
688 .npins = ARRAY_SIZE(vip_mux_pins),
689 .modemuxs = vip_mux_modemux,
690 .nmodemuxs = ARRAY_SIZE(vip_mux_modemux),
691};
692
693/* pad multiplexing for vip_mux_cam0 (disables cam0) device */
694static const unsigned vip_mux_cam0_pins[] = { 65, 66, 67, 68, 69, 70, 71, 72,
695 73, 74, 75 };
696static struct spear_muxreg vip_mux_cam0_muxreg[] = {
697 {
698 .reg = PAD_SHARED_IP_EN_1,
699 .mask = CAM0_MASK,
700 .val = 0,
701 }, {
702 .reg = PAD_FUNCTION_EN_3,
703 .mask = VIP_AND_CAM0_REG2_MASK,
704 .val = VIP_AND_CAM0_REG2_MASK,
705 },
706};
707
708static struct spear_modemux vip_mux_cam0_modemux[] = {
709 {
710 .muxregs = vip_mux_cam0_muxreg,
711 .nmuxregs = ARRAY_SIZE(vip_mux_cam0_muxreg),
712 },
713};
714
715static struct spear_pingroup vip_mux_cam0_pingroup = {
716 .name = "vip_mux_cam0_grp",
717 .pins = vip_mux_cam0_pins,
718 .npins = ARRAY_SIZE(vip_mux_cam0_pins),
719 .modemuxs = vip_mux_cam0_modemux,
720 .nmodemuxs = ARRAY_SIZE(vip_mux_cam0_modemux),
721};
722
723/* pad multiplexing for vip_mux_cam1 (disables cam1) device */
724static const unsigned vip_mux_cam1_pins[] = { 54, 55, 56, 57, 58, 59, 60, 61,
725 62, 63, 64 };
726static struct spear_muxreg vip_mux_cam1_muxreg[] = {
727 {
728 .reg = PAD_SHARED_IP_EN_1,
729 .mask = CAM1_MASK,
730 .val = 0,
731 }, {
732 .reg = PAD_FUNCTION_EN_2,
733 .mask = VIP_AND_CAM1_REG1_MASK,
734 .val = VIP_AND_CAM1_REG1_MASK,
735 }, {
736 .reg = PAD_FUNCTION_EN_3,
737 .mask = VIP_AND_CAM1_REG2_MASK,
738 .val = VIP_AND_CAM1_REG2_MASK,
739 },
740};
741
742static struct spear_modemux vip_mux_cam1_modemux[] = {
743 {
744 .muxregs = vip_mux_cam1_muxreg,
745 .nmuxregs = ARRAY_SIZE(vip_mux_cam1_muxreg),
746 },
747};
748
749static struct spear_pingroup vip_mux_cam1_pingroup = {
750 .name = "vip_mux_cam1_grp",
751 .pins = vip_mux_cam1_pins,
752 .npins = ARRAY_SIZE(vip_mux_cam1_pins),
753 .modemuxs = vip_mux_cam1_modemux,
754 .nmodemuxs = ARRAY_SIZE(vip_mux_cam1_modemux),
755};
756
757/* pad multiplexing for vip_mux_cam2 (disables cam2) device */
758static const unsigned vip_mux_cam2_pins[] = { 39, 44, 45, 46, 47, 48, 49, 50,
759 51, 52, 53 };
760static struct spear_muxreg vip_mux_cam2_muxreg[] = {
761 {
762 .reg = PAD_SHARED_IP_EN_1,
763 .mask = CAM2_MASK,
764 .val = 0,
765 }, {
766 .reg = PAD_FUNCTION_EN_2,
767 .mask = VIP_AND_CAM2_REG1_MASK,
768 .val = VIP_AND_CAM2_REG1_MASK,
769 },
770};
771
772static struct spear_modemux vip_mux_cam2_modemux[] = {
773 {
774 .muxregs = vip_mux_cam2_muxreg,
775 .nmuxregs = ARRAY_SIZE(vip_mux_cam2_muxreg),
776 },
777};
778
779static struct spear_pingroup vip_mux_cam2_pingroup = {
780 .name = "vip_mux_cam2_grp",
781 .pins = vip_mux_cam2_pins,
782 .npins = ARRAY_SIZE(vip_mux_cam2_pins),
783 .modemuxs = vip_mux_cam2_modemux,
784 .nmodemuxs = ARRAY_SIZE(vip_mux_cam2_modemux),
785};
786
787/* pad multiplexing for vip_mux_cam3 (disables cam3) device */
788static const unsigned vip_mux_cam3_pins[] = { 20, 25, 26, 27, 28, 29, 30, 31,
789 32, 33, 34 };
790static struct spear_muxreg vip_mux_cam3_muxreg[] = {
791 {
792 .reg = PAD_SHARED_IP_EN_1,
793 .mask = CAM3_MASK,
794 .val = 0,
795 }, {
796 .reg = PAD_FUNCTION_EN_1,
797 .mask = VIP_AND_CAM3_REG0_MASK,
798 .val = VIP_AND_CAM3_REG0_MASK,
799 }, {
800 .reg = PAD_FUNCTION_EN_2,
801 .mask = VIP_AND_CAM3_REG1_MASK,
802 .val = VIP_AND_CAM3_REG1_MASK,
803 },
804};
805
806static struct spear_modemux vip_mux_cam3_modemux[] = {
807 {
808 .muxregs = vip_mux_cam3_muxreg,
809 .nmuxregs = ARRAY_SIZE(vip_mux_cam3_muxreg),
810 },
811};
812
813static struct spear_pingroup vip_mux_cam3_pingroup = {
814 .name = "vip_mux_cam3_grp",
815 .pins = vip_mux_cam3_pins,
816 .npins = ARRAY_SIZE(vip_mux_cam3_pins),
817 .modemuxs = vip_mux_cam3_modemux,
818 .nmodemuxs = ARRAY_SIZE(vip_mux_cam3_modemux),
819};
820
821static const char *const vip_grps[] = { "vip_mux_grp", "vip_mux_cam0_grp" ,
822 "vip_mux_cam1_grp" , "vip_mux_cam2_grp", "vip_mux_cam3_grp" };
823static struct spear_function vip_function = {
824 .name = "vip",
825 .groups = vip_grps,
826 .ngroups = ARRAY_SIZE(vip_grps),
827};
828
829/* pad multiplexing for cam0 device */
830static const unsigned cam0_pins[] = { 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75
831};
832static struct spear_muxreg cam0_muxreg[] = {
833 {
834 .reg = PAD_SHARED_IP_EN_1,
835 .mask = CAM0_MASK,
836 .val = CAM0_MASK,
837 }, {
838 .reg = PAD_FUNCTION_EN_3,
839 .mask = VIP_AND_CAM0_REG2_MASK,
840 .val = VIP_AND_CAM0_REG2_MASK,
841 },
842};
843
844static struct spear_modemux cam0_modemux[] = {
845 {
846 .muxregs = cam0_muxreg,
847 .nmuxregs = ARRAY_SIZE(cam0_muxreg),
848 },
849};
850
851static struct spear_pingroup cam0_pingroup = {
852 .name = "cam0_grp",
853 .pins = cam0_pins,
854 .npins = ARRAY_SIZE(cam0_pins),
855 .modemuxs = cam0_modemux,
856 .nmodemuxs = ARRAY_SIZE(cam0_modemux),
857};
858
859static const char *const cam0_grps[] = { "cam0_grp" };
860static struct spear_function cam0_function = {
861 .name = "cam0",
862 .groups = cam0_grps,
863 .ngroups = ARRAY_SIZE(cam0_grps),
864};
865
866/* pad multiplexing for cam1 device */
867static const unsigned cam1_pins[] = { 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64
868};
869static struct spear_muxreg cam1_muxreg[] = {
870 {
871 .reg = PAD_SHARED_IP_EN_1,
872 .mask = CAM1_MASK,
873 .val = CAM1_MASK,
874 }, {
875 .reg = PAD_FUNCTION_EN_2,
876 .mask = VIP_AND_CAM1_REG1_MASK,
877 .val = VIP_AND_CAM1_REG1_MASK,
878 }, {
879 .reg = PAD_FUNCTION_EN_3,
880 .mask = VIP_AND_CAM1_REG2_MASK,
881 .val = VIP_AND_CAM1_REG2_MASK,
882 },
883};
884
885static struct spear_modemux cam1_modemux[] = {
886 {
887 .muxregs = cam1_muxreg,
888 .nmuxregs = ARRAY_SIZE(cam1_muxreg),
889 },
890};
891
892static struct spear_pingroup cam1_pingroup = {
893 .name = "cam1_grp",
894 .pins = cam1_pins,
895 .npins = ARRAY_SIZE(cam1_pins),
896 .modemuxs = cam1_modemux,
897 .nmodemuxs = ARRAY_SIZE(cam1_modemux),
898};
899
900static const char *const cam1_grps[] = { "cam1_grp" };
901static struct spear_function cam1_function = {
902 .name = "cam1",
903 .groups = cam1_grps,
904 .ngroups = ARRAY_SIZE(cam1_grps),
905};
906
907/* pad multiplexing for cam2 device */
908static const unsigned cam2_pins[] = { 39, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53
909};
910static struct spear_muxreg cam2_muxreg[] = {
911 {
912 .reg = PAD_SHARED_IP_EN_1,
913 .mask = CAM2_MASK,
914 .val = CAM2_MASK,
915 }, {
916 .reg = PAD_FUNCTION_EN_2,
917 .mask = VIP_AND_CAM2_REG1_MASK,
918 .val = VIP_AND_CAM2_REG1_MASK,
919 },
920};
921
922static struct spear_modemux cam2_modemux[] = {
923 {
924 .muxregs = cam2_muxreg,
925 .nmuxregs = ARRAY_SIZE(cam2_muxreg),
926 },
927};
928
929static struct spear_pingroup cam2_pingroup = {
930 .name = "cam2_grp",
931 .pins = cam2_pins,
932 .npins = ARRAY_SIZE(cam2_pins),
933 .modemuxs = cam2_modemux,
934 .nmodemuxs = ARRAY_SIZE(cam2_modemux),
935};
936
937static const char *const cam2_grps[] = { "cam2_grp" };
938static struct spear_function cam2_function = {
939 .name = "cam2",
940 .groups = cam2_grps,
941 .ngroups = ARRAY_SIZE(cam2_grps),
942};
943
944/* pad multiplexing for cam3 device */
945static const unsigned cam3_pins[] = { 20, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34
946};
947static struct spear_muxreg cam3_muxreg[] = {
948 {
949 .reg = PAD_SHARED_IP_EN_1,
950 .mask = CAM3_MASK,
951 .val = CAM3_MASK,
952 }, {
953 .reg = PAD_FUNCTION_EN_1,
954 .mask = VIP_AND_CAM3_REG0_MASK,
955 .val = VIP_AND_CAM3_REG0_MASK,
956 }, {
957 .reg = PAD_FUNCTION_EN_2,
958 .mask = VIP_AND_CAM3_REG1_MASK,
959 .val = VIP_AND_CAM3_REG1_MASK,
960 },
961};
962
963static struct spear_modemux cam3_modemux[] = {
964 {
965 .muxregs = cam3_muxreg,
966 .nmuxregs = ARRAY_SIZE(cam3_muxreg),
967 },
968};
969
970static struct spear_pingroup cam3_pingroup = {
971 .name = "cam3_grp",
972 .pins = cam3_pins,
973 .npins = ARRAY_SIZE(cam3_pins),
974 .modemuxs = cam3_modemux,
975 .nmodemuxs = ARRAY_SIZE(cam3_modemux),
976};
977
978static const char *const cam3_grps[] = { "cam3_grp" };
979static struct spear_function cam3_function = {
980 .name = "cam3",
981 .groups = cam3_grps,
982 .ngroups = ARRAY_SIZE(cam3_grps),
983};
984
985/* pad multiplexing for smi device */
986static const unsigned smi_pins[] = { 76, 77, 78, 79, 84 };
987static struct spear_muxreg smi_muxreg[] = {
988 {
989 .reg = PAD_FUNCTION_EN_3,
990 .mask = SMI_REG2_MASK,
991 .val = SMI_REG2_MASK,
992 },
993};
994
995static struct spear_modemux smi_modemux[] = {
996 {
997 .muxregs = smi_muxreg,
998 .nmuxregs = ARRAY_SIZE(smi_muxreg),
999 },
1000};
1001
1002static struct spear_pingroup smi_pingroup = {
1003 .name = "smi_grp",
1004 .pins = smi_pins,
1005 .npins = ARRAY_SIZE(smi_pins),
1006 .modemuxs = smi_modemux,
1007 .nmodemuxs = ARRAY_SIZE(smi_modemux),
1008};
1009
1010static const char *const smi_grps[] = { "smi_grp" };
1011static struct spear_function smi_function = {
1012 .name = "smi",
1013 .groups = smi_grps,
1014 .ngroups = ARRAY_SIZE(smi_grps),
1015};
1016
1017/* pad multiplexing for ssp0 device */
1018static const unsigned ssp0_pins[] = { 80, 81, 82, 83 };
1019static struct spear_muxreg ssp0_muxreg[] = {
1020 {
1021 .reg = PAD_FUNCTION_EN_3,
1022 .mask = SSP0_REG2_MASK,
1023 .val = SSP0_REG2_MASK,
1024 },
1025};
1026
1027static struct spear_modemux ssp0_modemux[] = {
1028 {
1029 .muxregs = ssp0_muxreg,
1030 .nmuxregs = ARRAY_SIZE(ssp0_muxreg),
1031 },
1032};
1033
1034static struct spear_pingroup ssp0_pingroup = {
1035 .name = "ssp0_grp",
1036 .pins = ssp0_pins,
1037 .npins = ARRAY_SIZE(ssp0_pins),
1038 .modemuxs = ssp0_modemux,
1039 .nmodemuxs = ARRAY_SIZE(ssp0_modemux),
1040};
1041
1042/* pad multiplexing for ssp0_cs1 device */
1043static const unsigned ssp0_cs1_pins[] = { 24 };
1044static struct spear_muxreg ssp0_cs1_muxreg[] = {
1045 {
1046 .reg = PAD_SHARED_IP_EN_1,
1047 .mask = SSP0_CS1_MASK,
1048 .val = SSP0_CS1_MASK,
1049 }, {
1050 .reg = PAD_FUNCTION_EN_1,
1051 .mask = PWM0_AND_SSP0_CS1_REG0_MASK,
1052 .val = PWM0_AND_SSP0_CS1_REG0_MASK,
1053 },
1054};
1055
1056static struct spear_modemux ssp0_cs1_modemux[] = {
1057 {
1058 .muxregs = ssp0_cs1_muxreg,
1059 .nmuxregs = ARRAY_SIZE(ssp0_cs1_muxreg),
1060 },
1061};
1062
1063static struct spear_pingroup ssp0_cs1_pingroup = {
1064 .name = "ssp0_cs1_grp",
1065 .pins = ssp0_cs1_pins,
1066 .npins = ARRAY_SIZE(ssp0_cs1_pins),
1067 .modemuxs = ssp0_cs1_modemux,
1068 .nmodemuxs = ARRAY_SIZE(ssp0_cs1_modemux),
1069};
1070
1071/* pad multiplexing for ssp0_cs2 device */
1072static const unsigned ssp0_cs2_pins[] = { 85 };
1073static struct spear_muxreg ssp0_cs2_muxreg[] = {
1074 {
1075 .reg = PAD_SHARED_IP_EN_1,
1076 .mask = SSP0_CS2_MASK,
1077 .val = SSP0_CS2_MASK,
1078 }, {
1079 .reg = PAD_FUNCTION_EN_3,
1080 .mask = TS_AND_SSP0_CS2_REG2_MASK,
1081 .val = TS_AND_SSP0_CS2_REG2_MASK,
1082 },
1083};
1084
1085static struct spear_modemux ssp0_cs2_modemux[] = {
1086 {
1087 .muxregs = ssp0_cs2_muxreg,
1088 .nmuxregs = ARRAY_SIZE(ssp0_cs2_muxreg),
1089 },
1090};
1091
1092static struct spear_pingroup ssp0_cs2_pingroup = {
1093 .name = "ssp0_cs2_grp",
1094 .pins = ssp0_cs2_pins,
1095 .npins = ARRAY_SIZE(ssp0_cs2_pins),
1096 .modemuxs = ssp0_cs2_modemux,
1097 .nmodemuxs = ARRAY_SIZE(ssp0_cs2_modemux),
1098};
1099
1100/* pad multiplexing for ssp0_cs3 device */
1101static const unsigned ssp0_cs3_pins[] = { 132 };
1102static struct spear_muxreg ssp0_cs3_muxreg[] = {
1103 {
1104 .reg = PAD_FUNCTION_EN_5,
1105 .mask = SSP0_CS3_REG4_MASK,
1106 .val = SSP0_CS3_REG4_MASK,
1107 },
1108};
1109
1110static struct spear_modemux ssp0_cs3_modemux[] = {
1111 {
1112 .muxregs = ssp0_cs3_muxreg,
1113 .nmuxregs = ARRAY_SIZE(ssp0_cs3_muxreg),
1114 },
1115};
1116
1117static struct spear_pingroup ssp0_cs3_pingroup = {
1118 .name = "ssp0_cs3_grp",
1119 .pins = ssp0_cs3_pins,
1120 .npins = ARRAY_SIZE(ssp0_cs3_pins),
1121 .modemuxs = ssp0_cs3_modemux,
1122 .nmodemuxs = ARRAY_SIZE(ssp0_cs3_modemux),
1123};
1124
1125static const char *const ssp0_grps[] = { "ssp0_grp", "ssp0_cs1_grp",
1126 "ssp0_cs2_grp", "ssp0_cs3_grp" };
1127static struct spear_function ssp0_function = {
1128 .name = "ssp0",
1129 .groups = ssp0_grps,
1130 .ngroups = ARRAY_SIZE(ssp0_grps),
1131};
1132
1133/* pad multiplexing for uart0 device */
1134static const unsigned uart0_pins[] = { 86, 87 };
1135static struct spear_muxreg uart0_muxreg[] = {
1136 {
1137 .reg = PAD_FUNCTION_EN_3,
1138 .mask = UART0_REG2_MASK,
1139 .val = UART0_REG2_MASK,
1140 },
1141};
1142
1143static struct spear_modemux uart0_modemux[] = {
1144 {
1145 .muxregs = uart0_muxreg,
1146 .nmuxregs = ARRAY_SIZE(uart0_muxreg),
1147 },
1148};
1149
1150static struct spear_pingroup uart0_pingroup = {
1151 .name = "uart0_grp",
1152 .pins = uart0_pins,
1153 .npins = ARRAY_SIZE(uart0_pins),
1154 .modemuxs = uart0_modemux,
1155 .nmodemuxs = ARRAY_SIZE(uart0_modemux),
1156};
1157
1158/* pad multiplexing for uart0_enh device */
1159static const unsigned uart0_enh_pins[] = { 11, 12, 13, 14, 15, 16 };
1160static struct spear_muxreg uart0_enh_muxreg[] = {
1161 {
1162 .reg = PAD_SHARED_IP_EN_1,
1163 .mask = GPT_MASK,
1164 .val = 0,
1165 }, {
1166 .reg = PAD_FUNCTION_EN_1,
1167 .mask = UART0_ENH_AND_GPT_REG0_MASK,
1168 .val = UART0_ENH_AND_GPT_REG0_MASK,
1169 },
1170};
1171
1172static struct spear_modemux uart0_enh_modemux[] = {
1173 {
1174 .muxregs = uart0_enh_muxreg,
1175 .nmuxregs = ARRAY_SIZE(uart0_enh_muxreg),
1176 },
1177};
1178
1179static struct spear_pingroup uart0_enh_pingroup = {
1180 .name = "uart0_enh_grp",
1181 .pins = uart0_enh_pins,
1182 .npins = ARRAY_SIZE(uart0_enh_pins),
1183 .modemuxs = uart0_enh_modemux,
1184 .nmodemuxs = ARRAY_SIZE(uart0_enh_modemux),
1185};
1186
1187static const char *const uart0_grps[] = { "uart0_grp", "uart0_enh_grp" };
1188static struct spear_function uart0_function = {
1189 .name = "uart0",
1190 .groups = uart0_grps,
1191 .ngroups = ARRAY_SIZE(uart0_grps),
1192};
1193
1194/* pad multiplexing for uart1 device */
1195static const unsigned uart1_pins[] = { 88, 89 };
1196static struct spear_muxreg uart1_muxreg[] = {
1197 {
1198 .reg = PAD_FUNCTION_EN_3,
1199 .mask = UART1_REG2_MASK,
1200 .val = UART1_REG2_MASK,
1201 },
1202};
1203
1204static struct spear_modemux uart1_modemux[] = {
1205 {
1206 .muxregs = uart1_muxreg,
1207 .nmuxregs = ARRAY_SIZE(uart1_muxreg),
1208 },
1209};
1210
1211static struct spear_pingroup uart1_pingroup = {
1212 .name = "uart1_grp",
1213 .pins = uart1_pins,
1214 .npins = ARRAY_SIZE(uart1_pins),
1215 .modemuxs = uart1_modemux,
1216 .nmodemuxs = ARRAY_SIZE(uart1_modemux),
1217};
1218
1219static const char *const uart1_grps[] = { "uart1_grp" };
1220static struct spear_function uart1_function = {
1221 .name = "uart1",
1222 .groups = uart1_grps,
1223 .ngroups = ARRAY_SIZE(uart1_grps),
1224};
1225
1226/* pad multiplexing for i2s_in device */
1227static const unsigned i2s_in_pins[] = { 90, 91, 92, 93, 94, 99 };
1228static struct spear_muxreg i2s_in_muxreg[] = {
1229 {
1230 .reg = PAD_FUNCTION_EN_3,
1231 .mask = I2S_IN_REG2_MASK,
1232 .val = I2S_IN_REG2_MASK,
1233 }, {
1234 .reg = PAD_FUNCTION_EN_4,
1235 .mask = I2S_IN_REG3_MASK,
1236 .val = I2S_IN_REG3_MASK,
1237 },
1238};
1239
1240static struct spear_modemux i2s_in_modemux[] = {
1241 {
1242 .muxregs = i2s_in_muxreg,
1243 .nmuxregs = ARRAY_SIZE(i2s_in_muxreg),
1244 },
1245};
1246
1247static struct spear_pingroup i2s_in_pingroup = {
1248 .name = "i2s_in_grp",
1249 .pins = i2s_in_pins,
1250 .npins = ARRAY_SIZE(i2s_in_pins),
1251 .modemuxs = i2s_in_modemux,
1252 .nmodemuxs = ARRAY_SIZE(i2s_in_modemux),
1253};
1254
1255/* pad multiplexing for i2s_out device */
1256static const unsigned i2s_out_pins[] = { 95, 96, 97, 98, 100, 101, 102, 103 };
1257static struct spear_muxreg i2s_out_muxreg[] = {
1258 {
1259 .reg = PAD_FUNCTION_EN_4,
1260 .mask = I2S_OUT_REG3_MASK,
1261 .val = I2S_OUT_REG3_MASK,
1262 },
1263};
1264
1265static struct spear_modemux i2s_out_modemux[] = {
1266 {
1267 .muxregs = i2s_out_muxreg,
1268 .nmuxregs = ARRAY_SIZE(i2s_out_muxreg),
1269 },
1270};
1271
1272static struct spear_pingroup i2s_out_pingroup = {
1273 .name = "i2s_out_grp",
1274 .pins = i2s_out_pins,
1275 .npins = ARRAY_SIZE(i2s_out_pins),
1276 .modemuxs = i2s_out_modemux,
1277 .nmodemuxs = ARRAY_SIZE(i2s_out_modemux),
1278};
1279
1280static const char *const i2s_grps[] = { "i2s_in_grp", "i2s_out_grp" };
1281static struct spear_function i2s_function = {
1282 .name = "i2s",
1283 .groups = i2s_grps,
1284 .ngroups = ARRAY_SIZE(i2s_grps),
1285};
1286
1287/* pad multiplexing for gmac device */
1288static const unsigned gmac_pins[] = { 104, 105, 106, 107, 108, 109, 110, 111,
1289 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125,
1290 126, 127, 128, 129, 130, 131 };
1291#define GMAC_MUXREG \
1292 { \
1293 .reg = PAD_FUNCTION_EN_4, \
1294 .mask = GMAC_REG3_MASK, \
1295 .val = GMAC_REG3_MASK, \
1296 }, { \
1297 .reg = PAD_FUNCTION_EN_5, \
1298 .mask = GMAC_REG4_MASK, \
1299 .val = GMAC_REG4_MASK, \
1300 }
1301
1302/* pad multiplexing for gmii device */
1303static struct spear_muxreg gmii_muxreg[] = {
1304 GMAC_MUXREG,
1305 {
1306 .reg = GMAC_CLK_CFG,
1307 .mask = GMAC_PHY_IF_SEL_MASK,
1308 .val = GMAC_PHY_IF_GMII_VAL,
1309 },
1310};
1311
1312static struct spear_modemux gmii_modemux[] = {
1313 {
1314 .muxregs = gmii_muxreg,
1315 .nmuxregs = ARRAY_SIZE(gmii_muxreg),
1316 },
1317};
1318
1319static struct spear_pingroup gmii_pingroup = {
1320 .name = "gmii_grp",
1321 .pins = gmac_pins,
1322 .npins = ARRAY_SIZE(gmac_pins),
1323 .modemuxs = gmii_modemux,
1324 .nmodemuxs = ARRAY_SIZE(gmii_modemux),
1325};
1326
1327/* pad multiplexing for rgmii device */
1328static struct spear_muxreg rgmii_muxreg[] = {
1329 GMAC_MUXREG,
1330 {
1331 .reg = GMAC_CLK_CFG,
1332 .mask = GMAC_PHY_IF_SEL_MASK,
1333 .val = GMAC_PHY_IF_RGMII_VAL,
1334 },
1335};
1336
1337static struct spear_modemux rgmii_modemux[] = {
1338 {
1339 .muxregs = rgmii_muxreg,
1340 .nmuxregs = ARRAY_SIZE(rgmii_muxreg),
1341 },
1342};
1343
1344static struct spear_pingroup rgmii_pingroup = {
1345 .name = "rgmii_grp",
1346 .pins = gmac_pins,
1347 .npins = ARRAY_SIZE(gmac_pins),
1348 .modemuxs = rgmii_modemux,
1349 .nmodemuxs = ARRAY_SIZE(rgmii_modemux),
1350};
1351
1352/* pad multiplexing for rmii device */
1353static struct spear_muxreg rmii_muxreg[] = {
1354 GMAC_MUXREG,
1355 {
1356 .reg = GMAC_CLK_CFG,
1357 .mask = GMAC_PHY_IF_SEL_MASK,
1358 .val = GMAC_PHY_IF_RMII_VAL,
1359 },
1360};
1361
1362static struct spear_modemux rmii_modemux[] = {
1363 {
1364 .muxregs = rmii_muxreg,
1365 .nmuxregs = ARRAY_SIZE(rmii_muxreg),
1366 },
1367};
1368
1369static struct spear_pingroup rmii_pingroup = {
1370 .name = "rmii_grp",
1371 .pins = gmac_pins,
1372 .npins = ARRAY_SIZE(gmac_pins),
1373 .modemuxs = rmii_modemux,
1374 .nmodemuxs = ARRAY_SIZE(rmii_modemux),
1375};
1376
1377/* pad multiplexing for sgmii device */
1378static struct spear_muxreg sgmii_muxreg[] = {
1379 GMAC_MUXREG,
1380 {
1381 .reg = GMAC_CLK_CFG,
1382 .mask = GMAC_PHY_IF_SEL_MASK,
1383 .val = GMAC_PHY_IF_SGMII_VAL,
1384 },
1385};
1386
1387static struct spear_modemux sgmii_modemux[] = {
1388 {
1389 .muxregs = sgmii_muxreg,
1390 .nmuxregs = ARRAY_SIZE(sgmii_muxreg),
1391 },
1392};
1393
1394static struct spear_pingroup sgmii_pingroup = {
1395 .name = "sgmii_grp",
1396 .pins = gmac_pins,
1397 .npins = ARRAY_SIZE(gmac_pins),
1398 .modemuxs = sgmii_modemux,
1399 .nmodemuxs = ARRAY_SIZE(sgmii_modemux),
1400};
1401
1402static const char *const gmac_grps[] = { "gmii_grp", "rgmii_grp", "rmii_grp",
1403 "sgmii_grp" };
1404static struct spear_function gmac_function = {
1405 .name = "gmac",
1406 .groups = gmac_grps,
1407 .ngroups = ARRAY_SIZE(gmac_grps),
1408};
1409
1410/* pad multiplexing for i2c0 device */
1411static const unsigned i2c0_pins[] = { 133, 134 };
1412static struct spear_muxreg i2c0_muxreg[] = {
1413 {
1414 .reg = PAD_FUNCTION_EN_5,
1415 .mask = I2C0_REG4_MASK,
1416 .val = I2C0_REG4_MASK,
1417 },
1418};
1419
1420static struct spear_modemux i2c0_modemux[] = {
1421 {
1422 .muxregs = i2c0_muxreg,
1423 .nmuxregs = ARRAY_SIZE(i2c0_muxreg),
1424 },
1425};
1426
1427static struct spear_pingroup i2c0_pingroup = {
1428 .name = "i2c0_grp",
1429 .pins = i2c0_pins,
1430 .npins = ARRAY_SIZE(i2c0_pins),
1431 .modemuxs = i2c0_modemux,
1432 .nmodemuxs = ARRAY_SIZE(i2c0_modemux),
1433};
1434
1435static const char *const i2c0_grps[] = { "i2c0_grp" };
1436static struct spear_function i2c0_function = {
1437 .name = "i2c0",
1438 .groups = i2c0_grps,
1439 .ngroups = ARRAY_SIZE(i2c0_grps),
1440};
1441
1442/* pad multiplexing for i2c1 device */
1443static const unsigned i2c1_pins[] = { 18, 23 };
1444static struct spear_muxreg i2c1_muxreg[] = {
1445 {
1446 .reg = PAD_FUNCTION_EN_1,
1447 .mask = I2C1_REG0_MASK,
1448 .val = I2C1_REG0_MASK,
1449 },
1450};
1451
1452static struct spear_modemux i2c1_modemux[] = {
1453 {
1454 .muxregs = i2c1_muxreg,
1455 .nmuxregs = ARRAY_SIZE(i2c1_muxreg),
1456 },
1457};
1458
1459static struct spear_pingroup i2c1_pingroup = {
1460 .name = "i2c1_grp",
1461 .pins = i2c1_pins,
1462 .npins = ARRAY_SIZE(i2c1_pins),
1463 .modemuxs = i2c1_modemux,
1464 .nmodemuxs = ARRAY_SIZE(i2c1_modemux),
1465};
1466
1467static const char *const i2c1_grps[] = { "i2c1_grp" };
1468static struct spear_function i2c1_function = {
1469 .name = "i2c1",
1470 .groups = i2c1_grps,
1471 .ngroups = ARRAY_SIZE(i2c1_grps),
1472};
1473
1474/* pad multiplexing for cec0 device */
1475static const unsigned cec0_pins[] = { 135 };
1476static struct spear_muxreg cec0_muxreg[] = {
1477 {
1478 .reg = PAD_FUNCTION_EN_5,
1479 .mask = CEC0_REG4_MASK,
1480 .val = CEC0_REG4_MASK,
1481 },
1482};
1483
1484static struct spear_modemux cec0_modemux[] = {
1485 {
1486 .muxregs = cec0_muxreg,
1487 .nmuxregs = ARRAY_SIZE(cec0_muxreg),
1488 },
1489};
1490
1491static struct spear_pingroup cec0_pingroup = {
1492 .name = "cec0_grp",
1493 .pins = cec0_pins,
1494 .npins = ARRAY_SIZE(cec0_pins),
1495 .modemuxs = cec0_modemux,
1496 .nmodemuxs = ARRAY_SIZE(cec0_modemux),
1497};
1498
1499static const char *const cec0_grps[] = { "cec0_grp" };
1500static struct spear_function cec0_function = {
1501 .name = "cec0",
1502 .groups = cec0_grps,
1503 .ngroups = ARRAY_SIZE(cec0_grps),
1504};
1505
1506/* pad multiplexing for cec1 device */
1507static const unsigned cec1_pins[] = { 136 };
1508static struct spear_muxreg cec1_muxreg[] = {
1509 {
1510 .reg = PAD_FUNCTION_EN_5,
1511 .mask = CEC1_REG4_MASK,
1512 .val = CEC1_REG4_MASK,
1513 },
1514};
1515
1516static struct spear_modemux cec1_modemux[] = {
1517 {
1518 .muxregs = cec1_muxreg,
1519 .nmuxregs = ARRAY_SIZE(cec1_muxreg),
1520 },
1521};
1522
1523static struct spear_pingroup cec1_pingroup = {
1524 .name = "cec1_grp",
1525 .pins = cec1_pins,
1526 .npins = ARRAY_SIZE(cec1_pins),
1527 .modemuxs = cec1_modemux,
1528 .nmodemuxs = ARRAY_SIZE(cec1_modemux),
1529};
1530
1531static const char *const cec1_grps[] = { "cec1_grp" };
1532static struct spear_function cec1_function = {
1533 .name = "cec1",
1534 .groups = cec1_grps,
1535 .ngroups = ARRAY_SIZE(cec1_grps),
1536};
1537
1538/* pad multiplexing for mcif devices */
1539static const unsigned mcif_pins[] = { 193, 194, 195, 196, 197, 198, 199, 200,
1540 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214,
1541 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228,
1542 229, 230, 231, 232, 237 };
1543#define MCIF_MUXREG \
1544 { \
1545 .reg = PAD_SHARED_IP_EN_1, \
1546 .mask = MCIF_MASK, \
1547 .val = MCIF_MASK, \
1548 }, { \
1549 .reg = PAD_FUNCTION_EN_7, \
1550 .mask = FSMC_PNOR_AND_MCIF_REG6_MASK | MCIF_REG6_MASK, \
1551 .val = FSMC_PNOR_AND_MCIF_REG6_MASK | MCIF_REG6_MASK, \
1552 }, { \
1553 .reg = PAD_FUNCTION_EN_8, \
1554 .mask = MCIF_REG7_MASK, \
1555 .val = MCIF_REG7_MASK, \
1556 }
1557
1558/* Pad multiplexing for sdhci device */
1559static struct spear_muxreg sdhci_muxreg[] = {
1560 MCIF_MUXREG,
1561 {
1562 .reg = PERIP_CFG,
1563 .mask = MCIF_SEL_MASK,
1564 .val = MCIF_SEL_SD,
1565 },
1566};
1567
1568static struct spear_modemux sdhci_modemux[] = {
1569 {
1570 .muxregs = sdhci_muxreg,
1571 .nmuxregs = ARRAY_SIZE(sdhci_muxreg),
1572 },
1573};
1574
1575static struct spear_pingroup sdhci_pingroup = {
1576 .name = "sdhci_grp",
1577 .pins = mcif_pins,
1578 .npins = ARRAY_SIZE(mcif_pins),
1579 .modemuxs = sdhci_modemux,
1580 .nmodemuxs = ARRAY_SIZE(sdhci_modemux),
1581};
1582
1583static const char *const sdhci_grps[] = { "sdhci_grp" };
1584static struct spear_function sdhci_function = {
1585 .name = "sdhci",
1586 .groups = sdhci_grps,
1587 .ngroups = ARRAY_SIZE(sdhci_grps),
1588};
1589
1590/* Pad multiplexing for cf device */
1591static struct spear_muxreg cf_muxreg[] = {
1592 MCIF_MUXREG,
1593 {
1594 .reg = PERIP_CFG,
1595 .mask = MCIF_SEL_MASK,
1596 .val = MCIF_SEL_CF,
1597 },
1598};
1599
1600static struct spear_modemux cf_modemux[] = {
1601 {
1602 .muxregs = cf_muxreg,
1603 .nmuxregs = ARRAY_SIZE(cf_muxreg),
1604 },
1605};
1606
1607static struct spear_pingroup cf_pingroup = {
1608 .name = "cf_grp",
1609 .pins = mcif_pins,
1610 .npins = ARRAY_SIZE(mcif_pins),
1611 .modemuxs = cf_modemux,
1612 .nmodemuxs = ARRAY_SIZE(cf_modemux),
1613};
1614
1615static const char *const cf_grps[] = { "cf_grp" };
1616static struct spear_function cf_function = {
1617 .name = "cf",
1618 .groups = cf_grps,
1619 .ngroups = ARRAY_SIZE(cf_grps),
1620};
1621
1622/* Pad multiplexing for xd device */
1623static struct spear_muxreg xd_muxreg[] = {
1624 MCIF_MUXREG,
1625 {
1626 .reg = PERIP_CFG,
1627 .mask = MCIF_SEL_MASK,
1628 .val = MCIF_SEL_XD,
1629 },
1630};
1631
1632static struct spear_modemux xd_modemux[] = {
1633 {
1634 .muxregs = xd_muxreg,
1635 .nmuxregs = ARRAY_SIZE(xd_muxreg),
1636 },
1637};
1638
1639static struct spear_pingroup xd_pingroup = {
1640 .name = "xd_grp",
1641 .pins = mcif_pins,
1642 .npins = ARRAY_SIZE(mcif_pins),
1643 .modemuxs = xd_modemux,
1644 .nmodemuxs = ARRAY_SIZE(xd_modemux),
1645};
1646
1647static const char *const xd_grps[] = { "xd_grp" };
1648static struct spear_function xd_function = {
1649 .name = "xd",
1650 .groups = xd_grps,
1651 .ngroups = ARRAY_SIZE(xd_grps),
1652};
1653
1654/* pad multiplexing for clcd device */
1655static const unsigned clcd_pins[] = { 138, 139, 140, 141, 142, 143, 144, 145,
1656 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159,
1657 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173,
1658 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187,
1659 188, 189, 190, 191 };
1660static struct spear_muxreg clcd_muxreg[] = {
1661 {
1662 .reg = PAD_SHARED_IP_EN_1,
1663 .mask = ARM_TRACE_MASK | MIPHY_DBG_MASK,
1664 .val = 0,
1665 }, {
1666 .reg = PAD_FUNCTION_EN_5,
1667 .mask = CLCD_REG4_MASK | CLCD_AND_ARM_TRACE_REG4_MASK,
1668 .val = CLCD_REG4_MASK | CLCD_AND_ARM_TRACE_REG4_MASK,
1669 }, {
1670 .reg = PAD_FUNCTION_EN_6,
1671 .mask = CLCD_AND_ARM_TRACE_REG5_MASK,
1672 .val = CLCD_AND_ARM_TRACE_REG5_MASK,
1673 }, {
1674 .reg = PAD_FUNCTION_EN_7,
1675 .mask = CLCD_AND_ARM_TRACE_REG6_MASK,
1676 .val = CLCD_AND_ARM_TRACE_REG6_MASK,
1677 },
1678};
1679
1680static struct spear_modemux clcd_modemux[] = {
1681 {
1682 .muxregs = clcd_muxreg,
1683 .nmuxregs = ARRAY_SIZE(clcd_muxreg),
1684 },
1685};
1686
1687static struct spear_pingroup clcd_pingroup = {
1688 .name = "clcd_grp",
1689 .pins = clcd_pins,
1690 .npins = ARRAY_SIZE(clcd_pins),
1691 .modemuxs = clcd_modemux,
1692 .nmodemuxs = ARRAY_SIZE(clcd_modemux),
1693};
1694
1695static const char *const clcd_grps[] = { "clcd_grp" };
1696static struct spear_function clcd_function = {
1697 .name = "clcd",
1698 .groups = clcd_grps,
1699 .ngroups = ARRAY_SIZE(clcd_grps),
1700};
1701
1702/* pad multiplexing for arm_trace device */
1703static const unsigned arm_trace_pins[] = { 158, 159, 160, 161, 162, 163, 164,
1704 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178,
1705 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192,
1706 193, 194, 195, 196, 197, 198, 199, 200 };
1707static struct spear_muxreg arm_trace_muxreg[] = {
1708 {
1709 .reg = PAD_SHARED_IP_EN_1,
1710 .mask = ARM_TRACE_MASK,
1711 .val = ARM_TRACE_MASK,
1712 }, {
1713 .reg = PAD_FUNCTION_EN_5,
1714 .mask = CLCD_AND_ARM_TRACE_REG4_MASK,
1715 .val = CLCD_AND_ARM_TRACE_REG4_MASK,
1716 }, {
1717 .reg = PAD_FUNCTION_EN_6,
1718 .mask = CLCD_AND_ARM_TRACE_REG5_MASK,
1719 .val = CLCD_AND_ARM_TRACE_REG5_MASK,
1720 }, {
1721 .reg = PAD_FUNCTION_EN_7,
1722 .mask = CLCD_AND_ARM_TRACE_REG6_MASK,
1723 .val = CLCD_AND_ARM_TRACE_REG6_MASK,
1724 },
1725};
1726
1727static struct spear_modemux arm_trace_modemux[] = {
1728 {
1729 .muxregs = arm_trace_muxreg,
1730 .nmuxregs = ARRAY_SIZE(arm_trace_muxreg),
1731 },
1732};
1733
1734static struct spear_pingroup arm_trace_pingroup = {
1735 .name = "arm_trace_grp",
1736 .pins = arm_trace_pins,
1737 .npins = ARRAY_SIZE(arm_trace_pins),
1738 .modemuxs = arm_trace_modemux,
1739 .nmodemuxs = ARRAY_SIZE(arm_trace_modemux),
1740};
1741
1742static const char *const arm_trace_grps[] = { "arm_trace_grp" };
1743static struct spear_function arm_trace_function = {
1744 .name = "arm_trace",
1745 .groups = arm_trace_grps,
1746 .ngroups = ARRAY_SIZE(arm_trace_grps),
1747};
1748
1749/* pad multiplexing for miphy_dbg device */
1750static const unsigned miphy_dbg_pins[] = { 96, 97, 98, 99, 100, 101, 102, 103,
1751 132, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147,
1752 148, 149, 150, 151, 152, 153, 154, 155, 156, 157 };
1753static struct spear_muxreg miphy_dbg_muxreg[] = {
1754 {
1755 .reg = PAD_SHARED_IP_EN_1,
1756 .mask = MIPHY_DBG_MASK,
1757 .val = MIPHY_DBG_MASK,
1758 }, {
1759 .reg = PAD_FUNCTION_EN_5,
1760 .mask = DEVS_GRP_AND_MIPHY_DBG_REG4_MASK,
1761 .val = DEVS_GRP_AND_MIPHY_DBG_REG4_MASK,
1762 },
1763};
1764
1765static struct spear_modemux miphy_dbg_modemux[] = {
1766 {
1767 .muxregs = miphy_dbg_muxreg,
1768 .nmuxregs = ARRAY_SIZE(miphy_dbg_muxreg),
1769 },
1770};
1771
1772static struct spear_pingroup miphy_dbg_pingroup = {
1773 .name = "miphy_dbg_grp",
1774 .pins = miphy_dbg_pins,
1775 .npins = ARRAY_SIZE(miphy_dbg_pins),
1776 .modemuxs = miphy_dbg_modemux,
1777 .nmodemuxs = ARRAY_SIZE(miphy_dbg_modemux),
1778};
1779
1780static const char *const miphy_dbg_grps[] = { "miphy_dbg_grp" };
1781static struct spear_function miphy_dbg_function = {
1782 .name = "miphy_dbg",
1783 .groups = miphy_dbg_grps,
1784 .ngroups = ARRAY_SIZE(miphy_dbg_grps),
1785};
1786
1787/* pad multiplexing for pcie device */
1788static const unsigned pcie_pins[] = { 250 };
1789static struct spear_muxreg pcie_muxreg[] = {
1790 {
1791 .reg = PCIE_SATA_CFG,
1792 .mask = SATA_PCIE_CFG_MASK,
1793 .val = PCIE_CFG_VAL,
1794 },
1795};
1796
1797static struct spear_modemux pcie_modemux[] = {
1798 {
1799 .muxregs = pcie_muxreg,
1800 .nmuxregs = ARRAY_SIZE(pcie_muxreg),
1801 },
1802};
1803
1804static struct spear_pingroup pcie_pingroup = {
1805 .name = "pcie_grp",
1806 .pins = pcie_pins,
1807 .npins = ARRAY_SIZE(pcie_pins),
1808 .modemuxs = pcie_modemux,
1809 .nmodemuxs = ARRAY_SIZE(pcie_modemux),
1810};
1811
1812static const char *const pcie_grps[] = { "pcie_grp" };
1813static struct spear_function pcie_function = {
1814 .name = "pcie",
1815 .groups = pcie_grps,
1816 .ngroups = ARRAY_SIZE(pcie_grps),
1817};
1818
1819/* pad multiplexing for sata device */
1820static const unsigned sata_pins[] = { 250 };
1821static struct spear_muxreg sata_muxreg[] = {
1822 {
1823 .reg = PCIE_SATA_CFG,
1824 .mask = SATA_PCIE_CFG_MASK,
1825 .val = SATA_CFG_VAL,
1826 },
1827};
1828
1829static struct spear_modemux sata_modemux[] = {
1830 {
1831 .muxregs = sata_muxreg,
1832 .nmuxregs = ARRAY_SIZE(sata_muxreg),
1833 },
1834};
1835
1836static struct spear_pingroup sata_pingroup = {
1837 .name = "sata_grp",
1838 .pins = sata_pins,
1839 .npins = ARRAY_SIZE(sata_pins),
1840 .modemuxs = sata_modemux,
1841 .nmodemuxs = ARRAY_SIZE(sata_modemux),
1842};
1843
1844static const char *const sata_grps[] = { "sata_grp" };
1845static struct spear_function sata_function = {
1846 .name = "sata",
1847 .groups = sata_grps,
1848 .ngroups = ARRAY_SIZE(sata_grps),
1849};
1850
1851/* pingroups */
1852static struct spear_pingroup *spear1340_pingroups[] = {
1853 &pads_as_gpio_pingroup,
1854 &fsmc_8bit_pingroup,
1855 &fsmc_16bit_pingroup,
1856 &fsmc_pnor_pingroup,
1857 &keyboard_row_col_pingroup,
1858 &keyboard_col5_pingroup,
1859 &spdif_in_pingroup,
1860 &spdif_out_pingroup,
1861 &gpt_0_1_pingroup,
1862 &pwm0_pingroup,
1863 &pwm1_pingroup,
1864 &pwm2_pingroup,
1865 &pwm3_pingroup,
1866 &vip_mux_pingroup,
1867 &vip_mux_cam0_pingroup,
1868 &vip_mux_cam1_pingroup,
1869 &vip_mux_cam2_pingroup,
1870 &vip_mux_cam3_pingroup,
1871 &cam0_pingroup,
1872 &cam1_pingroup,
1873 &cam2_pingroup,
1874 &cam3_pingroup,
1875 &smi_pingroup,
1876 &ssp0_pingroup,
1877 &ssp0_cs1_pingroup,
1878 &ssp0_cs2_pingroup,
1879 &ssp0_cs3_pingroup,
1880 &uart0_pingroup,
1881 &uart0_enh_pingroup,
1882 &uart1_pingroup,
1883 &i2s_in_pingroup,
1884 &i2s_out_pingroup,
1885 &gmii_pingroup,
1886 &rgmii_pingroup,
1887 &rmii_pingroup,
1888 &sgmii_pingroup,
1889 &i2c0_pingroup,
1890 &i2c1_pingroup,
1891 &cec0_pingroup,
1892 &cec1_pingroup,
1893 &sdhci_pingroup,
1894 &cf_pingroup,
1895 &xd_pingroup,
1896 &clcd_pingroup,
1897 &arm_trace_pingroup,
1898 &miphy_dbg_pingroup,
1899 &pcie_pingroup,
1900 &sata_pingroup,
1901};
1902
1903/* functions */
1904static struct spear_function *spear1340_functions[] = {
1905 &pads_as_gpio_function,
1906 &fsmc_function,
1907 &keyboard_function,
1908 &spdif_in_function,
1909 &spdif_out_function,
1910 &gpt_0_1_function,
1911 &pwm_function,
1912 &vip_function,
1913 &cam0_function,
1914 &cam1_function,
1915 &cam2_function,
1916 &cam3_function,
1917 &smi_function,
1918 &ssp0_function,
1919 &uart0_function,
1920 &uart1_function,
1921 &i2s_function,
1922 &gmac_function,
1923 &i2c0_function,
1924 &i2c1_function,
1925 &cec0_function,
1926 &cec1_function,
1927 &sdhci_function,
1928 &cf_function,
1929 &xd_function,
1930 &clcd_function,
1931 &arm_trace_function,
1932 &miphy_dbg_function,
1933 &pcie_function,
1934 &sata_function,
1935};
1936
1937static struct spear_pinctrl_machdata spear1340_machdata = {
1938 .pins = spear1340_pins,
1939 .npins = ARRAY_SIZE(spear1340_pins),
1940 .groups = spear1340_pingroups,
1941 .ngroups = ARRAY_SIZE(spear1340_pingroups),
1942 .functions = spear1340_functions,
1943 .nfunctions = ARRAY_SIZE(spear1340_functions),
1944 .modes_supported = false,
1945};
1946
1947static struct of_device_id spear1340_pinctrl_of_match[] __devinitdata = {
1948 {
1949 .compatible = "st,spear1340-pinmux",
1950 },
1951 {},
1952};
1953
1954static int __devinit spear1340_pinctrl_probe(struct platform_device *pdev)
1955{
1956 return spear_pinctrl_probe(pdev, &spear1340_machdata);
1957}
1958
1959static int __devexit spear1340_pinctrl_remove(struct platform_device *pdev)
1960{
1961 return spear_pinctrl_remove(pdev);
1962}
1963
1964static struct platform_driver spear1340_pinctrl_driver = {
1965 .driver = {
1966 .name = DRIVER_NAME,
1967 .owner = THIS_MODULE,
1968 .of_match_table = spear1340_pinctrl_of_match,
1969 },
1970 .probe = spear1340_pinctrl_probe,
1971 .remove = __devexit_p(spear1340_pinctrl_remove),
1972};
1973
1974static int __init spear1340_pinctrl_init(void)
1975{
1976 return platform_driver_register(&spear1340_pinctrl_driver);
1977}
1978arch_initcall(spear1340_pinctrl_init);
1979
1980static void __exit spear1340_pinctrl_exit(void)
1981{
1982 platform_driver_unregister(&spear1340_pinctrl_driver);
1983}
1984module_exit(spear1340_pinctrl_exit);
1985
1986MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>");
1987MODULE_DESCRIPTION("ST Microelectronics SPEAr1340 pinctrl driver");
1988MODULE_LICENSE("GPL v2");
1989MODULE_DEVICE_TABLE(of, spear1340_pinctrl_of_match);
diff --git a/drivers/pinctrl/spear/pinctrl-spear3xx.c b/drivers/pinctrl/spear/pinctrl-spear3xx.c
index 832049a8b1c9..91c883bc46a6 100644
--- a/drivers/pinctrl/spear/pinctrl-spear3xx.c
+++ b/drivers/pinctrl/spear/pinctrl-spear3xx.c
@@ -15,108 +15,7 @@
15 15
16/* pins */ 16/* pins */
17static const struct pinctrl_pin_desc spear3xx_pins[] = { 17static const struct pinctrl_pin_desc spear3xx_pins[] = {
18 PINCTRL_PIN(0, "PLGPIO0"), 18 SPEAR_PIN_0_TO_101,
19 PINCTRL_PIN(1, "PLGPIO1"),
20 PINCTRL_PIN(2, "PLGPIO2"),
21 PINCTRL_PIN(3, "PLGPIO3"),
22 PINCTRL_PIN(4, "PLGPIO4"),
23 PINCTRL_PIN(5, "PLGPIO5"),
24 PINCTRL_PIN(6, "PLGPIO6"),
25 PINCTRL_PIN(7, "PLGPIO7"),
26 PINCTRL_PIN(8, "PLGPIO8"),
27 PINCTRL_PIN(9, "PLGPIO9"),
28 PINCTRL_PIN(10, "PLGPIO10"),
29 PINCTRL_PIN(11, "PLGPIO11"),
30 PINCTRL_PIN(12, "PLGPIO12"),
31 PINCTRL_PIN(13, "PLGPIO13"),
32 PINCTRL_PIN(14, "PLGPIO14"),
33 PINCTRL_PIN(15, "PLGPIO15"),
34 PINCTRL_PIN(16, "PLGPIO16"),
35 PINCTRL_PIN(17, "PLGPIO17"),
36 PINCTRL_PIN(18, "PLGPIO18"),
37 PINCTRL_PIN(19, "PLGPIO19"),
38 PINCTRL_PIN(20, "PLGPIO20"),
39 PINCTRL_PIN(21, "PLGPIO21"),
40 PINCTRL_PIN(22, "PLGPIO22"),
41 PINCTRL_PIN(23, "PLGPIO23"),
42 PINCTRL_PIN(24, "PLGPIO24"),
43 PINCTRL_PIN(25, "PLGPIO25"),
44 PINCTRL_PIN(26, "PLGPIO26"),
45 PINCTRL_PIN(27, "PLGPIO27"),
46 PINCTRL_PIN(28, "PLGPIO28"),
47 PINCTRL_PIN(29, "PLGPIO29"),
48 PINCTRL_PIN(30, "PLGPIO30"),
49 PINCTRL_PIN(31, "PLGPIO31"),
50 PINCTRL_PIN(32, "PLGPIO32"),
51 PINCTRL_PIN(33, "PLGPIO33"),
52 PINCTRL_PIN(34, "PLGPIO34"),
53 PINCTRL_PIN(35, "PLGPIO35"),
54 PINCTRL_PIN(36, "PLGPIO36"),
55 PINCTRL_PIN(37, "PLGPIO37"),
56 PINCTRL_PIN(38, "PLGPIO38"),
57 PINCTRL_PIN(39, "PLGPIO39"),
58 PINCTRL_PIN(40, "PLGPIO40"),
59 PINCTRL_PIN(41, "PLGPIO41"),
60 PINCTRL_PIN(42, "PLGPIO42"),
61 PINCTRL_PIN(43, "PLGPIO43"),
62 PINCTRL_PIN(44, "PLGPIO44"),
63 PINCTRL_PIN(45, "PLGPIO45"),
64 PINCTRL_PIN(46, "PLGPIO46"),
65 PINCTRL_PIN(47, "PLGPIO47"),
66 PINCTRL_PIN(48, "PLGPIO48"),
67 PINCTRL_PIN(49, "PLGPIO49"),
68 PINCTRL_PIN(50, "PLGPIO50"),
69 PINCTRL_PIN(51, "PLGPIO51"),
70 PINCTRL_PIN(52, "PLGPIO52"),
71 PINCTRL_PIN(53, "PLGPIO53"),
72 PINCTRL_PIN(54, "PLGPIO54"),
73 PINCTRL_PIN(55, "PLGPIO55"),
74 PINCTRL_PIN(56, "PLGPIO56"),
75 PINCTRL_PIN(57, "PLGPIO57"),
76 PINCTRL_PIN(58, "PLGPIO58"),
77 PINCTRL_PIN(59, "PLGPIO59"),
78 PINCTRL_PIN(60, "PLGPIO60"),
79 PINCTRL_PIN(61, "PLGPIO61"),
80 PINCTRL_PIN(62, "PLGPIO62"),
81 PINCTRL_PIN(63, "PLGPIO63"),
82 PINCTRL_PIN(64, "PLGPIO64"),
83 PINCTRL_PIN(65, "PLGPIO65"),
84 PINCTRL_PIN(66, "PLGPIO66"),
85 PINCTRL_PIN(67, "PLGPIO67"),
86 PINCTRL_PIN(68, "PLGPIO68"),
87 PINCTRL_PIN(69, "PLGPIO69"),
88 PINCTRL_PIN(70, "PLGPIO70"),
89 PINCTRL_PIN(71, "PLGPIO71"),
90 PINCTRL_PIN(72, "PLGPIO72"),
91 PINCTRL_PIN(73, "PLGPIO73"),
92 PINCTRL_PIN(74, "PLGPIO74"),
93 PINCTRL_PIN(75, "PLGPIO75"),
94 PINCTRL_PIN(76, "PLGPIO76"),
95 PINCTRL_PIN(77, "PLGPIO77"),
96 PINCTRL_PIN(78, "PLGPIO78"),
97 PINCTRL_PIN(79, "PLGPIO79"),
98 PINCTRL_PIN(80, "PLGPIO80"),
99 PINCTRL_PIN(81, "PLGPIO81"),
100 PINCTRL_PIN(82, "PLGPIO82"),
101 PINCTRL_PIN(83, "PLGPIO83"),
102 PINCTRL_PIN(84, "PLGPIO84"),
103 PINCTRL_PIN(85, "PLGPIO85"),
104 PINCTRL_PIN(86, "PLGPIO86"),
105 PINCTRL_PIN(87, "PLGPIO87"),
106 PINCTRL_PIN(88, "PLGPIO88"),
107 PINCTRL_PIN(89, "PLGPIO89"),
108 PINCTRL_PIN(90, "PLGPIO90"),
109 PINCTRL_PIN(91, "PLGPIO91"),
110 PINCTRL_PIN(92, "PLGPIO92"),
111 PINCTRL_PIN(93, "PLGPIO93"),
112 PINCTRL_PIN(94, "PLGPIO94"),
113 PINCTRL_PIN(95, "PLGPIO95"),
114 PINCTRL_PIN(96, "PLGPIO96"),
115 PINCTRL_PIN(97, "PLGPIO97"),
116 PINCTRL_PIN(98, "PLGPIO98"),
117 PINCTRL_PIN(99, "PLGPIO99"),
118 PINCTRL_PIN(100, "PLGPIO100"),
119 PINCTRL_PIN(101, "PLGPIO101"),
120}; 19};
121 20
122/* firda_pins */ 21/* firda_pins */
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 00c024039c97..cd2fe350e724 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -311,7 +311,7 @@ config SPI_S3C24XX_FIQ
311 311
312config SPI_S3C64XX 312config SPI_S3C64XX
313 tristate "Samsung S3C64XX series type SPI" 313 tristate "Samsung S3C64XX series type SPI"
314 depends on (ARCH_S3C64XX || ARCH_S5P64X0 || ARCH_EXYNOS) 314 depends on (ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5P64X0 || ARCH_EXYNOS)
315 select S3C64XX_DMA if ARCH_S3C64XX 315 select S3C64XX_DMA if ARCH_S3C64XX
316 help 316 help
317 SPI driver for Samsung S3C64XX and newer SoCs. 317 SPI driver for Samsung S3C64XX and newer SoCs.
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-01 09:30:31 -0400