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-rw-r--r--Documentation/devicetree/bindings/arm/lpc32xx-mic.txt38
-rw-r--r--Documentation/devicetree/bindings/arm/lpc32xx.txt8
-rw-r--r--Documentation/devicetree/bindings/net/lpc-eth.txt24
-rw-r--r--arch/arm/Kconfig1
-rw-r--r--arch/arm/boot/dts/lpc32xx.dtsi292
-rw-r--r--arch/arm/boot/dts/phy3250.dts145
-rw-r--r--arch/arm/configs/lpc32xx_defconfig44
-rw-r--r--arch/arm/mach-lpc32xx/Kconfig26
-rw-r--r--arch/arm/mach-lpc32xx/clock.c77
-rw-r--r--arch/arm/mach-lpc32xx/common.c205
-rw-r--r--arch/arm/mach-lpc32xx/common.h14
-rw-r--r--arch/arm/mach-lpc32xx/irq.c78
-rw-r--r--arch/arm/mach-lpc32xx/phy3250.c149
-rw-r--r--drivers/net/ethernet/nxp/lpc_eth.c71
14 files changed, 754 insertions, 418 deletions
diff --git a/Documentation/devicetree/bindings/arm/lpc32xx-mic.txt b/Documentation/devicetree/bindings/arm/lpc32xx-mic.txt
new file mode 100644
index 000000000000..539adca19e8f
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/lpc32xx-mic.txt
@@ -0,0 +1,38 @@
1* NXP LPC32xx Main Interrupt Controller
2 (MIC, including SIC1 and SIC2 secondary controllers)
3
4Required properties:
5- compatible: Should be "nxp,lpc3220-mic"
6- interrupt-controller: Identifies the node as an interrupt controller.
7- interrupt-parent: Empty for the interrupt controller itself
8- #interrupt-cells: The number of cells to define the interrupts. Should be 2.
9 The first cell is the IRQ number
10 The second cell is used to specify mode:
11 1 = low-to-high edge triggered
12 2 = high-to-low edge triggered
13 4 = active high level-sensitive
14 8 = active low level-sensitive
15 Default for internal sources should be set to 4 (active high).
16- reg: Should contain MIC registers location and length
17
18Examples:
19 /*
20 * MIC
21 */
22 mic: interrupt-controller@40008000 {
23 compatible = "nxp,lpc3220-mic";
24 interrupt-controller;
25 interrupt-parent;
26 #interrupt-cells = <2>;
27 reg = <0x40008000 0xC000>;
28 };
29
30 /*
31 * ADC
32 */
33 adc@40048000 {
34 compatible = "nxp,lpc3220-adc";
35 reg = <0x40048000 0x1000>;
36 interrupt-parent = <&mic>;
37 interrupts = <39 4>;
38 };
diff --git a/Documentation/devicetree/bindings/arm/lpc32xx.txt b/Documentation/devicetree/bindings/arm/lpc32xx.txt
new file mode 100644
index 000000000000..56ec8ddc4a3b
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/lpc32xx.txt
@@ -0,0 +1,8 @@
1NXP LPC32xx Platforms Device Tree Bindings
2------------------------------------------
3
4Boards with the NXP LPC32xx SoC shall have the following properties:
5
6Required root node property:
7
8compatible: must be "nxp,lpc3220", "nxp,lpc3230", "nxp,lpc3240" or "nxp,lpc3250"
diff --git a/Documentation/devicetree/bindings/net/lpc-eth.txt b/Documentation/devicetree/bindings/net/lpc-eth.txt
new file mode 100644
index 000000000000..585021acd178
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/lpc-eth.txt
@@ -0,0 +1,24 @@
1* NXP LPC32xx SoC Ethernet Controller
2
3Required properties:
4- compatible: Should be "nxp,lpc-eth"
5- reg: Address and length of the register set for the device
6- interrupts: Should contain ethernet controller interrupt
7
8Optional properties:
9- phy-mode: String, operation mode of the PHY interface.
10 Supported values are: "mii", "rmii" (default)
11- use-iram: Use LPC32xx internal SRAM (IRAM) for DMA buffering
12- local-mac-address : 6 bytes, mac address
13
14Example:
15
16 mac: ethernet@31060000 {
17 compatible = "nxp,lpc-eth";
18 reg = <0x31060000 0x1000>;
19 interrupt-parent = <&mic>;
20 interrupts = <29 0>;
21
22 phy-mode = "rmii";
23 use-iram;
24 };
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index cf006d40342c..6e51ddde908a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -597,6 +597,7 @@ config ARCH_LPC32XX
597 select USB_ARCH_HAS_OHCI 597 select USB_ARCH_HAS_OHCI
598 select CLKDEV_LOOKUP 598 select CLKDEV_LOOKUP
599 select GENERIC_CLOCKEVENTS 599 select GENERIC_CLOCKEVENTS
600 select USE_OF
600 help 601 help
601 Support for the NXP LPC32XX family of processors 602 Support for the NXP LPC32XX family of processors
602 603
diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
new file mode 100644
index 000000000000..2d696866f71c
--- /dev/null
+++ b/arch/arm/boot/dts/lpc32xx.dtsi
@@ -0,0 +1,292 @@
1/*
2 * NXP LPC32xx SoC
3 *
4 * Copyright 2012 Roland Stigge <stigge@antcom.de>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "skeleton.dtsi"
15
16/ {
17 compatible = "nxp,lpc3220";
18 interrupt-parent = <&mic>;
19
20 cpus {
21 cpu@0 {
22 compatible = "arm,arm926ejs";
23 };
24 };
25
26 ahb {
27 #address-cells = <1>;
28 #size-cells = <1>;
29 compatible = "simple-bus";
30 ranges = <0x20000000 0x20000000 0x30000000>;
31
32 /*
33 * Enable either SLC or MLC
34 */
35 slc: flash@20020000 {
36 compatible = "nxp,lpc3220-slc";
37 reg = <0x20020000 0x1000>;
38 status = "disable";
39 };
40
41 mlc: flash@200B0000 {
42 compatible = "nxp,lpc3220-mlc";
43 reg = <0x200B0000 0x1000>;
44 status = "disable";
45 };
46
47 dma@31000000 {
48 compatible = "arm,pl080", "arm,primecell";
49 reg = <0x31000000 0x1000>;
50 interrupts = <0x1c 0>;
51 };
52
53 /*
54 * Enable either ohci or usbd (gadget)!
55 */
56 ohci@31020000 {
57 compatible = "nxp,ohci-nxp", "usb-ohci";
58 reg = <0x31020000 0x300>;
59 interrupts = <0x3b 0>;
60 status = "disable";
61 };
62
63 usbd@31020000 {
64 compatible = "nxp,lpc3220-udc";
65 reg = <0x31020000 0x300>;
66 interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>;
67 status = "disable";
68 };
69
70 clcd@31040000 {
71 compatible = "arm,pl110", "arm,primecell";
72 reg = <0x31040000 0x1000>;
73 interrupts = <0x0e 0>;
74 status = "disable";
75 };
76
77 mac: ethernet@31060000 {
78 compatible = "nxp,lpc-eth";
79 reg = <0x31060000 0x1000>;
80 interrupts = <0x1d 0>;
81 };
82
83 apb {
84 #address-cells = <1>;
85 #size-cells = <1>;
86 compatible = "simple-bus";
87 ranges = <0x20000000 0x20000000 0x30000000>;
88
89 ssp0: ssp@20084000 {
90 compatible = "arm,pl022", "arm,primecell";
91 reg = <0x20084000 0x1000>;
92 interrupts = <0x14 0>;
93 };
94
95 spi1: spi@20088000 {
96 compatible = "nxp,lpc3220-spi";
97 reg = <0x20088000 0x1000>;
98 };
99
100 ssp1: ssp@2008c000 {
101 compatible = "arm,pl022", "arm,primecell";
102 reg = <0x2008c000 0x1000>;
103 interrupts = <0x15 0>;
104 };
105
106 spi2: spi@20090000 {
107 compatible = "nxp,lpc3220-spi";
108 reg = <0x20090000 0x1000>;
109 };
110
111 i2s0: i2s@20094000 {
112 compatible = "nxp,lpc3220-i2s";
113 reg = <0x20094000 0x1000>;
114 };
115
116 sd@20098000 {
117 compatible = "arm,pl180", "arm,primecell";
118 reg = <0x20098000 0x1000>;
119 interrupts = <0x0f 0>, <0x0d 0>;
120 };
121
122 i2s1: i2s@2009C000 {
123 compatible = "nxp,lpc3220-i2s";
124 reg = <0x2009C000 0x1000>;
125 };
126
127 uart3: serial@40080000 {
128 compatible = "nxp,serial";
129 reg = <0x40080000 0x1000>;
130 };
131
132 uart4: serial@40088000 {
133 compatible = "nxp,serial";
134 reg = <0x40088000 0x1000>;
135 };
136
137 uart5: serial@40090000 {
138 compatible = "nxp,serial";
139 reg = <0x40090000 0x1000>;
140 };
141
142 uart6: serial@40098000 {
143 compatible = "nxp,serial";
144 reg = <0x40098000 0x1000>;
145 };
146
147 i2c1: i2c@400A0000 {
148 compatible = "nxp,pnx-i2c";
149 reg = <0x400A0000 0x100>;
150 interrupts = <0x33 0>;
151 #address-cells = <1>;
152 #size-cells = <0>;
153 pnx,timeout = <0x64>;
154 };
155
156 i2c2: i2c@400A8000 {
157 compatible = "nxp,pnx-i2c";
158 reg = <0x400A8000 0x100>;
159 interrupts = <0x32 0>;
160 #address-cells = <1>;
161 #size-cells = <0>;
162 pnx,timeout = <0x64>;
163 };
164
165 i2cusb: i2c@31020300 {
166 compatible = "nxp,pnx-i2c";
167 reg = <0x31020300 0x100>;
168 interrupts = <0x3f 0>;
169 #address-cells = <1>;
170 #size-cells = <0>;
171 pnx,timeout = <0x64>;
172 };
173 };
174
175 fab {
176 #address-cells = <1>;
177 #size-cells = <1>;
178 compatible = "simple-bus";
179 ranges = <0x20000000 0x20000000 0x30000000>;
180
181 /*
182 * MIC Interrupt controller includes:
183 * MIC @40008000
184 * SIC1 @4000C000
185 * SIC2 @40010000
186 */
187 mic: interrupt-controller@40008000 {
188 compatible = "nxp,lpc3220-mic";
189 interrupt-controller;
190 reg = <0x40008000 0xC000>;
191 #interrupt-cells = <2>;
192 };
193
194 uart1: serial@40014000 {
195 compatible = "nxp,serial";
196 reg = <0x40014000 0x1000>;
197 };
198
199 uart2: serial@40018000 {
200 compatible = "nxp,serial";
201 reg = <0x40018000 0x1000>;
202 };
203
204 uart7: serial@4001C000 {
205 compatible = "nxp,serial";
206 reg = <0x4001C000 0x1000>;
207 };
208
209 rtc@40024000 {
210 compatible = "nxp,lpc3220-rtc";
211 reg = <0x40024000 0x1000>;
212 interrupts = <0x34 0>;
213 };
214
215 gpio: gpio@40028000 {
216 compatible = "nxp,lpc3220-gpio";
217 reg = <0x40028000 0x1000>;
218 /* create a private address space for enumeration */
219 #address-cells = <1>;
220 #size-cells = <0>;
221
222 gpio_p0: gpio-bank@0 {
223 gpio-controller;
224 #gpio-cells = <2>;
225 reg = <0>;
226 };
227
228 gpio_p1: gpio-bank@1 {
229 gpio-controller;
230 #gpio-cells = <2>;
231 reg = <1>;
232 };
233
234 gpio_p2: gpio-bank@2 {
235 gpio-controller;
236 #gpio-cells = <2>;
237 reg = <2>;
238 };
239
240 gpio_p3: gpio-bank@3 {
241 gpio-controller;
242 #gpio-cells = <2>;
243 reg = <3>;
244 };
245
246 gpi_p3: gpio-bank@4 {
247 gpio-controller;
248 #gpio-cells = <2>;
249 reg = <4>;
250 };
251
252 gpo_p3: gpio-bank@5 {
253 gpio-controller;
254 #gpio-cells = <2>;
255 reg = <5>;
256 };
257 };
258
259 watchdog@4003C000 {
260 compatible = "nxp,pnx4008-wdt";
261 reg = <0x4003C000 0x1000>;
262 };
263
264 /*
265 * TSC vs. ADC: Since those two share the same
266 * hardware, you need to choose from one of the
267 * following two and do 'status = "okay";' for one of
268 * them
269 */
270
271 adc@40048000 {
272 compatible = "nxp,lpc3220-adc";
273 reg = <0x40048000 0x1000>;
274 interrupts = <0x27 0>;
275 status = "disable";
276 };
277
278 tsc@40048000 {
279 compatible = "nxp,lpc3220-tsc";
280 reg = <0x40048000 0x1000>;
281 interrupts = <0x27 0>;
282 status = "disable";
283 };
284
285 key@40050000 {
286 compatible = "nxp,lpc3220-key";
287 reg = <0x40050000 0x1000>;
288 };
289
290 };
291 };
292};
diff --git a/arch/arm/boot/dts/phy3250.dts b/arch/arm/boot/dts/phy3250.dts
new file mode 100644
index 000000000000..0167e86314c0
--- /dev/null
+++ b/arch/arm/boot/dts/phy3250.dts
@@ -0,0 +1,145 @@
1/*
2 * PHYTEC phyCORE-LPC3250 board
3 *
4 * Copyright 2012 Roland Stigge <stigge@antcom.de>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15/include/ "lpc32xx.dtsi"
16
17/ {
18 model = "PHYTEC phyCORE-LPC3250 board based on NXP LPC3250";
19 compatible = "phytec,phy3250", "nxp,lpc3250";
20 #address-cells = <1>;
21 #size-cells = <1>;
22
23 memory {
24 device_type = "memory";
25 reg = <0 0x4000000>;
26 };
27
28 ahb {
29 mac: ethernet@31060000 {
30 phy-mode = "rmii";
31 use-iram;
32 };
33
34 /* Here, choose exactly one from: ohci, usbd */
35 ohci@31020000 {
36 transceiver = <&isp1301>;
37 status = "okay";
38 };
39
40/*
41 usbd@31020000 {
42 transceiver = <&isp1301>;
43 status = "okay";
44 };
45*/
46
47 clcd@31040000 {
48 status = "okay";
49 };
50
51 /* 64MB Flash via SLC NAND controller */
52 slc: flash@20020000 {
53 status = "okay";
54 #address-cells = <1>;
55 #size-cells = <1>;
56
57 mtd0@00000000 {
58 label = "phy3250-boot";
59 reg = <0x00000000 0x00064000>;
60 read-only;
61 };
62
63 mtd1@00064000 {
64 label = "phy3250-uboot";
65 reg = <0x00064000 0x00190000>;
66 read-only;
67 };
68
69 mtd2@001f4000 {
70 label = "phy3250-ubt-prms";
71 reg = <0x001f4000 0x00010000>;
72 };
73
74 mtd3@00204000 {
75 label = "phy3250-kernel";
76 reg = <0x00204000 0x00400000>;
77 };
78
79 mtd4@00604000 {
80 label = "phy3250-rootfs";
81 reg = <0x00604000 0x039fc000>;
82 };
83 };
84
85 apb {
86 i2c1: i2c@400A0000 {
87 clock-frequency = <100000>;
88
89 pcf8563: rtc@51 {
90 compatible = "nxp,pcf8563";
91 reg = <0x51>;
92 };
93
94 uda1380: uda1380@18 {
95 compatible = "nxp,uda1380";
96 reg = <0x18>;
97 power-gpio = <&gpio 0x59 0>;
98 reset-gpio = <&gpio 0x51 0>;
99 dac-clk = "wspll";
100 };
101 };
102
103 i2c2: i2c@400A8000 {
104 clock-frequency = <100000>;
105 };
106
107 i2cusb: i2c@31020300 {
108 clock-frequency = <100000>;
109
110 isp1301: usb-transceiver@2c {
111 compatible = "nxp,isp1301";
112 reg = <0x2c>;
113 };
114 };
115
116 ssp0: ssp@20084000 {
117 eeprom: at25@0 {
118 compatible = "atmel,at25";
119 };
120 };
121 };
122
123 fab {
124 tsc@40048000 {
125 status = "okay";
126 };
127 };
128 };
129
130 leds {
131 compatible = "gpio-leds";
132
133 led0 {
134 gpios = <&gpo_p3 1 1>; /* GPO_P3 1, GPIO 80, active low */
135 linux,default-trigger = "heartbeat";
136 default-state = "off";
137 };
138
139 led1 {
140 gpios = <&gpo_p3 14 1>; /* GPO_P3 14, GPIO 93, active low */
141 linux,default-trigger = "timer";
142 default-state = "off";
143 };
144 };
145};
diff --git a/arch/arm/configs/lpc32xx_defconfig b/arch/arm/configs/lpc32xx_defconfig
index fb2088171ca9..4fa60547494a 100644
--- a/arch/arm/configs/lpc32xx_defconfig
+++ b/arch/arm/configs/lpc32xx_defconfig
@@ -2,7 +2,7 @@ CONFIG_EXPERIMENTAL=y
2CONFIG_SYSVIPC=y 2CONFIG_SYSVIPC=y
3CONFIG_IKCONFIG=y 3CONFIG_IKCONFIG=y
4CONFIG_IKCONFIG_PROC=y 4CONFIG_IKCONFIG_PROC=y
5CONFIG_LOG_BUF_SHIFT=14 5CONFIG_LOG_BUF_SHIFT=16
6CONFIG_SYSFS_DEPRECATED=y 6CONFIG_SYSFS_DEPRECATED=y
7CONFIG_SYSFS_DEPRECATED_V2=y 7CONFIG_SYSFS_DEPRECATED_V2=y
8CONFIG_BLK_DEV_INITRD=y 8CONFIG_BLK_DEV_INITRD=y
@@ -10,6 +10,7 @@ CONFIG_CC_OPTIMIZE_FOR_SIZE=y
10CONFIG_SYSCTL_SYSCALL=y 10CONFIG_SYSCTL_SYSCALL=y
11CONFIG_EMBEDDED=y 11CONFIG_EMBEDDED=y
12CONFIG_SLAB=y 12CONFIG_SLAB=y
13CONFIG_JUMP_LABEL=y
13CONFIG_MODULES=y 14CONFIG_MODULES=y
14CONFIG_MODULE_UNLOAD=y 15CONFIG_MODULE_UNLOAD=y
15# CONFIG_BLK_DEV_BSG is not set 16# CONFIG_BLK_DEV_BSG is not set
@@ -21,6 +22,8 @@ CONFIG_PREEMPT=y
21CONFIG_AEABI=y 22CONFIG_AEABI=y
22CONFIG_ZBOOT_ROM_TEXT=0x0 23CONFIG_ZBOOT_ROM_TEXT=0x0
23CONFIG_ZBOOT_ROM_BSS=0x0 24CONFIG_ZBOOT_ROM_BSS=0x0
25CONFIG_ARM_APPENDED_DTB=y
26CONFIG_ARM_ATAG_DTB_COMPAT=y
24CONFIG_CMDLINE="console=ttyS0,115200n81 root=/dev/ram0" 27CONFIG_CMDLINE="console=ttyS0,115200n81 root=/dev/ram0"
25CONFIG_CPU_IDLE=y 28CONFIG_CPU_IDLE=y
26CONFIG_FPE_NWFPE=y 29CONFIG_FPE_NWFPE=y
@@ -40,7 +43,8 @@ CONFIG_IP_PNP_BOOTP=y
40# CONFIG_INET_XFRM_MODE_BEET is not set 43# CONFIG_INET_XFRM_MODE_BEET is not set
41# CONFIG_INET_LRO is not set 44# CONFIG_INET_LRO is not set
42# CONFIG_INET_DIAG is not set 45# CONFIG_INET_DIAG is not set
43# CONFIG_IPV6 is not set 46CONFIG_IPV6=y
47CONFIG_IPV6_PRIVACY=y
44# CONFIG_WIRELESS is not set 48# CONFIG_WIRELESS is not set
45CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 49CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
46# CONFIG_FW_LOADER is not set 50# CONFIG_FW_LOADER is not set
@@ -55,13 +59,24 @@ CONFIG_BLK_DEV_CRYPTOLOOP=y
55CONFIG_BLK_DEV_RAM=y 59CONFIG_BLK_DEV_RAM=y
56CONFIG_BLK_DEV_RAM_COUNT=1 60CONFIG_BLK_DEV_RAM_COUNT=1
57CONFIG_BLK_DEV_RAM_SIZE=16384 61CONFIG_BLK_DEV_RAM_SIZE=16384
58CONFIG_MISC_DEVICES=y
59CONFIG_EEPROM_AT25=y 62CONFIG_EEPROM_AT25=y
60CONFIG_SCSI=y 63CONFIG_SCSI=y
61CONFIG_BLK_DEV_SD=y 64CONFIG_BLK_DEV_SD=y
62CONFIG_NETDEVICES=y 65CONFIG_NETDEVICES=y
63CONFIG_MII=y 66CONFIG_MII=y
64CONFIG_PHYLIB=y 67# CONFIG_NET_VENDOR_BROADCOM is not set
68# CONFIG_NET_VENDOR_CHELSIO is not set
69# CONFIG_NET_VENDOR_CIRRUS is not set
70# CONFIG_NET_VENDOR_FARADAY is not set
71# CONFIG_NET_VENDOR_INTEL is not set
72# CONFIG_NET_VENDOR_MARVELL is not set
73# CONFIG_NET_VENDOR_MICREL is not set
74# CONFIG_NET_VENDOR_MICROCHIP is not set
75# CONFIG_NET_VENDOR_NATSEMI is not set
76CONFIG_LPC_ENET=y
77# CONFIG_NET_VENDOR_SEEQ is not set
78# CONFIG_NET_VENDOR_SMSC is not set
79# CONFIG_NET_VENDOR_STMICRO is not set
65CONFIG_SMSC_PHY=y 80CONFIG_SMSC_PHY=y
66# CONFIG_WLAN is not set 81# CONFIG_WLAN is not set
67# CONFIG_INPUT_MOUSEDEV_PSAUX is not set 82# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
@@ -97,16 +112,22 @@ CONFIG_SND_SEQUENCER=y
97CONFIG_SND_MIXER_OSS=y 112CONFIG_SND_MIXER_OSS=y
98CONFIG_SND_PCM_OSS=y 113CONFIG_SND_PCM_OSS=y
99CONFIG_SND_SEQUENCER_OSS=y 114CONFIG_SND_SEQUENCER_OSS=y
100CONFIG_SND_DYNAMIC_MINORS=y 115# CONFIG_SND_SUPPORT_OLD_API is not set
101# CONFIG_SND_VERBOSE_PROCFS is not set 116# CONFIG_SND_VERBOSE_PROCFS is not set
117CONFIG_SND_DEBUG=y
118CONFIG_SND_DEBUG_VERBOSE=y
102# CONFIG_SND_DRIVERS is not set 119# CONFIG_SND_DRIVERS is not set
103# CONFIG_SND_ARM is not set 120# CONFIG_SND_ARM is not set
104# CONFIG_SND_SPI is not set 121# CONFIG_SND_SPI is not set
105CONFIG_SND_SOC=y 122CONFIG_SND_SOC=y
106# CONFIG_HID_SUPPORT is not set 123# CONFIG_HID_SUPPORT is not set
107CONFIG_USB=y 124CONFIG_USB=y
125CONFIG_USB_OHCI_HCD=y
108CONFIG_USB_STORAGE=y 126CONFIG_USB_STORAGE=y
109CONFIG_USB_LIBUSUAL=y 127CONFIG_USB_GADGET=y
128CONFIG_USB_LPC32XX=y
129CONFIG_USB_MASS_STORAGE=m
130CONFIG_USB_G_SERIAL=m
110CONFIG_MMC=y 131CONFIG_MMC=y
111# CONFIG_MMC_BLOCK_BOUNCE is not set 132# CONFIG_MMC_BLOCK_BOUNCE is not set
112CONFIG_MMC_ARMMMCI=y 133CONFIG_MMC_ARMMMCI=y
@@ -114,10 +135,21 @@ CONFIG_NEW_LEDS=y
114CONFIG_LEDS_CLASS=y 135CONFIG_LEDS_CLASS=y
115CONFIG_LEDS_GPIO=y 136CONFIG_LEDS_GPIO=y
116CONFIG_LEDS_TRIGGERS=y 137CONFIG_LEDS_TRIGGERS=y
138CONFIG_LEDS_TRIGGER_TIMER=y
117CONFIG_LEDS_TRIGGER_HEARTBEAT=y 139CONFIG_LEDS_TRIGGER_HEARTBEAT=y
140CONFIG_LEDS_TRIGGER_BACKLIGHT=y
141CONFIG_LEDS_TRIGGER_GPIO=y
142CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
118CONFIG_RTC_CLASS=y 143CONFIG_RTC_CLASS=y
119CONFIG_RTC_INTF_DEV_UIE_EMUL=y 144CONFIG_RTC_INTF_DEV_UIE_EMUL=y
145CONFIG_RTC_DRV_DS1374=y
146CONFIG_RTC_DRV_PCF8563=y
120CONFIG_RTC_DRV_LPC32XX=y 147CONFIG_RTC_DRV_LPC32XX=y
148CONFIG_DMADEVICES=y
149CONFIG_AMBA_PL08X=y
150CONFIG_STAGING=y
151CONFIG_IIO=y
152CONFIG_LPC32XX_ADC=y
121CONFIG_EXT2_FS=y 153CONFIG_EXT2_FS=y
122CONFIG_AUTOFS4_FS=y 154CONFIG_AUTOFS4_FS=y
123CONFIG_MSDOS_FS=y 155CONFIG_MSDOS_FS=y
diff --git a/arch/arm/mach-lpc32xx/Kconfig b/arch/arm/mach-lpc32xx/Kconfig
index 75946ac89ee9..e0b3eee83834 100644
--- a/arch/arm/mach-lpc32xx/Kconfig
+++ b/arch/arm/mach-lpc32xx/Kconfig
@@ -29,30 +29,4 @@ config ARCH_LPC32XX_UART6_SELECT
29 29
30endmenu 30endmenu
31 31
32menu "LPC32XX chip components"
33
34config ARCH_LPC32XX_IRAM_FOR_NET
35 bool "Use IRAM for network buffers"
36 default y
37 help
38 Say Y here to use the LPC internal fast IRAM (i.e. 256KB SRAM) as
39 network buffer. If the total combined required buffer sizes is
40 larger than the size of IRAM, then SDRAM will be used instead.
41
42 This can be enabled safely if the IRAM is not intended for other
43 uses.
44
45config ARCH_LPC32XX_MII_SUPPORT
46 bool "Check to enable MII support or leave disabled for RMII support"
47 help
48 Say Y here to enable MII support, or N for RMII support. Regardless of
49 which support is selected, the ethernet interface driver needs to be
50 selected in the device driver networking section.
51
52 The PHY3250 reference board uses RMII, so users of this board should
53 say N.
54
55endmenu
56
57endif 32endif
58
diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c
index 2fc24ca12054..f6a3ffec1f4b 100644
--- a/arch/arm/mach-lpc32xx/clock.c
+++ b/arch/arm/mach-lpc32xx/clock.c
@@ -1095,49 +1095,42 @@ struct clk *clk_get_parent(struct clk *clk)
1095} 1095}
1096EXPORT_SYMBOL(clk_get_parent); 1096EXPORT_SYMBOL(clk_get_parent);
1097 1097
1098#define _REGISTER_CLOCK(d, n, c) \
1099 { \
1100 .dev_id = (d), \
1101 .con_id = (n), \
1102 .clk = &(c), \
1103 },
1104
1105static struct clk_lookup lookups[] = { 1098static struct clk_lookup lookups[] = {
1106 _REGISTER_CLOCK(NULL, "osc_32KHz", osc_32KHz) 1099 CLKDEV_INIT(NULL, "osc_32KHz", &osc_32KHz),
1107 _REGISTER_CLOCK(NULL, "osc_pll397", osc_pll397) 1100 CLKDEV_INIT(NULL, "osc_pll397", &osc_pll397),
1108 _REGISTER_CLOCK(NULL, "osc_main", osc_main) 1101 CLKDEV_INIT(NULL, "osc_main", &osc_main),
1109 _REGISTER_CLOCK(NULL, "sys_ck", clk_sys) 1102 CLKDEV_INIT(NULL, "sys_ck", &clk_sys),
1110 _REGISTER_CLOCK(NULL, "arm_pll_ck", clk_armpll) 1103 CLKDEV_INIT(NULL, "arm_pll_ck", &clk_armpll),
1111 _REGISTER_CLOCK(NULL, "ck_pll5", clk_usbpll) 1104 CLKDEV_INIT(NULL, "ck_pll5", &clk_usbpll),
1112 _REGISTER_CLOCK(NULL, "hclk_ck", clk_hclk) 1105 CLKDEV_INIT(NULL, "hclk_ck", &clk_hclk),
1113 _REGISTER_CLOCK(NULL, "pclk_ck", clk_pclk) 1106 CLKDEV_INIT(NULL, "pclk_ck", &clk_pclk),
1114 _REGISTER_CLOCK(NULL, "timer0_ck", clk_timer0) 1107 CLKDEV_INIT(NULL, "timer0_ck", &clk_timer0),
1115 _REGISTER_CLOCK(NULL, "timer1_ck", clk_timer1) 1108 CLKDEV_INIT(NULL, "timer1_ck", &clk_timer1),
1116 _REGISTER_CLOCK(NULL, "timer2_ck", clk_timer2) 1109 CLKDEV_INIT(NULL, "timer2_ck", &clk_timer2),
1117 _REGISTER_CLOCK(NULL, "timer3_ck", clk_timer3) 1110 CLKDEV_INIT(NULL, "timer3_ck", &clk_timer3),
1118 _REGISTER_CLOCK(NULL, "vfp9_ck", clk_vfp9) 1111 CLKDEV_INIT(NULL, "vfp9_ck", &clk_vfp9),
1119 _REGISTER_CLOCK(NULL, "clk_dmac", clk_dma) 1112 CLKDEV_INIT("pl08xdmac", NULL, &clk_dma),
1120 _REGISTER_CLOCK("pnx4008-watchdog", NULL, clk_wdt) 1113 CLKDEV_INIT("4003c000.watchdog", NULL, &clk_wdt),
1121 _REGISTER_CLOCK(NULL, "uart3_ck", clk_uart3) 1114 CLKDEV_INIT(NULL, "uart3_ck", &clk_uart3),
1122 _REGISTER_CLOCK(NULL, "uart4_ck", clk_uart4) 1115 CLKDEV_INIT(NULL, "uart4_ck", &clk_uart4),
1123 _REGISTER_CLOCK(NULL, "uart5_ck", clk_uart5) 1116 CLKDEV_INIT(NULL, "uart5_ck", &clk_uart5),
1124 _REGISTER_CLOCK(NULL, "uart6_ck", clk_uart6) 1117 CLKDEV_INIT(NULL, "uart6_ck", &clk_uart6),
1125 _REGISTER_CLOCK("pnx-i2c.0", NULL, clk_i2c0) 1118 CLKDEV_INIT("400a0000.i2c", NULL, &clk_i2c0),
1126 _REGISTER_CLOCK("pnx-i2c.1", NULL, clk_i2c1) 1119 CLKDEV_INIT("400a8000.i2c", NULL, &clk_i2c1),
1127 _REGISTER_CLOCK("pnx-i2c.2", NULL, clk_i2c2) 1120 CLKDEV_INIT("31020300.i2c", NULL, &clk_i2c2),
1128 _REGISTER_CLOCK("dev:ssp0", NULL, clk_ssp0) 1121 CLKDEV_INIT("dev:ssp0", NULL, &clk_ssp0),
1129 _REGISTER_CLOCK("dev:ssp1", NULL, clk_ssp1) 1122 CLKDEV_INIT("dev:ssp1", NULL, &clk_ssp1),
1130 _REGISTER_CLOCK("lpc32xx_keys.0", NULL, clk_kscan) 1123 CLKDEV_INIT("lpc32xx_keys.0", NULL, &clk_kscan),
1131 _REGISTER_CLOCK("lpc32xx-nand.0", "nand_ck", clk_nand) 1124 CLKDEV_INIT("lpc32xx-nand.0", "nand_ck", &clk_nand),
1132 _REGISTER_CLOCK("lpc32xx-adc", NULL, clk_adc) 1125 CLKDEV_INIT("40048000.adc", NULL, &clk_adc),
1133 _REGISTER_CLOCK(NULL, "i2s0_ck", clk_i2s0) 1126 CLKDEV_INIT(NULL, "i2s0_ck", &clk_i2s0),
1134 _REGISTER_CLOCK(NULL, "i2s1_ck", clk_i2s1) 1127 CLKDEV_INIT(NULL, "i2s1_ck", &clk_i2s1),
1135 _REGISTER_CLOCK("ts-lpc32xx", NULL, clk_tsc) 1128 CLKDEV_INIT("40048000.tsc", NULL, &clk_tsc),
1136 _REGISTER_CLOCK("dev:mmc0", NULL, clk_mmc) 1129 CLKDEV_INIT("20098000.sd", NULL, &clk_mmc),
1137 _REGISTER_CLOCK("lpc-eth.0", NULL, clk_net) 1130 CLKDEV_INIT("31060000.ethernet", NULL, &clk_net),
1138 _REGISTER_CLOCK("dev:clcd", NULL, clk_lcd) 1131 CLKDEV_INIT("dev:clcd", NULL, &clk_lcd),
1139 _REGISTER_CLOCK("lpc32xx_udc", "ck_usbd", clk_usbd) 1132 CLKDEV_INIT("31020000.usbd", "ck_usbd", &clk_usbd),
1140 _REGISTER_CLOCK("lpc32xx_rtc", NULL, clk_rtc) 1133 CLKDEV_INIT("lpc32xx_rtc", NULL, &clk_rtc),
1141}; 1134};
1142 1135
1143static int __init clk_init(void) 1136static int __init clk_init(void)
diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c
index 6f255600fc97..5c96057b6d78 100644
--- a/arch/arm/mach-lpc32xx/common.c
+++ b/arch/arm/mach-lpc32xx/common.c
@@ -32,198 +32,6 @@
32#include "common.h" 32#include "common.h"
33 33
34/* 34/*
35 * Watchdog timer
36 */
37static struct resource watchdog_resources[] = {
38 [0] = {
39 .start = LPC32XX_WDTIM_BASE,
40 .end = LPC32XX_WDTIM_BASE + SZ_4K - 1,
41 .flags = IORESOURCE_MEM,
42 },
43};
44
45struct platform_device lpc32xx_watchdog_device = {
46 .name = "pnx4008-watchdog",
47 .id = -1,
48 .num_resources = ARRAY_SIZE(watchdog_resources),
49 .resource = watchdog_resources,
50};
51
52/*
53 * I2C busses
54 */
55static struct resource i2c0_resources[] = {
56 [0] = {
57 .start = LPC32XX_I2C1_BASE,
58 .end = LPC32XX_I2C1_BASE + 0x100 - 1,
59 .flags = IORESOURCE_MEM,
60 },
61 [1] = {
62 .start = IRQ_LPC32XX_I2C_1,
63 .end = IRQ_LPC32XX_I2C_1,
64 .flags = IORESOURCE_IRQ,
65 },
66};
67
68static struct resource i2c1_resources[] = {
69 [0] = {
70 .start = LPC32XX_I2C2_BASE,
71 .end = LPC32XX_I2C2_BASE + 0x100 - 1,
72 .flags = IORESOURCE_MEM,
73 },
74 [1] = {
75 .start = IRQ_LPC32XX_I2C_2,
76 .end = IRQ_LPC32XX_I2C_2,
77 .flags = IORESOURCE_IRQ,
78 },
79};
80
81static struct resource i2c2_resources[] = {
82 [0] = {
83 .start = LPC32XX_OTG_I2C_BASE,
84 .end = LPC32XX_OTG_I2C_BASE + 0x100 - 1,
85 .flags = IORESOURCE_MEM,
86 },
87 [1] = {
88 .start = IRQ_LPC32XX_USB_I2C,
89 .end = IRQ_LPC32XX_USB_I2C,
90 .flags = IORESOURCE_IRQ,
91 },
92};
93
94struct platform_device lpc32xx_i2c0_device = {
95 .name = "pnx-i2c.0",
96 .id = 0,
97 .num_resources = ARRAY_SIZE(i2c0_resources),
98 .resource = i2c0_resources,
99};
100
101struct platform_device lpc32xx_i2c1_device = {
102 .name = "pnx-i2c.1",
103 .id = 1,
104 .num_resources = ARRAY_SIZE(i2c1_resources),
105 .resource = i2c1_resources,
106};
107
108struct platform_device lpc32xx_i2c2_device = {
109 .name = "pnx-i2c.2",
110 .id = 2,
111 .num_resources = ARRAY_SIZE(i2c2_resources),
112 .resource = i2c2_resources,
113};
114
115/* TSC (Touch Screen Controller) */
116
117static struct resource lpc32xx_tsc_resources[] = {
118 {
119 .start = LPC32XX_ADC_BASE,
120 .end = LPC32XX_ADC_BASE + SZ_4K - 1,
121 .flags = IORESOURCE_MEM,
122 }, {
123 .start = IRQ_LPC32XX_TS_IRQ,
124 .end = IRQ_LPC32XX_TS_IRQ,
125 .flags = IORESOURCE_IRQ,
126 },
127};
128
129struct platform_device lpc32xx_tsc_device = {
130 .name = "ts-lpc32xx",
131 .id = -1,
132 .num_resources = ARRAY_SIZE(lpc32xx_tsc_resources),
133 .resource = lpc32xx_tsc_resources,
134};
135
136/* RTC */
137
138static struct resource lpc32xx_rtc_resources[] = {
139 {
140 .start = LPC32XX_RTC_BASE,
141 .end = LPC32XX_RTC_BASE + SZ_4K - 1,
142 .flags = IORESOURCE_MEM,
143 },{
144 .start = IRQ_LPC32XX_RTC,
145 .end = IRQ_LPC32XX_RTC,
146 .flags = IORESOURCE_IRQ,
147 },
148};
149
150struct platform_device lpc32xx_rtc_device = {
151 .name = "rtc-lpc32xx",
152 .id = -1,
153 .num_resources = ARRAY_SIZE(lpc32xx_rtc_resources),
154 .resource = lpc32xx_rtc_resources,
155};
156
157/*
158 * ADC support
159 */
160static struct resource adc_resources[] = {
161 {
162 .start = LPC32XX_ADC_BASE,
163 .end = LPC32XX_ADC_BASE + SZ_4K - 1,
164 .flags = IORESOURCE_MEM,
165 }, {
166 .start = IRQ_LPC32XX_TS_IRQ,
167 .end = IRQ_LPC32XX_TS_IRQ,
168 .flags = IORESOURCE_IRQ,
169 },
170};
171
172struct platform_device lpc32xx_adc_device = {
173 .name = "lpc32xx-adc",
174 .id = -1,
175 .num_resources = ARRAY_SIZE(adc_resources),
176 .resource = adc_resources,
177};
178
179/*
180 * USB support
181 */
182/* The dmamask must be set for OHCI to work */
183static u64 ohci_dmamask = ~(u32) 0;
184static struct resource ohci_resources[] = {
185 {
186 .start = IO_ADDRESS(LPC32XX_USB_BASE),
187 .end = IO_ADDRESS(LPC32XX_USB_BASE + 0x100 - 1),
188 .flags = IORESOURCE_MEM,
189 }, {
190 .start = IRQ_LPC32XX_USB_HOST,
191 .flags = IORESOURCE_IRQ,
192 },
193};
194struct platform_device lpc32xx_ohci_device = {
195 .name = "usb-ohci",
196 .id = -1,
197 .dev = {
198 .dma_mask = &ohci_dmamask,
199 .coherent_dma_mask = 0xFFFFFFFF,
200 },
201 .num_resources = ARRAY_SIZE(ohci_resources),
202 .resource = ohci_resources,
203};
204
205/*
206 * Network Support
207 */
208static struct resource net_resources[] = {
209 [0] = DEFINE_RES_MEM(LPC32XX_ETHERNET_BASE, SZ_4K),
210 [1] = DEFINE_RES_MEM(LPC32XX_IRAM_BASE, SZ_128K),
211 [2] = DEFINE_RES_IRQ(IRQ_LPC32XX_ETHERNET),
212};
213
214static u64 lpc32xx_mac_dma_mask = 0xffffffffUL;
215struct platform_device lpc32xx_net_device = {
216 .name = "lpc-eth",
217 .id = 0,
218 .dev = {
219 .dma_mask = &lpc32xx_mac_dma_mask,
220 .coherent_dma_mask = 0xffffffffUL,
221 },
222 .num_resources = ARRAY_SIZE(net_resources),
223 .resource = net_resources,
224};
225
226/*
227 * Returns the unique ID for the device 35 * Returns the unique ID for the device
228 */ 36 */
229void lpc32xx_get_uid(u32 devid[4]) 37void lpc32xx_get_uid(u32 devid[4])
@@ -415,3 +223,16 @@ void lpc23xx_restart(char mode, const char *cmd)
415 while (1) 223 while (1)
416 ; 224 ;
417} 225}
226
227static int __init lpc32xx_display_uid(void)
228{
229 u32 uid[4];
230
231 lpc32xx_get_uid(uid);
232
233 printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n",
234 uid[3], uid[2], uid[1], uid[0]);
235
236 return 1;
237}
238arch_initcall(lpc32xx_display_uid);
diff --git a/arch/arm/mach-lpc32xx/common.h b/arch/arm/mach-lpc32xx/common.h
index 68e45e8c9486..afeac3b1fae6 100644
--- a/arch/arm/mach-lpc32xx/common.h
+++ b/arch/arm/mach-lpc32xx/common.h
@@ -23,26 +23,12 @@
23#include <linux/platform_device.h> 23#include <linux/platform_device.h>
24 24
25/* 25/*
26 * Arch specific platform device structures
27 */
28extern struct platform_device lpc32xx_watchdog_device;
29extern struct platform_device lpc32xx_i2c0_device;
30extern struct platform_device lpc32xx_i2c1_device;
31extern struct platform_device lpc32xx_i2c2_device;
32extern struct platform_device lpc32xx_tsc_device;
33extern struct platform_device lpc32xx_adc_device;
34extern struct platform_device lpc32xx_rtc_device;
35extern struct platform_device lpc32xx_ohci_device;
36extern struct platform_device lpc32xx_net_device;
37
38/*
39 * Other arch specific structures and functions 26 * Other arch specific structures and functions
40 */ 27 */
41extern struct sys_timer lpc32xx_timer; 28extern struct sys_timer lpc32xx_timer;
42extern void __init lpc32xx_init_irq(void); 29extern void __init lpc32xx_init_irq(void);
43extern void __init lpc32xx_map_io(void); 30extern void __init lpc32xx_map_io(void);
44extern void __init lpc32xx_serial_init(void); 31extern void __init lpc32xx_serial_init(void);
45extern void __init lpc32xx_gpio_init(void);
46extern void lpc23xx_restart(char, const char *); 32extern void lpc23xx_restart(char, const char *);
47 33
48 34
diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c
index d080cb1123dd..5b1cc35e6fba 100644
--- a/arch/arm/mach-lpc32xx/irq.c
+++ b/arch/arm/mach-lpc32xx/irq.c
@@ -22,6 +22,11 @@
22#include <linux/irq.h> 22#include <linux/irq.h>
23#include <linux/err.h> 23#include <linux/err.h>
24#include <linux/io.h> 24#include <linux/io.h>
25#include <linux/of.h>
26#include <linux/of_address.h>
27#include <linux/of_irq.h>
28#include <linux/irqdomain.h>
29#include <linux/module.h>
25 30
26#include <mach/irqs.h> 31#include <mach/irqs.h>
27#include <mach/hardware.h> 32#include <mach/hardware.h>
@@ -44,6 +49,9 @@
44#define SIC1_ATR_DEFAULT 0x00026000 49#define SIC1_ATR_DEFAULT 0x00026000
45#define SIC2_ATR_DEFAULT 0x00000000 50#define SIC2_ATR_DEFAULT 0x00000000
46 51
52static struct irq_domain *lpc32xx_mic_domain;
53static struct device_node *lpc32xx_mic_np;
54
47struct lpc32xx_event_group_regs { 55struct lpc32xx_event_group_regs {
48 void __iomem *enab_reg; 56 void __iomem *enab_reg;
49 void __iomem *edge_reg; 57 void __iomem *edge_reg;
@@ -203,7 +211,7 @@ static void lpc32xx_mask_irq(struct irq_data *d)
203{ 211{
204 unsigned int reg, ctrl, mask; 212 unsigned int reg, ctrl, mask;
205 213
206 get_controller(d->irq, &ctrl, &mask); 214 get_controller(d->hwirq, &ctrl, &mask);
207 215
208 reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) & ~mask; 216 reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) & ~mask;
209 __raw_writel(reg, LPC32XX_INTC_MASK(ctrl)); 217 __raw_writel(reg, LPC32XX_INTC_MASK(ctrl));
@@ -213,7 +221,7 @@ static void lpc32xx_unmask_irq(struct irq_data *d)
213{ 221{
214 unsigned int reg, ctrl, mask; 222 unsigned int reg, ctrl, mask;
215 223
216 get_controller(d->irq, &ctrl, &mask); 224 get_controller(d->hwirq, &ctrl, &mask);
217 225
218 reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) | mask; 226 reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) | mask;
219 __raw_writel(reg, LPC32XX_INTC_MASK(ctrl)); 227 __raw_writel(reg, LPC32XX_INTC_MASK(ctrl));
@@ -223,14 +231,14 @@ static void lpc32xx_ack_irq(struct irq_data *d)
223{ 231{
224 unsigned int ctrl, mask; 232 unsigned int ctrl, mask;
225 233
226 get_controller(d->irq, &ctrl, &mask); 234 get_controller(d->hwirq, &ctrl, &mask);
227 235
228 __raw_writel(mask, LPC32XX_INTC_RAW_STAT(ctrl)); 236 __raw_writel(mask, LPC32XX_INTC_RAW_STAT(ctrl));
229 237
230 /* Also need to clear pending wake event */ 238 /* Also need to clear pending wake event */
231 if (lpc32xx_events[d->irq].mask != 0) 239 if (lpc32xx_events[d->hwirq].mask != 0)
232 __raw_writel(lpc32xx_events[d->irq].mask, 240 __raw_writel(lpc32xx_events[d->hwirq].mask,
233 lpc32xx_events[d->irq].event_group->rawstat_reg); 241 lpc32xx_events[d->hwirq].event_group->rawstat_reg);
234} 242}
235 243
236static void __lpc32xx_set_irq_type(unsigned int irq, int use_high_level, 244static void __lpc32xx_set_irq_type(unsigned int irq, int use_high_level,
@@ -274,22 +282,22 @@ static int lpc32xx_set_irq_type(struct irq_data *d, unsigned int type)
274 switch (type) { 282 switch (type) {
275 case IRQ_TYPE_EDGE_RISING: 283 case IRQ_TYPE_EDGE_RISING:
276 /* Rising edge sensitive */ 284 /* Rising edge sensitive */
277 __lpc32xx_set_irq_type(d->irq, 1, 1); 285 __lpc32xx_set_irq_type(d->hwirq, 1, 1);
278 break; 286 break;
279 287
280 case IRQ_TYPE_EDGE_FALLING: 288 case IRQ_TYPE_EDGE_FALLING:
281 /* Falling edge sensitive */ 289 /* Falling edge sensitive */
282 __lpc32xx_set_irq_type(d->irq, 0, 1); 290 __lpc32xx_set_irq_type(d->hwirq, 0, 1);
283 break; 291 break;
284 292
285 case IRQ_TYPE_LEVEL_LOW: 293 case IRQ_TYPE_LEVEL_LOW:
286 /* Low level sensitive */ 294 /* Low level sensitive */
287 __lpc32xx_set_irq_type(d->irq, 0, 0); 295 __lpc32xx_set_irq_type(d->hwirq, 0, 0);
288 break; 296 break;
289 297
290 case IRQ_TYPE_LEVEL_HIGH: 298 case IRQ_TYPE_LEVEL_HIGH:
291 /* High level sensitive */ 299 /* High level sensitive */
292 __lpc32xx_set_irq_type(d->irq, 1, 0); 300 __lpc32xx_set_irq_type(d->hwirq, 1, 0);
293 break; 301 break;
294 302
295 /* Other modes are not supported */ 303 /* Other modes are not supported */
@@ -298,7 +306,7 @@ static int lpc32xx_set_irq_type(struct irq_data *d, unsigned int type)
298 } 306 }
299 307
300 /* Ok to use the level handler for all types */ 308 /* Ok to use the level handler for all types */
301 irq_set_handler(d->irq, handle_level_irq); 309 irq_set_handler(d->hwirq, handle_level_irq);
302 310
303 return 0; 311 return 0;
304} 312}
@@ -307,33 +315,33 @@ static int lpc32xx_irq_wake(struct irq_data *d, unsigned int state)
307{ 315{
308 unsigned long eventreg; 316 unsigned long eventreg;
309 317
310 if (lpc32xx_events[d->irq].mask != 0) { 318 if (lpc32xx_events[d->hwirq].mask != 0) {
311 eventreg = __raw_readl(lpc32xx_events[d->irq]. 319 eventreg = __raw_readl(lpc32xx_events[d->hwirq].
312 event_group->enab_reg); 320 event_group->enab_reg);
313 321
314 if (state) 322 if (state)
315 eventreg |= lpc32xx_events[d->irq].mask; 323 eventreg |= lpc32xx_events[d->hwirq].mask;
316 else { 324 else {
317 eventreg &= ~lpc32xx_events[d->irq].mask; 325 eventreg &= ~lpc32xx_events[d->hwirq].mask;
318 326
319 /* 327 /*
320 * When disabling the wakeup, clear the latched 328 * When disabling the wakeup, clear the latched
321 * event 329 * event
322 */ 330 */
323 __raw_writel(lpc32xx_events[d->irq].mask, 331 __raw_writel(lpc32xx_events[d->hwirq].mask,
324 lpc32xx_events[d->irq]. 332 lpc32xx_events[d->hwirq].
325 event_group->rawstat_reg); 333 event_group->rawstat_reg);
326 } 334 }
327 335
328 __raw_writel(eventreg, 336 __raw_writel(eventreg,
329 lpc32xx_events[d->irq].event_group->enab_reg); 337 lpc32xx_events[d->hwirq].event_group->enab_reg);
330 338
331 return 0; 339 return 0;
332 } 340 }
333 341
334 /* Clear event */ 342 /* Clear event */
335 __raw_writel(lpc32xx_events[d->irq].mask, 343 __raw_writel(lpc32xx_events[d->hwirq].mask,
336 lpc32xx_events[d->irq].event_group->rawstat_reg); 344 lpc32xx_events[d->hwirq].event_group->rawstat_reg);
337 345
338 return -ENODEV; 346 return -ENODEV;
339} 347}
@@ -353,6 +361,7 @@ static void __init lpc32xx_set_default_mappings(unsigned int apr,
353} 361}
354 362
355static struct irq_chip lpc32xx_irq_chip = { 363static struct irq_chip lpc32xx_irq_chip = {
364 .name = "MIC",
356 .irq_ack = lpc32xx_ack_irq, 365 .irq_ack = lpc32xx_ack_irq,
357 .irq_mask = lpc32xx_mask_irq, 366 .irq_mask = lpc32xx_mask_irq,
358 .irq_unmask = lpc32xx_unmask_irq, 367 .irq_unmask = lpc32xx_unmask_irq,
@@ -386,9 +395,23 @@ static void lpc32xx_sic2_handler(unsigned int irq, struct irq_desc *desc)
386 } 395 }
387} 396}
388 397
398static int __init __lpc32xx_mic_of_init(struct device_node *node,
399 struct device_node *parent)
400{
401 lpc32xx_mic_np = node;
402
403 return 0;
404}
405
406static const struct of_device_id mic_of_match[] __initconst = {
407 { .compatible = "nxp,lpc3220-mic", .data = __lpc32xx_mic_of_init },
408 { }
409};
410
389void __init lpc32xx_init_irq(void) 411void __init lpc32xx_init_irq(void)
390{ 412{
391 unsigned int i; 413 unsigned int i;
414 int irq_base;
392 415
393 /* Setup MIC */ 416 /* Setup MIC */
394 __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_MIC_BASE)); 417 __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_MIC_BASE));
@@ -448,4 +471,19 @@ void __init lpc32xx_init_irq(void)
448 LPC32XX_CLKPWR_PIN_RS); 471 LPC32XX_CLKPWR_PIN_RS);
449 __raw_writel(__raw_readl(LPC32XX_CLKPWR_INT_RS), 472 __raw_writel(__raw_readl(LPC32XX_CLKPWR_INT_RS),
450 LPC32XX_CLKPWR_INT_RS); 473 LPC32XX_CLKPWR_INT_RS);
474
475 of_irq_init(mic_of_match);
476
477 irq_base = irq_alloc_descs(-1, 0, NR_IRQS, 0);
478 if (irq_base < 0) {
479 pr_warn("Cannot allocate irq_descs, assuming pre-allocated\n");
480 irq_base = 0;
481 }
482
483 lpc32xx_mic_domain = irq_domain_add_legacy(lpc32xx_mic_np, NR_IRQS,
484 irq_base, 0,
485 &irq_domain_simple_ops,
486 NULL);
487 if (!lpc32xx_mic_domain)
488 panic("Unable to add MIC irq domain\n");
451} 489}
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
index 7f7401ec7487..540106cdb9ec 100644
--- a/arch/arm/mach-lpc32xx/phy3250.c
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -1,8 +1,9 @@
1/* 1/*
2 * arch/arm/mach-lpc32xx/phy3250.c 2 * Platform support for LPC32xx SoC
3 * 3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com> 4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 * 5 *
6 * Copyright (C) 2012 Roland Stigge <stigge@antcom.de>
6 * Copyright (C) 2010 NXP Semiconductors 7 * Copyright (C) 2010 NXP Semiconductors
7 * 8 *
8 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
@@ -25,11 +26,16 @@
25#include <linux/device.h> 26#include <linux/device.h>
26#include <linux/spi/spi.h> 27#include <linux/spi/spi.h>
27#include <linux/spi/eeprom.h> 28#include <linux/spi/eeprom.h>
28#include <linux/leds.h>
29#include <linux/gpio.h> 29#include <linux/gpio.h>
30#include <linux/amba/bus.h> 30#include <linux/amba/bus.h>
31#include <linux/amba/clcd.h> 31#include <linux/amba/clcd.h>
32#include <linux/amba/pl022.h> 32#include <linux/amba/pl022.h>
33#include <linux/of.h>
34#include <linux/of_address.h>
35#include <linux/of_irq.h>
36#include <linux/of_platform.h>
37#include <linux/clk.h>
38#include <linux/amba/pl08x.h>
33 39
34#include <asm/setup.h> 40#include <asm/setup.h>
35#include <asm/mach-types.h> 41#include <asm/mach-types.h>
@@ -47,7 +53,6 @@
47#define SPI0_CS_GPIO LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5) 53#define SPI0_CS_GPIO LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
48#define LCD_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0) 54#define LCD_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0)
49#define BKL_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4) 55#define BKL_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4)
50#define LED_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 1)
51 56
52/* 57/*
53 * AMBA LCD controller 58 * AMBA LCD controller
@@ -150,9 +155,6 @@ static struct clcd_board lpc32xx_clcd_data = {
150 .remove = lpc32xx_clcd_remove, 155 .remove = lpc32xx_clcd_remove,
151}; 156};
152 157
153static AMBA_AHB_DEVICE(lpc32xx_clcd, "dev:clcd", 0,
154 LPC32XX_LCD_BASE, { IRQ_LPC32XX_LCD }, &lpc32xx_clcd_data);
155
156/* 158/*
157 * AMBA SSP (SPI) 159 * AMBA SSP (SPI)
158 */ 160 */
@@ -180,8 +182,11 @@ static struct pl022_ssp_controller lpc32xx_ssp0_data = {
180 .enable_dma = 0, 182 .enable_dma = 0,
181}; 183};
182 184
183static AMBA_APB_DEVICE(lpc32xx_ssp0, "dev:ssp0", 0, 185static struct pl022_ssp_controller lpc32xx_ssp1_data = {
184 LPC32XX_SSP0_BASE, { IRQ_LPC32XX_SSP0 }, &lpc32xx_ssp0_data); 186 .bus_id = 1,
187 .num_chipselect = 1,
188 .enable_dma = 0,
189};
185 190
186/* AT25 driver registration */ 191/* AT25 driver registration */
187static int __init phy3250_spi_board_register(void) 192static int __init phy3250_spi_board_register(void)
@@ -221,73 +226,20 @@ static int __init phy3250_spi_board_register(void)
221} 226}
222arch_initcall(phy3250_spi_board_register); 227arch_initcall(phy3250_spi_board_register);
223 228
224static struct i2c_board_info __initdata phy3250_i2c_board_info[] = { 229static struct pl08x_platform_data pl08x_pd = {
225 {
226 I2C_BOARD_INFO("pcf8563", 0x51),
227 },
228};
229
230static struct gpio_led phy_leds[] = {
231 {
232 .name = "led0",
233 .gpio = LED_GPIO,
234 .active_low = 1,
235 .default_trigger = "heartbeat",
236 },
237};
238
239static struct gpio_led_platform_data led_data = {
240 .leds = phy_leds,
241 .num_leds = ARRAY_SIZE(phy_leds),
242};
243
244static struct platform_device lpc32xx_gpio_led_device = {
245 .name = "leds-gpio",
246 .id = -1,
247 .dev.platform_data = &led_data,
248}; 230};
249 231
250static struct platform_device *phy3250_devs[] __initdata = { 232static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = {
251 &lpc32xx_rtc_device, 233 OF_DEV_AUXDATA("arm,pl022", 0x20084000, "dev:ssp0", &lpc32xx_ssp0_data),
252 &lpc32xx_tsc_device, 234 OF_DEV_AUXDATA("arm,pl022", 0x2008C000, "dev:ssp1", &lpc32xx_ssp1_data),
253 &lpc32xx_i2c0_device, 235 OF_DEV_AUXDATA("arm,pl110", 0x31040000, "dev:clcd", &lpc32xx_clcd_data),
254 &lpc32xx_i2c1_device, 236 OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd),
255 &lpc32xx_i2c2_device, 237 { }
256 &lpc32xx_watchdog_device,
257 &lpc32xx_gpio_led_device,
258 &lpc32xx_adc_device,
259 &lpc32xx_ohci_device,
260 &lpc32xx_net_device,
261}; 238};
262 239
263static struct amba_device *amba_devs[] __initdata = { 240static void __init lpc3250_machine_init(void)
264 &lpc32xx_clcd_device,
265 &lpc32xx_ssp0_device,
266};
267
268/*
269 * Board specific functions
270 */
271static void __init phy3250_board_init(void)
272{ 241{
273 u32 tmp; 242 u32 tmp;
274 int i;
275
276 lpc32xx_gpio_init();
277
278 /* Register GPIOs used on this board */
279 if (gpio_request(SPI0_CS_GPIO, "spi0 cs"))
280 printk(KERN_ERR "Error requesting gpio %u",
281 SPI0_CS_GPIO);
282 else if (gpio_direction_output(SPI0_CS_GPIO, 1))
283 printk(KERN_ERR "Error setting gpio %u to output",
284 SPI0_CS_GPIO);
285
286 /* Setup network interface for RMII mode */
287 tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL);
288 tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK;
289 tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS;
290 __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL);
291 243
292 /* Setup SLC NAND controller muxing */ 244 /* Setup SLC NAND controller muxing */
293 __raw_writel(LPC32XX_CLKPWR_NANDCLK_SEL_SLC, 245 __raw_writel(LPC32XX_CLKPWR_NANDCLK_SEL_SLC,
@@ -300,6 +252,12 @@ static void __init phy3250_board_init(void)
300 tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16; 252 tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16;
301 __raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL); 253 __raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL);
302 254
255 /* Set up USB power */
256 tmp = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
257 tmp |= LPC32XX_CLKPWR_USBCTRL_HCLK_EN |
258 LPC32XX_CLKPWR_USBCTRL_USBI2C_EN;
259 __raw_writel(tmp, LPC32XX_CLKPWR_USB_CTRL);
260
303 /* Set up I2C pull levels */ 261 /* Set up I2C pull levels */
304 tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL); 262 tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL);
305 tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE | 263 tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE |
@@ -321,54 +279,51 @@ static void __init phy3250_board_init(void)
321 /* 279 /*
322 * AMBA peripheral clocks need to be enabled prior to AMBA device 280 * AMBA peripheral clocks need to be enabled prior to AMBA device
323 * detection or a data fault will occur, so enable the clocks 281 * detection or a data fault will occur, so enable the clocks
324 * here. However, we don't want to enable them if the peripheral 282 * here.
325 * isn't included in the image
326 */ 283 */
327#ifdef CONFIG_FB_ARMCLCD
328 tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL); 284 tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
329 __raw_writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN), 285 __raw_writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN),
330 LPC32XX_CLKPWR_LCDCLK_CTRL); 286 LPC32XX_CLKPWR_LCDCLK_CTRL);
331#endif 287
332#ifdef CONFIG_SPI_PL022
333 tmp = __raw_readl(LPC32XX_CLKPWR_SSP_CLK_CTRL); 288 tmp = __raw_readl(LPC32XX_CLKPWR_SSP_CLK_CTRL);
334 __raw_writel((tmp | LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN), 289 __raw_writel((tmp | LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN),
335 LPC32XX_CLKPWR_SSP_CLK_CTRL); 290 LPC32XX_CLKPWR_SSP_CLK_CTRL);
336#endif
337 291
338 platform_add_devices(phy3250_devs, ARRAY_SIZE(phy3250_devs)); 292 tmp = __raw_readl(LPC32XX_CLKPWR_DMA_CLK_CTRL);
339 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { 293 __raw_writel((tmp | LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN),
340 struct amba_device *d = amba_devs[i]; 294 LPC32XX_CLKPWR_DMA_CLK_CTRL);
341 amba_device_register(d, &iomem_resource);
342 }
343 295
344 /* Test clock needed for UDA1380 initial init */ 296 /* Test clock needed for UDA1380 initial init */
345 __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC | 297 __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC |
346 LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN, 298 LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN,
347 LPC32XX_CLKPWR_TEST_CLK_SEL); 299 LPC32XX_CLKPWR_TEST_CLK_SEL);
348 300
349 i2c_register_board_info(0, phy3250_i2c_board_info, 301 of_platform_populate(NULL, of_default_bus_match_table,
350 ARRAY_SIZE(phy3250_i2c_board_info)); 302 lpc32xx_auxdata_lookup, NULL);
351}
352
353static int __init lpc32xx_display_uid(void)
354{
355 u32 uid[4];
356
357 lpc32xx_get_uid(uid);
358
359 printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n",
360 uid[3], uid[2], uid[1], uid[0]);
361 303
362 return 1; 304 /* Register GPIOs used on this board */
305 if (gpio_request(SPI0_CS_GPIO, "spi0 cs"))
306 printk(KERN_ERR "Error requesting gpio %u",
307 SPI0_CS_GPIO);
308 else if (gpio_direction_output(SPI0_CS_GPIO, 1))
309 printk(KERN_ERR "Error setting gpio %u to output",
310 SPI0_CS_GPIO);
363} 311}
364arch_initcall(lpc32xx_display_uid);
365 312
366MACHINE_START(PHY3250, "Phytec 3250 board with the LPC3250 Microcontroller") 313static char const *lpc32xx_dt_compat[] __initdata = {
367 /* Maintainer: Kevin Wells, NXP Semiconductors */ 314 "nxp,lpc3220",
315 "nxp,lpc3230",
316 "nxp,lpc3240",
317 "nxp,lpc3250",
318 NULL
319};
320
321DT_MACHINE_START(LPC32XX_DT, "LPC32XX SoC (Flattened Device Tree)")
368 .atag_offset = 0x100, 322 .atag_offset = 0x100,
369 .map_io = lpc32xx_map_io, 323 .map_io = lpc32xx_map_io,
370 .init_irq = lpc32xx_init_irq, 324 .init_irq = lpc32xx_init_irq,
371 .timer = &lpc32xx_timer, 325 .timer = &lpc32xx_timer,
372 .init_machine = phy3250_board_init, 326 .init_machine = lpc3250_machine_init,
327 .dt_compat = lpc32xx_dt_compat,
373 .restart = lpc23xx_restart, 328 .restart = lpc23xx_restart,
374MACHINE_END 329MACHINE_END
diff --git a/drivers/net/ethernet/nxp/lpc_eth.c b/drivers/net/ethernet/nxp/lpc_eth.c
index 6dfc26d85e47..52deec0b22ea 100644
--- a/drivers/net/ethernet/nxp/lpc_eth.c
+++ b/drivers/net/ethernet/nxp/lpc_eth.c
@@ -40,6 +40,7 @@
40#include <linux/skbuff.h> 40#include <linux/skbuff.h>
41#include <linux/phy.h> 41#include <linux/phy.h>
42#include <linux/dma-mapping.h> 42#include <linux/dma-mapping.h>
43#include <linux/of.h>
43#include <linux/of_net.h> 44#include <linux/of_net.h>
44#include <linux/types.h> 45#include <linux/types.h>
45 46
@@ -340,13 +341,17 @@
340 */ 341 */
341#define LPC_POWERDOWN_MACAHB (1 << 31) 342#define LPC_POWERDOWN_MACAHB (1 << 31)
342 343
343/* Upon the upcoming introduction of device tree usage in LPC32xx, 344static phy_interface_t lpc_phy_interface_mode(struct device *dev)
344 * lpc_phy_interface_mode() and use_iram_for_net() will be extended with a
345 * device parameter for access to device tree information at runtime, instead
346 * of defining the values at compile time
347 */
348static inline phy_interface_t lpc_phy_interface_mode(void)
349{ 345{
346 if (dev && dev->of_node) {
347 const char *mode = of_get_property(dev->of_node,
348 "phy-mode", NULL);
349 if (mode && !strcmp(mode, "mii"))
350 return PHY_INTERFACE_MODE_MII;
351 return PHY_INTERFACE_MODE_RMII;
352 }
353
354 /* non-DT */
350#ifdef CONFIG_ARCH_LPC32XX_MII_SUPPORT 355#ifdef CONFIG_ARCH_LPC32XX_MII_SUPPORT
351 return PHY_INTERFACE_MODE_MII; 356 return PHY_INTERFACE_MODE_MII;
352#else 357#else
@@ -354,12 +359,16 @@ static inline phy_interface_t lpc_phy_interface_mode(void)
354#endif 359#endif
355} 360}
356 361
357static inline int use_iram_for_net(void) 362static bool use_iram_for_net(struct device *dev)
358{ 363{
364 if (dev && dev->of_node)
365 return of_property_read_bool(dev->of_node, "use-iram");
366
367 /* non-DT */
359#ifdef CONFIG_ARCH_LPC32XX_IRAM_FOR_NET 368#ifdef CONFIG_ARCH_LPC32XX_IRAM_FOR_NET
360 return 1; 369 return true;
361#else 370#else
362 return 0; 371 return false;
363#endif 372#endif
364} 373}
365 374
@@ -664,7 +673,7 @@ static void __lpc_eth_init(struct netdata_local *pldat)
664 LPC_ENET_CLRT(pldat->net_base)); 673 LPC_ENET_CLRT(pldat->net_base));
665 writel(LPC_IPGR_LOAD_PART2(0x12), LPC_ENET_IPGR(pldat->net_base)); 674 writel(LPC_IPGR_LOAD_PART2(0x12), LPC_ENET_IPGR(pldat->net_base));
666 675
667 if (lpc_phy_interface_mode() == PHY_INTERFACE_MODE_MII) 676 if (lpc_phy_interface_mode(&pldat->pdev->dev) == PHY_INTERFACE_MODE_MII)
668 writel(LPC_COMMAND_PASSRUNTFRAME, 677 writel(LPC_COMMAND_PASSRUNTFRAME,
669 LPC_ENET_COMMAND(pldat->net_base)); 678 LPC_ENET_COMMAND(pldat->net_base));
670 else { 679 else {
@@ -804,12 +813,13 @@ static int lpc_mii_probe(struct net_device *ndev)
804 } 813 }
805 814
806 /* Attach to the PHY */ 815 /* Attach to the PHY */
807 if (lpc_phy_interface_mode() == PHY_INTERFACE_MODE_MII) 816 if (lpc_phy_interface_mode(&pldat->pdev->dev) == PHY_INTERFACE_MODE_MII)
808 netdev_info(ndev, "using MII interface\n"); 817 netdev_info(ndev, "using MII interface\n");
809 else 818 else
810 netdev_info(ndev, "using RMII interface\n"); 819 netdev_info(ndev, "using RMII interface\n");
811 phydev = phy_connect(ndev, dev_name(&phydev->dev), 820 phydev = phy_connect(ndev, dev_name(&phydev->dev),
812 &lpc_handle_link_change, 0, lpc_phy_interface_mode()); 821 &lpc_handle_link_change, 0,
822 lpc_phy_interface_mode(&pldat->pdev->dev));
813 823
814 if (IS_ERR(phydev)) { 824 if (IS_ERR(phydev)) {
815 netdev_err(ndev, "Could not attach to PHY\n"); 825 netdev_err(ndev, "Could not attach to PHY\n");
@@ -843,7 +853,7 @@ static int lpc_mii_init(struct netdata_local *pldat)
843 } 853 }
844 854
845 /* Setup MII mode */ 855 /* Setup MII mode */
846 if (lpc_phy_interface_mode() == PHY_INTERFACE_MODE_MII) 856 if (lpc_phy_interface_mode(&pldat->pdev->dev) == PHY_INTERFACE_MODE_MII)
847 writel(LPC_COMMAND_PASSRUNTFRAME, 857 writel(LPC_COMMAND_PASSRUNTFRAME,
848 LPC_ENET_COMMAND(pldat->net_base)); 858 LPC_ENET_COMMAND(pldat->net_base));
849 else { 859 else {
@@ -1315,18 +1325,26 @@ static const struct net_device_ops lpc_netdev_ops = {
1315static int lpc_eth_drv_probe(struct platform_device *pdev) 1325static int lpc_eth_drv_probe(struct platform_device *pdev)
1316{ 1326{
1317 struct resource *res; 1327 struct resource *res;
1318 struct resource *dma_res;
1319 struct net_device *ndev; 1328 struct net_device *ndev;
1320 struct netdata_local *pldat; 1329 struct netdata_local *pldat;
1321 struct phy_device *phydev; 1330 struct phy_device *phydev;
1322 dma_addr_t dma_handle; 1331 dma_addr_t dma_handle;
1323 int irq, ret; 1332 int irq, ret;
1333 u32 tmp;
1334
1335 /* Setup network interface for RMII or MII mode */
1336 tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL);
1337 tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK;
1338 if (lpc_phy_interface_mode(&pdev->dev) == PHY_INTERFACE_MODE_MII)
1339 tmp |= LPC32XX_CLKPWR_MACCTRL_USE_MII_PINS;
1340 else
1341 tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS;
1342 __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL);
1324 1343
1325 /* Get platform resources */ 1344 /* Get platform resources */
1326 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1345 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1327 dma_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1328 irq = platform_get_irq(pdev, 0); 1346 irq = platform_get_irq(pdev, 0);
1329 if ((!res) || (!dma_res) || (irq < 0) || (irq >= NR_IRQS)) { 1347 if ((!res) || (irq < 0) || (irq >= NR_IRQS)) {
1330 dev_err(&pdev->dev, "error getting resources.\n"); 1348 dev_err(&pdev->dev, "error getting resources.\n");
1331 ret = -ENXIO; 1349 ret = -ENXIO;
1332 goto err_exit; 1350 goto err_exit;
@@ -1389,17 +1407,19 @@ static int lpc_eth_drv_probe(struct platform_device *pdev)
1389 sizeof(struct txrx_desc_t) + sizeof(struct rx_status_t)); 1407 sizeof(struct txrx_desc_t) + sizeof(struct rx_status_t));
1390 pldat->dma_buff_base_v = 0; 1408 pldat->dma_buff_base_v = 0;
1391 1409
1392 if (use_iram_for_net()) { 1410 if (use_iram_for_net(&pldat->pdev->dev)) {
1393 dma_handle = dma_res->start; 1411 dma_handle = LPC32XX_IRAM_BASE;
1394 if (pldat->dma_buff_size <= lpc32xx_return_iram_size()) 1412 if (pldat->dma_buff_size <= lpc32xx_return_iram_size())
1395 pldat->dma_buff_base_v = 1413 pldat->dma_buff_base_v =
1396 io_p2v(dma_res->start); 1414 io_p2v(LPC32XX_IRAM_BASE);
1397 else 1415 else
1398 netdev_err(ndev, 1416 netdev_err(ndev,
1399 "IRAM not big enough for net buffers, using SDRAM instead.\n"); 1417 "IRAM not big enough for net buffers, using SDRAM instead.\n");
1400 } 1418 }
1401 1419
1402 if (pldat->dma_buff_base_v == 0) { 1420 if (pldat->dma_buff_base_v == 0) {
1421 pldat->pdev->dev.coherent_dma_mask = 0xFFFFFFFF;
1422 pldat->pdev->dev.dma_mask = &pldat->pdev->dev.coherent_dma_mask;
1403 pldat->dma_buff_size = PAGE_ALIGN(pldat->dma_buff_size); 1423 pldat->dma_buff_size = PAGE_ALIGN(pldat->dma_buff_size);
1404 1424
1405 /* Allocate a chunk of memory for the DMA ethernet buffers 1425 /* Allocate a chunk of memory for the DMA ethernet buffers
@@ -1488,7 +1508,7 @@ err_out_unregister_netdev:
1488 platform_set_drvdata(pdev, NULL); 1508 platform_set_drvdata(pdev, NULL);
1489 unregister_netdev(ndev); 1509 unregister_netdev(ndev);
1490err_out_dma_unmap: 1510err_out_dma_unmap:
1491 if (!use_iram_for_net() || 1511 if (!use_iram_for_net(&pldat->pdev->dev) ||
1492 pldat->dma_buff_size > lpc32xx_return_iram_size()) 1512 pldat->dma_buff_size > lpc32xx_return_iram_size())
1493 dma_free_coherent(&pldat->pdev->dev, pldat->dma_buff_size, 1513 dma_free_coherent(&pldat->pdev->dev, pldat->dma_buff_size,
1494 pldat->dma_buff_base_v, 1514 pldat->dma_buff_base_v,
@@ -1515,7 +1535,7 @@ static int lpc_eth_drv_remove(struct platform_device *pdev)
1515 unregister_netdev(ndev); 1535 unregister_netdev(ndev);
1516 platform_set_drvdata(pdev, NULL); 1536 platform_set_drvdata(pdev, NULL);
1517 1537
1518 if (!use_iram_for_net() || 1538 if (!use_iram_for_net(&pldat->pdev->dev) ||
1519 pldat->dma_buff_size > lpc32xx_return_iram_size()) 1539 pldat->dma_buff_size > lpc32xx_return_iram_size())
1520 dma_free_coherent(&pldat->pdev->dev, pldat->dma_buff_size, 1540 dma_free_coherent(&pldat->pdev->dev, pldat->dma_buff_size,
1521 pldat->dma_buff_base_v, 1541 pldat->dma_buff_base_v,
@@ -1584,6 +1604,14 @@ static int lpc_eth_drv_resume(struct platform_device *pdev)
1584} 1604}
1585#endif 1605#endif
1586 1606
1607#ifdef CONFIG_OF
1608static const struct of_device_id lpc_eth_match[] = {
1609 { .compatible = "nxp,lpc-eth" },
1610 { }
1611};
1612MODULE_DEVICE_TABLE(of, lpc_eth_match);
1613#endif
1614
1587static struct platform_driver lpc_eth_driver = { 1615static struct platform_driver lpc_eth_driver = {
1588 .probe = lpc_eth_drv_probe, 1616 .probe = lpc_eth_drv_probe,
1589 .remove = __devexit_p(lpc_eth_drv_remove), 1617 .remove = __devexit_p(lpc_eth_drv_remove),
@@ -1593,6 +1621,7 @@ static struct platform_driver lpc_eth_driver = {
1593#endif 1621#endif
1594 .driver = { 1622 .driver = {
1595 .name = MODNAME, 1623 .name = MODNAME,
1624 .of_match_table = of_match_ptr(lpc_eth_match),
1596 }, 1625 },
1597}; 1626};
1598 1627
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-10 05:32:20 -0500