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-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c341
1 files changed, 169 insertions, 172 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 3e9015ade867..378d4a73f9aa 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -556,9 +556,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
556 * sl2if 556 * sl2if
557 * slimbus1 557 * slimbus1
558 * slimbus2 558 * slimbus2
559 * smartreflex_core
560 * smartreflex_iva
561 * smartreflex_mpu
562 * spinlock 559 * spinlock
563 * timer1 560 * timer1
564 * timer10 561 * timer10
@@ -1393,6 +1390,170 @@ static struct omap_hwmod omap44xx_mpu_hwmod = {
1393}; 1390};
1394 1391
1395/* 1392/*
1393 * 'smartreflex' class
1394 * smartreflex module (monitor silicon performance and outputs a measure of
1395 * performance error)
1396 */
1397
1398/* The IP is not compliant to type1 / type2 scheme */
1399static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
1400 .sidle_shift = 24,
1401 .enwkup_shift = 26,
1402};
1403
1404static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
1405 .sysc_offs = 0x0038,
1406 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
1407 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1408 SIDLE_SMART_WKUP),
1409 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
1410};
1411
1412static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
1413 .name = "smartreflex",
1414 .sysc = &omap44xx_smartreflex_sysc,
1415 .rev = 2,
1416};
1417
1418/* smartreflex_core */
1419static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
1420static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
1421 { .irq = 19 + OMAP44XX_IRQ_GIC_START },
1422};
1423
1424static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
1425 {
1426 .pa_start = 0x4a0dd000,
1427 .pa_end = 0x4a0dd03f,
1428 .flags = ADDR_TYPE_RT
1429 },
1430};
1431
1432/* l4_cfg -> smartreflex_core */
1433static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
1434 .master = &omap44xx_l4_cfg_hwmod,
1435 .slave = &omap44xx_smartreflex_core_hwmod,
1436 .clk = "l4_div_ck",
1437 .addr = omap44xx_smartreflex_core_addrs,
1438 .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_addrs),
1439 .user = OCP_USER_MPU | OCP_USER_SDMA,
1440};
1441
1442/* smartreflex_core slave ports */
1443static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
1444 &omap44xx_l4_cfg__smartreflex_core,
1445};
1446
1447static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
1448 .name = "smartreflex_core",
1449 .class = &omap44xx_smartreflex_hwmod_class,
1450 .mpu_irqs = omap44xx_smartreflex_core_irqs,
1451 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_irqs),
1452 .main_clk = "smartreflex_core_fck",
1453 .vdd_name = "core",
1454 .prcm = {
1455 .omap4 = {
1456 .clkctrl_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
1457 },
1458 },
1459 .slaves = omap44xx_smartreflex_core_slaves,
1460 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
1461 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1462};
1463
1464/* smartreflex_iva */
1465static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
1466static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
1467 { .irq = 102 + OMAP44XX_IRQ_GIC_START },
1468};
1469
1470static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
1471 {
1472 .pa_start = 0x4a0db000,
1473 .pa_end = 0x4a0db03f,
1474 .flags = ADDR_TYPE_RT
1475 },
1476};
1477
1478/* l4_cfg -> smartreflex_iva */
1479static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
1480 .master = &omap44xx_l4_cfg_hwmod,
1481 .slave = &omap44xx_smartreflex_iva_hwmod,
1482 .clk = "l4_div_ck",
1483 .addr = omap44xx_smartreflex_iva_addrs,
1484 .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_addrs),
1485 .user = OCP_USER_MPU | OCP_USER_SDMA,
1486};
1487
1488/* smartreflex_iva slave ports */
1489static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
1490 &omap44xx_l4_cfg__smartreflex_iva,
1491};
1492
1493static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
1494 .name = "smartreflex_iva",
1495 .class = &omap44xx_smartreflex_hwmod_class,
1496 .mpu_irqs = omap44xx_smartreflex_iva_irqs,
1497 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_irqs),
1498 .main_clk = "smartreflex_iva_fck",
1499 .vdd_name = "iva",
1500 .prcm = {
1501 .omap4 = {
1502 .clkctrl_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
1503 },
1504 },
1505 .slaves = omap44xx_smartreflex_iva_slaves,
1506 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
1507 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1508};
1509
1510/* smartreflex_mpu */
1511static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
1512static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
1513 { .irq = 18 + OMAP44XX_IRQ_GIC_START },
1514};
1515
1516static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
1517 {
1518 .pa_start = 0x4a0d9000,
1519 .pa_end = 0x4a0d903f,
1520 .flags = ADDR_TYPE_RT
1521 },
1522};
1523
1524/* l4_cfg -> smartreflex_mpu */
1525static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
1526 .master = &omap44xx_l4_cfg_hwmod,
1527 .slave = &omap44xx_smartreflex_mpu_hwmod,
1528 .clk = "l4_div_ck",
1529 .addr = omap44xx_smartreflex_mpu_addrs,
1530 .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_addrs),
1531 .user = OCP_USER_MPU | OCP_USER_SDMA,
1532};
1533
1534/* smartreflex_mpu slave ports */
1535static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
1536 &omap44xx_l4_cfg__smartreflex_mpu,
1537};
1538
1539static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
1540 .name = "smartreflex_mpu",
1541 .class = &omap44xx_smartreflex_hwmod_class,
1542 .mpu_irqs = omap44xx_smartreflex_mpu_irqs,
1543 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_irqs),
1544 .main_clk = "smartreflex_mpu_fck",
1545 .vdd_name = "mpu",
1546 .prcm = {
1547 .omap4 = {
1548 .clkctrl_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
1549 },
1550 },
1551 .slaves = omap44xx_smartreflex_mpu_slaves,
1552 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
1553 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1554};
1555
1556/*
1396 * 'uart' class 1557 * 'uart' class
1397 * universal asynchronous receiver/transmitter (uart) 1558 * universal asynchronous receiver/transmitter (uart)
1398 */ 1559 */
@@ -1842,170 +2003,6 @@ static struct omap_hwmod omap44xx_dma_system_hwmod = {
1842 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 2003 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1843}; 2004};
1844 2005
1845/*
1846 * 'smartreflex' class
1847 * smartreflex module (monitor silicon performance and outputs a measure of
1848 * performance error)
1849 */
1850
1851/* The IP is not compliant to type1 / type2 scheme */
1852static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
1853 .sidle_shift = 24,
1854 .enwkup_shift = 26,
1855};
1856
1857static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
1858 .sysc_offs = 0x0038,
1859 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
1860 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1861 SIDLE_SMART_WKUP),
1862 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
1863};
1864
1865static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
1866 .name = "smartreflex",
1867 .sysc = &omap44xx_smartreflex_sysc,
1868 .rev = 2,
1869};
1870
1871/* smartreflex_core */
1872static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
1873static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
1874 { .irq = 19 + OMAP44XX_IRQ_GIC_START },
1875};
1876
1877static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
1878 {
1879 .pa_start = 0x4a0dd000,
1880 .pa_end = 0x4a0dd03f,
1881 .flags = ADDR_TYPE_RT
1882 },
1883};
1884
1885/* l4_cfg -> smartreflex_core */
1886static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
1887 .master = &omap44xx_l4_cfg_hwmod,
1888 .slave = &omap44xx_smartreflex_core_hwmod,
1889 .clk = "l4_div_ck",
1890 .addr = omap44xx_smartreflex_core_addrs,
1891 .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_addrs),
1892 .user = OCP_USER_MPU | OCP_USER_SDMA,
1893};
1894
1895/* smartreflex_core slave ports */
1896static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
1897 &omap44xx_l4_cfg__smartreflex_core,
1898};
1899
1900static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
1901 .name = "smartreflex_core",
1902 .class = &omap44xx_smartreflex_hwmod_class,
1903 .mpu_irqs = omap44xx_smartreflex_core_irqs,
1904 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_irqs),
1905 .main_clk = "smartreflex_core_fck",
1906 .vdd_name = "core",
1907 .prcm = {
1908 .omap4 = {
1909 .clkctrl_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
1910 },
1911 },
1912 .slaves = omap44xx_smartreflex_core_slaves,
1913 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
1914 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1915};
1916
1917/* smartreflex_iva */
1918static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
1919static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
1920 { .irq = 102 + OMAP44XX_IRQ_GIC_START },
1921};
1922
1923static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
1924 {
1925 .pa_start = 0x4a0db000,
1926 .pa_end = 0x4a0db03f,
1927 .flags = ADDR_TYPE_RT
1928 },
1929};
1930
1931/* l4_cfg -> smartreflex_iva */
1932static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
1933 .master = &omap44xx_l4_cfg_hwmod,
1934 .slave = &omap44xx_smartreflex_iva_hwmod,
1935 .clk = "l4_div_ck",
1936 .addr = omap44xx_smartreflex_iva_addrs,
1937 .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_addrs),
1938 .user = OCP_USER_MPU | OCP_USER_SDMA,
1939};
1940
1941/* smartreflex_iva slave ports */
1942static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
1943 &omap44xx_l4_cfg__smartreflex_iva,
1944};
1945
1946static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
1947 .name = "smartreflex_iva",
1948 .class = &omap44xx_smartreflex_hwmod_class,
1949 .mpu_irqs = omap44xx_smartreflex_iva_irqs,
1950 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_irqs),
1951 .main_clk = "smartreflex_iva_fck",
1952 .vdd_name = "iva",
1953 .prcm = {
1954 .omap4 = {
1955 .clkctrl_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
1956 },
1957 },
1958 .slaves = omap44xx_smartreflex_iva_slaves,
1959 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
1960 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1961};
1962
1963/* smartreflex_mpu */
1964static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
1965static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
1966 { .irq = 18 + OMAP44XX_IRQ_GIC_START },
1967};
1968
1969static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
1970 {
1971 .pa_start = 0x4a0d9000,
1972 .pa_end = 0x4a0d903f,
1973 .flags = ADDR_TYPE_RT
1974 },
1975};
1976
1977/* l4_cfg -> smartreflex_mpu */
1978static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
1979 .master = &omap44xx_l4_cfg_hwmod,
1980 .slave = &omap44xx_smartreflex_mpu_hwmod,
1981 .clk = "l4_div_ck",
1982 .addr = omap44xx_smartreflex_mpu_addrs,
1983 .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_addrs),
1984 .user = OCP_USER_MPU | OCP_USER_SDMA,
1985};
1986
1987/* smartreflex_mpu slave ports */
1988static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
1989 &omap44xx_l4_cfg__smartreflex_mpu,
1990};
1991
1992static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
1993 .name = "smartreflex_mpu",
1994 .class = &omap44xx_smartreflex_hwmod_class,
1995 .mpu_irqs = omap44xx_smartreflex_mpu_irqs,
1996 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_irqs),
1997 .main_clk = "smartreflex_mpu_fck",
1998 .vdd_name = "mpu",
1999 .prcm = {
2000 .omap4 = {
2001 .clkctrl_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
2002 },
2003 },
2004 .slaves = omap44xx_smartreflex_mpu_slaves,
2005 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
2006 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2007};
2008
2009static __initdata struct omap_hwmod *omap44xx_hwmods[] = { 2006static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
2010 /* dmm class */ 2007 /* dmm class */
2011 &omap44xx_dmm_hwmod, 2008 &omap44xx_dmm_hwmod,
@@ -2057,6 +2054,11 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
2057 /* mpu class */ 2054 /* mpu class */
2058 &omap44xx_mpu_hwmod, 2055 &omap44xx_mpu_hwmod,
2059 2056
2057 /* smartreflex class */
2058 &omap44xx_smartreflex_core_hwmod,
2059 &omap44xx_smartreflex_iva_hwmod,
2060 &omap44xx_smartreflex_mpu_hwmod,
2061
2060 /* uart class */ 2062 /* uart class */
2061 &omap44xx_uart1_hwmod, 2063 &omap44xx_uart1_hwmod,
2062 &omap44xx_uart2_hwmod, 2064 &omap44xx_uart2_hwmod,
@@ -2067,11 +2069,6 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
2067 &omap44xx_wd_timer2_hwmod, 2069 &omap44xx_wd_timer2_hwmod,
2068 &omap44xx_wd_timer3_hwmod, 2070 &omap44xx_wd_timer3_hwmod,
2069 2071
2070 /* smartreflex class */
2071 &omap44xx_smartreflex_core_hwmod,
2072 &omap44xx_smartreflex_iva_hwmod,
2073 &omap44xx_smartreflex_mpu_hwmod,
2074
2075 NULL, 2072 NULL,
2076}; 2073};
2077 2074
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 05:54:13 -0500