diff options
| -rw-r--r-- | drivers/video/via/hw.c | 101 |
1 files changed, 38 insertions, 63 deletions
diff --git a/drivers/video/via/hw.c b/drivers/video/via/hw.c index 30cc2f0961e3..c8f24058c570 100644 --- a/drivers/video/via/hw.c +++ b/drivers/video/via/hw.c | |||
| @@ -718,7 +718,6 @@ static struct rgbLUT palLUT_table[] = { | |||
| 718 | 0x00} | 718 | 0x00} |
| 719 | }; | 719 | }; |
| 720 | 720 | ||
| 721 | static void set_crt_output_path(int set_iga); | ||
| 722 | static void dvi_patch_skew_dvp0(void); | 721 | static void dvi_patch_skew_dvp0(void); |
| 723 | static void dvi_patch_skew_dvp_low(void); | 722 | static void dvi_patch_skew_dvp_low(void); |
| 724 | static void set_dvi_output_path(int set_iga, int output_interface); | 723 | static void set_dvi_output_path(int set_iga, int output_interface); |
| @@ -733,6 +732,7 @@ static void set_display_channel(void); | |||
| 733 | static void device_off(void); | 732 | static void device_off(void); |
| 734 | static void device_on(void); | 733 | static void device_on(void); |
| 735 | static void enable_second_display_channel(void); | 734 | static void enable_second_display_channel(void); |
| 735 | static void disable_second_display_channel(void); | ||
| 736 | 736 | ||
| 737 | void viafb_lock_crt(void) | 737 | void viafb_lock_crt(void) |
| 738 | { | 738 | { |
| @@ -948,7 +948,7 @@ void viafb_set_output_path(int device, int set_iga, int output_interface) | |||
| 948 | { | 948 | { |
| 949 | switch (device) { | 949 | switch (device) { |
| 950 | case DEVICE_CRT: | 950 | case DEVICE_CRT: |
| 951 | set_crt_output_path(set_iga); | 951 | viafb_write_reg_mask(CR36, VIACR, 0x00, BIT4 + BIT5); |
| 952 | break; | 952 | break; |
| 953 | case DEVICE_DVI: | 953 | case DEVICE_DVI: |
| 954 | set_dvi_output_path(set_iga, output_interface); | 954 | set_dvi_output_path(set_iga, output_interface); |
| @@ -957,9 +957,6 @@ void viafb_set_output_path(int device, int set_iga, int output_interface) | |||
| 957 | set_lcd_output_path(set_iga, output_interface); | 957 | set_lcd_output_path(set_iga, output_interface); |
| 958 | break; | 958 | break; |
| 959 | } | 959 | } |
| 960 | |||
| 961 | if (set_iga == IGA2) | ||
| 962 | enable_second_display_channel(); | ||
| 963 | } | 960 | } |
| 964 | 961 | ||
| 965 | static void set_source_common(u8 index, u8 offset, u8 iga) | 962 | static void set_source_common(u8 index, u8 offset, u8 iga) |
| @@ -1030,10 +1027,22 @@ static inline void set_lvds2_source(u8 iga) | |||
| 1030 | set_source_common(0x97, 4, iga); | 1027 | set_source_common(0x97, 4, iga); |
| 1031 | } | 1028 | } |
| 1032 | 1029 | ||
| 1033 | static void set_crt_output_path(int set_iga) | 1030 | void via_set_source(u32 devices, u8 iga) |
| 1034 | { | 1031 | { |
| 1035 | viafb_write_reg_mask(CR36, VIACR, 0x00, BIT4 + BIT5); | 1032 | if (devices & VIA_6C) |
| 1036 | set_crt_source(set_iga); | 1033 | set_6C_source(iga); |
| 1034 | if (devices & VIA_93) | ||
| 1035 | set_93_source(iga); | ||
| 1036 | if (devices & VIA_96) | ||
| 1037 | set_96_source(iga); | ||
| 1038 | if (devices & VIA_CRT) | ||
| 1039 | set_crt_source(iga); | ||
| 1040 | if (devices & VIA_DVP1) | ||
| 1041 | set_dvp1_source(iga); | ||
| 1042 | if (devices & VIA_LVDS1) | ||
| 1043 | set_lvds1_source(iga); | ||
| 1044 | if (devices & VIA_LVDS2) | ||
| 1045 | set_lvds2_source(iga); | ||
| 1037 | } | 1046 | } |
| 1038 | 1047 | ||
| 1039 | static void dvi_patch_skew_dvp0(void) | 1048 | static void dvi_patch_skew_dvp0(void) |
| @@ -1106,8 +1115,6 @@ static void set_dvi_output_path(int set_iga, int output_interface) | |||
| 1106 | { | 1115 | { |
| 1107 | switch (output_interface) { | 1116 | switch (output_interface) { |
| 1108 | case INTERFACE_DVP0: | 1117 | case INTERFACE_DVP0: |
| 1109 | set_96_source(set_iga); | ||
| 1110 | set_6C_source(set_iga); | ||
| 1111 | viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0); | 1118 | viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0); |
| 1112 | viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 + BIT5); | 1119 | viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 + BIT5); |
| 1113 | viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT7 + BIT6); | 1120 | viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT7 + BIT6); |
| @@ -1115,21 +1122,14 @@ static void set_dvi_output_path(int set_iga, int output_interface) | |||
| 1115 | break; | 1122 | break; |
| 1116 | 1123 | ||
| 1117 | case INTERFACE_DVP1: | 1124 | case INTERFACE_DVP1: |
| 1118 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) { | 1125 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) |
| 1119 | set_93_source(set_iga); | ||
| 1120 | viafb_write_reg_mask(CR93, VIACR, 0x21, BIT0 + BIT5); | 1126 | viafb_write_reg_mask(CR93, VIACR, 0x21, BIT0 + BIT5); |
| 1121 | } else { | ||
| 1122 | set_dvp1_source(set_iga); | ||
| 1123 | } | ||
| 1124 | 1127 | ||
| 1125 | viafb_write_reg_mask(SR1E, VIASR, 0x30, BIT4 + BIT5); | 1128 | viafb_write_reg_mask(SR1E, VIASR, 0x30, BIT4 + BIT5); |
| 1126 | break; | 1129 | break; |
| 1127 | case INTERFACE_DFP_HIGH: | 1130 | case INTERFACE_DFP_HIGH: |
| 1128 | if (viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266) { | 1131 | if (viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266) |
| 1129 | via_write_reg_mask(VIACR, CR97, 0x03, 0x03); | 1132 | via_write_reg_mask(VIACR, CR97, 0x03, 0x03); |
| 1130 | set_lvds2_source(set_iga); | ||
| 1131 | set_96_source(set_iga); | ||
| 1132 | } | ||
| 1133 | 1133 | ||
| 1134 | viafb_write_reg_mask(SR2A, VIASR, 0x0C, BIT2 + BIT3); | 1134 | viafb_write_reg_mask(SR2A, VIASR, 0x0C, BIT2 + BIT3); |
| 1135 | break; | 1135 | break; |
| @@ -1137,15 +1137,9 @@ static void set_dvi_output_path(int set_iga, int output_interface) | |||
| 1137 | case INTERFACE_DFP_LOW: | 1137 | case INTERFACE_DFP_LOW: |
| 1138 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) | 1138 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) |
| 1139 | break; | 1139 | break; |
| 1140 | set_dvp1_source(set_iga); | ||
| 1141 | set_lvds1_source(set_iga); | ||
| 1142 | viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); | 1140 | viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); |
| 1143 | dvi_patch_skew_dvp_low(); | 1141 | dvi_patch_skew_dvp_low(); |
| 1144 | break; | 1142 | break; |
| 1145 | |||
| 1146 | case INTERFACE_TMDS: | ||
| 1147 | set_lvds1_source(set_iga); | ||
| 1148 | break; | ||
| 1149 | } | 1143 | } |
| 1150 | 1144 | ||
| 1151 | if (set_iga == IGA2) { | 1145 | if (set_iga == IGA2) { |
| @@ -1163,53 +1157,19 @@ static void set_lcd_output_path(int set_iga, int output_interface) | |||
| 1163 | viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3); | 1157 | viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3); |
| 1164 | viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3); | 1158 | viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3); |
| 1165 | switch (output_interface) { | 1159 | switch (output_interface) { |
| 1166 | case INTERFACE_DVP0: | ||
| 1167 | set_96_source(set_iga); | ||
| 1168 | if (set_iga == IGA2) | ||
| 1169 | viafb_write_reg(CR91, VIACR, 0x00); | ||
| 1170 | break; | ||
| 1171 | |||
| 1172 | case INTERFACE_DVP1: | ||
| 1173 | set_dvp1_source(set_iga); | ||
| 1174 | if (set_iga == IGA2) | ||
| 1175 | viafb_write_reg(CR91, VIACR, 0x00); | ||
| 1176 | break; | ||
| 1177 | |||
| 1178 | case INTERFACE_DFP_HIGH: | ||
| 1179 | set_lvds2_source(set_iga); | ||
| 1180 | set_96_source(set_iga); | ||
| 1181 | if (set_iga == IGA2) | ||
| 1182 | viafb_write_reg(CR91, VIACR, 0x00); | ||
| 1183 | break; | ||
| 1184 | |||
| 1185 | case INTERFACE_DFP_LOW: | ||
| 1186 | set_lvds1_source(set_iga); | ||
| 1187 | set_dvp1_source(set_iga); | ||
| 1188 | if (set_iga == IGA2) | ||
| 1189 | viafb_write_reg(CR91, VIACR, 0x00); | ||
| 1190 | break; | ||
| 1191 | |||
| 1192 | case INTERFACE_DFP: | 1160 | case INTERFACE_DFP: |
| 1193 | if ((UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name) | 1161 | if ((UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name) |
| 1194 | || (UNICHROME_P4M890 == | 1162 | || (UNICHROME_P4M890 == |
| 1195 | viaparinfo->chip_info->gfx_chip_name)) | 1163 | viaparinfo->chip_info->gfx_chip_name)) |
| 1196 | viafb_write_reg_mask(CR97, VIACR, 0x84, | 1164 | viafb_write_reg_mask(CR97, VIACR, 0x84, |
| 1197 | BIT7 + BIT2 + BIT1 + BIT0); | 1165 | BIT7 + BIT2 + BIT1 + BIT0); |
| 1198 | 1166 | case INTERFACE_DVP0: | |
| 1199 | set_lvds1_source(set_iga); | 1167 | case INTERFACE_DVP1: |
| 1200 | set_lvds2_source(set_iga); | 1168 | case INTERFACE_DFP_HIGH: |
| 1169 | case INTERFACE_DFP_LOW: | ||
| 1201 | if (set_iga == IGA2) | 1170 | if (set_iga == IGA2) |
| 1202 | viafb_write_reg(CR91, VIACR, 0x00); | 1171 | viafb_write_reg(CR91, VIACR, 0x00); |
| 1203 | break; | 1172 | break; |
| 1204 | |||
| 1205 | case INTERFACE_LVDS0: | ||
| 1206 | case INTERFACE_LVDS0LVDS1: | ||
| 1207 | set_lvds1_source(set_iga); | ||
| 1208 | break; | ||
| 1209 | |||
| 1210 | case INTERFACE_LVDS1: | ||
| 1211 | set_lvds2_source(set_iga); | ||
| 1212 | break; | ||
| 1213 | } | 1173 | } |
| 1214 | } | 1174 | } |
| 1215 | 1175 | ||
| @@ -2454,6 +2414,13 @@ int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp, | |||
| 2454 | via_set_primary_color_depth(viaparinfo->depth); | 2414 | via_set_primary_color_depth(viaparinfo->depth); |
| 2455 | via_set_secondary_color_depth(viafb_dual_fb ? viaparinfo1->depth | 2415 | via_set_secondary_color_depth(viafb_dual_fb ? viaparinfo1->depth |
| 2456 | : viaparinfo->depth); | 2416 | : viaparinfo->depth); |
| 2417 | via_set_source(viaparinfo->shared->iga1_devices, IGA1); | ||
| 2418 | via_set_source(viaparinfo->shared->iga2_devices, IGA2); | ||
| 2419 | if (viaparinfo->shared->iga2_devices) | ||
| 2420 | enable_second_display_channel(); | ||
| 2421 | else | ||
| 2422 | disable_second_display_channel(); | ||
| 2423 | |||
| 2457 | /* Update Refresh Rate Setting */ | 2424 | /* Update Refresh Rate Setting */ |
| 2458 | 2425 | ||
| 2459 | /* Clear On Screen */ | 2426 | /* Clear On Screen */ |
| @@ -2647,6 +2614,14 @@ static void enable_second_display_channel(void) | |||
| 2647 | viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6); | 2614 | viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6); |
| 2648 | } | 2615 | } |
| 2649 | 2616 | ||
| 2617 | static void disable_second_display_channel(void) | ||
| 2618 | { | ||
| 2619 | /* to disable second display channel. */ | ||
| 2620 | viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6); | ||
| 2621 | viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT7); | ||
| 2622 | viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6); | ||
| 2623 | } | ||
| 2624 | |||
| 2650 | void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\ | 2625 | void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\ |
| 2651 | *p_gfx_dpa_setting) | 2626 | *p_gfx_dpa_setting) |
| 2652 | { | 2627 | { |
