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-rw-r--r--include/asm-blackfin/mach-bf527/cdefBF52x_base.h57
-rw-r--r--include/asm-blackfin/mach-bf533/cdefBF532.h31
-rw-r--r--include/asm-blackfin/mach-bf537/cdefBF534.h31
-rw-r--r--include/asm-blackfin/mach-bf548/cdefBF54x_base.h37
-rw-r--r--include/asm-blackfin/mach-bf561/cdefBF561.h34
5 files changed, 172 insertions, 18 deletions
diff --git a/include/asm-blackfin/mach-bf527/cdefBF52x_base.h b/include/asm-blackfin/mach-bf527/cdefBF52x_base.h
index 50e14e7da3ee..9dbdbec8ea1b 100644
--- a/include/asm-blackfin/mach-bf527/cdefBF52x_base.h
+++ b/include/asm-blackfin/mach-bf527/cdefBF52x_base.h
@@ -29,18 +29,71 @@
29 */ 29 */
30 30
31#ifndef _CDEF_BF52X_H 31#ifndef _CDEF_BF52X_H
32#define _CDEF_BF52X_H
33
34#include <asm/system.h>
35#include <asm/blackfin.h>
32 36
33#include "defBF52x_base.h" 37#include "defBF52x_base.h"
34 38
39/* Include core specific register pointer definitions */
40#include <asm/mach-common/cdef_LPBlackfin.h>
41
35/* ==== begin from cdefBF534.h ==== */ 42/* ==== begin from cdefBF534.h ==== */
36 43
37/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ 44/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
38#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) 45#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
39#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) 46/* Writing to PLL_CTL initiates a PLL relock sequence. */
47static __inline__ void bfin_write_PLL_CTL(unsigned int val)
48{
49 unsigned long flags, iwr0, iwr1;
50
51 if (val == bfin_read_PLL_CTL())
52 return;
53
54 local_irq_save(flags);
55 /* Enable the PLL Wakeup bit in SIC IWR */
56 iwr0 = bfin_read32(SIC_IWR0);
57 iwr1 = bfin_read32(SIC_IWR1);
58 /* Only allow PPL Wakeup) */
59 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
60 bfin_write32(SIC_IWR1, 0);
61
62 bfin_write16(PLL_CTL, val);
63 SSYNC();
64 asm("IDLE;");
65
66 bfin_write32(SIC_IWR0, iwr0);
67 bfin_write32(SIC_IWR1, iwr1);
68 local_irq_restore(flags);
69}
40#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) 70#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
41#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) 71#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
42#define bfin_read_VR_CTL() bfin_read16(VR_CTL) 72#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
43#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) 73/* Writing to VR_CTL initiates a PLL relock sequence. */
74static __inline__ void bfin_write_VR_CTL(unsigned int val)
75{
76 unsigned long flags, iwr0, iwr1;
77
78 if (val == bfin_read_VR_CTL())
79 return;
80
81 local_irq_save(flags);
82 /* Enable the PLL Wakeup bit in SIC IWR */
83 iwr0 = bfin_read32(SIC_IWR0);
84 iwr1 = bfin_read32(SIC_IWR1);
85 /* Only allow PPL Wakeup) */
86 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
87 bfin_write32(SIC_IWR1, 0);
88
89 bfin_write16(VR_CTL, val);
90 SSYNC();
91 asm("IDLE;");
92
93 bfin_write32(SIC_IWR0, iwr0);
94 bfin_write32(SIC_IWR1, iwr1);
95 local_irq_restore(flags);
96}
44#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) 97#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
45#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) 98#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
46#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) 99#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
diff --git a/include/asm-blackfin/mach-bf533/cdefBF532.h b/include/asm-blackfin/mach-bf533/cdefBF532.h
index c803e14b529c..154655452d4c 100644
--- a/include/asm-blackfin/mach-bf533/cdefBF532.h
+++ b/include/asm-blackfin/mach-bf533/cdefBF532.h
@@ -43,7 +43,27 @@
43 43
44/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */ 44/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */
45#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) 45#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
46#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL,val) 46/* Writing to PLL_CTL initiates a PLL relock sequence. */
47static __inline__ void bfin_write_PLL_CTL(unsigned int val)
48{
49 unsigned long flags, iwr;
50
51 if (val == bfin_read_PLL_CTL())
52 return;
53
54 local_irq_save(flags);
55 /* Enable the PLL Wakeup bit in SIC IWR */
56 iwr = bfin_read32(SIC_IWR);
57 /* Only allow PPL Wakeup) */
58 bfin_write32(SIC_IWR, IWR_ENABLE(0));
59
60 bfin_write16(PLL_CTL, val);
61 SSYNC();
62 asm("IDLE;");
63
64 bfin_write32(SIC_IWR, iwr);
65 local_irq_restore(flags);
66}
47#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) 67#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
48#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) 68#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
49#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) 69#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
@@ -57,6 +77,10 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
57{ 77{
58 unsigned long flags, iwr; 78 unsigned long flags, iwr;
59 79
80 if (val == bfin_read_VR_CTL())
81 return;
82
83 local_irq_save(flags);
60 /* Enable the PLL Wakeup bit in SIC IWR */ 84 /* Enable the PLL Wakeup bit in SIC IWR */
61 iwr = bfin_read32(SIC_IWR); 85 iwr = bfin_read32(SIC_IWR);
62 /* Only allow PPL Wakeup) */ 86 /* Only allow PPL Wakeup) */
@@ -64,11 +88,10 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
64 88
65 bfin_write16(VR_CTL, val); 89 bfin_write16(VR_CTL, val);
66 SSYNC(); 90 SSYNC();
67
68 local_irq_save(flags);
69 asm("IDLE;"); 91 asm("IDLE;");
70 local_irq_restore(flags); 92
71 bfin_write32(SIC_IWR, iwr); 93 bfin_write32(SIC_IWR, iwr);
94 local_irq_restore(flags);
72} 95}
73 96
74/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */ 97/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */
diff --git a/include/asm-blackfin/mach-bf537/cdefBF534.h b/include/asm-blackfin/mach-bf537/cdefBF534.h
index 048d26a61fd1..82de526f8097 100644
--- a/include/asm-blackfin/mach-bf537/cdefBF534.h
+++ b/include/asm-blackfin/mach-bf537/cdefBF534.h
@@ -44,7 +44,27 @@
44 44
45/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ 45/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
46#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) 46#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
47#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL,val) 47/* Writing to PLL_CTL initiates a PLL relock sequence. */
48static __inline__ void bfin_write_PLL_CTL(unsigned int val)
49{
50 unsigned long flags, iwr;
51
52 if (val == bfin_read_PLL_CTL())
53 return;
54
55 local_irq_save(flags);
56 /* Enable the PLL Wakeup bit in SIC IWR */
57 iwr = bfin_read32(SIC_IWR);
58 /* Only allow PPL Wakeup) */
59 bfin_write32(SIC_IWR, IWR_ENABLE(0));
60
61 bfin_write16(PLL_CTL, val);
62 SSYNC();
63 asm("IDLE;");
64
65 bfin_write32(SIC_IWR, iwr);
66 local_irq_restore(flags);
67}
48#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) 68#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
49#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val) 69#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
50#define bfin_read_VR_CTL() bfin_read16(VR_CTL) 70#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
@@ -53,6 +73,10 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
53{ 73{
54 unsigned long flags, iwr; 74 unsigned long flags, iwr;
55 75
76 if (val == bfin_read_VR_CTL())
77 return;
78
79 local_irq_save(flags);
56 /* Enable the PLL Wakeup bit in SIC IWR */ 80 /* Enable the PLL Wakeup bit in SIC IWR */
57 iwr = bfin_read32(SIC_IWR); 81 iwr = bfin_read32(SIC_IWR);
58 /* Only allow PPL Wakeup) */ 82 /* Only allow PPL Wakeup) */
@@ -60,11 +84,10 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
60 84
61 bfin_write16(VR_CTL, val); 85 bfin_write16(VR_CTL, val);
62 SSYNC(); 86 SSYNC();
63
64 local_irq_save(flags);
65 asm("IDLE;"); 87 asm("IDLE;");
66 local_irq_restore(flags); 88
67 bfin_write32(SIC_IWR, iwr); 89 bfin_write32(SIC_IWR, iwr);
90 local_irq_restore(flags);
68} 91}
69#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) 92#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
70#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) 93#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
diff --git a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
index 33c67500717c..57ac8cb9b1f6 100644
--- a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
+++ b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
@@ -43,7 +43,33 @@
43/* PLL Registers */ 43/* PLL Registers */
44 44
45#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) 45#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
46#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) 46/* Writing to PLL_CTL initiates a PLL relock sequence. */
47static __inline__ void bfin_write_PLL_CTL(unsigned int val)
48{
49 unsigned long flags, iwr0, iwr1, iwr2;
50
51 if (val == bfin_read_PLL_CTL())
52 return;
53
54 local_irq_save(flags);
55 /* Enable the PLL Wakeup bit in SIC IWR */
56 iwr0 = bfin_read32(SIC_IWR0);
57 iwr1 = bfin_read32(SIC_IWR1);
58 iwr2 = bfin_read32(SIC_IWR2);
59 /* Only allow PPL Wakeup) */
60 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
61 bfin_write32(SIC_IWR1, 0);
62 bfin_write32(SIC_IWR2, 0);
63
64 bfin_write16(PLL_CTL, val);
65 SSYNC();
66 asm("IDLE;");
67
68 bfin_write32(SIC_IWR0, iwr0);
69 bfin_write32(SIC_IWR1, iwr1);
70 bfin_write32(SIC_IWR2, iwr2);
71 local_irq_restore(flags);
72}
47#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) 73#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
48#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) 74#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
49#define bfin_read_VR_CTL() bfin_read16(VR_CTL) 75#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
@@ -52,6 +78,10 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
52{ 78{
53 unsigned long flags, iwr0, iwr1, iwr2; 79 unsigned long flags, iwr0, iwr1, iwr2;
54 80
81 if (val == bfin_read_VR_CTL())
82 return;
83
84 local_irq_save(flags);
55 /* Enable the PLL Wakeup bit in SIC IWR */ 85 /* Enable the PLL Wakeup bit in SIC IWR */
56 iwr0 = bfin_read32(SIC_IWR0); 86 iwr0 = bfin_read32(SIC_IWR0);
57 iwr1 = bfin_read32(SIC_IWR1); 87 iwr1 = bfin_read32(SIC_IWR1);
@@ -63,13 +93,12 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
63 93
64 bfin_write16(VR_CTL, val); 94 bfin_write16(VR_CTL, val);
65 SSYNC(); 95 SSYNC();
66
67 local_irq_save(flags);
68 asm("IDLE;"); 96 asm("IDLE;");
69 local_irq_restore(flags); 97
70 bfin_write32(SIC_IWR0, iwr0); 98 bfin_write32(SIC_IWR0, iwr0);
71 bfin_write32(SIC_IWR1, iwr1); 99 bfin_write32(SIC_IWR1, iwr1);
72 bfin_write32(SIC_IWR2, iwr2); 100 bfin_write32(SIC_IWR2, iwr2);
101 local_irq_restore(flags);
73} 102}
74#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) 103#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
75#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) 104#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
diff --git a/include/asm-blackfin/mach-bf561/cdefBF561.h b/include/asm-blackfin/mach-bf561/cdefBF561.h
index 1bc8d2f89ccc..b07ffccd66dd 100644
--- a/include/asm-blackfin/mach-bf561/cdefBF561.h
+++ b/include/asm-blackfin/mach-bf561/cdefBF561.h
@@ -47,7 +47,30 @@
47 47
48/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ 48/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
49#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) 49#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
50#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL,val) 50/* Writing to PLL_CTL initiates a PLL relock sequence. */
51static __inline__ void bfin_write_PLL_CTL(unsigned int val)
52{
53 unsigned long flags, iwr0, iwr1;
54
55 if (val == bfin_read_PLL_CTL())
56 return;
57
58 local_irq_save(flags);
59 /* Enable the PLL Wakeup bit in SIC IWR */
60 iwr0 = bfin_read32(SICA_IWR0);
61 iwr1 = bfin_read32(SICA_IWR1);
62 /* Only allow PPL Wakeup) */
63 bfin_write32(SICA_IWR0, IWR_ENABLE(0));
64 bfin_write32(SICA_IWR1, 0);
65
66 bfin_write16(PLL_CTL, val);
67 SSYNC();
68 asm("IDLE;");
69
70 bfin_write32(SICA_IWR0, iwr0);
71 bfin_write32(SICA_IWR1, iwr1);
72 local_irq_restore(flags);
73}
51#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) 74#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
52#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val) 75#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
53#define bfin_read_VR_CTL() bfin_read16(VR_CTL) 76#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
@@ -56,6 +79,10 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
56{ 79{
57 unsigned long flags, iwr0, iwr1; 80 unsigned long flags, iwr0, iwr1;
58 81
82 if (val == bfin_read_VR_CTL())
83 return;
84
85 local_irq_save(flags);
59 /* Enable the PLL Wakeup bit in SIC IWR */ 86 /* Enable the PLL Wakeup bit in SIC IWR */
60 iwr0 = bfin_read32(SICA_IWR0); 87 iwr0 = bfin_read32(SICA_IWR0);
61 iwr1 = bfin_read32(SICA_IWR1); 88 iwr1 = bfin_read32(SICA_IWR1);
@@ -65,12 +92,11 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
65 92
66 bfin_write16(VR_CTL, val); 93 bfin_write16(VR_CTL, val);
67 SSYNC(); 94 SSYNC();
68
69 local_irq_save(flags);
70 asm("IDLE;"); 95 asm("IDLE;");
71 local_irq_restore(flags); 96
72 bfin_write32(SICA_IWR0, iwr0); 97 bfin_write32(SICA_IWR0, iwr0);
73 bfin_write32(SICA_IWR1, iwr1); 98 bfin_write32(SICA_IWR1, iwr1);
99 local_irq_restore(flags);
74} 100}
75#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) 101#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
76#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) 102#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 09:00:53 -0500