3 files changed, 41 insertions, 18 deletions

diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
index cb7a9e97fd7e..feaa75f0013e 100644
--- a/arch/arm/include/asm/cache.h
+++ b/arch/arm/include/asm/cache.h
@@ -7,4 +7,20 @@
 #define L1_CACHE_SHIFT          5
 #define L1_CACHE_BYTES          (1 << L1_CACHE_SHIFT)
 
+/*
+ * Memory returned by kmalloc() may be used for DMA, so we must make
+ * sure that all such allocations are cache aligned. Otherwise,
+ * unrelated code may cause parts of the buffer to be read into the
+ * cache before the transfer is done, causing old data to be seen by
+ * the CPU.
+ */
+#define ARCH_KMALLOC_MINALIGN   L1_CACHE_BYTES
+
+/*
+ * With EABI on ARMv5 and above we must have 64-bit aligned slab pointers.
+ */
+#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
+#define ARCH_SLAB_MINALIGN 8
+#endif
+
 #endif
diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h
index e6eb8a67b807..7b522770f29d 100644
--- a/arch/arm/include/asm/page.h
+++ b/arch/arm/include/asm/page.h
@@ -202,13 +202,6 @@ typedef struct page *pgtable_t;
         (((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0) | \
          VM_READ | VM_WRITE | VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
 
-/*
- * With EABI on ARMv5 and above we must have 64-bit aligned slab pointers.
- */
-#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
-#define ARCH_SLAB_MINALIGN 8
-#endif
-
 #include <asm-generic/page.h>
 
 #endif
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 3397f1e64d76..a08d9d2380d3 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -184,23 +184,37 @@ __v7_setup:
         stmia   r12, {r0-r5, r7, r9, r11, lr}
         bl      v7_flush_dcache_all
         ldmia   r12, {r0-r5, r7, r9, r11, lr}
+
+        mrc     p15, 0, r0, c0, c0, 0           @ read main ID register
+        and     r10, r0, #0xff000000            @ ARM?
+        teq     r10, #0x41000000
+        bne     2f
+        and     r5, r0, #0x00f00000             @ variant
+        and     r6, r0, #0x0000000f             @ revision
+        orr     r0, r6, r5, lsr #20-4           @ combine variant and revision
+
 #ifdef CONFIG_ARM_ERRATA_430973
-        mrc     p15, 0, r10, c1, c0, 1          @ read aux control register
-        orr     r10, r10, #(1 << 6)             @ set IBE to 1
-        mcr     p15, 0, r10, c1, c0, 1          @ write aux control register
+        teq     r5, #0x00100000                 @ only present in r1p*
+        mrceq   p15, 0, r10, c1, c0, 1          @ read aux control register
+        orreq   r10, r10, #(1 << 6)             @ set IBE to 1
+        mcreq   p15, 0, r10, c1, c0, 1          @ write aux control register
 #endif
 #ifdef CONFIG_ARM_ERRATA_458693
-        mrc     p15, 0, r10, c1, c0, 1          @ read aux control register
-        orr     r10, r10, #(1 << 5)             @ set L1NEON to 1
-        orr     r10, r10, #(1 << 9)             @ set PLDNOP to 1
-        mcr     p15, 0, r10, c1, c0, 1          @ write aux control register
+        teq     r0, #0x20                       @ only present in r2p0
+        mrceq   p15, 0, r10, c1, c0, 1          @ read aux control register
+        orreq   r10, r10, #(1 << 5)             @ set L1NEON to 1
+        orreq   r10, r10, #(1 << 9)             @ set PLDNOP to 1
+        mcreq   p15, 0, r10, c1, c0, 1          @ write aux control register
 #endif
 #ifdef CONFIG_ARM_ERRATA_460075
-        mrc     p15, 1, r10, c9, c0, 2          @ read L2 cache aux ctrl register
-        orr     r10, r10, #(1 << 22)            @ set the Write Allocate disable bit
-        mcr     p15, 1, r10, c9, c0, 2          @ write the L2 cache aux ctrl register
+        teq     r0, #0x20                       @ only present in r2p0
+        mrceq   p15, 1, r10, c9, c0, 2          @ read L2 cache aux ctrl register
+        tsteq   r10, #1 << 22
+        orreq   r10, r10, #(1 << 22)            @ set the Write Allocate disable bit
+        mcreq   p15, 1, r10, c9, c0, 2          @ write the L2 cache aux ctrl register
 #endif
-        mov     r10, #0
+
+2:      mov     r10, #0
 #ifdef HARVARD_CACHE
         mcr     p15, 0, r10, c7, c5, 0          @ I+BTB cache invalidate
 #endif