diff options
-rw-r--r-- | include/asm-arm/arch-s3c2410/regs-gpio.h | 32 |
1 files changed, 29 insertions, 3 deletions
diff --git a/include/asm-arm/arch-s3c2410/regs-gpio.h b/include/asm-arm/arch-s3c2410/regs-gpio.h index eae91694edcd..dea578b8f7f6 100644 --- a/include/asm-arm/arch-s3c2410/regs-gpio.h +++ b/include/asm-arm/arch-s3c2410/regs-gpio.h | |||
@@ -201,7 +201,7 @@ | |||
201 | #define S3C2400_GPBDAT S3C2410_GPIOREG(0x0C) | 201 | #define S3C2400_GPBDAT S3C2410_GPIOREG(0x0C) |
202 | #define S3C2400_GPBUP S3C2410_GPIOREG(0x10) | 202 | #define S3C2400_GPBUP S3C2410_GPIOREG(0x10) |
203 | 203 | ||
204 | /* no i/o pin in port b can have value 3! */ | 204 | /* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */ |
205 | 205 | ||
206 | #define S3C2410_GPB0 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 0) | 206 | #define S3C2410_GPB0 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 0) |
207 | #define S3C2410_GPB0_INP (0x00 << 0) | 207 | #define S3C2410_GPB0_INP (0x00 << 0) |
@@ -242,6 +242,7 @@ | |||
242 | #define S3C2410_GPB5_INP (0x00 << 10) | 242 | #define S3C2410_GPB5_INP (0x00 << 10) |
243 | #define S3C2410_GPB5_OUTP (0x01 << 10) | 243 | #define S3C2410_GPB5_OUTP (0x01 << 10) |
244 | #define S3C2410_GPB5_nXBACK (0x02 << 10) | 244 | #define S3C2410_GPB5_nXBACK (0x02 << 10) |
245 | #define S3C2443_GPB5_XBACK (0x03 << 10) | ||
245 | #define S3C2400_GPB5_DATA21 (0x02 << 10) | 246 | #define S3C2400_GPB5_DATA21 (0x02 << 10) |
246 | #define S3C2400_GPB5_nCTS1 (0x03 << 10) | 247 | #define S3C2400_GPB5_nCTS1 (0x03 << 10) |
247 | 248 | ||
@@ -249,6 +250,7 @@ | |||
249 | #define S3C2410_GPB6_INP (0x00 << 12) | 250 | #define S3C2410_GPB6_INP (0x00 << 12) |
250 | #define S3C2410_GPB6_OUTP (0x01 << 12) | 251 | #define S3C2410_GPB6_OUTP (0x01 << 12) |
251 | #define S3C2410_GPB6_nXBREQ (0x02 << 12) | 252 | #define S3C2410_GPB6_nXBREQ (0x02 << 12) |
253 | #define S3C2443_GPB6_XBREQ (0x03 << 12) | ||
252 | #define S3C2400_GPB6_DATA22 (0x02 << 12) | 254 | #define S3C2400_GPB6_DATA22 (0x02 << 12) |
253 | #define S3C2400_GPB6_nRTS1 (0x03 << 12) | 255 | #define S3C2400_GPB6_nRTS1 (0x03 << 12) |
254 | 256 | ||
@@ -256,6 +258,7 @@ | |||
256 | #define S3C2410_GPB7_INP (0x00 << 14) | 258 | #define S3C2410_GPB7_INP (0x00 << 14) |
257 | #define S3C2410_GPB7_OUTP (0x01 << 14) | 259 | #define S3C2410_GPB7_OUTP (0x01 << 14) |
258 | #define S3C2410_GPB7_nXDACK1 (0x02 << 14) | 260 | #define S3C2410_GPB7_nXDACK1 (0x02 << 14) |
261 | #define S3C2443_GPB7_XDACK1 (0x03 << 14) | ||
259 | #define S3C2400_GPB7_DATA23 (0x02 << 14) | 262 | #define S3C2400_GPB7_DATA23 (0x02 << 14) |
260 | 263 | ||
261 | #define S3C2410_GPB8 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 8) | 264 | #define S3C2410_GPB8 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 8) |
@@ -268,6 +271,7 @@ | |||
268 | #define S3C2410_GPB9_INP (0x00 << 18) | 271 | #define S3C2410_GPB9_INP (0x00 << 18) |
269 | #define S3C2410_GPB9_OUTP (0x01 << 18) | 272 | #define S3C2410_GPB9_OUTP (0x01 << 18) |
270 | #define S3C2410_GPB9_nXDACK0 (0x02 << 18) | 273 | #define S3C2410_GPB9_nXDACK0 (0x02 << 18) |
274 | #define S3C2443_GPB9_XDACK0 (0x03 << 18) | ||
271 | #define S3C2400_GPB9_DATA25 (0x02 << 18) | 275 | #define S3C2400_GPB9_DATA25 (0x02 << 18) |
272 | #define S3C2400_GPB9_I2SSDI (0x03 << 18) | 276 | #define S3C2400_GPB9_I2SSDI (0x03 << 18) |
273 | 277 | ||
@@ -275,6 +279,7 @@ | |||
275 | #define S3C2410_GPB10_INP (0x00 << 20) | 279 | #define S3C2410_GPB10_INP (0x00 << 20) |
276 | #define S3C2410_GPB10_OUTP (0x01 << 20) | 280 | #define S3C2410_GPB10_OUTP (0x01 << 20) |
277 | #define S3C2410_GPB10_nXDRE0 (0x02 << 20) | 281 | #define S3C2410_GPB10_nXDRE0 (0x02 << 20) |
282 | #define S3C2443_GPB10_XDREQ0 (0x03 << 20) | ||
278 | #define S3C2400_GPB10_DATA26 (0x02 << 20) | 283 | #define S3C2400_GPB10_DATA26 (0x02 << 20) |
279 | #define S3C2400_GPB10_nSS (0x03 << 20) | 284 | #define S3C2400_GPB10_nSS (0x03 << 20) |
280 | 285 | ||
@@ -556,6 +561,7 @@ | |||
556 | #define S3C2410_GPE0_INP (0x00 << 0) | 561 | #define S3C2410_GPE0_INP (0x00 << 0) |
557 | #define S3C2410_GPE0_OUTP (0x01 << 0) | 562 | #define S3C2410_GPE0_OUTP (0x01 << 0) |
558 | #define S3C2410_GPE0_I2SLRCK (0x02 << 0) | 563 | #define S3C2410_GPE0_I2SLRCK (0x02 << 0) |
564 | #define S3C2443_GPE0_AC_nRESET (0x03 << 0) | ||
559 | #define S3C2400_GPE0_EINT0 (0x02 << 0) | 565 | #define S3C2400_GPE0_EINT0 (0x02 << 0) |
560 | #define S3C2410_GPE0_MASK (0x03 << 0) | 566 | #define S3C2410_GPE0_MASK (0x03 << 0) |
561 | 567 | ||
@@ -563,6 +569,7 @@ | |||
563 | #define S3C2410_GPE1_INP (0x00 << 2) | 569 | #define S3C2410_GPE1_INP (0x00 << 2) |
564 | #define S3C2410_GPE1_OUTP (0x01 << 2) | 570 | #define S3C2410_GPE1_OUTP (0x01 << 2) |
565 | #define S3C2410_GPE1_I2SSCLK (0x02 << 2) | 571 | #define S3C2410_GPE1_I2SSCLK (0x02 << 2) |
572 | #define S3C2443_GPE1_AC_SYNC (0x03 << 2) | ||
566 | #define S3C2400_GPE1_EINT1 (0x02 << 2) | 573 | #define S3C2400_GPE1_EINT1 (0x02 << 2) |
567 | #define S3C2400_GPE1_nSS (0x03 << 2) | 574 | #define S3C2400_GPE1_nSS (0x03 << 2) |
568 | #define S3C2410_GPE1_MASK (0x03 << 2) | 575 | #define S3C2410_GPE1_MASK (0x03 << 2) |
@@ -571,6 +578,7 @@ | |||
571 | #define S3C2410_GPE2_INP (0x00 << 4) | 578 | #define S3C2410_GPE2_INP (0x00 << 4) |
572 | #define S3C2410_GPE2_OUTP (0x01 << 4) | 579 | #define S3C2410_GPE2_OUTP (0x01 << 4) |
573 | #define S3C2410_GPE2_CDCLK (0x02 << 4) | 580 | #define S3C2410_GPE2_CDCLK (0x02 << 4) |
581 | #define S3C2443_GPE2_AC_BITCLK (0x03 << 4) | ||
574 | #define S3C2400_GPE2_EINT2 (0x02 << 4) | 582 | #define S3C2400_GPE2_EINT2 (0x02 << 4) |
575 | #define S3C2400_GPE2_I2SSDI (0x03 << 4) | 583 | #define S3C2400_GPE2_I2SSDI (0x03 << 4) |
576 | 584 | ||
@@ -578,6 +586,7 @@ | |||
578 | #define S3C2410_GPE3_INP (0x00 << 6) | 586 | #define S3C2410_GPE3_INP (0x00 << 6) |
579 | #define S3C2410_GPE3_OUTP (0x01 << 6) | 587 | #define S3C2410_GPE3_OUTP (0x01 << 6) |
580 | #define S3C2410_GPE3_I2SSDI (0x02 << 6) | 588 | #define S3C2410_GPE3_I2SSDI (0x02 << 6) |
589 | #define S3C2443_GPE3_AC_SDI (0x03 << 6) | ||
581 | #define S3C2400_GPE3_EINT3 (0x02 << 6) | 590 | #define S3C2400_GPE3_EINT3 (0x02 << 6) |
582 | #define S3C2400_GPE3_nCTS1 (0x03 << 6) | 591 | #define S3C2400_GPE3_nCTS1 (0x03 << 6) |
583 | #define S3C2410_GPE3_nSS0 (0x03 << 6) | 592 | #define S3C2410_GPE3_nSS0 (0x03 << 6) |
@@ -587,6 +596,7 @@ | |||
587 | #define S3C2410_GPE4_INP (0x00 << 8) | 596 | #define S3C2410_GPE4_INP (0x00 << 8) |
588 | #define S3C2410_GPE4_OUTP (0x01 << 8) | 597 | #define S3C2410_GPE4_OUTP (0x01 << 8) |
589 | #define S3C2410_GPE4_I2SSDO (0x02 << 8) | 598 | #define S3C2410_GPE4_I2SSDO (0x02 << 8) |
599 | #define S3C2443_GPE4_AC_SDO (0x03 << 8) | ||
590 | #define S3C2400_GPE4_EINT4 (0x02 << 8) | 600 | #define S3C2400_GPE4_EINT4 (0x02 << 8) |
591 | #define S3C2400_GPE4_nRTS1 (0x03 << 8) | 601 | #define S3C2400_GPE4_nRTS1 (0x03 << 8) |
592 | #define S3C2410_GPE4_I2SSDI (0x03 << 8) | 602 | #define S3C2410_GPE4_I2SSDI (0x03 << 8) |
@@ -596,6 +606,7 @@ | |||
596 | #define S3C2410_GPE5_INP (0x00 << 10) | 606 | #define S3C2410_GPE5_INP (0x00 << 10) |
597 | #define S3C2410_GPE5_OUTP (0x01 << 10) | 607 | #define S3C2410_GPE5_OUTP (0x01 << 10) |
598 | #define S3C2410_GPE5_SDCLK (0x02 << 10) | 608 | #define S3C2410_GPE5_SDCLK (0x02 << 10) |
609 | #define S3C2443_GPE5_SD1_CLK (0x02 << 10) | ||
599 | #define S3C2400_GPE5_EINT5 (0x02 << 10) | 610 | #define S3C2400_GPE5_EINT5 (0x02 << 10) |
600 | #define S3C2400_GPE5_TCLK1 (0x03 << 10) | 611 | #define S3C2400_GPE5_TCLK1 (0x03 << 10) |
601 | 612 | ||
@@ -603,24 +614,32 @@ | |||
603 | #define S3C2410_GPE6_INP (0x00 << 12) | 614 | #define S3C2410_GPE6_INP (0x00 << 12) |
604 | #define S3C2410_GPE6_OUTP (0x01 << 12) | 615 | #define S3C2410_GPE6_OUTP (0x01 << 12) |
605 | #define S3C2410_GPE6_SDCMD (0x02 << 12) | 616 | #define S3C2410_GPE6_SDCMD (0x02 << 12) |
617 | #define S3C2443_GPE6_SD1_CMD (0x02 << 12) | ||
618 | #define S3C2443_GPE6_AC_BITCLK (0x03 << 12) | ||
606 | #define S3C2400_GPE6_EINT6 (0x02 << 12) | 619 | #define S3C2400_GPE6_EINT6 (0x02 << 12) |
607 | 620 | ||
608 | #define S3C2410_GPE7 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 7) | 621 | #define S3C2410_GPE7 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 7) |
609 | #define S3C2410_GPE7_INP (0x00 << 14) | 622 | #define S3C2410_GPE7_INP (0x00 << 14) |
610 | #define S3C2410_GPE7_OUTP (0x01 << 14) | 623 | #define S3C2410_GPE7_OUTP (0x01 << 14) |
611 | #define S3C2410_GPE7_SDDAT0 (0x02 << 14) | 624 | #define S3C2410_GPE7_SDDAT0 (0x02 << 14) |
625 | #define S3C2443_GPE5_SD1_DAT0 (0x02 << 14) | ||
626 | #define S3C2443_GPE7_AC_SDI (0x03 << 14) | ||
612 | #define S3C2400_GPE7_EINT7 (0x02 << 14) | 627 | #define S3C2400_GPE7_EINT7 (0x02 << 14) |
613 | 628 | ||
614 | #define S3C2410_GPE8 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 8) | 629 | #define S3C2410_GPE8 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 8) |
615 | #define S3C2410_GPE8_INP (0x00 << 16) | 630 | #define S3C2410_GPE8_INP (0x00 << 16) |
616 | #define S3C2410_GPE8_OUTP (0x01 << 16) | 631 | #define S3C2410_GPE8_OUTP (0x01 << 16) |
617 | #define S3C2410_GPE8_SDDAT1 (0x02 << 16) | 632 | #define S3C2410_GPE8_SDDAT1 (0x02 << 16) |
633 | #define S3C2443_GPE8_SD1_DAT1 (0x02 << 16) | ||
634 | #define S3C2443_GPE8_AC_SDO (0x03 << 16) | ||
618 | #define S3C2400_GPE8_nXDACK0 (0x02 << 16) | 635 | #define S3C2400_GPE8_nXDACK0 (0x02 << 16) |
619 | 636 | ||
620 | #define S3C2410_GPE9 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 9) | 637 | #define S3C2410_GPE9 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 9) |
621 | #define S3C2410_GPE9_INP (0x00 << 18) | 638 | #define S3C2410_GPE9_INP (0x00 << 18) |
622 | #define S3C2410_GPE9_OUTP (0x01 << 18) | 639 | #define S3C2410_GPE9_OUTP (0x01 << 18) |
623 | #define S3C2410_GPE9_SDDAT2 (0x02 << 18) | 640 | #define S3C2410_GPE9_SDDAT2 (0x02 << 18) |
641 | #define S3C2443_GPE9_SD1_DAT2 (0x02 << 18) | ||
642 | #define S3C2443_GPE9_AC_SYNC (0x03 << 18) | ||
624 | #define S3C2400_GPE9_nXDACK1 (0x02 << 18) | 643 | #define S3C2400_GPE9_nXDACK1 (0x02 << 18) |
625 | #define S3C2400_GPE9_nXBACK (0x03 << 18) | 644 | #define S3C2400_GPE9_nXBACK (0x03 << 18) |
626 | 645 | ||
@@ -628,6 +647,8 @@ | |||
628 | #define S3C2410_GPE10_INP (0x00 << 20) | 647 | #define S3C2410_GPE10_INP (0x00 << 20) |
629 | #define S3C2410_GPE10_OUTP (0x01 << 20) | 648 | #define S3C2410_GPE10_OUTP (0x01 << 20) |
630 | #define S3C2410_GPE10_SDDAT3 (0x02 << 20) | 649 | #define S3C2410_GPE10_SDDAT3 (0x02 << 20) |
650 | #define S3C2443_GPE10_SD1_DAT3 (0x02 << 20) | ||
651 | #define S3C2443_GPE10_AC_nRESET (0x03 << 20) | ||
631 | #define S3C2400_GPE10_nXDREQ0 (0x02 << 20) | 652 | #define S3C2400_GPE10_nXDREQ0 (0x02 << 20) |
632 | 653 | ||
633 | #define S3C2410_GPE11 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 11) | 654 | #define S3C2410_GPE11 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 11) |
@@ -796,6 +817,7 @@ | |||
796 | #define S3C2400_GPG4_MMCCLK (0x02 << 8) | 817 | #define S3C2400_GPG4_MMCCLK (0x02 << 8) |
797 | #define S3C2400_GPG4_I2SSDI (0x03 << 8) | 818 | #define S3C2400_GPG4_I2SSDI (0x03 << 8) |
798 | #define S3C2410_GPG4_LCDPWREN (0x03 << 8) | 819 | #define S3C2410_GPG4_LCDPWREN (0x03 << 8) |
820 | #define S3C2443_GPG4_LCDPWRDN (0x03 << 8) | ||
799 | 821 | ||
800 | #define S3C2410_GPG5 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 5) | 822 | #define S3C2410_GPG5 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 5) |
801 | #define S3C2410_GPG5_INP (0x00 << 10) | 823 | #define S3C2410_GPG5_INP (0x00 << 10) |
@@ -803,7 +825,7 @@ | |||
803 | #define S3C2410_GPG5_EINT13 (0x02 << 10) | 825 | #define S3C2410_GPG5_EINT13 (0x02 << 10) |
804 | #define S3C2400_GPG5_MMCCMD (0x02 << 10) | 826 | #define S3C2400_GPG5_MMCCMD (0x02 << 10) |
805 | #define S3C2400_GPG5_IICSDA (0x03 << 10) | 827 | #define S3C2400_GPG5_IICSDA (0x03 << 10) |
806 | #define S3C2410_GPG5_SPIMISO1 (0x03 << 10) | 828 | #define S3C2410_GPG5_SPIMISO1 (0x03 << 10) /* not s3c2443 */ |
807 | 829 | ||
808 | #define S3C2410_GPG6 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 6) | 830 | #define S3C2410_GPG6 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 6) |
809 | #define S3C2410_GPG6_INP (0x00 << 12) | 831 | #define S3C2410_GPG6_INP (0x00 << 12) |
@@ -845,6 +867,7 @@ | |||
845 | #define S3C2410_GPG11_OUTP (0x01 << 22) | 867 | #define S3C2410_GPG11_OUTP (0x01 << 22) |
846 | #define S3C2410_GPG11_EINT19 (0x02 << 22) | 868 | #define S3C2410_GPG11_EINT19 (0x02 << 22) |
847 | #define S3C2410_GPG11_TCLK1 (0x03 << 22) | 869 | #define S3C2410_GPG11_TCLK1 (0x03 << 22) |
870 | #define S3C2443_GPG11_CF_nIREQ (0x03 << 22) | ||
848 | 871 | ||
849 | #define S3C2410_GPG12 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 12) | 872 | #define S3C2410_GPG12 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 12) |
850 | #define S3C2410_GPG12_INP (0x00 << 24) | 873 | #define S3C2410_GPG12_INP (0x00 << 24) |
@@ -852,25 +875,28 @@ | |||
852 | #define S3C2410_GPG12_EINT20 (0x02 << 24) | 875 | #define S3C2410_GPG12_EINT20 (0x02 << 24) |
853 | #define S3C2410_GPG12_XMON (0x03 << 24) | 876 | #define S3C2410_GPG12_XMON (0x03 << 24) |
854 | #define S3C2442_GPG12_nSPICS0 (0x03 << 24) | 877 | #define S3C2442_GPG12_nSPICS0 (0x03 << 24) |
878 | #define S3C2443_GPG12_nINPACK (0x03 << 24) | ||
855 | 879 | ||
856 | #define S3C2410_GPG13 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 13) | 880 | #define S3C2410_GPG13 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 13) |
857 | #define S3C2410_GPG13_INP (0x00 << 26) | 881 | #define S3C2410_GPG13_INP (0x00 << 26) |
858 | #define S3C2410_GPG13_OUTP (0x01 << 26) | 882 | #define S3C2410_GPG13_OUTP (0x01 << 26) |
859 | #define S3C2410_GPG13_EINT21 (0x02 << 26) | 883 | #define S3C2410_GPG13_EINT21 (0x02 << 26) |
860 | #define S3C2410_GPG13_nXPON (0x03 << 26) | 884 | #define S3C2410_GPG13_nXPON (0x03 << 26) |
885 | #define S3C2443_GPG13_CF_nREG (0x03 << 26) | ||
861 | 886 | ||
862 | #define S3C2410_GPG14 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 14) | 887 | #define S3C2410_GPG14 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 14) |
863 | #define S3C2410_GPG14_INP (0x00 << 28) | 888 | #define S3C2410_GPG14_INP (0x00 << 28) |
864 | #define S3C2410_GPG14_OUTP (0x01 << 28) | 889 | #define S3C2410_GPG14_OUTP (0x01 << 28) |
865 | #define S3C2410_GPG14_EINT22 (0x02 << 28) | 890 | #define S3C2410_GPG14_EINT22 (0x02 << 28) |
866 | #define S3C2410_GPG14_YMON (0x03 << 28) | 891 | #define S3C2410_GPG14_YMON (0x03 << 28) |
892 | #define S3C2443_GPG14_CF_RESET (0x03 << 28) | ||
867 | 893 | ||
868 | #define S3C2410_GPG15 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 15) | 894 | #define S3C2410_GPG15 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 15) |
869 | #define S3C2410_GPG15_INP (0x00 << 30) | 895 | #define S3C2410_GPG15_INP (0x00 << 30) |
870 | #define S3C2410_GPG15_OUTP (0x01 << 30) | 896 | #define S3C2410_GPG15_OUTP (0x01 << 30) |
871 | #define S3C2410_GPG15_EINT23 (0x02 << 30) | 897 | #define S3C2410_GPG15_EINT23 (0x02 << 30) |
872 | #define S3C2410_GPG15_nYPON (0x03 << 30) | 898 | #define S3C2410_GPG15_nYPON (0x03 << 30) |
873 | 899 | #define S3C2443_GPG15_CF_PWR (0x03 << 30) | |
874 | 900 | ||
875 | #define S3C2410_GPG_PUPDIS(x) (1<<(x)) | 901 | #define S3C2410_GPG_PUPDIS(x) (1<<(x)) |
876 | 902 | ||