aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--drivers/gpu/drm/radeon/ni.c550
-rw-r--r--drivers/gpu/drm/radeon/nid.h269
-rw-r--r--drivers/gpu/drm/radeon/radeon.h40
-rw-r--r--drivers/gpu/drm/radeon/radeon_kms.c9
4 files changed, 866 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 058aa4f84d19..eaefb5b066db 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -381,3 +381,553 @@ out:
381 return err; 381 return err;
382} 382}
383 383
384/*
385 * Core functions
386 */
387static u32 cayman_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
388 u32 num_tile_pipes,
389 u32 num_backends_per_asic,
390 u32 *backend_disable_mask_per_asic,
391 u32 num_shader_engines)
392{
393 u32 backend_map = 0;
394 u32 enabled_backends_mask = 0;
395 u32 enabled_backends_count = 0;
396 u32 num_backends_per_se;
397 u32 cur_pipe;
398 u32 swizzle_pipe[CAYMAN_MAX_PIPES];
399 u32 cur_backend = 0;
400 u32 i;
401 bool force_no_swizzle;
402
403 /* force legal values */
404 if (num_tile_pipes < 1)
405 num_tile_pipes = 1;
406 if (num_tile_pipes > rdev->config.cayman.max_tile_pipes)
407 num_tile_pipes = rdev->config.cayman.max_tile_pipes;
408 if (num_shader_engines < 1)
409 num_shader_engines = 1;
410 if (num_shader_engines > rdev->config.cayman.max_shader_engines)
411 num_shader_engines = rdev->config.cayman.max_shader_engines;
412 if (num_backends_per_asic > num_shader_engines)
413 num_backends_per_asic = num_shader_engines;
414 if (num_backends_per_asic > (rdev->config.cayman.max_backends_per_se * num_shader_engines))
415 num_backends_per_asic = rdev->config.cayman.max_backends_per_se * num_shader_engines;
416
417 /* make sure we have the same number of backends per se */
418 num_backends_per_asic = ALIGN(num_backends_per_asic, num_shader_engines);
419 /* set up the number of backends per se */
420 num_backends_per_se = num_backends_per_asic / num_shader_engines;
421 if (num_backends_per_se > rdev->config.cayman.max_backends_per_se) {
422 num_backends_per_se = rdev->config.cayman.max_backends_per_se;
423 num_backends_per_asic = num_backends_per_se * num_shader_engines;
424 }
425
426 /* create enable mask and count for enabled backends */
427 for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) {
428 if (((*backend_disable_mask_per_asic >> i) & 1) == 0) {
429 enabled_backends_mask |= (1 << i);
430 ++enabled_backends_count;
431 }
432 if (enabled_backends_count == num_backends_per_asic)
433 break;
434 }
435
436 /* force the backends mask to match the current number of backends */
437 if (enabled_backends_count != num_backends_per_asic) {
438 u32 this_backend_enabled;
439 u32 shader_engine;
440 u32 backend_per_se;
441
442 enabled_backends_mask = 0;
443 enabled_backends_count = 0;
444 *backend_disable_mask_per_asic = CAYMAN_MAX_BACKENDS_MASK;
445 for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) {
446 /* calc the current se */
447 shader_engine = i / rdev->config.cayman.max_backends_per_se;
448 /* calc the backend per se */
449 backend_per_se = i % rdev->config.cayman.max_backends_per_se;
450 /* default to not enabled */
451 this_backend_enabled = 0;
452 if ((shader_engine < num_shader_engines) &&
453 (backend_per_se < num_backends_per_se))
454 this_backend_enabled = 1;
455 if (this_backend_enabled) {
456 enabled_backends_mask |= (1 << i);
457 *backend_disable_mask_per_asic &= ~(1 << i);
458 ++enabled_backends_count;
459 }
460 }
461 }
462
463
464 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * CAYMAN_MAX_PIPES);
465 switch (rdev->family) {
466 case CHIP_CAYMAN:
467 force_no_swizzle = true;
468 break;
469 default:
470 force_no_swizzle = false;
471 break;
472 }
473 if (force_no_swizzle) {
474 bool last_backend_enabled = false;
475
476 force_no_swizzle = false;
477 for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) {
478 if (((enabled_backends_mask >> i) & 1) == 1) {
479 if (last_backend_enabled)
480 force_no_swizzle = true;
481 last_backend_enabled = true;
482 } else
483 last_backend_enabled = false;
484 }
485 }
486
487 switch (num_tile_pipes) {
488 case 1:
489 case 3:
490 case 5:
491 case 7:
492 DRM_ERROR("odd number of pipes!\n");
493 break;
494 case 2:
495 swizzle_pipe[0] = 0;
496 swizzle_pipe[1] = 1;
497 break;
498 case 4:
499 if (force_no_swizzle) {
500 swizzle_pipe[0] = 0;
501 swizzle_pipe[1] = 1;
502 swizzle_pipe[2] = 2;
503 swizzle_pipe[3] = 3;
504 } else {
505 swizzle_pipe[0] = 0;
506 swizzle_pipe[1] = 2;
507 swizzle_pipe[2] = 1;
508 swizzle_pipe[3] = 3;
509 }
510 break;
511 case 6:
512 if (force_no_swizzle) {
513 swizzle_pipe[0] = 0;
514 swizzle_pipe[1] = 1;
515 swizzle_pipe[2] = 2;
516 swizzle_pipe[3] = 3;
517 swizzle_pipe[4] = 4;
518 swizzle_pipe[5] = 5;
519 } else {
520 swizzle_pipe[0] = 0;
521 swizzle_pipe[1] = 2;
522 swizzle_pipe[2] = 4;
523 swizzle_pipe[3] = 1;
524 swizzle_pipe[4] = 3;
525 swizzle_pipe[5] = 5;
526 }
527 break;
528 case 8:
529 if (force_no_swizzle) {
530 swizzle_pipe[0] = 0;
531 swizzle_pipe[1] = 1;
532 swizzle_pipe[2] = 2;
533 swizzle_pipe[3] = 3;
534 swizzle_pipe[4] = 4;
535 swizzle_pipe[5] = 5;
536 swizzle_pipe[6] = 6;
537 swizzle_pipe[7] = 7;
538 } else {
539 swizzle_pipe[0] = 0;
540 swizzle_pipe[1] = 2;
541 swizzle_pipe[2] = 4;
542 swizzle_pipe[3] = 6;
543 swizzle_pipe[4] = 1;
544 swizzle_pipe[5] = 3;
545 swizzle_pipe[6] = 5;
546 swizzle_pipe[7] = 7;
547 }
548 break;
549 }
550
551 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
552 while (((1 << cur_backend) & enabled_backends_mask) == 0)
553 cur_backend = (cur_backend + 1) % CAYMAN_MAX_BACKENDS;
554
555 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
556
557 cur_backend = (cur_backend + 1) % CAYMAN_MAX_BACKENDS;
558 }
559
560 return backend_map;
561}
562
563static void cayman_program_channel_remap(struct radeon_device *rdev)
564{
565 u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp;
566
567 tmp = RREG32(MC_SHARED_CHMAP);
568 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
569 case 0:
570 case 1:
571 case 2:
572 case 3:
573 default:
574 /* default mapping */
575 mc_shared_chremap = 0x00fac688;
576 break;
577 }
578
579 switch (rdev->family) {
580 case CHIP_CAYMAN:
581 default:
582 //tcp_chan_steer_lo = 0x54763210
583 tcp_chan_steer_lo = 0x76543210;
584 tcp_chan_steer_hi = 0x0000ba98;
585 break;
586 }
587
588 WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo);
589 WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi);
590 WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
591}
592
593static u32 cayman_get_disable_mask_per_asic(struct radeon_device *rdev,
594 u32 disable_mask_per_se,
595 u32 max_disable_mask_per_se,
596 u32 num_shader_engines)
597{
598 u32 disable_field_width_per_se = r600_count_pipe_bits(disable_mask_per_se);
599 u32 disable_mask_per_asic = disable_mask_per_se & max_disable_mask_per_se;
600
601 if (num_shader_engines == 1)
602 return disable_mask_per_asic;
603 else if (num_shader_engines == 2)
604 return disable_mask_per_asic | (disable_mask_per_asic << disable_field_width_per_se);
605 else
606 return 0xffffffff;
607}
608
609static void cayman_gpu_init(struct radeon_device *rdev)
610{
611 u32 cc_rb_backend_disable = 0;
612 u32 cc_gc_shader_pipe_config;
613 u32 gb_addr_config = 0;
614 u32 mc_shared_chmap, mc_arb_ramcfg;
615 u32 gb_backend_map;
616 u32 cgts_tcc_disable;
617 u32 sx_debug_1;
618 u32 smx_dc_ctl0;
619 u32 gc_user_shader_pipe_config;
620 u32 gc_user_rb_backend_disable;
621 u32 cgts_user_tcc_disable;
622 u32 cgts_sm_ctrl_reg;
623 u32 hdp_host_path_cntl;
624 u32 tmp;
625 int i, j;
626
627 switch (rdev->family) {
628 case CHIP_CAYMAN:
629 default:
630 rdev->config.cayman.max_shader_engines = 2;
631 rdev->config.cayman.max_pipes_per_simd = 4;
632 rdev->config.cayman.max_tile_pipes = 8;
633 rdev->config.cayman.max_simds_per_se = 12;
634 rdev->config.cayman.max_backends_per_se = 4;
635 rdev->config.cayman.max_texture_channel_caches = 8;
636 rdev->config.cayman.max_gprs = 256;
637 rdev->config.cayman.max_threads = 256;
638 rdev->config.cayman.max_gs_threads = 32;
639 rdev->config.cayman.max_stack_entries = 512;
640 rdev->config.cayman.sx_num_of_sets = 8;
641 rdev->config.cayman.sx_max_export_size = 256;
642 rdev->config.cayman.sx_max_export_pos_size = 64;
643 rdev->config.cayman.sx_max_export_smx_size = 192;
644 rdev->config.cayman.max_hw_contexts = 8;
645 rdev->config.cayman.sq_num_cf_insts = 2;
646
647 rdev->config.cayman.sc_prim_fifo_size = 0x100;
648 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
649 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
650 break;
651 }
652
653 /* Initialize HDP */
654 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
655 WREG32((0x2c14 + j), 0x00000000);
656 WREG32((0x2c18 + j), 0x00000000);
657 WREG32((0x2c1c + j), 0x00000000);
658 WREG32((0x2c20 + j), 0x00000000);
659 WREG32((0x2c24 + j), 0x00000000);
660 }
661
662 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
663
664 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
665 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
666
667 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE);
668 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG);
669 cgts_tcc_disable = RREG32(CGTS_TCC_DISABLE);
670 gc_user_rb_backend_disable = RREG32(GC_USER_RB_BACKEND_DISABLE);
671 gc_user_shader_pipe_config = RREG32(GC_USER_SHADER_PIPE_CONFIG);
672 cgts_user_tcc_disable = RREG32(CGTS_USER_TCC_DISABLE);
673
674 rdev->config.cayman.num_shader_engines = rdev->config.cayman.max_shader_engines;
675 tmp = ((~gc_user_shader_pipe_config) & INACTIVE_QD_PIPES_MASK) >> INACTIVE_QD_PIPES_SHIFT;
676 rdev->config.cayman.num_shader_pipes_per_simd = r600_count_pipe_bits(tmp);
677 rdev->config.cayman.num_tile_pipes = rdev->config.cayman.max_tile_pipes;
678 tmp = ((~gc_user_shader_pipe_config) & INACTIVE_SIMDS_MASK) >> INACTIVE_SIMDS_SHIFT;
679 rdev->config.cayman.num_simds_per_se = r600_count_pipe_bits(tmp);
680 tmp = ((~gc_user_rb_backend_disable) & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT;
681 rdev->config.cayman.num_backends_per_se = r600_count_pipe_bits(tmp);
682 tmp = (gc_user_rb_backend_disable & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT;
683 rdev->config.cayman.backend_disable_mask_per_asic =
684 cayman_get_disable_mask_per_asic(rdev, tmp, CAYMAN_MAX_BACKENDS_PER_SE_MASK,
685 rdev->config.cayman.num_shader_engines);
686 rdev->config.cayman.backend_map =
687 cayman_get_tile_pipe_to_backend_map(rdev, rdev->config.cayman.num_tile_pipes,
688 rdev->config.cayman.num_backends_per_se *
689 rdev->config.cayman.num_shader_engines,
690 &rdev->config.cayman.backend_disable_mask_per_asic,
691 rdev->config.cayman.num_shader_engines);
692 tmp = ((~cgts_user_tcc_disable) & TCC_DISABLE_MASK) >> TCC_DISABLE_SHIFT;
693 rdev->config.cayman.num_texture_channel_caches = r600_count_pipe_bits(tmp);
694 tmp = (mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT;
695 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
696 if (rdev->config.cayman.mem_max_burst_length_bytes > 512)
697 rdev->config.cayman.mem_max_burst_length_bytes = 512;
698 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
699 rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
700 if (rdev->config.cayman.mem_row_size_in_kb > 4)
701 rdev->config.cayman.mem_row_size_in_kb = 4;
702 /* XXX use MC settings? */
703 rdev->config.cayman.shader_engine_tile_size = 32;
704 rdev->config.cayman.num_gpus = 1;
705 rdev->config.cayman.multi_gpu_tile_size = 64;
706
707 //gb_addr_config = 0x02011003
708#if 0
709 gb_addr_config = RREG32(GB_ADDR_CONFIG);
710#else
711 gb_addr_config = 0;
712 switch (rdev->config.cayman.num_tile_pipes) {
713 case 1:
714 default:
715 gb_addr_config |= NUM_PIPES(0);
716 break;
717 case 2:
718 gb_addr_config |= NUM_PIPES(1);
719 break;
720 case 4:
721 gb_addr_config |= NUM_PIPES(2);
722 break;
723 case 8:
724 gb_addr_config |= NUM_PIPES(3);
725 break;
726 }
727
728 tmp = (rdev->config.cayman.mem_max_burst_length_bytes / 256) - 1;
729 gb_addr_config |= PIPE_INTERLEAVE_SIZE(tmp);
730 gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.cayman.num_shader_engines - 1);
731 tmp = (rdev->config.cayman.shader_engine_tile_size / 16) - 1;
732 gb_addr_config |= SHADER_ENGINE_TILE_SIZE(tmp);
733 switch (rdev->config.cayman.num_gpus) {
734 case 1:
735 default:
736 gb_addr_config |= NUM_GPUS(0);
737 break;
738 case 2:
739 gb_addr_config |= NUM_GPUS(1);
740 break;
741 case 4:
742 gb_addr_config |= NUM_GPUS(2);
743 break;
744 }
745 switch (rdev->config.cayman.multi_gpu_tile_size) {
746 case 16:
747 gb_addr_config |= MULTI_GPU_TILE_SIZE(0);
748 break;
749 case 32:
750 default:
751 gb_addr_config |= MULTI_GPU_TILE_SIZE(1);
752 break;
753 case 64:
754 gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
755 break;
756 case 128:
757 gb_addr_config |= MULTI_GPU_TILE_SIZE(3);
758 break;
759 }
760 switch (rdev->config.cayman.mem_row_size_in_kb) {
761 case 1:
762 default:
763 gb_addr_config |= ROW_SIZE(0);
764 break;
765 case 2:
766 gb_addr_config |= ROW_SIZE(1);
767 break;
768 case 4:
769 gb_addr_config |= ROW_SIZE(2);
770 break;
771 }
772#endif
773
774 tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
775 rdev->config.cayman.num_tile_pipes = (1 << tmp);
776 tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
777 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
778 tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
779 rdev->config.cayman.num_shader_engines = tmp + 1;
780 tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
781 rdev->config.cayman.num_gpus = tmp + 1;
782 tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
783 rdev->config.cayman.multi_gpu_tile_size = 1 << tmp;
784 tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
785 rdev->config.cayman.mem_row_size_in_kb = 1 << tmp;
786
787 //gb_backend_map = 0x76541032;
788#if 0
789 gb_backend_map = RREG32(GB_BACKEND_MAP);
790#else
791 gb_backend_map =
792 cayman_get_tile_pipe_to_backend_map(rdev, rdev->config.cayman.num_tile_pipes,
793 rdev->config.cayman.num_backends_per_se *
794 rdev->config.cayman.num_shader_engines,
795 &rdev->config.cayman.backend_disable_mask_per_asic,
796 rdev->config.cayman.num_shader_engines);
797#endif
798 /* setup tiling info dword. gb_addr_config is not adequate since it does
799 * not have bank info, so create a custom tiling dword.
800 * bits 3:0 num_pipes
801 * bits 7:4 num_banks
802 * bits 11:8 group_size
803 * bits 15:12 row_size
804 */
805 rdev->config.cayman.tile_config = 0;
806 switch (rdev->config.cayman.num_tile_pipes) {
807 case 1:
808 default:
809 rdev->config.cayman.tile_config |= (0 << 0);
810 break;
811 case 2:
812 rdev->config.cayman.tile_config |= (1 << 0);
813 break;
814 case 4:
815 rdev->config.cayman.tile_config |= (2 << 0);
816 break;
817 case 8:
818 rdev->config.cayman.tile_config |= (3 << 0);
819 break;
820 }
821 rdev->config.cayman.tile_config |=
822 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
823 rdev->config.cayman.tile_config |=
824 (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
825 rdev->config.cayman.tile_config |=
826 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
827
828 WREG32(GB_BACKEND_MAP, gb_backend_map);
829 WREG32(GB_ADDR_CONFIG, gb_addr_config);
830 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
831 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
832
833 cayman_program_channel_remap(rdev);
834
835 /* primary versions */
836 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
837 WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
838 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
839
840 WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);
841 WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable);
842
843 /* user versions */
844 WREG32(GC_USER_RB_BACKEND_DISABLE, cc_rb_backend_disable);
845 WREG32(GC_USER_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
846 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
847
848 WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable);
849 WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable);
850
851 /* reprogram the shader complex */
852 cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG);
853 for (i = 0; i < 16; i++)
854 WREG32(CGTS_SM_CTRL_REG, OVERRIDE);
855 WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);
856
857 /* set HW defaults for 3D engine */
858 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
859
860 sx_debug_1 = RREG32(SX_DEBUG_1);
861 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
862 WREG32(SX_DEBUG_1, sx_debug_1);
863
864 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
865 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
866 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
867 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
868
869 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE);
870
871 /* need to be explicitly zero-ed */
872 WREG32(VGT_OFFCHIP_LDS_BASE, 0);
873 WREG32(SQ_LSTMP_RING_BASE, 0);
874 WREG32(SQ_HSTMP_RING_BASE, 0);
875 WREG32(SQ_ESTMP_RING_BASE, 0);
876 WREG32(SQ_GSTMP_RING_BASE, 0);
877 WREG32(SQ_VSTMP_RING_BASE, 0);
878 WREG32(SQ_PSTMP_RING_BASE, 0);
879
880 WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO);
881
882 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
883 POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
884 SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
885
886 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
887 SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
888 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
889
890
891 WREG32(VGT_NUM_INSTANCES, 1);
892
893 WREG32(CP_PERFMON_CNTL, 0);
894
895 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
896 FETCH_FIFO_HIWATER(0x4) |
897 DONE_FIFO_HIWATER(0xe0) |
898 ALU_UPDATE_FIFO_HIWATER(0x8)));
899
900 WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4));
901 WREG32(SQ_CONFIG, (VC_ENABLE |
902 EXPORT_SRC_C |
903 GFX_PRIO(0) |
904 CS1_PRIO(0) |
905 CS2_PRIO(1)));
906 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE);
907
908 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
909 FORCE_EOV_MAX_REZ_CNT(255)));
910
911 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
912 AUTO_INVLD_EN(ES_AND_GS_AUTO));
913
914 WREG32(VGT_GS_VERTEX_REUSE, 16);
915 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
916
917 WREG32(CB_PERF_CTR0_SEL_0, 0);
918 WREG32(CB_PERF_CTR0_SEL_1, 0);
919 WREG32(CB_PERF_CTR1_SEL_0, 0);
920 WREG32(CB_PERF_CTR1_SEL_1, 0);
921 WREG32(CB_PERF_CTR2_SEL_0, 0);
922 WREG32(CB_PERF_CTR2_SEL_1, 0);
923 WREG32(CB_PERF_CTR3_SEL_0, 0);
924 WREG32(CB_PERF_CTR3_SEL_1, 0);
925
926 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
927 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
928
929 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
930
931 udelay(50);
932}
933
diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h
index f7b445390e02..b4ba1b013ccb 100644
--- a/drivers/gpu/drm/radeon/nid.h
+++ b/drivers/gpu/drm/radeon/nid.h
@@ -24,7 +24,44 @@
24#ifndef NI_H 24#ifndef NI_H
25#define NI_H 25#define NI_H
26 26
27#define CAYMAN_MAX_SH_GPRS 256
28#define CAYMAN_MAX_TEMP_GPRS 16
29#define CAYMAN_MAX_SH_THREADS 256
30#define CAYMAN_MAX_SH_STACK_ENTRIES 4096
31#define CAYMAN_MAX_FRC_EOV_CNT 16384
32#define CAYMAN_MAX_BACKENDS 8
33#define CAYMAN_MAX_BACKENDS_MASK 0xFF
34#define CAYMAN_MAX_BACKENDS_PER_SE_MASK 0xF
35#define CAYMAN_MAX_SIMDS 16
36#define CAYMAN_MAX_SIMDS_MASK 0xFFFF
37#define CAYMAN_MAX_SIMDS_PER_SE_MASK 0xFFF
38#define CAYMAN_MAX_PIPES 8
39#define CAYMAN_MAX_PIPES_MASK 0xFF
40#define CAYMAN_MAX_LDS_NUM 0xFFFF
41#define CAYMAN_MAX_TCC 16
42#define CAYMAN_MAX_TCC_MASK 0xFF
43
44#define DMIF_ADDR_CONFIG 0xBD4
45
46#define MC_SHARED_CHMAP 0x2004
47#define NOOFCHAN_SHIFT 12
48#define NOOFCHAN_MASK 0x00003000
49#define MC_SHARED_CHREMAP 0x2008
27#define MC_SHARED_BLACKOUT_CNTL 0x20ac 50#define MC_SHARED_BLACKOUT_CNTL 0x20ac
51#define MC_ARB_RAMCFG 0x2760
52#define NOOFBANK_SHIFT 0
53#define NOOFBANK_MASK 0x00000003
54#define NOOFRANK_SHIFT 2
55#define NOOFRANK_MASK 0x00000004
56#define NOOFROWS_SHIFT 3
57#define NOOFROWS_MASK 0x00000038
58#define NOOFCOLS_SHIFT 6
59#define NOOFCOLS_MASK 0x000000C0
60#define CHANSIZE_SHIFT 8
61#define CHANSIZE_MASK 0x00000100
62#define BURSTLENGTH_SHIFT 9
63#define BURSTLENGTH_MASK 0x00000200
64#define CHANSIZE_OVERRIDE (1 << 11)
28#define MC_SEQ_SUP_CNTL 0x28c8 65#define MC_SEQ_SUP_CNTL 0x28c8
29#define RUN_MASK (1 << 0) 66#define RUN_MASK (1 << 0)
30#define MC_SEQ_SUP_PGM 0x28cc 67#define MC_SEQ_SUP_PGM 0x28cc
@@ -37,5 +74,237 @@
37#define MC_SEQ_IO_DEBUG_INDEX 0x2a44 74#define MC_SEQ_IO_DEBUG_INDEX 0x2a44
38#define MC_SEQ_IO_DEBUG_DATA 0x2a48 75#define MC_SEQ_IO_DEBUG_DATA 0x2a48
39 76
77#define HDP_HOST_PATH_CNTL 0x2C00
78#define HDP_NONSURFACE_BASE 0x2C04
79#define HDP_NONSURFACE_INFO 0x2C08
80#define HDP_NONSURFACE_SIZE 0x2C0C
81#define HDP_ADDR_CONFIG 0x2F48
82
83#define CC_SYS_RB_BACKEND_DISABLE 0x3F88
84#define GC_USER_SYS_RB_BACKEND_DISABLE 0x3F8C
85#define CGTS_SYS_TCC_DISABLE 0x3F90
86#define CGTS_USER_SYS_TCC_DISABLE 0x3F94
87
88#define CONFIG_MEMSIZE 0x5428
89
90#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
91
92#define GRBM_CNTL 0x8000
93#define GRBM_READ_TIMEOUT(x) ((x) << 0)
94#define GRBM_STATUS 0x8010
95#define CMDFIFO_AVAIL_MASK 0x0000000F
96#define RING2_RQ_PENDING (1 << 4)
97#define SRBM_RQ_PENDING (1 << 5)
98#define RING1_RQ_PENDING (1 << 6)
99#define CF_RQ_PENDING (1 << 7)
100#define PF_RQ_PENDING (1 << 8)
101#define GDS_DMA_RQ_PENDING (1 << 9)
102#define GRBM_EE_BUSY (1 << 10)
103#define SX_CLEAN (1 << 11)
104#define DB_CLEAN (1 << 12)
105#define CB_CLEAN (1 << 13)
106#define TA_BUSY (1 << 14)
107#define GDS_BUSY (1 << 15)
108#define VGT_BUSY_NO_DMA (1 << 16)
109#define VGT_BUSY (1 << 17)
110#define IA_BUSY_NO_DMA (1 << 18)
111#define IA_BUSY (1 << 19)
112#define SX_BUSY (1 << 20)
113#define SH_BUSY (1 << 21)
114#define SPI_BUSY (1 << 22)
115#define SC_BUSY (1 << 24)
116#define PA_BUSY (1 << 25)
117#define DB_BUSY (1 << 26)
118#define CP_COHERENCY_BUSY (1 << 28)
119#define CP_BUSY (1 << 29)
120#define CB_BUSY (1 << 30)
121#define GUI_ACTIVE (1 << 31)
122#define GRBM_STATUS_SE0 0x8014
123#define GRBM_STATUS_SE1 0x8018
124#define SE_SX_CLEAN (1 << 0)
125#define SE_DB_CLEAN (1 << 1)
126#define SE_CB_CLEAN (1 << 2)
127#define SE_VGT_BUSY (1 << 23)
128#define SE_PA_BUSY (1 << 24)
129#define SE_TA_BUSY (1 << 25)
130#define SE_SX_BUSY (1 << 26)
131#define SE_SPI_BUSY (1 << 27)
132#define SE_SH_BUSY (1 << 28)
133#define SE_SC_BUSY (1 << 29)
134#define SE_DB_BUSY (1 << 30)
135#define SE_CB_BUSY (1 << 31)
136#define GRBM_SOFT_RESET 0x8020
137#define SOFT_RESET_CP (1 << 0)
138#define SOFT_RESET_CB (1 << 1)
139#define SOFT_RESET_DB (1 << 3)
140#define SOFT_RESET_GDS (1 << 4)
141#define SOFT_RESET_PA (1 << 5)
142#define SOFT_RESET_SC (1 << 6)
143#define SOFT_RESET_SPI (1 << 8)
144#define SOFT_RESET_SH (1 << 9)
145#define SOFT_RESET_SX (1 << 10)
146#define SOFT_RESET_TC (1 << 11)
147#define SOFT_RESET_TA (1 << 12)
148#define SOFT_RESET_VGT (1 << 14)
149#define SOFT_RESET_IA (1 << 15)
150
151#define CP_MEQ_THRESHOLDS 0x8764
152#define MEQ1_START(x) ((x) << 0)
153#define MEQ2_START(x) ((x) << 8)
154#define CP_PERFMON_CNTL 0x87FC
155
156#define VGT_CACHE_INVALIDATION 0x88C4
157#define CACHE_INVALIDATION(x) ((x) << 0)
158#define VC_ONLY 0
159#define TC_ONLY 1
160#define VC_AND_TC 2
161#define AUTO_INVLD_EN(x) ((x) << 6)
162#define NO_AUTO 0
163#define ES_AUTO 1
164#define GS_AUTO 2
165#define ES_AND_GS_AUTO 3
166#define VGT_GS_VERTEX_REUSE 0x88D4
167
168#define CC_GC_SHADER_PIPE_CONFIG 0x8950
169#define GC_USER_SHADER_PIPE_CONFIG 0x8954
170#define INACTIVE_QD_PIPES(x) ((x) << 8)
171#define INACTIVE_QD_PIPES_MASK 0x0000FF00
172#define INACTIVE_QD_PIPES_SHIFT 8
173#define INACTIVE_SIMDS(x) ((x) << 16)
174#define INACTIVE_SIMDS_MASK 0xFFFF0000
175#define INACTIVE_SIMDS_SHIFT 16
176
177#define VGT_PRIMITIVE_TYPE 0x8958
178#define VGT_NUM_INSTANCES 0x8974
179#define VGT_TF_RING_SIZE 0x8988
180#define VGT_OFFCHIP_LDS_BASE 0x89b4
181
182#define PA_SC_LINE_STIPPLE_STATE 0x8B10
183#define PA_CL_ENHANCE 0x8A14
184#define CLIP_VTX_REORDER_ENA (1 << 0)
185#define NUM_CLIP_SEQ(x) ((x) << 1)
186#define PA_SC_FIFO_SIZE 0x8BCC
187#define SC_PRIM_FIFO_SIZE(x) ((x) << 0)
188#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12)
189#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20)
190#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
191#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
192#define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
193
194#define SQ_CONFIG 0x8C00
195#define VC_ENABLE (1 << 0)
196#define EXPORT_SRC_C (1 << 1)
197#define GFX_PRIO(x) ((x) << 2)
198#define CS1_PRIO(x) ((x) << 4)
199#define CS2_PRIO(x) ((x) << 6)
200#define SQ_GPR_RESOURCE_MGMT_1 0x8C04
201#define NUM_PS_GPRS(x) ((x) << 0)
202#define NUM_VS_GPRS(x) ((x) << 16)
203#define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)
204#define SQ_ESGS_RING_SIZE 0x8c44
205#define SQ_GSVS_RING_SIZE 0x8c4c
206#define SQ_ESTMP_RING_BASE 0x8c50
207#define SQ_ESTMP_RING_SIZE 0x8c54
208#define SQ_GSTMP_RING_BASE 0x8c58
209#define SQ_GSTMP_RING_SIZE 0x8c5c
210#define SQ_VSTMP_RING_BASE 0x8c60
211#define SQ_VSTMP_RING_SIZE 0x8c64
212#define SQ_PSTMP_RING_BASE 0x8c68
213#define SQ_PSTMP_RING_SIZE 0x8c6c
214#define SQ_MS_FIFO_SIZES 0x8CF0
215#define CACHE_FIFO_SIZE(x) ((x) << 0)
216#define FETCH_FIFO_HIWATER(x) ((x) << 8)
217#define DONE_FIFO_HIWATER(x) ((x) << 16)
218#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)
219#define SQ_LSTMP_RING_BASE 0x8e10
220#define SQ_LSTMP_RING_SIZE 0x8e14
221#define SQ_HSTMP_RING_BASE 0x8e18
222#define SQ_HSTMP_RING_SIZE 0x8e1c
223#define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C
224#define DYN_GPR_ENABLE (1 << 8)
225#define SQ_CONST_MEM_BASE 0x8df8
226
227#define SX_EXPORT_BUFFER_SIZES 0x900C
228#define COLOR_BUFFER_SIZE(x) ((x) << 0)
229#define POSITION_BUFFER_SIZE(x) ((x) << 8)
230#define SMX_BUFFER_SIZE(x) ((x) << 16)
231#define SX_DEBUG_1 0x9058
232#define ENABLE_NEW_SMX_ADDRESS (1 << 16)
233
234#define SPI_CONFIG_CNTL 0x9100
235#define GPR_WRITE_PRIORITY(x) ((x) << 0)
236#define SPI_CONFIG_CNTL_1 0x913C
237#define VTX_DONE_DELAY(x) ((x) << 0)
238#define INTERP_ONE_PRIM_PER_ROW (1 << 4)
239#define CRC_SIMD_ID_WADDR_DISABLE (1 << 8)
240
241#define CGTS_TCC_DISABLE 0x9148
242#define CGTS_USER_TCC_DISABLE 0x914C
243#define TCC_DISABLE_MASK 0xFFFF0000
244#define TCC_DISABLE_SHIFT 16
245#define CGTS_SM_CTRL_REG 0x915C
246#define OVERRIDE (1 << 21)
247
248#define TA_CNTL_AUX 0x9508
249#define DISABLE_CUBE_WRAP (1 << 0)
250#define DISABLE_CUBE_ANISO (1 << 1)
251
252#define TCP_CHAN_STEER_LO 0x960c
253#define TCP_CHAN_STEER_HI 0x9610
254
255#define CC_RB_BACKEND_DISABLE 0x98F4
256#define BACKEND_DISABLE(x) ((x) << 16)
257#define GB_ADDR_CONFIG 0x98F8
258#define NUM_PIPES(x) ((x) << 0)
259#define NUM_PIPES_MASK 0x00000007
260#define NUM_PIPES_SHIFT 0
261#define PIPE_INTERLEAVE_SIZE(x) ((x) << 4)
262#define PIPE_INTERLEAVE_SIZE_MASK 0x00000070
263#define PIPE_INTERLEAVE_SIZE_SHIFT 4
264#define BANK_INTERLEAVE_SIZE(x) ((x) << 8)
265#define NUM_SHADER_ENGINES(x) ((x) << 12)
266#define NUM_SHADER_ENGINES_MASK 0x00003000
267#define NUM_SHADER_ENGINES_SHIFT 12
268#define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16)
269#define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000
270#define SHADER_ENGINE_TILE_SIZE_SHIFT 16
271#define NUM_GPUS(x) ((x) << 20)
272#define NUM_GPUS_MASK 0x00700000
273#define NUM_GPUS_SHIFT 20
274#define MULTI_GPU_TILE_SIZE(x) ((x) << 24)
275#define MULTI_GPU_TILE_SIZE_MASK 0x03000000
276#define MULTI_GPU_TILE_SIZE_SHIFT 24
277#define ROW_SIZE(x) ((x) << 28)
278#define ROW_SIZE_MASK 0x30000007
279#define ROW_SIZE_SHIFT 28
280#define NUM_LOWER_PIPES(x) ((x) << 30)
281#define NUM_LOWER_PIPES_MASK 0x40000000
282#define NUM_LOWER_PIPES_SHIFT 30
283#define GB_BACKEND_MAP 0x98FC
284
285#define CB_PERF_CTR0_SEL_0 0x9A20
286#define CB_PERF_CTR0_SEL_1 0x9A24
287#define CB_PERF_CTR1_SEL_0 0x9A28
288#define CB_PERF_CTR1_SEL_1 0x9A2C
289#define CB_PERF_CTR2_SEL_0 0x9A30
290#define CB_PERF_CTR2_SEL_1 0x9A34
291#define CB_PERF_CTR3_SEL_0 0x9A38
292#define CB_PERF_CTR3_SEL_1 0x9A3C
293
294#define GC_USER_RB_BACKEND_DISABLE 0x9B7C
295#define BACKEND_DISABLE_MASK 0x00FF0000
296#define BACKEND_DISABLE_SHIFT 16
297
298#define SMX_DC_CTL0 0xA020
299#define USE_HASH_FUNCTION (1 << 0)
300#define NUMBER_OF_SETS(x) ((x) << 1)
301#define FLUSH_ALL_ON_EVENT (1 << 10)
302#define STALL_ON_EVENT (1 << 11)
303#define SMX_EVENT_CTL 0xA02C
304#define ES_FLUSH_CTL(x) ((x) << 0)
305#define GS_FLUSH_CTL(x) ((x) << 3)
306#define ACK_FLUSH_CTL(x) ((x) << 6)
307#define SYNC_FLUSH_CTL (1 << 8)
308
40#endif 309#endif
41 310
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 55fefe763965..4b77b79fbbc2 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1050,12 +1050,52 @@ struct evergreen_asic {
1050 struct r100_gpu_lockup lockup; 1050 struct r100_gpu_lockup lockup;
1051}; 1051};
1052 1052
1053struct cayman_asic {
1054 unsigned max_shader_engines;
1055 unsigned max_pipes_per_simd;
1056 unsigned max_tile_pipes;
1057 unsigned max_simds_per_se;
1058 unsigned max_backends_per_se;
1059 unsigned max_texture_channel_caches;
1060 unsigned max_gprs;
1061 unsigned max_threads;
1062 unsigned max_gs_threads;
1063 unsigned max_stack_entries;
1064 unsigned sx_num_of_sets;
1065 unsigned sx_max_export_size;
1066 unsigned sx_max_export_pos_size;
1067 unsigned sx_max_export_smx_size;
1068 unsigned max_hw_contexts;
1069 unsigned sq_num_cf_insts;
1070 unsigned sc_prim_fifo_size;
1071 unsigned sc_hiz_tile_fifo_size;
1072 unsigned sc_earlyz_tile_fifo_size;
1073
1074 unsigned num_shader_engines;
1075 unsigned num_shader_pipes_per_simd;
1076 unsigned num_tile_pipes;
1077 unsigned num_simds_per_se;
1078 unsigned num_backends_per_se;
1079 unsigned backend_disable_mask_per_asic;
1080 unsigned backend_map;
1081 unsigned num_texture_channel_caches;
1082 unsigned mem_max_burst_length_bytes;
1083 unsigned mem_row_size_in_kb;
1084 unsigned shader_engine_tile_size;
1085 unsigned num_gpus;
1086 unsigned multi_gpu_tile_size;
1087
1088 unsigned tile_config;
1089 struct r100_gpu_lockup lockup;
1090};
1091
1053union radeon_asic_config { 1092union radeon_asic_config {
1054 struct r300_asic r300; 1093 struct r300_asic r300;
1055 struct r100_asic r100; 1094 struct r100_asic r100;
1056 struct r600_asic r600; 1095 struct r600_asic r600;
1057 struct rv770_asic rv770; 1096 struct rv770_asic rv770;
1058 struct evergreen_asic evergreen; 1097 struct evergreen_asic evergreen;
1098 struct cayman_asic cayman;
1059}; 1099};
1060 1100
1061/* 1101/*
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
index 68a7b22c1fe9..bf7d4c061451 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -169,7 +169,9 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
169 value = rdev->accel_working; 169 value = rdev->accel_working;
170 break; 170 break;
171 case RADEON_INFO_TILING_CONFIG: 171 case RADEON_INFO_TILING_CONFIG:
172 if (rdev->family >= CHIP_CEDAR) 172 if (rdev->family >= CHIP_CAYMAN)
173 value = rdev->config.cayman.tile_config;
174 else if (rdev->family >= CHIP_CEDAR)
173 value = rdev->config.evergreen.tile_config; 175 value = rdev->config.evergreen.tile_config;
174 else if (rdev->family >= CHIP_RV770) 176 else if (rdev->family >= CHIP_RV770)
175 value = rdev->config.rv770.tile_config; 177 value = rdev->config.rv770.tile_config;
@@ -206,7 +208,10 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
206 value = rdev->clock.spll.reference_freq * 10; 208 value = rdev->clock.spll.reference_freq * 10;
207 break; 209 break;
208 case RADEON_INFO_NUM_BACKENDS: 210 case RADEON_INFO_NUM_BACKENDS:
209 if (rdev->family >= CHIP_CEDAR) 211 if (rdev->family >= CHIP_CAYMAN)
212 value = rdev->config.cayman.max_backends_per_se *
213 rdev->config.cayman.max_shader_engines;
214 else if (rdev->family >= CHIP_CEDAR)
210 value = rdev->config.evergreen.max_backends; 215 value = rdev->config.evergreen.max_backends;
211 else if (rdev->family >= CHIP_RV770) 216 else if (rdev->family >= CHIP_RV770)
212 value = rdev->config.rv770.max_backends; 217 value = rdev->config.rv770.max_backends;
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-13 10:50:47 -0500