24 files changed, 1909 insertions, 2 deletions

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 95ba3c5ca14d..c1d600383281 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -159,6 +159,7 @@ machine-$(CONFIG_ARCH_U300)		:= u300
 machine-$(CONFIG_ARCH_VERSATILE)        := versatile
 machine-$(CONFIG_ARCH_W90X900)          := w90x900
 machine-$(CONFIG_FOOTBRIDGE)            := footbridge
+machine-$(CONFIG_ARCH_MXC91231)         := mxc91231
 
 # Platform directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
diff --git a/arch/arm/mach-mxc91231/Kconfig b/arch/arm/mach-mxc91231/Kconfig
new file mode 100644
index 000000000000..8e5fa38ebb67
--- /dev/null
+++ b/arch/arm/mach-mxc91231/Kconfig
@@ -0,0 +1,11 @@
+if ARCH_MXC91231
+
+comment "MXC91231 platforms:"
+
+config MACH_MAGX_ZN5
+        bool "Support Motorola Zn5 GSM phone"
+        default n
+        help
+          Include support for Motorola Zn5 GSM phone.
+
+endif
diff --git a/arch/arm/mach-mxc91231/Makefile b/arch/arm/mach-mxc91231/Makefile
new file mode 100644
index 000000000000..eb70b669c556
--- /dev/null
+++ b/arch/arm/mach-mxc91231/Makefile
@@ -0,0 +1,2 @@
+obj-y   := mm.o clock.o devices.o system.o
+obj-$(CONFIG_MACH_MAGX_ZN5) += magx-zn5.o
diff --git a/arch/arm/mach-mxc91231/Makefile.boot b/arch/arm/mach-mxc91231/Makefile.boot
new file mode 100644
index 000000000000..9939a19d99a1
--- /dev/null
+++ b/arch/arm/mach-mxc91231/Makefile.boot
@@ -0,0 +1,3 @@
+   zreladdr-y   := 0x90008000
+params_phys-y   := 0x90000100
+initrd_phys-y   := 0x90800000
diff --git a/arch/arm/mach-mxc91231/clock.c b/arch/arm/mach-mxc91231/clock.c
new file mode 100644
index 000000000000..ecfa37fef8ad
--- /dev/null
+++ b/arch/arm/mach-mxc91231/clock.c
@@ -0,0 +1,642 @@
+#include <linux/clk.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+
+#include <mach/clock.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+
+#include <asm/clkdev.h>
+#include <asm/bug.h>
+#include <asm/div64.h>
+
+#include "crm_regs.h"
+
+#define CRM_SMALL_DIVIDER(base, name) \
+        crm_small_divider(base, \
+                          base ## _ ## name ## _OFFSET, \
+                          base ## _ ## name ## _MASK)
+#define CRM_1DIVIDER(base, name) \
+        crm_divider(base, \
+                    base ## _ ## name ## _OFFSET, \
+                    base ## _ ## name ## _MASK, 1)
+#define CRM_16DIVIDER(base, name) \
+        crm_divider(base, \
+                    base ## _ ## name ## _OFFSET, \
+                    base ## _ ## name ## _MASK, 16)
+
+static u32 crm_small_divider(void __iomem *reg, u8 offset, u32 mask)
+{
+        static const u32 crm_small_dividers[] = {
+                2, 3, 4, 5, 6, 8, 10, 12
+        };
+        u8 idx;
+
+        idx = (__raw_readl(reg) & mask) >> offset;
+        if (idx > 7)
+                return 1;
+
+        return crm_small_dividers[idx];
+}
+
+static u32 crm_divider(void __iomem *reg, u8 offset, u32 mask, u32 z)
+{
+        u32 div;
+        div = (__raw_readl(reg) & mask) >> offset;
+        return div ? div : z;
+}
+
+static int _clk_1bit_enable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(clk->enable_reg);
+        reg |= 1 << clk->enable_shift;
+        __raw_writel(reg, clk->enable_reg);
+
+        return 0;
+}
+
+static void _clk_1bit_disable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(clk->enable_reg);
+        reg &= ~(1 << clk->enable_shift);
+        __raw_writel(reg, clk->enable_reg);
+}
+
+static int _clk_3bit_enable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(clk->enable_reg);
+        reg |= 0x7 << clk->enable_shift;
+        __raw_writel(reg, clk->enable_reg);
+
+        return 0;
+}
+
+static void _clk_3bit_disable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(clk->enable_reg);
+        reg &= ~(0x7 << clk->enable_shift);
+        __raw_writel(reg, clk->enable_reg);
+}
+
+static unsigned long ckih_rate;
+
+static unsigned long clk_ckih_get_rate(struct clk *clk)
+{
+        return ckih_rate;
+}
+
+static struct clk ckih_clk = {
+        .get_rate = clk_ckih_get_rate,
+};
+
+static unsigned long clk_ckih_x2_get_rate(struct clk *clk)
+{
+        return 2 * clk_get_rate(clk->parent);
+}
+
+static struct clk ckih_x2_clk = {
+        .parent = &ckih_clk,
+        .get_rate = clk_ckih_x2_get_rate,
+};
+
+static unsigned long clk_ckil_get_rate(struct clk *clk)
+{
+        return CKIL_CLK_FREQ;
+}
+
+static struct clk ckil_clk = {
+        .get_rate = clk_ckil_get_rate,
+};
+
+/* plls stuff */
+static struct clk mcu_pll_clk;
+static struct clk dsp_pll_clk;
+static struct clk usb_pll_clk;
+
+static struct clk *pll_clk(u8 sel)
+{
+        switch (sel) {
+        case 0:
+                return &mcu_pll_clk;
+        case 1:
+                return &dsp_pll_clk;
+        case 2:
+                return &usb_pll_clk;
+        }
+        BUG();
+}
+
+static void __iomem *pll_base(struct clk *clk)
+{
+        if (clk == &mcu_pll_clk)
+                return MXC_PLL0_BASE;
+        else if (clk == &dsp_pll_clk)
+                return MXC_PLL1_BASE;
+        else if (clk == &usb_pll_clk)
+                return MXC_PLL2_BASE;
+        BUG();
+}
+
+static unsigned long clk_pll_get_rate(struct clk *clk)
+{
+        const void __iomem *pllbase;
+        unsigned long dp_op, dp_mfd, dp_mfn, pll_hfsm, ref_clk, mfi;
+        long mfn, mfn_abs, mfd, pdf;
+        s64 temp;
+        pllbase = pll_base(clk);
+
+        pll_hfsm = __raw_readl(pllbase + MXC_PLL_DP_CTL) & MXC_PLL_DP_CTL_HFSM;
+        if (pll_hfsm == 0) {
+                dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
+                dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
+                dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
+        } else {
+                dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP);
+                dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD);
+                dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN);
+        }
+
+        pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
+        mfi = (dp_op >> MXC_PLL_DP_OP_MFI_OFFSET) & MXC_PLL_DP_OP_PDF_MASK;
+        mfi = (mfi <= 5) ? 5 : mfi;
+        mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;
+        mfn = dp_mfn & MXC_PLL_DP_MFN_MASK;
+        mfn = (mfn <= 0x4000000) ? mfn : (mfn - 0x10000000);
+
+        if (mfn < 0)
+                mfn_abs = -mfn;
+        else
+                mfn_abs = mfn;
+
+/* XXX: actually this asumes that ckih is fed to pll, but spec says
+ * that ckih_x2 is also possible. need to check this out.
+ */
+        ref_clk = clk_get_rate(&ckih_clk);
+
+        ref_clk *= 2;
+        ref_clk /= pdf + 1;
+
+        temp = (u64) ref_clk * mfn_abs;
+        do_div(temp, mfd);
+        if (mfn < 0)
+                temp = -temp;
+        temp += ref_clk * mfi;
+
+        return temp;
+}
+
+static int clk_pll_enable(struct clk *clk)
+{
+        void __iomem *ctl;
+        u32 reg;
+
+        ctl = pll_base(clk);
+        reg = __raw_readl(ctl);
+        reg |= (MXC_PLL_DP_CTL_RST | MXC_PLL_DP_CTL_UPEN);
+        __raw_writel(reg, ctl);
+        do {
+                reg = __raw_readl(ctl);
+        } while ((reg & MXC_PLL_DP_CTL_LRF) != MXC_PLL_DP_CTL_LRF);
+        return 0;
+}
+
+static void clk_pll_disable(struct clk *clk)
+{
+        void __iomem *ctl;
+        u32 reg;
+
+        ctl = pll_base(clk);
+        reg = __raw_readl(ctl);
+        reg &= ~(MXC_PLL_DP_CTL_RST | MXC_PLL_DP_CTL_UPEN);
+        __raw_writel(reg, ctl);
+}
+
+static struct clk mcu_pll_clk = {
+        .parent = &ckih_clk,
+        .get_rate = clk_pll_get_rate,
+        .enable = clk_pll_enable,
+        .disable = clk_pll_disable,
+};
+
+static struct clk dsp_pll_clk = {
+        .parent = &ckih_clk,
+        .get_rate = clk_pll_get_rate,
+        .enable = clk_pll_enable,
+        .disable = clk_pll_disable,
+};
+
+static struct clk usb_pll_clk = {
+        .parent = &ckih_clk,
+        .get_rate = clk_pll_get_rate,
+        .enable = clk_pll_enable,
+        .disable = clk_pll_disable,
+};
+/* plls stuff end */
+
+/* ap_ref_clk stuff */
+static struct clk ap_ref_clk;
+
+static unsigned long clk_ap_ref_get_rate(struct clk *clk)
+{
+        u32 ascsr, acsr;
+        u8 ap_pat_ref_div_2, ap_isel, acs, ads;
+
+        ascsr = __raw_readl(MXC_CRMAP_ASCSR);
+        acsr = __raw_readl(MXC_CRMAP_ACSR);
+
+        /* 0 for ckih, 1 for ckih*2 */
+        ap_isel = ascsr & MXC_CRMAP_ASCSR_APISEL;
+        /* reg divider */
+        ap_pat_ref_div_2 = (ascsr >> MXC_CRMAP_ASCSR_AP_PATDIV2_OFFSET) & 0x1;
+        /* undocumented, 1 for disabling divider */
+        ads = (acsr >> MXC_CRMAP_ACSR_ADS_OFFSET) & 0x1;
+        /* 0 for pat_ref, 1 for divider out */
+        acs = acsr & MXC_CRMAP_ACSR_ACS;
+
+        if (acs & !ads)
+                /* use divided clock */
+                return clk_get_rate(clk->parent) / (ap_pat_ref_div_2 ? 2 : 1);
+
+        return clk_get_rate(clk->parent) * (ap_isel ? 2 : 1);
+}
+
+static struct clk ap_ref_clk = {
+        .parent = &ckih_clk,
+        .get_rate = clk_ap_ref_get_rate,
+};
+/* ap_ref_clk stuff end */
+
+/* ap_pre_dfs_clk stuff */
+static struct clk ap_pre_dfs_clk;
+
+static unsigned long clk_ap_pre_dfs_get_rate(struct clk *clk)
+{
+        u32 acsr, ascsr;
+
+        acsr = __raw_readl(MXC_CRMAP_ACSR);
+        ascsr = __raw_readl(MXC_CRMAP_ASCSR);
+
+        if (acsr & MXC_CRMAP_ACSR_ACS) {
+                u8 sel;
+                sel = (ascsr & MXC_CRMAP_ASCSR_APSEL_MASK) >>
+                        MXC_CRMAP_ASCSR_APSEL_OFFSET;
+                return clk_get_rate(pll_clk(sel)) /
+                        CRM_SMALL_DIVIDER(MXC_CRMAP_ACDR, ARMDIV);
+        }
+        return clk_get_rate(&ap_ref_clk);
+}
+
+static struct clk ap_pre_dfs_clk = {
+        .get_rate = clk_ap_pre_dfs_get_rate,
+};
+/* ap_pre_dfs_clk stuff end */
+
+/* usb_clk stuff */
+static struct clk usb_clk;
+
+static struct clk *clk_usb_parent(struct clk *clk)
+{
+        u32 acsr, ascsr;
+
+        acsr = __raw_readl(MXC_CRMAP_ACSR);
+        ascsr = __raw_readl(MXC_CRMAP_ASCSR);
+
+        if (acsr & MXC_CRMAP_ACSR_ACS) {
+                u8 sel;
+                sel = (ascsr & MXC_CRMAP_ASCSR_USBSEL_MASK) >>
+                        MXC_CRMAP_ASCSR_USBSEL_OFFSET;
+                return pll_clk(sel);
+        }
+        return &ap_ref_clk;
+}
+
+static unsigned long clk_usb_get_rate(struct clk *clk)
+{
+        return clk_get_rate(clk->parent) /
+                CRM_SMALL_DIVIDER(MXC_CRMAP_ACDER2, USBDIV);
+}
+
+static struct clk usb_clk = {
+        .enable_reg = MXC_CRMAP_ACDER2,
+        .enable_shift = MXC_CRMAP_ACDER2_USBEN_OFFSET,
+        .get_rate = clk_usb_get_rate,
+        .enable = _clk_1bit_enable,
+        .disable = _clk_1bit_disable,
+};
+/* usb_clk stuff end */
+
+static unsigned long clk_ipg_get_rate(struct clk *clk)
+{
+        return clk_get_rate(clk->parent) / CRM_16DIVIDER(MXC_CRMAP_ACDR, IPDIV);
+}
+
+static unsigned long clk_ahb_get_rate(struct clk *clk)
+{
+        return clk_get_rate(clk->parent) /
+                CRM_16DIVIDER(MXC_CRMAP_ACDR, AHBDIV);
+}
+
+static struct clk ipg_clk = {
+        .parent = &ap_pre_dfs_clk,
+        .get_rate = clk_ipg_get_rate,
+};
+
+static struct clk ahb_clk = {
+        .parent = &ap_pre_dfs_clk,
+        .get_rate = clk_ahb_get_rate,
+};
+
+/* perclk_clk stuff */
+static struct clk perclk_clk;
+
+static unsigned long clk_perclk_get_rate(struct clk *clk)
+{
+        u32 acder2;
+
+        acder2 = __raw_readl(MXC_CRMAP_ACDER2);
+        if (acder2 & MXC_CRMAP_ACDER2_BAUD_ISEL_MASK)
+                return 2 * clk_get_rate(clk->parent);
+
+        return clk_get_rate(clk->parent);
+}
+
+static struct clk perclk_clk = {
+        .parent = &ckih_clk,
+        .get_rate = clk_perclk_get_rate,
+};
+/* perclk_clk stuff end */
+
+/* uart_clk stuff */
+static struct clk uart_clk[];
+
+static unsigned long clk_uart_get_rate(struct clk *clk)
+{
+        u32 div;
+
+        switch (clk->id) {
+        case 0:
+        case 1:
+                div = CRM_SMALL_DIVIDER(MXC_CRMAP_ACDER2, BAUDDIV);
+                break;
+        case 2:
+                div = CRM_SMALL_DIVIDER(MXC_CRMAP_APRA, UART3DIV);
+                break;
+        default:
+                BUG();
+        }
+        return clk_get_rate(clk->parent) / div;
+}
+
+static struct clk uart_clk[] = {
+        {
+                .id = 0,
+                .parent = &perclk_clk,
+                .enable_reg = MXC_CRMAP_APRA,
+                .enable_shift = MXC_CRMAP_APRA_UART1EN_OFFSET,
+                .get_rate = clk_uart_get_rate,
+                .enable = _clk_1bit_enable,
+                .disable = _clk_1bit_disable,
+        }, {
+                .id = 1,
+                .parent = &perclk_clk,
+                .enable_reg = MXC_CRMAP_APRA,
+                .enable_shift = MXC_CRMAP_APRA_UART2EN_OFFSET,
+                .get_rate = clk_uart_get_rate,
+                .enable = _clk_1bit_enable,
+                .disable = _clk_1bit_disable,
+        }, {
+                .id = 2,
+                .parent = &perclk_clk,
+                .enable_reg = MXC_CRMAP_APRA,
+                .enable_shift = MXC_CRMAP_APRA_UART3EN_OFFSET,
+                .get_rate = clk_uart_get_rate,
+                .enable = _clk_1bit_enable,
+                .disable = _clk_1bit_disable,
+        },
+};
+/* uart_clk stuff end */
+
+/* sdhc_clk stuff */
+static struct clk nfc_clk;
+
+static unsigned long clk_nfc_get_rate(struct clk *clk)
+{
+        return clk_get_rate(clk->parent) /
+                CRM_1DIVIDER(MXC_CRMAP_ACDER2, NFCDIV);
+}
+
+static struct clk nfc_clk = {
+        .parent = &ahb_clk,
+        .enable_reg = MXC_CRMAP_ACDER2,
+        .enable_shift = MXC_CRMAP_ACDER2_NFCEN_OFFSET,
+        .get_rate = clk_nfc_get_rate,
+        .enable = _clk_1bit_enable,
+        .disable = _clk_1bit_disable,
+};
+/* sdhc_clk stuff end */
+
+/* sdhc_clk stuff */
+static struct clk sdhc_clk[];
+
+static struct clk *clk_sdhc_parent(struct clk *clk)
+{
+        u32 aprb;
+        u8 sel;
+        u32 mask;
+        int offset;
+
+        aprb = __raw_readl(MXC_CRMAP_APRB);
+
+        switch (clk->id) {
+        case 0:
+                mask = MXC_CRMAP_APRB_SDHC1_ISEL_MASK;
+                offset = MXC_CRMAP_APRB_SDHC1_ISEL_OFFSET;
+                break;
+        case 1:
+                mask = MXC_CRMAP_APRB_SDHC2_ISEL_MASK;
+                offset = MXC_CRMAP_APRB_SDHC2_ISEL_OFFSET;
+                break;
+        default:
+                BUG();
+        }
+        sel = (aprb & mask) >> offset;
+
+        switch (sel) {
+        case 0:
+                return &ckih_clk;
+        case 1:
+                return &ckih_x2_clk;
+        }
+        return &usb_clk;
+}
+
+static unsigned long clk_sdhc_get_rate(struct clk *clk)
+{
+        u32 div;
+
+        switch (clk->id) {
+        case 0:
+                div = CRM_SMALL_DIVIDER(MXC_CRMAP_APRB, SDHC1_DIV);
+                break;
+        case 1:
+                div = CRM_SMALL_DIVIDER(MXC_CRMAP_APRB, SDHC2_DIV);
+                break;
+        default:
+                BUG();
+        }
+
+        return clk_get_rate(clk->parent) / div;
+}
+
+static int clk_sdhc_enable(struct clk *clk)
+{
+        u32 amlpmre1, aprb;
+
+        amlpmre1 = __raw_readl(MXC_CRMAP_AMLPMRE1);
+        aprb = __raw_readl(MXC_CRMAP_APRB);
+        switch (clk->id) {
+        case 0:
+                amlpmre1 |= (0x7 << MXC_CRMAP_AMLPMRE1_MLPME4_OFFSET);
+                aprb |= (0x1 << MXC_CRMAP_APRB_SDHC1EN_OFFSET);
+                break;
+        case 1:
+                amlpmre1 |= (0x7 << MXC_CRMAP_AMLPMRE1_MLPME5_OFFSET);
+                aprb |= (0x1 << MXC_CRMAP_APRB_SDHC2EN_OFFSET);
+                break;
+        }
+        __raw_writel(amlpmre1, MXC_CRMAP_AMLPMRE1);
+        __raw_writel(aprb, MXC_CRMAP_APRB);
+        return 0;
+}
+
+static void clk_sdhc_disable(struct clk *clk)
+{
+        u32 amlpmre1, aprb;
+
+        amlpmre1 = __raw_readl(MXC_CRMAP_AMLPMRE1);
+        aprb = __raw_readl(MXC_CRMAP_APRB);
+        switch (clk->id) {
+        case 0:
+                amlpmre1 &= ~(0x7 << MXC_CRMAP_AMLPMRE1_MLPME4_OFFSET);
+                aprb &= ~(0x1 << MXC_CRMAP_APRB_SDHC1EN_OFFSET);
+                break;
+        case 1:
+                amlpmre1 &= ~(0x7 << MXC_CRMAP_AMLPMRE1_MLPME5_OFFSET);
+                aprb &= ~(0x1 << MXC_CRMAP_APRB_SDHC2EN_OFFSET);
+                break;
+        }
+        __raw_writel(amlpmre1, MXC_CRMAP_AMLPMRE1);
+        __raw_writel(aprb, MXC_CRMAP_APRB);
+}
+
+static struct clk sdhc_clk[] = {
+        {
+                .id = 0,
+                .get_rate = clk_sdhc_get_rate,
+                .enable = clk_sdhc_enable,
+                .disable = clk_sdhc_disable,
+        }, {
+                .id = 1,
+                .get_rate = clk_sdhc_get_rate,
+                .enable = clk_sdhc_enable,
+                .disable = clk_sdhc_disable,
+        },
+};
+/* sdhc_clk stuff end */
+
+/* wdog_clk stuff */
+static struct clk wdog_clk[] = {
+        {
+                .id = 0,
+                .parent = &ipg_clk,
+                .enable_reg = MXC_CRMAP_AMLPMRD,
+                .enable_shift = MXC_CRMAP_AMLPMRD_MLPMD7_OFFSET,
+                .enable = _clk_3bit_enable,
+                .disable = _clk_3bit_disable,
+        }, {
+                .id = 1,
+                .parent = &ipg_clk,
+                .enable_reg = MXC_CRMAP_AMLPMRD,
+                .enable_shift = MXC_CRMAP_AMLPMRD_MLPMD3_OFFSET,
+                .enable = _clk_3bit_enable,
+                .disable = _clk_3bit_disable,
+        },
+};
+/* wdog_clk stuff end */
+
+/* gpt_clk stuff */
+static struct clk gpt_clk = {
+        .parent = &ipg_clk,
+        .enable_reg = MXC_CRMAP_AMLPMRC,
+        .enable_shift = MXC_CRMAP_AMLPMRC_MLPMC4_OFFSET,
+        .enable = _clk_3bit_enable,
+        .disable = _clk_3bit_disable,
+};
+/* gpt_clk stuff end */
+
+/* cspi_clk stuff */
+static struct clk cspi_clk[] = {
+        {
+                .id = 0,
+                .parent = &ipg_clk,
+                .enable_reg = MXC_CRMAP_AMLPMRE2,
+                .enable_shift = MXC_CRMAP_AMLPMRE2_MLPME0_OFFSET,
+                .enable = _clk_3bit_enable,
+                .disable = _clk_3bit_disable,
+        }, {
+                .id = 1,
+                .parent = &ipg_clk,
+                .enable_reg = MXC_CRMAP_AMLPMRE1,
+                .enable_shift = MXC_CRMAP_AMLPMRE1_MLPME6_OFFSET,
+                .enable = _clk_3bit_enable,
+                .disable = _clk_3bit_disable,
+        },
+};
+/* cspi_clk stuff end */
+
+#define _REGISTER_CLOCK(d, n, c) \
+        { \
+                .dev_id = d, \
+                .con_id = n, \
+                .clk = &c, \
+        },
+
+static struct clk_lookup lookups[] = {
+        _REGISTER_CLOCK("imx-uart.0", NULL, uart_clk[0])
+        _REGISTER_CLOCK("imx-uart.1", NULL, uart_clk[1])
+        _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk[2])
+        _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc_clk[0])
+        _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc_clk[1])
+        _REGISTER_CLOCK("mxc-wdt.0", NULL, wdog_clk[0])
+        _REGISTER_CLOCK("spi_imx.0", NULL, cspi_clk[0])
+        _REGISTER_CLOCK("spi_imx.1", NULL, cspi_clk[1])
+};
+
+int __init mxc91231_clocks_init(unsigned long fref)
+{
+        void __iomem *gpt_base;
+        int i;
+
+        ckih_rate = fref;
+
+        usb_clk.parent = clk_usb_parent(&usb_clk);
+        sdhc_clk[0].parent = clk_sdhc_parent(&sdhc_clk[0]);
+        sdhc_clk[1].parent = clk_sdhc_parent(&sdhc_clk[1]);
+
+        for (i = 0; i < ARRAY_SIZE(lookups); i++)
+                clkdev_add(&lookups[i]);
+
+        gpt_base = MXC91231_IO_ADDRESS(MXC91231_GPT1_BASE_ADDR);
+        mxc_timer_init(&gpt_clk, gpt_base, MXC91231_INT_GPT);
+
+        return 0;
+}
diff --git a/arch/arm/mach-mxc91231/crm_regs.h b/arch/arm/mach-mxc91231/crm_regs.h
new file mode 100644
index 000000000000..ce4f59058189
--- /dev/null
+++ b/arch/arm/mach-mxc91231/crm_regs.h
@@ -0,0 +1,399 @@
+/*
+ * Copyright 2006 Freescale Semiconductor, Inc.
+ * Copyright 2006-2007 Motorola, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_
+#define _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_
+
+#define CKIL_CLK_FREQ                   32768
+
+#define MXC_CRM_AP_BASE                 MXC91231_IO_ADDRESS(MXC91231_CRM_AP_BASE_ADDR)
+#define MXC_CRM_COM_BASE                MXC91231_IO_ADDRESS(MXC91231_CRM_COM_BASE_ADDR)
+#define MXC_DSM_BASE                    MXC91231_IO_ADDRESS(MXC91231_DSM_BASE_ADDR)
+#define MXC_PLL0_BASE                   MXC91231_IO_ADDRESS(MXC91231_PLL0_BASE_ADDR)
+#define MXC_PLL1_BASE                   MXC91231_IO_ADDRESS(MXC91231_PLL1_BASE_ADDR)
+#define MXC_PLL2_BASE                   MXC91231_IO_ADDRESS(MXC91231_PLL2_BASE_ADDR)
+#define MXC_CLKCTL_BASE                 MXC91231_IO_ADDRESS(MXC91231_CLKCTL_BASE_ADDR)
+
+/* PLL Register Offsets */
+#define MXC_PLL_DP_CTL                  0x00
+#define MXC_PLL_DP_CONFIG               0x04
+#define MXC_PLL_DP_OP                   0x08
+#define MXC_PLL_DP_MFD                  0x0C
+#define MXC_PLL_DP_MFN                  0x10
+#define MXC_PLL_DP_HFS_OP               0x1C
+#define MXC_PLL_DP_HFS_MFD              0x20
+#define MXC_PLL_DP_HFS_MFN              0x24
+
+/* PLL Register Bit definitions */
+#define MXC_PLL_DP_CTL_DPDCK0_2_EN      0x1000
+#define MXC_PLL_DP_CTL_ADE              0x800
+#define MXC_PLL_DP_CTL_REF_CLK_DIV      0x400
+#define MXC_PLL_DP_CTL_HFSM             0x80
+#define MXC_PLL_DP_CTL_PRE              0x40
+#define MXC_PLL_DP_CTL_UPEN             0x20
+#define MXC_PLL_DP_CTL_RST              0x10
+#define MXC_PLL_DP_CTL_RCP              0x8
+#define MXC_PLL_DP_CTL_PLM              0x4
+#define MXC_PLL_DP_CTL_BRM0             0x2
+#define MXC_PLL_DP_CTL_LRF              0x1
+
+#define MXC_PLL_DP_OP_MFI_OFFSET        4
+#define MXC_PLL_DP_OP_MFI_MASK          0xF
+#define MXC_PLL_DP_OP_PDF_OFFSET        0
+#define MXC_PLL_DP_OP_PDF_MASK          0xF
+
+#define MXC_PLL_DP_MFD_OFFSET           0
+#define MXC_PLL_DP_MFD_MASK             0x7FFFFFF
+
+#define MXC_PLL_DP_MFN_OFFSET           0
+#define MXC_PLL_DP_MFN_MASK             0x7FFFFFF
+
+/* CRM AP Register Offsets */
+#define MXC_CRMAP_ASCSR                 (MXC_CRM_AP_BASE + 0x00)
+#define MXC_CRMAP_ACDR                  (MXC_CRM_AP_BASE + 0x04)
+#define MXC_CRMAP_ACDER1                (MXC_CRM_AP_BASE + 0x08)
+#define MXC_CRMAP_ACDER2                (MXC_CRM_AP_BASE + 0x0C)
+#define MXC_CRMAP_ACGCR                 (MXC_CRM_AP_BASE + 0x10)
+#define MXC_CRMAP_ACCGCR                (MXC_CRM_AP_BASE + 0x14)
+#define MXC_CRMAP_AMLPMRA               (MXC_CRM_AP_BASE + 0x18)
+#define MXC_CRMAP_AMLPMRB               (MXC_CRM_AP_BASE + 0x1C)
+#define MXC_CRMAP_AMLPMRC               (MXC_CRM_AP_BASE + 0x20)
+#define MXC_CRMAP_AMLPMRD               (MXC_CRM_AP_BASE + 0x24)
+#define MXC_CRMAP_AMLPMRE1              (MXC_CRM_AP_BASE + 0x28)
+#define MXC_CRMAP_AMLPMRE2              (MXC_CRM_AP_BASE + 0x2C)
+#define MXC_CRMAP_AMLPMRF               (MXC_CRM_AP_BASE + 0x30)
+#define MXC_CRMAP_AMLPMRG               (MXC_CRM_AP_BASE + 0x34)
+#define MXC_CRMAP_APGCR                 (MXC_CRM_AP_BASE + 0x38)
+#define MXC_CRMAP_ACSR                  (MXC_CRM_AP_BASE + 0x3C)
+#define MXC_CRMAP_ADCR                  (MXC_CRM_AP_BASE + 0x40)
+#define MXC_CRMAP_ACR                   (MXC_CRM_AP_BASE + 0x44)
+#define MXC_CRMAP_AMCR                  (MXC_CRM_AP_BASE + 0x48)
+#define MXC_CRMAP_APCR                  (MXC_CRM_AP_BASE + 0x4C)
+#define MXC_CRMAP_AMORA                 (MXC_CRM_AP_BASE + 0x50)
+#define MXC_CRMAP_AMORB                 (MXC_CRM_AP_BASE + 0x54)
+#define MXC_CRMAP_AGPR                  (MXC_CRM_AP_BASE + 0x58)
+#define MXC_CRMAP_APRA                  (MXC_CRM_AP_BASE + 0x5C)
+#define MXC_CRMAP_APRB                  (MXC_CRM_AP_BASE + 0x60)
+#define MXC_CRMAP_APOR                  (MXC_CRM_AP_BASE + 0x64)
+#define MXC_CRMAP_ADFMR                 (MXC_CRM_AP_BASE + 0x68)
+
+/* CRM AP Register Bit definitions */
+#define MXC_CRMAP_ASCSR_CRS                     0x10000
+#define MXC_CRMAP_ASCSR_AP_PATDIV2_OFFSET       15
+#define MXC_CRMAP_ASCSR_AP_PATREF_DIV2          0x8000
+#define MXC_CRMAP_ASCSR_USBSEL_OFFSET           13
+#define MXC_CRMAP_ASCSR_USBSEL_MASK             (0x3 << 13)
+#define MXC_CRMAP_ASCSR_CSISEL_OFFSET           11
+#define MXC_CRMAP_ASCSR_CSISEL_MASK             (0x3 << 11)
+#define MXC_CRMAP_ASCSR_SSI2SEL_OFFSET          7
+#define MXC_CRMAP_ASCSR_SSI2SEL_MASK            (0x3 << 7)
+#define MXC_CRMAP_ASCSR_SSI1SEL_OFFSET          5
+#define MXC_CRMAP_ASCSR_SSI1SEL_MASK            (0x3 << 5)
+#define MXC_CRMAP_ASCSR_APSEL_OFFSET            3
+#define MXC_CRMAP_ASCSR_APSEL_MASK              (0x3 << 3)
+#define MXC_CRMAP_ASCSR_AP_PATDIV1_OFFSET       2
+#define MXC_CRMAP_ASCSR_AP_PATREF_DIV1          0x4
+#define MXC_CRMAP_ASCSR_APISEL                  0x1
+
+#define MXC_CRMAP_ACDR_ARMDIV_OFFSET            8
+#define MXC_CRMAP_ACDR_ARMDIV_MASK              (0xF << 8)
+#define MXC_CRMAP_ACDR_AHBDIV_OFFSET            4
+#define MXC_CRMAP_ACDR_AHBDIV_MASK              (0xF << 4)
+#define MXC_CRMAP_ACDR_IPDIV_OFFSET             0
+#define MXC_CRMAP_ACDR_IPDIV_MASK               0xF
+
+#define MXC_CRMAP_ACDER1_CSIEN_OFFSET           30
+#define MXC_CRMAP_ACDER1_CSIDIV_OFFSET          24
+#define MXC_CRMAP_ACDER1_CSIDIV_MASK            (0x3F << 24)
+#define MXC_CRMAP_ACDER1_SSI2EN_OFFSET          14
+#define MXC_CRMAP_ACDER1_SSI2DIV_OFFSET         8
+#define MXC_CRMAP_ACDER1_SSI2DIV_MASK           (0x3F << 8)
+#define MXC_CRMAP_ACDER1_SSI1EN_OFFSET          6
+#define MXC_CRMAP_ACDER1_SSI1DIV_OFFSET         0
+#define MXC_CRMAP_ACDER1_SSI1DIV_MASK           0x3F
+
+#define MXC_CRMAP_ACDER2_CRCT_CLK_DIV_OFFSET    24
+#define MXC_CRMAP_ACDER2_CRCT_CLK_DIV_MASK      (0x7 << 24)
+#define MXC_CRMAP_ACDER2_NFCEN_OFFSET           20
+#define MXC_CRMAP_ACDER2_NFCDIV_OFFSET          16
+#define MXC_CRMAP_ACDER2_NFCDIV_MASK            (0xF << 16)
+#define MXC_CRMAP_ACDER2_USBEN_OFFSET           12
+#define MXC_CRMAP_ACDER2_USBDIV_OFFSET          8
+#define MXC_CRMAP_ACDER2_USBDIV_MASK            (0xF << 8)
+#define MXC_CRMAP_ACDER2_BAUD_ISEL_OFFSET       5
+#define MXC_CRMAP_ACDER2_BAUD_ISEL_MASK         (0x3 << 5)
+#define MXC_CRMAP_ACDER2_BAUDDIV_OFFSET         0
+#define MXC_CRMAP_ACDER2_BAUDDIV_MASK           0xF
+
+#define MXC_CRMAP_AMLPMRA_MLPMA7_OFFSET         22
+#define MXC_CRMAP_AMLPMRA_MLPMA7_MASK           (0x7 << 22)
+#define MXC_CRMAP_AMLPMRA_MLPMA6_OFFSET         19
+#define MXC_CRMAP_AMLPMRA_MLPMA6_MASK           (0x7 << 19)
+#define MXC_CRMAP_AMLPMRA_MLPMA4_OFFSET         12
+#define MXC_CRMAP_AMLPMRA_MLPMA4_MASK           (0x7 << 12)
+#define MXC_CRMAP_AMLPMRA_MLPMA3_OFFSET         9
+#define MXC_CRMAP_AMLPMRA_MLPMA3_MASK           (0x7 << 9)
+#define MXC_CRMAP_AMLPMRA_MLPMA2_OFFSET         6
+#define MXC_CRMAP_AMLPMRA_MLPMA2_MASK           (0x7 << 6)
+#define MXC_CRMAP_AMLPMRA_MLPMA1_OFFSET         3
+#define MXC_CRMAP_AMLPMRA_MLPMA1_MASK           (0x7 << 3)
+
+#define MXC_CRMAP_AMLPMRB_MLPMB0_OFFSET         0
+#define MXC_CRMAP_AMLPMRB_MLPMB0_MASK           0x7
+
+#define MXC_CRMAP_AMLPMRC_MLPMC9_OFFSET         28
+#define MXC_CRMAP_AMLPMRC_MLPMC9_MASK           (0x7 << 28)
+#define MXC_CRMAP_AMLPMRC_MLPMC7_OFFSET         22
+#define MXC_CRMAP_AMLPMRC_MLPMC7_MASK           (0x7 << 22)
+#define MXC_CRMAP_AMLPMRC_MLPMC5_OFFSET         16
+#define MXC_CRMAP_AMLPMRC_MLPMC5_MASK           (0x7 << 16)
+#define MXC_CRMAP_AMLPMRC_MLPMC4_OFFSET         12
+#define MXC_CRMAP_AMLPMRC_MLPMC4_MASK           (0x7 << 12)
+#define MXC_CRMAP_AMLPMRC_MLPMC3_OFFSET         9
+#define MXC_CRMAP_AMLPMRC_MLPMC3_MASK           (0x7 << 9)
+#define MXC_CRMAP_AMLPMRC_MLPMC2_OFFSET         6
+#define MXC_CRMAP_AMLPMRC_MLPMC2_MASK           (0x7 << 6)
+#define MXC_CRMAP_AMLPMRC_MLPMC1_OFFSET         3
+#define MXC_CRMAP_AMLPMRC_MLPMC1_MASK           (0x7 << 3)
+#define MXC_CRMAP_AMLPMRC_MLPMC0_OFFSET         0
+#define MXC_CRMAP_AMLPMRC_MLPMC0_MASK           0x7
+
+#define MXC_CRMAP_AMLPMRD_MLPMD7_OFFSET         22
+#define MXC_CRMAP_AMLPMRD_MLPMD7_MASK           (0x7 << 22)
+#define MXC_CRMAP_AMLPMRD_MLPMD4_OFFSET         12
+#define MXC_CRMAP_AMLPMRD_MLPMD4_MASK           (0x7 << 12)
+#define MXC_CRMAP_AMLPMRD_MLPMD3_OFFSET         9
+#define MXC_CRMAP_AMLPMRD_MLPMD3_MASK           (0x7 << 9)
+#define MXC_CRMAP_AMLPMRD_MLPMD2_OFFSET         6
+#define MXC_CRMAP_AMLPMRD_MLPMD2_MASK           (0x7 << 6)
+#define MXC_CRMAP_AMLPMRD_MLPMD0_OFFSET         0
+#define MXC_CRMAP_AMLPMRD_MLPMD0_MASK           0x7
+
+#define MXC_CRMAP_AMLPMRE1_MLPME9_OFFSET        28
+#define MXC_CRMAP_AMLPMRE1_MLPME9_MASK          (0x7 << 28)
+#define MXC_CRMAP_AMLPMRE1_MLPME8_OFFSET        25
+#define MXC_CRMAP_AMLPMRE1_MLPME8_MASK          (0x7 << 25)
+#define MXC_CRMAP_AMLPMRE1_MLPME7_OFFSET        22
+#define MXC_CRMAP_AMLPMRE1_MLPME7_MASK          (0x7 << 22)
+#define MXC_CRMAP_AMLPMRE1_MLPME6_OFFSET        19
+#define MXC_CRMAP_AMLPMRE1_MLPME6_MASK          (0x7 << 19)
+#define MXC_CRMAP_AMLPMRE1_MLPME5_OFFSET        16
+#define MXC_CRMAP_AMLPMRE1_MLPME5_MASK          (0x7 << 16)
+#define MXC_CRMAP_AMLPMRE1_MLPME4_OFFSET        12
+#define MXC_CRMAP_AMLPMRE1_MLPME4_MASK          (0x7 << 12)
+#define MXC_CRMAP_AMLPMRE1_MLPME3_OFFSET        9
+#define MXC_CRMAP_AMLPMRE1_MLPME3_MASK          (0x7 << 9)
+#define MXC_CRMAP_AMLPMRE1_MLPME2_OFFSET        6
+#define MXC_CRMAP_AMLPMRE1_MLPME2_MASK          (0x7 << 6)
+#define MXC_CRMAP_AMLPMRE1_MLPME1_OFFSET        3
+#define MXC_CRMAP_AMLPMRE1_MLPME1_MASK          (0x7 << 3)
+#define MXC_CRMAP_AMLPMRE1_MLPME0_OFFSET        0
+#define MXC_CRMAP_AMLPMRE1_MLPME0_MASK          0x7
+
+#define MXC_CRMAP_AMLPMRE2_MLPME0_OFFSET        0
+#define MXC_CRMAP_AMLPMRE2_MLPME0_MASK          0x7
+
+#define MXC_CRMAP_AMLPMRF_MLPMF6_OFFSET         19
+#define MXC_CRMAP_AMLPMRF_MLPMF6_MASK           (0x7 << 19)
+#define MXC_CRMAP_AMLPMRF_MLPMF5_OFFSET         16
+#define MXC_CRMAP_AMLPMRF_MLPMF5_MASK           (0x7 << 16)
+#define MXC_CRMAP_AMLPMRF_MLPMF3_OFFSET         9
+#define MXC_CRMAP_AMLPMRF_MLPMF3_MASK           (0x7 << 9)
+#define MXC_CRMAP_AMLPMRF_MLPMF2_OFFSET         6
+#define MXC_CRMAP_AMLPMRF_MLPMF2_MASK           (0x7 << 6)
+#define MXC_CRMAP_AMLPMRF_MLPMF1_OFFSET         3
+#define MXC_CRMAP_AMLPMRF_MLPMF1_MASK           (0x7 << 3)
+#define MXC_CRMAP_AMLPMRF_MLPMF0_OFFSET         0
+#define MXC_CRMAP_AMLPMRF_MLPMF0_MASK           (0x7 << 0)
+
+#define MXC_CRMAP_AMLPMRG_MLPMG9_OFFSET         28
+#define MXC_CRMAP_AMLPMRG_MLPMG9_MASK           (0x7 << 28)
+#define MXC_CRMAP_AMLPMRG_MLPMG7_OFFSET         22
+#define MXC_CRMAP_AMLPMRG_MLPMG7_MASK           (0x7 << 22)
+#define MXC_CRMAP_AMLPMRG_MLPMG6_OFFSET         19
+#define MXC_CRMAP_AMLPMRG_MLPMG6_MASK           (0x7 << 19)
+#define MXC_CRMAP_AMLPMRG_MLPMG5_OFFSET         16
+#define MXC_CRMAP_AMLPMRG_MLPMG5_MASK           (0x7 << 16)
+#define MXC_CRMAP_AMLPMRG_MLPMG4_OFFSET         12
+#define MXC_CRMAP_AMLPMRG_MLPMG4_MASK           (0x7 << 12)
+#define MXC_CRMAP_AMLPMRG_MLPMG3_OFFSET         9
+#define MXC_CRMAP_AMLPMRG_MLPMG3_MASK           (0x7 << 9)
+#define MXC_CRMAP_AMLPMRG_MLPMG2_OFFSET         6
+#define MXC_CRMAP_AMLPMRG_MLPMG2_MASK           (0x7 << 6)
+#define MXC_CRMAP_AMLPMRG_MLPMG1_OFFSET         3
+#define MXC_CRMAP_AMLPMRG_MLPMG1_MASK           (0x7 << 3)
+#define MXC_CRMAP_AMLPMRG_MLPMG0_OFFSET         0
+#define MXC_CRMAP_AMLPMRG_MLPMG0_MASK           0x7
+
+#define MXC_CRMAP_AGPR_IPUPAD_OFFSET            20
+#define MXC_CRMAP_AGPR_IPUPAD_MASK              (0x7 << 20)
+
+#define MXC_CRMAP_APRA_EL1TEN_OFFSET            29
+#define MXC_CRMAP_APRA_SIMEN_OFFSET             24
+#define MXC_CRMAP_APRA_UART3DIV_OFFSET          17
+#define MXC_CRMAP_APRA_UART3DIV_MASK            (0xF << 17)
+#define MXC_CRMAP_APRA_UART3EN_OFFSET           16
+#define MXC_CRMAP_APRA_SAHARA_DIV2_CLKEN_OFFSET 14
+#define MXC_CRMAP_APRA_MQSPIEN_OFFSET           13
+#define MXC_CRMAP_APRA_UART2EN_OFFSET           8
+#define MXC_CRMAP_APRA_UART1EN_OFFSET           0
+
+#define MXC_CRMAP_APRB_SDHC2_ISEL_OFFSET        13
+#define MXC_CRMAP_APRB_SDHC2_ISEL_MASK          (0x7 << 13)
+#define MXC_CRMAP_APRB_SDHC2_DIV_OFFSET         9
+#define MXC_CRMAP_APRB_SDHC2_DIV_MASK           (0xF << 9)
+#define MXC_CRMAP_APRB_SDHC2EN_OFFSET           8
+#define MXC_CRMAP_APRB_SDHC1_ISEL_OFFSET        5
+#define MXC_CRMAP_APRB_SDHC1_ISEL_MASK          (0x7 << 5)
+#define MXC_CRMAP_APRB_SDHC1_DIV_OFFSET         1
+#define MXC_CRMAP_APRB_SDHC1_DIV_MASK           (0xF << 1)
+#define MXC_CRMAP_APRB_SDHC1EN_OFFSET           0
+
+#define MXC_CRMAP_ACSR_ADS_OFFSET               8
+#define MXC_CRMAP_ACSR_ADS                      (0x1 << 8)
+#define MXC_CRMAP_ACSR_ACS                      0x1
+
+#define MXC_CRMAP_ADCR_LFDF_0                   (0x0 << 8)
+#define MXC_CRMAP_ADCR_LFDF_2                   (0x1 << 8)
+#define MXC_CRMAP_ADCR_LFDF_4                   (0x2 << 8)
+#define MXC_CRMAP_ADCR_LFDF_8                   (0x3 << 8)
+#define MXC_CRMAP_ADCR_LFDF_OFFSET              8
+#define MXC_CRMAP_ADCR_LFDF_MASK                (0x3 << 8)
+#define MXC_CRMAP_ADCR_ALT_PLL                  0x80
+#define MXC_CRMAP_ADCR_DFS_DIVEN                0x20
+#define MXC_CRMAP_ADCR_DIV_BYP                  0x2
+#define MXC_CRMAP_ADCR_VSTAT                    0x8
+#define MXC_CRMAP_ADCR_TSTAT                    0x10
+#define MXC_CRMAP_ADCR_DVFS_VCTRL               0x10
+#define MXC_CRMAP_ADCR_CLK_ON                   0x40
+
+#define MXC_CRMAP_ADFMR_FC_OFFSET               16
+#define MXC_CRMAP_ADFMR_FC_MASK                 (0x1F << 16)
+#define MXC_CRMAP_ADFMR_MF_OFFSET               1
+#define MXC_CRMAP_ADFMR_MF_MASK                 (0x3FF << 1)
+#define MXC_CRMAP_ADFMR_DFM_CLK_READY           0x1
+#define MXC_CRMAP_ADFMR_DFM_PWR_DOWN            0x8000
+
+#define MXC_CRMAP_ACR_CKOHS_HIGH                (1 << 18)
+#define MXC_CRMAP_ACR_CKOS_HIGH                 (1 << 16)
+#define MXC_CRMAP_ACR_CKOHS_MASK                (0x7 << 12)
+#define MXC_CRMAP_ACR_CKOHD                     (1 << 11)
+#define MXC_CRMAP_ACR_CKOHDIV_MASK              (0xF << 8)
+#define MXC_CRMAP_ACR_CKOHDIV_OFFSET            8
+#define MXC_CRMAP_ACR_CKOD                      (1 << 7)
+#define MXC_CRMAP_ACR_CKOS_MASK                 (0x7 << 4)
+
+/* AP Warm reset */
+#define MXC_CRMAP_AMCR_SW_AP                    (1 << 14)
+
+/* Bit definitions of ACGCR in CRM_AP for tree level clock gating */
+#define MXC_CRMAP_ACGCR_ACG0_STOP_WAIT          0x00000001
+#define MXC_CRMAP_ACGCR_ACG0_STOP               0x00000003
+#define MXC_CRMAP_ACGCR_ACG0_RUN                0x00000007
+#define MXC_CRMAP_ACGCR_ACG0_DISABLED           0x00000000
+
+#define MXC_CRMAP_ACGCR_ACG1_STOP_WAIT          0x00000008
+#define MXC_CRMAP_ACGCR_ACG1_STOP               0x00000018
+#define MXC_CRMAP_ACGCR_ACG1_RUN                0x00000038
+#define MXC_CRMAP_ACGCR_ACG1_DISABLED           0x00000000
+
+#define MXC_CRMAP_ACGCR_ACG2_STOP_WAIT          0x00000040
+#define MXC_CRMAP_ACGCR_ACG2_STOP               0x000000C0
+#define MXC_CRMAP_ACGCR_ACG2_RUN                0x000001C0
+#define MXC_CRMAP_ACGCR_ACG2_DISABLED           0x00000000
+
+#define MXC_CRMAP_ACGCR_ACG3_STOP_WAIT          0x00000200
+#define MXC_CRMAP_ACGCR_ACG3_STOP               0x00000600
+#define MXC_CRMAP_ACGCR_ACG3_RUN                0x00000E00
+#define MXC_CRMAP_ACGCR_ACG3_DISABLED           0x00000000
+
+#define MXC_CRMAP_ACGCR_ACG4_STOP_WAIT          0x00001000
+#define MXC_CRMAP_ACGCR_ACG4_STOP               0x00003000
+#define MXC_CRMAP_ACGCR_ACG4_RUN                0x00007000
+#define MXC_CRMAP_ACGCR_ACG4_DISABLED           0x00000000
+
+#define MXC_CRMAP_ACGCR_ACG5_STOP_WAIT          0x00010000
+#define MXC_CRMAP_ACGCR_ACG5_STOP               0x00030000
+#define MXC_CRMAP_ACGCR_ACG5_RUN                0x00070000
+#define MXC_CRMAP_ACGCR_ACG5_DISABLED           0x00000000
+
+#define MXC_CRMAP_ACGCR_ACG6_STOP_WAIT          0x00080000
+#define MXC_CRMAP_ACGCR_ACG6_STOP               0x00180000
+#define MXC_CRMAP_ACGCR_ACG6_RUN                0x00380000
+#define MXC_CRMAP_ACGCR_ACG6_DISABLED           0x00000000
+
+#define NUM_GATE_CTRL                           6
+
+/* CRM COM Register Offsets */
+#define MXC_CRMCOM_CSCR                         (MXC_CRM_COM_BASE + 0x0C)
+#define MXC_CRMCOM_CCCR                         (MXC_CRM_COM_BASE + 0x10)
+
+/* CRM COM Bit Definitions */
+#define MXC_CRMCOM_CSCR_PPD1                    0x08000000
+#define MXC_CRMCOM_CSCR_CKOHSEL                 (1 << 18)
+#define MXC_CRMCOM_CSCR_CKOSEL                  (1 << 17)
+#define MXC_CRMCOM_CCCR_CC_DIV_OFFSET           8
+#define MXC_CRMCOM_CCCR_CC_DIV_MASK             (0x1F << 8)
+#define MXC_CRMCOM_CCCR_CC_SEL_OFFSET           0
+#define MXC_CRMCOM_CCCR_CC_SEL_MASK             0x3
+
+/* DSM Register Offsets */
+#define MXC_DSM_SLEEP_TIME                      (MXC_DSM_BASE + 0x0c)
+#define MXC_DSM_CONTROL0                        (MXC_DSM_BASE + 0x20)
+#define MXC_DSM_CONTROL1                        (MXC_DSM_BASE + 0x24)
+#define MXC_DSM_CTREN                           (MXC_DSM_BASE + 0x28)
+#define MXC_DSM_WARM_PER                        (MXC_DSM_BASE + 0x40)
+#define MXC_DSM_LOCK_PER                        (MXC_DSM_BASE + 0x44)
+#define MXC_DSM_MGPER                           (MXC_DSM_BASE + 0x4c)
+#define MXC_DSM_CRM_CONTROL                     (MXC_DSM_BASE + 0x50)
+
+/* Bit definitions of various registers in DSM */
+#define MXC_DSM_CRM_CTRL_DVFS_BYP               0x00000008
+#define MXC_DSM_CRM_CTRL_DVFS_VCTRL             0x00000004
+#define MXC_DSM_CRM_CTRL_LPMD1                  0x00000002
+#define MXC_DSM_CRM_CTRL_LPMD0                  0x00000001
+#define MXC_DSM_CRM_CTRL_LPMD_STOP_MODE         0x00000000
+#define MXC_DSM_CRM_CTRL_LPMD_WAIT_MODE         0x00000001
+#define MXC_DSM_CRM_CTRL_LPMD_RUN_MODE          0x00000003
+#define MXC_DSM_CONTROL0_STBY_COMMIT_EN         0x00000200
+#define MXC_DSM_CONTROL0_MSTR_EN                0x00000001
+#define MXC_DSM_CONTROL0_RESTART                0x00000010
+/* Counter Block reset */
+#define MXC_DSM_CONTROL1_CB_RST                 0x00000002
+/* State Machine reset */
+#define MXC_DSM_CONTROL1_SM_RST                 0x00000004
+/* Bit needed to reset counter block */
+#define MXC_CONTROL1_RST_CNT32                  0x00000008
+#define MXC_DSM_CONTROL1_RST_CNT32_EN           0x00000800
+#define MXC_DSM_CONTROL1_SLEEP                  0x00000100
+#define MXC_DSM_CONTROL1_WAKEUP_DISABLE         0x00004000
+#define MXC_DSM_CTREN_CNT32                     0x00000001
+
+/* Magic Fix enable bit */
+#define MXC_DSM_MGPER_EN_MGFX                   0x80000000
+#define MXC_DSM_MGPER_PER_MASK                  0x000003FF
+#define MXC_DSM_MGPER_PER(n)                    (MXC_DSM_MGPER_PER_MASK & n)
+
+/* Address offsets of the CLKCTL registers */
+#define MXC_CLKCTL_GP_CTRL      (MXC_CLKCTL_BASE + 0x00)
+#define MXC_CLKCTL_GP_SER       (MXC_CLKCTL_BASE + 0x04)
+#define MXC_CLKCTL_GP_CER       (MXC_CLKCTL_BASE + 0x08)
+
+#endif /* _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_ */
diff --git a/arch/arm/mach-mxc91231/devices.c b/arch/arm/mach-mxc91231/devices.c
new file mode 100644
index 000000000000..353bd977b393
--- /dev/null
+++ b/arch/arm/mach-mxc91231/devices.c
@@ -0,0 +1,251 @@
+/*
+ * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/serial.h>
+#include <linux/gpio.h>
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+#include <mach/imx-uart.h>
+
+static struct resource uart0[] = {
+        {
+                .start = MXC91231_UART1_BASE_ADDR,
+                .end = MXC91231_UART1_BASE_ADDR + 0x0B5,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC91231_INT_UART1_RX,
+                .end = MXC91231_INT_UART1_RX,
+                .flags = IORESOURCE_IRQ,
+        }, {
+                .start = MXC91231_INT_UART1_TX,
+                .end = MXC91231_INT_UART1_TX,
+                .flags = IORESOURCE_IRQ,
+        }, {
+                .start = MXC91231_INT_UART1_MINT,
+                .end = MXC91231_INT_UART1_MINT,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_uart_device0 = {
+        .name = "imx-uart",
+        .id = 0,
+        .resource = uart0,
+        .num_resources = ARRAY_SIZE(uart0),
+};
+
+static struct resource uart1[] = {
+        {
+                .start = MXC91231_UART2_BASE_ADDR,
+                .end = MXC91231_UART2_BASE_ADDR + 0x0B5,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC91231_INT_UART2_RX,
+                .end = MXC91231_INT_UART2_RX,
+                .flags = IORESOURCE_IRQ,
+        }, {
+                .start = MXC91231_INT_UART2_TX,
+                .end = MXC91231_INT_UART2_TX,
+                .flags = IORESOURCE_IRQ,
+        }, {
+                .start = MXC91231_INT_UART2_MINT,
+                .end = MXC91231_INT_UART2_MINT,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_uart_device1 = {
+        .name = "imx-uart",
+        .id = 1,
+        .resource = uart1,
+        .num_resources = ARRAY_SIZE(uart1),
+};
+
+static struct resource uart2[] = {
+        {
+                .start = MXC91231_UART3_BASE_ADDR,
+                .end = MXC91231_UART3_BASE_ADDR + 0x0B5,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC91231_INT_UART3_RX,
+                .end = MXC91231_INT_UART3_RX,
+                .flags = IORESOURCE_IRQ,
+        }, {
+                .start = MXC91231_INT_UART3_TX,
+                .end = MXC91231_INT_UART3_TX,
+                .flags = IORESOURCE_IRQ,
+        }, {
+                .start = MXC91231_INT_UART3_MINT,
+                .end = MXC91231_INT_UART3_MINT,
+                .flags = IORESOURCE_IRQ,
+
+        },
+};
+
+struct platform_device mxc_uart_device2 = {
+        .name = "imx-uart",
+        .id = 2,
+        .resource = uart2,
+        .num_resources = ARRAY_SIZE(uart2),
+};
+
+/* GPIO port description */
+static struct mxc_gpio_port mxc_gpio_ports[] = {
+        [0] = {
+                .chip.label = "gpio-0",
+                .base = MXC91231_IO_ADDRESS(MXC91231_GPIO1_AP_BASE_ADDR),
+                .irq = MXC91231_INT_GPIO1,
+                .virtual_irq_start = MXC_GPIO_IRQ_START,
+        },
+        [1] = {
+                .chip.label = "gpio-1",
+                .base = MXC91231_IO_ADDRESS(MXC91231_GPIO2_AP_BASE_ADDR),
+                .irq = MXC91231_INT_GPIO2,
+                .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
+        },
+        [2] = {
+                .chip.label = "gpio-2",
+                .base = MXC91231_IO_ADDRESS(MXC91231_GPIO3_AP_BASE_ADDR),
+                .irq = MXC91231_INT_GPIO3,
+                .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
+        },
+        [3] = {
+                .chip.label = "gpio-3",
+                .base = MXC91231_IO_ADDRESS(MXC91231_GPIO4_SH_BASE_ADDR),
+                .irq = MXC91231_INT_GPIO4,
+                .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
+        },
+};
+
+int __init mxc_register_gpios(void)
+{
+        return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports));
+}
+
+static struct resource mxc_nand_resources[] = {
+        {
+                .start  = MXC91231_NFC_BASE_ADDR,
+                .end    = MXC91231_NFC_BASE_ADDR + 0xfff,
+                .flags  = IORESOURCE_MEM
+        }, {
+                .start  = MXC91231_INT_NANDFC,
+                .end    = MXC91231_INT_NANDFC,
+                .flags  = IORESOURCE_IRQ
+        },
+};
+
+struct platform_device mxc_nand_device = {
+        .name = "mxc_nand",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(mxc_nand_resources),
+        .resource = mxc_nand_resources,
+};
+
+static struct resource mxc_sdhc0_resources[] = {
+        {
+                .start = MXC91231_MMC_SDHC1_BASE_ADDR,
+                .end = MXC91231_MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC91231_INT_MMC_SDHC1,
+                .end = MXC91231_INT_MMC_SDHC1,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource mxc_sdhc1_resources[] = {
+        {
+                .start = MXC91231_MMC_SDHC2_BASE_ADDR,
+                .end = MXC91231_MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC91231_INT_MMC_SDHC2,
+                .end = MXC91231_INT_MMC_SDHC2,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_sdhc_device0 = {
+        .name = "mxc-mmc",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(mxc_sdhc0_resources),
+        .resource = mxc_sdhc0_resources,
+};
+
+struct platform_device mxc_sdhc_device1 = {
+        .name = "mxc-mmc",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(mxc_sdhc1_resources),
+        .resource = mxc_sdhc1_resources,
+};
+
+static struct resource mxc_cspi0_resources[] = {
+        {
+                .start = MXC91231_CSPI1_BASE_ADDR,
+                .end = MXC91231_CSPI1_BASE_ADDR + 0x20,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC91231_INT_CSPI1,
+                .end = MXC91231_INT_CSPI1,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_cspi_device0 = {
+        .name = "spi_imx",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(mxc_cspi0_resources),
+        .resource = mxc_cspi0_resources,
+};
+
+static struct resource mxc_cspi1_resources[] = {
+        {
+                .start = MXC91231_CSPI2_BASE_ADDR,
+                .end = MXC91231_CSPI2_BASE_ADDR + 0x20,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC91231_INT_CSPI2,
+                .end = MXC91231_INT_CSPI2,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_cspi_device1 = {
+        .name = "spi_imx",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(mxc_cspi1_resources),
+        .resource = mxc_cspi1_resources,
+};
+
+static struct resource mxc_wdog0_resources[] = {
+        {
+                .start = MXC91231_WDOG1_BASE_ADDR,
+                .end = MXC91231_WDOG1_BASE_ADDR + 0x10,
+                .flags = IORESOURCE_MEM,
+        },
+};
+
+struct platform_device mxc_wdog_device0 = {
+        .name = "mxc-wdt",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(mxc_wdog0_resources),
+        .resource = mxc_wdog0_resources,
+};
diff --git a/arch/arm/mach-mxc91231/devices.h b/arch/arm/mach-mxc91231/devices.h
new file mode 100644
index 000000000000..72a2136ce27d
--- /dev/null
+++ b/arch/arm/mach-mxc91231/devices.h
@@ -0,0 +1,13 @@
+extern struct platform_device mxc_uart_device0;
+extern struct platform_device mxc_uart_device1;
+extern struct platform_device mxc_uart_device2;
+
+extern struct platform_device mxc_nand_device;
+
+extern struct platform_device mxc_sdhc_device0;
+extern struct platform_device mxc_sdhc_device1;
+
+extern struct platform_device mxc_cspi_device0;
+extern struct platform_device mxc_cspi_device1;
+
+extern struct platform_device mxc_wdog_device0;
diff --git a/arch/arm/mach-mxc91231/magx-zn5.c b/arch/arm/mach-mxc91231/magx-zn5.c
new file mode 100644
index 000000000000..8757573b0a8a
--- /dev/null
+++ b/arch/arm/mach-mxc91231/magx-zn5.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2009 Dmitriy Taychenachev <dimichxp@gmail.com>
+ *
+ * This file is released under the GPLv2 or later.
+ */
+
+#include <linux/irq.h>
+#include <linux/init.h>
+#include <linux/device.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/time.h>
+#include <asm/mach/arch.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/mmc.h>
+#include <mach/imx-uart.h>
+
+#include "devices.h"
+
+static struct imxuart_platform_data uart_pdata = {
+};
+
+static struct imxmmc_platform_data sdhc_pdata = {
+};
+
+static void __init zn5_init(void)
+{
+        pm_power_off = mxc91231_power_off;
+
+        mxc_register_device(&mxc_uart_device1, &uart_pdata);
+        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+
+        mxc_register_device(&mxc_sdhc_device0, &sdhc_pdata);
+
+        mxc_register_device(&mxc_wdog_device0, NULL);
+
+        return;
+}
+
+static void __init zn5_timer_init(void)
+{
+        mxc91231_clocks_init(26000000); /* 26mhz ckih */
+}
+
+struct sys_timer zn5_timer = {
+        .init = zn5_timer_init,
+};
+
+MACHINE_START(MAGX_ZN5, "Motorola Zn5")
+        .phys_io        = MXC91231_AIPS1_BASE_ADDR,
+        .io_pg_offst    = ((MXC91231_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+        .boot_params    = PHYS_OFFSET + 0x100,
+        .map_io         = mxc91231_map_io,
+        .init_irq       = mxc91231_init_irq,
+        .timer          = &zn5_timer,
+        .init_machine   = zn5_init,
+MACHINE_END
diff --git a/arch/arm/mach-mxc91231/mm.c b/arch/arm/mach-mxc91231/mm.c
new file mode 100644
index 000000000000..6becda3ff331
--- /dev/null
+++ b/arch/arm/mach-mxc91231/mm.c
@@ -0,0 +1,94 @@
+/*
+ *  Copyright (C) 1999,2000 Arm Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ *  Copyright 2004-2005 Freescale Semiconductor, Inc. All Rights Reserved.
+ *    - add MXC specific definitions
+ *  Copyright 2006 Motorola, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <asm/pgtable.h>
+#include <asm/mach/map.h>
+
+/*
+ * This structure defines the MXC memory map.
+ */
+static struct map_desc mxc_io_desc[] __initdata = {
+        {
+                .virtual        = MXC91231_L2CC_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(MXC91231_L2CC_BASE_ADDR),
+                .length         = MXC91231_L2CC_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = MXC91231_X_MEMC_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(MXC91231_X_MEMC_BASE_ADDR),
+                .length         = MXC91231_X_MEMC_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = MXC91231_ROMP_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(MXC91231_ROMP_BASE_ADDR),
+                .length         = MXC91231_ROMP_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = MXC91231_AVIC_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(MXC91231_AVIC_BASE_ADDR),
+                .length         = MXC91231_AVIC_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = MXC91231_AIPS1_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(MXC91231_AIPS1_BASE_ADDR),
+                .length         = MXC91231_AIPS1_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = MXC91231_SPBA0_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(MXC91231_SPBA0_BASE_ADDR),
+                .length         = MXC91231_SPBA0_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = MXC91231_SPBA1_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(MXC91231_SPBA1_BASE_ADDR),
+                .length         = MXC91231_SPBA1_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = MXC91231_AIPS2_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(MXC91231_AIPS2_BASE_ADDR),
+                .length         = MXC91231_AIPS2_SIZE,
+                .type           = MT_DEVICE,
+        },
+};
+
+/*
+ * This function initializes the memory map. It is called during the
+ * system startup to create static physical to virtual memory map for
+ * the IO modules.
+ */
+void __init mxc91231_map_io(void)
+{
+        mxc_set_cpu_type(MXC_CPU_MXC91231);
+
+        iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
+}
+
+void __init mxc91231_init_irq(void)
+{
+        mxc_init_irq(MXC91231_IO_ADDRESS(MXC91231_AVIC_BASE_ADDR));
+}
diff --git a/arch/arm/mach-mxc91231/system.c b/arch/arm/mach-mxc91231/system.c
new file mode 100644
index 000000000000..736f7efd874a
--- /dev/null
+++ b/arch/arm/mach-mxc91231/system.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2009 Dmitriy Taychenachev <dimichxp@gmail.com>
+ *
+ * This file is released under the GPLv2 or later.
+ */
+
+#include <linux/delay.h>
+#include <linux/io.h>
+
+#include <asm/proc-fns.h>
+#include <mach/hardware.h>
+
+#include "crm_regs.h"
+
+#define WDOG_WCR                MXC91231_IO_ADDRESS(MXC91231_WDOG1_BASE_ADDR)
+#define WDOG_WCR_OUT_ENABLE     (1 << 6)
+#define WDOG_WCR_ASSERT         (1 << 5)
+
+void mxc91231_power_off(void)
+{
+        u16 wcr;
+
+        wcr = __raw_readw(WDOG_WCR);
+        wcr |= WDOG_WCR_OUT_ENABLE;
+        wcr &= ~WDOG_WCR_ASSERT;
+        __raw_writew(wcr, WDOG_WCR);
+}
+
+void mxc91231_arch_reset(char mode, const char *cmd)
+{
+        u32 amcr;
+
+        /* Reset the AP using CRM */
+        amcr = __raw_readl(MXC_CRMAP_AMCR);
+        amcr &= ~MXC_CRMAP_AMCR_SW_AP;
+        __raw_writel(amcr, MXC_CRMAP_AMCR);
+
+        mdelay(10);
+        cpu_reset(0);
+}
+
+void mxc91231_prepare_idle(void)
+{
+        u32 crm_ctl;
+
+        /* Go to WAIT mode after WFI */
+        crm_ctl = __raw_readl(MXC_DSM_CRM_CONTROL);
+        crm_ctl &= ~(MXC_DSM_CRM_CTRL_LPMD0 | MXC_DSM_CRM_CTRL_LPMD1);
+        crm_ctl |=  MXC_DSM_CRM_CTRL_LPMD_WAIT_MODE;
+        __raw_writel(crm_ctl, MXC_DSM_CRM_CONTROL);
+}
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index e342a2e61601..ca5c7c226341 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -34,12 +34,20 @@ config ARCH_MX3
         help
           This enables support for systems based on the Freescale i.MX3 family
 
+config ARCH_MXC91231
+        bool "MXC91231-based"
+        select CPU_V6
+        select COMMON_CLKDEV
+        help
+          This enables support for systems based on the Freescale MXC91231 family
+
 endchoice
 
 source "arch/arm/mach-mx1/Kconfig"
 source "arch/arm/mach-mx2/Kconfig"
 source "arch/arm/mach-mx3/Kconfig"
 source "arch/arm/mach-mx25/Kconfig"
+source "arch/arm/mach-mxc91231/Kconfig"
 
 endmenu
 
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 4e7af7412396..286cb9b0a25b 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -20,6 +20,7 @@ extern void mx25_map_io(void);
 extern void mx27_map_io(void);
 extern void mx31_map_io(void);
 extern void mx35_map_io(void);
+extern void mxc91231_map_io(void);
 extern void mxc_init_irq(void __iomem *);
 extern void mx1_init_irq(void);
 extern void mx21_init_irq(void);
@@ -27,6 +28,7 @@ extern void mx25_init_irq(void);
 extern void mx27_init_irq(void);
 extern void mx31_init_irq(void);
 extern void mx35_init_irq(void);
+extern void mxc91231_init_irq(void);
 extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int);
 extern int mx1_clocks_init(unsigned long fref);
 extern int mx21_clocks_init(unsigned long lref, unsigned long fref);
@@ -34,9 +36,13 @@ extern int mx25_clocks_init(unsigned long fref);
 extern int mx27_clocks_init(unsigned long fref);
 extern int mx31_clocks_init(unsigned long fref);
 extern int mx35_clocks_init(void);
+extern int mxc91231_clocks_init(unsigned long fref);
 extern int mxc_register_gpios(void);
 extern int mxc_register_device(struct platform_device *pdev, void *data);
 extern void mxc_set_cpu_type(unsigned int type);
 extern void mxc_arch_reset_init(void __iomem *);
+extern void mxc91231_power_off(void);
+extern void mxc91231_arch_reset(int, const char *);
+extern void mxc91231_prepare_idle(void);
 
 #endif
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S
index bf683de56b76..15b2b148a105 100644
--- a/arch/arm/plat-mxc/include/mach/debug-macro.S
+++ b/arch/arm/plat-mxc/include/mach/debug-macro.S
@@ -44,6 +44,14 @@
 #define UART_VADDR      AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
 #endif
 
+#ifdef CONFIG_ARCH_MXC91231
+#ifdef UART_PADDR
+#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
+#endif
+#include <mach/mxc91231.h>
+#define UART_PADDR      MXC91231_UART2_BASE_ADDR
+#define UART_VADDR      MXC91231_AIPS1_IO_ADDRESS(MXC91231_UART2_BASE_ADDR)
+#endif
                 .macro  addruart,rx
                 mrc     p15, 0, \rx, c1, c0
                 tst     \rx, #1                 @ MMU enabled?
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
index 569af3239c3c..78db75475f69 100644
--- a/arch/arm/plat-mxc/include/mach/hardware.h
+++ b/arch/arm/plat-mxc/include/mach/hardware.h
@@ -46,6 +46,10 @@
 # include <mach/mx25.h>
 #endif
 
+#ifdef CONFIG_ARCH_MXC91231
+# include <mach/mxc91231.h>
+#endif
+
 #include <mach/mxc.h>
 
 #endif /* __ASM_ARCH_MXC_HARDWARE_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h
index f39e016c1cc5..ead9d592168d 100644
--- a/arch/arm/plat-mxc/include/mach/irqs.h
+++ b/arch/arm/plat-mxc/include/mach/irqs.h
@@ -26,6 +26,8 @@
 #define MXC_GPIO_IRQS           (32 * 3)
 #elif defined CONFIG_ARCH_MX25
 #define MXC_GPIO_IRQS           (32 * 4)
+#elif defined CONFIG_ARCH_MXC91231
+#define MXC_GPIO_IRQS           (32 * 4)
 #endif
 
 /*
diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h
index 42db73941118..d3afafdcc0e5 100644
--- a/arch/arm/plat-mxc/include/mach/memory.h
+++ b/arch/arm/plat-mxc/include/mach/memory.h
@@ -24,6 +24,8 @@
 #define PHYS_OFFSET             UL(0x80000000)
 #elif defined CONFIG_ARCH_MX25
 #define PHYS_OFFSET             UL(0x80000000)
+#elif defined CONFIG_ARCH_MXC91231
+#define PHYS_OFFSET             UL(0x90000000)
 #endif
 
 #if defined(CONFIG_MX1_VIDEO)
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index 882b816729bd..51990536b845 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -30,6 +30,7 @@
 #define MXC_CPU_MX27            27
 #define MXC_CPU_MX31            31
 #define MXC_CPU_MX35            35
+#define MXC_CPU_MXC91231        91231
 
 #ifndef __ASSEMBLY__
 extern unsigned int __mxc_cpu_type;
@@ -107,13 +108,25 @@ extern unsigned int __mxc_cpu_type;
 # define cpu_is_mx35()          (0)
 #endif
 
+#ifdef CONFIG_ARCH_MXC91231
+# ifdef mxc_cpu_type
+#  undef mxc_cpu_type
+#  define mxc_cpu_type __mxc_cpu_type
+# else
+#  define mxc_cpu_type MXC_CPU_MXC91231
+# endif
+# define cpu_is_mxc91231()      (mxc_cpu_type == MXC_CPU_MXC91231)
+#else
+# define cpu_is_mxc91231()      (0)
+#endif
+
 #if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2)
 #define CSCR_U(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10)
 #define CSCR_L(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x4)
 #define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x8)
 #endif
 
-#define cpu_is_mx3()    (cpu_is_mx31() || cpu_is_mx35())
+#define cpu_is_mx3()    (cpu_is_mx31() || cpu_is_mx35() || cpu_is_mxc91231())
 #define cpu_is_mx2()    (cpu_is_mx21() || cpu_is_mx27())
 
 #endif /*  __ASM_ARCH_MXC_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mxc91231.h b/arch/arm/plat-mxc/include/mach/mxc91231.h
new file mode 100644
index 000000000000..81484d1ef232
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mxc91231.h
@@ -0,0 +1,315 @@
+/*
+ *  Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
+ *    - Platform specific register memory map
+ *
+ *  Copyright 2005-2007 Motorola, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __MACH_MXC91231_H__
+#define __MACH_MXC91231_H__
+
+/*
+ * L2CC
+ */
+#define MXC91231_L2CC_BASE_ADDR         0x30000000
+#define MXC91231_L2CC_BASE_ADDR_VIRT    0xF9000000
+#define MXC91231_L2CC_SIZE              SZ_64K
+
+/*
+ * AIPS 1
+ */
+#define MXC91231_AIPS1_BASE_ADDR        0x43F00000
+#define MXC91231_AIPS1_BASE_ADDR_VIRT   0xFC000000
+#define MXC91231_AIPS1_SIZE             SZ_1M
+
+#define MXC91231_AIPS1_CTRL_BASE_ADDR   MXC91231_AIPS1_BASE_ADDR
+#define MXC91231_MAX_BASE_ADDR          (MXC91231_AIPS1_BASE_ADDR + 0x04000)
+#define MXC91231_EVTMON_BASE_ADDR       (MXC91231_AIPS1_BASE_ADDR + 0x08000)
+#define MXC91231_CLKCTL_BASE_ADDR       (MXC91231_AIPS1_BASE_ADDR + 0x0C000)
+#define MXC91231_ETB_SLOT4_BASE_ADDR    (MXC91231_AIPS1_BASE_ADDR + 0x10000)
+#define MXC91231_ETB_SLOT5_BASE_ADDR    (MXC91231_AIPS1_BASE_ADDR + 0x14000)
+#define MXC91231_ECT_CTIO_BASE_ADDR     (MXC91231_AIPS1_BASE_ADDR + 0x18000)
+#define MXC91231_I2C_BASE_ADDR          (MXC91231_AIPS1_BASE_ADDR + 0x80000)
+#define MXC91231_MU_BASE_ADDR           (MXC91231_AIPS1_BASE_ADDR + 0x88000)
+#define MXC91231_UART1_BASE_ADDR        (MXC91231_AIPS1_BASE_ADDR + 0x90000)
+#define MXC91231_UART2_BASE_ADDR        (MXC91231_AIPS1_BASE_ADDR + 0x94000)
+#define MXC91231_DSM_BASE_ADDR          (MXC91231_AIPS1_BASE_ADDR + 0x98000)
+#define MXC91231_OWIRE_BASE_ADDR        (MXC91231_AIPS1_BASE_ADDR + 0x9C000)
+#define MXC91231_SSI1_BASE_ADDR         (MXC91231_AIPS1_BASE_ADDR + 0xA0000)
+#define MXC91231_KPP_BASE_ADDR          (MXC91231_AIPS1_BASE_ADDR + 0xA8000)
+#define MXC91231_IOMUX_AP_BASE_ADDR     (MXC91231_AIPS1_BASE_ADDR + 0xAC000)
+#define MXC91231_CTI_AP_BASE_ADDR       (MXC91231_AIPS1_BASE_ADDR + 0xB8000)
+
+/*
+ * AIPS 2
+ */
+#define MXC91231_AIPS2_BASE_ADDR        0x53F00000
+#define MXC91231_AIPS2_BASE_ADDR_VIRT   0xFC100000
+#define MXC91231_AIPS2_SIZE             SZ_1M
+
+#define MXC91231_GEMK_BASE_ADDR         (MXC91231_AIPS2_BASE_ADDR + 0x8C000)
+#define MXC91231_GPT1_BASE_ADDR         (MXC91231_AIPS2_BASE_ADDR + 0x90000)
+#define MXC91231_EPIT1_AP_BASE_ADDR     (MXC91231_AIPS2_BASE_ADDR + 0x94000)
+#define MXC91231_SCC_BASE_ADDR          (MXC91231_AIPS2_BASE_ADDR + 0xAC000)
+#define MXC91231_RNGA_BASE_ADDR         (MXC91231_AIPS2_BASE_ADDR + 0xB0000)
+#define MXC91231_IPU_CTRL_BASE_ADDR     (MXC91231_AIPS2_BASE_ADDR + 0xC0000)
+#define MXC91231_AUDMUX_BASE_ADDR       (MXC91231_AIPS2_BASE_ADDR + 0xC4000)
+#define MXC91231_EDIO_BASE_ADDR         (MXC91231_AIPS2_BASE_ADDR + 0xC8000)
+#define MXC91231_GPIO1_AP_BASE_ADDR     (MXC91231_AIPS2_BASE_ADDR + 0xCC000)
+#define MXC91231_GPIO2_AP_BASE_ADDR     (MXC91231_AIPS2_BASE_ADDR + 0xD0000)
+#define MXC91231_SDMA_BASE_ADDR         (MXC91231_AIPS2_BASE_ADDR + 0xD4000)
+#define MXC91231_RTC_BASE_ADDR          (MXC91231_AIPS2_BASE_ADDR + 0xD8000)
+#define MXC91231_WDOG1_BASE_ADDR        (MXC91231_AIPS2_BASE_ADDR + 0xDC000)
+#define MXC91231_PWM_BASE_ADDR          (MXC91231_AIPS2_BASE_ADDR + 0xE0000)
+#define MXC91231_GPIO3_AP_BASE_ADDR     (MXC91231_AIPS2_BASE_ADDR + 0xE4000)
+#define MXC91231_WDOG2_BASE_ADDR        (MXC91231_AIPS2_BASE_ADDR + 0xE8000)
+#define MXC91231_RTIC_BASE_ADDR         (MXC91231_AIPS2_BASE_ADDR + 0xEC000)
+#define MXC91231_LPMC_BASE_ADDR         (MXC91231_AIPS2_BASE_ADDR + 0xF0000)
+
+/*
+ * SPBA global module 0
+ */
+#define MXC91231_SPBA0_BASE_ADDR        0x50000000
+#define MXC91231_SPBA0_BASE_ADDR_VIRT   0xFC200000
+#define MXC91231_SPBA0_SIZE             SZ_1M
+
+#define MXC91231_MMC_SDHC1_BASE_ADDR    (MXC91231_SPBA0_BASE_ADDR + 0x04000)
+#define MXC91231_MMC_SDHC2_BASE_ADDR    (MXC91231_SPBA0_BASE_ADDR + 0x08000)
+#define MXC91231_UART3_BASE_ADDR        (MXC91231_SPBA0_BASE_ADDR + 0x0C000)
+#define MXC91231_CSPI2_BASE_ADDR        (MXC91231_SPBA0_BASE_ADDR + 0x10000)
+#define MXC91231_SSI2_BASE_ADDR         (MXC91231_SPBA0_BASE_ADDR + 0x14000)
+#define MXC91231_SIM_BASE_ADDR          (MXC91231_SPBA0_BASE_ADDR + 0x18000)
+#define MXC91231_IIM_BASE_ADDR          (MXC91231_SPBA0_BASE_ADDR + 0x1C000)
+#define MXC91231_CTI_SDMA_BASE_ADDR     (MXC91231_SPBA0_BASE_ADDR + 0x20000)
+#define MXC91231_USBOTG_CTRL_BASE_ADDR  (MXC91231_SPBA0_BASE_ADDR + 0x24000)
+#define MXC91231_USBOTG_DATA_BASE_ADDR  (MXC91231_SPBA0_BASE_ADDR + 0x28000)
+#define MXC91231_CSPI1_BASE_ADDR        (MXC91231_SPBA0_BASE_ADDR + 0x30000)
+#define MXC91231_SPBA_CTRL_BASE_ADDR    (MXC91231_SPBA0_BASE_ADDR + 0x3C000)
+#define MXC91231_IOMUX_COM_BASE_ADDR    (MXC91231_SPBA0_BASE_ADDR + 0x40000)
+#define MXC91231_CRM_COM_BASE_ADDR      (MXC91231_SPBA0_BASE_ADDR + 0x44000)
+#define MXC91231_CRM_AP_BASE_ADDR       (MXC91231_SPBA0_BASE_ADDR + 0x48000)
+#define MXC91231_PLL0_BASE_ADDR         (MXC91231_SPBA0_BASE_ADDR + 0x4C000)
+#define MXC91231_PLL1_BASE_ADDR         (MXC91231_SPBA0_BASE_ADDR + 0x50000)
+#define MXC91231_PLL2_BASE_ADDR         (MXC91231_SPBA0_BASE_ADDR + 0x54000)
+#define MXC91231_GPIO4_SH_BASE_ADDR     (MXC91231_SPBA0_BASE_ADDR + 0x58000)
+#define MXC91231_HAC_BASE_ADDR          (MXC91231_SPBA0_BASE_ADDR + 0x5C000)
+#define MXC91231_SAHARA_BASE_ADDR       (MXC91231_SPBA0_BASE_ADDR + 0x5C000)
+#define MXC91231_PLL3_BASE_ADDR         (MXC91231_SPBA0_BASE_ADDR + 0x60000)
+
+/*
+ * SPBA global module 1
+ */
+#define MXC91231_SPBA1_BASE_ADDR        0x52000000
+#define MXC91231_SPBA1_BASE_ADDR_VIRT   0xFC300000
+#define MXC91231_SPBA1_SIZE             SZ_1M
+
+#define MXC91231_MQSPI_BASE_ADDR        (MXC91231_SPBA1_BASE_ADDR + 0x34000)
+#define MXC91231_EL1T_BASE_ADDR         (MXC91231_SPBA1_BASE_ADDR + 0x38000)
+
+/*!
+ * Defines for SPBA modules
+ */
+#define MXC91231_SPBA_SDHC1             0x04
+#define MXC91231_SPBA_SDHC2             0x08
+#define MXC91231_SPBA_UART3             0x0C
+#define MXC91231_SPBA_CSPI2             0x10
+#define MXC91231_SPBA_SSI2              0x14
+#define MXC91231_SPBA_SIM               0x18
+#define MXC91231_SPBA_IIM               0x1C
+#define MXC91231_SPBA_CTI_SDMA          0x20
+#define MXC91231_SPBA_USBOTG_CTRL_REGS  0x24
+#define MXC91231_SPBA_USBOTG_DATA_REGS  0x28
+#define MXC91231_SPBA_CSPI1             0x30
+#define MXC91231_SPBA_MQSPI             0x34
+#define MXC91231_SPBA_EL1T              0x38
+#define MXC91231_SPBA_IOMUX             0x40
+#define MXC91231_SPBA_CRM_COM           0x44
+#define MXC91231_SPBA_CRM_AP            0x48
+#define MXC91231_SPBA_PLL0              0x4C
+#define MXC91231_SPBA_PLL1              0x50
+#define MXC91231_SPBA_PLL2              0x54
+#define MXC91231_SPBA_GPIO4             0x58
+#define MXC91231_SPBA_SAHARA            0x5C
+
+/*
+ * ROMP and AVIC
+ */
+#define MXC91231_ROMP_BASE_ADDR         0x60000000
+#define MXC91231_ROMP_BASE_ADDR_VIRT    0xFC400000
+#define MXC91231_ROMP_SIZE              SZ_64K
+
+#define MXC91231_AVIC_BASE_ADDR         0x68000000
+#define MXC91231_AVIC_BASE_ADDR_VIRT    0xFC410000
+#define MXC91231_AVIC_SIZE              SZ_64K
+
+/*
+ * NAND, SDRAM, WEIM, M3IF, EMI controllers
+ */
+#define MXC91231_X_MEMC_BASE_ADDR       0xB8000000
+#define MXC91231_X_MEMC_BASE_ADDR_VIRT  0xFC420000
+#define MXC91231_X_MEMC_SIZE            SZ_64K
+
+#define MXC91231_NFC_BASE_ADDR          (MXC91231_X_MEMC_BASE_ADDR + 0x0000)
+#define MXC91231_ESDCTL_BASE_ADDR       (MXC91231_X_MEMC_BASE_ADDR + 0x1000)
+#define MXC91231_WEIM_BASE_ADDR         (MXC91231_X_MEMC_BASE_ADDR + 0x2000)
+#define MXC91231_M3IF_BASE_ADDR         (MXC91231_X_MEMC_BASE_ADDR + 0x3000)
+#define MXC91231_EMI_CTL_BASE_ADDR      (MXC91231_X_MEMC_BASE_ADDR + 0x4000)
+
+/*
+ * Memory regions and CS
+ * CPLD is connected on CS4
+ * CS5 is TP1021 or it is not connected
+ * */
+#define MXC91231_FB_RAM_BASE_ADDR       0x78000000
+#define MXC91231_FB_RAM_SIZE            SZ_256K
+#define MXC91231_CSD0_BASE_ADDR         0x80000000
+#define MXC91231_CSD1_BASE_ADDR         0x90000000
+#define MXC91231_CS0_BASE_ADDR          0xA0000000
+#define MXC91231_CS1_BASE_ADDR          0xA8000000
+#define MXC91231_CS2_BASE_ADDR          0xB0000000
+#define MXC91231_CS3_BASE_ADDR          0xB2000000
+#define MXC91231_CS4_BASE_ADDR          0xB4000000
+#define MXC91231_CS5_BASE_ADDR          0xB6000000
+
+/* Is given address belongs to the specified memory region? */
+#define ADDRESS_IN_REGION(addr, start, size) \
+        (((addr) >= (start)) && ((addr) < (start)+(size)))
+
+/* Is given address belongs to the specified named `module'? */
+#define MXC91231_IS_MODULE(addr, module) \
+        ADDRESS_IN_REGION(addr, MXC91231_ ## module ## _BASE_ADDR, \
+                                MXC91231_ ## module ## _SIZE)
+/*
+ * This macro defines the physical to virtual address mapping for all the
+ * peripheral modules. It is used by passing in the physical address as x
+ * and returning the virtual address. If the physical address is not mapped,
+ * it returns 0xDEADBEEF
+ */
+
+#define MXC91231_IO_ADDRESS(x) \
+        (void __iomem *) \
+        (MXC91231_IS_MODULE(x, L2CC) ? MXC91231_L2CC_IO_ADDRESS(x) : \
+         MXC91231_IS_MODULE(x, AIPS1) ? MXC91231_AIPS1_IO_ADDRESS(x) : \
+         MXC91231_IS_MODULE(x, AIPS2) ? MXC91231_AIPS2_IO_ADDRESS(x) : \
+         MXC91231_IS_MODULE(x, SPBA0) ? MXC91231_SPBA0_IO_ADDRESS(x) : \
+         MXC91231_IS_MODULE(x, SPBA1) ? MXC91231_SPBA1_IO_ADDRESS(x) : \
+         MXC91231_IS_MODULE(x, ROMP) ? MXC91231_ROMP_IO_ADDRESS(x) : \
+         MXC91231_IS_MODULE(x, AVIC) ? MXC91231_AVIC_IO_ADDRESS(x) : \
+         MXC91231_IS_MODULE(x, X_MEMC) ? MXC91231_X_MEMC_IO_ADDRESS(x) : \
+         0xDEADBEEF)
+
+
+/*
+ * define the address mapping macros: in physical address order
+ */
+#define MXC91231_L2CC_IO_ADDRESS(x)  \
+        (((x) - MXC91231_L2CC_BASE_ADDR) + MXC91231_L2CC_BASE_ADDR_VIRT)
+
+#define MXC91231_AIPS1_IO_ADDRESS(x)  \
+        (((x) - MXC91231_AIPS1_BASE_ADDR) + MXC91231_AIPS1_BASE_ADDR_VIRT)
+
+#define MXC91231_SPBA0_IO_ADDRESS(x)  \
+        (((x) - MXC91231_SPBA0_BASE_ADDR) + MXC91231_SPBA0_BASE_ADDR_VIRT)
+
+#define MXC91231_SPBA1_IO_ADDRESS(x)  \
+        (((x) - MXC91231_SPBA1_BASE_ADDR) + MXC91231_SPBA1_BASE_ADDR_VIRT)
+
+#define MXC91231_AIPS2_IO_ADDRESS(x)  \
+        (((x) - MXC91231_AIPS2_BASE_ADDR) + MXC91231_AIPS2_BASE_ADDR_VIRT)
+
+#define MXC91231_ROMP_IO_ADDRESS(x)  \
+        (((x) - MXC91231_ROMP_BASE_ADDR) + MXC91231_ROMP_BASE_ADDR_VIRT)
+
+#define MXC91231_AVIC_IO_ADDRESS(x)  \
+        (((x) - MXC91231_AVIC_BASE_ADDR) + MXC91231_AVIC_BASE_ADDR_VIRT)
+
+#define MXC91231_X_MEMC_IO_ADDRESS(x)  \
+        (((x) - MXC91231_X_MEMC_BASE_ADDR) + MXC91231_X_MEMC_BASE_ADDR_VIRT)
+
+/*
+ * Interrupt numbers
+ */
+#define MXC91231_INT_GPIO3              0
+#define MXC91231_INT_EL1T_CI            1
+#define MXC91231_INT_EL1T_RFCI          2
+#define MXC91231_INT_EL1T_RFI           3
+#define MXC91231_INT_EL1T_MCU           4
+#define MXC91231_INT_EL1T_IPI           5
+#define MXC91231_INT_MU_GEN             6
+#define MXC91231_INT_GPIO4              7
+#define MXC91231_INT_MMC_SDHC2          8
+#define MXC91231_INT_MMC_SDHC1          9
+#define MXC91231_INT_I2C                10
+#define MXC91231_INT_SSI2               11
+#define MXC91231_INT_SSI1               12
+#define MXC91231_INT_CSPI2              13
+#define MXC91231_INT_CSPI1              14
+#define MXC91231_INT_RTIC               15
+#define MXC91231_INT_SAHARA             15
+#define MXC91231_INT_HAC                15
+#define MXC91231_INT_UART3_RX           16
+#define MXC91231_INT_UART3_TX           17
+#define MXC91231_INT_UART3_MINT         18
+#define MXC91231_INT_ECT                19
+#define MXC91231_INT_SIM_IPB            20
+#define MXC91231_INT_SIM_DATA           21
+#define MXC91231_INT_RNGA               22
+#define MXC91231_INT_DSM_AP             23
+#define MXC91231_INT_KPP                24
+#define MXC91231_INT_RTC                25
+#define MXC91231_INT_PWM                26
+#define MXC91231_INT_GEMK_AP            27
+#define MXC91231_INT_EPIT               28
+#define MXC91231_INT_GPT                29
+#define MXC91231_INT_UART2_RX           30
+#define MXC91231_INT_UART2_TX           31
+#define MXC91231_INT_UART2_MINT         32
+#define MXC91231_INT_NANDFC             33
+#define MXC91231_INT_SDMA               34
+#define MXC91231_INT_USB_WAKEUP         35
+#define MXC91231_INT_USB_SOF            36
+#define MXC91231_INT_PMU_EVTMON         37
+#define MXC91231_INT_USB_FUNC           38
+#define MXC91231_INT_USB_DMA            39
+#define MXC91231_INT_USB_CTRL           40
+#define MXC91231_INT_IPU_ERR            41
+#define MXC91231_INT_IPU_SYN            42
+#define MXC91231_INT_UART1_RX           43
+#define MXC91231_INT_UART1_TX           44
+#define MXC91231_INT_UART1_MINT         45
+#define MXC91231_INT_IIM                46
+#define MXC91231_INT_MU_RX_OR           47
+#define MXC91231_INT_MU_TX_OR           48
+#define MXC91231_INT_SCC_SCM            49
+#define MXC91231_INT_SCC_SMN            50
+#define MXC91231_INT_GPIO2              51
+#define MXC91231_INT_GPIO1              52
+#define MXC91231_INT_MQSPI1             53
+#define MXC91231_INT_MQSPI2             54
+#define MXC91231_INT_WDOG2              55
+#define MXC91231_INT_EXT_INT7           56
+#define MXC91231_INT_EXT_INT6           57
+#define MXC91231_INT_EXT_INT5           58
+#define MXC91231_INT_EXT_INT4           59
+#define MXC91231_INT_EXT_INT3           60
+#define MXC91231_INT_EXT_INT2           61
+#define MXC91231_INT_EXT_INT1           62
+#define MXC91231_INT_EXT_INT0           63
+
+#define MXC91231_MAX_INT_LINES          63
+#define MXC91231_MAX_EXT_LINES          8
+
+#endif /* __MACH_MXC91231_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h
index e56241af870e..ef00199568de 100644
--- a/arch/arm/plat-mxc/include/mach/system.h
+++ b/arch/arm/plat-mxc/include/mach/system.h
@@ -21,8 +21,18 @@
 #ifndef __ASM_ARCH_MXC_SYSTEM_H__
 #define __ASM_ARCH_MXC_SYSTEM_H__
 
+#include <mach/hardware.h>
+#include <mach/common.h>
+
 static inline void arch_idle(void)
 {
+#ifdef CONFIG_ARCH_MXC91231
+        if (cpu_is_mxc91231()) {
+                /* Need this to set DSM low-power mode */
+                mxc91231_prepare_idle();
+        }
+#endif
+
         cpu_do_idle();
 }
 
diff --git a/arch/arm/plat-mxc/include/mach/timex.h b/arch/arm/plat-mxc/include/mach/timex.h
index 0707b7d5b5ce..527a6c24788e 100644
--- a/arch/arm/plat-mxc/include/mach/timex.h
+++ b/arch/arm/plat-mxc/include/mach/timex.h
@@ -28,6 +28,8 @@
 #define CLOCK_TICK_RATE         16625000
 #elif defined CONFIG_ARCH_MX25
 #define CLOCK_TICK_RATE         16000000
+#elif defined CONFIG_ARCH_MXC91231
+#define CLOCK_TICK_RATE         13000000
 #endif
 
 #endif                          /* __ASM_ARCH_MXC_TIMEX_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h
index 1e24499f20b5..082a3908256b 100644
--- a/arch/arm/plat-mxc/include/mach/uncompress.h
+++ b/arch/arm/plat-mxc/include/mach/uncompress.h
@@ -66,6 +66,7 @@ static void putc(int ch)
 #define MX25_UART1_BASE_ADDR    0x43f90000
 #define MX2X_UART1_BASE_ADDR    0x1000a000
 #define MX3X_UART1_BASE_ADDR    0x43F90000
+#define MX3X_UART2_BASE_ADDR    0x43F94000
 
 static __inline__ void __arch_decomp_setup(unsigned long arch_id)
 {
@@ -95,6 +96,9 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
         case MACH_TYPE_PCM043:
                 uart_base = MX3X_UART1_BASE_ADDR;
                 break;
+        case MACH_TYPE_MAGX_ZN5:
+                uart_base = MX3X_UART2_BASE_ADDR;
+                break;
         default:
                 break;
         }
diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c
index 15e30532f4a5..97f42799fa58 100644
--- a/arch/arm/plat-mxc/system.c
+++ b/arch/arm/plat-mxc/system.c
@@ -27,6 +27,7 @@
 #include <linux/delay.h>
 
 #include <mach/hardware.h>
+#include <mach/common.h>
 #include <asm/proc-fns.h>
 #include <asm/system.h>
 
@@ -39,6 +40,12 @@ void arch_reset(char mode, const char *cmd)
 {
         unsigned int wcr_enable;
 
+#ifdef CONFIG_ARCH_MXC91231
+        if (cpu_is_mxc91231()) {
+                mxc91231_arch_reset(mode, cmd);
+                return;
+        }
+#endif
         if (cpu_is_mx1()) {
                 wcr_enable = (1 << 0);
         } else {
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c
index 59e33a3bf7f3..844567ee35fe 100644
--- a/arch/arm/plat-mxc/time.c
+++ b/arch/arm/plat-mxc/time.c
@@ -47,7 +47,7 @@
 #define MX2_TSTAT_CAPT          (1 << 1)
 #define MX2_TSTAT_COMP          (1 << 0)
 
-/* MX31, MX35, MX25 */
+/* MX31, MX35, MX25, MXC91231 */
 #define MX3_TCTL_WAITEN         (1 << 3)
 #define MX3_TCTL_CLK_IPG        (1 << 6)
 #define MX3_TCTL_FRR            (1 << 9)