diff options
-rw-r--r-- | arch/arm/mach-realview/core.h | 1 | ||||
-rw-r--r-- | arch/arm/mach-realview/realview_eb.c | 21 | ||||
-rw-r--r-- | arch/arm/mach-realview/realview_pb1176.c | 21 | ||||
-rw-r--r-- | arch/arm/mach-realview/realview_pb11mp.c | 21 | ||||
-rw-r--r-- | arch/arm/mach-realview/realview_pba8.c | 21 | ||||
-rw-r--r-- | arch/arm/mach-realview/realview_pbx.c | 21 |
6 files changed, 0 insertions, 106 deletions
diff --git a/arch/arm/mach-realview/core.h b/arch/arm/mach-realview/core.h index 27c927387083..5c83d1e87a03 100644 --- a/arch/arm/mach-realview/core.h +++ b/arch/arm/mach-realview/core.h | |||
@@ -42,7 +42,6 @@ static struct amba_device name##_device = { \ | |||
42 | }, \ | 42 | }, \ |
43 | .dma_mask = ~0, \ | 43 | .dma_mask = ~0, \ |
44 | .irq = base##_IRQ, \ | 44 | .irq = base##_IRQ, \ |
45 | /* .dma = base##_DMA,*/ \ | ||
46 | } | 45 | } |
47 | 46 | ||
48 | struct machine_desc; | 47 | struct machine_desc; |
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c index c00e52754efe..d0f851b886db 100644 --- a/arch/arm/mach-realview/realview_eb.c +++ b/arch/arm/mach-realview/realview_eb.c | |||
@@ -144,60 +144,39 @@ static struct pl022_ssp_controller ssp0_plat_data = { | |||
144 | * These devices are connected via the core APB bridge | 144 | * These devices are connected via the core APB bridge |
145 | */ | 145 | */ |
146 | #define GPIO2_IRQ { IRQ_EB_GPIO2, NO_IRQ } | 146 | #define GPIO2_IRQ { IRQ_EB_GPIO2, NO_IRQ } |
147 | #define GPIO2_DMA { 0, 0 } | ||
148 | #define GPIO3_IRQ { IRQ_EB_GPIO3, NO_IRQ } | 147 | #define GPIO3_IRQ { IRQ_EB_GPIO3, NO_IRQ } |
149 | #define GPIO3_DMA { 0, 0 } | ||
150 | 148 | ||
151 | #define AACI_IRQ { IRQ_EB_AACI, NO_IRQ } | 149 | #define AACI_IRQ { IRQ_EB_AACI, NO_IRQ } |
152 | #define AACI_DMA { 0x80, 0x81 } | ||
153 | #define MMCI0_IRQ { IRQ_EB_MMCI0A, IRQ_EB_MMCI0B } | 150 | #define MMCI0_IRQ { IRQ_EB_MMCI0A, IRQ_EB_MMCI0B } |
154 | #define MMCI0_DMA { 0x84, 0 } | ||
155 | #define KMI0_IRQ { IRQ_EB_KMI0, NO_IRQ } | 151 | #define KMI0_IRQ { IRQ_EB_KMI0, NO_IRQ } |
156 | #define KMI0_DMA { 0, 0 } | ||
157 | #define KMI1_IRQ { IRQ_EB_KMI1, NO_IRQ } | 152 | #define KMI1_IRQ { IRQ_EB_KMI1, NO_IRQ } |
158 | #define KMI1_DMA { 0, 0 } | ||
159 | 153 | ||
160 | /* | 154 | /* |
161 | * These devices are connected directly to the multi-layer AHB switch | 155 | * These devices are connected directly to the multi-layer AHB switch |
162 | */ | 156 | */ |
163 | #define EB_SMC_IRQ { NO_IRQ, NO_IRQ } | 157 | #define EB_SMC_IRQ { NO_IRQ, NO_IRQ } |
164 | #define EB_SMC_DMA { 0, 0 } | ||
165 | #define MPMC_IRQ { NO_IRQ, NO_IRQ } | 158 | #define MPMC_IRQ { NO_IRQ, NO_IRQ } |
166 | #define MPMC_DMA { 0, 0 } | ||
167 | #define EB_CLCD_IRQ { IRQ_EB_CLCD, NO_IRQ } | 159 | #define EB_CLCD_IRQ { IRQ_EB_CLCD, NO_IRQ } |
168 | #define EB_CLCD_DMA { 0, 0 } | ||
169 | #define DMAC_IRQ { IRQ_EB_DMA, NO_IRQ } | 160 | #define DMAC_IRQ { IRQ_EB_DMA, NO_IRQ } |
170 | #define DMAC_DMA { 0, 0 } | ||
171 | 161 | ||
172 | /* | 162 | /* |
173 | * These devices are connected via the core APB bridge | 163 | * These devices are connected via the core APB bridge |
174 | */ | 164 | */ |
175 | #define SCTL_IRQ { NO_IRQ, NO_IRQ } | 165 | #define SCTL_IRQ { NO_IRQ, NO_IRQ } |
176 | #define SCTL_DMA { 0, 0 } | ||
177 | #define EB_WATCHDOG_IRQ { IRQ_EB_WDOG, NO_IRQ } | 166 | #define EB_WATCHDOG_IRQ { IRQ_EB_WDOG, NO_IRQ } |
178 | #define EB_WATCHDOG_DMA { 0, 0 } | ||
179 | #define EB_GPIO0_IRQ { IRQ_EB_GPIO0, NO_IRQ } | 167 | #define EB_GPIO0_IRQ { IRQ_EB_GPIO0, NO_IRQ } |
180 | #define EB_GPIO0_DMA { 0, 0 } | ||
181 | #define GPIO1_IRQ { IRQ_EB_GPIO1, NO_IRQ } | 168 | #define GPIO1_IRQ { IRQ_EB_GPIO1, NO_IRQ } |
182 | #define GPIO1_DMA { 0, 0 } | ||
183 | #define EB_RTC_IRQ { IRQ_EB_RTC, NO_IRQ } | 169 | #define EB_RTC_IRQ { IRQ_EB_RTC, NO_IRQ } |
184 | #define EB_RTC_DMA { 0, 0 } | ||
185 | 170 | ||
186 | /* | 171 | /* |
187 | * These devices are connected via the DMA APB bridge | 172 | * These devices are connected via the DMA APB bridge |
188 | */ | 173 | */ |
189 | #define SCI_IRQ { IRQ_EB_SCI, NO_IRQ } | 174 | #define SCI_IRQ { IRQ_EB_SCI, NO_IRQ } |
190 | #define SCI_DMA { 7, 6 } | ||
191 | #define EB_UART0_IRQ { IRQ_EB_UART0, NO_IRQ } | 175 | #define EB_UART0_IRQ { IRQ_EB_UART0, NO_IRQ } |
192 | #define EB_UART0_DMA { 15, 14 } | ||
193 | #define EB_UART1_IRQ { IRQ_EB_UART1, NO_IRQ } | 176 | #define EB_UART1_IRQ { IRQ_EB_UART1, NO_IRQ } |
194 | #define EB_UART1_DMA { 13, 12 } | ||
195 | #define EB_UART2_IRQ { IRQ_EB_UART2, NO_IRQ } | 177 | #define EB_UART2_IRQ { IRQ_EB_UART2, NO_IRQ } |
196 | #define EB_UART2_DMA { 11, 10 } | ||
197 | #define EB_UART3_IRQ { IRQ_EB_UART3, NO_IRQ } | 178 | #define EB_UART3_IRQ { IRQ_EB_UART3, NO_IRQ } |
198 | #define EB_UART3_DMA { 0x86, 0x87 } | ||
199 | #define EB_SSP_IRQ { IRQ_EB_SSP, NO_IRQ } | 179 | #define EB_SSP_IRQ { IRQ_EB_SSP, NO_IRQ } |
200 | #define EB_SSP_DMA { 9, 8 } | ||
201 | 180 | ||
202 | /* FPGA Primecells */ | 181 | /* FPGA Primecells */ |
203 | AMBA_DEVICE(aaci, "fpga:aaci", AACI, NULL); | 182 | AMBA_DEVICE(aaci, "fpga:aaci", AACI, NULL); |
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c index f0447bbf809b..61f6a9d853fc 100644 --- a/arch/arm/mach-realview/realview_pb1176.c +++ b/arch/arm/mach-realview/realview_pb1176.c | |||
@@ -134,47 +134,26 @@ static struct pl022_ssp_controller ssp0_plat_data = { | |||
134 | * RealView PB1176 AMBA devices | 134 | * RealView PB1176 AMBA devices |
135 | */ | 135 | */ |
136 | #define GPIO2_IRQ { IRQ_PB1176_GPIO2, NO_IRQ } | 136 | #define GPIO2_IRQ { IRQ_PB1176_GPIO2, NO_IRQ } |
137 | #define GPIO2_DMA { 0, 0 } | ||
138 | #define GPIO3_IRQ { IRQ_PB1176_GPIO3, NO_IRQ } | 137 | #define GPIO3_IRQ { IRQ_PB1176_GPIO3, NO_IRQ } |
139 | #define GPIO3_DMA { 0, 0 } | ||
140 | #define AACI_IRQ { IRQ_PB1176_AACI, NO_IRQ } | 138 | #define AACI_IRQ { IRQ_PB1176_AACI, NO_IRQ } |
141 | #define AACI_DMA { 0x80, 0x81 } | ||
142 | #define MMCI0_IRQ { IRQ_PB1176_MMCI0A, IRQ_PB1176_MMCI0B } | 139 | #define MMCI0_IRQ { IRQ_PB1176_MMCI0A, IRQ_PB1176_MMCI0B } |
143 | #define MMCI0_DMA { 0x84, 0 } | ||
144 | #define KMI0_IRQ { IRQ_PB1176_KMI0, NO_IRQ } | 140 | #define KMI0_IRQ { IRQ_PB1176_KMI0, NO_IRQ } |
145 | #define KMI0_DMA { 0, 0 } | ||
146 | #define KMI1_IRQ { IRQ_PB1176_KMI1, NO_IRQ } | 141 | #define KMI1_IRQ { IRQ_PB1176_KMI1, NO_IRQ } |
147 | #define KMI1_DMA { 0, 0 } | ||
148 | #define PB1176_SMC_IRQ { NO_IRQ, NO_IRQ } | 142 | #define PB1176_SMC_IRQ { NO_IRQ, NO_IRQ } |
149 | #define PB1176_SMC_DMA { 0, 0 } | ||
150 | #define MPMC_IRQ { NO_IRQ, NO_IRQ } | 143 | #define MPMC_IRQ { NO_IRQ, NO_IRQ } |
151 | #define MPMC_DMA { 0, 0 } | ||
152 | #define PB1176_CLCD_IRQ { IRQ_DC1176_CLCD, NO_IRQ } | 144 | #define PB1176_CLCD_IRQ { IRQ_DC1176_CLCD, NO_IRQ } |
153 | #define PB1176_CLCD_DMA { 0, 0 } | ||
154 | #define SCTL_IRQ { NO_IRQ, NO_IRQ } | 145 | #define SCTL_IRQ { NO_IRQ, NO_IRQ } |
155 | #define SCTL_DMA { 0, 0 } | ||
156 | #define PB1176_WATCHDOG_IRQ { IRQ_DC1176_WATCHDOG, NO_IRQ } | 146 | #define PB1176_WATCHDOG_IRQ { IRQ_DC1176_WATCHDOG, NO_IRQ } |
157 | #define PB1176_WATCHDOG_DMA { 0, 0 } | ||
158 | #define PB1176_GPIO0_IRQ { IRQ_PB1176_GPIO0, NO_IRQ } | 147 | #define PB1176_GPIO0_IRQ { IRQ_PB1176_GPIO0, NO_IRQ } |
159 | #define PB1176_GPIO0_DMA { 0, 0 } | ||
160 | #define GPIO1_IRQ { IRQ_PB1176_GPIO1, NO_IRQ } | 148 | #define GPIO1_IRQ { IRQ_PB1176_GPIO1, NO_IRQ } |
161 | #define GPIO1_DMA { 0, 0 } | ||
162 | #define PB1176_RTC_IRQ { IRQ_DC1176_RTC, NO_IRQ } | 149 | #define PB1176_RTC_IRQ { IRQ_DC1176_RTC, NO_IRQ } |
163 | #define PB1176_RTC_DMA { 0, 0 } | ||
164 | #define SCI_IRQ { IRQ_PB1176_SCI, NO_IRQ } | 150 | #define SCI_IRQ { IRQ_PB1176_SCI, NO_IRQ } |
165 | #define SCI_DMA { 7, 6 } | ||
166 | #define PB1176_UART0_IRQ { IRQ_DC1176_UART0, NO_IRQ } | 151 | #define PB1176_UART0_IRQ { IRQ_DC1176_UART0, NO_IRQ } |
167 | #define PB1176_UART0_DMA { 15, 14 } | ||
168 | #define PB1176_UART1_IRQ { IRQ_DC1176_UART1, NO_IRQ } | 152 | #define PB1176_UART1_IRQ { IRQ_DC1176_UART1, NO_IRQ } |
169 | #define PB1176_UART1_DMA { 13, 12 } | ||
170 | #define PB1176_UART2_IRQ { IRQ_DC1176_UART2, NO_IRQ } | 153 | #define PB1176_UART2_IRQ { IRQ_DC1176_UART2, NO_IRQ } |
171 | #define PB1176_UART2_DMA { 11, 10 } | ||
172 | #define PB1176_UART3_IRQ { IRQ_DC1176_UART3, NO_IRQ } | 154 | #define PB1176_UART3_IRQ { IRQ_DC1176_UART3, NO_IRQ } |
173 | #define PB1176_UART3_DMA { 0x86, 0x87 } | ||
174 | #define PB1176_UART4_IRQ { IRQ_PB1176_UART4, NO_IRQ } | 155 | #define PB1176_UART4_IRQ { IRQ_PB1176_UART4, NO_IRQ } |
175 | #define PB1176_UART4_DMA { 0, 0 } | ||
176 | #define PB1176_SSP_IRQ { IRQ_DC1176_SSP, NO_IRQ } | 156 | #define PB1176_SSP_IRQ { IRQ_DC1176_SSP, NO_IRQ } |
177 | #define PB1176_SSP_DMA { 9, 8 } | ||
178 | 157 | ||
179 | /* FPGA Primecells */ | 158 | /* FPGA Primecells */ |
180 | AMBA_DEVICE(aaci, "fpga:aaci", AACI, NULL); | 159 | AMBA_DEVICE(aaci, "fpga:aaci", AACI, NULL); |
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c index 3b4f78870ac1..27bfeca89129 100644 --- a/arch/arm/mach-realview/realview_pb11mp.c +++ b/arch/arm/mach-realview/realview_pb11mp.c | |||
@@ -136,47 +136,26 @@ static struct pl022_ssp_controller ssp0_plat_data = { | |||
136 | */ | 136 | */ |
137 | 137 | ||
138 | #define GPIO2_IRQ { IRQ_PB11MP_GPIO2, NO_IRQ } | 138 | #define GPIO2_IRQ { IRQ_PB11MP_GPIO2, NO_IRQ } |
139 | #define GPIO2_DMA { 0, 0 } | ||
140 | #define GPIO3_IRQ { IRQ_PB11MP_GPIO3, NO_IRQ } | 139 | #define GPIO3_IRQ { IRQ_PB11MP_GPIO3, NO_IRQ } |
141 | #define GPIO3_DMA { 0, 0 } | ||
142 | #define AACI_IRQ { IRQ_TC11MP_AACI, NO_IRQ } | 140 | #define AACI_IRQ { IRQ_TC11MP_AACI, NO_IRQ } |
143 | #define AACI_DMA { 0x80, 0x81 } | ||
144 | #define MMCI0_IRQ { IRQ_TC11MP_MMCI0A, IRQ_TC11MP_MMCI0B } | 141 | #define MMCI0_IRQ { IRQ_TC11MP_MMCI0A, IRQ_TC11MP_MMCI0B } |
145 | #define MMCI0_DMA { 0x84, 0 } | ||
146 | #define KMI0_IRQ { IRQ_TC11MP_KMI0, NO_IRQ } | 142 | #define KMI0_IRQ { IRQ_TC11MP_KMI0, NO_IRQ } |
147 | #define KMI0_DMA { 0, 0 } | ||
148 | #define KMI1_IRQ { IRQ_TC11MP_KMI1, NO_IRQ } | 143 | #define KMI1_IRQ { IRQ_TC11MP_KMI1, NO_IRQ } |
149 | #define KMI1_DMA { 0, 0 } | ||
150 | #define PB11MP_SMC_IRQ { NO_IRQ, NO_IRQ } | 144 | #define PB11MP_SMC_IRQ { NO_IRQ, NO_IRQ } |
151 | #define PB11MP_SMC_DMA { 0, 0 } | ||
152 | #define MPMC_IRQ { NO_IRQ, NO_IRQ } | 145 | #define MPMC_IRQ { NO_IRQ, NO_IRQ } |
153 | #define MPMC_DMA { 0, 0 } | ||
154 | #define PB11MP_CLCD_IRQ { IRQ_PB11MP_CLCD, NO_IRQ } | 146 | #define PB11MP_CLCD_IRQ { IRQ_PB11MP_CLCD, NO_IRQ } |
155 | #define PB11MP_CLCD_DMA { 0, 0 } | ||
156 | #define DMAC_IRQ { IRQ_PB11MP_DMAC, NO_IRQ } | 147 | #define DMAC_IRQ { IRQ_PB11MP_DMAC, NO_IRQ } |
157 | #define DMAC_DMA { 0, 0 } | ||
158 | #define SCTL_IRQ { NO_IRQ, NO_IRQ } | 148 | #define SCTL_IRQ { NO_IRQ, NO_IRQ } |
159 | #define SCTL_DMA { 0, 0 } | ||
160 | #define PB11MP_WATCHDOG_IRQ { IRQ_PB11MP_WATCHDOG, NO_IRQ } | 149 | #define PB11MP_WATCHDOG_IRQ { IRQ_PB11MP_WATCHDOG, NO_IRQ } |
161 | #define PB11MP_WATCHDOG_DMA { 0, 0 } | ||
162 | #define PB11MP_GPIO0_IRQ { IRQ_PB11MP_GPIO0, NO_IRQ } | 150 | #define PB11MP_GPIO0_IRQ { IRQ_PB11MP_GPIO0, NO_IRQ } |
163 | #define PB11MP_GPIO0_DMA { 0, 0 } | ||
164 | #define GPIO1_IRQ { IRQ_PB11MP_GPIO1, NO_IRQ } | 151 | #define GPIO1_IRQ { IRQ_PB11MP_GPIO1, NO_IRQ } |
165 | #define GPIO1_DMA { 0, 0 } | ||
166 | #define PB11MP_RTC_IRQ { IRQ_TC11MP_RTC, NO_IRQ } | 152 | #define PB11MP_RTC_IRQ { IRQ_TC11MP_RTC, NO_IRQ } |
167 | #define PB11MP_RTC_DMA { 0, 0 } | ||
168 | #define SCI_IRQ { IRQ_PB11MP_SCI, NO_IRQ } | 153 | #define SCI_IRQ { IRQ_PB11MP_SCI, NO_IRQ } |
169 | #define SCI_DMA { 7, 6 } | ||
170 | #define PB11MP_UART0_IRQ { IRQ_TC11MP_UART0, NO_IRQ } | 154 | #define PB11MP_UART0_IRQ { IRQ_TC11MP_UART0, NO_IRQ } |
171 | #define PB11MP_UART0_DMA { 15, 14 } | ||
172 | #define PB11MP_UART1_IRQ { IRQ_TC11MP_UART1, NO_IRQ } | 155 | #define PB11MP_UART1_IRQ { IRQ_TC11MP_UART1, NO_IRQ } |
173 | #define PB11MP_UART1_DMA { 13, 12 } | ||
174 | #define PB11MP_UART2_IRQ { IRQ_PB11MP_UART2, NO_IRQ } | 156 | #define PB11MP_UART2_IRQ { IRQ_PB11MP_UART2, NO_IRQ } |
175 | #define PB11MP_UART2_DMA { 11, 10 } | ||
176 | #define PB11MP_UART3_IRQ { IRQ_PB11MP_UART3, NO_IRQ } | 157 | #define PB11MP_UART3_IRQ { IRQ_PB11MP_UART3, NO_IRQ } |
177 | #define PB11MP_UART3_DMA { 0x86, 0x87 } | ||
178 | #define PB11MP_SSP_IRQ { IRQ_PB11MP_SSP, NO_IRQ } | 158 | #define PB11MP_SSP_IRQ { IRQ_PB11MP_SSP, NO_IRQ } |
179 | #define PB11MP_SSP_DMA { 9, 8 } | ||
180 | 159 | ||
181 | /* FPGA Primecells */ | 160 | /* FPGA Primecells */ |
182 | AMBA_DEVICE(aaci, "fpga:aaci", AACI, NULL); | 161 | AMBA_DEVICE(aaci, "fpga:aaci", AACI, NULL); |
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c index f98d4fa74e30..11972df94313 100644 --- a/arch/arm/mach-realview/realview_pba8.c +++ b/arch/arm/mach-realview/realview_pba8.c | |||
@@ -126,47 +126,26 @@ static struct pl022_ssp_controller ssp0_plat_data = { | |||
126 | */ | 126 | */ |
127 | 127 | ||
128 | #define GPIO2_IRQ { IRQ_PBA8_GPIO2, NO_IRQ } | 128 | #define GPIO2_IRQ { IRQ_PBA8_GPIO2, NO_IRQ } |
129 | #define GPIO2_DMA { 0, 0 } | ||
130 | #define GPIO3_IRQ { IRQ_PBA8_GPIO3, NO_IRQ } | 129 | #define GPIO3_IRQ { IRQ_PBA8_GPIO3, NO_IRQ } |
131 | #define GPIO3_DMA { 0, 0 } | ||
132 | #define AACI_IRQ { IRQ_PBA8_AACI, NO_IRQ } | 130 | #define AACI_IRQ { IRQ_PBA8_AACI, NO_IRQ } |
133 | #define AACI_DMA { 0x80, 0x81 } | ||
134 | #define MMCI0_IRQ { IRQ_PBA8_MMCI0A, IRQ_PBA8_MMCI0B } | 131 | #define MMCI0_IRQ { IRQ_PBA8_MMCI0A, IRQ_PBA8_MMCI0B } |
135 | #define MMCI0_DMA { 0x84, 0 } | ||
136 | #define KMI0_IRQ { IRQ_PBA8_KMI0, NO_IRQ } | 132 | #define KMI0_IRQ { IRQ_PBA8_KMI0, NO_IRQ } |
137 | #define KMI0_DMA { 0, 0 } | ||
138 | #define KMI1_IRQ { IRQ_PBA8_KMI1, NO_IRQ } | 133 | #define KMI1_IRQ { IRQ_PBA8_KMI1, NO_IRQ } |
139 | #define KMI1_DMA { 0, 0 } | ||
140 | #define PBA8_SMC_IRQ { NO_IRQ, NO_IRQ } | 134 | #define PBA8_SMC_IRQ { NO_IRQ, NO_IRQ } |
141 | #define PBA8_SMC_DMA { 0, 0 } | ||
142 | #define MPMC_IRQ { NO_IRQ, NO_IRQ } | 135 | #define MPMC_IRQ { NO_IRQ, NO_IRQ } |
143 | #define MPMC_DMA { 0, 0 } | ||
144 | #define PBA8_CLCD_IRQ { IRQ_PBA8_CLCD, NO_IRQ } | 136 | #define PBA8_CLCD_IRQ { IRQ_PBA8_CLCD, NO_IRQ } |
145 | #define PBA8_CLCD_DMA { 0, 0 } | ||
146 | #define DMAC_IRQ { IRQ_PBA8_DMAC, NO_IRQ } | 137 | #define DMAC_IRQ { IRQ_PBA8_DMAC, NO_IRQ } |
147 | #define DMAC_DMA { 0, 0 } | ||
148 | #define SCTL_IRQ { NO_IRQ, NO_IRQ } | 138 | #define SCTL_IRQ { NO_IRQ, NO_IRQ } |
149 | #define SCTL_DMA { 0, 0 } | ||
150 | #define PBA8_WATCHDOG_IRQ { IRQ_PBA8_WATCHDOG, NO_IRQ } | 139 | #define PBA8_WATCHDOG_IRQ { IRQ_PBA8_WATCHDOG, NO_IRQ } |
151 | #define PBA8_WATCHDOG_DMA { 0, 0 } | ||
152 | #define PBA8_GPIO0_IRQ { IRQ_PBA8_GPIO0, NO_IRQ } | 140 | #define PBA8_GPIO0_IRQ { IRQ_PBA8_GPIO0, NO_IRQ } |
153 | #define PBA8_GPIO0_DMA { 0, 0 } | ||
154 | #define GPIO1_IRQ { IRQ_PBA8_GPIO1, NO_IRQ } | 141 | #define GPIO1_IRQ { IRQ_PBA8_GPIO1, NO_IRQ } |
155 | #define GPIO1_DMA { 0, 0 } | ||
156 | #define PBA8_RTC_IRQ { IRQ_PBA8_RTC, NO_IRQ } | 142 | #define PBA8_RTC_IRQ { IRQ_PBA8_RTC, NO_IRQ } |
157 | #define PBA8_RTC_DMA { 0, 0 } | ||
158 | #define SCI_IRQ { IRQ_PBA8_SCI, NO_IRQ } | 143 | #define SCI_IRQ { IRQ_PBA8_SCI, NO_IRQ } |
159 | #define SCI_DMA { 7, 6 } | ||
160 | #define PBA8_UART0_IRQ { IRQ_PBA8_UART0, NO_IRQ } | 144 | #define PBA8_UART0_IRQ { IRQ_PBA8_UART0, NO_IRQ } |
161 | #define PBA8_UART0_DMA { 15, 14 } | ||
162 | #define PBA8_UART1_IRQ { IRQ_PBA8_UART1, NO_IRQ } | 145 | #define PBA8_UART1_IRQ { IRQ_PBA8_UART1, NO_IRQ } |
163 | #define PBA8_UART1_DMA { 13, 12 } | ||
164 | #define PBA8_UART2_IRQ { IRQ_PBA8_UART2, NO_IRQ } | 146 | #define PBA8_UART2_IRQ { IRQ_PBA8_UART2, NO_IRQ } |
165 | #define PBA8_UART2_DMA { 11, 10 } | ||
166 | #define PBA8_UART3_IRQ { IRQ_PBA8_UART3, NO_IRQ } | 147 | #define PBA8_UART3_IRQ { IRQ_PBA8_UART3, NO_IRQ } |
167 | #define PBA8_UART3_DMA { 0x86, 0x87 } | ||
168 | #define PBA8_SSP_IRQ { IRQ_PBA8_SSP, NO_IRQ } | 148 | #define PBA8_SSP_IRQ { IRQ_PBA8_SSP, NO_IRQ } |
169 | #define PBA8_SSP_DMA { 9, 8 } | ||
170 | 149 | ||
171 | /* FPGA Primecells */ | 150 | /* FPGA Primecells */ |
172 | AMBA_DEVICE(aaci, "fpga:aaci", AACI, NULL); | 151 | AMBA_DEVICE(aaci, "fpga:aaci", AACI, NULL); |
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c index b0521e1bb1ae..73ab3ca9355e 100644 --- a/arch/arm/mach-realview/realview_pbx.c +++ b/arch/arm/mach-realview/realview_pbx.c | |||
@@ -148,47 +148,26 @@ static struct pl022_ssp_controller ssp0_plat_data = { | |||
148 | */ | 148 | */ |
149 | 149 | ||
150 | #define GPIO2_IRQ { IRQ_PBX_GPIO2, NO_IRQ } | 150 | #define GPIO2_IRQ { IRQ_PBX_GPIO2, NO_IRQ } |
151 | #define GPIO2_DMA { 0, 0 } | ||
152 | #define GPIO3_IRQ { IRQ_PBX_GPIO3, NO_IRQ } | 151 | #define GPIO3_IRQ { IRQ_PBX_GPIO3, NO_IRQ } |
153 | #define GPIO3_DMA { 0, 0 } | ||
154 | #define AACI_IRQ { IRQ_PBX_AACI, NO_IRQ } | 152 | #define AACI_IRQ { IRQ_PBX_AACI, NO_IRQ } |
155 | #define AACI_DMA { 0x80, 0x81 } | ||
156 | #define MMCI0_IRQ { IRQ_PBX_MMCI0A, IRQ_PBX_MMCI0B } | 153 | #define MMCI0_IRQ { IRQ_PBX_MMCI0A, IRQ_PBX_MMCI0B } |
157 | #define MMCI0_DMA { 0x84, 0 } | ||
158 | #define KMI0_IRQ { IRQ_PBX_KMI0, NO_IRQ } | 154 | #define KMI0_IRQ { IRQ_PBX_KMI0, NO_IRQ } |
159 | #define KMI0_DMA { 0, 0 } | ||
160 | #define KMI1_IRQ { IRQ_PBX_KMI1, NO_IRQ } | 155 | #define KMI1_IRQ { IRQ_PBX_KMI1, NO_IRQ } |
161 | #define KMI1_DMA { 0, 0 } | ||
162 | #define PBX_SMC_IRQ { NO_IRQ, NO_IRQ } | 156 | #define PBX_SMC_IRQ { NO_IRQ, NO_IRQ } |
163 | #define PBX_SMC_DMA { 0, 0 } | ||
164 | #define MPMC_IRQ { NO_IRQ, NO_IRQ } | 157 | #define MPMC_IRQ { NO_IRQ, NO_IRQ } |
165 | #define MPMC_DMA { 0, 0 } | ||
166 | #define PBX_CLCD_IRQ { IRQ_PBX_CLCD, NO_IRQ } | 158 | #define PBX_CLCD_IRQ { IRQ_PBX_CLCD, NO_IRQ } |
167 | #define PBX_CLCD_DMA { 0, 0 } | ||
168 | #define DMAC_IRQ { IRQ_PBX_DMAC, NO_IRQ } | 159 | #define DMAC_IRQ { IRQ_PBX_DMAC, NO_IRQ } |
169 | #define DMAC_DMA { 0, 0 } | ||
170 | #define SCTL_IRQ { NO_IRQ, NO_IRQ } | 160 | #define SCTL_IRQ { NO_IRQ, NO_IRQ } |
171 | #define SCTL_DMA { 0, 0 } | ||
172 | #define PBX_WATCHDOG_IRQ { IRQ_PBX_WATCHDOG, NO_IRQ } | 161 | #define PBX_WATCHDOG_IRQ { IRQ_PBX_WATCHDOG, NO_IRQ } |
173 | #define PBX_WATCHDOG_DMA { 0, 0 } | ||
174 | #define PBX_GPIO0_IRQ { IRQ_PBX_GPIO0, NO_IRQ } | 162 | #define PBX_GPIO0_IRQ { IRQ_PBX_GPIO0, NO_IRQ } |
175 | #define PBX_GPIO0_DMA { 0, 0 } | ||
176 | #define GPIO1_IRQ { IRQ_PBX_GPIO1, NO_IRQ } | 163 | #define GPIO1_IRQ { IRQ_PBX_GPIO1, NO_IRQ } |
177 | #define GPIO1_DMA { 0, 0 } | ||
178 | #define PBX_RTC_IRQ { IRQ_PBX_RTC, NO_IRQ } | 164 | #define PBX_RTC_IRQ { IRQ_PBX_RTC, NO_IRQ } |
179 | #define PBX_RTC_DMA { 0, 0 } | ||
180 | #define SCI_IRQ { IRQ_PBX_SCI, NO_IRQ } | 165 | #define SCI_IRQ { IRQ_PBX_SCI, NO_IRQ } |
181 | #define SCI_DMA { 7, 6 } | ||
182 | #define PBX_UART0_IRQ { IRQ_PBX_UART0, NO_IRQ } | 166 | #define PBX_UART0_IRQ { IRQ_PBX_UART0, NO_IRQ } |
183 | #define PBX_UART0_DMA { 15, 14 } | ||
184 | #define PBX_UART1_IRQ { IRQ_PBX_UART1, NO_IRQ } | 167 | #define PBX_UART1_IRQ { IRQ_PBX_UART1, NO_IRQ } |
185 | #define PBX_UART1_DMA { 13, 12 } | ||
186 | #define PBX_UART2_IRQ { IRQ_PBX_UART2, NO_IRQ } | 168 | #define PBX_UART2_IRQ { IRQ_PBX_UART2, NO_IRQ } |
187 | #define PBX_UART2_DMA { 11, 10 } | ||
188 | #define PBX_UART3_IRQ { IRQ_PBX_UART3, NO_IRQ } | 169 | #define PBX_UART3_IRQ { IRQ_PBX_UART3, NO_IRQ } |
189 | #define PBX_UART3_DMA { 0x86, 0x87 } | ||
190 | #define PBX_SSP_IRQ { IRQ_PBX_SSP, NO_IRQ } | 170 | #define PBX_SSP_IRQ { IRQ_PBX_SSP, NO_IRQ } |
191 | #define PBX_SSP_DMA { 9, 8 } | ||
192 | 171 | ||
193 | /* FPGA Primecells */ | 172 | /* FPGA Primecells */ |
194 | AMBA_DEVICE(aaci, "fpga:aaci", AACI, NULL); | 173 | AMBA_DEVICE(aaci, "fpga:aaci", AACI, NULL); |