81 files changed, 2323 insertions, 99 deletions

diff --git a/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt b/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt
new file mode 100644
index 000000000000..70c0dc5f00ed
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt
@@ -0,0 +1,23 @@
+Marvell Armada 370 and Armada XP Interrupt Controller
+-----------------------------------------------------
+
+Required properties:
+- compatible: Should be "marvell,mpic"
+- interrupt-controller: Identifies the node as an interrupt controller.
+- #interrupt-cells: The number of cells to define the interrupts. Should be 1.
+  The cell is the IRQ number
+- reg: Should contain PMIC registers location and length. First pair
+  for the main interrupt registers, second pair for the per-CPU
+  interrupt registers
+
+Example:
+
+        mpic: interrupt-controller@d0020000 {
+              compatible = "marvell,mpic";
+              #interrupt-cells = <1>;
+              #address-cells = <1>;
+              #size-cells = <1>;
+              interrupt-controller;
+              reg = <0xd0020000 0x1000>,
+                    <0xd0021000 0x1000>;
+        };
diff --git a/Documentation/devicetree/bindings/arm/armada-370-xp-timer.txt b/Documentation/devicetree/bindings/arm/armada-370-xp-timer.txt
new file mode 100644
index 000000000000..8b6ea2267c94
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/armada-370-xp-timer.txt
@@ -0,0 +1,11 @@
+Marvell Armada 370 and Armada XP Global Timers
+----------------------------------------------
+
+Required properties:
+- compatible: Should be "marvell,armada-370-xp-timer"
+- interrupts: Should contain the list of Global Timer interrupts
+- reg: Should contain the base address of the Global Timer registers
+
+Optional properties:
+- marvell,timer-25Mhz: Tells whether the Global timer supports the 25
+  Mhz fixed mode (available on Armada XP and not on Armada 370)
diff --git a/Documentation/devicetree/bindings/arm/armada-370-xp.txt b/Documentation/devicetree/bindings/arm/armada-370-xp.txt
new file mode 100644
index 000000000000..c6ed90ea6e17
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/armada-370-xp.txt
@@ -0,0 +1,24 @@
+Marvell Armada 370 and Armada XP Platforms Device Tree Bindings
+---------------------------------------------------------------
+
+Boards with a SoC of the Marvell Armada 370 and Armada XP families
+shall have the following property:
+
+Required root node property:
+
+compatible: must contain "marvell,armada-370-xp"
+
+In addition, boards using the Marvell Armada 370 SoC shall have the
+following property:
+
+Required root node property:
+
+compatible: must contain "marvell,armada370"
+
+In addition, boards using the Marvell Armada XP SoC shall have the
+following property:
+
+Required root node property:
+
+compatible: must contain "marvell,armadaxp"
+
diff --git a/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt b/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt
new file mode 100644
index 000000000000..081c6a786c8a
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt
@@ -0,0 +1,17 @@
+MVEBU System Controller
+-----------------------
+MVEBU (Marvell SOCs: Armada 370/XP, Dove, mv78xx0, Kirkwood, Orion5x)
+
+Required properties:
+
+- compatible: one of:
+        - "marvell,orion-system-controller"
+        - "marvell,armada-370-xp-system-controller"
+- reg: Should contain system controller registers location and length.
+
+Example:
+
+        system-controller@d0018200 {
+                compatible = "marvell,armada-370-xp-system-controller";
+                reg = <0xd0018200 0x500>;
+        };
diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt
index f186167dba9e..ccdd0e53451f 100644
--- a/Documentation/devicetree/bindings/arm/omap/omap.txt
+++ b/Documentation/devicetree/bindings/arm/omap/omap.txt
@@ -50,3 +50,6 @@ Boards:
 
 - AM335X Bone : Low cost community board
   compatible = "ti,am335x-bone", "ti,am33xx", "ti,omap3"
+
+- OMAP5 EVM : Evaluation Module
+  compatible = "ti,omap5-evm", "ti,omap5"
diff --git a/MAINTAINERS b/MAINTAINERS
index fe643e7b9df6..fe2fa33e2831 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -894,6 +894,14 @@ ARM/MAGICIAN MACHINE SUPPORT
 M:      Philipp Zabel <philipp.zabel@gmail.com>
 S:      Maintained
 
+ARM/Marvell Armada 370 and Armada XP SOC support
+M:      Jason Cooper <jason@lakedaemon.net>
+M:      Andrew Lunn <andrew@lunn.ch>
+M:      Gregory Clement <gregory.clement@free-electrons.com>
+L:      linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+S:      Maintained
+F:      arch/arm/mach-mvebu/
+
 ARM/Marvell Dove/Kirkwood/MV78xx0/Orion SOC support
 M:      Jason Cooper <jason@lakedaemon.net>
 M:      Andrew Lunn <andrew@lunn.ch>
@@ -1103,6 +1111,16 @@ S:	Supported
 F:      arch/arm/mach-shmobile/
 F:      drivers/sh/
 
+ARM/SOCFPGA ARCHITECTURE
+M:      Dinh Nguyen <dinguyen@altera.com>
+S:      Maintained
+F:      arch/arm/mach-socfpga/
+
+ARM/SOCFPGA CLOCK FRAMEWORK SUPPORT
+M:      Dinh Nguyen <dinguyen@altera.com>
+S:      Maintained
+F:      drivers/clk/socfpga/
+
 ARM/TECHNOLOGIC SYSTEMS TS7250 MACHINE SUPPORT
 M:      Lennert Buytenhek <kernel@wantstofly.org>
 L:      linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5dbb9562742c..b16396216896 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -250,6 +250,25 @@ choice
         prompt "ARM system type"
         default ARCH_VERSATILE
 
+config ARCH_SOCFPGA
+        bool "Altera SOCFPGA family"
+        select ARCH_WANT_OPTIONAL_GPIOLIB
+        select ARM_AMBA
+        select ARM_GIC
+        select CACHE_L2X0
+        select CLKDEV_LOOKUP
+        select COMMON_CLK
+        select CPU_V7
+        select DW_APB_TIMER
+        select DW_APB_TIMER_OF
+        select GENERIC_CLOCKEVENTS
+        select GPIO_PL061 if GPIOLIB
+        select HAVE_ARM_SCU
+        select SPARSE_IRQ
+        select USE_OF
+        help
+          This enables support for Altera SOCFPGA Cyclone V platform
+
 config ARCH_INTEGRATOR
         bool "ARM Ltd. Integrator family"
         select ARM_AMBA
@@ -537,6 +556,18 @@ config ARCH_IXP4XX
         help
           Support for Intel's IXP4XX (XScale) family of processors.
 
+config ARCH_MVEBU
+        bool "Marvell SOCs with Device Tree support"
+        select GENERIC_CLOCKEVENTS
+        select MULTI_IRQ_HANDLER
+        select SPARSE_IRQ
+        select CLKSRC_MMIO
+        select GENERIC_IRQ_CHIP
+        select IRQ_DOMAIN
+        select COMMON_CLK
+        help
+          Support for the Marvell SoC Family with device tree support
+
 config ARCH_DOVE
         bool "Marvell Dove"
         select CPU_V7
@@ -994,6 +1025,8 @@ endchoice
 # Kconfigs may be included either alphabetically (according to the
 # plat- suffix) or along side the corresponding mach-* source.
 #
+source "arch/arm/mach-mvebu/Kconfig"
+
 source "arch/arm/mach-at91/Kconfig"
 
 source "arch/arm/mach-bcmring/Kconfig"
@@ -1586,6 +1619,7 @@ config ARCH_NR_GPIO
         default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
         default 355 if ARCH_U8500
         default 264 if MACH_H4700
+        default 512 if SOC_OMAP5
         default 0
         help
           Maximum number of GPIOs in the system.
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 0298b00fe241..4d6d31115cf2 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -157,6 +157,7 @@ machine-$(CONFIG_ARCH_MV78XX0)		:= mv78xx0
 machine-$(CONFIG_ARCH_IMX_V4_V5)        := imx
 machine-$(CONFIG_ARCH_IMX_V6_V7)        := imx
 machine-$(CONFIG_ARCH_MXS)              := mxs
+machine-$(CONFIG_ARCH_MVEBU)            := mvebu
 machine-$(CONFIG_ARCH_NETX)             := netx
 machine-$(CONFIG_ARCH_NOMADIK)          := nomadik
 machine-$(CONFIG_ARCH_OMAP1)            := omap1
@@ -186,6 +187,7 @@ machine-$(CONFIG_ARCH_VEXPRESS)		:= vexpress
 machine-$(CONFIG_ARCH_VT8500)           := vt8500
 machine-$(CONFIG_ARCH_W90X900)          := w90x900
 machine-$(CONFIG_FOOTBRIDGE)            := footbridge
+machine-$(CONFIG_ARCH_SOCFPGA)          := socfpga
 machine-$(CONFIG_MACH_SPEAR1310)        := spear13xx
 machine-$(CONFIG_MACH_SPEAR1340)        := spear13xx
 machine-$(CONFIG_MACH_SPEAR300)         := spear3xx
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
new file mode 100644
index 000000000000..fffd5c2a3041
--- /dev/null
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -0,0 +1,42 @@
+/*
+ * Device Tree file for Marvell Armada 370 evaluation board
+ * (DB-88F6710-BP-DDR3)
+ *
+ *  Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+/include/ "armada-370.dtsi"
+
+/ {
+        model = "Marvell Armada 370 Evaluation Board";
+        compatible = "marvell,a370-db", "marvell,armada370", "marvell,armada-370-xp";
+
+        chosen {
+                bootargs = "console=ttyS0,115200 earlyprintk";
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x20000000>; /* 512 MB */
+        };
+
+        soc {
+                serial@d0012000 {
+                        clock-frequency = <200000000>;
+                        status = "okay";
+                };
+                timer@d0020300 {
+                        clock-frequency = <600000000>;
+                        status = "okay";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
new file mode 100644
index 000000000000..6b6b932a5a7d
--- /dev/null
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -0,0 +1,68 @@
+/*
+ * Device Tree Include file for Marvell Armada 370 and Armada XP SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ * Ben Dooks <ben.dooks@codethink.co.uk>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * This file contains the definitions that are common to the Armada
+ * 370 and Armada XP SoC.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        model = "Marvell Armada 370 and XP SoC";
+        compatible = "marvell,armada_370_xp";
+
+        cpus {
+                cpu@0 {
+                        compatible = "marvell,sheeva-v7";
+                };
+        };
+
+        mpic: interrupt-controller@d0020000 {
+              compatible = "marvell,mpic";
+              #interrupt-cells = <1>;
+              #address-cells = <1>;
+              #size-cells = <1>;
+              interrupt-controller;
+        };
+
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                interrupt-parent = <&mpic>;
+                ranges;
+
+                serial@d0012000 {
+                                compatible = "ns16550";
+                                reg = <0xd0012000 0x100>;
+                                reg-shift = <2>;
+                                interrupts = <41>;
+                                status = "disabled";
+                };
+                serial@d0012100 {
+                                compatible = "ns16550";
+                                reg = <0xd0012100 0x100>;
+                                reg-shift = <2>;
+                                interrupts = <42>;
+                                status = "disabled";
+                };
+
+                timer@d0020300 {
+                               compatible = "marvell,armada-370-xp-timer";
+                               reg = <0xd0020300 0x30>;
+                               interrupts = <37>, <38>, <39>, <40>;
+                };
+        };
+};
+
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
new file mode 100644
index 000000000000..3228ccc83332
--- /dev/null
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -0,0 +1,35 @@
+/*
+ * Device Tree Include file for Marvell Armada 370 family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Contains definitions specific to the Armada 370 SoC that are not
+ * common to all Armada SoCs.
+ */
+
+/include/ "armada-370-xp.dtsi"
+
+/ {
+        model = "Marvell Armada 370 family SoC";
+        compatible = "marvell,armada370", "marvell,armada-370-xp";
+
+        mpic: interrupt-controller@d0020000 {
+              reg = <0xd0020a00 0x1d0>,
+                    <0xd0021870 0x58>;
+        };
+
+        soc {
+                system-controller@d0018200 {
+                                compatible = "marvell,armada-370-xp-system-controller";
+                                reg = <0xd0018200 0x100>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
new file mode 100644
index 000000000000..f97040d4258d
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -0,0 +1,50 @@
+/*
+ * Device Tree file for Marvell Armada XP evaluation board
+ * (DB-78460-BP)
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+/include/ "armada-xp.dtsi"
+
+/ {
+        model = "Marvell Armada XP Evaluation Board";
+        compatible = "marvell,axp-db", "marvell,armadaxp", "marvell,armada-370-xp";
+
+        chosen {
+                bootargs = "console=ttyS0,115200 earlyprintk";
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x80000000>; /* 2 GB */
+        };
+
+        soc {
+                serial@d0012000 {
+                        clock-frequency = <250000000>;
+                        status = "okay";
+                };
+                serial@d0012100 {
+                        clock-frequency = <250000000>;
+                        status = "okay";
+                };
+                serial@d0012200 {
+                        clock-frequency = <250000000>;
+                        status = "okay";
+                };
+                serial@d0012300 {
+                        clock-frequency = <250000000>;
+                        status = "okay";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
new file mode 100644
index 000000000000..e1fa7e6edfe8
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -0,0 +1,55 @@
+/*
+ * Device Tree Include file for Marvell Armada XP family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ * Ben Dooks <ben.dooks@codethink.co.uk>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Contains definitions specific to the Armada 370 SoC that are not
+ * common to all Armada SoCs.
+ */
+
+/include/ "armada-370-xp.dtsi"
+
+/ {
+        model = "Marvell Armada XP family SoC";
+        compatible = "marvell,armadaxp", "marvell,armada-370-xp";
+
+        mpic: interrupt-controller@d0020000 {
+              reg = <0xd0020a00 0x1d0>,
+                    <0xd0021870 0x58>;
+        };
+
+        soc {
+                serial@d0012200 {
+                                compatible = "ns16550";
+                                reg = <0xd0012200 0x100>;
+                                reg-shift = <2>;
+                                interrupts = <43>;
+                                status = "disabled";
+                };
+                serial@d0012300 {
+                                compatible = "ns16550";
+                                reg = <0xd0012300 0x100>;
+                                reg-shift = <2>;
+                                interrupts = <44>;
+                                status = "disabled";
+                };
+
+                timer@d0020300 {
+                                marvell,timer-25Mhz;
+                };
+
+                system-controller@d0018200 {
+                                compatible = "marvell,armada-370-xp-system-controller";
+                                reg = <0xd0018200 0x500>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
new file mode 100644
index 000000000000..200c39ad1c82
--- /dev/null
+++ b/arch/arm/boot/dts/omap5-evm.dts
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+/include/ "omap5.dtsi"
+
+/ {
+        model = "TI OMAP5 EVM board";
+        compatible = "ti,omap5-evm", "ti,omap5";
+
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x40000000>; /* 1 GB */
+        };
+};
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
new file mode 100644
index 000000000000..57e527083746
--- /dev/null
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -0,0 +1,184 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ * Based on "omap4.dtsi"
+ */
+
+/*
+ * Carveout for multimedia usecases
+ * It should be the last 48MB of the first 512MB memory part
+ * In theory, it should not even exist. That zone should be reserved
+ * dynamically during the .reserve callback.
+ */
+/memreserve/ 0x9d000000 0x03000000;
+
+/include/ "skeleton.dtsi"
+
+/ {
+        compatible = "ti,omap5";
+        interrupt-parent = <&gic>;
+
+        aliases {
+                serial0 = &uart1;
+                serial1 = &uart2;
+                serial2 = &uart3;
+                serial3 = &uart4;
+                serial4 = &uart5;
+                serial5 = &uart6;
+        };
+
+        cpus {
+                cpu@0 {
+                        compatible = "arm,cortex-a15";
+                };
+                cpu@1 {
+                        compatible = "arm,cortex-a15";
+                };
+        };
+
+        /*
+         * The soc node represents the soc top level view. It is uses for IPs
+         * that are not memory mapped in the MPU view or for the MPU itself.
+         */
+        soc {
+                compatible = "ti,omap-infra";
+                mpu {
+                        compatible = "ti,omap5-mpu";
+                        ti,hwmods = "mpu";
+                };
+        };
+
+        /*
+         * XXX: Use a flat representation of the OMAP3 interconnect.
+         * The real OMAP interconnect network is quite complex.
+         * Since that will not bring real advantage to represent that in DT for
+         * the moment, just use a fake OCP bus entry to represent the whole bus
+         * hierarchy.
+         */
+        ocp {
+                compatible = "ti,omap4-l3-noc", "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
+
+                gic: interrupt-controller@48211000 {
+                        compatible = "arm,cortex-a15-gic";
+                        interrupt-controller;
+                        #interrupt-cells = <3>;
+                        reg = <0x48211000 0x1000>,
+                              <0x48212000 0x1000>;
+                };
+
+                gpio1: gpio@4ae10000 {
+                        compatible = "ti,omap4-gpio";
+                        ti,hwmods = "gpio1";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
+                gpio2: gpio@48055000 {
+                        compatible = "ti,omap4-gpio";
+                        ti,hwmods = "gpio2";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
+                gpio3: gpio@48057000 {
+                        compatible = "ti,omap4-gpio";
+                        ti,hwmods = "gpio3";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
+                gpio4: gpio@48059000 {
+                        compatible = "ti,omap4-gpio";
+                        ti,hwmods = "gpio4";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
+                gpio5: gpio@4805b000 {
+                        compatible = "ti,omap4-gpio";
+                        ti,hwmods = "gpio5";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
+                gpio6: gpio@4805d000 {
+                        compatible = "ti,omap4-gpio";
+                        ti,hwmods = "gpio6";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
+                gpio7: gpio@48051000 {
+                        compatible = "ti,omap4-gpio";
+                        ti,hwmods = "gpio7";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
+                gpio8: gpio@48053000 {
+                        compatible = "ti,omap4-gpio";
+                        ti,hwmods = "gpio8";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
+                uart1: serial@4806a000 {
+                        compatible = "ti,omap4-uart";
+                        ti,hwmods = "uart1";
+                        clock-frequency = <48000000>;
+                };
+
+                uart2: serial@4806c000 {
+                        compatible = "ti,omap4-uart";
+                        ti,hwmods = "uart2";
+                        clock-frequency = <48000000>;
+                };
+
+                uart3: serial@48020000 {
+                        compatible = "ti,omap4-uart";
+                        ti,hwmods = "uart3";
+                        clock-frequency = <48000000>;
+                };
+
+                uart4: serial@4806e000 {
+                        compatible = "ti,omap4-uart";
+                        ti,hwmods = "uart4";
+                        clock-frequency = <48000000>;
+                };
+
+                uart5: serial@48066000 {
+                        compatible = "ti,omap5-uart";
+                        ti,hwmods = "uart5";
+                        clock-frequency = <48000000>;
+                };
+
+                uart6: serial@48068000 {
+                        compatible = "ti,omap6-uart";
+                        ti,hwmods = "uart6";
+                        clock-frequency = <48000000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
new file mode 100644
index 000000000000..0772f5739f59
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -0,0 +1,147 @@
+/*
+ *  Copyright (C) 2012 Altera <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        aliases {
+                ethernet0 = &gmac0;
+                serial0 = &uart0;
+                serial1 = &uart1;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        compatible = "arm,cortex-a9";
+                        device_type = "cpu";
+                        reg = <0>;
+                        next-level-cache = <&L2>;
+                };
+                cpu@1 {
+                        compatible = "arm,cortex-a9";
+                        device_type = "cpu";
+                        reg = <1>;
+                        next-level-cache = <&L2>;
+                };
+        };
+
+        intc: intc@fffed000 {
+                compatible = "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                interrupt-controller;
+                reg = <0xfffed000 0x1000>,
+                      <0xfffec100 0x100>;
+        };
+
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                device_type = "soc";
+                interrupt-parent = <&intc>;
+                ranges;
+
+                amba {
+                        compatible = "arm,amba-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+
+                        pdma: pdma@ffe01000 {
+                                compatible = "arm,pl330", "arm,primecell";
+                                reg = <0xffe01000 0x1000>;
+                                interrupts = <0 180 4>;
+                        };
+                };
+
+                gmac0: stmmac@ff700000 {
+                        compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
+                        reg = <0xff700000 0x2000>;
+                        interrupts = <0 115 4>;
+                        interrupt-names = "macirq";
+                        mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
+                        phy-mode = "gmii";
+                };
+
+                L2: l2-cache@fffef000 {
+                        compatible = "arm,pl310-cache";
+                        reg = <0xfffef000 0x1000>;
+                        interrupts = <0 38 0x04>;
+                        cache-unified;
+                        cache-level = <2>;
+                };
+
+                /* Local timer */
+                timer@fffec600 {
+                        compatible = "arm,cortex-a9-twd-timer";
+                        reg = <0xfffec600 0x100>;
+                        interrupts = <1 13 0xf04>;
+                };
+
+                timer0: timer@ffc08000 {
+                        compatible = "snps,dw-apb-timer-sp";
+                        interrupts = <0 167 4>;
+                        clock-frequency = <200000000>;
+                        reg = <0xffc08000 0x1000>;
+                };
+
+                timer1: timer@ffc09000 {
+                        compatible = "snps,dw-apb-timer-sp";
+                        interrupts = <0 168 4>;
+                        clock-frequency = <200000000>;
+                        reg = <0xffc09000 0x1000>;
+                };
+
+                timer2: timer@ffd00000 {
+                        compatible = "snps,dw-apb-timer-osc";
+                        interrupts = <0 169 4>;
+                        clock-frequency = <200000000>;
+                        reg = <0xffd00000 0x1000>;
+                };
+
+                timer3: timer@ffd01000 {
+                        compatible = "snps,dw-apb-timer-osc";
+                        interrupts = <0 170 4>;
+                        clock-frequency = <200000000>;
+                        reg = <0xffd01000 0x1000>;
+                };
+
+                uart0: uart@ffc02000 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0xffc02000 0x1000>;
+                        clock-frequency = <7372800>;
+                        interrupts = <0 162 4>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                };
+
+                uart1: uart@ffc03000 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0xffc03000 0x1000>;
+                        clock-frequency = <7372800>;
+                        interrupts = <0 163 4>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts
new file mode 100644
index 000000000000..ab7e4a94299f
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dts
@@ -0,0 +1,34 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/dts-v1/;
+/include/ "socfpga.dtsi"
+
+/ {
+        model = "Altera SOCFPGA Cyclone V";
+        compatible = "altr,socfpga-cyclone5";
+
+        chosen {
+                bootargs = "console=ttyS0,57600";
+        };
+
+        memory {
+                name = "memory";
+                device_type = "memory";
+                reg = <0x0 0x10000000>; /* 256MB */
+        };
+};
diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig
new file mode 100644
index 000000000000..2e86b31c33cf
--- /dev/null
+++ b/arch/arm/configs/mvebu_defconfig
@@ -0,0 +1,46 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EXPERT=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_MACH_ARMADA_370_XP=y
+CONFIG_AEABI=y
+CONFIG_HIGHMEM=y
+CONFIG_USE_OF=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_VFP=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_FS_XATTR is not set
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=m
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+CONFIG_NLS_UTF8=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_FS=y
+# CONFIG_SCHED_DEBUG is not set
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_LL=y
+CONFIG_EARLY_PRINTK=y
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index d3c29b377af9..b152de79fd95 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -236,3 +236,4 @@ CONFIG_CRC_T10DIF=y
 CONFIG_CRC_ITU_T=y
 CONFIG_CRC7=y
 CONFIG_LIBCRC32C=y
+CONFIG_SOC_OMAP5=y
diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfpga_defconfig
new file mode 100644
index 000000000000..0ac1293dba10
--- /dev/null
+++ b/arch/arm/configs/socfpga_defconfig
@@ -0,0 +1,83 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_CGROUPS=y
+CONFIG_CPUSETS=y
+CONFIG_NAMESPACES=y
+CONFIG_EMBEDDED=y
+CONFIG_PROFILING=y
+CONFIG_OPROFILE=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_MACH_SOCFPGA_CYCLONE5=y
+CONFIG_ARM_THUMBEE=y
+# CONFIG_CACHE_L2X0 is not set
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_VMSPLIT_2G=y
+CONFIG_NR_CPUS=2
+CONFIG_AEABI=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=""
+CONFIG_VFP=y
+CONFIG_NEON=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_NET_KEY=y
+CONFIG_NET_KEY_MIGRATE=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_PROC_DEVICETREE=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=2
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_SCSI=y
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_BLK_DEV_SD=y
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_NETDEVICES=y
+CONFIG_STMMAC_ETH=y
+# CONFIG_STMMAC_PHY_ID_ZERO_WORKAROUND is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_SERIO_SERPORT is not set
+CONFIG_SERIO_AMBAKMI=y
+CONFIG_LEGACY_PTY_COUNT=16
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=2
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+CONFIG_SERIAL_8250_DW=y
+# CONFIG_RTC_HCTOSYS is not set
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY_USER is not set
+CONFIG_VFAT_FS=y
+CONFIG_NTFS_FS=y
+CONFIG_NTFS_RW=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_SCHED_DEBUG is not set
+CONFIG_DEBUG_INFO=y
+CONFIG_ENABLE_DEFAULT_TRACERS=y
+CONFIG_DEBUG_USER=y
+CONFIG_XZ_DEC=y
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
new file mode 100644
index 000000000000..caa2c5e734fe
--- /dev/null
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -0,0 +1,16 @@
+if ARCH_MVEBU
+
+menu "Marvell SOC with device tree"
+
+config MACH_ARMADA_370_XP
+        bool "Marvell Armada 370 and Aramada XP boards"
+        select ARMADA_370_XP_TIMER
+        select CPU_V7
+        help
+
+          Say 'Y' here if you want your kernel to support boards based on
+          Marvell Armada 370 or Armada XP with device tree.
+
+endmenu
+
+endif
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
new file mode 100644
index 000000000000..e61d2b8fdf50
--- /dev/null
+++ b/arch/arm/mach-mvebu/Makefile
@@ -0,0 +1,2 @@
+obj-y += system-controller.o
+obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o
diff --git a/arch/arm/mach-mvebu/Makefile.boot b/arch/arm/mach-mvebu/Makefile.boot
new file mode 100644
index 000000000000..2579a2fc2334
--- /dev/null
+++ b/arch/arm/mach-mvebu/Makefile.boot
@@ -0,0 +1,3 @@
+zreladdr-y := 0x00008000
+dtb-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-db.dtb
+dtb-$(CONFIG_MACH_ARMADA_370_XP) += armada-xp-db.dtb
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
new file mode 100644
index 000000000000..4ef923b032ec
--- /dev/null
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -0,0 +1,63 @@
+/*
+ * Device Tree support for Armada 370 and XP platforms.
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/of_platform.h>
+#include <linux/io.h>
+#include <linux/time-armada-370-xp.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+#include <mach/armada-370-xp.h>
+#include "common.h"
+
+static struct map_desc armada_370_xp_io_desc[] __initdata = {
+        {
+                .virtual        = ARMADA_370_XP_REGS_VIRT_BASE,
+                .pfn            = __phys_to_pfn(ARMADA_370_XP_REGS_PHYS_BASE),
+                .length         = ARMADA_370_XP_REGS_SIZE,
+                .type           = MT_DEVICE,
+        },
+};
+
+void __init armada_370_xp_map_io(void)
+{
+        iotable_init(armada_370_xp_io_desc, ARRAY_SIZE(armada_370_xp_io_desc));
+}
+
+struct sys_timer armada_370_xp_timer = {
+        .init           = armada_370_xp_timer_init,
+};
+
+static void __init armada_370_xp_dt_init(void)
+{
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static const char * const armada_370_xp_dt_board_dt_compat[] = {
+        "marvell,a370-db",
+        "marvell,axp-db",
+        NULL,
+};
+
+DT_MACHINE_START(ARMADA_XP_DT, "Marvell Aramada 370/XP (Device Tree)")
+        .init_machine   = armada_370_xp_dt_init,
+        .map_io         = armada_370_xp_map_io,
+        .init_irq       = armada_370_xp_init_irq,
+        .handle_irq     = armada_370_xp_handle_irq,
+        .timer          = &armada_370_xp_timer,
+        .restart        = mvebu_restart,
+        .dt_compat      = armada_370_xp_dt_board_dt_compat,
+MACHINE_END
diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h
new file mode 100644
index 000000000000..02f89eaa25fe
--- /dev/null
+++ b/arch/arm/mach-mvebu/common.h
@@ -0,0 +1,23 @@
+/*
+ * Core functions for Marvell System On Chip
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ARCH_MVEBU_COMMON_H
+#define __ARCH_MVEBU_COMMON_H
+
+void mvebu_restart(char mode, const char *cmd);
+
+void armada_370_xp_init_irq(void);
+void armada_370_xp_handle_irq(struct pt_regs *regs);
+
+#endif
diff --git a/arch/arm/mach-mvebu/include/mach/armada-370-xp.h b/arch/arm/mach-mvebu/include/mach/armada-370-xp.h
new file mode 100644
index 000000000000..25f0ca8d7820
--- /dev/null
+++ b/arch/arm/mach-mvebu/include/mach/armada-370-xp.h
@@ -0,0 +1,22 @@
+/*
+ * Generic definitions for Marvell Armada_370_XP SoCs
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_ARMADA_370_XP_H
+#define __MACH_ARMADA_370_XP_H
+
+#define ARMADA_370_XP_REGS_PHYS_BASE    0xd0000000
+#define ARMADA_370_XP_REGS_VIRT_BASE    0xfeb00000
+#define ARMADA_370_XP_REGS_SIZE         SZ_1M
+
+#endif /* __MACH_ARMADA_370_XP_H */
diff --git a/arch/arm/mach-mvebu/include/mach/debug-macro.S b/arch/arm/mach-mvebu/include/mach/debug-macro.S
new file mode 100644
index 000000000000..22825760c7e1
--- /dev/null
+++ b/arch/arm/mach-mvebu/include/mach/debug-macro.S
@@ -0,0 +1,24 @@
+/*
+ * Early serial output macro for Marvell  SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory Clement <gregory.clement@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <mach/armada-370-xp.h>
+
+        .macro  addruart, rp, rv, tmp
+        ldr     \rp, =ARMADA_370_XP_REGS_PHYS_BASE
+        ldr     \rv, =ARMADA_370_XP_REGS_VIRT_BASE
+        orr     \rp, \rp, #0x00012000
+        orr     \rv, \rv, #0x00012000
+        .endm
+
+#define UART_SHIFT      2
+#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-mvebu/include/mach/timex.h b/arch/arm/mach-mvebu/include/mach/timex.h
new file mode 100644
index 000000000000..ab324a3748f2
--- /dev/null
+++ b/arch/arm/mach-mvebu/include/mach/timex.h
@@ -0,0 +1,13 @@
+/*
+ * Marvell Armada SoC time definitions
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#define CLOCK_TICK_RATE         (100 * HZ)
diff --git a/arch/arm/mach-mvebu/include/mach/uncompress.h b/arch/arm/mach-mvebu/include/mach/uncompress.h
new file mode 100644
index 000000000000..d6a100ccf302
--- /dev/null
+++ b/arch/arm/mach-mvebu/include/mach/uncompress.h
@@ -0,0 +1,43 @@
+/*
+ * Marvell Armada SoC kernel uncompression UART routines
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <mach/armada-370-xp.h>
+
+#define UART_THR ((volatile unsigned char *)(ARMADA_370_XP_REGS_PHYS_BASE\
+                                                                + 0x12000))
+#define UART_LSR ((volatile unsigned char *)(ARMADA_370_XP_REGS_PHYS_BASE\
+                                                                + 0x12014))
+
+#define LSR_THRE        0x20
+
+static void putc(const char c)
+{
+        int i;
+
+        for (i = 0; i < 0x1000; i++) {
+                /* Transmit fifo not full? */
+                if (*UART_LSR & LSR_THRE)
+                        break;
+        }
+
+        *UART_THR = c;
+}
+
+static void flush(void)
+{
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-mvebu/irq-armada-370-xp.c b/arch/arm/mach-mvebu/irq-armada-370-xp.c
new file mode 100644
index 000000000000..5f5f9394b6b2
--- /dev/null
+++ b/arch/arm/mach-mvebu/irq-armada-370-xp.c
@@ -0,0 +1,133 @@
+/*
+ * Marvell Armada 370 and Armada XP SoC IRQ handling
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ * Ben Dooks <ben.dooks@codethink.co.uk>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/irqdomain.h>
+#include <asm/mach/arch.h>
+#include <asm/exception.h>
+
+/* Interrupt Controller Registers Map */
+#define ARMADA_370_XP_INT_SET_MASK_OFFS         (0x48)
+#define ARMADA_370_XP_INT_CLEAR_MASK_OFFS       (0x4C)
+
+#define ARMADA_370_XP_INT_CONTROL               (0x00)
+#define ARMADA_370_XP_INT_SET_ENABLE_OFFS       (0x30)
+#define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS     (0x34)
+
+#define ARMADA_370_XP_CPU_INTACK_OFFS           (0x44)
+
+static void __iomem *per_cpu_int_base;
+static void __iomem *main_int_base;
+static struct irq_domain *armada_370_xp_mpic_domain;
+
+static void armada_370_xp_irq_mask(struct irq_data *d)
+{
+        writel(irqd_to_hwirq(d),
+               per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);
+}
+
+static void armada_370_xp_irq_unmask(struct irq_data *d)
+{
+        writel(irqd_to_hwirq(d),
+               per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
+}
+
+static struct irq_chip armada_370_xp_irq_chip = {
+        .name           = "armada_370_xp_irq",
+        .irq_mask       = armada_370_xp_irq_mask,
+        .irq_mask_ack   = armada_370_xp_irq_mask,
+        .irq_unmask     = armada_370_xp_irq_unmask,
+};
+
+static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
+                                      unsigned int virq, irq_hw_number_t hw)
+{
+        armada_370_xp_irq_mask(irq_get_irq_data(virq));
+        writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
+
+        irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
+                                 handle_level_irq);
+        irq_set_status_flags(virq, IRQ_LEVEL);
+        set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
+
+        return 0;
+}
+
+static struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
+        .map = armada_370_xp_mpic_irq_map,
+        .xlate = irq_domain_xlate_onecell,
+};
+
+static int __init armada_370_xp_mpic_of_init(struct device_node *node,
+                                             struct device_node *parent)
+{
+        u32 control;
+
+        main_int_base = of_iomap(node, 0);
+        per_cpu_int_base = of_iomap(node, 1);
+
+        BUG_ON(!main_int_base);
+        BUG_ON(!per_cpu_int_base);
+
+        control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
+
+        armada_370_xp_mpic_domain =
+            irq_domain_add_linear(node, (control >> 2) & 0x3ff,
+                                  &armada_370_xp_mpic_irq_ops, NULL);
+
+        if (!armada_370_xp_mpic_domain)
+                panic("Unable to add Armada_370_Xp MPIC irq domain (DT)\n");
+
+        irq_set_default_host(armada_370_xp_mpic_domain);
+        return 0;
+}
+
+asmlinkage void __exception_irq_entry armada_370_xp_handle_irq(struct pt_regs
+                                                               *regs)
+{
+        u32 irqstat, irqnr;
+
+        do {
+                irqstat = readl_relaxed(per_cpu_int_base +
+                                        ARMADA_370_XP_CPU_INTACK_OFFS);
+                irqnr = irqstat & 0x3FF;
+
+                if (irqnr < 1023) {
+                        irqnr =
+                            irq_find_mapping(armada_370_xp_mpic_domain, irqnr);
+                        handle_IRQ(irqnr, regs);
+                        continue;
+                }
+
+                break;
+        } while (1);
+}
+
+static const struct of_device_id mpic_of_match[] __initconst = {
+        {.compatible = "marvell,mpic", .data = armada_370_xp_mpic_of_init},
+        {},
+};
+
+void __init armada_370_xp_init_irq(void)
+{
+        of_irq_init(mpic_of_match);
+}
diff --git a/arch/arm/mach-mvebu/system-controller.c b/arch/arm/mach-mvebu/system-controller.c
new file mode 100644
index 000000000000..b8079df8c986
--- /dev/null
+++ b/arch/arm/mach-mvebu/system-controller.c
@@ -0,0 +1,105 @@
+/*
+ * System controller support for Armada 370 and XP platforms.
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * The Armada 370 and Armada XP SoCs both have a range of
+ * miscellaneous registers, that do not belong to a particular device,
+ * but rather provide system-level features. This basic
+ * system-controller driver provides a device tree binding for those
+ * registers, and implements utility functions offering various
+ * features related to those registers.
+ *
+ * For now, the feature set is limited to restarting the platform by a
+ * soft-reset, but it might be extended in the future.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+
+static void __iomem *system_controller_base;
+
+struct mvebu_system_controller {
+        u32 rstoutn_mask_offset;
+        u32 system_soft_reset_offset;
+
+        u32 rstoutn_mask_reset_out_en;
+        u32 system_soft_reset;
+};
+static struct mvebu_system_controller *mvebu_sc;
+
+const struct mvebu_system_controller armada_370_xp_system_controller = {
+        .rstoutn_mask_offset = 0x60,
+        .system_soft_reset_offset = 0x64,
+        .rstoutn_mask_reset_out_en = 0x1,
+        .system_soft_reset = 0x1,
+};
+
+const struct mvebu_system_controller orion_system_controller = {
+        .rstoutn_mask_offset = 0x108,
+        .system_soft_reset_offset = 0x10c,
+        .rstoutn_mask_reset_out_en = 0x4,
+        .system_soft_reset = 0x1,
+};
+
+static struct of_device_id of_system_controller_table[] = {
+        {
+                .compatible = "marvell,orion-system-controller",
+                .data = (void *) &orion_system_controller,
+        }, {
+                .compatible = "marvell,armada-370-xp-system-controller",
+                .data = (void *) &armada_370_xp_system_controller,
+        },
+        { /* end of list */ },
+};
+
+void mvebu_restart(char mode, const char *cmd)
+{
+        if (!system_controller_base) {
+                pr_err("Cannot restart, system-controller not available: check the device tree\n");
+        } else {
+                /*
+                 * Enable soft reset to assert RSTOUTn.
+                 */
+                writel(mvebu_sc->rstoutn_mask_reset_out_en,
+                        system_controller_base +
+                        mvebu_sc->rstoutn_mask_offset);
+                /*
+                 * Assert soft reset.
+                 */
+                writel(mvebu_sc->system_soft_reset,
+                        system_controller_base +
+                        mvebu_sc->system_soft_reset_offset);
+        }
+
+        while (1)
+                ;
+}
+
+static int __init mvebu_system_controller_init(void)
+{
+        struct device_node *np;
+
+        np = of_find_matching_node(NULL, of_system_controller_table);
+        if (np) {
+                const struct of_device_id *match =
+                    of_match_node(of_system_controller_table, np);
+                BUG_ON(!match);
+                system_controller_base = of_iomap(np, 0);
+                mvebu_sc = (struct mvebu_system_controller *)match->data;
+        }
+
+        return 0;
+}
+
+arch_initcall(mvebu_system_controller_init);
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 2776eaacac5e..dd0fbf76ac79 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -9,7 +9,7 @@ config ARCH_OMAP2PLUS_TYPICAL
         select REGULATOR
         select PM_RUNTIME
         select VFP
-        select NEON if ARCH_OMAP3 || ARCH_OMAP4
+        select NEON if ARCH_OMAP3 || ARCH_OMAP4 || SOC_OMAP5
         select SERIAL_OMAP
         select SERIAL_OMAP_CONSOLE
         select I2C
@@ -63,6 +63,12 @@ config ARCH_OMAP4
         select USB_ARCH_HAS_EHCI if USB_SUPPORT
         select ARM_CPU_SUSPEND if PM
 
+config SOC_OMAP5
+        bool "TI OMAP5"
+        select CPU_V7
+        select ARM_GIC
+        select HAVE_SMP
+
 comment "OMAP Core Type"
         depends on ARCH_OMAP2
 
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index bdfd400b4996..b779ddd86faf 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
 obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
 obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
 obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common)
+obj-$(CONFIG_SOC_OMAP5)  += prm44xx.o $(hwmod-common) $(secure-common)
 
 ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)
 obj-y += mcbsp.o
@@ -29,8 +30,10 @@ obj-$(CONFIG_SOC_HAS_OMAP2_SDRC)	+= sdrc.o
 
 obj-$(CONFIG_SMP)                       += omap-smp.o omap-headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)               += omap-hotplug.o
-obj-$(CONFIG_ARCH_OMAP4)                += omap4-common.o omap-wakeupgen.o
-obj-$(CONFIG_ARCH_OMAP4)                += sleep44xx.o
+omap-4-5-common                         =  omap4-common.o omap-wakeupgen.o \
+                                           sleep44xx.o
+obj-$(CONFIG_ARCH_OMAP4)                += $(omap-4-5-common)
+obj-$(CONFIG_SOC_OMAP5)                 += $(omap-4-5-common)
 
 plus_sec := $(call as-instr,.arch_extension sec,+sec)
 AFLAGS_omap-headsmp.o                   :=-Wa,-march=armv7-a$(plus_sec)
@@ -69,6 +72,7 @@ obj-$(CONFIG_ARCH_OMAP2)		+= pm24xx.o
 obj-$(CONFIG_ARCH_OMAP2)                += sleep24xx.o
 obj-$(CONFIG_ARCH_OMAP3)                += pm34xx.o sleep34xx.o
 obj-$(CONFIG_ARCH_OMAP4)                += pm44xx.o omap-mpuss-lowpower.o
+obj-$(CONFIG_SOC_OMAP5)                 += omap-mpuss-lowpower.o
 obj-$(CONFIG_PM_DEBUG)                  += pm-debug.o
 obj-$(CONFIG_OMAP_SMARTREFLEX)          += sr_device.o smartreflex.o
 obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3)   += smartreflex-class3.o
@@ -88,14 +92,16 @@ obj-$(CONFIG_ARCH_OMAP4)                += cpuidle44xx.o
 endif
 
 # PRCM
+omap-prcm-4-5-common                    =  prcm.o cminst44xx.o cm44xx.o \
+                                           prcm_mpu44xx.o prminst44xx.o \
+                                           vc44xx_data.o vp44xx_data.o
 obj-y                                   += prm_common.o
 obj-$(CONFIG_ARCH_OMAP2)                += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
 obj-$(CONFIG_ARCH_OMAP3)                += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
 obj-$(CONFIG_ARCH_OMAP3)                += vc3xxx_data.o vp3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP4)                += prcm.o cminst44xx.o cm44xx.o
-obj-$(CONFIG_ARCH_OMAP4)                += prcm_mpu44xx.o prminst44xx.o
-obj-$(CONFIG_ARCH_OMAP4)                += vc44xx_data.o vp44xx_data.o prm44xx.o
 obj-$(CONFIG_SOC_AM33XX)                += prcm.o prm33xx.o cm33xx.o
+obj-$(CONFIG_ARCH_OMAP4)                += $(omap-prcm-4-5-common) prm44xx.o
+obj-$(CONFIG_SOC_OMAP5)                 += $(omap-prcm-4-5-common)
 
 # OMAP voltage domains
 voltagedomain-common                    := voltage.o vc.o vp.o
@@ -107,6 +113,7 @@ obj-$(CONFIG_ARCH_OMAP4)		+= $(voltagedomain-common)
 obj-$(CONFIG_ARCH_OMAP4)                += voltagedomains44xx_data.o
 obj-$(CONFIG_SOC_AM33XX)                += $(voltagedomain-common)
 obj-$(CONFIG_SOC_AM33XX)                += voltagedomains33xx_data.o
+obj-$(CONFIG_SOC_OMAP5)                 += $(voltagedomain-common)
 
 # OMAP powerdomain framework
 powerdomain-common                      += powerdomain.o powerdomain-common.o
@@ -124,6 +131,8 @@ obj-$(CONFIG_ARCH_OMAP4)		+= powerdomains44xx_data.o
 obj-$(CONFIG_SOC_AM33XX)                += $(powerdomain-common)
 obj-$(CONFIG_SOC_AM33XX)                += powerdomain33xx.o
 obj-$(CONFIG_SOC_AM33XX)                += powerdomains33xx_data.o
+obj-$(CONFIG_SOC_OMAP5)                 += $(powerdomain-common)
+obj-$(CONFIG_SOC_OMAP5)                 += powerdomain44xx.o
 
 # PRCM clockdomain control
 clockdomain-common                      += clockdomain.o
@@ -142,6 +151,8 @@ obj-$(CONFIG_ARCH_OMAP4)		+= clockdomains44xx_data.o
 obj-$(CONFIG_SOC_AM33XX)                += $(clockdomain-common)
 obj-$(CONFIG_SOC_AM33XX)                += clockdomain33xx.o
 obj-$(CONFIG_SOC_AM33XX)                += clockdomains33xx_data.o
+obj-$(CONFIG_SOC_OMAP5)                 += $(clockdomain-common)
+obj-$(CONFIG_SOC_OMAP5)                 += clockdomain44xx.o
 
 # Clock framework
 obj-$(CONFIG_ARCH_OMAP2)                += $(clock-common) clock2xxx.o
@@ -160,6 +171,8 @@ obj-$(CONFIG_ARCH_OMAP3)		+= clkt_iclk.o
 obj-$(CONFIG_ARCH_OMAP4)                += $(clock-common) clock44xx_data.o
 obj-$(CONFIG_ARCH_OMAP4)                += dpll3xxx.o dpll44xx.o
 obj-$(CONFIG_SOC_AM33XX)                += $(clock-common) dpll3xxx.o
+obj-$(CONFIG_SOC_OMAP5)                 += $(clock-common)
+obj-$(CONFIG_SOC_OMAP5)                 += dpll3xxx.o dpll44xx.o
 
 # OMAP2 clock rate set data (old "OPP" data)
 obj-$(CONFIG_SOC_OMAP2420)              += opp2420_data.o
@@ -187,6 +200,7 @@ obj-$(CONFIG_OMAP3_EMU)			+= emu.o
 # L3 interconnect
 obj-$(CONFIG_ARCH_OMAP3)                += omap_l3_smx.o
 obj-$(CONFIG_ARCH_OMAP4)                += omap_l3_noc.o
+obj-$(CONFIG_SOC_OMAP5)                 += omap_l3_noc.o
 
 obj-$(CONFIG_OMAP_MBOX_FWK)             += mailbox_mach.o
 mailbox_mach-objs                       := mailbox.o
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 2f2abfb82d84..6f93a20536ea 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -25,23 +25,12 @@
 #include "common-board-devices.h"
 
 #if !(defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3))
-#define omap_intc_of_init       NULL
+#define intc_of_init    NULL
 #endif
 #ifndef CONFIG_ARCH_OMAP4
 #define gic_of_init             NULL
 #endif
 
-static struct of_device_id irq_match[] __initdata = {
-        { .compatible = "ti,omap2-intc", .data = omap_intc_of_init, },
-        { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
-        { }
-};
-
-static void __init omap_init_irq(void)
-{
-        of_irq_init(irq_match);
-}
-
 static struct of_device_id omap_dt_match_table[] __initdata = {
         { .compatible = "simple-bus", },
         { .compatible = "ti,omap-infra", },
@@ -65,7 +54,7 @@ DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)")
         .reserve        = omap_reserve,
         .map_io         = omap242x_map_io,
         .init_early     = omap2420_init_early,
-        .init_irq       = omap_init_irq,
+        .init_irq       = omap_intc_of_init,
         .handle_irq     = omap2_intc_handle_irq,
         .init_machine   = omap_generic_init,
         .timer          = &omap2_timer,
@@ -84,7 +73,7 @@ DT_MACHINE_START(OMAP243X_DT, "Generic OMAP2430 (Flattened Device Tree)")
         .reserve        = omap_reserve,
         .map_io         = omap243x_map_io,
         .init_early     = omap2430_init_early,
-        .init_irq       = omap_init_irq,
+        .init_irq       = omap_intc_of_init,
         .handle_irq     = omap2_intc_handle_irq,
         .init_machine   = omap_generic_init,
         .timer          = &omap2_timer,
@@ -103,7 +92,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
         .reserve        = omap_reserve,
         .map_io         = omap3_map_io,
         .init_early     = omap3430_init_early,
-        .init_irq       = omap_init_irq,
+        .init_irq       = omap_intc_of_init,
         .handle_irq     = omap3_intc_handle_irq,
         .init_machine   = omap_generic_init,
         .timer          = &omap3_timer,
@@ -122,7 +111,7 @@ DT_MACHINE_START(AM33XX_DT, "Generic AM33XX (Flattened Device Tree)")
         .reserve        = omap_reserve,
         .map_io         = am33xx_map_io,
         .init_early     = am33xx_init_early,
-        .init_irq       = omap_init_irq,
+        .init_irq       = omap_intc_of_init,
         .handle_irq     = omap3_intc_handle_irq,
         .init_machine   = omap_generic_init,
         .timer          = &omap3_am33xx_timer,
@@ -140,7 +129,7 @@ DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
         .reserve        = omap_reserve,
         .map_io         = omap4_map_io,
         .init_early     = omap4430_init_early,
-        .init_irq       = omap_init_irq,
+        .init_irq       = omap_gic_of_init,
         .handle_irq     = gic_handle_irq,
         .init_machine   = omap_generic_init,
         .init_late      = omap4430_init_late,
@@ -149,3 +138,22 @@ DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
         .restart        = omap_prcm_restart,
 MACHINE_END
 #endif
+
+#ifdef CONFIG_SOC_OMAP5
+static const char *omap5_boards_compat[] __initdata = {
+        "ti,omap5",
+        NULL,
+};
+
+DT_MACHINE_START(OMAP5_DT, "Generic OMAP5 (Flattened Device Tree)")
+        .reserve        = omap_reserve,
+        .map_io         = omap5_map_io,
+        .init_early     = omap5_init_early,
+        .init_irq       = omap_gic_of_init,
+        .handle_irq     = gic_handle_irq,
+        .init_machine   = omap_generic_init,
+        .timer          = &omap5_timer,
+        .dt_compat      = omap5_boards_compat,
+        .restart        = omap_prcm_restart,
+MACHINE_END
+#endif
diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
index 73d2a0b9ca04..069f9725b1c3 100644
--- a/arch/arm/mach-omap2/common.c
+++ b/arch/arm/mach-omap2/common.c
@@ -178,3 +178,27 @@ void __init omap4_map_io(void)
 }
 #endif
 
+#if defined(CONFIG_SOC_OMAP5)
+static struct omap_globals omap5_globals = {
+        .class  = OMAP54XX_CLASS,
+        .tap    = OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
+        .ctrl   = OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
+        .ctrl_pad       = OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE),
+        .prm    = OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE),
+        .cm     = OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE),
+        .cm2    = OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE),
+        .prcm_mpu = OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE),
+};
+
+void __init omap2_set_globals_5xxx(void)
+{
+        omap2_set_globals_tap(&omap5_globals);
+        omap2_set_globals_control(&omap5_globals);
+        omap2_set_globals_prcm(&omap5_globals);
+}
+
+void __init omap5_map_io(void)
+{
+        omap5_map_common_io();
+}
+#endif
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 404f172d95a8..1f65b1871c23 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -115,6 +115,14 @@ static inline int omap_mux_late_init(void)
 }
 #endif
 
+#ifdef CONFIG_SOC_OMAP5
+extern void omap5_map_common_io(void);
+#else
+static inline void omap5_map_common_io(void)
+{
+}
+#endif
+
 extern void omap2_init_common_infrastructure(void);
 
 extern struct sys_timer omap2_timer;
@@ -122,6 +130,7 @@ extern struct sys_timer omap3_timer;
 extern struct sys_timer omap3_secure_timer;
 extern struct sys_timer omap3_am33xx_timer;
 extern struct sys_timer omap4_timer;
+extern struct sys_timer omap5_timer;
 
 void omap2420_init_early(void);
 void omap2430_init_early(void);
@@ -134,6 +143,7 @@ void am35xx_init_early(void);
 void ti81xx_init_early(void);
 void am33xx_init_early(void);
 void omap4430_init_early(void);
+void omap5_init_early(void);
 void omap3_init_late(void);     /* Do not use this one */
 void omap4430_init_late(void);
 void omap2420_init_late(void);
@@ -169,6 +179,7 @@ void omap2_set_globals_242x(void);
 void omap2_set_globals_243x(void);
 void omap2_set_globals_3xxx(void);
 void omap2_set_globals_443x(void);
+void omap2_set_globals_5xxx(void);
 void omap2_set_globals_ti81xx(void);
 void omap2_set_globals_am33xx(void);
 
@@ -188,6 +199,7 @@ void omap243x_map_io(void);
 void omap3_map_io(void);
 void am33xx_map_io(void);
 void omap4_map_io(void);
+void omap5_map_io(void);
 void ti81xx_map_io(void);
 void omap_barriers_init(void);
 
@@ -227,6 +239,8 @@ void omap3_intc_prepare_idle(void);
 void omap3_intc_resume_idle(void);
 void omap2_intc_handle_irq(struct pt_regs *regs);
 void omap3_intc_handle_irq(struct pt_regs *regs);
+void omap_intc_of_init(void);
+void omap_gic_of_init(void);
 
 #ifdef CONFIG_CACHE_L2X0
 extern void __iomem *omap4_get_l2cache_base(void);
@@ -234,10 +248,10 @@ extern void __iomem *omap4_get_l2cache_base(void);
 
 struct device_node;
 #ifdef CONFIG_OF
-int __init omap_intc_of_init(struct device_node *node,
+int __init intc_of_init(struct device_node *node,
                              struct device_node *parent);
 #else
-int __init omap_intc_of_init(struct device_node *node,
+int __init intc_of_init(struct device_node *node,
                              struct device_node *parent)
 {
         return 0;
@@ -264,6 +278,7 @@ extern void omap_secondary_startup(void);
 extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
 extern void omap_auxcoreboot_addr(u32 cpu_addr);
 extern u32 omap_read_auxcoreboot0(void);
+extern void omap5_secondary_startup(void);
 #endif
 
 #if defined(CONFIG_SMP) && defined(CONFIG_PM)
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index 295b39047a71..b8cdc8531b60 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -253,6 +253,10 @@
 /* TI81XX CONTROL_DEVCONF register offsets */
 #define TI81XX_CONTROL_DEVICE_ID        (TI81XX_CONTROL_DEVCONF + 0x000)
 
+/* OMAP54XX CONTROL STATUS register */
+#define OMAP5XXX_CONTROL_STATUS                0x134
+#define OMAP5_DEVICETYPE_MASK          (0x7 << 6)
+
 /*
  * REVISIT: This list of registers is not comprehensive - there are more
  * that should be added.
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 527c0046064d..71651e20a43e 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -84,7 +84,7 @@ static int __init omap4_l3_init(void)
          * To avoid code running on other OMAPs in
          * multi-omap builds
          */
-        if (!(cpu_is_omap44xx()))
+        if (!cpu_is_omap44xx() && !soc_is_omap54xx())
                 return -ENODEV;
 
         for (i = 0; i < L3_MODULES; i++) {
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 2286410671e7..b2b5759ab0fe 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -727,7 +727,8 @@ static int __init gpmc_init(void)
                 ck = "gpmc_fck";
                 l = OMAP34XX_GPMC_BASE;
                 gpmc_irq = INT_34XX_GPMC_IRQ;
-        } else if (cpu_is_omap44xx()) {
+        } else if (cpu_is_omap44xx() || soc_is_omap54xx()) {
+                /* Base address and irq number are same for OMAP4/5 */
                 ck = "gpmc_ck";
                 l = OMAP44XX_GPMC_BASE;
                 gpmc_irq = OMAP44XX_IRQ_GPMC;
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 37eb95aaf2f6..40373db649aa 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -50,6 +50,11 @@ int omap_type(void)
                 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
         } else if (cpu_is_omap44xx()) {
                 val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
+        } else if (soc_is_omap54xx()) {
+                val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS);
+                val &= OMAP5_DEVICETYPE_MASK;
+                val >>= 6;
+                goto out;
         } else {
                 pr_err("Cannot detect omap type!\n");
                 goto out;
@@ -100,7 +105,7 @@ static u16 tap_prod_id;
 
 void omap_get_die_id(struct omap_die_id *odi)
 {
-        if (cpu_is_omap44xx()) {
+        if (cpu_is_omap44xx() || soc_is_omap54xx()) {
                 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0);
                 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1);
                 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2);
@@ -513,6 +518,41 @@ void __init omap4xxx_check_revision(void)
                 ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf));
 }
 
+void __init omap5xxx_check_revision(void)
+{
+        u32 idcode;
+        u16 hawkeye;
+        u8 rev;
+
+        idcode = read_tap_reg(OMAP_TAP_IDCODE);
+        hawkeye = (idcode >> 12) & 0xffff;
+        rev = (idcode >> 28) & 0xff;
+        switch (hawkeye) {
+        case 0xb942:
+                switch (rev) {
+                case 0:
+                default:
+                        omap_revision = OMAP5430_REV_ES1_0;
+                }
+                break;
+
+        case 0xb998:
+                switch (rev) {
+                case 0:
+                default:
+                        omap_revision = OMAP5432_REV_ES1_0;
+                }
+                break;
+
+        default:
+                /* Unknown default to latest silicon rev as default*/
+                omap_revision = OMAP5430_REV_ES1_0;
+        }
+
+        pr_info("OMAP%04x ES%d.0\n",
+                        omap_rev() >> 16, ((omap_rev() >> 12) & 0xf));
+}
+
 /*
  * Set up things for map_io and processor detection later on. Gets called
  * pretty much first thing from board init. For multi-omap, this gets
diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S
index d7f844a99a7b..93d10de7129f 100644
--- a/arch/arm/mach-omap2/include/mach/debug-macro.S
+++ b/arch/arm/mach-omap2/include/mach/debug-macro.S
@@ -60,12 +60,12 @@ omap_uart_lsr:	.word	0
                 beq     23f                     @ configure OMAP2UART3
                 cmp     \rp, #OMAP3UART3        @ only on 34xx
                 beq     33f                     @ configure OMAP3UART3
-                cmp     \rp, #OMAP4UART3        @ only on 44xx
-                beq     43f                     @ configure OMAP4UART3
+                cmp     \rp, #OMAP4UART3        @ only on 44xx/54xx
+                beq     43f                     @ configure OMAP4/5UART3
                 cmp     \rp, #OMAP3UART4        @ only on 36xx
                 beq     34f                     @ configure OMAP3UART4
-                cmp     \rp, #OMAP4UART4        @ only on 44xx
-                beq     44f                     @ configure OMAP4UART4
+                cmp     \rp, #OMAP4UART4        @ only on 44xx/54xx
+                beq     44f                     @ configure OMAP4/5UART4
                 cmp     \rp, #TI81XXUART1       @ ti81Xx UART offsets different
                 beq     81f                     @ configure UART1
                 cmp     \rp, #TI81XXUART2       @ ti81Xx UART offsets different
diff --git a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
index 548de90b58c2..b0fd16f5c391 100644
--- a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
+++ b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
@@ -11,15 +11,20 @@
 #ifndef OMAP_ARCH_WAKEUPGEN_H
 #define OMAP_ARCH_WAKEUPGEN_H
 
+/* OMAP4 and OMAP5 has same base address */
+#define OMAP_WKUPGEN_BASE                       0x48281000
+
 #define OMAP_WKG_CONTROL_0                      0x00
 #define OMAP_WKG_ENB_A_0                        0x10
 #define OMAP_WKG_ENB_B_0                        0x14
 #define OMAP_WKG_ENB_C_0                        0x18
 #define OMAP_WKG_ENB_D_0                        0x1c
+#define OMAP_WKG_ENB_E_0                        0x20
 #define OMAP_WKG_ENB_A_1                        0x410
 #define OMAP_WKG_ENB_B_1                        0x414
 #define OMAP_WKG_ENB_C_1                        0x418
 #define OMAP_WKG_ENB_D_1                        0x41c
+#define OMAP_WKG_ENB_E_1                        0x420
 #define OMAP_AUX_CORE_BOOT_0                    0x800
 #define OMAP_AUX_CORE_BOOT_1                    0x804
 #define OMAP_PTMSYNCREQ_MASK                    0xc00
@@ -28,4 +33,6 @@
 #define OMAP_TIMESTAMPCYCLEHI                   0xc0c
 
 extern int __init omap_wakeupgen_init(void);
+extern void __iomem *omap_get_wakeupgen_base(void);
+extern int omap_secure_apis_support(void);
 #endif
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index cb6c11cd8df9..8976be90c8e8 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -233,6 +233,35 @@ static struct map_desc omap44xx_io_desc[] __initdata = {
 };
 #endif
 
+#ifdef  CONFIG_SOC_OMAP5
+static struct map_desc omap54xx_io_desc[] __initdata = {
+        {
+                .virtual        = L3_54XX_VIRT,
+                .pfn            = __phys_to_pfn(L3_54XX_PHYS),
+                .length         = L3_54XX_SIZE,
+                .type           = MT_DEVICE,
+        },
+        {
+                .virtual        = L4_54XX_VIRT,
+                .pfn            = __phys_to_pfn(L4_54XX_PHYS),
+                .length         = L4_54XX_SIZE,
+                .type           = MT_DEVICE,
+        },
+        {
+                .virtual        = L4_WK_54XX_VIRT,
+                .pfn            = __phys_to_pfn(L4_WK_54XX_PHYS),
+                .length         = L4_WK_54XX_SIZE,
+                .type           = MT_DEVICE,
+        },
+        {
+                .virtual        = L4_PER_54XX_VIRT,
+                .pfn            = __phys_to_pfn(L4_PER_54XX_PHYS),
+                .length         = L4_PER_54XX_SIZE,
+                .type           = MT_DEVICE,
+        },
+};
+#endif
+
 #ifdef CONFIG_SOC_OMAP2420
 void __init omap242x_map_common_io(void)
 {
@@ -278,6 +307,12 @@ void __init omap44xx_map_common_io(void)
 }
 #endif
 
+#ifdef CONFIG_SOC_OMAP5
+void __init omap5_map_common_io(void)
+{
+        iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
+}
+#endif
 /*
  * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
  *
@@ -513,6 +548,15 @@ void __init omap4430_init_late(void)
 }
 #endif
 
+#ifdef CONFIG_SOC_OMAP5
+void __init omap5_init_early(void)
+{
+        omap2_set_globals_5xxx();
+        omap5xxx_check_revision();
+        omap_common_init_early();
+}
+#endif
+
 void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
                                       struct omap_sdrc_params *sdrc_cs1)
 {
diff --git a/arch/arm/mach-omap2/iomap.h b/arch/arm/mach-omap2/iomap.h
index 80b88921faba..cce2b65039f1 100644
--- a/arch/arm/mach-omap2/iomap.h
+++ b/arch/arm/mach-omap2/iomap.h
@@ -1,6 +1,14 @@
 /*
  * IO mappings for OMAP2+
  *
+ * IO definitions for TI OMAP processors and boards
+ *
+ * Copied from arch/arm/mach-sa1100/include/mach/io.h
+ * Copyright (C) 1997-1999 Russell King
+ *
+ * Copyright (C) 2009-2012 Texas Instruments
+ * Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms of the GNU General Public License as published by the
  * Free Software Foundation; either version 2 of the License, or (at your
@@ -166,4 +174,23 @@
                                                 /* 0x49000000 --> 0xfb000000 */
 #define L4_ABE_44XX_VIRT        (L4_ABE_44XX_PHYS + OMAP2_L4_IO_OFFSET)
 #define L4_ABE_44XX_SIZE        SZ_1M
+/*
+ * ----------------------------------------------------------------------------
+ * Omap5 specific IO mapping
+ * ----------------------------------------------------------------------------
+ */
+#define L3_54XX_PHYS            L3_54XX_BASE    /* 0x44000000 --> 0xf8000000 */
+#define L3_54XX_VIRT            (L3_54XX_PHYS + OMAP4_L3_IO_OFFSET)
+#define L3_54XX_SIZE            SZ_1M
+
+#define L4_54XX_PHYS            L4_54XX_BASE    /* 0x4a000000 --> 0xfc000000 */
+#define L4_54XX_VIRT            (L4_54XX_PHYS + OMAP2_L4_IO_OFFSET)
+#define L4_54XX_SIZE            SZ_4M
+
+#define L4_WK_54XX_PHYS         L4_WK_54XX_BASE /* 0x4ae00000 --> 0xfce00000 */
+#define L4_WK_54XX_VIRT         (L4_WK_54XX_PHYS + OMAP2_L4_IO_OFFSET)
+#define L4_WK_54XX_SIZE         SZ_2M
 
+#define L4_PER_54XX_PHYS        L4_PER_54XX_BASE /* 0x48000000 --> 0xfa000000 */
+#define L4_PER_54XX_VIRT        (L4_PER_54XX_PHYS + OMAP2_L4_IO_OFFSET)
+#define L4_PER_54XX_SIZE        SZ_4M
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index a9c26b12cad2..bcd83db41bbc 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -21,6 +21,7 @@
 #include <linux/irqdomain.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/of_irq.h>
 
 #include <mach/hardware.h>
 
@@ -258,7 +259,7 @@ asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs
         omap_intc_handle_irq(base_addr, regs);
 }
 
-int __init omap_intc_of_init(struct device_node *node,
+int __init intc_of_init(struct device_node *node,
                              struct device_node *parent)
 {
         struct resource res;
@@ -280,6 +281,16 @@ int __init omap_intc_of_init(struct device_node *node,
         return 0;
 }
 
+static struct of_device_id irq_match[] __initdata = {
+        { .compatible = "ti,omap2-intc", .data = intc_of_init, },
+        { }
+};
+
+void __init omap_intc_of_init(void)
+{
+        of_irq_init(irq_match);
+}
+
 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX)
 static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
 
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S
index 503ac777a2ba..502e3135aad3 100644
--- a/arch/arm/mach-omap2/omap-headsmp.S
+++ b/arch/arm/mach-omap2/omap-headsmp.S
@@ -19,6 +19,27 @@
 #include <linux/init.h>
 
         __CPUINIT
+
+/* Physical address needed since MMU not enabled yet on secondary core */
+#define AUX_CORE_BOOT0_PA                       0x48281800
+
+/*
+ * OMAP5 specific entry point for secondary CPU to jump from ROM
+ * code.  This routine also provides a holding flag into which
+ * secondary core is held until we're ready for it to initialise.
+ * The primary core will update this flag using a hardware
++ * register AuxCoreBoot0.
+ */
+ENTRY(omap5_secondary_startup)
+wait:   ldr     r2, =AUX_CORE_BOOT0_PA  @ read from AuxCoreBoot0
+        ldr     r0, [r2]
+        mov     r0, r0, lsr #5
+        mrc     p15, 0, r4, c0, c0, 5
+        and     r4, r4, #0x0f
+        cmp     r0, r4
+        bne     wait
+        b       secondary_startup
+END(omap5_secondary_startup)
 /*
  * OMAP4 specific entry point for secondary CPU to jump from ROM
  * code.  This routine also provides a holding flag into which
diff --git a/arch/arm/mach-omap2/omap-hotplug.c b/arch/arm/mach-omap2/omap-hotplug.c
index 56c345b8b931..414083b427df 100644
--- a/arch/arm/mach-omap2/omap-hotplug.c
+++ b/arch/arm/mach-omap2/omap-hotplug.c
@@ -17,8 +17,10 @@
 #include <linux/kernel.h>
 #include <linux/errno.h>
 #include <linux/smp.h>
+#include <linux/io.h>
 
 #include <asm/cacheflush.h>
+#include <mach/omap-wakeupgen.h>
 
 #include "common.h"
 
@@ -35,7 +37,8 @@ int platform_cpu_kill(unsigned int cpu)
  */
 void __ref platform_cpu_die(unsigned int cpu)
 {
-        unsigned int this_cpu;
+        unsigned int boot_cpu = 0;
+        void __iomem *base = omap_get_wakeupgen_base();
 
         flush_cache_all();
         dsb();
@@ -43,16 +46,27 @@ void __ref platform_cpu_die(unsigned int cpu)
         /*
          * we're ready for shutdown now, so do it
          */
-        if (omap_modify_auxcoreboot0(0x0, 0x200) != 0x0)
-                pr_err("Secure clear status failed\n");
+        if (omap_secure_apis_support()) {
+                if (omap_modify_auxcoreboot0(0x0, 0x200) != 0x0)
+                        pr_err("Secure clear status failed\n");
+        } else {
+                __raw_writel(0, base + OMAP_AUX_CORE_BOOT_0);
+        }
+
 
         for (;;) {
                 /*
                  * Enter into low power state
                  */
                 omap4_hotplug_cpu(cpu, PWRDM_POWER_OFF);
-                this_cpu = smp_processor_id();
-                if (omap_read_auxcoreboot0() == this_cpu) {
+
+                if (omap_secure_apis_support())
+                        boot_cpu = omap_read_auxcoreboot0();
+                else
+                        boot_cpu =
+                                __raw_readl(base + OMAP_AUX_CORE_BOOT_0) >> 5;
+
+                if (boot_cpu == smp_processor_id()) {
                         /*
                          * OK, proper wakeup, we're done
                          */
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index deffbf1c9627..7d118b9bdd5f 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -26,11 +26,19 @@
 
 #include <mach/hardware.h>
 #include <mach/omap-secure.h>
+#include <mach/omap-wakeupgen.h>
+#include <asm/cputype.h>
 
 #include "iomap.h"
 #include "common.h"
 #include "clockdomain.h"
 
+#define CPU_MASK                0xff0ffff0
+#define CPU_CORTEX_A9           0x410FC090
+#define CPU_CORTEX_A15          0x410FC0F0
+
+#define OMAP5_CORE_COUNT        0x2
+
 /* SCU base address */
 static void __iomem *scu_base;
 
@@ -73,6 +81,8 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
         static struct clockdomain *cpu1_clkdm;
         static bool booted;
+        void __iomem *base = omap_get_wakeupgen_base();
+
         /*
          * Set synchronisation state between this boot processor
          * and the secondary one
@@ -85,7 +95,11 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
          * the AuxCoreBoot1 register is updated with cpu state
          * A barrier is added to ensure that write buffer is drained
          */
-        omap_modify_auxcoreboot0(0x200, 0xfffffdff);
+        if (omap_secure_apis_support())
+                omap_modify_auxcoreboot0(0x200, 0xfffffdff);
+        else
+                __raw_writel(0x20, base + OMAP_AUX_CORE_BOOT_0);
+
         flush_cache_all();
         smp_wmb();
 
@@ -124,13 +138,19 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 
 static void __init wakeup_secondary(void)
 {
+        void __iomem *base = omap_get_wakeupgen_base();
         /*
          * Write the address of secondary startup routine into the
          * AuxCoreBoot1 where ROM code will jump and start executing
          * on secondary core once out of WFE
          * A barrier is added to ensure that write buffer is drained
          */
-        omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup));
+        if (omap_secure_apis_support())
+                omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup));
+        else
+                __raw_writel(virt_to_phys(omap5_secondary_startup),
+                                                base + OMAP_AUX_CORE_BOOT_1);
+
         smp_wmb();
 
         /*
@@ -147,16 +167,21 @@ static void __init wakeup_secondary(void)
  */
 void __init smp_init_cpus(void)
 {
-        unsigned int i, ncores;
-
-        /*
-         * Currently we can't call ioremap here because
-         * SoC detection won't work until after init_early.
-         */
-        scu_base =  OMAP2_L4_IO_ADDRESS(OMAP44XX_SCU_BASE);
-        BUG_ON(!scu_base);
-
-        ncores = scu_get_core_count(scu_base);
+        unsigned int i = 0, ncores = 1, cpu_id;
+
+        /* Use ARM cpuid check here, as SoC detection will not work so early */
+        cpu_id = read_cpuid(CPUID_ID) & CPU_MASK;
+        if (cpu_id == CPU_CORTEX_A9) {
+                /*
+                 * Currently we can't call ioremap here because
+                 * SoC detection won't work until after init_early.
+                 */
+                scu_base =  OMAP2_L4_IO_ADDRESS(OMAP44XX_SCU_BASE);
+                BUG_ON(!scu_base);
+                ncores = scu_get_core_count(scu_base);
+        } else if (cpu_id == CPU_CORTEX_A15) {
+                ncores = OMAP5_CORE_COUNT;
+        }
 
         /* sanity check */
         if (ncores > nr_cpu_ids) {
@@ -178,6 +203,7 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
          * Initialise the SCU and wake up the secondary core using
          * wakeup_secondary().
          */
-        scu_enable(scu_base);
+        if (scu_base)
+                scu_enable(scu_base);
         wakeup_secondary();
 }
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
index d811c7790350..05fdebfaa195 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.c
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -33,18 +33,23 @@
 #include "omap4-sar-layout.h"
 #include "common.h"
 
-#define NR_REG_BANKS            4
-#define MAX_IRQS                128
+#define MAX_NR_REG_BANKS        5
+#define MAX_IRQS                160
 #define WKG_MASK_ALL            0x00000000
 #define WKG_UNMASK_ALL          0xffffffff
 #define CPU_ENA_OFFSET          0x400
 #define CPU0_ID                 0x0
 #define CPU1_ID                 0x1
+#define OMAP4_NR_BANKS          4
+#define OMAP4_NR_IRQS           128
 
 static void __iomem *wakeupgen_base;
 static void __iomem *sar_base;
 static DEFINE_SPINLOCK(wakeupgen_lock);
 static unsigned int irq_target_cpu[NR_IRQS];
+static unsigned int irq_banks = MAX_NR_REG_BANKS;
+static unsigned int max_irqs = MAX_IRQS;
+static unsigned int omap_secure_apis;
 
 /*
  * Static helper functions.
@@ -146,13 +151,13 @@ static void wakeupgen_unmask(struct irq_data *d)
 }
 
 #ifdef CONFIG_HOTPLUG_CPU
-static DEFINE_PER_CPU(u32 [NR_REG_BANKS], irqmasks);
+static DEFINE_PER_CPU(u32 [MAX_NR_REG_BANKS], irqmasks);
 
 static void _wakeupgen_save_masks(unsigned int cpu)
 {
         u8 i;
 
-        for (i = 0; i < NR_REG_BANKS; i++)
+        for (i = 0; i < irq_banks; i++)
                 per_cpu(irqmasks, cpu)[i] = wakeupgen_readl(i, cpu);
 }
 
@@ -160,7 +165,7 @@ static void _wakeupgen_restore_masks(unsigned int cpu)
 {
         u8 i;
 
-        for (i = 0; i < NR_REG_BANKS; i++)
+        for (i = 0; i < irq_banks; i++)
                 wakeupgen_writel(per_cpu(irqmasks, cpu)[i], i, cpu);
 }
 
@@ -168,7 +173,7 @@ static void _wakeupgen_set_all(unsigned int cpu, unsigned int reg)
 {
         u8 i;
 
-        for (i = 0; i < NR_REG_BANKS; i++)
+        for (i = 0; i < irq_banks; i++)
                 wakeupgen_writel(reg, i, cpu);
 }
 
@@ -196,25 +201,14 @@ static void wakeupgen_irqmask_all(unsigned int cpu, unsigned int set)
 #endif
 
 #ifdef CONFIG_CPU_PM
-/*
- * Save WakeupGen interrupt context in SAR BANK3. Restore is done by
- * ROM code. WakeupGen IP is integrated along with GIC to manage the
- * interrupt wakeups from CPU low power states. It manages
- * masking/unmasking of Shared peripheral interrupts(SPI). So the
- * interrupt enable/disable control should be in sync and consistent
- * at WakeupGen and GIC so that interrupts are not lost.
- */
-static void irq_save_context(void)
+static inline void omap4_irq_save_context(void)
 {
         u32 i, val;
 
         if (omap_rev() == OMAP4430_REV_ES1_0)
                 return;
 
-        if (!sar_base)
-                sar_base = omap4_get_sar_ram_base();
-
-        for (i = 0; i < NR_REG_BANKS; i++) {
+        for (i = 0; i < irq_banks; i++) {
                 /* Save the CPUx interrupt mask for IRQ 0 to 127 */
                 val = wakeupgen_readl(i, 0);
                 sar_writel(val, WAKEUPGENENB_OFFSET_CPU0, i);
@@ -254,6 +248,53 @@ static void irq_save_context(void)
         val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET);
         val |= SAR_BACKUP_STATUS_WAKEUPGEN;
         __raw_writel(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
+
+}
+
+static inline void omap5_irq_save_context(void)
+{
+        u32 i, val;
+
+        for (i = 0; i < irq_banks; i++) {
+                /* Save the CPUx interrupt mask for IRQ 0 to 159 */
+                val = wakeupgen_readl(i, 0);
+                sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU0, i);
+                val = wakeupgen_readl(i, 1);
+                sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU1, i);
+                sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0, i);
+                sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1, i);
+        }
+
+        /* Save AuxBoot* registers */
+        val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
+        __raw_writel(val, sar_base + OMAP5_AUXCOREBOOT0_OFFSET);
+        val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
+        __raw_writel(val, sar_base + OMAP5_AUXCOREBOOT1_OFFSET);
+
+        /* Set the Backup Bit Mask status */
+        val = __raw_readl(sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
+        val |= SAR_BACKUP_STATUS_WAKEUPGEN;
+        __raw_writel(val, sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
+
+}
+
+/*
+ * Save WakeupGen interrupt context in SAR BANK3. Restore is done by
+ * ROM code. WakeupGen IP is integrated along with GIC to manage the
+ * interrupt wakeups from CPU low power states. It manages
+ * masking/unmasking of Shared peripheral interrupts(SPI). So the
+ * interrupt enable/disable control should be in sync and consistent
+ * at WakeupGen and GIC so that interrupts are not lost.
+ */
+static void irq_save_context(void)
+{
+        if (!sar_base)
+                sar_base = omap4_get_sar_ram_base();
+
+        if (soc_is_omap54xx())
+                omap5_irq_save_context();
+        else
+                omap4_irq_save_context();
 }
 
 /*
@@ -262,9 +303,14 @@ static void irq_save_context(void)
 static void irq_sar_clear(void)
 {
         u32 val;
-        val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET);
+        u32 offset = SAR_BACKUP_STATUS_OFFSET;
+
+        if (soc_is_omap54xx())
+                offset = OMAP5_SAR_BACKUP_STATUS_OFFSET;
+
+        val = __raw_readl(sar_base + offset);
         val &= ~SAR_BACKUP_STATUS_WAKEUPGEN;
-        __raw_writel(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
+        __raw_writel(val, sar_base + offset);
 }
 
 /*
@@ -336,13 +382,25 @@ static struct notifier_block irq_notifier_block = {
 
 static void __init irq_pm_init(void)
 {
-        cpu_pm_register_notifier(&irq_notifier_block);
+        /* FIXME: Remove this when MPU OSWR support is added */
+        if (!soc_is_omap54xx())
+                cpu_pm_register_notifier(&irq_notifier_block);
 }
 #else
 static void __init irq_pm_init(void)
 {}
 #endif
 
+void __iomem *omap_get_wakeupgen_base(void)
+{
+        return wakeupgen_base;
+}
+
+int omap_secure_apis_support(void)
+{
+        return omap_secure_apis;
+}
+
 /*
  * Initialise the wakeupgen module.
  */
@@ -358,12 +416,18 @@ int __init omap_wakeupgen_init(void)
         }
 
         /* Static mapping, never released */
-        wakeupgen_base = ioremap(OMAP44XX_WKUPGEN_BASE, SZ_4K);
+        wakeupgen_base = ioremap(OMAP_WKUPGEN_BASE, SZ_4K);
         if (WARN_ON(!wakeupgen_base))
                 return -ENOMEM;
 
+        if (cpu_is_omap44xx()) {
+                irq_banks = OMAP4_NR_BANKS;
+                max_irqs = OMAP4_NR_IRQS;
+                omap_secure_apis = 1;
+        }
+
         /* Clear all IRQ bitmasks at wakeupGen level */
-        for (i = 0; i < NR_REG_BANKS; i++) {
+        for (i = 0; i < irq_banks; i++) {
                 wakeupgen_writel(0, i, CPU0_ID);
                 wakeupgen_writel(0, i, CPU1_ID);
         }
@@ -382,7 +446,7 @@ int __init omap_wakeupgen_init(void)
          */
 
         /* Associate all the IRQs to boot CPU like GIC init does. */
-        for (i = 0; i < NR_IRQS; i++)
+        for (i = 0; i < max_irqs; i++)
                 irq_target_cpu[i] = boot_cpu;
 
         irq_hotplug_init();
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index a8161e5f3204..c29dee998a79 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -21,6 +21,8 @@
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/map.h>
 #include <asm/memblock.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
 
 #include <plat/irqs.h>
 #include <plat/sram.h>
@@ -210,6 +212,18 @@ static int __init omap4_sar_ram_init(void)
 }
 early_initcall(omap4_sar_ram_init);
 
+static struct of_device_id irq_match[] __initdata = {
+        { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
+        { .compatible = "arm,cortex-a15-gic", .data = gic_of_init, },
+        { }
+};
+
+void __init omap_gic_of_init(void)
+{
+        omap_wakeupgen_init();
+        of_irq_init(irq_match);
+}
+
 #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
 static int omap4_twl6030_hsmmc_late_init(struct device *dev)
 {
diff --git a/arch/arm/mach-omap2/omap4-sar-layout.h b/arch/arm/mach-omap2/omap4-sar-layout.h
index fe5b545ad443..e170fe803b04 100644
--- a/arch/arm/mach-omap2/omap4-sar-layout.h
+++ b/arch/arm/mach-omap2/omap4-sar-layout.h
@@ -12,7 +12,7 @@
 #define OMAP_ARCH_OMAP4_SAR_LAYOUT_H
 
 /*
- * SAR BANK offsets from base address OMAP44XX_SAR_RAM_BASE
+ * SAR BANK offsets from base address OMAP44XX/54XX_SAR_RAM_BASE
  */
 #define SAR_BANK1_OFFSET                0x0000
 #define SAR_BANK2_OFFSET                0x1000
@@ -47,4 +47,14 @@
 #define PTMSYNCREQ_EN_OFFSET                    (SAR_BANK3_OFFSET + 0x6d0)
 #define SAR_BACKUP_STATUS_WAKEUPGEN             0x10
 
+/* WakeUpGen save restore offset from OMAP54XX_SAR_RAM_BASE */
+#define OMAP5_WAKEUPGENENB_OFFSET_CPU0          (SAR_BANK3_OFFSET + 0x8d4)
+#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0   (SAR_BANK3_OFFSET + 0x8e8)
+#define OMAP5_WAKEUPGENENB_OFFSET_CPU1          (SAR_BANK3_OFFSET + 0x8fc)
+#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1   (SAR_BANK3_OFFSET + 0x910)
+#define OMAP5_AUXCOREBOOT0_OFFSET               (SAR_BANK3_OFFSET + 0x924)
+#define OMAP5_AUXCOREBOOT1_OFFSET               (SAR_BANK3_OFFSET + 0x928)
+#define OMAP5_AMBA_IF_MODE_OFFSET               (SAR_BANK3_OFFSET + 0x92c)
+#define OMAP5_SAR_BACKUP_STATUS_OFFSET          (SAR_BANK3_OFFSET + 0x800)
+
 #endif
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 5d82bfca38c3..3f21568f1753 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -3635,7 +3635,7 @@ void __init omap_hwmod_init(void)
                 soc_ops.assert_hardreset = _omap2_assert_hardreset;
                 soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
                 soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted;
-        } else if (cpu_is_omap44xx()) {
+        } else if (cpu_is_omap44xx() || soc_is_omap54xx()) {
                 soc_ops.enable_module = _omap4_enable_module;
                 soc_ops.disable_module = _omap4_disable_module;
                 soc_ops.wait_target_ready = _omap4_wait_target_ready;
diff --git a/arch/arm/mach-omap2/omap_l3_noc.h b/arch/arm/mach-omap2/omap_l3_noc.h
index 90b50984cd2e..a6ce34dc4814 100644
--- a/arch/arm/mach-omap2/omap_l3_noc.h
+++ b/arch/arm/mach-omap2/omap_l3_noc.h
@@ -51,7 +51,9 @@ static u32 l3_targ_inst_clk1[] = {
         0x200, /* DMM2 */
         0x300, /* ABE */
         0x400, /* L4CFG */
-        0x600  /* CLK2 PWR DISC */
+        0x600,  /* CLK2 PWR DISC */
+        0x0,    /* Host CLK1 */
+        0x900   /* L4 Wakeup */
 };
 
 static u32 l3_targ_inst_clk2[] = {
@@ -72,11 +74,16 @@ static u32 l3_targ_inst_clk2[] = {
         0xE00, /* missing in TRM corresponds to AES2*/
         0xC00, /* L4 PER3 */
         0xA00, /* L4 PER1*/
-        0xB00 /* L4 PER2*/
+        0xB00, /* L4 PER2*/
+        0x0, /* HOST CLK2 */
+        0x1800, /* CAL */
+        0x1700 /* LLI */
 };
 
 static u32 l3_targ_inst_clk3[] = {
-        0x0100  /* EMUSS */
+        0x0100  /* EMUSS */,
+        0x0300, /* DEBUGSS_CT_TBR */
+        0x0 /* HOST CLK3 */
 };
 
 static struct l3_masters_data {
@@ -110,13 +117,15 @@ static struct l3_masters_data {
         { 0xC8, "USBHOSTFS"}
 };
 
-static char *l3_targ_inst_name[L3_MODULES][18] = {
+static char *l3_targ_inst_name[L3_MODULES][21] = {
         {
                 "DMM1",
                 "DMM2",
                 "ABE",
                 "L4CFG",
                 "CLK2 PWR DISC",
+                "HOST CLK1",
+                "L4 WAKEUP"
         },
         {
                 "CORTEX M3" ,
@@ -137,9 +146,14 @@ static char *l3_targ_inst_name[L3_MODULES][18] = {
                 "L4 PER3",
                 "L4 PER1",
                 "L4 PER2",
+                "HOST CLK2",
+                "CAL",
+                "LLI"
         },
         {
                 "EMUSS",
+                "DEBUG SOURCE",
+                "HOST CLK3"
         },
 };
 
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index cc1398e8b469..d5ae4e234bbc 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -416,7 +416,7 @@ extern void __iomem *cm_base;
 extern void __iomem *cm2_base;
 extern void __iomem *prcm_mpu_base;
 
-#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_OMAP5)
+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
 extern void omap_prm_base_init(void);
 extern void omap_cm_base_init(void);
 #else
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 28cbfb2b5733..053e24ed3c48 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -160,7 +160,7 @@ void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
         if (omap2_globals->prcm_mpu)
                 prcm_mpu_base = omap2_globals->prcm_mpu;
 
-        if (cpu_is_omap44xx()) {
+        if (cpu_is_omap44xx() || soc_is_omap54xx()) {
                 omap_prm_base_init();
                 omap_cm_base_init();
         }
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 2b318ec92d39..13d20c8a283d 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -393,6 +393,11 @@ static void __init omap4_timer_init(void)
 OMAP_SYS_TIMER(4)
 #endif
 
+#ifdef CONFIG_SOC_OMAP5
+OMAP_SYS_TIMER_INIT(5, 1, OMAP4_CLKEV_SOURCE, 2, OMAP4_MPU_SOURCE)
+OMAP_SYS_TIMER(5)
+#endif
+
 /**
  * omap_timer_init - build and register timer device with an
  * associated timer hwmod
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
new file mode 100644
index 000000000000..4fb93240971d
--- /dev/null
+++ b/arch/arm/mach-socfpga/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for the linux kernel.
+#
+
+obj-y                                   := socfpga.o
diff --git a/arch/arm/mach-socfpga/Makefile.boot b/arch/arm/mach-socfpga/Makefile.boot
new file mode 100644
index 000000000000..dae9661a7689
--- /dev/null
+++ b/arch/arm/mach-socfpga/Makefile.boot
@@ -0,0 +1 @@
+zreladdr-y      := 0x00008000
diff --git a/arch/arm/mach-socfpga/include/mach/debug-macro.S b/arch/arm/mach-socfpga/include/mach/debug-macro.S
new file mode 100644
index 000000000000..d6f26d23374f
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/debug-macro.S
@@ -0,0 +1,16 @@
+/*
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+                .macro  addruart, rp, rv, tmp
+                mov     \rp, #DEBUG_LL_UART_OFFSET
+                orr     \rp, \rp, #0x00c00000
+                orr     \rv, \rp, #0xfe000000   @ virtual base
+                orr     \rp, \rp, #0xff000000   @ physical base
+                .endm
+
diff --git a/arch/arm/mach-socfpga/include/mach/timex.h b/arch/arm/mach-socfpga/include/mach/timex.h
new file mode 100644
index 000000000000..43df4354e461
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/timex.h
@@ -0,0 +1,19 @@
+/*
+ *  Copyright (C) 2003 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#define CLOCK_TICK_RATE         (50000000 / 16)
diff --git a/arch/arm/mach-socfpga/include/mach/uncompress.h b/arch/arm/mach-socfpga/include/mach/uncompress.h
new file mode 100644
index 000000000000..bbe20e696325
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/uncompress.h
@@ -0,0 +1,9 @@
+#ifndef __MACH_UNCOMPRESS_H
+#define __MACH_UNCOMPRESS_H
+
+#define putc(c)
+#define flush()
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
+
+#endif
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
new file mode 100644
index 000000000000..f01e1ebf5396
--- /dev/null
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -0,0 +1,62 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/dw_apb_timer.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/hardware/gic.h>
+#include <asm/mach/arch.h>
+
+extern void socfpga_init_clocks(void);
+
+const static struct of_device_id irq_match[] = {
+        { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
+        {}
+};
+
+static void __init gic_init_irq(void)
+{
+        of_irq_init(irq_match);
+}
+
+static void socfpga_cyclone5_restart(char mode, const char *cmd)
+{
+        /* TODO: */
+}
+
+static void __init socfpga_cyclone5_init(void)
+{
+        l2x0_of_init(0, ~0UL);
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+        socfpga_init_clocks();
+}
+
+static const char *altera_dt_match[] = {
+        "altr,socfpga",
+        "altr,socfpga-cyclone5",
+        NULL
+};
+
+DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
+        .init_irq       = gic_init_irq,
+        .handle_irq     = gic_handle_irq,
+        .timer          = &dw_apb_timer,
+        .init_machine   = socfpga_cyclone5_init,
+        .restart        = socfpga_cyclone5_restart,
+        .dt_compat      = altera_dt_match,
+MACHINE_END
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index ad95c7a5d009..dcfb506a592e 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -29,7 +29,7 @@ config ARCH_OMAP2PLUS
         select USE_OF
         select PROC_DEVICETREE if PROC_FS
         help
-          "Systems based on OMAP2, OMAP3 or OMAP4"
+          "Systems based on OMAP2, OMAP3, OMAP4 or OMAP5"
 
 endchoice
 
@@ -150,7 +150,7 @@ config OMAP_32K_TIMER
           This timer saves power compared to the OMAP_MPU_TIMER, and has
           support for no tick during idle. The 32KHz timer provides less
           intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is
-          currently only available for OMAP16XX, 24XX, 34XX and OMAP4.
+          currently only available for OMAP16XX, 24XX, 34XX and OMAP4/5.
 
 config OMAP3_L2_AUX_SECURE_SAVE_RESTORE
         bool "OMAP3 HS/EMU save and restore for L2 AUX control register"
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index 0a9b9a970113..89a3723b3538 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -77,3 +77,12 @@ void __init omap_init_consistent_dma_size(void)
         init_consistent_dma_size(CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE << 20);
 #endif
 }
+
+/*
+ * Stub function for OMAP2 so that common files
+ * continue to build when custom builds are used
+ */
+int __weak omap_secure_ram_reserve_memblock(void)
+{
+        return 0;
+}
diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
index 2132c4f389e1..dbf1e03029a5 100644
--- a/arch/arm/plat-omap/counter_32k.c
+++ b/arch/arm/plat-omap/counter_32k.c
@@ -29,7 +29,10 @@
 #include <plat/clock.h>
 
 /* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */
-#define OMAP2_32KSYNCNT_CR_OFF          0x10
+#define OMAP2_32KSYNCNT_REV_OFF         0x0
+#define OMAP2_32KSYNCNT_REV_SCHEME      (0x3 << 30)
+#define OMAP2_32KSYNCNT_CR_OFF_LOW      0x10
+#define OMAP2_32KSYNCNT_CR_OFF_HIGH     0x30
 
 /*
  * 32KHz clocksource ... always available, on pretty most chips except
@@ -84,9 +87,16 @@ int __init omap_init_clocksource_32k(void __iomem *vbase)
         int ret;
 
         /*
-         * 32k sync Counter register offset is at 0x10
+         * 32k sync Counter IP register offsets vary between the
+         * highlander version and the legacy ones.
+         * The 'SCHEME' bits(30-31) of the revision register is used
+         * to identify the version.
          */
-        sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF;
+        if (__raw_readl(vbase + OMAP2_32KSYNCNT_REV_OFF) &
+                                                OMAP2_32KSYNCNT_REV_SCHEME)
+                sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_HIGH;
+        else
+                sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_LOW;
 
         /*
          * 120000 rough estimate from the calculations in
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index f91e0b99b30c..68b180edcfff 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -9,7 +9,7 @@
  *
  * Written by Tony Lindgren <tony.lindgren@nokia.com>
  *
- * Added OMAP4 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com>
+ * Added OMAP4/5 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -70,6 +70,7 @@ unsigned int omap_rev(void);
  * cpu_is_omap443x():   True for OMAP4430
  * cpu_is_omap446x():   True for OMAP4460
  * cpu_is_omap447x():   True for OMAP4470
+ * soc_is_omap543x():   True for OMAP5430, OMAP5432
  */
 #define GET_OMAP_CLASS  (omap_rev() & 0xff)
 
@@ -122,6 +123,7 @@ IS_OMAP_CLASS(24xx, 0x24)
 IS_OMAP_CLASS(34xx, 0x34)
 IS_OMAP_CLASS(44xx, 0x44)
 IS_AM_CLASS(35xx, 0x35)
+IS_OMAP_CLASS(54xx, 0x54)
 IS_AM_CLASS(33xx, 0x33)
 
 IS_TI_CLASS(81xx, 0x81)
@@ -133,6 +135,7 @@ IS_OMAP_SUBCLASS(363x, 0x363)
 IS_OMAP_SUBCLASS(443x, 0x443)
 IS_OMAP_SUBCLASS(446x, 0x446)
 IS_OMAP_SUBCLASS(447x, 0x447)
+IS_OMAP_SUBCLASS(543x, 0x543)
 
 IS_TI_SUBCLASS(816x, 0x816)
 IS_TI_SUBCLASS(814x, 0x814)
@@ -156,6 +159,8 @@ IS_AM_SUBCLASS(335x, 0x335)
 #define cpu_is_omap443x()               0
 #define cpu_is_omap446x()               0
 #define cpu_is_omap447x()               0
+#define soc_is_omap54xx()               0
+#define soc_is_omap543x()               0
 
 #if defined(MULTI_OMAP1)
 # if defined(CONFIG_ARCH_OMAP730)
@@ -285,6 +290,7 @@ IS_OMAP_TYPE(3430, 0x3430)
 #define cpu_is_omap2430()               0
 #define cpu_is_omap3430()               0
 #define cpu_is_omap3630()               0
+#define soc_is_omap5430()               0
 
 /*
  * Whether we have MULTI_OMAP1 or not, we still need to distinguish
@@ -355,11 +361,18 @@ IS_OMAP_TYPE(3430, 0x3430)
 # define cpu_is_omap447x()              is_omap447x()
 # endif
 
+# if defined(CONFIG_SOC_OMAP5)
+# undef soc_is_omap54xx
+# undef soc_is_omap543x
+# define soc_is_omap54xx()              is_omap54xx()
+# define soc_is_omap543x()              is_omap543x()
+#endif
+
 /* Macros to detect if we have OMAP1 or OMAP2 */
 #define cpu_class_is_omap1()    (cpu_is_omap7xx() || cpu_is_omap15xx() || \
                                 cpu_is_omap16xx())
 #define cpu_class_is_omap2()    (cpu_is_omap24xx() || cpu_is_omap34xx() || \
-                                cpu_is_omap44xx())
+                                cpu_is_omap44xx() || soc_is_omap54xx())
 
 /* Various silicon revisions for omap2 */
 #define OMAP242X_CLASS          0x24200024
@@ -412,9 +425,14 @@ IS_OMAP_TYPE(3430, 0x3430)
 #define OMAP447X_CLASS          0x44700044
 #define OMAP4470_REV_ES1_0      (OMAP447X_CLASS | (0x10 << 8))
 
+#define OMAP54XX_CLASS          0x54000054
+#define OMAP5430_REV_ES1_0      (OMAP54XX_CLASS | (0x30 << 16) | (0x10 << 8))
+#define OMAP5432_REV_ES1_0      (OMAP54XX_CLASS | (0x32 << 16) | (0x10 << 8))
+
 void omap2xxx_check_revision(void);
 void omap3xxx_check_revision(void);
 void omap4xxx_check_revision(void);
+void omap5xxx_check_revision(void);
 void omap3xxx_check_features(void);
 void ti81xx_check_features(void);
 void omap4xxx_check_features(void);
diff --git a/arch/arm/plat-omap/include/plat/hardware.h b/arch/arm/plat-omap/include/plat/hardware.h
index e897978371c2..ddbde38e1e33 100644
--- a/arch/arm/plat-omap/include/plat/hardware.h
+++ b/arch/arm/plat-omap/include/plat/hardware.h
@@ -288,5 +288,6 @@
 #include <plat/omap44xx.h>
 #include <plat/ti81xx.h>
 #include <plat/am33xx.h>
+#include <plat/omap54xx.h>
 
 #endif  /* __ASM_ARCH_OMAP_HARDWARE_H */
diff --git a/arch/arm/plat-omap/include/plat/multi.h b/arch/arm/plat-omap/include/plat/multi.h
index 999ffba2690c..045e320f1067 100644
--- a/arch/arm/plat-omap/include/plat/multi.h
+++ b/arch/arm/plat-omap/include/plat/multi.h
@@ -99,4 +99,13 @@
 # endif
 #endif
 
+#ifdef CONFIG_SOC_OMAP5
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP2
+#  define MULTI_OMAP2
+# else
+#  define OMAP_NAME omap5
+# endif
+#endif
+
 #endif  /* __PLAT_OMAP_MULTI_H */
diff --git a/arch/arm/plat-omap/include/plat/omap-secure.h b/arch/arm/plat-omap/include/plat/omap-secure.h
index 8c7994ce9869..0e4acd2d2deb 100644
--- a/arch/arm/plat-omap/include/plat/omap-secure.h
+++ b/arch/arm/plat-omap/include/plat/omap-secure.h
@@ -3,12 +3,7 @@
 
 #include <linux/types.h>
 
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
 extern int omap_secure_ram_reserve_memblock(void);
-#else
-static inline void omap_secure_ram_reserve_memblock(void)
-{ }
-#endif
 
 #ifdef CONFIG_OMAP4_ERRATA_I688
 extern int omap_barrier_reserve_memblock(void);
diff --git a/arch/arm/plat-omap/include/plat/omap54xx.h b/arch/arm/plat-omap/include/plat/omap54xx.h
new file mode 100644
index 000000000000..a2582bb3cab3
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/omap54xx.h
@@ -0,0 +1,32 @@
+/*:
+ * Address mappings and base address for OMAP5 interconnects
+ * and peripherals.
+ *
+ * Copyright (C) 2012 Texas Instruments
+ *      Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *      Sricharan <r.sricharan@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_SOC_OMAP54XX_H
+#define __ASM_SOC_OMAP54XX_H
+
+/*
+ * Please place only base defines here and put the rest in device
+ * specific headers.
+ */
+#define L4_54XX_BASE                    0x4a000000
+#define L4_WK_54XX_BASE                 0x4ae00000
+#define L4_PER_54XX_BASE                0x48000000
+#define L3_54XX_BASE                    0x44000000
+#define OMAP54XX_32KSYNCT_BASE          0x4ae04000
+#define OMAP54XX_CM_CORE_AON_BASE       0x4a004000
+#define OMAP54XX_CM_CORE_BASE           0x4a008000
+#define OMAP54XX_PRM_BASE               0x4ae06000
+#define OMAP54XX_PRCM_MPU_BASE          0x48243000
+#define OMAP54XX_SCM_BASE               0x4a002000
+#define OMAP54XX_CTRL_BASE              0x4a002800
+
+#endif /* __ASM_SOC_OMAP555554XX_H */
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h
index 28e2d250c2fd..65fce44dce34 100644
--- a/arch/arm/plat-omap/include/plat/serial.h
+++ b/arch/arm/plat-omap/include/plat/serial.h
@@ -63,6 +63,14 @@
 /* AM33XX serial port */
 #define AM33XX_UART1_BASE       0x44E09000
 
+/* OMAP5 serial ports */
+#define OMAP5_UART1_BASE        OMAP2_UART1_BASE
+#define OMAP5_UART2_BASE        OMAP2_UART2_BASE
+#define OMAP5_UART3_BASE        OMAP4_UART3_BASE
+#define OMAP5_UART4_BASE        OMAP4_UART4_BASE
+#define OMAP5_UART5_BASE        0x48066000
+#define OMAP5_UART6_BASE        0x48068000
+
 /* External port on Zoom2/3 */
 #define ZOOM_UART_BASE          0x10000000
 #define ZOOM_UART_VIRT          0xfa400000
@@ -97,6 +105,8 @@
 #define TI81XXUART2             82
 #define TI81XXUART3             83
 #define AM33XXUART1             84
+#define OMAP5UART3              OMAP4UART3
+#define OMAP5UART4              OMAP4UART4
 #define ZOOM_UART               95              /* Only on zoom2/3 */
 
 /* This is only used by 8250.c for omap1510 */
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index ac4323390213..b8d19a136781 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -95,6 +95,9 @@ static inline void flush(void)
         _DEBUG_LL_ENTRY(mach, OMAP4_UART##p##_BASE, OMAP_PORT_SHIFT,    \
                 OMAP4UART##p)
 
+#define DEBUG_LL_OMAP5(p, mach)                                         \
+        _DEBUG_LL_ENTRY(mach, OMAP5_UART##p##_BASE, OMAP_PORT_SHIFT,    \
+                OMAP5UART##p)
 /* Zoom2/3 shift is different for UART1 and external port */
 #define DEBUG_LL_ZOOM(mach)                                             \
         _DEBUG_LL_ENTRY(mach, ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART)
@@ -177,6 +180,9 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
                 DEBUG_LL_OMAP4(3, omap_4430sdp);
                 DEBUG_LL_OMAP4(3, omap4_panda);
 
+                /* omap5 based boards using UART3 */
+                DEBUG_LL_OMAP5(3, omap5_sevm);
+
                 /* zoom2/3 external uart */
                 DEBUG_LL_ZOOM(omap_zoom2);
                 DEBUG_LL_ZOOM(omap_zoom3);
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 70cf825bdd87..766181cb5c95 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -6,8 +6,8 @@
  * Copyright (C) 2005 Nokia Corporation
  * Written by Tony Lindgren <tony@atomide.com>
  *
- * Copyright (C) 2009 Texas Instruments
- * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ * Copyright (C) 2009-2012 Texas Instruments
+ * Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -44,6 +44,7 @@
 #else
 #define OMAP4_SRAM_PUB_PA       (OMAP4_SRAM_PA + 0x4000)
 #endif
+#define OMAP5_SRAM_PA           0x40300000
 
 #if defined(CONFIG_ARCH_OMAP2PLUS)
 #define SRAM_BOOTLOADER_SZ      0x00
@@ -118,6 +119,9 @@ static void __init omap_detect_sram(void)
                         } else if (cpu_is_omap44xx()) {
                                 omap_sram_start = OMAP4_SRAM_PUB_PA;
                                 omap_sram_size = 0xa000; /* 40K */
+                        } else if (soc_is_omap54xx()) {
+                                omap_sram_start = OMAP5_SRAM_PA;
+                                omap_sram_size = SZ_128K; /* 128KB */
                         } else {
                                 omap_sram_start = OMAP2_SRAM_PUB_PA;
                                 omap_sram_size = 0x800; /* 2K */
@@ -132,6 +136,9 @@ static void __init omap_detect_sram(void)
                         } else if (cpu_is_omap44xx()) {
                                 omap_sram_start = OMAP4_SRAM_PA;
                                 omap_sram_size = 0xe000; /* 56K */
+                        } else if (soc_is_omap54xx()) {
+                                omap_sram_start = OMAP5_SRAM_PA;
+                                omap_sram_size = SZ_128K; /* 128KB */
                         } else {
                                 omap_sram_start = OMAP2_SRAM_PA;
                                 if (cpu_is_omap242x())
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 26b6b92942e1..3669761d1bac 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -5,4 +5,5 @@ obj-$(CONFIG_COMMON_CLK)	+= clk.o clk-fixed-rate.o clk-gate.o \
 # SoCs specific
 obj-$(CONFIG_ARCH_NOMADIK)      += clk-nomadik.o
 obj-$(CONFIG_ARCH_MXS)          += mxs/
+obj-$(CONFIG_ARCH_SOCFPGA)      += socfpga/
 obj-$(CONFIG_PLAT_SPEAR)        += spear/
diff --git a/drivers/clk/socfpga/Makefile b/drivers/clk/socfpga/Makefile
new file mode 100644
index 000000000000..0303c0b99cd0
--- /dev/null
+++ b/drivers/clk/socfpga/Makefile
@@ -0,0 +1 @@
+obj-y += clk.o
diff --git a/drivers/clk/socfpga/clk.c b/drivers/clk/socfpga/clk.c
new file mode 100644
index 000000000000..2c855a6394ff
--- /dev/null
+++ b/drivers/clk/socfpga/clk.c
@@ -0,0 +1,51 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+
+#define SOCFPGA_OSC1_CLK        10000000
+#define SOCFPGA_MPU_CLK         800000000
+#define SOCFPGA_MAIN_QSPI_CLK           432000000
+#define SOCFPGA_MAIN_NAND_SDMMC_CLK     250000000
+#define SOCFPGA_S2F_USR_CLK             125000000
+
+void __init socfpga_init_clocks(void)
+{
+        struct clk *clk;
+
+        clk = clk_register_fixed_rate(NULL, "osc1_clk", NULL, CLK_IS_ROOT, SOCFPGA_OSC1_CLK);
+        clk_register_clkdev(clk, "osc1_clk", NULL);
+
+        clk = clk_register_fixed_rate(NULL, "mpu_clk", NULL, CLK_IS_ROOT, SOCFPGA_MPU_CLK);
+        clk_register_clkdev(clk, "mpu_clk", NULL);
+
+        clk = clk_register_fixed_rate(NULL, "main_clk", NULL, CLK_IS_ROOT, SOCFPGA_MPU_CLK/2);
+        clk_register_clkdev(clk, "main_clk", NULL);
+
+        clk = clk_register_fixed_rate(NULL, "dbg_base_clk", NULL, CLK_IS_ROOT, SOCFPGA_MPU_CLK/2);
+        clk_register_clkdev(clk, "dbg_base_clk", NULL);
+
+        clk = clk_register_fixed_rate(NULL, "main_qspi_clk", NULL, CLK_IS_ROOT, SOCFPGA_MAIN_QSPI_CLK);
+        clk_register_clkdev(clk, "main_qspi_clk", NULL);
+
+        clk = clk_register_fixed_rate(NULL, "main_nand_sdmmc_clk", NULL, CLK_IS_ROOT, SOCFPGA_MAIN_NAND_SDMMC_CLK);
+        clk_register_clkdev(clk, "main_nand_sdmmc_clk", NULL);
+
+        clk = clk_register_fixed_rate(NULL, "s2f_usr_clk", NULL, CLK_IS_ROOT, SOCFPGA_S2F_USR_CLK);
+        clk_register_clkdev(clk, "s2f_usr_clk", NULL);
+}
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index e62bc7e9d49b..d53cd0afc200 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -19,6 +19,9 @@ config DW_APB_TIMER
 config DW_APB_TIMER_OF
         bool
 
+config ARMADA_370_XP_TIMER
+        bool
+
 config CLKSRC_DBX500_PRCMU
         bool "Clocksource PRCMU Timer"
         depends on UX500_SOC_DB8500
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 2cdaf7d1019f..b65d0c56ab35 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -11,4 +11,5 @@ obj-$(CONFIG_CLKBLD_I8253)	+= i8253.o
 obj-$(CONFIG_CLKSRC_MMIO)       += mmio.o
 obj-$(CONFIG_DW_APB_TIMER)      += dw_apb_timer.o
 obj-$(CONFIG_DW_APB_TIMER_OF)   += dw_apb_timer_of.o
-obj-$(CONFIG_CLKSRC_DBX500_PRCMU)       += clksrc-dbx500-prcmu.o
\ No newline at end of file
+obj-$(CONFIG_CLKSRC_DBX500_PRCMU)       += clksrc-dbx500-prcmu.o
+obj-$(CONFIG_ARMADA_370_XP_TIMER)       += time-armada-370-xp.o
diff --git a/drivers/clocksource/time-armada-370-xp.c b/drivers/clocksource/time-armada-370-xp.c
new file mode 100644
index 000000000000..4674f94957cd
--- /dev/null
+++ b/drivers/clocksource/time-armada-370-xp.c
@@ -0,0 +1,226 @@
+/*
+ * Marvell Armada 370/XP SoC timer handling.
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Timer 0 is used as free-running clocksource, while timer 1 is
+ * used as clock_event_device.
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/kernel.h>
+#include <linux/timer.h>
+#include <linux/clockchips.h>
+#include <linux/interrupt.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/irq.h>
+#include <linux/module.h>
+#include <asm/sched_clock.h>
+
+/*
+ * Timer block registers.
+ */
+#define TIMER_CTRL_OFF          0x0000
+#define  TIMER0_EN               0x0001
+#define  TIMER0_RELOAD_EN        0x0002
+#define  TIMER0_25MHZ            0x0800
+#define  TIMER0_DIV(div)         ((div) << 19)
+#define  TIMER1_EN               0x0004
+#define  TIMER1_RELOAD_EN        0x0008
+#define  TIMER1_25MHZ            0x1000
+#define  TIMER1_DIV(div)         ((div) << 22)
+#define TIMER_EVENTS_STATUS     0x0004
+#define  TIMER0_CLR_MASK         (~0x1)
+#define  TIMER1_CLR_MASK         (~0x100)
+#define TIMER0_RELOAD_OFF       0x0010
+#define TIMER0_VAL_OFF          0x0014
+#define TIMER1_RELOAD_OFF       0x0018
+#define TIMER1_VAL_OFF          0x001c
+
+/* Global timers are connected to the coherency fabric clock, and the
+   below divider reduces their incrementing frequency. */
+#define TIMER_DIVIDER_SHIFT     5
+#define TIMER_DIVIDER           (1 << TIMER_DIVIDER_SHIFT)
+
+/*
+ * SoC-specific data.
+ */
+static void __iomem *timer_base;
+static int timer_irq;
+
+/*
+ * Number of timer ticks per jiffy.
+ */
+static u32 ticks_per_jiffy;
+
+static u32 notrace armada_370_xp_read_sched_clock(void)
+{
+        return ~readl(timer_base + TIMER0_VAL_OFF);
+}
+
+/*
+ * Clockevent handling.
+ */
+static int
+armada_370_xp_clkevt_next_event(unsigned long delta,
+                                struct clock_event_device *dev)
+{
+        u32 u;
+
+        /*
+         * Clear clockevent timer interrupt.
+         */
+        writel(TIMER1_CLR_MASK, timer_base + TIMER_EVENTS_STATUS);
+
+        /*
+         * Setup new clockevent timer value.
+         */
+        writel(delta, timer_base + TIMER1_VAL_OFF);
+
+        /*
+         * Enable the timer.
+         */
+        u = readl(timer_base + TIMER_CTRL_OFF);
+        u = ((u & ~TIMER1_RELOAD_EN) | TIMER1_EN |
+             TIMER1_DIV(TIMER_DIVIDER_SHIFT));
+        writel(u, timer_base + TIMER_CTRL_OFF);
+
+        return 0;
+}
+
+static void
+armada_370_xp_clkevt_mode(enum clock_event_mode mode,
+                          struct clock_event_device *dev)
+{
+        u32 u;
+
+        if (mode == CLOCK_EVT_MODE_PERIODIC) {
+                /*
+                 * Setup timer to fire at 1/HZ intervals.
+                 */
+                writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD_OFF);
+                writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL_OFF);
+
+                /*
+                 * Enable timer.
+                 */
+                u = readl(timer_base + TIMER_CTRL_OFF);
+
+                writel((u | TIMER1_EN | TIMER1_RELOAD_EN |
+                        TIMER1_DIV(TIMER_DIVIDER_SHIFT)),
+                       timer_base + TIMER_CTRL_OFF);
+        } else {
+                /*
+                 * Disable timer.
+                 */
+                u = readl(timer_base + TIMER_CTRL_OFF);
+                writel(u & ~TIMER1_EN, timer_base + TIMER_CTRL_OFF);
+
+                /*
+                 * ACK pending timer interrupt.
+                 */
+                writel(TIMER1_CLR_MASK, timer_base + TIMER_EVENTS_STATUS);
+
+        }
+}
+
+static struct clock_event_device armada_370_xp_clkevt = {
+        .name           = "armada_370_xp_tick",
+        .features       = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
+        .shift          = 32,
+        .rating         = 300,
+        .set_next_event = armada_370_xp_clkevt_next_event,
+        .set_mode       = armada_370_xp_clkevt_mode,
+};
+
+static irqreturn_t armada_370_xp_timer_interrupt(int irq, void *dev_id)
+{
+        /*
+         * ACK timer interrupt and call event handler.
+         */
+
+        writel(TIMER1_CLR_MASK, timer_base + TIMER_EVENTS_STATUS);
+        armada_370_xp_clkevt.event_handler(&armada_370_xp_clkevt);
+
+        return IRQ_HANDLED;
+}
+
+static struct irqaction armada_370_xp_timer_irq = {
+        .name           = "armada_370_xp_tick",
+        .flags          = IRQF_DISABLED | IRQF_TIMER,
+        .handler        = armada_370_xp_timer_interrupt
+};
+
+void __init armada_370_xp_timer_init(void)
+{
+        u32 u;
+        struct device_node *np;
+        unsigned int timer_clk;
+        int ret;
+        np = of_find_compatible_node(NULL, NULL, "marvell,armada-370-xp-timer");
+        timer_base = of_iomap(np, 0);
+        WARN_ON(!timer_base);
+
+        if (of_find_property(np, "marvell,timer-25Mhz", NULL)) {
+                /* The fixed 25MHz timer is available so let's use it */
+                u = readl(timer_base + TIMER_CTRL_OFF);
+                writel(u | TIMER0_25MHZ | TIMER1_25MHZ,
+                       timer_base + TIMER_CTRL_OFF);
+                timer_clk = 25000000;
+        } else {
+                u32 clk = 0;
+                ret = of_property_read_u32(np, "clock-frequency", &clk);
+                WARN_ON(!clk || ret < 0);
+                u = readl(timer_base + TIMER_CTRL_OFF);
+                writel(u & ~(TIMER0_25MHZ | TIMER1_25MHZ),
+                       timer_base + TIMER_CTRL_OFF);
+                timer_clk = clk / TIMER_DIVIDER;
+        }
+
+        /* We use timer 0 as clocksource, and timer 1 for
+           clockevents */
+        timer_irq = irq_of_parse_and_map(np, 1);
+
+        ticks_per_jiffy = (timer_clk + HZ / 2) / HZ;
+
+        /*
+         * Set scale and timer for sched_clock.
+         */
+        setup_sched_clock(armada_370_xp_read_sched_clock, 32, timer_clk);
+
+        /*
+         * Setup free-running clocksource timer (interrupts
+         * disabled).
+         */
+        writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
+        writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
+
+        u = readl(timer_base + TIMER_CTRL_OFF);
+
+        writel((u | TIMER0_EN | TIMER0_RELOAD_EN |
+                TIMER0_DIV(TIMER_DIVIDER_SHIFT)), timer_base + TIMER_CTRL_OFF);
+
+        clocksource_mmio_init(timer_base + TIMER0_VAL_OFF,
+                              "armada_370_xp_clocksource",
+                              timer_clk, 300, 32, clocksource_mmio_readl_down);
+
+        /*
+         * Setup clockevent timer (interrupt-driven).
+         */
+        setup_irq(timer_irq, &armada_370_xp_timer_irq);
+        armada_370_xp_clkevt.cpumask = cpumask_of(0);
+        clockevents_config_and_register(&armada_370_xp_clkevt,
+                                        timer_clk, 1, 0xfffffffe);
+}
+
diff --git a/include/linux/dw_apb_timer.h b/include/linux/dw_apb_timer.h
index 07261d52a6df..1148575fd134 100644
--- a/include/linux/dw_apb_timer.h
+++ b/include/linux/dw_apb_timer.h
@@ -53,4 +53,5 @@ void dw_apb_clocksource_start(struct dw_apb_clocksource *dw_cs);
 cycle_t dw_apb_clocksource_read(struct dw_apb_clocksource *dw_cs);
 void dw_apb_clocksource_unregister(struct dw_apb_clocksource *dw_cs);
 
+extern struct sys_timer dw_apb_timer;
 #endif /* __DW_APB_TIMER_H__ */
diff --git a/include/linux/time-armada-370-xp.h b/include/linux/time-armada-370-xp.h
new file mode 100644
index 000000000000..dfdfdc03115b
--- /dev/null
+++ b/include/linux/time-armada-370-xp.h
@@ -0,0 +1,18 @@
+/*
+ * Marvell Armada 370/XP SoC timer handling.
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ */
+#ifndef __TIME_ARMADA_370_XPPRCMU_H
+#define __TIME_ARMADA_370_XPPRCMU_H
+
+#include <linux/init.h>
+
+void __init armada_370_xp_timer_init(void);
+
+#endif