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-rw-r--r--drivers/dma/dw_dmac.c14
-rw-r--r--drivers/dma/dw_dmac_regs.h1
-rw-r--r--include/linux/dw_dmac.h30
3 files changed, 39 insertions, 6 deletions
diff --git a/drivers/dma/dw_dmac.c b/drivers/dma/dw_dmac.c
index 318a342fc7ec..90ea08a53d62 100644
--- a/drivers/dma/dw_dmac.c
+++ b/drivers/dma/dw_dmac.c
@@ -36,9 +36,11 @@
36 struct dw_dma_slave *__slave = (private); \ 36 struct dw_dma_slave *__slave = (private); \
37 int dms = __slave ? __slave->dst_master : 0; \ 37 int dms = __slave ? __slave->dst_master : 0; \
38 int sms = __slave ? __slave->src_master : 1; \ 38 int sms = __slave ? __slave->src_master : 1; \
39 u8 smsize = __slave ? __slave->src_msize : 0; \
40 u8 dmsize = __slave ? __slave->dst_msize : 0; \
39 \ 41 \
40 (DWC_CTLL_DST_MSIZE(0) \ 42 (DWC_CTLL_DST_MSIZE(dmsize) \
41 | DWC_CTLL_SRC_MSIZE(0) \ 43 | DWC_CTLL_SRC_MSIZE(smsize) \
42 | DWC_CTLL_LLP_D_EN \ 44 | DWC_CTLL_LLP_D_EN \
43 | DWC_CTLL_LLP_S_EN \ 45 | DWC_CTLL_LLP_S_EN \
44 | DWC_CTLL_DMS(dms) \ 46 | DWC_CTLL_DMS(dms) \
@@ -683,7 +685,7 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
683 | DWC_CTLL_DST_WIDTH(reg_width) 685 | DWC_CTLL_DST_WIDTH(reg_width)
684 | DWC_CTLL_DST_FIX 686 | DWC_CTLL_DST_FIX
685 | DWC_CTLL_SRC_INC 687 | DWC_CTLL_SRC_INC
686 | DWC_CTLL_FC_M2P); 688 | DWC_CTLL_FC(dws->fc));
687 reg = dws->tx_reg; 689 reg = dws->tx_reg;
688 for_each_sg(sgl, sg, sg_len, i) { 690 for_each_sg(sgl, sg, sg_len, i) {
689 struct dw_desc *desc; 691 struct dw_desc *desc;
@@ -728,7 +730,7 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
728 | DWC_CTLL_SRC_WIDTH(reg_width) 730 | DWC_CTLL_SRC_WIDTH(reg_width)
729 | DWC_CTLL_DST_INC 731 | DWC_CTLL_DST_INC
730 | DWC_CTLL_SRC_FIX 732 | DWC_CTLL_SRC_FIX
731 | DWC_CTLL_FC_P2M); 733 | DWC_CTLL_FC(dws->fc));
732 734
733 reg = dws->rx_reg; 735 reg = dws->rx_reg;
734 for_each_sg(sgl, sg, sg_len, i) { 736 for_each_sg(sgl, sg, sg_len, i) {
@@ -1146,7 +1148,7 @@ struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1146 | DWC_CTLL_SRC_WIDTH(reg_width) 1148 | DWC_CTLL_SRC_WIDTH(reg_width)
1147 | DWC_CTLL_DST_FIX 1149 | DWC_CTLL_DST_FIX
1148 | DWC_CTLL_SRC_INC 1150 | DWC_CTLL_SRC_INC
1149 | DWC_CTLL_FC_M2P 1151 | DWC_CTLL_FC(dws->fc)
1150 | DWC_CTLL_INT_EN); 1152 | DWC_CTLL_INT_EN);
1151 break; 1153 break;
1152 case DMA_FROM_DEVICE: 1154 case DMA_FROM_DEVICE:
@@ -1157,7 +1159,7 @@ struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1157 | DWC_CTLL_DST_WIDTH(reg_width) 1159 | DWC_CTLL_DST_WIDTH(reg_width)
1158 | DWC_CTLL_DST_INC 1160 | DWC_CTLL_DST_INC
1159 | DWC_CTLL_SRC_FIX 1161 | DWC_CTLL_SRC_FIX
1160 | DWC_CTLL_FC_P2M 1162 | DWC_CTLL_FC(dws->fc)
1161 | DWC_CTLL_INT_EN); 1163 | DWC_CTLL_INT_EN);
1162 break; 1164 break;
1163 default: 1165 default:
diff --git a/drivers/dma/dw_dmac_regs.h b/drivers/dma/dw_dmac_regs.h
index 6a8e6d35f359..9a32964bf795 100644
--- a/drivers/dma/dw_dmac_regs.h
+++ b/drivers/dma/dw_dmac_regs.h
@@ -86,6 +86,7 @@ struct dw_dma_regs {
86#define DWC_CTLL_SRC_MSIZE(n) ((n)<<14) 86#define DWC_CTLL_SRC_MSIZE(n) ((n)<<14)
87#define DWC_CTLL_S_GATH_EN (1 << 17) /* src gather, !FIX */ 87#define DWC_CTLL_S_GATH_EN (1 << 17) /* src gather, !FIX */
88#define DWC_CTLL_D_SCAT_EN (1 << 18) /* dst scatter, !FIX */ 88#define DWC_CTLL_D_SCAT_EN (1 << 18) /* dst scatter, !FIX */
89#define DWC_CTLL_FC(n) ((n) << 20)
89#define DWC_CTLL_FC_M2M (0 << 20) /* mem-to-mem */ 90#define DWC_CTLL_FC_M2M (0 << 20) /* mem-to-mem */
90#define DWC_CTLL_FC_M2P (1 << 20) /* mem-to-periph */ 91#define DWC_CTLL_FC_M2P (1 << 20) /* mem-to-periph */
91#define DWC_CTLL_FC_P2M (2 << 20) /* periph-to-mem */ 92#define DWC_CTLL_FC_P2M (2 << 20) /* periph-to-mem */
diff --git a/include/linux/dw_dmac.h b/include/linux/dw_dmac.h
index 3ba2f066ff46..6998d9376ef9 100644
--- a/include/linux/dw_dmac.h
+++ b/include/linux/dw_dmac.h
@@ -42,6 +42,30 @@ enum dw_dma_slave_width {
42 DW_DMA_SLAVE_WIDTH_32BIT, 42 DW_DMA_SLAVE_WIDTH_32BIT,
43}; 43};
44 44
45/* bursts size */
46enum dw_dma_msize {
47 DW_DMA_MSIZE_1,
48 DW_DMA_MSIZE_4,
49 DW_DMA_MSIZE_8,
50 DW_DMA_MSIZE_16,
51 DW_DMA_MSIZE_32,
52 DW_DMA_MSIZE_64,
53 DW_DMA_MSIZE_128,
54 DW_DMA_MSIZE_256,
55};
56
57/* flow controller */
58enum dw_dma_fc {
59 DW_DMA_FC_D_M2M,
60 DW_DMA_FC_D_M2P,
61 DW_DMA_FC_D_P2M,
62 DW_DMA_FC_D_P2P,
63 DW_DMA_FC_P_P2M,
64 DW_DMA_FC_SP_P2P,
65 DW_DMA_FC_P_M2P,
66 DW_DMA_FC_DP_P2P,
67};
68
45/** 69/**
46 * struct dw_dma_slave - Controller-specific information about a slave 70 * struct dw_dma_slave - Controller-specific information about a slave
47 * 71 *
@@ -55,6 +79,9 @@ enum dw_dma_slave_width {
55 * @cfg_lo: Platform-specific initializer for the CFG_LO register 79 * @cfg_lo: Platform-specific initializer for the CFG_LO register
56 * @src_master: src master for transfers on allocated channel. 80 * @src_master: src master for transfers on allocated channel.
57 * @dst_master: dest master for transfers on allocated channel. 81 * @dst_master: dest master for transfers on allocated channel.
82 * @src_msize: src burst size.
83 * @dst_msize: dest burst size.
84 * @fc: flow controller for DMA transfer
58 */ 85 */
59struct dw_dma_slave { 86struct dw_dma_slave {
60 struct device *dma_dev; 87 struct device *dma_dev;
@@ -65,6 +92,9 @@ struct dw_dma_slave {
65 u32 cfg_lo; 92 u32 cfg_lo;
66 u8 src_master; 93 u8 src_master;
67 u8 dst_master; 94 u8 dst_master;
95 u8 src_msize;
96 u8 dst_msize;
97 u8 fc;
68}; 98};
69 99
70/* Platform-configurable bits in CFG_HI */ 100/* Platform-configurable bits in CFG_HI */