diff options
-rw-r--r-- | arch/arm/include/asm/suspend.h | 17 | ||||
-rw-r--r-- | arch/arm/kernel/Makefile | 2 | ||||
-rw-r--r-- | arch/arm/kernel/sleep.S | 33 | ||||
-rw-r--r-- | arch/arm/kernel/suspend.c | 48 | ||||
-rw-r--r-- | arch/arm/mm/proc-arm920.S | 4 | ||||
-rw-r--r-- | arch/arm/mm/proc-arm926.S | 4 | ||||
-rw-r--r-- | arch/arm/mm/proc-sa1100.S | 4 | ||||
-rw-r--r-- | arch/arm/mm/proc-v6.S | 6 | ||||
-rw-r--r-- | arch/arm/mm/proc-v7.S | 6 | ||||
-rw-r--r-- | arch/arm/mm/proc-xsc3.S | 6 | ||||
-rw-r--r-- | arch/arm/mm/proc-xscale.S | 4 |
11 files changed, 62 insertions, 72 deletions
diff --git a/arch/arm/include/asm/suspend.h b/arch/arm/include/asm/suspend.h index b0e4e1a02318..1c0a551ae375 100644 --- a/arch/arm/include/asm/suspend.h +++ b/arch/arm/include/asm/suspend.h | |||
@@ -1,22 +1,7 @@ | |||
1 | #ifndef __ASM_ARM_SUSPEND_H | 1 | #ifndef __ASM_ARM_SUSPEND_H |
2 | #define __ASM_ARM_SUSPEND_H | 2 | #define __ASM_ARM_SUSPEND_H |
3 | 3 | ||
4 | #include <asm/memory.h> | ||
5 | #include <asm/tlbflush.h> | ||
6 | |||
7 | extern void cpu_resume(void); | 4 | extern void cpu_resume(void); |
8 | 5 | extern int cpu_suspend(unsigned long, int (*)(unsigned long)); | |
9 | /* | ||
10 | * Hide the first two arguments to __cpu_suspend - these are an implementation | ||
11 | * detail which platform code shouldn't have to know about. | ||
12 | */ | ||
13 | static inline int cpu_suspend(unsigned long arg, int (*fn)(unsigned long)) | ||
14 | { | ||
15 | extern int __cpu_suspend(int, long, unsigned long, | ||
16 | int (*)(unsigned long)); | ||
17 | int ret = __cpu_suspend(0, PHYS_OFFSET - PAGE_OFFSET, arg, fn); | ||
18 | flush_tlb_all(); | ||
19 | return ret; | ||
20 | } | ||
21 | 6 | ||
22 | #endif | 7 | #endif |
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index f7887dc53c1f..787b88823a56 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile | |||
@@ -29,7 +29,7 @@ obj-$(CONFIG_MODULES) += armksyms.o module.o | |||
29 | obj-$(CONFIG_ARTHUR) += arthur.o | 29 | obj-$(CONFIG_ARTHUR) += arthur.o |
30 | obj-$(CONFIG_ISA_DMA) += dma-isa.o | 30 | obj-$(CONFIG_ISA_DMA) += dma-isa.o |
31 | obj-$(CONFIG_PCI) += bios32.o isa.o | 31 | obj-$(CONFIG_PCI) += bios32.o isa.o |
32 | obj-$(CONFIG_PM_SLEEP) += sleep.o | 32 | obj-$(CONFIG_PM_SLEEP) += sleep.o suspend.o |
33 | obj-$(CONFIG_HAVE_SCHED_CLOCK) += sched_clock.o | 33 | obj-$(CONFIG_HAVE_SCHED_CLOCK) += sched_clock.o |
34 | obj-$(CONFIG_SMP) += smp.o smp_tlb.o | 34 | obj-$(CONFIG_SMP) += smp.o smp_tlb.o |
35 | obj-$(CONFIG_HAVE_ARM_SCU) += smp_scu.o | 35 | obj-$(CONFIG_HAVE_ARM_SCU) += smp_scu.o |
diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S index 46a9f460db83..8cf13de1e368 100644 --- a/arch/arm/kernel/sleep.S +++ b/arch/arm/kernel/sleep.S | |||
@@ -27,7 +27,7 @@ ENTRY(__cpu_suspend) | |||
27 | sub sp, sp, r5 @ allocate CPU state on stack | 27 | sub sp, sp, r5 @ allocate CPU state on stack |
28 | mov r0, sp @ save pointer to CPU save block | 28 | mov r0, sp @ save pointer to CPU save block |
29 | add ip, ip, r1 @ convert resume fn to phys | 29 | add ip, ip, r1 @ convert resume fn to phys |
30 | stmfd sp!, {r1, r6, ip} @ save v:p, virt SP, phys resume fn | 30 | stmfd sp!, {r6, ip} @ save virt SP, phys resume fn |
31 | ldr r5, =sleep_save_sp | 31 | ldr r5, =sleep_save_sp |
32 | add r6, sp, r1 @ convert SP to phys | 32 | add r6, sp, r1 @ convert SP to phys |
33 | stmfd sp!, {r2, r3} @ save suspend func arg and pointer | 33 | stmfd sp!, {r2, r3} @ save suspend func arg and pointer |
@@ -60,7 +60,7 @@ ENDPROC(__cpu_suspend) | |||
60 | .ltorg | 60 | .ltorg |
61 | 61 | ||
62 | cpu_suspend_abort: | 62 | cpu_suspend_abort: |
63 | ldmia sp!, {r1 - r3} @ pop v:p, virt SP, phys resume fn | 63 | ldmia sp!, {r2 - r3} @ pop virt SP, phys resume fn |
64 | teq r0, #0 | 64 | teq r0, #0 |
65 | moveq r0, #1 @ force non-zero value | 65 | moveq r0, #1 @ force non-zero value |
66 | mov sp, r2 | 66 | mov sp, r2 |
@@ -74,28 +74,19 @@ ENDPROC(cpu_suspend_abort) | |||
74 | * r3 = L1 section flags | 74 | * r3 = L1 section flags |
75 | */ | 75 | */ |
76 | ENTRY(cpu_resume_mmu) | 76 | ENTRY(cpu_resume_mmu) |
77 | adr r4, cpu_resume_turn_mmu_on | ||
78 | mov r4, r4, lsr #20 | ||
79 | orr r3, r3, r4, lsl #20 | ||
80 | ldr r5, [r2, r4, lsl #2] @ save old mapping | ||
81 | str r3, [r2, r4, lsl #2] @ setup 1:1 mapping for mmu code | ||
82 | sub r2, r2, r1 | ||
83 | ldr r3, =cpu_resume_after_mmu | 77 | ldr r3, =cpu_resume_after_mmu |
84 | bic r1, r0, #CR_C @ ensure D-cache is disabled | ||
85 | b cpu_resume_turn_mmu_on | 78 | b cpu_resume_turn_mmu_on |
86 | ENDPROC(cpu_resume_mmu) | 79 | ENDPROC(cpu_resume_mmu) |
87 | .ltorg | 80 | .ltorg |
88 | .align 5 | 81 | .align 5 |
89 | cpu_resume_turn_mmu_on: | 82 | ENTRY(cpu_resume_turn_mmu_on) |
90 | mcr p15, 0, r1, c1, c0, 0 @ turn on MMU, I-cache, etc | 83 | mcr p15, 0, r0, c1, c0, 0 @ turn on MMU, I-cache, etc |
91 | mrc p15, 0, r1, c0, c0, 0 @ read id reg | 84 | mrc p15, 0, r0, c0, c0, 0 @ read id reg |
92 | mov r1, r1 | 85 | mov r0, r0 |
93 | mov r1, r1 | 86 | mov r0, r0 |
94 | mov pc, r3 @ jump to virtual address | 87 | mov pc, r3 @ jump to virtual address |
95 | ENDPROC(cpu_resume_turn_mmu_on) | 88 | ENDPROC(cpu_resume_turn_mmu_on) |
96 | cpu_resume_after_mmu: | 89 | cpu_resume_after_mmu: |
97 | str r5, [r2, r4, lsl #2] @ restore old mapping | ||
98 | mcr p15, 0, r0, c1, c0, 0 @ turn on D-cache | ||
99 | bl cpu_init @ restore the und/abt/irq banked regs | 90 | bl cpu_init @ restore the und/abt/irq banked regs |
100 | mov r0, #0 @ return zero on success | 91 | mov r0, #0 @ return zero on success |
101 | ldmfd sp!, {r4 - r11, pc} | 92 | ldmfd sp!, {r4 - r11, pc} |
@@ -121,11 +112,11 @@ ENTRY(cpu_resume) | |||
121 | ldr r0, sleep_save_sp @ stack phys addr | 112 | ldr r0, sleep_save_sp @ stack phys addr |
122 | #endif | 113 | #endif |
123 | setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1 @ set SVC, irqs off | 114 | setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1 @ set SVC, irqs off |
124 | @ load v:p, stack, resume fn | 115 | @ load stack, resume fn |
125 | ARM( ldmia r0!, {r1, sp, pc} ) | 116 | ARM( ldmia r0!, {sp, pc} ) |
126 | THUMB( ldmia r0!, {r1, r2, r3} ) | 117 | THUMB( ldmia r0!, {r2, r3} ) |
127 | THUMB( mov sp, r2 ) | 118 | THUMB( mov sp, r2 ) |
128 | THUMB( bx r3 ) | 119 | THUMB( bx r3 ) |
129 | ENDPROC(cpu_resume) | 120 | ENDPROC(cpu_resume) |
130 | 121 | ||
131 | sleep_save_sp: | 122 | sleep_save_sp: |
diff --git a/arch/arm/kernel/suspend.c b/arch/arm/kernel/suspend.c new file mode 100644 index 000000000000..0a33f109549d --- /dev/null +++ b/arch/arm/kernel/suspend.c | |||
@@ -0,0 +1,48 @@ | |||
1 | #include <linux/init.h> | ||
2 | |||
3 | #include <asm/pgalloc.h> | ||
4 | #include <asm/pgtable.h> | ||
5 | #include <asm/memory.h> | ||
6 | #include <asm/suspend.h> | ||
7 | #include <asm/tlbflush.h> | ||
8 | |||
9 | static pgd_t *suspend_pgd; | ||
10 | |||
11 | extern int __cpu_suspend(int, long, unsigned long, int (*)(unsigned long)); | ||
12 | extern void cpu_resume_turn_mmu_on(void); | ||
13 | |||
14 | /* | ||
15 | * Hide the first two arguments to __cpu_suspend - these are an implementation | ||
16 | * detail which platform code shouldn't have to know about. | ||
17 | */ | ||
18 | int cpu_suspend(unsigned long arg, int (*fn)(unsigned long)) | ||
19 | { | ||
20 | struct mm_struct *mm = current->active_mm; | ||
21 | int ret; | ||
22 | |||
23 | if (!suspend_pgd) | ||
24 | return -EINVAL; | ||
25 | |||
26 | /* | ||
27 | * Temporarily switch the page tables to our suspend page | ||
28 | * tables, which contain the temporary identity mapping | ||
29 | * required for resuming. | ||
30 | */ | ||
31 | cpu_switch_mm(suspend_pgd, mm); | ||
32 | ret = __cpu_suspend(0, PHYS_OFFSET - PAGE_OFFSET, arg, fn); | ||
33 | cpu_switch_mm(mm->pgd, mm); | ||
34 | local_flush_tlb_all(); | ||
35 | |||
36 | return ret; | ||
37 | } | ||
38 | |||
39 | static int __init cpu_suspend_init(void) | ||
40 | { | ||
41 | suspend_pgd = pgd_alloc(&init_mm); | ||
42 | if (suspend_pgd) { | ||
43 | unsigned long addr = virt_to_phys(cpu_resume_turn_mmu_on); | ||
44 | identity_mapping_add(suspend_pgd, addr, addr + SECTION_SIZE); | ||
45 | } | ||
46 | return suspend_pgd ? 0 : -ENOMEM; | ||
47 | } | ||
48 | core_initcall(cpu_suspend_init); | ||
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S index 2e6849b41f66..035d57bf1b7a 100644 --- a/arch/arm/mm/proc-arm920.S +++ b/arch/arm/mm/proc-arm920.S | |||
@@ -400,10 +400,6 @@ ENTRY(cpu_arm920_do_resume) | |||
400 | mcr p15, 0, r5, c3, c0, 0 @ Domain ID | 400 | mcr p15, 0, r5, c3, c0, 0 @ Domain ID |
401 | mcr p15, 0, r6, c2, c0, 0 @ TTB address | 401 | mcr p15, 0, r6, c2, c0, 0 @ TTB address |
402 | mov r0, r7 @ control register | 402 | mov r0, r7 @ control register |
403 | mov r2, r6, lsr #14 @ get TTB0 base | ||
404 | mov r2, r2, lsl #14 | ||
405 | ldr r3, =PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | \ | ||
406 | PMD_SECT_CACHEABLE | PMD_BIT4 | PMD_SECT_AP_WRITE | ||
407 | b cpu_resume_mmu | 403 | b cpu_resume_mmu |
408 | ENDPROC(cpu_arm920_do_resume) | 404 | ENDPROC(cpu_arm920_do_resume) |
409 | #endif | 405 | #endif |
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S index cd8f79c3a282..48add848b997 100644 --- a/arch/arm/mm/proc-arm926.S +++ b/arch/arm/mm/proc-arm926.S | |||
@@ -415,10 +415,6 @@ ENTRY(cpu_arm926_do_resume) | |||
415 | mcr p15, 0, r5, c3, c0, 0 @ Domain ID | 415 | mcr p15, 0, r5, c3, c0, 0 @ Domain ID |
416 | mcr p15, 0, r6, c2, c0, 0 @ TTB address | 416 | mcr p15, 0, r6, c2, c0, 0 @ TTB address |
417 | mov r0, r7 @ control register | 417 | mov r0, r7 @ control register |
418 | mov r2, r6, lsr #14 @ get TTB0 base | ||
419 | mov r2, r2, lsl #14 | ||
420 | ldr r3, =PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | \ | ||
421 | PMD_SECT_CACHEABLE | PMD_BIT4 | PMD_SECT_AP_WRITE | ||
422 | b cpu_resume_mmu | 418 | b cpu_resume_mmu |
423 | ENDPROC(cpu_arm926_do_resume) | 419 | ENDPROC(cpu_arm926_do_resume) |
424 | #endif | 420 | #endif |
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S index 69e7f2ef7384..52f73fb47ac1 100644 --- a/arch/arm/mm/proc-sa1100.S +++ b/arch/arm/mm/proc-sa1100.S | |||
@@ -192,10 +192,6 @@ ENTRY(cpu_sa1100_do_resume) | |||
192 | mcr p15, 0, r5, c2, c0, 0 @ translation table base addr | 192 | mcr p15, 0, r5, c2, c0, 0 @ translation table base addr |
193 | mcr p15, 0, r6, c13, c0, 0 @ PID | 193 | mcr p15, 0, r6, c13, c0, 0 @ PID |
194 | mov r0, r7 @ control register | 194 | mov r0, r7 @ control register |
195 | mov r2, r5, lsr #14 @ get TTB0 base | ||
196 | mov r2, r2, lsl #14 | ||
197 | ldr r3, =PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | \ | ||
198 | PMD_SECT_CACHEABLE | PMD_SECT_AP_WRITE | ||
199 | b cpu_resume_mmu | 195 | b cpu_resume_mmu |
200 | ENDPROC(cpu_sa1100_do_resume) | 196 | ENDPROC(cpu_sa1100_do_resume) |
201 | #endif | 197 | #endif |
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S index a923aa0fd00d..414e3696bdf7 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S | |||
@@ -161,14 +161,8 @@ ENTRY(cpu_v6_do_resume) | |||
161 | mcr p15, 0, ip, c2, c0, 2 @ TTB control register | 161 | mcr p15, 0, ip, c2, c0, 2 @ TTB control register |
162 | mcr p15, 0, ip, c7, c5, 4 @ ISB | 162 | mcr p15, 0, ip, c7, c5, 4 @ ISB |
163 | mov r0, r11 @ control register | 163 | mov r0, r11 @ control register |
164 | mov r2, r7, lsr #14 @ get TTB0 base | ||
165 | mov r2, r2, lsl #14 | ||
166 | ldr r3, cpu_resume_l1_flags | ||
167 | b cpu_resume_mmu | 164 | b cpu_resume_mmu |
168 | ENDPROC(cpu_v6_do_resume) | 165 | ENDPROC(cpu_v6_do_resume) |
169 | cpu_resume_l1_flags: | ||
170 | ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_SMP) | ||
171 | ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_UP) | ||
172 | #endif | 166 | #endif |
173 | 167 | ||
174 | string cpu_v6_name, "ARMv6-compatible processor" | 168 | string cpu_v6_name, "ARMv6-compatible processor" |
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 9049c0764db2..21d6910d2208 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S | |||
@@ -259,14 +259,8 @@ ENTRY(cpu_v7_do_resume) | |||
259 | isb | 259 | isb |
260 | dsb | 260 | dsb |
261 | mov r0, r9 @ control register | 261 | mov r0, r9 @ control register |
262 | mov r2, r7, lsr #14 @ get TTB0 base | ||
263 | mov r2, r2, lsl #14 | ||
264 | ldr r3, cpu_resume_l1_flags | ||
265 | b cpu_resume_mmu | 262 | b cpu_resume_mmu |
266 | ENDPROC(cpu_v7_do_resume) | 263 | ENDPROC(cpu_v7_do_resume) |
267 | cpu_resume_l1_flags: | ||
268 | ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_SMP) | ||
269 | ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_UP) | ||
270 | #endif | 264 | #endif |
271 | 265 | ||
272 | __CPUINIT | 266 | __CPUINIT |
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S index 755e1bf22681..efd49492fa4d 100644 --- a/arch/arm/mm/proc-xsc3.S +++ b/arch/arm/mm/proc-xsc3.S | |||
@@ -435,13 +435,7 @@ ENTRY(cpu_xsc3_do_resume) | |||
435 | mcr p15, 0, r7, c3, c0, 0 @ domain ID | 435 | mcr p15, 0, r7, c3, c0, 0 @ domain ID |
436 | mcr p15, 0, r8, c2, c0, 0 @ translation table base addr | 436 | mcr p15, 0, r8, c2, c0, 0 @ translation table base addr |
437 | mcr p15, 0, r9, c1, c0, 1 @ auxiliary control reg | 437 | mcr p15, 0, r9, c1, c0, 1 @ auxiliary control reg |
438 | |||
439 | @ temporarily map resume_turn_on_mmu into the page table, | ||
440 | @ otherwise prefetch abort occurs after MMU is turned on | ||
441 | mov r0, r10 @ control register | 438 | mov r0, r10 @ control register |
442 | mov r2, r8, lsr #14 @ get TTB0 base | ||
443 | mov r2, r2, lsl #14 | ||
444 | ldr r3, =0x542e @ section flags | ||
445 | b cpu_resume_mmu | 439 | b cpu_resume_mmu |
446 | ENDPROC(cpu_xsc3_do_resume) | 440 | ENDPROC(cpu_xsc3_do_resume) |
447 | #endif | 441 | #endif |
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S index fbc06e55b87a..37dbadadf7c4 100644 --- a/arch/arm/mm/proc-xscale.S +++ b/arch/arm/mm/proc-xscale.S | |||
@@ -548,10 +548,6 @@ ENTRY(cpu_xscale_do_resume) | |||
548 | mcr p15, 0, r8, c2, c0, 0 @ translation table base addr | 548 | mcr p15, 0, r8, c2, c0, 0 @ translation table base addr |
549 | mcr p15, 0, r9, c1, c1, 0 @ auxiliary control reg | 549 | mcr p15, 0, r9, c1, c1, 0 @ auxiliary control reg |
550 | mov r0, r10 @ control register | 550 | mov r0, r10 @ control register |
551 | mov r2, r8, lsr #14 @ get TTB0 base | ||
552 | mov r2, r2, lsl #14 | ||
553 | ldr r3, =PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | \ | ||
554 | PMD_SECT_CACHEABLE | PMD_SECT_AP_WRITE | ||
555 | b cpu_resume_mmu | 551 | b cpu_resume_mmu |
556 | ENDPROC(cpu_xscale_do_resume) | 552 | ENDPROC(cpu_xscale_do_resume) |
557 | #endif | 553 | #endif |