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-rw-r--r--drivers/regulator/Kconfig7
-rw-r--r--drivers/regulator/Makefile1
-rw-r--r--drivers/regulator/wm831x-dcdc.c643
-rw-r--r--include/linux/mfd/wm831x/regulator.h571
4 files changed, 1222 insertions, 0 deletions
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index da7483ef32b3..38ea5dc8e143 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -82,6 +82,13 @@ config REGULATOR_TWL4030
82 This driver supports the voltage regulators provided by 82 This driver supports the voltage regulators provided by
83 this family of companion chips. 83 this family of companion chips.
84 84
85config REGULATOR_WM831X
86 tristate "Wolfson Microelcronics WM831x PMIC regulators"
87 depends on MFD_WM831X
88 help
89 Support the voltage and current regulators of the WM831x series
90 of PMIC devices.
91
85config REGULATOR_WM8350 92config REGULATOR_WM8350
86 tristate "Wolfson Microelectroncis WM8350 AudioPlus PMIC" 93 tristate "Wolfson Microelectroncis WM8350 AudioPlus PMIC"
87 depends on MFD_WM8350 94 depends on MFD_WM8350
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index 3a9748ff860b..b1d2b826f532 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_REGULATOR_BQ24022) += bq24022.o
12obj-$(CONFIG_REGULATOR_LP3971) += lp3971.o 12obj-$(CONFIG_REGULATOR_LP3971) += lp3971.o
13obj-$(CONFIG_REGULATOR_MAX1586) += max1586.o 13obj-$(CONFIG_REGULATOR_MAX1586) += max1586.o
14obj-$(CONFIG_REGULATOR_TWL4030) += twl4030-regulator.o 14obj-$(CONFIG_REGULATOR_TWL4030) += twl4030-regulator.o
15obj-$(CONFIG_REGULATOR_WM831X) += wm831x-dcdc.o
15obj-$(CONFIG_REGULATOR_WM8350) += wm8350-regulator.o 16obj-$(CONFIG_REGULATOR_WM8350) += wm8350-regulator.o
16obj-$(CONFIG_REGULATOR_WM8400) += wm8400-regulator.o 17obj-$(CONFIG_REGULATOR_WM8400) += wm8400-regulator.o
17obj-$(CONFIG_REGULATOR_DA903X) += da903x.o 18obj-$(CONFIG_REGULATOR_DA903X) += da903x.o
diff --git a/drivers/regulator/wm831x-dcdc.c b/drivers/regulator/wm831x-dcdc.c
new file mode 100644
index 000000000000..fa5126e38acc
--- /dev/null
+++ b/drivers/regulator/wm831x-dcdc.c
@@ -0,0 +1,643 @@
1/*
2 * wm831x-dcdc.c -- DC-DC buck convertor driver for the WM831x series
3 *
4 * Copyright 2009 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/bitops.h>
18#include <linux/err.h>
19#include <linux/i2c.h>
20#include <linux/platform_device.h>
21#include <linux/regulator/driver.h>
22
23#include <linux/mfd/wm831x/core.h>
24#include <linux/mfd/wm831x/regulator.h>
25#include <linux/mfd/wm831x/pdata.h>
26
27#define WM831X_BUCKV_MAX_SELECTOR 0x68
28#define WM831X_BUCKP_MAX_SELECTOR 0x66
29
30#define WM831X_DCDC_MODE_FAST 0
31#define WM831X_DCDC_MODE_NORMAL 1
32#define WM831X_DCDC_MODE_IDLE 2
33#define WM831X_DCDC_MODE_STANDBY 3
34
35#define WM831X_DCDC_MAX_NAME 6
36
37/* Register offsets in control block */
38#define WM831X_DCDC_CONTROL_1 0
39#define WM831X_DCDC_CONTROL_2 1
40#define WM831X_DCDC_ON_CONFIG 2
41#define WM831X_DCDC_SLEEP_CONTROL 3
42
43/*
44 * Shared
45 */
46
47struct wm831x_dcdc {
48 char name[WM831X_DCDC_MAX_NAME];
49 struct regulator_desc desc;
50 int base;
51 struct wm831x *wm831x;
52 struct regulator_dev *regulator;
53};
54
55static int wm831x_dcdc_is_enabled(struct regulator_dev *rdev)
56{
57 struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
58 struct wm831x *wm831x = dcdc->wm831x;
59 int mask = 1 << rdev_get_id(rdev);
60 int reg;
61
62 reg = wm831x_reg_read(wm831x, WM831X_DCDC_ENABLE);
63 if (reg < 0)
64 return reg;
65
66 if (reg & mask)
67 return 1;
68 else
69 return 0;
70}
71
72static int wm831x_dcdc_enable(struct regulator_dev *rdev)
73{
74 struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
75 struct wm831x *wm831x = dcdc->wm831x;
76 int mask = 1 << rdev_get_id(rdev);
77
78 return wm831x_set_bits(wm831x, WM831X_DCDC_ENABLE, mask, mask);
79}
80
81static int wm831x_dcdc_disable(struct regulator_dev *rdev)
82{
83 struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
84 struct wm831x *wm831x = dcdc->wm831x;
85 int mask = 1 << rdev_get_id(rdev);
86
87 return wm831x_set_bits(wm831x, WM831X_DCDC_ENABLE, mask, 0);
88}
89
90static unsigned int wm831x_dcdc_get_mode(struct regulator_dev *rdev)
91
92{
93 struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
94 struct wm831x *wm831x = dcdc->wm831x;
95 u16 reg = dcdc->base + WM831X_DCDC_ON_CONFIG;
96 int val;
97
98 val = wm831x_reg_read(wm831x, reg);
99 if (val < 0)
100 return val;
101
102 val = (val & WM831X_DC1_ON_MODE_MASK) >> WM831X_DC1_ON_MODE_SHIFT;
103
104 switch (val) {
105 case WM831X_DCDC_MODE_FAST:
106 return REGULATOR_MODE_FAST;
107 case WM831X_DCDC_MODE_NORMAL:
108 return REGULATOR_MODE_NORMAL;
109 case WM831X_DCDC_MODE_STANDBY:
110 return REGULATOR_MODE_STANDBY;
111 case WM831X_DCDC_MODE_IDLE:
112 return REGULATOR_MODE_IDLE;
113 default:
114 BUG();
115 }
116}
117
118static int wm831x_dcdc_set_mode_int(struct wm831x *wm831x, int reg,
119 unsigned int mode)
120{
121 int val;
122
123 switch (mode) {
124 case REGULATOR_MODE_FAST:
125 val = WM831X_DCDC_MODE_FAST;
126 break;
127 case REGULATOR_MODE_NORMAL:
128 val = WM831X_DCDC_MODE_NORMAL;
129 break;
130 case REGULATOR_MODE_STANDBY:
131 val = WM831X_DCDC_MODE_STANDBY;
132 break;
133 case REGULATOR_MODE_IDLE:
134 val = WM831X_DCDC_MODE_IDLE;
135 break;
136 default:
137 return -EINVAL;
138 }
139
140 return wm831x_set_bits(wm831x, reg, WM831X_DC1_ON_MODE_MASK,
141 val << WM831X_DC1_ON_MODE_SHIFT);
142}
143
144static int wm831x_dcdc_set_mode(struct regulator_dev *rdev, unsigned int mode)
145{
146 struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
147 struct wm831x *wm831x = dcdc->wm831x;
148 u16 reg = dcdc->base + WM831X_DCDC_ON_CONFIG;
149
150 return wm831x_dcdc_set_mode_int(wm831x, reg, mode);
151}
152
153static int wm831x_dcdc_set_suspend_mode(struct regulator_dev *rdev,
154 unsigned int mode)
155{
156 struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
157 struct wm831x *wm831x = dcdc->wm831x;
158 u16 reg = dcdc->base + WM831X_DCDC_SLEEP_CONTROL;
159
160 return wm831x_dcdc_set_mode_int(wm831x, reg, mode);
161}
162
163static int wm831x_dcdc_get_status(struct regulator_dev *rdev)
164{
165 struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
166 struct wm831x *wm831x = dcdc->wm831x;
167 int ret;
168
169 /* First, check for errors */
170 ret = wm831x_reg_read(wm831x, WM831X_DCDC_UV_STATUS);
171 if (ret < 0)
172 return ret;
173
174 if (ret & (1 << rdev_get_id(rdev))) {
175 dev_dbg(wm831x->dev, "DCDC%d under voltage\n",
176 rdev_get_id(rdev) + 1);
177 return REGULATOR_STATUS_ERROR;
178 }
179
180 /* DCDC1 and DCDC2 can additionally detect high voltage/current */
181 if (rdev_get_id(rdev) < 2) {
182 if (ret & (WM831X_DC1_OV_STS << rdev_get_id(rdev))) {
183 dev_dbg(wm831x->dev, "DCDC%d over voltage\n",
184 rdev_get_id(rdev) + 1);
185 return REGULATOR_STATUS_ERROR;
186 }
187
188 if (ret & (WM831X_DC1_HC_STS << rdev_get_id(rdev))) {
189 dev_dbg(wm831x->dev, "DCDC%d over current\n",
190 rdev_get_id(rdev) + 1);
191 return REGULATOR_STATUS_ERROR;
192 }
193 }
194
195 /* Is the regulator on? */
196 ret = wm831x_reg_read(wm831x, WM831X_DCDC_STATUS);
197 if (ret < 0)
198 return ret;
199 if (!(ret & (1 << rdev_get_id(rdev))))
200 return REGULATOR_STATUS_OFF;
201
202 /* TODO: When we handle hardware control modes so we can report the
203 * current mode. */
204 return REGULATOR_STATUS_ON;
205}
206
207static irqreturn_t wm831x_dcdc_uv_irq(int irq, void *data)
208{
209 struct wm831x_dcdc *dcdc = data;
210
211 regulator_notifier_call_chain(dcdc->regulator,
212 REGULATOR_EVENT_UNDER_VOLTAGE,
213 NULL);
214
215 return IRQ_HANDLED;
216}
217
218static irqreturn_t wm831x_dcdc_oc_irq(int irq, void *data)
219{
220 struct wm831x_dcdc *dcdc = data;
221
222 regulator_notifier_call_chain(dcdc->regulator,
223 REGULATOR_EVENT_OVER_CURRENT,
224 NULL);
225
226 return IRQ_HANDLED;
227}
228
229/*
230 * BUCKV specifics
231 */
232
233static int wm831x_buckv_list_voltage(struct regulator_dev *rdev,
234 unsigned selector)
235{
236 if (selector <= 0x8)
237 return 600000;
238 if (selector <= WM831X_BUCKV_MAX_SELECTOR)
239 return 600000 + ((selector - 0x8) * 12500);
240 return -EINVAL;
241}
242
243static int wm831x_buckv_set_voltage_int(struct regulator_dev *rdev, int reg,
244 int min_uV, int max_uV)
245{
246 struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
247 struct wm831x *wm831x = dcdc->wm831x;
248 u16 vsel;
249
250 if (min_uV < 600000)
251 vsel = 0;
252 else if (min_uV <= 1800000)
253 vsel = ((min_uV - 600000) / 12500) + 8;
254 else
255 return -EINVAL;
256
257 if (wm831x_buckv_list_voltage(rdev, vsel) > max_uV)
258 return -EINVAL;
259
260 return wm831x_set_bits(wm831x, reg, WM831X_DC1_ON_VSEL_MASK, vsel);
261}
262
263static int wm831x_buckv_set_voltage(struct regulator_dev *rdev,
264 int min_uV, int max_uV)
265{
266 struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
267 u16 reg = dcdc->base + WM831X_DCDC_ON_CONFIG;
268
269 return wm831x_buckv_set_voltage_int(rdev, reg, min_uV, max_uV);
270}
271
272static int wm831x_buckv_set_suspend_voltage(struct regulator_dev *rdev,
273 int uV)
274{
275 struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
276 u16 reg = dcdc->base + WM831X_DCDC_SLEEP_CONTROL;
277
278 return wm831x_buckv_set_voltage_int(rdev, reg, uV, uV);
279}
280
281static int wm831x_buckv_get_voltage(struct regulator_dev *rdev)
282{
283 struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
284 struct wm831x *wm831x = dcdc->wm831x;
285 u16 reg = dcdc->base + WM831X_DCDC_ON_CONFIG;
286 int val;
287
288 val = wm831x_reg_read(wm831x, reg);
289 if (val < 0)
290 return val;
291
292 return wm831x_buckv_list_voltage(rdev, val & WM831X_DC1_ON_VSEL_MASK);
293}
294
295/* Current limit options */
296static u16 wm831x_dcdc_ilim[] = {
297 125, 250, 375, 500, 625, 750, 875, 1000
298};
299
300static int wm831x_buckv_set_current_limit(struct regulator_dev *rdev,
301 int min_uA, int max_uA)
302{
303 struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
304 struct wm831x *wm831x = dcdc->wm831x;
305 u16 reg = dcdc->base + WM831X_DCDC_CONTROL_2;
306 int i;
307
308 for (i = 0; i < ARRAY_SIZE(wm831x_dcdc_ilim); i++) {
309 if (max_uA <= wm831x_dcdc_ilim[i])
310 break;
311 }
312 if (i == ARRAY_SIZE(wm831x_dcdc_ilim))
313 return -EINVAL;
314
315 return wm831x_set_bits(wm831x, reg, WM831X_DC1_HC_THR_MASK, i);
316}
317
318static int wm831x_buckv_get_current_limit(struct regulator_dev *rdev)
319{
320 struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
321 struct wm831x *wm831x = dcdc->wm831x;
322 u16 reg = dcdc->base + WM831X_DCDC_CONTROL_2;
323 int val;
324
325 val = wm831x_reg_read(wm831x, reg);
326 if (val < 0)
327 return val;
328
329 return wm831x_dcdc_ilim[val & WM831X_DC1_HC_THR_MASK];
330}
331
332static struct regulator_ops wm831x_buckv_ops = {
333 .set_voltage = wm831x_buckv_set_voltage,
334 .get_voltage = wm831x_buckv_get_voltage,
335 .list_voltage = wm831x_buckv_list_voltage,
336 .set_suspend_voltage = wm831x_buckv_set_suspend_voltage,
337 .set_current_limit = wm831x_buckv_set_current_limit,
338 .get_current_limit = wm831x_buckv_get_current_limit,
339
340 .is_enabled = wm831x_dcdc_is_enabled,
341 .enable = wm831x_dcdc_enable,
342 .disable = wm831x_dcdc_disable,
343 .get_status = wm831x_dcdc_get_status,
344 .get_mode = wm831x_dcdc_get_mode,
345 .set_mode = wm831x_dcdc_set_mode,
346 .set_suspend_mode = wm831x_dcdc_set_suspend_mode,
347};
348
349static __devinit int wm831x_buckv_probe(struct platform_device *pdev)
350{
351 struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);
352 struct wm831x_pdata *pdata = wm831x->dev->platform_data;
353 int id = pdev->id % ARRAY_SIZE(pdata->dcdc);
354 struct wm831x_dcdc *dcdc;
355 struct resource *res;
356 int ret, irq;
357
358 dev_dbg(&pdev->dev, "Probing DCDC%d\n", id + 1);
359
360 if (pdata == NULL || pdata->dcdc[id] == NULL)
361 return -ENODEV;
362
363 dcdc = kzalloc(sizeof(struct wm831x_dcdc), GFP_KERNEL);
364 if (dcdc == NULL) {
365 dev_err(&pdev->dev, "Unable to allocate private data\n");
366 return -ENOMEM;
367 }
368
369 dcdc->wm831x = wm831x;
370
371 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
372 if (res == NULL) {
373 dev_err(&pdev->dev, "No I/O resource\n");
374 ret = -EINVAL;
375 goto err;
376 }
377 dcdc->base = res->start;
378
379 snprintf(dcdc->name, sizeof(dcdc->name), "DCDC%d", id + 1);
380 dcdc->desc.name = dcdc->name;
381 dcdc->desc.id = id;
382 dcdc->desc.type = REGULATOR_VOLTAGE;
383 dcdc->desc.n_voltages = WM831X_BUCKV_MAX_SELECTOR + 1;
384 dcdc->desc.ops = &wm831x_buckv_ops;
385 dcdc->desc.owner = THIS_MODULE;
386
387 dcdc->regulator = regulator_register(&dcdc->desc, &pdev->dev,
388 pdata->dcdc[id], dcdc);
389 if (IS_ERR(dcdc->regulator)) {
390 ret = PTR_ERR(dcdc->regulator);
391 dev_err(wm831x->dev, "Failed to register DCDC%d: %d\n",
392 id + 1, ret);
393 goto err;
394 }
395
396 irq = platform_get_irq_byname(pdev, "UV");
397 ret = wm831x_request_irq(wm831x, irq, wm831x_dcdc_uv_irq,
398 IRQF_TRIGGER_RISING, dcdc->name,
399 dcdc);
400 if (ret != 0) {
401 dev_err(&pdev->dev, "Failed to request UV IRQ %d: %d\n",
402 irq, ret);
403 goto err_regulator;
404 }
405
406 irq = platform_get_irq_byname(pdev, "HC");
407 ret = wm831x_request_irq(wm831x, irq, wm831x_dcdc_oc_irq,
408 IRQF_TRIGGER_RISING, dcdc->name,
409 dcdc);
410 if (ret != 0) {
411 dev_err(&pdev->dev, "Failed to request HC IRQ %d: %d\n",
412 irq, ret);
413 goto err_uv;
414 }
415
416 platform_set_drvdata(pdev, dcdc);
417
418 return 0;
419
420err_uv:
421 wm831x_free_irq(wm831x, platform_get_irq_byname(pdev, "UV"), dcdc);
422err_regulator:
423 regulator_unregister(dcdc->regulator);
424err:
425 kfree(dcdc);
426 return ret;
427}
428
429static __devexit int wm831x_buckv_remove(struct platform_device *pdev)
430{
431 struct wm831x_dcdc *dcdc = platform_get_drvdata(pdev);
432 struct wm831x *wm831x = dcdc->wm831x;
433
434 wm831x_free_irq(wm831x, platform_get_irq_byname(pdev, "HC"), dcdc);
435 wm831x_free_irq(wm831x, platform_get_irq_byname(pdev, "UV"), dcdc);
436 regulator_unregister(dcdc->regulator);
437 kfree(dcdc);
438
439 return 0;
440}
441
442static struct platform_driver wm831x_buckv_driver = {
443 .probe = wm831x_buckv_probe,
444 .remove = __devexit_p(wm831x_buckv_remove),
445 .driver = {
446 .name = "wm831x-buckv",
447 },
448};
449
450/*
451 * BUCKP specifics
452 */
453
454static int wm831x_buckp_list_voltage(struct regulator_dev *rdev,
455 unsigned selector)
456{
457 if (selector <= WM831X_BUCKP_MAX_SELECTOR)
458 return 850000 + (selector * 25000);
459 else
460 return -EINVAL;
461}
462
463static int wm831x_buckp_set_voltage_int(struct regulator_dev *rdev, int reg,
464 int min_uV, int max_uV)
465{
466 struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
467 struct wm831x *wm831x = dcdc->wm831x;
468 u16 vsel;
469
470 if (min_uV <= 34000000)
471 vsel = (min_uV - 850000) / 25000;
472 else
473 return -EINVAL;
474
475 if (wm831x_buckp_list_voltage(rdev, vsel) > max_uV)
476 return -EINVAL;
477
478 return wm831x_set_bits(wm831x, reg, WM831X_DC3_ON_VSEL_MASK, vsel);
479}
480
481static int wm831x_buckp_set_voltage(struct regulator_dev *rdev,
482 int min_uV, int max_uV)
483{
484 struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
485 u16 reg = dcdc->base + WM831X_DCDC_ON_CONFIG;
486
487 return wm831x_buckp_set_voltage_int(rdev, reg, min_uV, max_uV);
488}
489
490static int wm831x_buckp_set_suspend_voltage(struct regulator_dev *rdev,
491 int uV)
492{
493 struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
494 u16 reg = dcdc->base + WM831X_DCDC_SLEEP_CONTROL;
495
496 return wm831x_buckp_set_voltage_int(rdev, reg, uV, uV);
497}
498
499static int wm831x_buckp_get_voltage(struct regulator_dev *rdev)
500{
501 struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
502 struct wm831x *wm831x = dcdc->wm831x;
503 u16 reg = dcdc->base + WM831X_DCDC_ON_CONFIG;
504 int val;
505
506 val = wm831x_reg_read(wm831x, reg);
507 if (val < 0)
508 return val;
509
510 return wm831x_buckp_list_voltage(rdev, val & WM831X_DC3_ON_VSEL_MASK);
511}
512
513static struct regulator_ops wm831x_buckp_ops = {
514 .set_voltage = wm831x_buckp_set_voltage,
515 .get_voltage = wm831x_buckp_get_voltage,
516 .list_voltage = wm831x_buckp_list_voltage,
517 .set_suspend_voltage = wm831x_buckp_set_suspend_voltage,
518
519 .is_enabled = wm831x_dcdc_is_enabled,
520 .enable = wm831x_dcdc_enable,
521 .disable = wm831x_dcdc_disable,
522 .get_status = wm831x_dcdc_get_status,
523 .get_mode = wm831x_dcdc_get_mode,
524 .set_mode = wm831x_dcdc_set_mode,
525 .set_suspend_mode = wm831x_dcdc_set_suspend_mode,
526};
527
528static __devinit int wm831x_buckp_probe(struct platform_device *pdev)
529{
530 struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);
531 struct wm831x_pdata *pdata = wm831x->dev->platform_data;
532 int id = pdev->id % ARRAY_SIZE(pdata->dcdc);
533 struct wm831x_dcdc *dcdc;
534 struct resource *res;
535 int ret, irq;
536
537 dev_dbg(&pdev->dev, "Probing DCDC%d\n", id + 1);
538
539 if (pdata == NULL || pdata->dcdc[id] == NULL)
540 return -ENODEV;
541
542 dcdc = kzalloc(sizeof(struct wm831x_dcdc), GFP_KERNEL);
543 if (dcdc == NULL) {
544 dev_err(&pdev->dev, "Unable to allocate private data\n");
545 return -ENOMEM;
546 }
547
548 dcdc->wm831x = wm831x;
549
550 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
551 if (res == NULL) {
552 dev_err(&pdev->dev, "No I/O resource\n");
553 ret = -EINVAL;
554 goto err;
555 }
556 dcdc->base = res->start;
557
558 snprintf(dcdc->name, sizeof(dcdc->name), "DCDC%d", id + 1);
559 dcdc->desc.name = dcdc->name;
560 dcdc->desc.id = id;
561 dcdc->desc.type = REGULATOR_VOLTAGE;
562 dcdc->desc.n_voltages = WM831X_BUCKP_MAX_SELECTOR + 1;
563 dcdc->desc.ops = &wm831x_buckp_ops;
564 dcdc->desc.owner = THIS_MODULE;
565
566 dcdc->regulator = regulator_register(&dcdc->desc, &pdev->dev,
567 pdata->dcdc[id], dcdc);
568 if (IS_ERR(dcdc->regulator)) {
569 ret = PTR_ERR(dcdc->regulator);
570 dev_err(wm831x->dev, "Failed to register DCDC%d: %d\n",
571 id + 1, ret);
572 goto err;
573 }
574
575 irq = platform_get_irq_byname(pdev, "UV");
576 ret = wm831x_request_irq(wm831x, irq, wm831x_dcdc_uv_irq,
577 IRQF_TRIGGER_RISING, dcdc->name,
578 dcdc);
579 if (ret != 0) {
580 dev_err(&pdev->dev, "Failed to request UV IRQ %d: %d\n",
581 irq, ret);
582 goto err_regulator;
583 }
584
585 platform_set_drvdata(pdev, dcdc);
586
587 return 0;
588
589err_regulator:
590 regulator_unregister(dcdc->regulator);
591err:
592 kfree(dcdc);
593 return ret;
594}
595
596static __devexit int wm831x_buckp_remove(struct platform_device *pdev)
597{
598 struct wm831x_dcdc *dcdc = platform_get_drvdata(pdev);
599 struct wm831x *wm831x = dcdc->wm831x;
600
601 wm831x_free_irq(wm831x, platform_get_irq_byname(pdev, "UV"), dcdc);
602 regulator_unregister(dcdc->regulator);
603 kfree(dcdc);
604
605 return 0;
606}
607
608static struct platform_driver wm831x_buckp_driver = {
609 .probe = wm831x_buckp_probe,
610 .remove = __devexit_p(wm831x_buckp_remove),
611 .driver = {
612 .name = "wm831x-buckp",
613 },
614};
615
616static int __init wm831x_dcdc_init(void)
617{
618 int ret;
619 ret = platform_driver_register(&wm831x_buckv_driver);
620 if (ret != 0)
621 pr_err("Failed to register WM831x BUCKV driver: %d\n", ret);
622
623 ret = platform_driver_register(&wm831x_buckp_driver);
624 if (ret != 0)
625 pr_err("Failed to register WM831x BUCKP driver: %d\n", ret);
626
627 return 0;
628}
629subsys_initcall(wm831x_dcdc_init);
630
631static void __exit wm831x_dcdc_exit(void)
632{
633 platform_driver_unregister(&wm831x_buckp_driver);
634 platform_driver_unregister(&wm831x_buckv_driver);
635}
636module_exit(wm831x_dcdc_exit);
637
638/* Module information */
639MODULE_AUTHOR("Mark Brown");
640MODULE_DESCRIPTION("WM831x DC-DC convertor driver");
641MODULE_LICENSE("GPL");
642MODULE_ALIAS("platform:wm831x-buckv");
643MODULE_ALIAS("platform:wm831x-buckp");
diff --git a/include/linux/mfd/wm831x/regulator.h b/include/linux/mfd/wm831x/regulator.h
index b5d58fb38b4e..c74d6aafdca8 100644
--- a/include/linux/mfd/wm831x/regulator.h
+++ b/include/linux/mfd/wm831x/regulator.h
@@ -15,6 +15,577 @@
15#ifndef __MFD_WM831X_REGULATOR_H__ 15#ifndef __MFD_WM831X_REGULATOR_H__
16#define __MFD_WM831X_REGULATOR_H__ 16#define __MFD_WM831X_REGULATOR_H__
17 17
18/*
19 * R16462 (0x404E) - Current Sink 1
20 */
21#define WM831X_CS1_ENA 0x8000 /* CS1_ENA */
22#define WM831X_CS1_ENA_MASK 0x8000 /* CS1_ENA */
23#define WM831X_CS1_ENA_SHIFT 15 /* CS1_ENA */
24#define WM831X_CS1_ENA_WIDTH 1 /* CS1_ENA */
25#define WM831X_CS1_DRIVE 0x4000 /* CS1_DRIVE */
26#define WM831X_CS1_DRIVE_MASK 0x4000 /* CS1_DRIVE */
27#define WM831X_CS1_DRIVE_SHIFT 14 /* CS1_DRIVE */
28#define WM831X_CS1_DRIVE_WIDTH 1 /* CS1_DRIVE */
29#define WM831X_CS1_SLPENA 0x1000 /* CS1_SLPENA */
30#define WM831X_CS1_SLPENA_MASK 0x1000 /* CS1_SLPENA */
31#define WM831X_CS1_SLPENA_SHIFT 12 /* CS1_SLPENA */
32#define WM831X_CS1_SLPENA_WIDTH 1 /* CS1_SLPENA */
33#define WM831X_CS1_OFF_RAMP_MASK 0x0C00 /* CS1_OFF_RAMP - [11:10] */
34#define WM831X_CS1_OFF_RAMP_SHIFT 10 /* CS1_OFF_RAMP - [11:10] */
35#define WM831X_CS1_OFF_RAMP_WIDTH 2 /* CS1_OFF_RAMP - [11:10] */
36#define WM831X_CS1_ON_RAMP_MASK 0x0300 /* CS1_ON_RAMP - [9:8] */
37#define WM831X_CS1_ON_RAMP_SHIFT 8 /* CS1_ON_RAMP - [9:8] */
38#define WM831X_CS1_ON_RAMP_WIDTH 2 /* CS1_ON_RAMP - [9:8] */
39#define WM831X_CS1_ISEL_MASK 0x003F /* CS1_ISEL - [5:0] */
40#define WM831X_CS1_ISEL_SHIFT 0 /* CS1_ISEL - [5:0] */
41#define WM831X_CS1_ISEL_WIDTH 6 /* CS1_ISEL - [5:0] */
42
43/*
44 * R16463 (0x404F) - Current Sink 2
45 */
46#define WM831X_CS2_ENA 0x8000 /* CS2_ENA */
47#define WM831X_CS2_ENA_MASK 0x8000 /* CS2_ENA */
48#define WM831X_CS2_ENA_SHIFT 15 /* CS2_ENA */
49#define WM831X_CS2_ENA_WIDTH 1 /* CS2_ENA */
50#define WM831X_CS2_DRIVE 0x4000 /* CS2_DRIVE */
51#define WM831X_CS2_DRIVE_MASK 0x4000 /* CS2_DRIVE */
52#define WM831X_CS2_DRIVE_SHIFT 14 /* CS2_DRIVE */
53#define WM831X_CS2_DRIVE_WIDTH 1 /* CS2_DRIVE */
54#define WM831X_CS2_SLPENA 0x1000 /* CS2_SLPENA */
55#define WM831X_CS2_SLPENA_MASK 0x1000 /* CS2_SLPENA */
56#define WM831X_CS2_SLPENA_SHIFT 12 /* CS2_SLPENA */
57#define WM831X_CS2_SLPENA_WIDTH 1 /* CS2_SLPENA */
58#define WM831X_CS2_OFF_RAMP_MASK 0x0C00 /* CS2_OFF_RAMP - [11:10] */
59#define WM831X_CS2_OFF_RAMP_SHIFT 10 /* CS2_OFF_RAMP - [11:10] */
60#define WM831X_CS2_OFF_RAMP_WIDTH 2 /* CS2_OFF_RAMP - [11:10] */
61#define WM831X_CS2_ON_RAMP_MASK 0x0300 /* CS2_ON_RAMP - [9:8] */
62#define WM831X_CS2_ON_RAMP_SHIFT 8 /* CS2_ON_RAMP - [9:8] */
63#define WM831X_CS2_ON_RAMP_WIDTH 2 /* CS2_ON_RAMP - [9:8] */
64#define WM831X_CS2_ISEL_MASK 0x003F /* CS2_ISEL - [5:0] */
65#define WM831X_CS2_ISEL_SHIFT 0 /* CS2_ISEL - [5:0] */
66#define WM831X_CS2_ISEL_WIDTH 6 /* CS2_ISEL - [5:0] */
67
68/*
69 * R16464 (0x4050) - DCDC Enable
70 */
71#define WM831X_EPE2_ENA 0x0080 /* EPE2_ENA */
72#define WM831X_EPE2_ENA_MASK 0x0080 /* EPE2_ENA */
73#define WM831X_EPE2_ENA_SHIFT 7 /* EPE2_ENA */
74#define WM831X_EPE2_ENA_WIDTH 1 /* EPE2_ENA */
75#define WM831X_EPE1_ENA 0x0040 /* EPE1_ENA */
76#define WM831X_EPE1_ENA_MASK 0x0040 /* EPE1_ENA */
77#define WM831X_EPE1_ENA_SHIFT 6 /* EPE1_ENA */
78#define WM831X_EPE1_ENA_WIDTH 1 /* EPE1_ENA */
79#define WM831X_DC4_ENA 0x0008 /* DC4_ENA */
80#define WM831X_DC4_ENA_MASK 0x0008 /* DC4_ENA */
81#define WM831X_DC4_ENA_SHIFT 3 /* DC4_ENA */
82#define WM831X_DC4_ENA_WIDTH 1 /* DC4_ENA */
83#define WM831X_DC3_ENA 0x0004 /* DC3_ENA */
84#define WM831X_DC3_ENA_MASK 0x0004 /* DC3_ENA */
85#define WM831X_DC3_ENA_SHIFT 2 /* DC3_ENA */
86#define WM831X_DC3_ENA_WIDTH 1 /* DC3_ENA */
87#define WM831X_DC2_ENA 0x0002 /* DC2_ENA */
88#define WM831X_DC2_ENA_MASK 0x0002 /* DC2_ENA */
89#define WM831X_DC2_ENA_SHIFT 1 /* DC2_ENA */
90#define WM831X_DC2_ENA_WIDTH 1 /* DC2_ENA */
91#define WM831X_DC1_ENA 0x0001 /* DC1_ENA */
92#define WM831X_DC1_ENA_MASK 0x0001 /* DC1_ENA */
93#define WM831X_DC1_ENA_SHIFT 0 /* DC1_ENA */
94#define WM831X_DC1_ENA_WIDTH 1 /* DC1_ENA */
95
96/*
97 * R16465 (0x4051) - LDO Enable
98 */
99#define WM831X_LDO11_ENA 0x0400 /* LDO11_ENA */
100#define WM831X_LDO11_ENA_MASK 0x0400 /* LDO11_ENA */
101#define WM831X_LDO11_ENA_SHIFT 10 /* LDO11_ENA */
102#define WM831X_LDO11_ENA_WIDTH 1 /* LDO11_ENA */
103#define WM831X_LDO10_ENA 0x0200 /* LDO10_ENA */
104#define WM831X_LDO10_ENA_MASK 0x0200 /* LDO10_ENA */
105#define WM831X_LDO10_ENA_SHIFT 9 /* LDO10_ENA */
106#define WM831X_LDO10_ENA_WIDTH 1 /* LDO10_ENA */
107#define WM831X_LDO9_ENA 0x0100 /* LDO9_ENA */
108#define WM831X_LDO9_ENA_MASK 0x0100 /* LDO9_ENA */
109#define WM831X_LDO9_ENA_SHIFT 8 /* LDO9_ENA */
110#define WM831X_LDO9_ENA_WIDTH 1 /* LDO9_ENA */
111#define WM831X_LDO8_ENA 0x0080 /* LDO8_ENA */
112#define WM831X_LDO8_ENA_MASK 0x0080 /* LDO8_ENA */
113#define WM831X_LDO8_ENA_SHIFT 7 /* LDO8_ENA */
114#define WM831X_LDO8_ENA_WIDTH 1 /* LDO8_ENA */
115#define WM831X_LDO7_ENA 0x0040 /* LDO7_ENA */
116#define WM831X_LDO7_ENA_MASK 0x0040 /* LDO7_ENA */
117#define WM831X_LDO7_ENA_SHIFT 6 /* LDO7_ENA */
118#define WM831X_LDO7_ENA_WIDTH 1 /* LDO7_ENA */
119#define WM831X_LDO6_ENA 0x0020 /* LDO6_ENA */
120#define WM831X_LDO6_ENA_MASK 0x0020 /* LDO6_ENA */
121#define WM831X_LDO6_ENA_SHIFT 5 /* LDO6_ENA */
122#define WM831X_LDO6_ENA_WIDTH 1 /* LDO6_ENA */
123#define WM831X_LDO5_ENA 0x0010 /* LDO5_ENA */
124#define WM831X_LDO5_ENA_MASK 0x0010 /* LDO5_ENA */
125#define WM831X_LDO5_ENA_SHIFT 4 /* LDO5_ENA */
126#define WM831X_LDO5_ENA_WIDTH 1 /* LDO5_ENA */
127#define WM831X_LDO4_ENA 0x0008 /* LDO4_ENA */
128#define WM831X_LDO4_ENA_MASK 0x0008 /* LDO4_ENA */
129#define WM831X_LDO4_ENA_SHIFT 3 /* LDO4_ENA */
130#define WM831X_LDO4_ENA_WIDTH 1 /* LDO4_ENA */
131#define WM831X_LDO3_ENA 0x0004 /* LDO3_ENA */
132#define WM831X_LDO3_ENA_MASK 0x0004 /* LDO3_ENA */
133#define WM831X_LDO3_ENA_SHIFT 2 /* LDO3_ENA */
134#define WM831X_LDO3_ENA_WIDTH 1 /* LDO3_ENA */
135#define WM831X_LDO2_ENA 0x0002 /* LDO2_ENA */
136#define WM831X_LDO2_ENA_MASK 0x0002 /* LDO2_ENA */
137#define WM831X_LDO2_ENA_SHIFT 1 /* LDO2_ENA */
138#define WM831X_LDO2_ENA_WIDTH 1 /* LDO2_ENA */
139#define WM831X_LDO1_ENA 0x0001 /* LDO1_ENA */
140#define WM831X_LDO1_ENA_MASK 0x0001 /* LDO1_ENA */
141#define WM831X_LDO1_ENA_SHIFT 0 /* LDO1_ENA */
142#define WM831X_LDO1_ENA_WIDTH 1 /* LDO1_ENA */
143
144/*
145 * R16466 (0x4052) - DCDC Status
146 */
147#define WM831X_EPE2_STS 0x0080 /* EPE2_STS */
148#define WM831X_EPE2_STS_MASK 0x0080 /* EPE2_STS */
149#define WM831X_EPE2_STS_SHIFT 7 /* EPE2_STS */
150#define WM831X_EPE2_STS_WIDTH 1 /* EPE2_STS */
151#define WM831X_EPE1_STS 0x0040 /* EPE1_STS */
152#define WM831X_EPE1_STS_MASK 0x0040 /* EPE1_STS */
153#define WM831X_EPE1_STS_SHIFT 6 /* EPE1_STS */
154#define WM831X_EPE1_STS_WIDTH 1 /* EPE1_STS */
155#define WM831X_DC4_STS 0x0008 /* DC4_STS */
156#define WM831X_DC4_STS_MASK 0x0008 /* DC4_STS */
157#define WM831X_DC4_STS_SHIFT 3 /* DC4_STS */
158#define WM831X_DC4_STS_WIDTH 1 /* DC4_STS */
159#define WM831X_DC3_STS 0x0004 /* DC3_STS */
160#define WM831X_DC3_STS_MASK 0x0004 /* DC3_STS */
161#define WM831X_DC3_STS_SHIFT 2 /* DC3_STS */
162#define WM831X_DC3_STS_WIDTH 1 /* DC3_STS */
163#define WM831X_DC2_STS 0x0002 /* DC2_STS */
164#define WM831X_DC2_STS_MASK 0x0002 /* DC2_STS */
165#define WM831X_DC2_STS_SHIFT 1 /* DC2_STS */
166#define WM831X_DC2_STS_WIDTH 1 /* DC2_STS */
167#define WM831X_DC1_STS 0x0001 /* DC1_STS */
168#define WM831X_DC1_STS_MASK 0x0001 /* DC1_STS */
169#define WM831X_DC1_STS_SHIFT 0 /* DC1_STS */
170#define WM831X_DC1_STS_WIDTH 1 /* DC1_STS */
171
172/*
173 * R16467 (0x4053) - LDO Status
174 */
175#define WM831X_LDO11_STS 0x0400 /* LDO11_STS */
176#define WM831X_LDO11_STS_MASK 0x0400 /* LDO11_STS */
177#define WM831X_LDO11_STS_SHIFT 10 /* LDO11_STS */
178#define WM831X_LDO11_STS_WIDTH 1 /* LDO11_STS */
179#define WM831X_LDO10_STS 0x0200 /* LDO10_STS */
180#define WM831X_LDO10_STS_MASK 0x0200 /* LDO10_STS */
181#define WM831X_LDO10_STS_SHIFT 9 /* LDO10_STS */
182#define WM831X_LDO10_STS_WIDTH 1 /* LDO10_STS */
183#define WM831X_LDO9_STS 0x0100 /* LDO9_STS */
184#define WM831X_LDO9_STS_MASK 0x0100 /* LDO9_STS */
185#define WM831X_LDO9_STS_SHIFT 8 /* LDO9_STS */
186#define WM831X_LDO9_STS_WIDTH 1 /* LDO9_STS */
187#define WM831X_LDO8_STS 0x0080 /* LDO8_STS */
188#define WM831X_LDO8_STS_MASK 0x0080 /* LDO8_STS */
189#define WM831X_LDO8_STS_SHIFT 7 /* LDO8_STS */
190#define WM831X_LDO8_STS_WIDTH 1 /* LDO8_STS */
191#define WM831X_LDO7_STS 0x0040 /* LDO7_STS */
192#define WM831X_LDO7_STS_MASK 0x0040 /* LDO7_STS */
193#define WM831X_LDO7_STS_SHIFT 6 /* LDO7_STS */
194#define WM831X_LDO7_STS_WIDTH 1 /* LDO7_STS */
195#define WM831X_LDO6_STS 0x0020 /* LDO6_STS */
196#define WM831X_LDO6_STS_MASK 0x0020 /* LDO6_STS */
197#define WM831X_LDO6_STS_SHIFT 5 /* LDO6_STS */
198#define WM831X_LDO6_STS_WIDTH 1 /* LDO6_STS */
199#define WM831X_LDO5_STS 0x0010 /* LDO5_STS */
200#define WM831X_LDO5_STS_MASK 0x0010 /* LDO5_STS */
201#define WM831X_LDO5_STS_SHIFT 4 /* LDO5_STS */
202#define WM831X_LDO5_STS_WIDTH 1 /* LDO5_STS */
203#define WM831X_LDO4_STS 0x0008 /* LDO4_STS */
204#define WM831X_LDO4_STS_MASK 0x0008 /* LDO4_STS */
205#define WM831X_LDO4_STS_SHIFT 3 /* LDO4_STS */
206#define WM831X_LDO4_STS_WIDTH 1 /* LDO4_STS */
207#define WM831X_LDO3_STS 0x0004 /* LDO3_STS */
208#define WM831X_LDO3_STS_MASK 0x0004 /* LDO3_STS */
209#define WM831X_LDO3_STS_SHIFT 2 /* LDO3_STS */
210#define WM831X_LDO3_STS_WIDTH 1 /* LDO3_STS */
211#define WM831X_LDO2_STS 0x0002 /* LDO2_STS */
212#define WM831X_LDO2_STS_MASK 0x0002 /* LDO2_STS */
213#define WM831X_LDO2_STS_SHIFT 1 /* LDO2_STS */
214#define WM831X_LDO2_STS_WIDTH 1 /* LDO2_STS */
215#define WM831X_LDO1_STS 0x0001 /* LDO1_STS */
216#define WM831X_LDO1_STS_MASK 0x0001 /* LDO1_STS */
217#define WM831X_LDO1_STS_SHIFT 0 /* LDO1_STS */
218#define WM831X_LDO1_STS_WIDTH 1 /* LDO1_STS */
219
220/*
221 * R16468 (0x4054) - DCDC UV Status
222 */
223#define WM831X_DC2_OV_STS 0x2000 /* DC2_OV_STS */
224#define WM831X_DC2_OV_STS_MASK 0x2000 /* DC2_OV_STS */
225#define WM831X_DC2_OV_STS_SHIFT 13 /* DC2_OV_STS */
226#define WM831X_DC2_OV_STS_WIDTH 1 /* DC2_OV_STS */
227#define WM831X_DC1_OV_STS 0x1000 /* DC1_OV_STS */
228#define WM831X_DC1_OV_STS_MASK 0x1000 /* DC1_OV_STS */
229#define WM831X_DC1_OV_STS_SHIFT 12 /* DC1_OV_STS */
230#define WM831X_DC1_OV_STS_WIDTH 1 /* DC1_OV_STS */
231#define WM831X_DC2_HC_STS 0x0200 /* DC2_HC_STS */
232#define WM831X_DC2_HC_STS_MASK 0x0200 /* DC2_HC_STS */
233#define WM831X_DC2_HC_STS_SHIFT 9 /* DC2_HC_STS */
234#define WM831X_DC2_HC_STS_WIDTH 1 /* DC2_HC_STS */
235#define WM831X_DC1_HC_STS 0x0100 /* DC1_HC_STS */
236#define WM831X_DC1_HC_STS_MASK 0x0100 /* DC1_HC_STS */
237#define WM831X_DC1_HC_STS_SHIFT 8 /* DC1_HC_STS */
238#define WM831X_DC1_HC_STS_WIDTH 1 /* DC1_HC_STS */
239#define WM831X_DC4_UV_STS 0x0008 /* DC4_UV_STS */
240#define WM831X_DC4_UV_STS_MASK 0x0008 /* DC4_UV_STS */
241#define WM831X_DC4_UV_STS_SHIFT 3 /* DC4_UV_STS */
242#define WM831X_DC4_UV_STS_WIDTH 1 /* DC4_UV_STS */
243#define WM831X_DC3_UV_STS 0x0004 /* DC3_UV_STS */
244#define WM831X_DC3_UV_STS_MASK 0x0004 /* DC3_UV_STS */
245#define WM831X_DC3_UV_STS_SHIFT 2 /* DC3_UV_STS */
246#define WM831X_DC3_UV_STS_WIDTH 1 /* DC3_UV_STS */
247#define WM831X_DC2_UV_STS 0x0002 /* DC2_UV_STS */
248#define WM831X_DC2_UV_STS_MASK 0x0002 /* DC2_UV_STS */
249#define WM831X_DC2_UV_STS_SHIFT 1 /* DC2_UV_STS */
250#define WM831X_DC2_UV_STS_WIDTH 1 /* DC2_UV_STS */
251#define WM831X_DC1_UV_STS 0x0001 /* DC1_UV_STS */
252#define WM831X_DC1_UV_STS_MASK 0x0001 /* DC1_UV_STS */
253#define WM831X_DC1_UV_STS_SHIFT 0 /* DC1_UV_STS */
254#define WM831X_DC1_UV_STS_WIDTH 1 /* DC1_UV_STS */
255
256/*
257 * R16469 (0x4055) - LDO UV Status
258 */
259#define WM831X_INTLDO_UV_STS 0x8000 /* INTLDO_UV_STS */
260#define WM831X_INTLDO_UV_STS_MASK 0x8000 /* INTLDO_UV_STS */
261#define WM831X_INTLDO_UV_STS_SHIFT 15 /* INTLDO_UV_STS */
262#define WM831X_INTLDO_UV_STS_WIDTH 1 /* INTLDO_UV_STS */
263#define WM831X_LDO10_UV_STS 0x0200 /* LDO10_UV_STS */
264#define WM831X_LDO10_UV_STS_MASK 0x0200 /* LDO10_UV_STS */
265#define WM831X_LDO10_UV_STS_SHIFT 9 /* LDO10_UV_STS */
266#define WM831X_LDO10_UV_STS_WIDTH 1 /* LDO10_UV_STS */
267#define WM831X_LDO9_UV_STS 0x0100 /* LDO9_UV_STS */
268#define WM831X_LDO9_UV_STS_MASK 0x0100 /* LDO9_UV_STS */
269#define WM831X_LDO9_UV_STS_SHIFT 8 /* LDO9_UV_STS */
270#define WM831X_LDO9_UV_STS_WIDTH 1 /* LDO9_UV_STS */
271#define WM831X_LDO8_UV_STS 0x0080 /* LDO8_UV_STS */
272#define WM831X_LDO8_UV_STS_MASK 0x0080 /* LDO8_UV_STS */
273#define WM831X_LDO8_UV_STS_SHIFT 7 /* LDO8_UV_STS */
274#define WM831X_LDO8_UV_STS_WIDTH 1 /* LDO8_UV_STS */
275#define WM831X_LDO7_UV_STS 0x0040 /* LDO7_UV_STS */
276#define WM831X_LDO7_UV_STS_MASK 0x0040 /* LDO7_UV_STS */
277#define WM831X_LDO7_UV_STS_SHIFT 6 /* LDO7_UV_STS */
278#define WM831X_LDO7_UV_STS_WIDTH 1 /* LDO7_UV_STS */
279#define WM831X_LDO6_UV_STS 0x0020 /* LDO6_UV_STS */
280#define WM831X_LDO6_UV_STS_MASK 0x0020 /* LDO6_UV_STS */
281#define WM831X_LDO6_UV_STS_SHIFT 5 /* LDO6_UV_STS */
282#define WM831X_LDO6_UV_STS_WIDTH 1 /* LDO6_UV_STS */
283#define WM831X_LDO5_UV_STS 0x0010 /* LDO5_UV_STS */
284#define WM831X_LDO5_UV_STS_MASK 0x0010 /* LDO5_UV_STS */
285#define WM831X_LDO5_UV_STS_SHIFT 4 /* LDO5_UV_STS */
286#define WM831X_LDO5_UV_STS_WIDTH 1 /* LDO5_UV_STS */
287#define WM831X_LDO4_UV_STS 0x0008 /* LDO4_UV_STS */
288#define WM831X_LDO4_UV_STS_MASK 0x0008 /* LDO4_UV_STS */
289#define WM831X_LDO4_UV_STS_SHIFT 3 /* LDO4_UV_STS */
290#define WM831X_LDO4_UV_STS_WIDTH 1 /* LDO4_UV_STS */
291#define WM831X_LDO3_UV_STS 0x0004 /* LDO3_UV_STS */
292#define WM831X_LDO3_UV_STS_MASK 0x0004 /* LDO3_UV_STS */
293#define WM831X_LDO3_UV_STS_SHIFT 2 /* LDO3_UV_STS */
294#define WM831X_LDO3_UV_STS_WIDTH 1 /* LDO3_UV_STS */
295#define WM831X_LDO2_UV_STS 0x0002 /* LDO2_UV_STS */
296#define WM831X_LDO2_UV_STS_MASK 0x0002 /* LDO2_UV_STS */
297#define WM831X_LDO2_UV_STS_SHIFT 1 /* LDO2_UV_STS */
298#define WM831X_LDO2_UV_STS_WIDTH 1 /* LDO2_UV_STS */
299#define WM831X_LDO1_UV_STS 0x0001 /* LDO1_UV_STS */
300#define WM831X_LDO1_UV_STS_MASK 0x0001 /* LDO1_UV_STS */
301#define WM831X_LDO1_UV_STS_SHIFT 0 /* LDO1_UV_STS */
302#define WM831X_LDO1_UV_STS_WIDTH 1 /* LDO1_UV_STS */
303
304/*
305 * R16470 (0x4056) - DC1 Control 1
306 */
307#define WM831X_DC1_RATE_MASK 0xC000 /* DC1_RATE - [15:14] */
308#define WM831X_DC1_RATE_SHIFT 14 /* DC1_RATE - [15:14] */
309#define WM831X_DC1_RATE_WIDTH 2 /* DC1_RATE - [15:14] */
310#define WM831X_DC1_PHASE 0x1000 /* DC1_PHASE */
311#define WM831X_DC1_PHASE_MASK 0x1000 /* DC1_PHASE */
312#define WM831X_DC1_PHASE_SHIFT 12 /* DC1_PHASE */
313#define WM831X_DC1_PHASE_WIDTH 1 /* DC1_PHASE */
314#define WM831X_DC1_FREQ_MASK 0x0300 /* DC1_FREQ - [9:8] */
315#define WM831X_DC1_FREQ_SHIFT 8 /* DC1_FREQ - [9:8] */
316#define WM831X_DC1_FREQ_WIDTH 2 /* DC1_FREQ - [9:8] */
317#define WM831X_DC1_FLT 0x0080 /* DC1_FLT */
318#define WM831X_DC1_FLT_MASK 0x0080 /* DC1_FLT */
319#define WM831X_DC1_FLT_SHIFT 7 /* DC1_FLT */
320#define WM831X_DC1_FLT_WIDTH 1 /* DC1_FLT */
321#define WM831X_DC1_SOFT_START_MASK 0x0030 /* DC1_SOFT_START - [5:4] */
322#define WM831X_DC1_SOFT_START_SHIFT 4 /* DC1_SOFT_START - [5:4] */
323#define WM831X_DC1_SOFT_START_WIDTH 2 /* DC1_SOFT_START - [5:4] */
324#define WM831X_DC1_CAP_MASK 0x0003 /* DC1_CAP - [1:0] */
325#define WM831X_DC1_CAP_SHIFT 0 /* DC1_CAP - [1:0] */
326#define WM831X_DC1_CAP_WIDTH 2 /* DC1_CAP - [1:0] */
327
328/*
329 * R16471 (0x4057) - DC1 Control 2
330 */
331#define WM831X_DC1_ERR_ACT_MASK 0xC000 /* DC1_ERR_ACT - [15:14] */
332#define WM831X_DC1_ERR_ACT_SHIFT 14 /* DC1_ERR_ACT - [15:14] */
333#define WM831X_DC1_ERR_ACT_WIDTH 2 /* DC1_ERR_ACT - [15:14] */
334#define WM831X_DC1_HWC_SRC_MASK 0x1800 /* DC1_HWC_SRC - [12:11] */
335#define WM831X_DC1_HWC_SRC_SHIFT 11 /* DC1_HWC_SRC - [12:11] */
336#define WM831X_DC1_HWC_SRC_WIDTH 2 /* DC1_HWC_SRC - [12:11] */
337#define WM831X_DC1_HWC_VSEL 0x0400 /* DC1_HWC_VSEL */
338#define WM831X_DC1_HWC_VSEL_MASK 0x0400 /* DC1_HWC_VSEL */
339#define WM831X_DC1_HWC_VSEL_SHIFT 10 /* DC1_HWC_VSEL */
340#define WM831X_DC1_HWC_VSEL_WIDTH 1 /* DC1_HWC_VSEL */
341#define WM831X_DC1_HWC_MODE_MASK 0x0300 /* DC1_HWC_MODE - [9:8] */
342#define WM831X_DC1_HWC_MODE_SHIFT 8 /* DC1_HWC_MODE - [9:8] */
343#define WM831X_DC1_HWC_MODE_WIDTH 2 /* DC1_HWC_MODE - [9:8] */
344#define WM831X_DC1_HC_THR_MASK 0x0070 /* DC1_HC_THR - [6:4] */
345#define WM831X_DC1_HC_THR_SHIFT 4 /* DC1_HC_THR - [6:4] */
346#define WM831X_DC1_HC_THR_WIDTH 3 /* DC1_HC_THR - [6:4] */
347#define WM831X_DC1_HC_IND_ENA 0x0001 /* DC1_HC_IND_ENA */
348#define WM831X_DC1_HC_IND_ENA_MASK 0x0001 /* DC1_HC_IND_ENA */
349#define WM831X_DC1_HC_IND_ENA_SHIFT 0 /* DC1_HC_IND_ENA */
350#define WM831X_DC1_HC_IND_ENA_WIDTH 1 /* DC1_HC_IND_ENA */
351
352/*
353 * R16472 (0x4058) - DC1 ON Config
354 */
355#define WM831X_DC1_ON_SLOT_MASK 0xE000 /* DC1_ON_SLOT - [15:13] */
356#define WM831X_DC1_ON_SLOT_SHIFT 13 /* DC1_ON_SLOT - [15:13] */
357#define WM831X_DC1_ON_SLOT_WIDTH 3 /* DC1_ON_SLOT - [15:13] */
358#define WM831X_DC1_ON_MODE_MASK 0x0300 /* DC1_ON_MODE - [9:8] */
359#define WM831X_DC1_ON_MODE_SHIFT 8 /* DC1_ON_MODE - [9:8] */
360#define WM831X_DC1_ON_MODE_WIDTH 2 /* DC1_ON_MODE - [9:8] */
361#define WM831X_DC1_ON_VSEL_MASK 0x007F /* DC1_ON_VSEL - [6:0] */
362#define WM831X_DC1_ON_VSEL_SHIFT 0 /* DC1_ON_VSEL - [6:0] */
363#define WM831X_DC1_ON_VSEL_WIDTH 7 /* DC1_ON_VSEL - [6:0] */
364
365/*
366 * R16473 (0x4059) - DC1 SLEEP Control
367 */
368#define WM831X_DC1_SLP_SLOT_MASK 0xE000 /* DC1_SLP_SLOT - [15:13] */
369#define WM831X_DC1_SLP_SLOT_SHIFT 13 /* DC1_SLP_SLOT - [15:13] */
370#define WM831X_DC1_SLP_SLOT_WIDTH 3 /* DC1_SLP_SLOT - [15:13] */
371#define WM831X_DC1_SLP_MODE_MASK 0x0300 /* DC1_SLP_MODE - [9:8] */
372#define WM831X_DC1_SLP_MODE_SHIFT 8 /* DC1_SLP_MODE - [9:8] */
373#define WM831X_DC1_SLP_MODE_WIDTH 2 /* DC1_SLP_MODE - [9:8] */
374#define WM831X_DC1_SLP_VSEL_MASK 0x007F /* DC1_SLP_VSEL - [6:0] */
375#define WM831X_DC1_SLP_VSEL_SHIFT 0 /* DC1_SLP_VSEL - [6:0] */
376#define WM831X_DC1_SLP_VSEL_WIDTH 7 /* DC1_SLP_VSEL - [6:0] */
377
378/*
379 * R16474 (0x405A) - DC1 DVS Control
380 */
381#define WM831X_DC1_DVS_SRC_MASK 0x1800 /* DC1_DVS_SRC - [12:11] */
382#define WM831X_DC1_DVS_SRC_SHIFT 11 /* DC1_DVS_SRC - [12:11] */
383#define WM831X_DC1_DVS_SRC_WIDTH 2 /* DC1_DVS_SRC - [12:11] */
384#define WM831X_DC1_DVS_VSEL_MASK 0x007F /* DC1_DVS_VSEL - [6:0] */
385#define WM831X_DC1_DVS_VSEL_SHIFT 0 /* DC1_DVS_VSEL - [6:0] */
386#define WM831X_DC1_DVS_VSEL_WIDTH 7 /* DC1_DVS_VSEL - [6:0] */
387
388/*
389 * R16475 (0x405B) - DC2 Control 1
390 */
391#define WM831X_DC2_RATE_MASK 0xC000 /* DC2_RATE - [15:14] */
392#define WM831X_DC2_RATE_SHIFT 14 /* DC2_RATE - [15:14] */
393#define WM831X_DC2_RATE_WIDTH 2 /* DC2_RATE - [15:14] */
394#define WM831X_DC2_PHASE 0x1000 /* DC2_PHASE */
395#define WM831X_DC2_PHASE_MASK 0x1000 /* DC2_PHASE */
396#define WM831X_DC2_PHASE_SHIFT 12 /* DC2_PHASE */
397#define WM831X_DC2_PHASE_WIDTH 1 /* DC2_PHASE */
398#define WM831X_DC2_FREQ_MASK 0x0300 /* DC2_FREQ - [9:8] */
399#define WM831X_DC2_FREQ_SHIFT 8 /* DC2_FREQ - [9:8] */
400#define WM831X_DC2_FREQ_WIDTH 2 /* DC2_FREQ - [9:8] */
401#define WM831X_DC2_FLT 0x0080 /* DC2_FLT */
402#define WM831X_DC2_FLT_MASK 0x0080 /* DC2_FLT */
403#define WM831X_DC2_FLT_SHIFT 7 /* DC2_FLT */
404#define WM831X_DC2_FLT_WIDTH 1 /* DC2_FLT */
405#define WM831X_DC2_SOFT_START_MASK 0x0030 /* DC2_SOFT_START - [5:4] */
406#define WM831X_DC2_SOFT_START_SHIFT 4 /* DC2_SOFT_START - [5:4] */
407#define WM831X_DC2_SOFT_START_WIDTH 2 /* DC2_SOFT_START - [5:4] */
408#define WM831X_DC2_CAP_MASK 0x0003 /* DC2_CAP - [1:0] */
409#define WM831X_DC2_CAP_SHIFT 0 /* DC2_CAP - [1:0] */
410#define WM831X_DC2_CAP_WIDTH 2 /* DC2_CAP - [1:0] */
411
412/*
413 * R16476 (0x405C) - DC2 Control 2
414 */
415#define WM831X_DC2_ERR_ACT_MASK 0xC000 /* DC2_ERR_ACT - [15:14] */
416#define WM831X_DC2_ERR_ACT_SHIFT 14 /* DC2_ERR_ACT - [15:14] */
417#define WM831X_DC2_ERR_ACT_WIDTH 2 /* DC2_ERR_ACT - [15:14] */
418#define WM831X_DC2_HWC_SRC_MASK 0x1800 /* DC2_HWC_SRC - [12:11] */
419#define WM831X_DC2_HWC_SRC_SHIFT 11 /* DC2_HWC_SRC - [12:11] */
420#define WM831X_DC2_HWC_SRC_WIDTH 2 /* DC2_HWC_SRC - [12:11] */
421#define WM831X_DC2_HWC_VSEL 0x0400 /* DC2_HWC_VSEL */
422#define WM831X_DC2_HWC_VSEL_MASK 0x0400 /* DC2_HWC_VSEL */
423#define WM831X_DC2_HWC_VSEL_SHIFT 10 /* DC2_HWC_VSEL */
424#define WM831X_DC2_HWC_VSEL_WIDTH 1 /* DC2_HWC_VSEL */
425#define WM831X_DC2_HWC_MODE_MASK 0x0300 /* DC2_HWC_MODE - [9:8] */
426#define WM831X_DC2_HWC_MODE_SHIFT 8 /* DC2_HWC_MODE - [9:8] */
427#define WM831X_DC2_HWC_MODE_WIDTH 2 /* DC2_HWC_MODE - [9:8] */
428#define WM831X_DC2_HC_THR_MASK 0x0070 /* DC2_HC_THR - [6:4] */
429#define WM831X_DC2_HC_THR_SHIFT 4 /* DC2_HC_THR - [6:4] */
430#define WM831X_DC2_HC_THR_WIDTH 3 /* DC2_HC_THR - [6:4] */
431#define WM831X_DC2_HC_IND_ENA 0x0001 /* DC2_HC_IND_ENA */
432#define WM831X_DC2_HC_IND_ENA_MASK 0x0001 /* DC2_HC_IND_ENA */
433#define WM831X_DC2_HC_IND_ENA_SHIFT 0 /* DC2_HC_IND_ENA */
434#define WM831X_DC2_HC_IND_ENA_WIDTH 1 /* DC2_HC_IND_ENA */
435
436/*
437 * R16477 (0x405D) - DC2 ON Config
438 */
439#define WM831X_DC2_ON_SLOT_MASK 0xE000 /* DC2_ON_SLOT - [15:13] */
440#define WM831X_DC2_ON_SLOT_SHIFT 13 /* DC2_ON_SLOT - [15:13] */
441#define WM831X_DC2_ON_SLOT_WIDTH 3 /* DC2_ON_SLOT - [15:13] */
442#define WM831X_DC2_ON_MODE_MASK 0x0300 /* DC2_ON_MODE - [9:8] */
443#define WM831X_DC2_ON_MODE_SHIFT 8 /* DC2_ON_MODE - [9:8] */
444#define WM831X_DC2_ON_MODE_WIDTH 2 /* DC2_ON_MODE - [9:8] */
445#define WM831X_DC2_ON_VSEL_MASK 0x007F /* DC2_ON_VSEL - [6:0] */
446#define WM831X_DC2_ON_VSEL_SHIFT 0 /* DC2_ON_VSEL - [6:0] */
447#define WM831X_DC2_ON_VSEL_WIDTH 7 /* DC2_ON_VSEL - [6:0] */
448
449/*
450 * R16478 (0x405E) - DC2 SLEEP Control
451 */
452#define WM831X_DC2_SLP_SLOT_MASK 0xE000 /* DC2_SLP_SLOT - [15:13] */
453#define WM831X_DC2_SLP_SLOT_SHIFT 13 /* DC2_SLP_SLOT - [15:13] */
454#define WM831X_DC2_SLP_SLOT_WIDTH 3 /* DC2_SLP_SLOT - [15:13] */
455#define WM831X_DC2_SLP_MODE_MASK 0x0300 /* DC2_SLP_MODE - [9:8] */
456#define WM831X_DC2_SLP_MODE_SHIFT 8 /* DC2_SLP_MODE - [9:8] */
457#define WM831X_DC2_SLP_MODE_WIDTH 2 /* DC2_SLP_MODE - [9:8] */
458#define WM831X_DC2_SLP_VSEL_MASK 0x007F /* DC2_SLP_VSEL - [6:0] */
459#define WM831X_DC2_SLP_VSEL_SHIFT 0 /* DC2_SLP_VSEL - [6:0] */
460#define WM831X_DC2_SLP_VSEL_WIDTH 7 /* DC2_SLP_VSEL - [6:0] */
461
462/*
463 * R16479 (0x405F) - DC2 DVS Control
464 */
465#define WM831X_DC2_DVS_SRC_MASK 0x1800 /* DC2_DVS_SRC - [12:11] */
466#define WM831X_DC2_DVS_SRC_SHIFT 11 /* DC2_DVS_SRC - [12:11] */
467#define WM831X_DC2_DVS_SRC_WIDTH 2 /* DC2_DVS_SRC - [12:11] */
468#define WM831X_DC2_DVS_VSEL_MASK 0x007F /* DC2_DVS_VSEL - [6:0] */
469#define WM831X_DC2_DVS_VSEL_SHIFT 0 /* DC2_DVS_VSEL - [6:0] */
470#define WM831X_DC2_DVS_VSEL_WIDTH 7 /* DC2_DVS_VSEL - [6:0] */
471
472/*
473 * R16480 (0x4060) - DC3 Control 1
474 */
475#define WM831X_DC3_PHASE 0x1000 /* DC3_PHASE */
476#define WM831X_DC3_PHASE_MASK 0x1000 /* DC3_PHASE */
477#define WM831X_DC3_PHASE_SHIFT 12 /* DC3_PHASE */
478#define WM831X_DC3_PHASE_WIDTH 1 /* DC3_PHASE */
479#define WM831X_DC3_FLT 0x0080 /* DC3_FLT */
480#define WM831X_DC3_FLT_MASK 0x0080 /* DC3_FLT */
481#define WM831X_DC3_FLT_SHIFT 7 /* DC3_FLT */
482#define WM831X_DC3_FLT_WIDTH 1 /* DC3_FLT */
483#define WM831X_DC3_SOFT_START_MASK 0x0030 /* DC3_SOFT_START - [5:4] */
484#define WM831X_DC3_SOFT_START_SHIFT 4 /* DC3_SOFT_START - [5:4] */
485#define WM831X_DC3_SOFT_START_WIDTH 2 /* DC3_SOFT_START - [5:4] */
486#define WM831X_DC3_STNBY_LIM_MASK 0x000C /* DC3_STNBY_LIM - [3:2] */
487#define WM831X_DC3_STNBY_LIM_SHIFT 2 /* DC3_STNBY_LIM - [3:2] */
488#define WM831X_DC3_STNBY_LIM_WIDTH 2 /* DC3_STNBY_LIM - [3:2] */
489#define WM831X_DC3_CAP_MASK 0x0003 /* DC3_CAP - [1:0] */
490#define WM831X_DC3_CAP_SHIFT 0 /* DC3_CAP - [1:0] */
491#define WM831X_DC3_CAP_WIDTH 2 /* DC3_CAP - [1:0] */
492
493/*
494 * R16481 (0x4061) - DC3 Control 2
495 */
496#define WM831X_DC3_ERR_ACT_MASK 0xC000 /* DC3_ERR_ACT - [15:14] */
497#define WM831X_DC3_ERR_ACT_SHIFT 14 /* DC3_ERR_ACT - [15:14] */
498#define WM831X_DC3_ERR_ACT_WIDTH 2 /* DC3_ERR_ACT - [15:14] */
499#define WM831X_DC3_HWC_SRC_MASK 0x1800 /* DC3_HWC_SRC - [12:11] */
500#define WM831X_DC3_HWC_SRC_SHIFT 11 /* DC3_HWC_SRC - [12:11] */
501#define WM831X_DC3_HWC_SRC_WIDTH 2 /* DC3_HWC_SRC - [12:11] */
502#define WM831X_DC3_HWC_VSEL 0x0400 /* DC3_HWC_VSEL */
503#define WM831X_DC3_HWC_VSEL_MASK 0x0400 /* DC3_HWC_VSEL */
504#define WM831X_DC3_HWC_VSEL_SHIFT 10 /* DC3_HWC_VSEL */
505#define WM831X_DC3_HWC_VSEL_WIDTH 1 /* DC3_HWC_VSEL */
506#define WM831X_DC3_HWC_MODE_MASK 0x0300 /* DC3_HWC_MODE - [9:8] */
507#define WM831X_DC3_HWC_MODE_SHIFT 8 /* DC3_HWC_MODE - [9:8] */
508#define WM831X_DC3_HWC_MODE_WIDTH 2 /* DC3_HWC_MODE - [9:8] */
509#define WM831X_DC3_OVP 0x0080 /* DC3_OVP */
510#define WM831X_DC3_OVP_MASK 0x0080 /* DC3_OVP */
511#define WM831X_DC3_OVP_SHIFT 7 /* DC3_OVP */
512#define WM831X_DC3_OVP_WIDTH 1 /* DC3_OVP */
513
514/*
515 * R16482 (0x4062) - DC3 ON Config
516 */
517#define WM831X_DC3_ON_SLOT_MASK 0xE000 /* DC3_ON_SLOT - [15:13] */
518#define WM831X_DC3_ON_SLOT_SHIFT 13 /* DC3_ON_SLOT - [15:13] */
519#define WM831X_DC3_ON_SLOT_WIDTH 3 /* DC3_ON_SLOT - [15:13] */
520#define WM831X_DC3_ON_MODE_MASK 0x0300 /* DC3_ON_MODE - [9:8] */
521#define WM831X_DC3_ON_MODE_SHIFT 8 /* DC3_ON_MODE - [9:8] */
522#define WM831X_DC3_ON_MODE_WIDTH 2 /* DC3_ON_MODE - [9:8] */
523#define WM831X_DC3_ON_VSEL_MASK 0x007F /* DC3_ON_VSEL - [6:0] */
524#define WM831X_DC3_ON_VSEL_SHIFT 0 /* DC3_ON_VSEL - [6:0] */
525#define WM831X_DC3_ON_VSEL_WIDTH 7 /* DC3_ON_VSEL - [6:0] */
526
527/*
528 * R16483 (0x4063) - DC3 SLEEP Control
529 */
530#define WM831X_DC3_SLP_SLOT_MASK 0xE000 /* DC3_SLP_SLOT - [15:13] */
531#define WM831X_DC3_SLP_SLOT_SHIFT 13 /* DC3_SLP_SLOT - [15:13] */
532#define WM831X_DC3_SLP_SLOT_WIDTH 3 /* DC3_SLP_SLOT - [15:13] */
533#define WM831X_DC3_SLP_MODE_MASK 0x0300 /* DC3_SLP_MODE - [9:8] */
534#define WM831X_DC3_SLP_MODE_SHIFT 8 /* DC3_SLP_MODE - [9:8] */
535#define WM831X_DC3_SLP_MODE_WIDTH 2 /* DC3_SLP_MODE - [9:8] */
536#define WM831X_DC3_SLP_VSEL_MASK 0x007F /* DC3_SLP_VSEL - [6:0] */
537#define WM831X_DC3_SLP_VSEL_SHIFT 0 /* DC3_SLP_VSEL - [6:0] */
538#define WM831X_DC3_SLP_VSEL_WIDTH 7 /* DC3_SLP_VSEL - [6:0] */
539
540/*
541 * R16484 (0x4064) - DC4 Control
542 */
543#define WM831X_DC4_ERR_ACT_MASK 0xC000 /* DC4_ERR_ACT - [15:14] */
544#define WM831X_DC4_ERR_ACT_SHIFT 14 /* DC4_ERR_ACT - [15:14] */
545#define WM831X_DC4_ERR_ACT_WIDTH 2 /* DC4_ERR_ACT - [15:14] */
546#define WM831X_DC4_HWC_SRC_MASK 0x1800 /* DC4_HWC_SRC - [12:11] */
547#define WM831X_DC4_HWC_SRC_SHIFT 11 /* DC4_HWC_SRC - [12:11] */
548#define WM831X_DC4_HWC_SRC_WIDTH 2 /* DC4_HWC_SRC - [12:11] */
549#define WM831X_DC4_HWC_MODE 0x0100 /* DC4_HWC_MODE */
550#define WM831X_DC4_HWC_MODE_MASK 0x0100 /* DC4_HWC_MODE */
551#define WM831X_DC4_HWC_MODE_SHIFT 8 /* DC4_HWC_MODE */
552#define WM831X_DC4_HWC_MODE_WIDTH 1 /* DC4_HWC_MODE */
553#define WM831X_DC4_RANGE_MASK 0x000C /* DC4_RANGE - [3:2] */
554#define WM831X_DC4_RANGE_SHIFT 2 /* DC4_RANGE - [3:2] */
555#define WM831X_DC4_RANGE_WIDTH 2 /* DC4_RANGE - [3:2] */
556#define WM831X_DC4_FBSRC 0x0001 /* DC4_FBSRC */
557#define WM831X_DC4_FBSRC_MASK 0x0001 /* DC4_FBSRC */
558#define WM831X_DC4_FBSRC_SHIFT 0 /* DC4_FBSRC */
559#define WM831X_DC4_FBSRC_WIDTH 1 /* DC4_FBSRC */
560
561/*
562 * R16485 (0x4065) - DC4 SLEEP Control
563 */
564#define WM831X_DC4_SLPENA 0x0100 /* DC4_SLPENA */
565#define WM831X_DC4_SLPENA_MASK 0x0100 /* DC4_SLPENA */
566#define WM831X_DC4_SLPENA_SHIFT 8 /* DC4_SLPENA */
567#define WM831X_DC4_SLPENA_WIDTH 1 /* DC4_SLPENA */
568
569/*
570 * R16526 (0x408E) - Power Good Source 1
571 */
572#define WM831X_DC4_OK 0x0008 /* DC4_OK */
573#define WM831X_DC4_OK_MASK 0x0008 /* DC4_OK */
574#define WM831X_DC4_OK_SHIFT 3 /* DC4_OK */
575#define WM831X_DC4_OK_WIDTH 1 /* DC4_OK */
576#define WM831X_DC3_OK 0x0004 /* DC3_OK */
577#define WM831X_DC3_OK_MASK 0x0004 /* DC3_OK */
578#define WM831X_DC3_OK_SHIFT 2 /* DC3_OK */
579#define WM831X_DC3_OK_WIDTH 1 /* DC3_OK */
580#define WM831X_DC2_OK 0x0002 /* DC2_OK */
581#define WM831X_DC2_OK_MASK 0x0002 /* DC2_OK */
582#define WM831X_DC2_OK_SHIFT 1 /* DC2_OK */
583#define WM831X_DC2_OK_WIDTH 1 /* DC2_OK */
584#define WM831X_DC1_OK 0x0001 /* DC1_OK */
585#define WM831X_DC1_OK_MASK 0x0001 /* DC1_OK */
586#define WM831X_DC1_OK_SHIFT 0 /* DC1_OK */
587#define WM831X_DC1_OK_WIDTH 1 /* DC1_OK */
588
18#define WM831X_ISINK_MAX_ISEL 56 589#define WM831X_ISINK_MAX_ISEL 56
19extern int wm831x_isinkv_values[WM831X_ISINK_MAX_ISEL]; 590extern int wm831x_isinkv_values[WM831X_ISINK_MAX_ISEL];
20 591
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 22:35:55 -0500