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-rw-r--r--include/asm-xtensa/xtensa/cacheasm.h708
-rw-r--r--include/asm-xtensa/xtensa/cacheattrasm.h432
-rw-r--r--include/asm-xtensa/xtensa/config-linux_be/core.h1270
-rw-r--r--include/asm-xtensa/xtensa/config-linux_be/defs.h270
-rw-r--r--include/asm-xtensa/xtensa/config-linux_be/specreg.h99
-rw-r--r--include/asm-xtensa/xtensa/config-linux_be/system.h198
-rw-r--r--include/asm-xtensa/xtensa/config-linux_be/tie.h275
-rw-r--r--include/asm-xtensa/xtensa/coreasm.h526
-rw-r--r--include/asm-xtensa/xtensa/corebits.h77
-rw-r--r--include/asm-xtensa/xtensa/hal.h822
-rw-r--r--include/asm-xtensa/xtensa/simcall.h130
-rw-r--r--include/asm-xtensa/xtensa/xt2000-uart.h155
-rw-r--r--include/asm-xtensa/xtensa/xt2000.h408
-rw-r--r--include/asm-xtensa/xtensa/xtboard.h120
14 files changed, 5490 insertions, 0 deletions
diff --git a/include/asm-xtensa/xtensa/cacheasm.h b/include/asm-xtensa/xtensa/cacheasm.h
new file mode 100644
index 000000000000..0cdbb0bf180e
--- /dev/null
+++ b/include/asm-xtensa/xtensa/cacheasm.h
@@ -0,0 +1,708 @@
1#ifndef XTENSA_CACHEASM_H
2#define XTENSA_CACHEASM_H
3
4/*
5 * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
6 *
7 * include/asm-xtensa/xtensa/cacheasm.h -- assembler-specific cache
8 * related definitions that depend on CORE configuration.
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive
12 * for more details.
13 *
14 * Copyright (C) 2002 Tensilica Inc.
15 */
16
17
18#include <xtensa/coreasm.h>
19
20
21/*
22 * This header file defines assembler macros of the form:
23 * <x>cache_<func>
24 * where <x> is 'i' or 'd' for instruction and data caches,
25 * and <func> indicates the function of the macro.
26 *
27 * The following functions <func> are defined,
28 * and apply only to the specified cache (I or D):
29 *
30 * reset
31 * Resets the cache.
32 *
33 * sync
34 * Makes sure any previous cache instructions have been completed;
35 * ie. makes sure any previous cache control operations
36 * have had full effect and been synchronized to memory.
37 * Eg. any invalidate completed [so as not to generate a hit],
38 * any writebacks or other pipelined writes written to memory, etc.
39 *
40 * invalidate_line (single cache line)
41 * invalidate_region (specified memory range)
42 * invalidate_all (entire cache)
43 * Invalidates all cache entries that cache
44 * data from the specified memory range.
45 * NOTE: locked entries are not invalidated.
46 *
47 * writeback_line (single cache line)
48 * writeback_region (specified memory range)
49 * writeback_all (entire cache)
50 * Writes back to memory all dirty cache entries
51 * that cache data from the specified memory range,
52 * and marks these entries as clean.
53 * NOTE: on some future implementations, this might
54 * also invalidate.
55 * NOTE: locked entries are written back, but never invalidated.
56 * NOTE: instruction caches never implement writeback.
57 *
58 * writeback_inv_line (single cache line)
59 * writeback_inv_region (specified memory range)
60 * writeback_inv_all (entire cache)
61 * Writes back to memory all dirty cache entries
62 * that cache data from the specified memory range,
63 * and invalidates these entries (including all clean
64 * cache entries that cache data from that range).
65 * NOTE: locked entries are written back but not invalidated.
66 * NOTE: instruction caches never implement writeback.
67 *
68 * lock_line (single cache line)
69 * lock_region (specified memory range)
70 * Prefetch and lock the specified memory range into cache.
71 * NOTE: if any part of the specified memory range cannot
72 * be locked, a ??? exception occurs. These macros don't
73 * do anything special (yet anyway) to handle this situation.
74 *
75 * unlock_line (single cache line)
76 * unlock_region (specified memory range)
77 * unlock_all (entire cache)
78 * Unlock cache entries that cache the specified memory range.
79 * Entries not already locked are unaffected.
80 */
81
82
83
84/*************************** GENERIC -- ALL CACHES ***************************/
85
86
87/*
88 * The following macros assume the following cache size/parameter limits
89 * in the current Xtensa core implementation:
90 * cache size: 1024 bytes minimum
91 * line size: 16 - 64 bytes
92 * way count: 1 - 4
93 *
94 * Minimum entries per way (ie. per associativity) = 1024 / 64 / 4 = 4
95 * Hence the assumption that each loop can execute four cache instructions.
96 *
97 * Correspondingly, the offset range of instructions is assumed able to cover
98 * four lines, ie. offsets {0,1,2,3} * line_size are assumed valid for
99 * both hit and indexed cache instructions. Ie. these offsets are all
100 * valid: 0, 16, 32, 48, 64, 96, 128, 192 (for line sizes 16, 32, 64).
101 * This is true of all original cache instructions
102 * (dhi, ihi, dhwb, dhwbi, dii, iii) which have offsets
103 * of 0 to 1020 in multiples of 4 (ie. 8 bits shifted by 2).
104 * This is also true of subsequent cache instructions
105 * (dhu, ihu, diu, iiu, diwb, diwbi, dpfl, ipfl) which have offsets
106 * of 0 to 240 in multiples of 16 (ie. 4 bits shifted by 4).
107 *
108 * (Maximum cache size, currently 32k, doesn't affect the following macros.
109 * Cache ways > MMU min page size cause aliasing but that's another matter.)
110 */
111
112
113
114/*
115 * Macro to apply an 'indexed' cache instruction to the entire cache.
116 *
117 * Parameters:
118 * cainst instruction/ that takes an address register parameter
119 * and an offset parameter (in range 0 .. 3*linesize).
120 * size size of cache in bytes
121 * linesize size of cache line in bytes
122 * assoc_or1 number of associativities (ways/sets) in cache
123 * if all sets affected by cainst,
124 * or 1 if only one set (or not all sets) of the cache
125 * is affected by cainst (eg. DIWB or DIWBI [not yet ISA defined]).
126 * aa, ab unique address registers (temporaries)
127 */
128
129 .macro cache_index_all cainst, size, linesize, assoc_or1, aa, ab
130
131 // Sanity-check on cache parameters:
132 .ifne (\size % (\linesize * \assoc_or1 * 4))
133 .err // cache configuration outside expected/supported range!
134 .endif
135
136 // \size byte cache, \linesize byte lines, \assoc_or1 way(s) affected by each \cainst.
137 movi \aa, (\size / (\linesize * \assoc_or1 * 4))
138 // Possible improvement: need only loop if \aa > 1 ;
139 // however that particular condition is highly unlikely.
140 movi \ab, 0 // to iterate over cache
141 floop \aa, cachex\@
142 \cainst \ab, 0*\linesize
143 \cainst \ab, 1*\linesize
144 \cainst \ab, 2*\linesize
145 \cainst \ab, 3*\linesize
146 addi \ab, \ab, 4*\linesize // move to next line
147 floopend \aa, cachex\@
148
149 .endm
150
151
152/*
153 * Macro to apply a 'hit' cache instruction to a memory region,
154 * ie. to any cache entries that cache a specified portion (region) of memory.
155 * Takes care of the unaligned cases, ie. may apply to one
156 * more cache line than $asize / lineSize if $aaddr is not aligned.
157 *
158 *
159 * Parameters are:
160 * cainst instruction/macro that takes an address register parameter
161 * and an offset parameter (currently always zero)
162 * and generates a cache instruction (eg. "dhi", "dhwb", "ihi", etc.)
163 * linesize_log2 log2(size of cache line in bytes)
164 * addr register containing start address of region (clobbered)
165 * asize register containing size of the region in bytes (clobbered)
166 * askew unique register used as temporary
167 *
168 * !?!?! 2DO: optimization: iterate max(cache_size and \asize) / linesize
169 */
170
171 .macro cache_hit_region cainst, linesize_log2, addr, asize, askew
172
173 // Make \asize the number of iterations:
174 extui \askew, \addr, 0, \linesize_log2 // get unalignment amount of \addr
175 add \asize, \asize, \askew // ... and add it to \asize
176 addi \asize, \asize, (1 << \linesize_log2) - 1 // round up!
177 srli \asize, \asize, \linesize_log2
178
179 // Iterate over region:
180 floopnez \asize, cacheh\@
181 \cainst \addr, 0
182 addi \addr, \addr, (1 << \linesize_log2) // move to next line
183 floopend \asize, cacheh\@
184
185 .endm
186
187
188
189
190
191/*************************** INSTRUCTION CACHE ***************************/
192
193
194/*
195 * Reset/initialize the instruction cache by simply invalidating it:
196 * (need to unlock first also, if cache locking implemented):
197 *
198 * Parameters:
199 * aa, ab unique address registers (temporaries)
200 */
201 .macro icache_reset aa, ab
202 icache_unlock_all \aa, \ab
203 icache_invalidate_all \aa, \ab
204 .endm
205
206
207/*
208 * Synchronize after an instruction cache operation,
209 * to be sure everything is in sync with memory as to be
210 * expected following any previous instruction cache control operations.
211 *
212 * Parameters are:
213 * ar an address register (temporary) (currently unused, but may be used in future)
214 */
215 .macro icache_sync ar
216#if XCHAL_ICACHE_SIZE > 0
217 isync
218#endif
219 .endm
220
221
222
223/*
224 * Invalidate a single line of the instruction cache.
225 * Parameters are:
226 * ar address register that contains (virtual) address to invalidate
227 * (may get clobbered in a future implementation, but not currently)
228 * offset (optional) offset to add to \ar to compute effective address to invalidate
229 * (note: some number of lsbits are ignored)
230 */
231 .macro icache_invalidate_line ar, offset
232#if XCHAL_ICACHE_SIZE > 0
233 ihi \ar, \offset // invalidate icache line
234 /*
235 * NOTE: in some version of the silicon [!!!SHOULD HAVE BEEN DOCUMENTED!!!]
236 * 'ihi' doesn't work, so it had been replaced with 'iii'
237 * (which would just invalidate more than it should,
238 * which should be okay other than the performance hit
239 * because cache locking did not exist in that version,
240 * unless user somehow relies on something being cached).
241 * [WHAT VERSION IS IT!!?!?
242 * IS THERE ANY WAY TO TEST FOR THAT HERE, TO OUTPUT 'III' ONLY IF NEEDED!?!?].
243 *
244 * iii \ar, \offset
245 */
246 icache_sync \ar
247#endif
248 .endm
249
250
251
252
253/*
254 * Invalidate instruction cache entries that cache a specified portion of memory.
255 * Parameters are:
256 * astart start address (register gets clobbered)
257 * asize size of the region in bytes (register gets clobbered)
258 * ac unique register used as temporary
259 */
260 .macro icache_invalidate_region astart, asize, ac
261#if XCHAL_ICACHE_SIZE > 0
262 // Instruction cache region invalidation:
263 cache_hit_region ihi, XCHAL_ICACHE_LINEWIDTH, \astart, \asize, \ac
264 icache_sync \ac
265 // End of instruction cache region invalidation
266#endif
267 .endm
268
269
270
271/*
272 * Invalidate entire instruction cache.
273 *
274 * Parameters:
275 * aa, ab unique address registers (temporaries)
276 */
277 .macro icache_invalidate_all aa, ab
278#if XCHAL_ICACHE_SIZE > 0
279 // Instruction cache invalidation:
280 cache_index_all iii, XCHAL_ICACHE_SIZE, XCHAL_ICACHE_LINESIZE, XCHAL_ICACHE_WAYS, \aa, \ab
281 icache_sync \aa
282 // End of instruction cache invalidation
283#endif
284 .endm
285
286
287
288/*
289 * Lock (prefetch & lock) a single line of the instruction cache.
290 *
291 * Parameters are:
292 * ar address register that contains (virtual) address to lock
293 * (may get clobbered in a future implementation, but not currently)
294 * offset offset to add to \ar to compute effective address to lock
295 * (note: some number of lsbits are ignored)
296 */
297 .macro icache_lock_line ar, offset
298#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
299 ipfl \ar, \offset /* prefetch and lock icache line */
300 icache_sync \ar
301#endif
302 .endm
303
304
305
306/*
307 * Lock (prefetch & lock) a specified portion of memory into the instruction cache.
308 * Parameters are:
309 * astart start address (register gets clobbered)
310 * asize size of the region in bytes (register gets clobbered)
311 * ac unique register used as temporary
312 */
313 .macro icache_lock_region astart, asize, ac
314#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
315 // Instruction cache region lock:
316 cache_hit_region ipfl, XCHAL_ICACHE_LINEWIDTH, \astart, \asize, \ac
317 icache_sync \ac
318 // End of instruction cache region lock
319#endif
320 .endm
321
322
323
324/*
325 * Unlock a single line of the instruction cache.
326 *
327 * Parameters are:
328 * ar address register that contains (virtual) address to unlock
329 * (may get clobbered in a future implementation, but not currently)
330 * offset offset to add to \ar to compute effective address to unlock
331 * (note: some number of lsbits are ignored)
332 */
333 .macro icache_unlock_line ar, offset
334#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
335 ihu \ar, \offset /* unlock icache line */
336 icache_sync \ar
337#endif
338 .endm
339
340
341
342/*
343 * Unlock a specified portion of memory from the instruction cache.
344 * Parameters are:
345 * astart start address (register gets clobbered)
346 * asize size of the region in bytes (register gets clobbered)
347 * ac unique register used as temporary
348 */
349 .macro icache_unlock_region astart, asize, ac
350#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
351 // Instruction cache region unlock:
352 cache_hit_region ihu, XCHAL_ICACHE_LINEWIDTH, \astart, \asize, \ac
353 icache_sync \ac
354 // End of instruction cache region unlock
355#endif
356 .endm
357
358
359
360/*
361 * Unlock entire instruction cache.
362 *
363 * Parameters:
364 * aa, ab unique address registers (temporaries)
365 */
366 .macro icache_unlock_all aa, ab
367#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
368 // Instruction cache unlock:
369 cache_index_all iiu, XCHAL_ICACHE_SIZE, XCHAL_ICACHE_LINESIZE, 1, \aa, \ab
370 icache_sync \aa
371 // End of instruction cache unlock
372#endif
373 .endm
374
375
376
377
378
379/*************************** DATA CACHE ***************************/
380
381
382
383/*
384 * Reset/initialize the data cache by simply invalidating it
385 * (need to unlock first also, if cache locking implemented):
386 *
387 * Parameters:
388 * aa, ab unique address registers (temporaries)
389 */
390 .macro dcache_reset aa, ab
391 dcache_unlock_all \aa, \ab
392 dcache_invalidate_all \aa, \ab
393 .endm
394
395
396
397
398/*
399 * Synchronize after a data cache operation,
400 * to be sure everything is in sync with memory as to be
401 * expected following any previous data cache control operations.
402 *
403 * Parameters are:
404 * ar an address register (temporary) (currently unused, but may be used in future)
405 */
406 .macro dcache_sync ar
407#if XCHAL_DCACHE_SIZE > 0
408 // This previous sequence errs on the conservative side (too much so); a DSYNC should be sufficient:
409 //memw // synchronize data cache changes relative to subsequent memory accesses
410 //isync // be conservative and ISYNC as well (just to be sure)
411
412 dsync
413#endif
414 .endm
415
416
417
418/*
419 * Synchronize after a data store operation,
420 * to be sure the stored data is completely off the processor
421 * (and assuming there is no buffering outside the processor,
422 * that the data is in memory). This may be required to
423 * ensure that the processor's write buffers are emptied.
424 * A MEMW followed by a read guarantees this, by definition.
425 * We also try to make sure the read itself completes.
426 *
427 * Parameters are:
428 * ar an address register (temporary)
429 */
430 .macro write_sync ar
431 memw // ensure previous memory accesses are complete prior to subsequent memory accesses
432 l32i \ar, sp, 0 // completing this read ensures any previous write has completed, because of MEMW
433 //slot
434 add \ar, \ar, \ar // use the result of the read to help ensure the read completes (in future architectures)
435 .endm
436
437
438/*
439 * Invalidate a single line of the data cache.
440 * Parameters are:
441 * ar address register that contains (virtual) address to invalidate
442 * (may get clobbered in a future implementation, but not currently)
443 * offset (optional) offset to add to \ar to compute effective address to invalidate
444 * (note: some number of lsbits are ignored)
445 */
446 .macro dcache_invalidate_line ar, offset
447#if XCHAL_DCACHE_SIZE > 0
448 dhi \ar, \offset
449 dcache_sync \ar
450#endif
451 .endm
452
453
454
455
456
457/*
458 * Invalidate data cache entries that cache a specified portion of memory.
459 * Parameters are:
460 * astart start address (register gets clobbered)
461 * asize size of the region in bytes (register gets clobbered)
462 * ac unique register used as temporary
463 */
464 .macro dcache_invalidate_region astart, asize, ac
465#if XCHAL_DCACHE_SIZE > 0
466 // Data cache region invalidation:
467 cache_hit_region dhi, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
468 dcache_sync \ac
469 // End of data cache region invalidation
470#endif
471 .endm
472
473
474
475#if 0
476/*
477 * This is a work-around for a bug in SiChip1 (???).
478 * There should be a proper mechanism for not outputting
479 * these instructions when not needed.
480 * To enable work-around, uncomment this and replace 'dii'
481 * with 'dii_s1' everywhere, eg. in dcache_invalidate_all
482 * macro below.
483 */
484 .macro dii_s1 ar, offset
485 dii \ar, \offset
486 or \ar, \ar, \ar
487 or \ar, \ar, \ar
488 or \ar, \ar, \ar
489 or \ar, \ar, \ar
490 .endm
491#endif
492
493
494/*
495 * Invalidate entire data cache.
496 *
497 * Parameters:
498 * aa, ab unique address registers (temporaries)
499 */
500 .macro dcache_invalidate_all aa, ab
501#if XCHAL_DCACHE_SIZE > 0
502 // Data cache invalidation:
503 cache_index_all dii, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, XCHAL_DCACHE_WAYS, \aa, \ab
504 dcache_sync \aa
505 // End of data cache invalidation
506#endif
507 .endm
508
509
510
511/*
512 * Writeback a single line of the data cache.
513 * Parameters are:
514 * ar address register that contains (virtual) address to writeback
515 * (may get clobbered in a future implementation, but not currently)
516 * offset offset to add to \ar to compute effective address to writeback
517 * (note: some number of lsbits are ignored)
518 */
519 .macro dcache_writeback_line ar, offset
520#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK
521 dhwb \ar, \offset
522 dcache_sync \ar
523#endif
524 .endm
525
526
527
528/*
529 * Writeback dirty data cache entries that cache a specified portion of memory.
530 * Parameters are:
531 * astart start address (register gets clobbered)
532 * asize size of the region in bytes (register gets clobbered)
533 * ac unique register used as temporary
534 */
535 .macro dcache_writeback_region astart, asize, ac
536#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK
537 // Data cache region writeback:
538 cache_hit_region dhwb, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
539 dcache_sync \ac
540 // End of data cache region writeback
541#endif
542 .endm
543
544
545
546/*
547 * Writeback entire data cache.
548 * Parameters:
549 * aa, ab unique address registers (temporaries)
550 */
551 .macro dcache_writeback_all aa, ab
552#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK
553 // Data cache writeback:
554 cache_index_all diwb, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, 1, \aa, \ab
555 dcache_sync \aa
556 // End of data cache writeback
557#endif
558 .endm
559
560
561
562/*
563 * Writeback and invalidate a single line of the data cache.
564 * Parameters are:
565 * ar address register that contains (virtual) address to writeback and invalidate
566 * (may get clobbered in a future implementation, but not currently)
567 * offset offset to add to \ar to compute effective address to writeback and invalidate
568 * (note: some number of lsbits are ignored)
569 */
570 .macro dcache_writeback_inv_line ar, offset
571#if XCHAL_DCACHE_SIZE > 0
572 dhwbi \ar, \offset /* writeback and invalidate dcache line */
573 dcache_sync \ar
574#endif
575 .endm
576
577
578
579/*
580 * Writeback and invalidate data cache entries that cache a specified portion of memory.
581 * Parameters are:
582 * astart start address (register gets clobbered)
583 * asize size of the region in bytes (register gets clobbered)
584 * ac unique register used as temporary
585 */
586 .macro dcache_writeback_inv_region astart, asize, ac
587#if XCHAL_DCACHE_SIZE > 0
588 // Data cache region writeback and invalidate:
589 cache_hit_region dhwbi, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
590 dcache_sync \ac
591 // End of data cache region writeback and invalidate
592#endif
593 .endm
594
595
596
597/*
598 * Writeback and invalidate entire data cache.
599 * Parameters:
600 * aa, ab unique address registers (temporaries)
601 */
602 .macro dcache_writeback_inv_all aa, ab
603#if XCHAL_DCACHE_SIZE > 0
604 // Data cache writeback and invalidate:
605#if XCHAL_DCACHE_IS_WRITEBACK
606 cache_index_all diwbi, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, 1, \aa, \ab
607 dcache_sync \aa
608#else /*writeback*/
609 // Data cache does not support writeback, so just invalidate: */
610 dcache_invalidate_all \aa, \ab
611#endif /*writeback*/
612 // End of data cache writeback and invalidate
613#endif
614 .endm
615
616
617
618
619/*
620 * Lock (prefetch & lock) a single line of the data cache.
621 *
622 * Parameters are:
623 * ar address register that contains (virtual) address to lock
624 * (may get clobbered in a future implementation, but not currently)
625 * offset offset to add to \ar to compute effective address to lock
626 * (note: some number of lsbits are ignored)
627 */
628 .macro dcache_lock_line ar, offset
629#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
630 dpfl \ar, \offset /* prefetch and lock dcache line */
631 dcache_sync \ar
632#endif
633 .endm
634
635
636
637/*
638 * Lock (prefetch & lock) a specified portion of memory into the data cache.
639 * Parameters are:
640 * astart start address (register gets clobbered)
641 * asize size of the region in bytes (register gets clobbered)
642 * ac unique register used as temporary
643 */
644 .macro dcache_lock_region astart, asize, ac
645#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
646 // Data cache region lock:
647 cache_hit_region dpfl, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
648 dcache_sync \ac
649 // End of data cache region lock
650#endif
651 .endm
652
653
654
655/*
656 * Unlock a single line of the data cache.
657 *
658 * Parameters are:
659 * ar address register that contains (virtual) address to unlock
660 * (may get clobbered in a future implementation, but not currently)
661 * offset offset to add to \ar to compute effective address to unlock
662 * (note: some number of lsbits are ignored)
663 */
664 .macro dcache_unlock_line ar, offset
665#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
666 dhu \ar, \offset /* unlock dcache line */
667 dcache_sync \ar
668#endif
669 .endm
670
671
672
673/*
674 * Unlock a specified portion of memory from the data cache.
675 * Parameters are:
676 * astart start address (register gets clobbered)
677 * asize size of the region in bytes (register gets clobbered)
678 * ac unique register used as temporary
679 */
680 .macro dcache_unlock_region astart, asize, ac
681#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
682 // Data cache region unlock:
683 cache_hit_region dhu, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
684 dcache_sync \ac
685 // End of data cache region unlock
686#endif
687 .endm
688
689
690
691/*
692 * Unlock entire data cache.
693 *
694 * Parameters:
695 * aa, ab unique address registers (temporaries)
696 */
697 .macro dcache_unlock_all aa, ab
698#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
699 // Data cache unlock:
700 cache_index_all diu, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, 1, \aa, \ab
701 dcache_sync \aa
702 // End of data cache unlock
703#endif
704 .endm
705
706
707#endif /*XTENSA_CACHEASM_H*/
708
diff --git a/include/asm-xtensa/xtensa/cacheattrasm.h b/include/asm-xtensa/xtensa/cacheattrasm.h
new file mode 100644
index 000000000000..1c3e117b3592
--- /dev/null
+++ b/include/asm-xtensa/xtensa/cacheattrasm.h
@@ -0,0 +1,432 @@
1#ifndef XTENSA_CACHEATTRASM_H
2#define XTENSA_CACHEATTRASM_H
3
4/*
5 * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
6 *
7 * include/asm-xtensa/xtensa/cacheattrasm.h -- assembler-specific
8 * CACHEATTR register related definitions that depend on CORE
9 * configuration.
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 *
15 * Copyright (C) 2002 Tensilica Inc.
16 */
17
18
19#include <xtensa/coreasm.h>
20
21
22/*
23 * This header file defines assembler macros of the form:
24 * <x>cacheattr_<func>
25 * where:
26 * <x> is 'i', 'd' or absent for instruction, data
27 * or both caches; and
28 * <func> indicates the function of the macro.
29 *
30 * The following functions are defined:
31 *
32 * icacheattr_get
33 * Reads I-cache CACHEATTR into a2 (clobbers a3-a5).
34 *
35 * dcacheattr_get
36 * Reads D-cache CACHEATTR into a2 (clobbers a3-a5).
37 * (Note: for configs with a real CACHEATTR register, the
38 * above two macros are identical.)
39 *
40 * cacheattr_set
41 * Writes both I-cache and D-cache CACHEATTRs from a2 (a3-a8 clobbered).
42 * Works even when changing one's own code's attributes.
43 *
44 * icacheattr_is_enabled label
45 * Branches to \label if I-cache appears to have been enabled
46 * (eg. if CACHEATTR contains a cache-enabled attribute).
47 * (clobbers a2-a5,SAR)
48 *
49 * dcacheattr_is_enabled label
50 * Branches to \label if D-cache appears to have been enabled
51 * (eg. if CACHEATTR contains a cache-enabled attribute).
52 * (clobbers a2-a5,SAR)
53 *
54 * cacheattr_is_enabled label
55 * Branches to \label if either I-cache or D-cache appears to have been enabled
56 * (eg. if CACHEATTR contains a cache-enabled attribute).
57 * (clobbers a2-a5,SAR)
58 *
59 * The following macros are only defined under certain conditions:
60 *
61 * icacheattr_set (if XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR)
62 * Writes I-cache CACHEATTR from a2 (a3-a8 clobbered).
63 *
64 * dcacheattr_set (if XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR)
65 * Writes D-cache CACHEATTR from a2 (a3-a8 clobbered).
66 */
67
68
69
70/*************************** GENERIC -- ALL CACHES ***************************/
71
72/*
73 * _cacheattr_get
74 *
75 * (Internal macro.)
76 * Returns value of CACHEATTR register (or closest equivalent) in a2.
77 *
78 * Entry:
79 * (none)
80 * Exit:
81 * a2 value read from CACHEATTR
82 * a3-a5 clobbered (temporaries)
83 */
84 .macro _cacheattr_get tlb
85#if XCHAL_HAVE_CACHEATTR
86 rsr a2, CACHEATTR
87#elif XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR
88 // We have a config that "mimics" CACHEATTR using a simplified
89 // "MMU" composed of a single statically-mapped way.
90 // DTLB and ITLB are independent, so there's no single
91 // cache attribute that can describe both. So for now
92 // just return the DTLB state.
93 movi a5, 0xE0000000
94 movi a2, 0
95 movi a3, 0
961: add a3, a3, a5 // next segment
97 r&tlb&1 a4, a3 // get PPN+CA of segment at 0xE0000000, 0xC0000000, ..., 0
98 dsync // interlock???
99 slli a2, a2, 4
100 extui a4, a4, 0, 4 // extract CA
101 or a2, a2, a4
102 bnez a3, 1b
103#else
104 // This macro isn't applicable to arbitrary MMU configurations.
105 // Just return zero.
106 movi a2, 0
107#endif
108 .endm
109
110 .macro icacheattr_get
111 _cacheattr_get itlb
112 .endm
113
114 .macro dcacheattr_get
115 _cacheattr_get dtlb
116 .endm
117
118
119#define XCHAL_CACHEATTR_ALL_BYPASS 0x22222222 /* default (powerup/reset) value of CACHEATTR, all BYPASS
120 mode (ie. disabled/bypassed caches) */
121
122#if XCHAL_HAVE_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR
123
124#define XCHAL_FCA_ENAMASK 0x001A /* bitmap of fetch attributes that require enabled icache */
125#define XCHAL_LCA_ENAMASK 0x0003 /* bitmap of load attributes that require enabled dcache */
126#define XCHAL_SCA_ENAMASK 0x0003 /* bitmap of store attributes that require enabled dcache */
127#define XCHAL_LSCA_ENAMASK (XCHAL_LCA_ENAMASK|XCHAL_SCA_ENAMASK) /* l/s attrs requiring enabled dcache */
128#define XCHAL_ALLCA_ENAMASK (XCHAL_FCA_ENAMASK|XCHAL_LSCA_ENAMASK) /* all attrs requiring enabled caches */
129
130/*
131 * _cacheattr_is_enabled
132 *
133 * (Internal macro.)
134 * Branches to \label if CACHEATTR in a2 indicates an enabled
135 * cache, using mask in a3.
136 *
137 * Parameters:
138 * label where to branch to if cache is enabled
139 * Entry:
140 * a2 contains CACHEATTR value used to determine whether
141 * caches are enabled
142 * a3 16-bit constant where each bit correspond to
143 * one of the 16 possible CA values (in a CACHEATTR mask);
144 * CA values that indicate the cache is enabled
145 * have their corresponding bit set in this mask
146 * (eg. use XCHAL_xCA_ENAMASK , above)
147 * Exit:
148 * a2,a4,a5 clobbered
149 * SAR clobbered
150 */
151 .macro _cacheattr_is_enabled label
152 movi a4, 8 // loop 8 times
153.Lcaife\@:
154 extui a5, a2, 0, 4 // get CA nibble
155 ssr a5 // index into mask according to CA...
156 srl a5, a3 // ...and get CA's mask bit in a5 bit 0
157 bbsi.l a5, 0, \label // if CA indicates cache enabled, jump to label
158 srli a2, a2, 4 // next nibble
159 addi a4, a4, -1
160 bnez a4, .Lcaife\@ // loop for each nibble
161 .endm
162
163#else /* XCHAL_HAVE_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR */
164 .macro _cacheattr_is_enabled label
165 j \label // macro not applicable, assume caches always enabled
166 .endm
167#endif /* XCHAL_HAVE_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR */
168
169
170
171/*
172 * icacheattr_is_enabled
173 *
174 * Branches to \label if I-cache is enabled.
175 *
176 * Parameters:
177 * label where to branch to if icache is enabled
178 * Entry:
179 * (none)
180 * Exit:
181 * a2-a5, SAR clobbered (temporaries)
182 */
183 .macro icacheattr_is_enabled label
184#if XCHAL_HAVE_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR
185 icacheattr_get
186 movi a3, XCHAL_FCA_ENAMASK
187#endif
188 _cacheattr_is_enabled \label
189 .endm
190
191/*
192 * dcacheattr_is_enabled
193 *
194 * Branches to \label if D-cache is enabled.
195 *
196 * Parameters:
197 * label where to branch to if dcache is enabled
198 * Entry:
199 * (none)
200 * Exit:
201 * a2-a5, SAR clobbered (temporaries)
202 */
203 .macro dcacheattr_is_enabled label
204#if XCHAL_HAVE_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR
205 dcacheattr_get
206 movi a3, XCHAL_LSCA_ENAMASK
207#endif
208 _cacheattr_is_enabled \label
209 .endm
210
211/*
212 * cacheattr_is_enabled
213 *
214 * Branches to \label if either I-cache or D-cache is enabled.
215 *
216 * Parameters:
217 * label where to branch to if a cache is enabled
218 * Entry:
219 * (none)
220 * Exit:
221 * a2-a5, SAR clobbered (temporaries)
222 */
223 .macro cacheattr_is_enabled label
224#if XCHAL_HAVE_CACHEATTR
225 rsr a2, CACHEATTR
226 movi a3, XCHAL_ALLCA_ENAMASK
227#elif XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR
228 icacheattr_get
229 movi a3, XCHAL_FCA_ENAMASK
230 _cacheattr_is_enabled \label
231 dcacheattr_get
232 movi a3, XCHAL_LSCA_ENAMASK
233#endif
234 _cacheattr_is_enabled \label
235 .endm
236
237
238
239/*
240 * The ISA does not have a defined way to change the
241 * instruction cache attributes of the running code,
242 * ie. of the memory area that encloses the current PC.
243 * However, each micro-architecture (or class of
244 * configurations within a micro-architecture)
245 * provides a way to deal with this issue.
246 *
247 * Here are a few macros used to implement the relevant
248 * approach taken.
249 */
250
251#if XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR
252 // We have a config that "mimics" CACHEATTR using a simplified
253 // "MMU" composed of a single statically-mapped way.
254
255/*
256 * icacheattr_set
257 *
258 * Entry:
259 * a2 cacheattr value to set
260 * Exit:
261 * a2 unchanged
262 * a3-a8 clobbered (temporaries)
263 */
264 .macro icacheattr_set
265
266 movi a5, 0xE0000000 // mask of upper 3 bits
267 movi a6, 3f // PC where ITLB is set
268 movi a3, 0 // start at region 0 (0 .. 7)
269 and a6, a6, a5 // upper 3 bits of local PC area
270 mov a7, a2 // copy a2 so it doesn't get clobbered
271 j 3f
272
273# if XCHAL_HAVE_XLT_CACHEATTR
274 // Can do translations, use generic method:
2751: sub a6, a3, a5 // address of some other segment
276 ritlb1 a8, a6 // save its PPN+CA
277 dsync // interlock??
278 witlb a4, a6 // make it translate to this code area
279 movi a6, 5f // where to jump into it
280 isync
281 sub a6, a6, a5 // adjust jump address within that other segment
282 jx a6
283
284 // Note that in the following code snippet, which runs at a different virtual
285 // address than it is assembled for, we avoid using literals (eg. via movi/l32r)
286 // just in case literals end up in a different 512 MB segment, and we avoid
287 // instructions that rely on the current PC being what is expected.
288 //
289 .align 4
290 _j 6f // this is at label '5' minus 4 bytes
291 .align 4
2925: witlb a4, a3 // we're in other segment, now can write previous segment's CA
293 isync
294 add a6, a6, a5 // back to previous segment
295 addi a6, a6, -4 // next jump label
296 jx a6
297
2986: sub a6, a3, a5 // address of some other segment
299 witlb a8, a6 // restore PPN+CA of other segment
300 mov a6, a3 // restore a6
301 isync
302# else /* XCHAL_HAVE_XLT_CACHEATTR */
303 // Use micro-architecture specific method.
304 // The following 4-instruction sequence is aligned such that
305 // it all fits within a single I-cache line. Sixteen byte
306 // alignment is sufficient for this (using XCHAL_ICACHE_LINESIZE
307 // actually causes problems because that can be greater than
308 // the alignment of the reset vector, where this macro is often
309 // invoked, which would cause the linker to align the reset
310 // vector code away from the reset vector!!).
311 .align 16 /*XCHAL_ICACHE_LINESIZE*/
3121: _witlb a4, a3 // write wired PTE (CA, no PPN) of 512MB segment to ITLB
313 _isync
314 nop
315 nop
316# endif /* XCHAL_HAVE_XLT_CACHEATTR */
317 beq a3, a5, 4f // done?
318
319 // Note that in the WITLB loop, we don't do any load/stores
320 // (may not be an issue here, but it is important in the DTLB case).
3212: srli a7, a7, 4 // next CA
322 sub a3, a3, a5 // next segment (add 0x20000000)
3233:
324# if XCHAL_HAVE_XLT_CACHEATTR /* if have translation, preserve it */
325 ritlb1 a8, a3 // get current PPN+CA of segment
326 dsync // interlock???
327 extui a4, a7, 0, 4 // extract CA to set
328 srli a8, a8, 4 // clear CA but keep PPN ...
329 slli a8, a8, 4 // ...
330 add a4, a4, a8 // combine new CA with PPN to preserve
331# else
332 extui a4, a7, 0, 4 // extract CA
333# endif
334 beq a3, a6, 1b // current PC's region? if so, do it in a safe way
335 witlb a4, a3 // write wired PTE (CA [+PPN]) of 512MB segment to ITLB
336 bne a3, a5, 2b
337 isync // make sure all ifetch changes take effect
3384:
339 .endm // icacheattr_set
340
341
342/*
343 * dcacheattr_set
344 *
345 * Entry:
346 * a2 cacheattr value to set
347 * Exit:
348 * a2 unchanged
349 * a3-a8 clobbered (temporaries)
350 */
351
352 .macro dcacheattr_set
353
354 movi a5, 0xE0000000 // mask of upper 3 bits
355 movi a3, 0 // start at region 0 (0 .. 7)
356 mov a7, a2 // copy a2 so it doesn't get clobbered
357 j 3f
358 // Note that in the WDTLB loop, we don't do any load/stores
359 // (including implicit l32r via movi) because it isn't safe.
3602: srli a7, a7, 4 // next CA
361 sub a3, a3, a5 // next segment (add 0x20000000)
3623:
363# if XCHAL_HAVE_XLT_CACHEATTR /* if have translation, preserve it */
364 rdtlb1 a8, a3 // get current PPN+CA of segment
365 dsync // interlock???
366 extui a4, a7, 0, 4 // extract CA to set
367 srli a8, a8, 4 // clear CA but keep PPN ...
368 slli a8, a8, 4 // ...
369 add a4, a4, a8 // combine new CA with PPN to preserve
370# else
371 extui a4, a7, 0, 4 // extract CA to set
372# endif
373 wdtlb a4, a3 // write wired PTE (CA [+PPN]) of 512MB segment to DTLB
374 bne a3, a5, 2b
375 dsync // make sure all data path changes take effect
376 .endm // dcacheattr_set
377
378#endif /* XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR */
379
380
381
382/*
383 * cacheattr_set
384 *
385 * Macro that sets the current CACHEATTR safely
386 * (both i and d) according to the current contents of a2.
387 * It works even when changing the cache attributes of
388 * the currently running code.
389 *
390 * Entry:
391 * a2 cacheattr value to set
392 * Exit:
393 * a2 unchanged
394 * a3-a8 clobbered (temporaries)
395 */
396 .macro cacheattr_set
397
398#if XCHAL_HAVE_CACHEATTR
399# if XCHAL_ICACHE_LINESIZE < 4
400 // No i-cache, so can always safely write to CACHEATTR:
401 wsr a2, CACHEATTR
402# else
403 // The Athens micro-architecture, when using the old
404 // exception architecture option (ie. with the CACHEATTR register)
405 // allows changing the cache attributes of the running code
406 // using the following exact sequence aligned to be within
407 // an instruction cache line. (NOTE: using XCHAL_ICACHE_LINESIZE
408 // alignment actually causes problems because that can be greater
409 // than the alignment of the reset vector, where this macro is often
410 // invoked, which would cause the linker to align the reset
411 // vector code away from the reset vector!!).
412 j 1f
413 .align 16 /*XCHAL_ICACHE_LINESIZE*/ // align to within an I-cache line
4141: _wsr a2, CACHEATTR
415 _isync
416 nop
417 nop
418# endif
419#elif XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR
420 // DTLB and ITLB are independent, but to keep semantics
421 // of this macro we simply write to both.
422 icacheattr_set
423 dcacheattr_set
424#else
425 // This macro isn't applicable to arbitrary MMU configurations.
426 // Do nothing in this case.
427#endif
428 .endm
429
430
431#endif /*XTENSA_CACHEATTRASM_H*/
432
diff --git a/include/asm-xtensa/xtensa/config-linux_be/core.h b/include/asm-xtensa/xtensa/config-linux_be/core.h
new file mode 100644
index 000000000000..d54fe5eb1064
--- /dev/null
+++ b/include/asm-xtensa/xtensa/config-linux_be/core.h
@@ -0,0 +1,1270 @@
1/*
2 * xtensa/config/core.h -- HAL definitions that are dependent on CORE configuration
3 *
4 * This header file is sometimes referred to as the "compile-time HAL" or CHAL.
5 * It was generated for a specific Xtensa processor configuration.
6 *
7 * Source for configuration-independent binaries (which link in a
8 * configuration-specific HAL library) must NEVER include this file.
9 * It is perfectly normal, however, for the HAL source itself to include this file.
10 */
11
12/*
13 * Copyright (c) 2003 Tensilica, Inc. All Rights Reserved.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of version 2.1 of the GNU Lesser General Public
17 * License as published by the Free Software Foundation.
18 *
19 * This program is distributed in the hope that it would be useful, but
20 * WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
22 *
23 * Further, this software is distributed without any warranty that it is
24 * free of the rightful claim of any third person regarding infringement
25 * or the like. Any license provided herein, whether implied or
26 * otherwise, applies only to this software file. Patent licenses, if
27 * any, provided herein do not apply to combinations of this program with
28 * other software, or any other product whatsoever.
29 *
30 * You should have received a copy of the GNU Lesser General Public
31 * License along with this program; if not, write the Free Software
32 * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
33 * USA.
34 */
35
36
37#ifndef XTENSA_CONFIG_CORE_H
38#define XTENSA_CONFIG_CORE_H
39
40#include <xtensa/hal.h>
41
42
43/*----------------------------------------------------------------------
44 GENERAL
45 ----------------------------------------------------------------------*/
46
47/*
48 * Separators for macros that expand into arrays.
49 * These can be predefined by files that #include this one,
50 * when different separators are required.
51 */
52/* Element separator for macros that expand into 1-dimensional arrays: */
53#ifndef XCHAL_SEP
54#define XCHAL_SEP ,
55#endif
56/* Array separator for macros that expand into 2-dimensional arrays: */
57#ifndef XCHAL_SEP2
58#define XCHAL_SEP2 },{
59#endif
60
61
62/*----------------------------------------------------------------------
63 ENDIANNESS
64 ----------------------------------------------------------------------*/
65
66#define XCHAL_HAVE_BE 1
67#define XCHAL_HAVE_LE 0
68#define XCHAL_MEMORY_ORDER XTHAL_BIGENDIAN
69
70
71/*----------------------------------------------------------------------
72 REGISTER WINDOWS
73 ----------------------------------------------------------------------*/
74
75#define XCHAL_HAVE_WINDOWED 1 /* 1 if windowed registers option configured, 0 otherwise */
76#define XCHAL_NUM_AREGS 64 /* number of physical address regs */
77#define XCHAL_NUM_AREGS_LOG2 6 /* log2(XCHAL_NUM_AREGS) */
78
79
80/*----------------------------------------------------------------------
81 ADDRESS ALIGNMENT
82 ----------------------------------------------------------------------*/
83
84/* These apply to a selected set of core load and store instructions only (see ISA): */
85#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* 1 if unaligned loads cause an exception, 0 otherwise */
86#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* 1 if unaligned stores cause an exception, 0 otherwise */
87
88
89/*----------------------------------------------------------------------
90 INTERRUPTS
91 ----------------------------------------------------------------------*/
92
93#define XCHAL_HAVE_INTERRUPTS 1 /* 1 if interrupt option configured, 0 otherwise */
94#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* 1 if high-priority interrupt option configured, 0 otherwise */
95#define XCHAL_HAVE_HIGHLEVEL_INTERRUPTS XCHAL_HAVE_HIGHPRI_INTERRUPTS
96#define XCHAL_HAVE_NMI 0 /* 1 if NMI option configured, 0 otherwise */
97#define XCHAL_NUM_INTERRUPTS 17 /* number of interrupts */
98#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* number of bits to hold an interrupt number: roundup(log2(number of interrupts)) */
99#define XCHAL_NUM_EXTINTERRUPTS 10 /* number of external interrupts */
100#define XCHAL_NUM_INTLEVELS 4 /* number of interrupt levels (not including level zero!) */
101#define XCHAL_NUM_LOWPRI_LEVELS 1 /* number of low-priority interrupt levels (always 1) */
102#define XCHAL_FIRST_HIGHPRI_LEVEL (XCHAL_NUM_LOWPRI_LEVELS+1) /* level of first high-priority interrupt (always 2) */
103#define XCHAL_EXCM_LEVEL 1 /* level of interrupts masked by PS.EXCM (XEA2 only; always 1 in T10xx);
104 for XEA1, where there is no PS.EXCM, this is always 1;
105 interrupts at levels FIRST_HIGHPRI <= n <= EXCM_LEVEL, if any,
106 are termed "medium priority" interrupts (post T10xx only) */
107/* Note: 1 <= LOWPRI_LEVELS <= EXCM_LEVEL < DEBUGLEVEL <= NUM_INTLEVELS < NMILEVEL <= 15 */
108
109/* Masks of interrupts at each interrupt level: */
110#define XCHAL_INTLEVEL0_MASK 0x00000000
111#define XCHAL_INTLEVEL1_MASK 0x000064F9
112#define XCHAL_INTLEVEL2_MASK 0x00008902
113#define XCHAL_INTLEVEL3_MASK 0x00011204
114#define XCHAL_INTLEVEL4_MASK 0x00000000
115#define XCHAL_INTLEVEL5_MASK 0x00000000
116#define XCHAL_INTLEVEL6_MASK 0x00000000
117#define XCHAL_INTLEVEL7_MASK 0x00000000
118#define XCHAL_INTLEVEL8_MASK 0x00000000
119#define XCHAL_INTLEVEL9_MASK 0x00000000
120#define XCHAL_INTLEVEL10_MASK 0x00000000
121#define XCHAL_INTLEVEL11_MASK 0x00000000
122#define XCHAL_INTLEVEL12_MASK 0x00000000
123#define XCHAL_INTLEVEL13_MASK 0x00000000
124#define XCHAL_INTLEVEL14_MASK 0x00000000
125#define XCHAL_INTLEVEL15_MASK 0x00000000
126/* As an array of entries (eg. for C constant arrays): */
127#define XCHAL_INTLEVEL_MASKS 0x00000000 XCHAL_SEP \
128 0x000064F9 XCHAL_SEP \
129 0x00008902 XCHAL_SEP \
130 0x00011204 XCHAL_SEP \
131 0x00000000 XCHAL_SEP \
132 0x00000000 XCHAL_SEP \
133 0x00000000 XCHAL_SEP \
134 0x00000000 XCHAL_SEP \
135 0x00000000 XCHAL_SEP \
136 0x00000000 XCHAL_SEP \
137 0x00000000 XCHAL_SEP \
138 0x00000000 XCHAL_SEP \
139 0x00000000 XCHAL_SEP \
140 0x00000000 XCHAL_SEP \
141 0x00000000 XCHAL_SEP \
142 0x00000000
143
144/* Masks of interrupts at each range 1..n of interrupt levels: */
145#define XCHAL_INTLEVEL0_ANDBELOW_MASK 0x00000000
146#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x000064F9
147#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x0000EDFB
148#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x0001FFFF
149#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x0001FFFF
150#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x0001FFFF
151#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x0001FFFF
152#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x0001FFFF
153#define XCHAL_INTLEVEL8_ANDBELOW_MASK 0x0001FFFF
154#define XCHAL_INTLEVEL9_ANDBELOW_MASK 0x0001FFFF
155#define XCHAL_INTLEVEL10_ANDBELOW_MASK 0x0001FFFF
156#define XCHAL_INTLEVEL11_ANDBELOW_MASK 0x0001FFFF
157#define XCHAL_INTLEVEL12_ANDBELOW_MASK 0x0001FFFF
158#define XCHAL_INTLEVEL13_ANDBELOW_MASK 0x0001FFFF
159#define XCHAL_INTLEVEL14_ANDBELOW_MASK 0x0001FFFF
160#define XCHAL_INTLEVEL15_ANDBELOW_MASK 0x0001FFFF
161#define XCHAL_LOWPRI_MASK XCHAL_INTLEVEL1_ANDBELOW_MASK /* mask of all low-priority interrupts */
162#define XCHAL_EXCM_MASK XCHAL_INTLEVEL1_ANDBELOW_MASK /* mask of all interrupts masked by PS.EXCM (or CEXCM) */
163/* As an array of entries (eg. for C constant arrays): */
164#define XCHAL_INTLEVEL_ANDBELOW_MASKS 0x00000000 XCHAL_SEP \
165 0x000064F9 XCHAL_SEP \
166 0x0000EDFB XCHAL_SEP \
167 0x0001FFFF XCHAL_SEP \
168 0x0001FFFF XCHAL_SEP \
169 0x0001FFFF XCHAL_SEP \
170 0x0001FFFF XCHAL_SEP \
171 0x0001FFFF XCHAL_SEP \
172 0x0001FFFF XCHAL_SEP \
173 0x0001FFFF XCHAL_SEP \
174 0x0001FFFF XCHAL_SEP \
175 0x0001FFFF XCHAL_SEP \
176 0x0001FFFF XCHAL_SEP \
177 0x0001FFFF XCHAL_SEP \
178 0x0001FFFF XCHAL_SEP \
179 0x0001FFFF
180
181/* Interrupt numbers for each interrupt level at which only one interrupt was configured: */
182/*#define XCHAL_INTLEVEL1_NUM ...more than one interrupt at this level...*/
183/*#define XCHAL_INTLEVEL2_NUM ...more than one interrupt at this level...*/
184/*#define XCHAL_INTLEVEL3_NUM ...more than one interrupt at this level...*/
185
186/* Level of each interrupt: */
187#define XCHAL_INT0_LEVEL 1
188#define XCHAL_INT1_LEVEL 2
189#define XCHAL_INT2_LEVEL 3
190#define XCHAL_INT3_LEVEL 1
191#define XCHAL_INT4_LEVEL 1
192#define XCHAL_INT5_LEVEL 1
193#define XCHAL_INT6_LEVEL 1
194#define XCHAL_INT7_LEVEL 1
195#define XCHAL_INT8_LEVEL 2
196#define XCHAL_INT9_LEVEL 3
197#define XCHAL_INT10_LEVEL 1
198#define XCHAL_INT11_LEVEL 2
199#define XCHAL_INT12_LEVEL 3
200#define XCHAL_INT13_LEVEL 1
201#define XCHAL_INT14_LEVEL 1
202#define XCHAL_INT15_LEVEL 2
203#define XCHAL_INT16_LEVEL 3
204#define XCHAL_INT17_LEVEL 0
205#define XCHAL_INT18_LEVEL 0
206#define XCHAL_INT19_LEVEL 0
207#define XCHAL_INT20_LEVEL 0
208#define XCHAL_INT21_LEVEL 0
209#define XCHAL_INT22_LEVEL 0
210#define XCHAL_INT23_LEVEL 0
211#define XCHAL_INT24_LEVEL 0
212#define XCHAL_INT25_LEVEL 0
213#define XCHAL_INT26_LEVEL 0
214#define XCHAL_INT27_LEVEL 0
215#define XCHAL_INT28_LEVEL 0
216#define XCHAL_INT29_LEVEL 0
217#define XCHAL_INT30_LEVEL 0
218#define XCHAL_INT31_LEVEL 0
219/* As an array of entries (eg. for C constant arrays): */
220#define XCHAL_INT_LEVELS 1 XCHAL_SEP \
221 2 XCHAL_SEP \
222 3 XCHAL_SEP \
223 1 XCHAL_SEP \
224 1 XCHAL_SEP \
225 1 XCHAL_SEP \
226 1 XCHAL_SEP \
227 1 XCHAL_SEP \
228 2 XCHAL_SEP \
229 3 XCHAL_SEP \
230 1 XCHAL_SEP \
231 2 XCHAL_SEP \
232 3 XCHAL_SEP \
233 1 XCHAL_SEP \
234 1 XCHAL_SEP \
235 2 XCHAL_SEP \
236 3 XCHAL_SEP \
237 0 XCHAL_SEP \
238 0 XCHAL_SEP \
239 0 XCHAL_SEP \
240 0 XCHAL_SEP \
241 0 XCHAL_SEP \
242 0 XCHAL_SEP \
243 0 XCHAL_SEP \
244 0 XCHAL_SEP \
245 0 XCHAL_SEP \
246 0 XCHAL_SEP \
247 0 XCHAL_SEP \
248 0 XCHAL_SEP \
249 0 XCHAL_SEP \
250 0 XCHAL_SEP \
251 0
252
253/* Type of each interrupt: */
254#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
255#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
256#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
257#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
258#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
259#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
260#define XCHAL_INT6_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
261#define XCHAL_INT7_TYPE XTHAL_INTTYPE_EXTERN_EDGE
262#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_EDGE
263#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_EDGE
264#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER
265#define XCHAL_INT11_TYPE XTHAL_INTTYPE_TIMER
266#define XCHAL_INT12_TYPE XTHAL_INTTYPE_TIMER
267#define XCHAL_INT13_TYPE XTHAL_INTTYPE_SOFTWARE
268#define XCHAL_INT14_TYPE XTHAL_INTTYPE_SOFTWARE
269#define XCHAL_INT15_TYPE XTHAL_INTTYPE_SOFTWARE
270#define XCHAL_INT16_TYPE XTHAL_INTTYPE_SOFTWARE
271#define XCHAL_INT17_TYPE XTHAL_INTTYPE_UNCONFIGURED
272#define XCHAL_INT18_TYPE XTHAL_INTTYPE_UNCONFIGURED
273#define XCHAL_INT19_TYPE XTHAL_INTTYPE_UNCONFIGURED
274#define XCHAL_INT20_TYPE XTHAL_INTTYPE_UNCONFIGURED
275#define XCHAL_INT21_TYPE XTHAL_INTTYPE_UNCONFIGURED
276#define XCHAL_INT22_TYPE XTHAL_INTTYPE_UNCONFIGURED
277#define XCHAL_INT23_TYPE XTHAL_INTTYPE_UNCONFIGURED
278#define XCHAL_INT24_TYPE XTHAL_INTTYPE_UNCONFIGURED
279#define XCHAL_INT25_TYPE XTHAL_INTTYPE_UNCONFIGURED
280#define XCHAL_INT26_TYPE XTHAL_INTTYPE_UNCONFIGURED
281#define XCHAL_INT27_TYPE XTHAL_INTTYPE_UNCONFIGURED
282#define XCHAL_INT28_TYPE XTHAL_INTTYPE_UNCONFIGURED
283#define XCHAL_INT29_TYPE XTHAL_INTTYPE_UNCONFIGURED
284#define XCHAL_INT30_TYPE XTHAL_INTTYPE_UNCONFIGURED
285#define XCHAL_INT31_TYPE XTHAL_INTTYPE_UNCONFIGURED
286/* As an array of entries (eg. for C constant arrays): */
287#define XCHAL_INT_TYPES XTHAL_INTTYPE_EXTERN_LEVEL XCHAL_SEP \
288 XTHAL_INTTYPE_EXTERN_LEVEL XCHAL_SEP \
289 XTHAL_INTTYPE_EXTERN_LEVEL XCHAL_SEP \
290 XTHAL_INTTYPE_EXTERN_LEVEL XCHAL_SEP \
291 XTHAL_INTTYPE_EXTERN_LEVEL XCHAL_SEP \
292 XTHAL_INTTYPE_EXTERN_LEVEL XCHAL_SEP \
293 XTHAL_INTTYPE_EXTERN_LEVEL XCHAL_SEP \
294 XTHAL_INTTYPE_EXTERN_EDGE XCHAL_SEP \
295 XTHAL_INTTYPE_EXTERN_EDGE XCHAL_SEP \
296 XTHAL_INTTYPE_EXTERN_EDGE XCHAL_SEP \
297 XTHAL_INTTYPE_TIMER XCHAL_SEP \
298 XTHAL_INTTYPE_TIMER XCHAL_SEP \
299 XTHAL_INTTYPE_TIMER XCHAL_SEP \
300 XTHAL_INTTYPE_SOFTWARE XCHAL_SEP \
301 XTHAL_INTTYPE_SOFTWARE XCHAL_SEP \
302 XTHAL_INTTYPE_SOFTWARE XCHAL_SEP \
303 XTHAL_INTTYPE_SOFTWARE XCHAL_SEP \
304 XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
305 XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
306 XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
307 XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
308 XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
309 XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
310 XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
311 XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
312 XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
313 XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
314 XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
315 XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
316 XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
317 XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
318 XTHAL_INTTYPE_UNCONFIGURED
319
320/* Masks of interrupts for each type of interrupt: */
321#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFFE0000
322#define XCHAL_INTTYPE_MASK_SOFTWARE 0x0001E000
323#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00000380
324#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000007F
325#define XCHAL_INTTYPE_MASK_TIMER 0x00001C00
326#define XCHAL_INTTYPE_MASK_NMI 0x00000000
327/* As an array of entries (eg. for C constant arrays): */
328#define XCHAL_INTTYPE_MASKS 0xFFFE0000 XCHAL_SEP \
329 0x0001E000 XCHAL_SEP \
330 0x00000380 XCHAL_SEP \
331 0x0000007F XCHAL_SEP \
332 0x00001C00 XCHAL_SEP \
333 0x00000000
334
335/* Interrupts assigned to each timer (CCOMPARE0 to CCOMPARE3), -1 if unassigned */
336#define XCHAL_TIMER0_INTERRUPT 10
337#define XCHAL_TIMER1_INTERRUPT 11
338#define XCHAL_TIMER2_INTERRUPT 12
339#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
340/* As an array of entries (eg. for C constant arrays): */
341#define XCHAL_TIMER_INTERRUPTS 10 XCHAL_SEP \
342 11 XCHAL_SEP \
343 12 XCHAL_SEP \
344 XTHAL_TIMER_UNCONFIGURED
345
346/* Indexing macros: */
347#define _XCHAL_INTLEVEL_MASK(n) XCHAL_INTLEVEL ## n ## _MASK
348#define XCHAL_INTLEVEL_MASK(n) _XCHAL_INTLEVEL_MASK(n) /* n = 0 .. 15 */
349#define _XCHAL_INTLEVEL_ANDBELOWMASK(n) XCHAL_INTLEVEL ## n ## _ANDBELOW_MASK
350#define XCHAL_INTLEVEL_ANDBELOW_MASK(n) _XCHAL_INTLEVEL_ANDBELOWMASK(n) /* n = 0 .. 15 */
351#define _XCHAL_INT_LEVEL(n) XCHAL_INT ## n ## _LEVEL
352#define XCHAL_INT_LEVEL(n) _XCHAL_INT_LEVEL(n) /* n = 0 .. 31 */
353#define _XCHAL_INT_TYPE(n) XCHAL_INT ## n ## _TYPE
354#define XCHAL_INT_TYPE(n) _XCHAL_INT_TYPE(n) /* n = 0 .. 31 */
355#define _XCHAL_TIMER_INTERRUPT(n) XCHAL_TIMER ## n ## _INTERRUPT
356#define XCHAL_TIMER_INTERRUPT(n) _XCHAL_TIMER_INTERRUPT(n) /* n = 0 .. 3 */
357
358
359
360/*
361 * External interrupt vectors/levels.
362 * These macros describe how Xtensa processor interrupt numbers
363 * (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
364 * map to external BInterrupt<n> pins, for those interrupts
365 * configured as external (level-triggered, edge-triggered, or NMI).
366 * See the Xtensa processor databook for more details.
367 */
368
369/* Core interrupt numbers mapped to each EXTERNAL interrupt number: */
370#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
371#define XCHAL_EXTINT1_NUM 1 /* (intlevel 2) */
372#define XCHAL_EXTINT2_NUM 2 /* (intlevel 3) */
373#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
374#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
375#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
376#define XCHAL_EXTINT6_NUM 6 /* (intlevel 1) */
377#define XCHAL_EXTINT7_NUM 7 /* (intlevel 1) */
378#define XCHAL_EXTINT8_NUM 8 /* (intlevel 2) */
379#define XCHAL_EXTINT9_NUM 9 /* (intlevel 3) */
380
381/* Corresponding interrupt masks: */
382#define XCHAL_EXTINT0_MASK 0x00000001
383#define XCHAL_EXTINT1_MASK 0x00000002
384#define XCHAL_EXTINT2_MASK 0x00000004
385#define XCHAL_EXTINT3_MASK 0x00000008
386#define XCHAL_EXTINT4_MASK 0x00000010
387#define XCHAL_EXTINT5_MASK 0x00000020
388#define XCHAL_EXTINT6_MASK 0x00000040
389#define XCHAL_EXTINT7_MASK 0x00000080
390#define XCHAL_EXTINT8_MASK 0x00000100
391#define XCHAL_EXTINT9_MASK 0x00000200
392
393/* Core config interrupt levels mapped to each external interrupt: */
394#define XCHAL_EXTINT0_LEVEL 1 /* (int number 0) */
395#define XCHAL_EXTINT1_LEVEL 2 /* (int number 1) */
396#define XCHAL_EXTINT2_LEVEL 3 /* (int number 2) */
397#define XCHAL_EXTINT3_LEVEL 1 /* (int number 3) */
398#define XCHAL_EXTINT4_LEVEL 1 /* (int number 4) */
399#define XCHAL_EXTINT5_LEVEL 1 /* (int number 5) */
400#define XCHAL_EXTINT6_LEVEL 1 /* (int number 6) */
401#define XCHAL_EXTINT7_LEVEL 1 /* (int number 7) */
402#define XCHAL_EXTINT8_LEVEL 2 /* (int number 8) */
403#define XCHAL_EXTINT9_LEVEL 3 /* (int number 9) */
404
405
406/*----------------------------------------------------------------------
407 EXCEPTIONS and VECTORS
408 ----------------------------------------------------------------------*/
409
410#define XCHAL_HAVE_EXCEPTIONS 1 /* 1 if exception option configured, 0 otherwise */
411
412#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture number: 1 for XEA1 (old), 2 for XEA2 (new) */
413#define XCHAL_HAVE_XEA1 0 /* 1 if XEA1, 0 otherwise */
414#define XCHAL_HAVE_XEA2 1 /* 1 if XEA2, 0 otherwise */
415/* For backward compatibility ONLY -- DO NOT USE (will be removed in future release): */
416#define XCHAL_HAVE_OLD_EXC_ARCH XCHAL_HAVE_XEA1 /* (DEPRECATED) 1 if old exception architecture (XEA1), 0 otherwise (eg. XEA2) */
417#define XCHAL_HAVE_EXCM XCHAL_HAVE_XEA2 /* (DEPRECATED) 1 if PS.EXCM bit exists (currently equals XCHAL_HAVE_TLBS) */
418
419#define XCHAL_RESET_VECTOR_VADDR 0xFE000020
420#define XCHAL_RESET_VECTOR_PADDR 0xFE000020
421#define XCHAL_USER_VECTOR_VADDR 0xD0000220
422#define XCHAL_PROGRAMEXC_VECTOR_VADDR XCHAL_USER_VECTOR_VADDR /* for backward compatibility */
423#define XCHAL_USEREXC_VECTOR_VADDR XCHAL_USER_VECTOR_VADDR /* for backward compatibility */
424#define XCHAL_USER_VECTOR_PADDR 0x00000220
425#define XCHAL_PROGRAMEXC_VECTOR_PADDR XCHAL_USER_VECTOR_PADDR /* for backward compatibility */
426#define XCHAL_USEREXC_VECTOR_PADDR XCHAL_USER_VECTOR_PADDR /* for backward compatibility */
427#define XCHAL_KERNEL_VECTOR_VADDR 0xD0000200
428#define XCHAL_STACKEDEXC_VECTOR_VADDR XCHAL_KERNEL_VECTOR_VADDR /* for backward compatibility */
429#define XCHAL_KERNELEXC_VECTOR_VADDR XCHAL_KERNEL_VECTOR_VADDR /* for backward compatibility */
430#define XCHAL_KERNEL_VECTOR_PADDR 0x00000200
431#define XCHAL_STACKEDEXC_VECTOR_PADDR XCHAL_KERNEL_VECTOR_PADDR /* for backward compatibility */
432#define XCHAL_KERNELEXC_VECTOR_PADDR XCHAL_KERNEL_VECTOR_PADDR /* for backward compatibility */
433#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0xD0000290
434#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x00000290
435#define XCHAL_WINDOW_VECTORS_VADDR 0xD0000000
436#define XCHAL_WINDOW_VECTORS_PADDR 0x00000000
437#define XCHAL_INTLEVEL2_VECTOR_VADDR 0xD0000240
438#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x00000240
439#define XCHAL_INTLEVEL3_VECTOR_VADDR 0xD0000250
440#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x00000250
441#define XCHAL_INTLEVEL4_VECTOR_VADDR 0xFE000520
442#define XCHAL_INTLEVEL4_VECTOR_PADDR 0xFE000520
443#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL4_VECTOR_VADDR
444#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL4_VECTOR_PADDR
445
446/* Indexing macros: */
447#define _XCHAL_INTLEVEL_VECTOR_VADDR(n) XCHAL_INTLEVEL ## n ## _VECTOR_VADDR
448#define XCHAL_INTLEVEL_VECTOR_VADDR(n) _XCHAL_INTLEVEL_VECTOR_VADDR(n) /* n = 0 .. 15 */
449
450/*
451 * General Exception Causes
452 * (values of EXCCAUSE special register set by general exceptions,
453 * which vector to the user, kernel, or double-exception vectors):
454 */
455#define XCHAL_EXCCAUSE_ILLEGAL_INSTRUCTION 0 /* Illegal Instruction (IllegalInstruction) */
456#define XCHAL_EXCCAUSE_SYSTEM_CALL 1 /* System Call (SystemCall) */
457#define XCHAL_EXCCAUSE_INSTRUCTION_FETCH_ERROR 2 /* Instruction Fetch Error (InstructionFetchError) */
458#define XCHAL_EXCCAUSE_LOAD_STORE_ERROR 3 /* Load Store Error (LoadStoreError) */
459#define XCHAL_EXCCAUSE_LEVEL1_INTERRUPT 4 /* Level 1 Interrupt (Level1Interrupt) */
460#define XCHAL_EXCCAUSE_ALLOCA 5 /* Stack Extension Assist (Alloca) */
461#define XCHAL_EXCCAUSE_INTEGER_DIVIDE_BY_ZERO 6 /* Integer Divide by Zero (IntegerDivideByZero) */
462#define XCHAL_EXCCAUSE_SPECULATION 7 /* Speculation (Speculation) */
463#define XCHAL_EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction (Privileged) */
464#define XCHAL_EXCCAUSE_UNALIGNED 9 /* Unaligned Load Store (Unaligned) */
465#define XCHAL_EXCCAUSE_ITLB_MISS 16 /* ITlb Miss Exception (ITlbMiss) */
466#define XCHAL_EXCCAUSE_ITLB_MULTIHIT 17 /* ITlb Mutltihit Exception (ITlbMultihit) */
467#define XCHAL_EXCCAUSE_ITLB_PRIVILEGE 18 /* ITlb Privilege Exception (ITlbPrivilege) */
468#define XCHAL_EXCCAUSE_ITLB_SIZE_RESTRICTION 19 /* ITlb Size Restriction Exception (ITlbSizeRestriction) */
469#define XCHAL_EXCCAUSE_FETCH_CACHE_ATTRIBUTE 20 /* Fetch Cache Attribute Exception (FetchCacheAttribute) */
470#define XCHAL_EXCCAUSE_DTLB_MISS 24 /* DTlb Miss Exception (DTlbMiss) */
471#define XCHAL_EXCCAUSE_DTLB_MULTIHIT 25 /* DTlb Multihit Exception (DTlbMultihit) */
472#define XCHAL_EXCCAUSE_DTLB_PRIVILEGE 26 /* DTlb Privilege Exception (DTlbPrivilege) */
473#define XCHAL_EXCCAUSE_DTLB_SIZE_RESTRICTION 27 /* DTlb Size Restriction Exception (DTlbSizeRestriction) */
474#define XCHAL_EXCCAUSE_LOAD_CACHE_ATTRIBUTE 28 /* Load Cache Attribute Exception (LoadCacheAttribute) */
475#define XCHAL_EXCCAUSE_STORE_CACHE_ATTRIBUTE 29 /* Store Cache Attribute Exception (StoreCacheAttribute) */
476#define XCHAL_EXCCAUSE_FLOATING_POINT 40 /* Floating Point Exception (FloatingPoint) */
477
478
479
480/*----------------------------------------------------------------------
481 TIMERS
482 ----------------------------------------------------------------------*/
483
484#define XCHAL_HAVE_CCOUNT 1 /* 1 if have CCOUNT, 0 otherwise */
485/*#define XCHAL_HAVE_TIMERS XCHAL_HAVE_CCOUNT*/
486#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */
487
488
489
490/*----------------------------------------------------------------------
491 DEBUG
492 ----------------------------------------------------------------------*/
493
494#define XCHAL_HAVE_DEBUG 1 /* 1 if debug option configured, 0 otherwise */
495#define XCHAL_HAVE_OCD 1 /* 1 if OnChipDebug option configured, 0 otherwise */
496#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
497#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
498#define XCHAL_DEBUGLEVEL 4 /* debug interrupt level */
499/*DebugExternalInterrupt 0 0|1*/
500/*DebugUseDIRArray 0 0|1*/
501
502
503
504
505/*----------------------------------------------------------------------
506 COPROCESSORS and EXTRA STATE
507 ----------------------------------------------------------------------*/
508
509#define XCHAL_HAVE_CP 0 /* 1 if coprocessor option configured (CPENABLE present) */
510#define XCHAL_CP_MAXCFG 0 /* max allowed cp id plus one (per cfg) */
511
512#include <xtensa/config/tie.h>
513
514
515
516
517/*----------------------------------------------------------------------
518 INTERNAL I/D RAM/ROMs and XLMI
519 ----------------------------------------------------------------------*/
520
521#define XCHAL_NUM_INSTROM 0 /* number of core instruction ROMs configured */
522#define XCHAL_NUM_INSTRAM 0 /* number of core instruction RAMs configured */
523#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs configured */
524#define XCHAL_NUM_DATARAM 0 /* number of core data RAMs configured */
525#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports configured */
526#define XCHAL_NUM_IROM XCHAL_NUM_INSTROM /* (DEPRECATED) */
527#define XCHAL_NUM_IRAM XCHAL_NUM_INSTRAM /* (DEPRECATED) */
528#define XCHAL_NUM_DROM XCHAL_NUM_DATAROM /* (DEPRECATED) */
529#define XCHAL_NUM_DRAM XCHAL_NUM_DATARAM /* (DEPRECATED) */
530
531
532
533/*----------------------------------------------------------------------
534 CACHE
535 ----------------------------------------------------------------------*/
536
537/* Size of the cache lines in log2(bytes): */
538#define XCHAL_ICACHE_LINEWIDTH 4
539#define XCHAL_DCACHE_LINEWIDTH 4
540/* Size of the cache lines in bytes: */
541#define XCHAL_ICACHE_LINESIZE 16
542#define XCHAL_DCACHE_LINESIZE 16
543/* Max for both I-cache and D-cache (used for general alignment): */
544#define XCHAL_CACHE_LINEWIDTH_MAX 4
545#define XCHAL_CACHE_LINESIZE_MAX 16
546
547/* Number of cache sets in log2(lines per way): */
548#define XCHAL_ICACHE_SETWIDTH 8
549#define XCHAL_DCACHE_SETWIDTH 8
550/* Max for both I-cache and D-cache (used for general cache-coherency page alignment): */
551#define XCHAL_CACHE_SETWIDTH_MAX 8
552#define XCHAL_CACHE_SETSIZE_MAX 256
553
554/* Cache set associativity (number of ways): */
555#define XCHAL_ICACHE_WAYS 2
556#define XCHAL_DCACHE_WAYS 2
557
558/* Size of the caches in bytes (ways * 2^(linewidth + setwidth)): */
559#define XCHAL_ICACHE_SIZE 8192
560#define XCHAL_DCACHE_SIZE 8192
561
562/* Cache features: */
563#define XCHAL_DCACHE_IS_WRITEBACK 0
564/* Whether cache locking feature is available: */
565#define XCHAL_ICACHE_LINE_LOCKABLE 0
566#define XCHAL_DCACHE_LINE_LOCKABLE 0
567
568/* Number of (encoded) cache attribute bits: */
569#define XCHAL_CA_BITS 4 /* number of bits needed to hold cache attribute encoding */
570/* (The number of access mode bits (decoded cache attribute bits) is defined by the architecture; see xtensa/hal.h?) */
571
572
573/* Cache Attribute encodings -- lists of access modes for each cache attribute: */
574#define XCHAL_FCA_LIST XTHAL_FAM_EXCEPTION XCHAL_SEP \
575 XTHAL_FAM_BYPASS XCHAL_SEP \
576 XTHAL_FAM_EXCEPTION XCHAL_SEP \
577 XTHAL_FAM_BYPASS XCHAL_SEP \
578 XTHAL_FAM_EXCEPTION XCHAL_SEP \
579 XTHAL_FAM_CACHED XCHAL_SEP \
580 XTHAL_FAM_EXCEPTION XCHAL_SEP \
581 XTHAL_FAM_CACHED XCHAL_SEP \
582 XTHAL_FAM_EXCEPTION XCHAL_SEP \
583 XTHAL_FAM_CACHED XCHAL_SEP \
584 XTHAL_FAM_EXCEPTION XCHAL_SEP \
585 XTHAL_FAM_CACHED XCHAL_SEP \
586 XTHAL_FAM_EXCEPTION XCHAL_SEP \
587 XTHAL_FAM_EXCEPTION XCHAL_SEP \
588 XTHAL_FAM_EXCEPTION XCHAL_SEP \
589 XTHAL_FAM_EXCEPTION
590#define XCHAL_LCA_LIST XTHAL_LAM_EXCEPTION XCHAL_SEP \
591 XTHAL_LAM_BYPASSG XCHAL_SEP \
592 XTHAL_LAM_EXCEPTION XCHAL_SEP \
593 XTHAL_LAM_BYPASSG XCHAL_SEP \
594 XTHAL_LAM_EXCEPTION XCHAL_SEP \
595 XTHAL_LAM_CACHED XCHAL_SEP \
596 XTHAL_LAM_EXCEPTION XCHAL_SEP \
597 XTHAL_LAM_CACHED XCHAL_SEP \
598 XTHAL_LAM_EXCEPTION XCHAL_SEP \
599 XTHAL_LAM_NACACHED XCHAL_SEP \
600 XTHAL_LAM_EXCEPTION XCHAL_SEP \
601 XTHAL_LAM_NACACHED XCHAL_SEP \
602 XTHAL_LAM_EXCEPTION XCHAL_SEP \
603 XTHAL_LAM_ISOLATE XCHAL_SEP \
604 XTHAL_LAM_EXCEPTION XCHAL_SEP \
605 XTHAL_LAM_CACHED
606#define XCHAL_SCA_LIST XTHAL_SAM_EXCEPTION XCHAL_SEP \
607 XTHAL_SAM_EXCEPTION XCHAL_SEP \
608 XTHAL_SAM_EXCEPTION XCHAL_SEP \
609 XTHAL_SAM_BYPASS XCHAL_SEP \
610 XTHAL_SAM_EXCEPTION XCHAL_SEP \
611 XTHAL_SAM_EXCEPTION XCHAL_SEP \
612 XTHAL_SAM_EXCEPTION XCHAL_SEP \
613 XTHAL_SAM_WRITETHRU XCHAL_SEP \
614 XTHAL_SAM_EXCEPTION XCHAL_SEP \
615 XTHAL_SAM_EXCEPTION XCHAL_SEP \
616 XTHAL_SAM_EXCEPTION XCHAL_SEP \
617 XTHAL_SAM_WRITETHRU XCHAL_SEP \
618 XTHAL_SAM_EXCEPTION XCHAL_SEP \
619 XTHAL_SAM_ISOLATE XCHAL_SEP \
620 XTHAL_SAM_EXCEPTION XCHAL_SEP \
621 XTHAL_SAM_WRITETHRU
622
623/* Test:
624 read/only: 0 + 1 + 2 + 4 + 5 + 6 + 8 + 9 + 10 + 12 + 14
625 read/only: 0 + 1 + 2 + 4 + 5 + 6 + 8 + 9 + 10 + 12 + 14
626 all: 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15
627 fault: 0 + 2 + 4 + 6 + 8 + 10 + 12 + 14
628 r/w/x cached:
629 r/w/x dcached:
630 I-bypass: 1 + 3
631
632 load guard bit set: 1 + 3
633 load guard bit clr: 0 + 2 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15
634 hit-cache r/w/x: 7 + 11
635
636 fams: 5
637 fams: 0 / 6 / 18 / 1 / 2
638 fams: Bypass / Isolate / Cached / Exception / NACached
639
640 MMU okay: yes
641*/
642
643
644/*----------------------------------------------------------------------
645 MMU
646 ----------------------------------------------------------------------*/
647
648/*
649 * General notes on MMU parameters.
650 *
651 * Terminology:
652 * ASID = address-space ID (acts as an "extension" of virtual addresses)
653 * VPN = virtual page number
654 * PPN = physical page number
655 * CA = encoded cache attribute (access modes)
656 * TLB = translation look-aside buffer (term is stretched somewhat here)
657 * I = instruction (fetch accesses)
658 * D = data (load and store accesses)
659 * way = each TLB (ITLB and DTLB) consists of a number of "ways"
660 * that simultaneously match the virtual address of an access;
661 * a TLB successfully translates a virtual address if exactly
662 * one way matches the vaddr; if none match, it is a miss;
663 * if multiple match, one gets a "multihit" exception;
664 * each way can be independently configured in terms of number of
665 * entries, page sizes, which fields are writable or constant, etc.
666 * set = group of contiguous ways with exactly identical parameters
667 * ARF = auto-refill; hardware services a 1st-level miss by loading a PTE
668 * from the page table and storing it in one of the auto-refill ways;
669 * if this PTE load also misses, a miss exception is posted for s/w.
670 * min-wired = a "min-wired" way can be used to map a single (minimum-sized)
671 * page arbitrarily under program control; it has a single entry,
672 * is non-auto-refill (some other way(s) must be auto-refill),
673 * all its fields (VPN, PPN, ASID, CA) are all writable, and it
674 * supports the XCHAL_MMU_MIN_PTE_PAGE_SIZE page size (a current
675 * restriction is that this be the only page size it supports).
676 *
677 * TLB way entries are virtually indexed.
678 * TLB ways that support multiple page sizes:
679 * - must have all writable VPN and PPN fields;
680 * - can only use one page size at any given time (eg. setup at startup),
681 * selected by the respective ITLBCFG or DTLBCFG special register,
682 * whose bits n*4+3 .. n*4 index the list of page sizes for way n
683 * (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n);
684 * this list may be sparse for auto-refill ways because auto-refill
685 * ways have independent lists of supported page sizes sharing a
686 * common encoding with PTE entries; the encoding is the index into
687 * this list; unsupported sizes for a given way are zero in the list;
688 * selecting unsupported sizes results in undefined hardware behaviour;
689 * - is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition).
690 */
691
692#define XCHAL_HAVE_CACHEATTR 0 /* 1 if CACHEATTR register present, 0 if TLBs present instead */
693#define XCHAL_HAVE_TLBS 1 /* 1 if TLBs present, 0 if CACHEATTR present instead */
694#define XCHAL_HAVE_MMU XCHAL_HAVE_TLBS /* (DEPRECATED; use XCHAL_HAVE_TLBS instead; will be removed in future release) */
695#define XCHAL_HAVE_SPANNING_WAY 0 /* 1 if single way maps entire virtual address space in I+D */
696#define XCHAL_HAVE_IDENTITY_MAP 0 /* 1 if virtual addr == physical addr always, 0 otherwise */
697#define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* 1 if have MMU that mimics a CACHEATTR config (CaMMU) */
698#define XCHAL_HAVE_XLT_CACHEATTR 0 /* 1 if have MMU that mimics a CACHEATTR config, but with translation (CaXltMMU) */
699
700#define XCHAL_MMU_ASID_BITS 8 /* number of bits in ASIDs (address space IDs) */
701#define XCHAL_MMU_ASID_INVALID 0 /* ASID value indicating invalid address space */
702#define XCHAL_MMU_ASID_KERNEL 1 /* ASID value indicating kernel (ring 0) address space */
703#define XCHAL_MMU_RINGS 4 /* number of rings supported (1..4) */
704#define XCHAL_MMU_RING_BITS 2 /* number of bits needed to hold ring number */
705#define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */
706#define XCHAL_MMU_CA_BITS 4 /* number of bits needed to hold cache attribute encoding */
707#define XCHAL_MMU_MAX_PTE_PAGE_SIZE 12 /* max page size in a PTE structure (log2) */
708#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12 /* min page size in a PTE structure (log2) */
709
710
711/*** Instruction TLB: ***/
712
713#define XCHAL_ITLB_WAY_BITS 3 /* number of bits holding the ways */
714#define XCHAL_ITLB_WAYS 7 /* number of ways (n-way set-associative TLB) */
715#define XCHAL_ITLB_ARF_WAYS 4 /* number of auto-refill ways */
716#define XCHAL_ITLB_SETS 4 /* number of sets (groups of ways with identical settings) */
717
718/* Way set to which each way belongs: */
719#define XCHAL_ITLB_WAY0_SET 0
720#define XCHAL_ITLB_WAY1_SET 0
721#define XCHAL_ITLB_WAY2_SET 0
722#define XCHAL_ITLB_WAY3_SET 0
723#define XCHAL_ITLB_WAY4_SET 1
724#define XCHAL_ITLB_WAY5_SET 2
725#define XCHAL_ITLB_WAY6_SET 3
726
727/* Ways sets that are used by hardware auto-refill (ARF): */
728#define XCHAL_ITLB_ARF_SETS 1 /* number of auto-refill sets */
729#define XCHAL_ITLB_ARF_SET0 0 /* index of n'th auto-refill set */
730
731/* Way sets that are "min-wired" (see terminology comment above): */
732#define XCHAL_ITLB_MINWIRED_SETS 0 /* number of "min-wired" sets */
733
734
735/* ITLB way set 0 (group of ways 0 thru 3): */
736#define XCHAL_ITLB_SET0_WAY 0 /* index of first way in this way set */
737#define XCHAL_ITLB_SET0_WAYS 4 /* number of (contiguous) ways in this way set */
738#define XCHAL_ITLB_SET0_ENTRIES_LOG2 2 /* log2(number of entries in this way) */
739#define XCHAL_ITLB_SET0_ENTRIES 4 /* number of entries in this way (always a power of 2) */
740#define XCHAL_ITLB_SET0_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
741#define XCHAL_ITLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */
742#define XCHAL_ITLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */
743#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */
744#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */
745#define XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP;
746 2^PAGESZ_BITS entries in list, unsupported entries are zero */
747#define XCHAL_ITLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
748#define XCHAL_ITLB_SET0_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
749#define XCHAL_ITLB_SET0_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
750#define XCHAL_ITLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
751#define XCHAL_ITLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
752#define XCHAL_ITLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
753#define XCHAL_ITLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
754#define XCHAL_ITLB_SET0_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
755
756/* ITLB way set 1 (group of ways 4 thru 4): */
757#define XCHAL_ITLB_SET1_WAY 4 /* index of first way in this way set */
758#define XCHAL_ITLB_SET1_WAYS 1 /* number of (contiguous) ways in this way set */
759#define XCHAL_ITLB_SET1_ENTRIES_LOG2 2 /* log2(number of entries in this way) */
760#define XCHAL_ITLB_SET1_ENTRIES 4 /* number of entries in this way (always a power of 2) */
761#define XCHAL_ITLB_SET1_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
762#define XCHAL_ITLB_SET1_PAGESIZES 4 /* number of supported page sizes in this way */
763#define XCHAL_ITLB_SET1_PAGESZ_BITS 2 /* number of bits to encode the page size */
764#define XCHAL_ITLB_SET1_PAGESZ_LOG2_MIN 20 /* log2(minimum supported page size) */
765#define XCHAL_ITLB_SET1_PAGESZ_LOG2_MAX 26 /* log2(maximum supported page size) */
766#define XCHAL_ITLB_SET1_PAGESZ_LOG2_LIST 20 XCHAL_SEP 22 XCHAL_SEP 24 XCHAL_SEP 26 /* list of log2(page size)s, separated by XCHAL_SEP;
767 2^PAGESZ_BITS entries in list, unsupported entries are zero */
768#define XCHAL_ITLB_SET1_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
769#define XCHAL_ITLB_SET1_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
770#define XCHAL_ITLB_SET1_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
771#define XCHAL_ITLB_SET1_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
772#define XCHAL_ITLB_SET1_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
773#define XCHAL_ITLB_SET1_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
774#define XCHAL_ITLB_SET1_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
775#define XCHAL_ITLB_SET1_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
776
777/* ITLB way set 2 (group of ways 5 thru 5): */
778#define XCHAL_ITLB_SET2_WAY 5 /* index of first way in this way set */
779#define XCHAL_ITLB_SET2_WAYS 1 /* number of (contiguous) ways in this way set */
780#define XCHAL_ITLB_SET2_ENTRIES_LOG2 1 /* log2(number of entries in this way) */
781#define XCHAL_ITLB_SET2_ENTRIES 2 /* number of entries in this way (always a power of 2) */
782#define XCHAL_ITLB_SET2_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
783#define XCHAL_ITLB_SET2_PAGESIZES 1 /* number of supported page sizes in this way */
784#define XCHAL_ITLB_SET2_PAGESZ_BITS 0 /* number of bits to encode the page size */
785#define XCHAL_ITLB_SET2_PAGESZ_LOG2_MIN 27 /* log2(minimum supported page size) */
786#define XCHAL_ITLB_SET2_PAGESZ_LOG2_MAX 27 /* log2(maximum supported page size) */
787#define XCHAL_ITLB_SET2_PAGESZ_LOG2_LIST 27 /* list of log2(page size)s, separated by XCHAL_SEP;
788 2^PAGESZ_BITS entries in list, unsupported entries are zero */
789#define XCHAL_ITLB_SET2_ASID_CONSTMASK 0xFF /* constant ASID bits; 0 if all writable */
790#define XCHAL_ITLB_SET2_VPN_CONSTMASK 0xF0000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
791#define XCHAL_ITLB_SET2_PPN_CONSTMASK 0xF8000000 /* constant PPN bits, including entry index bits; 0 if all writable */
792#define XCHAL_ITLB_SET2_CA_CONSTMASK 0x0000000F /* constant CA bits; 0 if all writable */
793#define XCHAL_ITLB_SET2_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
794#define XCHAL_ITLB_SET2_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
795#define XCHAL_ITLB_SET2_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
796#define XCHAL_ITLB_SET2_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
797/* Constant ASID values for each entry of ITLB way set 2 (because ASID_CONSTMASK is non-zero): */
798#define XCHAL_ITLB_SET2_E0_ASID_CONST 0x01
799#define XCHAL_ITLB_SET2_E1_ASID_CONST 0x01
800/* Constant VPN values for each entry of ITLB way set 2 (because VPN_CONSTMASK is non-zero): */
801#define XCHAL_ITLB_SET2_E0_VPN_CONST 0xD0000000
802#define XCHAL_ITLB_SET2_E1_VPN_CONST 0xD8000000
803/* Constant PPN values for each entry of ITLB way set 2 (because PPN_CONSTMASK is non-zero): */
804#define XCHAL_ITLB_SET2_E0_PPN_CONST 0x00000000
805#define XCHAL_ITLB_SET2_E1_PPN_CONST 0x00000000
806/* Constant CA values for each entry of ITLB way set 2 (because CA_CONSTMASK is non-zero): */
807#define XCHAL_ITLB_SET2_E0_CA_CONST 0x07
808#define XCHAL_ITLB_SET2_E1_CA_CONST 0x03
809
810/* ITLB way set 3 (group of ways 6 thru 6): */
811#define XCHAL_ITLB_SET3_WAY 6 /* index of first way in this way set */
812#define XCHAL_ITLB_SET3_WAYS 1 /* number of (contiguous) ways in this way set */
813#define XCHAL_ITLB_SET3_ENTRIES_LOG2 1 /* log2(number of entries in this way) */
814#define XCHAL_ITLB_SET3_ENTRIES 2 /* number of entries in this way (always a power of 2) */
815#define XCHAL_ITLB_SET3_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
816#define XCHAL_ITLB_SET3_PAGESIZES 1 /* number of supported page sizes in this way */
817#define XCHAL_ITLB_SET3_PAGESZ_BITS 0 /* number of bits to encode the page size */
818#define XCHAL_ITLB_SET3_PAGESZ_LOG2_MIN 28 /* log2(minimum supported page size) */
819#define XCHAL_ITLB_SET3_PAGESZ_LOG2_MAX 28 /* log2(maximum supported page size) */
820#define XCHAL_ITLB_SET3_PAGESZ_LOG2_LIST 28 /* list of log2(page size)s, separated by XCHAL_SEP;
821 2^PAGESZ_BITS entries in list, unsupported entries are zero */
822#define XCHAL_ITLB_SET3_ASID_CONSTMASK 0xFF /* constant ASID bits; 0 if all writable */
823#define XCHAL_ITLB_SET3_VPN_CONSTMASK 0xE0000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
824#define XCHAL_ITLB_SET3_PPN_CONSTMASK 0xF0000000 /* constant PPN bits, including entry index bits; 0 if all writable */
825#define XCHAL_ITLB_SET3_CA_CONSTMASK 0x0000000F /* constant CA bits; 0 if all writable */
826#define XCHAL_ITLB_SET3_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
827#define XCHAL_ITLB_SET3_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
828#define XCHAL_ITLB_SET3_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
829#define XCHAL_ITLB_SET3_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
830/* Constant ASID values for each entry of ITLB way set 3 (because ASID_CONSTMASK is non-zero): */
831#define XCHAL_ITLB_SET3_E0_ASID_CONST 0x01
832#define XCHAL_ITLB_SET3_E1_ASID_CONST 0x01
833/* Constant VPN values for each entry of ITLB way set 3 (because VPN_CONSTMASK is non-zero): */
834#define XCHAL_ITLB_SET3_E0_VPN_CONST 0xE0000000
835#define XCHAL_ITLB_SET3_E1_VPN_CONST 0xF0000000
836/* Constant PPN values for each entry of ITLB way set 3 (because PPN_CONSTMASK is non-zero): */
837#define XCHAL_ITLB_SET3_E0_PPN_CONST 0xF0000000
838#define XCHAL_ITLB_SET3_E1_PPN_CONST 0xF0000000
839/* Constant CA values for each entry of ITLB way set 3 (because CA_CONSTMASK is non-zero): */
840#define XCHAL_ITLB_SET3_E0_CA_CONST 0x07
841#define XCHAL_ITLB_SET3_E1_CA_CONST 0x03
842
843/* Indexing macros: */
844#define _XCHAL_ITLB_SET(n,_what) XCHAL_ITLB_SET ## n ## _what
845#define XCHAL_ITLB_SET(n,what) _XCHAL_ITLB_SET(n, _ ## what )
846#define _XCHAL_ITLB_SET_E(n,i,_what) XCHAL_ITLB_SET ## n ## _E ## i ## _what
847#define XCHAL_ITLB_SET_E(n,i,what) _XCHAL_ITLB_SET_E(n,i, _ ## what )
848/*
849 * Example use: XCHAL_ITLB_SET(XCHAL_ITLB_ARF_SET0,ENTRIES)
850 * to get the value of XCHAL_ITLB_SET<n>_ENTRIES where <n> is the first auto-refill set.
851 */
852
853
854/*** Data TLB: ***/
855
856#define XCHAL_DTLB_WAY_BITS 4 /* number of bits holding the ways */
857#define XCHAL_DTLB_WAYS 10 /* number of ways (n-way set-associative TLB) */
858#define XCHAL_DTLB_ARF_WAYS 4 /* number of auto-refill ways */
859#define XCHAL_DTLB_SETS 5 /* number of sets (groups of ways with identical settings) */
860
861/* Way set to which each way belongs: */
862#define XCHAL_DTLB_WAY0_SET 0
863#define XCHAL_DTLB_WAY1_SET 0
864#define XCHAL_DTLB_WAY2_SET 0
865#define XCHAL_DTLB_WAY3_SET 0
866#define XCHAL_DTLB_WAY4_SET 1
867#define XCHAL_DTLB_WAY5_SET 2
868#define XCHAL_DTLB_WAY6_SET 3
869#define XCHAL_DTLB_WAY7_SET 4
870#define XCHAL_DTLB_WAY8_SET 4
871#define XCHAL_DTLB_WAY9_SET 4
872
873/* Ways sets that are used by hardware auto-refill (ARF): */
874#define XCHAL_DTLB_ARF_SETS 1 /* number of auto-refill sets */
875#define XCHAL_DTLB_ARF_SET0 0 /* index of n'th auto-refill set */
876
877/* Way sets that are "min-wired" (see terminology comment above): */
878#define XCHAL_DTLB_MINWIRED_SETS 1 /* number of "min-wired" sets */
879#define XCHAL_DTLB_MINWIRED_SET0 4 /* index of n'th "min-wired" set */
880
881
882/* DTLB way set 0 (group of ways 0 thru 3): */
883#define XCHAL_DTLB_SET0_WAY 0 /* index of first way in this way set */
884#define XCHAL_DTLB_SET0_WAYS 4 /* number of (contiguous) ways in this way set */
885#define XCHAL_DTLB_SET0_ENTRIES_LOG2 2 /* log2(number of entries in this way) */
886#define XCHAL_DTLB_SET0_ENTRIES 4 /* number of entries in this way (always a power of 2) */
887#define XCHAL_DTLB_SET0_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
888#define XCHAL_DTLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */
889#define XCHAL_DTLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */
890#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */
891#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */
892#define XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP;
893 2^PAGESZ_BITS entries in list, unsupported entries are zero */
894#define XCHAL_DTLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
895#define XCHAL_DTLB_SET0_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
896#define XCHAL_DTLB_SET0_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
897#define XCHAL_DTLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
898#define XCHAL_DTLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
899#define XCHAL_DTLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
900#define XCHAL_DTLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
901#define XCHAL_DTLB_SET0_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
902
903/* DTLB way set 1 (group of ways 4 thru 4): */
904#define XCHAL_DTLB_SET1_WAY 4 /* index of first way in this way set */
905#define XCHAL_DTLB_SET1_WAYS 1 /* number of (contiguous) ways in this way set */
906#define XCHAL_DTLB_SET1_ENTRIES_LOG2 2 /* log2(number of entries in this way) */
907#define XCHAL_DTLB_SET1_ENTRIES 4 /* number of entries in this way (always a power of 2) */
908#define XCHAL_DTLB_SET1_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
909#define XCHAL_DTLB_SET1_PAGESIZES 4 /* number of supported page sizes in this way */
910#define XCHAL_DTLB_SET1_PAGESZ_BITS 2 /* number of bits to encode the page size */
911#define XCHAL_DTLB_SET1_PAGESZ_LOG2_MIN 20 /* log2(minimum supported page size) */
912#define XCHAL_DTLB_SET1_PAGESZ_LOG2_MAX 26 /* log2(maximum supported page size) */
913#define XCHAL_DTLB_SET1_PAGESZ_LOG2_LIST 20 XCHAL_SEP 22 XCHAL_SEP 24 XCHAL_SEP 26 /* list of log2(page size)s, separated by XCHAL_SEP;
914 2^PAGESZ_BITS entries in list, unsupported entries are zero */
915#define XCHAL_DTLB_SET1_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
916#define XCHAL_DTLB_SET1_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
917#define XCHAL_DTLB_SET1_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
918#define XCHAL_DTLB_SET1_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
919#define XCHAL_DTLB_SET1_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
920#define XCHAL_DTLB_SET1_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
921#define XCHAL_DTLB_SET1_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
922#define XCHAL_DTLB_SET1_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
923
924/* DTLB way set 2 (group of ways 5 thru 5): */
925#define XCHAL_DTLB_SET2_WAY 5 /* index of first way in this way set */
926#define XCHAL_DTLB_SET2_WAYS 1 /* number of (contiguous) ways in this way set */
927#define XCHAL_DTLB_SET2_ENTRIES_LOG2 1 /* log2(number of entries in this way) */
928#define XCHAL_DTLB_SET2_ENTRIES 2 /* number of entries in this way (always a power of 2) */
929#define XCHAL_DTLB_SET2_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
930#define XCHAL_DTLB_SET2_PAGESIZES 1 /* number of supported page sizes in this way */
931#define XCHAL_DTLB_SET2_PAGESZ_BITS 0 /* number of bits to encode the page size */
932#define XCHAL_DTLB_SET2_PAGESZ_LOG2_MIN 27 /* log2(minimum supported page size) */
933#define XCHAL_DTLB_SET2_PAGESZ_LOG2_MAX 27 /* log2(maximum supported page size) */
934#define XCHAL_DTLB_SET2_PAGESZ_LOG2_LIST 27 /* list of log2(page size)s, separated by XCHAL_SEP;
935 2^PAGESZ_BITS entries in list, unsupported entries are zero */
936#define XCHAL_DTLB_SET2_ASID_CONSTMASK 0xFF /* constant ASID bits; 0 if all writable */
937#define XCHAL_DTLB_SET2_VPN_CONSTMASK 0xF0000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
938#define XCHAL_DTLB_SET2_PPN_CONSTMASK 0xF8000000 /* constant PPN bits, including entry index bits; 0 if all writable */
939#define XCHAL_DTLB_SET2_CA_CONSTMASK 0x0000000F /* constant CA bits; 0 if all writable */
940#define XCHAL_DTLB_SET2_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
941#define XCHAL_DTLB_SET2_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
942#define XCHAL_DTLB_SET2_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
943#define XCHAL_DTLB_SET2_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
944/* Constant ASID values for each entry of DTLB way set 2 (because ASID_CONSTMASK is non-zero): */
945#define XCHAL_DTLB_SET2_E0_ASID_CONST 0x01
946#define XCHAL_DTLB_SET2_E1_ASID_CONST 0x01
947/* Constant VPN values for each entry of DTLB way set 2 (because VPN_CONSTMASK is non-zero): */
948#define XCHAL_DTLB_SET2_E0_VPN_CONST 0xD0000000
949#define XCHAL_DTLB_SET2_E1_VPN_CONST 0xD8000000
950/* Constant PPN values for each entry of DTLB way set 2 (because PPN_CONSTMASK is non-zero): */
951#define XCHAL_DTLB_SET2_E0_PPN_CONST 0x00000000
952#define XCHAL_DTLB_SET2_E1_PPN_CONST 0x00000000
953/* Constant CA values for each entry of DTLB way set 2 (because CA_CONSTMASK is non-zero): */
954#define XCHAL_DTLB_SET2_E0_CA_CONST 0x07
955#define XCHAL_DTLB_SET2_E1_CA_CONST 0x03
956
957/* DTLB way set 3 (group of ways 6 thru 6): */
958#define XCHAL_DTLB_SET3_WAY 6 /* index of first way in this way set */
959#define XCHAL_DTLB_SET3_WAYS 1 /* number of (contiguous) ways in this way set */
960#define XCHAL_DTLB_SET3_ENTRIES_LOG2 1 /* log2(number of entries in this way) */
961#define XCHAL_DTLB_SET3_ENTRIES 2 /* number of entries in this way (always a power of 2) */
962#define XCHAL_DTLB_SET3_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
963#define XCHAL_DTLB_SET3_PAGESIZES 1 /* number of supported page sizes in this way */
964#define XCHAL_DTLB_SET3_PAGESZ_BITS 0 /* number of bits to encode the page size */
965#define XCHAL_DTLB_SET3_PAGESZ_LOG2_MIN 28 /* log2(minimum supported page size) */
966#define XCHAL_DTLB_SET3_PAGESZ_LOG2_MAX 28 /* log2(maximum supported page size) */
967#define XCHAL_DTLB_SET3_PAGESZ_LOG2_LIST 28 /* list of log2(page size)s, separated by XCHAL_SEP;
968 2^PAGESZ_BITS entries in list, unsupported entries are zero */
969#define XCHAL_DTLB_SET3_ASID_CONSTMASK 0xFF /* constant ASID bits; 0 if all writable */
970#define XCHAL_DTLB_SET3_VPN_CONSTMASK 0xE0000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
971#define XCHAL_DTLB_SET3_PPN_CONSTMASK 0xF0000000 /* constant PPN bits, including entry index bits; 0 if all writable */
972#define XCHAL_DTLB_SET3_CA_CONSTMASK 0x0000000F /* constant CA bits; 0 if all writable */
973#define XCHAL_DTLB_SET3_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
974#define XCHAL_DTLB_SET3_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
975#define XCHAL_DTLB_SET3_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
976#define XCHAL_DTLB_SET3_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
977/* Constant ASID values for each entry of DTLB way set 3 (because ASID_CONSTMASK is non-zero): */
978#define XCHAL_DTLB_SET3_E0_ASID_CONST 0x01
979#define XCHAL_DTLB_SET3_E1_ASID_CONST 0x01
980/* Constant VPN values for each entry of DTLB way set 3 (because VPN_CONSTMASK is non-zero): */
981#define XCHAL_DTLB_SET3_E0_VPN_CONST 0xE0000000
982#define XCHAL_DTLB_SET3_E1_VPN_CONST 0xF0000000
983/* Constant PPN values for each entry of DTLB way set 3 (because PPN_CONSTMASK is non-zero): */
984#define XCHAL_DTLB_SET3_E0_PPN_CONST 0xF0000000
985#define XCHAL_DTLB_SET3_E1_PPN_CONST 0xF0000000
986/* Constant CA values for each entry of DTLB way set 3 (because CA_CONSTMASK is non-zero): */
987#define XCHAL_DTLB_SET3_E0_CA_CONST 0x07
988#define XCHAL_DTLB_SET3_E1_CA_CONST 0x03
989
990/* DTLB way set 4 (group of ways 7 thru 9): */
991#define XCHAL_DTLB_SET4_WAY 7 /* index of first way in this way set */
992#define XCHAL_DTLB_SET4_WAYS 3 /* number of (contiguous) ways in this way set */
993#define XCHAL_DTLB_SET4_ENTRIES_LOG2 0 /* log2(number of entries in this way) */
994#define XCHAL_DTLB_SET4_ENTRIES 1 /* number of entries in this way (always a power of 2) */
995#define XCHAL_DTLB_SET4_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
996#define XCHAL_DTLB_SET4_PAGESIZES 1 /* number of supported page sizes in this way */
997#define XCHAL_DTLB_SET4_PAGESZ_BITS 0 /* number of bits to encode the page size */
998#define XCHAL_DTLB_SET4_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */
999#define XCHAL_DTLB_SET4_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */
1000#define XCHAL_DTLB_SET4_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP;
1001 2^PAGESZ_BITS entries in list, unsupported entries are zero */
1002#define XCHAL_DTLB_SET4_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
1003#define XCHAL_DTLB_SET4_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
1004#define XCHAL_DTLB_SET4_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
1005#define XCHAL_DTLB_SET4_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
1006#define XCHAL_DTLB_SET4_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
1007#define XCHAL_DTLB_SET4_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
1008#define XCHAL_DTLB_SET4_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
1009#define XCHAL_DTLB_SET4_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
1010
1011/* Indexing macros: */
1012#define _XCHAL_DTLB_SET(n,_what) XCHAL_DTLB_SET ## n ## _what
1013#define XCHAL_DTLB_SET(n,what) _XCHAL_DTLB_SET(n, _ ## what )
1014#define _XCHAL_DTLB_SET_E(n,i,_what) XCHAL_DTLB_SET ## n ## _E ## i ## _what
1015#define XCHAL_DTLB_SET_E(n,i,what) _XCHAL_DTLB_SET_E(n,i, _ ## what )
1016/*
1017 * Example use: XCHAL_DTLB_SET(XCHAL_DTLB_ARF_SET0,ENTRIES)
1018 * to get the value of XCHAL_DTLB_SET<n>_ENTRIES where <n> is the first auto-refill set.
1019 */
1020
1021
1022/*
1023 * Determine whether we have a full MMU (with Page Table and Protection)
1024 * usable for an MMU-based OS:
1025 */
1026#if XCHAL_HAVE_TLBS && !XCHAL_HAVE_SPANNING_WAY && XCHAL_ITLB_ARF_WAYS > 0 && XCHAL_DTLB_ARF_WAYS > 0 && XCHAL_MMU_RINGS >= 2
1027# define XCHAL_HAVE_PTP_MMU 1 /* have full MMU (with page table [autorefill] and protection) */
1028#else
1029# define XCHAL_HAVE_PTP_MMU 0 /* don't have full MMU */
1030#endif
1031
1032/*
1033 * For full MMUs, report kernel RAM segment and kernel I/O segment static page mappings:
1034 */
1035#if XCHAL_HAVE_PTP_MMU
1036#define XCHAL_KSEG_CACHED_VADDR 0xD0000000 /* virt.addr of kernel RAM cached static map */
1037#define XCHAL_KSEG_CACHED_PADDR 0x00000000 /* phys.addr of kseg_cached */
1038#define XCHAL_KSEG_CACHED_SIZE 0x08000000 /* size in bytes of kseg_cached (assumed power of 2!!!) */
1039#define XCHAL_KSEG_BYPASS_VADDR 0xD8000000 /* virt.addr of kernel RAM bypass (uncached) static map */
1040#define XCHAL_KSEG_BYPASS_PADDR 0x00000000 /* phys.addr of kseg_bypass */
1041#define XCHAL_KSEG_BYPASS_SIZE 0x08000000 /* size in bytes of kseg_bypass (assumed power of 2!!!) */
1042
1043#define XCHAL_KIO_CACHED_VADDR 0xE0000000 /* virt.addr of kernel I/O cached static map */
1044#define XCHAL_KIO_CACHED_PADDR 0xF0000000 /* phys.addr of kio_cached */
1045#define XCHAL_KIO_CACHED_SIZE 0x10000000 /* size in bytes of kio_cached (assumed power of 2!!!) */
1046#define XCHAL_KIO_BYPASS_VADDR 0xF0000000 /* virt.addr of kernel I/O bypass (uncached) static map */
1047#define XCHAL_KIO_BYPASS_PADDR 0xF0000000 /* phys.addr of kio_bypass */
1048#define XCHAL_KIO_BYPASS_SIZE 0x10000000 /* size in bytes of kio_bypass (assumed power of 2!!!) */
1049
1050#define XCHAL_SEG_MAPPABLE_VADDR 0x00000000 /* start of largest non-static-mapped virtual addr area */
1051#define XCHAL_SEG_MAPPABLE_SIZE 0xD0000000 /* size in bytes of " */
1052/* define XCHAL_SEG_MAPPABLE2_xxx if more areas present, sorted in order of descending size. */
1053#endif
1054
1055
1056/*----------------------------------------------------------------------
1057 MISC
1058 ----------------------------------------------------------------------*/
1059
1060#define XCHAL_NUM_WRITEBUFFER_ENTRIES 4 /* number of write buffer entries */
1061
1062#define XCHAL_CORE_ID "linux_be" /* configuration's alphanumeric core identifier
1063 (CoreID) set in the Xtensa Processor Generator */
1064
1065#define XCHAL_BUILD_UNIQUE_ID 0x00003256 /* software build-unique ID (22-bit) */
1066
1067/* These definitions describe the hardware targeted by this software: */
1068#define XCHAL_HW_CONFIGID0 0xC103D1FF /* config ID reg 0 value (upper 32 of 64 bits) */
1069#define XCHAL_HW_CONFIGID1 0x00803256 /* config ID reg 1 value (lower 32 of 64 bits) */
1070#define XCHAL_CONFIGID0 XCHAL_HW_CONFIGID0 /* for backward compatibility only -- don't use! */
1071#define XCHAL_CONFIGID1 XCHAL_HW_CONFIGID1 /* for backward compatibility only -- don't use! */
1072#define XCHAL_HW_RELEASE_MAJOR 1050 /* major release of targeted hardware */
1073#define XCHAL_HW_RELEASE_MINOR 1 /* minor release of targeted hardware */
1074#define XCHAL_HW_RELEASE_NAME "T1050.1" /* full release name of targeted hardware */
1075#define XTHAL_HW_REL_T1050 1
1076#define XTHAL_HW_REL_T1050_1 1
1077#define XCHAL_HW_CONFIGID_RELIABLE 1
1078
1079
1080/*
1081 * Miscellaneous special register fields:
1082 */
1083
1084
1085/* DBREAKC (special register number 160): */
1086#define XCHAL_DBREAKC_VALIDMASK 0xC000003F /* bits of DBREAKC that are defined */
1087/* MASK field: */
1088#define XCHAL_DBREAKC_MASK_BITS 6 /* number of bits in MASK field */
1089#define XCHAL_DBREAKC_MASK_NUM 64 /* max number of possible causes (2^bits) */
1090#define XCHAL_DBREAKC_MASK_SHIFT 0 /* position of MASK bits in DBREAKC, starting from lsbit */
1091#define XCHAL_DBREAKC_MASK_MASK 0x0000003F /* mask of bits in MASK field of DBREAKC */
1092/* LOADBREAK field: */
1093#define XCHAL_DBREAKC_LOADBREAK_BITS 1 /* number of bits in LOADBREAK field */
1094#define XCHAL_DBREAKC_LOADBREAK_NUM 2 /* max number of possible causes (2^bits) */
1095#define XCHAL_DBREAKC_LOADBREAK_SHIFT 30 /* position of LOADBREAK bits in DBREAKC, starting from lsbit */
1096#define XCHAL_DBREAKC_LOADBREAK_MASK 0x40000000 /* mask of bits in LOADBREAK field of DBREAKC */
1097/* STOREBREAK field: */
1098#define XCHAL_DBREAKC_STOREBREAK_BITS 1 /* number of bits in STOREBREAK field */
1099#define XCHAL_DBREAKC_STOREBREAK_NUM 2 /* max number of possible causes (2^bits) */
1100#define XCHAL_DBREAKC_STOREBREAK_SHIFT 31 /* position of STOREBREAK bits in DBREAKC, starting from lsbit */
1101#define XCHAL_DBREAKC_STOREBREAK_MASK 0x80000000 /* mask of bits in STOREBREAK field of DBREAKC */
1102
1103/* PS (special register number 230): */
1104#define XCHAL_PS_VALIDMASK 0x00070FFF /* bits of PS that are defined */
1105/* INTLEVEL field: */
1106#define XCHAL_PS_INTLEVEL_BITS 4 /* number of bits in INTLEVEL field */
1107#define XCHAL_PS_INTLEVEL_NUM 16 /* max number of possible causes (2^bits) */
1108#define XCHAL_PS_INTLEVEL_SHIFT 0 /* position of INTLEVEL bits in PS, starting from lsbit */
1109#define XCHAL_PS_INTLEVEL_MASK 0x0000000F /* mask of bits in INTLEVEL field of PS */
1110/* EXCM field: */
1111#define XCHAL_PS_EXCM_BITS 1 /* number of bits in EXCM field */
1112#define XCHAL_PS_EXCM_NUM 2 /* max number of possible causes (2^bits) */
1113#define XCHAL_PS_EXCM_SHIFT 4 /* position of EXCM bits in PS, starting from lsbit */
1114#define XCHAL_PS_EXCM_MASK 0x00000010 /* mask of bits in EXCM field of PS */
1115/* PROGSTACK field: */
1116#define XCHAL_PS_PROGSTACK_BITS 1 /* number of bits in PROGSTACK field */
1117#define XCHAL_PS_PROGSTACK_NUM 2 /* max number of possible causes (2^bits) */
1118#define XCHAL_PS_PROGSTACK_SHIFT 5 /* position of PROGSTACK bits in PS, starting from lsbit */
1119#define XCHAL_PS_PROGSTACK_MASK 0x00000020 /* mask of bits in PROGSTACK field of PS */
1120/* RING field: */
1121#define XCHAL_PS_RING_BITS 2 /* number of bits in RING field */
1122#define XCHAL_PS_RING_NUM 4 /* max number of possible causes (2^bits) */
1123#define XCHAL_PS_RING_SHIFT 6 /* position of RING bits in PS, starting from lsbit */
1124#define XCHAL_PS_RING_MASK 0x000000C0 /* mask of bits in RING field of PS */
1125/* OWB field: */
1126#define XCHAL_PS_OWB_BITS 4 /* number of bits in OWB field */
1127#define XCHAL_PS_OWB_NUM 16 /* max number of possible causes (2^bits) */
1128#define XCHAL_PS_OWB_SHIFT 8 /* position of OWB bits in PS, starting from lsbit */
1129#define XCHAL_PS_OWB_MASK 0x00000F00 /* mask of bits in OWB field of PS */
1130/* CALLINC field: */
1131#define XCHAL_PS_CALLINC_BITS 2 /* number of bits in CALLINC field */
1132#define XCHAL_PS_CALLINC_NUM 4 /* max number of possible causes (2^bits) */
1133#define XCHAL_PS_CALLINC_SHIFT 16 /* position of CALLINC bits in PS, starting from lsbit */
1134#define XCHAL_PS_CALLINC_MASK 0x00030000 /* mask of bits in CALLINC field of PS */
1135/* WOE field: */
1136#define XCHAL_PS_WOE_BITS 1 /* number of bits in WOE field */
1137#define XCHAL_PS_WOE_NUM 2 /* max number of possible causes (2^bits) */
1138#define XCHAL_PS_WOE_SHIFT 18 /* position of WOE bits in PS, starting from lsbit */
1139#define XCHAL_PS_WOE_MASK 0x00040000 /* mask of bits in WOE field of PS */
1140
1141/* EXCCAUSE (special register number 232): */
1142#define XCHAL_EXCCAUSE_VALIDMASK 0x0000003F /* bits of EXCCAUSE that are defined */
1143/* EXCCAUSE field: */
1144#define XCHAL_EXCCAUSE_BITS 6 /* number of bits in EXCCAUSE register */
1145#define XCHAL_EXCCAUSE_NUM 64 /* max number of possible causes (2^bits) */
1146#define XCHAL_EXCCAUSE_SHIFT 0 /* position of EXCCAUSE bits in register, starting from lsbit */
1147#define XCHAL_EXCCAUSE_MASK 0x0000003F /* mask of bits in EXCCAUSE register */
1148
1149/* DEBUGCAUSE (special register number 233): */
1150#define XCHAL_DEBUGCAUSE_VALIDMASK 0x0000003F /* bits of DEBUGCAUSE that are defined */
1151/* ICOUNT field: */
1152#define XCHAL_DEBUGCAUSE_ICOUNT_BITS 1 /* number of bits in ICOUNT field */
1153#define XCHAL_DEBUGCAUSE_ICOUNT_NUM 2 /* max number of possible causes (2^bits) */
1154#define XCHAL_DEBUGCAUSE_ICOUNT_SHIFT 0 /* position of ICOUNT bits in DEBUGCAUSE, starting from lsbit */
1155#define XCHAL_DEBUGCAUSE_ICOUNT_MASK 0x00000001 /* mask of bits in ICOUNT field of DEBUGCAUSE */
1156/* IBREAK field: */
1157#define XCHAL_DEBUGCAUSE_IBREAK_BITS 1 /* number of bits in IBREAK field */
1158#define XCHAL_DEBUGCAUSE_IBREAK_NUM 2 /* max number of possible causes (2^bits) */
1159#define XCHAL_DEBUGCAUSE_IBREAK_SHIFT 1 /* position of IBREAK bits in DEBUGCAUSE, starting from lsbit */
1160#define XCHAL_DEBUGCAUSE_IBREAK_MASK 0x00000002 /* mask of bits in IBREAK field of DEBUGCAUSE */
1161/* DBREAK field: */
1162#define XCHAL_DEBUGCAUSE_DBREAK_BITS 1 /* number of bits in DBREAK field */
1163#define XCHAL_DEBUGCAUSE_DBREAK_NUM 2 /* max number of possible causes (2^bits) */
1164#define XCHAL_DEBUGCAUSE_DBREAK_SHIFT 2 /* position of DBREAK bits in DEBUGCAUSE, starting from lsbit */
1165#define XCHAL_DEBUGCAUSE_DBREAK_MASK 0x00000004 /* mask of bits in DBREAK field of DEBUGCAUSE */
1166/* BREAK field: */
1167#define XCHAL_DEBUGCAUSE_BREAK_BITS 1 /* number of bits in BREAK field */
1168#define XCHAL_DEBUGCAUSE_BREAK_NUM 2 /* max number of possible causes (2^bits) */
1169#define XCHAL_DEBUGCAUSE_BREAK_SHIFT 3 /* position of BREAK bits in DEBUGCAUSE, starting from lsbit */
1170#define XCHAL_DEBUGCAUSE_BREAK_MASK 0x00000008 /* mask of bits in BREAK field of DEBUGCAUSE */
1171/* BREAKN field: */
1172#define XCHAL_DEBUGCAUSE_BREAKN_BITS 1 /* number of bits in BREAKN field */
1173#define XCHAL_DEBUGCAUSE_BREAKN_NUM 2 /* max number of possible causes (2^bits) */
1174#define XCHAL_DEBUGCAUSE_BREAKN_SHIFT 4 /* position of BREAKN bits in DEBUGCAUSE, starting from lsbit */
1175#define XCHAL_DEBUGCAUSE_BREAKN_MASK 0x00000010 /* mask of bits in BREAKN field of DEBUGCAUSE */
1176/* DEBUGINT field: */
1177#define XCHAL_DEBUGCAUSE_DEBUGINT_BITS 1 /* number of bits in DEBUGINT field */
1178#define XCHAL_DEBUGCAUSE_DEBUGINT_NUM 2 /* max number of possible causes (2^bits) */
1179#define XCHAL_DEBUGCAUSE_DEBUGINT_SHIFT 5 /* position of DEBUGINT bits in DEBUGCAUSE, starting from lsbit */
1180#define XCHAL_DEBUGCAUSE_DEBUGINT_MASK 0x00000020 /* mask of bits in DEBUGINT field of DEBUGCAUSE */
1181
1182
1183
1184/*----------------------------------------------------------------------
1185 ISA
1186 ----------------------------------------------------------------------*/
1187
1188#define XCHAL_HAVE_DENSITY 1 /* 1 if density option configured, 0 otherwise */
1189#define XCHAL_HAVE_LOOPS 1 /* 1 if zero-overhead loops option configured, 0 otherwise */
1190/* Misc instructions: */
1191#define XCHAL_HAVE_NSA 0 /* 1 if NSA/NSAU instructions option configured, 0 otherwise */
1192#define XCHAL_HAVE_MINMAX 0 /* 1 if MIN/MAX instructions option configured, 0 otherwise */
1193#define XCHAL_HAVE_SEXT 0 /* 1 if sign-extend instruction option configured, 0 otherwise */
1194#define XCHAL_HAVE_CLAMPS 0 /* 1 if CLAMPS instruction option configured, 0 otherwise */
1195#define XCHAL_HAVE_MAC16 0 /* 1 if MAC16 option configured, 0 otherwise */
1196#define XCHAL_HAVE_MUL16 0 /* 1 if 16-bit integer multiply option configured, 0 otherwise */
1197/*#define XCHAL_HAVE_POPC 0*/ /* 1 if CRC instruction option configured, 0 otherwise */
1198/*#define XCHAL_HAVE_CRC 0*/ /* 1 if POPC instruction option configured, 0 otherwise */
1199
1200#define XCHAL_HAVE_SPECULATION 0 /* 1 if speculation option configured, 0 otherwise */
1201/*#define XCHAL_HAVE_MP_SYNC 0*/ /* 1 if multiprocessor sync. option configured, 0 otherwise */
1202#define XCHAL_HAVE_PRID 0 /* 1 if processor ID register configured, 0 otherwise */
1203
1204#define XCHAL_NUM_MISC_REGS 2 /* number of miscellaneous registers (0..4) */
1205
1206/* These relate a bit more to TIE: */
1207#define XCHAL_HAVE_BOOLEANS 0 /* 1 if booleans option configured, 0 otherwise */
1208#define XCHAL_HAVE_MUL32 0 /* 1 if 32-bit integer multiply option configured, 0 otherwise */
1209#define XCHAL_HAVE_MUL32_HIGH 0 /* 1 if MUL32 option includes MULUH and MULSH, 0 otherwise */
1210#define XCHAL_HAVE_FP 0 /* 1 if floating point option configured, 0 otherwise */
1211
1212
1213/*----------------------------------------------------------------------
1214 DERIVED
1215 ----------------------------------------------------------------------*/
1216
1217#if XCHAL_HAVE_BE
1218#define XCHAL_INST_ILLN 0xD60F /* 2-byte illegal instruction, msb-first */
1219#define XCHAL_INST_ILLN_BYTE0 0xD6 /* 2-byte illegal instruction, 1st byte */
1220#define XCHAL_INST_ILLN_BYTE1 0x0F /* 2-byte illegal instruction, 2nd byte */
1221#else
1222#define XCHAL_INST_ILLN 0xF06D /* 2-byte illegal instruction, lsb-first */
1223#define XCHAL_INST_ILLN_BYTE0 0x6D /* 2-byte illegal instruction, 1st byte */
1224#define XCHAL_INST_ILLN_BYTE1 0xF0 /* 2-byte illegal instruction, 2nd byte */
1225#endif
1226/* Belongs in xtensa/hal.h: */
1227#define XTHAL_INST_ILL 0x000000 /* 3-byte illegal instruction */
1228
1229
1230/*
1231 * Because information as to exactly which hardware release is targeted
1232 * by a given software build is not always available, compile-time HAL
1233 * Hardware-Release "_AT" macros are fuzzy (return 0, 1, or XCHAL_MAYBE):
1234 */
1235#ifndef XCHAL_HW_RELEASE_MAJOR
1236# define XCHAL_HW_CONFIGID_RELIABLE 0
1237#endif
1238#if XCHAL_HW_CONFIGID_RELIABLE
1239# define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor) (XTHAL_REL_LE( XCHAL_HW_RELEASE_MAJOR,XCHAL_HW_RELEASE_MINOR, major,minor ) ? 1 : 0)
1240# define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor) (XTHAL_REL_GE( XCHAL_HW_RELEASE_MAJOR,XCHAL_HW_RELEASE_MINOR, major,minor ) ? 1 : 0)
1241# define XCHAL_HW_RELEASE_AT(major,minor) (XTHAL_REL_EQ( XCHAL_HW_RELEASE_MAJOR,XCHAL_HW_RELEASE_MINOR, major,minor ) ? 1 : 0)
1242# define XCHAL_HW_RELEASE_MAJOR_AT(major) ((XCHAL_HW_RELEASE_MAJOR == (major)) ? 1 : 0)
1243#else
1244# define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor) ( ((major) < 1040 && XCHAL_HAVE_XEA2) ? 0 \
1245 : ((major) > 1050 && XCHAL_HAVE_XEA1) ? 1 \
1246 : XTHAL_MAYBE )
1247# define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor) ( ((major) >= 2000 && XCHAL_HAVE_XEA1) ? 0 \
1248 : (XTHAL_REL_LE(major,minor, 1040,0) && XCHAL_HAVE_XEA2) ? 1 \
1249 : XTHAL_MAYBE )
1250# define XCHAL_HW_RELEASE_AT(major,minor) ( (((major) < 1040 && XCHAL_HAVE_XEA2) || \
1251 ((major) >= 2000 && XCHAL_HAVE_XEA1)) ? 0 : XTHAL_MAYBE)
1252# define XCHAL_HW_RELEASE_MAJOR_AT(major) XCHAL_HW_RELEASE_AT(major,0)
1253#endif
1254
1255/*
1256 * Specific errata:
1257 */
1258
1259/*
1260 * Erratum T1020.H13, T1030.H7, T1040.H10, T1050.H4 (fixed in T1040.3 and T1050.1;
1261 * relevant only in XEA1, kernel-vector mode, level-one interrupts and overflows enabled):
1262 */
1263#define XCHAL_MAYHAVE_ERRATUM_XEA1KWIN (XCHAL_HAVE_XEA1 && \
1264 (XCHAL_HW_RELEASE_AT_OR_BELOW(1040,2) != 0 \
1265 || XCHAL_HW_RELEASE_AT(1050,0)))
1266
1267
1268
1269#endif /*XTENSA_CONFIG_CORE_H*/
1270
diff --git a/include/asm-xtensa/xtensa/config-linux_be/defs.h b/include/asm-xtensa/xtensa/config-linux_be/defs.h
new file mode 100644
index 000000000000..f7c58b273371
--- /dev/null
+++ b/include/asm-xtensa/xtensa/config-linux_be/defs.h
@@ -0,0 +1,270 @@
1/* Definitions for Xtensa instructions, types, and protos. */
2
3/*
4 * Copyright (c) 2003 Tensilica, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of version 2.1 of the GNU Lesser General Public
8 * License as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it would be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
13 *
14 * Further, this software is distributed without any warranty that it is
15 * free of the rightful claim of any third person regarding infringement
16 * or the like. Any license provided herein, whether implied or
17 * otherwise, applies only to this software file. Patent licenses, if
18 * any, provided herein do not apply to combinations of this program with
19 * other software, or any other product whatsoever.
20 *
21 * You should have received a copy of the GNU Lesser General Public
22 * License along with this program; if not, write the Free Software
23 * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
24 * USA.
25 */
26
27/* Do not modify. This is automatically generated.*/
28
29#ifndef _XTENSA_BASE_HEADER
30#define _XTENSA_BASE_HEADER
31
32#ifdef __XTENSA__
33#if defined(__GNUC__) && !defined(__XCC__)
34
35#define L8UI_ASM(arr, ars, imm) { \
36 __asm__ volatile("l8ui %0, %1, %2" : "=a" (arr) : "a" (ars) , "i" (imm)); \
37}
38
39#define XT_L8UI(ars, imm) \
40({ \
41 unsigned char _arr; \
42 const unsigned char *_ars = ars; \
43 L8UI_ASM(_arr, _ars, imm); \
44 _arr; \
45})
46
47#define L16UI_ASM(arr, ars, imm) { \
48 __asm__ volatile("l16ui %0, %1, %2" : "=a" (arr) : "a" (ars) , "i" (imm)); \
49}
50
51#define XT_L16UI(ars, imm) \
52({ \
53 unsigned short _arr; \
54 const unsigned short *_ars = ars; \
55 L16UI_ASM(_arr, _ars, imm); \
56 _arr; \
57})
58
59#define L16SI_ASM(arr, ars, imm) {\
60 __asm__ volatile("l16si %0, %1, %2" : "=a" (arr) : "a" (ars) , "i" (imm)); \
61}
62
63#define XT_L16SI(ars, imm) \
64({ \
65 signed short _arr; \
66 const signed short *_ars = ars; \
67 L16SI_ASM(_arr, _ars, imm); \
68 _arr; \
69})
70
71#define L32I_ASM(arr, ars, imm) { \
72 __asm__ volatile("l32i %0, %1, %2" : "=a" (arr) : "a" (ars) , "i" (imm)); \
73}
74
75#define XT_L32I(ars, imm) \
76({ \
77 unsigned _arr; \
78 const unsigned *_ars = ars; \
79 L32I_ASM(_arr, _ars, imm); \
80 _arr; \
81})
82
83#define S8I_ASM(arr, ars, imm) {\
84 __asm__ volatile("s8i %0, %1, %2" : : "a" (arr), "a" (ars) , "i" (imm) : "memory" ); \
85}
86
87#define XT_S8I(arr, ars, imm) \
88({ \
89 signed char _arr = arr; \
90 const signed char *_ars = ars; \
91 S8I_ASM(_arr, _ars, imm); \
92})
93
94#define S16I_ASM(arr, ars, imm) {\
95 __asm__ volatile("s16i %0, %1, %2" : : "a" (arr), "a" (ars) , "i" (imm) : "memory" ); \
96}
97
98#define XT_S16I(arr, ars, imm) \
99({ \
100 signed short _arr = arr; \
101 const signed short *_ars = ars; \
102 S16I_ASM(_arr, _ars, imm); \
103})
104
105#define S32I_ASM(arr, ars, imm) { \
106 __asm__ volatile("s32i %0, %1, %2" : : "a" (arr), "a" (ars) , "i" (imm) : "memory" ); \
107}
108
109#define XT_S32I(arr, ars, imm) \
110({ \
111 signed int _arr = arr; \
112 const signed int *_ars = ars; \
113 S32I_ASM(_arr, _ars, imm); \
114})
115
116#define ADDI_ASM(art, ars, imm) {\
117 __asm__ ("addi %0, %1, %2" : "=a" (art) : "a" (ars), "i" (imm)); \
118}
119
120#define XT_ADDI(ars, imm) \
121({ \
122 unsigned _art; \
123 unsigned _ars = ars; \
124 ADDI_ASM(_art, _ars, imm); \
125 _art; \
126})
127
128#define ABS_ASM(arr, art) {\
129 __asm__ ("abs %0, %1" : "=a" (arr) : "a" (art)); \
130}
131
132#define XT_ABS(art) \
133({ \
134 unsigned _arr; \
135 signed _art = art; \
136 ABS_ASM(_arr, _art); \
137 _arr; \
138})
139
140/* Note: In the following macros that reference SAR, the magic "state"
141 register is used to capture the dependency on SAR. This is because
142 SAR is a 5-bit register and thus there are no C types that can be
143 used to represent it. It doesn't appear that the SAR register is
144 even relevant to GCC, but it is marked as "clobbered" just in
145 case. */
146
147#define SRC_ASM(arr, ars, art) {\
148 register int _xt_sar __asm__ ("state"); \
149 __asm__ ("src %0, %1, %2" \
150 : "=a" (arr) : "a" (ars), "a" (art), "t" (_xt_sar)); \
151}
152
153#define XT_SRC(ars, art) \
154({ \
155 unsigned _arr; \
156 unsigned _ars = ars; \
157 unsigned _art = art; \
158 SRC_ASM(_arr, _ars, _art); \
159 _arr; \
160})
161
162#define SSR_ASM(ars) {\
163 register int _xt_sar __asm__ ("state"); \
164 __asm__ ("ssr %1" : "=t" (_xt_sar) : "a" (ars) : "sar"); \
165}
166
167#define XT_SSR(ars) \
168({ \
169 unsigned _ars = ars; \
170 SSR_ASM(_ars); \
171})
172
173#define SSL_ASM(ars) {\
174 register int _xt_sar __asm__ ("state"); \
175 __asm__ ("ssl %1" : "=t" (_xt_sar) : "a" (ars) : "sar"); \
176}
177
178#define XT_SSL(ars) \
179({ \
180 unsigned _ars = ars; \
181 SSL_ASM(_ars); \
182})
183
184#define SSA8B_ASM(ars) {\
185 register int _xt_sar __asm__ ("state"); \
186 __asm__ ("ssa8b %1" : "=t" (_xt_sar) : "a" (ars) : "sar"); \
187}
188
189#define XT_SSA8B(ars) \
190({ \
191 unsigned _ars = ars; \
192 SSA8B_ASM(_ars); \
193})
194
195#define SSA8L_ASM(ars) {\
196 register int _xt_sar __asm__ ("state"); \
197 __asm__ ("ssa8l %1" : "=t" (_xt_sar) : "a" (ars) : "sar"); \
198}
199
200#define XT_SSA8L(ars) \
201({ \
202 unsigned _ars = ars; \
203 SSA8L_ASM(_ars); \
204})
205
206#define SSAI_ASM(imm) {\
207 register int _xt_sar __asm__ ("state"); \
208 __asm__ ("ssai %1" : "=t" (_xt_sar) : "i" (imm) : "sar"); \
209}
210
211#define XT_SSAI(imm) \
212({ \
213 SSAI_ASM(imm); \
214})
215
216
217
218
219
220
221
222
223#endif /* __GNUC__ && !__XCC__ */
224
225#ifdef __XCC__
226
227/* Core load/store instructions */
228extern unsigned char _TIE_L8UI(const unsigned char * ars, immediate imm);
229extern unsigned short _TIE_L16UI(const unsigned short * ars, immediate imm);
230extern signed short _TIE_L16SI(const signed short * ars, immediate imm);
231extern unsigned _TIE_L32I(const unsigned * ars, immediate imm);
232extern void _TIE_S8I(unsigned char arr, unsigned char * ars, immediate imm);
233extern void _TIE_S16I(unsigned short arr, unsigned short * ars, immediate imm);
234extern void _TIE_S32I(unsigned arr, unsigned * ars, immediate imm);
235
236#define XT_L8UI _TIE_L8UI
237#define XT_L16UI _TIE_L16UI
238#define XT_L16SI _TIE_L16SI
239#define XT_L32I _TIE_L32I
240#define XT_S8I _TIE_S8I
241#define XT_S16I _TIE_S16I
242#define XT_S32I _TIE_S32I
243
244/* Add-immediate instruction */
245extern unsigned _TIE_ADDI(unsigned ars, immediate imm);
246#define XT_ADDI _TIE_ADDI
247
248/* Absolute value instruction */
249extern unsigned _TIE_ABS(int art);
250#define XT_ABS _TIE_ABS
251
252/* funnel shift instructions */
253extern unsigned _TIE_SRC(unsigned ars, unsigned art);
254#define XT_SRC _TIE_SRC
255extern void _TIE_SSR(unsigned ars);
256#define XT_SSR _TIE_SSR
257extern void _TIE_SSL(unsigned ars);
258#define XT_SSL _TIE_SSL
259extern void _TIE_SSA8B(unsigned ars);
260#define XT_SSA8B _TIE_SSA8B
261extern void _TIE_SSA8L(unsigned ars);
262#define XT_SSA8L _TIE_SSA8L
263extern void _TIE_SSAI(immediate imm);
264#define XT_SSAI _TIE_SSAI
265
266
267#endif /* __XCC__ */
268
269#endif /* __XTENSA__ */
270#endif /* !_XTENSA_BASE_HEADER */
diff --git a/include/asm-xtensa/xtensa/config-linux_be/specreg.h b/include/asm-xtensa/xtensa/config-linux_be/specreg.h
new file mode 100644
index 000000000000..fa4106aa9a02
--- /dev/null
+++ b/include/asm-xtensa/xtensa/config-linux_be/specreg.h
@@ -0,0 +1,99 @@
1/*
2 * Xtensa Special Register symbolic names
3 */
4
5/* $Id: specreg.h,v 1.2 2003/03/07 19:15:18 joetaylor Exp $ */
6
7/*
8 * Copyright (c) 2003 Tensilica, Inc. All Rights Reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2.1 of the GNU Lesser General Public
12 * License as published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it would be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
17 *
18 * Further, this software is distributed without any warranty that it is
19 * free of the rightful claim of any third person regarding infringement
20 * or the like. Any license provided herein, whether implied or
21 * otherwise, applies only to this software file. Patent licenses, if
22 * any, provided herein do not apply to combinations of this program with
23 * other software, or any other product whatsoever.
24 *
25 * You should have received a copy of the GNU Lesser General Public
26 * License along with this program; if not, write the Free Software
27 * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
28 * USA.
29 */
30
31#ifndef XTENSA_SPECREG_H
32#define XTENSA_SPECREG_H
33
34/* Include these special register bitfield definitions, for historical reasons: */
35#include <xtensa/corebits.h>
36
37
38/* Special registers: */
39#define LBEG 0
40#define LEND 1
41#define LCOUNT 2
42#define SAR 3
43#define WINDOWBASE 72
44#define WINDOWSTART 73
45#define PTEVADDR 83
46#define RASID 90
47#define ITLBCFG 91
48#define DTLBCFG 92
49#define IBREAKENABLE 96
50#define DDR 104
51#define IBREAKA_0 128
52#define IBREAKA_1 129
53#define DBREAKA_0 144
54#define DBREAKA_1 145
55#define DBREAKC_0 160
56#define DBREAKC_1 161
57#define EPC_1 177
58#define EPC_2 178
59#define EPC_3 179
60#define EPC_4 180
61#define DEPC 192
62#define EPS_2 194
63#define EPS_3 195
64#define EPS_4 196
65#define EXCSAVE_1 209
66#define EXCSAVE_2 210
67#define EXCSAVE_3 211
68#define EXCSAVE_4 212
69#define INTERRUPT 226
70#define INTENABLE 228
71#define PS 230
72#define EXCCAUSE 232
73#define DEBUGCAUSE 233
74#define CCOUNT 234
75#define ICOUNT 236
76#define ICOUNTLEVEL 237
77#define EXCVADDR 238
78#define CCOMPARE_0 240
79#define CCOMPARE_1 241
80#define CCOMPARE_2 242
81#define MISC_REG_0 244
82#define MISC_REG_1 245
83
84/* Special cases (bases of special register series): */
85#define IBREAKA 128
86#define DBREAKA 144
87#define DBREAKC 160
88#define EPC 176
89#define EPS 192
90#define EXCSAVE 208
91#define CCOMPARE 240
92
93/* Special names for read-only and write-only interrupt registers: */
94#define INTREAD 226
95#define INTSET 226
96#define INTCLEAR 227
97
98#endif /* XTENSA_SPECREG_H */
99
diff --git a/include/asm-xtensa/xtensa/config-linux_be/system.h b/include/asm-xtensa/xtensa/config-linux_be/system.h
new file mode 100644
index 000000000000..cf9d4d308e3a
--- /dev/null
+++ b/include/asm-xtensa/xtensa/config-linux_be/system.h
@@ -0,0 +1,198 @@
1/*
2 * xtensa/config/system.h -- HAL definitions that are dependent on SYSTEM configuration
3 *
4 * NOTE: The location and contents of this file are highly subject to change.
5 *
6 * Source for configuration-independent binaries (which link in a
7 * configuration-specific HAL library) must NEVER include this file.
8 * The HAL itself has historically included this file in some instances,
9 * but this is not appropriate either, because the HAL is meant to be
10 * core-specific but system independent.
11 */
12
13/*
14 * Copyright (c) 2003 Tensilica, Inc. All Rights Reserved.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of version 2.1 of the GNU Lesser General Public
18 * License as published by the Free Software Foundation.
19 *
20 * This program is distributed in the hope that it would be useful, but
21 * WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
23 *
24 * Further, this software is distributed without any warranty that it is
25 * free of the rightful claim of any third person regarding infringement
26 * or the like. Any license provided herein, whether implied or
27 * otherwise, applies only to this software file. Patent licenses, if
28 * any, provided herein do not apply to combinations of this program with
29 * other software, or any other product whatsoever.
30 *
31 * You should have received a copy of the GNU Lesser General Public
32 * License along with this program; if not, write the Free Software
33 * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
34 * USA.
35 */
36
37
38#ifndef XTENSA_CONFIG_SYSTEM_H
39#define XTENSA_CONFIG_SYSTEM_H
40
41/*#include <xtensa/hal.h>*/
42
43
44
45/*----------------------------------------------------------------------
46 DEVICE ADDRESSES
47 ----------------------------------------------------------------------*/
48
49/*
50 * Strange place to find these, but the configuration GUI
51 * allows moving these around to account for various core
52 * configurations. Specific boards (and their BSP software)
53 * will have specific meanings for these components.
54 */
55
56/* I/O Block areas: */
57#define XSHAL_IOBLOCK_CACHED_VADDR 0xE0000000
58#define XSHAL_IOBLOCK_CACHED_PADDR 0xF0000000
59#define XSHAL_IOBLOCK_CACHED_SIZE 0x0E000000
60
61#define XSHAL_IOBLOCK_BYPASS_VADDR 0xF0000000
62#define XSHAL_IOBLOCK_BYPASS_PADDR 0xF0000000
63#define XSHAL_IOBLOCK_BYPASS_SIZE 0x0E000000
64
65/* System ROM: */
66#define XSHAL_ROM_VADDR 0xEE000000
67#define XSHAL_ROM_PADDR 0xFE000000
68#define XSHAL_ROM_SIZE 0x00400000
69/* Largest available area (free of vectors): */
70#define XSHAL_ROM_AVAIL_VADDR 0xEE00052C
71#define XSHAL_ROM_AVAIL_VSIZE 0x003FFAD4
72
73/* System RAM: */
74#define XSHAL_RAM_VADDR 0xD0000000
75#define XSHAL_RAM_PADDR 0x00000000
76#define XSHAL_RAM_VSIZE 0x08000000
77#define XSHAL_RAM_PSIZE 0x10000000
78#define XSHAL_RAM_SIZE XSHAL_RAM_PSIZE
79/* Largest available area (free of vectors): */
80#define XSHAL_RAM_AVAIL_VADDR 0xD0000370
81#define XSHAL_RAM_AVAIL_VSIZE 0x07FFFC90
82
83/*
84 * Shadow system RAM (same device as system RAM, at different address).
85 * (Emulation boards need this for the SONIC Ethernet driver
86 * when data caches are configured for writeback mode.)
87 * NOTE: on full MMU configs, this points to the BYPASS virtual address
88 * of system RAM, ie. is the same as XSHAL_RAM_* except that virtual
89 * addresses are viewed through the BYPASS static map rather than
90 * the CACHED static map.
91 */
92#define XSHAL_RAM_BYPASS_VADDR 0xD8000000
93#define XSHAL_RAM_BYPASS_PADDR 0x00000000
94#define XSHAL_RAM_BYPASS_PSIZE 0x08000000
95
96/* Alternate system RAM (different device than system RAM): */
97#define XSHAL_ALTRAM_VADDR 0xCEE00000
98#define XSHAL_ALTRAM_PADDR 0xC0000000
99#define XSHAL_ALTRAM_SIZE 0x00200000
100
101
102/*----------------------------------------------------------------------
103 * DEVICE-ADDRESS DEPENDENT...
104 *
105 * Values written to CACHEATTR special register (or its equivalent)
106 * to enable and disable caches in various modes.
107 *----------------------------------------------------------------------*/
108
109/*----------------------------------------------------------------------
110 BACKWARD COMPATIBILITY ...
111 ----------------------------------------------------------------------*/
112
113/*
114 * NOTE: the following two macros are DEPRECATED. Use the latter
115 * board-specific macros instead, which are specially tuned for the
116 * particular target environments' memory maps.
117 */
118#define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */
119#define XSHAL_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_DEFAULT /* default setting to enable caches (no writeback!) */
120
121/*----------------------------------------------------------------------
122 ISS (Instruction Set Simulator) SPECIFIC ...
123 ----------------------------------------------------------------------*/
124
125#define XSHAL_ISS_CACHEATTR_WRITEBACK 0x1122222F /* enable caches in write-back mode */
126#define XSHAL_ISS_CACHEATTR_WRITEALLOC 0x1122222F /* enable caches in write-allocate mode */
127#define XSHAL_ISS_CACHEATTR_WRITETHRU 0x1122222F /* enable caches in write-through mode */
128#define XSHAL_ISS_CACHEATTR_BYPASS 0x2222222F /* disable caches in bypass mode */
129#define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_ISS_CACHEATTR_WRITEBACK /* default setting to enable caches */
130
131/* For Coware only: */
132#define XSHAL_COWARE_CACHEATTR_WRITEBACK 0x11222222 /* enable caches in write-back mode */
133#define XSHAL_COWARE_CACHEATTR_WRITEALLOC 0x11222222 /* enable caches in write-allocate mode */
134#define XSHAL_COWARE_CACHEATTR_WRITETHRU 0x11222222 /* enable caches in write-through mode */
135#define XSHAL_COWARE_CACHEATTR_BYPASS 0x22222222 /* disable caches in bypass mode */
136#define XSHAL_COWARE_CACHEATTR_DEFAULT XSHAL_COWARE_CACHEATTR_WRITEBACK /* default setting to enable caches */
137
138/* For BFM and other purposes: */
139#define XSHAL_ALLVALID_CACHEATTR_WRITEBACK 0x11222222 /* enable caches without any invalid regions */
140#define XSHAL_ALLVALID_CACHEATTR_DEFAULT XSHAL_ALLVALID_CACHEATTR_WRITEBACK /* default setting for caches without any invalid regions */
141
142#define XSHAL_ISS_PIPE_REGIONS 0
143#define XSHAL_ISS_SDRAM_REGIONS 0
144
145
146/*----------------------------------------------------------------------
147 XT2000 BOARD SPECIFIC ...
148 ----------------------------------------------------------------------*/
149
150#define XSHAL_XT2000_CACHEATTR_WRITEBACK 0x22FFFFFF /* enable caches in write-back mode */
151#define XSHAL_XT2000_CACHEATTR_WRITEALLOC 0x22FFFFFF /* enable caches in write-allocate mode */
152#define XSHAL_XT2000_CACHEATTR_WRITETHRU 0x22FFFFFF /* enable caches in write-through mode */
153#define XSHAL_XT2000_CACHEATTR_BYPASS 0x22FFFFFF /* disable caches in bypass mode */
154#define XSHAL_XT2000_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_WRITEBACK /* default setting to enable caches */
155
156#define XSHAL_XT2000_PIPE_REGIONS 0x00001000 /* BusInt pipeline regions */
157#define XSHAL_XT2000_SDRAM_REGIONS 0x00000005 /* BusInt SDRAM regions */
158
159
160/*----------------------------------------------------------------------
161 VECTOR SIZES
162 ----------------------------------------------------------------------*/
163
164/*
165 * Sizes allocated to vectors by the system (memory map) configuration.
166 * These sizes are constrained by core configuration (eg. one vector's
167 * code cannot overflow into another vector) but are dependent on the
168 * system or board (or LSP) memory map configuration.
169 *
170 * Whether or not each vector happens to be in a system ROM is also
171 * a system configuration matter, sometimes useful, included here also:
172 */
173#define XSHAL_RESET_VECTOR_SIZE 0x000004E0
174#define XSHAL_RESET_VECTOR_ISROM 1
175#define XSHAL_USER_VECTOR_SIZE 0x0000001C
176#define XSHAL_USER_VECTOR_ISROM 0
177#define XSHAL_PROGRAMEXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */
178#define XSHAL_USEREXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */
179#define XSHAL_KERNEL_VECTOR_SIZE 0x0000001C
180#define XSHAL_KERNEL_VECTOR_ISROM 0
181#define XSHAL_STACKEDEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */
182#define XSHAL_KERNELEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */
183#define XSHAL_DOUBLEEXC_VECTOR_SIZE 0x000000E0
184#define XSHAL_DOUBLEEXC_VECTOR_ISROM 0
185#define XSHAL_WINDOW_VECTORS_SIZE 0x00000180
186#define XSHAL_WINDOW_VECTORS_ISROM 0
187#define XSHAL_INTLEVEL2_VECTOR_SIZE 0x0000000C
188#define XSHAL_INTLEVEL2_VECTOR_ISROM 0
189#define XSHAL_INTLEVEL3_VECTOR_SIZE 0x0000000C
190#define XSHAL_INTLEVEL3_VECTOR_ISROM 0
191#define XSHAL_INTLEVEL4_VECTOR_SIZE 0x0000000C
192#define XSHAL_INTLEVEL4_VECTOR_ISROM 1
193#define XSHAL_DEBUG_VECTOR_SIZE XSHAL_INTLEVEL4_VECTOR_SIZE
194#define XSHAL_DEBUG_VECTOR_ISROM XSHAL_INTLEVEL4_VECTOR_ISROM
195
196
197#endif /*XTENSA_CONFIG_SYSTEM_H*/
198
diff --git a/include/asm-xtensa/xtensa/config-linux_be/tie.h b/include/asm-xtensa/xtensa/config-linux_be/tie.h
new file mode 100644
index 000000000000..3c2e514602f4
--- /dev/null
+++ b/include/asm-xtensa/xtensa/config-linux_be/tie.h
@@ -0,0 +1,275 @@
1/*
2 * xtensa/config/tie.h -- HAL definitions that are dependent on CORE and TIE configuration
3 *
4 * This header file is sometimes referred to as the "compile-time HAL" or CHAL.
5 * It was generated for a specific Xtensa processor configuration,
6 * and furthermore for a specific set of TIE source files that extend
7 * basic core functionality.
8 *
9 * Source for configuration-independent binaries (which link in a
10 * configuration-specific HAL library) must NEVER include this file.
11 * It is perfectly normal, however, for the HAL source itself to include this file.
12 */
13
14/*
15 * Copyright (c) 2003 Tensilica, Inc. All Rights Reserved.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of version 2.1 of the GNU Lesser General Public
19 * License as published by the Free Software Foundation.
20 *
21 * This program is distributed in the hope that it would be useful, but
22 * WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
24 *
25 * Further, this software is distributed without any warranty that it is
26 * free of the rightful claim of any third person regarding infringement
27 * or the like. Any license provided herein, whether implied or
28 * otherwise, applies only to this software file. Patent licenses, if
29 * any, provided herein do not apply to combinations of this program with
30 * other software, or any other product whatsoever.
31 *
32 * You should have received a copy of the GNU Lesser General Public
33 * License along with this program; if not, write the Free Software
34 * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
35 * USA.
36 */
37
38
39#ifndef XTENSA_CONFIG_TIE_H
40#define XTENSA_CONFIG_TIE_H
41
42#include <xtensa/hal.h>
43
44
45/*----------------------------------------------------------------------
46 GENERAL
47 ----------------------------------------------------------------------*/
48
49/*
50 * Separators for macros that expand into arrays.
51 * These can be predefined by files that #include this one,
52 * when different separators are required.
53 */
54/* Element separator for macros that expand into 1-dimensional arrays: */
55#ifndef XCHAL_SEP
56#define XCHAL_SEP ,
57#endif
58/* Array separator for macros that expand into 2-dimensional arrays: */
59#ifndef XCHAL_SEP2
60#define XCHAL_SEP2 },{
61#endif
62
63
64
65
66
67
68/*----------------------------------------------------------------------
69 COPROCESSORS and EXTRA STATE
70 ----------------------------------------------------------------------*/
71
72#define XCHAL_CP_NUM 0 /* number of coprocessors */
73#define XCHAL_CP_MAX 0 /* max coprocessor id plus one (0 if none) */
74#define XCHAL_CP_MASK 0x00 /* bitmask of coprocessors by id */
75
76/* Space for coprocessors' state save areas: */
77#define XCHAL_CP0_SA_SIZE 0
78#define XCHAL_CP1_SA_SIZE 0
79#define XCHAL_CP2_SA_SIZE 0
80#define XCHAL_CP3_SA_SIZE 0
81#define XCHAL_CP4_SA_SIZE 0
82#define XCHAL_CP5_SA_SIZE 0
83#define XCHAL_CP6_SA_SIZE 0
84#define XCHAL_CP7_SA_SIZE 0
85/* Minimum required alignments of CP state save areas: */
86#define XCHAL_CP0_SA_ALIGN 1
87#define XCHAL_CP1_SA_ALIGN 1
88#define XCHAL_CP2_SA_ALIGN 1
89#define XCHAL_CP3_SA_ALIGN 1
90#define XCHAL_CP4_SA_ALIGN 1
91#define XCHAL_CP5_SA_ALIGN 1
92#define XCHAL_CP6_SA_ALIGN 1
93#define XCHAL_CP7_SA_ALIGN 1
94
95/* Indexing macros: */
96#define _XCHAL_CP_SA_SIZE(n) XCHAL_CP ## n ## _SA_SIZE
97#define XCHAL_CP_SA_SIZE(n) _XCHAL_CP_SA_SIZE(n) /* n = 0 .. 7 */
98#define _XCHAL_CP_SA_ALIGN(n) XCHAL_CP ## n ## _SA_ALIGN
99#define XCHAL_CP_SA_ALIGN(n) _XCHAL_CP_SA_ALIGN(n) /* n = 0 .. 7 */
100
101
102/* Space for "extra" state (user special registers and non-cp TIE) save area: */
103#define XCHAL_EXTRA_SA_SIZE 0
104#define XCHAL_EXTRA_SA_ALIGN 1
105
106/* Total save area size (extra + all coprocessors) */
107/* (not useful until xthal_{save,restore}_all_extra() is implemented, */
108/* but included for Tor2 beta; doesn't account for alignment!): */
109#define XCHAL_CPEXTRA_SA_SIZE_TOR2 0 /* Tor2Beta temporary definition -- do not use */
110
111/* Combined required alignment for all CP and EXTRA state save areas */
112/* (does not include required alignment for any base config registers): */
113#define XCHAL_CPEXTRA_SA_ALIGN 1
114
115/* ... */
116
117
118#ifdef _ASMLANGUAGE
119/*
120 * Assembly-language specific definitions (assembly macros, etc.).
121 */
122#include <xtensa/config/specreg.h>
123
124/********************
125 * Macros to save and restore the non-coprocessor TIE portion of EXTRA state.
126 */
127
128/* (none) */
129
130
131/********************
132 * Macros to create functions that save and restore all EXTRA (non-coprocessor) state
133 * (does not include zero-overhead loop registers and non-optional registers).
134 */
135
136 /*
137 * Macro that expands to the body of a function that
138 * stores the extra (non-coprocessor) optional/custom state.
139 * Entry: a2 = ptr to save area in which to save extra state
140 * Exit: any register a2-a15 (?) may have been clobbered.
141 */
142 .macro xchal_extra_store_funcbody
143 .endm
144
145
146 /*
147 * Macro that expands to the body of a function that
148 * loads the extra (non-coprocessor) optional/custom state.
149 * Entry: a2 = ptr to save area from which to restore extra state
150 * Exit: any register a2-a15 (?) may have been clobbered.
151 */
152 .macro xchal_extra_load_funcbody
153 .endm
154
155
156/********************
157 * Macros to save and restore the state of each TIE coprocessor.
158 */
159
160
161
162/********************
163 * Macros to create functions that save and restore the state of *any* TIE coprocessor.
164 */
165
166 /*
167 * Macro that expands to the body of a function
168 * that stores the selected coprocessor's state (registers etc).
169 * Entry: a2 = ptr to save area in which to save cp state
170 * a3 = coprocessor number
171 * Exit: any register a2-a15 (?) may have been clobbered.
172 */
173 .macro xchal_cpi_store_funcbody
174 .endm
175
176
177 /*
178 * Macro that expands to the body of a function
179 * that loads the selected coprocessor's state (registers etc).
180 * Entry: a2 = ptr to save area from which to restore cp state
181 * a3 = coprocessor number
182 * Exit: any register a2-a15 (?) may have been clobbered.
183 */
184 .macro xchal_cpi_load_funcbody
185 .endm
186
187#endif /*_ASMLANGUAGE*/
188
189
190/*
191 * Contents of save areas in terms of libdb register numbers.
192 * NOTE: CONTENTS_LIBDB_{UREG,REGF} macros are not defined in this file;
193 * it is up to the user of this header file to define these macros
194 * usefully before each expansion of the CONTENTS_LIBDB macros.
195 * (Fields rsv[123] are reserved for future additions; they are currently
196 * set to zero but may be set to some useful values in the future.)
197 *
198 * CONTENTS_LIBDB_SREG(libdbnum, offset, size, align, rsv1, name, sregnum, bitmask, rsv2, rsv3)
199 * CONTENTS_LIBDB_UREG(libdbnum, offset, size, align, rsv1, name, uregnum, bitmask, rsv2, rsv3)
200 * CONTENTS_LIBDB_REGF(libdbnum, offset, size, align, rsv1, name, index, numentries, contentsize, regname_base, regfile_name, rsv2, rsv3)
201 */
202
203#define XCHAL_EXTRA_SA_CONTENTS_LIBDB_NUM 0
204#define XCHAL_EXTRA_SA_CONTENTS_LIBDB /* empty */
205
206#define XCHAL_CP0_SA_CONTENTS_LIBDB_NUM 0
207#define XCHAL_CP0_SA_CONTENTS_LIBDB /* empty */
208
209#define XCHAL_CP1_SA_CONTENTS_LIBDB_NUM 0
210#define XCHAL_CP1_SA_CONTENTS_LIBDB /* empty */
211
212#define XCHAL_CP2_SA_CONTENTS_LIBDB_NUM 0
213#define XCHAL_CP2_SA_CONTENTS_LIBDB /* empty */
214
215#define XCHAL_CP3_SA_CONTENTS_LIBDB_NUM 0
216#define XCHAL_CP3_SA_CONTENTS_LIBDB /* empty */
217
218#define XCHAL_CP4_SA_CONTENTS_LIBDB_NUM 0
219#define XCHAL_CP4_SA_CONTENTS_LIBDB /* empty */
220
221#define XCHAL_CP5_SA_CONTENTS_LIBDB_NUM 0
222#define XCHAL_CP5_SA_CONTENTS_LIBDB /* empty */
223
224#define XCHAL_CP6_SA_CONTENTS_LIBDB_NUM 0
225#define XCHAL_CP6_SA_CONTENTS_LIBDB /* empty */
226
227#define XCHAL_CP7_SA_CONTENTS_LIBDB_NUM 0
228#define XCHAL_CP7_SA_CONTENTS_LIBDB /* empty */
229
230
231
232
233
234
235/*----------------------------------------------------------------------
236 MISC
237 ----------------------------------------------------------------------*/
238
239#if 0 /* is there something equivalent for user TIE? */
240#define XCHAL_CORE_ID "linux_be" /* configuration's alphanumeric core identifier
241 (CoreID) set in the Xtensa Processor Generator */
242
243#define XCHAL_BUILD_UNIQUE_ID 0x00003256 /* software build-unique ID (22-bit) */
244
245/* These definitions describe the hardware targeted by this software: */
246#define XCHAL_HW_CONFIGID0 0xC103D1FF /* config ID reg 0 value (upper 32 of 64 bits) */
247#define XCHAL_HW_CONFIGID1 0x00803256 /* config ID reg 1 value (lower 32 of 64 bits) */
248#define XCHAL_CONFIGID0 XCHAL_HW_CONFIGID0 /* for backward compatibility only -- don't use! */
249#define XCHAL_CONFIGID1 XCHAL_HW_CONFIGID1 /* for backward compatibility only -- don't use! */
250#define XCHAL_HW_RELEASE_MAJOR 1050 /* major release of targeted hardware */
251#define XCHAL_HW_RELEASE_MINOR 1 /* minor release of targeted hardware */
252#define XCHAL_HW_RELEASE_NAME "T1050.1" /* full release name of targeted hardware */
253#define XTHAL_HW_REL_T1050 1
254#define XTHAL_HW_REL_T1050_1 1
255#define XCHAL_HW_CONFIGID_RELIABLE 1
256#endif /*0*/
257
258
259
260/*----------------------------------------------------------------------
261 ISA
262 ----------------------------------------------------------------------*/
263
264#if 0 /* these probably don't belong here, but are related to or implemented using TIE */
265#define XCHAL_HAVE_BOOLEANS 0 /* 1 if booleans option configured, 0 otherwise */
266/* Misc instructions: */
267#define XCHAL_HAVE_MUL32 0 /* 1 if 32-bit integer multiply option configured, 0 otherwise */
268#define XCHAL_HAVE_MUL32_HIGH 0 /* 1 if MUL32 option includes MULUH and MULSH, 0 otherwise */
269
270#define XCHAL_HAVE_FP 0 /* 1 if floating point option configured, 0 otherwise */
271#endif /*0*/
272
273
274#endif /*XTENSA_CONFIG_TIE_H*/
275
diff --git a/include/asm-xtensa/xtensa/coreasm.h b/include/asm-xtensa/xtensa/coreasm.h
new file mode 100644
index 000000000000..a8cfb54c20a1
--- /dev/null
+++ b/include/asm-xtensa/xtensa/coreasm.h
@@ -0,0 +1,526 @@
1#ifndef XTENSA_COREASM_H
2#define XTENSA_COREASM_H
3
4/*
5 * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
6 *
7 * include/asm-xtensa/xtensa/coreasm.h -- assembler-specific
8 * definitions that depend on CORE configuration.
9 *
10 * Source for configuration-independent binaries (which link in a
11 * configuration-specific HAL library) must NEVER include this file.
12 * It is perfectly normal, however, for the HAL itself to include this
13 * file.
14 *
15 * This file must NOT include xtensa/config/system.h. Any assembler
16 * header file that depends on system information should likely go in
17 * a new systemasm.h (or sysasm.h) header file.
18 *
19 * NOTE: macro beqi32 is NOT configuration-dependent, and is placed
20 * here til we will have configuration-independent header file.
21 *
22 * This file is subject to the terms and conditions of the GNU General
23 * Public License. See the file "COPYING" in the main directory of
24 * this archive for more details.
25 *
26 * Copyright (C) 2002 Tensilica Inc.
27 */
28
29
30#include <xtensa/config/core.h>
31#include <xtensa/config/specreg.h>
32
33/*
34 * Assembly-language specific definitions (assembly macros, etc.).
35 */
36
37/*----------------------------------------------------------------------
38 * find_ms_setbit
39 *
40 * This macro finds the most significant bit that is set in <as>
41 * and return its index + <base> in <ad>, or <base> - 1 if <as> is zero.
42 * The index counts starting at zero for the lsbit, so the return
43 * value ranges from <base>-1 (no bit set) to <base>+31 (msbit set).
44 *
45 * Parameters:
46 * <ad> destination address register (any register)
47 * <as> source address register
48 * <at> temporary address register (must be different than <as>)
49 * <base> constant value added to result (usually 0 or 1)
50 * On entry:
51 * <ad> = undefined if different than <as>
52 * <as> = value whose most significant set bit is to be found
53 * <at> = undefined
54 * no other registers are used by this macro.
55 * On exit:
56 * <ad> = <base> + index of msbit set in original <as>,
57 * = <base> - 1 if original <as> was zero.
58 * <as> clobbered (if not <ad>)
59 * <at> clobbered (if not <ad>)
60 * Example:
61 * find_ms_setbit a0, a4, a0, 0 -- return in a0 index of msbit set in a4
62 */
63
64 .macro find_ms_setbit ad, as, at, base
65#if XCHAL_HAVE_NSA
66 movi \at, 31+\base
67 nsau \as, \as // get index of \as, numbered from msbit (32 if absent)
68 sub \ad, \at, \as // get numbering from lsbit (0..31, -1 if absent)
69#else /* XCHAL_HAVE_NSA */
70 movi \at, \base // start with result of 0 (point to lsbit of 32)
71
72 beqz \as, 2f // special case for zero argument: return -1
73 bltui \as, 0x10000, 1f // is it one of the 16 lsbits? (if so, check lower 16 bits)
74 addi \at, \at, 16 // no, increment result to upper 16 bits (of 32)
75 //srli \as, \as, 16 // check upper half (shift right 16 bits)
76 extui \as, \as, 16, 16 // check upper half (shift right 16 bits)
771: bltui \as, 0x100, 1f // is it one of the 8 lsbits? (if so, check lower 8 bits)
78 addi \at, \at, 8 // no, increment result to upper 8 bits (of 16)
79 srli \as, \as, 8 // shift right to check upper 8 bits
801: bltui \as, 0x10, 1f // is it one of the 4 lsbits? (if so, check lower 4 bits)
81 addi \at, \at, 4 // no, increment result to upper 4 bits (of 8)
82 srli \as, \as, 4 // shift right 4 bits to check upper half
831: bltui \as, 0x4, 1f // is it one of the 2 lsbits? (if so, check lower 2 bits)
84 addi \at, \at, 2 // no, increment result to upper 2 bits (of 4)
85 srli \as, \as, 2 // shift right 2 bits to check upper half
861: bltui \as, 0x2, 1f // is it the lsbit?
87 addi \at, \at, 2 // no, increment result to upper bit (of 2)
882: addi \at, \at, -1 // (from just above: add 1; from beqz: return -1)
89 //srli \as, \as, 1
901: // done! \at contains index of msbit set (or -1 if none set)
91 .if 0x\ad - 0x\at // destination different than \at ? (works because regs are a0-a15)
92 mov \ad, \at // then move result to \ad
93 .endif
94#endif /* XCHAL_HAVE_NSA */
95 .endm // find_ms_setbit
96
97/*----------------------------------------------------------------------
98 * find_ls_setbit
99 *
100 * This macro finds the least significant bit that is set in <as>,
101 * and return its index in <ad>.
102 * Usage is the same as for the find_ms_setbit macro.
103 * Example:
104 * find_ls_setbit a0, a4, a0, 0 -- return in a0 index of lsbit set in a4
105 */
106
107 .macro find_ls_setbit ad, as, at, base
108 neg \at, \as // keep only the least-significant bit that is set...
109 and \as, \at, \as // ... in \as
110 find_ms_setbit \ad, \as, \at, \base
111 .endm // find_ls_setbit
112
113/*----------------------------------------------------------------------
114 * find_ls_one
115 *
116 * Same as find_ls_setbit with base zero.
117 * Source (as) and destination (ad) registers must be different.
118 * Provided for backward compatibility.
119 */
120
121 .macro find_ls_one ad, as
122 find_ls_setbit \ad, \as, \ad, 0
123 .endm // find_ls_one
124
125/*----------------------------------------------------------------------
126 * floop, floopnez, floopgtz, floopend
127 *
128 * These macros are used for fast inner loops that
129 * work whether or not the Loops options is configured.
130 * If the Loops option is configured, they simply use
131 * the zero-overhead LOOP instructions; otherwise
132 * they use explicit decrement and branch instructions.
133 *
134 * They are used in pairs, with floop, floopnez or floopgtz
135 * at the beginning of the loop, and floopend at the end.
136 *
137 * Each pair of loop macro calls must be given the loop count
138 * address register and a unique label for that loop.
139 *
140 * Example:
141 *
142 * movi a3, 16 // loop 16 times
143 * floop a3, myloop1
144 * :
145 * bnez a7, end1 // exit loop if a7 != 0
146 * :
147 * floopend a3, myloop1
148 * end1:
149 *
150 * Like the LOOP instructions, these macros cannot be
151 * nested, must include at least one instruction,
152 * cannot call functions inside the loop, etc.
153 * The loop can be exited by jumping to the instruction
154 * following floopend (or elsewhere outside the loop),
155 * or continued by jumping to a NOP instruction placed
156 * immediately before floopend.
157 *
158 * Unlike LOOP instructions, the register passed to floop*
159 * cannot be used inside the loop, because it is used as
160 * the loop counter if the Loops option is not configured.
161 * And its value is undefined after exiting the loop.
162 * And because the loop counter register is active inside
163 * the loop, you can't easily use this construct to loop
164 * across a register file using ROTW as you might with LOOP
165 * instructions, unless you copy the loop register along.
166 */
167
168 /* Named label version of the macros: */
169
170 .macro floop ar, endlabel
171 floop_ \ar, .Lfloopstart_\endlabel, .Lfloopend_\endlabel
172 .endm
173
174 .macro floopnez ar, endlabel
175 floopnez_ \ar, .Lfloopstart_\endlabel, .Lfloopend_\endlabel
176 .endm
177
178 .macro floopgtz ar, endlabel
179 floopgtz_ \ar, .Lfloopstart_\endlabel, .Lfloopend_\endlabel
180 .endm
181
182 .macro floopend ar, endlabel
183 floopend_ \ar, .Lfloopstart_\endlabel, .Lfloopend_\endlabel
184 .endm
185
186 /* Numbered local label version of the macros: */
187#if 0 /*UNTESTED*/
188 .macro floop89 ar
189 floop_ \ar, 8, 9f
190 .endm
191
192 .macro floopnez89 ar
193 floopnez_ \ar, 8, 9f
194 .endm
195
196 .macro floopgtz89 ar
197 floopgtz_ \ar, 8, 9f
198 .endm
199
200 .macro floopend89 ar
201 floopend_ \ar, 8b, 9
202 .endm
203#endif /*0*/
204
205 /* Underlying version of the macros: */
206
207 .macro floop_ ar, startlabel, endlabelref
208 .ifdef _infloop_
209 .if _infloop_
210 .err // Error: floop cannot be nested
211 .endif
212 .endif
213 .set _infloop_, 1
214#if XCHAL_HAVE_LOOPS
215 loop \ar, \endlabelref
216#else /* XCHAL_HAVE_LOOPS */
217\startlabel:
218 addi \ar, \ar, -1
219#endif /* XCHAL_HAVE_LOOPS */
220 .endm // floop_
221
222 .macro floopnez_ ar, startlabel, endlabelref
223 .ifdef _infloop_
224 .if _infloop_
225 .err // Error: floopnez cannot be nested
226 .endif
227 .endif
228 .set _infloop_, 1
229#if XCHAL_HAVE_LOOPS
230 loopnez \ar, \endlabelref
231#else /* XCHAL_HAVE_LOOPS */
232 beqz \ar, \endlabelref
233\startlabel:
234 addi \ar, \ar, -1
235#endif /* XCHAL_HAVE_LOOPS */
236 .endm // floopnez_
237
238 .macro floopgtz_ ar, startlabel, endlabelref
239 .ifdef _infloop_
240 .if _infloop_
241 .err // Error: floopgtz cannot be nested
242 .endif
243 .endif
244 .set _infloop_, 1
245#if XCHAL_HAVE_LOOPS
246 loopgtz \ar, \endlabelref
247#else /* XCHAL_HAVE_LOOPS */
248 bltz \ar, \endlabelref
249 beqz \ar, \endlabelref
250\startlabel:
251 addi \ar, \ar, -1
252#endif /* XCHAL_HAVE_LOOPS */
253 .endm // floopgtz_
254
255
256 .macro floopend_ ar, startlabelref, endlabel
257 .ifndef _infloop_
258 .err // Error: floopend without matching floopXXX
259 .endif
260 .ifeq _infloop_
261 .err // Error: floopend without matching floopXXX
262 .endif
263 .set _infloop_, 0
264#if ! XCHAL_HAVE_LOOPS
265 bnez \ar, \startlabelref
266#endif /* XCHAL_HAVE_LOOPS */
267\endlabel:
268 .endm // floopend_
269
270/*----------------------------------------------------------------------
271 * crsil -- conditional RSIL (read/set interrupt level)
272 *
273 * Executes the RSIL instruction if it exists, else just reads PS.
274 * The RSIL instruction does not exist in the new exception architecture
275 * if the interrupt option is not selected.
276 */
277
278 .macro crsil ar, newlevel
279#if XCHAL_HAVE_OLD_EXC_ARCH || XCHAL_HAVE_INTERRUPTS
280 rsil \ar, \newlevel
281#else
282 rsr \ar, PS
283#endif
284 .endm // crsil
285
286/*----------------------------------------------------------------------
287 * window_spill{4,8,12}
288 *
289 * These macros spill callers' register windows to the stack.
290 * They work for both privileged and non-privileged tasks.
291 * Must be called from a windowed ABI context, eg. within
292 * a windowed ABI function (ie. valid stack frame, window
293 * exceptions enabled, not in exception mode, etc).
294 *
295 * This macro requires a single invocation of the window_spill_common
296 * macro in the same assembly unit and section.
297 *
298 * Note that using window_spill{4,8,12} macros is more efficient
299 * than calling a function implemented using window_spill_function,
300 * because the latter needs extra code to figure out the size of
301 * the call to the spilling function.
302 *
303 * Example usage:
304 *
305 * .text
306 * .align 4
307 * .global some_function
308 * .type some_function,@function
309 * some_function:
310 * entry a1, 16
311 * :
312 * :
313 *
314 * window_spill4 // spill windows of some_function's callers; preserves a0..a3 only;
315 * // to use window_spill{8,12} in this example function we'd have
316 * // to increase space allocated by the entry instruction, because
317 * // 16 bytes only allows call4; 32 or 48 bytes (+locals) are needed
318 * // for call8/window_spill8 or call12/window_spill12 respectively.
319 * :
320 *
321 * retw
322 *
323 * window_spill_common // instantiates code used by window_spill4
324 *
325 *
326 * On entry:
327 * none (if window_spill4)
328 * stack frame has enough space allocated for call8 (if window_spill8)
329 * stack frame has enough space allocated for call12 (if window_spill12)
330 * On exit:
331 * a4..a15 clobbered (if window_spill4)
332 * a8..a15 clobbered (if window_spill8)
333 * a12..a15 clobbered (if window_spill12)
334 * no caller windows are in live registers
335 */
336
337 .macro window_spill4
338#if XCHAL_HAVE_WINDOWED
339# if XCHAL_NUM_AREGS == 16
340 movi a15, 0 // for 16-register files, no need to call to reach the end
341# elif XCHAL_NUM_AREGS == 32
342 call4 .L__wdwspill_assist28 // call deep enough to clear out any live callers
343# elif XCHAL_NUM_AREGS == 64
344 call4 .L__wdwspill_assist60 // call deep enough to clear out any live callers
345# endif
346#endif
347 .endm // window_spill4
348
349 .macro window_spill8
350#if XCHAL_HAVE_WINDOWED
351# if XCHAL_NUM_AREGS == 16
352 movi a15, 0 // for 16-register files, no need to call to reach the end
353# elif XCHAL_NUM_AREGS == 32
354 call8 .L__wdwspill_assist24 // call deep enough to clear out any live callers
355# elif XCHAL_NUM_AREGS == 64
356 call8 .L__wdwspill_assist56 // call deep enough to clear out any live callers
357# endif
358#endif
359 .endm // window_spill8
360
361 .macro window_spill12
362#if XCHAL_HAVE_WINDOWED
363# if XCHAL_NUM_AREGS == 16
364 movi a15, 0 // for 16-register files, no need to call to reach the end
365# elif XCHAL_NUM_AREGS == 32
366 call12 .L__wdwspill_assist20 // call deep enough to clear out any live callers
367# elif XCHAL_NUM_AREGS == 64
368 call12 .L__wdwspill_assist52 // call deep enough to clear out any live callers
369# endif
370#endif
371 .endm // window_spill12
372
373/*----------------------------------------------------------------------
374 * window_spill_function
375 *
376 * This macro outputs a function that will spill its caller's callers'
377 * register windows to the stack. Eg. it could be used to implement
378 * a version of xthal_window_spill() that works in non-privileged tasks.
379 * This works for both privileged and non-privileged tasks.
380 *
381 * Typical usage:
382 *
383 * .text
384 * .align 4
385 * .global my_spill_function
386 * .type my_spill_function,@function
387 * my_spill_function:
388 * window_spill_function
389 *
390 * On entry to resulting function:
391 * none
392 * On exit from resulting function:
393 * none (no caller windows are in live registers)
394 */
395
396 .macro window_spill_function
397#if XCHAL_HAVE_WINDOWED
398# if XCHAL_NUM_AREGS == 32
399 entry sp, 48
400 bbci.l a0, 31, 1f // branch if called with call4
401 bbsi.l a0, 30, 2f // branch if called with call12
402 call8 .L__wdwspill_assist16 // called with call8, only need another 8
403 retw
4041: call12 .L__wdwspill_assist16 // called with call4, only need another 12
405 retw
4062: call4 .L__wdwspill_assist16 // called with call12, only need another 4
407 retw
408# elif XCHAL_NUM_AREGS == 64
409 entry sp, 48
410 bbci.l a0, 31, 1f // branch if called with call4
411 bbsi.l a0, 30, 2f // branch if called with call12
412 call4 .L__wdwspill_assist52 // called with call8, only need a call4
413 retw
4141: call8 .L__wdwspill_assist52 // called with call4, only need a call8
415 retw
4162: call12 .L__wdwspill_assist40 // called with call12, can skip a call12
417 retw
418# elif XCHAL_NUM_AREGS == 16
419 entry sp, 16
420 bbci.l a0, 31, 1f // branch if called with call4
421 bbsi.l a0, 30, 2f // branch if called with call12
422 movi a7, 0 // called with call8
423 retw
4241: movi a11, 0 // called with call4
4252: retw // if called with call12, everything already spilled
426
427// movi a15, 0 // trick to spill all but the direct caller
428// j 1f
429// // The entry instruction is magical in the assembler (gets auto-aligned)
430// // so we have to jump to it to avoid falling through the padding.
431// // We need entry/retw to know where to return.
432//1: entry sp, 16
433// retw
434# else
435# error "unrecognized address register file size"
436# endif
437#endif /* XCHAL_HAVE_WINDOWED */
438 window_spill_common
439 .endm // window_spill_function
440
441/*----------------------------------------------------------------------
442 * window_spill_common
443 *
444 * Common code used by any number of invocations of the window_spill##
445 * and window_spill_function macros.
446 *
447 * Must be instantiated exactly once within a given assembly unit,
448 * within call/j range of and same section as window_spill##
449 * macro invocations for that assembly unit.
450 * (Is automatically instantiated by the window_spill_function macro.)
451 */
452
453 .macro window_spill_common
454#if XCHAL_HAVE_WINDOWED && (XCHAL_NUM_AREGS == 32 || XCHAL_NUM_AREGS == 64)
455 .ifndef .L__wdwspill_defined
456# if XCHAL_NUM_AREGS >= 64
457.L__wdwspill_assist60:
458 entry sp, 32
459 call8 .L__wdwspill_assist52
460 retw
461.L__wdwspill_assist56:
462 entry sp, 16
463 call4 .L__wdwspill_assist52
464 retw
465.L__wdwspill_assist52:
466 entry sp, 48
467 call12 .L__wdwspill_assist40
468 retw
469.L__wdwspill_assist40:
470 entry sp, 48
471 call12 .L__wdwspill_assist28
472 retw
473# endif
474.L__wdwspill_assist28:
475 entry sp, 48
476 call12 .L__wdwspill_assist16
477 retw
478.L__wdwspill_assist24:
479 entry sp, 32
480 call8 .L__wdwspill_assist16
481 retw
482.L__wdwspill_assist20:
483 entry sp, 16
484 call4 .L__wdwspill_assist16
485 retw
486.L__wdwspill_assist16:
487 entry sp, 16
488 movi a15, 0
489 retw
490 .set .L__wdwspill_defined, 1
491 .endif
492#endif /* XCHAL_HAVE_WINDOWED with 32 or 64 aregs */
493 .endm // window_spill_common
494
495/*----------------------------------------------------------------------
496 * beqi32
497 *
498 * macro implements version of beqi for arbitrary 32-bit immidiate value
499 *
500 * beqi32 ax, ay, imm32, label
501 *
502 * Compares value in register ax with imm32 value and jumps to label if
503 * equal. Clobberes register ay if needed
504 *
505 */
506 .macro beqi32 ax, ay, imm, label
507 .ifeq ((\imm-1) & ~7) // 1..8 ?
508 beqi \ax, \imm, \label
509 .else
510 .ifeq (\imm+1) // -1 ?
511 beqi \ax, \imm, \label
512 .else
513 .ifeq (\imm) // 0 ?
514 beqz \ax, \label
515 .else
516 // We could also handle immediates 10,12,16,32,64,128,256
517 // but it would be a long macro...
518 movi \ay, \imm
519 beq \ax, \ay, \label
520 .endif
521 .endif
522 .endif
523 .endm // beqi32
524
525#endif /*XTENSA_COREASM_H*/
526
diff --git a/include/asm-xtensa/xtensa/corebits.h b/include/asm-xtensa/xtensa/corebits.h
new file mode 100644
index 000000000000..e578ade41632
--- /dev/null
+++ b/include/asm-xtensa/xtensa/corebits.h
@@ -0,0 +1,77 @@
1#ifndef XTENSA_COREBITS_H
2#define XTENSA_COREBITS_H
3
4/*
5 * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
6 *
7 * xtensa/corebits.h - Xtensa Special Register field positions and masks.
8 *
9 * (In previous releases, these were defined in specreg.h, a generated file.
10 * This file is not generated, i.e. it is processor configuration independent.)
11 */
12
13
14/* EXCCAUSE register fields: */
15#define EXCCAUSE_EXCCAUSE_SHIFT 0
16#define EXCCAUSE_EXCCAUSE_MASK 0x3F
17/* Exception causes (mostly incomplete!): */
18#define EXCCAUSE_ILLEGAL 0
19#define EXCCAUSE_SYSCALL 1
20#define EXCCAUSE_IFETCHERROR 2
21#define EXCCAUSE_LOADSTOREERROR 3
22#define EXCCAUSE_LEVEL1INTERRUPT 4
23#define EXCCAUSE_ALLOCA 5
24
25/* PS register fields: */
26#define PS_WOE_SHIFT 18
27#define PS_WOE_MASK 0x00040000
28#define PS_WOE PS_WOE_MASK
29#define PS_CALLINC_SHIFT 16
30#define PS_CALLINC_MASK 0x00030000
31#define PS_CALLINC(n) (((n)&3)<<PS_CALLINC_SHIFT) /* n = 0..3 */
32#define PS_OWB_SHIFT 8
33#define PS_OWB_MASK 0x00000F00
34#define PS_OWB(n) (((n)&15)<<PS_OWB_SHIFT) /* n = 0..15 (or 0..7) */
35#define PS_RING_SHIFT 6
36#define PS_RING_MASK 0x000000C0
37#define PS_RING(n) (((n)&3)<<PS_RING_SHIFT) /* n = 0..3 */
38#define PS_UM_SHIFT 5
39#define PS_UM_MASK 0x00000020
40#define PS_UM PS_UM_MASK
41#define PS_EXCM_SHIFT 4
42#define PS_EXCM_MASK 0x00000010
43#define PS_EXCM PS_EXCM_MASK
44#define PS_INTLEVEL_SHIFT 0
45#define PS_INTLEVEL_MASK 0x0000000F
46#define PS_INTLEVEL(n) ((n)&PS_INTLEVEL_MASK) /* n = 0..15 */
47/* Backward compatibility (deprecated): */
48#define PS_PROGSTACK_SHIFT PS_UM_SHIFT
49#define PS_PROGSTACK_MASK PS_UM_MASK
50#define PS_PROG_SHIFT PS_UM_SHIFT
51#define PS_PROG_MASK PS_UM_MASK
52#define PS_PROG PS_UM
53
54/* DBREAKCn register fields: */
55#define DBREAKC_MASK_SHIFT 0
56#define DBREAKC_MASK_MASK 0x0000003F
57#define DBREAKC_LOADBREAK_SHIFT 30
58#define DBREAKC_LOADBREAK_MASK 0x40000000
59#define DBREAKC_STOREBREAK_SHIFT 31
60#define DBREAKC_STOREBREAK_MASK 0x80000000
61
62/* DEBUGCAUSE register fields: */
63#define DEBUGCAUSE_DEBUGINT_SHIFT 5
64#define DEBUGCAUSE_DEBUGINT_MASK 0x20 /* debug interrupt */
65#define DEBUGCAUSE_BREAKN_SHIFT 4
66#define DEBUGCAUSE_BREAKN_MASK 0x10 /* BREAK.N instruction */
67#define DEBUGCAUSE_BREAK_SHIFT 3
68#define DEBUGCAUSE_BREAK_MASK 0x08 /* BREAK instruction */
69#define DEBUGCAUSE_DBREAK_SHIFT 2
70#define DEBUGCAUSE_DBREAK_MASK 0x04 /* DBREAK match */
71#define DEBUGCAUSE_IBREAK_SHIFT 1
72#define DEBUGCAUSE_IBREAK_MASK 0x02 /* IBREAK match */
73#define DEBUGCAUSE_ICOUNT_SHIFT 0
74#define DEBUGCAUSE_ICOUNT_MASK 0x01 /* ICOUNT would increment to zero */
75
76#endif /*XTENSA_COREBITS_H*/
77
diff --git a/include/asm-xtensa/xtensa/hal.h b/include/asm-xtensa/xtensa/hal.h
new file mode 100644
index 000000000000..d10472505454
--- /dev/null
+++ b/include/asm-xtensa/xtensa/hal.h
@@ -0,0 +1,822 @@
1#ifndef XTENSA_HAL_H
2#define XTENSA_HAL_H
3
4/*
5 * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
6 *
7 * include/asm-xtensa/xtensa/hal.h -- contains a definition of the
8 * Core HAL interface.
9 *
10 * All definitions in this header file are independent of any specific
11 * Xtensa processor configuration. Thus an OS or other software can
12 * include this header file and be compiled into configuration-
13 * independent objects that can be distributed and eventually linked
14 * to the HAL library (libhal.a) to create a configuration-specific
15 * final executable.
16 *
17 * Certain definitions, however, are release-specific -- such as the
18 * XTHAL_RELEASE_xxx macros (or additions made in later releases).
19 *
20 * This file is subject to the terms and conditions of the GNU General Public
21 * License. See the file "COPYING" in the main directory of this archive
22 * for more details.
23 *
24 * Copyright (C) 2002 Tensilica Inc.
25 */
26
27
28/*----------------------------------------------------------------------
29 Constant Definitions
30 (shared with assembly)
31 ----------------------------------------------------------------------*/
32
33/* Software release information (not configuration-specific!): */
34#define XTHAL_RELEASE_MAJOR 1050
35#define XTHAL_RELEASE_MINOR 0
36#define XTHAL_RELEASE_NAME "T1050.0-2002-08-06-eng0"
37#define XTHAL_RELEASE_INTERNAL "2002-08-06-eng0"
38#define XTHAL_REL_T1050 1
39#define XTHAL_REL_T1050_0 1
40#define XTHAL_REL_T1050_0_2002 1
41#define XTHAL_REL_T1050_0_2002_08 1
42#define XTHAL_REL_T1050_0_2002_08_06 1
43#define XTHAL_REL_T1050_0_2002_08_06_ENG0 1
44
45/* HAL version numbers (these names are for backward compatibility): */
46#define XTHAL_MAJOR_REV XTHAL_RELEASE_MAJOR
47#define XTHAL_MINOR_REV XTHAL_RELEASE_MINOR
48/*
49 * A bit of software release history on values of XTHAL_{MAJOR,MINOR}_REV:
50 *
51 * Release MAJOR MINOR Comment
52 * ======= ===== ===== =======
53 * T1015.n n/a n/a (HAL not yet available)
54 * T1020.{0,1,2} 0 1 (HAL beta)
55 * T1020.{3,4} 0 2 First release.
56 * T1020.n (n>4) 0 2 or >3 (TBD)
57 * T1030.0 0 1 (HAL beta)
58 * T1030.{1,2} 0 3 Equivalent to first release.
59 * T1030.n (n>=3) 0 >= 3 (TBD)
60 * T1040.n 1040 n Full CHAL available from T1040.2
61 * T1050.n 1050 n Current release.
62 *
63 *
64 * Note: there is a distinction between the software release with
65 * which something is compiled (accessible using XTHAL_RELEASE_* macros)
66 * and the software release with which the HAL library was compiled
67 * (accessible using Xthal_release_* global variables). This
68 * distinction is particularly relevant for vendors that distribute
69 * configuration-independent binaries (eg. an OS), where their customer
70 * might link it with a HAL of a different Xtensa software release.
71 * In this case, it may be appropriate for the OS to verify at run-time
72 * whether XTHAL_RELEASE_* and Xthal_release_* are compatible.
73 * [Guidelines as to which release is compatible with which are not
74 * currently provided explicitly, but might be inferred from reading
75 * OSKit documentation for all releases -- compatibility is also highly
76 * dependent on which HAL features are used. Each release is usually
77 * backward compatible, with very few exceptions if any.]
78 *
79 * Notes:
80 * Tornado 2.0 supported in T1020.3+, T1030.1+, and T1040.{0,1} only.
81 * Tornado 2.0.2 supported in T1040.2+, and T1050.
82 * Compile-time HAL port of NucleusPlus supported by T1040.2+ and T1050.
83 */
84
85
86/*
87 * Architectural limits, independent of configuration.
88 * Note that these are ISA-defined limits, not micro-architecture implementation
89 * limits enforced by the Xtensa Processor Generator (which may be stricter than
90 * these below).
91 */
92#define XTHAL_MAX_CPS 8 /* max number of coprocessors (0..7) */
93#define XTHAL_MAX_INTERRUPTS 32 /* max number of interrupts (0..31) */
94#define XTHAL_MAX_INTLEVELS 16 /* max number of interrupt levels (0..15) */
95 /* (as of T1040, implementation limit is 7: 0..6) */
96#define XTHAL_MAX_TIMERS 4 /* max number of timers (CCOMPARE0..CCOMPARE3) */
97 /* (as of T1040, implementation limit is 3: 0..2) */
98
99/* Misc: */
100#define XTHAL_LITTLEENDIAN 0
101#define XTHAL_BIGENDIAN 1
102
103
104/* Interrupt types: */
105#define XTHAL_INTTYPE_UNCONFIGURED 0
106#define XTHAL_INTTYPE_SOFTWARE 1
107#define XTHAL_INTTYPE_EXTERN_EDGE 2
108#define XTHAL_INTTYPE_EXTERN_LEVEL 3
109#define XTHAL_INTTYPE_TIMER 4
110#define XTHAL_INTTYPE_NMI 5
111#define XTHAL_MAX_INTTYPES 6 /* number of interrupt types */
112
113/* Timer related: */
114#define XTHAL_TIMER_UNCONFIGURED -1 /* Xthal_timer_interrupt[] value for non-existent timers */
115#define XTHAL_TIMER_UNASSIGNED XTHAL_TIMER_UNCONFIGURED /* (for backwards compatibility only) */
116
117
118/* Access Mode bits (tentative): */ /* bit abbr unit short_name PPC equ - Description */
119#define XTHAL_AMB_EXCEPTION 0 /* 001 E EX fls: EXception none - generate exception on any access (aka "illegal") */
120#define XTHAL_AMB_HITCACHE 1 /* 002 C CH fls: use Cache on Hit ~(I CI) - use cache on hit -- way from tag match [or H HC, or U UC] (ISA: same, except for Isolate case) */
121#define XTHAL_AMB_ALLOCATE 2 /* 004 A AL fl?: ALlocate none - refill cache on miss -- way from LRU [or F FI fill] (ISA: Read/Write Miss Refill) */
122#define XTHAL_AMB_WRITETHRU 3 /* 008 W WT --s: WriteThrough W WT - store immediately to memory (ISA: same) */
123#define XTHAL_AMB_ISOLATE 4 /* 010 I IS fls: ISolate none - use cache regardless of hit-vs-miss -- way from vaddr (ISA: use-cache-on-miss+hit) */
124#define XTHAL_AMB_GUARD 5 /* 020 G GU ?l?: GUard G * - non-speculative; spec/replay refs not permitted */
125#if 0
126#define XTHAL_AMB_ORDERED x /* 000 O OR fls: ORdered G * - mem accesses cannot be out of order */
127#define XTHAL_AMB_FUSEWRITES x /* 000 F FW --s: FuseWrites none - allow combining/merging multiple writes (to same datapath data unit) into one (implied by writeback) */
128#define XTHAL_AMB_COHERENT x /* 000 M MC fl?: Mem/MP Coherent M - on reads, other CPUs/bus-masters may need to supply data */
129#define XTHAL_AMB_TRUSTED x /* 000 T TR ?l?: TRusted none - memory will not bus error (if it does, handle as fatal imprecise interrupt) */
130#define XTHAL_AMB_PREFETCH x /* 000 P PR fl?: PRefetch none - on refill, read line+1 into prefetch buffers */
131#define XTHAL_AMB_STREAM x /* 000 S ST ???: STreaming none - access one of N stream buffers */
132#endif /*0*/
133
134#define XTHAL_AM_EXCEPTION (1<<XTHAL_AMB_EXCEPTION)
135#define XTHAL_AM_HITCACHE (1<<XTHAL_AMB_HITCACHE)
136#define XTHAL_AM_ALLOCATE (1<<XTHAL_AMB_ALLOCATE)
137#define XTHAL_AM_WRITETHRU (1<<XTHAL_AMB_WRITETHRU)
138#define XTHAL_AM_ISOLATE (1<<XTHAL_AMB_ISOLATE)
139#define XTHAL_AM_GUARD (1<<XTHAL_AMB_GUARD)
140#if 0
141#define XTHAL_AM_ORDERED (1<<XTHAL_AMB_ORDERED)
142#define XTHAL_AM_FUSEWRITES (1<<XTHAL_AMB_FUSEWRITES)
143#define XTHAL_AM_COHERENT (1<<XTHAL_AMB_COHERENT)
144#define XTHAL_AM_TRUSTED (1<<XTHAL_AMB_TRUSTED)
145#define XTHAL_AM_PREFETCH (1<<XTHAL_AMB_PREFETCH)
146#define XTHAL_AM_STREAM (1<<XTHAL_AMB_STREAM)
147#endif /*0*/
148
149/*
150 * Allowed Access Modes (bit combinations).
151 *
152 * Columns are:
153 * "FOGIWACE"
154 * Access mode bits (see XTHAL_AMB_xxx above).
155 * <letter> = bit is set
156 * '-' = bit is clear
157 * '.' = bit is irrelevant / don't care, as follows:
158 * E=1 makes all others irrelevant
159 * W,F relevant only for stores
160 * "2345"
161 * Indicates which Xtensa releases support the corresponding
162 * access mode. Releases for each character column are:
163 * 2 = prior to T1020.2: T1015 (V1.5), T1020.0, T1020.1
164 * 3 = T1020.2 and later: T1020.2+, T1030
165 * 4 = T1040
166 * 5 = T1050 (maybe)
167 * And the character column contents are:
168 * <number> = support by release(s)
169 * "." = unsupported by release(s)
170 * "?" = support unknown
171 */
172 /* FOGIWACE 2345 */
173/* For instruction fetch: */
174#define XTHAL_FAM_EXCEPTION 0x001 /* .......E 2345 exception */
175#define XTHAL_FAM_ISOLATE 0x012 /* .--I.-C- .... isolate */
176#define XTHAL_FAM_BYPASS 0x000 /* .---.--- 2345 bypass */
177#define XTHAL_FAM_NACACHED 0x002 /* .---.-C- .... cached no-allocate (frozen) */
178#define XTHAL_FAM_CACHED 0x006 /* .---.AC- 2345 cached */
179/* For data load: */
180#define XTHAL_LAM_EXCEPTION 0x001 /* .......E 2345 exception */
181#define XTHAL_LAM_ISOLATE 0x012 /* .--I.-C- 2345 isolate */
182#define XTHAL_LAM_BYPASS 0x000 /* .O--.--- 2... bypass speculative */
183#define XTHAL_LAM_BYPASSG 0x020 /* .OG-.--- .345 bypass guarded */
184#define XTHAL_LAM_NACACHED 0x002 /* .O--.-C- 2... cached no-allocate speculative */
185#define XTHAL_LAM_NACACHEDG 0x022 /* .OG-.-C- .345 cached no-allocate guarded */
186#define XTHAL_LAM_CACHED 0x006 /* .---.AC- 2345 cached speculative */
187#define XTHAL_LAM_CACHEDG 0x026 /* .?G-.AC- .... cached guarded */
188/* For data store: */
189#define XTHAL_SAM_EXCEPTION 0x001 /* .......E 2345 exception */
190#define XTHAL_SAM_ISOLATE 0x032 /* .-GI--C- 2345 isolate */
191#define XTHAL_SAM_BYPASS 0x028 /* -OG-W--- 2345 bypass */
192/*efine XTHAL_SAM_BYPASSF 0x028*/ /* F-G-W--- ...? bypass write-combined */
193#define XTHAL_SAM_WRITETHRU 0x02A /* -OG-W-C- 234? writethrough */
194/*efine XTHAL_SAM_WRITETHRUF 0x02A*/ /* F-G-W-C- ...5 writethrough write-combined */
195#define XTHAL_SAM_WRITEALLOC 0x02E /* -OG-WAC- ...? writethrough-allocate */
196/*efine XTHAL_SAM_WRITEALLOCF 0x02E*/ /* F-G-WAC- ...? writethrough-allocate write-combined */
197#define XTHAL_SAM_WRITEBACK 0x026 /* F-G--AC- ...5 writeback */
198
199#if 0
200/*
201 Cache attribute encoding for CACHEATTR (per ISA):
202 (Note: if this differs from ISA Ref Manual, ISA has precedence)
203
204 Inst-fetches Loads Stores
205 ------------- ------------ -------------
2060x0 FCA_EXCEPTION ?LCA_NACACHED_G* SCA_WRITETHRU "uncached"
2070x1 FCA_CACHED LCA_CACHED SCA_WRITETHRU cached
2080x2 FCA_BYPASS LCA_BYPASS_G* SCA_BYPASS bypass
2090x3 FCA_CACHED LCA_CACHED SCA_WRITEALLOCF write-allocate
210 or LCA_EXCEPTION SCA_EXCEPTION (if unimplemented)
2110x4 FCA_CACHED LCA_CACHED SCA_WRITEBACK write-back
212 or LCA_EXCEPTION SCA_EXCEPTION (if unimplemented)
2130x5..D FCA_EXCEPTION LCA_EXCEPTION SCA_EXCEPTION (reserved)
2140xE FCA_EXCEPTION LCA_ISOLATE SCA_ISOLATE isolate
2150xF FCA_EXCEPTION LCA_EXCEPTION SCA_EXCEPTION illegal
216 * Prior to T1020.2?, guard feature not supported, this defaulted to speculative (no _G)
217*/
218#endif /*0*/
219
220
221#if !defined(__ASSEMBLY__) && !defined(_NOCLANGUAGE)
222#ifdef __cplusplus
223extern "C" {
224#endif
225
226/*----------------------------------------------------------------------
227 HAL
228 ----------------------------------------------------------------------*/
229
230/* Constant to be checked in build = (XTHAL_MAJOR_REV<<16)|XTHAL_MINOR_REV */
231extern const unsigned int Xthal_rev_no;
232
233
234/*----------------------------------------------------------------------
235 Processor State
236 ----------------------------------------------------------------------*/
237/* save & restore the extra processor state */
238extern void xthal_save_extra(void *base);
239extern void xthal_restore_extra(void *base);
240
241extern void xthal_save_cpregs(void *base, int);
242extern void xthal_restore_cpregs(void *base, int);
243
244/*extern void xthal_save_all_extra(void *base);*/
245/*extern void xthal_restore_all_extra(void *base);*/
246
247/* space for processor state */
248extern const unsigned int Xthal_extra_size;
249extern const unsigned int Xthal_extra_align;
250/* space for TIE register files */
251extern const unsigned int Xthal_cpregs_size[XTHAL_MAX_CPS];
252extern const unsigned int Xthal_cpregs_align[XTHAL_MAX_CPS];
253
254/* total of space for the processor state (for Tor2) */
255extern const unsigned int Xthal_all_extra_size;
256extern const unsigned int Xthal_all_extra_align;
257
258/* initialize the extra processor */
259/*extern void xthal_init_extra(void);*/
260/* initialize the TIE coprocessor */
261/*extern void xthal_init_cp(int);*/
262
263/* initialize the extra processor */
264extern void xthal_init_mem_extra(void *);
265/* initialize the TIE coprocessor */
266extern void xthal_init_mem_cp(void *, int);
267
268/* validate & invalidate the TIE register file */
269extern void xthal_validate_cp(int);
270extern void xthal_invalidate_cp(int);
271
272/* the number of TIE coprocessors contiguous from zero (for Tor2) */
273extern const unsigned int Xthal_num_coprocessors;
274
275/* actual number of coprocessors */
276extern const unsigned char Xthal_cp_num;
277/* index of highest numbered coprocessor, plus one */
278extern const unsigned char Xthal_cp_max;
279/* index of highest allowed coprocessor number, per cfg, plus one */
280/*extern const unsigned char Xthal_cp_maxcfg;*/
281/* bitmask of which coprocessors are present */
282extern const unsigned int Xthal_cp_mask;
283
284/* read and write cpenable register */
285extern void xthal_set_cpenable(unsigned);
286extern unsigned xthal_get_cpenable(void);
287
288/* read & write extra state register */
289/*extern int xthal_read_extra(void *base, unsigned reg, unsigned *value);*/
290/*extern int xthal_write_extra(void *base, unsigned reg, unsigned value);*/
291
292/* read & write a TIE coprocessor register */
293/*extern int xthal_read_cpreg(void *base, int cp, unsigned reg, unsigned *value);*/
294/*extern int xthal_write_cpreg(void *base, int cp, unsigned reg, unsigned value);*/
295
296/* return coprocessor number based on register */
297/*extern int xthal_which_cp(unsigned reg);*/
298
299/*----------------------------------------------------------------------
300 Interrupts
301 ----------------------------------------------------------------------*/
302
303/* the number of interrupt levels */
304extern const unsigned char Xthal_num_intlevels;
305/* the number of interrupts */
306extern const unsigned char Xthal_num_interrupts;
307
308/* mask for level of interrupts */
309extern const unsigned int Xthal_intlevel_mask[XTHAL_MAX_INTLEVELS];
310/* mask for level 0 to N interrupts */
311extern const unsigned int Xthal_intlevel_andbelow_mask[XTHAL_MAX_INTLEVELS];
312
313/* level of each interrupt */
314extern const unsigned char Xthal_intlevel[XTHAL_MAX_INTERRUPTS];
315
316/* type per interrupt */
317extern const unsigned char Xthal_inttype[XTHAL_MAX_INTERRUPTS];
318
319/* masks of each type of interrupt */
320extern const unsigned int Xthal_inttype_mask[XTHAL_MAX_INTTYPES];
321
322/* interrupt numbers assigned to each timer interrupt */
323extern const int Xthal_timer_interrupt[XTHAL_MAX_TIMERS];
324
325/*** Virtual interrupt prioritization: ***/
326
327/* Convert between interrupt levels (as per PS.INTLEVEL) and virtual interrupt priorities: */
328extern unsigned xthal_vpri_to_intlevel(unsigned vpri);
329extern unsigned xthal_intlevel_to_vpri(unsigned intlevel);
330
331/* Enables/disables given set (mask) of interrupts; returns previous enabled-mask of all ints: */
332extern unsigned xthal_int_enable(unsigned);
333extern unsigned xthal_int_disable(unsigned);
334
335/* Set/get virtual priority of an interrupt: */
336extern int xthal_set_int_vpri(int intnum, int vpri);
337extern int xthal_get_int_vpri(int intnum);
338
339/* Set/get interrupt lockout level for exclusive access to virtual priority data structures: */
340extern void xthal_set_vpri_locklevel(unsigned intlevel);
341extern unsigned xthal_get_vpri_locklevel(void);
342
343/* Set/get current virtual interrupt priority: */
344extern unsigned xthal_set_vpri(unsigned vpri);
345extern unsigned xthal_get_vpri(unsigned vpri);
346extern unsigned xthal_set_vpri_intlevel(unsigned intlevel);
347extern unsigned xthal_set_vpri_lock(void);
348
349
350
351/*----------------------------------------------------------------------
352 Generic Interrupt Trampolining Support
353 ----------------------------------------------------------------------*/
354
355typedef void (XtHalVoidFunc)(void);
356
357/*
358 * Bitmask of interrupts currently trampolining down:
359 */
360extern unsigned Xthal_tram_pending;
361
362/*
363 * Bitmask of which interrupts currently trampolining down
364 * synchronously are actually enabled; this bitmask is necessary
365 * because INTENABLE cannot hold that state (sync-trampolining
366 * interrupts must be kept disabled while trampolining);
367 * in the current implementation, any bit set here is not set
368 * in INTENABLE, and vice-versa; once a sync-trampoline is
369 * handled (at level one), its enable bit must be moved from
370 * here to INTENABLE:
371 */
372extern unsigned Xthal_tram_enabled;
373
374/*
375 * Bitmask of interrupts configured for sync trampolining:
376 */
377extern unsigned Xthal_tram_sync;
378
379
380/* Trampoline support functions: */
381extern unsigned xthal_tram_pending_to_service( void );
382extern void xthal_tram_done( unsigned serviced_mask );
383extern int xthal_tram_set_sync( int intnum, int sync );
384extern XtHalVoidFunc* xthal_set_tram_trigger_func( XtHalVoidFunc *trigger_fn );
385
386/* INTENABLE,INTREAD,INTSET,INTCLEAR register access functions: */
387extern unsigned xthal_get_intenable( void );
388extern void xthal_set_intenable( unsigned );
389extern unsigned xthal_get_intread( void );
390extern void xthal_set_intset( unsigned );
391extern void xthal_set_intclear( unsigned );
392
393
394/*----------------------------------------------------------------------
395 Register Windows
396 ----------------------------------------------------------------------*/
397
398/* number of registers in register window */
399extern const unsigned int Xthal_num_aregs;
400extern const unsigned char Xthal_num_aregs_log2;
401
402/* This spill any live register windows (other than the caller's): */
403extern void xthal_window_spill( void );
404
405
406/*----------------------------------------------------------------------
407 Cache
408 ----------------------------------------------------------------------*/
409
410/* size of the cache lines in log2(bytes) */
411extern const unsigned char Xthal_icache_linewidth;
412extern const unsigned char Xthal_dcache_linewidth;
413/* size of the cache lines in bytes */
414extern const unsigned short Xthal_icache_linesize;
415extern const unsigned short Xthal_dcache_linesize;
416/* number of cache sets in log2(lines per way) */
417extern const unsigned char Xthal_icache_setwidth;
418extern const unsigned char Xthal_dcache_setwidth;
419/* cache set associativity (number of ways) */
420extern const unsigned int Xthal_icache_ways;
421extern const unsigned int Xthal_dcache_ways;
422/* size of the caches in bytes (ways * 2^(linewidth + setwidth)) */
423extern const unsigned int Xthal_icache_size;
424extern const unsigned int Xthal_dcache_size;
425/* cache features */
426extern const unsigned char Xthal_dcache_is_writeback;
427extern const unsigned char Xthal_icache_line_lockable;
428extern const unsigned char Xthal_dcache_line_lockable;
429
430/* cache attribute register control (used by other HAL routines) */
431extern unsigned xthal_get_cacheattr( void );
432extern unsigned xthal_get_icacheattr( void );
433extern unsigned xthal_get_dcacheattr( void );
434extern void xthal_set_cacheattr( unsigned );
435extern void xthal_set_icacheattr( unsigned );
436extern void xthal_set_dcacheattr( unsigned );
437
438/* initialize cache support (must be called once at startup, before all other cache calls) */
439/*extern void xthal_cache_startinit( void );*/
440/* reset caches */
441/*extern void xthal_icache_reset( void );*/
442/*extern void xthal_dcache_reset( void );*/
443/* enable caches */
444extern void xthal_icache_enable( void ); /* DEPRECATED */
445extern void xthal_dcache_enable( void ); /* DEPRECATED */
446/* disable caches */
447extern void xthal_icache_disable( void ); /* DEPRECATED */
448extern void xthal_dcache_disable( void ); /* DEPRECATED */
449
450/* invalidate the caches */
451extern void xthal_icache_all_invalidate( void );
452extern void xthal_dcache_all_invalidate( void );
453extern void xthal_icache_region_invalidate( void *addr, unsigned size );
454extern void xthal_dcache_region_invalidate( void *addr, unsigned size );
455extern void xthal_icache_line_invalidate(void *addr);
456extern void xthal_dcache_line_invalidate(void *addr);
457/* write dirty data back */
458extern void xthal_dcache_all_writeback( void );
459extern void xthal_dcache_region_writeback( void *addr, unsigned size );
460extern void xthal_dcache_line_writeback(void *addr);
461/* write dirty data back and invalidate */
462extern void xthal_dcache_all_writeback_inv( void );
463extern void xthal_dcache_region_writeback_inv( void *addr, unsigned size );
464extern void xthal_dcache_line_writeback_inv(void *addr);
465/* prefetch and lock specified memory range into cache */
466extern void xthal_icache_region_lock( void *addr, unsigned size );
467extern void xthal_dcache_region_lock( void *addr, unsigned size );
468extern void xthal_icache_line_lock(void *addr);
469extern void xthal_dcache_line_lock(void *addr);
470/* unlock from cache */
471extern void xthal_icache_all_unlock( void );
472extern void xthal_dcache_all_unlock( void );
473extern void xthal_icache_region_unlock( void *addr, unsigned size );
474extern void xthal_dcache_region_unlock( void *addr, unsigned size );
475extern void xthal_icache_line_unlock(void *addr);
476extern void xthal_dcache_line_unlock(void *addr);
477
478
479/* sync icache and memory */
480extern void xthal_icache_sync( void );
481/* sync dcache and memory */
482extern void xthal_dcache_sync( void );
483
484/*----------------------------------------------------------------------
485 Debug
486 ----------------------------------------------------------------------*/
487
488/* 1 if debug option configured, 0 if not: */
489extern const int Xthal_debug_configured;
490
491/* Number of instruction and data break registers: */
492extern const int Xthal_num_ibreak;
493extern const int Xthal_num_dbreak;
494
495/* Set (plant) and remove software breakpoint, both synchronizing cache: */
496extern unsigned int xthal_set_soft_break(void *addr);
497extern void xthal_remove_soft_break(void *addr, unsigned int);
498
499
500/*----------------------------------------------------------------------
501 Disassembler
502 ----------------------------------------------------------------------*/
503
504/* Max expected size of the return buffer for a disassembled instruction (hint only): */
505#define XTHAL_DISASM_BUFSIZE 80
506
507/* Disassembly option bits for selecting what to return: */
508#define XTHAL_DISASM_OPT_ADDR 0x0001 /* display address */
509#define XTHAL_DISASM_OPT_OPHEX 0x0002 /* display opcode bytes in hex */
510#define XTHAL_DISASM_OPT_OPCODE 0x0004 /* display opcode name (mnemonic) */
511#define XTHAL_DISASM_OPT_PARMS 0x0008 /* display parameters */
512#define XTHAL_DISASM_OPT_ALL 0x0FFF /* display everything */
513
514/* routine to get a string for the disassembled instruction */
515extern int xthal_disassemble( unsigned char *instr_buf, void *tgt_addr,
516 char *buffer, unsigned buflen, unsigned options );
517
518/* routine to get the size of the next instruction. Returns 0 for
519 illegal instruction */
520extern int xthal_disassemble_size( unsigned char *instr_buf );
521
522
523/*----------------------------------------------------------------------
524 Core Counter
525 ----------------------------------------------------------------------*/
526
527/* counter info */
528extern const unsigned char Xthal_have_ccount; /* set if CCOUNT register present */
529extern const unsigned char Xthal_num_ccompare; /* number of CCOMPAREn registers */
530
531/* get CCOUNT register (if not present return 0) */
532extern unsigned xthal_get_ccount(void);
533
534/* set and get CCOMPAREn registers (if not present, get returns 0) */
535extern void xthal_set_ccompare(int, unsigned);
536extern unsigned xthal_get_ccompare(int);
537
538
539/*----------------------------------------------------------------------
540 Instruction/Data RAM/ROM Access
541 ----------------------------------------------------------------------*/
542
543extern void* xthal_memcpy(void *dst, const void *src, unsigned len);
544extern void* xthal_bcopy(const void *src, void *dst, unsigned len);
545
546/*----------------------------------------------------------------------
547 MP Synchronization
548 ----------------------------------------------------------------------*/
549extern int xthal_compare_and_set( int *addr, int test_val, int compare_val );
550extern unsigned xthal_get_prid( void );
551
552/*extern const char Xthal_have_s32c1i;*/
553extern const unsigned char Xthal_have_prid;
554
555
556/*----------------------------------------------------------------------
557 Miscellaneous
558 ----------------------------------------------------------------------*/
559
560extern const unsigned int Xthal_release_major;
561extern const unsigned int Xthal_release_minor;
562extern const char * const Xthal_release_name;
563extern const char * const Xthal_release_internal;
564
565extern const unsigned char Xthal_memory_order;
566extern const unsigned char Xthal_have_windowed;
567extern const unsigned char Xthal_have_density;
568extern const unsigned char Xthal_have_booleans;
569extern const unsigned char Xthal_have_loops;
570extern const unsigned char Xthal_have_nsa;
571extern const unsigned char Xthal_have_minmax;
572extern const unsigned char Xthal_have_sext;
573extern const unsigned char Xthal_have_clamps;
574extern const unsigned char Xthal_have_mac16;
575extern const unsigned char Xthal_have_mul16;
576extern const unsigned char Xthal_have_fp;
577extern const unsigned char Xthal_have_speculation;
578extern const unsigned char Xthal_have_exceptions;
579extern const unsigned char Xthal_xea_version;
580extern const unsigned char Xthal_have_interrupts;
581extern const unsigned char Xthal_have_highlevel_interrupts;
582extern const unsigned char Xthal_have_nmi;
583
584extern const unsigned short Xthal_num_writebuffer_entries;
585
586extern const unsigned int Xthal_build_unique_id;
587/* Release info for hardware targeted by software upgrades: */
588extern const unsigned int Xthal_hw_configid0;
589extern const unsigned int Xthal_hw_configid1;
590extern const unsigned int Xthal_hw_release_major;
591extern const unsigned int Xthal_hw_release_minor;
592extern const char * const Xthal_hw_release_name;
593extern const char * const Xthal_hw_release_internal;
594
595
596/* Internal memories... */
597
598extern const unsigned char Xthal_num_instrom;
599extern const unsigned char Xthal_num_instram;
600extern const unsigned char Xthal_num_datarom;
601extern const unsigned char Xthal_num_dataram;
602extern const unsigned char Xthal_num_xlmi;
603extern const unsigned int Xthal_instrom_vaddr[1];
604extern const unsigned int Xthal_instrom_paddr[1];
605extern const unsigned int Xthal_instrom_size [1];
606extern const unsigned int Xthal_instram_vaddr[1];
607extern const unsigned int Xthal_instram_paddr[1];
608extern const unsigned int Xthal_instram_size [1];
609extern const unsigned int Xthal_datarom_vaddr[1];
610extern const unsigned int Xthal_datarom_paddr[1];
611extern const unsigned int Xthal_datarom_size [1];
612extern const unsigned int Xthal_dataram_vaddr[1];
613extern const unsigned int Xthal_dataram_paddr[1];
614extern const unsigned int Xthal_dataram_size [1];
615extern const unsigned int Xthal_xlmi_vaddr[1];
616extern const unsigned int Xthal_xlmi_paddr[1];
617extern const unsigned int Xthal_xlmi_size [1];
618
619
620
621/*----------------------------------------------------------------------
622 Memory Management Unit
623 ----------------------------------------------------------------------*/
624
625extern const unsigned char Xthal_have_spanning_way;
626extern const unsigned char Xthal_have_identity_map;
627extern const unsigned char Xthal_have_mimic_cacheattr;
628extern const unsigned char Xthal_have_xlt_cacheattr;
629extern const unsigned char Xthal_have_cacheattr;
630extern const unsigned char Xthal_have_tlbs;
631
632extern const unsigned char Xthal_mmu_asid_bits; /* 0 .. 8 */
633extern const unsigned char Xthal_mmu_asid_kernel;
634extern const unsigned char Xthal_mmu_rings; /* 1 .. 4 (perhaps 0 if no MMU and/or no protection?) */
635extern const unsigned char Xthal_mmu_ring_bits;
636extern const unsigned char Xthal_mmu_sr_bits;
637extern const unsigned char Xthal_mmu_ca_bits;
638extern const unsigned int Xthal_mmu_max_pte_page_size;
639extern const unsigned int Xthal_mmu_min_pte_page_size;
640
641extern const unsigned char Xthal_itlb_way_bits;
642extern const unsigned char Xthal_itlb_ways;
643extern const unsigned char Xthal_itlb_arf_ways;
644extern const unsigned char Xthal_dtlb_way_bits;
645extern const unsigned char Xthal_dtlb_ways;
646extern const unsigned char Xthal_dtlb_arf_ways;
647
648/* Convert between virtual and physical addresses (through static maps only): */
649/*** WARNING: these two functions may go away in a future release; don't depend on them! ***/
650extern int xthal_static_v2p( unsigned vaddr, unsigned *paddrp );
651extern int xthal_static_p2v( unsigned paddr, unsigned *vaddrp, unsigned cached );
652
653#if 0
654/******************* EXPERIMENTAL AND TENTATIVE ONLY ********************/
655
656#define XTHAL_MMU_PAGESZ_COUNT_MAX 8 /* maximum number of different page sizes */
657extern const char Xthal_mmu_pagesz_count; /* 0 .. 8 number of different page sizes configured */
658
659/* Note: the following table doesn't necessarily have page sizes in increasing order: */
660extern const char Xthal_mmu_pagesz_log2[XTHAL_MMU_PAGESZ_COUNT_MAX]; /* 10 .. 28 (0 past count) */
661
662/* Sorted (increasing) table of page sizes, that indexes into the above table: */
663extern const char Xthal_mmu_pagesz_sorted[XTHAL_MMU_PAGESZ_COUNT_MAX]; /* 0 .. 7 (0 past count) */
664
665/*u32 Xthal_virtual_exceptions;*/ /* bitmask of which exceptions execute in virtual mode... */
666
667extern const char Xthal_mmu_pte_pagesz_log2_min; /* ?? minimum page size in PTEs */
668extern const char Xthal_mmu_pte_pagesz_log2_max; /* ?? maximum page size in PTEs */
669
670/* Cache Attribute Bits Implemented by the Cache (part of the cache abstraction) */
671extern const char Xthal_icache_fca_bits_implemented; /* ITLB/UTLB only! */
672extern const char Xthal_dcache_lca_bits_implemented; /* DTLB/UTLB only! */
673extern const char Xthal_dcache_sca_bits_implemented; /* DTLB/UTLB only! */
674
675/* Per TLB Parameters (Instruction, Data, Unified) */
676struct XtHalMmuTlb Xthal_itlb; /* description of MMU I-TLB generic features */
677struct XtHalMmuTlb Xthal_dtlb; /* description of MMU D-TLB generic features */
678struct XtHalMmuTlb Xthal_utlb; /* description of MMU U-TLB generic features */
679
680#define XTHAL_MMU_WAYS_MAX 8 /* maximum number of ways (associativities) for each TLB */
681
682/* Structure for common information described for each possible TLB (instruction, data and unified): */
683typedef struct XtHalMmuTlb {
684 u8 va_bits; /* 32 (number of virtual address bits) */
685 u8 pa_bits; /* 32 (number of physical address bits) */
686 bool tlb_va_indexed; /* 1 (set if TLB is indexed by virtual address) */
687 bool tlb_va_tagged; /* 0 (set if TLB is tagged by virtual address) */
688 bool cache_va_indexed; /* 1 (set if cache is indexed by virtual address) */
689 bool cache_va_tagged; /* 0 (set if cache is tagged by virtual address) */
690 /*bool (whether page tables are traversed in vaddr sorted order, paddr sorted order, ...) */
691 /*u8 (set of available page attribute bits, other than cache attribute bits defined above) */
692 /*u32 (various masks for pages, MMU table/TLB entries, etc.) */
693 u8 way_count; /* 0 .. 8 (number of ways, a.k.a. associativities, for this TLB) */
694 XtHalMmuTlbWay * ways[XTHAL_MMU_WAYS_MAX]; /* pointers to per-way parms for each way */
695} XtHalMmuTlb;
696
697/* Per TLB Way (Per Associativity) Parameters */
698typedef struct XtHalMmuTlbWay {
699 u32 index_count_log2; /* 0 .. 4 */
700 u32 pagesz_mask; /* 0 .. 2^pagesz_count - 1 (each bit corresponds to a size */
701 /* defined in the Xthal_mmu_pagesz_log2[] table) */
702 u32 vpn_const_mask;
703 u32 vpn_const_value;
704 u64 ppn_const_mask; /* future may support pa_bits > 32 */
705 u64 ppn_const_value;
706 u32 ppn_id_mask; /* paddr bits taken directly from vaddr */
707 bool backgnd_match; /* 0 or 1 */
708 /* These are defined in terms of the XTHAL_CACHE_xxx bits: */
709 u8 fca_const_mask; /* ITLB/UTLB only! */
710 u8 fca_const_value; /* ITLB/UTLB only! */
711 u8 lca_const_mask; /* DTLB/UTLB only! */
712 u8 lca_const_value; /* DTLB/UTLB only! */
713 u8 sca_const_mask; /* DTLB/UTLB only! */
714 u8 sca_const_value; /* DTLB/UTLB only! */
715 /* These define an encoding that map 5 bits in TLB and PTE entries to */
716 /* 8 bits (FCA, ITLB), 16 bits (LCA+SCA, DTLB) or 24 bits (FCA+LCA+SCA, UTLB): */
717 /* (they may be moved to struct XtHalMmuTlb) */
718 u8 ca_bits; /* number of bits in TLB/PTE entries for cache attributes */
719 u32 * ca_map; /* pointer to array of 2^ca_bits entries of FCA+LCA+SCA bits */
720} XtHalMmuTlbWay;
721
722/*
723 * The way to determine whether protection support is present in core
724 * is to [look at Xthal_mmu_rings ???].
725 * Give info on memory requirements for MMU tables and other in-memory
726 * data structures (globally, per task, base and per page, etc.) - whatever bounds can be calculated.
727 */
728
729
730/* Default vectors: */
731xthal_immu_fetch_miss_vector
732xthal_dmmu_load_miss_vector
733xthal_dmmu_store_miss_vector
734
735/* Functions called when a fault is detected: */
736typedef void (XtHalMmuFaultFunc)( unsigned vaddr, ...context... );
737/* Or, */
738/* a? = vaddr */
739/* a? = context... */
740/* PS.xxx = xxx */
741XtHalMMuFaultFunc *Xthal_immu_fetch_fault_func;
742XtHalMMuFaultFunc *Xthal_dmmu_load_fault_func;
743XtHalMMuFaultFunc *Xthal_dmmu_store_fault_func;
744
745/* Default Handlers: */
746/* The user and/or kernel exception handlers may jump to these handlers to handle the relevant exceptions,
747 * according to the value of EXCCAUSE. The exact register state on entry to these handlers is TBD. */
748/* When multiple TLB entries match (hit) on the same access: */
749xthal_immu_fetch_multihit_handler
750xthal_dmmu_load_multihit_handler
751xthal_dmmu_store_multihit_handler
752/* Protection violations according to cache attributes, and other cache attribute mismatches: */
753xthal_immu_fetch_attr_handler
754xthal_dmmu_load_attr_handler
755xthal_dmmu_store_attr_handler
756/* Protection violations due to insufficient ring level: */
757xthal_immu_fetch_priv_handler
758xthal_dmmu_load_priv_handler
759xthal_dmmu_store_priv_handler
760/* Alignment exception handlers (if supported by the particular Xtensa MMU configuration): */
761xthal_dmmu_load_align_handler
762xthal_dmmu_store_align_handler
763
764/* Or, alternatively, the OS user and/or kernel exception handlers may simply jump to the
765 * following entry points which will handle any values of EXCCAUSE not handled by the OS: */
766xthal_user_exc_default_handler
767xthal_kernel_exc_default_handler
768
769#endif /*0*/
770
771#ifdef INCLUDE_DEPRECATED_HAL_CODE
772extern const unsigned char Xthal_have_old_exc_arch;
773extern const unsigned char Xthal_have_mmu;
774extern const unsigned int Xthal_num_regs;
775extern const unsigned char Xthal_num_iroms;
776extern const unsigned char Xthal_num_irams;
777extern const unsigned char Xthal_num_droms;
778extern const unsigned char Xthal_num_drams;
779extern const unsigned int Xthal_configid0;
780extern const unsigned int Xthal_configid1;
781#endif
782
783#ifdef INCLUDE_DEPRECATED_HAL_DEBUG_CODE
784#define XTHAL_24_BIT_BREAK 0x80000000
785#define XTHAL_16_BIT_BREAK 0x40000000
786extern const unsigned short Xthal_ill_inst_16[16];
787#define XTHAL_DEST_REG 0xf0000000 /* Mask for destination register */
788#define XTHAL_DEST_REG_INST 0x08000000 /* Branch address is in register */
789#define XTHAL_DEST_REL_INST 0x04000000 /* Branch address is relative */
790#define XTHAL_RFW_INST 0x00000800
791#define XTHAL_RFUE_INST 0x00000400
792#define XTHAL_RFI_INST 0x00000200
793#define XTHAL_RFE_INST 0x00000100
794#define XTHAL_RET_INST 0x00000080
795#define XTHAL_BREAK_INST 0x00000040
796#define XTHAL_SYSCALL_INST 0x00000020
797#define XTHAL_LOOP_END 0x00000010 /* Not set by xthal_inst_type */
798#define XTHAL_JUMP_INST 0x00000008 /* Call or jump instruction */
799#define XTHAL_BRANCH_INST 0x00000004 /* Branch instruction */
800#define XTHAL_24_BIT_INST 0x00000002
801#define XTHAL_16_BIT_INST 0x00000001
802typedef struct xthal_state {
803 unsigned pc;
804 unsigned ar[16];
805 unsigned lbeg;
806 unsigned lend;
807 unsigned lcount;
808 unsigned extra_ptr;
809 unsigned cpregs_ptr[XTHAL_MAX_CPS];
810} XTHAL_STATE;
811extern unsigned int xthal_inst_type(void *addr);
812extern unsigned int xthal_branch_addr(void *addr);
813extern unsigned int xthal_get_npc(XTHAL_STATE *user_state);
814#endif /* INCLUDE_DEPRECATED_HAL_DEBUG_CODE */
815
816#ifdef __cplusplus
817}
818#endif
819#endif /*!__ASSEMBLY__ */
820
821#endif /*XTENSA_HAL_H*/
822
diff --git a/include/asm-xtensa/xtensa/simcall.h b/include/asm-xtensa/xtensa/simcall.h
new file mode 100644
index 000000000000..a2b868929a49
--- /dev/null
+++ b/include/asm-xtensa/xtensa/simcall.h
@@ -0,0 +1,130 @@
1#ifndef SIMCALL_INCLUDED
2#define SIMCALL_INCLUDED
3
4/*
5 * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
6 *
7 * include/asm-xtensa/xtensa/simcall.h - Simulator call numbers
8 *
9 * This file is subject to the terms and conditions of the GNU General
10 * Public License. See the file "COPYING" in the main directory of
11 * this archive for more details.
12 *
13 * Copyright (C) 2002 Tensilica Inc.
14 */
15
16
17/*
18 * System call like services offered by the simulator host.
19 * These are modeled after the Linux 2.4 kernel system calls
20 * for Xtensa processors. However not all system calls and
21 * not all functionality of a given system call are implemented,
22 * or necessarily have well defined or equivalent semantics in
23 * the context of a simulation (as opposed to a Unix kernel).
24 *
25 * These services behave largely as if they had been invoked
26 * as a task in the simulator host's operating system
27 * (eg. files accessed are those of the simulator host).
28 * However, these SIMCALLs model a virtual operating system
29 * so that various definitions, bit assignments etc
30 * (eg. open mode bits, errno values, etc) are independent
31 * of the host operating system used to run the simulation.
32 * Rather these definitions are specific to the Xtensa ISS.
33 * This way Xtensa ISA code written to use these SIMCALLs
34 * can (in principle) be simulated on any host.
35 *
36 * Up to 6 parameters are passed in registers a3 to a8
37 * (note the 6th parameter isn't passed on the stack,
38 * unlike windowed function calling conventions).
39 * The return value is in a2. A negative value in the
40 * range -4096 to -1 indicates a negated error code to be
41 * reported in errno with a return value of -1, otherwise
42 * the value in a2 is returned as is.
43 */
44
45/* These #defines need to match what's in Xtensa/OS/vxworks/xtiss/simcalls.c */
46
47#define SYS_nop 0 /* n/a - setup; used to flush register windows */
48#define SYS_exit 1 /*x*/
49#define SYS_fork 2
50#define SYS_read 3 /*x*/
51#define SYS_write 4 /*x*/
52#define SYS_open 5 /*x*/
53#define SYS_close 6 /*x*/
54#define SYS_rename 7 /*x 38 - waitpid */
55#define SYS_creat 8 /*x*/
56#define SYS_link 9 /*x (not implemented on WIN32) */
57#define SYS_unlink 10 /*x*/
58#define SYS_execv 11 /* n/a - execve */
59#define SYS_execve 12 /* 11 - chdir */
60#define SYS_pipe 13 /* 42 - time */
61#define SYS_stat 14 /* 106 - mknod */
62#define SYS_chmod 15
63#define SYS_chown 16 /* 202 - lchown */
64#define SYS_utime 17 /* 30 - break */
65#define SYS_wait 18 /* n/a - oldstat */
66#define SYS_lseek 19 /*x*/
67#define SYS_getpid 20
68#define SYS_isatty 21 /* n/a - mount */
69#define SYS_fstat 22 /* 108 - oldumount */
70#define SYS_time 23 /* 13 - setuid */
71#define SYS_gettimeofday 24 /*x 78 - getuid (not implemented on WIN32) */
72#define SYS_times 25 /*X 43 - stime (Xtensa-specific implementation) */
73#define SYS_socket 26
74#define SYS_sendto 27
75#define SYS_recvfrom 28
76#define SYS_select_one 29 /* not compitible select, one file descriptor at the time */
77#define SYS_bind 30
78#define SYS_ioctl 31
79
80/*
81 * Other...
82 */
83#define SYS_iss_argc 1000 /* returns value of argc */
84#define SYS_iss_argv_size 1001 /* bytes needed for argv & arg strings */
85#define SYS_iss_set_argv 1002 /* saves argv & arg strings at given addr */
86
87/*
88 * SIMCALLs for the ferret memory debugger. All are invoked by
89 * libferret.a ... ( Xtensa/Target-Libs/ferret )
90 */
91#define SYS_ferret 1010
92#define SYS_malloc 1011
93#define SYS_free 1012
94#define SYS_more_heap 1013
95#define SYS_no_heap 1014
96
97
98/*
99 * Extra SIMCALLs for GDB:
100 */
101#define SYS_gdb_break -1 /* invoked by XTOS on user exceptions if EPC points
102 to a break.n/break, regardless of cause! */
103#define SYS_xmon_out -2 /* invoked by XMON: ... */
104#define SYS_xmon_in -3 /* invoked by XMON: ... */
105#define SYS_xmon_flush -4 /* invoked by XMON: ... */
106#define SYS_gdb_abort -5 /* invoked by XTOS in _xtos_panic() */
107#define SYS_gdb_illegal_inst -6 /* invoked by XTOS for illegal instructions (too deeply) */
108#define SYS_xmon_init -7 /* invoked by XMON: ... */
109#define SYS_gdb_enter_sktloop -8 /* invoked by XTOS on debug exceptions */
110
111/*
112 * SIMCALLs for vxWorks xtiss BSP:
113 */
114#define SYS_setup_ppp_pipes -83
115#define SYS_log_msg -84
116
117/*
118 * Test SIMCALLs:
119 */
120#define SYS_test_write_state -100
121#define SYS_test_read_state -101
122
123/*
124 * SYS_select_one specifiers
125 */
126#define XTISS_SELECT_ONE_READ 1
127#define XTISS_SELECT_ONE_WRITE 2
128#define XTISS_SELECT_ONE_EXCEPT 3
129
130#endif /* !SIMCALL_INCLUDED */
diff --git a/include/asm-xtensa/xtensa/xt2000-uart.h b/include/asm-xtensa/xtensa/xt2000-uart.h
new file mode 100644
index 000000000000..0154460f0ed8
--- /dev/null
+++ b/include/asm-xtensa/xtensa/xt2000-uart.h
@@ -0,0 +1,155 @@
1#ifndef _uart_h_included_
2#define _uart_h_included_
3
4/*
5 * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
6 *
7 * include/asm-xtensa/xtensa/xt2000-uart.h -- NatSemi PC16552D DUART
8 * definitions
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive
12 * for more details.
13 *
14 * Copyright (C) 2002 Tensilica Inc.
15 */
16
17
18#include <xtensa/xt2000.h>
19
20
21/* 16550 UART DEVICE REGISTERS
22 The XT2000 board aligns each register to a 32-bit word but the UART device only uses
23 one byte of the word, which is the least-significant byte regardless of the
24 endianness of the core (ie. byte offset 0 for little-endian and 3 for big-endian).
25 So if using word accesses then endianness doesn't matter.
26 The macros provided here do that.
27*/
28struct uart_dev_s {
29 union {
30 unsigned int rxb; /* DLAB=0: receive buffer, read-only */
31 unsigned int txb; /* DLAB=0: transmit buffer, write-only */
32 unsigned int dll; /* DLAB=1: divisor, least-significant byte latch (was write-only?) */
33 } w0;
34 union {
35 unsigned int ier; /* DLAB=0: interrupt-enable register (was write-only?) */
36 unsigned int dlm; /* DLAB=1: divisor, most-significant byte latch (was write-only?) */
37 } w1;
38
39 union {
40 unsigned int isr; /* DLAB=0: interrupt status register, read-only */
41 unsigned int fcr; /* DLAB=0: FIFO control register, write-only */
42 unsigned int afr; /* DLAB=1: alternate function register */
43 } w2;
44
45 unsigned int lcr; /* line control-register, write-only */
46 unsigned int mcr; /* modem control-regsiter, write-only */
47 unsigned int lsr; /* line status register, read-only */
48 unsigned int msr; /* modem status register, read-only */
49 unsigned int scr; /* scratch regsiter, read/write */
50};
51
52#define _RXB(u) ((u)->w0.rxb)
53#define _TXB(u) ((u)->w0.txb)
54#define _DLL(u) ((u)->w0.dll)
55#define _IER(u) ((u)->w1.ier)
56#define _DLM(u) ((u)->w1.dlm)
57#define _ISR(u) ((u)->w2.isr)
58#define _FCR(u) ((u)->w2.fcr)
59#define _AFR(u) ((u)->w2.afr)
60#define _LCR(u) ((u)->lcr)
61#define _MCR(u) ((u)->mcr)
62#define _LSR(u) ((u)->lsr)
63#define _MSR(u) ((u)->msr)
64#define _SCR(u) ((u)->scr)
65
66typedef volatile struct uart_dev_s uart_dev_t;
67
68/* IER bits */
69#define RCVR_DATA_REG_INTENABLE 0x01
70#define XMIT_HOLD_REG_INTENABLE 0x02
71#define RCVR_STATUS_INTENABLE 0x04
72#define MODEM_STATUS_INTENABLE 0x08
73
74/* FCR bits */
75#define _FIFO_ENABLE 0x01
76#define RCVR_FIFO_RESET 0x02
77#define XMIT_FIFO_RESET 0x04
78#define DMA_MODE_SELECT 0x08
79#define RCVR_TRIGGER_LSB 0x40
80#define RCVR_TRIGGER_MSB 0x80
81
82/* AFR bits */
83#define AFR_CONC_WRITE 0x01
84#define AFR_BAUDOUT_SEL 0x02
85#define AFR_RXRDY_SEL 0x04
86
87/* ISR bits */
88#define INT_STATUS(r) ((r)&1)
89#define INT_PRIORITY(r) (((r)>>1)&0x7)
90
91/* LCR bits */
92#define WORD_LENGTH(n) (((n)-5)&0x3)
93#define STOP_BIT_ENABLE 0x04
94#define PARITY_ENABLE 0x08
95#define EVEN_PARITY 0x10
96#define FORCE_PARITY 0x20
97#define XMIT_BREAK 0x40
98#define DLAB_ENABLE 0x80
99
100/* MCR bits */
101#define _DTR 0x01
102#define _RTS 0x02
103#define _OP1 0x04
104#define _OP2 0x08
105#define LOOP_BACK 0x10
106
107/* LSR Bits */
108#define RCVR_DATA_READY 0x01
109#define OVERRUN_ERROR 0x02
110#define PARITY_ERROR 0x04
111#define FRAMING_ERROR 0x08
112#define BREAK_INTERRUPT 0x10
113#define XMIT_HOLD_EMPTY 0x20
114#define XMIT_EMPTY 0x40
115#define FIFO_ERROR 0x80
116#define RCVR_READY(u) (_LSR(u)&RCVR_DATA_READY)
117#define XMIT_READY(u) (_LSR(u)&XMIT_HOLD_EMPTY)
118
119/* MSR bits */
120#define _RDR 0x01
121#define DELTA_DSR 0x02
122#define DELTA_RI 0x04
123#define DELTA_CD 0x08
124#define _CTS 0x10
125#define _DSR 0x20
126#define _RI 0x40
127#define _CD 0x80
128
129/* prototypes */
130void uart_init( uart_dev_t *u, int bitrate );
131void uart_out( uart_dev_t *u, char c );
132void uart_puts( uart_dev_t *u, char *s );
133char uart_in( uart_dev_t *u );
134void uart_enable_rcvr_int( uart_dev_t *u );
135void uart_disable_rcvr_int( uart_dev_t *u );
136
137#ifdef DUART16552_1_VADDR
138/* DUART present. */
139#define DUART_1_BASE (*(uart_dev_t*)DUART16552_1_VADDR)
140#define DUART_2_BASE (*(uart_dev_t*)DUART16552_2_VADDR)
141#define UART1_PUTS(s) uart_puts( &DUART_1_BASE, s )
142#define UART2_PUTS(s) uart_puts( &DUART_2_BASE, s )
143#else
144/* DUART not configured, use dummy placeholders to allow compiles to work. */
145#define DUART_1_BASE (*(uart_dev_t*)0)
146#define DUART_2_BASE (*(uart_dev_t*)0)
147#define UART1_PUTS(s)
148#define UART2_PUTS(s)
149#endif
150
151/* Compute 16-bit divisor for baudrate generator, with rounding: */
152#define DUART_DIVISOR(crystal,speed) (((crystal)/16 + (speed)/2)/(speed))
153
154#endif /*_uart_h_included_*/
155
diff --git a/include/asm-xtensa/xtensa/xt2000.h b/include/asm-xtensa/xtensa/xt2000.h
new file mode 100644
index 000000000000..703a45002f8f
--- /dev/null
+++ b/include/asm-xtensa/xtensa/xt2000.h
@@ -0,0 +1,408 @@
1#ifndef _INC_XT2000_H_
2#define _INC_XT2000_H_
3
4/*
5 * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
6 *
7 * include/asm-xtensa/xtensa/xt2000.h - Definitions specific to the
8 * Tensilica XT2000 Emulation Board
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive
12 * for more details.
13 *
14 * Copyright (C) 2002 Tensilica Inc.
15 */
16
17
18#include <xtensa/config/core.h>
19#include <xtensa/config/system.h>
20
21
22/*
23 * Default assignment of XT2000 devices to external interrupts.
24 */
25
26/* Ethernet interrupt: */
27#ifdef XCHAL_EXTINT3_NUM
28#define SONIC83934_INTNUM XCHAL_EXTINT3_NUM
29#define SONIC83934_INTLEVEL XCHAL_EXTINT3_LEVEL
30#define SONIC83934_INTMASK XCHAL_EXTINT3_MASK
31#else
32#define SONIC83934_INTMASK 0
33#endif
34
35/* DUART channel 1 interrupt (P1 - console): */
36#ifdef XCHAL_EXTINT4_NUM
37#define DUART16552_1_INTNUM XCHAL_EXTINT4_NUM
38#define DUART16552_1_INTLEVEL XCHAL_EXTINT4_LEVEL
39#define DUART16552_1_INTMASK XCHAL_EXTINT4_MASK
40#else
41#define DUART16552_1_INTMASK 0
42#endif
43
44/* DUART channel 2 interrupt (P2 - 2nd serial port): */
45#ifdef XCHAL_EXTINT5_NUM
46#define DUART16552_2_INTNUM XCHAL_EXTINT5_NUM
47#define DUART16552_2_INTLEVEL XCHAL_EXTINT5_LEVEL
48#define DUART16552_2_INTMASK XCHAL_EXTINT5_MASK
49#else
50#define DUART16552_2_INTMASK 0
51#endif
52
53/* FPGA-combined PCI/etc interrupts: */
54#ifdef XCHAL_EXTINT6_NUM
55#define XT2000_FPGAPCI_INTNUM XCHAL_EXTINT6_NUM
56#define XT2000_FPGAPCI_INTLEVEL XCHAL_EXTINT6_LEVEL
57#define XT2000_FPGAPCI_INTMASK XCHAL_EXTINT6_MASK
58#else
59#define XT2000_FPGAPCI_INTMASK 0
60#endif
61
62
63
64/*
65 * Device addresses.
66 *
67 * Note: for endianness-independence, use 32-bit loads and stores for all
68 * register accesses to Ethernet, DUART and LED devices. Undefined bits
69 * may need to be masked out if needed when reading if the actual register
70 * size is smaller than 32 bits.
71 *
72 * Note: XT2000 bus byte lanes are defined in terms of msbyte and lsbyte
73 * relative to the processor. So 32-bit registers are accessed consistently
74 * from both big and little endian processors. However, this means byte
75 * sequences are not consistent between big and little endian processors.
76 * This is fine for RAM, and for ROM if ROM is created for a specific
77 * processor (and thus has correct byte sequences). However this may be
78 * unexpected for Flash, which might contain a file-system that one wants
79 * to use for multiple processor configurations (eg. the Flash might contain
80 * the Ethernet card's address, endianness-independent application data, etc).
81 * That is, byte sequences written in Flash by a core of a given endianness
82 * will be byte-swapped when seen by a core of the other endianness.
83 * Someone implementing an endianness-independent Flash file system will
84 * likely handle this byte-swapping issue in the Flash driver software.
85 */
86
87#define DUART16552_XTAL_FREQ 18432000 /* crystal frequency in Hz */
88#define XTBOARD_FLASH_MAXSIZE 0x4000000 /* 64 MB (max; depends on what is socketed!) */
89#define XTBOARD_EPROM_MAXSIZE 0x0400000 /* 4 MB (max; depends on what is socketed!) */
90#define XTBOARD_EEPROM_MAXSIZE 0x0080000 /* 512 kB (max; depends on what is socketed!) */
91#define XTBOARD_ASRAM_SIZE 0x0100000 /* 1 MB */
92#define XTBOARD_PCI_MEM_SIZE 0x8000000 /* 128 MB (allocated) */
93#define XTBOARD_PCI_IO_SIZE 0x1000000 /* 16 MB (allocated) */
94
95#ifdef XSHAL_IOBLOCK_BYPASS_PADDR
96/* PCI memory space: */
97# define XTBOARD_PCI_MEM_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0000000)
98/* Socketed Flash (eg. 2 x 16-bit devices): */
99# define XTBOARD_FLASH_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x8000000)
100/* PCI I/O space: */
101# define XTBOARD_PCI_IO_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0xC000000)
102/* V3 PCI interface chip register/config space: */
103# define XTBOARD_V3PCI_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0xD000000)
104/* Bus Interface registers: */
105# define XTBOARD_BUSINT_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0xD010000)
106/* FPGA registers: */
107# define XT2000_FPGAREGS_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0xD020000)
108/* SONIC SN83934 Ethernet controller/transceiver: */
109# define SONIC83934_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0xD030000)
110/* 8-character bitmapped LED display: */
111# define XTBOARD_LED_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0xD040000)
112/* National-Semi PC16552D DUART: */
113# define DUART16552_1_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0xD050020) /* channel 1 (P1 - console) */
114# define DUART16552_2_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0xD050000) /* channel 2 (P2) */
115/* Asynchronous Static RAM: */
116# define XTBOARD_ASRAM_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0xD400000)
117/* 8-bit EEPROM: */
118# define XTBOARD_EEPROM_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0xD600000)
119/* 2 x 16-bit EPROMs: */
120# define XTBOARD_EPROM_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0xD800000)
121#endif /* XSHAL_IOBLOCK_BYPASS_PADDR */
122
123/* These devices might be accessed cached: */
124#ifdef XSHAL_IOBLOCK_CACHED_PADDR
125# define XTBOARD_PCI_MEM_CACHED_PADDR (XSHAL_IOBLOCK_CACHED_PADDR+0x0000000)
126# define XTBOARD_FLASH_CACHED_PADDR (XSHAL_IOBLOCK_CACHED_PADDR+0x8000000)
127# define XTBOARD_ASRAM_CACHED_PADDR (XSHAL_IOBLOCK_CACHED_PADDR+0xD400000)
128# define XTBOARD_EEPROM_CACHED_PADDR (XSHAL_IOBLOCK_CACHED_PADDR+0xD600000)
129# define XTBOARD_EPROM_CACHED_PADDR (XSHAL_IOBLOCK_CACHED_PADDR+0xD800000)
130#endif /* XSHAL_IOBLOCK_CACHED_PADDR */
131
132
133/*** Same thing over again, this time with virtual addresses: ***/
134
135#ifdef XSHAL_IOBLOCK_BYPASS_VADDR
136/* PCI memory space: */
137# define XTBOARD_PCI_MEM_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0000000)
138/* Socketed Flash (eg. 2 x 16-bit devices): */
139# define XTBOARD_FLASH_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x8000000)
140/* PCI I/O space: */
141# define XTBOARD_PCI_IO_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0xC000000)
142/* V3 PCI interface chip register/config space: */
143# define XTBOARD_V3PCI_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0xD000000)
144/* Bus Interface registers: */
145# define XTBOARD_BUSINT_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0xD010000)
146/* FPGA registers: */
147# define XT2000_FPGAREGS_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0xD020000)
148/* SONIC SN83934 Ethernet controller/transceiver: */
149# define SONIC83934_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0xD030000)
150/* 8-character bitmapped LED display: */
151# define XTBOARD_LED_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0xD040000)
152/* National-Semi PC16552D DUART: */
153# define DUART16552_1_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0xD050020) /* channel 1 (P1 - console) */
154# define DUART16552_2_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0xD050000) /* channel 2 (P2) */
155/* Asynchronous Static RAM: */
156# define XTBOARD_ASRAM_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0xD400000)
157/* 8-bit EEPROM: */
158# define XTBOARD_EEPROM_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0xD600000)
159/* 2 x 16-bit EPROMs: */
160# define XTBOARD_EPROM_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0xD800000)
161#endif /* XSHAL_IOBLOCK_BYPASS_VADDR */
162
163/* These devices might be accessed cached: */
164#ifdef XSHAL_IOBLOCK_CACHED_VADDR
165# define XTBOARD_PCI_MEM_CACHED_VADDR (XSHAL_IOBLOCK_CACHED_VADDR+0x0000000)
166# define XTBOARD_FLASH_CACHED_VADDR (XSHAL_IOBLOCK_CACHED_VADDR+0x8000000)
167# define XTBOARD_ASRAM_CACHED_VADDR (XSHAL_IOBLOCK_CACHED_VADDR+0xD400000)
168# define XTBOARD_EEPROM_CACHED_VADDR (XSHAL_IOBLOCK_CACHED_VADDR+0xD600000)
169# define XTBOARD_EPROM_CACHED_VADDR (XSHAL_IOBLOCK_CACHED_VADDR+0xD800000)
170#endif /* XSHAL_IOBLOCK_CACHED_VADDR */
171
172
173/* System ROM: */
174#define XTBOARD_ROM_SIZE XSHAL_ROM_SIZE
175#ifdef XSHAL_ROM_VADDR
176#define XTBOARD_ROM_VADDR XSHAL_ROM_VADDR
177#endif
178#ifdef XSHAL_ROM_PADDR
179#define XTBOARD_ROM_PADDR XSHAL_ROM_PADDR
180#endif
181
182/* System RAM: */
183#define XTBOARD_RAM_SIZE XSHAL_RAM_SIZE
184#ifdef XSHAL_RAM_VADDR
185#define XTBOARD_RAM_VADDR XSHAL_RAM_VADDR
186#endif
187#ifdef XSHAL_RAM_PADDR
188#define XTBOARD_RAM_PADDR XSHAL_RAM_PADDR
189#endif
190#define XTBOARD_RAM_BYPASS_VADDR XSHAL_RAM_BYPASS_VADDR
191#define XTBOARD_RAM_BYPASS_PADDR XSHAL_RAM_BYPASS_PADDR
192
193
194
195/*
196 * Things that depend on device addresses.
197 */
198
199
200#define XTBOARD_CACHEATTR_WRITEBACK XSHAL_XT2000_CACHEATTR_WRITEBACK
201#define XTBOARD_CACHEATTR_WRITEALLOC XSHAL_XT2000_CACHEATTR_WRITEALLOC
202#define XTBOARD_CACHEATTR_WRITETHRU XSHAL_XT2000_CACHEATTR_WRITETHRU
203#define XTBOARD_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS
204#define XTBOARD_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_DEFAULT
205
206#define XTBOARD_BUSINT_PIPE_REGIONS XSHAL_XT2000_PIPE_REGIONS
207#define XTBOARD_BUSINT_SDRAM_REGIONS XSHAL_XT2000_SDRAM_REGIONS
208
209
210
211/*
212 * BusLogic (FPGA) registers.
213 * All these registers are normally accessed using 32-bit loads/stores.
214 */
215
216/* Register offsets: */
217#define XT2000_DATECD_OFS 0x00 /* date code (read-only) */
218#define XT2000_STSREG_OFS 0x04 /* status (read-only) */
219#define XT2000_SYSLED_OFS 0x08 /* system LED */
220#define XT2000_WRPROT_OFS 0x0C /* write protect */
221#define XT2000_SWRST_OFS 0x10 /* software reset */
222#define XT2000_SYSRST_OFS 0x14 /* system (peripherals) reset */
223#define XT2000_IMASK_OFS 0x18 /* interrupt mask */
224#define XT2000_ISTAT_OFS 0x1C /* interrupt status */
225#define XT2000_V3CFG_OFS 0x20 /* V3 config (V320 PCI) */
226
227/* Physical register addresses: */
228#ifdef XT2000_FPGAREGS_PADDR
229#define XT2000_DATECD_PADDR (XT2000_FPGAREGS_PADDR+XT2000_DATECD_OFS)
230#define XT2000_STSREG_PADDR (XT2000_FPGAREGS_PADDR+XT2000_STSREG_OFS)
231#define XT2000_SYSLED_PADDR (XT2000_FPGAREGS_PADDR+XT2000_SYSLED_OFS)
232#define XT2000_WRPROT_PADDR (XT2000_FPGAREGS_PADDR+XT2000_WRPROT_OFS)
233#define XT2000_SWRST_PADDR (XT2000_FPGAREGS_PADDR+XT2000_SWRST_OFS)
234#define XT2000_SYSRST_PADDR (XT2000_FPGAREGS_PADDR+XT2000_SYSRST_OFS)
235#define XT2000_IMASK_PADDR (XT2000_FPGAREGS_PADDR+XT2000_IMASK_OFS)
236#define XT2000_ISTAT_PADDR (XT2000_FPGAREGS_PADDR+XT2000_ISTAT_OFS)
237#define XT2000_V3CFG_PADDR (XT2000_FPGAREGS_PADDR+XT2000_V3CFG_OFS)
238#endif
239
240/* Virtual register addresses: */
241#ifdef XT2000_FPGAREGS_VADDR
242#define XT2000_DATECD_VADDR (XT2000_FPGAREGS_VADDR+XT2000_DATECD_OFS)
243#define XT2000_STSREG_VADDR (XT2000_FPGAREGS_VADDR+XT2000_STSREG_OFS)
244#define XT2000_SYSLED_VADDR (XT2000_FPGAREGS_VADDR+XT2000_SYSLED_OFS)
245#define XT2000_WRPROT_VADDR (XT2000_FPGAREGS_VADDR+XT2000_WRPROT_OFS)
246#define XT2000_SWRST_VADDR (XT2000_FPGAREGS_VADDR+XT2000_SWRST_OFS)
247#define XT2000_SYSRST_VADDR (XT2000_FPGAREGS_VADDR+XT2000_SYSRST_OFS)
248#define XT2000_IMASK_VADDR (XT2000_FPGAREGS_VADDR+XT2000_IMASK_OFS)
249#define XT2000_ISTAT_VADDR (XT2000_FPGAREGS_VADDR+XT2000_ISTAT_OFS)
250#define XT2000_V3CFG_VADDR (XT2000_FPGAREGS_VADDR+XT2000_V3CFG_OFS)
251/* Register access (for C code): */
252#define XT2000_DATECD_REG (*(volatile unsigned*) XT2000_DATECD_VADDR)
253#define XT2000_STSREG_REG (*(volatile unsigned*) XT2000_STSREG_VADDR)
254#define XT2000_SYSLED_REG (*(volatile unsigned*) XT2000_SYSLED_VADDR)
255#define XT2000_WRPROT_REG (*(volatile unsigned*) XT2000_WRPROT_VADDR)
256#define XT2000_SWRST_REG (*(volatile unsigned*) XT2000_SWRST_VADDR)
257#define XT2000_SYSRST_REG (*(volatile unsigned*) XT2000_SYSRST_VADDR)
258#define XT2000_IMASK_REG (*(volatile unsigned*) XT2000_IMASK_VADDR)
259#define XT2000_ISTAT_REG (*(volatile unsigned*) XT2000_ISTAT_VADDR)
260#define XT2000_V3CFG_REG (*(volatile unsigned*) XT2000_V3CFG_VADDR)
261#endif
262
263/* DATECD (date code) bit fields: */
264
265/* BCD-coded month (01..12): */
266#define XT2000_DATECD_MONTH_SHIFT 24
267#define XT2000_DATECD_MONTH_BITS 8
268#define XT2000_DATECD_MONTH_MASK 0xFF000000
269/* BCD-coded day (01..31): */
270#define XT2000_DATECD_DAY_SHIFT 16
271#define XT2000_DATECD_DAY_BITS 8
272#define XT2000_DATECD_DAY_MASK 0x00FF0000
273/* BCD-coded year (2001..9999): */
274#define XT2000_DATECD_YEAR_SHIFT 0
275#define XT2000_DATECD_YEAR_BITS 16
276#define XT2000_DATECD_YEAR_MASK 0x0000FFFF
277
278/* STSREG (status) bit fields: */
279
280/* Switch SW3 setting bit fields (0=off/up, 1=on/down): */
281#define XT2000_STSREG_SW3_SHIFT 0
282#define XT2000_STSREG_SW3_BITS 4
283#define XT2000_STSREG_SW3_MASK 0x0000000F
284/* Boot-select bits of switch SW3: */
285#define XT2000_STSREG_BOOTSEL_SHIFT 0
286#define XT2000_STSREG_BOOTSEL_BITS 2
287#define XT2000_STSREG_BOOTSEL_MASK 0x00000003
288/* Boot-select values: */
289#define XT2000_STSREG_BOOTSEL_FLASH 0
290#define XT2000_STSREG_BOOTSEL_EPROM16 1
291#define XT2000_STSREG_BOOTSEL_PROM8 2
292#define XT2000_STSREG_BOOTSEL_ASRAM 3
293/* User-defined bits of switch SW3: */
294#define XT2000_STSREG_SW3_2_SHIFT 2
295#define XT2000_STSREG_SW3_2_MASK 0x00000004
296#define XT2000_STSREG_SW3_3_SHIFT 3
297#define XT2000_STSREG_SW3_3_MASK 0x00000008
298
299/* SYSLED (system LED) bit fields: */
300
301/* LED control bit (0=off, 1=on): */
302#define XT2000_SYSLED_LEDON_SHIFT 0
303#define XT2000_SYSLED_LEDON_MASK 0x00000001
304
305/* WRPROT (write protect) bit fields (0=writable, 1=write-protected [default]): */
306
307/* Flash write protect: */
308#define XT2000_WRPROT_FLWP_SHIFT 0
309#define XT2000_WRPROT_FLWP_MASK 0x00000001
310/* Reserved but present write protect bits: */
311#define XT2000_WRPROT_WRP_SHIFT 1
312#define XT2000_WRPROT_WRP_BITS 7
313#define XT2000_WRPROT_WRP_MASK 0x000000FE
314
315/* SWRST (software reset; allows s/w to generate power-on equivalent reset): */
316
317/* Software reset bits: */
318#define XT2000_SWRST_SWR_SHIFT 0
319#define XT2000_SWRST_SWR_BITS 16
320#define XT2000_SWRST_SWR_MASK 0x0000FFFF
321/* Software reset value -- writing this value resets the board: */
322#define XT2000_SWRST_RESETVALUE 0x0000DEAD
323
324/* SYSRST (system reset; controls reset of individual peripherals): */
325
326/* All-device reset: */
327#define XT2000_SYSRST_ALL_SHIFT 0
328#define XT2000_SYSRST_ALL_BITS 4
329#define XT2000_SYSRST_ALL_MASK 0x0000000F
330/* HDSP-2534 LED display reset (1=reset, 0=nothing): */
331#define XT2000_SYSRST_LED_SHIFT 0
332#define XT2000_SYSRST_LED_MASK 0x00000001
333/* Sonic DP83934 Ethernet controller reset (1=reset, 0=nothing): */
334#define XT2000_SYSRST_SONIC_SHIFT 1
335#define XT2000_SYSRST_SONIC_MASK 0x00000002
336/* DP16552 DUART reset (1=reset, 0=nothing): */
337#define XT2000_SYSRST_DUART_SHIFT 2
338#define XT2000_SYSRST_DUART_MASK 0x00000004
339/* V3 V320 PCI bridge controller reset (1=reset, 0=nothing): */
340#define XT2000_SYSRST_V3_SHIFT 3
341#define XT2000_SYSRST_V3_MASK 0x00000008
342
343/* IMASK (interrupt mask; 0=disable, 1=enable): */
344/* ISTAT (interrupt status; 0=inactive, 1=pending): */
345
346/* PCI INTP interrupt: */
347#define XT2000_INTMUX_PCI_INTP_SHIFT 2
348#define XT2000_INTMUX_PCI_INTP_MASK 0x00000004
349/* PCI INTS interrupt: */
350#define XT2000_INTMUX_PCI_INTS_SHIFT 3
351#define XT2000_INTMUX_PCI_INTS_MASK 0x00000008
352/* PCI INTD interrupt: */
353#define XT2000_INTMUX_PCI_INTD_SHIFT 4
354#define XT2000_INTMUX_PCI_INTD_MASK 0x00000010
355/* V320 PCI controller interrupt: */
356#define XT2000_INTMUX_V3_SHIFT 5
357#define XT2000_INTMUX_V3_MASK 0x00000020
358/* PCI ENUM interrupt: */
359#define XT2000_INTMUX_PCI_ENUM_SHIFT 6
360#define XT2000_INTMUX_PCI_ENUM_MASK 0x00000040
361/* PCI DEG interrupt: */
362#define XT2000_INTMUX_PCI_DEG_SHIFT 7
363#define XT2000_INTMUX_PCI_DEG_MASK 0x00000080
364
365/* V3CFG (V3 config, V320 PCI controller): */
366
367/* V3 address control (0=pass-thru, 1=V3 address bits 31:28 set to 4'b0001 [default]): */
368#define XT2000_V3CFG_V3ADC_SHIFT 0
369#define XT2000_V3CFG_V3ADC_MASK 0x00000001
370
371/* I2C Devices */
372
373#define XT2000_I2C_RTC_ID 0x68
374#define XT2000_I2C_NVRAM0_ID 0x56 /* 1st 256 byte block */
375#define XT2000_I2C_NVRAM1_ID 0x57 /* 2nd 256 byte block */
376
377/* NVRAM Board Info structure: */
378
379#define XT2000_NVRAM_SIZE 512
380
381#define XT2000_NVRAM_BINFO_START 0x100
382#define XT2000_NVRAM_BINFO_SIZE 0x20
383#define XT2000_NVRAM_BINFO_VERSION 0x10 /* version 1.0 */
384#if 0
385#define XT2000_NVRAM_BINFO_VERSION_OFFSET 0x00
386#define XT2000_NVRAM_BINFO_VERSION_SIZE 0x1
387#define XT2000_NVRAM_BINFO_ETH_ADDR_OFFSET 0x02
388#define XT2000_NVRAM_BINFO_ETH_ADDR_SIZE 0x6
389#define XT2000_NVRAM_BINFO_SN_OFFSET 0x10
390#define XT2000_NVRAM_BINFO_SN_SIZE 0xE
391#define XT2000_NVRAM_BINFO_CRC_OFFSET 0x1E
392#define XT2000_NVRAM_BINFO_CRC_SIZE 0x2
393#endif /*0*/
394
395#if !defined(__ASSEMBLY__) && !defined(_NOCLANGUAGE)
396typedef struct xt2000_nvram_binfo {
397 unsigned char version;
398 unsigned char reserved1;
399 unsigned char eth_addr[6];
400 unsigned char reserved8[8];
401 unsigned char serialno[14];
402 unsigned char crc[2]; /* 16-bit CRC */
403} xt2000_nvram_binfo;
404#endif /*!__ASSEMBLY__ && !_NOCLANGUAGE*/
405
406
407#endif /*_INC_XT2000_H_*/
408
diff --git a/include/asm-xtensa/xtensa/xtboard.h b/include/asm-xtensa/xtensa/xtboard.h
new file mode 100644
index 000000000000..22469c175307
--- /dev/null
+++ b/include/asm-xtensa/xtensa/xtboard.h
@@ -0,0 +1,120 @@
1#ifndef _xtboard_h_included_
2#define _xtboard_h_included_
3
4/*
5 * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
6 *
7 * xtboard.h -- Routines for getting useful information from the board.
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 *
13 * Copyright (C) 2002 Tensilica Inc.
14 */
15
16
17#include <xtensa/xt2000.h>
18
19#define XTBOARD_RTC_ERROR -1
20#define XTBOARD_RTC_STOPPED -2
21
22
23/* xt2000-i2cdev.c: */
24typedef void XtboardDelayFunc( unsigned );
25extern XtboardDelayFunc* xtboard_set_nsdelay_func( XtboardDelayFunc *delay_fn );
26extern int xtboard_i2c_read (unsigned id, unsigned char *buf, unsigned addr, unsigned size);
27extern int xtboard_i2c_write(unsigned id, unsigned char *buf, unsigned addr, unsigned size);
28extern int xtboard_i2c_wait_nvram_ack(unsigned id, unsigned swtimer);
29
30/* xtboard.c: */
31extern int xtboard_nvram_read (unsigned addr, unsigned len, unsigned char *buf);
32extern int xtboard_nvram_write(unsigned addr, unsigned len, unsigned char *buf);
33extern int xtboard_nvram_binfo_read (xt2000_nvram_binfo *buf);
34extern int xtboard_nvram_binfo_write(xt2000_nvram_binfo *buf);
35extern int xtboard_nvram_binfo_valid(xt2000_nvram_binfo *buf);
36extern int xtboard_ethermac_get(unsigned char *buf);
37extern int xtboard_ethermac_set(unsigned char *buf);
38
39/*+*----------------------------------------------------------------------------
40/ Function: xtboard_get_rtc_time
41/
42/ Description: Get time stored in real-time clock.
43/
44/ Returns: time in seconds stored in real-time clock.
45/-**----------------------------------------------------------------------------*/
46
47extern unsigned xtboard_get_rtc_time(void);
48
49/*+*----------------------------------------------------------------------------
50/ Function: xtboard_set_rtc_time
51/
52/ Description: Set time stored in real-time clock.
53/
54/ Parameters: time -- time in seconds to store to real-time clock
55/
56/ Returns: 0 on success, xtboard_i2c_write() error code otherwise.
57/-**----------------------------------------------------------------------------*/
58
59extern int xtboard_set_rtc_time(unsigned time);
60
61
62/* xtfreq.c: */
63/*+*----------------------------------------------------------------------------
64/ Function: xtboard_measure_sys_clk
65/
66/ Description: Get frequency of system clock.
67/
68/ Parameters: none
69/
70/ Returns: frequency of system clock.
71/-**----------------------------------------------------------------------------*/
72
73extern unsigned xtboard_measure_sys_clk(void);
74
75
76#if 0 /* old stuff from xtboard.c: */
77
78/*+*----------------------------------------------------------------------------
79/ Function: xtboard_nvram valid
80/
81/ Description: Determines if data in NVRAM is valid.
82/
83/ Parameters: delay -- 10us delay function
84/
85/ Returns: 1 if NVRAM is valid, 0 otherwise
86/-**----------------------------------------------------------------------------*/
87
88extern unsigned xtboard_nvram_valid(void (*delay)( void ));
89
90/*+*----------------------------------------------------------------------------
91/ Function: xtboard_get_nvram_contents
92/
93/ Description: Returns contents of NVRAM.
94/
95/ Parameters: buf -- buffer to NVRAM contents.
96/ delay -- 10us delay function
97/
98/ Returns: 1 if NVRAM is valid, 0 otherwise
99/-**----------------------------------------------------------------------------*/
100
101extern unsigned xtboard_get_nvram_contents(unsigned char *buf, void (*delay)( void ));
102
103/*+*----------------------------------------------------------------------------
104/ Function: xtboard_get_ether_addr
105/
106/ Description: Returns ethernet address of board.
107/
108/ Parameters: buf -- buffer to store ethernet address
109/ delay -- 10us delay function
110/
111/ Returns: nothing.
112/-**----------------------------------------------------------------------------*/
113
114extern void xtboard_get_ether_addr(unsigned char *buf, void (*delay)( void ));
115
116#endif /*0*/
117
118
119#endif /*_xtboard_h_included_*/
120
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-23 00:38:30 -0400