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-rw-r--r--Documentation/devicetree/bindings/dma/snps-dma.txt17
-rw-r--r--arch/arm/include/asm/hardware/pl080.h2
-rw-r--r--arch/arm/mach-at91/at91sam9g45_devices.c1
-rw-r--r--arch/arm/mach-at91/include/mach/at_hdmac.h26
-rw-r--r--drivers/dma/amba-pl08x.c52
-rw-r--r--drivers/dma/at_hdmac.c15
-rw-r--r--drivers/dma/at_hdmac_regs.h21
-rw-r--r--drivers/dma/coh901318.c2
-rw-r--r--drivers/dma/coh901318_lli.c4
-rw-r--r--drivers/dma/dw_dmac.c26
-rw-r--r--drivers/dma/imx-dma.c12
-rw-r--r--drivers/dma/imx-sdma.c68
-rw-r--r--drivers/dma/intel_mid_dma.c8
-rw-r--r--drivers/dma/mxs-dma.c6
-rw-r--r--drivers/dma/pch_dma.c2
-rw-r--r--drivers/dma/pl330.c1
-rw-r--r--drivers/dma/ste_dma40.c2
-rw-r--r--include/linux/amba/pl08x.h3
-rw-r--r--include/linux/dmaengine.h6
19 files changed, 169 insertions, 105 deletions
diff --git a/Documentation/devicetree/bindings/dma/snps-dma.txt b/Documentation/devicetree/bindings/dma/snps-dma.txt
new file mode 100644
index 000000000000..c0d85dbcada5
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/snps-dma.txt
@@ -0,0 +1,17 @@
1* Synopsys Designware DMA Controller
2
3Required properties:
4- compatible: "snps,dma-spear1340"
5- reg: Address range of the DMAC registers
6- interrupt-parent: Should be the phandle for the interrupt controller
7 that services interrupts for this device
8- interrupt: Should contain the DMAC interrupt number
9
10Example:
11
12 dma@fc000000 {
13 compatible = "snps,dma-spear1340";
14 reg = <0xfc000000 0x1000>;
15 interrupt-parent = <&vic1>;
16 interrupts = <12>;
17 };
diff --git a/arch/arm/include/asm/hardware/pl080.h b/arch/arm/include/asm/hardware/pl080.h
index 33c78d7af2e1..4eea2107214b 100644
--- a/arch/arm/include/asm/hardware/pl080.h
+++ b/arch/arm/include/asm/hardware/pl080.h
@@ -102,6 +102,8 @@
102#define PL080_WIDTH_16BIT (0x1) 102#define PL080_WIDTH_16BIT (0x1)
103#define PL080_WIDTH_32BIT (0x2) 103#define PL080_WIDTH_32BIT (0x2)
104 104
105#define PL080N_CONFIG_ITPROT (1 << 20)
106#define PL080N_CONFIG_SECPROT (1 << 19)
105#define PL080_CONFIG_HALT (1 << 18) 107#define PL080_CONFIG_HALT (1 << 18)
106#define PL080_CONFIG_ACTIVE (1 << 17) /* RO */ 108#define PL080_CONFIG_ACTIVE (1 << 17) /* RO */
107#define PL080_CONFIG_LOCK (1 << 16) 109#define PL080_CONFIG_LOCK (1 << 16)
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index f6747246d649..933fc9afe7d0 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -436,7 +436,6 @@ void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
436 atslave->dma_dev = &at_hdmac_device.dev; 436 atslave->dma_dev = &at_hdmac_device.dev;
437 atslave->cfg = ATC_FIFOCFG_HALFFIFO 437 atslave->cfg = ATC_FIFOCFG_HALFFIFO
438 | ATC_SRC_H2SEL_HW | ATC_DST_H2SEL_HW; 438 | ATC_SRC_H2SEL_HW | ATC_DST_H2SEL_HW;
439 atslave->ctrla = ATC_SCSIZE_16 | ATC_DCSIZE_16;
440 if (mmc_id == 0) /* MCI0 */ 439 if (mmc_id == 0) /* MCI0 */
441 atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI0) 440 atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI0)
442 | ATC_DST_PER(AT_DMA_ID_MCI0); 441 | ATC_DST_PER(AT_DMA_ID_MCI0);
diff --git a/arch/arm/mach-at91/include/mach/at_hdmac.h b/arch/arm/mach-at91/include/mach/at_hdmac.h
index fff48d1a0f4e..cab0997be3de 100644
--- a/arch/arm/mach-at91/include/mach/at_hdmac.h
+++ b/arch/arm/mach-at91/include/mach/at_hdmac.h
@@ -26,18 +26,11 @@ struct at_dma_platform_data {
26/** 26/**
27 * struct at_dma_slave - Controller-specific information about a slave 27 * struct at_dma_slave - Controller-specific information about a slave
28 * @dma_dev: required DMA master device 28 * @dma_dev: required DMA master device
29 * @tx_reg: physical address of data register used for
30 * memory-to-peripheral transfers
31 * @rx_reg: physical address of data register used for
32 * peripheral-to-memory transfers
33 * @reg_width: peripheral register width
34 * @cfg: Platform-specific initializer for the CFG register 29 * @cfg: Platform-specific initializer for the CFG register
35 * @ctrla: Platform-specific initializer for the CTRLA register
36 */ 30 */
37struct at_dma_slave { 31struct at_dma_slave {
38 struct device *dma_dev; 32 struct device *dma_dev;
39 u32 cfg; 33 u32 cfg;
40 u32 ctrla;
41}; 34};
42 35
43 36
@@ -64,24 +57,5 @@ struct at_dma_slave {
64#define ATC_FIFOCFG_HALFFIFO (0x1 << 28) 57#define ATC_FIFOCFG_HALFFIFO (0x1 << 28)
65#define ATC_FIFOCFG_ENOUGHSPACE (0x2 << 28) 58#define ATC_FIFOCFG_ENOUGHSPACE (0x2 << 28)
66 59
67/* Platform-configurable bits in CTRLA */
68#define ATC_SCSIZE_MASK (0x7 << 16) /* Source Chunk Transfer Size */
69#define ATC_SCSIZE_1 (0x0 << 16)
70#define ATC_SCSIZE_4 (0x1 << 16)
71#define ATC_SCSIZE_8 (0x2 << 16)
72#define ATC_SCSIZE_16 (0x3 << 16)
73#define ATC_SCSIZE_32 (0x4 << 16)
74#define ATC_SCSIZE_64 (0x5 << 16)
75#define ATC_SCSIZE_128 (0x6 << 16)
76#define ATC_SCSIZE_256 (0x7 << 16)
77#define ATC_DCSIZE_MASK (0x7 << 20) /* Destination Chunk Transfer Size */
78#define ATC_DCSIZE_1 (0x0 << 20)
79#define ATC_DCSIZE_4 (0x1 << 20)
80#define ATC_DCSIZE_8 (0x2 << 20)
81#define ATC_DCSIZE_16 (0x3 << 20)
82#define ATC_DCSIZE_32 (0x4 << 20)
83#define ATC_DCSIZE_64 (0x5 << 20)
84#define ATC_DCSIZE_128 (0x6 << 20)
85#define ATC_DCSIZE_256 (0x7 << 20)
86 60
87#endif /* AT_HDMAC_H */ 61#endif /* AT_HDMAC_H */
diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index 3d704abd7912..49ecbbb8932d 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -95,10 +95,14 @@ static struct amba_driver pl08x_amba_driver;
95 * struct vendor_data - vendor-specific config parameters for PL08x derivatives 95 * struct vendor_data - vendor-specific config parameters for PL08x derivatives
96 * @channels: the number of channels available in this variant 96 * @channels: the number of channels available in this variant
97 * @dualmaster: whether this version supports dual AHB masters or not. 97 * @dualmaster: whether this version supports dual AHB masters or not.
98 * @nomadik: whether the channels have Nomadik security extension bits
99 * that need to be checked for permission before use and some registers are
100 * missing
98 */ 101 */
99struct vendor_data { 102struct vendor_data {
100 u8 channels; 103 u8 channels;
101 bool dualmaster; 104 bool dualmaster;
105 bool nomadik;
102}; 106};
103 107
104/* 108/*
@@ -385,7 +389,7 @@ pl08x_get_phy_channel(struct pl08x_driver_data *pl08x,
385 389
386 spin_lock_irqsave(&ch->lock, flags); 390 spin_lock_irqsave(&ch->lock, flags);
387 391
388 if (!ch->serving) { 392 if (!ch->locked && !ch->serving) {
389 ch->serving = virt_chan; 393 ch->serving = virt_chan;
390 ch->signal = -1; 394 ch->signal = -1;
391 spin_unlock_irqrestore(&ch->lock, flags); 395 spin_unlock_irqrestore(&ch->lock, flags);
@@ -1324,7 +1328,7 @@ static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
1324 int ret, tmp; 1328 int ret, tmp;
1325 1329
1326 dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n", 1330 dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n",
1327 __func__, sgl->length, plchan->name); 1331 __func__, sg_dma_len(sgl), plchan->name);
1328 1332
1329 txd = pl08x_get_txd(plchan, flags); 1333 txd = pl08x_get_txd(plchan, flags);
1330 if (!txd) { 1334 if (!txd) {
@@ -1378,11 +1382,11 @@ static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
1378 1382
1379 dsg->len = sg_dma_len(sg); 1383 dsg->len = sg_dma_len(sg);
1380 if (direction == DMA_MEM_TO_DEV) { 1384 if (direction == DMA_MEM_TO_DEV) {
1381 dsg->src_addr = sg_phys(sg); 1385 dsg->src_addr = sg_dma_address(sg);
1382 dsg->dst_addr = slave_addr; 1386 dsg->dst_addr = slave_addr;
1383 } else { 1387 } else {
1384 dsg->src_addr = slave_addr; 1388 dsg->src_addr = slave_addr;
1385 dsg->dst_addr = sg_phys(sg); 1389 dsg->dst_addr = sg_dma_address(sg);
1386 } 1390 }
1387 } 1391 }
1388 1392
@@ -1484,6 +1488,9 @@ bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
1484 */ 1488 */
1485static void pl08x_ensure_on(struct pl08x_driver_data *pl08x) 1489static void pl08x_ensure_on(struct pl08x_driver_data *pl08x)
1486{ 1490{
1491 /* The Nomadik variant does not have the config register */
1492 if (pl08x->vd->nomadik)
1493 return;
1487 writel(PL080_CONFIG_ENABLE, pl08x->base + PL080_CONFIG); 1494 writel(PL080_CONFIG_ENABLE, pl08x->base + PL080_CONFIG);
1488} 1495}
1489 1496
@@ -1616,7 +1623,7 @@ static irqreturn_t pl08x_irq(int irq, void *dev)
1616 __func__, err); 1623 __func__, err);
1617 writel(err, pl08x->base + PL080_ERR_CLEAR); 1624 writel(err, pl08x->base + PL080_ERR_CLEAR);
1618 } 1625 }
1619 tc = readl(pl08x->base + PL080_INT_STATUS); 1626 tc = readl(pl08x->base + PL080_TC_STATUS);
1620 if (tc) 1627 if (tc)
1621 writel(tc, pl08x->base + PL080_TC_CLEAR); 1628 writel(tc, pl08x->base + PL080_TC_CLEAR);
1622 1629
@@ -1773,8 +1780,10 @@ static int pl08x_debugfs_show(struct seq_file *s, void *data)
1773 spin_lock_irqsave(&ch->lock, flags); 1780 spin_lock_irqsave(&ch->lock, flags);
1774 virt_chan = ch->serving; 1781 virt_chan = ch->serving;
1775 1782
1776 seq_printf(s, "%d\t\t%s\n", 1783 seq_printf(s, "%d\t\t%s%s\n",
1777 ch->id, virt_chan ? virt_chan->name : "(none)"); 1784 ch->id,
1785 virt_chan ? virt_chan->name : "(none)",
1786 ch->locked ? " LOCKED" : "");
1778 1787
1779 spin_unlock_irqrestore(&ch->lock, flags); 1788 spin_unlock_irqrestore(&ch->lock, flags);
1780 } 1789 }
@@ -1918,7 +1927,7 @@ static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
1918 } 1927 }
1919 1928
1920 /* Initialize physical channels */ 1929 /* Initialize physical channels */
1921 pl08x->phy_chans = kmalloc((vd->channels * sizeof(*pl08x->phy_chans)), 1930 pl08x->phy_chans = kzalloc((vd->channels * sizeof(*pl08x->phy_chans)),
1922 GFP_KERNEL); 1931 GFP_KERNEL);
1923 if (!pl08x->phy_chans) { 1932 if (!pl08x->phy_chans) {
1924 dev_err(&adev->dev, "%s failed to allocate " 1933 dev_err(&adev->dev, "%s failed to allocate "
@@ -1933,8 +1942,23 @@ static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
1933 ch->id = i; 1942 ch->id = i;
1934 ch->base = pl08x->base + PL080_Cx_BASE(i); 1943 ch->base = pl08x->base + PL080_Cx_BASE(i);
1935 spin_lock_init(&ch->lock); 1944 spin_lock_init(&ch->lock);
1936 ch->serving = NULL;
1937 ch->signal = -1; 1945 ch->signal = -1;
1946
1947 /*
1948 * Nomadik variants can have channels that are locked
1949 * down for the secure world only. Lock up these channels
1950 * by perpetually serving a dummy virtual channel.
1951 */
1952 if (vd->nomadik) {
1953 u32 val;
1954
1955 val = readl(ch->base + PL080_CH_CONFIG);
1956 if (val & (PL080N_CONFIG_ITPROT | PL080N_CONFIG_SECPROT)) {
1957 dev_info(&adev->dev, "physical channel %d reserved for secure access only\n", i);
1958 ch->locked = true;
1959 }
1960 }
1961
1938 dev_dbg(&adev->dev, "physical channel %d is %s\n", 1962 dev_dbg(&adev->dev, "physical channel %d is %s\n",
1939 i, pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE"); 1963 i, pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE");
1940 } 1964 }
@@ -2017,6 +2041,12 @@ static struct vendor_data vendor_pl080 = {
2017 .dualmaster = true, 2041 .dualmaster = true,
2018}; 2042};
2019 2043
2044static struct vendor_data vendor_nomadik = {
2045 .channels = 8,
2046 .dualmaster = true,
2047 .nomadik = true,
2048};
2049
2020static struct vendor_data vendor_pl081 = { 2050static struct vendor_data vendor_pl081 = {
2021 .channels = 2, 2051 .channels = 2,
2022 .dualmaster = false, 2052 .dualmaster = false,
@@ -2037,9 +2067,9 @@ static struct amba_id pl08x_ids[] = {
2037 }, 2067 },
2038 /* Nomadik 8815 PL080 variant */ 2068 /* Nomadik 8815 PL080 variant */
2039 { 2069 {
2040 .id = 0x00280880, 2070 .id = 0x00280080,
2041 .mask = 0x00ffffff, 2071 .mask = 0x00ffffff,
2042 .data = &vendor_pl080, 2072 .data = &vendor_nomadik,
2043 }, 2073 },
2044 { 0, 0 }, 2074 { 0, 0 },
2045}; 2075};
diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
index bf0d7e4e345b..7292aa87b2dd 100644
--- a/drivers/dma/at_hdmac.c
+++ b/drivers/dma/at_hdmac.c
@@ -39,7 +39,6 @@
39 */ 39 */
40 40
41#define ATC_DEFAULT_CFG (ATC_FIFOCFG_HALFFIFO) 41#define ATC_DEFAULT_CFG (ATC_FIFOCFG_HALFFIFO)
42#define ATC_DEFAULT_CTRLA (0)
43#define ATC_DEFAULT_CTRLB (ATC_SIF(AT_DMA_MEM_IF) \ 42#define ATC_DEFAULT_CTRLB (ATC_SIF(AT_DMA_MEM_IF) \
44 |ATC_DIF(AT_DMA_MEM_IF)) 43 |ATC_DIF(AT_DMA_MEM_IF))
45 44
@@ -574,7 +573,6 @@ atc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
574 return NULL; 573 return NULL;
575 } 574 }
576 575
577 ctrla = ATC_DEFAULT_CTRLA;
578 ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN 576 ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN
579 | ATC_SRC_ADDR_MODE_INCR 577 | ATC_SRC_ADDR_MODE_INCR
580 | ATC_DST_ADDR_MODE_INCR 578 | ATC_DST_ADDR_MODE_INCR
@@ -585,13 +583,13 @@ atc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
585 * of the most common optimization. 583 * of the most common optimization.
586 */ 584 */
587 if (!((src | dest | len) & 3)) { 585 if (!((src | dest | len) & 3)) {
588 ctrla |= ATC_SRC_WIDTH_WORD | ATC_DST_WIDTH_WORD; 586 ctrla = ATC_SRC_WIDTH_WORD | ATC_DST_WIDTH_WORD;
589 src_width = dst_width = 2; 587 src_width = dst_width = 2;
590 } else if (!((src | dest | len) & 1)) { 588 } else if (!((src | dest | len) & 1)) {
591 ctrla |= ATC_SRC_WIDTH_HALFWORD | ATC_DST_WIDTH_HALFWORD; 589 ctrla = ATC_SRC_WIDTH_HALFWORD | ATC_DST_WIDTH_HALFWORD;
592 src_width = dst_width = 1; 590 src_width = dst_width = 1;
593 } else { 591 } else {
594 ctrla |= ATC_SRC_WIDTH_BYTE | ATC_DST_WIDTH_BYTE; 592 ctrla = ATC_SRC_WIDTH_BYTE | ATC_DST_WIDTH_BYTE;
595 src_width = dst_width = 0; 593 src_width = dst_width = 0;
596 } 594 }
597 595
@@ -668,7 +666,8 @@ atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
668 return NULL; 666 return NULL;
669 } 667 }
670 668
671 ctrla = ATC_DEFAULT_CTRLA | atslave->ctrla; 669 ctrla = ATC_SCSIZE(sconfig->src_maxburst)
670 | ATC_DCSIZE(sconfig->dst_maxburst);
672 ctrlb = ATC_IEN; 671 ctrlb = ATC_IEN;
673 672
674 switch (direction) { 673 switch (direction) {
@@ -796,12 +795,12 @@ atc_dma_cyclic_fill_desc(struct dma_chan *chan, struct at_desc *desc,
796 enum dma_transfer_direction direction) 795 enum dma_transfer_direction direction)
797{ 796{
798 struct at_dma_chan *atchan = to_at_dma_chan(chan); 797 struct at_dma_chan *atchan = to_at_dma_chan(chan);
799 struct at_dma_slave *atslave = chan->private;
800 struct dma_slave_config *sconfig = &atchan->dma_sconfig; 798 struct dma_slave_config *sconfig = &atchan->dma_sconfig;
801 u32 ctrla; 799 u32 ctrla;
802 800
803 /* prepare common CRTLA value */ 801 /* prepare common CRTLA value */
804 ctrla = ATC_DEFAULT_CTRLA | atslave->ctrla 802 ctrla = ATC_SCSIZE(sconfig->src_maxburst)
803 | ATC_DCSIZE(sconfig->dst_maxburst)
805 | ATC_DST_WIDTH(reg_width) 804 | ATC_DST_WIDTH(reg_width)
806 | ATC_SRC_WIDTH(reg_width) 805 | ATC_SRC_WIDTH(reg_width)
807 | period_len >> reg_width; 806 | period_len >> reg_width;
diff --git a/drivers/dma/at_hdmac_regs.h b/drivers/dma/at_hdmac_regs.h
index 897a8bcaec90..8a6c8e8b2940 100644
--- a/drivers/dma/at_hdmac_regs.h
+++ b/drivers/dma/at_hdmac_regs.h
@@ -87,7 +87,26 @@
87/* Bitfields in CTRLA */ 87/* Bitfields in CTRLA */
88#define ATC_BTSIZE_MAX 0xFFFFUL /* Maximum Buffer Transfer Size */ 88#define ATC_BTSIZE_MAX 0xFFFFUL /* Maximum Buffer Transfer Size */
89#define ATC_BTSIZE(x) (ATC_BTSIZE_MAX & (x)) /* Buffer Transfer Size */ 89#define ATC_BTSIZE(x) (ATC_BTSIZE_MAX & (x)) /* Buffer Transfer Size */
90/* Chunck Tranfer size definitions are in at_hdmac.h */ 90#define ATC_SCSIZE_MASK (0x7 << 16) /* Source Chunk Transfer Size */
91#define ATC_SCSIZE(x) (ATC_SCSIZE_MASK & ((x) << 16))
92#define ATC_SCSIZE_1 (0x0 << 16)
93#define ATC_SCSIZE_4 (0x1 << 16)
94#define ATC_SCSIZE_8 (0x2 << 16)
95#define ATC_SCSIZE_16 (0x3 << 16)
96#define ATC_SCSIZE_32 (0x4 << 16)
97#define ATC_SCSIZE_64 (0x5 << 16)
98#define ATC_SCSIZE_128 (0x6 << 16)
99#define ATC_SCSIZE_256 (0x7 << 16)
100#define ATC_DCSIZE_MASK (0x7 << 20) /* Destination Chunk Transfer Size */
101#define ATC_DCSIZE(x) (ATC_DCSIZE_MASK & ((x) << 20))
102#define ATC_DCSIZE_1 (0x0 << 20)
103#define ATC_DCSIZE_4 (0x1 << 20)
104#define ATC_DCSIZE_8 (0x2 << 20)
105#define ATC_DCSIZE_16 (0x3 << 20)
106#define ATC_DCSIZE_32 (0x4 << 20)
107#define ATC_DCSIZE_64 (0x5 << 20)
108#define ATC_DCSIZE_128 (0x6 << 20)
109#define ATC_DCSIZE_256 (0x7 << 20)
91#define ATC_SRC_WIDTH_MASK (0x3 << 24) /* Source Single Transfer Size */ 110#define ATC_SRC_WIDTH_MASK (0x3 << 24) /* Source Single Transfer Size */
92#define ATC_SRC_WIDTH(x) ((x) << 24) 111#define ATC_SRC_WIDTH(x) ((x) << 24)
93#define ATC_SRC_WIDTH_BYTE (0x0 << 24) 112#define ATC_SRC_WIDTH_BYTE (0x0 << 24)
diff --git a/drivers/dma/coh901318.c b/drivers/dma/coh901318.c
index 750925f9638b..e67b4e06a918 100644
--- a/drivers/dma/coh901318.c
+++ b/drivers/dma/coh901318.c
@@ -1033,7 +1033,7 @@ coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
1033 1033
1034 if (!sgl) 1034 if (!sgl)
1035 goto out; 1035 goto out;
1036 if (sgl->length == 0) 1036 if (sg_dma_len(sgl) == 0)
1037 goto out; 1037 goto out;
1038 1038
1039 spin_lock_irqsave(&cohc->lock, flg); 1039 spin_lock_irqsave(&cohc->lock, flg);
diff --git a/drivers/dma/coh901318_lli.c b/drivers/dma/coh901318_lli.c
index 6c0e2d4c6682..780e0429b38c 100644
--- a/drivers/dma/coh901318_lli.c
+++ b/drivers/dma/coh901318_lli.c
@@ -270,10 +270,10 @@ coh901318_lli_fill_sg(struct coh901318_pool *pool,
270 270
271 if (dir == DMA_MEM_TO_DEV) 271 if (dir == DMA_MEM_TO_DEV)
272 /* increment source address */ 272 /* increment source address */
273 src = sg_phys(sg); 273 src = sg_dma_address(sg);
274 else 274 else
275 /* increment destination address */ 275 /* increment destination address */
276 dst = sg_phys(sg); 276 dst = sg_dma_address(sg);
277 277
278 bytes_to_transfer = sg_dma_len(sg); 278 bytes_to_transfer = sg_dma_len(sg);
279 279
diff --git a/drivers/dma/dw_dmac.c b/drivers/dma/dw_dmac.c
index 7439079f5eed..e23dc82d43ac 100644
--- a/drivers/dma/dw_dmac.c
+++ b/drivers/dma/dw_dmac.c
@@ -17,6 +17,7 @@
17#include <linux/init.h> 17#include <linux/init.h>
18#include <linux/interrupt.h> 18#include <linux/interrupt.h>
19#include <linux/io.h> 19#include <linux/io.h>
20#include <linux/of.h>
20#include <linux/mm.h> 21#include <linux/mm.h>
21#include <linux/module.h> 22#include <linux/module.h>
22#include <linux/platform_device.h> 23#include <linux/platform_device.h>
@@ -742,7 +743,7 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
742 struct dw_desc *desc; 743 struct dw_desc *desc;
743 u32 len, dlen, mem; 744 u32 len, dlen, mem;
744 745
745 mem = sg_phys(sg); 746 mem = sg_dma_address(sg);
746 len = sg_dma_len(sg); 747 len = sg_dma_len(sg);
747 748
748 if (!((mem | len) & 7)) 749 if (!((mem | len) & 7))
@@ -809,7 +810,7 @@ slave_sg_todev_fill_desc:
809 struct dw_desc *desc; 810 struct dw_desc *desc;
810 u32 len, dlen, mem; 811 u32 len, dlen, mem;
811 812
812 mem = sg_phys(sg); 813 mem = sg_dma_address(sg);
813 len = sg_dma_len(sg); 814 len = sg_dma_len(sg);
814 815
815 if (!((mem | len) & 7)) 816 if (!((mem | len) & 7))
@@ -1429,7 +1430,7 @@ static int __init dw_probe(struct platform_device *pdev)
1429 err = PTR_ERR(dw->clk); 1430 err = PTR_ERR(dw->clk);
1430 goto err_clk; 1431 goto err_clk;
1431 } 1432 }
1432 clk_enable(dw->clk); 1433 clk_prepare_enable(dw->clk);
1433 1434
1434 /* force dma off, just in case */ 1435 /* force dma off, just in case */
1435 dw_dma_off(dw); 1436 dw_dma_off(dw);
@@ -1510,7 +1511,7 @@ static int __init dw_probe(struct platform_device *pdev)
1510 return 0; 1511 return 0;
1511 1512
1512err_irq: 1513err_irq:
1513 clk_disable(dw->clk); 1514 clk_disable_unprepare(dw->clk);
1514 clk_put(dw->clk); 1515 clk_put(dw->clk);
1515err_clk: 1516err_clk:
1516 iounmap(dw->regs); 1517 iounmap(dw->regs);
@@ -1540,7 +1541,7 @@ static int __exit dw_remove(struct platform_device *pdev)
1540 channel_clear_bit(dw, CH_EN, dwc->mask); 1541 channel_clear_bit(dw, CH_EN, dwc->mask);
1541 } 1542 }
1542 1543
1543 clk_disable(dw->clk); 1544 clk_disable_unprepare(dw->clk);
1544 clk_put(dw->clk); 1545 clk_put(dw->clk);
1545 1546
1546 iounmap(dw->regs); 1547 iounmap(dw->regs);
@@ -1559,7 +1560,7 @@ static void dw_shutdown(struct platform_device *pdev)
1559 struct dw_dma *dw = platform_get_drvdata(pdev); 1560 struct dw_dma *dw = platform_get_drvdata(pdev);
1560 1561
1561 dw_dma_off(platform_get_drvdata(pdev)); 1562 dw_dma_off(platform_get_drvdata(pdev));
1562 clk_disable(dw->clk); 1563 clk_disable_unprepare(dw->clk);
1563} 1564}
1564 1565
1565static int dw_suspend_noirq(struct device *dev) 1566static int dw_suspend_noirq(struct device *dev)
@@ -1568,7 +1569,7 @@ static int dw_suspend_noirq(struct device *dev)
1568 struct dw_dma *dw = platform_get_drvdata(pdev); 1569 struct dw_dma *dw = platform_get_drvdata(pdev);
1569 1570
1570 dw_dma_off(platform_get_drvdata(pdev)); 1571 dw_dma_off(platform_get_drvdata(pdev));
1571 clk_disable(dw->clk); 1572 clk_disable_unprepare(dw->clk);
1572 1573
1573 return 0; 1574 return 0;
1574} 1575}
@@ -1578,7 +1579,7 @@ static int dw_resume_noirq(struct device *dev)
1578 struct platform_device *pdev = to_platform_device(dev); 1579 struct platform_device *pdev = to_platform_device(dev);
1579 struct dw_dma *dw = platform_get_drvdata(pdev); 1580 struct dw_dma *dw = platform_get_drvdata(pdev);
1580 1581
1581 clk_enable(dw->clk); 1582 clk_prepare_enable(dw->clk);
1582 dma_writel(dw, CFG, DW_CFG_DMA_EN); 1583 dma_writel(dw, CFG, DW_CFG_DMA_EN);
1583 return 0; 1584 return 0;
1584} 1585}
@@ -1592,12 +1593,21 @@ static const struct dev_pm_ops dw_dev_pm_ops = {
1592 .poweroff_noirq = dw_suspend_noirq, 1593 .poweroff_noirq = dw_suspend_noirq,
1593}; 1594};
1594 1595
1596#ifdef CONFIG_OF
1597static const struct of_device_id dw_dma_id_table[] = {
1598 { .compatible = "snps,dma-spear1340" },
1599 {}
1600};
1601MODULE_DEVICE_TABLE(of, dw_dma_id_table);
1602#endif
1603
1595static struct platform_driver dw_driver = { 1604static struct platform_driver dw_driver = {
1596 .remove = __exit_p(dw_remove), 1605 .remove = __exit_p(dw_remove),
1597 .shutdown = dw_shutdown, 1606 .shutdown = dw_shutdown,
1598 .driver = { 1607 .driver = {
1599 .name = "dw_dmac", 1608 .name = "dw_dmac",
1600 .pm = &dw_dev_pm_ops, 1609 .pm = &dw_dev_pm_ops,
1610 .of_match_table = of_match_ptr(dw_dma_id_table),
1601 }, 1611 },
1602}; 1612};
1603 1613
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index bb787d8e1529..fcfeb3cd8d31 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -227,7 +227,7 @@ static inline int imxdma_sg_next(struct imxdma_desc *d)
227 struct scatterlist *sg = d->sg; 227 struct scatterlist *sg = d->sg;
228 unsigned long now; 228 unsigned long now;
229 229
230 now = min(d->len, sg->length); 230 now = min(d->len, sg_dma_len(sg));
231 if (d->len != IMX_DMA_LENGTH_LOOP) 231 if (d->len != IMX_DMA_LENGTH_LOOP)
232 d->len -= now; 232 d->len -= now;
233 233
@@ -763,16 +763,16 @@ static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
763 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); 763 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
764 764
765 for_each_sg(sgl, sg, sg_len, i) { 765 for_each_sg(sgl, sg, sg_len, i) {
766 dma_length += sg->length; 766 dma_length += sg_dma_len(sg);
767 } 767 }
768 768
769 switch (imxdmac->word_size) { 769 switch (imxdmac->word_size) {
770 case DMA_SLAVE_BUSWIDTH_4_BYTES: 770 case DMA_SLAVE_BUSWIDTH_4_BYTES:
771 if (sgl->length & 3 || sgl->dma_address & 3) 771 if (sg_dma_len(sgl) & 3 || sgl->dma_address & 3)
772 return NULL; 772 return NULL;
773 break; 773 break;
774 case DMA_SLAVE_BUSWIDTH_2_BYTES: 774 case DMA_SLAVE_BUSWIDTH_2_BYTES:
775 if (sgl->length & 1 || sgl->dma_address & 1) 775 if (sg_dma_len(sgl) & 1 || sgl->dma_address & 1)
776 return NULL; 776 return NULL;
777 break; 777 break;
778 case DMA_SLAVE_BUSWIDTH_1_BYTE: 778 case DMA_SLAVE_BUSWIDTH_1_BYTE:
@@ -831,13 +831,13 @@ static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
831 imxdmac->sg_list[i].page_link = 0; 831 imxdmac->sg_list[i].page_link = 0;
832 imxdmac->sg_list[i].offset = 0; 832 imxdmac->sg_list[i].offset = 0;
833 imxdmac->sg_list[i].dma_address = dma_addr; 833 imxdmac->sg_list[i].dma_address = dma_addr;
834 imxdmac->sg_list[i].length = period_len; 834 sg_dma_len(&imxdmac->sg_list[i]) = period_len;
835 dma_addr += period_len; 835 dma_addr += period_len;
836 } 836 }
837 837
838 /* close the loop */ 838 /* close the loop */
839 imxdmac->sg_list[periods].offset = 0; 839 imxdmac->sg_list[periods].offset = 0;
840 imxdmac->sg_list[periods].length = 0; 840 sg_dma_len(&imxdmac->sg_list[periods]) = 0;
841 imxdmac->sg_list[periods].page_link = 841 imxdmac->sg_list[periods].page_link =
842 ((unsigned long)imxdmac->sg_list | 0x01) & ~0x02; 842 ((unsigned long)imxdmac->sg_list | 0x01) & ~0x02;
843 843
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index d3e38e28bb6b..a472a29d8497 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -24,7 +24,7 @@
24#include <linux/mm.h> 24#include <linux/mm.h>
25#include <linux/interrupt.h> 25#include <linux/interrupt.h>
26#include <linux/clk.h> 26#include <linux/clk.h>
27#include <linux/wait.h> 27#include <linux/delay.h>
28#include <linux/sched.h> 28#include <linux/sched.h>
29#include <linux/semaphore.h> 29#include <linux/semaphore.h>
30#include <linux/spinlock.h> 30#include <linux/spinlock.h>
@@ -271,6 +271,7 @@ struct sdma_channel {
271 enum dma_status status; 271 enum dma_status status;
272 unsigned int chn_count; 272 unsigned int chn_count;
273 unsigned int chn_real_count; 273 unsigned int chn_real_count;
274 struct tasklet_struct tasklet;
274}; 275};
275 276
276#define IMX_DMA_SG_LOOP BIT(0) 277#define IMX_DMA_SG_LOOP BIT(0)
@@ -323,7 +324,7 @@ struct sdma_engine {
323 dma_addr_t context_phys; 324 dma_addr_t context_phys;
324 struct dma_device dma_device; 325 struct dma_device dma_device;
325 struct clk *clk; 326 struct clk *clk;
326 struct mutex channel_0_lock; 327 spinlock_t channel_0_lock;
327 struct sdma_script_start_addrs *script_addrs; 328 struct sdma_script_start_addrs *script_addrs;
328}; 329};
329 330
@@ -401,19 +402,27 @@ static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
401} 402}
402 403
403/* 404/*
404 * sdma_run_channel - run a channel and wait till it's done 405 * sdma_run_channel0 - run a channel and wait till it's done
405 */ 406 */
406static int sdma_run_channel(struct sdma_channel *sdmac) 407static int sdma_run_channel0(struct sdma_engine *sdma)
407{ 408{
408 struct sdma_engine *sdma = sdmac->sdma;
409 int channel = sdmac->channel;
410 int ret; 409 int ret;
410 unsigned long timeout = 500;
411 411
412 init_completion(&sdmac->done); 412 sdma_enable_channel(sdma, 0);
413 413
414 sdma_enable_channel(sdma, channel); 414 while (!(ret = readl_relaxed(sdma->regs + SDMA_H_INTR) & 1)) {
415 if (timeout-- <= 0)
416 break;
417 udelay(1);
418 }
415 419
416 ret = wait_for_completion_timeout(&sdmac->done, HZ); 420 if (ret) {
421 /* Clear the interrupt status */
422 writel_relaxed(ret, sdma->regs + SDMA_H_INTR);
423 } else {
424 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n");
425 }
417 426
418 return ret ? 0 : -ETIMEDOUT; 427 return ret ? 0 : -ETIMEDOUT;
419} 428}
@@ -425,17 +434,17 @@ static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
425 void *buf_virt; 434 void *buf_virt;
426 dma_addr_t buf_phys; 435 dma_addr_t buf_phys;
427 int ret; 436 int ret;
428 437 unsigned long flags;
429 mutex_lock(&sdma->channel_0_lock);
430 438
431 buf_virt = dma_alloc_coherent(NULL, 439 buf_virt = dma_alloc_coherent(NULL,
432 size, 440 size,
433 &buf_phys, GFP_KERNEL); 441 &buf_phys, GFP_KERNEL);
434 if (!buf_virt) { 442 if (!buf_virt) {
435 ret = -ENOMEM; 443 return -ENOMEM;
436 goto err_out;
437 } 444 }
438 445
446 spin_lock_irqsave(&sdma->channel_0_lock, flags);
447
439 bd0->mode.command = C0_SETPM; 448 bd0->mode.command = C0_SETPM;
440 bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD; 449 bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
441 bd0->mode.count = size / 2; 450 bd0->mode.count = size / 2;
@@ -444,12 +453,11 @@ static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
444 453
445 memcpy(buf_virt, buf, size); 454 memcpy(buf_virt, buf, size);
446 455
447 ret = sdma_run_channel(&sdma->channel[0]); 456 ret = sdma_run_channel0(sdma);
448 457
449 dma_free_coherent(NULL, size, buf_virt, buf_phys); 458 spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
450 459
451err_out: 460 dma_free_coherent(NULL, size, buf_virt, buf_phys);
452 mutex_unlock(&sdma->channel_0_lock);
453 461
454 return ret; 462 return ret;
455} 463}
@@ -534,13 +542,11 @@ static void mxc_sdma_handle_channel_normal(struct sdma_channel *sdmac)
534 sdmac->desc.callback(sdmac->desc.callback_param); 542 sdmac->desc.callback(sdmac->desc.callback_param);
535} 543}
536 544
537static void mxc_sdma_handle_channel(struct sdma_channel *sdmac) 545static void sdma_tasklet(unsigned long data)
538{ 546{
539 complete(&sdmac->done); 547 struct sdma_channel *sdmac = (struct sdma_channel *) data;
540 548
541 /* not interested in channel 0 interrupts */ 549 complete(&sdmac->done);
542 if (sdmac->channel == 0)
543 return;
544 550
545 if (sdmac->flags & IMX_DMA_SG_LOOP) 551 if (sdmac->flags & IMX_DMA_SG_LOOP)
546 sdma_handle_channel_loop(sdmac); 552 sdma_handle_channel_loop(sdmac);
@@ -554,13 +560,15 @@ static irqreturn_t sdma_int_handler(int irq, void *dev_id)
554 unsigned long stat; 560 unsigned long stat;
555 561
556 stat = readl_relaxed(sdma->regs + SDMA_H_INTR); 562 stat = readl_relaxed(sdma->regs + SDMA_H_INTR);
563 /* not interested in channel 0 interrupts */
564 stat &= ~1;
557 writel_relaxed(stat, sdma->regs + SDMA_H_INTR); 565 writel_relaxed(stat, sdma->regs + SDMA_H_INTR);
558 566
559 while (stat) { 567 while (stat) {
560 int channel = fls(stat) - 1; 568 int channel = fls(stat) - 1;
561 struct sdma_channel *sdmac = &sdma->channel[channel]; 569 struct sdma_channel *sdmac = &sdma->channel[channel];
562 570
563 mxc_sdma_handle_channel(sdmac); 571 tasklet_schedule(&sdmac->tasklet);
564 572
565 __clear_bit(channel, &stat); 573 __clear_bit(channel, &stat);
566 } 574 }
@@ -659,6 +667,7 @@ static int sdma_load_context(struct sdma_channel *sdmac)
659 struct sdma_context_data *context = sdma->context; 667 struct sdma_context_data *context = sdma->context;
660 struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd; 668 struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
661 int ret; 669 int ret;
670 unsigned long flags;
662 671
663 if (sdmac->direction == DMA_DEV_TO_MEM) { 672 if (sdmac->direction == DMA_DEV_TO_MEM) {
664 load_address = sdmac->pc_from_device; 673 load_address = sdmac->pc_from_device;
@@ -676,7 +685,7 @@ static int sdma_load_context(struct sdma_channel *sdmac)
676 dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]); 685 dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]);
677 dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]); 686 dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]);
678 687
679 mutex_lock(&sdma->channel_0_lock); 688 spin_lock_irqsave(&sdma->channel_0_lock, flags);
680 689
681 memset(context, 0, sizeof(*context)); 690 memset(context, 0, sizeof(*context));
682 context->channel_state.pc = load_address; 691 context->channel_state.pc = load_address;
@@ -695,10 +704,9 @@ static int sdma_load_context(struct sdma_channel *sdmac)
695 bd0->mode.count = sizeof(*context) / 4; 704 bd0->mode.count = sizeof(*context) / 4;
696 bd0->buffer_addr = sdma->context_phys; 705 bd0->buffer_addr = sdma->context_phys;
697 bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel; 706 bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
707 ret = sdma_run_channel0(sdma);
698 708
699 ret = sdma_run_channel(&sdma->channel[0]); 709 spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
700
701 mutex_unlock(&sdma->channel_0_lock);
702 710
703 return ret; 711 return ret;
704} 712}
@@ -938,7 +946,7 @@ static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
938 946
939 bd->buffer_addr = sg->dma_address; 947 bd->buffer_addr = sg->dma_address;
940 948
941 count = sg->length; 949 count = sg_dma_len(sg);
942 950
943 if (count > 0xffff) { 951 if (count > 0xffff) {
944 dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n", 952 dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
@@ -1297,7 +1305,7 @@ static int __init sdma_probe(struct platform_device *pdev)
1297 if (!sdma) 1305 if (!sdma)
1298 return -ENOMEM; 1306 return -ENOMEM;
1299 1307
1300 mutex_init(&sdma->channel_0_lock); 1308 spin_lock_init(&sdma->channel_0_lock);
1301 1309
1302 sdma->dev = &pdev->dev; 1310 sdma->dev = &pdev->dev;
1303 1311
@@ -1359,6 +1367,8 @@ static int __init sdma_probe(struct platform_device *pdev)
1359 dma_cookie_init(&sdmac->chan); 1367 dma_cookie_init(&sdmac->chan);
1360 sdmac->channel = i; 1368 sdmac->channel = i;
1361 1369
1370 tasklet_init(&sdmac->tasklet, sdma_tasklet,
1371 (unsigned long) sdmac);
1362 /* 1372 /*
1363 * Add the channel to the DMAC list. Do not add channel 0 though 1373 * Add the channel to the DMAC list. Do not add channel 0 though
1364 * because we need it internally in the SDMA driver. This also means 1374 * because we need it internally in the SDMA driver. This also means
diff --git a/drivers/dma/intel_mid_dma.c b/drivers/dma/intel_mid_dma.c
index c900ca7aaec4..222e907bfaaa 100644
--- a/drivers/dma/intel_mid_dma.c
+++ b/drivers/dma/intel_mid_dma.c
@@ -394,11 +394,11 @@ static int midc_lli_fill_sg(struct intel_mid_dma_chan *midc,
394 } 394 }
395 } 395 }
396 /*Populate CTL_HI values*/ 396 /*Populate CTL_HI values*/
397 ctl_hi.ctlx.block_ts = get_block_ts(sg->length, 397 ctl_hi.ctlx.block_ts = get_block_ts(sg_dma_len(sg),
398 desc->width, 398 desc->width,
399 midc->dma->block_size); 399 midc->dma->block_size);
400 /*Populate SAR and DAR values*/ 400 /*Populate SAR and DAR values*/
401 sg_phy_addr = sg_phys(sg); 401 sg_phy_addr = sg_dma_address(sg);
402 if (desc->dirn == DMA_MEM_TO_DEV) { 402 if (desc->dirn == DMA_MEM_TO_DEV) {
403 lli_bloc_desc->sar = sg_phy_addr; 403 lli_bloc_desc->sar = sg_phy_addr;
404 lli_bloc_desc->dar = mids->dma_slave.dst_addr; 404 lli_bloc_desc->dar = mids->dma_slave.dst_addr;
@@ -747,7 +747,7 @@ static struct dma_async_tx_descriptor *intel_mid_dma_prep_slave_sg(
747 txd = intel_mid_dma_prep_memcpy(chan, 747 txd = intel_mid_dma_prep_memcpy(chan,
748 mids->dma_slave.dst_addr, 748 mids->dma_slave.dst_addr,
749 mids->dma_slave.src_addr, 749 mids->dma_slave.src_addr,
750 sgl->length, 750 sg_dma_len(sgl),
751 flags); 751 flags);
752 return txd; 752 return txd;
753 } else { 753 } else {
@@ -759,7 +759,7 @@ static struct dma_async_tx_descriptor *intel_mid_dma_prep_slave_sg(
759 pr_debug("MDMA: SG Length = %d, direction = %d, Flags = %#lx\n", 759 pr_debug("MDMA: SG Length = %d, direction = %d, Flags = %#lx\n",
760 sg_len, direction, flags); 760 sg_len, direction, flags);
761 761
762 txd = intel_mid_dma_prep_memcpy(chan, 0, 0, sgl->length, flags); 762 txd = intel_mid_dma_prep_memcpy(chan, 0, 0, sg_dma_len(sgl), flags);
763 if (NULL == txd) { 763 if (NULL == txd) {
764 pr_err("MDMA: Prep memcpy failed\n"); 764 pr_err("MDMA: Prep memcpy failed\n");
765 return NULL; 765 return NULL;
diff --git a/drivers/dma/mxs-dma.c b/drivers/dma/mxs-dma.c
index 655d4ce6ed0d..3db3a48d3f01 100644
--- a/drivers/dma/mxs-dma.c
+++ b/drivers/dma/mxs-dma.c
@@ -415,9 +415,9 @@ static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg(
415 ccw->bits |= BF_CCW(MXS_DMA_CMD_NO_XFER, COMMAND); 415 ccw->bits |= BF_CCW(MXS_DMA_CMD_NO_XFER, COMMAND);
416 } else { 416 } else {
417 for_each_sg(sgl, sg, sg_len, i) { 417 for_each_sg(sgl, sg, sg_len, i) {
418 if (sg->length > MAX_XFER_BYTES) { 418 if (sg_dma_len(sg) > MAX_XFER_BYTES) {
419 dev_err(mxs_dma->dma_device.dev, "maximum bytes for sg entry exceeded: %d > %d\n", 419 dev_err(mxs_dma->dma_device.dev, "maximum bytes for sg entry exceeded: %d > %d\n",
420 sg->length, MAX_XFER_BYTES); 420 sg_dma_len(sg), MAX_XFER_BYTES);
421 goto err_out; 421 goto err_out;
422 } 422 }
423 423
@@ -425,7 +425,7 @@ static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg(
425 425
426 ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx; 426 ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx;
427 ccw->bufaddr = sg->dma_address; 427 ccw->bufaddr = sg->dma_address;
428 ccw->xfer_bytes = sg->length; 428 ccw->xfer_bytes = sg_dma_len(sg);
429 429
430 ccw->bits = 0; 430 ccw->bits = 0;
431 ccw->bits |= CCW_CHAIN; 431 ccw->bits |= CCW_CHAIN;
diff --git a/drivers/dma/pch_dma.c b/drivers/dma/pch_dma.c
index 65c0495a6d40..987ab5cd2617 100644
--- a/drivers/dma/pch_dma.c
+++ b/drivers/dma/pch_dma.c
@@ -621,7 +621,7 @@ static struct dma_async_tx_descriptor *pd_prep_slave_sg(struct dma_chan *chan,
621 goto err_desc_get; 621 goto err_desc_get;
622 622
623 desc->regs.dev_addr = reg; 623 desc->regs.dev_addr = reg;
624 desc->regs.mem_addr = sg_phys(sg); 624 desc->regs.mem_addr = sg_dma_address(sg);
625 desc->regs.size = sg_dma_len(sg); 625 desc->regs.size = sg_dma_len(sg);
626 desc->regs.next = DMA_DESC_FOLLOW_WITHOUT_IRQ; 626 desc->regs.next = DMA_DESC_FOLLOW_WITHOUT_IRQ;
627 627
diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
index fa3fb21e60be..cbcc28e79be6 100644
--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
@@ -21,7 +21,6 @@
21#include <linux/interrupt.h> 21#include <linux/interrupt.h>
22#include <linux/dma-mapping.h> 22#include <linux/dma-mapping.h>
23#include <linux/dmaengine.h> 23#include <linux/dmaengine.h>
24#include <linux/interrupt.h>
25#include <linux/amba/bus.h> 24#include <linux/amba/bus.h>
26#include <linux/amba/pl330.h> 25#include <linux/amba/pl330.h>
27#include <linux/pm_runtime.h> 26#include <linux/pm_runtime.h>
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 2ed1ac3513f3..000d309602b2 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -2362,7 +2362,7 @@ dma40_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr,
2362 } 2362 }
2363 2363
2364 sg[periods].offset = 0; 2364 sg[periods].offset = 0;
2365 sg[periods].length = 0; 2365 sg_dma_len(&sg[periods]) = 0;
2366 sg[periods].page_link = 2366 sg[periods].page_link =
2367 ((unsigned long)sg | 0x01) & ~0x02; 2367 ((unsigned long)sg | 0x01) & ~0x02;
2368 2368
diff --git a/include/linux/amba/pl08x.h b/include/linux/amba/pl08x.h
index e64ce2cfee99..02549017212a 100644
--- a/include/linux/amba/pl08x.h
+++ b/include/linux/amba/pl08x.h
@@ -92,6 +92,8 @@ struct pl08x_bus_data {
92 * right now 92 * right now
93 * @serving: the virtual channel currently being served by this physical 93 * @serving: the virtual channel currently being served by this physical
94 * channel 94 * channel
95 * @locked: channel unavailable for the system, e.g. dedicated to secure
96 * world
95 */ 97 */
96struct pl08x_phy_chan { 98struct pl08x_phy_chan {
97 unsigned int id; 99 unsigned int id;
@@ -99,6 +101,7 @@ struct pl08x_phy_chan {
99 spinlock_t lock; 101 spinlock_t lock;
100 int signal; 102 int signal;
101 struct pl08x_dma_chan *serving; 103 struct pl08x_dma_chan *serving;
104 bool locked;
102}; 105};
103 106
104/** 107/**
diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
index f9a2e5e67a54..d3fec584e8c3 100644
--- a/include/linux/dmaengine.h
+++ b/include/linux/dmaengine.h
@@ -615,11 +615,13 @@ static inline int dmaengine_slave_config(struct dma_chan *chan,
615} 615}
616 616
617static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single( 617static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single(
618 struct dma_chan *chan, void *buf, size_t len, 618 struct dma_chan *chan, dma_addr_t buf, size_t len,
619 enum dma_transfer_direction dir, unsigned long flags) 619 enum dma_transfer_direction dir, unsigned long flags)
620{ 620{
621 struct scatterlist sg; 621 struct scatterlist sg;
622 sg_init_one(&sg, buf, len); 622 sg_init_table(&sg, 1);
623 sg_dma_address(&sg) = buf;
624 sg_dma_len(&sg) = len;
623 625
624 return chan->device->device_prep_slave_sg(chan, &sg, 1, 626 return chan->device->device_prep_slave_sg(chan, &sg, 1,
625 dir, flags, NULL); 627 dir, flags, NULL);