diff options
-rw-r--r-- | sound/soc/codecs/twl4030.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c index 74f0d65f0784..e0106a5fd40b 100644 --- a/sound/soc/codecs/twl4030.c +++ b/sound/soc/codecs/twl4030.c | |||
@@ -64,12 +64,12 @@ static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = { | |||
64 | 0x00, /* REG_VRXPGA (0x14) */ | 64 | 0x00, /* REG_VRXPGA (0x14) */ |
65 | 0x00, /* REG_VSTPGA (0x15) */ | 65 | 0x00, /* REG_VSTPGA (0x15) */ |
66 | 0x00, /* REG_VRX2ARXPGA (0x16) */ | 66 | 0x00, /* REG_VRX2ARXPGA (0x16) */ |
67 | 0x0c, /* REG_AVDAC_CTL (0x17) */ | 67 | 0x00, /* REG_AVDAC_CTL (0x17) */ |
68 | 0x00, /* REG_ARX2VTXPGA (0x18) */ | 68 | 0x00, /* REG_ARX2VTXPGA (0x18) */ |
69 | 0x00, /* REG_ARXL1_APGA_CTL (0x19) */ | 69 | 0x00, /* REG_ARXL1_APGA_CTL (0x19) */ |
70 | 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */ | 70 | 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */ |
71 | 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */ | 71 | 0x4a, /* REG_ARXL2_APGA_CTL (0x1B) */ |
72 | 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */ | 72 | 0x4a, /* REG_ARXR2_APGA_CTL (0x1C) */ |
73 | 0x00, /* REG_ATX2ARXPGA (0x1D) */ | 73 | 0x00, /* REG_ATX2ARXPGA (0x1D) */ |
74 | 0x00, /* REG_BT_IF (0x1E) */ | 74 | 0x00, /* REG_BT_IF (0x1E) */ |
75 | 0x00, /* REG_BTPGA (0x1F) */ | 75 | 0x00, /* REG_BTPGA (0x1F) */ |
@@ -99,7 +99,7 @@ static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = { | |||
99 | 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */ | 99 | 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */ |
100 | 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */ | 100 | 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */ |
101 | 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */ | 101 | 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */ |
102 | 0x16, /* REG_APLL_CTL (0x3A) */ | 102 | 0x06, /* REG_APLL_CTL (0x3A) */ |
103 | 0x00, /* REG_DTMF_CTL (0x3B) */ | 103 | 0x00, /* REG_DTMF_CTL (0x3B) */ |
104 | 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */ | 104 | 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */ |
105 | 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */ | 105 | 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */ |