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-rw-r--r--arch/arm/mach-omap2/clkt2xxx_apll.c10
-rw-r--r--arch/arm/mach-omap2/clkt2xxx_dpllcore.c8
-rw-r--r--arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c12
-rw-r--r--arch/arm/mach-omap2/clockdomain.c22
-rw-r--r--arch/arm/mach-omap2/cm2xxx_3xxx.c352
-rw-r--r--arch/arm/mach-omap2/cm2xxx_3xxx.h10
-rw-r--r--arch/arm/mach-omap2/control.c40
-rw-r--r--arch/arm/mach-omap2/dsp.c12
-rw-r--r--arch/arm/mach-omap2/pm-debug.c8
-rw-r--r--arch/arm/mach-omap2/pm24xx.c194
-rw-r--r--arch/arm/mach-omap2/pm34xx.c143
-rw-r--r--arch/arm/mach-omap2/powerdomain2xxx_3xxx.c66
-rw-r--r--arch/arm/mach-omap2/powerdomain44xx.c33
-rw-r--r--arch/arm/mach-omap2/prcm.c16
-rw-r--r--arch/arm/mach-omap2/prm2xxx_3xxx.c34
-rw-r--r--arch/arm/mach-omap2/prm2xxx_3xxx.h12
-rw-r--r--arch/arm/mach-omap2/sdrc2xxx.c4
-rw-r--r--arch/arm/mach-omap2/serial.c1
-rw-r--r--arch/arm/plat-omap/mcbsp.c8
19 files changed, 507 insertions, 478 deletions
diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c
index 954d11f37542..f51cffd1fc53 100644
--- a/arch/arm/mach-omap2/clkt2xxx_apll.c
+++ b/arch/arm/mach-omap2/clkt2xxx_apll.c
@@ -49,14 +49,14 @@ static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)
49 49
50 apll_mask = EN_APLL_LOCKED << clk->enable_bit; 50 apll_mask = EN_APLL_LOCKED << clk->enable_bit;
51 51
52 cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN); 52 cval = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
53 53
54 if ((cval & apll_mask) == apll_mask) 54 if ((cval & apll_mask) == apll_mask)
55 return 0; /* apll already enabled */ 55 return 0; /* apll already enabled */
56 56
57 cval &= ~apll_mask; 57 cval &= ~apll_mask;
58 cval |= apll_mask; 58 cval |= apll_mask;
59 cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); 59 omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
60 60
61 omap2_cm_wait_idlest(cm_idlest_pll, status_mask, 61 omap2_cm_wait_idlest(cm_idlest_pll, status_mask,
62 OMAP24XX_CM_IDLEST_VAL, clk->name); 62 OMAP24XX_CM_IDLEST_VAL, clk->name);
@@ -83,9 +83,9 @@ static void omap2_clk_apll_disable(struct clk *clk)
83{ 83{
84 u32 cval; 84 u32 cval;
85 85
86 cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN); 86 cval = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
87 cval &= ~(EN_APLL_LOCKED << clk->enable_bit); 87 cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
88 cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); 88 omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
89} 89}
90 90
91/* Public data */ 91/* Public data */
@@ -106,7 +106,7 @@ u32 omap2xxx_get_apll_clkin(void)
106{ 106{
107 u32 aplls, srate = 0; 107 u32 aplls, srate = 0;
108 108
109 aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1); 109 aplls = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
110 aplls &= OMAP24XX_APLLS_CLKIN_MASK; 110 aplls &= OMAP24XX_APLLS_CLKIN_MASK;
111 aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT; 111 aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
112 112
diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
index 530a76bc4a6c..4ae439222085 100644
--- a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
+++ b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
@@ -54,7 +54,7 @@ unsigned long omap2xxx_clk_get_core_rate(struct clk *clk)
54 54
55 core_clk = omap2_get_dpll_rate(clk); 55 core_clk = omap2_get_dpll_rate(clk);
56 56
57 v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); 57 v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
58 v &= OMAP24XX_CORE_CLK_SRC_MASK; 58 v &= OMAP24XX_CORE_CLK_SRC_MASK;
59 59
60 if (v == CORE_CLK_SRC_32K) 60 if (v == CORE_CLK_SRC_32K)
@@ -73,7 +73,7 @@ static long omap2_dpllcore_round_rate(unsigned long target_rate)
73{ 73{
74 u32 high, low, core_clk_src; 74 u32 high, low, core_clk_src;
75 75
76 core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); 76 core_clk_src = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
77 core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK; 77 core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
78 78
79 if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */ 79 if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */
@@ -111,7 +111,7 @@ int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
111 const struct dpll_data *dd; 111 const struct dpll_data *dd;
112 112
113 cur_rate = omap2xxx_clk_get_core_rate(dclk); 113 cur_rate = omap2xxx_clk_get_core_rate(dclk);
114 mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); 114 mult = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
115 mult &= OMAP24XX_CORE_CLK_SRC_MASK; 115 mult &= OMAP24XX_CORE_CLK_SRC_MASK;
116 116
117 if ((rate == (cur_rate / 2)) && (mult == 2)) { 117 if ((rate == (cur_rate / 2)) && (mult == 2)) {
@@ -136,7 +136,7 @@ int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
136 tmpset.cm_clksel1_pll &= ~(dd->mult_mask | 136 tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
137 dd->div1_mask); 137 dd->div1_mask);
138 div = ((curr_prcm_set->xtal_speed / 1000000) - 1); 138 div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
139 tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); 139 tmpset.cm_clksel2_pll = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
140 tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK; 140 tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
141 if (rate > low) { 141 if (rate > low) {
142 tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2; 142 tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
index f49f47d7457d..39f9d5a58d0c 100644
--- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
+++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
@@ -133,21 +133,21 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate)
133 done_rate = CORE_CLK_SRC_DPLL; 133 done_rate = CORE_CLK_SRC_DPLL;
134 134
135 /* MPU divider */ 135 /* MPU divider */
136 cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL); 136 omap2_cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
137 137
138 /* dsp + iva1 div(2420), iva2.1(2430) */ 138 /* dsp + iva1 div(2420), iva2.1(2430) */
139 cm_write_mod_reg(prcm->cm_clksel_dsp, 139 omap2_cm_write_mod_reg(prcm->cm_clksel_dsp,
140 OMAP24XX_DSP_MOD, CM_CLKSEL); 140 OMAP24XX_DSP_MOD, CM_CLKSEL);
141 141
142 cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL); 142 omap2_cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
143 143
144 /* Major subsystem dividers */ 144 /* Major subsystem dividers */
145 tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK; 145 tmp = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
146 cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, 146 omap2_cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD,
147 CM_CLKSEL1); 147 CM_CLKSEL1);
148 148
149 if (cpu_is_omap2430()) 149 if (cpu_is_omap2430())
150 cm_write_mod_reg(prcm->cm_clksel_mdm, 150 omap2_cm_write_mod_reg(prcm->cm_clksel_mdm,
151 OMAP2430_MDM_MOD, CM_CLKSEL); 151 OMAP2430_MDM_MOD, CM_CLKSEL);
152 152
153 /* x2 to enter omap2xxx_sdrc_init_params() */ 153 /* x2 to enter omap2xxx_sdrc_init_params() */
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index a2142e0f1ef4..da74f719d874 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -13,7 +13,6 @@
13 */ 13 */
14#undef DEBUG 14#undef DEBUG
15 15
16#include <linux/module.h>
17#include <linux/kernel.h> 16#include <linux/kernel.h>
18#include <linux/device.h> 17#include <linux/device.h>
19#include <linux/list.h> 18#include <linux/list.h>
@@ -30,7 +29,6 @@
30#include "prm2xxx_3xxx.h" 29#include "prm2xxx_3xxx.h"
31#include "prm-regbits-24xx.h" 30#include "prm-regbits-24xx.h"
32#include "cm2xxx_3xxx.h" 31#include "cm2xxx_3xxx.h"
33#include "cm2xxx_3xxx.h"
34 32
35#include <plat/clock.h> 33#include <plat/clock.h>
36#include <plat/powerdomain.h> 34#include <plat/powerdomain.h>
@@ -410,7 +408,7 @@ int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
410 pr_debug("clockdomain: hardware will wake up %s when %s wakes " 408 pr_debug("clockdomain: hardware will wake up %s when %s wakes "
411 "up\n", clkdm1->name, clkdm2->name); 409 "up\n", clkdm1->name, clkdm2->name);
412 410
413 prm_set_mod_reg_bits((1 << clkdm2->dep_bit), 411 omap2_prm_set_mod_reg_bits((1 << clkdm2->dep_bit),
414 clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP); 412 clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
415 } 413 }
416 414
@@ -445,7 +443,7 @@ int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
445 pr_debug("clockdomain: hardware will no longer wake up %s " 443 pr_debug("clockdomain: hardware will no longer wake up %s "
446 "after %s wakes up\n", clkdm1->name, clkdm2->name); 444 "after %s wakes up\n", clkdm1->name, clkdm2->name);
447 445
448 prm_clear_mod_reg_bits((1 << clkdm2->dep_bit), 446 omap2_prm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
449 clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP); 447 clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
450 } 448 }
451 449
@@ -481,7 +479,7 @@ int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
481 } 479 }
482 480
483 /* XXX It's faster to return the atomic wkdep_usecount */ 481 /* XXX It's faster to return the atomic wkdep_usecount */
484 return prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP, 482 return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP,
485 (1 << clkdm2->dep_bit)); 483 (1 << clkdm2->dep_bit));
486} 484}
487 485
@@ -515,7 +513,7 @@ int clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
515 atomic_set(&cd->wkdep_usecount, 0); 513 atomic_set(&cd->wkdep_usecount, 0);
516 } 514 }
517 515
518 prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, PM_WKDEP); 516 omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, PM_WKDEP);
519 517
520 return 0; 518 return 0;
521} 519}
@@ -554,7 +552,7 @@ int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
554 pr_debug("clockdomain: will prevent %s from sleeping if %s " 552 pr_debug("clockdomain: will prevent %s from sleeping if %s "
555 "is active\n", clkdm1->name, clkdm2->name); 553 "is active\n", clkdm1->name, clkdm2->name);
556 554
557 cm_set_mod_reg_bits((1 << clkdm2->dep_bit), 555 omap2_cm_set_mod_reg_bits((1 << clkdm2->dep_bit),
558 clkdm1->pwrdm.ptr->prcm_offs, 556 clkdm1->pwrdm.ptr->prcm_offs,
559 OMAP3430_CM_SLEEPDEP); 557 OMAP3430_CM_SLEEPDEP);
560 } 558 }
@@ -597,7 +595,7 @@ int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
597 "sleeping if %s is active\n", clkdm1->name, 595 "sleeping if %s is active\n", clkdm1->name,
598 clkdm2->name); 596 clkdm2->name);
599 597
600 cm_clear_mod_reg_bits((1 << clkdm2->dep_bit), 598 omap2_cm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
601 clkdm1->pwrdm.ptr->prcm_offs, 599 clkdm1->pwrdm.ptr->prcm_offs,
602 OMAP3430_CM_SLEEPDEP); 600 OMAP3430_CM_SLEEPDEP);
603 } 601 }
@@ -640,7 +638,7 @@ int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
640 } 638 }
641 639
642 /* XXX It's faster to return the atomic sleepdep_usecount */ 640 /* XXX It's faster to return the atomic sleepdep_usecount */
643 return prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, 641 return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
644 OMAP3430_CM_SLEEPDEP, 642 OMAP3430_CM_SLEEPDEP,
645 (1 << clkdm2->dep_bit)); 643 (1 << clkdm2->dep_bit));
646} 644}
@@ -678,7 +676,7 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
678 atomic_set(&cd->sleepdep_usecount, 0); 676 atomic_set(&cd->sleepdep_usecount, 0);
679 } 677 }
680 678
681 prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, 679 omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
682 OMAP3430_CM_SLEEPDEP); 680 OMAP3430_CM_SLEEPDEP);
683 681
684 return 0; 682 return 0;
@@ -730,7 +728,7 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm)
730 728
731 if (cpu_is_omap24xx()) { 729 if (cpu_is_omap24xx()) {
732 730
733 cm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK, 731 omap2_cm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
734 clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL); 732 clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL);
735 733
736 } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) { 734 } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
@@ -774,7 +772,7 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm)
774 772
775 if (cpu_is_omap24xx()) { 773 if (cpu_is_omap24xx()) {
776 774
777 cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK, 775 omap2_cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
778 clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL); 776 clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL);
779 777
780 } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) { 778 } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.c b/arch/arm/mach-omap2/cm2xxx_3xxx.c
index 1c98dfc93a83..e3d598a4c624 100644
--- a/arch/arm/mach-omap2/cm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/cm2xxx_3xxx.c
@@ -29,37 +29,37 @@ static const u8 cm_idlest_offs[] = {
29 CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3 29 CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
30}; 30};
31 31
32u32 cm_read_mod_reg(s16 module, u16 idx) 32u32 omap2_cm_read_mod_reg(s16 module, u16 idx)
33{ 33{
34 return __raw_readl(cm_base + module + idx); 34 return __raw_readl(cm_base + module + idx);
35} 35}
36 36
37void cm_write_mod_reg(u32 val, s16 module, u16 idx) 37void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx)
38{ 38{
39 __raw_writel(val, cm_base + module + idx); 39 __raw_writel(val, cm_base + module + idx);
40} 40}
41 41
42/* Read-modify-write a register in a CM module. Caller must lock */ 42/* Read-modify-write a register in a CM module. Caller must lock */
43u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) 43u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
44{ 44{
45 u32 v; 45 u32 v;
46 46
47 v = cm_read_mod_reg(module, idx); 47 v = omap2_cm_read_mod_reg(module, idx);
48 v &= ~mask; 48 v &= ~mask;
49 v |= bits; 49 v |= bits;
50 cm_write_mod_reg(v, module, idx); 50 omap2_cm_write_mod_reg(v, module, idx);
51 51
52 return v; 52 return v;
53} 53}
54 54
55u32 cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) 55u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
56{ 56{
57 return cm_rmw_mod_reg_bits(bits, bits, module, idx); 57 return omap2_cm_rmw_mod_reg_bits(bits, bits, module, idx);
58} 58}
59 59
60u32 cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) 60u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
61{ 61{
62 return cm_rmw_mod_reg_bits(bits, 0x0, module, idx); 62 return omap2_cm_rmw_mod_reg_bits(bits, 0x0, module, idx);
63} 63}
64 64
65/** 65/**
@@ -90,7 +90,7 @@ int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
90 else 90 else
91 BUG(); 91 BUG();
92 92
93 omap_test_timeout(((cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena), 93 omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena),
94 MAX_MODULE_READY_TIME, i); 94 MAX_MODULE_READY_TIME, i);
95 95
96 return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; 96 return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
@@ -166,228 +166,238 @@ static struct omap3_cm_regs cm_context;
166void omap3_cm_save_context(void) 166void omap3_cm_save_context(void)
167{ 167{
168 cm_context.iva2_cm_clksel1 = 168 cm_context.iva2_cm_clksel1 =
169 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1); 169 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
170 cm_context.iva2_cm_clksel2 = 170 cm_context.iva2_cm_clksel2 =
171 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2); 171 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
172 cm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG); 172 cm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
173 cm_context.sgx_cm_clksel = 173 cm_context.sgx_cm_clksel =
174 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL); 174 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
175 cm_context.dss_cm_clksel = 175 cm_context.dss_cm_clksel =
176 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL); 176 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
177 cm_context.cam_cm_clksel = 177 cm_context.cam_cm_clksel =
178 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL); 178 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);
179 cm_context.per_cm_clksel = 179 cm_context.per_cm_clksel =
180 cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL); 180 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);
181 cm_context.emu_cm_clksel = 181 cm_context.emu_cm_clksel =
182 cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1); 182 omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
183 cm_context.emu_cm_clkstctrl = 183 cm_context.emu_cm_clkstctrl =
184 cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL); 184 omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL);
185 cm_context.pll_cm_autoidle2 = 185 cm_context.pll_cm_autoidle2 =
186 cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2); 186 omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
187 cm_context.pll_cm_clksel4 = 187 cm_context.pll_cm_clksel4 =
188 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4); 188 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
189 cm_context.pll_cm_clksel5 = 189 cm_context.pll_cm_clksel5 =
190 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5); 190 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
191 cm_context.pll_cm_clken2 = 191 cm_context.pll_cm_clken2 =
192 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2); 192 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
193 cm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL); 193 cm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);
194 cm_context.iva2_cm_fclken = 194 cm_context.iva2_cm_fclken =
195 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN); 195 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
196 cm_context.iva2_cm_clken_pll = cm_read_mod_reg(OMAP3430_IVA2_MOD, 196 cm_context.iva2_cm_clken_pll =
197 OMAP3430_CM_CLKEN_PLL); 197 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL);
198 cm_context.core_cm_fclken1 = 198 cm_context.core_cm_fclken1 =
199 cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); 199 omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
200 cm_context.core_cm_fclken3 = 200 cm_context.core_cm_fclken3 =
201 cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3); 201 omap2_cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
202 cm_context.sgx_cm_fclken = 202 cm_context.sgx_cm_fclken =
203 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN); 203 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);
204 cm_context.wkup_cm_fclken = 204 cm_context.wkup_cm_fclken =
205 cm_read_mod_reg(WKUP_MOD, CM_FCLKEN); 205 omap2_cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
206 cm_context.dss_cm_fclken = 206 cm_context.dss_cm_fclken =
207 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN); 207 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);
208 cm_context.cam_cm_fclken = 208 cm_context.cam_cm_fclken =
209 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN); 209 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);
210 cm_context.per_cm_fclken = 210 cm_context.per_cm_fclken =
211 cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN); 211 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
212 cm_context.usbhost_cm_fclken = 212 cm_context.usbhost_cm_fclken =
213 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN); 213 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
214 cm_context.core_cm_iclken1 = 214 cm_context.core_cm_iclken1 =
215 cm_read_mod_reg(CORE_MOD, CM_ICLKEN1); 215 omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
216 cm_context.core_cm_iclken2 = 216 cm_context.core_cm_iclken2 =
217 cm_read_mod_reg(CORE_MOD, CM_ICLKEN2); 217 omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);
218 cm_context.core_cm_iclken3 = 218 cm_context.core_cm_iclken3 =
219 cm_read_mod_reg(CORE_MOD, CM_ICLKEN3); 219 omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
220 cm_context.sgx_cm_iclken = 220 cm_context.sgx_cm_iclken =
221 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN); 221 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);
222 cm_context.wkup_cm_iclken = 222 cm_context.wkup_cm_iclken =
223 cm_read_mod_reg(WKUP_MOD, CM_ICLKEN); 223 omap2_cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
224 cm_context.dss_cm_iclken = 224 cm_context.dss_cm_iclken =
225 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN); 225 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);
226 cm_context.cam_cm_iclken = 226 cm_context.cam_cm_iclken =
227 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN); 227 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);
228 cm_context.per_cm_iclken = 228 cm_context.per_cm_iclken =
229 cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN); 229 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
230 cm_context.usbhost_cm_iclken = 230 cm_context.usbhost_cm_iclken =
231 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN); 231 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
232 cm_context.iva2_cm_autoidle2 = 232 cm_context.iva2_cm_autoidle2 =
233 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2); 233 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
234 cm_context.mpu_cm_autoidle2 = 234 cm_context.mpu_cm_autoidle2 =
235 cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2); 235 omap2_cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
236 cm_context.iva2_cm_clkstctrl = 236 cm_context.iva2_cm_clkstctrl =
237 cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL); 237 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
238 cm_context.mpu_cm_clkstctrl = 238 cm_context.mpu_cm_clkstctrl =
239 cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL); 239 omap2_cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL);
240 cm_context.core_cm_clkstctrl = 240 cm_context.core_cm_clkstctrl =
241 cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL); 241 omap2_cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL);
242 cm_context.sgx_cm_clkstctrl = 242 cm_context.sgx_cm_clkstctrl =
243 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP2_CM_CLKSTCTRL); 243 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP2_CM_CLKSTCTRL);
244 cm_context.dss_cm_clkstctrl = 244 cm_context.dss_cm_clkstctrl =
245 cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL); 245 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL);
246 cm_context.cam_cm_clkstctrl = 246 cm_context.cam_cm_clkstctrl =
247 cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL); 247 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL);
248 cm_context.per_cm_clkstctrl = 248 cm_context.per_cm_clkstctrl =
249 cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL); 249 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL);
250 cm_context.neon_cm_clkstctrl = 250 cm_context.neon_cm_clkstctrl =
251 cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL); 251 omap2_cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL);
252 cm_context.usbhost_cm_clkstctrl = 252 cm_context.usbhost_cm_clkstctrl =
253 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL); 253 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
254 OMAP2_CM_CLKSTCTRL);
254 cm_context.core_cm_autoidle1 = 255 cm_context.core_cm_autoidle1 =
255 cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1); 256 omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);
256 cm_context.core_cm_autoidle2 = 257 cm_context.core_cm_autoidle2 =
257 cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2); 258 omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2);
258 cm_context.core_cm_autoidle3 = 259 cm_context.core_cm_autoidle3 =
259 cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3); 260 omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3);
260 cm_context.wkup_cm_autoidle = 261 cm_context.wkup_cm_autoidle =
261 cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE); 262 omap2_cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);
262 cm_context.dss_cm_autoidle = 263 cm_context.dss_cm_autoidle =
263 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE); 264 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);
264 cm_context.cam_cm_autoidle = 265 cm_context.cam_cm_autoidle =
265 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE); 266 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE);
266 cm_context.per_cm_autoidle = 267 cm_context.per_cm_autoidle =
267 cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE); 268 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
268 cm_context.usbhost_cm_autoidle = 269 cm_context.usbhost_cm_autoidle =
269 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE); 270 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
270 cm_context.sgx_cm_sleepdep = 271 cm_context.sgx_cm_sleepdep =
271 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP3430_CM_SLEEPDEP); 272 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
273 OMAP3430_CM_SLEEPDEP);
272 cm_context.dss_cm_sleepdep = 274 cm_context.dss_cm_sleepdep =
273 cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP); 275 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP);
274 cm_context.cam_cm_sleepdep = 276 cm_context.cam_cm_sleepdep =
275 cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP); 277 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP);
276 cm_context.per_cm_sleepdep = 278 cm_context.per_cm_sleepdep =
277 cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP); 279 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP);
278 cm_context.usbhost_cm_sleepdep = 280 cm_context.usbhost_cm_sleepdep =
279 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP); 281 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
282 OMAP3430_CM_SLEEPDEP);
280 cm_context.cm_clkout_ctrl = 283 cm_context.cm_clkout_ctrl =
281 cm_read_mod_reg(OMAP3430_CCR_MOD, OMAP3_CM_CLKOUT_CTRL_OFFSET); 284 omap2_cm_read_mod_reg(OMAP3430_CCR_MOD,
285 OMAP3_CM_CLKOUT_CTRL_OFFSET);
282} 286}
283 287
284void omap3_cm_restore_context(void) 288void omap3_cm_restore_context(void)
285{ 289{
286 cm_write_mod_reg(cm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD, 290 omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,
287 CM_CLKSEL1); 291 CM_CLKSEL1);
288 cm_write_mod_reg(cm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD, 292 omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
289 CM_CLKSEL2); 293 CM_CLKSEL2);
290 __raw_writel(cm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG); 294 __raw_writel(cm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
291 cm_write_mod_reg(cm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD, 295 omap2_cm_write_mod_reg(cm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
292 CM_CLKSEL); 296 CM_CLKSEL);
293 cm_write_mod_reg(cm_context.dss_cm_clksel, OMAP3430_DSS_MOD, 297 omap2_cm_write_mod_reg(cm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
294 CM_CLKSEL); 298 CM_CLKSEL);
295 cm_write_mod_reg(cm_context.cam_cm_clksel, OMAP3430_CAM_MOD, 299 omap2_cm_write_mod_reg(cm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
296 CM_CLKSEL); 300 CM_CLKSEL);
297 cm_write_mod_reg(cm_context.per_cm_clksel, OMAP3430_PER_MOD, 301 omap2_cm_write_mod_reg(cm_context.per_cm_clksel, OMAP3430_PER_MOD,
298 CM_CLKSEL); 302 CM_CLKSEL);
299 cm_write_mod_reg(cm_context.emu_cm_clksel, OMAP3430_EMU_MOD, 303 omap2_cm_write_mod_reg(cm_context.emu_cm_clksel, OMAP3430_EMU_MOD,
300 CM_CLKSEL1); 304 CM_CLKSEL1);
301 cm_write_mod_reg(cm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD, 305 omap2_cm_write_mod_reg(cm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
302 OMAP2_CM_CLKSTCTRL); 306 OMAP2_CM_CLKSTCTRL);
303 cm_write_mod_reg(cm_context.pll_cm_autoidle2, PLL_MOD, 307 omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle2, PLL_MOD,
304 CM_AUTOIDLE2); 308 CM_AUTOIDLE2);
305 cm_write_mod_reg(cm_context.pll_cm_clksel4, PLL_MOD, 309 omap2_cm_write_mod_reg(cm_context.pll_cm_clksel4, PLL_MOD,
306 OMAP3430ES2_CM_CLKSEL4); 310 OMAP3430ES2_CM_CLKSEL4);
307 cm_write_mod_reg(cm_context.pll_cm_clksel5, PLL_MOD, 311 omap2_cm_write_mod_reg(cm_context.pll_cm_clksel5, PLL_MOD,
308 OMAP3430ES2_CM_CLKSEL5); 312 OMAP3430ES2_CM_CLKSEL5);
309 cm_write_mod_reg(cm_context.pll_cm_clken2, PLL_MOD, 313 omap2_cm_write_mod_reg(cm_context.pll_cm_clken2, PLL_MOD,
310 OMAP3430ES2_CM_CLKEN2); 314 OMAP3430ES2_CM_CLKEN2);
311 __raw_writel(cm_context.cm_polctrl, OMAP3430_CM_POLCTRL); 315 __raw_writel(cm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
312 cm_write_mod_reg(cm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD, 316 omap2_cm_write_mod_reg(cm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
313 CM_FCLKEN); 317 CM_FCLKEN);
314 cm_write_mod_reg(cm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD, 318 omap2_cm_write_mod_reg(cm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
315 OMAP3430_CM_CLKEN_PLL); 319 OMAP3430_CM_CLKEN_PLL);
316 cm_write_mod_reg(cm_context.core_cm_fclken1, CORE_MOD, CM_FCLKEN1); 320 omap2_cm_write_mod_reg(cm_context.core_cm_fclken1, CORE_MOD,
317 cm_write_mod_reg(cm_context.core_cm_fclken3, CORE_MOD, 321 CM_FCLKEN1);
318 OMAP3430ES2_CM_FCLKEN3); 322 omap2_cm_write_mod_reg(cm_context.core_cm_fclken3, CORE_MOD,
319 cm_write_mod_reg(cm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD, 323 OMAP3430ES2_CM_FCLKEN3);
320 CM_FCLKEN); 324 omap2_cm_write_mod_reg(cm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD,
321 cm_write_mod_reg(cm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN); 325 CM_FCLKEN);
322 cm_write_mod_reg(cm_context.dss_cm_fclken, OMAP3430_DSS_MOD, 326 omap2_cm_write_mod_reg(cm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN);
323 CM_FCLKEN); 327 omap2_cm_write_mod_reg(cm_context.dss_cm_fclken, OMAP3430_DSS_MOD,
324 cm_write_mod_reg(cm_context.cam_cm_fclken, OMAP3430_CAM_MOD, 328 CM_FCLKEN);
325 CM_FCLKEN); 329 omap2_cm_write_mod_reg(cm_context.cam_cm_fclken, OMAP3430_CAM_MOD,
326 cm_write_mod_reg(cm_context.per_cm_fclken, OMAP3430_PER_MOD, 330 CM_FCLKEN);
327 CM_FCLKEN); 331 omap2_cm_write_mod_reg(cm_context.per_cm_fclken, OMAP3430_PER_MOD,
328 cm_write_mod_reg(cm_context.usbhost_cm_fclken, 332 CM_FCLKEN);
329 OMAP3430ES2_USBHOST_MOD, CM_FCLKEN); 333 omap2_cm_write_mod_reg(cm_context.usbhost_cm_fclken,
330 cm_write_mod_reg(cm_context.core_cm_iclken1, CORE_MOD, CM_ICLKEN1); 334 OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
331 cm_write_mod_reg(cm_context.core_cm_iclken2, CORE_MOD, CM_ICLKEN2); 335 omap2_cm_write_mod_reg(cm_context.core_cm_iclken1, CORE_MOD,
332 cm_write_mod_reg(cm_context.core_cm_iclken3, CORE_MOD, CM_ICLKEN3); 336 CM_ICLKEN1);
333 cm_write_mod_reg(cm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD, 337 omap2_cm_write_mod_reg(cm_context.core_cm_iclken2, CORE_MOD,
334 CM_ICLKEN); 338 CM_ICLKEN2);
335 cm_write_mod_reg(cm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN); 339 omap2_cm_write_mod_reg(cm_context.core_cm_iclken3, CORE_MOD,
336 cm_write_mod_reg(cm_context.dss_cm_iclken, OMAP3430_DSS_MOD, 340 CM_ICLKEN3);
337 CM_ICLKEN); 341 omap2_cm_write_mod_reg(cm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD,
338 cm_write_mod_reg(cm_context.cam_cm_iclken, OMAP3430_CAM_MOD, 342 CM_ICLKEN);
339 CM_ICLKEN); 343 omap2_cm_write_mod_reg(cm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN);
340 cm_write_mod_reg(cm_context.per_cm_iclken, OMAP3430_PER_MOD, 344 omap2_cm_write_mod_reg(cm_context.dss_cm_iclken, OMAP3430_DSS_MOD,
341 CM_ICLKEN); 345 CM_ICLKEN);
342 cm_write_mod_reg(cm_context.usbhost_cm_iclken, 346 omap2_cm_write_mod_reg(cm_context.cam_cm_iclken, OMAP3430_CAM_MOD,
343 OMAP3430ES2_USBHOST_MOD, CM_ICLKEN); 347 CM_ICLKEN);
344 cm_write_mod_reg(cm_context.iva2_cm_autoidle2, OMAP3430_IVA2_MOD, 348 omap2_cm_write_mod_reg(cm_context.per_cm_iclken, OMAP3430_PER_MOD,
345 CM_AUTOIDLE2); 349 CM_ICLKEN);
346 cm_write_mod_reg(cm_context.mpu_cm_autoidle2, MPU_MOD, CM_AUTOIDLE2); 350 omap2_cm_write_mod_reg(cm_context.usbhost_cm_iclken,
347 cm_write_mod_reg(cm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD, 351 OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
348 OMAP2_CM_CLKSTCTRL); 352 omap2_cm_write_mod_reg(cm_context.iva2_cm_autoidle2, OMAP3430_IVA2_MOD,
349 cm_write_mod_reg(cm_context.mpu_cm_clkstctrl, MPU_MOD, 353 CM_AUTOIDLE2);
350 OMAP2_CM_CLKSTCTRL); 354 omap2_cm_write_mod_reg(cm_context.mpu_cm_autoidle2, MPU_MOD,
351 cm_write_mod_reg(cm_context.core_cm_clkstctrl, CORE_MOD, 355 CM_AUTOIDLE2);
352 OMAP2_CM_CLKSTCTRL); 356 omap2_cm_write_mod_reg(cm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
353 cm_write_mod_reg(cm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD, 357 OMAP2_CM_CLKSTCTRL);
354 OMAP2_CM_CLKSTCTRL); 358 omap2_cm_write_mod_reg(cm_context.mpu_cm_clkstctrl, MPU_MOD,
355 cm_write_mod_reg(cm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD, 359 OMAP2_CM_CLKSTCTRL);
356 OMAP2_CM_CLKSTCTRL); 360 omap2_cm_write_mod_reg(cm_context.core_cm_clkstctrl, CORE_MOD,
357 cm_write_mod_reg(cm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD, 361 OMAP2_CM_CLKSTCTRL);
358 OMAP2_CM_CLKSTCTRL); 362 omap2_cm_write_mod_reg(cm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,
359 cm_write_mod_reg(cm_context.per_cm_clkstctrl, OMAP3430_PER_MOD, 363 OMAP2_CM_CLKSTCTRL);
360 OMAP2_CM_CLKSTCTRL); 364 omap2_cm_write_mod_reg(cm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,
361 cm_write_mod_reg(cm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD, 365 OMAP2_CM_CLKSTCTRL);
362 OMAP2_CM_CLKSTCTRL); 366 omap2_cm_write_mod_reg(cm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,
363 cm_write_mod_reg(cm_context.usbhost_cm_clkstctrl, 367 OMAP2_CM_CLKSTCTRL);
364 OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL); 368 omap2_cm_write_mod_reg(cm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,
365 cm_write_mod_reg(cm_context.core_cm_autoidle1, CORE_MOD, 369 OMAP2_CM_CLKSTCTRL);
366 CM_AUTOIDLE1); 370 omap2_cm_write_mod_reg(cm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,
367 cm_write_mod_reg(cm_context.core_cm_autoidle2, CORE_MOD, 371 OMAP2_CM_CLKSTCTRL);
368 CM_AUTOIDLE2); 372 omap2_cm_write_mod_reg(cm_context.usbhost_cm_clkstctrl,
369 cm_write_mod_reg(cm_context.core_cm_autoidle3, CORE_MOD, 373 OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL);
370 CM_AUTOIDLE3); 374 omap2_cm_write_mod_reg(cm_context.core_cm_autoidle1, CORE_MOD,
371 cm_write_mod_reg(cm_context.wkup_cm_autoidle, WKUP_MOD, CM_AUTOIDLE); 375 CM_AUTOIDLE1);
372 cm_write_mod_reg(cm_context.dss_cm_autoidle, OMAP3430_DSS_MOD, 376 omap2_cm_write_mod_reg(cm_context.core_cm_autoidle2, CORE_MOD,
373 CM_AUTOIDLE); 377 CM_AUTOIDLE2);
374 cm_write_mod_reg(cm_context.cam_cm_autoidle, OMAP3430_CAM_MOD, 378 omap2_cm_write_mod_reg(cm_context.core_cm_autoidle3, CORE_MOD,
375 CM_AUTOIDLE); 379 CM_AUTOIDLE3);
376 cm_write_mod_reg(cm_context.per_cm_autoidle, OMAP3430_PER_MOD, 380 omap2_cm_write_mod_reg(cm_context.wkup_cm_autoidle, WKUP_MOD,
377 CM_AUTOIDLE); 381 CM_AUTOIDLE);
378 cm_write_mod_reg(cm_context.usbhost_cm_autoidle, 382 omap2_cm_write_mod_reg(cm_context.dss_cm_autoidle, OMAP3430_DSS_MOD,
379 OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE); 383 CM_AUTOIDLE);
380 cm_write_mod_reg(cm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD, 384 omap2_cm_write_mod_reg(cm_context.cam_cm_autoidle, OMAP3430_CAM_MOD,
381 OMAP3430_CM_SLEEPDEP); 385 CM_AUTOIDLE);
382 cm_write_mod_reg(cm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD, 386 omap2_cm_write_mod_reg(cm_context.per_cm_autoidle, OMAP3430_PER_MOD,
383 OMAP3430_CM_SLEEPDEP); 387 CM_AUTOIDLE);
384 cm_write_mod_reg(cm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD, 388 omap2_cm_write_mod_reg(cm_context.usbhost_cm_autoidle,
385 OMAP3430_CM_SLEEPDEP); 389 OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
386 cm_write_mod_reg(cm_context.per_cm_sleepdep, OMAP3430_PER_MOD, 390 omap2_cm_write_mod_reg(cm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD,
387 OMAP3430_CM_SLEEPDEP); 391 OMAP3430_CM_SLEEPDEP);
388 cm_write_mod_reg(cm_context.usbhost_cm_sleepdep, 392 omap2_cm_write_mod_reg(cm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD,
389 OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP); 393 OMAP3430_CM_SLEEPDEP);
390 cm_write_mod_reg(cm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD, 394 omap2_cm_write_mod_reg(cm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD,
391 OMAP3_CM_CLKOUT_CTRL_OFFSET); 395 OMAP3430_CM_SLEEPDEP);
396 omap2_cm_write_mod_reg(cm_context.per_cm_sleepdep, OMAP3430_PER_MOD,
397 OMAP3430_CM_SLEEPDEP);
398 omap2_cm_write_mod_reg(cm_context.usbhost_cm_sleepdep,
399 OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
400 omap2_cm_write_mod_reg(cm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,
401 OMAP3_CM_CLKOUT_CTRL_OFFSET);
392} 402}
393#endif 403#endif
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.h b/arch/arm/mach-omap2/cm2xxx_3xxx.h
index ce2582c1441b..ff24edf54d31 100644
--- a/arch/arm/mach-omap2/cm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/cm2xxx_3xxx.h
@@ -104,14 +104,14 @@
104 104
105#ifndef __ASSEMBLER__ 105#ifndef __ASSEMBLER__
106 106
107extern u32 cm_read_mod_reg(s16 module, u16 idx); 107extern u32 omap2_cm_read_mod_reg(s16 module, u16 idx);
108extern void cm_write_mod_reg(u32 val, s16 module, u16 idx); 108extern void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx);
109extern u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); 109extern u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
110 110
111extern int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, 111extern int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id,
112 u8 idlest_shift); 112 u8 idlest_shift);
113extern u32 cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx); 113extern u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx);
114extern u32 cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx); 114extern u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx);
115 115
116#endif 116#endif
117 117
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 2506edfc4acb..61101e807df1 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -252,13 +252,13 @@ void omap3_clear_scratchpad_contents(void)
252 void __iomem *v_addr; 252 void __iomem *v_addr;
253 u32 offset = 0; 253 u32 offset = 0;
254 v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM); 254 v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);
255 if (prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) & 255 if (omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
256 OMAP3430_GLOBAL_COLD_RST_MASK) { 256 OMAP3430_GLOBAL_COLD_RST_MASK) {
257 for ( ; offset <= max_offset; offset += 0x4) 257 for ( ; offset <= max_offset; offset += 0x4)
258 __raw_writel(0x0, (v_addr + offset)); 258 __raw_writel(0x0, (v_addr + offset));
259 prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK, 259 omap2_prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK,
260 OMAP3430_GR_MOD, 260 OMAP3430_GR_MOD,
261 OMAP3_PRM_RSTST_OFFSET); 261 OMAP3_PRM_RSTST_OFFSET);
262 } 262 }
263} 263}
264 264
@@ -300,32 +300,34 @@ void omap3_save_scratchpad_contents(void)
300 scratchpad_contents.sdrc_block_offset = 0x64; 300 scratchpad_contents.sdrc_block_offset = 0x64;
301 301
302 /* Populate the PRCM block contents */ 302 /* Populate the PRCM block contents */
303 prcm_block_contents.prm_clksrc_ctrl = prm_read_mod_reg(OMAP3430_GR_MOD, 303 prcm_block_contents.prm_clksrc_ctrl =
304 OMAP3_PRM_CLKSRC_CTRL_OFFSET); 304 omap2_prm_read_mod_reg(OMAP3430_GR_MOD,
305 prcm_block_contents.prm_clksel = prm_read_mod_reg(OMAP3430_CCR_MOD, 305 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
306 OMAP3_PRM_CLKSEL_OFFSET); 306 prcm_block_contents.prm_clksel =
307 omap2_prm_read_mod_reg(OMAP3430_CCR_MOD,
308 OMAP3_PRM_CLKSEL_OFFSET);
307 prcm_block_contents.cm_clksel_core = 309 prcm_block_contents.cm_clksel_core =
308 cm_read_mod_reg(CORE_MOD, CM_CLKSEL); 310 omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL);
309 prcm_block_contents.cm_clksel_wkup = 311 prcm_block_contents.cm_clksel_wkup =
310 cm_read_mod_reg(WKUP_MOD, CM_CLKSEL); 312 omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
311 prcm_block_contents.cm_clken_pll = 313 prcm_block_contents.cm_clken_pll =
312 cm_read_mod_reg(PLL_MOD, CM_CLKEN); 314 omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
313 prcm_block_contents.cm_autoidle_pll = 315 prcm_block_contents.cm_autoidle_pll =
314 cm_read_mod_reg(PLL_MOD, OMAP3430_CM_AUTOIDLE_PLL); 316 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_AUTOIDLE_PLL);
315 prcm_block_contents.cm_clksel1_pll = 317 prcm_block_contents.cm_clksel1_pll =
316 cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL); 318 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
317 prcm_block_contents.cm_clksel2_pll = 319 prcm_block_contents.cm_clksel2_pll =
318 cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL); 320 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL);
319 prcm_block_contents.cm_clksel3_pll = 321 prcm_block_contents.cm_clksel3_pll =
320 cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3); 322 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3);
321 prcm_block_contents.cm_clken_pll_mpu = 323 prcm_block_contents.cm_clken_pll_mpu =
322 cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL); 324 omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL);
323 prcm_block_contents.cm_autoidle_pll_mpu = 325 prcm_block_contents.cm_autoidle_pll_mpu =
324 cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL); 326 omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL);
325 prcm_block_contents.cm_clksel1_pll_mpu = 327 prcm_block_contents.cm_clksel1_pll_mpu =
326 cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL); 328 omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL);
327 prcm_block_contents.cm_clksel2_pll_mpu = 329 prcm_block_contents.cm_clksel2_pll_mpu =
328 cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL); 330 omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL);
329 prcm_block_contents.prcm_block_size = 0x0; 331 prcm_block_contents.prcm_block_size = 0x0;
330 332
331 /* Populate the SDRC block contents */ 333 /* Populate the SDRC block contents */
diff --git a/arch/arm/mach-omap2/dsp.c b/arch/arm/mach-omap2/dsp.c
index cf5f3331af27..911cd2e68d46 100644
--- a/arch/arm/mach-omap2/dsp.c
+++ b/arch/arm/mach-omap2/dsp.c
@@ -38,12 +38,12 @@ static struct omap_dsp_platform_data omap_dsp_pdata __initdata = {
38 .cpu_set_freq = omap_pm_cpu_set_freq, 38 .cpu_set_freq = omap_pm_cpu_set_freq,
39 .cpu_get_freq = omap_pm_cpu_get_freq, 39 .cpu_get_freq = omap_pm_cpu_get_freq,
40#endif 40#endif
41 .dsp_prm_read = prm_read_mod_reg, 41 .dsp_prm_read = omap2_prm_read_mod_reg,
42 .dsp_prm_write = prm_write_mod_reg, 42 .dsp_prm_write = omap2_prm_write_mod_reg,
43 .dsp_prm_rmw_bits = prm_rmw_mod_reg_bits, 43 .dsp_prm_rmw_bits = omap2_prm_rmw_mod_reg_bits,
44 .dsp_cm_read = cm_read_mod_reg, 44 .dsp_cm_read = omap2_cm_read_mod_reg,
45 .dsp_cm_write = cm_write_mod_reg, 45 .dsp_cm_write = omap2_cm_write_mod_reg,
46 .dsp_cm_rmw_bits = cm_rmw_mod_reg_bits, 46 .dsp_cm_rmw_bits = omap2_cm_rmw_mod_reg_bits,
47}; 47};
48 48
49static int __init omap_dsp_init(void) 49static int __init omap_dsp_init(void)
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 1f5d68beabf3..1a4efb5e435a 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -45,10 +45,10 @@ u32 wakeup_timer_milliseconds;
45 45
46#define DUMP_PRM_MOD_REG(mod, reg) \ 46#define DUMP_PRM_MOD_REG(mod, reg) \
47 regs[reg_count].name = #mod "." #reg; \ 47 regs[reg_count].name = #mod "." #reg; \
48 regs[reg_count++].val = prm_read_mod_reg(mod, reg) 48 regs[reg_count++].val = omap2_prm_read_mod_reg(mod, reg)
49#define DUMP_CM_MOD_REG(mod, reg) \ 49#define DUMP_CM_MOD_REG(mod, reg) \
50 regs[reg_count].name = #mod "." #reg; \ 50 regs[reg_count].name = #mod "." #reg; \
51 regs[reg_count++].val = cm_read_mod_reg(mod, reg) 51 regs[reg_count++].val = omap2_cm_read_mod_reg(mod, reg)
52#define DUMP_PRM_REG(reg) \ 52#define DUMP_PRM_REG(reg) \
53 regs[reg_count].name = #reg; \ 53 regs[reg_count].name = #reg; \
54 regs[reg_count++].val = __raw_readl(reg) 54 regs[reg_count++].val = __raw_readl(reg)
@@ -328,10 +328,10 @@ static void pm_dbg_regset_store(u32 *ptr)
328 for (j = pm_dbg_reg_modules[i].low; 328 for (j = pm_dbg_reg_modules[i].low;
329 j <= pm_dbg_reg_modules[i].high; j += 4) { 329 j <= pm_dbg_reg_modules[i].high; j += 4) {
330 if (pm_dbg_reg_modules[i].type == MOD_CM) 330 if (pm_dbg_reg_modules[i].type == MOD_CM)
331 val = cm_read_mod_reg( 331 val = omap2_cm_read_mod_reg(
332 pm_dbg_reg_modules[i].offset, j); 332 pm_dbg_reg_modules[i].offset, j);
333 else 333 else
334 val = prm_read_mod_reg( 334 val = omap2_prm_read_mod_reg(
335 pm_dbg_reg_modules[i].offset, j); 335 pm_dbg_reg_modules[i].offset, j);
336 *(ptr++) = val; 336 *(ptr++) = val;
337 } 337 }
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 8ea49dcaae4d..bf0c36b239f9 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -79,8 +79,8 @@ static int omap2_fclks_active(void)
79{ 79{
80 u32 f1, f2; 80 u32 f1, f2;
81 81
82 f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); 82 f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
83 f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); 83 f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
84 84
85 /* Ignore UART clocks. These are handled by UART core (serial.c) */ 85 /* Ignore UART clocks. These are handled by UART core (serial.c) */
86 f1 &= ~(OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_UART2_MASK); 86 f1 &= ~(OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_UART2_MASK);
@@ -105,9 +105,9 @@ static void omap2_enter_full_retention(void)
105 105
106 /* Clear old wake-up events */ 106 /* Clear old wake-up events */
107 /* REVISIT: These write to reserved bits? */ 107 /* REVISIT: These write to reserved bits? */
108 prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); 108 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
109 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); 109 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
110 prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); 110 omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
111 111
112 /* 112 /*
113 * Set MPU powerdomain's next power state to RETENTION; 113 * Set MPU powerdomain's next power state to RETENTION;
@@ -167,30 +167,30 @@ no_sleep:
167 clk_enable(osc_ck); 167 clk_enable(osc_ck);
168 168
169 /* clear CORE wake-up events */ 169 /* clear CORE wake-up events */
170 prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); 170 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
171 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); 171 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
172 172
173 /* wakeup domain events - bit 1: GPT1, bit5 GPIO */ 173 /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
174 prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST); 174 omap2_prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
175 175
176 /* MPU domain wake events */ 176 /* MPU domain wake events */
177 l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); 177 l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
178 if (l & 0x01) 178 if (l & 0x01)
179 prm_write_mod_reg(0x01, OCP_MOD, 179 omap2_prm_write_mod_reg(0x01, OCP_MOD,
180 OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); 180 OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
181 if (l & 0x20) 181 if (l & 0x20)
182 prm_write_mod_reg(0x20, OCP_MOD, 182 omap2_prm_write_mod_reg(0x20, OCP_MOD,
183 OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); 183 OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
184 184
185 /* Mask future PRCM-to-MPU interrupts */ 185 /* Mask future PRCM-to-MPU interrupts */
186 prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); 186 omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
187} 187}
188 188
189static int omap2_i2c_active(void) 189static int omap2_i2c_active(void)
190{ 190{
191 u32 l; 191 u32 l;
192 192
193 l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); 193 l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
194 return l & (OMAP2420_EN_I2C2_MASK | OMAP2420_EN_I2C1_MASK); 194 return l & (OMAP2420_EN_I2C2_MASK | OMAP2420_EN_I2C1_MASK);
195} 195}
196 196
@@ -201,13 +201,13 @@ static int omap2_allow_mpu_retention(void)
201 u32 l; 201 u32 l;
202 202
203 /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */ 203 /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
204 l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); 204 l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
205 if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK | 205 if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK |
206 OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK | 206 OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK |
207 OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK)) 207 OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK))
208 return 0; 208 return 0;
209 /* Check for UART3. */ 209 /* Check for UART3. */
210 l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); 210 l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
211 if (l & OMAP24XX_EN_UART3_MASK) 211 if (l & OMAP24XX_EN_UART3_MASK)
212 return 0; 212 return 0;
213 if (sti_console_enabled) 213 if (sti_console_enabled)
@@ -230,18 +230,18 @@ static void omap2_enter_mpu_retention(void)
230 * it is in retention mode. */ 230 * it is in retention mode. */
231 if (omap2_allow_mpu_retention()) { 231 if (omap2_allow_mpu_retention()) {
232 /* REVISIT: These write to reserved bits? */ 232 /* REVISIT: These write to reserved bits? */
233 prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); 233 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
234 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); 234 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
235 prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); 235 omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
236 236
237 /* Try to enter MPU retention */ 237 /* Try to enter MPU retention */
238 prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) | 238 omap2_prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
239 OMAP_LOGICRETSTATE_MASK, 239 OMAP_LOGICRETSTATE_MASK,
240 MPU_MOD, OMAP2_PM_PWSTCTRL); 240 MPU_MOD, OMAP2_PM_PWSTCTRL);
241 } else { 241 } else {
242 /* Block MPU retention */ 242 /* Block MPU retention */
243 243
244 prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD, 244 omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD,
245 OMAP2_PM_PWSTCTRL); 245 OMAP2_PM_PWSTCTRL);
246 only_idle = 1; 246 only_idle = 1;
247 } 247 }
@@ -310,9 +310,9 @@ static int omap2_pm_suspend(void)
310{ 310{
311 u32 wken_wkup, mir1; 311 u32 wken_wkup, mir1;
312 312
313 wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN); 313 wken_wkup = omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
314 wken_wkup &= ~OMAP24XX_EN_GPT1_MASK; 314 wken_wkup &= ~OMAP24XX_EN_GPT1_MASK;
315 prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN); 315 omap2_prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
316 316
317 /* Mask GPT1 */ 317 /* Mask GPT1 */
318 mir1 = omap_readl(0x480fe0a4); 318 mir1 = omap_readl(0x480fe0a4);
@@ -322,7 +322,7 @@ static int omap2_pm_suspend(void)
322 omap2_enter_full_retention(); 322 omap2_enter_full_retention();
323 323
324 omap_writel(mir1, 0x480fe0a4); 324 omap_writel(mir1, 0x480fe0a4);
325 prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN); 325 omap2_prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
326 326
327 return 0; 327 return 0;
328} 328}
@@ -376,7 +376,7 @@ static void __init prcm_setup_regs(void)
376 struct powerdomain *pwrdm; 376 struct powerdomain *pwrdm;
377 377
378 /* Enable autoidle */ 378 /* Enable autoidle */
379 prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD, 379 omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
380 OMAP2_PRCM_SYSCONFIG_OFFSET); 380 OMAP2_PRCM_SYSCONFIG_OFFSET);
381 381
382 /* 382 /*
@@ -415,87 +415,87 @@ static void __init prcm_setup_regs(void)
415 clkdm_add_wkdep(mpu_clkdm, wkup_clkdm); 415 clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
416 416
417 /* Enable clock autoidle for all domains */ 417 /* Enable clock autoidle for all domains */
418 cm_write_mod_reg(OMAP24XX_AUTO_CAM_MASK | 418 omap2_cm_write_mod_reg(OMAP24XX_AUTO_CAM_MASK |
419 OMAP24XX_AUTO_MAILBOXES_MASK | 419 OMAP24XX_AUTO_MAILBOXES_MASK |
420 OMAP24XX_AUTO_WDT4_MASK | 420 OMAP24XX_AUTO_WDT4_MASK |
421 OMAP2420_AUTO_WDT3_MASK | 421 OMAP2420_AUTO_WDT3_MASK |
422 OMAP24XX_AUTO_MSPRO_MASK | 422 OMAP24XX_AUTO_MSPRO_MASK |
423 OMAP2420_AUTO_MMC_MASK | 423 OMAP2420_AUTO_MMC_MASK |
424 OMAP24XX_AUTO_FAC_MASK | 424 OMAP24XX_AUTO_FAC_MASK |
425 OMAP2420_AUTO_EAC_MASK | 425 OMAP2420_AUTO_EAC_MASK |
426 OMAP24XX_AUTO_HDQ_MASK | 426 OMAP24XX_AUTO_HDQ_MASK |
427 OMAP24XX_AUTO_UART2_MASK | 427 OMAP24XX_AUTO_UART2_MASK |
428 OMAP24XX_AUTO_UART1_MASK | 428 OMAP24XX_AUTO_UART1_MASK |
429 OMAP24XX_AUTO_I2C2_MASK | 429 OMAP24XX_AUTO_I2C2_MASK |
430 OMAP24XX_AUTO_I2C1_MASK | 430 OMAP24XX_AUTO_I2C1_MASK |
431 OMAP24XX_AUTO_MCSPI2_MASK | 431 OMAP24XX_AUTO_MCSPI2_MASK |
432 OMAP24XX_AUTO_MCSPI1_MASK | 432 OMAP24XX_AUTO_MCSPI1_MASK |
433 OMAP24XX_AUTO_MCBSP2_MASK | 433 OMAP24XX_AUTO_MCBSP2_MASK |
434 OMAP24XX_AUTO_MCBSP1_MASK | 434 OMAP24XX_AUTO_MCBSP1_MASK |
435 OMAP24XX_AUTO_GPT12_MASK | 435 OMAP24XX_AUTO_GPT12_MASK |
436 OMAP24XX_AUTO_GPT11_MASK | 436 OMAP24XX_AUTO_GPT11_MASK |
437 OMAP24XX_AUTO_GPT10_MASK | 437 OMAP24XX_AUTO_GPT10_MASK |
438 OMAP24XX_AUTO_GPT9_MASK | 438 OMAP24XX_AUTO_GPT9_MASK |
439 OMAP24XX_AUTO_GPT8_MASK | 439 OMAP24XX_AUTO_GPT8_MASK |
440 OMAP24XX_AUTO_GPT7_MASK | 440 OMAP24XX_AUTO_GPT7_MASK |
441 OMAP24XX_AUTO_GPT6_MASK | 441 OMAP24XX_AUTO_GPT6_MASK |
442 OMAP24XX_AUTO_GPT5_MASK | 442 OMAP24XX_AUTO_GPT5_MASK |
443 OMAP24XX_AUTO_GPT4_MASK | 443 OMAP24XX_AUTO_GPT4_MASK |
444 OMAP24XX_AUTO_GPT3_MASK | 444 OMAP24XX_AUTO_GPT3_MASK |
445 OMAP24XX_AUTO_GPT2_MASK | 445 OMAP24XX_AUTO_GPT2_MASK |
446 OMAP2420_AUTO_VLYNQ_MASK | 446 OMAP2420_AUTO_VLYNQ_MASK |
447 OMAP24XX_AUTO_DSS_MASK, 447 OMAP24XX_AUTO_DSS_MASK,
448 CORE_MOD, CM_AUTOIDLE1); 448 CORE_MOD, CM_AUTOIDLE1);
449 cm_write_mod_reg(OMAP24XX_AUTO_UART3_MASK | 449 omap2_cm_write_mod_reg(OMAP24XX_AUTO_UART3_MASK |
450 OMAP24XX_AUTO_SSI_MASK | 450 OMAP24XX_AUTO_SSI_MASK |
451 OMAP24XX_AUTO_USB_MASK, 451 OMAP24XX_AUTO_USB_MASK,
452 CORE_MOD, CM_AUTOIDLE2); 452 CORE_MOD, CM_AUTOIDLE2);
453 cm_write_mod_reg(OMAP24XX_AUTO_SDRC_MASK | 453 omap2_cm_write_mod_reg(OMAP24XX_AUTO_SDRC_MASK |
454 OMAP24XX_AUTO_GPMC_MASK | 454 OMAP24XX_AUTO_GPMC_MASK |
455 OMAP24XX_AUTO_SDMA_MASK, 455 OMAP24XX_AUTO_SDMA_MASK,
456 CORE_MOD, CM_AUTOIDLE3); 456 CORE_MOD, CM_AUTOIDLE3);
457 cm_write_mod_reg(OMAP24XX_AUTO_PKA_MASK | 457 omap2_cm_write_mod_reg(OMAP24XX_AUTO_PKA_MASK |
458 OMAP24XX_AUTO_AES_MASK | 458 OMAP24XX_AUTO_AES_MASK |
459 OMAP24XX_AUTO_RNG_MASK | 459 OMAP24XX_AUTO_RNG_MASK |
460 OMAP24XX_AUTO_SHA_MASK | 460 OMAP24XX_AUTO_SHA_MASK |
461 OMAP24XX_AUTO_DES_MASK, 461 OMAP24XX_AUTO_DES_MASK,
462 CORE_MOD, OMAP24XX_CM_AUTOIDLE4); 462 CORE_MOD, OMAP24XX_CM_AUTOIDLE4);
463 463
464 cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI_MASK, OMAP24XX_DSP_MOD, 464 omap2_cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI_MASK, OMAP24XX_DSP_MOD,
465 CM_AUTOIDLE); 465 CM_AUTOIDLE);
466 466
467 /* Put DPLL and both APLLs into autoidle mode */ 467 /* Put DPLL and both APLLs into autoidle mode */
468 cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) | 468 omap2_cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) |
469 (0x03 << OMAP24XX_AUTO_96M_SHIFT) | 469 (0x03 << OMAP24XX_AUTO_96M_SHIFT) |
470 (0x03 << OMAP24XX_AUTO_54M_SHIFT), 470 (0x03 << OMAP24XX_AUTO_54M_SHIFT),
471 PLL_MOD, CM_AUTOIDLE); 471 PLL_MOD, CM_AUTOIDLE);
472 472
473 cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL_MASK | 473 omap2_cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL_MASK |
474 OMAP24XX_AUTO_WDT1_MASK | 474 OMAP24XX_AUTO_WDT1_MASK |
475 OMAP24XX_AUTO_MPU_WDT_MASK | 475 OMAP24XX_AUTO_MPU_WDT_MASK |
476 OMAP24XX_AUTO_GPIOS_MASK | 476 OMAP24XX_AUTO_GPIOS_MASK |
477 OMAP24XX_AUTO_32KSYNC_MASK | 477 OMAP24XX_AUTO_32KSYNC_MASK |
478 OMAP24XX_AUTO_GPT1_MASK, 478 OMAP24XX_AUTO_GPT1_MASK,
479 WKUP_MOD, CM_AUTOIDLE); 479 WKUP_MOD, CM_AUTOIDLE);
480 480
481 /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk 481 /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
482 * stabilisation */ 482 * stabilisation */
483 prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD, 483 omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
484 OMAP2_PRCM_CLKSSETUP_OFFSET); 484 OMAP2_PRCM_CLKSSETUP_OFFSET);
485 485
486 /* Configure automatic voltage transition */ 486 /* Configure automatic voltage transition */
487 prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD, 487 omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
488 OMAP2_PRCM_VOLTSETUP_OFFSET); 488 OMAP2_PRCM_VOLTSETUP_OFFSET);
489 prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK | 489 omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK |
490 (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) | 490 (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
491 OMAP24XX_MEMRETCTRL_MASK | 491 OMAP24XX_MEMRETCTRL_MASK |
492 (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) | 492 (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
493 (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT), 493 (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
494 OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET); 494 OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
495 495
496 /* Enable wake-up events */ 496 /* Enable wake-up events */
497 prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK, 497 omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
498 WKUP_MOD, PM_WKEN); 498 WKUP_MOD, PM_WKEN);
499} 499}
500 500
501static int __init omap2_pm_init(void) 501static int __init omap2_pm_init(void)
@@ -506,7 +506,7 @@ static int __init omap2_pm_init(void)
506 return -ENODEV; 506 return -ENODEV;
507 507
508 printk(KERN_INFO "Power Management for OMAP2 initializing\n"); 508 printk(KERN_INFO "Power Management for OMAP2 initializing\n");
509 l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET); 509 l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
510 printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f); 510 printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
511 511
512 /* Look up important powerdomains */ 512 /* Look up important powerdomains */
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index cfff321c747e..1ca6ef4c25b3 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -105,12 +105,12 @@ static void omap3_enable_io_chain(void)
105 int timeout = 0; 105 int timeout = 0;
106 106
107 if (omap_rev() >= OMAP3430_REV_ES3_1) { 107 if (omap_rev() >= OMAP3430_REV_ES3_1) {
108 prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, 108 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
109 PM_WKEN); 109 PM_WKEN);
110 /* Do a readback to assure write has been done */ 110 /* Do a readback to assure write has been done */
111 prm_read_mod_reg(WKUP_MOD, PM_WKEN); 111 omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
112 112
113 while (!(prm_read_mod_reg(WKUP_MOD, PM_WKEN) & 113 while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
114 OMAP3430_ST_IO_CHAIN_MASK)) { 114 OMAP3430_ST_IO_CHAIN_MASK)) {
115 timeout++; 115 timeout++;
116 if (timeout > 1000) { 116 if (timeout > 1000) {
@@ -118,7 +118,7 @@ static void omap3_enable_io_chain(void)
118 "activation failed.\n"); 118 "activation failed.\n");
119 return; 119 return;
120 } 120 }
121 prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, 121 omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
122 WKUP_MOD, PM_WKEN); 122 WKUP_MOD, PM_WKEN);
123 } 123 }
124 } 124 }
@@ -127,7 +127,7 @@ static void omap3_enable_io_chain(void)
127static void omap3_disable_io_chain(void) 127static void omap3_disable_io_chain(void)
128{ 128{
129 if (omap_rev() >= OMAP3430_REV_ES3_1) 129 if (omap_rev() >= OMAP3430_REV_ES3_1)
130 prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, 130 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
131 PM_WKEN); 131 PM_WKEN);
132} 132}
133 133
@@ -221,27 +221,27 @@ static int prcm_clear_mod_irqs(s16 module, u8 regs)
221 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL; 221 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
222 int c = 0; 222 int c = 0;
223 223
224 wkst = prm_read_mod_reg(module, wkst_off); 224 wkst = omap2_prm_read_mod_reg(module, wkst_off);
225 wkst &= prm_read_mod_reg(module, grpsel_off); 225 wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
226 if (wkst) { 226 if (wkst) {
227 iclk = cm_read_mod_reg(module, iclk_off); 227 iclk = omap2_cm_read_mod_reg(module, iclk_off);
228 fclk = cm_read_mod_reg(module, fclk_off); 228 fclk = omap2_cm_read_mod_reg(module, fclk_off);
229 while (wkst) { 229 while (wkst) {
230 clken = wkst; 230 clken = wkst;
231 cm_set_mod_reg_bits(clken, module, iclk_off); 231 omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
232 /* 232 /*
233 * For USBHOST, we don't know whether HOST1 or 233 * For USBHOST, we don't know whether HOST1 or
234 * HOST2 woke us up, so enable both f-clocks 234 * HOST2 woke us up, so enable both f-clocks
235 */ 235 */
236 if (module == OMAP3430ES2_USBHOST_MOD) 236 if (module == OMAP3430ES2_USBHOST_MOD)
237 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT; 237 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
238 cm_set_mod_reg_bits(clken, module, fclk_off); 238 omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
239 prm_write_mod_reg(wkst, module, wkst_off); 239 omap2_prm_write_mod_reg(wkst, module, wkst_off);
240 wkst = prm_read_mod_reg(module, wkst_off); 240 wkst = omap2_prm_read_mod_reg(module, wkst_off);
241 c++; 241 c++;
242 } 242 }
243 cm_write_mod_reg(iclk, module, iclk_off); 243 omap2_cm_write_mod_reg(iclk, module, iclk_off);
244 cm_write_mod_reg(fclk, module, fclk_off); 244 omap2_cm_write_mod_reg(fclk, module, fclk_off);
245 } 245 }
246 246
247 return c; 247 return c;
@@ -284,9 +284,9 @@ static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
284 u32 irqenable_mpu, irqstatus_mpu; 284 u32 irqenable_mpu, irqstatus_mpu;
285 int c = 0; 285 int c = 0;
286 286
287 irqenable_mpu = prm_read_mod_reg(OCP_MOD, 287 irqenable_mpu = omap2_prm_read_mod_reg(OCP_MOD,
288 OMAP3_PRM_IRQENABLE_MPU_OFFSET); 288 OMAP3_PRM_IRQENABLE_MPU_OFFSET);
289 irqstatus_mpu = prm_read_mod_reg(OCP_MOD, 289 irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
290 OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 290 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
291 irqstatus_mpu &= irqenable_mpu; 291 irqstatus_mpu &= irqenable_mpu;
292 292
@@ -307,10 +307,10 @@ static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
307 "no code to handle it (%08x)\n", irqstatus_mpu); 307 "no code to handle it (%08x)\n", irqstatus_mpu);
308 } 308 }
309 309
310 prm_write_mod_reg(irqstatus_mpu, OCP_MOD, 310 omap2_prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
311 OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 311 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
312 312
313 irqstatus_mpu = prm_read_mod_reg(OCP_MOD, 313 irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
314 OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 314 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
315 irqstatus_mpu &= irqenable_mpu; 315 irqstatus_mpu &= irqenable_mpu;
316 316
@@ -398,7 +398,7 @@ void omap_sram_idle(void)
398 if (omap3_has_io_wakeup() && 398 if (omap3_has_io_wakeup() &&
399 (per_next_state < PWRDM_POWER_ON || 399 (per_next_state < PWRDM_POWER_ON ||
400 core_next_state < PWRDM_POWER_ON)) { 400 core_next_state < PWRDM_POWER_ON)) {
401 prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); 401 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
402 omap3_enable_io_chain(); 402 omap3_enable_io_chain();
403 } 403 }
404 404
@@ -471,7 +471,7 @@ void omap_sram_idle(void)
471 omap_uart_resume_idle(0); 471 omap_uart_resume_idle(0);
472 omap_uart_resume_idle(1); 472 omap_uart_resume_idle(1);
473 if (core_next_state == PWRDM_POWER_OFF) 473 if (core_next_state == PWRDM_POWER_OFF)
474 prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK, 474 omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
475 OMAP3430_GR_MOD, 475 OMAP3430_GR_MOD,
476 OMAP3_PRM_VOLTCTRL_OFFSET); 476 OMAP3_PRM_VOLTCTRL_OFFSET);
477 } 477 }
@@ -495,7 +495,8 @@ console_still_active:
495 if (omap3_has_io_wakeup() && 495 if (omap3_has_io_wakeup() &&
496 (per_next_state < PWRDM_POWER_ON || 496 (per_next_state < PWRDM_POWER_ON ||
497 core_next_state < PWRDM_POWER_ON)) { 497 core_next_state < PWRDM_POWER_ON)) {
498 prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); 498 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
499 PM_WKEN);
499 omap3_disable_io_chain(); 500 omap3_disable_io_chain();
500 } 501 }
501 502
@@ -633,21 +634,21 @@ static struct platform_suspend_ops omap_pm_ops = {
633static void __init omap3_iva_idle(void) 634static void __init omap3_iva_idle(void)
634{ 635{
635 /* ensure IVA2 clock is disabled */ 636 /* ensure IVA2 clock is disabled */
636 cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 637 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
637 638
638 /* if no clock activity, nothing else to do */ 639 /* if no clock activity, nothing else to do */
639 if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) & 640 if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
640 OMAP3430_CLKACTIVITY_IVA2_MASK)) 641 OMAP3430_CLKACTIVITY_IVA2_MASK))
641 return; 642 return;
642 643
643 /* Reset IVA2 */ 644 /* Reset IVA2 */
644 prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | 645 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
645 OMAP3430_RST2_IVA2_MASK | 646 OMAP3430_RST2_IVA2_MASK |
646 OMAP3430_RST3_IVA2_MASK, 647 OMAP3430_RST3_IVA2_MASK,
647 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 648 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
648 649
649 /* Enable IVA2 clock */ 650 /* Enable IVA2 clock */
650 cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK, 651 omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
651 OMAP3430_IVA2_MOD, CM_FCLKEN); 652 OMAP3430_IVA2_MOD, CM_FCLKEN);
652 653
653 /* Set IVA2 boot mode to 'idle' */ 654 /* Set IVA2 boot mode to 'idle' */
@@ -655,13 +656,13 @@ static void __init omap3_iva_idle(void)
655 OMAP343X_CONTROL_IVA2_BOOTMOD); 656 OMAP343X_CONTROL_IVA2_BOOTMOD);
656 657
657 /* Un-reset IVA2 */ 658 /* Un-reset IVA2 */
658 prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 659 omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
659 660
660 /* Disable IVA2 clock */ 661 /* Disable IVA2 clock */
661 cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 662 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
662 663
663 /* Reset IVA2 */ 664 /* Reset IVA2 */
664 prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | 665 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
665 OMAP3430_RST2_IVA2_MASK | 666 OMAP3430_RST2_IVA2_MASK |
666 OMAP3430_RST3_IVA2_MASK, 667 OMAP3430_RST3_IVA2_MASK,
667 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 668 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
@@ -685,10 +686,10 @@ static void __init omap3_d2d_idle(void)
685 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); 686 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
686 687
687 /* reset modem */ 688 /* reset modem */
688 prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK | 689 omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
689 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK, 690 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
690 CORE_MOD, OMAP2_RM_RSTCTRL); 691 CORE_MOD, OMAP2_RM_RSTCTRL);
691 prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL); 692 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
692} 693}
693 694
694static void __init prcm_setup_regs(void) 695static void __init prcm_setup_regs(void)
@@ -703,23 +704,23 @@ static void __init prcm_setup_regs(void)
703 704
704 /* XXX Reset all wkdeps. This should be done when initializing 705 /* XXX Reset all wkdeps. This should be done when initializing
705 * powerdomains */ 706 * powerdomains */
706 prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP); 707 omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
707 prm_write_mod_reg(0, MPU_MOD, PM_WKDEP); 708 omap2_prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
708 prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP); 709 omap2_prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
709 prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP); 710 omap2_prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
710 prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP); 711 omap2_prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
711 prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP); 712 omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
712 if (omap_rev() > OMAP3430_REV_ES1_0) { 713 if (omap_rev() > OMAP3430_REV_ES1_0) {
713 prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP); 714 omap2_prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
714 prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP); 715 omap2_prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
715 } else 716 } else
716 prm_write_mod_reg(0, GFX_MOD, PM_WKDEP); 717 omap2_prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
717 718
718 /* 719 /*
719 * Enable interface clock autoidle for all modules. 720 * Enable interface clock autoidle for all modules.
720 * Note that in the long run this should be done by clockfw 721 * Note that in the long run this should be done by clockfw
721 */ 722 */
722 cm_write_mod_reg( 723 omap2_cm_write_mod_reg(
723 OMAP3430_AUTO_MODEM_MASK | 724 OMAP3430_AUTO_MODEM_MASK |
724 OMAP3430ES2_AUTO_MMC3_MASK | 725 OMAP3430ES2_AUTO_MMC3_MASK |
725 OMAP3430ES2_AUTO_ICR_MASK | 726 OMAP3430ES2_AUTO_ICR_MASK |
@@ -752,7 +753,7 @@ static void __init prcm_setup_regs(void)
752 OMAP3430_AUTO_SSI_MASK, 753 OMAP3430_AUTO_SSI_MASK,
753 CORE_MOD, CM_AUTOIDLE1); 754 CORE_MOD, CM_AUTOIDLE1);
754 755
755 cm_write_mod_reg( 756 omap2_cm_write_mod_reg(
756 OMAP3430_AUTO_PKA_MASK | 757 OMAP3430_AUTO_PKA_MASK |
757 OMAP3430_AUTO_AES1_MASK | 758 OMAP3430_AUTO_AES1_MASK |
758 OMAP3430_AUTO_RNG_MASK | 759 OMAP3430_AUTO_RNG_MASK |
@@ -761,13 +762,13 @@ static void __init prcm_setup_regs(void)
761 CORE_MOD, CM_AUTOIDLE2); 762 CORE_MOD, CM_AUTOIDLE2);
762 763
763 if (omap_rev() > OMAP3430_REV_ES1_0) { 764 if (omap_rev() > OMAP3430_REV_ES1_0) {
764 cm_write_mod_reg( 765 omap2_cm_write_mod_reg(
765 OMAP3430_AUTO_MAD2D_MASK | 766 OMAP3430_AUTO_MAD2D_MASK |
766 OMAP3430ES2_AUTO_USBTLL_MASK, 767 OMAP3430ES2_AUTO_USBTLL_MASK,
767 CORE_MOD, CM_AUTOIDLE3); 768 CORE_MOD, CM_AUTOIDLE3);
768 } 769 }
769 770
770 cm_write_mod_reg( 771 omap2_cm_write_mod_reg(
771 OMAP3430_AUTO_WDT2_MASK | 772 OMAP3430_AUTO_WDT2_MASK |
772 OMAP3430_AUTO_WDT1_MASK | 773 OMAP3430_AUTO_WDT1_MASK |
773 OMAP3430_AUTO_GPIO1_MASK | 774 OMAP3430_AUTO_GPIO1_MASK |
@@ -776,17 +777,17 @@ static void __init prcm_setup_regs(void)
776 OMAP3430_AUTO_GPT1_MASK, 777 OMAP3430_AUTO_GPT1_MASK,
777 WKUP_MOD, CM_AUTOIDLE); 778 WKUP_MOD, CM_AUTOIDLE);
778 779
779 cm_write_mod_reg( 780 omap2_cm_write_mod_reg(
780 OMAP3430_AUTO_DSS_MASK, 781 OMAP3430_AUTO_DSS_MASK,
781 OMAP3430_DSS_MOD, 782 OMAP3430_DSS_MOD,
782 CM_AUTOIDLE); 783 CM_AUTOIDLE);
783 784
784 cm_write_mod_reg( 785 omap2_cm_write_mod_reg(
785 OMAP3430_AUTO_CAM_MASK, 786 OMAP3430_AUTO_CAM_MASK,
786 OMAP3430_CAM_MOD, 787 OMAP3430_CAM_MOD,
787 CM_AUTOIDLE); 788 CM_AUTOIDLE);
788 789
789 cm_write_mod_reg( 790 omap2_cm_write_mod_reg(
790 omap3630_auto_uart4_mask | 791 omap3630_auto_uart4_mask |
791 OMAP3430_AUTO_GPIO6_MASK | 792 OMAP3430_AUTO_GPIO6_MASK |
792 OMAP3430_AUTO_GPIO5_MASK | 793 OMAP3430_AUTO_GPIO5_MASK |
@@ -810,7 +811,7 @@ static void __init prcm_setup_regs(void)
810 CM_AUTOIDLE); 811 CM_AUTOIDLE);
811 812
812 if (omap_rev() > OMAP3430_REV_ES1_0) { 813 if (omap_rev() > OMAP3430_REV_ES1_0) {
813 cm_write_mod_reg( 814 omap2_cm_write_mod_reg(
814 OMAP3430ES2_AUTO_USBHOST_MASK, 815 OMAP3430ES2_AUTO_USBHOST_MASK,
815 OMAP3430ES2_USBHOST_MOD, 816 OMAP3430ES2_USBHOST_MOD,
816 CM_AUTOIDLE); 817 CM_AUTOIDLE);
@@ -822,16 +823,16 @@ static void __init prcm_setup_regs(void)
822 * Set all plls to autoidle. This is needed until autoidle is 823 * Set all plls to autoidle. This is needed until autoidle is
823 * enabled by clockfw 824 * enabled by clockfw
824 */ 825 */
825 cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT, 826 omap2_cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
826 OMAP3430_IVA2_MOD, CM_AUTOIDLE2); 827 OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
827 cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT, 828 omap2_cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
828 MPU_MOD, 829 MPU_MOD,
829 CM_AUTOIDLE2); 830 CM_AUTOIDLE2);
830 cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) | 831 omap2_cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
831 (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT), 832 (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
832 PLL_MOD, 833 PLL_MOD,
833 CM_AUTOIDLE); 834 CM_AUTOIDLE);
834 cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT, 835 omap2_cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
835 PLL_MOD, 836 PLL_MOD,
836 CM_AUTOIDLE2); 837 CM_AUTOIDLE2);
837 838
@@ -840,31 +841,31 @@ static void __init prcm_setup_regs(void)
840 * sys_clkreq. In the long run clock framework should 841 * sys_clkreq. In the long run clock framework should
841 * take care of this. 842 * take care of this.
842 */ 843 */
843 prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, 844 omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
844 1 << OMAP_AUTOEXTCLKMODE_SHIFT, 845 1 << OMAP_AUTOEXTCLKMODE_SHIFT,
845 OMAP3430_GR_MOD, 846 OMAP3430_GR_MOD,
846 OMAP3_PRM_CLKSRC_CTRL_OFFSET); 847 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
847 848
848 /* setup wakup source */ 849 /* setup wakup source */
849 prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK | 850 omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
850 OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK, 851 OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
851 WKUP_MOD, PM_WKEN); 852 WKUP_MOD, PM_WKEN);
852 /* No need to write EN_IO, that is always enabled */ 853 /* No need to write EN_IO, that is always enabled */
853 prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK | 854 omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
854 OMAP3430_GRPSEL_GPT1_MASK | 855 OMAP3430_GRPSEL_GPT1_MASK |
855 OMAP3430_GRPSEL_GPT12_MASK, 856 OMAP3430_GRPSEL_GPT12_MASK,
856 WKUP_MOD, OMAP3430_PM_MPUGRPSEL); 857 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
857 /* For some reason IO doesn't generate wakeup event even if 858 /* For some reason IO doesn't generate wakeup event even if
858 * it is selected to mpu wakeup goup */ 859 * it is selected to mpu wakeup goup */
859 prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK, 860 omap2_prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK,
860 OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); 861 OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
861 862
862 /* Enable PM_WKEN to support DSS LPR */ 863 /* Enable PM_WKEN to support DSS LPR */
863 prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK, 864 omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
864 OMAP3430_DSS_MOD, PM_WKEN); 865 OMAP3430_DSS_MOD, PM_WKEN);
865 866
866 /* Enable wakeups in PER */ 867 /* Enable wakeups in PER */
867 prm_write_mod_reg(omap3630_en_uart4_mask | 868 omap2_prm_write_mod_reg(omap3630_en_uart4_mask |
868 OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK | 869 OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
869 OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK | 870 OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
870 OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK | 871 OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
@@ -872,7 +873,7 @@ static void __init prcm_setup_regs(void)
872 OMAP3430_EN_MCBSP4_MASK, 873 OMAP3430_EN_MCBSP4_MASK,
873 OMAP3430_PER_MOD, PM_WKEN); 874 OMAP3430_PER_MOD, PM_WKEN);
874 /* and allow them to wake up MPU */ 875 /* and allow them to wake up MPU */
875 prm_write_mod_reg(omap3630_grpsel_uart4_mask | 876 omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask |
876 OMAP3430_GRPSEL_GPIO2_MASK | 877 OMAP3430_GRPSEL_GPIO2_MASK |
877 OMAP3430_GRPSEL_GPIO3_MASK | 878 OMAP3430_GRPSEL_GPIO3_MASK |
878 OMAP3430_GRPSEL_GPIO4_MASK | 879 OMAP3430_GRPSEL_GPIO4_MASK |
@@ -885,22 +886,22 @@ static void __init prcm_setup_regs(void)
885 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); 886 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
886 887
887 /* Don't attach IVA interrupts */ 888 /* Don't attach IVA interrupts */
888 prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); 889 omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
889 prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); 890 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
890 prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); 891 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
891 prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); 892 omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
892 893
893 /* Clear any pending 'reset' flags */ 894 /* Clear any pending 'reset' flags */
894 prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST); 895 omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
895 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST); 896 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
896 prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST); 897 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
897 prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST); 898 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
898 prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST); 899 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
899 prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST); 900 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
900 prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST); 901 omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
901 902
902 /* Clear any pending PRCM interrupts */ 903 /* Clear any pending PRCM interrupts */
903 prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 904 omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
904 905
905 omap3_iva_idle(); 906 omap3_iva_idle();
906 omap3_d2d_idle(); 907 omap3_d2d_idle();
diff --git a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
index 838ac758c513..b5e9e4d18b8c 100644
--- a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
@@ -28,7 +28,7 @@
28/* Common functions across OMAP2 and OMAP3 */ 28/* Common functions across OMAP2 and OMAP3 */
29static int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) 29static int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
30{ 30{
31 prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK, 31 omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
32 (pwrst << OMAP_POWERSTATE_SHIFT), 32 (pwrst << OMAP_POWERSTATE_SHIFT),
33 pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); 33 pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
34 return 0; 34 return 0;
@@ -36,14 +36,16 @@ static int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
36 36
37static int omap2_pwrdm_read_next_pwrst(struct powerdomain *pwrdm) 37static int omap2_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
38{ 38{
39 return prm_read_mod_bits_shift(pwrdm->prcm_offs, 39 return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
40 OMAP2_PM_PWSTCTRL, OMAP_POWERSTATE_MASK); 40 OMAP2_PM_PWSTCTRL,
41 OMAP_POWERSTATE_MASK);
41} 42}
42 43
43static int omap2_pwrdm_read_pwrst(struct powerdomain *pwrdm) 44static int omap2_pwrdm_read_pwrst(struct powerdomain *pwrdm)
44{ 45{
45 return prm_read_mod_bits_shift(pwrdm->prcm_offs, 46 return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
46 OMAP2_PM_PWSTST, OMAP_POWERSTATEST_MASK); 47 OMAP2_PM_PWSTST,
48 OMAP_POWERSTATEST_MASK);
47} 49}
48 50
49static int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, 51static int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
@@ -53,8 +55,8 @@ static int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
53 55
54 m = omap2_pwrdm_get_mem_bank_onstate_mask(bank); 56 m = omap2_pwrdm_get_mem_bank_onstate_mask(bank);
55 57
56 prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, 58 omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
57 OMAP2_PM_PWSTCTRL); 59 OMAP2_PM_PWSTCTRL);
58 60
59 return 0; 61 return 0;
60} 62}
@@ -66,8 +68,8 @@ static int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
66 68
67 m = omap2_pwrdm_get_mem_bank_retst_mask(bank); 69 m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
68 70
69 prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, 71 omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
70 OMAP2_PM_PWSTCTRL); 72 OMAP2_PM_PWSTCTRL);
71 73
72 return 0; 74 return 0;
73} 75}
@@ -78,7 +80,8 @@ static int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
78 80
79 m = omap2_pwrdm_get_mem_bank_stst_mask(bank); 81 m = omap2_pwrdm_get_mem_bank_stst_mask(bank);
80 82
81 return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST, m); 83 return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST,
84 m);
82} 85}
83 86
84static int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) 87static int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
@@ -87,7 +90,8 @@ static int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
87 90
88 m = omap2_pwrdm_get_mem_bank_retst_mask(bank); 91 m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
89 92
90 return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL, m); 93 return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
94 OMAP2_PM_PWSTCTRL, m);
91} 95}
92 96
93static int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) 97static int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
@@ -95,8 +99,8 @@ static int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
95 u32 v; 99 u32 v;
96 100
97 v = pwrst << __ffs(OMAP3430_LOGICL1CACHERETSTATE_MASK); 101 v = pwrst << __ffs(OMAP3430_LOGICL1CACHERETSTATE_MASK);
98 prm_rmw_mod_reg_bits(OMAP3430_LOGICL1CACHERETSTATE_MASK, v, 102 omap2_prm_rmw_mod_reg_bits(OMAP3430_LOGICL1CACHERETSTATE_MASK, v,
99 pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); 103 pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
100 104
101 return 0; 105 return 0;
102} 106}
@@ -112,7 +116,7 @@ static int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm)
112 */ 116 */
113 117
114 /* XXX Is this udelay() value meaningful? */ 118 /* XXX Is this udelay() value meaningful? */
115 while ((prm_read_mod_reg(pwrdm->prcm_offs, OMAP2_PM_PWSTST) & 119 while ((omap2_prm_read_mod_reg(pwrdm->prcm_offs, OMAP2_PM_PWSTST) &
116 OMAP_INTRANSITION_MASK) && 120 OMAP_INTRANSITION_MASK) &&
117 (c++ < PWRDM_TRANSITION_BAILOUT)) 121 (c++ < PWRDM_TRANSITION_BAILOUT))
118 udelay(1); 122 udelay(1);
@@ -131,26 +135,30 @@ static int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm)
131/* Applicable only for OMAP3. Not supported on OMAP2 */ 135/* Applicable only for OMAP3. Not supported on OMAP2 */
132static int omap3_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) 136static int omap3_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
133{ 137{
134 return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST, 138 return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
135 OMAP3430_LASTPOWERSTATEENTERED_MASK); 139 OMAP3430_PM_PREPWSTST,
140 OMAP3430_LASTPOWERSTATEENTERED_MASK);
136} 141}
137 142
138static int omap3_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) 143static int omap3_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
139{ 144{
140 return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST, 145 return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
141 OMAP3430_LOGICSTATEST_MASK); 146 OMAP2_PM_PWSTST,
147 OMAP3430_LOGICSTATEST_MASK);
142} 148}
143 149
144static int omap3_pwrdm_read_logic_retst(struct powerdomain *pwrdm) 150static int omap3_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
145{ 151{
146 return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL, 152 return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
147 OMAP3430_LOGICSTATEST_MASK); 153 OMAP2_PM_PWSTCTRL,
154 OMAP3430_LOGICSTATEST_MASK);
148} 155}
149 156
150static int omap3_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm) 157static int omap3_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
151{ 158{
152 return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST, 159 return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
153 OMAP3430_LASTLOGICSTATEENTERED_MASK); 160 OMAP3430_PM_PREPWSTST,
161 OMAP3430_LASTLOGICSTATEENTERED_MASK);
154} 162}
155 163
156static int omap3_get_mem_bank_lastmemst_mask(u8 bank) 164static int omap3_get_mem_bank_lastmemst_mask(u8 bank)
@@ -177,26 +185,28 @@ static int omap3_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
177 185
178 m = omap3_get_mem_bank_lastmemst_mask(bank); 186 m = omap3_get_mem_bank_lastmemst_mask(bank);
179 187
180 return prm_read_mod_bits_shift(pwrdm->prcm_offs, 188 return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
181 OMAP3430_PM_PREPWSTST, m); 189 OMAP3430_PM_PREPWSTST, m);
182} 190}
183 191
184static int omap3_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm) 192static int omap3_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
185{ 193{
186 prm_write_mod_reg(0, pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST); 194 omap2_prm_write_mod_reg(0, pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST);
187 return 0; 195 return 0;
188} 196}
189 197
190static int omap3_pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm) 198static int omap3_pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm)
191{ 199{
192 return prm_rmw_mod_reg_bits(0, 1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, 200 return omap2_prm_rmw_mod_reg_bits(0,
193 pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); 201 1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT,
202 pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
194} 203}
195 204
196static int omap3_pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm) 205static int omap3_pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm)
197{ 206{
198 return prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, 0, 207 return omap2_prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT,
199 pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); 208 0, pwrdm->prcm_offs,
209 OMAP2_PM_PWSTCTRL);
200} 210}
201 211
202struct pwrdm_ops omap2_pwrdm_operations = { 212struct pwrdm_ops omap2_pwrdm_operations = {
diff --git a/arch/arm/mach-omap2/powerdomain44xx.c b/arch/arm/mach-omap2/powerdomain44xx.c
index dae767bf1952..4c5ab1a2d44b 100644
--- a/arch/arm/mach-omap2/powerdomain44xx.c
+++ b/arch/arm/mach-omap2/powerdomain44xx.c
@@ -25,7 +25,7 @@
25 25
26static int omap4_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) 26static int omap4_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
27{ 27{
28 prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK, 28 omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
29 (pwrst << OMAP_POWERSTATE_SHIFT), 29 (pwrst << OMAP_POWERSTATE_SHIFT),
30 pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL); 30 pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
31 return 0; 31 return 0;
@@ -33,25 +33,25 @@ static int omap4_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
33 33
34static int omap4_pwrdm_read_next_pwrst(struct powerdomain *pwrdm) 34static int omap4_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
35{ 35{
36 return prm_read_mod_bits_shift(pwrdm->prcm_offs, 36 return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
37 OMAP4_PM_PWSTCTRL, OMAP_POWERSTATE_MASK); 37 OMAP4_PM_PWSTCTRL, OMAP_POWERSTATE_MASK);
38} 38}
39 39
40static int omap4_pwrdm_read_pwrst(struct powerdomain *pwrdm) 40static int omap4_pwrdm_read_pwrst(struct powerdomain *pwrdm)
41{ 41{
42 return prm_read_mod_bits_shift(pwrdm->prcm_offs, 42 return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
43 OMAP4_PM_PWSTST, OMAP_POWERSTATEST_MASK); 43 OMAP4_PM_PWSTST, OMAP_POWERSTATEST_MASK);
44} 44}
45 45
46static int omap4_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) 46static int omap4_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
47{ 47{
48 return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP4_PM_PWSTST, 48 return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP4_PM_PWSTST,
49 OMAP4430_LASTPOWERSTATEENTERED_MASK); 49 OMAP4430_LASTPOWERSTATEENTERED_MASK);
50} 50}
51 51
52static int omap4_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm) 52static int omap4_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
53{ 53{
54 prm_rmw_mod_reg_bits(OMAP4430_LOWPOWERSTATECHANGE_MASK, 54 omap2_prm_rmw_mod_reg_bits(OMAP4430_LOWPOWERSTATECHANGE_MASK,
55 (1 << OMAP4430_LOWPOWERSTATECHANGE_SHIFT), 55 (1 << OMAP4430_LOWPOWERSTATECHANGE_SHIFT),
56 pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL); 56 pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
57 return 0; 57 return 0;
@@ -59,7 +59,7 @@ static int omap4_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
59 59
60static int omap4_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm) 60static int omap4_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
61{ 61{
62 prm_rmw_mod_reg_bits(OMAP4430_LASTPOWERSTATEENTERED_MASK, 62 omap2_prm_rmw_mod_reg_bits(OMAP4430_LASTPOWERSTATEENTERED_MASK,
63 OMAP4430_LASTPOWERSTATEENTERED_MASK, 63 OMAP4430_LASTPOWERSTATEENTERED_MASK,
64 pwrdm->prcm_offs, OMAP4_PM_PWSTST); 64 pwrdm->prcm_offs, OMAP4_PM_PWSTST);
65 return 0; 65 return 0;
@@ -70,7 +70,7 @@ static int omap4_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
70 u32 v; 70 u32 v;
71 71
72 v = pwrst << __ffs(OMAP4430_LOGICRETSTATE_MASK); 72 v = pwrst << __ffs(OMAP4430_LOGICRETSTATE_MASK);
73 prm_rmw_mod_reg_bits(OMAP4430_LOGICRETSTATE_MASK, v, 73 omap2_prm_rmw_mod_reg_bits(OMAP4430_LOGICRETSTATE_MASK, v,
74 pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL); 74 pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
75 75
76 return 0; 76 return 0;
@@ -83,7 +83,7 @@ static int omap4_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
83 83
84 m = omap2_pwrdm_get_mem_bank_onstate_mask(bank); 84 m = omap2_pwrdm_get_mem_bank_onstate_mask(bank);
85 85
86 prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, 86 omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
87 OMAP4_PM_PWSTCTRL); 87 OMAP4_PM_PWSTCTRL);
88 88
89 return 0; 89 return 0;
@@ -96,7 +96,7 @@ static int omap4_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
96 96
97 m = omap2_pwrdm_get_mem_bank_retst_mask(bank); 97 m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
98 98
99 prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, 99 omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
100 OMAP4_PM_PWSTCTRL); 100 OMAP4_PM_PWSTCTRL);
101 101
102 return 0; 102 return 0;
@@ -104,14 +104,15 @@ static int omap4_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
104 104
105static int omap4_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) 105static int omap4_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
106{ 106{
107 return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP4_PM_PWSTST, 107 return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP4_PM_PWSTST,
108 OMAP4430_LOGICSTATEST_MASK); 108 OMAP4430_LOGICSTATEST_MASK);
109} 109}
110 110
111static int omap4_pwrdm_read_logic_retst(struct powerdomain *pwrdm) 111static int omap4_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
112{ 112{
113 return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL, 113 return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
114 OMAP4430_LOGICRETSTATE_MASK); 114 OMAP4_PM_PWSTCTRL,
115 OMAP4430_LOGICRETSTATE_MASK);
115} 116}
116 117
117static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) 118static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
@@ -120,7 +121,8 @@ static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
120 121
121 m = omap2_pwrdm_get_mem_bank_stst_mask(bank); 122 m = omap2_pwrdm_get_mem_bank_stst_mask(bank);
122 123
123 return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP4_PM_PWSTST, m); 124 return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP4_PM_PWSTST,
125 m);
124} 126}
125 127
126static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) 128static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
@@ -129,7 +131,8 @@ static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
129 131
130 m = omap2_pwrdm_get_mem_bank_retst_mask(bank); 132 m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
131 133
132 return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL, m); 134 return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
135 OMAP4_PM_PWSTCTRL, m);
133} 136}
134 137
135static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm) 138static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm)
@@ -143,7 +146,7 @@ static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm)
143 */ 146 */
144 147
145 /* XXX Is this udelay() value meaningful? */ 148 /* XXX Is this udelay() value meaningful? */
146 while ((prm_read_mod_reg(pwrdm->prcm_offs, OMAP4_PM_PWSTST) & 149 while ((omap2_prm_read_mod_reg(pwrdm->prcm_offs, OMAP4_PM_PWSTST) &
147 OMAP_INTRANSITION_MASK) && 150 OMAP_INTRANSITION_MASK) &&
148 (c++ < PWRDM_TRANSITION_BAILOUT)) 151 (c++ < PWRDM_TRANSITION_BAILOUT))
149 udelay(1); 152 udelay(1);
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 68c541f98ad2..c22e726de121 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -17,7 +17,8 @@
17 * it under the terms of the GNU General Public License version 2 as 17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation. 18 * published by the Free Software Foundation.
19 */ 19 */
20#include <linux/module.h> 20
21#include <linux/kernel.h>
21#include <linux/init.h> 22#include <linux/init.h>
22#include <linux/clk.h> 23#include <linux/clk.h>
23#include <linux/io.h> 24#include <linux/io.h>
@@ -30,10 +31,9 @@
30#include "clock.h" 31#include "clock.h"
31#include "clock2xxx.h" 32#include "clock2xxx.h"
32#include "cm2xxx_3xxx.h" 33#include "cm2xxx_3xxx.h"
33#include "cm44xx.h"
34#include "prm2xxx_3xxx.h" 34#include "prm2xxx_3xxx.h"
35#include "prm44xx.h" 35#include "prm44xx.h"
36#include "prcm44xx.h" 36#include "prminst44xx.h"
37#include "prm-regbits-24xx.h" 37#include "prm-regbits-24xx.h"
38#include "prm-regbits-44xx.h" 38#include "prm-regbits-44xx.h"
39#include "control.h" 39#include "control.h"
@@ -48,9 +48,9 @@ u32 omap_prcm_get_reset_sources(void)
48{ 48{
49 /* XXX This presumably needs modification for 34XX */ 49 /* XXX This presumably needs modification for 34XX */
50 if (cpu_is_omap24xx() || cpu_is_omap34xx()) 50 if (cpu_is_omap24xx() || cpu_is_omap34xx())
51 return prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f; 51 return omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f;
52 if (cpu_is_omap44xx()) 52 if (cpu_is_omap44xx())
53 return prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f; 53 return omap2_prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f;
54 54
55 return 0; 55 return 0;
56} 56}
@@ -75,9 +75,9 @@ void omap_prcm_arch_reset(char mode, const char *cmd)
75 } 75 }
76 76
77 /* XXX should be moved to some OMAP2/3 specific code */ 77 /* XXX should be moved to some OMAP2/3 specific code */
78 prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs, 78 omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs,
79 OMAP2_RM_RSTCTRL); 79 OMAP2_RM_RSTCTRL);
80 prm_read_mod_reg(prcm_offs, OMAP2_RM_RSTCTRL); /* OCP barrier */ 80 omap2_prm_read_mod_reg(prcm_offs, OMAP2_RM_RSTCTRL); /* OCP barrier */
81} 81}
82 82
83/** 83/**
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
index 3e1d36c83fc4..ec0362574b5e 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
@@ -25,49 +25,49 @@
25#include "prm-regbits-24xx.h" 25#include "prm-regbits-24xx.h"
26#include "prm-regbits-34xx.h" 26#include "prm-regbits-34xx.h"
27 27
28u32 prm_read_mod_reg(s16 module, u16 idx) 28u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
29{ 29{
30 return __raw_readl(prm_base + module + idx); 30 return __raw_readl(prm_base + module + idx);
31} 31}
32 32
33void prm_write_mod_reg(u32 val, s16 module, u16 idx) 33void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
34{ 34{
35 __raw_writel(val, prm_base + module + idx); 35 __raw_writel(val, prm_base + module + idx);
36} 36}
37 37
38/* Read-modify-write a register in a PRM module. Caller must lock */ 38/* Read-modify-write a register in a PRM module. Caller must lock */
39u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) 39u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
40{ 40{
41 u32 v; 41 u32 v;
42 42
43 v = prm_read_mod_reg(module, idx); 43 v = omap2_prm_read_mod_reg(module, idx);
44 v &= ~mask; 44 v &= ~mask;
45 v |= bits; 45 v |= bits;
46 prm_write_mod_reg(v, module, idx); 46 omap2_prm_write_mod_reg(v, module, idx);
47 47
48 return v; 48 return v;
49} 49}
50 50
51/* Read a PRM register, AND it, and shift the result down to bit 0 */ 51/* Read a PRM register, AND it, and shift the result down to bit 0 */
52u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask) 52u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
53{ 53{
54 u32 v; 54 u32 v;
55 55
56 v = prm_read_mod_reg(domain, idx); 56 v = omap2_prm_read_mod_reg(domain, idx);
57 v &= mask; 57 v &= mask;
58 v >>= __ffs(mask); 58 v >>= __ffs(mask);
59 59
60 return v; 60 return v;
61} 61}
62 62
63u32 prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) 63u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
64{ 64{
65 return prm_rmw_mod_reg_bits(bits, bits, module, idx); 65 return omap2_prm_rmw_mod_reg_bits(bits, bits, module, idx);
66} 66}
67 67
68u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) 68u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
69{ 69{
70 return prm_rmw_mod_reg_bits(bits, 0x0, module, idx); 70 return omap2_prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
71} 71}
72 72
73 73
@@ -86,7 +86,7 @@ int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift)
86 if (!(cpu_is_omap24xx() || cpu_is_omap34xx())) 86 if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
87 return -EINVAL; 87 return -EINVAL;
88 88
89 return prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, 89 return omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL,
90 (1 << shift)); 90 (1 << shift));
91} 91}
92 92
@@ -110,7 +110,7 @@ int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift)
110 return -EINVAL; 110 return -EINVAL;
111 111
112 mask = 1 << shift; 112 mask = 1 << shift;
113 prm_rmw_mod_reg_bits(mask, mask, prm_mod, OMAP2_RM_RSTCTRL); 113 omap2_prm_rmw_mod_reg_bits(mask, mask, prm_mod, OMAP2_RM_RSTCTRL);
114 114
115 return 0; 115 return 0;
116} 116}
@@ -140,15 +140,15 @@ int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift)
140 mask = 1 << shift; 140 mask = 1 << shift;
141 141
142 /* Check the current status to avoid de-asserting the line twice */ 142 /* Check the current status to avoid de-asserting the line twice */
143 if (prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, mask) == 0) 143 if (omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, mask) == 0)
144 return -EEXIST; 144 return -EEXIST;
145 145
146 /* Clear the reset status by writing 1 to the status bit */ 146 /* Clear the reset status by writing 1 to the status bit */
147 prm_rmw_mod_reg_bits(0xffffffff, mask, prm_mod, OMAP2_RM_RSTST); 147 omap2_prm_rmw_mod_reg_bits(0xffffffff, mask, prm_mod, OMAP2_RM_RSTST);
148 /* de-assert the reset control line */ 148 /* de-assert the reset control line */
149 prm_rmw_mod_reg_bits(mask, 0, prm_mod, OMAP2_RM_RSTCTRL); 149 omap2_prm_rmw_mod_reg_bits(mask, 0, prm_mod, OMAP2_RM_RSTCTRL);
150 /* wait the status to be set */ 150 /* wait the status to be set */
151 omap_test_timeout(prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTST, 151 omap_test_timeout(omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTST,
152 mask), 152 mask),
153 MAX_MODULE_HARDRESET_WAIT, c); 153 MAX_MODULE_HARDRESET_WAIT, c);
154 154
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h
index ab28517c82ce..53d44f6e3736 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h
@@ -230,12 +230,12 @@
230#ifndef __ASSEMBLER__ 230#ifndef __ASSEMBLER__
231 231
232/* Power/reset management domain register get/set */ 232/* Power/reset management domain register get/set */
233extern u32 prm_read_mod_reg(s16 module, u16 idx); 233extern u32 omap2_prm_read_mod_reg(s16 module, u16 idx);
234extern void prm_write_mod_reg(u32 val, s16 module, u16 idx); 234extern void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx);
235extern u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); 235extern u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
236extern u32 prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx); 236extern u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx);
237extern u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx); 237extern u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx);
238extern u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask); 238extern u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask);
239 239
240/* These omap2_ PRM functions apply to both OMAP2 and 3 */ 240/* These omap2_ PRM functions apply to both OMAP2 and 3 */
241extern int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift); 241extern int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift);
diff --git a/arch/arm/mach-omap2/sdrc2xxx.c b/arch/arm/mach-omap2/sdrc2xxx.c
index 64778b6240c1..ccdb010f169d 100644
--- a/arch/arm/mach-omap2/sdrc2xxx.c
+++ b/arch/arm/mach-omap2/sdrc2xxx.c
@@ -99,6 +99,10 @@ u32 omap2xxx_sdrc_reprogram(u32 level, u32 force)
99 m_type = omap2xxx_sdrc_get_type(); 99 m_type = omap2xxx_sdrc_get_type();
100 100
101 local_irq_save(flags); 101 local_irq_save(flags);
102 /*
103 * XXX These calls should be abstracted out through a
104 * prm2xxx.c function
105 */
102 if (cpu_is_omap2420()) 106 if (cpu_is_omap2420())
103 __raw_writel(0xffff, OMAP2420_PRCM_VOLTSETUP); 107 __raw_writel(0xffff, OMAP2420_PRCM_VOLTSETUP);
104 else 108 else
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 26770d80419e..c8740ba4fba5 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -490,6 +490,7 @@ static void omap_uart_idle_init(struct omap_uart_state *uart)
490 u32 wk_mask = 0; 490 u32 wk_mask = 0;
491 u32 padconf = 0; 491 u32 padconf = 0;
492 492
493 /* XXX These PRM accesses do not belong here */
493 uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1); 494 uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
494 uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1); 495 uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
495 switch (uart->num) { 496 switch (uart->num) {
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index 95449b90074d..b5a6e178a7f9 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -236,9 +236,9 @@ static void omap_st_on(struct omap_mcbsp *mcbsp)
236 * Sidetone uses McBSP ICLK - which must not idle when sidetones 236 * Sidetone uses McBSP ICLK - which must not idle when sidetones
237 * are enabled or sidetones start sounding ugly. 237 * are enabled or sidetones start sounding ugly.
238 */ 238 */
239 w = cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE); 239 w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
240 w &= ~(1 << (mcbsp->id - 2)); 240 w &= ~(1 << (mcbsp->id - 2));
241 cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE); 241 omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
242 242
243 /* Enable McBSP Sidetone */ 243 /* Enable McBSP Sidetone */
244 w = MCBSP_READ(mcbsp, SSELCR); 244 w = MCBSP_READ(mcbsp, SSELCR);
@@ -265,9 +265,9 @@ static void omap_st_off(struct omap_mcbsp *mcbsp)
265 w = MCBSP_READ(mcbsp, SSELCR); 265 w = MCBSP_READ(mcbsp, SSELCR);
266 MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN)); 266 MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
267 267
268 w = cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE); 268 w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
269 w |= 1 << (mcbsp->id - 2); 269 w |= 1 << (mcbsp->id - 2);
270 cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE); 270 omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
271} 271}
272 272
273static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir) 273static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 15:33:12 -0500